1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
46 #define Mmode enum machine_mode
49 /* Some function declarations. */
50 static HOST_WIDE_INT int_log2 PARAMS ((HOST_WIDE_INT));
51 static char * output_multi_immediate PARAMS ((rtx *, char *, char *, int, HOST_WIDE_INT));
52 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, HOST_WIDE_INT, rtx, rtx, int, int));
53 static int arm_naked_function_p PARAMS ((tree));
54 static void init_fpa_table PARAMS ((void));
55 static enum machine_mode select_dominance_cc_mode PARAMS ((rtx, rtx, HOST_WIDE_INT));
56 static HOST_WIDE_INT add_minipool_constant PARAMS ((rtx, Mmode));
57 static void dump_minipool PARAMS ((rtx));
58 static rtx find_barrier PARAMS ((rtx, int));
59 static void push_minipool_fix PARAMS ((rtx, int, rtx *, Mmode, rtx));
60 static void push_minipool_barrier PARAMS ((rtx, int));
61 static void note_invalid_constants PARAMS ((rtx, int));
62 static char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
63 static int eliminate_lr2ip PARAMS ((rtx *));
64 static char * shift_op PARAMS ((rtx, HOST_WIDE_INT *));
65 static int pattern_really_clobbers_lr PARAMS ((rtx));
66 static int function_really_clobbers_lr PARAMS ((rtx));
67 static void emit_multi_reg_push PARAMS ((int));
68 static void emit_sfm PARAMS ((int, int));
69 static enum arm_cond_code get_arm_condition_code PARAMS ((rtx));
70 static int const_ok_for_op PARAMS ((HOST_WIDE_INT, enum rtx_code));
71 static void arm_add_gc_roots PARAMS ((void));
73 /* The maximum number of insns skipped which will be conditionalised if
75 static int max_insns_skipped = 5;
77 extern FILE * asm_out_file;
79 /* True if we are currently building a constant table. */
80 int making_const_table;
82 /* Define the information needed to generate branch insns. This is
83 stored from the compare operation. */
84 rtx arm_compare_op0, arm_compare_op1;
86 /* What type of floating point are we tuning for? */
87 enum floating_point_type arm_fpu;
89 /* What type of floating point instructions are available? */
90 enum floating_point_type arm_fpu_arch;
92 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
93 enum prog_mode_type arm_prgmode;
95 /* Set by the -mfp=... option */
96 const char * target_fp_name = NULL;
98 /* Used to parse -mstructure_size_boundary command line option. */
99 const char * structure_size_string = NULL;
100 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
102 /* Bit values used to identify processor capabilities. */
103 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
104 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
105 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
106 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
107 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
108 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
109 #define FL_THUMB (1 << 6) /* Thumb aware */
110 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
111 #define FL_STRONG (1 << 8) /* StrongARM */
113 /* The bits in this mask specify which instructions we are allowed to
115 static int insn_flags = 0;
116 /* The bits in this mask specify which instruction scheduling options should
117 be used. Note - there is an overlap with the FL_FAST_MULT. For some
118 hardware we want to be able to generate the multiply instructions, but to
119 tune as if they were not present in the architecture. */
120 static int tune_flags = 0;
122 /* The following are used in the arm.md file as equivalents to bits
123 in the above two flag variables. */
125 /* Nonzero if this is an "M" variant of the processor. */
126 int arm_fast_multiply = 0;
128 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
131 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
134 /* Nonzero if this chip can benefit from load scheduling. */
135 int arm_ld_sched = 0;
137 /* Nonzero if this chip is a StrongARM. */
138 int arm_is_strong = 0;
140 /* Nonzero if this chip is a an ARM6 or an ARM7. */
141 int arm_is_6_or_7 = 0;
143 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
144 must report the mode of the memory reference from PRINT_OPERAND to
145 PRINT_OPERAND_ADDRESS. */
146 enum machine_mode output_memory_reference_mode;
148 /* Nonzero if the prologue must setup `fp'. */
149 int current_function_anonymous_args;
151 /* The register number to be used for the PIC offset register. */
152 const char * arm_pic_register_string = NULL;
153 int arm_pic_register = 9;
155 /* Set to one if we think that lr is only saved because of subroutine calls,
156 but all of these can be `put after' return insns */
157 int lr_save_eliminated;
159 /* Set to 1 when a return insn is output, this means that the epilogue
161 static int return_used_this_function;
163 /* Set to 1 after arm_reorg has started. Reset to start at the start of
164 the next function. */
165 static int after_arm_reorg = 0;
167 /* The maximum number of insns to be used when loading a constant. */
168 static int arm_constant_limit = 3;
170 /* For an explanation of these variables, see final_prescan_insn below. */
172 enum arm_cond_code arm_current_cc;
174 int arm_target_label;
176 /* The condition codes of the ARM, and the inverse function. */
177 char * arm_condition_codes[] =
179 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
180 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
183 static enum arm_cond_code get_arm_condition_code ();
185 #define streq(string1, string2) (strcmp (string1, string2) == 0)
187 /* Initialization code */
195 /* Not all of these give usefully different compilation alternatives,
196 but there is no simple way of generalizing them. */
197 static struct processors all_cores[] =
201 {"arm2", FL_CO_PROC | FL_MODE26 },
202 {"arm250", FL_CO_PROC | FL_MODE26 },
203 {"arm3", FL_CO_PROC | FL_MODE26 },
204 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
205 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
206 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm610", FL_MODE26 | FL_MODE32 },
208 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
210 /* arm7m doesn't exist on its own, but only with D, (and I), but
211 those don't alter the code, so arm7m is sometimes used. */
212 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
213 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
214 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
215 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
216 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
217 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
218 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
219 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
220 {"arm710", FL_MODE26 | FL_MODE32 },
221 {"arm720", FL_MODE26 | FL_MODE32 },
222 {"arm710c", FL_MODE26 | FL_MODE32 },
223 {"arm7100", FL_MODE26 | FL_MODE32 },
224 {"arm7500", FL_MODE26 | FL_MODE32 },
225 /* Doesn't have an external co-proc, but does have embedded fpu. */
226 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
227 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
228 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
229 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
230 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
231 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
232 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
233 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
234 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
235 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
236 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
241 static struct processors all_architectures[] =
243 /* ARM Architectures */
245 { "armv2", FL_CO_PROC | FL_MODE26 },
246 { "armv2a", FL_CO_PROC | FL_MODE26 },
247 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
248 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
249 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
250 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
251 implementations that support it, so we will leave it out for now. */
252 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
253 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
257 /* This is a magic stucture. The 'string' field is magically filled in
258 with a pointer to the value specified by the user on the command line
259 assuming that the user has specified such a value. */
261 struct arm_cpu_select arm_select[] =
263 /* string name processors */
264 { NULL, "-mcpu=", all_cores },
265 { NULL, "-march=", all_architectures },
266 { NULL, "-mtune=", all_cores }
269 /* Return the number of bits set in value' */
274 unsigned int count = 0;
278 value &= ~(value & - value);
285 /* Fix up any incompatible options that the user has specified.
286 This has now turned into a maze. */
288 arm_override_options ()
292 /* Set up the flags based on the cpu/architecture selected by the user. */
293 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
295 struct arm_cpu_select * ptr = arm_select + i;
297 if (ptr->string != NULL && ptr->string[0] != '\0')
299 const struct processors * sel;
301 for (sel = ptr->processors; sel->name != NULL; sel ++)
302 if (streq (ptr->string, sel->name))
305 tune_flags = sel->flags;
308 /* If we have been given an architecture and a processor
309 make sure that they are compatible. We only generate
310 a warning though, and we prefer the CPU over the
312 if (insn_flags != 0 && (insn_flags ^ sel->flags))
313 warning ("switch -mcpu=%s conflicts with -march= switch",
316 insn_flags = sel->flags;
322 if (sel->name == NULL)
323 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
327 /* If the user did not specify a processor, choose one for them. */
330 struct processors * sel;
332 static struct cpu_default
339 { TARGET_CPU_arm2, "arm2" },
340 { TARGET_CPU_arm6, "arm6" },
341 { TARGET_CPU_arm610, "arm610" },
342 { TARGET_CPU_arm710, "arm710" },
343 { TARGET_CPU_arm7m, "arm7m" },
344 { TARGET_CPU_arm7500fe, "arm7500fe" },
345 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
346 { TARGET_CPU_arm8, "arm8" },
347 { TARGET_CPU_arm810, "arm810" },
348 { TARGET_CPU_arm9, "arm9" },
349 { TARGET_CPU_strongarm, "strongarm" },
350 { TARGET_CPU_generic, "arm" },
353 struct cpu_default * def;
355 /* Find the default. */
356 for (def = cpu_defaults; def->name; def ++)
357 if (def->cpu == TARGET_CPU_DEFAULT)
360 /* Make sure we found the default CPU. */
361 if (def->name == NULL)
364 /* Find the default CPU's flags. */
365 for (sel = all_cores; sel->name != NULL; sel ++)
366 if (streq (def->name, sel->name))
369 if (sel->name == NULL)
372 insn_flags = sel->flags;
374 /* Now check to see if the user has specified some command line
375 switch that require certain abilities from the cpu. */
378 if (TARGET_INTERWORK)
380 sought |= (FL_THUMB | FL_MODE32);
382 /* Force apcs-32 to be used for interworking. */
383 target_flags |= ARM_FLAG_APCS_32;
385 /* There are no ARM processor that supports both APCS-26 and
386 interworking. Therefore we force FL_MODE26 to be removed
387 from insn_flags here (if it was set), so that the search
388 below will always be able to find a compatible processor. */
389 insn_flags &= ~ FL_MODE26;
392 if (! TARGET_APCS_32)
395 if (sought != 0 && ((sought & insn_flags) != sought))
397 /* Try to locate a CPU type that supports all of the abilities
398 of the default CPU, plus the extra abilities requested by
400 for (sel = all_cores; sel->name != NULL; sel ++)
401 if ((sel->flags & sought) == (sought | insn_flags))
404 if (sel->name == NULL)
406 unsigned int current_bit_count = 0;
407 struct processors * best_fit = NULL;
409 /* Ideally we would like to issue an error message here
410 saying that it was not possible to find a CPU compatible
411 with the default CPU, but which also supports the command
412 line options specified by the programmer, and so they
413 ought to use the -mcpu=<name> command line option to
414 override the default CPU type.
416 Unfortunately this does not work with multilibing. We
417 need to be able to support multilibs for -mapcs-26 and for
418 -mthumb-interwork and there is no CPU that can support both
419 options. Instead if we cannot find a cpu that has both the
420 characteristics of the default cpu and the given command line
421 options we scan the array again looking for a best match. */
422 for (sel = all_cores; sel->name != NULL; sel ++)
423 if ((sel->flags & sought) == sought)
427 count = bit_count (sel->flags & insn_flags);
429 if (count >= current_bit_count)
432 current_bit_count = count;
436 if (best_fit == NULL)
442 insn_flags = sel->flags;
446 /* If tuning has not been specified, tune for whichever processor or
447 architecture has been selected. */
449 tune_flags = insn_flags;
451 /* Make sure that the processor choice does not conflict with any of the
452 other command line choices. */
453 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
455 /* If APCS-32 was not the default then it must have been set by the
456 user, so issue a warning message. If the user has specified
457 "-mapcs-32 -mcpu=arm2" then we loose here. */
458 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
459 warning ("target CPU does not support APCS-32" );
460 target_flags &= ~ ARM_FLAG_APCS_32;
462 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
464 warning ("target CPU does not support APCS-26" );
465 target_flags |= ARM_FLAG_APCS_32;
468 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
470 warning ("target CPU does not support interworking" );
471 target_flags &= ~ARM_FLAG_INTERWORK;
474 /* If interworking is enabled then APCS-32 must be selected as well. */
475 if (TARGET_INTERWORK)
477 if (! TARGET_APCS_32)
478 warning ("interworking forces APCS-32 to be used" );
479 target_flags |= ARM_FLAG_APCS_32;
482 if (TARGET_APCS_STACK && ! TARGET_APCS)
484 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
485 target_flags |= ARM_FLAG_APCS_FRAME;
488 if (TARGET_POKE_FUNCTION_NAME)
489 target_flags |= ARM_FLAG_APCS_FRAME;
491 if (TARGET_APCS_REENT && flag_pic)
492 fatal ("-fpic and -mapcs-reent are incompatible");
494 if (TARGET_APCS_REENT)
495 warning ("APCS reentrant code not supported. Ignored");
497 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
498 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
500 if (TARGET_BUGGY_RETURN_IN_MEMORY && TARGET_ATPCS)
502 warning ("-mbuggy-return-in-memory is overriden by -matpcs.");
503 target_flags &= ~ARM_FLAG_BUGGY_RETURN_IN_MEMORY;
506 /* If stack checking is disabled, we can use r10 as the PIC register,
507 which keeps r9 available. */
508 if (flag_pic && ! TARGET_APCS_STACK)
509 arm_pic_register = 10;
511 if (TARGET_APCS_FLOAT)
512 warning ("Passing floating point arguments in fp regs not yet supported");
514 /* Initialise boolean versions of the flags, for use in the arm.md file. */
515 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
516 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
517 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
519 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
520 arm_is_strong = (tune_flags & FL_STRONG) != 0;
521 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
522 && !(tune_flags & FL_ARCH4)) != 0;
524 /* Default value for floating point code... if no co-processor
525 bus, then schedule for emulated floating point. Otherwise,
526 assume the user has an FPA.
527 Note: this does not prevent use of floating point instructions,
528 -msoft-float does that. */
529 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
533 if (streq (target_fp_name, "2"))
534 arm_fpu_arch = FP_SOFT2;
535 else if (streq (target_fp_name, "3"))
536 arm_fpu_arch = FP_SOFT3;
538 fatal ("Invalid floating point emulation option: -mfpe-%s",
542 arm_fpu_arch = FP_DEFAULT;
544 if (TARGET_FPE && arm_fpu != FP_HARD)
547 /* For arm2/3 there is no need to do any scheduling if there is only
548 a floating point emulator, or we are doing software floating-point. */
549 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
550 && (tune_flags & FL_MODE32) == 0)
551 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
553 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
555 if (structure_size_string != NULL)
557 int size = strtol (structure_size_string, NULL, 0);
559 if (size == 8 || size == 32)
560 arm_structure_size_boundary = size;
562 warning ("Structure size boundary can only be set to 8 or 32");
565 if (arm_pic_register_string != NULL)
570 warning ("-mpic-register= is useless without -fpic");
572 pic_register = decode_reg_name (arm_pic_register_string);
574 /* Prevent the user from choosing an obviously stupid PIC register. */
575 if (pic_register < 0 || call_used_regs[pic_register]
576 || pic_register == HARD_FRAME_POINTER_REGNUM
577 || pic_register == STACK_POINTER_REGNUM
578 || pic_register >= PC_REGNUM)
579 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
581 arm_pic_register = pic_register;
584 /* If optimizing for space, don't synthesize constants.
585 For processors with load scheduling, it never costs more than 2 cycles
586 to load a constant, and the load scheduler may well reduce that to 1. */
587 if (optimize_size || (tune_flags & FL_LDSCHED))
588 arm_constant_limit = 1;
590 /* If optimizing for size, bump the number of instructions that we
591 are prepared to conditionally execute (even on a StrongARM).
592 Otherwise for the StrongARM, which has early execution of branches,
593 a sequence that is worth skipping is shorter. */
595 max_insns_skipped = 6;
596 else if (arm_is_strong)
597 max_insns_skipped = 3;
599 /* Register global variables with the garbage collector. */
606 ggc_add_rtx_root (&arm_compare_op0, 1);
607 ggc_add_rtx_root (&arm_compare_op1, 1);
608 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
609 /* XXX: What about the minipool tables? */
613 /* Return 1 if it is possible to return using a single instruction */
616 use_return_insn (iscond)
621 if (!reload_completed
622 || current_function_pretend_args_size
623 || current_function_anonymous_args
624 || ((get_frame_size () + current_function_outgoing_args_size != 0)
625 && !(TARGET_APCS && frame_pointer_needed)))
628 /* Can't be done if interworking with Thumb, and any registers have been
629 stacked. Similarly, on StrongARM, conditional returns are expensive
630 if they aren't taken and registers have been stacked. */
631 if (iscond && arm_is_strong && frame_pointer_needed)
633 if ((iscond && arm_is_strong)
636 for (regno = 0; regno < 16; regno++)
637 if (regs_ever_live[regno] && ! call_used_regs[regno])
640 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
644 /* Can't be done if any of the FPU regs are pushed, since this also
646 for (regno = 16; regno < 24; regno++)
647 if (regs_ever_live[regno] && ! call_used_regs[regno])
650 /* If a function is naked, don't use the "return" insn. */
651 if (arm_naked_function_p (current_function_decl))
657 /* Return TRUE if int I is a valid immediate ARM constant. */
663 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
665 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
666 be all zero, or all one. */
667 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
668 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
669 != ((~(unsigned HOST_WIDE_INT) 0)
670 & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
673 /* Fast return for 0 and powers of 2 */
674 if ((i & (i - 1)) == 0)
679 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
682 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
683 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
684 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
689 /* Return true if I is a valid constant for the operation CODE. */
691 const_ok_for_op (i, code)
695 if (const_ok_for_arm (i))
701 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
703 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
709 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
716 /* Emit a sequence of insns to handle a large constant.
717 CODE is the code of the operation required, it can be any of SET, PLUS,
718 IOR, AND, XOR, MINUS;
719 MODE is the mode in which the operation is being performed;
720 VAL is the integer to operate on;
721 SOURCE is the other operand (a register, or a null-pointer for SET);
722 SUBTARGETS means it is safe to create scratch registers if that will
723 either produce a simpler sequence, or we will want to cse the values.
724 Return value is the number of insns emitted. */
727 arm_split_constant (code, mode, val, target, source, subtargets)
729 enum machine_mode mode;
735 if (subtargets || code == SET
736 || (GET_CODE (target) == REG && GET_CODE (source) == REG
737 && REGNO (target) != REGNO (source)))
739 /* After arm_reorg has been called, we can't fix up expensive
740 constants by pushing them into memory so we must synthesise
741 them in-line, regardless of the cost. This is only likely to
742 be more costly on chips that have load delay slots and we are
743 compiling without running the scheduler (so no splitting
744 occurred before the final instruction emission).
746 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
748 if (! after_arm_reorg
749 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
750 > arm_constant_limit + (code != SET)))
754 /* Currently SET is the only monadic value for CODE, all
755 the rest are diadic. */
756 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
761 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
763 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
764 /* For MINUS, the value is subtracted from, since we never
765 have subtraction of a constant. */
767 emit_insn (gen_rtx_SET (VOIDmode, target,
768 gen_rtx (code, mode, temp, source)));
770 emit_insn (gen_rtx_SET (VOIDmode, target,
771 gen_rtx (code, mode, source, temp)));
777 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
780 /* As above, but extra parameter GENERATE which, if clear, suppresses
783 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
785 enum machine_mode mode;
794 int can_negate_initial = 0;
797 int num_bits_set = 0;
798 int set_sign_bit_copies = 0;
799 int clear_sign_bit_copies = 0;
800 int clear_zero_bit_copies = 0;
801 int set_zero_bit_copies = 0;
803 unsigned HOST_WIDE_INT temp1, temp2;
804 unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
806 /* find out which operations are safe for a given CODE. Also do a quick
807 check for degenerate cases; these can occur when DImode operations
819 can_negate_initial = 1;
823 if (remainder == 0xffffffffUL)
826 emit_insn (gen_rtx_SET (VOIDmode, target,
827 GEN_INT (ARM_SIGN_EXTEND (val))));
832 if (reload_completed && rtx_equal_p (target, source))
835 emit_insn (gen_rtx_SET (VOIDmode, target, source));
844 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
847 if (remainder == 0xffffffffUL)
849 if (reload_completed && rtx_equal_p (target, source))
852 emit_insn (gen_rtx_SET (VOIDmode, target, source));
861 if (reload_completed && rtx_equal_p (target, source))
864 emit_insn (gen_rtx_SET (VOIDmode, target, source));
867 if (remainder == 0xffffffffUL)
870 emit_insn (gen_rtx_SET (VOIDmode, target,
871 gen_rtx_NOT (mode, source)));
875 /* We don't know how to handle this yet below. */
879 /* We treat MINUS as (val - source), since (source - val) is always
880 passed as (source + (-val)). */
884 emit_insn (gen_rtx_SET (VOIDmode, target,
885 gen_rtx_NEG (mode, source)));
888 if (const_ok_for_arm (val))
891 emit_insn (gen_rtx_SET (VOIDmode, target,
892 gen_rtx_MINUS (mode, GEN_INT (val),
904 /* If we can do it in one insn get out quickly */
905 if (const_ok_for_arm (val)
906 || (can_negate_initial && const_ok_for_arm (-val))
907 || (can_invert && const_ok_for_arm (~val)))
910 emit_insn (gen_rtx_SET (VOIDmode, target,
911 (source ? gen_rtx (code, mode, source,
918 /* Calculate a few attributes that may be useful for specific
921 for (i = 31; i >= 0; i--)
923 if ((remainder & (1 << i)) == 0)
924 clear_sign_bit_copies++;
929 for (i = 31; i >= 0; i--)
931 if ((remainder & (1 << i)) != 0)
932 set_sign_bit_copies++;
937 for (i = 0; i <= 31; i++)
939 if ((remainder & (1 << i)) == 0)
940 clear_zero_bit_copies++;
945 for (i = 0; i <= 31; i++)
947 if ((remainder & (1 << i)) != 0)
948 set_zero_bit_copies++;
956 /* See if we can do this by sign_extending a constant that is known
957 to be negative. This is a good, way of doing it, since the shift
958 may well merge into a subsequent insn. */
959 if (set_sign_bit_copies > 1)
962 (temp1 = ARM_SIGN_EXTEND (remainder
963 << (set_sign_bit_copies - 1))))
967 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
968 emit_insn (gen_rtx_SET (VOIDmode, new_src,
970 emit_insn (gen_ashrsi3 (target, new_src,
971 GEN_INT (set_sign_bit_copies - 1)));
975 /* For an inverted constant, we will need to set the low bits,
976 these will be shifted out of harm's way. */
977 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
978 if (const_ok_for_arm (~temp1))
982 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
983 emit_insn (gen_rtx_SET (VOIDmode, new_src,
985 emit_insn (gen_ashrsi3 (target, new_src,
986 GEN_INT (set_sign_bit_copies - 1)));
992 /* See if we can generate this by setting the bottom (or the top)
993 16 bits, and then shifting these into the other half of the
994 word. We only look for the simplest cases, to do more would cost
995 too much. Be careful, however, not to generate this when the
996 alternative would take fewer insns. */
997 if (val & 0xffff0000UL)
999 temp1 = remainder & 0xffff0000UL;
1000 temp2 = remainder & 0x0000ffff;
1002 /* Overlaps outside this range are best done using other methods. */
1003 for (i = 9; i < 24; i++)
1005 if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
1006 && ! const_ok_for_arm (temp2))
1008 rtx new_src = (subtargets
1009 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1011 insns = arm_gen_constant (code, mode, temp2, new_src,
1012 source, subtargets, generate);
1015 emit_insn (gen_rtx_SET
1018 gen_rtx_ASHIFT (mode, source,
1025 /* Don't duplicate cases already considered. */
1026 for (i = 17; i < 24; i++)
1028 if (((temp1 | (temp1 >> i)) == remainder)
1029 && ! const_ok_for_arm (temp1))
1031 rtx new_src = (subtargets
1032 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1034 insns = arm_gen_constant (code, mode, temp1, new_src,
1035 source, subtargets, generate);
1039 (gen_rtx_SET (VOIDmode, target,
1042 gen_rtx_LSHIFTRT (mode, source,
1053 /* If we have IOR or XOR, and the constant can be loaded in a
1054 single instruction, and we can find a temporary to put it in,
1055 then this can be done in two instructions instead of 3-4. */
1057 /* TARGET can't be NULL if SUBTARGETS is 0 */
1058 || (reload_completed && ! reg_mentioned_p (target, source)))
1060 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1064 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1066 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1067 emit_insn (gen_rtx_SET (VOIDmode, target,
1068 gen_rtx (code, mode, source, sub)));
1077 if (set_sign_bit_copies > 8
1078 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1082 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1083 rtx shift = GEN_INT (set_sign_bit_copies);
1085 emit_insn (gen_rtx_SET (VOIDmode, sub,
1087 gen_rtx_ASHIFT (mode,
1090 emit_insn (gen_rtx_SET (VOIDmode, target,
1092 gen_rtx_LSHIFTRT (mode, sub,
1098 if (set_zero_bit_copies > 8
1099 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1103 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1104 rtx shift = GEN_INT (set_zero_bit_copies);
1106 emit_insn (gen_rtx_SET (VOIDmode, sub,
1108 gen_rtx_LSHIFTRT (mode,
1111 emit_insn (gen_rtx_SET (VOIDmode, target,
1113 gen_rtx_ASHIFT (mode, sub,
1119 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1123 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1124 emit_insn (gen_rtx_SET (VOIDmode, sub,
1125 gen_rtx_NOT (mode, source)));
1128 sub = gen_reg_rtx (mode);
1129 emit_insn (gen_rtx_SET (VOIDmode, sub,
1130 gen_rtx_AND (mode, source,
1132 emit_insn (gen_rtx_SET (VOIDmode, target,
1133 gen_rtx_NOT (mode, sub)));
1140 /* See if two shifts will do 2 or more insn's worth of work. */
1141 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1143 HOST_WIDE_INT shift_mask = ((0xffffffffUL
1144 << (32 - clear_sign_bit_copies))
1147 if ((remainder | shift_mask) != 0xffffffffUL)
1151 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1152 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1153 new_src, source, subtargets, 1);
1158 rtx targ = subtargets ? NULL_RTX : target;
1159 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1160 targ, source, subtargets, 0);
1166 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1167 rtx shift = GEN_INT (clear_sign_bit_copies);
1169 emit_insn (gen_ashlsi3 (new_src, source, shift));
1170 emit_insn (gen_lshrsi3 (target, new_src, shift));
1176 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1178 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1180 if ((remainder | shift_mask) != 0xffffffffUL)
1184 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1186 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1187 new_src, source, subtargets, 1);
1192 rtx targ = subtargets ? NULL_RTX : target;
1194 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1195 targ, source, subtargets, 0);
1201 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1202 rtx shift = GEN_INT (clear_zero_bit_copies);
1204 emit_insn (gen_lshrsi3 (new_src, source, shift));
1205 emit_insn (gen_ashlsi3 (target, new_src, shift));
1217 for (i = 0; i < 32; i++)
1218 if (remainder & (1 << i))
1221 if (code == AND || (can_invert && num_bits_set > 16))
1222 remainder = (~remainder) & 0xffffffffUL;
1223 else if (code == PLUS && num_bits_set > 16)
1224 remainder = (-remainder) & 0xffffffffUL;
1231 /* Now try and find a way of doing the job in either two or three
1233 We start by looking for the largest block of zeros that are aligned on
1234 a 2-bit boundary, we then fill up the temps, wrapping around to the
1235 top of the word when we drop off the bottom.
1236 In the worst case this code should produce no more than four insns. */
1239 int best_consecutive_zeros = 0;
1241 for (i = 0; i < 32; i += 2)
1243 int consecutive_zeros = 0;
1245 if (! (remainder & (3 << i)))
1247 while ((i < 32) && ! (remainder & (3 << i)))
1249 consecutive_zeros += 2;
1252 if (consecutive_zeros > best_consecutive_zeros)
1254 best_consecutive_zeros = consecutive_zeros;
1255 best_start = i - consecutive_zeros;
1261 /* Now start emitting the insns, starting with the one with the highest
1262 bit set: we do this so that the smallest number will be emitted last;
1263 this is more likely to be combinable with addressing insns. */
1271 if (remainder & (3 << (i - 2)))
1276 temp1 = remainder & ((0x0ff << end)
1277 | ((i < end) ? (0xff >> (32 - end)) : 0));
1278 remainder &= ~temp1;
1285 emit_insn (gen_rtx_SET (VOIDmode,
1286 new_src = (subtargets
1287 ? gen_reg_rtx (mode)
1290 ? ~temp1 : temp1)));
1291 else if (code == MINUS)
1292 emit_insn (gen_rtx_SET (VOIDmode,
1293 new_src = (subtargets
1294 ? gen_reg_rtx (mode)
1296 gen_rtx (code, mode, GEN_INT (temp1),
1299 emit_insn (gen_rtx_SET (VOIDmode,
1300 new_src = (remainder
1302 ? gen_reg_rtx (mode)
1305 gen_rtx (code, mode, source,
1306 GEN_INT (can_invert ? ~temp1
1318 else if (code == MINUS)
1325 } while (remainder);
1330 /* Canonicalize a comparison so that we are more likely to recognize it.
1331 This can be done for a few constant compares, where we can make the
1332 immediate value easier to load. */
1334 arm_canonicalize_comparison (code, op1)
1338 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1348 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1350 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1352 *op1 = GEN_INT (i+1);
1353 return code == GT ? GE : LT;
1359 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1360 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1362 *op1 = GEN_INT (i-1);
1363 return code == GE ? GT : LE;
1369 if (i != ~((unsigned HOST_WIDE_INT) 0)
1370 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1372 *op1 = GEN_INT (i + 1);
1373 return code == GTU ? GEU : LTU;
1380 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1382 *op1 = GEN_INT (i - 1);
1383 return code == GEU ? GTU : LEU;
1394 /* Decide whether a type should be returned in memory (true)
1395 or in a register (false). This is called by the macro
1396 RETURN_IN_MEMORY. */
1398 arm_return_in_memory (type)
1401 if (! AGGREGATE_TYPE_P (type))
1402 /* All simple types are returned in registers. */
1405 if (int_size_in_bytes (type) > 4)
1406 /* All structures/unions bigger than one word are returned in memory. */
1410 /* The ATPCS says that any structure or union of no larger than
1411 one word is returned in a register. */
1414 if (TREE_CODE (type) == RECORD_TYPE)
1418 /* For a struct the APCS says that we only return in a register
1419 if the type is 'integer like' and every addressable element
1420 has an offset of zero. For practical purposes this means
1421 that the structure can have at most one non bit-field element
1422 and that this element must be the first one in the structure. */
1424 /* Find the first field, ignoring non FIELD_DECL things which will
1425 have been created by C++. */
1426 for (field = TYPE_FIELDS (type);
1427 field && TREE_CODE (field) != FIELD_DECL;
1428 field = TREE_CHAIN (field))
1432 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1434 /* Check that the first field is valid for returning in a register... */
1436 /* The APCS only says that the structrue must be integer-like. It
1437 does not say that it may not contain integer values. Thus
1438 struct { float a; } should be returned in a register. Earlier
1439 implementations got this wrong. */
1440 if (TARGET_BUGGY_RETURN_IN_MEMORY
1441 && FLOAT_TYPE_P (TREE_TYPE (field)))
1444 /* Similarly the APCS only insists that all the sub-fields of a
1445 structure be addressible. It does not insist that if these
1446 sub-fields themselves are structures that they also conform
1447 to the integer-like specification. This is another thing
1448 that the old compiler did incorrectly. */
1449 if (TARGET_BUGGY_RETURN_IN_MEMORY
1450 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1453 /* Now check the remaining fields, if any. Only bitfields are allowed,
1454 since they are not addressable. */
1455 for (field = TREE_CHAIN (field);
1457 field = TREE_CHAIN (field))
1459 if (TREE_CODE (field) != FIELD_DECL)
1462 if (! DECL_BIT_FIELD_TYPE (field))
1469 if (TREE_CODE (type) == UNION_TYPE)
1473 /* Unions can be returned in registers if every element is
1474 integral, or can be returned in an integer register. */
1475 for (field = TYPE_FIELDS (type);
1477 field = TREE_CHAIN (field))
1479 if (TREE_CODE (field) != FIELD_DECL)
1482 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1485 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1492 /* XXX Not sure what should be done for
1493 other aggregates so put them in memory. */
1497 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1498 for a call to a function whose data type is FNTYPE.
1499 For a library call, FNTYPE is NULL. */
1501 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1502 CUMULATIVE_ARGS * pcum;
1504 rtx libname ATTRIBUTE_UNUSED;
1505 int indirect ATTRIBUTE_UNUSED;
1507 /* On the ARM, the offset starts at 0. */
1508 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1510 pcum->call_cookie = CALL_NORMAL;
1512 if (TARGET_LONG_CALLS)
1513 pcum->call_cookie = CALL_LONG;
1515 /* Check for long call/short call attributes. The attributes
1516 override any command line option. */
1519 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1520 pcum->call_cookie = CALL_SHORT;
1521 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1522 pcum->call_cookie = CALL_LONG;
1526 /* Determine where to put an argument to a function.
1527 Value is zero to push the argument on the stack,
1528 or a hard register in which to store the argument.
1530 MODE is the argument's machine mode.
1531 TYPE is the data type of the argument (as a tree).
1532 This is null for libcalls where that information may
1534 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1535 the preceding args and about the function being called.
1536 NAMED is nonzero if this argument is a named parameter
1537 (otherwise it is an extra parameter matching an ellipsis). */
1539 arm_function_arg (pcum, mode, type, named)
1540 CUMULATIVE_ARGS * pcum;
1541 enum machine_mode mode;
1542 tree type ATTRIBUTE_UNUSED;
1545 if (mode == VOIDmode)
1546 /* Compute operand 2 of the call insn. */
1547 return GEN_INT (pcum->call_cookie);
1549 if (! named || pcum->nregs >= NUM_ARG_REGS)
1552 return gen_rtx_REG (mode, pcum->nregs);
1555 /* Encode the current state of the #pragma [no_]long_calls. */
1558 OFF, /* No #pramgma [no_]long_calls is in effect. */
1559 LONG, /* #pragma long_calls is in effect. */
1560 SHORT /* #pragma no_long_calls is in effect. */
1563 static arm_pragma_enum arm_pragma_long_calls = OFF;
1565 /* Handle pragmas for compatibility with Intel's compilers.
1566 FIXME: This is incomplete, since it does not handle all
1567 the pragmas that the Intel compilers understand. */
1569 arm_process_pragma (p_getc, p_ungetc, pname)
1570 int (* p_getc) PARAMS ((void)) ATTRIBUTE_UNUSED;
1571 void (* p_ungetc) PARAMS ((int)) ATTRIBUTE_UNUSED;
1574 /* Should be pragma 'far' or equivalent for callx/balx here. */
1575 if (strcmp (pname, "long_calls") == 0)
1576 arm_pragma_long_calls = LONG;
1577 else if (strcmp (pname, "no_long_calls") == 0)
1578 arm_pragma_long_calls = SHORT;
1579 else if (strcmp (pname, "long_calls_off") == 0)
1580 arm_pragma_long_calls = OFF;
1587 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1588 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1589 assigned to TYPE. */
1591 arm_valid_type_attribute_p (type, attributes, identifier, args)
1593 tree attributes ATTRIBUTE_UNUSED;
1597 if ( TREE_CODE (type) != FUNCTION_TYPE
1598 && TREE_CODE (type) != METHOD_TYPE
1599 && TREE_CODE (type) != FIELD_DECL
1600 && TREE_CODE (type) != TYPE_DECL)
1603 /* Function calls made to this symbol must be done indirectly, because
1604 it may lie outside of the 26 bit addressing range of a normal function
1606 if (is_attribute_p ("long_call", identifier))
1607 return (args == NULL_TREE);
1609 /* Whereas these functions are always known to reside within the 26 bit
1610 addressing range. */
1611 if (is_attribute_p ("short_call", identifier))
1612 return (args == NULL_TREE);
1617 /* Return 0 if the attributes for two types are incompatible, 1 if they
1618 are compatible, and 2 if they are nearly compatible (which causes a
1619 warning to be generated). */
1621 arm_comp_type_attributes (type1, type2)
1627 /* Check for mismatch of non-default calling convention. */
1628 if (TREE_CODE (type1) != FUNCTION_TYPE)
1631 /* Check for mismatched call attributes. */
1632 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1633 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1634 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1635 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1637 /* Only bother to check if an attribute is defined. */
1638 if (l1 | l2 | s1 | s2)
1640 /* If one type has an attribute, the other must have the same attribute. */
1641 if ((l1 != l2) || (s1 != s2))
1644 /* Disallow mixed attributes. */
1645 if ((l1 & s2) || (l2 & s1))
1652 /* Check the ARM specific attributes on the given function decl.
1653 If any of them would prevent the function from being inlined,
1654 return a tesxtual description of why not. Otherwise return NULL. */
1656 arm_function_attribute_inlineable_p (fndecl)
1659 if (lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (fndecl)))
1660 return "naked functions cannot be inlined";
1662 /* Allow functions with short_call and long_call attributes to be inlined. */
1666 /* Encode long_call or short_call attribute by prefixing
1667 symbol name in DECL with a special character FLAG. */
1669 arm_encode_call_attribute (decl, flag)
1673 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1674 int len = strlen (str);
1677 if (TREE_CODE (decl) != FUNCTION_DECL)
1680 /* Do not allow weak functions to be treated as short call. */
1681 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1685 newstr = ggc_alloc_string (NULL, len + 2);
1687 newstr = permalloc (len + 2);
1689 sprintf (newstr, "%c%s", flag, str);
1691 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1694 /* Assigns default attributes to newly defined type. This is used to
1695 set short_call/long_call attributes for function types of
1696 functions defined inside corresponding #pragma scopes. */
1698 arm_set_default_type_attributes (type)
1701 /* Add __attribute__ ((long_call)) to all functions, when
1702 inside #pragma long_calls or __attribute__ ((short_call)),
1703 when inside #pragma no_long_calls. */
1704 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
1706 tree type_attr_list, attr_name;
1707 type_attr_list = TYPE_ATTRIBUTES (type);
1709 if (arm_pragma_long_calls == LONG)
1710 attr_name = get_identifier ("long_call");
1711 else if (arm_pragma_long_calls == SHORT)
1712 attr_name = get_identifier ("short_call");
1716 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
1717 TYPE_ATTRIBUTES (type) = type_attr_list;
1721 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1722 defined within the current compilation unit. If this caanot be
1723 determined, then 0 is returned. */
1725 current_file_function_operand (sym_ref)
1728 /* This is a bit of a fib. A function will have a short call flag
1729 applied to its name if it has the short call attribute, or it has
1730 already been defined within the current compilation unit. */
1731 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
1734 /* The current funciton is always defined within the current compilation
1735 unit. if it s a weak defintion however, then this may not be the real
1736 defintion of the function, and so we have to say no. */
1737 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
1738 && ! DECL_WEAK (current_function_decl))
1741 /* We cannot make the determination - default to returning 0. */
1745 /* Return non-zero if a 32 bit "long_call" should be generated for
1746 this call. We generate a long_call if the function:
1748 a. has an __attribute__((long call))
1749 or b. is within the scope of a #pragma long_calls
1750 or c. the -mlong-calls command line switch has been specified
1752 However we do not generate a long call if the function:
1754 d. has an __attribute__ ((short_call))
1755 or e. is inside the scope of a #pragma no_long_calls
1756 or f. has an __attribute__ ((section))
1757 or g. is defined within the current compilation unit.
1759 This function will be called by C fragments contained in the machine
1760 description file. CALL_REF and CALL_COOKIE correspond to the matched
1761 rtl operands. CALL_SYMBOL is used to distinguish between
1762 two different callers of the function. It is set to 1 in the
1763 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1764 and "call_value" patterns. This is because of the difference in the
1765 SYM_REFs passed by these patterns. */
1767 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
1774 if (GET_CODE (sym_ref) != MEM)
1777 sym_ref = XEXP (sym_ref, 0);
1780 if (GET_CODE (sym_ref) != SYMBOL_REF)
1783 if (call_cookie & CALL_SHORT)
1786 if (TARGET_LONG_CALLS && flag_function_sections)
1789 if (current_file_function_operand (sym_ref, VOIDmode))
1792 return (call_cookie & CALL_LONG)
1793 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
1794 || TARGET_LONG_CALLS;
1798 legitimate_pic_operand_p (x)
1801 if (CONSTANT_P (x) && flag_pic
1802 && (GET_CODE (x) == SYMBOL_REF
1803 || (GET_CODE (x) == CONST
1804 && GET_CODE (XEXP (x, 0)) == PLUS
1805 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1812 legitimize_pic_address (orig, mode, reg)
1814 enum machine_mode mode;
1817 if (GET_CODE (orig) == SYMBOL_REF)
1819 rtx pic_ref, address;
1825 if (reload_in_progress || reload_completed)
1828 reg = gen_reg_rtx (Pmode);
1833 #ifdef AOF_ASSEMBLER
1834 /* The AOF assembler can generate relocations for these directly, and
1835 understands that the PIC register has to be added into the offset.
1837 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1840 address = gen_reg_rtx (Pmode);
1844 emit_insn (gen_pic_load_addr (address, orig));
1846 pic_ref = gen_rtx_MEM (Pmode,
1847 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1849 RTX_UNCHANGING_P (pic_ref) = 1;
1850 insn = emit_move_insn (reg, pic_ref);
1852 current_function_uses_pic_offset_table = 1;
1853 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1855 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1859 else if (GET_CODE (orig) == CONST)
1863 if (GET_CODE (XEXP (orig, 0)) == PLUS
1864 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1869 if (reload_in_progress || reload_completed)
1872 reg = gen_reg_rtx (Pmode);
1875 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1877 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1878 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1879 base == reg ? 0 : reg);
1884 if (GET_CODE (offset) == CONST_INT)
1886 /* The base register doesn't really matter, we only want to
1887 test the index for the appropriate mode. */
1888 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1890 if (! reload_in_progress && ! reload_completed)
1891 offset = force_reg (Pmode, offset);
1896 if (GET_CODE (offset) == CONST_INT)
1897 return plus_constant_for_output (base, INTVAL (offset));
1900 if (GET_MODE_SIZE (mode) > 4
1901 && (GET_MODE_CLASS (mode) == MODE_INT
1902 || TARGET_SOFT_FLOAT))
1904 emit_insn (gen_addsi3 (reg, base, offset));
1908 return gen_rtx_PLUS (Pmode, base, offset);
1910 else if (GET_CODE (orig) == LABEL_REF)
1912 current_function_uses_pic_offset_table = 1;
1916 rtx pic_ref, address = gen_reg_rtx (Pmode);
1918 emit_insn (gen_pic_load_addr (address, orig));
1919 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
1921 emit_move_insn (address, pic_ref);
1943 #ifndef AOF_ASSEMBLER
1944 rtx l1, pic_tmp, pic_tmp2, seq;
1945 rtx global_offset_table;
1947 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
1954 l1 = gen_label_rtx ();
1956 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1957 /* On the ARM the PC register contains 'dot + 8' at the time of the
1959 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1961 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1962 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1964 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1966 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1968 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1969 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1971 seq = gen_sequence ();
1973 emit_insn_after (seq, get_insns ());
1975 /* Need to emit this whether or not we obey regdecls,
1976 since setjmp/longjmp can cause life info to screw up. */
1977 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1978 #endif /* AOF_ASSEMBLER */
1981 #define REG_OR_SUBREG_REG(X) \
1982 (GET_CODE (X) == REG \
1983 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1985 #define REG_OR_SUBREG_RTX(X) \
1986 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1988 #define ARM_FRAME_RTX(X) \
1989 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1990 || (X) == arg_pointer_rtx)
1993 arm_rtx_costs (x, code)
1997 enum machine_mode mode = GET_MODE (x);
1998 enum rtx_code subcode;
2004 /* Memory costs quite a lot for the first word, but subsequent words
2005 load at the equivalent of a single insn each. */
2006 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2007 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2014 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2021 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2023 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2024 + ((GET_CODE (XEXP (x, 0)) == REG
2025 || (GET_CODE (XEXP (x, 0)) == SUBREG
2026 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2028 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2029 || (GET_CODE (XEXP (x, 0)) == SUBREG
2030 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2032 + ((GET_CODE (XEXP (x, 1)) == REG
2033 || (GET_CODE (XEXP (x, 1)) == SUBREG
2034 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2035 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2040 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2041 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2042 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2043 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2046 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2047 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2048 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2049 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2051 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2052 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2053 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2056 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2057 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2058 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2059 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2060 || subcode == ASHIFTRT || subcode == LSHIFTRT
2061 || subcode == ROTATE || subcode == ROTATERT
2063 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2064 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2065 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2066 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2067 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2068 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2069 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2074 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2075 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2076 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2077 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2078 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2082 case AND: case XOR: case IOR:
2085 /* Normally the frame registers will be spilt into reg+const during
2086 reload, so it is a bad idea to combine them with other instructions,
2087 since then they might not be moved outside of loops. As a compromise
2088 we allow integration with ops that have a constant as their second
2090 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2091 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2092 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2093 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2094 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2098 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2099 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2100 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2101 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2104 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2105 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2106 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2107 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2108 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2111 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2112 return (1 + extra_cost
2113 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2114 || subcode == LSHIFTRT || subcode == ASHIFTRT
2115 || subcode == ROTATE || subcode == ROTATERT
2117 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2118 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2119 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2120 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2121 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2122 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2128 /* There is no point basing this on the tuning, since it is always the
2129 fast variant if it exists at all */
2130 if (arm_fast_multiply && mode == DImode
2131 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2132 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2133 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2136 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2140 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2142 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2143 & (unsigned HOST_WIDE_INT) 0xffffffffUL);
2144 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2146 /* Tune as appropriate */
2147 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2149 for (j = 0; i && j < 32; j += booth_unit_size)
2151 i >>= booth_unit_size;
2158 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2159 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2160 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2163 if (arm_fast_multiply && mode == SImode
2164 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2165 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2166 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2167 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2168 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2169 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2174 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2175 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2179 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2181 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2184 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2192 return 4 + (mode == DImode ? 4 : 0);
2195 if (GET_MODE (XEXP (x, 0)) == QImode)
2196 return (4 + (mode == DImode ? 4 : 0)
2197 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2200 switch (GET_MODE (XEXP (x, 0)))
2203 return (1 + (mode == DImode ? 4 : 0)
2204 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2207 return (4 + (mode == DImode ? 4 : 0)
2208 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2211 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2224 arm_adjust_cost (insn, link, dep, cost)
2232 /* XXX This is not strictly true for the FPA. */
2233 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
2234 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
2237 if ((i_pat = single_set (insn)) != NULL
2238 && GET_CODE (SET_SRC (i_pat)) == MEM
2239 && (d_pat = single_set (dep)) != NULL
2240 && GET_CODE (SET_DEST (d_pat)) == MEM)
2242 /* This is a load after a store, there is no conflict if the load reads
2243 from a cached area. Assume that loads from the stack, and from the
2244 constant pool are cached, and that others will miss. This is a
2247 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2248 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2249 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2250 || reg_mentioned_p (hard_frame_pointer_rtx,
2251 XEXP (SET_SRC (i_pat), 0)))
2258 /* This code has been fixed for cross compilation. */
2260 static int fpa_consts_inited = 0;
2262 char * strings_fpa[8] =
2265 "4", "5", "0.5", "10"
2268 static REAL_VALUE_TYPE values_fpa[8];
2276 for (i = 0; i < 8; i++)
2278 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2282 fpa_consts_inited = 1;
2285 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2288 const_double_rtx_ok_for_fpu (x)
2294 if (!fpa_consts_inited)
2297 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2298 if (REAL_VALUE_MINUS_ZERO (r))
2301 for (i = 0; i < 8; i++)
2302 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2308 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2311 neg_const_double_rtx_ok_for_fpu (x)
2317 if (!fpa_consts_inited)
2320 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2321 r = REAL_VALUE_NEGATE (r);
2322 if (REAL_VALUE_MINUS_ZERO (r))
2325 for (i = 0; i < 8; i++)
2326 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2332 /* Predicates for `match_operand' and `match_operator'. */
2334 /* s_register_operand is the same as register_operand, but it doesn't accept
2337 This function exists because at the time it was put in it led to better
2338 code. SUBREG(MEM) always needs a reload in the places where
2339 s_register_operand is used, and this seemed to lead to excessive
2343 s_register_operand (op, mode)
2345 enum machine_mode mode;
2347 if (GET_MODE (op) != mode && mode != VOIDmode)
2350 if (GET_CODE (op) == SUBREG)
2351 op = SUBREG_REG (op);
2353 /* We don't consider registers whose class is NO_REGS
2354 to be a register operand. */
2355 return (GET_CODE (op) == REG
2356 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2357 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2360 /* Only accept reg, subreg(reg), const_int. */
2363 reg_or_int_operand (op, mode)
2365 enum machine_mode mode;
2367 if (GET_CODE (op) == CONST_INT)
2370 if (GET_MODE (op) != mode && mode != VOIDmode)
2373 if (GET_CODE (op) == SUBREG)
2374 op = SUBREG_REG (op);
2376 /* We don't consider registers whose class is NO_REGS
2377 to be a register operand. */
2378 return (GET_CODE (op) == REG
2379 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2380 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2383 /* Return 1 if OP is an item in memory, given that we are in reload. */
2386 reload_memory_operand (op, mode)
2388 enum machine_mode mode ATTRIBUTE_UNUSED;
2390 int regno = true_regnum (op);
2392 return (! CONSTANT_P (op)
2394 || (GET_CODE (op) == REG
2395 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2398 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2399 memory access (architecture V4) */
2401 bad_signed_byte_operand (op, mode)
2403 enum machine_mode mode;
2405 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2410 /* A sum of anything more complex than reg + reg or reg + const is bad */
2411 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2412 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2413 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2414 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2417 /* Big constants are also bad */
2418 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2419 && (INTVAL (XEXP (op, 1)) > 0xff
2420 || -INTVAL (XEXP (op, 1)) > 0xff))
2423 /* Everything else is good, or can will automatically be made so. */
2427 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2430 arm_rhs_operand (op, mode)
2432 enum machine_mode mode;
2434 return (s_register_operand (op, mode)
2435 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2438 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2442 arm_rhsm_operand (op, mode)
2444 enum machine_mode mode;
2446 return (s_register_operand (op, mode)
2447 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2448 || memory_operand (op, mode));
2451 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2452 constant that is valid when negated. */
2455 arm_add_operand (op, mode)
2457 enum machine_mode mode;
2459 return (s_register_operand (op, mode)
2460 || (GET_CODE (op) == CONST_INT
2461 && (const_ok_for_arm (INTVAL (op))
2462 || const_ok_for_arm (-INTVAL (op)))));
2466 arm_not_operand (op, mode)
2468 enum machine_mode mode;
2470 return (s_register_operand (op, mode)
2471 || (GET_CODE (op) == CONST_INT
2472 && (const_ok_for_arm (INTVAL (op))
2473 || const_ok_for_arm (~INTVAL (op)))));
2476 /* Return TRUE if the operand is a memory reference which contains an
2477 offsettable address. */
2479 offsettable_memory_operand (op, mode)
2481 enum machine_mode mode;
2483 if (mode == VOIDmode)
2484 mode = GET_MODE (op);
2486 return (mode == GET_MODE (op)
2487 && GET_CODE (op) == MEM
2488 && offsettable_address_p (reload_completed | reload_in_progress,
2489 mode, XEXP (op, 0)));
2492 /* Return TRUE if the operand is a memory reference which is, or can be
2493 made word aligned by adjusting the offset. */
2495 alignable_memory_operand (op, mode)
2497 enum machine_mode mode;
2501 if (mode == VOIDmode)
2502 mode = GET_MODE (op);
2504 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2509 return ((GET_CODE (reg = op) == REG
2510 || (GET_CODE (op) == SUBREG
2511 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2512 || (GET_CODE (op) == PLUS
2513 && GET_CODE (XEXP (op, 1)) == CONST_INT
2514 && (GET_CODE (reg = XEXP (op, 0)) == REG
2515 || (GET_CODE (XEXP (op, 0)) == SUBREG
2516 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2517 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2520 /* Similar to s_register_operand, but does not allow hard integer
2523 f_register_operand (op, mode)
2525 enum machine_mode mode;
2527 if (GET_MODE (op) != mode && mode != VOIDmode)
2530 if (GET_CODE (op) == SUBREG)
2531 op = SUBREG_REG (op);
2533 /* We don't consider registers whose class is NO_REGS
2534 to be a register operand. */
2535 return (GET_CODE (op) == REG
2536 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2537 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2540 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2543 fpu_rhs_operand (op, mode)
2545 enum machine_mode mode;
2547 if (s_register_operand (op, mode))
2550 if (GET_MODE (op) != mode && mode != VOIDmode)
2553 if (GET_CODE (op) == CONST_DOUBLE)
2554 return const_double_rtx_ok_for_fpu (op);
2560 fpu_add_operand (op, mode)
2562 enum machine_mode mode;
2564 if (s_register_operand (op, mode))
2567 if (GET_MODE (op) != mode && mode != VOIDmode)
2570 if (GET_CODE (op) == CONST_DOUBLE)
2571 return (const_double_rtx_ok_for_fpu (op)
2572 || neg_const_double_rtx_ok_for_fpu (op));
2577 /* Return nonzero if OP is a constant power of two. */
2580 power_of_two_operand (op, mode)
2582 enum machine_mode mode ATTRIBUTE_UNUSED;
2584 if (GET_CODE (op) == CONST_INT)
2586 HOST_WIDE_INT value = INTVAL(op);
2587 return value != 0 && (value & (value - 1)) == 0;
2592 /* Return TRUE for a valid operand of a DImode operation.
2593 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2594 Note that this disallows MEM(REG+REG), but allows
2595 MEM(PRE/POST_INC/DEC(REG)). */
2598 di_operand (op, mode)
2600 enum machine_mode mode;
2602 if (s_register_operand (op, mode))
2605 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
2608 if (GET_CODE (op) == SUBREG)
2609 op = SUBREG_REG (op);
2611 switch (GET_CODE (op))
2618 return memory_address_p (DImode, XEXP (op, 0));
2625 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2626 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2627 Note that this disallows MEM(REG+REG), but allows
2628 MEM(PRE/POST_INC/DEC(REG)). */
2631 soft_df_operand (op, mode)
2633 enum machine_mode mode;
2635 if (s_register_operand (op, mode))
2638 if (mode != VOIDmode && GET_MODE (op) != mode)
2641 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
2644 if (GET_CODE (op) == SUBREG)
2645 op = SUBREG_REG (op);
2647 switch (GET_CODE (op))
2653 return memory_address_p (DFmode, XEXP (op, 0));
2660 /* Return TRUE for valid index operands. */
2663 index_operand (op, mode)
2665 enum machine_mode mode;
2667 return (s_register_operand(op, mode)
2668 || (immediate_operand (op, mode)
2669 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2672 /* Return TRUE for valid shifts by a constant. This also accepts any
2673 power of two on the (somewhat overly relaxed) assumption that the
2674 shift operator in this case was a mult. */
2677 const_shift_operand (op, mode)
2679 enum machine_mode mode;
2681 return (power_of_two_operand (op, mode)
2682 || (immediate_operand (op, mode)
2683 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2686 /* Return TRUE for arithmetic operators which can be combined with a multiply
2690 shiftable_operator (x, mode)
2692 enum machine_mode mode;
2694 if (GET_MODE (x) != mode)
2698 enum rtx_code code = GET_CODE (x);
2700 return (code == PLUS || code == MINUS
2701 || code == IOR || code == XOR || code == AND);
2705 /* Return TRUE for binary logical operators. */
2708 logical_binary_operator (x, mode)
2710 enum machine_mode mode;
2712 if (GET_MODE (x) != mode)
2716 enum rtx_code code = GET_CODE (x);
2718 return (code == IOR || code == XOR || code == AND);
2722 /* Return TRUE for shift operators. */
2725 shift_operator (x, mode)
2727 enum machine_mode mode;
2729 if (GET_MODE (x) != mode)
2733 enum rtx_code code = GET_CODE (x);
2736 return power_of_two_operand (XEXP (x, 1), mode);
2738 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2739 || code == ROTATERT);
2743 int equality_operator (x, mode)
2745 enum machine_mode mode ATTRIBUTE_UNUSED;
2747 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2750 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2753 minmax_operator (x, mode)
2755 enum machine_mode mode;
2757 enum rtx_code code = GET_CODE (x);
2759 if (GET_MODE (x) != mode)
2762 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2765 /* return TRUE if x is EQ or NE */
2767 /* Return TRUE if this is the condition code register, if we aren't given
2768 a mode, accept any class CCmode register */
2771 cc_register (x, mode)
2773 enum machine_mode mode;
2775 if (mode == VOIDmode)
2777 mode = GET_MODE (x);
2778 if (GET_MODE_CLASS (mode) != MODE_CC)
2782 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2788 /* Return TRUE if this is the condition code register, if we aren't given
2789 a mode, accept any class CCmode register which indicates a dominance
2793 dominant_cc_register (x, mode)
2795 enum machine_mode mode;
2797 if (mode == VOIDmode)
2799 mode = GET_MODE (x);
2800 if (GET_MODE_CLASS (mode) != MODE_CC)
2804 if (mode != CC_DNEmode && mode != CC_DEQmode
2805 && mode != CC_DLEmode && mode != CC_DLTmode
2806 && mode != CC_DGEmode && mode != CC_DGTmode
2807 && mode != CC_DLEUmode && mode != CC_DLTUmode
2808 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2811 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2817 /* Return TRUE if X references a SYMBOL_REF. */
2819 symbol_mentioned_p (x)
2822 register const char * fmt;
2825 if (GET_CODE (x) == SYMBOL_REF)
2828 fmt = GET_RTX_FORMAT (GET_CODE (x));
2829 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2835 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2836 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2839 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2846 /* Return TRUE if X references a LABEL_REF. */
2848 label_mentioned_p (x)
2851 register const char * fmt;
2854 if (GET_CODE (x) == LABEL_REF)
2857 fmt = GET_RTX_FORMAT (GET_CODE (x));
2858 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2864 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2865 if (label_mentioned_p (XVECEXP (x, i, j)))
2868 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2879 enum rtx_code code = GET_CODE (x);
2883 else if (code == SMIN)
2885 else if (code == UMIN)
2887 else if (code == UMAX)
2893 /* Return 1 if memory locations are adjacent */
2896 adjacent_mem_locations (a, b)
2899 int val0 = 0, val1 = 0;
2902 if ((GET_CODE (XEXP (a, 0)) == REG
2903 || (GET_CODE (XEXP (a, 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2905 && (GET_CODE (XEXP (b, 0)) == REG
2906 || (GET_CODE (XEXP (b, 0)) == PLUS
2907 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2909 if (GET_CODE (XEXP (a, 0)) == PLUS)
2911 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2912 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2915 reg0 = REGNO (XEXP (a, 0));
2916 if (GET_CODE (XEXP (b, 0)) == PLUS)
2918 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2919 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2922 reg1 = REGNO (XEXP (b, 0));
2923 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2928 /* Return 1 if OP is a load multiple operation. It is known to be
2929 parallel and the first section will be tested. */
2932 load_multiple_operation (op, mode)
2934 enum machine_mode mode ATTRIBUTE_UNUSED;
2936 HOST_WIDE_INT count = XVECLEN (op, 0);
2939 HOST_WIDE_INT i = 1, base = 0;
2943 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2946 /* Check to see if this might be a write-back */
2947 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2952 /* Now check it more carefully */
2953 if (GET_CODE (SET_DEST (elt)) != REG
2954 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2955 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2956 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2957 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2958 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2959 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2960 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2961 != REGNO (SET_DEST (elt)))
2967 /* Perform a quick check so we don't blow up below. */
2969 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2970 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2971 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2974 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2975 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2977 for (; i < count; i++)
2979 elt = XVECEXP (op, 0, i);
2981 if (GET_CODE (elt) != SET
2982 || GET_CODE (SET_DEST (elt)) != REG
2983 || GET_MODE (SET_DEST (elt)) != SImode
2984 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2985 || GET_CODE (SET_SRC (elt)) != MEM
2986 || GET_MODE (SET_SRC (elt)) != SImode
2987 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2988 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2989 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2990 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2997 /* Return 1 if OP is a store multiple operation. It is known to be
2998 parallel and the first section will be tested. */
3001 store_multiple_operation (op, mode)
3003 enum machine_mode mode ATTRIBUTE_UNUSED;
3005 HOST_WIDE_INT count = XVECLEN (op, 0);
3008 HOST_WIDE_INT i = 1, base = 0;
3012 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3015 /* Check to see if this might be a write-back */
3016 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3021 /* Now check it more carefully */
3022 if (GET_CODE (SET_DEST (elt)) != REG
3023 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3024 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3025 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3026 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
3027 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
3028 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
3029 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
3030 != REGNO (SET_DEST (elt)))
3036 /* Perform a quick check so we don't blow up below. */
3038 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3039 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3040 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3043 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3044 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3046 for (; i < count; i++)
3048 elt = XVECEXP (op, 0, i);
3050 if (GET_CODE (elt) != SET
3051 || GET_CODE (SET_SRC (elt)) != REG
3052 || GET_MODE (SET_SRC (elt)) != SImode
3053 || REGNO (SET_SRC (elt)) != src_regno + i - base
3054 || GET_CODE (SET_DEST (elt)) != MEM
3055 || GET_MODE (SET_DEST (elt)) != SImode
3056 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3057 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3058 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3059 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3067 load_multiple_sequence (operands, nops, regs, base, load_offset)
3072 HOST_WIDE_INT * load_offset;
3074 int unsorted_regs[4];
3075 HOST_WIDE_INT unsorted_offsets[4];
3080 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3081 extended if required. */
3082 if (nops < 2 || nops > 4)
3085 /* Loop over the operands and check that the memory references are
3086 suitable (ie immediate offsets from the same base register). At
3087 the same time, extract the target register, and the memory
3089 for (i = 0; i < nops; i++)
3094 /* Convert a subreg of a mem into the mem itself. */
3095 if (GET_CODE (operands[nops + i]) == SUBREG)
3096 operands[nops + i] = alter_subreg(operands[nops + i]);
3098 if (GET_CODE (operands[nops + i]) != MEM)
3101 /* Don't reorder volatile memory references; it doesn't seem worth
3102 looking for the case where the order is ok anyway. */
3103 if (MEM_VOLATILE_P (operands[nops + i]))
3106 offset = const0_rtx;
3108 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3109 || (GET_CODE (reg) == SUBREG
3110 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3111 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3112 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3114 || (GET_CODE (reg) == SUBREG
3115 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3116 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3121 base_reg = REGNO(reg);
3122 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3123 ? REGNO (operands[i])
3124 : REGNO (SUBREG_REG (operands[i])));
3129 if (base_reg != REGNO (reg))
3130 /* Not addressed from the same base register. */
3133 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3134 ? REGNO (operands[i])
3135 : REGNO (SUBREG_REG (operands[i])));
3136 if (unsorted_regs[i] < unsorted_regs[order[0]])
3140 /* If it isn't an integer register, or if it overwrites the
3141 base register but isn't the last insn in the list, then
3142 we can't do this. */
3143 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3144 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3147 unsorted_offsets[i] = INTVAL (offset);
3150 /* Not a suitable memory address. */
3154 /* All the useful information has now been extracted from the
3155 operands into unsorted_regs and unsorted_offsets; additionally,
3156 order[0] has been set to the lowest numbered register in the
3157 list. Sort the registers into order, and check that the memory
3158 offsets are ascending and adjacent. */
3160 for (i = 1; i < nops; i++)
3164 order[i] = order[i - 1];
3165 for (j = 0; j < nops; j++)
3166 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3167 && (order[i] == order[i - 1]
3168 || unsorted_regs[j] < unsorted_regs[order[i]]))
3171 /* Have we found a suitable register? if not, one must be used more
3173 if (order[i] == order[i - 1])
3176 /* Is the memory address adjacent and ascending? */
3177 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3185 for (i = 0; i < nops; i++)
3186 regs[i] = unsorted_regs[order[i]];
3188 *load_offset = unsorted_offsets[order[0]];
3191 if (unsorted_offsets[order[0]] == 0)
3192 return 1; /* ldmia */
3194 if (unsorted_offsets[order[0]] == 4)
3195 return 2; /* ldmib */
3197 if (unsorted_offsets[order[nops - 1]] == 0)
3198 return 3; /* ldmda */
3200 if (unsorted_offsets[order[nops - 1]] == -4)
3201 return 4; /* ldmdb */
3203 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3204 if the offset isn't small enough. The reason 2 ldrs are faster
3205 is because these ARMs are able to do more than one cache access
3206 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3207 whilst the ARM8 has a double bandwidth cache. This means that
3208 these cores can do both an instruction fetch and a data fetch in
3209 a single cycle, so the trick of calculating the address into a
3210 scratch register (one of the result regs) and then doing a load
3211 multiple actually becomes slower (and no smaller in code size).
3212 That is the transformation
3214 ldr rd1, [rbase + offset]
3215 ldr rd2, [rbase + offset + 4]
3219 add rd1, rbase, offset
3220 ldmia rd1, {rd1, rd2}
3222 produces worse code -- '3 cycles + any stalls on rd2' instead of
3223 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3224 access per cycle, the first sequence could never complete in less
3225 than 6 cycles, whereas the ldm sequence would only take 5 and
3226 would make better use of sequential accesses if not hitting the
3229 We cheat here and test 'arm_ld_sched' which we currently know to
3230 only be true for the ARM8, ARM9 and StrongARM. If this ever
3231 changes, then the test below needs to be reworked. */
3232 if (nops == 2 && arm_ld_sched)
3235 /* Can't do it without setting up the offset, only do this if it takes
3236 no more than one insn. */
3237 return (const_ok_for_arm (unsorted_offsets[order[0]])
3238 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3242 emit_ldm_seq (operands, nops)
3248 HOST_WIDE_INT offset;
3252 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3255 strcpy (buf, "ldm%?ia\t");
3259 strcpy (buf, "ldm%?ib\t");
3263 strcpy (buf, "ldm%?da\t");
3267 strcpy (buf, "ldm%?db\t");
3272 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3273 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3276 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3277 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3279 output_asm_insn (buf, operands);
3281 strcpy (buf, "ldm%?ia\t");
3288 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3289 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3291 for (i = 1; i < nops; i++)
3292 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3293 reg_names[regs[i]]);
3295 strcat (buf, "}\t%@ phole ldm");
3297 output_asm_insn (buf, operands);
3302 store_multiple_sequence (operands, nops, regs, base, load_offset)
3307 HOST_WIDE_INT * load_offset;
3309 int unsorted_regs[4];
3310 HOST_WIDE_INT unsorted_offsets[4];
3315 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3316 extended if required. */
3317 if (nops < 2 || nops > 4)
3320 /* Loop over the operands and check that the memory references are
3321 suitable (ie immediate offsets from the same base register). At
3322 the same time, extract the target register, and the memory
3324 for (i = 0; i < nops; i++)
3329 /* Convert a subreg of a mem into the mem itself. */
3330 if (GET_CODE (operands[nops + i]) == SUBREG)
3331 operands[nops + i] = alter_subreg(operands[nops + i]);
3333 if (GET_CODE (operands[nops + i]) != MEM)
3336 /* Don't reorder volatile memory references; it doesn't seem worth
3337 looking for the case where the order is ok anyway. */
3338 if (MEM_VOLATILE_P (operands[nops + i]))
3341 offset = const0_rtx;
3343 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3344 || (GET_CODE (reg) == SUBREG
3345 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3346 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3347 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3349 || (GET_CODE (reg) == SUBREG
3350 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3351 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3356 base_reg = REGNO (reg);
3357 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3358 ? REGNO (operands[i])
3359 : REGNO (SUBREG_REG (operands[i])));
3364 if (base_reg != REGNO (reg))
3365 /* Not addressed from the same base register. */
3368 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3369 ? REGNO (operands[i])
3370 : REGNO (SUBREG_REG (operands[i])));
3371 if (unsorted_regs[i] < unsorted_regs[order[0]])
3375 /* If it isn't an integer register, then we can't do this. */
3376 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3379 unsorted_offsets[i] = INTVAL (offset);
3382 /* Not a suitable memory address. */
3386 /* All the useful information has now been extracted from the
3387 operands into unsorted_regs and unsorted_offsets; additionally,
3388 order[0] has been set to the lowest numbered register in the
3389 list. Sort the registers into order, and check that the memory
3390 offsets are ascending and adjacent. */
3392 for (i = 1; i < nops; i++)
3396 order[i] = order[i - 1];
3397 for (j = 0; j < nops; j++)
3398 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3399 && (order[i] == order[i - 1]
3400 || unsorted_regs[j] < unsorted_regs[order[i]]))
3403 /* Have we found a suitable register? if not, one must be used more
3405 if (order[i] == order[i - 1])
3408 /* Is the memory address adjacent and ascending? */
3409 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3417 for (i = 0; i < nops; i++)
3418 regs[i] = unsorted_regs[order[i]];
3420 *load_offset = unsorted_offsets[order[0]];
3423 if (unsorted_offsets[order[0]] == 0)
3424 return 1; /* stmia */
3426 if (unsorted_offsets[order[0]] == 4)
3427 return 2; /* stmib */
3429 if (unsorted_offsets[order[nops - 1]] == 0)
3430 return 3; /* stmda */
3432 if (unsorted_offsets[order[nops - 1]] == -4)
3433 return 4; /* stmdb */
3439 emit_stm_seq (operands, nops)
3445 HOST_WIDE_INT offset;
3449 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3452 strcpy (buf, "stm%?ia\t");
3456 strcpy (buf, "stm%?ib\t");
3460 strcpy (buf, "stm%?da\t");
3464 strcpy (buf, "stm%?db\t");
3471 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3472 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3474 for (i = 1; i < nops; i++)
3475 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3476 reg_names[regs[i]]);
3478 strcat (buf, "}\t%@ phole stm");
3480 output_asm_insn (buf, operands);
3485 multi_register_push (op, mode)
3487 enum machine_mode mode ATTRIBUTE_UNUSED;
3489 if (GET_CODE (op) != PARALLEL
3490 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3491 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3492 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3499 /* Routines for use with attributes. */
3501 /* Return nonzero if ATTR is a valid attribute for DECL.
3502 ATTRIBUTES are any existing attributes and ARGS are
3503 the arguments supplied with ATTR.
3505 Supported attributes:
3507 naked: don't output any prologue or epilogue code,
3508 the user is assumed to do the right thing.
3511 arm_valid_machine_decl_attribute (decl, attr, args)
3516 if (args != NULL_TREE)
3519 if (is_attribute_p ("naked", attr))
3520 return TREE_CODE (decl) == FUNCTION_DECL;
3524 /* Return non-zero if FUNC is a naked function. */
3527 arm_naked_function_p (func)
3532 if (TREE_CODE (func) != FUNCTION_DECL)
3535 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3536 return a != NULL_TREE;
3539 /* Routines for use in generating RTL */
3542 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3543 in_struct_p, scalar_p)
3555 int sign = up ? 1 : -1;
3558 result = gen_rtx_PARALLEL (VOIDmode,
3559 rtvec_alloc (count + (write_back ? 2 : 0)));
3562 XVECEXP (result, 0, 0)
3563 = gen_rtx_SET (GET_MODE (from), from,
3564 plus_constant (from, count * 4 * sign));
3569 for (j = 0; i < count; i++, j++)
3571 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3572 RTX_UNCHANGING_P (mem) = unchanging_p;
3573 MEM_IN_STRUCT_P (mem) = in_struct_p;
3574 MEM_SCALAR_P (mem) = scalar_p;
3575 XVECEXP (result, 0, i)
3576 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3580 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3586 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3587 in_struct_p, scalar_p)
3599 int sign = up ? 1 : -1;
3602 result = gen_rtx_PARALLEL (VOIDmode,
3603 rtvec_alloc (count + (write_back ? 2 : 0)));
3606 XVECEXP (result, 0, 0)
3607 = gen_rtx_SET (GET_MODE (to), to,
3608 plus_constant (to, count * 4 * sign));
3613 for (j = 0; i < count; i++, j++)
3615 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3616 RTX_UNCHANGING_P (mem) = unchanging_p;
3617 MEM_IN_STRUCT_P (mem) = in_struct_p;
3618 MEM_SCALAR_P (mem) = scalar_p;
3620 XVECEXP (result, 0, i)
3621 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3625 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3631 arm_gen_movstrqi (operands)
3634 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3637 rtx st_src, st_dst, fin_src, fin_dst;
3638 rtx part_bytes_reg = NULL;
3640 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3641 int dst_scalar_p, src_scalar_p;
3643 if (GET_CODE (operands[2]) != CONST_INT
3644 || GET_CODE (operands[3]) != CONST_INT
3645 || INTVAL (operands[2]) > 64
3646 || INTVAL (operands[3]) & 3)
3649 st_dst = XEXP (operands[0], 0);
3650 st_src = XEXP (operands[1], 0);
3652 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3653 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3654 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3655 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3656 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3657 src_scalar_p = MEM_SCALAR_P (operands[1]);
3659 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3660 fin_src = src = copy_to_mode_reg (SImode, st_src);
3662 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3663 out_words_to_go = INTVAL (operands[2]) / 4;
3664 last_bytes = INTVAL (operands[2]) & 3;
3666 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3667 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3669 for (i = 0; in_words_to_go >= 2; i+=4)
3671 if (in_words_to_go > 4)
3672 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3677 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3678 FALSE, src_unchanging_p,
3679 src_in_struct_p, src_scalar_p));
3681 if (out_words_to_go)
3683 if (out_words_to_go > 4)
3684 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3688 else if (out_words_to_go != 1)
3689 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3698 mem = gen_rtx_MEM (SImode, dst);
3699 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3700 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3701 MEM_SCALAR_P (mem) = dst_scalar_p;
3702 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3703 if (last_bytes != 0)
3704 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3708 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3709 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3712 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3713 if (out_words_to_go)
3717 mem = gen_rtx_MEM (SImode, src);
3718 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3719 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3720 MEM_SCALAR_P (mem) = src_scalar_p;
3721 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3722 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3724 mem = gen_rtx_MEM (SImode, dst);
3725 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3726 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3727 MEM_SCALAR_P (mem) = dst_scalar_p;
3728 emit_move_insn (mem, sreg);
3729 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3732 if (in_words_to_go) /* Sanity check */
3738 if (in_words_to_go < 0)
3741 mem = gen_rtx_MEM (SImode, src);
3742 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3743 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3744 MEM_SCALAR_P (mem) = src_scalar_p;
3745 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3748 if (BYTES_BIG_ENDIAN && last_bytes)
3750 rtx tmp = gen_reg_rtx (SImode);
3752 if (part_bytes_reg == NULL)
3755 /* The bytes we want are in the top end of the word */
3756 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3757 GEN_INT (8 * (4 - last_bytes))));
3758 part_bytes_reg = tmp;
3762 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3763 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3764 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3765 MEM_SCALAR_P (mem) = dst_scalar_p;
3766 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3770 tmp = gen_reg_rtx (SImode);
3771 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3772 part_bytes_reg = tmp;
3781 if (part_bytes_reg == NULL)
3784 mem = gen_rtx_MEM (QImode, dst);
3785 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3786 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3787 MEM_SCALAR_P (mem) = dst_scalar_p;
3788 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3792 rtx tmp = gen_reg_rtx (SImode);
3794 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3795 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3796 part_bytes_reg = tmp;
3804 /* Generate a memory reference for a half word, such that it will be loaded
3805 into the top 16 bits of the word. We can assume that the address is
3806 known to be alignable and of the form reg, or plus (reg, const). */
3808 gen_rotated_half_load (memref)
3811 HOST_WIDE_INT offset = 0;
3812 rtx base = XEXP (memref, 0);
3814 if (GET_CODE (base) == PLUS)
3816 offset = INTVAL (XEXP (base, 1));
3817 base = XEXP (base, 0);
3820 /* If we aren't allowed to generate unaligned addresses, then fail. */
3821 if (TARGET_MMU_TRAPS
3822 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3825 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3827 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3830 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3833 static enum machine_mode
3834 select_dominance_cc_mode (x, y, cond_or)
3837 HOST_WIDE_INT cond_or;
3839 enum rtx_code cond1, cond2;
3842 /* Currently we will probably get the wrong result if the individual
3843 comparisons are not simple. This also ensures that it is safe to
3844 reverse a comparison if necessary. */
3845 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3847 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3852 cond1 = reverse_condition (cond1);
3854 /* If the comparisons are not equal, and one doesn't dominate the other,
3855 then we can't do this. */
3857 && ! comparison_dominates_p (cond1, cond2)
3858 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3863 enum rtx_code temp = cond1;
3871 if (cond2 == EQ || ! cond_or)
3876 case LE: return CC_DLEmode;
3877 case LEU: return CC_DLEUmode;
3878 case GE: return CC_DGEmode;
3879 case GEU: return CC_DGEUmode;
3886 if (cond2 == LT || ! cond_or)
3895 if (cond2 == GT || ! cond_or)
3904 if (cond2 == LTU || ! cond_or)
3913 if (cond2 == GTU || ! cond_or)
3921 /* The remaining cases only occur when both comparisons are the
3946 arm_select_cc_mode (op, x, y)
3951 /* All floating point compares return CCFP if it is an equality
3952 comparison, and CCFPE otherwise. */
3953 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3954 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3956 /* A compare with a shifted operand. Because of canonicalization, the
3957 comparison will have to be swapped when we emit the assembler. */
3958 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3959 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3960 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3961 || GET_CODE (x) == ROTATERT))
3964 /* This is a special case that is used by combine to allow a
3965 comparison of a shifted byte load to be split into a zero-extend
3966 followed by a comparison of the shifted integer (only valid for
3967 equalities and unsigned inequalities). */
3968 if (GET_MODE (x) == SImode
3969 && GET_CODE (x) == ASHIFT
3970 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3971 && GET_CODE (XEXP (x, 0)) == SUBREG
3972 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3973 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3974 && (op == EQ || op == NE
3975 || op == GEU || op == GTU || op == LTU || op == LEU)
3976 && GET_CODE (y) == CONST_INT)
3979 /* An operation that sets the condition codes as a side-effect, the
3980 V flag is not set correctly, so we can only use comparisons where
3981 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3983 if (GET_MODE (x) == SImode
3985 && (op == EQ || op == NE || op == LT || op == GE)
3986 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3987 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3988 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3989 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3990 || GET_CODE (x) == LSHIFTRT
3991 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3992 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3995 /* A construct for a conditional compare, if the false arm contains
3996 0, then both conditions must be true, otherwise either condition
3997 must be true. Not all conditions are possible, so CCmode is
3998 returned if it can't be done. */
3999 if (GET_CODE (x) == IF_THEN_ELSE
4000 && (XEXP (x, 2) == const0_rtx
4001 || XEXP (x, 2) == const1_rtx)
4002 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4003 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4004 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4005 INTVAL (XEXP (x, 2)));
4007 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4010 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4011 && GET_CODE (x) == PLUS
4012 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4018 /* X and Y are two things to compare using CODE. Emit the compare insn and
4019 return the rtx for register 0 in the proper mode. FP means this is a
4020 floating point compare: I don't think that it is needed on the arm. */
4023 gen_compare_reg (code, x, y)
4027 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4028 rtx cc_reg = gen_rtx_REG (mode, 24);
4030 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4031 gen_rtx_COMPARE (mode, x, y)));
4037 arm_reload_in_hi (operands)
4040 rtx ref = operands[1];
4042 HOST_WIDE_INT offset = 0;
4044 if (GET_CODE (ref) == SUBREG)
4046 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4047 if (BYTES_BIG_ENDIAN)
4048 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4049 - MIN (UNITS_PER_WORD,
4050 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4051 ref = SUBREG_REG (ref);
4054 if (GET_CODE (ref) == REG)
4056 /* We have a pseudo which has been spilt onto the stack; there
4057 are two cases here: the first where there is a simple
4058 stack-slot replacement and a second where the stack-slot is
4059 out of range, or is used as a subreg. */
4060 if (reg_equiv_mem[REGNO (ref)])
4062 ref = reg_equiv_mem[REGNO (ref)];
4063 base = find_replacement (&XEXP (ref, 0));
4066 /* The slot is out of range, or was dressed up in a SUBREG */
4067 base = reg_equiv_address[REGNO (ref)];
4070 base = find_replacement (&XEXP (ref, 0));
4072 /* Handle the case where the address is too complex to be offset by 1. */
4073 if (GET_CODE (base) == MINUS
4074 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4076 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4078 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4081 else if (GET_CODE (base) == PLUS)
4083 /* The addend must be CONST_INT, or we would have dealt with it above */
4084 HOST_WIDE_INT hi, lo;
4086 offset += INTVAL (XEXP (base, 1));
4087 base = XEXP (base, 0);
4089 /* Rework the address into a legal sequence of insns */
4090 /* Valid range for lo is -4095 -> 4095 */
4093 : -((-offset) & 0xfff));
4095 /* Corner case, if lo is the max offset then we would be out of range
4096 once we have added the additional 1 below, so bump the msb into the
4097 pre-loading insn(s). */
4101 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4102 ^ (HOST_WIDE_INT) 0x80000000UL)
4103 - (HOST_WIDE_INT) 0x80000000UL);
4105 if (hi + lo != offset)
4110 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4112 /* Get the base address; addsi3 knows how to handle constants
4113 that require more than one insn */
4114 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4120 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4121 emit_insn (gen_zero_extendqisi2 (scratch,
4122 gen_rtx_MEM (QImode,
4123 plus_constant (base,
4125 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4126 gen_rtx_MEM (QImode,
4127 plus_constant (base,
4129 if (! BYTES_BIG_ENDIAN)
4130 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4131 gen_rtx_IOR (SImode,
4134 gen_rtx_SUBREG (SImode, operands[0], 0),
4138 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4139 gen_rtx_IOR (SImode,
4140 gen_rtx_ASHIFT (SImode, scratch,
4142 gen_rtx_SUBREG (SImode, operands[0],
4146 /* Handle storing a half-word to memory during reload by synthesising as two
4147 byte stores. Take care not to clobber the input values until after we
4148 have moved them somewhere safe. This code assumes that if the DImode
4149 scratch in operands[2] overlaps either the input value or output address
4150 in some way, then that value must die in this insn (we absolutely need
4151 two scratch registers for some corner cases). */
4153 arm_reload_out_hi (operands)
4156 rtx ref = operands[0];
4157 rtx outval = operands[1];
4159 HOST_WIDE_INT offset = 0;
4161 if (GET_CODE (ref) == SUBREG)
4163 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
4164 if (BYTES_BIG_ENDIAN)
4165 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
4166 - MIN (UNITS_PER_WORD,
4167 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
4168 ref = SUBREG_REG (ref);
4172 if (GET_CODE (ref) == REG)
4174 /* We have a pseudo which has been spilt onto the stack; there
4175 are two cases here: the first where there is a simple
4176 stack-slot replacement and a second where the stack-slot is
4177 out of range, or is used as a subreg. */
4178 if (reg_equiv_mem[REGNO (ref)])
4180 ref = reg_equiv_mem[REGNO (ref)];
4181 base = find_replacement (&XEXP (ref, 0));
4184 /* The slot is out of range, or was dressed up in a SUBREG */
4185 base = reg_equiv_address[REGNO (ref)];
4188 base = find_replacement (&XEXP (ref, 0));
4190 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4192 /* Handle the case where the address is too complex to be offset by 1. */
4193 if (GET_CODE (base) == MINUS
4194 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4196 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4198 /* Be careful not to destroy OUTVAL. */
4199 if (reg_overlap_mentioned_p (base_plus, outval))
4201 /* Updating base_plus might destroy outval, see if we can
4202 swap the scratch and base_plus. */
4203 if (! reg_overlap_mentioned_p (scratch, outval))
4206 scratch = base_plus;
4211 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4213 /* Be conservative and copy OUTVAL into the scratch now,
4214 this should only be necessary if outval is a subreg
4215 of something larger than a word. */
4216 /* XXX Might this clobber base? I can't see how it can,
4217 since scratch is known to overlap with OUTVAL, and
4218 must be wider than a word. */
4219 emit_insn (gen_movhi (scratch_hi, outval));
4220 outval = scratch_hi;
4224 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4227 else if (GET_CODE (base) == PLUS)
4229 /* The addend must be CONST_INT, or we would have dealt with it above */
4230 HOST_WIDE_INT hi, lo;
4232 offset += INTVAL (XEXP (base, 1));
4233 base = XEXP (base, 0);
4235 /* Rework the address into a legal sequence of insns */
4236 /* Valid range for lo is -4095 -> 4095 */
4239 : -((-offset) & 0xfff));
4241 /* Corner case, if lo is the max offset then we would be out of range
4242 once we have added the additional 1 below, so bump the msb into the
4243 pre-loading insn(s). */
4247 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
4248 ^ (HOST_WIDE_INT) 0x80000000UL)
4249 - (HOST_WIDE_INT) 0x80000000UL);
4251 if (hi + lo != offset)
4256 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4258 /* Be careful not to destroy OUTVAL. */
4259 if (reg_overlap_mentioned_p (base_plus, outval))
4261 /* Updating base_plus might destroy outval, see if we
4262 can swap the scratch and base_plus. */
4263 if (! reg_overlap_mentioned_p (scratch, outval))
4266 scratch = base_plus;
4271 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4273 /* Be conservative and copy outval into scratch now,
4274 this should only be necessary if outval is a
4275 subreg of something larger than a word. */
4276 /* XXX Might this clobber base? I can't see how it
4277 can, since scratch is known to overlap with
4279 emit_insn (gen_movhi (scratch_hi, outval));
4280 outval = scratch_hi;
4284 /* Get the base address; addsi3 knows how to handle constants
4285 that require more than one insn */
4286 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4292 if (BYTES_BIG_ENDIAN)
4294 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4295 plus_constant (base, offset + 1)),
4296 gen_rtx_SUBREG (QImode, outval, 0)));
4297 emit_insn (gen_lshrsi3 (scratch,
4298 gen_rtx_SUBREG (SImode, outval, 0),
4300 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4301 gen_rtx_SUBREG (QImode, scratch, 0)));
4305 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
4306 gen_rtx_SUBREG (QImode, outval, 0)));
4307 emit_insn (gen_lshrsi3 (scratch,
4308 gen_rtx_SUBREG (SImode, outval, 0),
4310 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
4311 plus_constant (base, offset + 1)),
4312 gen_rtx_SUBREG (QImode, scratch, 0)));
4316 /* Routines for manipulation of the constant pool. */
4318 /* Arm instructions cannot load a large constant directly into a
4319 register; they have to come from a pc relative load. The constant
4320 must therefore be placed in the addressable range of the pc
4321 relative load. Depending on the precise pc relative load
4322 instruction the range is somewhere between 256 bytes and 4k. This
4323 means that we often have to dump a constant inside a function, and
4324 generate code to branch around it.
4326 It is important to minimize this, since the branches will slow
4327 things down and make the code larger.
4329 Normally we can hide the table after an existing unconditional
4330 branch so that there is no interruption of the flow, but in the
4331 worst case the code looks like this:
4349 We fix this by performing a scan after scheduling, which notices
4350 which instructions need to have their operands fetched from the
4351 constant table and builds the table.
4353 The algorithm starts by building a table of all the constants that
4354 need fixing up and all the natural barriers in the function (places
4355 where a constant table can be dropped without breaking the flow).
4356 For each fixup we note how far the pc-relative replacement will be
4357 able to reach and the offset of the instruction into the function.
4359 Having built the table we then group the fixes together to form
4360 tables that are as large as possible (subject to addressing
4361 constraints) and emit each table of constants after the last
4362 barrier that is within range of all the instructions in the group.
4363 If a group does not contain a barrier, then we forcibly create one
4364 by inserting a jump instruction into the flow. Once the table has
4365 been inserted, the insns are then modified to reference the
4366 relevant entry in the pool.
4368 Possible enhancements to the alogorithm (not implemented) are:
4370 1) ARM instructions (but not thumb) can use negative offsets, so we
4371 could reference back to a previous pool rather than forwards to a
4372 new one. For large functions this may reduce the number of pools
4375 2) For some processors and object formats, there may be benefit in
4376 aligning the pools to the start of cache lines; this alignment
4377 would need to be taken into account when calculating addressability
4384 rtx value; /* Value in table */
4385 HOST_WIDE_INT next_offset;
4386 enum machine_mode mode; /* Mode of value */
4389 /* The maximum number of constants that can fit into one pool, since
4390 the pc relative range is 0...4092 bytes and constants are at least 4
4393 #define MAX_MINIPOOL_SIZE (4092/4)
4394 static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
4395 static int minipool_size;
4396 static rtx minipool_vector_label;
4398 /* Add a constant to the pool and return its offset within the current
4401 X is the rtx we want to replace. MODE is its mode. On return,
4402 ADDRESS_ONLY will be non-zero if we really want the address of such
4403 a constant, not the constant itself. */
4404 static HOST_WIDE_INT
4405 add_minipool_constant (x, mode)
4407 enum machine_mode mode;
4410 HOST_WIDE_INT offset;
4412 /* First, see if we've already got it. */
4413 for (i = 0; i < minipool_size; i++)
4415 if (GET_CODE (x) == minipool_vector[i].value->code
4416 && mode == minipool_vector[i].mode)
4418 if (GET_CODE (x) == CODE_LABEL)
4420 if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
4423 if (rtx_equal_p (x, minipool_vector[i].value))
4424 return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
4428 /* Need a new one */
4429 minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
4431 if (minipool_size == 0)
4432 minipool_vector_label = gen_label_rtx ();
4434 minipool_vector[minipool_size].next_offset
4435 += (offset = minipool_vector[minipool_size - 1].next_offset);
4437 minipool_vector[minipool_size].value = x;
4438 minipool_vector[minipool_size].mode = mode;
4443 /* Output the literal table */
4445 dump_minipool (scan)
4450 scan = emit_label_after (gen_label_rtx (), scan);
4451 scan = emit_insn_after (gen_align_4 (), scan);
4452 scan = emit_label_after (minipool_vector_label, scan);
4454 for (i = 0; i < minipool_size; i++)
4456 minipool_node *p = minipool_vector + i;
4458 switch (GET_MODE_SIZE (p->mode))
4461 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4465 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4474 scan = emit_insn_after (gen_consttable_end (), scan);
4475 scan = emit_barrier_after (scan);
4479 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4482 find_barrier (from, max_count)
4487 rtx found_barrier = 0;
4490 while (from && count < max_count)
4494 if (GET_CODE (from) == BARRIER)
4495 found_barrier = from;
4497 /* Count the length of this insn */
4498 if (GET_CODE (from) == JUMP_INSN
4499 && JUMP_LABEL (from) != 0
4500 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4501 == next_real_insn (from))
4503 && GET_CODE (tmp) == JUMP_INSN
4504 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4505 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4507 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4508 count += (get_attr_length (from)
4509 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4510 /* Continue after the dispatch table. */
4512 from = NEXT_INSN (tmp);
4516 count += get_attr_length (from);
4519 from = NEXT_INSN (from);
4522 if (! found_barrier)
4524 /* We didn't find a barrier in time to
4525 dump our stuff, so we'll make one. */
4526 rtx label = gen_label_rtx ();
4529 from = PREV_INSN (last);
4531 from = get_last_insn ();
4533 /* Walk back to be just before any jump. */
4534 while (GET_CODE (from) == JUMP_INSN
4535 || GET_CODE (from) == NOTE
4536 || GET_CODE (from) == CODE_LABEL)
4537 from = PREV_INSN (from);
4539 from = emit_jump_insn_after (gen_jump (label), from);
4540 JUMP_LABEL (from) = label;
4541 found_barrier = emit_barrier_after (from);
4542 emit_label_after (label, found_barrier);
4545 return found_barrier;
4548 struct minipool_fixup
4550 struct minipool_fixup *next;
4554 enum machine_mode mode;
4559 struct minipool_fixup *minipool_fix_head;
4560 struct minipool_fixup *minipool_fix_tail;
4563 push_minipool_barrier (insn, address)
4567 struct minipool_fixup *fix
4568 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4571 fix->address = address;
4574 if (minipool_fix_head != NULL)
4575 minipool_fix_tail->next = fix;
4577 minipool_fix_head = fix;
4579 minipool_fix_tail = fix;
4583 push_minipool_fix (insn, address, loc, mode, value)
4587 enum machine_mode mode;
4590 struct minipool_fixup *fix
4591 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4593 #ifdef AOF_ASSEMBLER
4594 /* PIC symbol refereneces need to be converted into offsets into the
4596 if (flag_pic && GET_MODE == SYMBOL_REF)
4597 value = aof_pic_entry (value);
4598 #endif /* AOF_ASSEMBLER */
4601 fix->address = address;
4605 fix->range = get_attr_pool_range (insn);
4607 /* If an insn doesn't have a range defined for it, then it isn't
4608 expecting to be reworked by this code. Better to abort now than
4609 to generate duff assembly code. */
4610 if (fix->range == 0)
4613 /* Add it to the chain of fixes */
4615 if (minipool_fix_head != NULL)
4616 minipool_fix_tail->next = fix;
4618 minipool_fix_head = fix;
4620 minipool_fix_tail = fix;
4624 note_invalid_constants (insn, address)
4630 /* Extract the operands of the insn */
4633 /* Find the alternative selected */
4634 if (! constrain_operands (1))
4635 fatal_insn_not_found (insn);
4637 /* Preprocess the constraints, to extract some useful information. */
4638 preprocess_constraints ();
4640 for (opno = 0; opno < recog_data.n_operands; opno++)
4642 /* Things we need to fix can only occur in inputs */
4643 if (recog_data.operand_type[opno] != OP_IN)
4646 /* If this alternative is a memory reference, then any mention
4647 of constants in this alternative is really to fool reload
4648 into allowing us to accept one there. We need to fix them up
4649 now so that we output the right code. */
4650 if (recog_op_alt[opno][which_alternative].memory_ok)
4652 rtx op = recog_data.operand[opno];
4654 if (CONSTANT_P (op))
4655 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4656 recog_data.operand_mode[opno], op);
4657 #ifndef AOF_ASSEMBLER
4658 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
4659 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4660 recog_data.operand_mode[opno],
4661 XVECEXP (op, 0, 0));
4663 else if (recog_data.operand_mode[opno] == SImode
4664 && GET_CODE (op) == MEM
4665 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
4666 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4667 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
4668 recog_data.operand_mode[opno],
4669 get_pool_constant (XEXP (op, 0)));
4680 struct minipool_fixup *fix;
4682 minipool_fix_head = minipool_fix_tail = NULL;
4684 /* The first insn must always be a note, or the code below won't
4685 scan it properly. */
4686 if (GET_CODE (first) != NOTE)
4689 /* Scan all the insns and record the operands that will need fixing. */
4690 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
4693 if (GET_CODE (insn) == BARRIER)
4694 push_minipool_barrier(insn, address);
4695 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
4696 || GET_CODE (insn) == JUMP_INSN)
4700 note_invalid_constants (insn, address);
4701 address += get_attr_length (insn);
4702 /* If the insn is a vector jump, add the size of the table
4703 and skip the table. */
4704 if (GET_CODE (insn) == JUMP_INSN
4705 && JUMP_LABEL (insn) != NULL
4706 && ((table = next_real_insn (JUMP_LABEL (insn)))
4707 == next_real_insn (insn))
4709 && GET_CODE (table) == JUMP_INSN
4710 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4711 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4713 int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
4715 address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
4722 /* Now scan the fixups and perform the required changes. */
4723 for (fix = minipool_fix_head; fix; fix = fix->next)
4725 struct minipool_fixup *ftmp;
4726 struct minipool_fixup *last_barrier = NULL;
4729 struct minipool_fixup *this_fix;
4730 int new_minipool_size = 0;
4732 /* Skip any further barriers before the next fix. */
4733 while (fix && GET_CODE (fix->insn) == BARRIER)
4740 max_range = fix->address + fix->range;
4742 /* Find all the other fixes that can live in the same pool. */
4743 while (ftmp->next && ftmp->next->address < max_range
4744 && (GET_CODE (ftmp->next->insn) == BARRIER
4745 /* Ensure we can reach the constant inside the pool. */
4746 || ftmp->next->range > new_minipool_size))
4749 if (GET_CODE (ftmp->insn) == BARRIER)
4750 last_barrier = ftmp;
4753 /* Does this fix constrain the range we can search? */
4754 if (ftmp->address + ftmp->range - new_minipool_size < max_range)
4755 max_range = ftmp->address + ftmp->range - new_minipool_size;
4757 new_minipool_size += GET_MODE_SIZE (ftmp->mode);
4761 /* If we found a barrier, drop back to that; any fixes that we could
4762 have reached but come after the barrier will now go in the next
4764 if (last_barrier != NULL)
4766 barrier = last_barrier->insn;
4767 ftmp = last_barrier;
4769 /* ftmp is last fix that we can fit into this pool and we
4770 failed to find a barrier that we could use. Insert a new
4771 barrier in the code and arrange to jump around it. */
4774 /* Check that there isn't another fix that is in range that
4775 we couldn't fit into this pool because the pool was
4776 already too large: we need to put the pool before such an
4778 if (ftmp->next && ftmp->next->address < max_range)
4779 max_range = ftmp->address;
4781 barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
4784 /* Scan over the fixes we have identified for this pool, fixing them
4785 up and adding the constants to the pool itself. */
4786 for (this_fix = fix; this_fix && ftmp->next != this_fix;
4787 this_fix = this_fix->next)
4788 if (GET_CODE (this_fix->insn) != BARRIER)
4790 int offset = add_minipool_constant (this_fix->value,
4793 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4794 minipool_vector_label),
4796 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
4799 dump_minipool (barrier);
4803 /* From now on we must synthesize any constants that we can't handle
4804 directly. This can happen if the RTL gets split during final
4805 instruction generation. */
4806 after_arm_reorg = 1;
4810 /* Routines to output assembly language. */
4812 /* If the rtx is the correct value then return the string of the number.
4813 In this way we can ensure that valid double constants are generated even
4814 when cross compiling. */
4816 fp_immediate_constant (x)
4822 if (!fpa_consts_inited)
4825 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4826 for (i = 0; i < 8; i++)
4827 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4828 return strings_fpa[i];
4833 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4835 fp_const_from_val (r)
4836 REAL_VALUE_TYPE * r;
4840 if (! fpa_consts_inited)
4843 for (i = 0; i < 8; i++)
4844 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4845 return strings_fpa[i];
4850 /* Output the operands of a LDM/STM instruction to STREAM.
4851 MASK is the ARM register set mask of which only bits 0-15 are important.
4852 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4853 must follow the register list. */
4856 print_multi_reg (stream, instr, reg, mask, hat)
4864 int not_first = FALSE;
4866 fputc ('\t', stream);
4867 asm_fprintf (stream, instr, reg);
4868 fputs (", {", stream);
4870 for (i = 0; i < 16; i++)
4871 if (mask & (1 << i))
4874 fprintf (stream, ", ");
4876 asm_fprintf (stream, "%r", i);
4880 fprintf (stream, "}%s\n", hat ? "^" : "");
4883 /* Output a 'call' insn. */
4886 output_call (operands)
4889 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4891 if (REGNO (operands[0]) == LR_REGNUM)
4893 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
4894 output_asm_insn ("mov%?\t%0, %|lr", operands);
4897 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4899 if (TARGET_INTERWORK)
4900 output_asm_insn ("bx%?\t%0", operands);
4902 output_asm_insn ("mov%?\t%|pc, %0", operands);
4911 int something_changed = 0;
4913 int code = GET_CODE (x0);
4915 register const char * fmt;
4920 if (REGNO (x0) == LR_REGNUM)
4922 *x = gen_rtx_REG (SImode, IP_REGNUM);
4927 /* Scan through the sub-elements and change any references there */
4928 fmt = GET_RTX_FORMAT (code);
4930 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4932 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4933 else if (fmt[i] == 'E')
4934 for (j = 0; j < XVECLEN (x0, i); j++)
4935 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4937 return something_changed;
4941 /* Output a 'call' insn that is a reference in memory. */
4944 output_call_mem (operands)
4947 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4948 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4950 if (eliminate_lr2ip (&operands[0]))
4951 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4953 if (TARGET_INTERWORK)
4955 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4956 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4957 output_asm_insn ("bx%?\t%|ip", operands);
4961 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4962 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4969 /* Output a move from arm registers to an fpu registers.
4970 OPERANDS[0] is an fpu register.
4971 OPERANDS[1] is the first registers of an arm register pair. */
4974 output_mov_long_double_fpu_from_arm (operands)
4977 int arm_reg0 = REGNO (operands[1]);
4980 if (arm_reg0 == IP_REGNUM)
4983 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4984 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4985 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4987 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4988 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4993 /* Output a move from an fpu register to arm registers.
4994 OPERANDS[0] is the first registers of an arm register pair.
4995 OPERANDS[1] is an fpu register. */
4998 output_mov_long_double_arm_from_fpu (operands)
5001 int arm_reg0 = REGNO (operands[0]);
5004 if (arm_reg0 == IP_REGNUM)
5007 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5008 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5009 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
5011 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
5012 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
5016 /* Output a move from arm registers to arm registers of a long double
5017 OPERANDS[0] is the destination.
5018 OPERANDS[1] is the source. */
5020 output_mov_long_double_arm_from_arm (operands)
5023 /* We have to be careful here because the two might overlap */
5024 int dest_start = REGNO (operands[0]);
5025 int src_start = REGNO (operands[1]);
5029 if (dest_start < src_start)
5031 for (i = 0; i < 3; i++)
5033 ops[0] = gen_rtx_REG (SImode, dest_start + i);
5034 ops[1] = gen_rtx_REG (SImode, src_start + i);
5035 output_asm_insn ("mov%?\t%0, %1", ops);
5040 for (i = 2; i >= 0; i--)
5042 ops[0] = gen_rtx_REG (SImode, dest_start + i);
5043 ops[1] = gen_rtx_REG (SImode, src_start + i);
5044 output_asm_insn ("mov%?\t%0, %1", ops);
5052 /* Output a move from arm registers to an fpu registers.
5053 OPERANDS[0] is an fpu register.
5054 OPERANDS[1] is the first registers of an arm register pair. */
5057 output_mov_double_fpu_from_arm (operands)
5060 int arm_reg0 = REGNO (operands[1]);
5063 if (arm_reg0 == IP_REGNUM)
5066 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5067 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5068 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
5069 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
5073 /* Output a move from an fpu register to arm registers.
5074 OPERANDS[0] is the first registers of an arm register pair.
5075 OPERANDS[1] is an fpu register. */
5078 output_mov_double_arm_from_fpu (operands)
5081 int arm_reg0 = REGNO (operands[0]);
5084 if (arm_reg0 == IP_REGNUM)
5087 ops[0] = gen_rtx_REG (SImode, arm_reg0);
5088 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5089 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
5090 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
5094 /* Output a move between double words.
5095 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
5096 or MEM<-REG and all MEMs must be offsettable addresses. */
5099 output_move_double (operands)
5102 enum rtx_code code0 = GET_CODE (operands[0]);
5103 enum rtx_code code1 = GET_CODE (operands[1]);
5108 int reg0 = REGNO (operands[0]);
5110 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
5114 int reg1 = REGNO (operands[1]);
5115 if (reg1 == IP_REGNUM)
5118 /* Ensure the second source is not overwritten */
5119 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
5120 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
5122 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
5124 else if (code1 == CONST_DOUBLE)
5126 if (GET_MODE (operands[1]) == DFmode)
5129 union real_extract u;
5131 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
5133 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
5134 otherops[1] = GEN_INT(l[1]);
5135 operands[1] = GEN_INT(l[0]);
5137 else if (GET_MODE (operands[1]) != VOIDmode)
5139 else if (WORDS_BIG_ENDIAN)
5142 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5143 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5148 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5149 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5152 output_mov_immediate (operands);
5153 output_mov_immediate (otherops);
5155 else if (code1 == CONST_INT)
5157 #if HOST_BITS_PER_WIDE_INT > 32
5158 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5159 what the upper word is. */
5160 if (WORDS_BIG_ENDIAN)
5162 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5163 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5167 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
5168 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
5171 /* Sign extend the intval into the high-order word */
5172 if (WORDS_BIG_ENDIAN)
5174 otherops[1] = operands[1];
5175 operands[1] = (INTVAL (operands[1]) < 0
5176 ? constm1_rtx : const0_rtx);
5179 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
5181 output_mov_immediate (otherops);
5182 output_mov_immediate (operands);
5184 else if (code1 == MEM)
5186 switch (GET_CODE (XEXP (operands[1], 0)))
5189 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
5193 abort (); /* Should never happen now */
5197 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
5201 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
5205 abort (); /* Should never happen now */
5210 output_asm_insn ("adr%?\t%0, %1", operands);
5211 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
5215 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
5216 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
5218 otherops[0] = operands[0];
5219 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
5220 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
5221 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
5223 if (GET_CODE (otherops[2]) == CONST_INT)
5225 switch (INTVAL (otherops[2]))
5228 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
5231 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
5234 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
5237 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
5238 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
5240 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5243 output_asm_insn ("add%?\t%0, %1, %2", otherops);
5246 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
5248 return "ldm%?ia\t%0, %M0";
5252 otherops[1] = adj_offsettable_operand (operands[1], 4);
5253 /* Take care of overlapping base/data reg. */
5254 if (reg_mentioned_p (operands[0], operands[1]))
5256 output_asm_insn ("ldr%?\t%0, %1", otherops);
5257 output_asm_insn ("ldr%?\t%0, %1", operands);
5261 output_asm_insn ("ldr%?\t%0, %1", operands);
5262 output_asm_insn ("ldr%?\t%0, %1", otherops);
5268 abort (); /* Constraints should prevent this */
5270 else if (code0 == MEM && code1 == REG)
5272 if (REGNO (operands[1]) == IP_REGNUM)
5275 switch (GET_CODE (XEXP (operands[0], 0)))
5278 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
5282 abort (); /* Should never happen now */
5286 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
5290 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
5294 abort (); /* Should never happen now */
5298 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
5300 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
5303 output_asm_insn ("stm%?db\t%m0, %M1", operands);
5307 output_asm_insn ("stm%?da\t%m0, %M1", operands);
5311 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
5318 otherops[0] = adj_offsettable_operand (operands[0], 4);
5319 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
5320 output_asm_insn ("str%?\t%1, %0", operands);
5321 output_asm_insn ("str%?\t%1, %0", otherops);
5325 abort (); /* Constraints should prevent this */
5331 /* Output an arbitrary MOV reg, #n.
5332 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
5335 output_mov_immediate (operands)
5338 HOST_WIDE_INT n = INTVAL (operands[1]);
5342 /* Try to use one MOV */
5343 if (const_ok_for_arm (n))
5345 output_asm_insn ("mov%?\t%0, %1", operands);
5349 /* Try to use one MVN */
5350 if (const_ok_for_arm (~n))
5352 operands[1] = GEN_INT (~n);
5353 output_asm_insn ("mvn%?\t%0, %1", operands);
5357 /* If all else fails, make it out of ORRs or BICs as appropriate. */
5359 for (i=0; i < 32; i++)
5363 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
5364 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
5367 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
5374 /* Output an ADD r, s, #n where n may be too big for one instruction. If
5375 adding zero to one register, output nothing. */
5378 output_add_immediate (operands)
5381 HOST_WIDE_INT n = INTVAL (operands[2]);
5383 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
5386 output_multi_immediate (operands,
5387 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
5390 output_multi_immediate (operands,
5391 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
5398 /* Output a multiple immediate operation.
5399 OPERANDS is the vector of operands referred to in the output patterns.
5400 INSTR1 is the output pattern to use for the first constant.
5401 INSTR2 is the output pattern to use for subsequent constants.
5402 IMMED_OP is the index of the constant slot in OPERANDS.
5403 N is the constant value. */
5406 output_multi_immediate (operands, instr1, instr2, immed_op, n)
5408 char * instr1, * instr2;
5412 #if HOST_BITS_PER_WIDE_INT > 32
5418 operands[immed_op] = const0_rtx;
5419 output_asm_insn (instr1, operands); /* Quick and easy output */
5424 char *instr = instr1;
5426 /* Note that n is never zero here (which would give no output) */
5427 for (i = 0; i < 32; i += 2)
5431 operands[immed_op] = GEN_INT (n & (255 << i));
5432 output_asm_insn (instr, operands);
5442 /* Return the appropriate ARM instruction for the operation code.
5443 The returned result should not be overwritten. OP is the rtx of the
5444 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5448 arithmetic_instr (op, shift_first_arg)
5450 int shift_first_arg;
5452 switch (GET_CODE (op))
5458 return shift_first_arg ? "rsb" : "sub";
5475 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5476 for the operation code. The returned result should not be overwritten.
5477 OP is the rtx code of the shift.
5478 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5482 shift_op (op, amountp)
5484 HOST_WIDE_INT *amountp;
5487 enum rtx_code code = GET_CODE (op);
5489 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5491 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5492 *amountp = INTVAL (XEXP (op, 1));
5515 /* We never have to worry about the amount being other than a
5516 power of 2, since this case can never be reloaded from a reg. */
5518 *amountp = int_log2 (*amountp);
5529 /* This is not 100% correct, but follows from the desire to merge
5530 multiplication by a power of 2 with the recognizer for a
5531 shift. >=32 is not a valid shift for "asl", so we must try and
5532 output a shift that produces the correct arithmetical result.
5533 Using lsr #32 is identical except for the fact that the carry bit
5534 is not set correctly if we set the flags; but we never use the
5535 carry bit from such an operation, so we can ignore that. */
5536 if (code == ROTATERT)
5537 *amountp &= 31; /* Rotate is just modulo 32 */
5538 else if (*amountp != (*amountp & 31))
5545 /* Shifts of 0 are no-ops. */
5554 /* Obtain the shift from the POWER of two. */
5556 static HOST_WIDE_INT
5558 HOST_WIDE_INT power;
5560 HOST_WIDE_INT shift = 0;
5562 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5572 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5573 /bin/as is horribly restrictive. */
5574 #define MAX_ASCII_LEN 51
5577 output_ascii_pseudo_op (stream, p, len)
5579 const unsigned char * p;
5585 fputs ("\t.ascii\t\"", stream);
5587 for (i = 0; i < len; i++)
5589 register int c = p[i];
5591 if (len_so_far >= MAX_ASCII_LEN)
5593 fputs ("\"\n\t.ascii\t\"", stream);
5600 fputs ("\\t", stream);
5605 fputs ("\\f", stream);
5610 fputs ("\\b", stream);
5615 fputs ("\\r", stream);
5619 case TARGET_NEWLINE:
5620 fputs ("\\n", stream);
5622 if ((c >= ' ' && c <= '~')
5624 /* This is a good place for a line break. */
5625 len_so_far = MAX_ASCII_LEN;
5632 putc ('\\', stream);
5637 if (c >= ' ' && c <= '~')
5644 fprintf (stream, "\\%03o", c);
5651 fputs ("\"\n", stream);
5655 /* Try to determine whether a pattern really clobbers the link register.
5656 This information is useful when peepholing, so that lr need not be pushed
5657 if we combine a call followed by a return.
5658 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5659 such a check should not be needed because these only update an existing
5660 value within a register; the register must still be set elsewhere within
5664 pattern_really_clobbers_lr (x)
5669 switch (GET_CODE (x))
5672 switch (GET_CODE (SET_DEST (x)))
5675 return REGNO (SET_DEST (x)) == LR_REGNUM;
5678 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5679 return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
5681 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5690 for (i = 0; i < XVECLEN (x, 0); i++)
5691 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5696 switch (GET_CODE (XEXP (x, 0)))
5699 return REGNO (XEXP (x, 0)) == LR_REGNUM;
5702 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5703 return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
5719 function_really_clobbers_lr (first)
5724 for (insn = first; insn; insn = next_nonnote_insn (insn))
5726 switch (GET_CODE (insn))
5731 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5735 if (pattern_really_clobbers_lr (PATTERN (insn)))
5740 /* Don't yet know how to handle those calls that are not to a
5742 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5745 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5748 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5754 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5760 default: /* Don't recognize it, be safe */
5764 /* A call can be made (by peepholing) not to clobber lr iff it is
5765 followed by a return. There may, however, be a use insn iff
5766 we are returning the result of the call.
5767 If we run off the end of the insn chain, then that means the
5768 call was at the end of the function. Unfortunately we don't
5769 have a return insn for the peephole to recognize, so we
5770 must reject this. (Can this be fixed by adding our own insn?) */
5771 if ((next = next_nonnote_insn (insn)) == NULL)
5774 /* No need to worry about lr if the call never returns */
5775 if (GET_CODE (next) == BARRIER)
5778 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5779 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5780 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5781 == REGNO (XEXP (PATTERN (next), 0))))
5782 if ((next = next_nonnote_insn (next)) == NULL)
5785 if (GET_CODE (next) == JUMP_INSN
5786 && GET_CODE (PATTERN (next)) == RETURN)
5795 /* We have reached the end of the chain so lr was _not_ clobbered */
5800 output_return_instruction (operand, really_return, reverse)
5806 int reg, live_regs = 0;
5807 int volatile_func = (optimize > 0
5808 && TREE_THIS_VOLATILE (current_function_decl));
5810 return_used_this_function = 1;
5812 if (TARGET_ABORT_NORETURN && volatile_func)
5814 /* If this function was declared non-returning, and we have found a tail
5815 call, then we have to trust that the called function won't return. */
5820 /* Otherwise, trap an attempted return by aborting. */
5822 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
5824 assemble_external_libcall (ops[1]);
5825 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5831 if (current_function_calls_alloca && ! really_return)
5834 for (reg = 0; reg <= 10; reg++)
5835 if (regs_ever_live[reg] && ! call_used_regs[reg])
5838 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5839 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5842 if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
5845 if (frame_pointer_needed)
5848 /* On some ARM architectures it is faster to use LDR rather than LDM to
5849 load a single register. On other architectures, the cost is the same. */
5851 && regs_ever_live[LR_REGNUM]
5852 && ! lr_save_eliminated
5853 /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
5854 really_return is true, and only the PC needs restoring. */
5857 output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
5858 : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
5862 if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
5865 if (frame_pointer_needed)
5867 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5870 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5872 for (reg = 0; reg <= 10; reg++)
5873 if (regs_ever_live[reg]
5874 && (! call_used_regs[reg]
5875 || (flag_pic && ! TARGET_SINGLE_PIC_BASE
5876 && reg == PIC_OFFSET_TABLE_REGNUM)))
5878 strcat (instr, "%|");
5879 strcat (instr, reg_names[reg]);
5881 strcat (instr, ", ");
5884 if (frame_pointer_needed)
5886 strcat (instr, "%|");
5887 strcat (instr, reg_names[11]);
5888 strcat (instr, ", ");
5889 strcat (instr, "%|");
5890 strcat (instr, reg_names[13]);
5891 strcat (instr, ", ");
5892 strcat (instr, "%|");
5893 strcat (instr, TARGET_INTERWORK || (! really_return)
5894 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
5898 strcat (instr, "%|");
5899 if (TARGET_INTERWORK && really_return)
5900 strcat (instr, reg_names[IP_REGNUM]);
5902 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
5904 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5905 output_asm_insn (instr, &operand);
5907 if (TARGET_INTERWORK && really_return)
5909 strcpy (instr, "bx%?");
5910 strcat (instr, reverse ? "%D0" : "%d0");
5911 strcat (instr, "\t%|");
5912 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5914 output_asm_insn (instr, & operand);
5917 else if (really_return)
5919 if (TARGET_INTERWORK)
5920 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5922 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5923 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5925 output_asm_insn (instr, & operand);
5931 /* Return nonzero if optimizing and the current function is volatile.
5932 Such functions never return, and many memory cycles can be saved
5933 by not storing register values that will never be needed again.
5934 This optimization was added to speed up context switching in a
5935 kernel application. */
5938 arm_volatile_func ()
5940 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5943 /* Write the function name into the code section, directly preceding
5944 the function prologue.
5946 Code will be output similar to this:
5948 .ascii "arm_poke_function_name", 0
5951 .word 0xff000000 + (t1 - t0)
5952 arm_poke_function_name
5954 stmfd sp!, {fp, ip, lr, pc}
5957 When performing a stack backtrace, code can inspect the value
5958 of 'pc' stored at 'fp' + 0. If the trace function then looks
5959 at location pc - 12 and the top 8 bits are set, then we know
5960 that there is a function name embedded immediately preceding this
5961 location and has length ((pc[-3]) & 0xff000000).
5963 We assume that pc is declared as a pointer to an unsigned long.
5965 It is of no benefit to output the function name if we are assembling
5966 a leaf function. These function types will not contain a stack
5967 backtrace structure, therefore it is not possible to determine the
5971 arm_poke_function_name (stream, name)
5975 unsigned long alignlength;
5976 unsigned long length;
5979 length = strlen (name) + 1;
5980 alignlength = (length + 3) & ~3;
5982 ASM_OUTPUT_ASCII (stream, name, length);
5983 ASM_OUTPUT_ALIGN (stream, 2);
5984 x = GEN_INT (0xff000000UL + alignlength);
5985 ASM_OUTPUT_INT (stream, x);
5988 /* The amount of stack adjustment that happens here, in output_return and in
5989 output_epilogue must be exactly the same as was calculated during reload,
5990 or things will point to the wrong place. The only time we can safely
5991 ignore this constraint is when a function has no arguments on the stack,
5992 no stack frame requirement and no live registers execpt for `lr'. If we
5993 can guarantee that by making all function calls into tail calls and that
5994 lr is not clobbered in any other way, then there is no need to push lr
5998 output_func_prologue (f, frame_size)
6002 int reg, live_regs_mask = 0;
6003 int volatile_func = (optimize > 0
6004 && TREE_THIS_VOLATILE (current_function_decl));
6006 /* Nonzero if we must stuff some register arguments onto the stack as if
6007 they were passed there. */
6008 int store_arg_regs = 0;
6010 if (arm_ccfsm_state || arm_target_insn)
6011 abort (); /* Sanity check */
6013 if (arm_naked_function_p (current_function_decl))
6016 return_used_this_function = 0;
6017 lr_save_eliminated = 0;
6019 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
6020 current_function_args_size,
6021 current_function_pretend_args_size, frame_size);
6022 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
6023 frame_pointer_needed,
6024 current_function_anonymous_args);
6027 asm_fprintf (f, "\t%@ Volatile function.\n");
6029 if (current_function_anonymous_args && current_function_pretend_args_size)
6032 for (reg = 0; reg <= 10; reg++)
6033 if (regs_ever_live[reg] && ! call_used_regs[reg])
6034 live_regs_mask |= (1 << reg);
6036 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
6037 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6038 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6040 if (frame_pointer_needed)
6041 live_regs_mask |= 0xD800;
6042 else if (regs_ever_live[LR_REGNUM])
6044 if (! current_function_args_size
6045 && ! function_really_clobbers_lr (get_insns ()))
6046 lr_save_eliminated = 1;
6048 live_regs_mask |= 1 << LR_REGNUM;
6053 /* if a di mode load/store multiple is used, and the base register
6054 is r3, then r4 can become an ever live register without lr
6055 doing so, in this case we need to push lr as well, or we
6056 will fail to get a proper return. */
6058 live_regs_mask |= 1 << LR_REGNUM;
6059 lr_save_eliminated = 0;
6063 if (lr_save_eliminated)
6064 asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
6066 #ifdef AOF_ASSEMBLER
6068 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
6073 arm_output_epilogue ()
6076 int live_regs_mask = 0;
6077 /* If we need this, then it will always be at least this much */
6078 int floats_offset = 12;
6080 int frame_size = get_frame_size ();
6081 FILE *f = asm_out_file;
6082 int volatile_func = (optimize > 0
6083 && TREE_THIS_VOLATILE (current_function_decl));
6085 if (use_return_insn (FALSE) && return_used_this_function)
6088 /* Naked functions don't have epilogues. */
6089 if (arm_naked_function_p (current_function_decl))
6092 /* A volatile function should never return. Call abort. */
6093 if (TARGET_ABORT_NORETURN && volatile_func)
6096 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
6097 assemble_external_libcall (op);
6098 output_asm_insn ("bl\t%a0", &op);
6102 for (reg = 0; reg <= 10; reg++)
6103 if (regs_ever_live[reg] && ! call_used_regs[reg])
6105 live_regs_mask |= (1 << reg);
6109 /* If we aren't loading the PIC register, don't stack it even though it may
6111 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
6112 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6114 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
6118 if (frame_pointer_needed)
6120 if (arm_fpu_arch == FP_SOFT2)
6122 for (reg = 23; reg > 15; reg--)
6123 if (regs_ever_live[reg] && ! call_used_regs[reg])
6125 floats_offset += 12;
6126 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
6127 reg, FP_REGNUM, floats_offset);
6134 for (reg = 23; reg > 15; reg--)
6136 if (regs_ever_live[reg] && ! call_used_regs[reg])
6138 floats_offset += 12;
6140 /* We can't unstack more than four registers at once */
6141 if (start_reg - reg == 3)
6143 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
6144 reg, FP_REGNUM, floats_offset);
6145 start_reg = reg - 1;
6150 if (reg != start_reg)
6151 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6152 reg + 1, start_reg - reg,
6153 FP_REGNUM, floats_offset);
6154 start_reg = reg - 1;
6158 /* Just in case the last register checked also needs unstacking. */
6159 if (reg != start_reg)
6160 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
6161 reg + 1, start_reg - reg,
6162 FP_REGNUM, floats_offset);
6165 if (TARGET_INTERWORK)
6167 live_regs_mask |= 0x6800;
6168 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
6169 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6173 live_regs_mask |= 0xA800;
6174 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
6175 TARGET_APCS_32 ? FALSE : TRUE);
6180 /* Restore stack pointer if necessary. */
6181 if (frame_size + current_function_outgoing_args_size != 0)
6183 operands[0] = operands[1] = stack_pointer_rtx;
6184 operands[2] = GEN_INT (frame_size
6185 + current_function_outgoing_args_size);
6186 output_add_immediate (operands);
6189 if (arm_fpu_arch == FP_SOFT2)
6191 for (reg = 16; reg < 24; reg++)
6192 if (regs_ever_live[reg] && ! call_used_regs[reg])
6193 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
6200 for (reg = 16; reg < 24; reg++)
6202 if (regs_ever_live[reg] && ! call_used_regs[reg])
6204 if (reg - start_reg == 3)
6206 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
6207 start_reg, SP_REGNUM);
6208 start_reg = reg + 1;
6213 if (reg != start_reg)
6214 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6215 start_reg, reg - start_reg,
6218 start_reg = reg + 1;
6222 /* Just in case the last register checked also needs unstacking. */
6223 if (reg != start_reg)
6224 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
6225 start_reg, reg - start_reg, SP_REGNUM);
6228 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
6230 if (TARGET_INTERWORK)
6232 if (! lr_save_eliminated)
6233 live_regs_mask |= 1 << LR_REGNUM;
6235 if (live_regs_mask != 0)
6236 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6238 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6240 else if (lr_save_eliminated)
6242 TARGET_APCS_32 ? "\tmov\t%r, %r\n" : "\tmovs\t%r, %r\n",
6243 PC_REGNUM, LR_REGNUM);
6245 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
6246 TARGET_APCS_32 ? FALSE : TRUE);
6250 if (live_regs_mask || regs_ever_live[LR_REGNUM])
6252 /* Restore the integer regs, and the return address into lr */
6253 if (! lr_save_eliminated)
6254 live_regs_mask |= 1 << LR_REGNUM;
6256 if (live_regs_mask != 0)
6257 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
6260 if (current_function_pretend_args_size)
6262 /* Unwind the pre-pushed regs */
6263 operands[0] = operands[1] = stack_pointer_rtx;
6264 operands[2] = GEN_INT (current_function_pretend_args_size);
6265 output_add_immediate (operands);
6267 /* And finally, go home */
6268 if (TARGET_INTERWORK)
6269 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
6270 else if (TARGET_APCS_32)
6271 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6273 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6281 output_func_epilogue (frame_size)
6284 if (use_return_insn (FALSE) && return_used_this_function
6285 && (frame_size + current_function_outgoing_args_size) != 0
6286 && ! (frame_pointer_needed && TARGET_APCS))
6289 /* Reset the ARM-specific per-function variables. */
6290 current_function_anonymous_args = 0;
6291 after_arm_reorg = 0;
6295 emit_multi_reg_push (mask)
6302 for (i = 0; i < 16; i++)
6303 if (mask & (1 << i))
6306 if (num_regs == 0 || num_regs > 16)
6309 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
6311 for (i = 0; i < 16; i++)
6313 if (mask & (1 << i))
6316 = gen_rtx_SET (VOIDmode,
6317 gen_rtx_MEM (BLKmode,
6318 gen_rtx_PRE_DEC (BLKmode,
6319 stack_pointer_rtx)),
6320 gen_rtx_UNSPEC (BLKmode,
6322 gen_rtx_REG (SImode, i)),
6328 for (j = 1, i++; j < num_regs; i++)
6330 if (mask & (1 << i))
6333 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
6342 emit_sfm (base_reg, count)
6349 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
6352 = gen_rtx_SET (VOIDmode,
6353 gen_rtx_MEM (BLKmode,
6354 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
6355 gen_rtx_UNSPEC (BLKmode,
6356 gen_rtvec (1, gen_rtx_REG (XFmode,
6359 for (i = 1; i < count; i++)
6360 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
6361 gen_rtx_REG (XFmode, base_reg++));
6367 arm_expand_prologue ()
6370 rtx amount = GEN_INT (-(get_frame_size ()
6371 + current_function_outgoing_args_size));
6372 int live_regs_mask = 0;
6373 int store_arg_regs = 0;
6374 /* If this function doesn't return, then there is no need to push
6375 the call-saved regs. */
6376 int volatile_func = (optimize > 0
6377 && TREE_THIS_VOLATILE (current_function_decl));
6379 /* Naked functions don't have prologues. */
6380 if (arm_naked_function_p (current_function_decl))
6383 if (current_function_anonymous_args && current_function_pretend_args_size)
6386 if (! volatile_func)
6388 for (reg = 0; reg <= 10; reg++)
6389 if (regs_ever_live[reg] && ! call_used_regs[reg])
6390 live_regs_mask |= 1 << reg;
6392 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6393 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6395 if (regs_ever_live[LR_REGNUM])
6396 live_regs_mask |= 1 << LR_REGNUM;
6399 if (frame_pointer_needed)
6401 live_regs_mask |= 0xD800;
6402 emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
6403 stack_pointer_rtx));
6406 if (current_function_pretend_args_size)
6409 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
6412 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6413 GEN_INT (-current_function_pretend_args_size)));
6418 /* If we have to push any regs, then we must push lr as well, or
6419 we won't get a proper return. */
6420 live_regs_mask |= 1 << LR_REGNUM;
6421 emit_multi_reg_push (live_regs_mask);
6424 /* For now the integer regs are still pushed in output_func_epilogue (). */
6426 if (! volatile_func)
6428 if (arm_fpu_arch == FP_SOFT2)
6430 for (reg = 23; reg > 15; reg--)
6431 if (regs_ever_live[reg] && ! call_used_regs[reg])
6432 emit_insn (gen_rtx_SET
6434 gen_rtx_MEM (XFmode,
6435 gen_rtx_PRE_DEC (XFmode,
6436 stack_pointer_rtx)),
6437 gen_rtx_REG (XFmode, reg)));
6443 for (reg = 23; reg > 15; reg--)
6445 if (regs_ever_live[reg] && ! call_used_regs[reg])
6447 if (start_reg - reg == 3)
6450 start_reg = reg - 1;
6455 if (start_reg != reg)
6456 emit_sfm (reg + 1, start_reg - reg);
6457 start_reg = reg - 1;
6461 if (start_reg != reg)
6462 emit_sfm (reg + 1, start_reg - reg);
6466 if (frame_pointer_needed)
6467 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, IP_REGNUM),
6469 (-(4 + current_function_pretend_args_size)))));
6471 if (amount != const0_rtx)
6473 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
6474 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6475 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
6478 /* If we are profiling, make sure no instructions are scheduled before
6479 the call to mcount. Similarly if the user has requested no
6480 scheduling in the prolog. */
6481 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
6482 emit_insn (gen_blockage ());
6486 /* If CODE is 'd', then the X is a condition operand and the instruction
6487 should only be executed if the condition is true.
6488 if CODE is 'D', then the X is a condition operand and the instruction
6489 should only be executed if the condition is false: however, if the mode
6490 of the comparison is CCFPEmode, then always execute the instruction -- we
6491 do this because in these circumstances !GE does not necessarily imply LT;
6492 in these cases the instruction pattern will take care to make sure that
6493 an instruction containing %d will follow, thereby undoing the effects of
6494 doing this instruction unconditionally.
6495 If CODE is 'N' then X is a floating point operand that must be negated
6497 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6498 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6501 arm_print_operand (stream, x, code)
6509 fputs (ASM_COMMENT_START, stream);
6513 fputs (REGISTER_PREFIX, stream);
6517 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
6518 fputs (arm_condition_codes[arm_current_cc], stream);
6524 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6525 r = REAL_VALUE_NEGATE (r);
6526 fprintf (stream, "%s", fp_const_from_val (&r));
6531 if (GET_CODE (x) == CONST_INT)
6534 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6535 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6540 output_addr_const (stream, x);
6545 fprintf (stream, "%s", arithmetic_instr (x, 1));
6549 fprintf (stream, "%s", arithmetic_instr (x, 0));
6555 char * shift = shift_op (x, & val);
6559 fprintf (stream, ", %s ", shift_op (x, & val));
6561 arm_print_operand (stream, XEXP (x, 1), 0);
6564 fputc ('#', stream);
6565 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6574 fputs (REGISTER_PREFIX, stream);
6575 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6581 fputs (REGISTER_PREFIX, stream);
6582 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6586 fputs (REGISTER_PREFIX, stream);
6587 if (GET_CODE (XEXP (x, 0)) == REG)
6588 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6590 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6594 asm_fprintf (stream, "{%r-%r}",
6595 REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
6600 fputs (arm_condition_codes[get_arm_condition_code (x)],
6606 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6607 (get_arm_condition_code (x))],
6615 if (GET_CODE (x) == REG)
6617 fputs (REGISTER_PREFIX, stream);
6618 fputs (reg_names[REGNO (x)], stream);
6620 else if (GET_CODE (x) == MEM)
6622 output_memory_reference_mode = GET_MODE (x);
6623 output_address (XEXP (x, 0));
6625 else if (GET_CODE (x) == CONST_DOUBLE)
6626 fprintf (stream, "#%s", fp_immediate_constant (x));
6627 else if (GET_CODE (x) == NEG)
6628 abort (); /* This should never happen now. */
6631 fputc ('#', stream);
6632 output_addr_const (stream, x);
6637 /* A finite state machine takes care of noticing whether or not instructions
6638 can be conditionally executed, and thus decrease execution time and code
6639 size by deleting branch instructions. The fsm is controlled by
6640 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6642 /* The state of the fsm controlling condition codes are:
6643 0: normal, do nothing special
6644 1: make ASM_OUTPUT_OPCODE not output this instruction
6645 2: make ASM_OUTPUT_OPCODE not output this instruction
6646 3: make instructions conditional
6647 4: make instructions conditional
6649 State transitions (state->state by whom under condition):
6650 0 -> 1 final_prescan_insn if the `target' is a label
6651 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6652 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6653 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6654 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6655 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6656 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6657 (the target insn is arm_target_insn).
6659 If the jump clobbers the conditions then we use states 2 and 4.
6661 A similar thing can be done with conditional return insns.
6663 XXX In case the `target' is an unconditional branch, this conditionalising
6664 of the instructions always reduces code size, but not always execution
6665 time. But then, I want to reduce the code size to somewhere near what
6666 /bin/cc produces. */
6668 /* Returns the index of the ARM condition code string in
6669 `arm_condition_codes'. COMPARISON should be an rtx like
6670 `(eq (...) (...))'. */
6672 static enum arm_cond_code
6673 get_arm_condition_code (comparison)
6676 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6678 register enum rtx_code comp_code = GET_CODE (comparison);
6680 if (GET_MODE_CLASS (mode) != MODE_CC)
6681 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6682 XEXP (comparison, 1));
6686 case CC_DNEmode: code = ARM_NE; goto dominance;
6687 case CC_DEQmode: code = ARM_EQ; goto dominance;
6688 case CC_DGEmode: code = ARM_GE; goto dominance;
6689 case CC_DGTmode: code = ARM_GT; goto dominance;
6690 case CC_DLEmode: code = ARM_LE; goto dominance;
6691 case CC_DLTmode: code = ARM_LT; goto dominance;
6692 case CC_DGEUmode: code = ARM_CS; goto dominance;
6693 case CC_DGTUmode: code = ARM_HI; goto dominance;
6694 case CC_DLEUmode: code = ARM_LS; goto dominance;
6695 case CC_DLTUmode: code = ARM_CC;
6698 if (comp_code != EQ && comp_code != NE)
6701 if (comp_code == EQ)
6702 return ARM_INVERSE_CONDITION_CODE (code);
6708 case NE: return ARM_NE;
6709 case EQ: return ARM_EQ;
6710 case GE: return ARM_PL;
6711 case LT: return ARM_MI;
6719 case NE: return ARM_NE;
6720 case EQ: return ARM_EQ;
6727 case GE: return ARM_GE;
6728 case GT: return ARM_GT;
6729 case LE: return ARM_LS;
6730 case LT: return ARM_MI;
6737 case NE: return ARM_NE;
6738 case EQ: return ARM_EQ;
6739 case GE: return ARM_LE;
6740 case GT: return ARM_LT;
6741 case LE: return ARM_GE;
6742 case LT: return ARM_GT;
6743 case GEU: return ARM_LS;
6744 case GTU: return ARM_CC;
6745 case LEU: return ARM_CS;
6746 case LTU: return ARM_HI;
6753 case LTU: return ARM_CS;
6754 case GEU: return ARM_CC;
6761 case NE: return ARM_NE;
6762 case EQ: return ARM_EQ;
6763 case GE: return ARM_GE;
6764 case GT: return ARM_GT;
6765 case LE: return ARM_LE;
6766 case LT: return ARM_LT;
6767 case GEU: return ARM_CS;
6768 case GTU: return ARM_HI;
6769 case LEU: return ARM_LS;
6770 case LTU: return ARM_CC;
6782 arm_final_prescan_insn (insn)
6785 /* BODY will hold the body of INSN. */
6786 register rtx body = PATTERN (insn);
6788 /* This will be 1 if trying to repeat the trick, and things need to be
6789 reversed if it appears to fail. */
6792 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6793 taken are clobbered, even if the rtl suggests otherwise. It also
6794 means that we have to grub around within the jump expression to find
6795 out what the conditions are when the jump isn't taken. */
6796 int jump_clobbers = 0;
6798 /* If we start with a return insn, we only succeed if we find another one. */
6799 int seeking_return = 0;
6801 /* START_INSN will hold the insn from where we start looking. This is the
6802 first insn after the following code_label if REVERSE is true. */
6803 rtx start_insn = insn;
6805 /* If in state 4, check if the target branch is reached, in order to
6806 change back to state 0. */
6807 if (arm_ccfsm_state == 4)
6809 if (insn == arm_target_insn)
6811 arm_target_insn = NULL;
6812 arm_ccfsm_state = 0;
6817 /* If in state 3, it is possible to repeat the trick, if this insn is an
6818 unconditional branch to a label, and immediately following this branch
6819 is the previous target label which is only used once, and the label this
6820 branch jumps to is not too far off. */
6821 if (arm_ccfsm_state == 3)
6823 if (simplejump_p (insn))
6825 start_insn = next_nonnote_insn (start_insn);
6826 if (GET_CODE (start_insn) == BARRIER)
6828 /* XXX Isn't this always a barrier? */
6829 start_insn = next_nonnote_insn (start_insn);
6831 if (GET_CODE (start_insn) == CODE_LABEL
6832 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6833 && LABEL_NUSES (start_insn) == 1)
6838 else if (GET_CODE (body) == RETURN)
6840 start_insn = next_nonnote_insn (start_insn);
6841 if (GET_CODE (start_insn) == BARRIER)
6842 start_insn = next_nonnote_insn (start_insn);
6843 if (GET_CODE (start_insn) == CODE_LABEL
6844 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6845 && LABEL_NUSES (start_insn) == 1)
6857 if (arm_ccfsm_state != 0 && !reverse)
6859 if (GET_CODE (insn) != JUMP_INSN)
6862 /* This jump might be paralleled with a clobber of the condition codes
6863 the jump should always come first */
6864 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6865 body = XVECEXP (body, 0, 0);
6868 /* If this is a conditional return then we don't want to know */
6869 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6870 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6871 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6872 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6877 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6878 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6881 int fail = FALSE, succeed = FALSE;
6882 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6883 int then_not_else = TRUE;
6884 rtx this_insn = start_insn, label = 0;
6886 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6888 /* The code below is wrong for these, and I haven't time to
6889 fix it now. So we just do the safe thing and return. This
6890 whole function needs re-writing anyway. */
6895 /* Register the insn jumped to. */
6898 if (!seeking_return)
6899 label = XEXP (SET_SRC (body), 0);
6901 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6902 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6903 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6905 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6906 then_not_else = FALSE;
6908 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6910 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6913 then_not_else = FALSE;
6918 /* See how many insns this branch skips, and what kind of insns. If all
6919 insns are okay, and the label or unconditional branch to the same
6920 label is not too far away, succeed. */
6921 for (insns_skipped = 0;
6922 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6926 this_insn = next_nonnote_insn (this_insn);
6930 switch (GET_CODE (this_insn))
6933 /* Succeed if it is the target label, otherwise fail since
6934 control falls in from somewhere else. */
6935 if (this_insn == label)
6939 arm_ccfsm_state = 2;
6940 this_insn = next_nonnote_insn (this_insn);
6943 arm_ccfsm_state = 1;
6951 /* Succeed if the following insn is the target label.
6953 If return insns are used then the last insn in a function
6954 will be a barrier. */
6955 this_insn = next_nonnote_insn (this_insn);
6956 if (this_insn && this_insn == label)
6960 arm_ccfsm_state = 2;
6961 this_insn = next_nonnote_insn (this_insn);
6964 arm_ccfsm_state = 1;
6972 /* If using 32-bit addresses the cc is not preserved over
6976 /* Succeed if the following insn is the target label,
6977 or if the following two insns are a barrier and
6978 the target label. */
6979 this_insn = next_nonnote_insn (this_insn);
6980 if (this_insn && GET_CODE (this_insn) == BARRIER)
6981 this_insn = next_nonnote_insn (this_insn);
6983 if (this_insn && this_insn == label
6984 && insns_skipped < max_insns_skipped)
6988 arm_ccfsm_state = 2;
6989 this_insn = next_nonnote_insn (this_insn);
6992 arm_ccfsm_state = 1;
7001 /* If this is an unconditional branch to the same label, succeed.
7002 If it is to another label, do nothing. If it is conditional,
7004 /* XXX Probably, the tests for SET and the PC are unnecessary. */
7006 scanbody = PATTERN (this_insn);
7007 if (GET_CODE (scanbody) == SET
7008 && GET_CODE (SET_DEST (scanbody)) == PC)
7010 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
7011 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
7013 arm_ccfsm_state = 2;
7016 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
7019 /* Fail if a conditional return is undesirable (eg on a
7020 StrongARM), but still allow this if optimizing for size. */
7021 else if (GET_CODE (scanbody) == RETURN
7022 && ! use_return_insn (TRUE)
7025 else if (GET_CODE (scanbody) == RETURN
7028 arm_ccfsm_state = 2;
7031 else if (GET_CODE (scanbody) == PARALLEL)
7033 switch (get_attr_conds (this_insn))
7045 /* Instructions using or affecting the condition codes make it
7047 scanbody = PATTERN (this_insn);
7048 if (! (GET_CODE (scanbody) == SET
7049 || GET_CODE (scanbody) == PARALLEL)
7050 || get_attr_conds (this_insn) != CONDS_NOCOND)
7060 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
7061 arm_target_label = CODE_LABEL_NUMBER (label);
7062 else if (seeking_return || arm_ccfsm_state == 2)
7064 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
7066 this_insn = next_nonnote_insn (this_insn);
7067 if (this_insn && (GET_CODE (this_insn) == BARRIER
7068 || GET_CODE (this_insn) == CODE_LABEL))
7073 /* Oh, dear! we ran off the end.. give up */
7074 recog (PATTERN (insn), insn, NULL_PTR);
7075 arm_ccfsm_state = 0;
7076 arm_target_insn = NULL;
7079 arm_target_insn = this_insn;
7088 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
7090 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
7091 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7092 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
7093 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7097 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
7100 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
7104 if (reverse || then_not_else)
7105 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
7108 /* Restore recog_data (getting the attributes of other insns can
7109 destroy this array, but final.c assumes that it remains intact
7110 across this call; since the insn has been recognized already we
7111 call recog direct). */
7112 recog (PATTERN (insn), insn, NULL_PTR);
7116 /* Return the length of a function name prefix
7117 that starts with the character 'c'. */
7119 arm_get_strip_length (char c)
7123 ARM_NAME_ENCODING_LENGTHS
7128 /* Return a pointer to a function's name with any
7129 and all prefix encodings stripped from it. */
7131 arm_strip_name_encoding (const char * name)
7135 while ((skip = arm_get_strip_length (* name)))
7141 #ifdef AOF_ASSEMBLER
7142 /* Special functions only needed when producing AOF syntax assembler. */
7144 rtx aof_pic_label = NULL_RTX;
7147 struct pic_chain * next;
7151 static struct pic_chain * aof_pic_chain = NULL;
7157 struct pic_chain ** chainp;
7160 if (aof_pic_label == NULL_RTX)
7162 /* We mark this here and not in arm_add_gc_roots() to avoid
7163 polluting even more code with ifdefs, and because it never
7164 contains anything useful until we assign to it here. */
7165 ggc_add_rtx_root (&aof_pic_label, 1);
7166 /* This needs to persist throughout the compilation. */
7167 end_temporary_allocation ();
7168 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
7169 resume_temporary_allocation ();
7172 for (offset = 0, chainp = &aof_pic_chain; *chainp;
7173 offset += 4, chainp = &(*chainp)->next)
7174 if ((*chainp)->symname == XSTR (x, 0))
7175 return plus_constant (aof_pic_label, offset);
7177 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
7178 (*chainp)->next = NULL;
7179 (*chainp)->symname = XSTR (x, 0);
7180 return plus_constant (aof_pic_label, offset);
7184 aof_dump_pic_table (f)
7187 struct pic_chain * chain;
7189 if (aof_pic_chain == NULL)
7192 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
7193 PIC_OFFSET_TABLE_REGNUM,
7194 PIC_OFFSET_TABLE_REGNUM);
7195 fputs ("|x$adcons|\n", f);
7197 for (chain = aof_pic_chain; chain; chain = chain->next)
7199 fputs ("\tDCD\t", f);
7200 assemble_name (f, chain->symname);
7205 int arm_text_section_count = 1;
7210 static char buf[100];
7211 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
7212 arm_text_section_count++);
7214 strcat (buf, ", PIC, REENTRANT");
7218 static int arm_data_section_count = 1;
7223 static char buf[100];
7224 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
7228 /* The AOF assembler is religiously strict about declarations of
7229 imported and exported symbols, so that it is impossible to declare
7230 a function as imported near the beginning of the file, and then to
7231 export it later on. It is, however, possible to delay the decision
7232 until all the functions in the file have been compiled. To get
7233 around this, we maintain a list of the imports and exports, and
7234 delete from it any that are subsequently defined. At the end of
7235 compilation we spit the remainder of the list out before the END
7240 struct import * next;
7244 static struct import * imports_list = NULL;
7247 aof_add_import (name)
7250 struct import * new;
7252 for (new = imports_list; new; new = new->next)
7253 if (new->name == name)
7256 new = (struct import *) xmalloc (sizeof (struct import));
7257 new->next = imports_list;
7263 aof_delete_import (name)
7266 struct import ** old;
7268 for (old = &imports_list; *old; old = & (*old)->next)
7270 if ((*old)->name == name)
7272 *old = (*old)->next;
7278 int arm_main_function = 0;
7281 aof_dump_imports (f)
7284 /* The AOF assembler needs this to cause the startup code to be extracted
7285 from the library. Brining in __main causes the whole thing to work
7287 if (arm_main_function)
7290 fputs ("\tIMPORT __main\n", f);
7291 fputs ("\tDCD __main\n", f);
7294 /* Now dump the remaining imports. */
7295 while (imports_list)
7297 fprintf (f, "\tIMPORT\t");
7298 assemble_name (f, imports_list->name);
7300 imports_list = imports_list->next;
7303 #endif /* AOF_ASSEMBLER */