1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static unsigned long thumb_compute_save_reg_mask (void);
75 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
76 static rtx emit_multi_reg_push (int);
77 static rtx emit_sfm (int, int);
79 static bool arm_assemble_integer (rtx, unsigned int, int);
81 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
82 static arm_cc get_arm_condition_code (rtx);
83 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
84 static rtx is_jump_table (rtx);
85 static const char *output_multi_immediate (rtx *, const char *, const char *,
87 static void print_multi_reg (FILE *, const char *, int, int);
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static int number_of_first_bit_set (int);
91 static void replace_symbols_in_block (tree, rtx, rtx);
92 static void thumb_exit (FILE *, int);
93 static void thumb_pushpop (FILE *, int, int, int *, int);
94 static rtx is_jump_table (rtx);
95 static HOST_WIDE_INT get_jump_table_size (rtx);
96 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_forward_ref (Mfix *);
98 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
99 static Mnode *add_minipool_backward_ref (Mfix *);
100 static void assign_minipool_offsets (Mfix *);
101 static void arm_print_value (FILE *, rtx);
102 static void dump_minipool (rtx);
103 static int arm_barrier_cost (rtx);
104 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
105 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
106 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
108 static void arm_reorg (void);
109 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
110 static int current_file_function_operand (rtx);
111 static unsigned long arm_compute_save_reg0_reg12_mask (void);
112 static unsigned long arm_compute_save_reg_mask (void);
113 static unsigned long arm_isr_value (tree);
114 static unsigned long arm_compute_func_type (void);
115 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
116 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
133 static bool arm_9e_rtx_costs (rtx, int, int, int *);
134 static int arm_address_cost (rtx);
135 static bool arm_memory_load_p (rtx);
136 static bool arm_cirrus_insn_p (rtx);
137 static void cirrus_reorg (rtx);
138 static void arm_init_builtins (void);
139 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140 static void arm_init_iwmmxt_builtins (void);
141 static rtx safe_vector_operand (rtx, enum machine_mode);
142 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
143 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
144 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
145 static void emit_constant_insn (rtx cond, rtx pattern);
147 #ifdef OBJECT_FORMAT_ELF
148 static void arm_elf_asm_named_section (const char *, unsigned int);
151 static void arm_encode_section_info (tree, rtx, int);
154 static void aof_globalize_label (FILE *, const char *);
155 static void aof_dump_imports (FILE *);
156 static void aof_dump_pic_table (FILE *);
157 static void aof_file_start (void);
158 static void aof_file_end (void);
160 static rtx arm_struct_value_rtx (tree, int);
161 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
163 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
164 enum machine_mode, tree, bool);
165 static bool arm_promote_prototypes (tree);
166 static bool arm_default_short_enums (void);
167 static bool arm_align_anon_bitfield (void);
169 static tree arm_cxx_guard_type (void);
170 static bool arm_cxx_guard_mask_bit (void);
171 static tree arm_get_cookie_size (tree);
172 static bool arm_cookie_has_size (void);
173 static bool arm_cxx_cdtor_returns_this (void);
174 static void arm_init_libfuncs (void);
177 /* Initialize the GCC target structure. */
178 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
179 #undef TARGET_MERGE_DECL_ATTRIBUTES
180 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
183 #undef TARGET_ATTRIBUTE_TABLE
184 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
187 #undef TARGET_ASM_BYTE_OP
188 #define TARGET_ASM_BYTE_OP "\tDCB\t"
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
193 #undef TARGET_ASM_GLOBALIZE_LABEL
194 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
195 #undef TARGET_ASM_FILE_START
196 #define TARGET_ASM_FILE_START aof_file_start
197 #undef TARGET_ASM_FILE_END
198 #define TARGET_ASM_FILE_END aof_file_end
200 #undef TARGET_ASM_ALIGNED_SI_OP
201 #define TARGET_ASM_ALIGNED_SI_OP NULL
202 #undef TARGET_ASM_INTEGER
203 #define TARGET_ASM_INTEGER arm_assemble_integer
206 #undef TARGET_ASM_FUNCTION_PROLOGUE
207 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
209 #undef TARGET_ASM_FUNCTION_EPILOGUE
210 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
212 #undef TARGET_COMP_TYPE_ATTRIBUTES
213 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
215 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
216 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
218 #undef TARGET_SCHED_ADJUST_COST
219 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
221 #undef TARGET_ENCODE_SECTION_INFO
223 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
225 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
228 #undef TARGET_STRIP_NAME_ENCODING
229 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
231 #undef TARGET_ASM_INTERNAL_LABEL
232 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
234 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
235 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
237 #undef TARGET_ASM_OUTPUT_MI_THUNK
238 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
239 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
240 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
242 /* This will be overridden in arm_override_options. */
243 #undef TARGET_RTX_COSTS
244 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
245 #undef TARGET_ADDRESS_COST
246 #define TARGET_ADDRESS_COST arm_address_cost
248 #undef TARGET_MACHINE_DEPENDENT_REORG
249 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
251 #undef TARGET_INIT_BUILTINS
252 #define TARGET_INIT_BUILTINS arm_init_builtins
253 #undef TARGET_EXPAND_BUILTIN
254 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
256 #undef TARGET_INIT_LIBFUNCS
257 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
259 #undef TARGET_PROMOTE_FUNCTION_ARGS
260 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
261 #undef TARGET_PROMOTE_FUNCTION_RETURN
262 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
263 #undef TARGET_PROMOTE_PROTOTYPES
264 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
265 #undef TARGET_PASS_BY_REFERENCE
266 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
268 #undef TARGET_STRUCT_VALUE_RTX
269 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
271 #undef TARGET_SETUP_INCOMING_VARARGS
272 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
274 #undef TARGET_DEFAULT_SHORT_ENUMS
275 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
277 #undef TARGET_ALIGN_ANON_BITFIELD
278 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
280 #undef TARGET_CXX_GUARD_TYPE
281 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
283 #undef TARGET_CXX_GUARD_MASK_BIT
284 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
286 #undef TARGET_CXX_GET_COOKIE_SIZE
287 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
289 #undef TARGET_CXX_COOKIE_HAS_SIZE
290 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
292 #undef TARGET_CXX_CDTOR_RETURNS_THIS
293 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
295 struct gcc_target targetm = TARGET_INITIALIZER;
297 /* Obstack for minipool constant handling. */
298 static struct obstack minipool_obstack;
299 static char * minipool_startobj;
301 /* The maximum number of insns skipped which
302 will be conditionalised if possible. */
303 static int max_insns_skipped = 5;
305 extern FILE * asm_out_file;
307 /* True if we are currently building a constant table. */
308 int making_const_table;
310 /* Define the information needed to generate branch insns. This is
311 stored from the compare operation. */
312 rtx arm_compare_op0, arm_compare_op1;
314 /* The processor for which instructions should be scheduled. */
315 enum processor_type arm_tune = arm_none;
317 /* Which floating point model to use. */
318 enum arm_fp_model arm_fp_model;
320 /* Which floating point hardware is available. */
321 enum fputype arm_fpu_arch;
323 /* Which floating point hardware to schedule for. */
324 enum fputype arm_fpu_tune;
326 /* Whether to use floating point hardware. */
327 enum float_abi_type arm_float_abi;
329 /* Which ABI to use. */
330 enum arm_abi_type arm_abi;
332 /* Set by the -mfpu=... option. */
333 const char * target_fpu_name = NULL;
335 /* Set by the -mfpe=... option. */
336 const char * target_fpe_name = NULL;
338 /* Set by the -mfloat-abi=... option. */
339 const char * target_float_abi_name = NULL;
341 /* Set by the -mabi=... option. */
342 const char * target_abi_name = NULL;
344 /* Used to parse -mstructure_size_boundary command line option. */
345 const char * structure_size_string = NULL;
346 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
348 /* Bit values used to identify processor capabilities. */
349 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
350 #define FL_ARCH3M (1 << 1) /* Extended multiply */
351 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
352 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
353 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
354 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
355 #define FL_THUMB (1 << 6) /* Thumb aware */
356 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
357 #define FL_STRONG (1 << 8) /* StrongARM */
358 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
359 #define FL_XSCALE (1 << 10) /* XScale */
360 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
361 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
362 media instructions. */
363 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
365 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
367 #define FL_FOR_ARCH2 0
368 #define FL_FOR_ARCH3 FL_MODE32
369 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
370 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
371 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
372 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
373 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
374 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
375 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
376 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
377 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
378 #define FL_FOR_ARCH6J FL_FOR_ARCH6
380 /* The bits in this mask specify which
381 instructions we are allowed to generate. */
382 static unsigned long insn_flags = 0;
384 /* The bits in this mask specify which instruction scheduling options should
386 static unsigned long tune_flags = 0;
388 /* The following are used in the arm.md file as equivalents to bits
389 in the above two flag variables. */
391 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
394 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
397 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
400 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
403 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
406 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
409 /* Nonzero if this chip can benefit from load scheduling. */
410 int arm_ld_sched = 0;
412 /* Nonzero if this chip is a StrongARM. */
413 int arm_is_strong = 0;
415 /* Nonzero if this chip is a Cirrus variant. */
416 int arm_arch_cirrus = 0;
418 /* Nonzero if this chip supports Intel Wireless MMX technology. */
419 int arm_arch_iwmmxt = 0;
421 /* Nonzero if this chip is an XScale. */
422 int arm_arch_xscale = 0;
424 /* Nonzero if tuning for XScale */
425 int arm_tune_xscale = 0;
427 /* Nonzero if this chip is an ARM6 or an ARM7. */
428 int arm_is_6_or_7 = 0;
430 /* Nonzero if generating Thumb instructions. */
433 /* Nonzero if we should define __THUMB_INTERWORK__ in the
435 XXX This is a bit of a hack, it's intended to help work around
436 problems in GLD which doesn't understand that armv5t code is
437 interworking clean. */
438 int arm_cpp_interwork = 0;
440 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
441 must report the mode of the memory reference from PRINT_OPERAND to
442 PRINT_OPERAND_ADDRESS. */
443 enum machine_mode output_memory_reference_mode;
445 /* The register number to be used for the PIC offset register. */
446 const char * arm_pic_register_string = NULL;
447 int arm_pic_register = INVALID_REGNUM;
449 /* Set to 1 when a return insn is output, this means that the epilogue
451 int return_used_this_function;
453 /* Set to 1 after arm_reorg has started. Reset to start at the start of
454 the next function. */
455 static int after_arm_reorg = 0;
457 /* The maximum number of insns to be used when loading a constant. */
458 static int arm_constant_limit = 3;
460 /* For an explanation of these variables, see final_prescan_insn below. */
462 enum arm_cond_code arm_current_cc;
464 int arm_target_label;
466 /* The condition codes of the ARM, and the inverse function. */
467 static const char * const arm_condition_codes[] =
469 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
470 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
473 #define streq(string1, string2) (strcmp (string1, string2) == 0)
475 /* Initialization code. */
479 const char *const name;
480 enum processor_type core;
482 const unsigned long flags;
483 bool (* rtx_costs) (rtx, int, int, int *);
486 /* Not all of these give usefully different compilation alternatives,
487 but there is no simple way of generalizing them. */
488 static const struct processors all_cores[] =
491 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
492 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
493 #include "arm-cores.def"
495 {NULL, arm_none, NULL, 0, NULL}
498 static const struct processors all_architectures[] =
500 /* ARM Architectures */
501 /* We don't specify rtx_costs here as it will be figured out
504 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
505 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
506 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
507 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
508 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
509 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
510 implementations that support it, so we will leave it out for now. */
511 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
512 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
513 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
514 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
515 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
516 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
517 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
518 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
519 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
520 {NULL, arm_none, NULL, 0 , NULL}
523 /* This is a magic structure. The 'string' field is magically filled in
524 with a pointer to the value specified by the user on the command line
525 assuming that the user has specified such a value. */
527 struct arm_cpu_select arm_select[] =
529 /* string name processors */
530 { NULL, "-mcpu=", all_cores },
531 { NULL, "-march=", all_architectures },
532 { NULL, "-mtune=", all_cores }
536 /* The name of the proprocessor macro to define for this architecture. */
538 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
547 /* Available values for for -mfpu=. */
549 static const struct fpu_desc all_fpus[] =
551 {"fpa", FPUTYPE_FPA},
552 {"fpe2", FPUTYPE_FPA_EMU2},
553 {"fpe3", FPUTYPE_FPA_EMU2},
554 {"maverick", FPUTYPE_MAVERICK},
559 /* Floating point models used by the different hardware.
560 See fputype in arm.h. */
562 static const enum fputype fp_model_for_fpu[] =
564 /* No FP hardware. */
565 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
566 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
567 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
568 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
569 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
570 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
577 enum float_abi_type abi_type;
581 /* Available values for -mfloat-abi=. */
583 static const struct float_abi all_float_abis[] =
585 {"soft", ARM_FLOAT_ABI_SOFT},
586 {"softfp", ARM_FLOAT_ABI_SOFTFP},
587 {"hard", ARM_FLOAT_ABI_HARD}
594 enum arm_abi_type abi_type;
598 /* Available values for -mabi=. */
600 static const struct abi_name arm_all_abis[] =
602 {"apcs-gnu", ARM_ABI_APCS},
603 {"atpcs", ARM_ABI_ATPCS},
604 {"aapcs", ARM_ABI_AAPCS},
605 {"iwmmxt", ARM_ABI_IWMMXT}
608 /* Return the number of bits set in VALUE. */
610 bit_count (unsigned long value)
612 unsigned long count = 0;
617 value &= value - 1; /* Clear the least-significant set bit. */
623 /* Set up library functions uqniue to ARM. */
626 arm_init_libfuncs (void)
628 /* There are no special library functions unless we are using the
633 /* The functions below are described in Section 4 of the "Run-Time
634 ABI for the ARM architecture", Version 1.0. */
636 /* Double-precision floating-point arithmetic. Table 2. */
637 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
638 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
639 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
640 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
641 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
643 /* Double-precision comparisions. Table 3. */
644 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
645 set_optab_libfunc (ne_optab, DFmode, NULL);
646 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
647 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
648 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
649 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
650 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
652 /* Single-precision floating-point arithmetic. Table 4. */
653 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
654 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
655 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
656 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
657 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
659 /* Single-precision comparisions. Table 5. */
660 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
661 set_optab_libfunc (ne_optab, SFmode, NULL);
662 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
663 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
664 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
665 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
666 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
668 /* Floating-point to integer conversions. Table 6. */
669 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
670 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
671 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
672 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
673 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
674 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
675 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
676 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
678 /* Conversions between floating types. Table 7. */
679 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
680 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
682 /* Integer to floating-point converisons. Table 8. */
683 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
684 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
685 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
686 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
687 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
688 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
689 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
690 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
692 /* Long long. Table 9. */
693 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
694 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
695 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
696 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
697 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
698 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
699 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
700 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
702 /* Integer (32/32->32) division. \S 4.3.1. */
703 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
704 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
706 /* The divmod functions are designed so that they can be used for
707 plain division, even though they return both the quotient and the
708 remainder. The quotient is returned in the usual location (i.e.,
709 r0 for SImode, {r0, r1} for DImode), just as would be expected
710 for an ordinary division routine. Because the AAPCS calling
711 conventions specify that all of { r0, r1, r2, r3 } are
712 callee-saved registers, there is no need to tell the compiler
713 explicitly that those registers are clobbered by these
715 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
716 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
717 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
718 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
721 /* Fix up any incompatible options that the user has specified.
722 This has now turned into a maze. */
724 arm_override_options (void)
728 /* Set up the flags based on the cpu/architecture selected by the user. */
729 for (i = ARRAY_SIZE (arm_select); i--;)
731 struct arm_cpu_select * ptr = arm_select + i;
733 if (ptr->string != NULL && ptr->string[0] != '\0')
735 const struct processors * sel;
737 for (sel = ptr->processors; sel->name != NULL; sel++)
738 if (streq (ptr->string, sel->name))
740 /* Set the architecture define. */
742 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
744 /* Determine the processor core for which we should
745 tune code-generation. */
746 if (/* -mcpu= is a sensible default. */
748 /* If -march= is used, and -mcpu= has not been used,
749 assume that we should tune for a representative
750 CPU from that architecture. */
752 /* -mtune= overrides -mcpu= and -march=. */
754 arm_tune = (enum processor_type) (sel - ptr->processors);
758 /* If we have been given an architecture and a processor
759 make sure that they are compatible. We only generate
760 a warning though, and we prefer the CPU over the
762 if (insn_flags != 0 && (insn_flags ^ sel->flags))
763 warning ("switch -mcpu=%s conflicts with -march= switch",
766 insn_flags = sel->flags;
772 if (sel->name == NULL)
773 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
777 /* If the user did not specify a processor, choose one for them. */
780 const struct processors * sel;
782 enum processor_type cpu;
784 cpu = TARGET_CPU_DEFAULT;
787 #ifdef SUBTARGET_CPU_DEFAULT
788 /* Use the subtarget default CPU if none was specified by
790 cpu = SUBTARGET_CPU_DEFAULT;
792 /* Default to ARM6. */
796 sel = &all_cores[cpu];
798 insn_flags = sel->flags;
800 /* Now check to see if the user has specified some command line
801 switch that require certain abilities from the cpu. */
804 if (TARGET_INTERWORK || TARGET_THUMB)
806 sought |= (FL_THUMB | FL_MODE32);
808 /* There are no ARM processors that support both APCS-26 and
809 interworking. Therefore we force FL_MODE26 to be removed
810 from insn_flags here (if it was set), so that the search
811 below will always be able to find a compatible processor. */
812 insn_flags &= ~FL_MODE26;
815 if (sought != 0 && ((sought & insn_flags) != sought))
817 /* Try to locate a CPU type that supports all of the abilities
818 of the default CPU, plus the extra abilities requested by
820 for (sel = all_cores; sel->name != NULL; sel++)
821 if ((sel->flags & sought) == (sought | insn_flags))
824 if (sel->name == NULL)
826 unsigned current_bit_count = 0;
827 const struct processors * best_fit = NULL;
829 /* Ideally we would like to issue an error message here
830 saying that it was not possible to find a CPU compatible
831 with the default CPU, but which also supports the command
832 line options specified by the programmer, and so they
833 ought to use the -mcpu=<name> command line option to
834 override the default CPU type.
836 If we cannot find a cpu that has both the
837 characteristics of the default cpu and the given
838 command line options we scan the array again looking
840 for (sel = all_cores; sel->name != NULL; sel++)
841 if ((sel->flags & sought) == sought)
845 count = bit_count (sel->flags & insn_flags);
847 if (count >= current_bit_count)
850 current_bit_count = count;
854 if (best_fit == NULL)
860 insn_flags = sel->flags;
862 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
863 if (arm_tune == arm_none)
864 arm_tune = (enum processor_type) (sel - all_cores);
867 /* The processor for which we should tune should now have been
869 if (arm_tune == arm_none)
872 tune_flags = all_cores[(int)arm_tune].flags;
873 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
875 /* Make sure that the processor choice does not conflict with any of the
876 other command line choices. */
877 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
879 warning ("target CPU does not support interworking" );
880 target_flags &= ~ARM_FLAG_INTERWORK;
883 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
885 warning ("target CPU does not support THUMB instructions");
886 target_flags &= ~ARM_FLAG_THUMB;
889 if (TARGET_APCS_FRAME && TARGET_THUMB)
891 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
892 target_flags &= ~ARM_FLAG_APCS_FRAME;
895 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
896 from here where no function is being compiled currently. */
897 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
899 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
901 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
902 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
904 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
905 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
907 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
909 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
910 target_flags |= ARM_FLAG_APCS_FRAME;
913 if (TARGET_POKE_FUNCTION_NAME)
914 target_flags |= ARM_FLAG_APCS_FRAME;
916 if (TARGET_APCS_REENT && flag_pic)
917 error ("-fpic and -mapcs-reent are incompatible");
919 if (TARGET_APCS_REENT)
920 warning ("APCS reentrant code not supported. Ignored");
922 /* If this target is normally configured to use APCS frames, warn if they
923 are turned off and debugging is turned on. */
925 && write_symbols != NO_DEBUG
926 && !TARGET_APCS_FRAME
927 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
928 warning ("-g with -mno-apcs-frame may not give sensible debugging");
930 /* If stack checking is disabled, we can use r10 as the PIC register,
931 which keeps r9 available. */
933 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
935 if (TARGET_APCS_FLOAT)
936 warning ("passing floating point arguments in fp regs not yet supported");
938 /* Initialize boolean versions of the flags, for use in the arm.md file. */
939 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
940 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
941 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
942 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
943 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
944 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
945 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
946 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
948 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
949 arm_is_strong = (tune_flags & FL_STRONG) != 0;
950 thumb_code = (TARGET_ARM == 0);
951 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
952 && !(tune_flags & FL_ARCH4))) != 0;
953 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
954 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
956 /* V5 code we generate is completely interworking capable, so we turn off
957 TARGET_INTERWORK here to avoid many tests later on. */
959 /* XXX However, we must pass the right pre-processor defines to CPP
960 or GLD can get confused. This is a hack. */
961 if (TARGET_INTERWORK)
962 arm_cpp_interwork = 1;
965 target_flags &= ~ARM_FLAG_INTERWORK;
969 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
971 if (streq (arm_all_abis[i].name, target_abi_name))
973 arm_abi = arm_all_abis[i].abi_type;
977 if (i == ARRAY_SIZE (arm_all_abis))
978 error ("invalid ABI option: -mabi=%s", target_abi_name);
981 arm_abi = ARM_DEFAULT_ABI;
983 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
984 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
986 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
987 error ("iwmmxt abi requires an iwmmxt capable cpu");
989 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
990 if (target_fpu_name == NULL && target_fpe_name != NULL)
992 if (streq (target_fpe_name, "2"))
993 target_fpu_name = "fpe2";
994 else if (streq (target_fpe_name, "3"))
995 target_fpu_name = "fpe3";
997 error ("invalid floating point emulation option: -mfpe=%s",
1000 if (target_fpu_name != NULL)
1002 /* The user specified a FPU. */
1003 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1005 if (streq (all_fpus[i].name, target_fpu_name))
1007 arm_fpu_arch = all_fpus[i].fpu;
1008 arm_fpu_tune = arm_fpu_arch;
1009 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1013 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1014 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1018 #ifdef FPUTYPE_DEFAULT
1019 /* Use the default if it is specified for this platform. */
1020 arm_fpu_arch = FPUTYPE_DEFAULT;
1021 arm_fpu_tune = FPUTYPE_DEFAULT;
1023 /* Pick one based on CPU type. */
1024 /* ??? Some targets assume FPA is the default.
1025 if ((insn_flags & FL_VFP) != 0)
1026 arm_fpu_arch = FPUTYPE_VFP;
1029 if (arm_arch_cirrus)
1030 arm_fpu_arch = FPUTYPE_MAVERICK;
1032 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1034 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1035 arm_fpu_tune = FPUTYPE_FPA;
1037 arm_fpu_tune = arm_fpu_arch;
1038 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1039 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1043 if (target_float_abi_name != NULL)
1045 /* The user specified a FP ABI. */
1046 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1048 if (streq (all_float_abis[i].name, target_float_abi_name))
1050 arm_float_abi = all_float_abis[i].abi_type;
1054 if (i == ARRAY_SIZE (all_float_abis))
1055 error ("invalid floating point abi: -mfloat-abi=%s",
1056 target_float_abi_name);
1060 /* Use soft-float target flag. */
1061 if (target_flags & ARM_FLAG_SOFT_FLOAT)
1062 arm_float_abi = ARM_FLOAT_ABI_SOFT;
1064 arm_float_abi = ARM_FLOAT_ABI_HARD;
1067 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
1068 sorry ("-mfloat-abi=softfp");
1069 /* If soft-float is specified then don't use FPU. */
1070 if (TARGET_SOFT_FLOAT)
1071 arm_fpu_arch = FPUTYPE_NONE;
1073 /* For arm2/3 there is no need to do any scheduling if there is only
1074 a floating point emulator, or we are doing software floating-point. */
1075 if ((TARGET_SOFT_FLOAT
1076 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1077 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1078 && (tune_flags & FL_MODE32) == 0)
1079 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1081 /* Override the default structure alignment for AAPCS ABI. */
1082 if (arm_abi == ARM_ABI_AAPCS)
1083 arm_structure_size_boundary = 8;
1085 if (structure_size_string != NULL)
1087 int size = strtol (structure_size_string, NULL, 0);
1089 if (size == 8 || size == 32
1090 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1091 arm_structure_size_boundary = size;
1093 warning ("structure size boundary can only be set to %s",
1094 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1097 if (arm_pic_register_string != NULL)
1099 int pic_register = decode_reg_name (arm_pic_register_string);
1102 warning ("-mpic-register= is useless without -fpic");
1104 /* Prevent the user from choosing an obviously stupid PIC register. */
1105 else if (pic_register < 0 || call_used_regs[pic_register]
1106 || pic_register == HARD_FRAME_POINTER_REGNUM
1107 || pic_register == STACK_POINTER_REGNUM
1108 || pic_register >= PC_REGNUM)
1109 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1111 arm_pic_register = pic_register;
1114 if (TARGET_THUMB && flag_schedule_insns)
1116 /* Don't warn since it's on by default in -O2. */
1117 flag_schedule_insns = 0;
1122 /* There's some dispute as to whether this should be 1 or 2. However,
1123 experiments seem to show that in pathological cases a setting of
1124 1 degrades less severely than a setting of 2. This could change if
1125 other parts of the compiler change their behavior. */
1126 arm_constant_limit = 1;
1128 /* If optimizing for size, bump the number of instructions that we
1129 are prepared to conditionally execute (even on a StrongARM). */
1130 max_insns_skipped = 6;
1134 /* For processors with load scheduling, it never costs more than
1135 2 cycles to load a constant, and the load scheduler may well
1136 reduce that to 1. */
1137 if (tune_flags & FL_LDSCHED)
1138 arm_constant_limit = 1;
1140 /* On XScale the longer latency of a load makes it more difficult
1141 to achieve a good schedule, so it's faster to synthesize
1142 constants that can be done in two insns. */
1143 if (arm_tune_xscale)
1144 arm_constant_limit = 2;
1146 /* StrongARM has early execution of branches, so a sequence
1147 that is worth skipping is shorter. */
1149 max_insns_skipped = 3;
1152 /* Register global variables with the garbage collector. */
1153 arm_add_gc_roots ();
1157 arm_add_gc_roots (void)
1159 gcc_obstack_init(&minipool_obstack);
1160 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1163 /* A table of known ARM exception types.
1164 For use with the interrupt function attribute. */
1168 const char *const arg;
1169 const unsigned long return_value;
1173 static const isr_attribute_arg isr_attribute_args [] =
1175 { "IRQ", ARM_FT_ISR },
1176 { "irq", ARM_FT_ISR },
1177 { "FIQ", ARM_FT_FIQ },
1178 { "fiq", ARM_FT_FIQ },
1179 { "ABORT", ARM_FT_ISR },
1180 { "abort", ARM_FT_ISR },
1181 { "ABORT", ARM_FT_ISR },
1182 { "abort", ARM_FT_ISR },
1183 { "UNDEF", ARM_FT_EXCEPTION },
1184 { "undef", ARM_FT_EXCEPTION },
1185 { "SWI", ARM_FT_EXCEPTION },
1186 { "swi", ARM_FT_EXCEPTION },
1187 { NULL, ARM_FT_NORMAL }
1190 /* Returns the (interrupt) function type of the current
1191 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1193 static unsigned long
1194 arm_isr_value (tree argument)
1196 const isr_attribute_arg * ptr;
1199 /* No argument - default to IRQ. */
1200 if (argument == NULL_TREE)
1203 /* Get the value of the argument. */
1204 if (TREE_VALUE (argument) == NULL_TREE
1205 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1206 return ARM_FT_UNKNOWN;
1208 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1210 /* Check it against the list of known arguments. */
1211 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1212 if (streq (arg, ptr->arg))
1213 return ptr->return_value;
1215 /* An unrecognized interrupt type. */
1216 return ARM_FT_UNKNOWN;
1219 /* Computes the type of the current function. */
1221 static unsigned long
1222 arm_compute_func_type (void)
1224 unsigned long type = ARM_FT_UNKNOWN;
1228 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1231 /* Decide if the current function is volatile. Such functions
1232 never return, and many memory cycles can be saved by not storing
1233 register values that will never be needed again. This optimization
1234 was added to speed up context switching in a kernel application. */
1236 && TREE_NOTHROW (current_function_decl)
1237 && TREE_THIS_VOLATILE (current_function_decl))
1238 type |= ARM_FT_VOLATILE;
1240 if (cfun->static_chain_decl != NULL)
1241 type |= ARM_FT_NESTED;
1243 attr = DECL_ATTRIBUTES (current_function_decl);
1245 a = lookup_attribute ("naked", attr);
1247 type |= ARM_FT_NAKED;
1249 a = lookup_attribute ("isr", attr);
1251 a = lookup_attribute ("interrupt", attr);
1254 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1256 type |= arm_isr_value (TREE_VALUE (a));
1261 /* Returns the type of the current function. */
1264 arm_current_func_type (void)
1266 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1267 cfun->machine->func_type = arm_compute_func_type ();
1269 return cfun->machine->func_type;
1272 /* Return 1 if it is possible to return using a single instruction.
1273 If SIBLING is non-null, this is a test for a return before a sibling
1274 call. SIBLING is the call insn, so we can examine its register usage. */
1277 use_return_insn (int iscond, rtx sibling)
1280 unsigned int func_type;
1281 unsigned long saved_int_regs;
1282 unsigned HOST_WIDE_INT stack_adjust;
1283 arm_stack_offsets *offsets;
1285 /* Never use a return instruction before reload has run. */
1286 if (!reload_completed)
1289 func_type = arm_current_func_type ();
1291 /* Naked functions and volatile functions need special
1293 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1296 /* So do interrupt functions that use the frame pointer. */
1297 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1300 offsets = arm_get_frame_offsets ();
1301 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1303 /* As do variadic functions. */
1304 if (current_function_pretend_args_size
1305 || cfun->machine->uses_anonymous_args
1306 /* Or if the function calls __builtin_eh_return () */
1307 || current_function_calls_eh_return
1308 /* Or if the function calls alloca */
1309 || current_function_calls_alloca
1310 /* Or if there is a stack adjustment. However, if the stack pointer
1311 is saved on the stack, we can use a pre-incrementing stack load. */
1312 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1315 saved_int_regs = arm_compute_save_reg_mask ();
1317 /* Unfortunately, the insn
1319 ldmib sp, {..., sp, ...}
1321 triggers a bug on most SA-110 based devices, such that the stack
1322 pointer won't be correctly restored if the instruction takes a
1323 page fault. We work around this problem by popping r3 along with
1324 the other registers, since that is never slower than executing
1325 another instruction.
1327 We test for !arm_arch5 here, because code for any architecture
1328 less than this could potentially be run on one of the buggy
1330 if (stack_adjust == 4 && !arm_arch5)
1332 /* Validate that r3 is a call-clobbered register (always true in
1333 the default abi) ... */
1334 if (!call_used_regs[3])
1337 /* ... that it isn't being used for a return value (always true
1338 until we implement return-in-regs), or for a tail-call
1342 if (GET_CODE (sibling) != CALL_INSN)
1345 if (find_regno_fusage (sibling, USE, 3))
1349 /* ... and that there are no call-saved registers in r0-r2
1350 (always true in the default ABI). */
1351 if (saved_int_regs & 0x7)
1355 /* Can't be done if interworking with Thumb, and any registers have been
1357 if (TARGET_INTERWORK && saved_int_regs != 0)
1360 /* On StrongARM, conditional returns are expensive if they aren't
1361 taken and multiple registers have been stacked. */
1362 if (iscond && arm_is_strong)
1364 /* Conditional return when just the LR is stored is a simple
1365 conditional-load instruction, that's not expensive. */
1366 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1369 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1373 /* If there are saved registers but the LR isn't saved, then we need
1374 two instructions for the return. */
1375 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1378 /* Can't be done if any of the FPA regs are pushed,
1379 since this also requires an insn. */
1380 if (TARGET_HARD_FLOAT && TARGET_FPA)
1381 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1382 if (regs_ever_live[regno] && !call_used_regs[regno])
1385 /* Likewise VFP regs. */
1386 if (TARGET_HARD_FLOAT && TARGET_VFP)
1387 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1388 if (regs_ever_live[regno] && !call_used_regs[regno])
1391 if (TARGET_REALLY_IWMMXT)
1392 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1393 if (regs_ever_live[regno] && ! call_used_regs [regno])
1399 /* Return TRUE if int I is a valid immediate ARM constant. */
1402 const_ok_for_arm (HOST_WIDE_INT i)
1404 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1406 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1407 be all zero, or all one. */
1408 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1409 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1410 != ((~(unsigned HOST_WIDE_INT) 0)
1411 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1414 /* Fast return for 0 and powers of 2 */
1415 if ((i & (i - 1)) == 0)
1420 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1423 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1424 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1426 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1431 /* Return true if I is a valid constant for the operation CODE. */
1433 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1435 if (const_ok_for_arm (i))
1441 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1443 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1449 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1456 /* Emit a sequence of insns to handle a large constant.
1457 CODE is the code of the operation required, it can be any of SET, PLUS,
1458 IOR, AND, XOR, MINUS;
1459 MODE is the mode in which the operation is being performed;
1460 VAL is the integer to operate on;
1461 SOURCE is the other operand (a register, or a null-pointer for SET);
1462 SUBTARGETS means it is safe to create scratch registers if that will
1463 either produce a simpler sequence, or we will want to cse the values.
1464 Return value is the number of insns emitted. */
1467 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1468 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1472 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1473 cond = COND_EXEC_TEST (PATTERN (insn));
1477 if (subtargets || code == SET
1478 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1479 && REGNO (target) != REGNO (source)))
1481 /* After arm_reorg has been called, we can't fix up expensive
1482 constants by pushing them into memory so we must synthesize
1483 them in-line, regardless of the cost. This is only likely to
1484 be more costly on chips that have load delay slots and we are
1485 compiling without running the scheduler (so no splitting
1486 occurred before the final instruction emission).
1488 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1490 if (!after_arm_reorg
1492 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1494 > arm_constant_limit + (code != SET)))
1498 /* Currently SET is the only monadic value for CODE, all
1499 the rest are diadic. */
1500 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1505 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1507 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1508 /* For MINUS, the value is subtracted from, since we never
1509 have subtraction of a constant. */
1511 emit_insn (gen_rtx_SET (VOIDmode, target,
1512 gen_rtx_MINUS (mode, temp, source)));
1514 emit_insn (gen_rtx_SET (VOIDmode, target,
1515 gen_rtx_fmt_ee (code, mode, source, temp)));
1521 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1526 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1528 HOST_WIDE_INT temp1;
1536 if (remainder & (3 << (i - 2)))
1541 temp1 = remainder & ((0x0ff << end)
1542 | ((i < end) ? (0xff >> (32 - end)) : 0));
1543 remainder &= ~temp1;
1548 } while (remainder);
1552 /* Emit an instruction with the indicated PATTERN. If COND is
1553 non-NULL, conditionalize the execution of the instruction on COND
1557 emit_constant_insn (rtx cond, rtx pattern)
1560 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1561 emit_insn (pattern);
1564 /* As above, but extra parameter GENERATE which, if clear, suppresses
1568 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1569 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1574 int can_negate_initial = 0;
1577 int num_bits_set = 0;
1578 int set_sign_bit_copies = 0;
1579 int clear_sign_bit_copies = 0;
1580 int clear_zero_bit_copies = 0;
1581 int set_zero_bit_copies = 0;
1583 unsigned HOST_WIDE_INT temp1, temp2;
1584 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1586 /* Find out which operations are safe for a given CODE. Also do a quick
1587 check for degenerate cases; these can occur when DImode operations
1599 can_negate_initial = 1;
1603 if (remainder == 0xffffffff)
1606 emit_constant_insn (cond,
1607 gen_rtx_SET (VOIDmode, target,
1608 GEN_INT (ARM_SIGN_EXTEND (val))));
1613 if (reload_completed && rtx_equal_p (target, source))
1616 emit_constant_insn (cond,
1617 gen_rtx_SET (VOIDmode, target, source));
1626 emit_constant_insn (cond,
1627 gen_rtx_SET (VOIDmode, target, const0_rtx));
1630 if (remainder == 0xffffffff)
1632 if (reload_completed && rtx_equal_p (target, source))
1635 emit_constant_insn (cond,
1636 gen_rtx_SET (VOIDmode, target, source));
1645 if (reload_completed && rtx_equal_p (target, source))
1648 emit_constant_insn (cond,
1649 gen_rtx_SET (VOIDmode, target, source));
1652 if (remainder == 0xffffffff)
1655 emit_constant_insn (cond,
1656 gen_rtx_SET (VOIDmode, target,
1657 gen_rtx_NOT (mode, source)));
1661 /* We don't know how to handle this yet below. */
1665 /* We treat MINUS as (val - source), since (source - val) is always
1666 passed as (source + (-val)). */
1670 emit_constant_insn (cond,
1671 gen_rtx_SET (VOIDmode, target,
1672 gen_rtx_NEG (mode, source)));
1675 if (const_ok_for_arm (val))
1678 emit_constant_insn (cond,
1679 gen_rtx_SET (VOIDmode, target,
1680 gen_rtx_MINUS (mode, GEN_INT (val),
1692 /* If we can do it in one insn get out quickly. */
1693 if (const_ok_for_arm (val)
1694 || (can_negate_initial && const_ok_for_arm (-val))
1695 || (can_invert && const_ok_for_arm (~val)))
1698 emit_constant_insn (cond,
1699 gen_rtx_SET (VOIDmode, target,
1701 ? gen_rtx_fmt_ee (code, mode, source,
1707 /* Calculate a few attributes that may be useful for specific
1709 for (i = 31; i >= 0; i--)
1711 if ((remainder & (1 << i)) == 0)
1712 clear_sign_bit_copies++;
1717 for (i = 31; i >= 0; i--)
1719 if ((remainder & (1 << i)) != 0)
1720 set_sign_bit_copies++;
1725 for (i = 0; i <= 31; i++)
1727 if ((remainder & (1 << i)) == 0)
1728 clear_zero_bit_copies++;
1733 for (i = 0; i <= 31; i++)
1735 if ((remainder & (1 << i)) != 0)
1736 set_zero_bit_copies++;
1744 /* See if we can do this by sign_extending a constant that is known
1745 to be negative. This is a good, way of doing it, since the shift
1746 may well merge into a subsequent insn. */
1747 if (set_sign_bit_copies > 1)
1749 if (const_ok_for_arm
1750 (temp1 = ARM_SIGN_EXTEND (remainder
1751 << (set_sign_bit_copies - 1))))
1755 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1756 emit_constant_insn (cond,
1757 gen_rtx_SET (VOIDmode, new_src,
1759 emit_constant_insn (cond,
1760 gen_ashrsi3 (target, new_src,
1761 GEN_INT (set_sign_bit_copies - 1)));
1765 /* For an inverted constant, we will need to set the low bits,
1766 these will be shifted out of harm's way. */
1767 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1768 if (const_ok_for_arm (~temp1))
1772 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1773 emit_constant_insn (cond,
1774 gen_rtx_SET (VOIDmode, new_src,
1776 emit_constant_insn (cond,
1777 gen_ashrsi3 (target, new_src,
1778 GEN_INT (set_sign_bit_copies - 1)));
1784 /* See if we can generate this by setting the bottom (or the top)
1785 16 bits, and then shifting these into the other half of the
1786 word. We only look for the simplest cases, to do more would cost
1787 too much. Be careful, however, not to generate this when the
1788 alternative would take fewer insns. */
1789 if (val & 0xffff0000)
1791 temp1 = remainder & 0xffff0000;
1792 temp2 = remainder & 0x0000ffff;
1794 /* Overlaps outside this range are best done using other methods. */
1795 for (i = 9; i < 24; i++)
1797 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1798 && !const_ok_for_arm (temp2))
1800 rtx new_src = (subtargets
1801 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1803 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1804 source, subtargets, generate);
1812 gen_rtx_ASHIFT (mode, source,
1819 /* Don't duplicate cases already considered. */
1820 for (i = 17; i < 24; i++)
1822 if (((temp1 | (temp1 >> i)) == remainder)
1823 && !const_ok_for_arm (temp1))
1825 rtx new_src = (subtargets
1826 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1828 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1829 source, subtargets, generate);
1834 gen_rtx_SET (VOIDmode, target,
1837 gen_rtx_LSHIFTRT (mode, source,
1848 /* If we have IOR or XOR, and the constant can be loaded in a
1849 single instruction, and we can find a temporary to put it in,
1850 then this can be done in two instructions instead of 3-4. */
1852 /* TARGET can't be NULL if SUBTARGETS is 0 */
1853 || (reload_completed && !reg_mentioned_p (target, source)))
1855 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1859 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1861 emit_constant_insn (cond,
1862 gen_rtx_SET (VOIDmode, sub,
1864 emit_constant_insn (cond,
1865 gen_rtx_SET (VOIDmode, target,
1866 gen_rtx_fmt_ee (code, mode,
1876 if (set_sign_bit_copies > 8
1877 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1881 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1882 rtx shift = GEN_INT (set_sign_bit_copies);
1886 gen_rtx_SET (VOIDmode, sub,
1888 gen_rtx_ASHIFT (mode,
1893 gen_rtx_SET (VOIDmode, target,
1895 gen_rtx_LSHIFTRT (mode, sub,
1901 if (set_zero_bit_copies > 8
1902 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1906 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1907 rtx shift = GEN_INT (set_zero_bit_copies);
1911 gen_rtx_SET (VOIDmode, sub,
1913 gen_rtx_LSHIFTRT (mode,
1918 gen_rtx_SET (VOIDmode, target,
1920 gen_rtx_ASHIFT (mode, sub,
1926 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1930 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1931 emit_constant_insn (cond,
1932 gen_rtx_SET (VOIDmode, sub,
1933 gen_rtx_NOT (mode, source)));
1936 sub = gen_reg_rtx (mode);
1937 emit_constant_insn (cond,
1938 gen_rtx_SET (VOIDmode, sub,
1939 gen_rtx_AND (mode, source,
1941 emit_constant_insn (cond,
1942 gen_rtx_SET (VOIDmode, target,
1943 gen_rtx_NOT (mode, sub)));
1950 /* See if two shifts will do 2 or more insn's worth of work. */
1951 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1953 HOST_WIDE_INT shift_mask = ((0xffffffff
1954 << (32 - clear_sign_bit_copies))
1957 if ((remainder | shift_mask) != 0xffffffff)
1961 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1962 insns = arm_gen_constant (AND, mode, cond,
1963 remainder | shift_mask,
1964 new_src, source, subtargets, 1);
1969 rtx targ = subtargets ? NULL_RTX : target;
1970 insns = arm_gen_constant (AND, mode, cond,
1971 remainder | shift_mask,
1972 targ, source, subtargets, 0);
1978 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1979 rtx shift = GEN_INT (clear_sign_bit_copies);
1981 emit_insn (gen_ashlsi3 (new_src, source, shift));
1982 emit_insn (gen_lshrsi3 (target, new_src, shift));
1988 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1990 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1992 if ((remainder | shift_mask) != 0xffffffff)
1996 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1998 insns = arm_gen_constant (AND, mode, cond,
1999 remainder | shift_mask,
2000 new_src, source, subtargets, 1);
2005 rtx targ = subtargets ? NULL_RTX : target;
2007 insns = arm_gen_constant (AND, mode, cond,
2008 remainder | shift_mask,
2009 targ, source, subtargets, 0);
2015 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2016 rtx shift = GEN_INT (clear_zero_bit_copies);
2018 emit_insn (gen_lshrsi3 (new_src, source, shift));
2019 emit_insn (gen_ashlsi3 (target, new_src, shift));
2031 for (i = 0; i < 32; i++)
2032 if (remainder & (1 << i))
2035 if (code == AND || (can_invert && num_bits_set > 16))
2036 remainder = (~remainder) & 0xffffffff;
2037 else if (code == PLUS && num_bits_set > 16)
2038 remainder = (-remainder) & 0xffffffff;
2045 /* Now try and find a way of doing the job in either two or three
2047 We start by looking for the largest block of zeros that are aligned on
2048 a 2-bit boundary, we then fill up the temps, wrapping around to the
2049 top of the word when we drop off the bottom.
2050 In the worst case this code should produce no more than four insns. */
2053 int best_consecutive_zeros = 0;
2055 for (i = 0; i < 32; i += 2)
2057 int consecutive_zeros = 0;
2059 if (!(remainder & (3 << i)))
2061 while ((i < 32) && !(remainder & (3 << i)))
2063 consecutive_zeros += 2;
2066 if (consecutive_zeros > best_consecutive_zeros)
2068 best_consecutive_zeros = consecutive_zeros;
2069 best_start = i - consecutive_zeros;
2075 /* So long as it won't require any more insns to do so, it's
2076 desirable to emit a small constant (in bits 0...9) in the last
2077 insn. This way there is more chance that it can be combined with
2078 a later addressing insn to form a pre-indexed load or store
2079 operation. Consider:
2081 *((volatile int *)0xe0000100) = 1;
2082 *((volatile int *)0xe0000110) = 2;
2084 We want this to wind up as:
2088 str rB, [rA, #0x100]
2090 str rB, [rA, #0x110]
2092 rather than having to synthesize both large constants from scratch.
2094 Therefore, we calculate how many insns would be required to emit
2095 the constant starting from `best_start', and also starting from
2096 zero (ie with bit 31 first to be output). If `best_start' doesn't
2097 yield a shorter sequence, we may as well use zero. */
2099 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2100 && (count_insns_for_constant (remainder, 0) <=
2101 count_insns_for_constant (remainder, best_start)))
2104 /* Now start emitting the insns. */
2112 if (remainder & (3 << (i - 2)))
2117 temp1 = remainder & ((0x0ff << end)
2118 | ((i < end) ? (0xff >> (32 - end)) : 0));
2119 remainder &= ~temp1;
2123 rtx new_src, temp1_rtx;
2125 if (code == SET || code == MINUS)
2127 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2128 if (can_invert && code != MINUS)
2133 if (remainder && subtargets)
2134 new_src = gen_reg_rtx (mode);
2139 else if (can_negate)
2143 temp1 = trunc_int_for_mode (temp1, mode);
2144 temp1_rtx = GEN_INT (temp1);
2148 else if (code == MINUS)
2149 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2151 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2153 emit_constant_insn (cond,
2154 gen_rtx_SET (VOIDmode, new_src,
2164 else if (code == MINUS)
2178 /* Canonicalize a comparison so that we are more likely to recognize it.
2179 This can be done for a few constant compares, where we can make the
2180 immediate value easier to load. */
2183 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2185 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2195 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2196 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2198 *op1 = GEN_INT (i + 1);
2199 return code == GT ? GE : LT;
2205 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2206 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2208 *op1 = GEN_INT (i - 1);
2209 return code == GE ? GT : LE;
2215 if (i != ~((unsigned HOST_WIDE_INT) 0)
2216 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2218 *op1 = GEN_INT (i + 1);
2219 return code == GTU ? GEU : LTU;
2226 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2228 *op1 = GEN_INT (i - 1);
2229 return code == GEU ? GTU : LEU;
2241 /* Define how to find the value returned by a function. */
2243 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2245 enum machine_mode mode;
2246 int unsignedp ATTRIBUTE_UNUSED;
2247 rtx r ATTRIBUTE_UNUSED;
2250 mode = TYPE_MODE (type);
2251 /* Promote integer types. */
2252 if (INTEGRAL_TYPE_P (type))
2253 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2254 return LIBCALL_VALUE(mode);
2258 /* Decide whether a type should be returned in memory (true)
2259 or in a register (false). This is called by the macro
2260 RETURN_IN_MEMORY. */
2262 arm_return_in_memory (tree type)
2266 if (!AGGREGATE_TYPE_P (type))
2267 /* All simple types are returned in registers. */
2270 size = int_size_in_bytes (type);
2272 if (arm_abi != ARM_ABI_APCS)
2274 /* ATPCS and later return aggregate types in memory only if they are
2275 larger than a word (or are variable size). */
2276 return (size < 0 || size > UNITS_PER_WORD);
2279 /* For the arm-wince targets we choose to be compatible with Microsoft's
2280 ARM and Thumb compilers, which always return aggregates in memory. */
2282 /* All structures/unions bigger than one word are returned in memory.
2283 Also catch the case where int_size_in_bytes returns -1. In this case
2284 the aggregate is either huge or of variable size, and in either case
2285 we will want to return it via memory and not in a register. */
2286 if (size < 0 || size > UNITS_PER_WORD)
2289 if (TREE_CODE (type) == RECORD_TYPE)
2293 /* For a struct the APCS says that we only return in a register
2294 if the type is 'integer like' and every addressable element
2295 has an offset of zero. For practical purposes this means
2296 that the structure can have at most one non bit-field element
2297 and that this element must be the first one in the structure. */
2299 /* Find the first field, ignoring non FIELD_DECL things which will
2300 have been created by C++. */
2301 for (field = TYPE_FIELDS (type);
2302 field && TREE_CODE (field) != FIELD_DECL;
2303 field = TREE_CHAIN (field))
2307 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2309 /* Check that the first field is valid for returning in a register. */
2311 /* ... Floats are not allowed */
2312 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2315 /* ... Aggregates that are not themselves valid for returning in
2316 a register are not allowed. */
2317 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2320 /* Now check the remaining fields, if any. Only bitfields are allowed,
2321 since they are not addressable. */
2322 for (field = TREE_CHAIN (field);
2324 field = TREE_CHAIN (field))
2326 if (TREE_CODE (field) != FIELD_DECL)
2329 if (!DECL_BIT_FIELD_TYPE (field))
2336 if (TREE_CODE (type) == UNION_TYPE)
2340 /* Unions can be returned in registers if every element is
2341 integral, or can be returned in an integer register. */
2342 for (field = TYPE_FIELDS (type);
2344 field = TREE_CHAIN (field))
2346 if (TREE_CODE (field) != FIELD_DECL)
2349 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2352 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2358 #endif /* not ARM_WINCE */
2360 /* Return all other types in memory. */
2364 /* Indicate whether or not words of a double are in big-endian order. */
2367 arm_float_words_big_endian (void)
2369 if (TARGET_MAVERICK)
2372 /* For FPA, float words are always big-endian. For VFP, floats words
2373 follow the memory system mode. */
2381 return (TARGET_BIG_END ? 1 : 0);
2386 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2387 for a call to a function whose data type is FNTYPE.
2388 For a library call, FNTYPE is NULL. */
2390 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2391 rtx libname ATTRIBUTE_UNUSED,
2392 tree fndecl ATTRIBUTE_UNUSED)
2394 /* On the ARM, the offset starts at 0. */
2395 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2396 pcum->iwmmxt_nregs = 0;
2397 pcum->can_split = true;
2399 pcum->call_cookie = CALL_NORMAL;
2401 if (TARGET_LONG_CALLS)
2402 pcum->call_cookie = CALL_LONG;
2404 /* Check for long call/short call attributes. The attributes
2405 override any command line option. */
2408 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2409 pcum->call_cookie = CALL_SHORT;
2410 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2411 pcum->call_cookie = CALL_LONG;
2414 /* Varargs vectors are treated the same as long long.
2415 named_count avoids having to change the way arm handles 'named' */
2416 pcum->named_count = 0;
2419 if (TARGET_REALLY_IWMMXT && fntype)
2423 for (fn_arg = TYPE_ARG_TYPES (fntype);
2425 fn_arg = TREE_CHAIN (fn_arg))
2426 pcum->named_count += 1;
2428 if (! pcum->named_count)
2429 pcum->named_count = INT_MAX;
2434 /* Return true if mode/type need doubleword alignment. */
2436 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2438 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2439 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2443 /* Determine where to put an argument to a function.
2444 Value is zero to push the argument on the stack,
2445 or a hard register in which to store the argument.
2447 MODE is the argument's machine mode.
2448 TYPE is the data type of the argument (as a tree).
2449 This is null for libcalls where that information may
2451 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2452 the preceding args and about the function being called.
2453 NAMED is nonzero if this argument is a named parameter
2454 (otherwise it is an extra parameter matching an ellipsis). */
2457 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2458 tree type, int named)
2462 /* Varargs vectors are treated the same as long long.
2463 named_count avoids having to change the way arm handles 'named' */
2464 if (TARGET_IWMMXT_ABI
2465 && VECTOR_MODE_SUPPORTED_P (mode)
2466 && pcum->named_count > pcum->nargs + 1)
2468 if (pcum->iwmmxt_nregs <= 9)
2469 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2472 pcum->can_split = false;
2477 /* Put doubleword aligned quantities in even register pairs. */
2479 && ARM_DOUBLEWORD_ALIGN
2480 && arm_needs_doubleword_align (mode, type))
2483 if (mode == VOIDmode)
2484 /* Compute operand 2 of the call insn. */
2485 return GEN_INT (pcum->call_cookie);
2487 /* Only allow splitting an arg between regs and memory if all preceding
2488 args were allocated to regs. For args passed by reference we only count
2489 the reference pointer. */
2490 if (pcum->can_split)
2493 nregs = ARM_NUM_REGS2 (mode, type);
2495 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2498 return gen_rtx_REG (mode, pcum->nregs);
2501 /* Variable sized types are passed by reference. This is a GCC
2502 extension to the ARM ABI. */
2505 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2506 enum machine_mode mode ATTRIBUTE_UNUSED,
2507 tree type, bool named ATTRIBUTE_UNUSED)
2509 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2512 /* Encode the current state of the #pragma [no_]long_calls. */
2515 OFF, /* No #pramgma [no_]long_calls is in effect. */
2516 LONG, /* #pragma long_calls is in effect. */
2517 SHORT /* #pragma no_long_calls is in effect. */
2520 static arm_pragma_enum arm_pragma_long_calls = OFF;
2523 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2525 arm_pragma_long_calls = LONG;
2529 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2531 arm_pragma_long_calls = SHORT;
2535 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2537 arm_pragma_long_calls = OFF;
2540 /* Table of machine attributes. */
2541 const struct attribute_spec arm_attribute_table[] =
2543 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2544 /* Function calls made to this symbol must be done indirectly, because
2545 it may lie outside of the 26 bit addressing range of a normal function
2547 { "long_call", 0, 0, false, true, true, NULL },
2548 /* Whereas these functions are always known to reside within the 26 bit
2549 addressing range. */
2550 { "short_call", 0, 0, false, true, true, NULL },
2551 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2552 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2553 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2554 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2556 /* ARM/PE has three new attributes:
2558 dllexport - for exporting a function/variable that will live in a dll
2559 dllimport - for importing a function/variable from a dll
2561 Microsoft allows multiple declspecs in one __declspec, separating
2562 them with spaces. We do NOT support this. Instead, use __declspec
2565 { "dllimport", 0, 0, true, false, false, NULL },
2566 { "dllexport", 0, 0, true, false, false, NULL },
2567 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2568 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2569 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2570 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2572 { NULL, 0, 0, false, false, false, NULL }
2575 /* Handle an attribute requiring a FUNCTION_DECL;
2576 arguments as in struct attribute_spec.handler. */
2578 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2579 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2581 if (TREE_CODE (*node) != FUNCTION_DECL)
2583 warning ("`%s' attribute only applies to functions",
2584 IDENTIFIER_POINTER (name));
2585 *no_add_attrs = true;
2591 /* Handle an "interrupt" or "isr" attribute;
2592 arguments as in struct attribute_spec.handler. */
2594 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2599 if (TREE_CODE (*node) != FUNCTION_DECL)
2601 warning ("`%s' attribute only applies to functions",
2602 IDENTIFIER_POINTER (name));
2603 *no_add_attrs = true;
2605 /* FIXME: the argument if any is checked for type attributes;
2606 should it be checked for decl ones? */
2610 if (TREE_CODE (*node) == FUNCTION_TYPE
2611 || TREE_CODE (*node) == METHOD_TYPE)
2613 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2615 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2616 *no_add_attrs = true;
2619 else if (TREE_CODE (*node) == POINTER_TYPE
2620 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2621 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2622 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2624 *node = build_type_copy (*node);
2625 TREE_TYPE (*node) = build_type_attribute_variant
2627 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2628 *no_add_attrs = true;
2632 /* Possibly pass this attribute on from the type to a decl. */
2633 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2634 | (int) ATTR_FLAG_FUNCTION_NEXT
2635 | (int) ATTR_FLAG_ARRAY_NEXT))
2637 *no_add_attrs = true;
2638 return tree_cons (name, args, NULL_TREE);
2642 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2650 /* Return 0 if the attributes for two types are incompatible, 1 if they
2651 are compatible, and 2 if they are nearly compatible (which causes a
2652 warning to be generated). */
2654 arm_comp_type_attributes (tree type1, tree type2)
2658 /* Check for mismatch of non-default calling convention. */
2659 if (TREE_CODE (type1) != FUNCTION_TYPE)
2662 /* Check for mismatched call attributes. */
2663 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2664 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2665 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2666 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2668 /* Only bother to check if an attribute is defined. */
2669 if (l1 | l2 | s1 | s2)
2671 /* If one type has an attribute, the other must have the same attribute. */
2672 if ((l1 != l2) || (s1 != s2))
2675 /* Disallow mixed attributes. */
2676 if ((l1 & s2) || (l2 & s1))
2680 /* Check for mismatched ISR attribute. */
2681 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2683 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2684 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2686 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2693 /* Encode long_call or short_call attribute by prefixing
2694 symbol name in DECL with a special character FLAG. */
2696 arm_encode_call_attribute (tree decl, int flag)
2698 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2699 int len = strlen (str);
2702 /* Do not allow weak functions to be treated as short call. */
2703 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2706 newstr = alloca (len + 2);
2708 strcpy (newstr + 1, str);
2710 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2711 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2714 /* Assigns default attributes to newly defined type. This is used to
2715 set short_call/long_call attributes for function types of
2716 functions defined inside corresponding #pragma scopes. */
2718 arm_set_default_type_attributes (tree type)
2720 /* Add __attribute__ ((long_call)) to all functions, when
2721 inside #pragma long_calls or __attribute__ ((short_call)),
2722 when inside #pragma no_long_calls. */
2723 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2725 tree type_attr_list, attr_name;
2726 type_attr_list = TYPE_ATTRIBUTES (type);
2728 if (arm_pragma_long_calls == LONG)
2729 attr_name = get_identifier ("long_call");
2730 else if (arm_pragma_long_calls == SHORT)
2731 attr_name = get_identifier ("short_call");
2735 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2736 TYPE_ATTRIBUTES (type) = type_attr_list;
2740 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2741 defined within the current compilation unit. If this cannot be
2742 determined, then 0 is returned. */
2744 current_file_function_operand (rtx sym_ref)
2746 /* This is a bit of a fib. A function will have a short call flag
2747 applied to its name if it has the short call attribute, or it has
2748 already been defined within the current compilation unit. */
2749 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2752 /* The current function is always defined within the current compilation
2753 unit. If it s a weak definition however, then this may not be the real
2754 definition of the function, and so we have to say no. */
2755 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2756 && !DECL_WEAK (current_function_decl))
2759 /* We cannot make the determination - default to returning 0. */
2763 /* Return nonzero if a 32 bit "long_call" should be generated for
2764 this call. We generate a long_call if the function:
2766 a. has an __attribute__((long call))
2767 or b. is within the scope of a #pragma long_calls
2768 or c. the -mlong-calls command line switch has been specified
2770 1. -ffunction-sections is in effect
2771 or 2. the current function has __attribute__ ((section))
2772 or 3. the target function has __attribute__ ((section))
2774 However we do not generate a long call if the function:
2776 d. has an __attribute__ ((short_call))
2777 or e. is inside the scope of a #pragma no_long_calls
2778 or f. is defined within the current compilation unit.
2780 This function will be called by C fragments contained in the machine
2781 description file. SYM_REF and CALL_COOKIE correspond to the matched
2782 rtl operands. CALL_SYMBOL is used to distinguish between
2783 two different callers of the function. It is set to 1 in the
2784 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2785 and "call_value" patterns. This is because of the difference in the
2786 SYM_REFs passed by these patterns. */
2788 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2792 if (GET_CODE (sym_ref) != MEM)
2795 sym_ref = XEXP (sym_ref, 0);
2798 if (GET_CODE (sym_ref) != SYMBOL_REF)
2801 if (call_cookie & CALL_SHORT)
2804 if (TARGET_LONG_CALLS)
2806 if (flag_function_sections
2807 || DECL_SECTION_NAME (current_function_decl))
2808 /* c.3 is handled by the defintion of the
2809 ARM_DECLARE_FUNCTION_SIZE macro. */
2813 if (current_file_function_operand (sym_ref))
2816 return (call_cookie & CALL_LONG)
2817 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2818 || TARGET_LONG_CALLS;
2821 /* Return nonzero if it is ok to make a tail-call to DECL. */
2823 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2825 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2827 if (cfun->machine->sibcall_blocked)
2830 /* Never tailcall something for which we have no decl, or if we
2831 are in Thumb mode. */
2832 if (decl == NULL || TARGET_THUMB)
2835 /* Get the calling method. */
2836 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2837 call_type = CALL_SHORT;
2838 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2839 call_type = CALL_LONG;
2841 /* Cannot tail-call to long calls, since these are out of range of
2842 a branch instruction. However, if not compiling PIC, we know
2843 we can reach the symbol if it is in this compilation unit. */
2844 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2847 /* If we are interworking and the function is not declared static
2848 then we can't tail-call it unless we know that it exists in this
2849 compilation unit (since it might be a Thumb routine). */
2850 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2853 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2854 if (IS_INTERRUPT (arm_current_func_type ()))
2857 /* Everything else is ok. */
2862 /* Addressing mode support functions. */
2864 /* Return nonzero if X is a legitimate immediate operand when compiling
2867 legitimate_pic_operand_p (rtx x)
2871 && (GET_CODE (x) == SYMBOL_REF
2872 || (GET_CODE (x) == CONST
2873 && GET_CODE (XEXP (x, 0)) == PLUS
2874 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2881 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2883 if (GET_CODE (orig) == SYMBOL_REF
2884 || GET_CODE (orig) == LABEL_REF)
2886 #ifndef AOF_ASSEMBLER
2887 rtx pic_ref, address;
2897 reg = gen_reg_rtx (Pmode);
2902 #ifdef AOF_ASSEMBLER
2903 /* The AOF assembler can generate relocations for these directly, and
2904 understands that the PIC register has to be added into the offset. */
2905 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2908 address = gen_reg_rtx (Pmode);
2913 emit_insn (gen_pic_load_addr_arm (address, orig));
2915 emit_insn (gen_pic_load_addr_thumb (address, orig));
2917 if ((GET_CODE (orig) == LABEL_REF
2918 || (GET_CODE (orig) == SYMBOL_REF &&
2919 SYMBOL_REF_LOCAL_P (orig)))
2921 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2924 pic_ref = gen_rtx_MEM (Pmode,
2925 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2927 RTX_UNCHANGING_P (pic_ref) = 1;
2930 insn = emit_move_insn (reg, pic_ref);
2932 current_function_uses_pic_offset_table = 1;
2933 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2935 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2939 else if (GET_CODE (orig) == CONST)
2943 if (GET_CODE (XEXP (orig, 0)) == PLUS
2944 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2952 reg = gen_reg_rtx (Pmode);
2955 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2957 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2958 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2959 base == reg ? 0 : reg);
2964 if (GET_CODE (offset) == CONST_INT)
2966 /* The base register doesn't really matter, we only want to
2967 test the index for the appropriate mode. */
2968 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2970 if (!no_new_pseudos)
2971 offset = force_reg (Pmode, offset);
2976 if (GET_CODE (offset) == CONST_INT)
2977 return plus_constant (base, INTVAL (offset));
2980 if (GET_MODE_SIZE (mode) > 4
2981 && (GET_MODE_CLASS (mode) == MODE_INT
2982 || TARGET_SOFT_FLOAT))
2984 emit_insn (gen_addsi3 (reg, base, offset));
2988 return gen_rtx_PLUS (Pmode, base, offset);
2995 /* Find a spare low register. */
2998 thumb_find_work_register (int live_regs_mask)
3002 /* Use a spare arg register. */
3003 if (!regs_ever_live[LAST_ARG_REGNUM])
3004 return LAST_ARG_REGNUM;
3006 /* Look for a pushed register. */
3007 for (reg = 0; reg < LAST_LO_REGNUM; reg++)
3008 if (live_regs_mask & (1 << reg))
3011 /* Something went wrong. */
3015 /* Generate code to load the PIC register. PROLOGUE is true if
3016 called from arm_expand_prologue (in which case we want the
3017 generated insns at the start of the function); false if called
3018 by an exception receiver that needs the PIC register reloaded
3019 (in which case the insns are just dumped at the current location). */
3021 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
3023 #ifndef AOF_ASSEMBLER
3024 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
3025 rtx global_offset_table;
3027 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3034 l1 = gen_label_rtx ();
3036 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3037 /* On the ARM the PC register contains 'dot + 8' at the time of the
3038 addition, on the Thumb it is 'dot + 4'. */
3039 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3041 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3042 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3044 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3046 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3050 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3051 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3055 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3056 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3062 emit_insn_after (seq, get_insns ());
3066 /* Need to emit this whether or not we obey regdecls,
3067 since setjmp/longjmp can cause life info to screw up. */
3068 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3069 #endif /* AOF_ASSEMBLER */
3072 /* Return nonzero if X is valid as an ARM state addressing register. */
3074 arm_address_register_rtx_p (rtx x, int strict_p)
3078 if (GET_CODE (x) != REG)
3084 return ARM_REGNO_OK_FOR_BASE_P (regno);
3086 return (regno <= LAST_ARM_REGNUM
3087 || regno >= FIRST_PSEUDO_REGISTER
3088 || regno == FRAME_POINTER_REGNUM
3089 || regno == ARG_POINTER_REGNUM);
3092 /* Return nonzero if X is a valid ARM state address operand. */
3094 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3098 enum rtx_code code = GET_CODE (x);
3100 if (arm_address_register_rtx_p (x, strict_p))
3103 use_ldrd = (TARGET_LDRD
3105 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3107 if (code == POST_INC || code == PRE_DEC
3108 || ((code == PRE_INC || code == POST_DEC)
3109 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3110 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3112 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3113 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3114 && GET_CODE (XEXP (x, 1)) == PLUS
3115 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3117 rtx addend = XEXP (XEXP (x, 1), 1);
3119 /* Don't allow ldrd post increment by register becuase it's hard
3120 to fixup invalid register choices. */
3122 && GET_CODE (x) == POST_MODIFY
3123 && GET_CODE (addend) == REG)
3126 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3127 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3130 /* After reload constants split into minipools will have addresses
3131 from a LABEL_REF. */
3132 else if (reload_completed
3133 && (code == LABEL_REF
3135 && GET_CODE (XEXP (x, 0)) == PLUS
3136 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3137 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3140 else if (mode == TImode)
3143 else if (code == PLUS)
3145 rtx xop0 = XEXP (x, 0);
3146 rtx xop1 = XEXP (x, 1);
3148 return ((arm_address_register_rtx_p (xop0, strict_p)
3149 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3150 || (arm_address_register_rtx_p (xop1, strict_p)
3151 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3155 /* Reload currently can't handle MINUS, so disable this for now */
3156 else if (GET_CODE (x) == MINUS)
3158 rtx xop0 = XEXP (x, 0);
3159 rtx xop1 = XEXP (x, 1);
3161 return (arm_address_register_rtx_p (xop0, strict_p)
3162 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3166 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3167 && code == SYMBOL_REF
3168 && CONSTANT_POOL_ADDRESS_P (x)
3170 && symbol_mentioned_p (get_pool_constant (x))))
3176 /* Return nonzero if INDEX is valid for an address index operand in
3179 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3182 HOST_WIDE_INT range;
3183 enum rtx_code code = GET_CODE (index);
3185 /* Standard coprocessor addressing modes. */
3186 if (TARGET_HARD_FLOAT
3187 && (TARGET_FPA || TARGET_MAVERICK)
3188 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3189 || (TARGET_MAVERICK && mode == DImode)))
3190 return (code == CONST_INT && INTVAL (index) < 1024
3191 && INTVAL (index) > -1024
3192 && (INTVAL (index) & 3) == 0);
3194 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3195 return (code == CONST_INT
3196 && INTVAL (index) < 1024
3197 && INTVAL (index) > -1024
3198 && (INTVAL (index) & 3) == 0);
3200 if (arm_address_register_rtx_p (index, strict_p)
3201 && (GET_MODE_SIZE (mode) <= 4))
3204 if (mode == DImode || mode == DFmode)
3206 if (code == CONST_INT)
3208 HOST_WIDE_INT val = INTVAL (index);
3211 return val > -256 && val < 256;
3213 return val > -4096 && val < 4092;
3216 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3219 if (GET_MODE_SIZE (mode) <= 4
3222 || (mode == QImode && outer == SIGN_EXTEND))))
3226 rtx xiop0 = XEXP (index, 0);
3227 rtx xiop1 = XEXP (index, 1);
3229 return ((arm_address_register_rtx_p (xiop0, strict_p)
3230 && power_of_two_operand (xiop1, SImode))
3231 || (arm_address_register_rtx_p (xiop1, strict_p)
3232 && power_of_two_operand (xiop0, SImode)));
3234 else if (code == LSHIFTRT || code == ASHIFTRT
3235 || code == ASHIFT || code == ROTATERT)
3237 rtx op = XEXP (index, 1);
3239 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3240 && GET_CODE (op) == CONST_INT
3242 && INTVAL (op) <= 31);
3246 /* For ARM v4 we may be doing a sign-extend operation during the
3250 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3256 range = (mode == HImode) ? 4095 : 4096;
3258 return (code == CONST_INT
3259 && INTVAL (index) < range
3260 && INTVAL (index) > -range);
3263 /* Return nonzero if X is valid as a Thumb state base register. */
3265 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3269 if (GET_CODE (x) != REG)
3275 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3277 return (regno <= LAST_LO_REGNUM
3278 || regno > LAST_VIRTUAL_REGISTER
3279 || regno == FRAME_POINTER_REGNUM
3280 || (GET_MODE_SIZE (mode) >= 4
3281 && (regno == STACK_POINTER_REGNUM
3282 || regno >= FIRST_PSEUDO_REGISTER
3283 || x == hard_frame_pointer_rtx
3284 || x == arg_pointer_rtx)));
3287 /* Return nonzero if x is a legitimate index register. This is the case
3288 for any base register that can access a QImode object. */
3290 thumb_index_register_rtx_p (rtx x, int strict_p)
3292 return thumb_base_register_rtx_p (x, QImode, strict_p);
3295 /* Return nonzero if x is a legitimate Thumb-state address.
3297 The AP may be eliminated to either the SP or the FP, so we use the
3298 least common denominator, e.g. SImode, and offsets from 0 to 64.
3300 ??? Verify whether the above is the right approach.
3302 ??? Also, the FP may be eliminated to the SP, so perhaps that
3303 needs special handling also.
3305 ??? Look at how the mips16 port solves this problem. It probably uses
3306 better ways to solve some of these problems.
3308 Although it is not incorrect, we don't accept QImode and HImode
3309 addresses based on the frame pointer or arg pointer until the
3310 reload pass starts. This is so that eliminating such addresses
3311 into stack based ones won't produce impossible code. */
3313 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3315 /* ??? Not clear if this is right. Experiment. */
3316 if (GET_MODE_SIZE (mode) < 4
3317 && !(reload_in_progress || reload_completed)
3318 && (reg_mentioned_p (frame_pointer_rtx, x)
3319 || reg_mentioned_p (arg_pointer_rtx, x)
3320 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3321 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3322 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3323 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3326 /* Accept any base register. SP only in SImode or larger. */
3327 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3330 /* This is PC relative data before arm_reorg runs. */
3331 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3332 && GET_CODE (x) == SYMBOL_REF
3333 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3336 /* This is PC relative data after arm_reorg runs. */
3337 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3338 && (GET_CODE (x) == LABEL_REF
3339 || (GET_CODE (x) == CONST
3340 && GET_CODE (XEXP (x, 0)) == PLUS
3341 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3342 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3345 /* Post-inc indexing only supported for SImode and larger. */
3346 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3347 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3350 else if (GET_CODE (x) == PLUS)
3352 /* REG+REG address can be any two index registers. */
3353 /* We disallow FRAME+REG addressing since we know that FRAME
3354 will be replaced with STACK, and SP relative addressing only
3355 permits SP+OFFSET. */
3356 if (GET_MODE_SIZE (mode) <= 4
3357 && XEXP (x, 0) != frame_pointer_rtx
3358 && XEXP (x, 1) != frame_pointer_rtx
3359 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3360 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3363 /* REG+const has 5-7 bit offset for non-SP registers. */
3364 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3365 || XEXP (x, 0) == arg_pointer_rtx)
3366 && GET_CODE (XEXP (x, 1)) == CONST_INT
3367 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3370 /* REG+const has 10 bit offset for SP, but only SImode and
3371 larger is supported. */
3372 /* ??? Should probably check for DI/DFmode overflow here
3373 just like GO_IF_LEGITIMATE_OFFSET does. */
3374 else if (GET_CODE (XEXP (x, 0)) == REG
3375 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3376 && GET_MODE_SIZE (mode) >= 4
3377 && GET_CODE (XEXP (x, 1)) == CONST_INT
3378 && INTVAL (XEXP (x, 1)) >= 0
3379 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3380 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3383 else if (GET_CODE (XEXP (x, 0)) == REG
3384 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3385 && GET_MODE_SIZE (mode) >= 4
3386 && GET_CODE (XEXP (x, 1)) == CONST_INT
3387 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3391 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3392 && GET_MODE_SIZE (mode) == 4
3393 && GET_CODE (x) == SYMBOL_REF
3394 && CONSTANT_POOL_ADDRESS_P (x)
3396 && symbol_mentioned_p (get_pool_constant (x))))
3402 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3403 instruction of mode MODE. */
3405 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3407 switch (GET_MODE_SIZE (mode))
3410 return val >= 0 && val < 32;
3413 return val >= 0 && val < 64 && (val & 1) == 0;
3417 && (val + GET_MODE_SIZE (mode)) <= 128
3422 /* Try machine-dependent ways of modifying an illegitimate address
3423 to be legitimate. If we find one, return the new, valid address. */
3425 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3427 if (GET_CODE (x) == PLUS)
3429 rtx xop0 = XEXP (x, 0);
3430 rtx xop1 = XEXP (x, 1);
3432 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3433 xop0 = force_reg (SImode, xop0);
3435 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3436 xop1 = force_reg (SImode, xop1);
3438 if (ARM_BASE_REGISTER_RTX_P (xop0)
3439 && GET_CODE (xop1) == CONST_INT)
3441 HOST_WIDE_INT n, low_n;
3445 /* VFP addressing modes actually allow greater offsets, but for
3446 now we just stick with the lowest common denominator. */
3448 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3460 low_n = ((mode) == TImode ? 0
3461 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3465 base_reg = gen_reg_rtx (SImode);
3466 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3467 GEN_INT (n)), NULL_RTX);
3468 emit_move_insn (base_reg, val);
3469 x = (low_n == 0 ? base_reg
3470 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3472 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3473 x = gen_rtx_PLUS (SImode, xop0, xop1);
3476 /* XXX We don't allow MINUS any more -- see comment in
3477 arm_legitimate_address_p (). */
3478 else if (GET_CODE (x) == MINUS)
3480 rtx xop0 = XEXP (x, 0);
3481 rtx xop1 = XEXP (x, 1);
3483 if (CONSTANT_P (xop0))
3484 xop0 = force_reg (SImode, xop0);
3486 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3487 xop1 = force_reg (SImode, xop1);
3489 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3490 x = gen_rtx_MINUS (SImode, xop0, xop1);
3495 /* We need to find and carefully transform any SYMBOL and LABEL
3496 references; so go back to the original address expression. */
3497 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3499 if (new_x != orig_x)
3507 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3508 to be legitimate. If we find one, return the new, valid address. */
3510 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3512 if (GET_CODE (x) == PLUS
3513 && GET_CODE (XEXP (x, 1)) == CONST_INT
3514 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3515 || INTVAL (XEXP (x, 1)) < 0))
3517 rtx xop0 = XEXP (x, 0);
3518 rtx xop1 = XEXP (x, 1);
3519 HOST_WIDE_INT offset = INTVAL (xop1);
3521 /* Try and fold the offset into a biasing of the base register and
3522 then offsetting that. Don't do this when optimizing for space
3523 since it can cause too many CSEs. */
3524 if (optimize_size && offset >= 0
3525 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3527 HOST_WIDE_INT delta;
3530 delta = offset - (256 - GET_MODE_SIZE (mode));
3531 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3532 delta = 31 * GET_MODE_SIZE (mode);
3534 delta = offset & (~31 * GET_MODE_SIZE (mode));
3536 xop0 = force_operand (plus_constant (xop0, offset - delta),
3538 x = plus_constant (xop0, delta);
3540 else if (offset < 0 && offset > -256)
3541 /* Small negative offsets are best done with a subtract before the
3542 dereference, forcing these into a register normally takes two
3544 x = force_operand (x, NULL_RTX);
3547 /* For the remaining cases, force the constant into a register. */
3548 xop1 = force_reg (SImode, xop1);
3549 x = gen_rtx_PLUS (SImode, xop0, xop1);
3552 else if (GET_CODE (x) == PLUS
3553 && s_register_operand (XEXP (x, 1), SImode)
3554 && !s_register_operand (XEXP (x, 0), SImode))
3556 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3558 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3563 /* We need to find and carefully transform any SYMBOL and LABEL
3564 references; so go back to the original address expression. */
3565 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3567 if (new_x != orig_x)
3576 #define REG_OR_SUBREG_REG(X) \
3577 (GET_CODE (X) == REG \
3578 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3580 #define REG_OR_SUBREG_RTX(X) \
3581 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3583 #ifndef COSTS_N_INSNS
3584 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3587 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3589 enum machine_mode mode = GET_MODE (x);
3602 return COSTS_N_INSNS (1);
3605 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3608 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3615 return COSTS_N_INSNS (2) + cycles;
3617 return COSTS_N_INSNS (1) + 16;
3620 return (COSTS_N_INSNS (1)
3621 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3622 + GET_CODE (SET_DEST (x)) == MEM));
3627 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3629 if (thumb_shiftable_const (INTVAL (x)))
3630 return COSTS_N_INSNS (2);
3631 return COSTS_N_INSNS (3);
3633 else if ((outer == PLUS || outer == COMPARE)
3634 && INTVAL (x) < 256 && INTVAL (x) > -256)
3636 else if (outer == AND
3637 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3638 return COSTS_N_INSNS (1);
3639 else if (outer == ASHIFT || outer == ASHIFTRT
3640 || outer == LSHIFTRT)
3642 return COSTS_N_INSNS (2);
3648 return COSTS_N_INSNS (3);
3666 /* XXX another guess. */
3667 /* Memory costs quite a lot for the first word, but subsequent words
3668 load at the equivalent of a single insn each. */
3669 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3670 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3675 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3680 /* XXX still guessing. */
3681 switch (GET_MODE (XEXP (x, 0)))
3684 return (1 + (mode == DImode ? 4 : 0)
3685 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3688 return (4 + (mode == DImode ? 4 : 0)
3689 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3692 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3704 /* Worker routine for arm_rtx_costs. */
3706 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3708 enum machine_mode mode = GET_MODE (x);
3709 enum rtx_code subcode;
3715 /* Memory costs quite a lot for the first word, but subsequent words
3716 load at the equivalent of a single insn each. */
3717 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3718 + (GET_CODE (x) == SYMBOL_REF
3719 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3725 return optimize_size ? COSTS_N_INSNS (2) : 100;
3728 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3735 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3737 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3738 + ((GET_CODE (XEXP (x, 0)) == REG
3739 || (GET_CODE (XEXP (x, 0)) == SUBREG
3740 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3742 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3743 || (GET_CODE (XEXP (x, 0)) == SUBREG
3744 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3746 + ((GET_CODE (XEXP (x, 1)) == REG
3747 || (GET_CODE (XEXP (x, 1)) == SUBREG
3748 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3749 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3754 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3755 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3756 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3757 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3760 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3761 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3762 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3763 && arm_const_double_rtx (XEXP (x, 1))))
3765 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3766 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3767 && arm_const_double_rtx (XEXP (x, 0))))
3770 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3771 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3772 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3773 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3774 || subcode == ASHIFTRT || subcode == LSHIFTRT
3775 || subcode == ROTATE || subcode == ROTATERT
3777 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3778 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3779 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3780 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3781 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3782 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3783 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3788 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3789 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3790 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3791 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3792 && arm_const_double_rtx (XEXP (x, 1))))
3796 case AND: case XOR: case IOR:
3799 /* Normally the frame registers will be spilt into reg+const during
3800 reload, so it is a bad idea to combine them with other instructions,
3801 since then they might not be moved outside of loops. As a compromise
3802 we allow integration with ops that have a constant as their second
3804 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3805 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3806 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3807 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3808 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3812 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3813 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3814 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3815 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3818 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3819 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3820 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3821 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3822 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3825 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3826 return (1 + extra_cost
3827 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3828 || subcode == LSHIFTRT || subcode == ASHIFTRT
3829 || subcode == ROTATE || subcode == ROTATERT
3831 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3832 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3833 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3834 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3835 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3836 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3842 /* This should have been handled by the CPU specific routines. */
3846 if (arm_arch3m && mode == SImode
3847 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3848 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3849 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3850 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3851 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3852 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3857 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3858 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3862 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3864 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3867 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3875 return 4 + (mode == DImode ? 4 : 0);
3878 if (GET_MODE (XEXP (x, 0)) == QImode)
3879 return (4 + (mode == DImode ? 4 : 0)
3880 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3883 switch (GET_MODE (XEXP (x, 0)))
3886 return (1 + (mode == DImode ? 4 : 0)
3887 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3890 return (4 + (mode == DImode ? 4 : 0)
3891 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3894 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3909 if (const_ok_for_arm (INTVAL (x)))
3910 return outer == SET ? 2 : -1;
3911 else if (outer == AND
3912 && const_ok_for_arm (~INTVAL (x)))
3914 else if ((outer == COMPARE
3915 || outer == PLUS || outer == MINUS)
3916 && const_ok_for_arm (-INTVAL (x)))
3927 if (arm_const_double_rtx (x))
3928 return outer == SET ? 2 : -1;
3929 else if ((outer == COMPARE || outer == PLUS)
3930 && neg_const_double_rtx_ok_for_fpa (x))
3939 /* RTX costs for cores with a slow MUL implementation. */
3942 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3944 enum machine_mode mode = GET_MODE (x);
3948 *total = thumb_rtx_costs (x, code, outer_code);
3955 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3962 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3964 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3965 & (unsigned HOST_WIDE_INT) 0xffffffff);
3966 int cost, const_ok = const_ok_for_arm (i);
3967 int j, booth_unit_size;
3969 /* Tune as appropriate. */
3970 cost = const_ok ? 4 : 8;
3971 booth_unit_size = 2;
3972 for (j = 0; i && j < 32; j += booth_unit_size)
3974 i >>= booth_unit_size;
3982 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3983 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3987 *total = arm_rtx_costs_1 (x, code, outer_code);
3993 /* RTX cost for cores with a fast multiply unit (M variants). */
3996 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3998 enum machine_mode mode = GET_MODE (x);
4002 *total = thumb_rtx_costs (x, code, outer_code);
4009 /* There is no point basing this on the tuning, since it is always the
4010 fast variant if it exists at all. */
4012 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4013 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4014 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4021 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4028 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4030 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4031 & (unsigned HOST_WIDE_INT) 0xffffffff);
4032 int cost, const_ok = const_ok_for_arm (i);
4033 int j, booth_unit_size;
4035 /* Tune as appropriate. */
4036 cost = const_ok ? 4 : 8;
4037 booth_unit_size = 8;
4038 for (j = 0; i && j < 32; j += booth_unit_size)
4040 i >>= booth_unit_size;
4048 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4049 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4053 *total = arm_rtx_costs_1 (x, code, outer_code);
4059 /* RTX cost for XScale CPUs. */
4062 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4064 enum machine_mode mode = GET_MODE (x);
4068 *total = thumb_rtx_costs (x, code, outer_code);
4075 /* There is no point basing this on the tuning, since it is always the
4076 fast variant if it exists at all. */
4078 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4079 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4080 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4087 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4094 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4096 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4097 & (unsigned HOST_WIDE_INT) 0xffffffff);
4098 int cost, const_ok = const_ok_for_arm (i);
4099 unsigned HOST_WIDE_INT masked_const;
4101 /* The cost will be related to two insns.
4102 First a load of the constant (MOV or LDR), then a multiply. */
4105 cost += 1; /* LDR is probably more expensive because
4106 of longer result latency. */
4107 masked_const = i & 0xffff8000;
4108 if (masked_const != 0 && masked_const != 0xffff8000)
4110 masked_const = i & 0xf8000000;
4111 if (masked_const == 0 || masked_const == 0xf8000000)
4120 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4121 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4125 *total = arm_rtx_costs_1 (x, code, outer_code);
4131 /* RTX costs for 9e (and later) cores. */
4134 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4136 enum machine_mode mode = GET_MODE (x);
4145 *total = COSTS_N_INSNS (3);
4149 *total = thumb_rtx_costs (x, code, outer_code);
4157 /* There is no point basing this on the tuning, since it is always the
4158 fast variant if it exists at all. */
4160 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4161 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4162 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4169 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4186 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4187 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4191 *total = arm_rtx_costs_1 (x, code, outer_code);
4195 /* All address computations that can be done are free, but rtx cost returns
4196 the same for practically all of them. So we weight the different types
4197 of address here in the order (most pref first):
4198 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4200 arm_arm_address_cost (rtx x)
4202 enum rtx_code c = GET_CODE (x);
4204 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4206 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4209 if (c == PLUS || c == MINUS)
4211 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4214 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4224 arm_thumb_address_cost (rtx x)
4226 enum rtx_code c = GET_CODE (x);
4231 && GET_CODE (XEXP (x, 0)) == REG
4232 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4239 arm_address_cost (rtx x)
4241 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4245 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4249 /* Some true dependencies can have a higher cost depending
4250 on precisely how certain input operands are used. */
4252 && REG_NOTE_KIND (link) == 0
4253 && recog_memoized (insn) >= 0
4254 && recog_memoized (dep) >= 0)
4256 int shift_opnum = get_attr_shift (insn);
4257 enum attr_type attr_type = get_attr_type (dep);
4259 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4260 operand for INSN. If we have a shifted input operand and the
4261 instruction we depend on is another ALU instruction, then we may
4262 have to account for an additional stall. */
4263 if (shift_opnum != 0
4264 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4266 rtx shifted_operand;
4269 /* Get the shifted operand. */
4270 extract_insn (insn);
4271 shifted_operand = recog_data.operand[shift_opnum];
4273 /* Iterate over all the operands in DEP. If we write an operand
4274 that overlaps with SHIFTED_OPERAND, then we have increase the
4275 cost of this dependency. */
4277 preprocess_constraints ();
4278 for (opno = 0; opno < recog_data.n_operands; opno++)
4280 /* We can ignore strict inputs. */
4281 if (recog_data.operand_type[opno] == OP_IN)
4284 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4291 /* XXX This is not strictly true for the FPA. */
4292 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4293 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4296 /* Call insns don't incur a stall, even if they follow a load. */
4297 if (REG_NOTE_KIND (link) == 0
4298 && GET_CODE (insn) == CALL_INSN)
4301 if ((i_pat = single_set (insn)) != NULL
4302 && GET_CODE (SET_SRC (i_pat)) == MEM
4303 && (d_pat = single_set (dep)) != NULL
4304 && GET_CODE (SET_DEST (d_pat)) == MEM)
4306 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4307 /* This is a load after a store, there is no conflict if the load reads
4308 from a cached area. Assume that loads from the stack, and from the
4309 constant pool are cached, and that others will miss. This is a
4312 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4313 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4314 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4315 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4322 static int fp_consts_inited = 0;
4324 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4325 static const char * const strings_fp[8] =
4328 "4", "5", "0.5", "10"
4331 static REAL_VALUE_TYPE values_fp[8];
4334 init_fp_table (void)
4340 fp_consts_inited = 1;
4342 fp_consts_inited = 8;
4344 for (i = 0; i < fp_consts_inited; i++)
4346 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4351 /* Return TRUE if rtx X is a valid immediate FP constant. */
4353 arm_const_double_rtx (rtx x)
4358 if (!fp_consts_inited)
4361 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4362 if (REAL_VALUE_MINUS_ZERO (r))
4365 for (i = 0; i < fp_consts_inited; i++)
4366 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4372 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4374 neg_const_double_rtx_ok_for_fpa (rtx x)
4379 if (!fp_consts_inited)
4382 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4383 r = REAL_VALUE_NEGATE (r);
4384 if (REAL_VALUE_MINUS_ZERO (r))
4387 for (i = 0; i < 8; i++)
4388 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4394 /* Predicates for `match_operand' and `match_operator'. */
4396 /* s_register_operand is the same as register_operand, but it doesn't accept
4399 This function exists because at the time it was put in it led to better
4400 code. SUBREG(MEM) always needs a reload in the places where
4401 s_register_operand is used, and this seemed to lead to excessive
4404 s_register_operand (rtx op, enum machine_mode mode)
4406 if (GET_MODE (op) != mode && mode != VOIDmode)
4409 if (GET_CODE (op) == SUBREG)
4410 op = SUBREG_REG (op);
4412 /* We don't consider registers whose class is NO_REGS
4413 to be a register operand. */
4414 /* XXX might have to check for lo regs only for thumb ??? */
4415 return (GET_CODE (op) == REG
4416 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4417 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4420 /* A hard register operand (even before reload. */
4422 arm_hard_register_operand (rtx op, enum machine_mode mode)
4424 if (GET_MODE (op) != mode && mode != VOIDmode)
4427 return (GET_CODE (op) == REG
4428 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4431 /* An arm register operand. */
4433 arm_general_register_operand (rtx op, enum machine_mode mode)
4435 if (GET_MODE (op) != mode && mode != VOIDmode)
4438 if (GET_CODE (op) == SUBREG)
4439 op = SUBREG_REG (op);
4441 return (GET_CODE (op) == REG
4442 && (REGNO (op) <= LAST_ARM_REGNUM
4443 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4446 /* Only accept reg, subreg(reg), const_int. */
4448 reg_or_int_operand (rtx op, enum machine_mode mode)
4450 if (GET_CODE (op) == CONST_INT)
4453 if (GET_MODE (op) != mode && mode != VOIDmode)
4456 if (GET_CODE (op) == SUBREG)
4457 op = SUBREG_REG (op);
4459 /* We don't consider registers whose class is NO_REGS
4460 to be a register operand. */
4461 return (GET_CODE (op) == REG
4462 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4463 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4466 /* Return 1 if OP is an item in memory, given that we are in reload. */
4468 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4470 int regno = true_regnum (op);
4472 return (!CONSTANT_P (op)
4474 || (GET_CODE (op) == REG
4475 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4478 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4480 arm_rhs_operand (rtx op, enum machine_mode mode)
4482 return (s_register_operand (op, mode)
4483 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4486 /* Return TRUE for valid operands for the
4487 rhs of an ARM instruction, or a load. */
4489 arm_rhsm_operand (rtx op, enum machine_mode mode)
4491 return (s_register_operand (op, mode)
4492 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4493 || memory_operand (op, mode));
4496 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4497 constant that is valid when negated. */
4499 arm_add_operand (rtx op, enum machine_mode mode)
4502 return thumb_cmp_operand (op, mode);
4504 return (s_register_operand (op, mode)
4505 || (GET_CODE (op) == CONST_INT
4506 && (const_ok_for_arm (INTVAL (op))
4507 || const_ok_for_arm (-INTVAL (op)))));
4510 /* Return TRUE for valid ARM constants (or when valid if negated). */
4512 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4514 return (GET_CODE (op) == CONST_INT
4515 && (const_ok_for_arm (INTVAL (op))
4516 || const_ok_for_arm (-INTVAL (op))));
4520 arm_not_operand (rtx op, enum machine_mode mode)
4522 return (s_register_operand (op, mode)
4523 || (GET_CODE (op) == CONST_INT
4524 && (const_ok_for_arm (INTVAL (op))
4525 || const_ok_for_arm (~INTVAL (op)))));
4528 /* Return TRUE if the operand is a memory reference which contains an
4529 offsettable address. */
4531 offsettable_memory_operand (rtx op, enum machine_mode mode)
4533 if (mode == VOIDmode)
4534 mode = GET_MODE (op);
4536 return (mode == GET_MODE (op)
4537 && GET_CODE (op) == MEM
4538 && offsettable_address_p (reload_completed | reload_in_progress,
4539 mode, XEXP (op, 0)));
4542 /* Return TRUE if the operand is a memory reference which is, or can be
4543 made word aligned by adjusting the offset. */
4545 alignable_memory_operand (rtx op, enum machine_mode mode)
4549 if (mode == VOIDmode)
4550 mode = GET_MODE (op);
4552 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4557 return ((GET_CODE (reg = op) == REG
4558 || (GET_CODE (op) == SUBREG
4559 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4560 || (GET_CODE (op) == PLUS
4561 && GET_CODE (XEXP (op, 1)) == CONST_INT
4562 && (GET_CODE (reg = XEXP (op, 0)) == REG
4563 || (GET_CODE (XEXP (op, 0)) == SUBREG
4564 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4565 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4568 /* Similar to s_register_operand, but does not allow hard integer
4571 f_register_operand (rtx op, enum machine_mode mode)
4573 if (GET_MODE (op) != mode && mode != VOIDmode)
4576 if (GET_CODE (op) == SUBREG)
4577 op = SUBREG_REG (op);
4579 /* We don't consider registers whose class is NO_REGS
4580 to be a register operand. */
4581 return (GET_CODE (op) == REG
4582 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4583 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4586 /* Return TRUE for valid operands for the rhs of an floating point insns.
4587 Allows regs or certain consts on FPA, just regs for everything else. */
4589 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4591 if (s_register_operand (op, mode))
4594 if (GET_MODE (op) != mode && mode != VOIDmode)
4597 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4598 return arm_const_double_rtx (op);
4604 arm_float_add_operand (rtx op, enum machine_mode mode)
4606 if (s_register_operand (op, mode))
4609 if (GET_MODE (op) != mode && mode != VOIDmode)
4612 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4613 return (arm_const_double_rtx (op)
4614 || neg_const_double_rtx_ok_for_fpa (op));
4620 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4621 Depends which fpu we are targeting. */
4624 arm_float_compare_operand (rtx op, enum machine_mode mode)
4627 return vfp_compare_operand (op, mode);
4629 return arm_float_rhs_operand (op, mode);
4633 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4635 cirrus_memory_offset (rtx op)
4637 /* Reject eliminable registers. */
4638 if (! (reload_in_progress || reload_completed)
4639 && ( reg_mentioned_p (frame_pointer_rtx, op)
4640 || reg_mentioned_p (arg_pointer_rtx, op)
4641 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4642 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4643 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4644 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4647 if (GET_CODE (op) == MEM)
4653 /* Match: (mem (reg)). */
4654 if (GET_CODE (ind) == REG)
4660 if (GET_CODE (ind) == PLUS
4661 && GET_CODE (XEXP (ind, 0)) == REG
4662 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4663 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4671 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4673 if (!memory_operand (op, mode))
4676 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4679 /* Return nonzero if OP is a Cirrus or general register. */
4681 cirrus_register_operand (rtx op, enum machine_mode mode)
4683 if (GET_MODE (op) != mode && mode != VOIDmode)
4686 if (GET_CODE (op) == SUBREG)
4687 op = SUBREG_REG (op);
4689 return (GET_CODE (op) == REG
4690 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4691 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4694 /* Return nonzero if OP is a cirrus FP register. */
4696 cirrus_fp_register (rtx op, enum machine_mode mode)
4698 if (GET_MODE (op) != mode && mode != VOIDmode)
4701 if (GET_CODE (op) == SUBREG)
4702 op = SUBREG_REG (op);
4704 return (GET_CODE (op) == REG
4705 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4706 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4709 /* Return nonzero if OP is a 6bit constant (0..63). */
4711 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4713 return (GET_CODE (op) == CONST_INT
4715 && INTVAL (op) < 64);
4719 /* Return TRUE if OP is a valid VFP memory address pattern.
4720 WB if true if writeback address modes are allowed. */
4723 arm_coproc_mem_operand (rtx op, bool wb)
4727 /* Reject eliminable registers. */
4728 if (! (reload_in_progress || reload_completed)
4729 && ( reg_mentioned_p (frame_pointer_rtx, op)
4730 || reg_mentioned_p (arg_pointer_rtx, op)
4731 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4732 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4733 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4734 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4737 /* Constants are converted into offsets from labels. */
4738 if (GET_CODE (op) != MEM)
4743 if (reload_completed
4744 && (GET_CODE (ind) == LABEL_REF
4745 || (GET_CODE (ind) == CONST
4746 && GET_CODE (XEXP (ind, 0)) == PLUS
4747 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4748 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4751 /* Match: (mem (reg)). */
4752 if (GET_CODE (ind) == REG)
4753 return arm_address_register_rtx_p (ind, 0);
4755 /* Autoincremment addressing modes. */
4757 && (GET_CODE (ind) == PRE_INC
4758 || GET_CODE (ind) == POST_INC
4759 || GET_CODE (ind) == PRE_DEC
4760 || GET_CODE (ind) == POST_DEC))
4761 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4764 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4765 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4766 && GET_CODE (XEXP (ind, 1)) == PLUS
4767 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4768 ind = XEXP (ind, 1);
4773 if (GET_CODE (ind) == PLUS
4774 && GET_CODE (XEXP (ind, 0)) == REG
4775 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4776 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4777 && INTVAL (XEXP (ind, 1)) > -1024
4778 && INTVAL (XEXP (ind, 1)) < 1024
4779 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
4786 /* Return TRUE if OP is a REG or constant zero. */
4788 vfp_compare_operand (rtx op, enum machine_mode mode)
4790 if (s_register_operand (op, mode))
4793 return (GET_CODE (op) == CONST_DOUBLE
4794 && arm_const_double_rtx (op));
4798 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4799 VFP registers. Otherwise return NO_REGS. */
4802 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4804 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
4807 return GENERAL_REGS;
4811 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4812 Use by the Cirrus Maverick code which has to workaround
4813 a hardware bug triggered by such instructions. */
4815 arm_memory_load_p (rtx insn)
4817 rtx body, lhs, rhs;;
4819 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4822 body = PATTERN (insn);
4824 if (GET_CODE (body) != SET)
4827 lhs = XEXP (body, 0);
4828 rhs = XEXP (body, 1);
4830 lhs = REG_OR_SUBREG_RTX (lhs);
4832 /* If the destination is not a general purpose
4833 register we do not have to worry. */
4834 if (GET_CODE (lhs) != REG
4835 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4838 /* As well as loads from memory we also have to react
4839 to loads of invalid constants which will be turned
4840 into loads from the minipool. */
4841 return (GET_CODE (rhs) == MEM
4842 || GET_CODE (rhs) == SYMBOL_REF
4843 || note_invalid_constants (insn, -1, false));
4846 /* Return TRUE if INSN is a Cirrus instruction. */
4848 arm_cirrus_insn_p (rtx insn)
4850 enum attr_cirrus attr;
4852 /* get_attr aborts on USE and CLOBBER. */
4854 || GET_CODE (insn) != INSN
4855 || GET_CODE (PATTERN (insn)) == USE
4856 || GET_CODE (PATTERN (insn)) == CLOBBER)
4859 attr = get_attr_cirrus (insn);
4861 return attr != CIRRUS_NOT;
4864 /* Cirrus reorg for invalid instruction combinations. */
4866 cirrus_reorg (rtx first)
4868 enum attr_cirrus attr;
4869 rtx body = PATTERN (first);
4873 /* Any branch must be followed by 2 non Cirrus instructions. */
4874 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4877 t = next_nonnote_insn (first);
4879 if (arm_cirrus_insn_p (t))
4882 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4886 emit_insn_after (gen_nop (), first);
4891 /* (float (blah)) is in parallel with a clobber. */
4892 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4893 body = XVECEXP (body, 0, 0);
4895 if (GET_CODE (body) == SET)
4897 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4899 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4900 be followed by a non Cirrus insn. */
4901 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4903 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4904 emit_insn_after (gen_nop (), first);
4908 else if (arm_memory_load_p (first))
4910 unsigned int arm_regno;
4912 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4913 ldr/cfmv64hr combination where the Rd field is the same
4914 in both instructions must be split with a non Cirrus
4921 /* Get Arm register number for ldr insn. */
4922 if (GET_CODE (lhs) == REG)
4923 arm_regno = REGNO (lhs);
4924 else if (GET_CODE (rhs) == REG)
4925 arm_regno = REGNO (rhs);
4930 first = next_nonnote_insn (first);
4932 if (! arm_cirrus_insn_p (first))
4935 body = PATTERN (first);
4937 /* (float (blah)) is in parallel with a clobber. */
4938 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4939 body = XVECEXP (body, 0, 0);
4941 if (GET_CODE (body) == FLOAT)
4942 body = XEXP (body, 0);
4944 if (get_attr_cirrus (first) == CIRRUS_MOVE
4945 && GET_CODE (XEXP (body, 1)) == REG
4946 && arm_regno == REGNO (XEXP (body, 1)))
4947 emit_insn_after (gen_nop (), first);
4953 /* get_attr aborts on USE and CLOBBER. */
4955 || GET_CODE (first) != INSN
4956 || GET_CODE (PATTERN (first)) == USE
4957 || GET_CODE (PATTERN (first)) == CLOBBER)
4960 attr = get_attr_cirrus (first);
4962 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4963 must be followed by a non-coprocessor instruction. */
4964 if (attr == CIRRUS_COMPARE)
4968 t = next_nonnote_insn (first);
4970 if (arm_cirrus_insn_p (t))
4973 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4977 emit_insn_after (gen_nop (), first);
4983 /* Return nonzero if OP is a constant power of two. */
4985 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4987 if (GET_CODE (op) == CONST_INT)
4989 HOST_WIDE_INT value = INTVAL (op);
4991 return value != 0 && (value & (value - 1)) == 0;
4997 /* Return TRUE for a valid operand of a DImode operation.
4998 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4999 Note that this disallows MEM(REG+REG), but allows
5000 MEM(PRE/POST_INC/DEC(REG)). */
5002 di_operand (rtx op, enum machine_mode mode)
5004 if (s_register_operand (op, mode))
5007 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
5010 if (GET_CODE (op) == SUBREG)
5011 op = SUBREG_REG (op);
5013 switch (GET_CODE (op))
5020 return memory_address_p (DImode, XEXP (op, 0));
5027 /* Like di_operand, but don't accept constants. */
5029 nonimmediate_di_operand (rtx op, enum machine_mode mode)
5031 if (s_register_operand (op, mode))
5034 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
5037 if (GET_CODE (op) == SUBREG)
5038 op = SUBREG_REG (op);
5040 if (GET_CODE (op) == MEM)
5041 return memory_address_p (DImode, XEXP (op, 0));
5046 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
5047 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5048 Note that this disallows MEM(REG+REG), but allows
5049 MEM(PRE/POST_INC/DEC(REG)). */
5051 soft_df_operand (rtx op, enum machine_mode mode)
5053 if (s_register_operand (op, mode))
5056 if (mode != VOIDmode && GET_MODE (op) != mode)
5059 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
5062 if (GET_CODE (op) == SUBREG)
5063 op = SUBREG_REG (op);
5065 switch (GET_CODE (op))
5071 return memory_address_p (DFmode, XEXP (op, 0));
5078 /* Like soft_df_operand, but don't accept constants. */
5080 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
5082 if (s_register_operand (op, mode))
5085 if (mode != VOIDmode && GET_MODE (op) != mode)
5088 if (GET_CODE (op) == SUBREG)
5089 op = SUBREG_REG (op);
5091 if (GET_CODE (op) == MEM)
5092 return memory_address_p (DFmode, XEXP (op, 0));
5096 /* Return TRUE for valid index operands. */
5098 index_operand (rtx op, enum machine_mode mode)
5100 return (s_register_operand (op, mode)
5101 || (immediate_operand (op, mode)
5102 && (GET_CODE (op) != CONST_INT
5103 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
5106 /* Return TRUE for valid shifts by a constant. This also accepts any
5107 power of two on the (somewhat overly relaxed) assumption that the
5108 shift operator in this case was a mult. */
5110 const_shift_operand (rtx op, enum machine_mode mode)
5112 return (power_of_two_operand (op, mode)
5113 || (immediate_operand (op, mode)
5114 && (GET_CODE (op) != CONST_INT
5115 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5118 /* Return TRUE for arithmetic operators which can be combined with a multiply
5121 shiftable_operator (rtx x, enum machine_mode mode)
5125 if (GET_MODE (x) != mode)
5128 code = GET_CODE (x);
5130 return (code == PLUS || code == MINUS
5131 || code == IOR || code == XOR || code == AND);
5134 /* Return TRUE for binary logical operators. */
5136 logical_binary_operator (rtx x, enum machine_mode mode)
5140 if (GET_MODE (x) != mode)
5143 code = GET_CODE (x);
5145 return (code == IOR || code == XOR || code == AND);
5148 /* Return TRUE for shift operators. */
5150 shift_operator (rtx x,enum machine_mode mode)
5154 if (GET_MODE (x) != mode)
5157 code = GET_CODE (x);
5160 return power_of_two_operand (XEXP (x, 1), mode);
5162 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5163 || code == ROTATERT);
5166 /* Return TRUE if x is EQ or NE. */
5168 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5170 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5173 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5175 arm_comparison_operator (rtx x, enum machine_mode mode)
5177 return (comparison_operator (x, mode)
5178 && GET_CODE (x) != LTGT
5179 && GET_CODE (x) != UNEQ);
5182 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5184 minmax_operator (rtx x, enum machine_mode mode)
5186 enum rtx_code code = GET_CODE (x);
5188 if (GET_MODE (x) != mode)
5191 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5194 /* Return TRUE if this is the condition code register, if we aren't given
5195 a mode, accept any class CCmode register. */
5197 cc_register (rtx x, enum machine_mode mode)
5199 if (mode == VOIDmode)
5201 mode = GET_MODE (x);
5203 if (GET_MODE_CLASS (mode) != MODE_CC)
5207 if ( GET_MODE (x) == mode
5208 && GET_CODE (x) == REG
5209 && REGNO (x) == CC_REGNUM)
5215 /* Return TRUE if this is the condition code register, if we aren't given
5216 a mode, accept any class CCmode register which indicates a dominance
5219 dominant_cc_register (rtx x, enum machine_mode mode)
5221 if (mode == VOIDmode)
5223 mode = GET_MODE (x);
5225 if (GET_MODE_CLASS (mode) != MODE_CC)
5229 if (mode != CC_DNEmode && mode != CC_DEQmode
5230 && mode != CC_DLEmode && mode != CC_DLTmode
5231 && mode != CC_DGEmode && mode != CC_DGTmode
5232 && mode != CC_DLEUmode && mode != CC_DLTUmode
5233 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5236 return cc_register (x, mode);
5239 /* Return TRUE if X references a SYMBOL_REF. */
5241 symbol_mentioned_p (rtx x)
5246 if (GET_CODE (x) == SYMBOL_REF)
5249 fmt = GET_RTX_FORMAT (GET_CODE (x));
5251 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5257 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5258 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5261 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5268 /* Return TRUE if X references a LABEL_REF. */
5270 label_mentioned_p (rtx x)
5275 if (GET_CODE (x) == LABEL_REF)
5278 fmt = GET_RTX_FORMAT (GET_CODE (x));
5279 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5285 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5286 if (label_mentioned_p (XVECEXP (x, i, j)))
5289 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5299 enum rtx_code code = GET_CODE (x);
5303 else if (code == SMIN)
5305 else if (code == UMIN)
5307 else if (code == UMAX)
5313 /* Return 1 if memory locations are adjacent. */
5315 adjacent_mem_locations (rtx a, rtx b)
5317 if ((GET_CODE (XEXP (a, 0)) == REG
5318 || (GET_CODE (XEXP (a, 0)) == PLUS
5319 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5320 && (GET_CODE (XEXP (b, 0)) == REG
5321 || (GET_CODE (XEXP (b, 0)) == PLUS
5322 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5324 int val0 = 0, val1 = 0;
5327 if (GET_CODE (XEXP (a, 0)) == PLUS)
5329 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5330 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5333 reg0 = REGNO (XEXP (a, 0));
5335 if (GET_CODE (XEXP (b, 0)) == PLUS)
5337 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5338 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5341 reg1 = REGNO (XEXP (b, 0));
5343 /* Don't accept any offset that will require multiple
5344 instructions to handle, since this would cause the
5345 arith_adjacentmem pattern to output an overlong sequence. */
5346 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5349 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5354 /* Return 1 if OP is a load multiple operation. It is known to be
5355 parallel and the first section will be tested. */
5357 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5359 HOST_WIDE_INT count = XVECLEN (op, 0);
5362 HOST_WIDE_INT i = 1, base = 0;
5366 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5369 /* Check to see if this might be a write-back. */
5370 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5375 /* Now check it more carefully. */
5376 if (GET_CODE (SET_DEST (elt)) != REG
5377 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5378 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5379 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5383 /* Perform a quick check so we don't blow up below. */
5385 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5386 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5387 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5390 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5391 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5393 for (; i < count; i++)
5395 elt = XVECEXP (op, 0, i);
5397 if (GET_CODE (elt) != SET
5398 || GET_CODE (SET_DEST (elt)) != REG
5399 || GET_MODE (SET_DEST (elt)) != SImode
5400 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5401 || GET_CODE (SET_SRC (elt)) != MEM
5402 || GET_MODE (SET_SRC (elt)) != SImode
5403 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5404 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5405 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5406 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5413 /* Return 1 if OP is a store multiple operation. It is known to be
5414 parallel and the first section will be tested. */
5416 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5418 HOST_WIDE_INT count = XVECLEN (op, 0);
5421 HOST_WIDE_INT i = 1, base = 0;
5425 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5428 /* Check to see if this might be a write-back. */
5429 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5434 /* Now check it more carefully. */
5435 if (GET_CODE (SET_DEST (elt)) != REG
5436 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5437 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5438 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5442 /* Perform a quick check so we don't blow up below. */
5444 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5445 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5446 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5449 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5450 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5452 for (; i < count; i++)
5454 elt = XVECEXP (op, 0, i);
5456 if (GET_CODE (elt) != SET
5457 || GET_CODE (SET_SRC (elt)) != REG
5458 || GET_MODE (SET_SRC (elt)) != SImode
5459 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5460 || GET_CODE (SET_DEST (elt)) != MEM
5461 || GET_MODE (SET_DEST (elt)) != SImode
5462 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5463 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5464 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5465 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5473 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5474 HOST_WIDE_INT *load_offset)
5476 int unsorted_regs[4];
5477 HOST_WIDE_INT unsorted_offsets[4];
5482 /* Can only handle 2, 3, or 4 insns at present,
5483 though could be easily extended if required. */
5484 if (nops < 2 || nops > 4)
5487 /* Loop over the operands and check that the memory references are
5488 suitable (ie immediate offsets from the same base register). At
5489 the same time, extract the target register, and the memory
5491 for (i = 0; i < nops; i++)
5496 /* Convert a subreg of a mem into the mem itself. */
5497 if (GET_CODE (operands[nops + i]) == SUBREG)
5498 operands[nops + i] = alter_subreg (operands + (nops + i));
5500 if (GET_CODE (operands[nops + i]) != MEM)
5503 /* Don't reorder volatile memory references; it doesn't seem worth
5504 looking for the case where the order is ok anyway. */
5505 if (MEM_VOLATILE_P (operands[nops + i]))
5508 offset = const0_rtx;
5510 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5511 || (GET_CODE (reg) == SUBREG
5512 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5513 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5514 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5516 || (GET_CODE (reg) == SUBREG
5517 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5518 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5523 base_reg = REGNO (reg);
5524 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5525 ? REGNO (operands[i])
5526 : REGNO (SUBREG_REG (operands[i])));
5531 if (base_reg != (int) REGNO (reg))
5532 /* Not addressed from the same base register. */
5535 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5536 ? REGNO (operands[i])
5537 : REGNO (SUBREG_REG (operands[i])));
5538 if (unsorted_regs[i] < unsorted_regs[order[0]])
5542 /* If it isn't an integer register, or if it overwrites the
5543 base register but isn't the last insn in the list, then
5544 we can't do this. */
5545 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5546 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5549 unsorted_offsets[i] = INTVAL (offset);
5552 /* Not a suitable memory address. */
5556 /* All the useful information has now been extracted from the
5557 operands into unsorted_regs and unsorted_offsets; additionally,
5558 order[0] has been set to the lowest numbered register in the
5559 list. Sort the registers into order, and check that the memory
5560 offsets are ascending and adjacent. */
5562 for (i = 1; i < nops; i++)
5566 order[i] = order[i - 1];
5567 for (j = 0; j < nops; j++)
5568 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5569 && (order[i] == order[i - 1]
5570 || unsorted_regs[j] < unsorted_regs[order[i]]))
5573 /* Have we found a suitable register? if not, one must be used more
5575 if (order[i] == order[i - 1])
5578 /* Is the memory address adjacent and ascending? */
5579 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5587 for (i = 0; i < nops; i++)
5588 regs[i] = unsorted_regs[order[i]];
5590 *load_offset = unsorted_offsets[order[0]];
5593 if (unsorted_offsets[order[0]] == 0)
5594 return 1; /* ldmia */
5596 if (unsorted_offsets[order[0]] == 4)
5597 return 2; /* ldmib */
5599 if (unsorted_offsets[order[nops - 1]] == 0)
5600 return 3; /* ldmda */
5602 if (unsorted_offsets[order[nops - 1]] == -4)
5603 return 4; /* ldmdb */
5605 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5606 if the offset isn't small enough. The reason 2 ldrs are faster
5607 is because these ARMs are able to do more than one cache access
5608 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5609 whilst the ARM8 has a double bandwidth cache. This means that
5610 these cores can do both an instruction fetch and a data fetch in
5611 a single cycle, so the trick of calculating the address into a
5612 scratch register (one of the result regs) and then doing a load
5613 multiple actually becomes slower (and no smaller in code size).
5614 That is the transformation
5616 ldr rd1, [rbase + offset]
5617 ldr rd2, [rbase + offset + 4]
5621 add rd1, rbase, offset
5622 ldmia rd1, {rd1, rd2}
5624 produces worse code -- '3 cycles + any stalls on rd2' instead of
5625 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5626 access per cycle, the first sequence could never complete in less
5627 than 6 cycles, whereas the ldm sequence would only take 5 and
5628 would make better use of sequential accesses if not hitting the
5631 We cheat here and test 'arm_ld_sched' which we currently know to
5632 only be true for the ARM8, ARM9 and StrongARM. If this ever
5633 changes, then the test below needs to be reworked. */
5634 if (nops == 2 && arm_ld_sched)
5637 /* Can't do it without setting up the offset, only do this if it takes
5638 no more than one insn. */
5639 return (const_ok_for_arm (unsorted_offsets[order[0]])
5640 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5644 emit_ldm_seq (rtx *operands, int nops)
5648 HOST_WIDE_INT offset;
5652 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5655 strcpy (buf, "ldm%?ia\t");
5659 strcpy (buf, "ldm%?ib\t");
5663 strcpy (buf, "ldm%?da\t");
5667 strcpy (buf, "ldm%?db\t");
5672 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5673 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5676 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5677 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5679 output_asm_insn (buf, operands);
5681 strcpy (buf, "ldm%?ia\t");
5688 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5689 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5691 for (i = 1; i < nops; i++)
5692 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5693 reg_names[regs[i]]);
5695 strcat (buf, "}\t%@ phole ldm");
5697 output_asm_insn (buf, operands);
5702 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5703 HOST_WIDE_INT * load_offset)
5705 int unsorted_regs[4];
5706 HOST_WIDE_INT unsorted_offsets[4];
5711 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5712 extended if required. */
5713 if (nops < 2 || nops > 4)
5716 /* Loop over the operands and check that the memory references are
5717 suitable (ie immediate offsets from the same base register). At
5718 the same time, extract the target register, and the memory
5720 for (i = 0; i < nops; i++)
5725 /* Convert a subreg of a mem into the mem itself. */
5726 if (GET_CODE (operands[nops + i]) == SUBREG)
5727 operands[nops + i] = alter_subreg (operands + (nops + i));
5729 if (GET_CODE (operands[nops + i]) != MEM)
5732 /* Don't reorder volatile memory references; it doesn't seem worth
5733 looking for the case where the order is ok anyway. */
5734 if (MEM_VOLATILE_P (operands[nops + i]))
5737 offset = const0_rtx;
5739 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5740 || (GET_CODE (reg) == SUBREG
5741 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5742 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5743 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5745 || (GET_CODE (reg) == SUBREG
5746 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5747 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5752 base_reg = REGNO (reg);
5753 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5754 ? REGNO (operands[i])
5755 : REGNO (SUBREG_REG (operands[i])));
5760 if (base_reg != (int) REGNO (reg))
5761 /* Not addressed from the same base register. */
5764 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5765 ? REGNO (operands[i])
5766 : REGNO (SUBREG_REG (operands[i])));
5767 if (unsorted_regs[i] < unsorted_regs[order[0]])
5771 /* If it isn't an integer register, then we can't do this. */
5772 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5775 unsorted_offsets[i] = INTVAL (offset);
5778 /* Not a suitable memory address. */
5782 /* All the useful information has now been extracted from the
5783 operands into unsorted_regs and unsorted_offsets; additionally,
5784 order[0] has been set to the lowest numbered register in the
5785 list. Sort the registers into order, and check that the memory
5786 offsets are ascending and adjacent. */
5788 for (i = 1; i < nops; i++)
5792 order[i] = order[i - 1];
5793 for (j = 0; j < nops; j++)
5794 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5795 && (order[i] == order[i - 1]
5796 || unsorted_regs[j] < unsorted_regs[order[i]]))
5799 /* Have we found a suitable register? if not, one must be used more
5801 if (order[i] == order[i - 1])
5804 /* Is the memory address adjacent and ascending? */
5805 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5813 for (i = 0; i < nops; i++)
5814 regs[i] = unsorted_regs[order[i]];
5816 *load_offset = unsorted_offsets[order[0]];
5819 if (unsorted_offsets[order[0]] == 0)
5820 return 1; /* stmia */
5822 if (unsorted_offsets[order[0]] == 4)
5823 return 2; /* stmib */
5825 if (unsorted_offsets[order[nops - 1]] == 0)
5826 return 3; /* stmda */
5828 if (unsorted_offsets[order[nops - 1]] == -4)
5829 return 4; /* stmdb */
5835 emit_stm_seq (rtx *operands, int nops)
5839 HOST_WIDE_INT offset;
5843 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5846 strcpy (buf, "stm%?ia\t");
5850 strcpy (buf, "stm%?ib\t");
5854 strcpy (buf, "stm%?da\t");
5858 strcpy (buf, "stm%?db\t");
5865 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5866 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5868 for (i = 1; i < nops; i++)
5869 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5870 reg_names[regs[i]]);
5872 strcat (buf, "}\t%@ phole stm");
5874 output_asm_insn (buf, operands);
5879 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5881 if (GET_CODE (op) != PARALLEL
5882 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5883 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5884 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5890 /* Routines for use in generating RTL. */
5893 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5894 int write_back, int unchanging_p, int in_struct_p,
5899 int sign = up ? 1 : -1;
5902 /* XScale has load-store double instructions, but they have stricter
5903 alignment requirements than load-store multiple, so we can not
5906 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5907 the pipeline until completion.
5915 An ldr instruction takes 1-3 cycles, but does not block the
5924 Best case ldr will always win. However, the more ldr instructions
5925 we issue, the less likely we are to be able to schedule them well.
5926 Using ldr instructions also increases code size.
5928 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5929 for counts of 3 or 4 regs. */
5930 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5936 for (i = 0; i < count; i++)
5938 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5939 RTX_UNCHANGING_P (mem) = unchanging_p;
5940 MEM_IN_STRUCT_P (mem) = in_struct_p;
5941 MEM_SCALAR_P (mem) = scalar_p;
5942 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5946 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5954 result = gen_rtx_PARALLEL (VOIDmode,
5955 rtvec_alloc (count + (write_back ? 1 : 0)));
5958 XVECEXP (result, 0, 0)
5959 = gen_rtx_SET (GET_MODE (from), from,
5960 plus_constant (from, count * 4 * sign));
5965 for (j = 0; i < count; i++, j++)
5967 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5968 RTX_UNCHANGING_P (mem) = unchanging_p;
5969 MEM_IN_STRUCT_P (mem) = in_struct_p;
5970 MEM_SCALAR_P (mem) = scalar_p;
5971 XVECEXP (result, 0, i)
5972 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5979 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5980 int write_back, int unchanging_p, int in_struct_p,
5985 int sign = up ? 1 : -1;
5988 /* See arm_gen_load_multiple for discussion of
5989 the pros/cons of ldm/stm usage for XScale. */
5990 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5996 for (i = 0; i < count; i++)
5998 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5999 RTX_UNCHANGING_P (mem) = unchanging_p;
6000 MEM_IN_STRUCT_P (mem) = in_struct_p;
6001 MEM_SCALAR_P (mem) = scalar_p;
6002 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6006 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6014 result = gen_rtx_PARALLEL (VOIDmode,
6015 rtvec_alloc (count + (write_back ? 1 : 0)));
6018 XVECEXP (result, 0, 0)
6019 = gen_rtx_SET (GET_MODE (to), to,
6020 plus_constant (to, count * 4 * sign));
6025 for (j = 0; i < count; i++, j++)
6027 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
6028 RTX_UNCHANGING_P (mem) = unchanging_p;
6029 MEM_IN_STRUCT_P (mem) = in_struct_p;
6030 MEM_SCALAR_P (mem) = scalar_p;
6032 XVECEXP (result, 0, i)
6033 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6040 arm_gen_movmemqi (rtx *operands)
6042 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6045 rtx st_src, st_dst, fin_src, fin_dst;
6046 rtx part_bytes_reg = NULL;
6048 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
6049 int dst_scalar_p, src_scalar_p;
6051 if (GET_CODE (operands[2]) != CONST_INT
6052 || GET_CODE (operands[3]) != CONST_INT
6053 || INTVAL (operands[2]) > 64
6054 || INTVAL (operands[3]) & 3)
6057 st_dst = XEXP (operands[0], 0);
6058 st_src = XEXP (operands[1], 0);
6060 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
6061 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
6062 dst_scalar_p = MEM_SCALAR_P (operands[0]);
6063 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
6064 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
6065 src_scalar_p = MEM_SCALAR_P (operands[1]);
6067 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
6068 fin_src = src = copy_to_mode_reg (SImode, st_src);
6070 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6071 out_words_to_go = INTVAL (operands[2]) / 4;
6072 last_bytes = INTVAL (operands[2]) & 3;
6074 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6075 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6077 for (i = 0; in_words_to_go >= 2; i+=4)
6079 if (in_words_to_go > 4)
6080 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6085 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6086 FALSE, src_unchanging_p,
6087 src_in_struct_p, src_scalar_p));
6089 if (out_words_to_go)
6091 if (out_words_to_go > 4)
6092 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6096 else if (out_words_to_go != 1)
6097 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6106 mem = gen_rtx_MEM (SImode, dst);
6107 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6108 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6109 MEM_SCALAR_P (mem) = dst_scalar_p;
6110 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6111 if (last_bytes != 0)
6112 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6116 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6117 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6120 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6121 if (out_words_to_go)
6125 mem = gen_rtx_MEM (SImode, src);
6126 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6127 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6128 MEM_SCALAR_P (mem) = src_scalar_p;
6129 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
6130 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6132 mem = gen_rtx_MEM (SImode, dst);
6133 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6134 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6135 MEM_SCALAR_P (mem) = dst_scalar_p;
6136 emit_move_insn (mem, sreg);
6137 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6140 if (in_words_to_go) /* Sanity check */
6146 if (in_words_to_go < 0)
6149 mem = gen_rtx_MEM (SImode, src);
6150 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6151 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6152 MEM_SCALAR_P (mem) = src_scalar_p;
6153 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6156 if (last_bytes && part_bytes_reg == NULL)
6159 if (BYTES_BIG_ENDIAN && last_bytes)
6161 rtx tmp = gen_reg_rtx (SImode);
6163 /* The bytes we want are in the top end of the word. */
6164 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6165 GEN_INT (8 * (4 - last_bytes))));
6166 part_bytes_reg = tmp;
6170 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6171 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6172 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6173 MEM_SCALAR_P (mem) = dst_scalar_p;
6174 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6178 tmp = gen_reg_rtx (SImode);
6179 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6180 part_bytes_reg = tmp;
6189 mem = gen_rtx_MEM (HImode, dst);
6190 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6191 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6192 MEM_SCALAR_P (mem) = dst_scalar_p;
6193 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6197 rtx tmp = gen_reg_rtx (SImode);
6199 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6200 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6201 part_bytes_reg = tmp;
6207 mem = gen_rtx_MEM (QImode, dst);
6208 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6209 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6210 MEM_SCALAR_P (mem) = dst_scalar_p;
6211 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6218 /* Generate a memory reference for a half word, such that it will be loaded
6219 into the top 16 bits of the word. We can assume that the address is
6220 known to be alignable and of the form reg, or plus (reg, const). */
6223 arm_gen_rotated_half_load (rtx memref)
6225 HOST_WIDE_INT offset = 0;
6226 rtx base = XEXP (memref, 0);
6228 if (GET_CODE (base) == PLUS)
6230 offset = INTVAL (XEXP (base, 1));
6231 base = XEXP (base, 0);
6234 /* If we aren't allowed to generate unaligned addresses, then fail. */
6235 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6238 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6240 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6243 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6246 /* Select a dominance comparison mode if possible for a test of the general
6247 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6248 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6249 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6250 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6251 In all cases OP will be either EQ or NE, but we don't need to know which
6252 here. If we are unable to support a dominance comparison we return
6253 CC mode. This will then fail to match for the RTL expressions that
6254 generate this call. */
6256 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6258 enum rtx_code cond1, cond2;
6261 /* Currently we will probably get the wrong result if the individual
6262 comparisons are not simple. This also ensures that it is safe to
6263 reverse a comparison if necessary. */
6264 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6266 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6270 /* The if_then_else variant of this tests the second condition if the
6271 first passes, but is true if the first fails. Reverse the first
6272 condition to get a true "inclusive-or" expression. */
6273 if (cond_or == DOM_CC_NX_OR_Y)
6274 cond1 = reverse_condition (cond1);
6276 /* If the comparisons are not equal, and one doesn't dominate the other,
6277 then we can't do this. */
6279 && !comparison_dominates_p (cond1, cond2)
6280 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6285 enum rtx_code temp = cond1;
6293 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6298 case LE: return CC_DLEmode;
6299 case LEU: return CC_DLEUmode;
6300 case GE: return CC_DGEmode;
6301 case GEU: return CC_DGEUmode;
6308 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6317 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6326 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6335 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6343 /* The remaining cases only occur when both comparisons are the
6368 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6370 /* All floating point compares return CCFP if it is an equality
6371 comparison, and CCFPE otherwise. */
6372 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6392 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6401 /* A compare with a shifted operand. Because of canonicalization, the
6402 comparison will have to be swapped when we emit the assembler. */
6403 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6404 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6405 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6406 || GET_CODE (x) == ROTATERT))
6409 /* This is a special case that is used by combine to allow a
6410 comparison of a shifted byte load to be split into a zero-extend
6411 followed by a comparison of the shifted integer (only valid for
6412 equalities and unsigned inequalities). */
6413 if (GET_MODE (x) == SImode
6414 && GET_CODE (x) == ASHIFT
6415 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6416 && GET_CODE (XEXP (x, 0)) == SUBREG
6417 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6418 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6419 && (op == EQ || op == NE
6420 || op == GEU || op == GTU || op == LTU || op == LEU)
6421 && GET_CODE (y) == CONST_INT)
6424 /* A construct for a conditional compare, if the false arm contains
6425 0, then both conditions must be true, otherwise either condition
6426 must be true. Not all conditions are possible, so CCmode is
6427 returned if it can't be done. */
6428 if (GET_CODE (x) == IF_THEN_ELSE
6429 && (XEXP (x, 2) == const0_rtx
6430 || XEXP (x, 2) == const1_rtx)
6431 && COMPARISON_P (XEXP (x, 0))
6432 && COMPARISON_P (XEXP (x, 1)))
6433 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6434 INTVAL (XEXP (x, 2)));
6436 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6437 if (GET_CODE (x) == AND
6438 && COMPARISON_P (XEXP (x, 0))
6439 && COMPARISON_P (XEXP (x, 1)))
6440 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6443 if (GET_CODE (x) == IOR
6444 && COMPARISON_P (XEXP (x, 0))
6445 && COMPARISON_P (XEXP (x, 1)))
6446 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6449 /* An operation (on Thumb) where we want to test for a single bit.
6450 This is done by shifting that bit up into the top bit of a
6451 scratch register; we can then branch on the sign bit. */
6453 && GET_MODE (x) == SImode
6454 && (op == EQ || op == NE)
6455 && (GET_CODE (x) == ZERO_EXTRACT))
6458 /* An operation that sets the condition codes as a side-effect, the
6459 V flag is not set correctly, so we can only use comparisons where
6460 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6462 if (GET_MODE (x) == SImode
6464 && (op == EQ || op == NE || op == LT || op == GE)
6465 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6466 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6467 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6468 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6469 || GET_CODE (x) == LSHIFTRT
6470 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6471 || GET_CODE (x) == ROTATERT
6472 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6475 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6478 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6479 && GET_CODE (x) == PLUS
6480 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6486 /* X and Y are two things to compare using CODE. Emit the compare insn and
6487 return the rtx for register 0 in the proper mode. FP means this is a
6488 floating point compare: I don't think that it is needed on the arm. */
6490 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6492 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6493 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6495 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6496 gen_rtx_COMPARE (mode, x, y)));
6501 /* Generate a sequence of insns that will generate the correct return
6502 address mask depending on the physical architecture that the program
6505 arm_gen_return_addr_mask (void)
6507 rtx reg = gen_reg_rtx (Pmode);
6509 emit_insn (gen_return_addr_mask (reg));
6514 arm_reload_in_hi (rtx *operands)
6516 rtx ref = operands[1];
6518 HOST_WIDE_INT offset = 0;
6520 if (GET_CODE (ref) == SUBREG)
6522 offset = SUBREG_BYTE (ref);
6523 ref = SUBREG_REG (ref);
6526 if (GET_CODE (ref) == REG)
6528 /* We have a pseudo which has been spilt onto the stack; there
6529 are two cases here: the first where there is a simple
6530 stack-slot replacement and a second where the stack-slot is
6531 out of range, or is used as a subreg. */
6532 if (reg_equiv_mem[REGNO (ref)])
6534 ref = reg_equiv_mem[REGNO (ref)];
6535 base = find_replacement (&XEXP (ref, 0));
6538 /* The slot is out of range, or was dressed up in a SUBREG. */
6539 base = reg_equiv_address[REGNO (ref)];
6542 base = find_replacement (&XEXP (ref, 0));
6544 /* Handle the case where the address is too complex to be offset by 1. */
6545 if (GET_CODE (base) == MINUS
6546 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6548 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6550 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6553 else if (GET_CODE (base) == PLUS)
6555 /* The addend must be CONST_INT, or we would have dealt with it above. */
6556 HOST_WIDE_INT hi, lo;
6558 offset += INTVAL (XEXP (base, 1));
6559 base = XEXP (base, 0);
6561 /* Rework the address into a legal sequence of insns. */
6562 /* Valid range for lo is -4095 -> 4095 */
6565 : -((-offset) & 0xfff));
6567 /* Corner case, if lo is the max offset then we would be out of range
6568 once we have added the additional 1 below, so bump the msb into the
6569 pre-loading insn(s). */
6573 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6574 ^ (HOST_WIDE_INT) 0x80000000)
6575 - (HOST_WIDE_INT) 0x80000000);
6577 if (hi + lo != offset)
6582 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6584 /* Get the base address; addsi3 knows how to handle constants
6585 that require more than one insn. */
6586 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6592 /* Operands[2] may overlap operands[0] (though it won't overlap
6593 operands[1]), that's why we asked for a DImode reg -- so we can
6594 use the bit that does not overlap. */
6595 if (REGNO (operands[2]) == REGNO (operands[0]))
6596 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6598 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6600 emit_insn (gen_zero_extendqisi2 (scratch,
6601 gen_rtx_MEM (QImode,
6602 plus_constant (base,
6604 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6605 gen_rtx_MEM (QImode,
6606 plus_constant (base,
6608 if (!BYTES_BIG_ENDIAN)
6609 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6610 gen_rtx_IOR (SImode,
6613 gen_rtx_SUBREG (SImode, operands[0], 0),
6617 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6618 gen_rtx_IOR (SImode,
6619 gen_rtx_ASHIFT (SImode, scratch,
6621 gen_rtx_SUBREG (SImode, operands[0],
6625 /* Handle storing a half-word to memory during reload by synthesizing as two
6626 byte stores. Take care not to clobber the input values until after we
6627 have moved them somewhere safe. This code assumes that if the DImode
6628 scratch in operands[2] overlaps either the input value or output address
6629 in some way, then that value must die in this insn (we absolutely need
6630 two scratch registers for some corner cases). */
6632 arm_reload_out_hi (rtx *operands)
6634 rtx ref = operands[0];
6635 rtx outval = operands[1];
6637 HOST_WIDE_INT offset = 0;
6639 if (GET_CODE (ref) == SUBREG)
6641 offset = SUBREG_BYTE (ref);
6642 ref = SUBREG_REG (ref);
6645 if (GET_CODE (ref) == REG)
6647 /* We have a pseudo which has been spilt onto the stack; there
6648 are two cases here: the first where there is a simple
6649 stack-slot replacement and a second where the stack-slot is
6650 out of range, or is used as a subreg. */
6651 if (reg_equiv_mem[REGNO (ref)])
6653 ref = reg_equiv_mem[REGNO (ref)];
6654 base = find_replacement (&XEXP (ref, 0));
6657 /* The slot is out of range, or was dressed up in a SUBREG. */
6658 base = reg_equiv_address[REGNO (ref)];
6661 base = find_replacement (&XEXP (ref, 0));
6663 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6665 /* Handle the case where the address is too complex to be offset by 1. */
6666 if (GET_CODE (base) == MINUS
6667 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6669 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6671 /* Be careful not to destroy OUTVAL. */
6672 if (reg_overlap_mentioned_p (base_plus, outval))
6674 /* Updating base_plus might destroy outval, see if we can
6675 swap the scratch and base_plus. */
6676 if (!reg_overlap_mentioned_p (scratch, outval))
6679 scratch = base_plus;
6684 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6686 /* Be conservative and copy OUTVAL into the scratch now,
6687 this should only be necessary if outval is a subreg
6688 of something larger than a word. */
6689 /* XXX Might this clobber base? I can't see how it can,
6690 since scratch is known to overlap with OUTVAL, and
6691 must be wider than a word. */
6692 emit_insn (gen_movhi (scratch_hi, outval));
6693 outval = scratch_hi;
6697 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6700 else if (GET_CODE (base) == PLUS)
6702 /* The addend must be CONST_INT, or we would have dealt with it above. */
6703 HOST_WIDE_INT hi, lo;
6705 offset += INTVAL (XEXP (base, 1));
6706 base = XEXP (base, 0);
6708 /* Rework the address into a legal sequence of insns. */
6709 /* Valid range for lo is -4095 -> 4095 */
6712 : -((-offset) & 0xfff));
6714 /* Corner case, if lo is the max offset then we would be out of range
6715 once we have added the additional 1 below, so bump the msb into the
6716 pre-loading insn(s). */
6720 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6721 ^ (HOST_WIDE_INT) 0x80000000)
6722 - (HOST_WIDE_INT) 0x80000000);
6724 if (hi + lo != offset)
6729 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6731 /* Be careful not to destroy OUTVAL. */
6732 if (reg_overlap_mentioned_p (base_plus, outval))
6734 /* Updating base_plus might destroy outval, see if we
6735 can swap the scratch and base_plus. */
6736 if (!reg_overlap_mentioned_p (scratch, outval))
6739 scratch = base_plus;
6744 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6746 /* Be conservative and copy outval into scratch now,
6747 this should only be necessary if outval is a
6748 subreg of something larger than a word. */
6749 /* XXX Might this clobber base? I can't see how it
6750 can, since scratch is known to overlap with
6752 emit_insn (gen_movhi (scratch_hi, outval));
6753 outval = scratch_hi;
6757 /* Get the base address; addsi3 knows how to handle constants
6758 that require more than one insn. */
6759 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6765 if (BYTES_BIG_ENDIAN)
6767 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6768 plus_constant (base, offset + 1)),
6769 gen_lowpart (QImode, outval)));
6770 emit_insn (gen_lshrsi3 (scratch,
6771 gen_rtx_SUBREG (SImode, outval, 0),
6773 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6774 gen_lowpart (QImode, scratch)));
6778 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6779 gen_lowpart (QImode, outval)));
6780 emit_insn (gen_lshrsi3 (scratch,
6781 gen_rtx_SUBREG (SImode, outval, 0),
6783 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6784 plus_constant (base, offset + 1)),
6785 gen_lowpart (QImode, scratch)));
6789 /* Print a symbolic form of X to the debug file, F. */
6791 arm_print_value (FILE *f, rtx x)
6793 switch (GET_CODE (x))
6796 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6800 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6808 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6810 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6811 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6819 fprintf (f, "\"%s\"", XSTR (x, 0));
6823 fprintf (f, "`%s'", XSTR (x, 0));
6827 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6831 arm_print_value (f, XEXP (x, 0));
6835 arm_print_value (f, XEXP (x, 0));
6837 arm_print_value (f, XEXP (x, 1));
6845 fprintf (f, "????");
6850 /* Routines for manipulation of the constant pool. */
6852 /* Arm instructions cannot load a large constant directly into a
6853 register; they have to come from a pc relative load. The constant
6854 must therefore be placed in the addressable range of the pc
6855 relative load. Depending on the precise pc relative load
6856 instruction the range is somewhere between 256 bytes and 4k. This
6857 means that we often have to dump a constant inside a function, and
6858 generate code to branch around it.
6860 It is important to minimize this, since the branches will slow
6861 things down and make the code larger.
6863 Normally we can hide the table after an existing unconditional
6864 branch so that there is no interruption of the flow, but in the
6865 worst case the code looks like this:
6883 We fix this by performing a scan after scheduling, which notices
6884 which instructions need to have their operands fetched from the
6885 constant table and builds the table.
6887 The algorithm starts by building a table of all the constants that
6888 need fixing up and all the natural barriers in the function (places
6889 where a constant table can be dropped without breaking the flow).
6890 For each fixup we note how far the pc-relative replacement will be
6891 able to reach and the offset of the instruction into the function.
6893 Having built the table we then group the fixes together to form
6894 tables that are as large as possible (subject to addressing
6895 constraints) and emit each table of constants after the last
6896 barrier that is within range of all the instructions in the group.
6897 If a group does not contain a barrier, then we forcibly create one
6898 by inserting a jump instruction into the flow. Once the table has
6899 been inserted, the insns are then modified to reference the
6900 relevant entry in the pool.
6902 Possible enhancements to the algorithm (not implemented) are:
6904 1) For some processors and object formats, there may be benefit in
6905 aligning the pools to the start of cache lines; this alignment
6906 would need to be taken into account when calculating addressability
6909 /* These typedefs are located at the start of this file, so that
6910 they can be used in the prototypes there. This comment is to
6911 remind readers of that fact so that the following structures
6912 can be understood more easily.
6914 typedef struct minipool_node Mnode;
6915 typedef struct minipool_fixup Mfix; */
6917 struct minipool_node
6919 /* Doubly linked chain of entries. */
6922 /* The maximum offset into the code that this entry can be placed. While
6923 pushing fixes for forward references, all entries are sorted in order
6924 of increasing max_address. */
6925 HOST_WIDE_INT max_address;
6926 /* Similarly for an entry inserted for a backwards ref. */
6927 HOST_WIDE_INT min_address;
6928 /* The number of fixes referencing this entry. This can become zero
6929 if we "unpush" an entry. In this case we ignore the entry when we
6930 come to emit the code. */
6932 /* The offset from the start of the minipool. */
6933 HOST_WIDE_INT offset;
6934 /* The value in table. */
6936 /* The mode of value. */
6937 enum machine_mode mode;
6938 /* The size of the value. With iWMMXt enabled
6939 sizes > 4 also imply an alignment of 8-bytes. */
6943 struct minipool_fixup
6947 HOST_WIDE_INT address;
6949 enum machine_mode mode;
6953 HOST_WIDE_INT forwards;
6954 HOST_WIDE_INT backwards;
6957 /* Fixes less than a word need padding out to a word boundary. */
6958 #define MINIPOOL_FIX_SIZE(mode) \
6959 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6961 static Mnode * minipool_vector_head;
6962 static Mnode * minipool_vector_tail;
6963 static rtx minipool_vector_label;
6965 /* The linked list of all minipool fixes required for this function. */
6966 Mfix * minipool_fix_head;
6967 Mfix * minipool_fix_tail;
6968 /* The fix entry for the current minipool, once it has been placed. */
6969 Mfix * minipool_barrier;
6971 /* Determines if INSN is the start of a jump table. Returns the end
6972 of the TABLE or NULL_RTX. */
6974 is_jump_table (rtx insn)
6978 if (GET_CODE (insn) == JUMP_INSN
6979 && JUMP_LABEL (insn) != NULL
6980 && ((table = next_real_insn (JUMP_LABEL (insn)))
6981 == next_real_insn (insn))
6983 && GET_CODE (table) == JUMP_INSN
6984 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6985 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6991 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6992 #define JUMP_TABLES_IN_TEXT_SECTION 0
6995 static HOST_WIDE_INT
6996 get_jump_table_size (rtx insn)
6998 /* ADDR_VECs only take room if read-only data does into the text
7000 if (JUMP_TABLES_IN_TEXT_SECTION
7001 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7006 rtx body = PATTERN (insn);
7007 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7009 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
7015 /* Move a minipool fix MP from its current location to before MAX_MP.
7016 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7017 constraints may need updating. */
7019 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7020 HOST_WIDE_INT max_address)
7022 /* This should never be true and the code below assumes these are
7029 if (max_address < mp->max_address)
7030 mp->max_address = max_address;
7034 if (max_address > max_mp->max_address - mp->fix_size)
7035 mp->max_address = max_mp->max_address - mp->fix_size;
7037 mp->max_address = max_address;
7039 /* Unlink MP from its current position. Since max_mp is non-null,
7040 mp->prev must be non-null. */
7041 mp->prev->next = mp->next;
7042 if (mp->next != NULL)
7043 mp->next->prev = mp->prev;
7045 minipool_vector_tail = mp->prev;
7047 /* Re-insert it before MAX_MP. */
7049 mp->prev = max_mp->prev;
7052 if (mp->prev != NULL)
7053 mp->prev->next = mp;
7055 minipool_vector_head = mp;
7058 /* Save the new entry. */
7061 /* Scan over the preceding entries and adjust their addresses as
7063 while (mp->prev != NULL
7064 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7066 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7073 /* Add a constant to the minipool for a forward reference. Returns the
7074 node added or NULL if the constant will not fit in this pool. */
7076 add_minipool_forward_ref (Mfix *fix)
7078 /* If set, max_mp is the first pool_entry that has a lower
7079 constraint than the one we are trying to add. */
7080 Mnode * max_mp = NULL;
7081 HOST_WIDE_INT max_address = fix->address + fix->forwards;
7084 /* If this fix's address is greater than the address of the first
7085 entry, then we can't put the fix in this pool. We subtract the
7086 size of the current fix to ensure that if the table is fully
7087 packed we still have enough room to insert this value by suffling
7088 the other fixes forwards. */
7089 if (minipool_vector_head &&
7090 fix->address >= minipool_vector_head->max_address - fix->fix_size)
7093 /* Scan the pool to see if a constant with the same value has
7094 already been added. While we are doing this, also note the
7095 location where we must insert the constant if it doesn't already
7097 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7099 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7100 && fix->mode == mp->mode
7101 && (GET_CODE (fix->value) != CODE_LABEL
7102 || (CODE_LABEL_NUMBER (fix->value)
7103 == CODE_LABEL_NUMBER (mp->value)))
7104 && rtx_equal_p (fix->value, mp->value))
7106 /* More than one fix references this entry. */
7108 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7111 /* Note the insertion point if necessary. */
7113 && mp->max_address > max_address)
7116 /* If we are inserting an 8-bytes aligned quantity and
7117 we have not already found an insertion point, then
7118 make sure that all such 8-byte aligned quantities are
7119 placed at the start of the pool. */
7120 if (ARM_DOUBLEWORD_ALIGN
7122 && fix->fix_size == 8
7123 && mp->fix_size != 8)
7126 max_address = mp->max_address;
7130 /* The value is not currently in the minipool, so we need to create
7131 a new entry for it. If MAX_MP is NULL, the entry will be put on
7132 the end of the list since the placement is less constrained than
7133 any existing entry. Otherwise, we insert the new fix before
7134 MAX_MP and, if necessary, adjust the constraints on the other
7136 mp = xmalloc (sizeof (* mp));
7137 mp->fix_size = fix->fix_size;
7138 mp->mode = fix->mode;
7139 mp->value = fix->value;
7141 /* Not yet required for a backwards ref. */
7142 mp->min_address = -65536;
7146 mp->max_address = max_address;
7148 mp->prev = minipool_vector_tail;
7150 if (mp->prev == NULL)
7152 minipool_vector_head = mp;
7153 minipool_vector_label = gen_label_rtx ();
7156 mp->prev->next = mp;
7158 minipool_vector_tail = mp;
7162 if (max_address > max_mp->max_address - mp->fix_size)
7163 mp->max_address = max_mp->max_address - mp->fix_size;
7165 mp->max_address = max_address;
7168 mp->prev = max_mp->prev;
7170 if (mp->prev != NULL)
7171 mp->prev->next = mp;
7173 minipool_vector_head = mp;
7176 /* Save the new entry. */
7179 /* Scan over the preceding entries and adjust their addresses as
7181 while (mp->prev != NULL
7182 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7184 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7192 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7193 HOST_WIDE_INT min_address)
7195 HOST_WIDE_INT offset;
7197 /* This should never be true, and the code below assumes these are
7204 if (min_address > mp->min_address)
7205 mp->min_address = min_address;
7209 /* We will adjust this below if it is too loose. */
7210 mp->min_address = min_address;
7212 /* Unlink MP from its current position. Since min_mp is non-null,
7213 mp->next must be non-null. */
7214 mp->next->prev = mp->prev;
7215 if (mp->prev != NULL)
7216 mp->prev->next = mp->next;
7218 minipool_vector_head = mp->next;
7220 /* Reinsert it after MIN_MP. */
7222 mp->next = min_mp->next;
7224 if (mp->next != NULL)
7225 mp->next->prev = mp;
7227 minipool_vector_tail = mp;
7233 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7235 mp->offset = offset;
7236 if (mp->refcount > 0)
7237 offset += mp->fix_size;
7239 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7240 mp->next->min_address = mp->min_address + mp->fix_size;
7246 /* Add a constant to the minipool for a backward reference. Returns the
7247 node added or NULL if the constant will not fit in this pool.
7249 Note that the code for insertion for a backwards reference can be
7250 somewhat confusing because the calculated offsets for each fix do
7251 not take into account the size of the pool (which is still under
7254 add_minipool_backward_ref (Mfix *fix)
7256 /* If set, min_mp is the last pool_entry that has a lower constraint
7257 than the one we are trying to add. */
7258 Mnode *min_mp = NULL;
7259 /* This can be negative, since it is only a constraint. */
7260 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7263 /* If we can't reach the current pool from this insn, or if we can't
7264 insert this entry at the end of the pool without pushing other
7265 fixes out of range, then we don't try. This ensures that we
7266 can't fail later on. */
7267 if (min_address >= minipool_barrier->address
7268 || (minipool_vector_tail->min_address + fix->fix_size
7269 >= minipool_barrier->address))
7272 /* Scan the pool to see if a constant with the same value has
7273 already been added. While we are doing this, also note the
7274 location where we must insert the constant if it doesn't already
7276 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7278 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7279 && fix->mode == mp->mode
7280 && (GET_CODE (fix->value) != CODE_LABEL
7281 || (CODE_LABEL_NUMBER (fix->value)
7282 == CODE_LABEL_NUMBER (mp->value)))
7283 && rtx_equal_p (fix->value, mp->value)
7284 /* Check that there is enough slack to move this entry to the
7285 end of the table (this is conservative). */
7287 > (minipool_barrier->address
7288 + minipool_vector_tail->offset
7289 + minipool_vector_tail->fix_size)))
7292 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7296 mp->min_address += fix->fix_size;
7299 /* Note the insertion point if necessary. */
7300 if (mp->min_address < min_address)
7302 /* For now, we do not allow the insertion of 8-byte alignment
7303 requiring nodes anywhere but at the start of the pool. */
7304 if (ARM_DOUBLEWORD_ALIGN
7305 && fix->fix_size == 8 && mp->fix_size != 8)
7310 else if (mp->max_address
7311 < minipool_barrier->address + mp->offset + fix->fix_size)
7313 /* Inserting before this entry would push the fix beyond
7314 its maximum address (which can happen if we have
7315 re-located a forwards fix); force the new fix to come
7318 min_address = mp->min_address + fix->fix_size;
7320 /* If we are inserting an 8-bytes aligned quantity and
7321 we have not already found an insertion point, then
7322 make sure that all such 8-byte aligned quantities are
7323 placed at the start of the pool. */
7324 else if (ARM_DOUBLEWORD_ALIGN
7326 && fix->fix_size == 8
7327 && mp->fix_size < 8)
7330 min_address = mp->min_address + fix->fix_size;
7335 /* We need to create a new entry. */
7336 mp = xmalloc (sizeof (* mp));
7337 mp->fix_size = fix->fix_size;
7338 mp->mode = fix->mode;
7339 mp->value = fix->value;
7341 mp->max_address = minipool_barrier->address + 65536;
7343 mp->min_address = min_address;
7348 mp->next = minipool_vector_head;
7350 if (mp->next == NULL)
7352 minipool_vector_tail = mp;
7353 minipool_vector_label = gen_label_rtx ();
7356 mp->next->prev = mp;
7358 minipool_vector_head = mp;
7362 mp->next = min_mp->next;
7366 if (mp->next != NULL)
7367 mp->next->prev = mp;
7369 minipool_vector_tail = mp;
7372 /* Save the new entry. */
7380 /* Scan over the following entries and adjust their offsets. */
7381 while (mp->next != NULL)
7383 if (mp->next->min_address < mp->min_address + mp->fix_size)
7384 mp->next->min_address = mp->min_address + mp->fix_size;
7387 mp->next->offset = mp->offset + mp->fix_size;
7389 mp->next->offset = mp->offset;
7398 assign_minipool_offsets (Mfix *barrier)
7400 HOST_WIDE_INT offset = 0;
7403 minipool_barrier = barrier;
7405 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7407 mp->offset = offset;
7409 if (mp->refcount > 0)
7410 offset += mp->fix_size;
7414 /* Output the literal table */
7416 dump_minipool (rtx scan)
7422 if (ARM_DOUBLEWORD_ALIGN)
7423 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7424 if (mp->refcount > 0 && mp->fix_size == 8)
7432 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7433 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7435 scan = emit_label_after (gen_label_rtx (), scan);
7436 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7437 scan = emit_label_after (minipool_vector_label, scan);
7439 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7441 if (mp->refcount > 0)
7446 ";; Offset %u, min %ld, max %ld ",
7447 (unsigned) mp->offset, (unsigned long) mp->min_address,
7448 (unsigned long) mp->max_address);
7449 arm_print_value (dump_file, mp->value);
7450 fputc ('\n', dump_file);
7453 switch (mp->fix_size)
7455 #ifdef HAVE_consttable_1
7457 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7461 #ifdef HAVE_consttable_2
7463 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7467 #ifdef HAVE_consttable_4
7469 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7473 #ifdef HAVE_consttable_8
7475 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7489 minipool_vector_head = minipool_vector_tail = NULL;
7490 scan = emit_insn_after (gen_consttable_end (), scan);
7491 scan = emit_barrier_after (scan);
7494 /* Return the cost of forcibly inserting a barrier after INSN. */
7496 arm_barrier_cost (rtx insn)
7498 /* Basing the location of the pool on the loop depth is preferable,
7499 but at the moment, the basic block information seems to be
7500 corrupt by this stage of the compilation. */
7502 rtx next = next_nonnote_insn (insn);
7504 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7507 switch (GET_CODE (insn))
7510 /* It will always be better to place the table before the label, rather
7519 return base_cost - 10;
7522 return base_cost + 10;
7526 /* Find the best place in the insn stream in the range
7527 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7528 Create the barrier by inserting a jump and add a new fix entry for
7531 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7533 HOST_WIDE_INT count = 0;
7535 rtx from = fix->insn;
7536 rtx selected = from;
7538 HOST_WIDE_INT selected_address;
7540 HOST_WIDE_INT max_count = max_address - fix->address;
7541 rtx label = gen_label_rtx ();
7543 selected_cost = arm_barrier_cost (from);
7544 selected_address = fix->address;
7546 while (from && count < max_count)
7551 /* This code shouldn't have been called if there was a natural barrier
7553 if (GET_CODE (from) == BARRIER)
7556 /* Count the length of this insn. */
7557 count += get_attr_length (from);
7559 /* If there is a jump table, add its length. */
7560 tmp = is_jump_table (from);
7563 count += get_jump_table_size (tmp);
7565 /* Jump tables aren't in a basic block, so base the cost on
7566 the dispatch insn. If we select this location, we will
7567 still put the pool after the table. */
7568 new_cost = arm_barrier_cost (from);
7570 if (count < max_count && new_cost <= selected_cost)
7573 selected_cost = new_cost;
7574 selected_address = fix->address + count;
7577 /* Continue after the dispatch table. */
7578 from = NEXT_INSN (tmp);
7582 new_cost = arm_barrier_cost (from);
7584 if (count < max_count && new_cost <= selected_cost)
7587 selected_cost = new_cost;
7588 selected_address = fix->address + count;
7591 from = NEXT_INSN (from);
7594 /* Create a new JUMP_INSN that branches around a barrier. */
7595 from = emit_jump_insn_after (gen_jump (label), selected);
7596 JUMP_LABEL (from) = label;
7597 barrier = emit_barrier_after (from);
7598 emit_label_after (label, barrier);
7600 /* Create a minipool barrier entry for the new barrier. */
7601 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7602 new_fix->insn = barrier;
7603 new_fix->address = selected_address;
7604 new_fix->next = fix->next;
7605 fix->next = new_fix;
7610 /* Record that there is a natural barrier in the insn stream at
7613 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7615 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7618 fix->address = address;
7621 if (minipool_fix_head != NULL)
7622 minipool_fix_tail->next = fix;
7624 minipool_fix_head = fix;
7626 minipool_fix_tail = fix;
7629 /* Record INSN, which will need fixing up to load a value from the
7630 minipool. ADDRESS is the offset of the insn since the start of the
7631 function; LOC is a pointer to the part of the insn which requires
7632 fixing; VALUE is the constant that must be loaded, which is of type
7635 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7636 enum machine_mode mode, rtx value)
7638 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7640 #ifdef AOF_ASSEMBLER
7641 /* PIC symbol references need to be converted into offsets into the
7643 /* XXX This shouldn't be done here. */
7644 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7645 value = aof_pic_entry (value);
7646 #endif /* AOF_ASSEMBLER */
7649 fix->address = address;
7652 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7654 fix->forwards = get_attr_pool_range (insn);
7655 fix->backwards = get_attr_neg_pool_range (insn);
7656 fix->minipool = NULL;
7658 /* If an insn doesn't have a range defined for it, then it isn't
7659 expecting to be reworked by this code. Better to abort now than
7660 to generate duff assembly code. */
7661 if (fix->forwards == 0 && fix->backwards == 0)
7664 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7665 So there might be an empty word before the start of the pool.
7666 Hence we reduce the forward range by 4 to allow for this
7668 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7674 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7675 GET_MODE_NAME (mode),
7676 INSN_UID (insn), (unsigned long) address,
7677 -1 * (long)fix->backwards, (long)fix->forwards);
7678 arm_print_value (dump_file, fix->value);
7679 fprintf (dump_file, "\n");
7682 /* Add it to the chain of fixes. */
7685 if (minipool_fix_head != NULL)
7686 minipool_fix_tail->next = fix;
7688 minipool_fix_head = fix;
7690 minipool_fix_tail = fix;
7693 /* Scan INSN and note any of its operands that need fixing.
7694 If DO_PUSHES is false we do not actually push any of the fixups
7695 needed. The function returns TRUE is any fixups were needed/pushed.
7696 This is used by arm_memory_load_p() which needs to know about loads
7697 of constants that will be converted into minipool loads. */
7699 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7701 bool result = false;
7704 extract_insn (insn);
7706 if (!constrain_operands (1))
7707 fatal_insn_not_found (insn);
7709 if (recog_data.n_alternatives == 0)
7712 /* Fill in recog_op_alt with information about the constraints of this insn. */
7713 preprocess_constraints ();
7715 for (opno = 0; opno < recog_data.n_operands; opno++)
7717 /* Things we need to fix can only occur in inputs. */
7718 if (recog_data.operand_type[opno] != OP_IN)
7721 /* If this alternative is a memory reference, then any mention
7722 of constants in this alternative is really to fool reload
7723 into allowing us to accept one there. We need to fix them up
7724 now so that we output the right code. */
7725 if (recog_op_alt[opno][which_alternative].memory_ok)
7727 rtx op = recog_data.operand[opno];
7729 if (CONSTANT_P (op))
7732 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7733 recog_data.operand_mode[opno], op);
7736 else if (GET_CODE (op) == MEM
7737 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7738 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7742 rtx cop = avoid_constant_pool_reference (op);
7744 /* Casting the address of something to a mode narrower
7745 than a word can cause avoid_constant_pool_reference()
7746 to return the pool reference itself. That's no good to
7747 us here. Lets just hope that we can use the
7748 constant pool value directly. */
7750 cop = get_pool_constant (XEXP (op, 0));
7752 push_minipool_fix (insn, address,
7753 recog_data.operand_loc[opno],
7754 recog_data.operand_mode[opno], cop);
7765 /* Gcc puts the pool in the wrong place for ARM, since we can only
7766 load addresses a limited distance around the pc. We do some
7767 special munging to move the constant pool values to the correct
7768 point in the code. */
7773 HOST_WIDE_INT address = 0;
7776 minipool_fix_head = minipool_fix_tail = NULL;
7778 /* The first insn must always be a note, or the code below won't
7779 scan it properly. */
7780 insn = get_insns ();
7781 if (GET_CODE (insn) != NOTE)
7784 /* Scan all the insns and record the operands that will need fixing. */
7785 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7787 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7788 && (arm_cirrus_insn_p (insn)
7789 || GET_CODE (insn) == JUMP_INSN
7790 || arm_memory_load_p (insn)))
7791 cirrus_reorg (insn);
7793 if (GET_CODE (insn) == BARRIER)
7794 push_minipool_barrier (insn, address);
7795 else if (INSN_P (insn))
7799 note_invalid_constants (insn, address, true);
7800 address += get_attr_length (insn);
7802 /* If the insn is a vector jump, add the size of the table
7803 and skip the table. */
7804 if ((table = is_jump_table (insn)) != NULL)
7806 address += get_jump_table_size (table);
7812 fix = minipool_fix_head;
7814 /* Now scan the fixups and perform the required changes. */
7819 Mfix * last_added_fix;
7820 Mfix * last_barrier = NULL;
7823 /* Skip any further barriers before the next fix. */
7824 while (fix && GET_CODE (fix->insn) == BARRIER)
7827 /* No more fixes. */
7831 last_added_fix = NULL;
7833 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7835 if (GET_CODE (ftmp->insn) == BARRIER)
7837 if (ftmp->address >= minipool_vector_head->max_address)
7840 last_barrier = ftmp;
7842 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7845 last_added_fix = ftmp; /* Keep track of the last fix added. */
7848 /* If we found a barrier, drop back to that; any fixes that we
7849 could have reached but come after the barrier will now go in
7850 the next mini-pool. */
7851 if (last_barrier != NULL)
7853 /* Reduce the refcount for those fixes that won't go into this
7855 for (fdel = last_barrier->next;
7856 fdel && fdel != ftmp;
7859 fdel->minipool->refcount--;
7860 fdel->minipool = NULL;
7863 ftmp = last_barrier;
7867 /* ftmp is first fix that we can't fit into this pool and
7868 there no natural barriers that we could use. Insert a
7869 new barrier in the code somewhere between the previous
7870 fix and this one, and arrange to jump around it. */
7871 HOST_WIDE_INT max_address;
7873 /* The last item on the list of fixes must be a barrier, so
7874 we can never run off the end of the list of fixes without
7875 last_barrier being set. */
7879 max_address = minipool_vector_head->max_address;
7880 /* Check that there isn't another fix that is in range that
7881 we couldn't fit into this pool because the pool was
7882 already too large: we need to put the pool before such an
7884 if (ftmp->address < max_address)
7885 max_address = ftmp->address;
7887 last_barrier = create_fix_barrier (last_added_fix, max_address);
7890 assign_minipool_offsets (last_barrier);
7894 if (GET_CODE (ftmp->insn) != BARRIER
7895 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7902 /* Scan over the fixes we have identified for this pool, fixing them
7903 up and adding the constants to the pool itself. */
7904 for (this_fix = fix; this_fix && ftmp != this_fix;
7905 this_fix = this_fix->next)
7906 if (GET_CODE (this_fix->insn) != BARRIER)
7909 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7910 minipool_vector_label),
7911 this_fix->minipool->offset);
7912 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7915 dump_minipool (last_barrier->insn);
7919 /* From now on we must synthesize any constants that we can't handle
7920 directly. This can happen if the RTL gets split during final
7921 instruction generation. */
7922 after_arm_reorg = 1;
7924 /* Free the minipool memory. */
7925 obstack_free (&minipool_obstack, minipool_startobj);
7928 /* Routines to output assembly language. */
7930 /* If the rtx is the correct value then return the string of the number.
7931 In this way we can ensure that valid double constants are generated even
7932 when cross compiling. */
7934 fp_immediate_constant (rtx x)
7939 if (!fp_consts_inited)
7942 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7943 for (i = 0; i < 8; i++)
7944 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7945 return strings_fp[i];
7950 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7952 fp_const_from_val (REAL_VALUE_TYPE *r)
7956 if (!fp_consts_inited)
7959 for (i = 0; i < 8; i++)
7960 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7961 return strings_fp[i];
7966 /* Output the operands of a LDM/STM instruction to STREAM.
7967 MASK is the ARM register set mask of which only bits 0-15 are important.
7968 REG is the base register, either the frame pointer or the stack pointer,
7969 INSTR is the possibly suffixed load or store instruction. */
7971 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7974 int not_first = FALSE;
7976 fputc ('\t', stream);
7977 asm_fprintf (stream, instr, reg);
7978 fputs (", {", stream);
7980 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7981 if (mask & (1 << i))
7984 fprintf (stream, ", ");
7986 asm_fprintf (stream, "%r", i);
7990 fprintf (stream, "}\n");
7994 /* Output a FLDMX instruction to STREAM.
7995 BASE if the register containing the address.
7996 REG and COUNT specify the register range.
7997 Extra registers may be added to avoid hardware bugs. */
8000 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8004 /* Workaround ARM10 VFPr1 bug. */
8005 if (count == 2 && !arm_arch6)
8012 fputc ('\t', stream);
8013 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8015 for (i = reg; i < reg + count; i++)
8018 fputs (", ", stream);
8019 asm_fprintf (stream, "d%d", i);
8021 fputs ("}\n", stream);
8026 /* Output the assembly for a store multiple. */
8029 vfp_output_fstmx (rtx * operands)
8036 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8037 p = strlen (pattern);
8039 if (GET_CODE (operands[1]) != REG)
8042 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8043 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8045 p += sprintf (&pattern[p], ", d%d", base + i);
8047 strcpy (&pattern[p], "}");
8049 output_asm_insn (pattern, operands);
8054 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8055 number of bytes pushed. */
8058 vfp_emit_fstmx (int base_reg, int count)
8065 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8066 register pairs are stored by a store multiple insn. We avoid this
8067 by pushing an extra pair. */
8068 if (count == 2 && !arm_arch6)
8070 if (base_reg == LAST_VFP_REGNUM - 3)
8075 /* ??? The frame layout is implementation defined. We describe
8076 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8077 We really need some way of representing the whole block so that the
8078 unwinder can figure it out at runtime. */
8079 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8080 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8082 reg = gen_rtx_REG (DFmode, base_reg);
8086 = gen_rtx_SET (VOIDmode,
8087 gen_rtx_MEM (BLKmode,
8088 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8089 gen_rtx_UNSPEC (BLKmode,
8093 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8094 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8095 GEN_INT (-(count * 8 + 4))));
8096 RTX_FRAME_RELATED_P (tmp) = 1;
8097 XVECEXP (dwarf, 0, 0) = tmp;
8099 tmp = gen_rtx_SET (VOIDmode,
8100 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8102 RTX_FRAME_RELATED_P (tmp) = 1;
8103 XVECEXP (dwarf, 0, 1) = tmp;
8105 for (i = 1; i < count; i++)
8107 reg = gen_rtx_REG (DFmode, base_reg);
8109 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8111 tmp = gen_rtx_SET (VOIDmode,
8112 gen_rtx_MEM (DFmode,
8113 gen_rtx_PLUS (SImode,
8117 RTX_FRAME_RELATED_P (tmp) = 1;
8118 XVECEXP (dwarf, 0, i + 1) = tmp;
8121 par = emit_insn (par);
8122 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8124 RTX_FRAME_RELATED_P (par) = 1;
8126 return count * 8 + 4;
8130 /* Output a 'call' insn. */
8132 output_call (rtx *operands)
8135 abort (); /* Patterns should call blx <reg> directly. */
8137 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8138 if (REGNO (operands[0]) == LR_REGNUM)
8140 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8141 output_asm_insn ("mov%?\t%0, %|lr", operands);
8144 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8146 if (TARGET_INTERWORK || arm_arch4t)
8147 output_asm_insn ("bx%?\t%0", operands);
8149 output_asm_insn ("mov%?\t%|pc, %0", operands);
8154 /* Output a 'call' insn that is a reference in memory. */
8156 output_call_mem (rtx *operands)
8158 if (TARGET_INTERWORK && !arm_arch5)
8160 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8161 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8162 output_asm_insn ("bx%?\t%|ip", operands);
8164 else if (regno_use_in (LR_REGNUM, operands[0]))
8166 /* LR is used in the memory address. We load the address in the
8167 first instruction. It's safe to use IP as the target of the
8168 load since the call will kill it anyway. */
8169 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8171 output_asm_insn ("blx%?%|ip", operands);
8174 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8176 output_asm_insn ("bx%?\t%|ip", operands);
8178 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8183 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8184 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8191 /* Output a move from arm registers to an fpa registers.
8192 OPERANDS[0] is an fpa register.
8193 OPERANDS[1] is the first registers of an arm register pair. */
8195 output_mov_long_double_fpa_from_arm (rtx *operands)
8197 int arm_reg0 = REGNO (operands[1]);
8200 if (arm_reg0 == IP_REGNUM)
8203 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8204 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8205 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8207 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8208 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8213 /* Output a move from an fpa register to arm registers.
8214 OPERANDS[0] is the first registers of an arm register pair.
8215 OPERANDS[1] is an fpa register. */
8217 output_mov_long_double_arm_from_fpa (rtx *operands)
8219 int arm_reg0 = REGNO (operands[0]);
8222 if (arm_reg0 == IP_REGNUM)
8225 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8226 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8227 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8229 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8230 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8234 /* Output a move from arm registers to arm registers of a long double
8235 OPERANDS[0] is the destination.
8236 OPERANDS[1] is the source. */
8238 output_mov_long_double_arm_from_arm (rtx *operands)
8240 /* We have to be careful here because the two might overlap. */
8241 int dest_start = REGNO (operands[0]);
8242 int src_start = REGNO (operands[1]);
8246 if (dest_start < src_start)
8248 for (i = 0; i < 3; i++)
8250 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8251 ops[1] = gen_rtx_REG (SImode, src_start + i);
8252 output_asm_insn ("mov%?\t%0, %1", ops);
8257 for (i = 2; i >= 0; i--)
8259 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8260 ops[1] = gen_rtx_REG (SImode, src_start + i);
8261 output_asm_insn ("mov%?\t%0, %1", ops);
8269 /* Output a move from arm registers to an fpa registers.
8270 OPERANDS[0] is an fpa register.
8271 OPERANDS[1] is the first registers of an arm register pair. */
8273 output_mov_double_fpa_from_arm (rtx *operands)
8275 int arm_reg0 = REGNO (operands[1]);
8278 if (arm_reg0 == IP_REGNUM)
8281 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8282 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8283 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8284 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8288 /* Output a move from an fpa register to arm registers.
8289 OPERANDS[0] is the first registers of an arm register pair.
8290 OPERANDS[1] is an fpa register. */
8292 output_mov_double_arm_from_fpa (rtx *operands)
8294 int arm_reg0 = REGNO (operands[0]);
8297 if (arm_reg0 == IP_REGNUM)
8300 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8301 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8302 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8303 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8307 /* Output a move between double words.
8308 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8309 or MEM<-REG and all MEMs must be offsettable addresses. */
8311 output_move_double (rtx *operands)
8313 enum rtx_code code0 = GET_CODE (operands[0]);
8314 enum rtx_code code1 = GET_CODE (operands[1]);
8319 int reg0 = REGNO (operands[0]);
8321 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8325 int reg1 = REGNO (operands[1]);
8326 if (reg1 == IP_REGNUM)
8329 /* Ensure the second source is not overwritten. */
8330 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8331 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8333 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8335 else if (code1 == CONST_VECTOR)
8337 HOST_WIDE_INT hint = 0;
8339 switch (GET_MODE (operands[1]))
8342 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8343 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8347 if (BYTES_BIG_ENDIAN)
8349 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8351 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8355 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8357 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8360 otherops[1] = GEN_INT (hint);
8363 if (BYTES_BIG_ENDIAN)
8365 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8367 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8371 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8373 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8376 operands[1] = GEN_INT (hint);
8380 if (BYTES_BIG_ENDIAN)
8382 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8384 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8386 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8388 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8392 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8394 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8396 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8398 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8401 otherops[1] = GEN_INT (hint);
8404 if (BYTES_BIG_ENDIAN)
8406 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8408 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8410 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8412 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8416 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8418 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8420 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8422 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8425 operands[1] = GEN_INT (hint);
8431 output_mov_immediate (operands);
8432 output_mov_immediate (otherops);
8434 else if (code1 == CONST_DOUBLE)
8436 if (GET_MODE (operands[1]) == DFmode)
8441 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8442 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8443 otherops[1] = GEN_INT (l[1]);
8444 operands[1] = GEN_INT (l[0]);
8446 else if (GET_MODE (operands[1]) != VOIDmode)
8448 else if (WORDS_BIG_ENDIAN)
8450 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8451 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8455 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8456 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8459 output_mov_immediate (operands);
8460 output_mov_immediate (otherops);
8462 else if (code1 == CONST_INT)
8464 #if HOST_BITS_PER_WIDE_INT > 32
8465 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8466 what the upper word is. */
8467 if (WORDS_BIG_ENDIAN)
8469 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8470 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8474 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8475 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8478 /* Sign extend the intval into the high-order word. */
8479 if (WORDS_BIG_ENDIAN)
8481 otherops[1] = operands[1];
8482 operands[1] = (INTVAL (operands[1]) < 0
8483 ? constm1_rtx : const0_rtx);
8486 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8488 output_mov_immediate (otherops);
8489 output_mov_immediate (operands);
8491 else if (code1 == MEM)
8493 switch (GET_CODE (XEXP (operands[1], 0)))
8496 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8501 abort (); /* Should never happen now. */
8502 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8506 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8510 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8515 abort (); /* Should never happen now. */
8516 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8521 otherops[0] = operands[0];
8522 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8523 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8525 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8527 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8529 /* Registers overlap so split out the increment. */
8530 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8531 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8534 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8538 /* We only allow constant increments, so this is safe. */
8539 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8545 output_asm_insn ("adr%?\t%0, %1", operands);
8546 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8550 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8551 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8553 otherops[0] = operands[0];
8554 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8555 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8557 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8559 if (GET_CODE (otherops[2]) == CONST_INT)
8561 switch ((int) INTVAL (otherops[2]))
8564 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8567 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8570 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8575 && (GET_CODE (otherops[2]) == REG
8576 || (GET_CODE (otherops[2]) == CONST_INT
8577 && INTVAL (otherops[2]) > -256
8578 && INTVAL (otherops[2]) < 256)))
8580 if (reg_overlap_mentioned_p (otherops[0],
8583 /* Swap base and index registers over to
8584 avoid a conflict. */
8585 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8586 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8589 /* If both registers conflict, it will usually
8590 have been fixed by a splitter. */
8591 if (reg_overlap_mentioned_p (otherops[0],
8594 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8595 output_asm_insn ("ldr%?d\t%0, [%1]",
8601 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8606 if (GET_CODE (otherops[2]) == CONST_INT)
8608 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8609 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8611 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8614 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8617 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8619 return "ldm%?ia\t%0, %M0";
8623 otherops[1] = adjust_address (operands[1], SImode, 4);
8624 /* Take care of overlapping base/data reg. */
8625 if (reg_mentioned_p (operands[0], operands[1]))
8627 output_asm_insn ("ldr%?\t%0, %1", otherops);
8628 output_asm_insn ("ldr%?\t%0, %1", operands);
8632 output_asm_insn ("ldr%?\t%0, %1", operands);
8633 output_asm_insn ("ldr%?\t%0, %1", otherops);
8639 abort (); /* Constraints should prevent this. */
8641 else if (code0 == MEM && code1 == REG)
8643 if (REGNO (operands[1]) == IP_REGNUM)
8646 switch (GET_CODE (XEXP (operands[0], 0)))
8649 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8654 abort (); /* Should never happen now. */
8655 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8659 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8663 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8668 abort (); /* Should never happen now. */
8669 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8674 otherops[0] = operands[1];
8675 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8676 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8678 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8679 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8681 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8685 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8686 if (GET_CODE (otherops[2]) == CONST_INT)
8688 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8691 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8695 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8699 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8704 && (GET_CODE (otherops[2]) == REG
8705 || (GET_CODE (otherops[2]) == CONST_INT
8706 && INTVAL (otherops[2]) > -256
8707 && INTVAL (otherops[2]) < 256)))
8709 otherops[0] = operands[1];
8710 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8711 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8717 otherops[0] = adjust_address (operands[0], SImode, 4);
8718 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8719 output_asm_insn ("str%?\t%1, %0", operands);
8720 output_asm_insn ("str%?\t%1, %0", otherops);
8724 /* Constraints should prevent this. */
8731 /* Output an arbitrary MOV reg, #n.
8732 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8734 output_mov_immediate (rtx *operands)
8736 HOST_WIDE_INT n = INTVAL (operands[1]);
8738 /* Try to use one MOV. */
8739 if (const_ok_for_arm (n))
8740 output_asm_insn ("mov%?\t%0, %1", operands);
8742 /* Try to use one MVN. */
8743 else if (const_ok_for_arm (~n))
8745 operands[1] = GEN_INT (~n);
8746 output_asm_insn ("mvn%?\t%0, %1", operands);
8753 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8754 for (i = 0; i < 32; i++)
8758 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8759 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8761 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8767 /* Output an ADD r, s, #n where n may be too big for one instruction.
8768 If adding zero to one register, output nothing. */
8770 output_add_immediate (rtx *operands)
8772 HOST_WIDE_INT n = INTVAL (operands[2]);
8774 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8777 output_multi_immediate (operands,
8778 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8781 output_multi_immediate (operands,
8782 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8789 /* Output a multiple immediate operation.
8790 OPERANDS is the vector of operands referred to in the output patterns.
8791 INSTR1 is the output pattern to use for the first constant.
8792 INSTR2 is the output pattern to use for subsequent constants.
8793 IMMED_OP is the index of the constant slot in OPERANDS.
8794 N is the constant value. */
8796 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8797 int immed_op, HOST_WIDE_INT n)
8799 #if HOST_BITS_PER_WIDE_INT > 32
8805 /* Quick and easy output. */
8806 operands[immed_op] = const0_rtx;
8807 output_asm_insn (instr1, operands);
8812 const char * instr = instr1;
8814 /* Note that n is never zero here (which would give no output). */
8815 for (i = 0; i < 32; i += 2)
8819 operands[immed_op] = GEN_INT (n & (255 << i));
8820 output_asm_insn (instr, operands);
8830 /* Return the appropriate ARM instruction for the operation code.
8831 The returned result should not be overwritten. OP is the rtx of the
8832 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8835 arithmetic_instr (rtx op, int shift_first_arg)
8837 switch (GET_CODE (op))
8843 return shift_first_arg ? "rsb" : "sub";
8859 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8860 for the operation code. The returned result should not be overwritten.
8861 OP is the rtx code of the shift.
8862 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8865 shift_op (rtx op, HOST_WIDE_INT *amountp)
8868 enum rtx_code code = GET_CODE (op);
8870 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8872 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8873 *amountp = INTVAL (XEXP (op, 1));
8896 /* We never have to worry about the amount being other than a
8897 power of 2, since this case can never be reloaded from a reg. */
8899 *amountp = int_log2 (*amountp);
8910 /* This is not 100% correct, but follows from the desire to merge
8911 multiplication by a power of 2 with the recognizer for a
8912 shift. >=32 is not a valid shift for "asl", so we must try and
8913 output a shift that produces the correct arithmetical result.
8914 Using lsr #32 is identical except for the fact that the carry bit
8915 is not set correctly if we set the flags; but we never use the
8916 carry bit from such an operation, so we can ignore that. */
8917 if (code == ROTATERT)
8918 /* Rotate is just modulo 32. */
8920 else if (*amountp != (*amountp & 31))
8927 /* Shifts of 0 are no-ops. */
8935 /* Obtain the shift from the POWER of two. */
8937 static HOST_WIDE_INT
8938 int_log2 (HOST_WIDE_INT power)
8940 HOST_WIDE_INT shift = 0;
8942 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8952 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8953 /bin/as is horribly restrictive. */
8954 #define MAX_ASCII_LEN 51
8957 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8962 fputs ("\t.ascii\t\"", stream);
8964 for (i = 0; i < len; i++)
8968 if (len_so_far >= MAX_ASCII_LEN)
8970 fputs ("\"\n\t.ascii\t\"", stream);
8977 fputs ("\\t", stream);
8982 fputs ("\\f", stream);
8987 fputs ("\\b", stream);
8992 fputs ("\\r", stream);
8996 case TARGET_NEWLINE:
8997 fputs ("\\n", stream);
8999 if ((c >= ' ' && c <= '~')
9001 /* This is a good place for a line break. */
9002 len_so_far = MAX_ASCII_LEN;
9009 putc ('\\', stream);
9014 if (c >= ' ' && c <= '~')
9021 fprintf (stream, "\\%03o", c);
9028 fputs ("\"\n", stream);
9031 /* Compute the register save mask for registers 0 through 12
9032 inclusive. This code is used by arm_compute_save_reg_mask. */
9033 static unsigned long
9034 arm_compute_save_reg0_reg12_mask (void)
9036 unsigned long func_type = arm_current_func_type ();
9037 unsigned int save_reg_mask = 0;
9040 if (IS_INTERRUPT (func_type))
9042 unsigned int max_reg;
9043 /* Interrupt functions must not corrupt any registers,
9044 even call clobbered ones. If this is a leaf function
9045 we can just examine the registers used by the RTL, but
9046 otherwise we have to assume that whatever function is
9047 called might clobber anything, and so we have to save
9048 all the call-clobbered registers as well. */
9049 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9050 /* FIQ handlers have registers r8 - r12 banked, so
9051 we only need to check r0 - r7, Normal ISRs only
9052 bank r14 and r15, so we must check up to r12.
9053 r13 is the stack pointer which is always preserved,
9054 so we do not need to consider it here. */
9059 for (reg = 0; reg <= max_reg; reg++)
9060 if (regs_ever_live[reg]
9061 || (! current_function_is_leaf && call_used_regs [reg]))
9062 save_reg_mask |= (1 << reg);
9066 /* In the normal case we only need to save those registers
9067 which are call saved and which are used by this function. */
9068 for (reg = 0; reg <= 10; reg++)
9069 if (regs_ever_live[reg] && ! call_used_regs [reg])
9070 save_reg_mask |= (1 << reg);
9072 /* Handle the frame pointer as a special case. */
9073 if (! TARGET_APCS_FRAME
9074 && ! frame_pointer_needed
9075 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9076 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9077 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9079 /* If we aren't loading the PIC register,
9080 don't stack it even though it may be live. */
9082 && ! TARGET_SINGLE_PIC_BASE
9083 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
9084 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9087 /* Save registers so the exception handler can modify them. */
9088 if (current_function_calls_eh_return)
9094 reg = EH_RETURN_DATA_REGNO (i);
9095 if (reg == INVALID_REGNUM)
9097 save_reg_mask |= 1 << reg;
9101 return save_reg_mask;
9104 /* Compute a bit mask of which registers need to be
9105 saved on the stack for the current function. */
9107 static unsigned long
9108 arm_compute_save_reg_mask (void)
9110 unsigned int save_reg_mask = 0;
9111 unsigned long func_type = arm_current_func_type ();
9113 if (IS_NAKED (func_type))
9114 /* This should never really happen. */
9117 /* If we are creating a stack frame, then we must save the frame pointer,
9118 IP (which will hold the old stack pointer), LR and the PC. */
9119 if (frame_pointer_needed)
9121 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9126 /* Volatile functions do not return, so there
9127 is no need to save any other registers. */
9128 if (IS_VOLATILE (func_type))
9129 return save_reg_mask;
9131 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9133 /* Decide if we need to save the link register.
9134 Interrupt routines have their own banked link register,
9135 so they never need to save it.
9136 Otherwise if we do not use the link register we do not need to save
9137 it. If we are pushing other registers onto the stack however, we
9138 can save an instruction in the epilogue by pushing the link register
9139 now and then popping it back into the PC. This incurs extra memory
9140 accesses though, so we only do it when optimizing for size, and only
9141 if we know that we will not need a fancy return sequence. */
9142 if (regs_ever_live [LR_REGNUM]
9145 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9146 && !current_function_calls_eh_return))
9147 save_reg_mask |= 1 << LR_REGNUM;
9149 if (cfun->machine->lr_save_eliminated)
9150 save_reg_mask &= ~ (1 << LR_REGNUM);
9152 if (TARGET_REALLY_IWMMXT
9153 && ((bit_count (save_reg_mask)
9154 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9158 /* The total number of registers that are going to be pushed
9159 onto the stack is odd. We need to ensure that the stack
9160 is 64-bit aligned before we start to save iWMMXt registers,
9161 and also before we start to create locals. (A local variable
9162 might be a double or long long which we will load/store using
9163 an iWMMXt instruction). Therefore we need to push another
9164 ARM register, so that the stack will be 64-bit aligned. We
9165 try to avoid using the arg registers (r0 -r3) as they might be
9166 used to pass values in a tail call. */
9167 for (reg = 4; reg <= 12; reg++)
9168 if ((save_reg_mask & (1 << reg)) == 0)
9172 save_reg_mask |= (1 << reg);
9175 cfun->machine->sibcall_blocked = 1;
9176 save_reg_mask |= (1 << 3);
9180 return save_reg_mask;
9184 /* Compute a bit mask of which registers need to be
9185 saved on the stack for the current function. */
9186 static unsigned long
9187 thumb_compute_save_reg_mask (void)
9193 for (reg = 0; reg < 12; reg ++)
9195 if (regs_ever_live[reg] && !call_used_regs[reg])
9199 if (flag_pic && !TARGET_SINGLE_PIC_BASE)
9200 mask |= PIC_OFFSET_TABLE_REGNUM;
9201 if (TARGET_SINGLE_PIC_BASE)
9202 mask &= ~(1 << arm_pic_register);
9204 /* lr will also be pushed if any lo regs are pushed. */
9205 if (mask & 0xff || thumb_force_lr_save ())
9206 mask |= (1 << LR_REGNUM);
9208 /* Make sure we have a low work register if we need one. */
9209 if (((mask & 0xff) == 0 && regs_ever_live[LAST_ARG_REGNUM])
9210 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9211 mask |= 1 << LAST_LO_REGNUM;
9217 /* Return the number of bytes required to save VFP registers. */
9219 arm_get_vfp_saved_size (void)
9226 /* Space for saved VFP registers. */
9227 if (TARGET_HARD_FLOAT && TARGET_VFP)
9230 for (regno = FIRST_VFP_REGNUM;
9231 regno < LAST_VFP_REGNUM;
9234 if ((!regs_ever_live[regno] || call_used_regs[regno])
9235 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9239 /* Workaround ARM10 VFPr1 bug. */
9240 if (count == 2 && !arm_arch6)
9242 saved += count * 8 + 4;
9251 if (count == 2 && !arm_arch6)
9253 saved += count * 8 + 4;
9260 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9261 everything bar the final return instruction. */
9263 output_return_instruction (rtx operand, int really_return, int reverse)
9265 char conditional[10];
9268 unsigned long live_regs_mask;
9269 unsigned long func_type;
9270 arm_stack_offsets *offsets;
9272 func_type = arm_current_func_type ();
9274 if (IS_NAKED (func_type))
9277 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9279 /* If this function was declared non-returning, and we have
9280 found a tail call, then we have to trust that the called
9281 function won't return. */
9286 /* Otherwise, trap an attempted return by aborting. */
9288 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9290 assemble_external_libcall (ops[1]);
9291 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9297 if (current_function_calls_alloca && !really_return)
9300 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9302 return_used_this_function = 1;
9304 live_regs_mask = arm_compute_save_reg_mask ();
9308 const char * return_reg;
9310 /* If we do not have any special requirements for function exit
9311 (eg interworking, or ISR) then we can load the return address
9312 directly into the PC. Otherwise we must load it into LR. */
9314 && ! TARGET_INTERWORK)
9315 return_reg = reg_names[PC_REGNUM];
9317 return_reg = reg_names[LR_REGNUM];
9319 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9321 /* There are three possible reasons for the IP register
9322 being saved. 1) a stack frame was created, in which case
9323 IP contains the old stack pointer, or 2) an ISR routine
9324 corrupted it, or 3) it was saved to align the stack on
9325 iWMMXt. In case 1, restore IP into SP, otherwise just
9327 if (frame_pointer_needed)
9329 live_regs_mask &= ~ (1 << IP_REGNUM);
9330 live_regs_mask |= (1 << SP_REGNUM);
9334 if (! IS_INTERRUPT (func_type)
9335 && ! TARGET_REALLY_IWMMXT)
9340 /* On some ARM architectures it is faster to use LDR rather than
9341 LDM to load a single register. On other architectures, the
9342 cost is the same. In 26 bit mode, or for exception handlers,
9343 we have to use LDM to load the PC so that the CPSR is also
9345 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9347 if (live_regs_mask == (unsigned int)(1 << reg))
9350 if (reg <= LAST_ARM_REGNUM
9351 && (reg != LR_REGNUM
9353 || ! IS_INTERRUPT (func_type)))
9355 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9356 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9363 /* Generate the load multiple instruction to restore the
9364 registers. Note we can get here, even if
9365 frame_pointer_needed is true, but only if sp already
9366 points to the base of the saved core registers. */
9367 if (live_regs_mask & (1 << SP_REGNUM))
9369 unsigned HOST_WIDE_INT stack_adjust;
9371 offsets = arm_get_frame_offsets ();
9372 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9373 if (stack_adjust != 0 && stack_adjust != 4)
9376 if (stack_adjust && arm_arch5)
9377 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9380 /* If we can't use ldmib (SA110 bug), then try to pop r3
9383 live_regs_mask |= 1 << 3;
9384 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9388 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9390 p = instr + strlen (instr);
9392 for (reg = 0; reg <= SP_REGNUM; reg++)
9393 if (live_regs_mask & (1 << reg))
9395 int l = strlen (reg_names[reg]);
9401 memcpy (p, ", ", 2);
9405 memcpy (p, "%|", 2);
9406 memcpy (p + 2, reg_names[reg], l);
9410 if (live_regs_mask & (1 << LR_REGNUM))
9412 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9413 /* If returning from an interrupt, restore the CPSR. */
9414 if (IS_INTERRUPT (func_type))
9421 output_asm_insn (instr, & operand);
9423 /* See if we need to generate an extra instruction to
9424 perform the actual function return. */
9426 && func_type != ARM_FT_INTERWORKED
9427 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9429 /* The return has already been handled
9430 by loading the LR into the PC. */
9437 switch ((int) ARM_FUNC_TYPE (func_type))
9441 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9444 case ARM_FT_INTERWORKED:
9445 sprintf (instr, "bx%s\t%%|lr", conditional);
9448 case ARM_FT_EXCEPTION:
9449 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9453 /* Use bx if it's available. */
9454 if (arm_arch5 || arm_arch4t)
9455 sprintf (instr, "bx%s\t%%|lr", conditional);
9457 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9461 output_asm_insn (instr, & operand);
9467 /* Write the function name into the code section, directly preceding
9468 the function prologue.
9470 Code will be output similar to this:
9472 .ascii "arm_poke_function_name", 0
9475 .word 0xff000000 + (t1 - t0)
9476 arm_poke_function_name
9478 stmfd sp!, {fp, ip, lr, pc}
9481 When performing a stack backtrace, code can inspect the value
9482 of 'pc' stored at 'fp' + 0. If the trace function then looks
9483 at location pc - 12 and the top 8 bits are set, then we know
9484 that there is a function name embedded immediately preceding this
9485 location and has length ((pc[-3]) & 0xff000000).
9487 We assume that pc is declared as a pointer to an unsigned long.
9489 It is of no benefit to output the function name if we are assembling
9490 a leaf function. These function types will not contain a stack
9491 backtrace structure, therefore it is not possible to determine the
9494 arm_poke_function_name (FILE *stream, const char *name)
9496 unsigned long alignlength;
9497 unsigned long length;
9500 length = strlen (name) + 1;
9501 alignlength = ROUND_UP_WORD (length);
9503 ASM_OUTPUT_ASCII (stream, name, length);
9504 ASM_OUTPUT_ALIGN (stream, 2);
9505 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9506 assemble_aligned_integer (UNITS_PER_WORD, x);
9509 /* Place some comments into the assembler stream
9510 describing the current function. */
9512 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9514 unsigned long func_type;
9518 thumb_output_function_prologue (f, frame_size);
9523 if (arm_ccfsm_state || arm_target_insn)
9526 func_type = arm_current_func_type ();
9528 switch ((int) ARM_FUNC_TYPE (func_type))
9533 case ARM_FT_INTERWORKED:
9534 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9537 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9540 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9542 case ARM_FT_EXCEPTION:
9543 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9547 if (IS_NAKED (func_type))
9548 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9550 if (IS_VOLATILE (func_type))
9551 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9553 if (IS_NESTED (func_type))
9554 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9556 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9557 current_function_args_size,
9558 current_function_pretend_args_size, frame_size);
9560 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9561 frame_pointer_needed,
9562 cfun->machine->uses_anonymous_args);
9564 if (cfun->machine->lr_save_eliminated)
9565 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9567 if (current_function_calls_eh_return)
9568 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9570 #ifdef AOF_ASSEMBLER
9572 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9575 return_used_this_function = 0;
9579 arm_output_epilogue (rtx sibling)
9582 unsigned long saved_regs_mask;
9583 unsigned long func_type;
9584 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9585 frame that is $fp + 4 for a non-variadic function. */
9586 int floats_offset = 0;
9588 FILE * f = asm_out_file;
9589 unsigned int lrm_count = 0;
9590 int really_return = (sibling == NULL);
9592 arm_stack_offsets *offsets;
9594 /* If we have already generated the return instruction
9595 then it is futile to generate anything else. */
9596 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9599 func_type = arm_current_func_type ();
9601 if (IS_NAKED (func_type))
9602 /* Naked functions don't have epilogues. */
9605 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9609 /* A volatile function should never return. Call abort. */
9610 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9611 assemble_external_libcall (op);
9612 output_asm_insn ("bl\t%a0", &op);
9617 if (current_function_calls_eh_return
9619 /* If we are throwing an exception, then we really must
9620 be doing a return, so we can't tail-call. */
9623 offsets = arm_get_frame_offsets ();
9624 saved_regs_mask = arm_compute_save_reg_mask ();
9627 lrm_count = bit_count (saved_regs_mask);
9629 floats_offset = offsets->saved_args;
9630 /* Compute how far away the floats will be. */
9631 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9632 if (saved_regs_mask & (1 << reg))
9635 if (frame_pointer_needed)
9637 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9638 int vfp_offset = offsets->frame;
9640 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9642 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9643 if (regs_ever_live[reg] && !call_used_regs[reg])
9645 floats_offset += 12;
9646 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9647 reg, FP_REGNUM, floats_offset - vfp_offset);
9652 start_reg = LAST_FPA_REGNUM;
9654 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9656 if (regs_ever_live[reg] && !call_used_regs[reg])
9658 floats_offset += 12;
9660 /* We can't unstack more than four registers at once. */
9661 if (start_reg - reg == 3)
9663 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9664 reg, FP_REGNUM, floats_offset - vfp_offset);
9665 start_reg = reg - 1;
9670 if (reg != start_reg)
9671 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9672 reg + 1, start_reg - reg,
9673 FP_REGNUM, floats_offset - vfp_offset);
9674 start_reg = reg - 1;
9678 /* Just in case the last register checked also needs unstacking. */
9679 if (reg != start_reg)
9680 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9681 reg + 1, start_reg - reg,
9682 FP_REGNUM, floats_offset - vfp_offset);
9685 if (TARGET_HARD_FLOAT && TARGET_VFP)
9689 /* The fldmx insn does not have base+offset addressing modes,
9690 so we use IP to hold the address. */
9691 saved_size = arm_get_vfp_saved_size ();
9695 floats_offset += saved_size;
9696 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9697 FP_REGNUM, floats_offset - vfp_offset);
9699 start_reg = FIRST_VFP_REGNUM;
9700 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9702 if ((!regs_ever_live[reg] || call_used_regs[reg])
9703 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9705 if (start_reg != reg)
9706 arm_output_fldmx (f, IP_REGNUM,
9707 (start_reg - FIRST_VFP_REGNUM) / 2,
9708 (reg - start_reg) / 2);
9709 start_reg = reg + 2;
9712 if (start_reg != reg)
9713 arm_output_fldmx (f, IP_REGNUM,
9714 (start_reg - FIRST_VFP_REGNUM) / 2,
9715 (reg - start_reg) / 2);
9720 /* The frame pointer is guaranteed to be non-double-word aligned.
9721 This is because it is set to (old_stack_pointer - 4) and the
9722 old_stack_pointer was double word aligned. Thus the offset to
9723 the iWMMXt registers to be loaded must also be non-double-word
9724 sized, so that the resultant address *is* double-word aligned.
9725 We can ignore floats_offset since that was already included in
9726 the live_regs_mask. */
9727 lrm_count += (lrm_count % 2 ? 2 : 1);
9729 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9730 if (regs_ever_live[reg] && !call_used_regs[reg])
9732 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9733 reg, FP_REGNUM, lrm_count * 4);
9738 /* saved_regs_mask should contain the IP, which at the time of stack
9739 frame generation actually contains the old stack pointer. So a
9740 quick way to unwind the stack is just pop the IP register directly
9741 into the stack pointer. */
9742 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9744 saved_regs_mask &= ~ (1 << IP_REGNUM);
9745 saved_regs_mask |= (1 << SP_REGNUM);
9747 /* There are two registers left in saved_regs_mask - LR and PC. We
9748 only need to restore the LR register (the return address), but to
9749 save time we can load it directly into the PC, unless we need a
9750 special function exit sequence, or we are not really returning. */
9752 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9753 && !current_function_calls_eh_return)
9754 /* Delete the LR from the register mask, so that the LR on
9755 the stack is loaded into the PC in the register mask. */
9756 saved_regs_mask &= ~ (1 << LR_REGNUM);
9758 saved_regs_mask &= ~ (1 << PC_REGNUM);
9760 /* We must use SP as the base register, because SP is one of the
9761 registers being restored. If an interrupt or page fault
9762 happens in the ldm instruction, the SP might or might not
9763 have been restored. That would be bad, as then SP will no
9764 longer indicate the safe area of stack, and we can get stack
9765 corruption. Using SP as the base register means that it will
9766 be reset correctly to the original value, should an interrupt
9767 occur. If the stack pointer already points at the right
9768 place, then omit the subtraction. */
9769 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9770 || current_function_calls_alloca)
9771 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9772 4 * bit_count (saved_regs_mask));
9773 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9775 if (IS_INTERRUPT (func_type))
9776 /* Interrupt handlers will have pushed the
9777 IP onto the stack, so restore it now. */
9778 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9782 /* Restore stack pointer if necessary. */
9783 if (offsets->outgoing_args != offsets->saved_regs)
9785 operands[0] = operands[1] = stack_pointer_rtx;
9786 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9787 output_add_immediate (operands);
9790 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9792 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9793 if (regs_ever_live[reg] && !call_used_regs[reg])
9794 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9799 start_reg = FIRST_FPA_REGNUM;
9801 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9803 if (regs_ever_live[reg] && !call_used_regs[reg])
9805 if (reg - start_reg == 3)
9807 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9808 start_reg, SP_REGNUM);
9809 start_reg = reg + 1;
9814 if (reg != start_reg)
9815 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9816 start_reg, reg - start_reg,
9819 start_reg = reg + 1;
9823 /* Just in case the last register checked also needs unstacking. */
9824 if (reg != start_reg)
9825 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9826 start_reg, reg - start_reg, SP_REGNUM);
9829 if (TARGET_HARD_FLOAT && TARGET_VFP)
9831 start_reg = FIRST_VFP_REGNUM;
9832 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9834 if ((!regs_ever_live[reg] || call_used_regs[reg])
9835 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9837 if (start_reg != reg)
9838 arm_output_fldmx (f, SP_REGNUM,
9839 (start_reg - FIRST_VFP_REGNUM) / 2,
9840 (reg - start_reg) / 2);
9841 start_reg = reg + 2;
9844 if (start_reg != reg)
9845 arm_output_fldmx (f, SP_REGNUM,
9846 (start_reg - FIRST_VFP_REGNUM) / 2,
9847 (reg - start_reg) / 2);
9850 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9851 if (regs_ever_live[reg] && !call_used_regs[reg])
9852 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
9854 /* If we can, restore the LR into the PC. */
9855 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9857 && current_function_pretend_args_size == 0
9858 && saved_regs_mask & (1 << LR_REGNUM)
9859 && !current_function_calls_eh_return)
9861 saved_regs_mask &= ~ (1 << LR_REGNUM);
9862 saved_regs_mask |= (1 << PC_REGNUM);
9865 /* Load the registers off the stack. If we only have one register
9866 to load use the LDR instruction - it is faster. */
9867 if (saved_regs_mask == (1 << LR_REGNUM))
9869 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9871 else if (saved_regs_mask)
9873 if (saved_regs_mask & (1 << SP_REGNUM))
9874 /* Note - write back to the stack register is not enabled
9875 (ie "ldmfd sp!..."). We know that the stack pointer is
9876 in the list of registers and if we add writeback the
9877 instruction becomes UNPREDICTABLE. */
9878 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9880 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9883 if (current_function_pretend_args_size)
9885 /* Unwind the pre-pushed regs. */
9886 operands[0] = operands[1] = stack_pointer_rtx;
9887 operands[2] = GEN_INT (current_function_pretend_args_size);
9888 output_add_immediate (operands);
9892 /* We may have already restored PC directly from the stack. */
9893 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
9896 /* Stack adjustment for exception handler. */
9897 if (current_function_calls_eh_return)
9898 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
9899 ARM_EH_STACKADJ_REGNUM);
9901 /* Generate the return instruction. */
9902 switch ((int) ARM_FUNC_TYPE (func_type))
9906 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9909 case ARM_FT_EXCEPTION:
9910 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9913 case ARM_FT_INTERWORKED:
9914 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9918 if (arm_arch5 || arm_arch4t)
9919 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9921 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9929 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9930 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9932 arm_stack_offsets *offsets;
9936 /* ??? Probably not safe to set this here, since it assumes that a
9937 function will be emitted as assembly immediately after we generate
9938 RTL for it. This does not happen for inline functions. */
9939 return_used_this_function = 0;
9943 /* We need to take into account any stack-frame rounding. */
9944 offsets = arm_get_frame_offsets ();
9946 if (use_return_insn (FALSE, NULL)
9947 && return_used_this_function
9948 && offsets->saved_regs != offsets->outgoing_args
9949 && !frame_pointer_needed)
9952 /* Reset the ARM-specific per-function variables. */
9953 after_arm_reorg = 0;
9957 /* Generate and emit an insn that we will recognize as a push_multi.
9958 Unfortunately, since this insn does not reflect very well the actual
9959 semantics of the operation, we need to annotate the insn for the benefit
9960 of DWARF2 frame unwind information. */
9962 emit_multi_reg_push (int mask)
9969 int dwarf_par_index;
9972 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9973 if (mask & (1 << i))
9976 if (num_regs == 0 || num_regs > 16)
9979 /* We don't record the PC in the dwarf frame information. */
9980 num_dwarf_regs = num_regs;
9981 if (mask & (1 << PC_REGNUM))
9984 /* For the body of the insn we are going to generate an UNSPEC in
9985 parallel with several USEs. This allows the insn to be recognized
9986 by the push_multi pattern in the arm.md file. The insn looks
9987 something like this:
9990 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9991 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9992 (use (reg:SI 11 fp))
9993 (use (reg:SI 12 ip))
9994 (use (reg:SI 14 lr))
9995 (use (reg:SI 15 pc))
9998 For the frame note however, we try to be more explicit and actually
9999 show each register being stored into the stack frame, plus a (single)
10000 decrement of the stack pointer. We do it this way in order to be
10001 friendly to the stack unwinding code, which only wants to see a single
10002 stack decrement per instruction. The RTL we generate for the note looks
10003 something like this:
10006 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10007 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10008 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10009 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10010 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10013 This sequence is used both by the code to support stack unwinding for
10014 exceptions handlers and the code to generate dwarf2 frame debugging. */
10016 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10017 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10018 dwarf_par_index = 1;
10020 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10022 if (mask & (1 << i))
10024 reg = gen_rtx_REG (SImode, i);
10026 XVECEXP (par, 0, 0)
10027 = gen_rtx_SET (VOIDmode,
10028 gen_rtx_MEM (BLKmode,
10029 gen_rtx_PRE_DEC (BLKmode,
10030 stack_pointer_rtx)),
10031 gen_rtx_UNSPEC (BLKmode,
10032 gen_rtvec (1, reg),
10033 UNSPEC_PUSH_MULT));
10035 if (i != PC_REGNUM)
10037 tmp = gen_rtx_SET (VOIDmode,
10038 gen_rtx_MEM (SImode, stack_pointer_rtx),
10040 RTX_FRAME_RELATED_P (tmp) = 1;
10041 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10049 for (j = 1, i++; j < num_regs; i++)
10051 if (mask & (1 << i))
10053 reg = gen_rtx_REG (SImode, i);
10055 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10057 if (i != PC_REGNUM)
10059 tmp = gen_rtx_SET (VOIDmode,
10060 gen_rtx_MEM (SImode,
10061 plus_constant (stack_pointer_rtx,
10064 RTX_FRAME_RELATED_P (tmp) = 1;
10065 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10072 par = emit_insn (par);
10074 tmp = gen_rtx_SET (SImode,
10076 gen_rtx_PLUS (SImode,
10078 GEN_INT (-4 * num_regs)));
10079 RTX_FRAME_RELATED_P (tmp) = 1;
10080 XVECEXP (dwarf, 0, 0) = tmp;
10082 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10088 emit_sfm (int base_reg, int count)
10095 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10096 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10098 reg = gen_rtx_REG (XFmode, base_reg++);
10100 XVECEXP (par, 0, 0)
10101 = gen_rtx_SET (VOIDmode,
10102 gen_rtx_MEM (BLKmode,
10103 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
10104 gen_rtx_UNSPEC (BLKmode,
10105 gen_rtvec (1, reg),
10106 UNSPEC_PUSH_MULT));
10107 tmp = gen_rtx_SET (VOIDmode,
10108 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
10109 RTX_FRAME_RELATED_P (tmp) = 1;
10110 XVECEXP (dwarf, 0, 1) = tmp;
10112 for (i = 1; i < count; i++)
10114 reg = gen_rtx_REG (XFmode, base_reg++);
10115 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10117 tmp = gen_rtx_SET (VOIDmode,
10118 gen_rtx_MEM (XFmode,
10119 plus_constant (stack_pointer_rtx,
10122 RTX_FRAME_RELATED_P (tmp) = 1;
10123 XVECEXP (dwarf, 0, i + 1) = tmp;
10126 tmp = gen_rtx_SET (VOIDmode,
10128 gen_rtx_PLUS (SImode,
10130 GEN_INT (-12 * count)));
10131 RTX_FRAME_RELATED_P (tmp) = 1;
10132 XVECEXP (dwarf, 0, 0) = tmp;
10134 par = emit_insn (par);
10135 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10141 /* Return true if the current function needs to save/restore LR. */
10144 thumb_force_lr_save (void)
10146 return !cfun->machine->lr_save_eliminated
10147 && (!leaf_function_p ()
10148 || thumb_far_jump_used_p ()
10149 || regs_ever_live [LR_REGNUM]);
10153 /* Compute the distance from register FROM to register TO.
10154 These can be the arg pointer (26), the soft frame pointer (25),
10155 the stack pointer (13) or the hard frame pointer (11).
10156 In thumb mode r7 is used as the soft frame pointer, if needed.
10157 Typical stack layout looks like this:
10159 old stack pointer -> | |
10162 | | saved arguments for
10163 | | vararg functions
10166 hard FP & arg pointer -> | | \
10174 soft frame pointer -> | | /
10184 current stack pointer -> | | /
10187 For a given function some or all of these stack components
10188 may not be needed, giving rise to the possibility of
10189 eliminating some of the registers.
10191 The values returned by this function must reflect the behavior
10192 of arm_expand_prologue() and arm_compute_save_reg_mask().
10194 The sign of the number returned reflects the direction of stack
10195 growth, so the values are positive for all eliminations except
10196 from the soft frame pointer to the hard frame pointer.
10198 SFP may point just inside the local variables block to ensure correct
10202 /* Calculate stack offsets. These are used to calculate register elimination
10203 offsets and in prologue/epilogue code. */
10205 static arm_stack_offsets *
10206 arm_get_frame_offsets (void)
10208 struct arm_stack_offsets *offsets;
10209 unsigned long func_type;
10212 HOST_WIDE_INT frame_size;
10214 offsets = &cfun->machine->stack_offsets;
10216 /* We need to know if we are a leaf function. Unfortunately, it
10217 is possible to be called after start_sequence has been called,
10218 which causes get_insns to return the insns for the sequence,
10219 not the function, which will cause leaf_function_p to return
10220 the incorrect result.
10222 to know about leaf functions once reload has completed, and the
10223 frame size cannot be changed after that time, so we can safely
10224 use the cached value. */
10226 if (reload_completed)
10229 /* Initially this is the size of the local variables. It will translated
10230 into an offset once we have determined the size of preceding data. */
10231 frame_size = ROUND_UP_WORD (get_frame_size ());
10233 leaf = leaf_function_p ();
10235 /* Space for variadic functions. */
10236 offsets->saved_args = current_function_pretend_args_size;
10238 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10242 unsigned int regno;
10244 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10246 /* We know that SP will be doubleword aligned on entry, and we must
10247 preserve that condition at any subroutine call. We also require the
10248 soft frame pointer to be doubleword aligned. */
10250 if (TARGET_REALLY_IWMMXT)
10252 /* Check for the call-saved iWMMXt registers. */
10253 for (regno = FIRST_IWMMXT_REGNUM;
10254 regno <= LAST_IWMMXT_REGNUM;
10256 if (regs_ever_live [regno] && ! call_used_regs [regno])
10260 func_type = arm_current_func_type ();
10261 if (! IS_VOLATILE (func_type))
10263 /* Space for saved FPA registers. */
10264 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10265 if (regs_ever_live[regno] && ! call_used_regs[regno])
10268 /* Space for saved VFP registers. */
10269 if (TARGET_HARD_FLOAT && TARGET_VFP)
10270 saved += arm_get_vfp_saved_size ();
10273 else /* TARGET_THUMB */
10275 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10276 if (TARGET_BACKTRACE)
10280 /* Saved registers include the stack frame. */
10281 offsets->saved_regs = offsets->saved_args + saved;
10282 offsets->soft_frame = offsets->saved_regs;
10283 /* A leaf function does not need any stack alignment if it has nothing
10285 if (leaf && frame_size == 0)
10287 offsets->outgoing_args = offsets->soft_frame;
10291 /* Ensure SFP has the correct alignment. */
10292 if (ARM_DOUBLEWORD_ALIGN
10293 && (offsets->soft_frame & 7))
10294 offsets->soft_frame += 4;
10296 offsets->outgoing_args = offsets->soft_frame + frame_size
10297 + current_function_outgoing_args_size;
10299 if (ARM_DOUBLEWORD_ALIGN)
10301 /* Ensure SP remains doubleword aligned. */
10302 if (offsets->outgoing_args & 7)
10303 offsets->outgoing_args += 4;
10304 if (offsets->outgoing_args & 7)
10312 /* Calculate the relative offsets for the different stack pointers. Positive
10313 offsets are in the direction of stack growth. */
10316 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10318 arm_stack_offsets *offsets;
10320 offsets = arm_get_frame_offsets ();
10322 /* OK, now we have enough information to compute the distances.
10323 There must be an entry in these switch tables for each pair
10324 of registers in ELIMINABLE_REGS, even if some of the entries
10325 seem to be redundant or useless. */
10328 case ARG_POINTER_REGNUM:
10331 case THUMB_HARD_FRAME_POINTER_REGNUM:
10334 case FRAME_POINTER_REGNUM:
10335 /* This is the reverse of the soft frame pointer
10336 to hard frame pointer elimination below. */
10337 return offsets->soft_frame - offsets->saved_args;
10339 case ARM_HARD_FRAME_POINTER_REGNUM:
10340 /* If there is no stack frame then the hard
10341 frame pointer and the arg pointer coincide. */
10342 if (offsets->frame == offsets->saved_regs)
10344 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10345 return (frame_pointer_needed
10346 && cfun->static_chain_decl != NULL
10347 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10349 case STACK_POINTER_REGNUM:
10350 /* If nothing has been pushed on the stack at all
10351 then this will return -4. This *is* correct! */
10352 return offsets->outgoing_args - (offsets->saved_args + 4);
10359 case FRAME_POINTER_REGNUM:
10362 case THUMB_HARD_FRAME_POINTER_REGNUM:
10365 case ARM_HARD_FRAME_POINTER_REGNUM:
10366 /* The hard frame pointer points to the top entry in the
10367 stack frame. The soft frame pointer to the bottom entry
10368 in the stack frame. If there is no stack frame at all,
10369 then they are identical. */
10371 return offsets->frame - offsets->soft_frame;
10373 case STACK_POINTER_REGNUM:
10374 return offsets->outgoing_args - offsets->soft_frame;
10382 /* You cannot eliminate from the stack pointer.
10383 In theory you could eliminate from the hard frame
10384 pointer to the stack pointer, but this will never
10385 happen, since if a stack frame is not needed the
10386 hard frame pointer will never be used. */
10392 /* Generate the prologue instructions for entry into an ARM function. */
10394 arm_expand_prologue (void)
10400 unsigned long live_regs_mask;
10401 unsigned long func_type;
10403 int saved_pretend_args = 0;
10404 int saved_regs = 0;
10405 unsigned int args_to_push;
10406 arm_stack_offsets *offsets;
10408 func_type = arm_current_func_type ();
10410 /* Naked functions don't have prologues. */
10411 if (IS_NAKED (func_type))
10414 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10415 args_to_push = current_function_pretend_args_size;
10417 /* Compute which register we will have to save onto the stack. */
10418 live_regs_mask = arm_compute_save_reg_mask ();
10420 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10422 if (frame_pointer_needed)
10424 if (IS_INTERRUPT (func_type))
10426 /* Interrupt functions must not corrupt any registers.
10427 Creating a frame pointer however, corrupts the IP
10428 register, so we must push it first. */
10429 insn = emit_multi_reg_push (1 << IP_REGNUM);
10431 /* Do not set RTX_FRAME_RELATED_P on this insn.
10432 The dwarf stack unwinding code only wants to see one
10433 stack decrement per function, and this is not it. If
10434 this instruction is labeled as being part of the frame
10435 creation sequence then dwarf2out_frame_debug_expr will
10436 abort when it encounters the assignment of IP to FP
10437 later on, since the use of SP here establishes SP as
10438 the CFA register and not IP.
10440 Anyway this instruction is not really part of the stack
10441 frame creation although it is part of the prologue. */
10443 else if (IS_NESTED (func_type))
10445 /* The Static chain register is the same as the IP register
10446 used as a scratch register during stack frame creation.
10447 To get around this need to find somewhere to store IP
10448 whilst the frame is being created. We try the following
10451 1. The last argument register.
10452 2. A slot on the stack above the frame. (This only
10453 works if the function is not a varargs function).
10454 3. Register r3, after pushing the argument registers
10457 Note - we only need to tell the dwarf2 backend about the SP
10458 adjustment in the second variant; the static chain register
10459 doesn't need to be unwound, as it doesn't contain a value
10460 inherited from the caller. */
10462 if (regs_ever_live[3] == 0)
10464 insn = gen_rtx_REG (SImode, 3);
10465 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10466 insn = emit_insn (insn);
10468 else if (args_to_push == 0)
10471 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10472 insn = gen_rtx_MEM (SImode, insn);
10473 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10474 insn = emit_insn (insn);
10478 /* Just tell the dwarf backend that we adjusted SP. */
10479 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10480 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10481 GEN_INT (-fp_offset)));
10482 RTX_FRAME_RELATED_P (insn) = 1;
10483 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10484 dwarf, REG_NOTES (insn));
10488 /* Store the args on the stack. */
10489 if (cfun->machine->uses_anonymous_args)
10490 insn = emit_multi_reg_push
10491 ((0xf0 >> (args_to_push / 4)) & 0xf);
10494 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10495 GEN_INT (- args_to_push)));
10497 RTX_FRAME_RELATED_P (insn) = 1;
10499 saved_pretend_args = 1;
10500 fp_offset = args_to_push;
10503 /* Now reuse r3 to preserve IP. */
10504 insn = gen_rtx_REG (SImode, 3);
10505 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10506 (void) emit_insn (insn);
10512 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10513 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10516 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10518 insn = emit_insn (insn);
10519 RTX_FRAME_RELATED_P (insn) = 1;
10524 /* Push the argument registers, or reserve space for them. */
10525 if (cfun->machine->uses_anonymous_args)
10526 insn = emit_multi_reg_push
10527 ((0xf0 >> (args_to_push / 4)) & 0xf);
10530 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10531 GEN_INT (- args_to_push)));
10532 RTX_FRAME_RELATED_P (insn) = 1;
10535 /* If this is an interrupt service routine, and the link register
10536 is going to be pushed, and we are not creating a stack frame,
10537 (which would involve an extra push of IP and a pop in the epilogue)
10538 subtracting four from LR now will mean that the function return
10539 can be done with a single instruction. */
10540 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10541 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10542 && ! frame_pointer_needed)
10543 emit_insn (gen_rtx_SET (SImode,
10544 gen_rtx_REG (SImode, LR_REGNUM),
10545 gen_rtx_PLUS (SImode,
10546 gen_rtx_REG (SImode, LR_REGNUM),
10549 if (live_regs_mask)
10551 insn = emit_multi_reg_push (live_regs_mask);
10552 saved_regs += bit_count (live_regs_mask) * 4;
10553 RTX_FRAME_RELATED_P (insn) = 1;
10557 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10558 if (regs_ever_live[reg] && ! call_used_regs [reg])
10560 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10561 insn = gen_rtx_MEM (V2SImode, insn);
10562 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10563 gen_rtx_REG (V2SImode, reg)));
10564 RTX_FRAME_RELATED_P (insn) = 1;
10568 if (! IS_VOLATILE (func_type))
10572 /* Save any floating point call-saved registers used by this
10574 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10576 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10577 if (regs_ever_live[reg] && !call_used_regs[reg])
10579 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10580 insn = gen_rtx_MEM (XFmode, insn);
10581 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10582 gen_rtx_REG (XFmode, reg)));
10583 RTX_FRAME_RELATED_P (insn) = 1;
10589 start_reg = LAST_FPA_REGNUM;
10591 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10593 if (regs_ever_live[reg] && !call_used_regs[reg])
10595 if (start_reg - reg == 3)
10597 insn = emit_sfm (reg, 4);
10598 RTX_FRAME_RELATED_P (insn) = 1;
10600 start_reg = reg - 1;
10605 if (start_reg != reg)
10607 insn = emit_sfm (reg + 1, start_reg - reg);
10608 RTX_FRAME_RELATED_P (insn) = 1;
10609 saved_regs += (start_reg - reg) * 12;
10611 start_reg = reg - 1;
10615 if (start_reg != reg)
10617 insn = emit_sfm (reg + 1, start_reg - reg);
10618 saved_regs += (start_reg - reg) * 12;
10619 RTX_FRAME_RELATED_P (insn) = 1;
10622 if (TARGET_HARD_FLOAT && TARGET_VFP)
10624 start_reg = FIRST_VFP_REGNUM;
10626 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10628 if ((!regs_ever_live[reg] || call_used_regs[reg])
10629 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10631 if (start_reg != reg)
10632 saved_regs += vfp_emit_fstmx (start_reg,
10633 (reg - start_reg) / 2);
10634 start_reg = reg + 2;
10637 if (start_reg != reg)
10638 saved_regs += vfp_emit_fstmx (start_reg,
10639 (reg - start_reg) / 2);
10643 if (frame_pointer_needed)
10645 /* Create the new frame pointer. */
10646 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10647 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10648 RTX_FRAME_RELATED_P (insn) = 1;
10650 if (IS_NESTED (func_type))
10652 /* Recover the static chain register. */
10653 if (regs_ever_live [3] == 0
10654 || saved_pretend_args)
10655 insn = gen_rtx_REG (SImode, 3);
10656 else /* if (current_function_pretend_args_size == 0) */
10658 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10660 insn = gen_rtx_MEM (SImode, insn);
10663 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10664 /* Add a USE to stop propagate_one_insn() from barfing. */
10665 emit_insn (gen_prologue_use (ip_rtx));
10669 offsets = arm_get_frame_offsets ();
10670 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10672 /* This add can produce multiple insns for a large constant, so we
10673 need to get tricky. */
10674 rtx last = get_last_insn ();
10676 amount = GEN_INT (offsets->saved_args + saved_regs
10677 - offsets->outgoing_args);
10679 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10683 last = last ? NEXT_INSN (last) : get_insns ();
10684 RTX_FRAME_RELATED_P (last) = 1;
10686 while (last != insn);
10688 /* If the frame pointer is needed, emit a special barrier that
10689 will prevent the scheduler from moving stores to the frame
10690 before the stack adjustment. */
10691 if (frame_pointer_needed)
10692 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10693 hard_frame_pointer_rtx));
10696 /* If we are profiling, make sure no instructions are scheduled before
10697 the call to mcount. Similarly if the user has requested no
10698 scheduling in the prolog. */
10699 if (current_function_profile || TARGET_NO_SCHED_PRO)
10700 emit_insn (gen_blockage ());
10702 /* If the link register is being kept alive, with the return address in it,
10703 then make sure that it does not get reused by the ce2 pass. */
10704 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10706 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10707 cfun->machine->lr_save_eliminated = 1;
10711 /* If CODE is 'd', then the X is a condition operand and the instruction
10712 should only be executed if the condition is true.
10713 if CODE is 'D', then the X is a condition operand and the instruction
10714 should only be executed if the condition is false: however, if the mode
10715 of the comparison is CCFPEmode, then always execute the instruction -- we
10716 do this because in these circumstances !GE does not necessarily imply LT;
10717 in these cases the instruction pattern will take care to make sure that
10718 an instruction containing %d will follow, thereby undoing the effects of
10719 doing this instruction unconditionally.
10720 If CODE is 'N' then X is a floating point operand that must be negated
10722 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10723 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10725 arm_print_operand (FILE *stream, rtx x, int code)
10730 fputs (ASM_COMMENT_START, stream);
10734 fputs (user_label_prefix, stream);
10738 fputs (REGISTER_PREFIX, stream);
10742 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10744 if (TARGET_THUMB || current_insn_predicate != NULL)
10747 fputs (arm_condition_codes[arm_current_cc], stream);
10749 else if (current_insn_predicate)
10751 enum arm_cond_code code;
10756 code = get_arm_condition_code (current_insn_predicate);
10757 fputs (arm_condition_codes[code], stream);
10764 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10765 r = REAL_VALUE_NEGATE (r);
10766 fprintf (stream, "%s", fp_const_from_val (&r));
10771 if (GET_CODE (x) == CONST_INT)
10774 val = ARM_SIGN_EXTEND (~INTVAL (x));
10775 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10779 putc ('~', stream);
10780 output_addr_const (stream, x);
10785 fprintf (stream, "%s", arithmetic_instr (x, 1));
10788 /* Truncate Cirrus shift counts. */
10790 if (GET_CODE (x) == CONST_INT)
10792 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10795 arm_print_operand (stream, x, 0);
10799 fprintf (stream, "%s", arithmetic_instr (x, 0));
10805 const char * shift = shift_op (x, &val);
10809 fprintf (stream, ", %s ", shift_op (x, &val));
10811 arm_print_operand (stream, XEXP (x, 1), 0);
10813 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10818 /* An explanation of the 'Q', 'R' and 'H' register operands:
10820 In a pair of registers containing a DI or DF value the 'Q'
10821 operand returns the register number of the register containing
10822 the least significant part of the value. The 'R' operand returns
10823 the register number of the register containing the most
10824 significant part of the value.
10826 The 'H' operand returns the higher of the two register numbers.
10827 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10828 same as the 'Q' operand, since the most significant part of the
10829 value is held in the lower number register. The reverse is true
10830 on systems where WORDS_BIG_ENDIAN is false.
10832 The purpose of these operands is to distinguish between cases
10833 where the endian-ness of the values is important (for example
10834 when they are added together), and cases where the endian-ness
10835 is irrelevant, but the order of register operations is important.
10836 For example when loading a value from memory into a register
10837 pair, the endian-ness does not matter. Provided that the value
10838 from the lower memory address is put into the lower numbered
10839 register, and the value from the higher address is put into the
10840 higher numbered register, the load will work regardless of whether
10841 the value being loaded is big-wordian or little-wordian. The
10842 order of the two register loads can matter however, if the address
10843 of the memory location is actually held in one of the registers
10844 being overwritten by the load. */
10846 if (REGNO (x) > LAST_ARM_REGNUM)
10848 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10852 if (REGNO (x) > LAST_ARM_REGNUM)
10854 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10858 if (REGNO (x) > LAST_ARM_REGNUM)
10860 asm_fprintf (stream, "%r", REGNO (x) + 1);
10864 asm_fprintf (stream, "%r",
10865 GET_CODE (XEXP (x, 0)) == REG
10866 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10870 asm_fprintf (stream, "{%r-%r}",
10872 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10876 /* CONST_TRUE_RTX means always -- that's the default. */
10877 if (x == const_true_rtx)
10880 fputs (arm_condition_codes[get_arm_condition_code (x)],
10885 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10886 want to do that. */
10887 if (x == const_true_rtx)
10890 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10891 (get_arm_condition_code (x))],
10895 /* Cirrus registers can be accessed in a variety of ways:
10896 single floating point (f)
10897 double floating point (d)
10899 64bit integer (dx). */
10900 case 'W': /* Cirrus register in F mode. */
10901 case 'X': /* Cirrus register in D mode. */
10902 case 'Y': /* Cirrus register in FX mode. */
10903 case 'Z': /* Cirrus register in DX mode. */
10904 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10907 fprintf (stream, "mv%s%s",
10909 : code == 'X' ? "d"
10910 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10914 /* Print cirrus register in the mode specified by the register's mode. */
10917 int mode = GET_MODE (x);
10919 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10922 fprintf (stream, "mv%s%s",
10923 mode == DFmode ? "d"
10924 : mode == SImode ? "fx"
10925 : mode == DImode ? "dx"
10926 : "f", reg_names[REGNO (x)] + 2);
10932 if (GET_CODE (x) != REG
10933 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10934 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10935 /* Bad value for wCG register number. */
10938 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10941 /* Print an iWMMXt control register name. */
10943 if (GET_CODE (x) != CONST_INT
10945 || INTVAL (x) >= 16)
10946 /* Bad value for wC register number. */
10950 static const char * wc_reg_names [16] =
10952 "wCID", "wCon", "wCSSF", "wCASF",
10953 "wC4", "wC5", "wC6", "wC7",
10954 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10955 "wC12", "wC13", "wC14", "wC15"
10958 fprintf (stream, wc_reg_names [INTVAL (x)]);
10962 /* Print a VFP double precision register name. */
10965 int mode = GET_MODE (x);
10968 if (mode != DImode && mode != DFmode)
10971 if (GET_CODE (x) != REG
10972 || !IS_VFP_REGNUM (REGNO (x)))
10975 num = REGNO(x) - FIRST_VFP_REGNUM;
10979 fprintf (stream, "d%d", num >> 1);
10987 if (GET_CODE (x) == REG)
10988 asm_fprintf (stream, "%r", REGNO (x));
10989 else if (GET_CODE (x) == MEM)
10991 output_memory_reference_mode = GET_MODE (x);
10992 output_address (XEXP (x, 0));
10994 else if (GET_CODE (x) == CONST_DOUBLE)
10995 fprintf (stream, "#%s", fp_immediate_constant (x));
10996 else if (GET_CODE (x) == NEG)
10997 abort (); /* This should never happen now. */
11000 fputc ('#', stream);
11001 output_addr_const (stream, x);
11006 #ifndef AOF_ASSEMBLER
11007 /* Target hook for assembling integer objects. The ARM version needs to
11008 handle word-sized values specially. */
11010 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11012 if (size == UNITS_PER_WORD && aligned_p)
11014 fputs ("\t.word\t", asm_out_file);
11015 output_addr_const (asm_out_file, x);
11017 /* Mark symbols as position independent. We only do this in the
11018 .text segment, not in the .data segment. */
11019 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11020 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11022 if (GET_CODE (x) == SYMBOL_REF
11023 && (CONSTANT_POOL_ADDRESS_P (x)
11024 || SYMBOL_REF_LOCAL_P (x)))
11025 fputs ("(GOTOFF)", asm_out_file);
11026 else if (GET_CODE (x) == LABEL_REF)
11027 fputs ("(GOTOFF)", asm_out_file);
11029 fputs ("(GOT)", asm_out_file);
11031 fputc ('\n', asm_out_file);
11035 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
11039 if (GET_CODE (x) != CONST_VECTOR)
11042 units = CONST_VECTOR_NUNITS (x);
11044 switch (GET_MODE (x))
11046 case V2SImode: size = 4; break;
11047 case V4HImode: size = 2; break;
11048 case V8QImode: size = 1; break;
11053 for (i = 0; i < units; i++)
11057 elt = CONST_VECTOR_ELT (x, i);
11059 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11065 return default_assemble_integer (x, size, aligned_p);
11069 /* A finite state machine takes care of noticing whether or not instructions
11070 can be conditionally executed, and thus decrease execution time and code
11071 size by deleting branch instructions. The fsm is controlled by
11072 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11074 /* The state of the fsm controlling condition codes are:
11075 0: normal, do nothing special
11076 1: make ASM_OUTPUT_OPCODE not output this instruction
11077 2: make ASM_OUTPUT_OPCODE not output this instruction
11078 3: make instructions conditional
11079 4: make instructions conditional
11081 State transitions (state->state by whom under condition):
11082 0 -> 1 final_prescan_insn if the `target' is a label
11083 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11084 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11085 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11086 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11087 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11088 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11089 (the target insn is arm_target_insn).
11091 If the jump clobbers the conditions then we use states 2 and 4.
11093 A similar thing can be done with conditional return insns.
11095 XXX In case the `target' is an unconditional branch, this conditionalising
11096 of the instructions always reduces code size, but not always execution
11097 time. But then, I want to reduce the code size to somewhere near what
11098 /bin/cc produces. */
11100 /* Returns the index of the ARM condition code string in
11101 `arm_condition_codes'. COMPARISON should be an rtx like
11102 `(eq (...) (...))'. */
11103 static enum arm_cond_code
11104 get_arm_condition_code (rtx comparison)
11106 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11108 enum rtx_code comp_code = GET_CODE (comparison);
11110 if (GET_MODE_CLASS (mode) != MODE_CC)
11111 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11112 XEXP (comparison, 1));
11116 case CC_DNEmode: code = ARM_NE; goto dominance;
11117 case CC_DEQmode: code = ARM_EQ; goto dominance;
11118 case CC_DGEmode: code = ARM_GE; goto dominance;
11119 case CC_DGTmode: code = ARM_GT; goto dominance;
11120 case CC_DLEmode: code = ARM_LE; goto dominance;
11121 case CC_DLTmode: code = ARM_LT; goto dominance;
11122 case CC_DGEUmode: code = ARM_CS; goto dominance;
11123 case CC_DGTUmode: code = ARM_HI; goto dominance;
11124 case CC_DLEUmode: code = ARM_LS; goto dominance;
11125 case CC_DLTUmode: code = ARM_CC;
11128 if (comp_code != EQ && comp_code != NE)
11131 if (comp_code == EQ)
11132 return ARM_INVERSE_CONDITION_CODE (code);
11138 case NE: return ARM_NE;
11139 case EQ: return ARM_EQ;
11140 case GE: return ARM_PL;
11141 case LT: return ARM_MI;
11148 case NE: return ARM_NE;
11149 case EQ: return ARM_EQ;
11156 case NE: return ARM_MI;
11157 case EQ: return ARM_PL;
11163 /* These encodings assume that AC=1 in the FPA system control
11164 byte. This allows us to handle all cases except UNEQ and
11168 case GE: return ARM_GE;
11169 case GT: return ARM_GT;
11170 case LE: return ARM_LS;
11171 case LT: return ARM_MI;
11172 case NE: return ARM_NE;
11173 case EQ: return ARM_EQ;
11174 case ORDERED: return ARM_VC;
11175 case UNORDERED: return ARM_VS;
11176 case UNLT: return ARM_LT;
11177 case UNLE: return ARM_LE;
11178 case UNGT: return ARM_HI;
11179 case UNGE: return ARM_PL;
11180 /* UNEQ and LTGT do not have a representation. */
11181 case UNEQ: /* Fall through. */
11182 case LTGT: /* Fall through. */
11189 case NE: return ARM_NE;
11190 case EQ: return ARM_EQ;
11191 case GE: return ARM_LE;
11192 case GT: return ARM_LT;
11193 case LE: return ARM_GE;
11194 case LT: return ARM_GT;
11195 case GEU: return ARM_LS;
11196 case GTU: return ARM_CC;
11197 case LEU: return ARM_CS;
11198 case LTU: return ARM_HI;
11205 case LTU: return ARM_CS;
11206 case GEU: return ARM_CC;
11213 case NE: return ARM_NE;
11214 case EQ: return ARM_EQ;
11215 case GE: return ARM_GE;
11216 case GT: return ARM_GT;
11217 case LE: return ARM_LE;
11218 case LT: return ARM_LT;
11219 case GEU: return ARM_CS;
11220 case GTU: return ARM_HI;
11221 case LEU: return ARM_LS;
11222 case LTU: return ARM_CC;
11233 arm_final_prescan_insn (rtx insn)
11235 /* BODY will hold the body of INSN. */
11236 rtx body = PATTERN (insn);
11238 /* This will be 1 if trying to repeat the trick, and things need to be
11239 reversed if it appears to fail. */
11242 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11243 taken are clobbered, even if the rtl suggests otherwise. It also
11244 means that we have to grub around within the jump expression to find
11245 out what the conditions are when the jump isn't taken. */
11246 int jump_clobbers = 0;
11248 /* If we start with a return insn, we only succeed if we find another one. */
11249 int seeking_return = 0;
11251 /* START_INSN will hold the insn from where we start looking. This is the
11252 first insn after the following code_label if REVERSE is true. */
11253 rtx start_insn = insn;
11255 /* If in state 4, check if the target branch is reached, in order to
11256 change back to state 0. */
11257 if (arm_ccfsm_state == 4)
11259 if (insn == arm_target_insn)
11261 arm_target_insn = NULL;
11262 arm_ccfsm_state = 0;
11267 /* If in state 3, it is possible to repeat the trick, if this insn is an
11268 unconditional branch to a label, and immediately following this branch
11269 is the previous target label which is only used once, and the label this
11270 branch jumps to is not too far off. */
11271 if (arm_ccfsm_state == 3)
11273 if (simplejump_p (insn))
11275 start_insn = next_nonnote_insn (start_insn);
11276 if (GET_CODE (start_insn) == BARRIER)
11278 /* XXX Isn't this always a barrier? */
11279 start_insn = next_nonnote_insn (start_insn);
11281 if (GET_CODE (start_insn) == CODE_LABEL
11282 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11283 && LABEL_NUSES (start_insn) == 1)
11288 else if (GET_CODE (body) == RETURN)
11290 start_insn = next_nonnote_insn (start_insn);
11291 if (GET_CODE (start_insn) == BARRIER)
11292 start_insn = next_nonnote_insn (start_insn);
11293 if (GET_CODE (start_insn) == CODE_LABEL
11294 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11295 && LABEL_NUSES (start_insn) == 1)
11298 seeking_return = 1;
11307 if (arm_ccfsm_state != 0 && !reverse)
11309 if (GET_CODE (insn) != JUMP_INSN)
11312 /* This jump might be paralleled with a clobber of the condition codes
11313 the jump should always come first */
11314 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11315 body = XVECEXP (body, 0, 0);
11318 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11319 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11322 int fail = FALSE, succeed = FALSE;
11323 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11324 int then_not_else = TRUE;
11325 rtx this_insn = start_insn, label = 0;
11327 /* If the jump cannot be done with one instruction, we cannot
11328 conditionally execute the instruction in the inverse case. */
11329 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11335 /* Register the insn jumped to. */
11338 if (!seeking_return)
11339 label = XEXP (SET_SRC (body), 0);
11341 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11342 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11343 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11345 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11346 then_not_else = FALSE;
11348 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11349 seeking_return = 1;
11350 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11352 seeking_return = 1;
11353 then_not_else = FALSE;
11358 /* See how many insns this branch skips, and what kind of insns. If all
11359 insns are okay, and the label or unconditional branch to the same
11360 label is not too far away, succeed. */
11361 for (insns_skipped = 0;
11362 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11366 this_insn = next_nonnote_insn (this_insn);
11370 switch (GET_CODE (this_insn))
11373 /* Succeed if it is the target label, otherwise fail since
11374 control falls in from somewhere else. */
11375 if (this_insn == label)
11379 arm_ccfsm_state = 2;
11380 this_insn = next_nonnote_insn (this_insn);
11383 arm_ccfsm_state = 1;
11391 /* Succeed if the following insn is the target label.
11393 If return insns are used then the last insn in a function
11394 will be a barrier. */
11395 this_insn = next_nonnote_insn (this_insn);
11396 if (this_insn && this_insn == label)
11400 arm_ccfsm_state = 2;
11401 this_insn = next_nonnote_insn (this_insn);
11404 arm_ccfsm_state = 1;
11412 /* The AAPCS says that conditional calls should not be
11413 used since they make interworking inefficient (the
11414 linker can't transform BL<cond> into BLX). That's
11415 only a problem if the machine has BLX. */
11422 /* Succeed if the following insn is the target label, or
11423 if the following two insns are a barrier and the
11425 this_insn = next_nonnote_insn (this_insn);
11426 if (this_insn && GET_CODE (this_insn) == BARRIER)
11427 this_insn = next_nonnote_insn (this_insn);
11429 if (this_insn && this_insn == label
11430 && insns_skipped < max_insns_skipped)
11434 arm_ccfsm_state = 2;
11435 this_insn = next_nonnote_insn (this_insn);
11438 arm_ccfsm_state = 1;
11446 /* If this is an unconditional branch to the same label, succeed.
11447 If it is to another label, do nothing. If it is conditional,
11449 /* XXX Probably, the tests for SET and the PC are
11452 scanbody = PATTERN (this_insn);
11453 if (GET_CODE (scanbody) == SET
11454 && GET_CODE (SET_DEST (scanbody)) == PC)
11456 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11457 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11459 arm_ccfsm_state = 2;
11462 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11465 /* Fail if a conditional return is undesirable (eg on a
11466 StrongARM), but still allow this if optimizing for size. */
11467 else if (GET_CODE (scanbody) == RETURN
11468 && !use_return_insn (TRUE, NULL)
11471 else if (GET_CODE (scanbody) == RETURN
11474 arm_ccfsm_state = 2;
11477 else if (GET_CODE (scanbody) == PARALLEL)
11479 switch (get_attr_conds (this_insn))
11489 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11494 /* Instructions using or affecting the condition codes make it
11496 scanbody = PATTERN (this_insn);
11497 if (!(GET_CODE (scanbody) == SET
11498 || GET_CODE (scanbody) == PARALLEL)
11499 || get_attr_conds (this_insn) != CONDS_NOCOND)
11502 /* A conditional cirrus instruction must be followed by
11503 a non Cirrus instruction. However, since we
11504 conditionalize instructions in this function and by
11505 the time we get here we can't add instructions
11506 (nops), because shorten_branches() has already been
11507 called, we will disable conditionalizing Cirrus
11508 instructions to be safe. */
11509 if (GET_CODE (scanbody) != USE
11510 && GET_CODE (scanbody) != CLOBBER
11511 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11521 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11522 arm_target_label = CODE_LABEL_NUMBER (label);
11523 else if (seeking_return || arm_ccfsm_state == 2)
11525 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11527 this_insn = next_nonnote_insn (this_insn);
11528 if (this_insn && (GET_CODE (this_insn) == BARRIER
11529 || GET_CODE (this_insn) == CODE_LABEL))
11534 /* Oh, dear! we ran off the end.. give up. */
11535 recog (PATTERN (insn), insn, NULL);
11536 arm_ccfsm_state = 0;
11537 arm_target_insn = NULL;
11540 arm_target_insn = this_insn;
11549 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11551 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11552 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11553 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11554 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11558 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11561 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11565 if (reverse || then_not_else)
11566 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11569 /* Restore recog_data (getting the attributes of other insns can
11570 destroy this array, but final.c assumes that it remains intact
11571 across this call; since the insn has been recognized already we
11572 call recog direct). */
11573 recog (PATTERN (insn), insn, NULL);
11577 /* Returns true if REGNO is a valid register
11578 for holding a quantity of tyoe MODE. */
11580 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11582 if (GET_MODE_CLASS (mode) == MODE_CC)
11583 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11586 /* For the Thumb we only allow values bigger than SImode in
11587 registers 0 - 6, so that there is always a second low
11588 register available to hold the upper part of the value.
11589 We probably we ought to ensure that the register is the
11590 start of an even numbered register pair. */
11591 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11593 if (IS_CIRRUS_REGNUM (regno))
11594 /* We have outlawed SI values in Cirrus registers because they
11595 reside in the lower 32 bits, but SF values reside in the
11596 upper 32 bits. This causes gcc all sorts of grief. We can't
11597 even split the registers into pairs because Cirrus SI values
11598 get sign extended to 64bits-- aldyh. */
11599 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11601 if (IS_VFP_REGNUM (regno))
11603 if (mode == SFmode || mode == SImode)
11606 /* DFmode values are only valid in even register pairs. */
11607 if (mode == DFmode)
11608 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11612 if (IS_IWMMXT_GR_REGNUM (regno))
11613 return mode == SImode;
11615 if (IS_IWMMXT_REGNUM (regno))
11616 return VALID_IWMMXT_REG_MODE (mode);
11618 /* We allow any value to be stored in the general registers.
11619 Restrict doubleword quantities to even register pairs so that we can
11621 if (regno <= LAST_ARM_REGNUM)
11622 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11624 if ( regno == FRAME_POINTER_REGNUM
11625 || regno == ARG_POINTER_REGNUM)
11626 /* We only allow integers in the fake hard registers. */
11627 return GET_MODE_CLASS (mode) == MODE_INT;
11629 /* The only registers left are the FPA registers
11630 which we only allow to hold FP values. */
11631 return GET_MODE_CLASS (mode) == MODE_FLOAT
11632 && regno >= FIRST_FPA_REGNUM
11633 && regno <= LAST_FPA_REGNUM;
11637 arm_regno_class (int regno)
11641 if (regno == STACK_POINTER_REGNUM)
11643 if (regno == CC_REGNUM)
11650 if ( regno <= LAST_ARM_REGNUM
11651 || regno == FRAME_POINTER_REGNUM
11652 || regno == ARG_POINTER_REGNUM)
11653 return GENERAL_REGS;
11655 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11658 if (IS_CIRRUS_REGNUM (regno))
11659 return CIRRUS_REGS;
11661 if (IS_VFP_REGNUM (regno))
11664 if (IS_IWMMXT_REGNUM (regno))
11665 return IWMMXT_REGS;
11667 if (IS_IWMMXT_GR_REGNUM (regno))
11668 return IWMMXT_GR_REGS;
11673 /* Handle a special case when computing the offset
11674 of an argument from the frame pointer. */
11676 arm_debugger_arg_offset (int value, rtx addr)
11680 /* We are only interested if dbxout_parms() failed to compute the offset. */
11684 /* We can only cope with the case where the address is held in a register. */
11685 if (GET_CODE (addr) != REG)
11688 /* If we are using the frame pointer to point at the argument, then
11689 an offset of 0 is correct. */
11690 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11693 /* If we are using the stack pointer to point at the
11694 argument, then an offset of 0 is correct. */
11695 if ((TARGET_THUMB || !frame_pointer_needed)
11696 && REGNO (addr) == SP_REGNUM)
11699 /* Oh dear. The argument is pointed to by a register rather
11700 than being held in a register, or being stored at a known
11701 offset from the frame pointer. Since GDB only understands
11702 those two kinds of argument we must translate the address
11703 held in the register into an offset from the frame pointer.
11704 We do this by searching through the insns for the function
11705 looking to see where this register gets its value. If the
11706 register is initialized from the frame pointer plus an offset
11707 then we are in luck and we can continue, otherwise we give up.
11709 This code is exercised by producing debugging information
11710 for a function with arguments like this:
11712 double func (double a, double b, int c, double d) {return d;}
11714 Without this code the stab for parameter 'd' will be set to
11715 an offset of 0 from the frame pointer, rather than 8. */
11717 /* The if() statement says:
11719 If the insn is a normal instruction
11720 and if the insn is setting the value in a register
11721 and if the register being set is the register holding the address of the argument
11722 and if the address is computing by an addition
11723 that involves adding to a register
11724 which is the frame pointer
11729 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11731 if ( GET_CODE (insn) == INSN
11732 && GET_CODE (PATTERN (insn)) == SET
11733 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11734 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11735 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11736 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11737 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11740 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11749 warning ("unable to compute real location of stacked parameter");
11750 value = 8; /* XXX magic hack */
11756 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11759 if ((MASK) & insn_flags) \
11760 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11761 BUILT_IN_MD, NULL, NULL_TREE); \
11765 struct builtin_description
11767 const unsigned int mask;
11768 const enum insn_code icode;
11769 const char * const name;
11770 const enum arm_builtins code;
11771 const enum rtx_code comparison;
11772 const unsigned int flag;
11775 static const struct builtin_description bdesc_2arg[] =
11777 #define IWMMXT_BUILTIN(code, string, builtin) \
11778 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11779 ARM_BUILTIN_##builtin, 0, 0 },
11781 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11782 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11783 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11784 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11785 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11786 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11787 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11788 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11789 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11790 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11791 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11792 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11793 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11794 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11795 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11796 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11797 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11798 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11799 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11800 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11801 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11802 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11803 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11804 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11805 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11806 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11807 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11808 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11809 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11810 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11811 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11812 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11813 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11814 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11815 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11816 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11817 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11818 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11819 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11820 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11821 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11822 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11823 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11824 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11825 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11826 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11827 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11828 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11829 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11830 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11831 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11832 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11833 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11834 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11835 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11836 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11837 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11838 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11840 #define IWMMXT_BUILTIN2(code, builtin) \
11841 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11843 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11844 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11845 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11846 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11847 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11848 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11849 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11850 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11851 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11852 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11853 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11854 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11855 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11856 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11857 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11858 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11859 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11860 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11861 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11862 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11863 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11864 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11865 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11866 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11867 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11868 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11869 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11870 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11871 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11872 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11873 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11874 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11877 static const struct builtin_description bdesc_1arg[] =
11879 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11880 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11881 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11882 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11883 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11884 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11885 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11886 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11887 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11888 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11889 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11890 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11891 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11892 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11893 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11894 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11895 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11896 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11899 /* Set up all the iWMMXt builtins. This is
11900 not called if TARGET_IWMMXT is zero. */
11903 arm_init_iwmmxt_builtins (void)
11905 const struct builtin_description * d;
11907 tree endlink = void_list_node;
11909 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11910 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11911 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11914 = build_function_type (integer_type_node,
11915 tree_cons (NULL_TREE, integer_type_node, endlink));
11916 tree v8qi_ftype_v8qi_v8qi_int
11917 = build_function_type (V8QI_type_node,
11918 tree_cons (NULL_TREE, V8QI_type_node,
11919 tree_cons (NULL_TREE, V8QI_type_node,
11920 tree_cons (NULL_TREE,
11923 tree v4hi_ftype_v4hi_int
11924 = build_function_type (V4HI_type_node,
11925 tree_cons (NULL_TREE, V4HI_type_node,
11926 tree_cons (NULL_TREE, integer_type_node,
11928 tree v2si_ftype_v2si_int
11929 = build_function_type (V2SI_type_node,
11930 tree_cons (NULL_TREE, V2SI_type_node,
11931 tree_cons (NULL_TREE, integer_type_node,
11933 tree v2si_ftype_di_di
11934 = build_function_type (V2SI_type_node,
11935 tree_cons (NULL_TREE, long_long_integer_type_node,
11936 tree_cons (NULL_TREE, long_long_integer_type_node,
11938 tree di_ftype_di_int
11939 = build_function_type (long_long_integer_type_node,
11940 tree_cons (NULL_TREE, long_long_integer_type_node,
11941 tree_cons (NULL_TREE, integer_type_node,
11943 tree di_ftype_di_int_int
11944 = build_function_type (long_long_integer_type_node,
11945 tree_cons (NULL_TREE, long_long_integer_type_node,
11946 tree_cons (NULL_TREE, integer_type_node,
11947 tree_cons (NULL_TREE,
11950 tree int_ftype_v8qi
11951 = build_function_type (integer_type_node,
11952 tree_cons (NULL_TREE, V8QI_type_node,
11954 tree int_ftype_v4hi
11955 = build_function_type (integer_type_node,
11956 tree_cons (NULL_TREE, V4HI_type_node,
11958 tree int_ftype_v2si
11959 = build_function_type (integer_type_node,
11960 tree_cons (NULL_TREE, V2SI_type_node,
11962 tree int_ftype_v8qi_int
11963 = build_function_type (integer_type_node,
11964 tree_cons (NULL_TREE, V8QI_type_node,
11965 tree_cons (NULL_TREE, integer_type_node,
11967 tree int_ftype_v4hi_int
11968 = build_function_type (integer_type_node,
11969 tree_cons (NULL_TREE, V4HI_type_node,
11970 tree_cons (NULL_TREE, integer_type_node,
11972 tree int_ftype_v2si_int
11973 = build_function_type (integer_type_node,
11974 tree_cons (NULL_TREE, V2SI_type_node,
11975 tree_cons (NULL_TREE, integer_type_node,
11977 tree v8qi_ftype_v8qi_int_int
11978 = build_function_type (V8QI_type_node,
11979 tree_cons (NULL_TREE, V8QI_type_node,
11980 tree_cons (NULL_TREE, integer_type_node,
11981 tree_cons (NULL_TREE,
11984 tree v4hi_ftype_v4hi_int_int
11985 = build_function_type (V4HI_type_node,
11986 tree_cons (NULL_TREE, V4HI_type_node,
11987 tree_cons (NULL_TREE, integer_type_node,
11988 tree_cons (NULL_TREE,
11991 tree v2si_ftype_v2si_int_int
11992 = build_function_type (V2SI_type_node,
11993 tree_cons (NULL_TREE, V2SI_type_node,
11994 tree_cons (NULL_TREE, integer_type_node,
11995 tree_cons (NULL_TREE,
11998 /* Miscellaneous. */
11999 tree v8qi_ftype_v4hi_v4hi
12000 = build_function_type (V8QI_type_node,
12001 tree_cons (NULL_TREE, V4HI_type_node,
12002 tree_cons (NULL_TREE, V4HI_type_node,
12004 tree v4hi_ftype_v2si_v2si
12005 = build_function_type (V4HI_type_node,
12006 tree_cons (NULL_TREE, V2SI_type_node,
12007 tree_cons (NULL_TREE, V2SI_type_node,
12009 tree v2si_ftype_v4hi_v4hi
12010 = build_function_type (V2SI_type_node,
12011 tree_cons (NULL_TREE, V4HI_type_node,
12012 tree_cons (NULL_TREE, V4HI_type_node,
12014 tree v2si_ftype_v8qi_v8qi
12015 = build_function_type (V2SI_type_node,
12016 tree_cons (NULL_TREE, V8QI_type_node,
12017 tree_cons (NULL_TREE, V8QI_type_node,
12019 tree v4hi_ftype_v4hi_di
12020 = build_function_type (V4HI_type_node,
12021 tree_cons (NULL_TREE, V4HI_type_node,
12022 tree_cons (NULL_TREE,
12023 long_long_integer_type_node,
12025 tree v2si_ftype_v2si_di
12026 = build_function_type (V2SI_type_node,
12027 tree_cons (NULL_TREE, V2SI_type_node,
12028 tree_cons (NULL_TREE,
12029 long_long_integer_type_node,
12031 tree void_ftype_int_int
12032 = build_function_type (void_type_node,
12033 tree_cons (NULL_TREE, integer_type_node,
12034 tree_cons (NULL_TREE, integer_type_node,
12037 = build_function_type (long_long_unsigned_type_node, endlink);
12039 = build_function_type (long_long_integer_type_node,
12040 tree_cons (NULL_TREE, V8QI_type_node,
12043 = build_function_type (long_long_integer_type_node,
12044 tree_cons (NULL_TREE, V4HI_type_node,
12047 = build_function_type (long_long_integer_type_node,
12048 tree_cons (NULL_TREE, V2SI_type_node,
12050 tree v2si_ftype_v4hi
12051 = build_function_type (V2SI_type_node,
12052 tree_cons (NULL_TREE, V4HI_type_node,
12054 tree v4hi_ftype_v8qi
12055 = build_function_type (V4HI_type_node,
12056 tree_cons (NULL_TREE, V8QI_type_node,
12059 tree di_ftype_di_v4hi_v4hi
12060 = build_function_type (long_long_unsigned_type_node,
12061 tree_cons (NULL_TREE,
12062 long_long_unsigned_type_node,
12063 tree_cons (NULL_TREE, V4HI_type_node,
12064 tree_cons (NULL_TREE,
12068 tree di_ftype_v4hi_v4hi
12069 = build_function_type (long_long_unsigned_type_node,
12070 tree_cons (NULL_TREE, V4HI_type_node,
12071 tree_cons (NULL_TREE, V4HI_type_node,
12074 /* Normal vector binops. */
12075 tree v8qi_ftype_v8qi_v8qi
12076 = build_function_type (V8QI_type_node,
12077 tree_cons (NULL_TREE, V8QI_type_node,
12078 tree_cons (NULL_TREE, V8QI_type_node,
12080 tree v4hi_ftype_v4hi_v4hi
12081 = build_function_type (V4HI_type_node,
12082 tree_cons (NULL_TREE, V4HI_type_node,
12083 tree_cons (NULL_TREE, V4HI_type_node,
12085 tree v2si_ftype_v2si_v2si
12086 = build_function_type (V2SI_type_node,
12087 tree_cons (NULL_TREE, V2SI_type_node,
12088 tree_cons (NULL_TREE, V2SI_type_node,
12090 tree di_ftype_di_di
12091 = build_function_type (long_long_unsigned_type_node,
12092 tree_cons (NULL_TREE, long_long_unsigned_type_node,
12093 tree_cons (NULL_TREE,
12094 long_long_unsigned_type_node,
12097 /* Add all builtins that are more or less simple operations on two
12099 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12101 /* Use one of the operands; the target can have a different mode for
12102 mask-generating compares. */
12103 enum machine_mode mode;
12109 mode = insn_data[d->icode].operand[1].mode;
12114 type = v8qi_ftype_v8qi_v8qi;
12117 type = v4hi_ftype_v4hi_v4hi;
12120 type = v2si_ftype_v2si_v2si;
12123 type = di_ftype_di_di;
12130 def_mbuiltin (d->mask, d->name, type, d->code);
12133 /* Add the remaining MMX insns with somewhat more complicated types. */
12134 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12135 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12136 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12138 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12139 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12140 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12141 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12142 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12143 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12145 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12146 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12147 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12148 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12149 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12150 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12152 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12153 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12154 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12155 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12156 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12157 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12159 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12160 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12161 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12162 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12163 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12164 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12166 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12168 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12169 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12170 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12171 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12173 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12174 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12175 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12176 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12177 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12178 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12179 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12180 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12181 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12183 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12184 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12185 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12187 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12188 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12189 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12191 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12192 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12193 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12194 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12195 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12196 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12198 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12199 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12200 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12201 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12202 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12203 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12204 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12205 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12206 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12207 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12208 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12209 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12211 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12212 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12213 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12214 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12216 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12217 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12218 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12219 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12220 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12221 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12222 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12226 arm_init_builtins (void)
12228 if (TARGET_REALLY_IWMMXT)
12229 arm_init_iwmmxt_builtins ();
12232 /* Errors in the source file can cause expand_expr to return const0_rtx
12233 where we expect a vector. To avoid crashing, use one of the vector
12234 clear instructions. */
12237 safe_vector_operand (rtx x, enum machine_mode mode)
12239 if (x != const0_rtx)
12241 x = gen_reg_rtx (mode);
12243 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12244 : gen_rtx_SUBREG (DImode, x, 0)));
12248 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12251 arm_expand_binop_builtin (enum insn_code icode,
12252 tree arglist, rtx target)
12255 tree arg0 = TREE_VALUE (arglist);
12256 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12257 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12258 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12259 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12260 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12261 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12263 if (VECTOR_MODE_P (mode0))
12264 op0 = safe_vector_operand (op0, mode0);
12265 if (VECTOR_MODE_P (mode1))
12266 op1 = safe_vector_operand (op1, mode1);
12269 || GET_MODE (target) != tmode
12270 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12271 target = gen_reg_rtx (tmode);
12273 /* In case the insn wants input operands in modes different from
12274 the result, abort. */
12275 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12278 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12279 op0 = copy_to_mode_reg (mode0, op0);
12280 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12281 op1 = copy_to_mode_reg (mode1, op1);
12283 pat = GEN_FCN (icode) (target, op0, op1);
12290 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12293 arm_expand_unop_builtin (enum insn_code icode,
12294 tree arglist, rtx target, int do_load)
12297 tree arg0 = TREE_VALUE (arglist);
12298 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12299 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12300 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12303 || GET_MODE (target) != tmode
12304 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12305 target = gen_reg_rtx (tmode);
12307 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12310 if (VECTOR_MODE_P (mode0))
12311 op0 = safe_vector_operand (op0, mode0);
12313 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12314 op0 = copy_to_mode_reg (mode0, op0);
12317 pat = GEN_FCN (icode) (target, op0);
12324 /* Expand an expression EXP that calls a built-in function,
12325 with result going to TARGET if that's convenient
12326 (and in mode MODE if that's convenient).
12327 SUBTARGET may be used as the target for computing one of EXP's operands.
12328 IGNORE is nonzero if the value is to be ignored. */
12331 arm_expand_builtin (tree exp,
12333 rtx subtarget ATTRIBUTE_UNUSED,
12334 enum machine_mode mode ATTRIBUTE_UNUSED,
12335 int ignore ATTRIBUTE_UNUSED)
12337 const struct builtin_description * d;
12338 enum insn_code icode;
12339 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12340 tree arglist = TREE_OPERAND (exp, 1);
12348 int fcode = DECL_FUNCTION_CODE (fndecl);
12350 enum machine_mode tmode;
12351 enum machine_mode mode0;
12352 enum machine_mode mode1;
12353 enum machine_mode mode2;
12357 case ARM_BUILTIN_TEXTRMSB:
12358 case ARM_BUILTIN_TEXTRMUB:
12359 case ARM_BUILTIN_TEXTRMSH:
12360 case ARM_BUILTIN_TEXTRMUH:
12361 case ARM_BUILTIN_TEXTRMSW:
12362 case ARM_BUILTIN_TEXTRMUW:
12363 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12364 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12365 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12366 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12367 : CODE_FOR_iwmmxt_textrmw);
12369 arg0 = TREE_VALUE (arglist);
12370 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12371 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12372 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12373 tmode = insn_data[icode].operand[0].mode;
12374 mode0 = insn_data[icode].operand[1].mode;
12375 mode1 = insn_data[icode].operand[2].mode;
12377 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12378 op0 = copy_to_mode_reg (mode0, op0);
12379 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12381 /* @@@ better error message */
12382 error ("selector must be an immediate");
12383 return gen_reg_rtx (tmode);
12386 || GET_MODE (target) != tmode
12387 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12388 target = gen_reg_rtx (tmode);
12389 pat = GEN_FCN (icode) (target, op0, op1);
12395 case ARM_BUILTIN_TINSRB:
12396 case ARM_BUILTIN_TINSRH:
12397 case ARM_BUILTIN_TINSRW:
12398 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12399 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12400 : CODE_FOR_iwmmxt_tinsrw);
12401 arg0 = TREE_VALUE (arglist);
12402 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12403 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12404 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12405 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12406 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12407 tmode = insn_data[icode].operand[0].mode;
12408 mode0 = insn_data[icode].operand[1].mode;
12409 mode1 = insn_data[icode].operand[2].mode;
12410 mode2 = insn_data[icode].operand[3].mode;
12412 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12413 op0 = copy_to_mode_reg (mode0, op0);
12414 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12415 op1 = copy_to_mode_reg (mode1, op1);
12416 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12418 /* @@@ better error message */
12419 error ("selector must be an immediate");
12423 || GET_MODE (target) != tmode
12424 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12425 target = gen_reg_rtx (tmode);
12426 pat = GEN_FCN (icode) (target, op0, op1, op2);
12432 case ARM_BUILTIN_SETWCX:
12433 arg0 = TREE_VALUE (arglist);
12434 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12435 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12436 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12437 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12440 case ARM_BUILTIN_GETWCX:
12441 arg0 = TREE_VALUE (arglist);
12442 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12443 target = gen_reg_rtx (SImode);
12444 emit_insn (gen_iwmmxt_tmrc (target, op0));
12447 case ARM_BUILTIN_WSHUFH:
12448 icode = CODE_FOR_iwmmxt_wshufh;
12449 arg0 = TREE_VALUE (arglist);
12450 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12451 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12452 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12453 tmode = insn_data[icode].operand[0].mode;
12454 mode1 = insn_data[icode].operand[1].mode;
12455 mode2 = insn_data[icode].operand[2].mode;
12457 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12458 op0 = copy_to_mode_reg (mode1, op0);
12459 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12461 /* @@@ better error message */
12462 error ("mask must be an immediate");
12466 || GET_MODE (target) != tmode
12467 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12468 target = gen_reg_rtx (tmode);
12469 pat = GEN_FCN (icode) (target, op0, op1);
12475 case ARM_BUILTIN_WSADB:
12476 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12477 case ARM_BUILTIN_WSADH:
12478 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12479 case ARM_BUILTIN_WSADBZ:
12480 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12481 case ARM_BUILTIN_WSADHZ:
12482 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12484 /* Several three-argument builtins. */
12485 case ARM_BUILTIN_WMACS:
12486 case ARM_BUILTIN_WMACU:
12487 case ARM_BUILTIN_WALIGN:
12488 case ARM_BUILTIN_TMIA:
12489 case ARM_BUILTIN_TMIAPH:
12490 case ARM_BUILTIN_TMIATT:
12491 case ARM_BUILTIN_TMIATB:
12492 case ARM_BUILTIN_TMIABT:
12493 case ARM_BUILTIN_TMIABB:
12494 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12495 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12496 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12497 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12498 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12499 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12500 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12501 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12502 : CODE_FOR_iwmmxt_walign);
12503 arg0 = TREE_VALUE (arglist);
12504 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12505 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12506 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12507 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12508 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12509 tmode = insn_data[icode].operand[0].mode;
12510 mode0 = insn_data[icode].operand[1].mode;
12511 mode1 = insn_data[icode].operand[2].mode;
12512 mode2 = insn_data[icode].operand[3].mode;
12514 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12515 op0 = copy_to_mode_reg (mode0, op0);
12516 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12517 op1 = copy_to_mode_reg (mode1, op1);
12518 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12519 op2 = copy_to_mode_reg (mode2, op2);
12521 || GET_MODE (target) != tmode
12522 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12523 target = gen_reg_rtx (tmode);
12524 pat = GEN_FCN (icode) (target, op0, op1, op2);
12530 case ARM_BUILTIN_WZERO:
12531 target = gen_reg_rtx (DImode);
12532 emit_insn (gen_iwmmxt_clrdi (target));
12539 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12540 if (d->code == (const enum arm_builtins) fcode)
12541 return arm_expand_binop_builtin (d->icode, arglist, target);
12543 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12544 if (d->code == (const enum arm_builtins) fcode)
12545 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12547 /* @@@ Should really do something sensible here. */
12551 /* Recursively search through all of the blocks in a function
12552 checking to see if any of the variables created in that
12553 function match the RTX called 'orig'. If they do then
12554 replace them with the RTX called 'new'. */
12556 replace_symbols_in_block (tree block, rtx orig, rtx new)
12558 for (; block; block = BLOCK_CHAIN (block))
12562 if (!TREE_USED (block))
12565 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12567 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12568 || DECL_IGNORED_P (sym)
12569 || TREE_CODE (sym) != VAR_DECL
12570 || DECL_EXTERNAL (sym)
12571 || !rtx_equal_p (DECL_RTL (sym), orig)
12575 SET_DECL_RTL (sym, new);
12578 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12582 /* Return the number (counting from 0) of
12583 the least significant set bit in MASK. */
12586 number_of_first_bit_set (int mask)
12591 (mask & (1 << bit)) == 0;
12598 /* Generate code to return from a thumb function.
12599 If 'reg_containing_return_addr' is -1, then the return address is
12600 actually on the stack, at the stack pointer. */
12602 thumb_exit (FILE *f, int reg_containing_return_addr)
12604 unsigned regs_available_for_popping;
12605 unsigned regs_to_pop;
12607 unsigned available;
12611 int restore_a4 = FALSE;
12613 /* Compute the registers we need to pop. */
12617 if (reg_containing_return_addr == -1)
12619 regs_to_pop |= 1 << LR_REGNUM;
12623 if (TARGET_BACKTRACE)
12625 /* Restore the (ARM) frame pointer and stack pointer. */
12626 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12630 /* If there is nothing to pop then just emit the BX instruction and
12632 if (pops_needed == 0)
12634 if (current_function_calls_eh_return)
12635 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12637 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12640 /* Otherwise if we are not supporting interworking and we have not created
12641 a backtrace structure and the function was not entered in ARM mode then
12642 just pop the return address straight into the PC. */
12643 else if (!TARGET_INTERWORK
12644 && !TARGET_BACKTRACE
12645 && !is_called_in_ARM_mode (current_function_decl)
12646 && !current_function_calls_eh_return)
12648 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12652 /* Find out how many of the (return) argument registers we can corrupt. */
12653 regs_available_for_popping = 0;
12655 /* If returning via __builtin_eh_return, the bottom three registers
12656 all contain information needed for the return. */
12657 if (current_function_calls_eh_return)
12661 /* If we can deduce the registers used from the function's
12662 return value. This is more reliable that examining
12663 regs_ever_live[] because that will be set if the register is
12664 ever used in the function, not just if the register is used
12665 to hold a return value. */
12667 if (current_function_return_rtx != 0)
12668 mode = GET_MODE (current_function_return_rtx);
12670 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12672 size = GET_MODE_SIZE (mode);
12676 /* In a void function we can use any argument register.
12677 In a function that returns a structure on the stack
12678 we can use the second and third argument registers. */
12679 if (mode == VOIDmode)
12680 regs_available_for_popping =
12681 (1 << ARG_REGISTER (1))
12682 | (1 << ARG_REGISTER (2))
12683 | (1 << ARG_REGISTER (3));
12685 regs_available_for_popping =
12686 (1 << ARG_REGISTER (2))
12687 | (1 << ARG_REGISTER (3));
12689 else if (size <= 4)
12690 regs_available_for_popping =
12691 (1 << ARG_REGISTER (2))
12692 | (1 << ARG_REGISTER (3));
12693 else if (size <= 8)
12694 regs_available_for_popping =
12695 (1 << ARG_REGISTER (3));
12698 /* Match registers to be popped with registers into which we pop them. */
12699 for (available = regs_available_for_popping,
12700 required = regs_to_pop;
12701 required != 0 && available != 0;
12702 available &= ~(available & - available),
12703 required &= ~(required & - required))
12706 /* If we have any popping registers left over, remove them. */
12708 regs_available_for_popping &= ~available;
12710 /* Otherwise if we need another popping register we can use
12711 the fourth argument register. */
12712 else if (pops_needed)
12714 /* If we have not found any free argument registers and
12715 reg a4 contains the return address, we must move it. */
12716 if (regs_available_for_popping == 0
12717 && reg_containing_return_addr == LAST_ARG_REGNUM)
12719 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12720 reg_containing_return_addr = LR_REGNUM;
12722 else if (size > 12)
12724 /* Register a4 is being used to hold part of the return value,
12725 but we have dire need of a free, low register. */
12728 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12731 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12733 /* The fourth argument register is available. */
12734 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12740 /* Pop as many registers as we can. */
12741 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12742 regs_available_for_popping);
12744 /* Process the registers we popped. */
12745 if (reg_containing_return_addr == -1)
12747 /* The return address was popped into the lowest numbered register. */
12748 regs_to_pop &= ~(1 << LR_REGNUM);
12750 reg_containing_return_addr =
12751 number_of_first_bit_set (regs_available_for_popping);
12753 /* Remove this register for the mask of available registers, so that
12754 the return address will not be corrupted by further pops. */
12755 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12758 /* If we popped other registers then handle them here. */
12759 if (regs_available_for_popping)
12763 /* Work out which register currently contains the frame pointer. */
12764 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12766 /* Move it into the correct place. */
12767 asm_fprintf (f, "\tmov\t%r, %r\n",
12768 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12770 /* (Temporarily) remove it from the mask of popped registers. */
12771 regs_available_for_popping &= ~(1 << frame_pointer);
12772 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12774 if (regs_available_for_popping)
12778 /* We popped the stack pointer as well,
12779 find the register that contains it. */
12780 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12782 /* Move it into the stack register. */
12783 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12785 /* At this point we have popped all necessary registers, so
12786 do not worry about restoring regs_available_for_popping
12787 to its correct value:
12789 assert (pops_needed == 0)
12790 assert (regs_available_for_popping == (1 << frame_pointer))
12791 assert (regs_to_pop == (1 << STACK_POINTER)) */
12795 /* Since we have just move the popped value into the frame
12796 pointer, the popping register is available for reuse, and
12797 we know that we still have the stack pointer left to pop. */
12798 regs_available_for_popping |= (1 << frame_pointer);
12802 /* If we still have registers left on the stack, but we no longer have
12803 any registers into which we can pop them, then we must move the return
12804 address into the link register and make available the register that
12806 if (regs_available_for_popping == 0 && pops_needed > 0)
12808 regs_available_for_popping |= 1 << reg_containing_return_addr;
12810 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12811 reg_containing_return_addr);
12813 reg_containing_return_addr = LR_REGNUM;
12816 /* If we have registers left on the stack then pop some more.
12817 We know that at most we will want to pop FP and SP. */
12818 if (pops_needed > 0)
12823 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12824 regs_available_for_popping);
12826 /* We have popped either FP or SP.
12827 Move whichever one it is into the correct register. */
12828 popped_into = number_of_first_bit_set (regs_available_for_popping);
12829 move_to = number_of_first_bit_set (regs_to_pop);
12831 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12833 regs_to_pop &= ~(1 << move_to);
12838 /* If we still have not popped everything then we must have only
12839 had one register available to us and we are now popping the SP. */
12840 if (pops_needed > 0)
12844 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12845 regs_available_for_popping);
12847 popped_into = number_of_first_bit_set (regs_available_for_popping);
12849 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12851 assert (regs_to_pop == (1 << STACK_POINTER))
12852 assert (pops_needed == 1)
12856 /* If necessary restore the a4 register. */
12859 if (reg_containing_return_addr != LR_REGNUM)
12861 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12862 reg_containing_return_addr = LR_REGNUM;
12865 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12868 if (current_function_calls_eh_return)
12869 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12871 /* Return to caller. */
12872 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12875 /* Emit code to push or pop registers to or from the stack. F is the
12876 assembly file. MASK is the registers to push or pop. PUSH is
12877 nonzero if we should push, and zero if we should pop. For debugging
12878 output, if pushing, adjust CFA_OFFSET by the amount of space added
12879 to the stack. REAL_REGS should have the same number of bits set as
12880 MASK, and will be used instead (in the same order) to describe which
12881 registers were saved - this is used to mark the save slots when we
12882 push high registers after moving them to low registers. */
12884 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12887 int lo_mask = mask & 0xFF;
12888 int pushed_words = 0;
12890 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12892 /* Special case. Do not generate a POP PC statement here, do it in
12894 thumb_exit (f, -1);
12898 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12900 /* Look at the low registers first. */
12901 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12905 asm_fprintf (f, "%r", regno);
12907 if ((lo_mask & ~1) != 0)
12914 if (push && (mask & (1 << LR_REGNUM)))
12916 /* Catch pushing the LR. */
12920 asm_fprintf (f, "%r", LR_REGNUM);
12924 else if (!push && (mask & (1 << PC_REGNUM)))
12926 /* Catch popping the PC. */
12927 if (TARGET_INTERWORK || TARGET_BACKTRACE
12928 || current_function_calls_eh_return)
12930 /* The PC is never poped directly, instead
12931 it is popped into r3 and then BX is used. */
12932 fprintf (f, "}\n");
12934 thumb_exit (f, -1);
12943 asm_fprintf (f, "%r", PC_REGNUM);
12947 fprintf (f, "}\n");
12949 if (push && pushed_words && dwarf2out_do_frame ())
12951 char *l = dwarf2out_cfi_label ();
12952 int pushed_mask = real_regs;
12954 *cfa_offset += pushed_words * 4;
12955 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12958 pushed_mask = real_regs;
12959 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12961 if (pushed_mask & 1)
12962 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12968 thumb_final_prescan_insn (rtx insn)
12970 if (flag_print_asm_name)
12971 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12972 INSN_ADDRESSES (INSN_UID (insn)));
12976 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12978 unsigned HOST_WIDE_INT mask = 0xff;
12981 if (val == 0) /* XXX */
12984 for (i = 0; i < 25; i++)
12985 if ((val & (mask << i)) == val)
12991 /* Returns nonzero if the current function contains,
12992 or might contain a far jump. */
12994 thumb_far_jump_used_p (void)
12998 /* This test is only important for leaf functions. */
12999 /* assert (!leaf_function_p ()); */
13001 /* If we have already decided that far jumps may be used,
13002 do not bother checking again, and always return true even if
13003 it turns out that they are not being used. Once we have made
13004 the decision that far jumps are present (and that hence the link
13005 register will be pushed onto the stack) we cannot go back on it. */
13006 if (cfun->machine->far_jump_used)
13009 /* If this function is not being called from the prologue/epilogue
13010 generation code then it must be being called from the
13011 INITIAL_ELIMINATION_OFFSET macro. */
13012 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
13014 /* In this case we know that we are being asked about the elimination
13015 of the arg pointer register. If that register is not being used,
13016 then there are no arguments on the stack, and we do not have to
13017 worry that a far jump might force the prologue to push the link
13018 register, changing the stack offsets. In this case we can just
13019 return false, since the presence of far jumps in the function will
13020 not affect stack offsets.
13022 If the arg pointer is live (or if it was live, but has now been
13023 eliminated and so set to dead) then we do have to test to see if
13024 the function might contain a far jump. This test can lead to some
13025 false negatives, since before reload is completed, then length of
13026 branch instructions is not known, so gcc defaults to returning their
13027 longest length, which in turn sets the far jump attribute to true.
13029 A false negative will not result in bad code being generated, but it
13030 will result in a needless push and pop of the link register. We
13031 hope that this does not occur too often.
13033 If we need doubleword stack alignment this could affect the other
13034 elimination offsets so we can't risk getting it wrong. */
13035 if (regs_ever_live [ARG_POINTER_REGNUM])
13036 cfun->machine->arg_pointer_live = 1;
13037 else if (!cfun->machine->arg_pointer_live)
13041 /* Check to see if the function contains a branch
13042 insn with the far jump attribute set. */
13043 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13045 if (GET_CODE (insn) == JUMP_INSN
13046 /* Ignore tablejump patterns. */
13047 && GET_CODE (PATTERN (insn)) != ADDR_VEC
13048 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
13049 && get_attr_far_jump (insn) == FAR_JUMP_YES
13052 /* Record the fact that we have decided that
13053 the function does use far jumps. */
13054 cfun->machine->far_jump_used = 1;
13062 /* Return nonzero if FUNC must be entered in ARM mode. */
13064 is_called_in_ARM_mode (tree func)
13066 if (TREE_CODE (func) != FUNCTION_DECL)
13069 /* Ignore the problem about functions whoes address is taken. */
13070 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
13074 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
13080 /* The bits which aren't usefully expanded as rtl. */
13082 thumb_unexpanded_epilogue (void)
13085 int live_regs_mask = 0;
13086 int high_regs_pushed = 0;
13087 int had_to_push_lr;
13091 if (return_used_this_function)
13094 if (IS_NAKED (arm_current_func_type ()))
13097 live_regs_mask = thumb_compute_save_reg_mask ();
13098 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13100 /* If we can deduce the registers used from the function's return value.
13101 This is more reliable that examining regs_ever_live[] because that
13102 will be set if the register is ever used in the function, not just if
13103 the register is used to hold a return value. */
13105 if (current_function_return_rtx != 0)
13106 mode = GET_MODE (current_function_return_rtx);
13108 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13110 size = GET_MODE_SIZE (mode);
13112 /* The prolog may have pushed some high registers to use as
13113 work registers. eg the testsuite file:
13114 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13115 compiles to produce:
13116 push {r4, r5, r6, r7, lr}
13120 as part of the prolog. We have to undo that pushing here. */
13122 if (high_regs_pushed)
13124 int mask = live_regs_mask & 0xff;
13127 /* The available low registers depend on the size of the value we are
13135 /* Oh dear! We have no low registers into which we can pop
13138 ("no low registers available for popping high registers");
13140 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13141 if (live_regs_mask & (1 << next_hi_reg))
13144 while (high_regs_pushed)
13146 /* Find lo register(s) into which the high register(s) can
13148 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13150 if (mask & (1 << regno))
13151 high_regs_pushed--;
13152 if (high_regs_pushed == 0)
13156 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13158 /* Pop the values into the low register(s). */
13159 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13161 /* Move the value(s) into the high registers. */
13162 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13164 if (mask & (1 << regno))
13166 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13169 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13170 if (live_regs_mask & (1 << next_hi_reg))
13175 live_regs_mask &= ~0x0f00;
13178 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13179 live_regs_mask &= 0xff;
13181 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13183 /* Pop the return address into the PC. */
13184 if (had_to_push_lr)
13185 live_regs_mask |= 1 << PC_REGNUM;
13187 /* Either no argument registers were pushed or a backtrace
13188 structure was created which includes an adjusted stack
13189 pointer, so just pop everything. */
13190 if (live_regs_mask)
13191 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13194 /* We have either just popped the return address into the
13195 PC or it is was kept in LR for the entire function. */
13196 if (!had_to_push_lr)
13197 thumb_exit (asm_out_file, LR_REGNUM);
13201 /* Pop everything but the return address. */
13202 if (live_regs_mask)
13203 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13206 if (had_to_push_lr)
13210 /* We have no free low regs, so save one. */
13211 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13215 /* Get the return address into a temporary register. */
13216 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13217 1 << LAST_ARG_REGNUM);
13221 /* Move the return address to lr. */
13222 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13224 /* Restore the low register. */
13225 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13230 regno = LAST_ARG_REGNUM;
13235 /* Remove the argument registers that were pushed onto the stack. */
13236 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13237 SP_REGNUM, SP_REGNUM,
13238 current_function_pretend_args_size);
13240 thumb_exit (asm_out_file, regno);
13246 /* Functions to save and restore machine-specific function data. */
13247 static struct machine_function *
13248 arm_init_machine_status (void)
13250 struct machine_function *machine;
13251 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13253 #if ARM_FT_UNKNOWN != 0
13254 machine->func_type = ARM_FT_UNKNOWN;
13259 /* Return an RTX indicating where the return address to the
13260 calling function can be found. */
13262 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13267 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13270 /* Do anything needed before RTL is emitted for each function. */
13272 arm_init_expanders (void)
13274 /* Arrange to initialize and mark the machine per-function status. */
13275 init_machine_status = arm_init_machine_status;
13277 /* This is to stop the combine pass optimizing away the alignment
13278 adjustment of va_arg. */
13279 /* ??? It is claimed that this should not be necessary. */
13281 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13285 /* Like arm_compute_initial_elimination offset. Simpler because
13286 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13289 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13291 arm_stack_offsets *offsets;
13293 offsets = arm_get_frame_offsets ();
13297 case ARG_POINTER_REGNUM:
13300 case STACK_POINTER_REGNUM:
13301 return offsets->outgoing_args - offsets->saved_args;
13303 case FRAME_POINTER_REGNUM:
13304 return offsets->soft_frame - offsets->saved_args;
13306 case THUMB_HARD_FRAME_POINTER_REGNUM:
13307 case ARM_HARD_FRAME_POINTER_REGNUM:
13308 return offsets->saved_regs - offsets->saved_args;
13315 case FRAME_POINTER_REGNUM:
13318 case STACK_POINTER_REGNUM:
13319 return offsets->outgoing_args - offsets->soft_frame;
13321 case THUMB_HARD_FRAME_POINTER_REGNUM:
13322 case ARM_HARD_FRAME_POINTER_REGNUM:
13323 return offsets->saved_regs - offsets->soft_frame;
13336 /* Generate the rest of a function's prologue. */
13338 thumb_expand_prologue (void)
13342 HOST_WIDE_INT amount;
13343 arm_stack_offsets *offsets;
13344 unsigned long func_type;
13346 unsigned long live_regs_mask;
13348 func_type = arm_current_func_type ();
13350 /* Naked functions don't have prologues. */
13351 if (IS_NAKED (func_type))
13354 if (IS_INTERRUPT (func_type))
13356 error ("interrupt Service Routines cannot be coded in Thumb mode");
13360 offsets = arm_get_frame_offsets ();
13362 if (frame_pointer_needed)
13364 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13365 stack_pointer_rtx));
13366 RTX_FRAME_RELATED_P (insn) = 1;
13369 live_regs_mask = thumb_compute_save_reg_mask ();
13370 amount = offsets->outgoing_args - offsets->saved_regs;
13375 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13376 GEN_INT (- amount)));
13377 RTX_FRAME_RELATED_P (insn) = 1;
13383 /* The stack decrement is too big for an immediate value in a single
13384 insn. In theory we could issue multiple subtracts, but after
13385 three of them it becomes more space efficient to place the full
13386 value in the constant pool and load into a register. (Also the
13387 ARM debugger really likes to see only one stack decrement per
13388 function). So instead we look for a scratch register into which
13389 we can load the decrement, and then we subtract this from the
13390 stack pointer. Unfortunately on the thumb the only available
13391 scratch registers are the argument registers, and we cannot use
13392 these as they may hold arguments to the function. Instead we
13393 attempt to locate a call preserved register which is used by this
13394 function. If we can find one, then we know that it will have
13395 been pushed at the start of the prologue and so we can corrupt
13397 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13398 if (live_regs_mask & (1 << regno)
13399 && !(frame_pointer_needed
13400 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13403 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13405 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13407 /* Choose an arbitrary, non-argument low register. */
13408 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13410 /* Save it by copying it into a high, scratch register. */
13411 emit_insn (gen_movsi (spare, reg));
13412 /* Add a USE to stop propagate_one_insn() from barfing. */
13413 emit_insn (gen_prologue_use (spare));
13415 /* Decrement the stack. */
13416 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13417 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13418 stack_pointer_rtx, reg));
13419 RTX_FRAME_RELATED_P (insn) = 1;
13420 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13421 plus_constant (stack_pointer_rtx,
13423 RTX_FRAME_RELATED_P (dwarf) = 1;
13425 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13428 /* Restore the low register's original value. */
13429 emit_insn (gen_movsi (reg, spare));
13431 /* Emit a USE of the restored scratch register, so that flow
13432 analysis will not consider the restore redundant. The
13433 register won't be used again in this function and isn't
13434 restored by the epilogue. */
13435 emit_insn (gen_prologue_use (reg));
13439 reg = gen_rtx_REG (SImode, regno);
13441 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13443 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13444 stack_pointer_rtx, reg));
13445 RTX_FRAME_RELATED_P (insn) = 1;
13446 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13447 plus_constant (stack_pointer_rtx,
13449 RTX_FRAME_RELATED_P (dwarf) = 1;
13451 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13455 /* If the frame pointer is needed, emit a special barrier that
13456 will prevent the scheduler from moving stores to the frame
13457 before the stack adjustment. */
13458 if (frame_pointer_needed)
13459 emit_insn (gen_stack_tie (stack_pointer_rtx,
13460 hard_frame_pointer_rtx));
13463 if (current_function_profile || TARGET_NO_SCHED_PRO)
13464 emit_insn (gen_blockage ());
13466 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13467 if (live_regs_mask & 0xff)
13468 cfun->machine->lr_save_eliminated = 0;
13470 /* If the link register is being kept alive, with the return address in it,
13471 then make sure that it does not get reused by the ce2 pass. */
13472 if (cfun->machine->lr_save_eliminated)
13473 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13478 thumb_expand_epilogue (void)
13480 HOST_WIDE_INT amount;
13481 arm_stack_offsets *offsets;
13484 /* Naked functions don't have prologues. */
13485 if (IS_NAKED (arm_current_func_type ()))
13488 offsets = arm_get_frame_offsets ();
13489 amount = offsets->outgoing_args - offsets->saved_regs;
13491 if (frame_pointer_needed)
13492 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13496 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13497 GEN_INT (amount)));
13500 /* r3 is always free in the epilogue. */
13501 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13503 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13504 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13508 /* Emit a USE (stack_pointer_rtx), so that
13509 the stack adjustment will not be deleted. */
13510 emit_insn (gen_prologue_use (stack_pointer_rtx));
13512 if (current_function_profile || TARGET_NO_SCHED_PRO)
13513 emit_insn (gen_blockage ());
13515 /* Emit a clobber for each insn that will be restored in the epilogue,
13516 so that flow2 will get register lifetimes correct. */
13517 for (regno = 0; regno < 13; regno++)
13518 if (regs_ever_live[regno] && !call_used_regs[regno])
13519 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13521 if (! regs_ever_live[LR_REGNUM])
13522 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13526 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13528 int live_regs_mask = 0;
13530 int high_regs_pushed = 0;
13531 int cfa_offset = 0;
13534 if (IS_NAKED (arm_current_func_type ()))
13537 if (is_called_in_ARM_mode (current_function_decl))
13541 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13543 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13545 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13547 /* Generate code sequence to switch us into Thumb mode. */
13548 /* The .code 32 directive has already been emitted by
13549 ASM_DECLARE_FUNCTION_NAME. */
13550 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13551 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13553 /* Generate a label, so that the debugger will notice the
13554 change in instruction sets. This label is also used by
13555 the assembler to bypass the ARM code when this function
13556 is called from a Thumb encoded function elsewhere in the
13557 same file. Hence the definition of STUB_NAME here must
13558 agree with the definition in gas/config/tc-arm.c. */
13560 #define STUB_NAME ".real_start_of"
13562 fprintf (f, "\t.code\t16\n");
13564 if (arm_dllexport_name_p (name))
13565 name = arm_strip_name_encoding (name);
13567 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13568 fprintf (f, "\t.thumb_func\n");
13569 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13572 if (current_function_pretend_args_size)
13574 if (cfun->machine->uses_anonymous_args)
13578 fprintf (f, "\tpush\t{");
13580 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13582 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13583 regno <= LAST_ARG_REGNUM;
13585 asm_fprintf (f, "%r%s", regno,
13586 regno == LAST_ARG_REGNUM ? "" : ", ");
13588 fprintf (f, "}\n");
13591 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13592 SP_REGNUM, SP_REGNUM,
13593 current_function_pretend_args_size);
13595 /* We don't need to record the stores for unwinding (would it
13596 help the debugger any if we did?), but record the change in
13597 the stack pointer. */
13598 if (dwarf2out_do_frame ())
13600 char *l = dwarf2out_cfi_label ();
13601 cfa_offset = cfa_offset + current_function_pretend_args_size;
13602 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13606 live_regs_mask = thumb_compute_save_reg_mask ();
13607 /* Just low regs and lr. */
13608 l_mask = live_regs_mask & 0x40ff;
13610 if (TARGET_BACKTRACE)
13615 /* We have been asked to create a stack backtrace structure.
13616 The code looks like this:
13620 0 sub SP, #16 Reserve space for 4 registers.
13621 2 push {R7} Push low registers.
13622 4 add R7, SP, #20 Get the stack pointer before the push.
13623 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13624 8 mov R7, PC Get hold of the start of this code plus 12.
13625 10 str R7, [SP, #16] Store it.
13626 12 mov R7, FP Get hold of the current frame pointer.
13627 14 str R7, [SP, #4] Store it.
13628 16 mov R7, LR Get hold of the current return address.
13629 18 str R7, [SP, #12] Store it.
13630 20 add R7, SP, #16 Point at the start of the backtrace structure.
13631 22 mov FP, R7 Put this value into the frame pointer. */
13633 work_register = thumb_find_work_register (live_regs_mask);
13636 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13637 SP_REGNUM, SP_REGNUM);
13639 if (dwarf2out_do_frame ())
13641 char *l = dwarf2out_cfi_label ();
13642 cfa_offset = cfa_offset + 16;
13643 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13648 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13649 offset = bit_count (l_mask);
13654 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13655 offset + 16 + current_function_pretend_args_size);
13657 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13660 /* Make sure that the instruction fetching the PC is in the right place
13661 to calculate "start of backtrace creation code + 12". */
13664 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13665 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13667 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13668 ARM_HARD_FRAME_POINTER_REGNUM);
13669 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13674 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13675 ARM_HARD_FRAME_POINTER_REGNUM);
13676 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13678 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13679 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13683 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13684 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13686 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13688 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13689 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13692 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13694 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13696 if (high_regs_pushed)
13698 int pushable_regs = 0;
13701 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13702 if (live_regs_mask & (1 << next_hi_reg))
13705 pushable_regs = l_mask & 0xff;
13707 if (pushable_regs == 0)
13708 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13710 while (high_regs_pushed > 0)
13712 int real_regs_mask = 0;
13714 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13716 if (pushable_regs & (1 << regno))
13718 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13720 high_regs_pushed--;
13721 real_regs_mask |= (1 << next_hi_reg);
13723 if (high_regs_pushed)
13725 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13727 if (live_regs_mask & (1 << next_hi_reg))
13732 pushable_regs &= ~((1 << regno) - 1);
13738 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13743 /* Handle the case of a double word load into a low register from
13744 a computed memory address. The computed address may involve a
13745 register which is overwritten by the load. */
13747 thumb_load_double_from_address (rtx *operands)
13755 if (GET_CODE (operands[0]) != REG)
13758 if (GET_CODE (operands[1]) != MEM)
13761 /* Get the memory address. */
13762 addr = XEXP (operands[1], 0);
13764 /* Work out how the memory address is computed. */
13765 switch (GET_CODE (addr))
13768 operands[2] = gen_rtx_MEM (SImode,
13769 plus_constant (XEXP (operands[1], 0), 4));
13771 if (REGNO (operands[0]) == REGNO (addr))
13773 output_asm_insn ("ldr\t%H0, %2", operands);
13774 output_asm_insn ("ldr\t%0, %1", operands);
13778 output_asm_insn ("ldr\t%0, %1", operands);
13779 output_asm_insn ("ldr\t%H0, %2", operands);
13784 /* Compute <address> + 4 for the high order load. */
13785 operands[2] = gen_rtx_MEM (SImode,
13786 plus_constant (XEXP (operands[1], 0), 4));
13788 output_asm_insn ("ldr\t%0, %1", operands);
13789 output_asm_insn ("ldr\t%H0, %2", operands);
13793 arg1 = XEXP (addr, 0);
13794 arg2 = XEXP (addr, 1);
13796 if (CONSTANT_P (arg1))
13797 base = arg2, offset = arg1;
13799 base = arg1, offset = arg2;
13801 if (GET_CODE (base) != REG)
13804 /* Catch the case of <address> = <reg> + <reg> */
13805 if (GET_CODE (offset) == REG)
13807 int reg_offset = REGNO (offset);
13808 int reg_base = REGNO (base);
13809 int reg_dest = REGNO (operands[0]);
13811 /* Add the base and offset registers together into the
13812 higher destination register. */
13813 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13814 reg_dest + 1, reg_base, reg_offset);
13816 /* Load the lower destination register from the address in
13817 the higher destination register. */
13818 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13819 reg_dest, reg_dest + 1);
13821 /* Load the higher destination register from its own address
13823 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13824 reg_dest + 1, reg_dest + 1);
13828 /* Compute <address> + 4 for the high order load. */
13829 operands[2] = gen_rtx_MEM (SImode,
13830 plus_constant (XEXP (operands[1], 0), 4));
13832 /* If the computed address is held in the low order register
13833 then load the high order register first, otherwise always
13834 load the low order register first. */
13835 if (REGNO (operands[0]) == REGNO (base))
13837 output_asm_insn ("ldr\t%H0, %2", operands);
13838 output_asm_insn ("ldr\t%0, %1", operands);
13842 output_asm_insn ("ldr\t%0, %1", operands);
13843 output_asm_insn ("ldr\t%H0, %2", operands);
13849 /* With no registers to worry about we can just load the value
13851 operands[2] = gen_rtx_MEM (SImode,
13852 plus_constant (XEXP (operands[1], 0), 4));
13854 output_asm_insn ("ldr\t%H0, %2", operands);
13855 output_asm_insn ("ldr\t%0, %1", operands);
13867 thumb_output_move_mem_multiple (int n, rtx *operands)
13874 if (REGNO (operands[4]) > REGNO (operands[5]))
13877 operands[4] = operands[5];
13880 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13881 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13885 if (REGNO (operands[4]) > REGNO (operands[5]))
13888 operands[4] = operands[5];
13891 if (REGNO (operands[5]) > REGNO (operands[6]))
13894 operands[5] = operands[6];
13897 if (REGNO (operands[4]) > REGNO (operands[5]))
13900 operands[4] = operands[5];
13904 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13905 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13915 /* Routines for generating rtl. */
13917 thumb_expand_movmemqi (rtx *operands)
13919 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13920 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13921 HOST_WIDE_INT len = INTVAL (operands[2]);
13922 HOST_WIDE_INT offset = 0;
13926 emit_insn (gen_movmem12b (out, in, out, in));
13932 emit_insn (gen_movmem8b (out, in, out, in));
13938 rtx reg = gen_reg_rtx (SImode);
13939 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13940 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13947 rtx reg = gen_reg_rtx (HImode);
13948 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13949 plus_constant (in, offset))));
13950 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13958 rtx reg = gen_reg_rtx (QImode);
13959 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13960 plus_constant (in, offset))));
13961 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13967 thumb_cmp_operand (rtx op, enum machine_mode mode)
13969 return ((GET_CODE (op) == CONST_INT
13970 && INTVAL (op) < 256
13971 && INTVAL (op) >= 0)
13972 || s_register_operand (op, mode));
13976 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13978 return (GET_CODE (op) == CONST_INT
13980 && INTVAL (op) > -256);
13983 /* Return TRUE if a result can be stored in OP without clobbering the
13984 condition code register. Prior to reload we only accept a
13985 register. After reload we have to be able to handle memory as
13986 well, since a pseudo may not get a hard reg and reload cannot
13987 handle output-reloads on jump insns.
13989 We could possibly handle mem before reload as well, but that might
13990 complicate things with the need to handle increment
13994 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13996 return (s_register_operand (op, mode)
13997 || ((reload_in_progress || reload_completed)
13998 && memory_operand (op, mode)));
14001 /* Handle storing a half-word to memory during reload. */
14003 thumb_reload_out_hi (rtx *operands)
14005 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
14008 /* Handle reading a half-word from memory during reload. */
14010 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
14015 /* Return the length of a function name prefix
14016 that starts with the character 'c'. */
14018 arm_get_strip_length (int c)
14022 ARM_NAME_ENCODING_LENGTHS
14027 /* Return a pointer to a function's name with any
14028 and all prefix encodings stripped from it. */
14030 arm_strip_name_encoding (const char *name)
14034 while ((skip = arm_get_strip_length (* name)))
14040 /* If there is a '*' anywhere in the name's prefix, then
14041 emit the stripped name verbatim, otherwise prepend an
14042 underscore if leading underscores are being used. */
14044 arm_asm_output_labelref (FILE *stream, const char *name)
14049 while ((skip = arm_get_strip_length (* name)))
14051 verbatim |= (*name == '*');
14056 fputs (name, stream);
14058 asm_fprintf (stream, "%U%s", name);
14063 #ifdef AOF_ASSEMBLER
14064 /* Special functions only needed when producing AOF syntax assembler. */
14068 struct pic_chain * next;
14069 const char * symname;
14072 static struct pic_chain * aof_pic_chain = NULL;
14075 aof_pic_entry (rtx x)
14077 struct pic_chain ** chainp;
14080 if (aof_pic_label == NULL_RTX)
14082 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14085 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14086 offset += 4, chainp = &(*chainp)->next)
14087 if ((*chainp)->symname == XSTR (x, 0))
14088 return plus_constant (aof_pic_label, offset);
14090 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14091 (*chainp)->next = NULL;
14092 (*chainp)->symname = XSTR (x, 0);
14093 return plus_constant (aof_pic_label, offset);
14097 aof_dump_pic_table (FILE *f)
14099 struct pic_chain * chain;
14101 if (aof_pic_chain == NULL)
14104 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14105 PIC_OFFSET_TABLE_REGNUM,
14106 PIC_OFFSET_TABLE_REGNUM);
14107 fputs ("|x$adcons|\n", f);
14109 for (chain = aof_pic_chain; chain; chain = chain->next)
14111 fputs ("\tDCD\t", f);
14112 assemble_name (f, chain->symname);
14117 int arm_text_section_count = 1;
14120 aof_text_section (void )
14122 static char buf[100];
14123 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14124 arm_text_section_count++);
14126 strcat (buf, ", PIC, REENTRANT");
14130 static int arm_data_section_count = 1;
14133 aof_data_section (void)
14135 static char buf[100];
14136 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14140 /* The AOF assembler is religiously strict about declarations of
14141 imported and exported symbols, so that it is impossible to declare
14142 a function as imported near the beginning of the file, and then to
14143 export it later on. It is, however, possible to delay the decision
14144 until all the functions in the file have been compiled. To get
14145 around this, we maintain a list of the imports and exports, and
14146 delete from it any that are subsequently defined. At the end of
14147 compilation we spit the remainder of the list out before the END
14152 struct import * next;
14156 static struct import * imports_list = NULL;
14159 aof_add_import (const char *name)
14161 struct import * new;
14163 for (new = imports_list; new; new = new->next)
14164 if (new->name == name)
14167 new = (struct import *) xmalloc (sizeof (struct import));
14168 new->next = imports_list;
14169 imports_list = new;
14174 aof_delete_import (const char *name)
14176 struct import ** old;
14178 for (old = &imports_list; *old; old = & (*old)->next)
14180 if ((*old)->name == name)
14182 *old = (*old)->next;
14188 int arm_main_function = 0;
14191 aof_dump_imports (FILE *f)
14193 /* The AOF assembler needs this to cause the startup code to be extracted
14194 from the library. Brining in __main causes the whole thing to work
14196 if (arm_main_function)
14199 fputs ("\tIMPORT __main\n", f);
14200 fputs ("\tDCD __main\n", f);
14203 /* Now dump the remaining imports. */
14204 while (imports_list)
14206 fprintf (f, "\tIMPORT\t");
14207 assemble_name (f, imports_list->name);
14209 imports_list = imports_list->next;
14214 aof_globalize_label (FILE *stream, const char *name)
14216 default_globalize_label (stream, name);
14217 if (! strcmp (name, "main"))
14218 arm_main_function = 1;
14222 aof_file_start (void)
14224 fputs ("__r0\tRN\t0\n", asm_out_file);
14225 fputs ("__a1\tRN\t0\n", asm_out_file);
14226 fputs ("__a2\tRN\t1\n", asm_out_file);
14227 fputs ("__a3\tRN\t2\n", asm_out_file);
14228 fputs ("__a4\tRN\t3\n", asm_out_file);
14229 fputs ("__v1\tRN\t4\n", asm_out_file);
14230 fputs ("__v2\tRN\t5\n", asm_out_file);
14231 fputs ("__v3\tRN\t6\n", asm_out_file);
14232 fputs ("__v4\tRN\t7\n", asm_out_file);
14233 fputs ("__v5\tRN\t8\n", asm_out_file);
14234 fputs ("__v6\tRN\t9\n", asm_out_file);
14235 fputs ("__sl\tRN\t10\n", asm_out_file);
14236 fputs ("__fp\tRN\t11\n", asm_out_file);
14237 fputs ("__ip\tRN\t12\n", asm_out_file);
14238 fputs ("__sp\tRN\t13\n", asm_out_file);
14239 fputs ("__lr\tRN\t14\n", asm_out_file);
14240 fputs ("__pc\tRN\t15\n", asm_out_file);
14241 fputs ("__f0\tFN\t0\n", asm_out_file);
14242 fputs ("__f1\tFN\t1\n", asm_out_file);
14243 fputs ("__f2\tFN\t2\n", asm_out_file);
14244 fputs ("__f3\tFN\t3\n", asm_out_file);
14245 fputs ("__f4\tFN\t4\n", asm_out_file);
14246 fputs ("__f5\tFN\t5\n", asm_out_file);
14247 fputs ("__f6\tFN\t6\n", asm_out_file);
14248 fputs ("__f7\tFN\t7\n", asm_out_file);
14253 aof_file_end (void)
14256 aof_dump_pic_table (asm_out_file);
14257 aof_dump_imports (asm_out_file);
14258 fputs ("\tEND\n", asm_out_file);
14260 #endif /* AOF_ASSEMBLER */
14262 #ifdef OBJECT_FORMAT_ELF
14263 /* Switch to an arbitrary section NAME with attributes as specified
14264 by FLAGS. ALIGN specifies any known alignment requirements for
14265 the section; 0 if the default should be used.
14267 Differs from the default elf version only in the prefix character
14268 used before the section type. */
14271 arm_elf_asm_named_section (const char *name, unsigned int flags)
14273 char flagchars[10], *f = flagchars;
14275 if (! named_section_first_declaration (name))
14277 fprintf (asm_out_file, "\t.section\t%s\n", name);
14281 if (!(flags & SECTION_DEBUG))
14283 if (flags & SECTION_WRITE)
14285 if (flags & SECTION_CODE)
14287 if (flags & SECTION_SMALL)
14289 if (flags & SECTION_MERGE)
14291 if (flags & SECTION_STRINGS)
14293 if (flags & SECTION_TLS)
14297 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14299 if (!(flags & SECTION_NOTYPE))
14303 if (flags & SECTION_BSS)
14308 fprintf (asm_out_file, ",%%%s", type);
14310 if (flags & SECTION_ENTSIZE)
14311 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14314 putc ('\n', asm_out_file);
14319 /* Symbols in the text segment can be accessed without indirecting via the
14320 constant pool; it may take an extra binary operation, but this is still
14321 faster than indirecting via memory. Don't do this when not optimizing,
14322 since we won't be calculating al of the offsets necessary to do this
14326 arm_encode_section_info (tree decl, rtx rtl, int first)
14328 /* This doesn't work with AOF syntax, since the string table may be in
14329 a different AREA. */
14330 #ifndef AOF_ASSEMBLER
14331 if (optimize > 0 && TREE_CONSTANT (decl))
14332 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14335 /* If we are referencing a function that is weak then encode a long call
14336 flag in the function name, otherwise if the function is static or
14337 or known to be defined in this file then encode a short call flag. */
14338 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14340 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14341 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14342 else if (! TREE_PUBLIC (decl))
14343 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14346 #endif /* !ARM_PE */
14349 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14351 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14352 && !strcmp (prefix, "L"))
14354 arm_ccfsm_state = 0;
14355 arm_target_insn = NULL;
14357 default_internal_label (stream, prefix, labelno);
14360 /* Output code to add DELTA to the first argument, and then jump
14361 to FUNCTION. Used for C++ multiple inheritance. */
14363 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14364 HOST_WIDE_INT delta,
14365 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14368 static int thunk_label = 0;
14370 int mi_delta = delta;
14371 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14373 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14376 mi_delta = - mi_delta;
14379 int labelno = thunk_label++;
14380 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14381 fputs ("\tldr\tr12, ", file);
14382 assemble_name (file, label);
14383 fputc ('\n', file);
14385 while (mi_delta != 0)
14387 if ((mi_delta & (3 << shift)) == 0)
14391 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14392 mi_op, this_regno, this_regno,
14393 mi_delta & (0xff << shift));
14394 mi_delta &= ~(0xff << shift);
14400 fprintf (file, "\tbx\tr12\n");
14401 ASM_OUTPUT_ALIGN (file, 2);
14402 assemble_name (file, label);
14403 fputs (":\n", file);
14404 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14408 fputs ("\tb\t", file);
14409 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14410 if (NEED_PLT_RELOC)
14411 fputs ("(PLT)", file);
14412 fputc ('\n', file);
14417 arm_emit_vector_const (FILE *file, rtx x)
14420 const char * pattern;
14422 if (GET_CODE (x) != CONST_VECTOR)
14425 switch (GET_MODE (x))
14427 case V2SImode: pattern = "%08x"; break;
14428 case V4HImode: pattern = "%04x"; break;
14429 case V8QImode: pattern = "%02x"; break;
14433 fprintf (file, "0x");
14434 for (i = CONST_VECTOR_NUNITS (x); i--;)
14438 element = CONST_VECTOR_ELT (x, i);
14439 fprintf (file, pattern, INTVAL (element));
14446 arm_output_load_gr (rtx *operands)
14453 if (GET_CODE (operands [1]) != MEM
14454 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14455 || GET_CODE (reg = XEXP (sum, 0)) != REG
14456 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14457 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14458 return "wldrw%?\t%0, %1";
14460 /* Fix up an out-of-range load of a GR register. */
14461 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14462 wcgr = operands[0];
14464 output_asm_insn ("ldr%?\t%0, %1", operands);
14466 operands[0] = wcgr;
14468 output_asm_insn ("tmcr%?\t%0, %1", operands);
14469 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14475 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14476 int incoming ATTRIBUTE_UNUSED)
14479 /* FIXME: The ARM backend has special code to handle structure
14480 returns, and will reserve its own hidden first argument. So
14481 if this macro is enabled a *second* hidden argument will be
14482 reserved, which will break binary compatibility with old
14483 toolchains and also thunk handling. One day this should be
14487 /* Register in which address to store a structure value
14488 is passed to a function. */
14489 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14493 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14495 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14496 named arg and all anonymous args onto the stack.
14497 XXX I know the prologue shouldn't be pushing registers, but it is faster
14501 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14502 enum machine_mode mode ATTRIBUTE_UNUSED,
14503 tree type ATTRIBUTE_UNUSED,
14505 int second_time ATTRIBUTE_UNUSED)
14507 cfun->machine->uses_anonymous_args = 1;
14508 if (cum->nregs < NUM_ARG_REGS)
14509 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14512 /* Return nonzero if the CONSUMER instruction (a store) does not need
14513 PRODUCER's value to calculate the address. */
14516 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14518 rtx value = PATTERN (producer);
14519 rtx addr = PATTERN (consumer);
14521 if (GET_CODE (value) == COND_EXEC)
14522 value = COND_EXEC_CODE (value);
14523 if (GET_CODE (value) == PARALLEL)
14524 value = XVECEXP (value, 0, 0);
14525 value = XEXP (value, 0);
14526 if (GET_CODE (addr) == COND_EXEC)
14527 addr = COND_EXEC_CODE (addr);
14528 if (GET_CODE (addr) == PARALLEL)
14529 addr = XVECEXP (addr, 0, 0);
14530 addr = XEXP (addr, 0);
14532 return !reg_overlap_mentioned_p (value, addr);
14535 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14536 have an early register shift value or amount dependency on the
14537 result of PRODUCER. */
14540 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14542 rtx value = PATTERN (producer);
14543 rtx op = PATTERN (consumer);
14546 if (GET_CODE (value) == COND_EXEC)
14547 value = COND_EXEC_CODE (value);
14548 if (GET_CODE (value) == PARALLEL)
14549 value = XVECEXP (value, 0, 0);
14550 value = XEXP (value, 0);
14551 if (GET_CODE (op) == COND_EXEC)
14552 op = COND_EXEC_CODE (op);
14553 if (GET_CODE (op) == PARALLEL)
14554 op = XVECEXP (op, 0, 0);
14557 early_op = XEXP (op, 0);
14558 /* This is either an actual independent shift, or a shift applied to
14559 the first operand of another operation. We want the whole shift
14561 if (GET_CODE (early_op) == REG)
14564 return !reg_overlap_mentioned_p (value, early_op);
14567 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14568 have an early register shift value dependency on the result of
14572 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14574 rtx value = PATTERN (producer);
14575 rtx op = PATTERN (consumer);
14578 if (GET_CODE (value) == COND_EXEC)
14579 value = COND_EXEC_CODE (value);
14580 if (GET_CODE (value) == PARALLEL)
14581 value = XVECEXP (value, 0, 0);
14582 value = XEXP (value, 0);
14583 if (GET_CODE (op) == COND_EXEC)
14584 op = COND_EXEC_CODE (op);
14585 if (GET_CODE (op) == PARALLEL)
14586 op = XVECEXP (op, 0, 0);
14589 early_op = XEXP (op, 0);
14591 /* This is either an actual independent shift, or a shift applied to
14592 the first operand of another operation. We want the value being
14593 shifted, in either case. */
14594 if (GET_CODE (early_op) != REG)
14595 early_op = XEXP (early_op, 0);
14597 return !reg_overlap_mentioned_p (value, early_op);
14600 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14601 have an early register mult dependency on the result of
14605 arm_no_early_mul_dep (rtx producer, rtx consumer)
14607 rtx value = PATTERN (producer);
14608 rtx op = PATTERN (consumer);
14610 if (GET_CODE (value) == COND_EXEC)
14611 value = COND_EXEC_CODE (value);
14612 if (GET_CODE (value) == PARALLEL)
14613 value = XVECEXP (value, 0, 0);
14614 value = XEXP (value, 0);
14615 if (GET_CODE (op) == COND_EXEC)
14616 op = COND_EXEC_CODE (op);
14617 if (GET_CODE (op) == PARALLEL)
14618 op = XVECEXP (op, 0, 0);
14621 return (GET_CODE (op) == PLUS
14622 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14626 /* We can't rely on the caller doing the proper promotion when
14627 using APCS or ATPCS. */
14630 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14632 return !TARGET_AAPCS_BASED;
14636 /* AAPCS based ABIs use short enums by default. */
14639 arm_default_short_enums (void)
14641 return TARGET_AAPCS_BASED;
14645 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14648 arm_align_anon_bitfield (void)
14650 return TARGET_AAPCS_BASED;
14654 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14657 arm_cxx_guard_type (void)
14659 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14663 /* The EABI says test the least significan bit of a guard variable. */
14666 arm_cxx_guard_mask_bit (void)
14668 return TARGET_AAPCS_BASED;
14672 /* The EABI specifies that all array cookies are 8 bytes long. */
14675 arm_get_cookie_size (tree type)
14679 if (!TARGET_AAPCS_BASED)
14680 return default_cxx_get_cookie_size (type);
14682 size = build_int_2 (8, 0);
14683 TREE_TYPE (size) = sizetype;
14688 /* The EABI says that array cookies should also contain the element size. */
14691 arm_cookie_has_size (void)
14693 return TARGET_AAPCS_BASED;
14697 /* The EABI says constructors and destructors should return a pointer to
14698 the object constructed/destroyed. */
14701 arm_cxx_cdtor_returns_this (void)
14703 return TARGET_AAPCS_BASED;
14708 arm_set_return_address (rtx source, rtx scratch)
14710 arm_stack_offsets *offsets;
14711 HOST_WIDE_INT delta;
14713 unsigned long saved_regs;
14715 saved_regs = arm_compute_save_reg_mask ();
14717 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14718 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14721 if (frame_pointer_needed)
14722 addr = plus_constant(hard_frame_pointer_rtx, -4);
14725 /* LR will be the first saved register. */
14726 offsets = arm_get_frame_offsets ();
14727 delta = offsets->outgoing_args - (offsets->frame + 4);
14732 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14733 GEN_INT (delta & ~4095)));
14738 addr = stack_pointer_rtx;
14740 addr = plus_constant (addr, delta);
14742 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14748 thumb_set_return_address (rtx source, rtx scratch)
14750 arm_stack_offsets *offsets;
14751 HOST_WIDE_INT delta;
14754 unsigned long mask;
14756 emit_insn (gen_rtx_USE (VOIDmode, source));
14758 mask = thumb_compute_save_reg_mask ();
14759 if (mask & (1 << LR_REGNUM))
14761 offsets = arm_get_frame_offsets ();
14763 /* Find the saved regs. */
14764 if (frame_pointer_needed)
14766 delta = offsets->soft_frame - offsets->saved_args;
14767 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14771 delta = offsets->outgoing_args - offsets->saved_args;
14774 /* Allow for the stack frame. */
14775 if (TARGET_BACKTRACE)
14777 /* The link register is always the first saved register. */
14780 /* Construct the address. */
14781 addr = gen_rtx_REG (SImode, reg);
14782 if ((reg != SP_REGNUM && delta >= 128)
14785 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14786 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14790 addr = plus_constant (addr, delta);
14792 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14795 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);