1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 static int max_insns_skipped = 5;
46 extern FILE * asm_out_file;
47 /* Some function declarations. */
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char * output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((rtx, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char * shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
71 static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));
73 /* True if we are currently building a constant table. */
74 int making_const_table;
76 /* Define the information needed to generate branch insns. This is
77 stored from the compare operation. */
78 rtx arm_compare_op0, arm_compare_op1;
80 /* What type of floating point are we tuning for? */
81 enum floating_point_type arm_fpu;
83 /* What type of floating point instructions are available? */
84 enum floating_point_type arm_fpu_arch;
86 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
87 enum prog_mode_type arm_prgmode;
89 /* Set by the -mfp=... option */
90 const char * target_fp_name = NULL;
92 /* Used to parse -mstructure_size_boundary command line option. */
93 const char * structure_size_string = NULL;
94 int arm_structure_size_boundary = 32; /* Used to be 8 */
96 /* Bit values used to identify processor capabilities. */
97 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
98 #define FL_FAST_MULT 0x02 /* Fast multiply */
99 #define FL_MODE26 0x04 /* 26-bit mode support */
100 #define FL_MODE32 0x08 /* 32-bit mode support */
101 #define FL_ARCH4 0x10 /* Architecture rel 4 */
102 #define FL_THUMB 0x20 /* Thumb aware */
103 #define FL_LDSCHED 0x40 /* Load scheduling necessary */
104 #define FL_STRONG 0x80 /* StrongARM */
106 /* The bits in this mask specify which instructions we are allowed to generate. */
107 static int insn_flags = 0;
108 /* The bits in this mask specify which instruction scheduling options should
109 be used. Note - there is an overlap with the FL_FAST_MULT. For some
110 hardware we want to be able to generate the multiply instructions, but to
111 tune as if they were not present in the architecture. */
112 static int tune_flags = 0;
114 /* The following are used in the arm.md file as equivalents to bits
115 in the above two flag variables. */
117 /* Nonzero if this is an "M" variant of the processor. */
118 int arm_fast_multiply = 0;
120 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
123 /* Nonzero if this chip can benefit from load scheduling. */
124 int arm_ld_sched = 0;
126 /* Nonzero if this chip is a StrongARM. */
127 int arm_is_strong = 0;
129 /* Nonzero if this chip is a an ARM6 or an ARM7. */
130 int arm_is_6_or_7 = 0;
132 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
133 must report the mode of the memory reference from PRINT_OPERAND to
134 PRINT_OPERAND_ADDRESS. */
135 enum machine_mode output_memory_reference_mode;
137 /* Nonzero if the prologue must setup `fp'. */
138 int current_function_anonymous_args;
140 /* The register number to be used for the PIC offset register. */
141 int arm_pic_register = 9;
143 /* Location counter of .text segment. */
144 int arm_text_location = 0;
146 /* Set to one if we think that lr is only saved because of subroutine calls,
147 but all of these can be `put after' return insns */
148 int lr_save_eliminated;
150 /* Set to 1 when a return insn is output, this means that the epilogue
152 static int return_used_this_function;
154 /* Set to 1 after arm_reorg has started. Reset to start at the start of
155 the next function. */
156 static int after_arm_reorg = 0;
158 /* The maximum number of insns to be used when loading a constant. */
159 static int arm_constant_limit = 3;
161 /* For an explanation of these variables, see final_prescan_insn below. */
163 enum arm_cond_code arm_current_cc;
165 int arm_target_label;
167 /* The condition codes of the ARM, and the inverse function. */
168 char * arm_condition_codes[] =
170 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
171 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
174 static enum arm_cond_code get_arm_condition_code ();
176 #define streq(string1, string2) (strcmp (string1, string2) == 0)
178 /* Initialization code */
186 /* Not all of these give usefully different compilation alternatives,
187 but there is no simple way of generalizing them. */
188 static struct processors all_cores[] =
192 {"arm2", FL_CO_PROC | FL_MODE26 },
193 {"arm250", FL_CO_PROC | FL_MODE26 },
194 {"arm3", FL_CO_PROC | FL_MODE26 },
195 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
196 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
197 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
198 {"arm610", FL_MODE26 | FL_MODE32 },
199 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
200 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
201 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */
202 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* but only with D, (and I), */
203 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */
204 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* so arm7m is sometimes used. */
205 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
206 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
208 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
209 {"arm710", FL_MODE26 | FL_MODE32 },
210 {"arm710c", FL_MODE26 | FL_MODE32 },
211 {"arm7100", FL_MODE26 | FL_MODE32 },
212 {"arm7500", FL_MODE26 | FL_MODE32 },
213 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu. */
214 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
215 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
216 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
217 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
218 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
219 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
220 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
221 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
222 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
223 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
228 static struct processors all_architectures[] =
230 /* ARM Architectures */
232 {"armv2", FL_CO_PROC | FL_MODE26 },
233 {"armv2a", FL_CO_PROC | FL_MODE26 },
234 {"armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
235 {"armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
236 {"armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
237 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
238 implementations that support it, so we will leave it out for now. */
239 {"armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
243 /* This is a magic stucture. The 'string' field is magically filled in
244 with a pointer to the value specified by the user on the command line
245 assuming that the user has specified such a value. */
247 struct arm_cpu_select arm_select[] =
249 /* string name processors */
250 { NULL, "-mcpu=", all_cores },
251 { NULL, "-march=", all_architectures },
252 { NULL, "-mtune=", all_cores }
255 /* Return the number of bits set in value' */
260 unsigned int count = 0;
264 value &= ~(value & - value);
271 /* Fix up any incompatible options that the user has specified.
272 This has now turned into a maze. */
274 arm_override_options ()
278 /* Set up the flags based on the cpu/architecture selected by the user. */
279 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
281 struct arm_cpu_select * ptr = arm_select + i;
283 if (ptr->string != NULL && ptr->string[0] != '\0')
285 const struct processors * sel;
287 for (sel = ptr->processors; sel->name != NULL; sel ++)
288 if (streq (ptr->string, sel->name))
291 tune_flags = sel->flags;
294 /* If we have been given an architecture and a processor
295 make sure that they are compatible. We only generate
296 a warning though, and we prefer the CPU over the
298 if (insn_flags != 0 && (insn_flags ^ sel->flags))
299 warning ("switch -mcpu=%s conflicts with -march= switch",
302 insn_flags = sel->flags;
308 if (sel->name == NULL)
309 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
313 /* If the user did not specify a processor, choose one for them. */
316 struct processors * sel;
318 static struct cpu_default
325 { TARGET_CPU_arm2, "arm2" },
326 { TARGET_CPU_arm6, "arm6" },
327 { TARGET_CPU_arm610, "arm610" },
328 { TARGET_CPU_arm710, "arm710" },
329 { TARGET_CPU_arm7m, "arm7m" },
330 { TARGET_CPU_arm7500fe, "arm7500fe" },
331 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
332 { TARGET_CPU_arm8, "arm8" },
333 { TARGET_CPU_arm810, "arm810" },
334 { TARGET_CPU_arm9, "arm9" },
335 { TARGET_CPU_strongarm, "strongarm" },
336 { TARGET_CPU_generic, "arm" },
339 struct cpu_default * def;
341 /* Find the default. */
342 for (def = cpu_defaults; def->name; def ++)
343 if (def->cpu == TARGET_CPU_DEFAULT)
346 /* Make sure we found the default CPU. */
347 if (def->name == NULL)
350 /* Find the default CPU's flags. */
351 for (sel = all_cores; sel->name != NULL; sel ++)
352 if (streq (def->name, sel->name))
355 if (sel->name == NULL)
358 insn_flags = sel->flags;
360 /* Now check to see if the user has specified some command line
361 switch that require certain abilities from the cpu. */
364 if (TARGET_THUMB_INTERWORK)
366 sought |= (FL_THUMB | FL_MODE32);
368 /* Force apcs-32 to be used for interworking. */
369 target_flags |= ARM_FLAG_APCS_32;
371 /* There are no ARM processor that supports both APCS-26 and
372 interworking. Therefore we force FL_MODE26 to be removed
373 from insn_flags here (if it was set), so that the search
374 below will always be able to find a compatible processor. */
375 insn_flags &= ~ FL_MODE26;
378 if (! TARGET_APCS_32)
381 if (sought != 0 && ((sought & insn_flags) != sought))
383 /* Try to locate a CPU type that supports all of the abilities
384 of the default CPU, plus the extra abilities requested by
386 for (sel = all_cores; sel->name != NULL; sel ++)
387 if ((sel->flags & sought) == (sought | insn_flags))
390 if (sel->name == NULL)
392 unsigned int current_bit_count = 0;
393 struct processors * best_fit = NULL;
395 /* Ideally we would like to issue an error message here
396 saying that it was not possible to find a CPU compatible
397 with the default CPU, but which also supports the command
398 line options specified by the programmer, and so they
399 ought to use the -mcpu=<name> command line option to
400 override the default CPU type.
402 Unfortunately this does not work with multilibing. We
403 need to be able to support multilibs for -mapcs-26 and for
404 -mthumb-interwork and there is no CPU that can support both
405 options. Instead if we cannot find a cpu that has both the
406 characteristics of the default cpu and the given command line
407 options we scan the array again looking for a best match. */
408 for (sel = all_cores; sel->name != NULL; sel ++)
409 if ((sel->flags & sought) == sought)
413 count = bit_count (sel->flags & insn_flags);
415 if (count >= current_bit_count)
418 current_bit_count = count;
422 if (best_fit == NULL)
428 insn_flags = sel->flags;
432 /* If tuning has not been specified, tune for whichever processor or
433 architecture has been selected. */
435 tune_flags = insn_flags;
437 /* Make sure that the processor choice does not conflict with any of the
438 other command line choices. */
439 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
441 /* If APCS-32 was not the default then it must have been set by the
442 user, so issue a warning message. If the user has specified
443 "-mapcs-32 -mcpu=arm2" then we loose here. */
444 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
445 warning ("target CPU does not support APCS-32" );
446 target_flags &= ~ ARM_FLAG_APCS_32;
448 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
450 warning ("target CPU does not support APCS-26" );
451 target_flags |= ARM_FLAG_APCS_32;
454 if (TARGET_THUMB_INTERWORK && !(insn_flags & FL_THUMB))
456 warning ("target CPU does not support interworking" );
457 target_flags &= ~ARM_FLAG_THUMB;
460 /* If interworking is enabled then APCS-32 must be selected as well. */
461 if (TARGET_THUMB_INTERWORK)
463 if (! TARGET_APCS_32)
464 warning ("interworking forces APCS-32 to be used" );
465 target_flags |= ARM_FLAG_APCS_32;
468 if (TARGET_APCS_STACK && ! TARGET_APCS)
470 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
471 target_flags |= ARM_FLAG_APCS_FRAME;
474 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
475 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
477 if (TARGET_POKE_FUNCTION_NAME)
478 target_flags |= ARM_FLAG_APCS_FRAME;
480 if (TARGET_APCS_REENT && flag_pic)
481 fatal ("-fpic and -mapcs-reent are incompatible");
483 if (TARGET_APCS_REENT)
484 warning ("APCS reentrant code not supported. Ignored");
486 /* If stack checking is disabled, we can use r10 as the PIC register,
487 which keeps r9 available. */
488 if (flag_pic && ! TARGET_APCS_STACK)
489 arm_pic_register = 10;
491 /* Well, I'm about to have a go, but pic is NOT going to be compatible
492 with APCS reentrancy, since that requires too much support in the
493 assembler and linker, and the ARMASM assembler seems to lack some
494 required directives. */
496 warning ("Position independent code not supported");
498 if (TARGET_APCS_FLOAT)
499 warning ("Passing floating point arguments in fp regs not yet supported");
501 /* Initialise boolean versions of the flags, for use in the arm.md file. */
502 arm_fast_multiply = insn_flags & FL_FAST_MULT;
503 arm_arch4 = insn_flags & FL_ARCH4;
505 arm_ld_sched = tune_flags & FL_LDSCHED;
506 arm_is_strong = tune_flags & FL_STRONG;
507 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
508 && !(tune_flags & FL_ARCH4));
510 /* Default value for floating point code... if no co-processor
511 bus, then schedule for emulated floating point. Otherwise,
512 assume the user has an FPA.
513 Note: this does not prevent use of floating point instructions,
514 -msoft-float does that. */
515 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
519 if (streq (target_fp_name, "2"))
520 arm_fpu_arch = FP_SOFT2;
521 else if (streq (target_fp_name, "3"))
522 arm_fpu_arch = FP_SOFT3;
524 fatal ("Invalid floating point emulation option: -mfpe-%s",
528 arm_fpu_arch = FP_DEFAULT;
530 if (TARGET_FPE && arm_fpu != FP_HARD)
533 /* For arm2/3 there is no need to do any scheduling if there is only
534 a floating point emulator, or we are doing software floating-point. */
535 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && (tune_flags & FL_MODE32) == 0)
536 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
538 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
540 if (structure_size_string != NULL)
542 int size = strtol (structure_size_string, NULL, 0);
544 if (size == 8 || size == 32)
545 arm_structure_size_boundary = size;
547 warning ("Structure size boundary can only be set to 8 or 32");
550 /* If optimizing for space, don't synthesize constants.
551 For processors with load scheduling, it never costs more than 2 cycles
552 to load a constant, and the load scheduler may well reduce that to 1. */
553 if (optimize_size || (tune_flags & FL_LDSCHED))
554 arm_constant_limit = 1;
556 /* If optimizing for size, bump the number of instructions that we
557 are prepared to conditionally execute (even on a StrongARM).
558 Otherwise for the StrongARM, which has early execution of branches,
559 a sequence that is worth skipping is shorter. */
561 max_insns_skipped = 6;
562 else if (arm_is_strong)
563 max_insns_skipped = 3;
566 /* Return 1 if it is possible to return using a single instruction */
569 use_return_insn (iscond)
574 if (!reload_completed
575 || current_function_pretend_args_size
576 || current_function_anonymous_args
577 || ((get_frame_size () + current_function_outgoing_args_size != 0)
578 && !(TARGET_APCS && frame_pointer_needed)))
581 /* Can't be done if interworking with Thumb, and any registers have been
582 stacked. Similarly, on StrongARM, conditional returns are expensive
583 if they aren't taken and registers have been stacked. */
584 if (iscond && arm_is_strong && frame_pointer_needed)
586 if ((iscond && arm_is_strong)
587 || TARGET_THUMB_INTERWORK)
589 for (regno = 0; regno < 16; regno++)
590 if (regs_ever_live[regno] && ! call_used_regs[regno])
593 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
597 /* Can't be done if any of the FPU regs are pushed, since this also
599 for (regno = 16; regno < 24; regno++)
600 if (regs_ever_live[regno] && ! call_used_regs[regno])
603 /* If a function is naked, don't use the "return" insn. */
604 if (arm_naked_function_p (current_function_decl))
610 /* Return TRUE if int I is a valid immediate ARM constant. */
616 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
618 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
619 be all zero, or all one. */
620 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
621 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
622 != ((~(unsigned HOST_WIDE_INT) 0)
623 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
626 /* Fast return for 0 and powers of 2 */
627 if ((i & (i - 1)) == 0)
632 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
635 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
636 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
637 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
642 /* Return true if I is a valid constant for the operation CODE. */
644 const_ok_for_op (i, code)
648 if (const_ok_for_arm (i))
654 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
656 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
662 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
669 /* Emit a sequence of insns to handle a large constant.
670 CODE is the code of the operation required, it can be any of SET, PLUS,
671 IOR, AND, XOR, MINUS;
672 MODE is the mode in which the operation is being performed;
673 VAL is the integer to operate on;
674 SOURCE is the other operand (a register, or a null-pointer for SET);
675 SUBTARGETS means it is safe to create scratch registers if that will
676 either produce a simpler sequence, or we will want to cse the values.
677 Return value is the number of insns emitted. */
680 arm_split_constant (code, mode, val, target, source, subtargets)
682 enum machine_mode mode;
688 if (subtargets || code == SET
689 || (GET_CODE (target) == REG && GET_CODE (source) == REG
690 && REGNO (target) != REGNO (source)))
692 /* After arm_reorg has been called, we can't fix up expensive
693 constants by pushing them into memory so we must synthesise
694 them in-line, regardless of the cost. This is only likely to
695 be more costly on chips that have load delay slots and we are
696 compiling without running the scheduler (so no splitting
697 occurred before the final instruction emission).
699 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
701 if (! after_arm_reorg
702 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
703 > arm_constant_limit + (code != SET)))
707 /* Currently SET is the only monadic value for CODE, all
708 the rest are diadic. */
709 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
714 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
716 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
717 /* For MINUS, the value is subtracted from, since we never
718 have subtraction of a constant. */
720 emit_insn (gen_rtx_SET (VOIDmode, target,
721 gen_rtx (code, mode, temp, source)));
723 emit_insn (gen_rtx_SET (VOIDmode, target,
724 gen_rtx (code, mode, source, temp)));
730 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
733 /* As above, but extra parameter GENERATE which, if clear, suppresses
736 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
738 enum machine_mode mode;
747 int can_negate_initial = 0;
750 int num_bits_set = 0;
751 int set_sign_bit_copies = 0;
752 int clear_sign_bit_copies = 0;
753 int clear_zero_bit_copies = 0;
754 int set_zero_bit_copies = 0;
756 unsigned HOST_WIDE_INT temp1, temp2;
757 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
759 /* find out which operations are safe for a given CODE. Also do a quick
760 check for degenerate cases; these can occur when DImode operations
772 can_negate_initial = 1;
776 if (remainder == 0xffffffff)
779 emit_insn (gen_rtx_SET (VOIDmode, target,
780 GEN_INT (ARM_SIGN_EXTEND (val))));
785 if (reload_completed && rtx_equal_p (target, source))
788 emit_insn (gen_rtx_SET (VOIDmode, target, source));
797 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
800 if (remainder == 0xffffffff)
802 if (reload_completed && rtx_equal_p (target, source))
805 emit_insn (gen_rtx_SET (VOIDmode, target, source));
814 if (reload_completed && rtx_equal_p (target, source))
817 emit_insn (gen_rtx_SET (VOIDmode, target, source));
820 if (remainder == 0xffffffff)
823 emit_insn (gen_rtx_SET (VOIDmode, target,
824 gen_rtx_NOT (mode, source)));
828 /* We don't know how to handle this yet below. */
832 /* We treat MINUS as (val - source), since (source - val) is always
833 passed as (source + (-val)). */
837 emit_insn (gen_rtx_SET (VOIDmode, target,
838 gen_rtx_NEG (mode, source)));
841 if (const_ok_for_arm (val))
844 emit_insn (gen_rtx_SET (VOIDmode, target,
845 gen_rtx_MINUS (mode, GEN_INT (val),
857 /* If we can do it in one insn get out quickly */
858 if (const_ok_for_arm (val)
859 || (can_negate_initial && const_ok_for_arm (-val))
860 || (can_invert && const_ok_for_arm (~val)))
863 emit_insn (gen_rtx_SET (VOIDmode, target,
864 (source ? gen_rtx (code, mode, source,
871 /* Calculate a few attributes that may be useful for specific
874 for (i = 31; i >= 0; i--)
876 if ((remainder & (1 << i)) == 0)
877 clear_sign_bit_copies++;
882 for (i = 31; i >= 0; i--)
884 if ((remainder & (1 << i)) != 0)
885 set_sign_bit_copies++;
890 for (i = 0; i <= 31; i++)
892 if ((remainder & (1 << i)) == 0)
893 clear_zero_bit_copies++;
898 for (i = 0; i <= 31; i++)
900 if ((remainder & (1 << i)) != 0)
901 set_zero_bit_copies++;
909 /* See if we can do this by sign_extending a constant that is known
910 to be negative. This is a good, way of doing it, since the shift
911 may well merge into a subsequent insn. */
912 if (set_sign_bit_copies > 1)
915 (temp1 = ARM_SIGN_EXTEND (remainder
916 << (set_sign_bit_copies - 1))))
920 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
921 emit_insn (gen_rtx_SET (VOIDmode, new_src,
923 emit_insn (gen_ashrsi3 (target, new_src,
924 GEN_INT (set_sign_bit_copies - 1)));
928 /* For an inverted constant, we will need to set the low bits,
929 these will be shifted out of harm's way. */
930 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
931 if (const_ok_for_arm (~temp1))
935 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
936 emit_insn (gen_rtx_SET (VOIDmode, new_src,
938 emit_insn (gen_ashrsi3 (target, new_src,
939 GEN_INT (set_sign_bit_copies - 1)));
945 /* See if we can generate this by setting the bottom (or the top)
946 16 bits, and then shifting these into the other half of the
947 word. We only look for the simplest cases, to do more would cost
948 too much. Be careful, however, not to generate this when the
949 alternative would take fewer insns. */
950 if (val & 0xffff0000)
952 temp1 = remainder & 0xffff0000;
953 temp2 = remainder & 0x0000ffff;
955 /* Overlaps outside this range are best done using other methods. */
956 for (i = 9; i < 24; i++)
958 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
959 && ! const_ok_for_arm (temp2))
961 rtx new_src = (subtargets
962 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
964 insns = arm_gen_constant (code, mode, temp2, new_src,
965 source, subtargets, generate);
968 emit_insn (gen_rtx_SET
971 gen_rtx_ASHIFT (mode, source,
978 /* Don't duplicate cases already considered. */
979 for (i = 17; i < 24; i++)
981 if (((temp1 | (temp1 >> i)) == remainder)
982 && ! const_ok_for_arm (temp1))
984 rtx new_src = (subtargets
985 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
987 insns = arm_gen_constant (code, mode, temp1, new_src,
988 source, subtargets, generate);
992 (gen_rtx_SET (VOIDmode, target,
995 gen_rtx_LSHIFTRT (mode, source,
1006 /* If we have IOR or XOR, and the constant can be loaded in a
1007 single instruction, and we can find a temporary to put it in,
1008 then this can be done in two instructions instead of 3-4. */
1010 /* TARGET can't be NULL if SUBTARGETS is 0 */
1011 || (reload_completed && ! reg_mentioned_p (target, source)))
1013 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1017 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1019 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1020 emit_insn (gen_rtx_SET (VOIDmode, target,
1021 gen_rtx (code, mode, source, sub)));
1030 if (set_sign_bit_copies > 8
1031 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1035 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1036 rtx shift = GEN_INT (set_sign_bit_copies);
1038 emit_insn (gen_rtx_SET (VOIDmode, sub,
1040 gen_rtx_ASHIFT (mode,
1043 emit_insn (gen_rtx_SET (VOIDmode, target,
1045 gen_rtx_LSHIFTRT (mode, sub,
1051 if (set_zero_bit_copies > 8
1052 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1056 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1057 rtx shift = GEN_INT (set_zero_bit_copies);
1059 emit_insn (gen_rtx_SET (VOIDmode, sub,
1061 gen_rtx_LSHIFTRT (mode,
1064 emit_insn (gen_rtx_SET (VOIDmode, target,
1066 gen_rtx_ASHIFT (mode, sub,
1072 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1076 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1077 emit_insn (gen_rtx_SET (VOIDmode, sub,
1078 gen_rtx_NOT (mode, source)));
1081 sub = gen_reg_rtx (mode);
1082 emit_insn (gen_rtx_SET (VOIDmode, sub,
1083 gen_rtx_AND (mode, source,
1085 emit_insn (gen_rtx_SET (VOIDmode, target,
1086 gen_rtx_NOT (mode, sub)));
1093 /* See if two shifts will do 2 or more insn's worth of work. */
1094 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1096 HOST_WIDE_INT shift_mask = ((0xffffffff
1097 << (32 - clear_sign_bit_copies))
1100 if ((remainder | shift_mask) != 0xffffffff)
1104 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1105 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1106 new_src, source, subtargets, 1);
1111 rtx targ = subtargets ? NULL_RTX : target;
1112 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1113 targ, source, subtargets, 0);
1119 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1120 rtx shift = GEN_INT (clear_sign_bit_copies);
1122 emit_insn (gen_ashlsi3 (new_src, source, shift));
1123 emit_insn (gen_lshrsi3 (target, new_src, shift));
1129 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1131 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1133 if ((remainder | shift_mask) != 0xffffffff)
1137 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1139 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1140 new_src, source, subtargets, 1);
1145 rtx targ = subtargets ? NULL_RTX : target;
1147 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1148 targ, source, subtargets, 0);
1154 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1155 rtx shift = GEN_INT (clear_zero_bit_copies);
1157 emit_insn (gen_lshrsi3 (new_src, source, shift));
1158 emit_insn (gen_ashlsi3 (target, new_src, shift));
1170 for (i = 0; i < 32; i++)
1171 if (remainder & (1 << i))
1174 if (code == AND || (can_invert && num_bits_set > 16))
1175 remainder = (~remainder) & 0xffffffff;
1176 else if (code == PLUS && num_bits_set > 16)
1177 remainder = (-remainder) & 0xffffffff;
1184 /* Now try and find a way of doing the job in either two or three
1186 We start by looking for the largest block of zeros that are aligned on
1187 a 2-bit boundary, we then fill up the temps, wrapping around to the
1188 top of the word when we drop off the bottom.
1189 In the worst case this code should produce no more than four insns. */
1192 int best_consecutive_zeros = 0;
1194 for (i = 0; i < 32; i += 2)
1196 int consecutive_zeros = 0;
1198 if (! (remainder & (3 << i)))
1200 while ((i < 32) && ! (remainder & (3 << i)))
1202 consecutive_zeros += 2;
1205 if (consecutive_zeros > best_consecutive_zeros)
1207 best_consecutive_zeros = consecutive_zeros;
1208 best_start = i - consecutive_zeros;
1214 /* Now start emitting the insns, starting with the one with the highest
1215 bit set: we do this so that the smallest number will be emitted last;
1216 this is more likely to be combinable with addressing insns. */
1224 if (remainder & (3 << (i - 2)))
1229 temp1 = remainder & ((0x0ff << end)
1230 | ((i < end) ? (0xff >> (32 - end)) : 0));
1231 remainder &= ~temp1;
1238 emit_insn (gen_rtx_SET (VOIDmode,
1239 new_src = (subtargets
1240 ? gen_reg_rtx (mode)
1243 ? ~temp1 : temp1)));
1244 else if (code == MINUS)
1245 emit_insn (gen_rtx_SET (VOIDmode,
1246 new_src = (subtargets
1247 ? gen_reg_rtx (mode)
1249 gen_rtx (code, mode, GEN_INT (temp1),
1252 emit_insn (gen_rtx_SET (VOIDmode,
1253 new_src = (remainder
1255 ? gen_reg_rtx (mode)
1258 gen_rtx (code, mode, source,
1259 GEN_INT (can_invert ? ~temp1
1271 else if (code == MINUS)
1278 } while (remainder);
1283 /* Canonicalize a comparison so that we are more likely to recognize it.
1284 This can be done for a few constant compares, where we can make the
1285 immediate value easier to load. */
1287 arm_canonicalize_comparison (code, op1)
1291 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1301 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1303 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1305 *op1 = GEN_INT (i+1);
1306 return code == GT ? GE : LT;
1312 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1313 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1315 *op1 = GEN_INT (i-1);
1316 return code == GE ? GT : LE;
1322 if (i != ~((unsigned HOST_WIDE_INT) 0)
1323 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1325 *op1 = GEN_INT (i + 1);
1326 return code == GTU ? GEU : LTU;
1333 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1335 *op1 = GEN_INT (i - 1);
1336 return code == GEU ? GTU : LEU;
1347 /* Decide whether a type should be returned in memory (true)
1348 or in a register (false). This is called by the macro
1349 RETURN_IN_MEMORY. */
1351 arm_return_in_memory (type)
1354 if (! AGGREGATE_TYPE_P (type))
1356 /* All simple types are returned in registers. */
1359 else if (int_size_in_bytes (type) > 4)
1361 /* All structures/unions bigger than one word are returned in memory. */
1364 else if (TREE_CODE (type) == RECORD_TYPE)
1368 /* For a struct the APCS says that we must return in a register if
1369 every addressable element has an offset of zero. For practical
1370 purposes this means that the structure can have at most one non
1371 bit-field element and that this element must be the first one in
1374 /* Find the first field, ignoring non FIELD_DECL things which will
1375 have been created by C++. */
1376 for (field = TYPE_FIELDS (type);
1377 field && TREE_CODE (field) != FIELD_DECL;
1378 field = TREE_CHAIN (field))
1382 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1384 /* Now check the remaining fields, if any. */
1385 for (field = TREE_CHAIN (field);
1387 field = TREE_CHAIN (field))
1389 if (TREE_CODE (field) != FIELD_DECL)
1392 if (! DECL_BIT_FIELD_TYPE (field))
1398 else if (TREE_CODE (type) == UNION_TYPE)
1402 /* Unions can be returned in registers if every element is
1403 integral, or can be returned in an integer register. */
1404 for (field = TYPE_FIELDS (type);
1406 field = TREE_CHAIN (field))
1408 if (TREE_CODE (field) != FIELD_DECL)
1411 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1414 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1421 /* XXX Not sure what should be done for other aggregates, so put them in
1427 legitimate_pic_operand_p (x)
1430 if (CONSTANT_P (x) && flag_pic
1431 && (GET_CODE (x) == SYMBOL_REF
1432 || (GET_CODE (x) == CONST
1433 && GET_CODE (XEXP (x, 0)) == PLUS
1434 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1441 legitimize_pic_address (orig, mode, reg)
1443 enum machine_mode mode;
1446 if (GET_CODE (orig) == SYMBOL_REF)
1448 rtx pic_ref, address;
1454 if (reload_in_progress || reload_completed)
1457 reg = gen_reg_rtx (Pmode);
1462 #ifdef AOF_ASSEMBLER
1463 /* The AOF assembler can generate relocations for these directly, and
1464 understands that the PIC register has to be added into the offset.
1466 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1469 address = gen_reg_rtx (Pmode);
1473 emit_insn (gen_pic_load_addr (address, orig));
1475 pic_ref = gen_rtx_MEM (Pmode,
1476 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1478 RTX_UNCHANGING_P (pic_ref) = 1;
1479 insn = emit_move_insn (reg, pic_ref);
1481 current_function_uses_pic_offset_table = 1;
1482 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1484 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1488 else if (GET_CODE (orig) == CONST)
1492 if (GET_CODE (XEXP (orig, 0)) == PLUS
1493 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1498 if (reload_in_progress || reload_completed)
1501 reg = gen_reg_rtx (Pmode);
1504 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1506 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1507 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1508 base == reg ? 0 : reg);
1513 if (GET_CODE (offset) == CONST_INT)
1515 /* The base register doesn't really matter, we only want to
1516 test the index for the appropriate mode. */
1517 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1519 if (! reload_in_progress && ! reload_completed)
1520 offset = force_reg (Pmode, offset);
1525 if (GET_CODE (offset) == CONST_INT)
1526 return plus_constant_for_output (base, INTVAL (offset));
1529 if (GET_MODE_SIZE (mode) > 4
1530 && (GET_MODE_CLASS (mode) == MODE_INT
1531 || TARGET_SOFT_FLOAT))
1533 emit_insn (gen_addsi3 (reg, base, offset));
1537 return gen_rtx_PLUS (Pmode, base, offset);
1539 else if (GET_CODE (orig) == LABEL_REF)
1540 current_function_uses_pic_offset_table = 1;
1559 #ifndef AOF_ASSEMBLER
1560 rtx l1, pic_tmp, pic_tmp2, seq;
1561 rtx global_offset_table;
1563 if (current_function_uses_pic_offset_table == 0)
1570 l1 = gen_label_rtx ();
1572 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1573 /* On the ARM the PC register contains 'dot + 8' at the time of the
1575 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1577 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1578 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1580 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1582 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1584 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1585 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1587 seq = gen_sequence ();
1589 emit_insn_after (seq, get_insns ());
1591 /* Need to emit this whether or not we obey regdecls,
1592 since setjmp/longjmp can cause life info to screw up. */
1593 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1594 #endif /* AOF_ASSEMBLER */
1597 #define REG_OR_SUBREG_REG(X) \
1598 (GET_CODE (X) == REG \
1599 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1601 #define REG_OR_SUBREG_RTX(X) \
1602 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1604 #define ARM_FRAME_RTX(X) \
1605 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1606 || (X) == arg_pointer_rtx)
1609 arm_rtx_costs (x, code)
1613 enum machine_mode mode = GET_MODE (x);
1614 enum rtx_code subcode;
1620 /* Memory costs quite a lot for the first word, but subsequent words
1621 load at the equivalent of a single insn each. */
1622 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1623 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1630 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1637 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1639 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1640 + ((GET_CODE (XEXP (x, 0)) == REG
1641 || (GET_CODE (XEXP (x, 0)) == SUBREG
1642 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1644 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1645 || (GET_CODE (XEXP (x, 0)) == SUBREG
1646 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1648 + ((GET_CODE (XEXP (x, 1)) == REG
1649 || (GET_CODE (XEXP (x, 1)) == SUBREG
1650 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1651 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1656 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1657 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1658 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1659 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1662 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1663 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1664 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1665 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1667 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1668 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1669 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1672 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1673 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1674 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1675 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1676 || subcode == ASHIFTRT || subcode == LSHIFTRT
1677 || subcode == ROTATE || subcode == ROTATERT
1679 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1680 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1681 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1682 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1683 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1684 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1685 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1690 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1691 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1692 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1693 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1694 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1698 case AND: case XOR: case IOR:
1701 /* Normally the frame registers will be spilt into reg+const during
1702 reload, so it is a bad idea to combine them with other instructions,
1703 since then they might not be moved outside of loops. As a compromise
1704 we allow integration with ops that have a constant as their second
1706 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1707 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1708 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1709 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1710 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1714 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1715 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1716 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1717 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1720 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1721 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1722 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1723 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1724 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1727 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1728 return (1 + extra_cost
1729 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1730 || subcode == LSHIFTRT || subcode == ASHIFTRT
1731 || subcode == ROTATE || subcode == ROTATERT
1733 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1734 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1735 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1736 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1737 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1738 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1744 /* There is no point basing this on the tuning, since it is always the
1745 fast variant if it exists at all */
1746 if (arm_fast_multiply && mode == DImode
1747 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1748 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1749 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1752 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1756 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1758 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1759 & (unsigned HOST_WIDE_INT) 0xffffffff);
1760 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1762 /* Tune as appropriate */
1763 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1765 for (j = 0; i && j < 32; j += booth_unit_size)
1767 i >>= booth_unit_size;
1774 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1775 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1776 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1779 if (arm_fast_multiply && mode == SImode
1780 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1781 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1782 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1783 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1784 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1785 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1790 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1791 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1795 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1797 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1800 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1808 return 4 + (mode == DImode ? 4 : 0);
1811 if (GET_MODE (XEXP (x, 0)) == QImode)
1812 return (4 + (mode == DImode ? 4 : 0)
1813 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1816 switch (GET_MODE (XEXP (x, 0)))
1819 return (1 + (mode == DImode ? 4 : 0)
1820 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1823 return (4 + (mode == DImode ? 4 : 0)
1824 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1827 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1840 arm_adjust_cost (insn, link, dep, cost)
1848 /* XXX This is not strictly true for the FPA. */
1849 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
1850 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
1853 if ((i_pat = single_set (insn)) != NULL
1854 && GET_CODE (SET_SRC (i_pat)) == MEM
1855 && (d_pat = single_set (dep)) != NULL
1856 && GET_CODE (SET_DEST (d_pat)) == MEM)
1858 /* This is a load after a store, there is no conflict if the load reads
1859 from a cached area. Assume that loads from the stack, and from the
1860 constant pool are cached, and that others will miss. This is a
1863 /* debug_rtx (insn);
1866 fprintf (stderr, "costs %d\n", cost); */
1868 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1869 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1870 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1871 || reg_mentioned_p (hard_frame_pointer_rtx,
1872 XEXP (SET_SRC (i_pat), 0)))
1874 /* fprintf (stderr, "***** Now 1\n"); */
1882 /* This code has been fixed for cross compilation. */
1884 static int fpa_consts_inited = 0;
1886 char *strings_fpa[8] = {
1888 "4", "5", "0.5", "10"
1891 static REAL_VALUE_TYPE values_fpa[8];
1899 for (i = 0; i < 8; i++)
1901 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1905 fpa_consts_inited = 1;
1908 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1911 const_double_rtx_ok_for_fpu (x)
1917 if (!fpa_consts_inited)
1920 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1921 if (REAL_VALUE_MINUS_ZERO (r))
1924 for (i = 0; i < 8; i++)
1925 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1931 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1934 neg_const_double_rtx_ok_for_fpu (x)
1940 if (!fpa_consts_inited)
1943 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1944 r = REAL_VALUE_NEGATE (r);
1945 if (REAL_VALUE_MINUS_ZERO (r))
1948 for (i = 0; i < 8; i++)
1949 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1955 /* Predicates for `match_operand' and `match_operator'. */
1957 /* s_register_operand is the same as register_operand, but it doesn't accept
1960 This function exists because at the time it was put in it led to better
1961 code. SUBREG(MEM) always needs a reload in the places where
1962 s_register_operand is used, and this seemed to lead to excessive
1966 s_register_operand (op, mode)
1968 enum machine_mode mode;
1970 if (GET_MODE (op) != mode && mode != VOIDmode)
1973 if (GET_CODE (op) == SUBREG)
1974 op = SUBREG_REG (op);
1976 /* We don't consider registers whose class is NO_REGS
1977 to be a register operand. */
1978 return (GET_CODE (op) == REG
1979 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1980 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1983 /* Only accept reg, subreg(reg), const_int. */
1986 reg_or_int_operand (op, mode)
1988 enum machine_mode mode;
1990 if (GET_CODE (op) == CONST_INT)
1993 if (GET_MODE (op) != mode && mode != VOIDmode)
1996 if (GET_CODE (op) == SUBREG)
1997 op = SUBREG_REG (op);
1999 /* We don't consider registers whose class is NO_REGS
2000 to be a register operand. */
2001 return (GET_CODE (op) == REG
2002 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2003 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2006 /* Return 1 if OP is an item in memory, given that we are in reload. */
2009 reload_memory_operand (op, mode)
2011 enum machine_mode mode ATTRIBUTE_UNUSED;
2013 int regno = true_regnum (op);
2015 return (! CONSTANT_P (op)
2017 || (GET_CODE (op) == REG
2018 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2021 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2022 memory access (architecture V4) */
2024 bad_signed_byte_operand (op, mode)
2026 enum machine_mode mode;
2028 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2033 /* A sum of anything more complex than reg + reg or reg + const is bad */
2034 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2035 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2036 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2037 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2040 /* Big constants are also bad */
2041 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2042 && (INTVAL (XEXP (op, 1)) > 0xff
2043 || -INTVAL (XEXP (op, 1)) > 0xff))
2046 /* Everything else is good, or can will automatically be made so. */
2050 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2053 arm_rhs_operand (op, mode)
2055 enum machine_mode mode;
2057 return (s_register_operand (op, mode)
2058 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2061 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2065 arm_rhsm_operand (op, mode)
2067 enum machine_mode mode;
2069 return (s_register_operand (op, mode)
2070 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2071 || memory_operand (op, mode));
2074 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2075 constant that is valid when negated. */
2078 arm_add_operand (op, mode)
2080 enum machine_mode mode;
2082 return (s_register_operand (op, mode)
2083 || (GET_CODE (op) == CONST_INT
2084 && (const_ok_for_arm (INTVAL (op))
2085 || const_ok_for_arm (-INTVAL (op)))));
2089 arm_not_operand (op, mode)
2091 enum machine_mode mode;
2093 return (s_register_operand (op, mode)
2094 || (GET_CODE (op) == CONST_INT
2095 && (const_ok_for_arm (INTVAL (op))
2096 || const_ok_for_arm (~INTVAL (op)))));
2099 /* Return TRUE if the operand is a memory reference which contains an
2100 offsettable address. */
2102 offsettable_memory_operand (op, mode)
2104 enum machine_mode mode;
2106 if (mode == VOIDmode)
2107 mode = GET_MODE (op);
2109 return (mode == GET_MODE (op)
2110 && GET_CODE (op) == MEM
2111 && offsettable_address_p (reload_completed | reload_in_progress,
2112 mode, XEXP (op, 0)));
2115 /* Return TRUE if the operand is a memory reference which is, or can be
2116 made word aligned by adjusting the offset. */
2118 alignable_memory_operand (op, mode)
2120 enum machine_mode mode;
2124 if (mode == VOIDmode)
2125 mode = GET_MODE (op);
2127 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2132 return ((GET_CODE (reg = op) == REG
2133 || (GET_CODE (op) == SUBREG
2134 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2135 || (GET_CODE (op) == PLUS
2136 && GET_CODE (XEXP (op, 1)) == CONST_INT
2137 && (GET_CODE (reg = XEXP (op, 0)) == REG
2138 || (GET_CODE (XEXP (op, 0)) == SUBREG
2139 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2140 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2143 /* Similar to s_register_operand, but does not allow hard integer
2146 f_register_operand (op, mode)
2148 enum machine_mode mode;
2150 if (GET_MODE (op) != mode && mode != VOIDmode)
2153 if (GET_CODE (op) == SUBREG)
2154 op = SUBREG_REG (op);
2156 /* We don't consider registers whose class is NO_REGS
2157 to be a register operand. */
2158 return (GET_CODE (op) == REG
2159 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2160 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2163 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2166 fpu_rhs_operand (op, mode)
2168 enum machine_mode mode;
2170 if (s_register_operand (op, mode))
2172 else if (GET_CODE (op) == CONST_DOUBLE)
2173 return (const_double_rtx_ok_for_fpu (op));
2179 fpu_add_operand (op, mode)
2181 enum machine_mode mode;
2183 if (s_register_operand (op, mode))
2185 else if (GET_CODE (op) == CONST_DOUBLE)
2186 return (const_double_rtx_ok_for_fpu (op)
2187 || neg_const_double_rtx_ok_for_fpu (op));
2192 /* Return nonzero if OP is a constant power of two. */
2195 power_of_two_operand (op, mode)
2197 enum machine_mode mode ATTRIBUTE_UNUSED;
2199 if (GET_CODE (op) == CONST_INT)
2201 HOST_WIDE_INT value = INTVAL(op);
2202 return value != 0 && (value & (value - 1)) == 0;
2207 /* Return TRUE for a valid operand of a DImode operation.
2208 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2209 Note that this disallows MEM(REG+REG), but allows
2210 MEM(PRE/POST_INC/DEC(REG)). */
2213 di_operand (op, mode)
2215 enum machine_mode mode;
2217 if (s_register_operand (op, mode))
2220 if (GET_CODE (op) == SUBREG)
2221 op = SUBREG_REG (op);
2223 switch (GET_CODE (op))
2230 return memory_address_p (DImode, XEXP (op, 0));
2237 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2238 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2239 Note that this disallows MEM(REG+REG), but allows
2240 MEM(PRE/POST_INC/DEC(REG)). */
2243 soft_df_operand (op, mode)
2245 enum machine_mode mode;
2247 if (s_register_operand (op, mode))
2250 if (GET_CODE (op) == SUBREG)
2251 op = SUBREG_REG (op);
2253 switch (GET_CODE (op))
2259 return memory_address_p (DFmode, XEXP (op, 0));
2266 /* Return TRUE for valid index operands. */
2269 index_operand (op, mode)
2271 enum machine_mode mode;
2273 return (s_register_operand(op, mode)
2274 || (immediate_operand (op, mode)
2275 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2278 /* Return TRUE for valid shifts by a constant. This also accepts any
2279 power of two on the (somewhat overly relaxed) assumption that the
2280 shift operator in this case was a mult. */
2283 const_shift_operand (op, mode)
2285 enum machine_mode mode;
2287 return (power_of_two_operand (op, mode)
2288 || (immediate_operand (op, mode)
2289 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2292 /* Return TRUE for arithmetic operators which can be combined with a multiply
2296 shiftable_operator (x, mode)
2298 enum machine_mode mode;
2300 if (GET_MODE (x) != mode)
2304 enum rtx_code code = GET_CODE (x);
2306 return (code == PLUS || code == MINUS
2307 || code == IOR || code == XOR || code == AND);
2311 /* Return TRUE for shift operators. */
2314 shift_operator (x, mode)
2316 enum machine_mode mode;
2318 if (GET_MODE (x) != mode)
2322 enum rtx_code code = GET_CODE (x);
2325 return power_of_two_operand (XEXP (x, 1), mode);
2327 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2328 || code == ROTATERT);
2332 int equality_operator (x, mode)
2334 enum machine_mode mode ATTRIBUTE_UNUSED;
2336 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2339 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2342 minmax_operator (x, mode)
2344 enum machine_mode mode;
2346 enum rtx_code code = GET_CODE (x);
2348 if (GET_MODE (x) != mode)
2351 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2354 /* return TRUE if x is EQ or NE */
2356 /* Return TRUE if this is the condition code register, if we aren't given
2357 a mode, accept any class CCmode register */
2360 cc_register (x, mode)
2362 enum machine_mode mode;
2364 if (mode == VOIDmode)
2366 mode = GET_MODE (x);
2367 if (GET_MODE_CLASS (mode) != MODE_CC)
2371 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2377 /* Return TRUE if this is the condition code register, if we aren't given
2378 a mode, accept any class CCmode register which indicates a dominance
2382 dominant_cc_register (x, mode)
2384 enum machine_mode mode;
2386 if (mode == VOIDmode)
2388 mode = GET_MODE (x);
2389 if (GET_MODE_CLASS (mode) != MODE_CC)
2393 if (mode != CC_DNEmode && mode != CC_DEQmode
2394 && mode != CC_DLEmode && mode != CC_DLTmode
2395 && mode != CC_DGEmode && mode != CC_DGTmode
2396 && mode != CC_DLEUmode && mode != CC_DLTUmode
2397 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2400 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2406 /* Return TRUE if X references a SYMBOL_REF. */
2408 symbol_mentioned_p (x)
2414 if (GET_CODE (x) == SYMBOL_REF)
2417 fmt = GET_RTX_FORMAT (GET_CODE (x));
2418 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2424 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2425 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2428 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2435 /* Return TRUE if X references a LABEL_REF. */
2437 label_mentioned_p (x)
2443 if (GET_CODE (x) == LABEL_REF)
2446 fmt = GET_RTX_FORMAT (GET_CODE (x));
2447 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2453 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2454 if (label_mentioned_p (XVECEXP (x, i, j)))
2457 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2468 enum rtx_code code = GET_CODE (x);
2472 else if (code == SMIN)
2474 else if (code == UMIN)
2476 else if (code == UMAX)
2482 /* Return 1 if memory locations are adjacent */
2485 adjacent_mem_locations (a, b)
2488 int val0 = 0, val1 = 0;
2491 if ((GET_CODE (XEXP (a, 0)) == REG
2492 || (GET_CODE (XEXP (a, 0)) == PLUS
2493 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2494 && (GET_CODE (XEXP (b, 0)) == REG
2495 || (GET_CODE (XEXP (b, 0)) == PLUS
2496 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2498 if (GET_CODE (XEXP (a, 0)) == PLUS)
2500 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2501 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2504 reg0 = REGNO (XEXP (a, 0));
2505 if (GET_CODE (XEXP (b, 0)) == PLUS)
2507 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2508 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2511 reg1 = REGNO (XEXP (b, 0));
2512 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2517 /* Return 1 if OP is a load multiple operation. It is known to be
2518 parallel and the first section will be tested. */
2521 load_multiple_operation (op, mode)
2523 enum machine_mode mode ATTRIBUTE_UNUSED;
2525 HOST_WIDE_INT count = XVECLEN (op, 0);
2528 HOST_WIDE_INT i = 1, base = 0;
2532 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2535 /* Check to see if this might be a write-back */
2536 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2541 /* Now check it more carefully */
2542 if (GET_CODE (SET_DEST (elt)) != REG
2543 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2544 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2545 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2546 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2547 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2548 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2549 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2550 != REGNO (SET_DEST (elt)))
2556 /* Perform a quick check so we don't blow up below. */
2558 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2559 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2560 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2563 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2564 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2566 for (; i < count; i++)
2568 elt = XVECEXP (op, 0, i);
2570 if (GET_CODE (elt) != SET
2571 || GET_CODE (SET_DEST (elt)) != REG
2572 || GET_MODE (SET_DEST (elt)) != SImode
2573 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2574 || GET_CODE (SET_SRC (elt)) != MEM
2575 || GET_MODE (SET_SRC (elt)) != SImode
2576 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2577 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2578 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2579 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2586 /* Return 1 if OP is a store multiple operation. It is known to be
2587 parallel and the first section will be tested. */
2590 store_multiple_operation (op, mode)
2592 enum machine_mode mode ATTRIBUTE_UNUSED;
2594 HOST_WIDE_INT count = XVECLEN (op, 0);
2597 HOST_WIDE_INT i = 1, base = 0;
2601 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2604 /* Check to see if this might be a write-back */
2605 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2610 /* Now check it more carefully */
2611 if (GET_CODE (SET_DEST (elt)) != REG
2612 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2613 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2614 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2615 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2616 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2617 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2618 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2619 != REGNO (SET_DEST (elt)))
2625 /* Perform a quick check so we don't blow up below. */
2627 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2628 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2629 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2632 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2633 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2635 for (; i < count; i++)
2637 elt = XVECEXP (op, 0, i);
2639 if (GET_CODE (elt) != SET
2640 || GET_CODE (SET_SRC (elt)) != REG
2641 || GET_MODE (SET_SRC (elt)) != SImode
2642 || REGNO (SET_SRC (elt)) != src_regno + i - base
2643 || GET_CODE (SET_DEST (elt)) != MEM
2644 || GET_MODE (SET_DEST (elt)) != SImode
2645 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2646 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2647 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2648 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2656 load_multiple_sequence (operands, nops, regs, base, load_offset)
2661 HOST_WIDE_INT *load_offset;
2663 int unsorted_regs[4];
2664 HOST_WIDE_INT unsorted_offsets[4];
2669 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2670 extended if required. */
2671 if (nops < 2 || nops > 4)
2674 /* Loop over the operands and check that the memory references are
2675 suitable (ie immediate offsets from the same base register). At
2676 the same time, extract the target register, and the memory
2678 for (i = 0; i < nops; i++)
2683 /* Convert a subreg of a mem into the mem itself. */
2684 if (GET_CODE (operands[nops + i]) == SUBREG)
2685 operands[nops + i] = alter_subreg(operands[nops + i]);
2687 if (GET_CODE (operands[nops + i]) != MEM)
2690 /* Don't reorder volatile memory references; it doesn't seem worth
2691 looking for the case where the order is ok anyway. */
2692 if (MEM_VOLATILE_P (operands[nops + i]))
2695 offset = const0_rtx;
2697 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2698 || (GET_CODE (reg) == SUBREG
2699 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2700 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2701 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2703 || (GET_CODE (reg) == SUBREG
2704 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2705 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2710 base_reg = REGNO(reg);
2711 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2712 ? REGNO (operands[i])
2713 : REGNO (SUBREG_REG (operands[i])));
2718 if (base_reg != REGNO (reg))
2719 /* Not addressed from the same base register. */
2722 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2723 ? REGNO (operands[i])
2724 : REGNO (SUBREG_REG (operands[i])));
2725 if (unsorted_regs[i] < unsorted_regs[order[0]])
2729 /* If it isn't an integer register, or if it overwrites the
2730 base register but isn't the last insn in the list, then
2731 we can't do this. */
2732 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2733 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2736 unsorted_offsets[i] = INTVAL (offset);
2739 /* Not a suitable memory address. */
2743 /* All the useful information has now been extracted from the
2744 operands into unsorted_regs and unsorted_offsets; additionally,
2745 order[0] has been set to the lowest numbered register in the
2746 list. Sort the registers into order, and check that the memory
2747 offsets are ascending and adjacent. */
2749 for (i = 1; i < nops; i++)
2753 order[i] = order[i - 1];
2754 for (j = 0; j < nops; j++)
2755 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2756 && (order[i] == order[i - 1]
2757 || unsorted_regs[j] < unsorted_regs[order[i]]))
2760 /* Have we found a suitable register? if not, one must be used more
2762 if (order[i] == order[i - 1])
2765 /* Is the memory address adjacent and ascending? */
2766 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2774 for (i = 0; i < nops; i++)
2775 regs[i] = unsorted_regs[order[i]];
2777 *load_offset = unsorted_offsets[order[0]];
2780 if (unsorted_offsets[order[0]] == 0)
2781 return 1; /* ldmia */
2783 if (unsorted_offsets[order[0]] == 4)
2784 return 2; /* ldmib */
2786 if (unsorted_offsets[order[nops - 1]] == 0)
2787 return 3; /* ldmda */
2789 if (unsorted_offsets[order[nops - 1]] == -4)
2790 return 4; /* ldmdb */
2792 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if
2793 the offset isn't small enough. The reason 2 ldrs are faster is because
2794 these ARMs are able to do more than one cache access in a single cycle.
2795 The ARM9 and StrongARM have Harvard caches, whilst the ARM8 has a double
2796 bandwidth cache. This means that these cores can do both an instruction
2797 fetch and a data fetch in a single cycle, so the trick of calculating the
2798 address into a scratch register (one of the result regs) and then doing a
2799 load multiple actually becomes slower (and no smaller in code size). That
2800 is the transformation
2802 ldr rd1, [rbase + offset]
2803 ldr rd2, [rbase + offset + 4]
2807 add rd1, rbase, offset
2808 ldmia rd1, {rd1, rd2}
2810 produces worse code -- '3 cycles + any stalls on rd2' instead of '2 cycles
2811 + any stalls on rd2'. On ARMs with only one cache access per cycle, the
2812 first sequence could never complete in less than 6 cycles, whereas the ldm
2813 sequence would only take 5 and would make better use of sequential accesses
2814 if not hitting the cache.
2816 We cheat here and test 'arm_ld_sched' which we currently know to only be
2817 true for the ARM8, ARM9 and StrongARM. If this ever changes, then the test
2818 below needs to be reworked. */
2819 if (nops == 2 && arm_ld_sched)
2822 /* Can't do it without setting up the offset, only do this if it takes
2823 no more than one insn. */
2824 return (const_ok_for_arm (unsorted_offsets[order[0]])
2825 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2829 emit_ldm_seq (operands, nops)
2835 HOST_WIDE_INT offset;
2839 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2842 strcpy (buf, "ldm%?ia\t");
2846 strcpy (buf, "ldm%?ib\t");
2850 strcpy (buf, "ldm%?da\t");
2854 strcpy (buf, "ldm%?db\t");
2859 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2860 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2863 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2864 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2866 output_asm_insn (buf, operands);
2868 strcpy (buf, "ldm%?ia\t");
2875 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2876 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2878 for (i = 1; i < nops; i++)
2879 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2880 reg_names[regs[i]]);
2882 strcat (buf, "}\t%@ phole ldm");
2884 output_asm_insn (buf, operands);
2889 store_multiple_sequence (operands, nops, regs, base, load_offset)
2894 HOST_WIDE_INT *load_offset;
2896 int unsorted_regs[4];
2897 HOST_WIDE_INT unsorted_offsets[4];
2902 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2903 extended if required. */
2904 if (nops < 2 || nops > 4)
2907 /* Loop over the operands and check that the memory references are
2908 suitable (ie immediate offsets from the same base register). At
2909 the same time, extract the target register, and the memory
2911 for (i = 0; i < nops; i++)
2916 /* Convert a subreg of a mem into the mem itself. */
2917 if (GET_CODE (operands[nops + i]) == SUBREG)
2918 operands[nops + i] = alter_subreg(operands[nops + i]);
2920 if (GET_CODE (operands[nops + i]) != MEM)
2923 /* Don't reorder volatile memory references; it doesn't seem worth
2924 looking for the case where the order is ok anyway. */
2925 if (MEM_VOLATILE_P (operands[nops + i]))
2928 offset = const0_rtx;
2930 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2931 || (GET_CODE (reg) == SUBREG
2932 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2933 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2934 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2936 || (GET_CODE (reg) == SUBREG
2937 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2938 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2943 base_reg = REGNO(reg);
2944 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2945 ? REGNO (operands[i])
2946 : REGNO (SUBREG_REG (operands[i])));
2951 if (base_reg != REGNO (reg))
2952 /* Not addressed from the same base register. */
2955 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2956 ? REGNO (operands[i])
2957 : REGNO (SUBREG_REG (operands[i])));
2958 if (unsorted_regs[i] < unsorted_regs[order[0]])
2962 /* If it isn't an integer register, then we can't do this. */
2963 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2966 unsorted_offsets[i] = INTVAL (offset);
2969 /* Not a suitable memory address. */
2973 /* All the useful information has now been extracted from the
2974 operands into unsorted_regs and unsorted_offsets; additionally,
2975 order[0] has been set to the lowest numbered register in the
2976 list. Sort the registers into order, and check that the memory
2977 offsets are ascending and adjacent. */
2979 for (i = 1; i < nops; i++)
2983 order[i] = order[i - 1];
2984 for (j = 0; j < nops; j++)
2985 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2986 && (order[i] == order[i - 1]
2987 || unsorted_regs[j] < unsorted_regs[order[i]]))
2990 /* Have we found a suitable register? if not, one must be used more
2992 if (order[i] == order[i - 1])
2995 /* Is the memory address adjacent and ascending? */
2996 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3004 for (i = 0; i < nops; i++)
3005 regs[i] = unsorted_regs[order[i]];
3007 *load_offset = unsorted_offsets[order[0]];
3010 if (unsorted_offsets[order[0]] == 0)
3011 return 1; /* stmia */
3013 if (unsorted_offsets[order[0]] == 4)
3014 return 2; /* stmib */
3016 if (unsorted_offsets[order[nops - 1]] == 0)
3017 return 3; /* stmda */
3019 if (unsorted_offsets[order[nops - 1]] == -4)
3020 return 4; /* stmdb */
3026 emit_stm_seq (operands, nops)
3032 HOST_WIDE_INT offset;
3036 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3039 strcpy (buf, "stm%?ia\t");
3043 strcpy (buf, "stm%?ib\t");
3047 strcpy (buf, "stm%?da\t");
3051 strcpy (buf, "stm%?db\t");
3058 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3059 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3061 for (i = 1; i < nops; i++)
3062 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3063 reg_names[regs[i]]);
3065 strcat (buf, "}\t%@ phole stm");
3067 output_asm_insn (buf, operands);
3072 multi_register_push (op, mode)
3074 enum machine_mode mode ATTRIBUTE_UNUSED;
3076 if (GET_CODE (op) != PARALLEL
3077 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3078 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3079 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3086 /* Routines for use with attributes */
3088 /* Return nonzero if ATTR is a valid attribute for DECL.
3089 ATTRIBUTES are any existing attributes and ARGS are the arguments
3092 Supported attributes:
3094 naked: don't output any prologue or epilogue code, the user is assumed
3095 to do the right thing. */
3098 arm_valid_machine_decl_attribute (decl, attr, args)
3103 if (args != NULL_TREE)
3106 if (is_attribute_p ("naked", attr))
3107 return TREE_CODE (decl) == FUNCTION_DECL;
3111 /* Return non-zero if FUNC is a naked function. */
3114 arm_naked_function_p (func)
3119 if (TREE_CODE (func) != FUNCTION_DECL)
3122 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3123 return a != NULL_TREE;
3126 /* Routines for use in generating RTL */
3129 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3130 in_struct_p, scalar_p)
3142 int sign = up ? 1 : -1;
3145 result = gen_rtx_PARALLEL (VOIDmode,
3146 rtvec_alloc (count + (write_back ? 2 : 0)));
3149 XVECEXP (result, 0, 0)
3150 = gen_rtx_SET (GET_MODE (from), from,
3151 plus_constant (from, count * 4 * sign));
3156 for (j = 0; i < count; i++, j++)
3158 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3159 RTX_UNCHANGING_P (mem) = unchanging_p;
3160 MEM_IN_STRUCT_P (mem) = in_struct_p;
3161 MEM_SCALAR_P (mem) = scalar_p;
3162 XVECEXP (result, 0, i)
3163 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3167 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3173 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3174 in_struct_p, scalar_p)
3186 int sign = up ? 1 : -1;
3189 result = gen_rtx_PARALLEL (VOIDmode,
3190 rtvec_alloc (count + (write_back ? 2 : 0)));
3193 XVECEXP (result, 0, 0)
3194 = gen_rtx_SET (GET_MODE (to), to,
3195 plus_constant (to, count * 4 * sign));
3200 for (j = 0; i < count; i++, j++)
3202 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3203 RTX_UNCHANGING_P (mem) = unchanging_p;
3204 MEM_IN_STRUCT_P (mem) = in_struct_p;
3205 MEM_SCALAR_P (mem) = scalar_p;
3207 XVECEXP (result, 0, i)
3208 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3212 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3218 arm_gen_movstrqi (operands)
3221 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3224 rtx st_src, st_dst, fin_src, fin_dst;
3225 rtx part_bytes_reg = NULL;
3227 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3228 int dst_scalar_p, src_scalar_p;
3230 if (GET_CODE (operands[2]) != CONST_INT
3231 || GET_CODE (operands[3]) != CONST_INT
3232 || INTVAL (operands[2]) > 64
3233 || INTVAL (operands[3]) & 3)
3236 st_dst = XEXP (operands[0], 0);
3237 st_src = XEXP (operands[1], 0);
3239 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3240 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3241 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3242 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3243 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3244 src_scalar_p = MEM_SCALAR_P (operands[1]);
3246 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3247 fin_src = src = copy_to_mode_reg (SImode, st_src);
3249 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3250 out_words_to_go = INTVAL (operands[2]) / 4;
3251 last_bytes = INTVAL (operands[2]) & 3;
3253 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3254 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3256 for (i = 0; in_words_to_go >= 2; i+=4)
3258 if (in_words_to_go > 4)
3259 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3264 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3265 FALSE, src_unchanging_p,
3266 src_in_struct_p, src_scalar_p));
3268 if (out_words_to_go)
3270 if (out_words_to_go > 4)
3271 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3275 else if (out_words_to_go != 1)
3276 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3285 mem = gen_rtx_MEM (SImode, dst);
3286 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3287 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3288 MEM_SCALAR_P (mem) = dst_scalar_p;
3289 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3290 if (last_bytes != 0)
3291 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3295 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3296 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3299 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3300 if (out_words_to_go)
3304 mem = gen_rtx_MEM (SImode, src);
3305 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3306 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3307 MEM_SCALAR_P (mem) = src_scalar_p;
3308 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3309 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3311 mem = gen_rtx_MEM (SImode, dst);
3312 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3313 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3314 MEM_SCALAR_P (mem) = dst_scalar_p;
3315 emit_move_insn (mem, sreg);
3316 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3319 if (in_words_to_go) /* Sanity check */
3325 if (in_words_to_go < 0)
3328 mem = gen_rtx_MEM (SImode, src);
3329 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3330 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3331 MEM_SCALAR_P (mem) = src_scalar_p;
3332 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3335 if (BYTES_BIG_ENDIAN && last_bytes)
3337 rtx tmp = gen_reg_rtx (SImode);
3339 if (part_bytes_reg == NULL)
3342 /* The bytes we want are in the top end of the word */
3343 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3344 GEN_INT (8 * (4 - last_bytes))));
3345 part_bytes_reg = tmp;
3349 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3350 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3351 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3352 MEM_SCALAR_P (mem) = dst_scalar_p;
3353 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3356 tmp = gen_reg_rtx (SImode);
3357 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3358 part_bytes_reg = tmp;
3367 if (part_bytes_reg == NULL)
3370 mem = gen_rtx_MEM (QImode, dst);
3371 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3372 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3373 MEM_SCALAR_P (mem) = dst_scalar_p;
3374 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3377 rtx tmp = gen_reg_rtx (SImode);
3379 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3380 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3381 part_bytes_reg = tmp;
3389 /* Generate a memory reference for a half word, such that it will be loaded
3390 into the top 16 bits of the word. We can assume that the address is
3391 known to be alignable and of the form reg, or plus (reg, const). */
3393 gen_rotated_half_load (memref)
3396 HOST_WIDE_INT offset = 0;
3397 rtx base = XEXP (memref, 0);
3399 if (GET_CODE (base) == PLUS)
3401 offset = INTVAL (XEXP (base, 1));
3402 base = XEXP (base, 0);
3405 /* If we aren't allowed to generate unaligned addresses, then fail. */
3406 if (TARGET_SHORT_BY_BYTES
3407 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3410 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3412 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3415 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3418 static enum machine_mode
3419 select_dominance_cc_mode (x, y, cond_or)
3422 HOST_WIDE_INT cond_or;
3424 enum rtx_code cond1, cond2;
3427 /* Currently we will probably get the wrong result if the individual
3428 comparisons are not simple. This also ensures that it is safe to
3429 reverse a comparison if necessary. */
3430 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3432 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3437 cond1 = reverse_condition (cond1);
3439 /* If the comparisons are not equal, and one doesn't dominate the other,
3440 then we can't do this. */
3442 && ! comparison_dominates_p (cond1, cond2)
3443 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3448 enum rtx_code temp = cond1;
3456 if (cond2 == EQ || ! cond_or)
3461 case LE: return CC_DLEmode;
3462 case LEU: return CC_DLEUmode;
3463 case GE: return CC_DGEmode;
3464 case GEU: return CC_DGEUmode;
3471 if (cond2 == LT || ! cond_or)
3480 if (cond2 == GT || ! cond_or)
3489 if (cond2 == LTU || ! cond_or)
3498 if (cond2 == GTU || ! cond_or)
3506 /* The remaining cases only occur when both comparisons are the
3531 arm_select_cc_mode (op, x, y)
3536 /* All floating point compares return CCFP if it is an equality
3537 comparison, and CCFPE otherwise. */
3538 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3539 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3541 /* A compare with a shifted operand. Because of canonicalization, the
3542 comparison will have to be swapped when we emit the assembler. */
3543 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3544 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3545 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3546 || GET_CODE (x) == ROTATERT))
3549 /* This is a special case that is used by combine to allow a
3550 comparison of a shifted byte load to be split into a zero-extend
3551 followed by a comparison of the shifted integer (only valid for
3552 equalities and unsigned inequalities). */
3553 if (GET_MODE (x) == SImode
3554 && GET_CODE (x) == ASHIFT
3555 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3556 && GET_CODE (XEXP (x, 0)) == SUBREG
3557 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3558 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3559 && (op == EQ || op == NE
3560 || op == GEU || op == GTU || op == LTU || op == LEU)
3561 && GET_CODE (y) == CONST_INT)
3564 /* An operation that sets the condition codes as a side-effect, the
3565 V flag is not set correctly, so we can only use comparisons where
3566 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3568 if (GET_MODE (x) == SImode
3570 && (op == EQ || op == NE || op == LT || op == GE)
3571 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3572 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3573 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3574 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3575 || GET_CODE (x) == LSHIFTRT
3576 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3577 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3580 /* A construct for a conditional compare, if the false arm contains
3581 0, then both conditions must be true, otherwise either condition
3582 must be true. Not all conditions are possible, so CCmode is
3583 returned if it can't be done. */
3584 if (GET_CODE (x) == IF_THEN_ELSE
3585 && (XEXP (x, 2) == const0_rtx
3586 || XEXP (x, 2) == const1_rtx)
3587 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3588 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3589 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3590 INTVAL (XEXP (x, 2)));
3592 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3595 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3596 && GET_CODE (x) == PLUS
3597 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3603 /* X and Y are two things to compare using CODE. Emit the compare insn and
3604 return the rtx for register 0 in the proper mode. FP means this is a
3605 floating point compare: I don't think that it is needed on the arm. */
3608 gen_compare_reg (code, x, y)
3612 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3613 rtx cc_reg = gen_rtx_REG (mode, 24);
3615 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
3616 gen_rtx_COMPARE (mode, x, y)));
3622 arm_reload_in_hi (operands)
3625 rtx ref = operands[1];
3627 HOST_WIDE_INT offset = 0;
3629 if (GET_CODE (ref) == SUBREG)
3631 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3632 if (BYTES_BIG_ENDIAN)
3633 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3634 - MIN (UNITS_PER_WORD,
3635 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3636 ref = SUBREG_REG (ref);
3639 if (GET_CODE (ref) == REG)
3641 /* We have a pseudo which has been spilt onto the stack; there
3642 are two cases here: the first where there is a simple
3643 stack-slot replacement and a second where the stack-slot is
3644 out of range, or is used as a subreg. */
3645 if (reg_equiv_mem[REGNO (ref)])
3647 ref = reg_equiv_mem[REGNO (ref)];
3648 base = find_replacement (&XEXP (ref, 0));
3651 /* The slot is out of range, or was dressed up in a SUBREG */
3652 base = reg_equiv_address[REGNO (ref)];
3655 base = find_replacement (&XEXP (ref, 0));
3657 /* Handle the case where the address is too complex to be offset by 1. */
3658 if (GET_CODE (base) == MINUS
3659 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3661 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3663 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3666 else if (GET_CODE (base) == PLUS)
3668 /* The addend must be CONST_INT, or we would have dealt with it above */
3669 HOST_WIDE_INT hi, lo;
3671 offset += INTVAL (XEXP (base, 1));
3672 base = XEXP (base, 0);
3674 /* Rework the address into a legal sequence of insns */
3675 /* Valid range for lo is -4095 -> 4095 */
3678 : -((-offset) & 0xfff));
3680 /* Corner case, if lo is the max offset then we would be out of range
3681 once we have added the additional 1 below, so bump the msb into the
3682 pre-loading insn(s). */
3686 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3687 ^ (HOST_WIDE_INT) 0x80000000)
3688 - (HOST_WIDE_INT) 0x80000000);
3690 if (hi + lo != offset)
3695 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3697 /* Get the base address; addsi3 knows how to handle constants
3698 that require more than one insn */
3699 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3705 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3706 emit_insn (gen_zero_extendqisi2 (scratch,
3707 gen_rtx_MEM (QImode,
3708 plus_constant (base,
3710 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
3711 gen_rtx_MEM (QImode,
3712 plus_constant (base,
3714 if (BYTES_BIG_ENDIAN)
3715 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3716 gen_rtx_IOR (SImode,
3719 gen_rtx_SUBREG (SImode, operands[0], 0),
3723 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3724 gen_rtx_IOR (SImode,
3725 gen_rtx_ASHIFT (SImode, scratch,
3727 gen_rtx_SUBREG (SImode, operands[0],
3731 /* Handle storing a half-word to memory during reload by synthesising as two
3732 byte stores. Take care not to clobber the input values until after we
3733 have moved them somewhere safe. This code assumes that if the DImode
3734 scratch in operands[2] overlaps either the input value or output address
3735 in some way, then that value must die in this insn (we absolutely need
3736 two scratch registers for some corner cases). */
3738 arm_reload_out_hi (operands)
3741 rtx ref = operands[0];
3742 rtx outval = operands[1];
3744 HOST_WIDE_INT offset = 0;
3746 if (GET_CODE (ref) == SUBREG)
3748 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3749 if (BYTES_BIG_ENDIAN)
3750 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3751 - MIN (UNITS_PER_WORD,
3752 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3753 ref = SUBREG_REG (ref);
3757 if (GET_CODE (ref) == REG)
3759 /* We have a pseudo which has been spilt onto the stack; there
3760 are two cases here: the first where there is a simple
3761 stack-slot replacement and a second where the stack-slot is
3762 out of range, or is used as a subreg. */
3763 if (reg_equiv_mem[REGNO (ref)])
3765 ref = reg_equiv_mem[REGNO (ref)];
3766 base = find_replacement (&XEXP (ref, 0));
3769 /* The slot is out of range, or was dressed up in a SUBREG */
3770 base = reg_equiv_address[REGNO (ref)];
3773 base = find_replacement (&XEXP (ref, 0));
3775 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3777 /* Handle the case where the address is too complex to be offset by 1. */
3778 if (GET_CODE (base) == MINUS
3779 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3781 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3783 /* Be careful not to destroy OUTVAL. */
3784 if (reg_overlap_mentioned_p (base_plus, outval))
3786 /* Updating base_plus might destroy outval, see if we can
3787 swap the scratch and base_plus. */
3788 if (! reg_overlap_mentioned_p (scratch, outval))
3791 scratch = base_plus;
3796 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3798 /* Be conservative and copy OUTVAL into the scratch now,
3799 this should only be necessary if outval is a subreg
3800 of something larger than a word. */
3801 /* XXX Might this clobber base? I can't see how it can,
3802 since scratch is known to overlap with OUTVAL, and
3803 must be wider than a word. */
3804 emit_insn (gen_movhi (scratch_hi, outval));
3805 outval = scratch_hi;
3809 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3812 else if (GET_CODE (base) == PLUS)
3814 /* The addend must be CONST_INT, or we would have dealt with it above */
3815 HOST_WIDE_INT hi, lo;
3817 offset += INTVAL (XEXP (base, 1));
3818 base = XEXP (base, 0);
3820 /* Rework the address into a legal sequence of insns */
3821 /* Valid range for lo is -4095 -> 4095 */
3824 : -((-offset) & 0xfff));
3826 /* Corner case, if lo is the max offset then we would be out of range
3827 once we have added the additional 1 below, so bump the msb into the
3828 pre-loading insn(s). */
3832 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3833 ^ (HOST_WIDE_INT) 0x80000000)
3834 - (HOST_WIDE_INT) 0x80000000);
3836 if (hi + lo != offset)
3841 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3843 /* Be careful not to destroy OUTVAL. */
3844 if (reg_overlap_mentioned_p (base_plus, outval))
3846 /* Updating base_plus might destroy outval, see if we
3847 can swap the scratch and base_plus. */
3848 if (! reg_overlap_mentioned_p (scratch, outval))
3851 scratch = base_plus;
3856 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3858 /* Be conservative and copy outval into scratch now,
3859 this should only be necessary if outval is a
3860 subreg of something larger than a word. */
3861 /* XXX Might this clobber base? I can't see how it
3862 can, since scratch is known to overlap with
3864 emit_insn (gen_movhi (scratch_hi, outval));
3865 outval = scratch_hi;
3869 /* Get the base address; addsi3 knows how to handle constants
3870 that require more than one insn */
3871 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3877 if (BYTES_BIG_ENDIAN)
3879 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3880 plus_constant (base, offset + 1)),
3881 gen_rtx_SUBREG (QImode, outval, 0)));
3882 emit_insn (gen_lshrsi3 (scratch,
3883 gen_rtx_SUBREG (SImode, outval, 0),
3885 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3886 gen_rtx_SUBREG (QImode, scratch, 0)));
3890 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3891 gen_rtx_SUBREG (QImode, outval, 0)));
3892 emit_insn (gen_lshrsi3 (scratch,
3893 gen_rtx_SUBREG (SImode, outval, 0),
3895 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3896 plus_constant (base, offset + 1)),
3897 gen_rtx_SUBREG (QImode, scratch, 0)));
3901 /* Routines for manipulation of the constant pool. */
3902 /* This is unashamedly hacked from the version in sh.c, since the problem is
3903 extremely similar. */
3905 /* Arm instructions cannot load a large constant into a register,
3906 constants have to come from a pc relative load. The reference of a pc
3907 relative load instruction must be less than 1k infront of the instruction.
3908 This means that we often have to dump a constant inside a function, and
3909 generate code to branch around it.
3911 It is important to minimize this, since the branches will slow things
3912 down and make things bigger.
3914 Worst case code looks like:
3930 We fix this by performing a scan before scheduling, which notices which
3931 instructions need to have their operands fetched from the constant table
3932 and builds the table.
3937 scan, find an instruction which needs a pcrel move. Look forward, find th
3938 last barrier which is within MAX_COUNT bytes of the requirement.
3939 If there isn't one, make one. Process all the instructions between
3940 the find and the barrier.
3942 In the above example, we can tell that L3 is within 1k of L1, so
3943 the first move can be shrunk from the 2 insn+constant sequence into
3944 just 1 insn, and the constant moved to L3 to make:
3955 Then the second move becomes the target for the shortening process.
3961 rtx value; /* Value in table */
3962 HOST_WIDE_INT next_offset;
3963 enum machine_mode mode; /* Mode of value */
3966 /* The maximum number of constants that can fit into one pool, since
3967 the pc relative range is 0...1020 bytes and constants are at least 4
3970 #define MAX_POOL_SIZE (1020/4)
3971 static pool_node pool_vector[MAX_POOL_SIZE];
3972 static int pool_size;
3973 static rtx pool_vector_label;
3975 /* Add a constant to the pool and return its offset within the current
3978 X is the rtx we want to replace. MODE is its mode. On return,
3979 ADDRESS_ONLY will be non-zero if we really want the address of such
3980 a constant, not the constant itself. */
3981 static HOST_WIDE_INT
3982 add_constant (x, mode, address_only)
3984 enum machine_mode mode;
3988 HOST_WIDE_INT offset;
3992 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3993 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3994 x = get_pool_constant (XEXP (x, 0));
3995 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3998 mode = get_pool_mode (x);
3999 x = get_pool_constant (x);
4001 #ifndef AOF_ASSEMBLER
4002 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
4003 x = XVECEXP (x, 0, 0);
4006 #ifdef AOF_ASSEMBLER
4007 /* PIC Symbol references need to be converted into offsets into the
4009 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
4010 x = aof_pic_entry (x);
4011 #endif /* AOF_ASSEMBLER */
4013 /* First see if we've already got it */
4014 for (i = 0; i < pool_size; i++)
4016 if (GET_CODE (x) == pool_vector[i].value->code
4017 && mode == pool_vector[i].mode)
4019 if (GET_CODE (x) == CODE_LABEL)
4021 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4024 if (rtx_equal_p (x, pool_vector[i].value))
4025 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
4029 /* Need a new one */
4030 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
4033 pool_vector_label = gen_label_rtx ();
4035 pool_vector[pool_size].next_offset
4036 += (offset = pool_vector[pool_size - 1].next_offset);
4038 pool_vector[pool_size].value = x;
4039 pool_vector[pool_size].mode = mode;
4044 /* Output the literal table */
4051 scan = emit_label_after (gen_label_rtx (), scan);
4052 scan = emit_insn_after (gen_align_4 (), scan);
4053 scan = emit_label_after (pool_vector_label, scan);
4055 for (i = 0; i < pool_size; i++)
4057 pool_node *p = pool_vector + i;
4059 switch (GET_MODE_SIZE (p->mode))
4062 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4066 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4075 scan = emit_insn_after (gen_consttable_end (), scan);
4076 scan = emit_barrier_after (scan);
4080 /* Non zero if the src operand needs to be fixed up */
4082 fixit (src, mode, destreg)
4084 enum machine_mode mode;
4087 if (CONSTANT_P (src))
4089 if (GET_CODE (src) == CONST_INT)
4090 return (! const_ok_for_arm (INTVAL (src))
4091 && ! const_ok_for_arm (~INTVAL (src)));
4092 if (GET_CODE (src) == CONST_DOUBLE)
4093 return (GET_MODE (src) == VOIDmode
4095 || (! const_double_rtx_ok_for_fpu (src)
4096 && ! neg_const_double_rtx_ok_for_fpu (src)));
4097 return symbol_mentioned_p (src);
4099 #ifndef AOF_ASSEMBLER
4100 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
4104 return (mode == SImode && GET_CODE (src) == MEM
4105 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
4106 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
4109 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
4111 find_barrier (from, max_count)
4116 rtx found_barrier = 0;
4119 while (from && count < max_count)
4123 if (GET_CODE (from) == BARRIER)
4124 found_barrier = from;
4126 /* Count the length of this insn */
4127 if (GET_CODE (from) == INSN
4128 && GET_CODE (PATTERN (from)) == SET
4129 && CONSTANT_P (SET_SRC (PATTERN (from)))
4130 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
4132 /* Handle table jumps as a single entity. */
4133 else if (GET_CODE (from) == JUMP_INSN
4134 && JUMP_LABEL (from) != 0
4135 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4136 == next_real_insn (from))
4138 && GET_CODE (tmp) == JUMP_INSN
4139 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4140 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4142 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4143 count += (get_attr_length (from)
4144 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4145 /* Continue after the dispatch table. */
4147 from = NEXT_INSN (tmp);
4151 count += get_attr_length (from);
4154 from = NEXT_INSN (from);
4157 if (! found_barrier)
4159 /* We didn't find a barrier in time to
4160 dump our stuff, so we'll make one. */
4161 rtx label = gen_label_rtx ();
4164 from = PREV_INSN (last);
4166 from = get_last_insn ();
4168 /* Walk back to be just before any jump. */
4169 while (GET_CODE (from) == JUMP_INSN
4170 || GET_CODE (from) == NOTE
4171 || GET_CODE (from) == CODE_LABEL)
4172 from = PREV_INSN (from);
4174 from = emit_jump_insn_after (gen_jump (label), from);
4175 JUMP_LABEL (from) = label;
4176 found_barrier = emit_barrier_after (from);
4177 emit_label_after (label, found_barrier);
4180 return found_barrier;
4183 /* Non zero if the insn is a move instruction which needs to be fixed. */
4188 if (!INSN_DELETED_P (insn)
4189 && GET_CODE (insn) == INSN
4190 && GET_CODE (PATTERN (insn)) == SET)
4192 rtx pat = PATTERN (insn);
4193 rtx src = SET_SRC (pat);
4194 rtx dst = SET_DEST (pat);
4196 enum machine_mode mode = GET_MODE (dst);
4201 if (GET_CODE (dst) == REG)
4202 destreg = REGNO (dst);
4203 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
4204 destreg = REGNO (SUBREG_REG (dst));
4208 return fixit (src, mode, destreg);
4221 /* The ldr instruction can work with up to a 4k offset, and most constants
4222 will be loaded with one of these instructions; however, the adr
4223 instruction and the ldf instructions only work with a 1k offset. This
4224 code needs to be rewritten to use the 4k offset when possible, and to
4225 adjust when a 1k offset is needed. For now we just use a 1k offset
4229 /* Floating point operands can't work further than 1024 bytes from the
4230 PC, so to make things simple we restrict all loads for such functions.
4232 if (TARGET_HARD_FLOAT)
4236 for (regno = 16; regno < 24; regno++)
4237 if (regs_ever_live[regno])
4247 for (insn = first; insn; insn = NEXT_INSN (insn))
4249 if (broken_move (insn))
4251 /* This is a broken move instruction, scan ahead looking for
4252 a barrier to stick the constant table behind */
4254 rtx barrier = find_barrier (insn, count_size);
4256 /* Now find all the moves between the points and modify them */
4257 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
4259 if (broken_move (scan))
4261 /* This is a broken move instruction, add it to the pool */
4262 rtx pat = PATTERN (scan);
4263 rtx src = SET_SRC (pat);
4264 rtx dst = SET_DEST (pat);
4265 enum machine_mode mode = GET_MODE (dst);
4266 HOST_WIDE_INT offset;
4273 /* If this is an HImode constant load, convert it into
4274 an SImode constant load. Since the register is always
4275 32 bits this is safe. We have to do this, since the
4276 load pc-relative instruction only does a 32-bit load. */
4280 if (GET_CODE (dst) != REG)
4282 PUT_MODE (dst, SImode);
4285 offset = add_constant (src, mode, &address_only);
4286 addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4290 /* If we only want the address of the pool entry, or
4291 for wide moves to integer regs we need to split
4292 the address calculation off into a separate insn.
4293 If necessary, the load can then be done with a
4294 load-multiple. This is safe, since we have
4295 already noted the length of such insns to be 8,
4296 and we are immediately over-writing the scratch
4297 we have grabbed with the final result. */
4298 if ((address_only || GET_MODE_SIZE (mode) > 4)
4299 && (scratch = REGNO (dst)) < 16)
4306 reg = gen_rtx_REG (SImode, scratch);
4308 newinsn = emit_insn_after (gen_movaddr (reg, addr),
4315 newsrc = gen_rtx_MEM (mode, addr);
4317 /* XXX Fixme -- I think the following is bogus. */
4318 /* Build a jump insn wrapper around the move instead
4319 of an ordinary insn, because we want to have room for
4320 the target label rtx in fld[7], which an ordinary
4321 insn doesn't have. */
4323 = emit_jump_insn_after (gen_rtx_SET (VOIDmode, dst,
4326 JUMP_LABEL (newinsn) = pool_vector_label;
4328 /* But it's still an ordinary insn */
4329 PUT_CODE (newinsn, INSN);
4337 dump_table (barrier);
4342 after_arm_reorg = 1;
4346 /* Routines to output assembly language. */
4348 /* If the rtx is the correct value then return the string of the number.
4349 In this way we can ensure that valid double constants are generated even
4350 when cross compiling. */
4352 fp_immediate_constant (x)
4358 if (!fpa_consts_inited)
4361 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4362 for (i = 0; i < 8; i++)
4363 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4364 return strings_fpa[i];
4369 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4371 fp_const_from_val (r)
4376 if (! fpa_consts_inited)
4379 for (i = 0; i < 8; i++)
4380 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4381 return strings_fpa[i];
4386 /* Output the operands of a LDM/STM instruction to STREAM.
4387 MASK is the ARM register set mask of which only bits 0-15 are important.
4388 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4389 must follow the register list. */
4392 print_multi_reg (stream, instr, mask, hat)
4398 int not_first = FALSE;
4400 fputc ('\t', stream);
4401 fprintf (stream, instr, REGISTER_PREFIX);
4402 fputs (", {", stream);
4403 for (i = 0; i < 16; i++)
4404 if (mask & (1 << i))
4407 fprintf (stream, ", ");
4408 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
4412 fprintf (stream, "}%s\n", hat ? "^" : "");
4415 /* Output a 'call' insn. */
4418 output_call (operands)
4421 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4423 if (REGNO (operands[0]) == 14)
4425 operands[0] = gen_rtx_REG (SImode, 12);
4426 output_asm_insn ("mov%?\t%0, %|lr", operands);
4428 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4430 if (TARGET_THUMB_INTERWORK)
4431 output_asm_insn ("bx%?\t%0", operands);
4433 output_asm_insn ("mov%?\t%|pc, %0", operands);
4442 int something_changed = 0;
4444 int code = GET_CODE (x0);
4451 if (REGNO (x0) == 14)
4453 *x = gen_rtx_REG (SImode, 12);
4458 /* Scan through the sub-elements and change any references there */
4459 fmt = GET_RTX_FORMAT (code);
4460 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4462 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4463 else if (fmt[i] == 'E')
4464 for (j = 0; j < XVECLEN (x0, i); j++)
4465 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4466 return something_changed;
4470 /* Output a 'call' insn that is a reference in memory. */
4473 output_call_mem (operands)
4476 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4477 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4479 if (eliminate_lr2ip (&operands[0]))
4480 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4482 if (TARGET_THUMB_INTERWORK)
4484 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4485 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4486 output_asm_insn ("bx%?\t%|ip", operands);
4490 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4491 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4498 /* Output a move from arm registers to an fpu registers.
4499 OPERANDS[0] is an fpu register.
4500 OPERANDS[1] is the first registers of an arm register pair. */
4503 output_mov_long_double_fpu_from_arm (operands)
4506 int arm_reg0 = REGNO (operands[1]);
4512 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4513 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4514 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4516 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4517 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4521 /* Output a move from an fpu register to arm registers.
4522 OPERANDS[0] is the first registers of an arm register pair.
4523 OPERANDS[1] is an fpu register. */
4526 output_mov_long_double_arm_from_fpu (operands)
4529 int arm_reg0 = REGNO (operands[0]);
4535 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4536 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4537 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4539 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4540 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4544 /* Output a move from arm registers to arm registers of a long double
4545 OPERANDS[0] is the destination.
4546 OPERANDS[1] is the source. */
4548 output_mov_long_double_arm_from_arm (operands)
4551 /* We have to be careful here because the two might overlap */
4552 int dest_start = REGNO (operands[0]);
4553 int src_start = REGNO (operands[1]);
4557 if (dest_start < src_start)
4559 for (i = 0; i < 3; i++)
4561 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4562 ops[1] = gen_rtx_REG (SImode, src_start + i);
4563 output_asm_insn ("mov%?\t%0, %1", ops);
4568 for (i = 2; i >= 0; i--)
4570 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4571 ops[1] = gen_rtx_REG (SImode, src_start + i);
4572 output_asm_insn ("mov%?\t%0, %1", ops);
4580 /* Output a move from arm registers to an fpu registers.
4581 OPERANDS[0] is an fpu register.
4582 OPERANDS[1] is the first registers of an arm register pair. */
4585 output_mov_double_fpu_from_arm (operands)
4588 int arm_reg0 = REGNO (operands[1]);
4593 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4594 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4595 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4596 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4600 /* Output a move from an fpu register to arm registers.
4601 OPERANDS[0] is the first registers of an arm register pair.
4602 OPERANDS[1] is an fpu register. */
4605 output_mov_double_arm_from_fpu (operands)
4608 int arm_reg0 = REGNO (operands[0]);
4614 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4615 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4616 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4617 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4621 /* Output a move between double words.
4622 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4623 or MEM<-REG and all MEMs must be offsettable addresses. */
4626 output_move_double (operands)
4629 enum rtx_code code0 = GET_CODE (operands[0]);
4630 enum rtx_code code1 = GET_CODE (operands[1]);
4635 int reg0 = REGNO (operands[0]);
4637 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
4641 int reg1 = REGNO (operands[1]);
4645 /* Ensure the second source is not overwritten */
4646 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4647 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4649 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4651 else if (code1 == CONST_DOUBLE)
4653 if (GET_MODE (operands[1]) == DFmode)
4656 union real_extract u;
4658 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4660 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4661 otherops[1] = GEN_INT(l[1]);
4662 operands[1] = GEN_INT(l[0]);
4664 else if (GET_MODE (operands[1]) != VOIDmode)
4666 else if (WORDS_BIG_ENDIAN)
4669 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4670 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4675 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4676 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4678 output_mov_immediate (operands);
4679 output_mov_immediate (otherops);
4681 else if (code1 == CONST_INT)
4683 #if HOST_BITS_PER_WIDE_INT > 32
4684 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4685 what the upper word is. */
4686 if (WORDS_BIG_ENDIAN)
4688 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4689 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4693 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4694 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4697 /* Sign extend the intval into the high-order word */
4698 if (WORDS_BIG_ENDIAN)
4700 otherops[1] = operands[1];
4701 operands[1] = (INTVAL (operands[1]) < 0
4702 ? constm1_rtx : const0_rtx);
4705 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4707 output_mov_immediate (otherops);
4708 output_mov_immediate (operands);
4710 else if (code1 == MEM)
4712 switch (GET_CODE (XEXP (operands[1], 0)))
4715 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4719 abort (); /* Should never happen now */
4723 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4727 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4731 abort (); /* Should never happen now */
4736 output_asm_insn ("adr%?\t%0, %1", operands);
4737 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4741 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
4742 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
4744 otherops[0] = operands[0];
4745 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4746 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4747 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4749 if (GET_CODE (otherops[2]) == CONST_INT)
4751 switch (INTVAL (otherops[2]))
4754 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4757 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4760 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4763 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4764 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4766 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4769 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4772 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4773 return "ldm%?ia\t%0, %M0";
4777 otherops[1] = adj_offsettable_operand (operands[1], 4);
4778 /* Take care of overlapping base/data reg. */
4779 if (reg_mentioned_p (operands[0], operands[1]))
4781 output_asm_insn ("ldr%?\t%0, %1", otherops);
4782 output_asm_insn ("ldr%?\t%0, %1", operands);
4786 output_asm_insn ("ldr%?\t%0, %1", operands);
4787 output_asm_insn ("ldr%?\t%0, %1", otherops);
4793 abort(); /* Constraints should prevent this */
4795 else if (code0 == MEM && code1 == REG)
4797 if (REGNO (operands[1]) == 12)
4800 switch (GET_CODE (XEXP (operands[0], 0)))
4803 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4807 abort (); /* Should never happen now */
4811 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4815 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4819 abort (); /* Should never happen now */
4823 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4825 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4828 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4832 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4836 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4843 otherops[0] = adj_offsettable_operand (operands[0], 4);
4844 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
4845 output_asm_insn ("str%?\t%1, %0", operands);
4846 output_asm_insn ("str%?\t%1, %0", otherops);
4850 abort(); /* Constraints should prevent this */
4856 /* Output an arbitrary MOV reg, #n.
4857 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4860 output_mov_immediate (operands)
4863 HOST_WIDE_INT n = INTVAL (operands[1]);
4867 /* Try to use one MOV */
4868 if (const_ok_for_arm (n))
4870 output_asm_insn ("mov%?\t%0, %1", operands);
4874 /* Try to use one MVN */
4875 if (const_ok_for_arm (~n))
4877 operands[1] = GEN_INT (~n);
4878 output_asm_insn ("mvn%?\t%0, %1", operands);
4882 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4884 for (i=0; i < 32; i++)
4888 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4889 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4892 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4899 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4900 adding zero to one register, output nothing. */
4903 output_add_immediate (operands)
4906 HOST_WIDE_INT n = INTVAL (operands[2]);
4908 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4911 output_multi_immediate (operands,
4912 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4915 output_multi_immediate (operands,
4916 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4923 /* Output a multiple immediate operation.
4924 OPERANDS is the vector of operands referred to in the output patterns.
4925 INSTR1 is the output pattern to use for the first constant.
4926 INSTR2 is the output pattern to use for subsequent constants.
4927 IMMED_OP is the index of the constant slot in OPERANDS.
4928 N is the constant value. */
4931 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4933 char *instr1, *instr2;
4937 #if HOST_BITS_PER_WIDE_INT > 32
4943 operands[immed_op] = const0_rtx;
4944 output_asm_insn (instr1, operands); /* Quick and easy output */
4949 char *instr = instr1;
4951 /* Note that n is never zero here (which would give no output) */
4952 for (i = 0; i < 32; i += 2)
4956 operands[immed_op] = GEN_INT (n & (255 << i));
4957 output_asm_insn (instr, operands);
4967 /* Return the appropriate ARM instruction for the operation code.
4968 The returned result should not be overwritten. OP is the rtx of the
4969 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4973 arithmetic_instr (op, shift_first_arg)
4975 int shift_first_arg;
4977 switch (GET_CODE (op))
4983 return shift_first_arg ? "rsb" : "sub";
5000 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5001 for the operation code. The returned result should not be overwritten.
5002 OP is the rtx code of the shift.
5003 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5007 shift_op (op, amountp)
5009 HOST_WIDE_INT *amountp;
5012 enum rtx_code code = GET_CODE (op);
5014 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5016 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5017 *amountp = INTVAL (XEXP (op, 1));
5040 /* We never have to worry about the amount being other than a
5041 power of 2, since this case can never be reloaded from a reg. */
5043 *amountp = int_log2 (*amountp);
5054 /* This is not 100% correct, but follows from the desire to merge
5055 multiplication by a power of 2 with the recognizer for a
5056 shift. >=32 is not a valid shift for "asl", so we must try and
5057 output a shift that produces the correct arithmetical result.
5058 Using lsr #32 is identical except for the fact that the carry bit
5059 is not set correctly if we set the flags; but we never use the
5060 carry bit from such an operation, so we can ignore that. */
5061 if (code == ROTATERT)
5062 *amountp &= 31; /* Rotate is just modulo 32 */
5063 else if (*amountp != (*amountp & 31))
5070 /* Shifts of 0 are no-ops. */
5079 /* Obtain the shift from the POWER of two. */
5081 static HOST_WIDE_INT
5083 HOST_WIDE_INT power;
5085 HOST_WIDE_INT shift = 0;
5087 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5097 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5098 /bin/as is horribly restrictive. */
5101 output_ascii_pseudo_op (stream, p, len)
5107 int len_so_far = 1000;
5108 int chars_so_far = 0;
5110 for (i = 0; i < len; i++)
5112 register int c = p[i];
5114 if (len_so_far > 50)
5117 fputs ("\"\n", stream);
5118 fputs ("\t.ascii\t\"", stream);
5123 if (c == '\"' || c == '\\')
5129 if (c >= ' ' && c < 0177)
5136 fprintf (stream, "\\%03o", c);
5143 fputs ("\"\n", stream);
5147 /* Try to determine whether a pattern really clobbers the link register.
5148 This information is useful when peepholing, so that lr need not be pushed
5149 if we combine a call followed by a return.
5150 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5151 such a check should not be needed because these only update an existing
5152 value within a register; the register must still be set elsewhere within
5156 pattern_really_clobbers_lr (x)
5161 switch (GET_CODE (x))
5164 switch (GET_CODE (SET_DEST (x)))
5167 return REGNO (SET_DEST (x)) == 14;
5170 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5171 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
5173 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5182 for (i = 0; i < XVECLEN (x, 0); i++)
5183 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5188 switch (GET_CODE (XEXP (x, 0)))
5191 return REGNO (XEXP (x, 0)) == 14;
5194 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5195 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
5211 function_really_clobbers_lr (first)
5216 for (insn = first; insn; insn = next_nonnote_insn (insn))
5218 switch (GET_CODE (insn))
5223 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5228 if (pattern_really_clobbers_lr (PATTERN (insn)))
5233 /* Don't yet know how to handle those calls that are not to a
5235 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5238 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5241 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5247 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5253 default: /* Don't recognize it, be safe */
5257 /* A call can be made (by peepholing) not to clobber lr iff it is
5258 followed by a return. There may, however, be a use insn iff
5259 we are returning the result of the call.
5260 If we run off the end of the insn chain, then that means the
5261 call was at the end of the function. Unfortunately we don't
5262 have a return insn for the peephole to recognize, so we
5263 must reject this. (Can this be fixed by adding our own insn?) */
5264 if ((next = next_nonnote_insn (insn)) == NULL)
5267 /* No need to worry about lr if the call never returns */
5268 if (GET_CODE (next) == BARRIER)
5271 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5272 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5273 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5274 == REGNO (XEXP (PATTERN (next), 0))))
5275 if ((next = next_nonnote_insn (next)) == NULL)
5278 if (GET_CODE (next) == JUMP_INSN
5279 && GET_CODE (PATTERN (next)) == RETURN)
5288 /* We have reached the end of the chain so lr was _not_ clobbered */
5293 output_return_instruction (operand, really_return, reverse)
5299 int reg, live_regs = 0;
5300 int volatile_func = (optimize > 0
5301 && TREE_THIS_VOLATILE (current_function_decl));
5303 return_used_this_function = 1;
5308 /* If this function was declared non-returning, and we have found a tail
5309 call, then we have to trust that the called function won't return. */
5310 if (! really_return)
5313 /* Otherwise, trap an attempted return by aborting. */
5315 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)"
5317 assemble_external_libcall (ops[1]);
5318 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5322 if (current_function_calls_alloca && ! really_return)
5325 for (reg = 0; reg <= 10; reg++)
5326 if (regs_ever_live[reg] && ! call_used_regs[reg])
5329 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5332 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
5335 if (frame_pointer_needed)
5340 if (lr_save_eliminated || ! regs_ever_live[14])
5343 if (frame_pointer_needed)
5345 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5348 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5350 for (reg = 0; reg <= 10; reg++)
5351 if (regs_ever_live[reg]
5352 && (! call_used_regs[reg]
5353 || (flag_pic && reg == PIC_OFFSET_TABLE_REGNUM)))
5355 strcat (instr, "%|");
5356 strcat (instr, reg_names[reg]);
5358 strcat (instr, ", ");
5361 if (frame_pointer_needed)
5363 strcat (instr, "%|");
5364 strcat (instr, reg_names[11]);
5365 strcat (instr, ", ");
5366 strcat (instr, "%|");
5367 strcat (instr, reg_names[13]);
5368 strcat (instr, ", ");
5369 strcat (instr, "%|");
5370 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
5371 ? reg_names[14] : reg_names[15] );
5375 strcat (instr, "%|");
5376 if (TARGET_THUMB_INTERWORK && really_return)
5377 strcat (instr, reg_names[12]);
5379 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
5381 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5382 output_asm_insn (instr, &operand);
5384 if (TARGET_THUMB_INTERWORK && really_return)
5386 strcpy (instr, "bx%?");
5387 strcat (instr, reverse ? "%D0" : "%d0");
5388 strcat (instr, "\t%|");
5389 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5391 output_asm_insn (instr, & operand);
5394 else if (really_return)
5396 if (TARGET_THUMB_INTERWORK)
5397 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5399 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5400 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5402 output_asm_insn (instr, & operand);
5408 /* Return nonzero if optimizing and the current function is volatile.
5409 Such functions never return, and many memory cycles can be saved
5410 by not storing register values that will never be needed again.
5411 This optimization was added to speed up context switching in a
5412 kernel application. */
5415 arm_volatile_func ()
5417 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5420 /* Write the function name into the code section, directly preceding
5421 the function prologue.
5423 Code will be output similar to this:
5425 .ascii "arm_poke_function_name", 0
5428 .word 0xff000000 + (t1 - t0)
5429 arm_poke_function_name
5431 stmfd sp!, {fp, ip, lr, pc}
5434 When performing a stack backtrace, code can inspect the value
5435 of 'pc' stored at 'fp' + 0. If the trace function then looks
5436 at location pc - 12 and the top 8 bits are set, then we know
5437 that there is a function name embedded immediately preceding this
5438 location and has length ((pc[-3]) & 0xff000000).
5440 We assume that pc is declared as a pointer to an unsigned long.
5442 It is of no benefit to output the function name if we are assembling
5443 a leaf function. These function types will not contain a stack
5444 backtrace structure, therefore it is not possible to determine the
5448 arm_poke_function_name (stream, name)
5452 unsigned long alignlength;
5453 unsigned long length;
5456 length = strlen (name);
5457 alignlength = (length + 1) + 3 & ~3;
5459 ASM_OUTPUT_ASCII (stream, name, length + 1);
5460 ASM_OUTPUT_ALIGN (stream, 2);
5461 x = GEN_INT (0xff000000UL + alignlength);
5462 ASM_OUTPUT_INT (stream, x);
5465 /* The amount of stack adjustment that happens here, in output_return and in
5466 output_epilogue must be exactly the same as was calculated during reload,
5467 or things will point to the wrong place. The only time we can safely
5468 ignore this constraint is when a function has no arguments on the stack,
5469 no stack frame requirement and no live registers execpt for `lr'. If we
5470 can guarantee that by making all function calls into tail calls and that
5471 lr is not clobbered in any other way, then there is no need to push lr
5475 output_func_prologue (f, frame_size)
5479 int reg, live_regs_mask = 0;
5480 int volatile_func = (optimize > 0
5481 && TREE_THIS_VOLATILE (current_function_decl));
5483 /* Nonzero if we must stuff some register arguments onto the stack as if
5484 they were passed there. */
5485 int store_arg_regs = 0;
5487 if (arm_ccfsm_state || arm_target_insn)
5488 abort (); /* Sanity check */
5490 if (arm_naked_function_p (current_function_decl))
5493 return_used_this_function = 0;
5494 lr_save_eliminated = 0;
5496 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
5497 ASM_COMMENT_START, current_function_args_size,
5498 current_function_pretend_args_size, frame_size);
5499 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
5500 ASM_COMMENT_START, frame_pointer_needed,
5501 current_function_anonymous_args);
5504 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
5506 if (current_function_anonymous_args && current_function_pretend_args_size)
5509 for (reg = 0; reg <= 10; reg++)
5510 if (regs_ever_live[reg] && ! call_used_regs[reg])
5511 live_regs_mask |= (1 << reg);
5513 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5514 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5516 if (frame_pointer_needed)
5517 live_regs_mask |= 0xD800;
5518 else if (regs_ever_live[14])
5520 if (! current_function_args_size
5521 && ! function_really_clobbers_lr (get_insns ()))
5522 lr_save_eliminated = 1;
5524 live_regs_mask |= 0x4000;
5529 /* if a di mode load/store multiple is used, and the base register
5530 is r3, then r4 can become an ever live register without lr
5531 doing so, in this case we need to push lr as well, or we
5532 will fail to get a proper return. */
5534 live_regs_mask |= 0x4000;
5535 lr_save_eliminated = 0;
5539 if (lr_save_eliminated)
5540 fprintf (f,"\t%s I don't think this function clobbers lr\n",
5543 #ifdef AOF_ASSEMBLER
5545 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
5546 reg_names[PIC_OFFSET_TABLE_REGNUM]);
5552 output_func_epilogue (f, frame_size)
5556 int reg, live_regs_mask = 0;
5557 /* If we need this then it will always be at least this much */
5558 int floats_offset = 12;
5560 int volatile_func = (optimize > 0
5561 && TREE_THIS_VOLATILE (current_function_decl));
5563 if (use_return_insn (FALSE) && return_used_this_function)
5565 if ((frame_size + current_function_outgoing_args_size) != 0
5566 && !(frame_pointer_needed && TARGET_APCS))
5571 /* Naked functions don't have epilogues. */
5572 if (arm_naked_function_p (current_function_decl))
5575 /* A volatile function should never return. Call abort. */
5576 if (TARGET_ABORT_NORETURN && volatile_func)
5579 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_GOT ? "abort(PLT)" : "abort");
5580 assemble_external_libcall (op);
5581 output_asm_insn ("bl\t%a0", &op);
5585 for (reg = 0; reg <= 10; reg++)
5586 if (regs_ever_live[reg] && ! call_used_regs[reg])
5588 live_regs_mask |= (1 << reg);
5592 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5594 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5598 if (frame_pointer_needed)
5600 if (arm_fpu_arch == FP_SOFT2)
5602 for (reg = 23; reg > 15; reg--)
5603 if (regs_ever_live[reg] && ! call_used_regs[reg])
5605 floats_offset += 12;
5606 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
5607 reg_names[reg], REGISTER_PREFIX, floats_offset);
5614 for (reg = 23; reg > 15; reg--)
5616 if (regs_ever_live[reg] && ! call_used_regs[reg])
5618 floats_offset += 12;
5619 /* We can't unstack more than four registers at once */
5620 if (start_reg - reg == 3)
5622 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
5623 REGISTER_PREFIX, reg_names[reg],
5624 REGISTER_PREFIX, floats_offset);
5625 start_reg = reg - 1;
5630 if (reg != start_reg)
5631 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5632 REGISTER_PREFIX, reg_names[reg + 1],
5633 start_reg - reg, REGISTER_PREFIX, floats_offset);
5635 start_reg = reg - 1;
5639 /* Just in case the last register checked also needs unstacking. */
5640 if (reg != start_reg)
5641 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5642 REGISTER_PREFIX, reg_names[reg + 1],
5643 start_reg - reg, REGISTER_PREFIX, floats_offset);
5646 if (TARGET_THUMB_INTERWORK)
5648 live_regs_mask |= 0x6800;
5649 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5650 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5654 live_regs_mask |= 0xA800;
5655 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5656 TARGET_APCS_32 ? FALSE : TRUE);
5661 /* Restore stack pointer if necessary. */
5662 if (frame_size + current_function_outgoing_args_size != 0)
5664 operands[0] = operands[1] = stack_pointer_rtx;
5665 operands[2] = GEN_INT (frame_size
5666 + current_function_outgoing_args_size);
5667 output_add_immediate (operands);
5670 if (arm_fpu_arch == FP_SOFT2)
5672 for (reg = 16; reg < 24; reg++)
5673 if (regs_ever_live[reg] && ! call_used_regs[reg])
5674 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5675 reg_names[reg], REGISTER_PREFIX);
5681 for (reg = 16; reg < 24; reg++)
5683 if (regs_ever_live[reg] && ! call_used_regs[reg])
5685 if (reg - start_reg == 3)
5687 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5688 REGISTER_PREFIX, reg_names[start_reg],
5690 start_reg = reg + 1;
5695 if (reg != start_reg)
5696 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5697 REGISTER_PREFIX, reg_names[start_reg],
5698 reg - start_reg, REGISTER_PREFIX);
5700 start_reg = reg + 1;
5704 /* Just in case the last register checked also needs unstacking. */
5705 if (reg != start_reg)
5706 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5707 REGISTER_PREFIX, reg_names[start_reg],
5708 reg - start_reg, REGISTER_PREFIX);
5711 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5713 if (TARGET_THUMB_INTERWORK)
5715 if (! lr_save_eliminated)
5716 live_regs_mask |= 0x4000;
5718 if (live_regs_mask != 0)
5719 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5721 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5723 else if (lr_save_eliminated)
5724 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5725 : "\tmovs\t%spc, %slr\n"),
5726 REGISTER_PREFIX, REGISTER_PREFIX, f);
5728 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5729 TARGET_APCS_32 ? FALSE : TRUE);
5733 if (live_regs_mask || regs_ever_live[14])
5735 /* Restore the integer regs, and the return address into lr */
5736 if (! lr_save_eliminated)
5737 live_regs_mask |= 0x4000;
5739 if (live_regs_mask != 0)
5740 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5743 if (current_function_pretend_args_size)
5745 /* Unwind the pre-pushed regs */
5746 operands[0] = operands[1] = stack_pointer_rtx;
5747 operands[2] = GEN_INT (current_function_pretend_args_size);
5748 output_add_immediate (operands);
5750 /* And finally, go home */
5751 if (TARGET_THUMB_INTERWORK)
5752 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5753 else if (TARGET_APCS_32)
5754 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5756 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5762 /* Reset the ARM-specific per-function variables. */
5763 current_function_anonymous_args = 0;
5764 after_arm_reorg = 0;
5768 emit_multi_reg_push (mask)
5775 for (i = 0; i < 16; i++)
5776 if (mask & (1 << i))
5779 if (num_regs == 0 || num_regs > 16)
5782 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
5784 for (i = 0; i < 16; i++)
5786 if (mask & (1 << i))
5789 = gen_rtx_SET (VOIDmode,
5790 gen_rtx_MEM (BLKmode,
5791 gen_rtx_PRE_DEC (BLKmode,
5792 stack_pointer_rtx)),
5793 gen_rtx_UNSPEC (BLKmode,
5795 gen_rtx_REG (SImode, i)),
5801 for (j = 1, i++; j < num_regs; i++)
5803 if (mask & (1 << i))
5806 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
5815 emit_sfm (base_reg, count)
5822 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
5825 = gen_rtx_SET (VOIDmode,
5826 gen_rtx_MEM (BLKmode,
5827 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
5828 gen_rtx_UNSPEC (BLKmode,
5829 gen_rtvec (1, gen_rtx_REG (XFmode,
5832 for (i = 1; i < count; i++)
5833 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
5834 gen_rtx_REG (XFmode, base_reg++));
5840 arm_expand_prologue ()
5843 rtx amount = GEN_INT (-(get_frame_size ()
5844 + current_function_outgoing_args_size));
5845 int live_regs_mask = 0;
5846 int store_arg_regs = 0;
5847 int volatile_func = (optimize > 0
5848 && TREE_THIS_VOLATILE (current_function_decl));
5850 /* Naked functions don't have prologues. */
5851 if (arm_naked_function_p (current_function_decl))
5854 if (current_function_anonymous_args && current_function_pretend_args_size)
5857 if (! volatile_func)
5859 for (reg = 0; reg <= 10; reg++)
5860 if (regs_ever_live[reg] && ! call_used_regs[reg])
5861 live_regs_mask |= 1 << reg;
5863 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5864 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
5866 if (regs_ever_live[14])
5867 live_regs_mask |= 0x4000;
5870 if (frame_pointer_needed)
5872 live_regs_mask |= 0xD800;
5873 emit_insn (gen_movsi (gen_rtx_REG (SImode, 12),
5874 stack_pointer_rtx));
5877 if (current_function_pretend_args_size)
5880 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5883 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5884 GEN_INT (-current_function_pretend_args_size)));
5889 /* If we have to push any regs, then we must push lr as well, or
5890 we won't get a proper return. */
5891 live_regs_mask |= 0x4000;
5892 emit_multi_reg_push (live_regs_mask);
5895 /* For now the integer regs are still pushed in output_func_epilogue (). */
5897 if (! volatile_func)
5899 if (arm_fpu_arch == FP_SOFT2)
5901 for (reg = 23; reg > 15; reg--)
5902 if (regs_ever_live[reg] && ! call_used_regs[reg])
5903 emit_insn (gen_rtx_SET
5905 gen_rtx_MEM (XFmode,
5906 gen_rtx_PRE_DEC (XFmode,
5907 stack_pointer_rtx)),
5908 gen_rtx_REG (XFmode, reg)));
5914 for (reg = 23; reg > 15; reg--)
5916 if (regs_ever_live[reg] && ! call_used_regs[reg])
5918 if (start_reg - reg == 3)
5921 start_reg = reg - 1;
5926 if (start_reg != reg)
5927 emit_sfm (reg + 1, start_reg - reg);
5928 start_reg = reg - 1;
5932 if (start_reg != reg)
5933 emit_sfm (reg + 1, start_reg - reg);
5937 if (frame_pointer_needed)
5938 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, 12),
5940 (-(4 + current_function_pretend_args_size)))));
5942 if (amount != const0_rtx)
5944 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5945 emit_insn (gen_rtx_CLOBBER (VOIDmode,
5946 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
5949 /* If we are profiling, make sure no instructions are scheduled before
5950 the call to mcount. Similarly if the user has requested no
5951 scheduling in the prolog. */
5952 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
5953 emit_insn (gen_blockage ());
5957 /* If CODE is 'd', then the X is a condition operand and the instruction
5958 should only be executed if the condition is true.
5959 if CODE is 'D', then the X is a condition operand and the instruction
5960 should only be executed if the condition is false: however, if the mode
5961 of the comparison is CCFPEmode, then always execute the instruction -- we
5962 do this because in these circumstances !GE does not necessarily imply LT;
5963 in these cases the instruction pattern will take care to make sure that
5964 an instruction containing %d will follow, thereby undoing the effects of
5965 doing this instruction unconditionally.
5966 If CODE is 'N' then X is a floating point operand that must be negated
5968 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5969 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5972 arm_print_operand (stream, x, code)
5980 fputs (ASM_COMMENT_START, stream);
5984 fputs (REGISTER_PREFIX, stream);
5988 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5989 fputs (arm_condition_codes[arm_current_cc], stream);
5995 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5996 r = REAL_VALUE_NEGATE (r);
5997 fprintf (stream, "%s", fp_const_from_val (&r));
6002 if (GET_CODE (x) == CONST_INT)
6005 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6006 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6011 output_addr_const (stream, x);
6016 fprintf (stream, "%s", arithmetic_instr (x, 1));
6020 fprintf (stream, "%s", arithmetic_instr (x, 0));
6026 char * shift = shift_op (x, & val);
6030 fprintf (stream, ", %s ", shift_op (x, & val));
6032 arm_print_operand (stream, XEXP (x, 1), 0);
6035 fputc ('#', stream);
6036 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6045 fputs (REGISTER_PREFIX, stream);
6046 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6052 fputs (REGISTER_PREFIX, stream);
6053 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6057 fputs (REGISTER_PREFIX, stream);
6058 if (GET_CODE (XEXP (x, 0)) == REG)
6059 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6061 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6065 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
6066 REGISTER_PREFIX, reg_names[REGNO (x) - 1
6067 + ((GET_MODE_SIZE (GET_MODE (x))
6068 + GET_MODE_SIZE (SImode) - 1)
6069 / GET_MODE_SIZE (SImode))]);
6074 fputs (arm_condition_codes[get_arm_condition_code (x)],
6080 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6081 (get_arm_condition_code (x))],
6089 if (GET_CODE (x) == REG)
6091 fputs (REGISTER_PREFIX, stream);
6092 fputs (reg_names[REGNO (x)], stream);
6094 else if (GET_CODE (x) == MEM)
6096 output_memory_reference_mode = GET_MODE (x);
6097 output_address (XEXP (x, 0));
6099 else if (GET_CODE (x) == CONST_DOUBLE)
6100 fprintf (stream, "#%s", fp_immediate_constant (x));
6101 else if (GET_CODE (x) == NEG)
6102 abort (); /* This should never happen now. */
6105 fputc ('#', stream);
6106 output_addr_const (stream, x);
6112 /* A finite state machine takes care of noticing whether or not instructions
6113 can be conditionally executed, and thus decrease execution time and code
6114 size by deleting branch instructions. The fsm is controlled by
6115 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6117 /* The state of the fsm controlling condition codes are:
6118 0: normal, do nothing special
6119 1: make ASM_OUTPUT_OPCODE not output this instruction
6120 2: make ASM_OUTPUT_OPCODE not output this instruction
6121 3: make instructions conditional
6122 4: make instructions conditional
6124 State transitions (state->state by whom under condition):
6125 0 -> 1 final_prescan_insn if the `target' is a label
6126 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6127 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6128 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6129 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6130 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6131 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6132 (the target insn is arm_target_insn).
6134 If the jump clobbers the conditions then we use states 2 and 4.
6136 A similar thing can be done with conditional return insns.
6138 XXX In case the `target' is an unconditional branch, this conditionalising
6139 of the instructions always reduces code size, but not always execution
6140 time. But then, I want to reduce the code size to somewhere near what
6141 /bin/cc produces. */
6143 /* Returns the index of the ARM condition code string in
6144 `arm_condition_codes'. COMPARISON should be an rtx like
6145 `(eq (...) (...))'. */
6147 static enum arm_cond_code
6148 get_arm_condition_code (comparison)
6151 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6153 register enum rtx_code comp_code = GET_CODE (comparison);
6155 if (GET_MODE_CLASS (mode) != MODE_CC)
6156 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6157 XEXP (comparison, 1));
6161 case CC_DNEmode: code = ARM_NE; goto dominance;
6162 case CC_DEQmode: code = ARM_EQ; goto dominance;
6163 case CC_DGEmode: code = ARM_GE; goto dominance;
6164 case CC_DGTmode: code = ARM_GT; goto dominance;
6165 case CC_DLEmode: code = ARM_LE; goto dominance;
6166 case CC_DLTmode: code = ARM_LT; goto dominance;
6167 case CC_DGEUmode: code = ARM_CS; goto dominance;
6168 case CC_DGTUmode: code = ARM_HI; goto dominance;
6169 case CC_DLEUmode: code = ARM_LS; goto dominance;
6170 case CC_DLTUmode: code = ARM_CC;
6173 if (comp_code != EQ && comp_code != NE)
6176 if (comp_code == EQ)
6177 return ARM_INVERSE_CONDITION_CODE (code);
6183 case NE: return ARM_NE;
6184 case EQ: return ARM_EQ;
6185 case GE: return ARM_PL;
6186 case LT: return ARM_MI;
6194 case NE: return ARM_NE;
6195 case EQ: return ARM_EQ;
6202 case GE: return ARM_GE;
6203 case GT: return ARM_GT;
6204 case LE: return ARM_LS;
6205 case LT: return ARM_MI;
6212 case NE: return ARM_NE;
6213 case EQ: return ARM_EQ;
6214 case GE: return ARM_LE;
6215 case GT: return ARM_LT;
6216 case LE: return ARM_GE;
6217 case LT: return ARM_GT;
6218 case GEU: return ARM_LS;
6219 case GTU: return ARM_CC;
6220 case LEU: return ARM_CS;
6221 case LTU: return ARM_HI;
6228 case LTU: return ARM_CS;
6229 case GEU: return ARM_CC;
6236 case NE: return ARM_NE;
6237 case EQ: return ARM_EQ;
6238 case GE: return ARM_GE;
6239 case GT: return ARM_GT;
6240 case LE: return ARM_LE;
6241 case LT: return ARM_LT;
6242 case GEU: return ARM_CS;
6243 case GTU: return ARM_HI;
6244 case LEU: return ARM_LS;
6245 case LTU: return ARM_CC;
6257 arm_final_prescan_insn (insn)
6260 /* BODY will hold the body of INSN. */
6261 register rtx body = PATTERN (insn);
6263 /* This will be 1 if trying to repeat the trick, and things need to be
6264 reversed if it appears to fail. */
6267 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6268 taken are clobbered, even if the rtl suggests otherwise. It also
6269 means that we have to grub around within the jump expression to find
6270 out what the conditions are when the jump isn't taken. */
6271 int jump_clobbers = 0;
6273 /* If we start with a return insn, we only succeed if we find another one. */
6274 int seeking_return = 0;
6276 /* START_INSN will hold the insn from where we start looking. This is the
6277 first insn after the following code_label if REVERSE is true. */
6278 rtx start_insn = insn;
6280 /* If in state 4, check if the target branch is reached, in order to
6281 change back to state 0. */
6282 if (arm_ccfsm_state == 4)
6284 if (insn == arm_target_insn)
6286 arm_target_insn = NULL;
6287 arm_ccfsm_state = 0;
6292 /* If in state 3, it is possible to repeat the trick, if this insn is an
6293 unconditional branch to a label, and immediately following this branch
6294 is the previous target label which is only used once, and the label this
6295 branch jumps to is not too far off. */
6296 if (arm_ccfsm_state == 3)
6298 if (simplejump_p (insn))
6300 start_insn = next_nonnote_insn (start_insn);
6301 if (GET_CODE (start_insn) == BARRIER)
6303 /* XXX Isn't this always a barrier? */
6304 start_insn = next_nonnote_insn (start_insn);
6306 if (GET_CODE (start_insn) == CODE_LABEL
6307 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6308 && LABEL_NUSES (start_insn) == 1)
6313 else if (GET_CODE (body) == RETURN)
6315 start_insn = next_nonnote_insn (start_insn);
6316 if (GET_CODE (start_insn) == BARRIER)
6317 start_insn = next_nonnote_insn (start_insn);
6318 if (GET_CODE (start_insn) == CODE_LABEL
6319 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6320 && LABEL_NUSES (start_insn) == 1)
6332 if (arm_ccfsm_state != 0 && !reverse)
6334 if (GET_CODE (insn) != JUMP_INSN)
6337 /* This jump might be paralleled with a clobber of the condition codes
6338 the jump should always come first */
6339 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6340 body = XVECEXP (body, 0, 0);
6343 /* If this is a conditional return then we don't want to know */
6344 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6345 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6346 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6347 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6352 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6353 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6356 int fail = FALSE, succeed = FALSE;
6357 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6358 int then_not_else = TRUE;
6359 rtx this_insn = start_insn, label = 0;
6361 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6363 /* The code below is wrong for these, and I haven't time to
6364 fix it now. So we just do the safe thing and return. This
6365 whole function needs re-writing anyway. */
6370 /* Register the insn jumped to. */
6373 if (!seeking_return)
6374 label = XEXP (SET_SRC (body), 0);
6376 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6377 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6378 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6380 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6381 then_not_else = FALSE;
6383 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6385 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6388 then_not_else = FALSE;
6393 /* See how many insns this branch skips, and what kind of insns. If all
6394 insns are okay, and the label or unconditional branch to the same
6395 label is not too far away, succeed. */
6396 for (insns_skipped = 0;
6397 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6401 this_insn = next_nonnote_insn (this_insn);
6405 switch (GET_CODE (this_insn))
6408 /* Succeed if it is the target label, otherwise fail since
6409 control falls in from somewhere else. */
6410 if (this_insn == label)
6414 arm_ccfsm_state = 2;
6415 this_insn = next_nonnote_insn (this_insn);
6418 arm_ccfsm_state = 1;
6426 /* Succeed if the following insn is the target label.
6428 If return insns are used then the last insn in a function
6429 will be a barrier. */
6430 this_insn = next_nonnote_insn (this_insn);
6431 if (this_insn && this_insn == label)
6435 arm_ccfsm_state = 2;
6436 this_insn = next_nonnote_insn (this_insn);
6439 arm_ccfsm_state = 1;
6447 /* If using 32-bit addresses the cc is not preserved over
6451 /* Succeed if the following insn is the target label,
6452 or if the following two insns are a barrier and
6453 the target label. */
6454 this_insn = next_nonnote_insn (this_insn);
6455 if (this_insn && GET_CODE (this_insn) == BARRIER)
6456 this_insn = next_nonnote_insn (this_insn);
6458 if (this_insn && this_insn == label
6459 && insns_skipped < max_insns_skipped)
6463 arm_ccfsm_state = 2;
6464 this_insn = next_nonnote_insn (this_insn);
6467 arm_ccfsm_state = 1;
6476 /* If this is an unconditional branch to the same label, succeed.
6477 If it is to another label, do nothing. If it is conditional,
6479 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6481 scanbody = PATTERN (this_insn);
6482 if (GET_CODE (scanbody) == SET
6483 && GET_CODE (SET_DEST (scanbody)) == PC)
6485 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
6486 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
6488 arm_ccfsm_state = 2;
6491 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
6494 /* Fail if a conditional return is undesirable (eg on a
6495 StrongARM), but still allow this if optimizing for size. */
6496 else if (GET_CODE (scanbody) == RETURN
6497 && ! use_return_insn (TRUE)
6500 else if (GET_CODE (scanbody) == RETURN
6503 arm_ccfsm_state = 2;
6506 else if (GET_CODE (scanbody) == PARALLEL)
6508 switch (get_attr_conds (this_insn))
6520 /* Instructions using or affecting the condition codes make it
6522 scanbody = PATTERN (this_insn);
6523 if (! (GET_CODE (scanbody) == SET
6524 || GET_CODE (scanbody) == PARALLEL)
6525 || get_attr_conds (this_insn) != CONDS_NOCOND)
6535 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
6536 arm_target_label = CODE_LABEL_NUMBER (label);
6537 else if (seeking_return || arm_ccfsm_state == 2)
6539 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
6541 this_insn = next_nonnote_insn (this_insn);
6542 if (this_insn && (GET_CODE (this_insn) == BARRIER
6543 || GET_CODE (this_insn) == CODE_LABEL))
6548 /* Oh, dear! we ran off the end.. give up */
6549 recog (PATTERN (insn), insn, NULL_PTR);
6550 arm_ccfsm_state = 0;
6551 arm_target_insn = NULL;
6554 arm_target_insn = this_insn;
6563 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
6565 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
6566 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6567 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
6568 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6572 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6575 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
6579 if (reverse || then_not_else)
6580 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6582 /* restore recog_operand (getting the attributes of other insns can
6583 destroy this array, but final.c assumes that it remains intact
6584 across this call; since the insn has been recognized already we
6585 call recog direct). */
6586 recog (PATTERN (insn), insn, NULL_PTR);
6590 #ifdef AOF_ASSEMBLER
6591 /* Special functions only needed when producing AOF syntax assembler. */
6593 rtx aof_pic_label = NULL_RTX;
6596 struct pic_chain *next;
6600 static struct pic_chain *aof_pic_chain = NULL;
6606 struct pic_chain **chainp;
6609 if (aof_pic_label == NULL_RTX)
6611 /* This needs to persist throughout the compilation. */
6612 end_temporary_allocation ();
6613 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
6614 resume_temporary_allocation ();
6617 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6618 offset += 4, chainp = &(*chainp)->next)
6619 if ((*chainp)->symname == XSTR (x, 0))
6620 return plus_constant (aof_pic_label, offset);
6622 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6623 (*chainp)->next = NULL;
6624 (*chainp)->symname = XSTR (x, 0);
6625 return plus_constant (aof_pic_label, offset);
6629 aof_dump_pic_table (f)
6632 struct pic_chain *chain;
6634 if (aof_pic_chain == NULL)
6637 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
6638 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
6639 reg_names[PIC_OFFSET_TABLE_REGNUM]);
6640 fputs ("|x$adcons|\n", f);
6642 for (chain = aof_pic_chain; chain; chain = chain->next)
6644 fputs ("\tDCD\t", f);
6645 assemble_name (f, chain->symname);
6650 int arm_text_section_count = 1;
6655 static char buf[100];
6656 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6657 arm_text_section_count++);
6659 strcat (buf, ", PIC, REENTRANT");
6663 static int arm_data_section_count = 1;
6668 static char buf[100];
6669 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6673 /* The AOF assembler is religiously strict about declarations of
6674 imported and exported symbols, so that it is impossible to declare
6675 a function as imported near the beginning of the file, and then to
6676 export it later on. It is, however, possible to delay the decision
6677 until all the functions in the file have been compiled. To get
6678 around this, we maintain a list of the imports and exports, and
6679 delete from it any that are subsequently defined. At the end of
6680 compilation we spit the remainder of the list out before the END
6685 struct import *next;
6689 static struct import *imports_list = NULL;
6692 aof_add_import (name)
6697 for (new = imports_list; new; new = new->next)
6698 if (new->name == name)
6701 new = (struct import *) xmalloc (sizeof (struct import));
6702 new->next = imports_list;
6708 aof_delete_import (name)
6711 struct import **old;
6713 for (old = &imports_list; *old; old = & (*old)->next)
6715 if ((*old)->name == name)
6717 *old = (*old)->next;
6723 int arm_main_function = 0;
6726 aof_dump_imports (f)
6729 /* The AOF assembler needs this to cause the startup code to be extracted
6730 from the library. Brining in __main causes the whole thing to work
6732 if (arm_main_function)
6735 fputs ("\tIMPORT __main\n", f);
6736 fputs ("\tDCD __main\n", f);
6739 /* Now dump the remaining imports. */
6740 while (imports_list)
6742 fprintf (f, "\tIMPORT\t");
6743 assemble_name (f, imports_list->name);
6745 imports_list = imports_list->next;
6748 #endif /* AOF_ASSEMBLER */