1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
43 /* The maximum number of insns skipped which will be conditionalised if
45 static int max_insns_skipped = 5;
47 extern FILE * asm_out_file;
48 /* Some function declarations. */
50 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
51 static char * output_multi_immediate PROTO ((rtx *, char *, char *, int,
53 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
54 HOST_WIDE_INT, rtx, rtx, int, int));
55 static int arm_naked_function_p PROTO ((tree));
56 static void init_fpa_table PROTO ((void));
57 static enum machine_mode select_dominance_cc_mode PROTO ((rtx, rtx,
59 static HOST_WIDE_INT add_minipool_constant PROTO ((rtx, enum machine_mode));
60 static void dump_minipool PROTO ((rtx));
61 static rtx find_barrier PROTO ((rtx, int));
62 static void push_minipool_fix PROTO ((rtx, int, rtx *, enum machine_mode,
64 static void push_minipool_barrier PROTO ((rtx, int));
65 static void note_invalid_constants PROTO ((rtx, int));
66 static char * fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
67 static int eliminate_lr2ip PROTO ((rtx *));
68 static char * shift_op PROTO ((rtx, HOST_WIDE_INT *));
69 static int pattern_really_clobbers_lr PROTO ((rtx));
70 static int function_really_clobbers_lr PROTO ((rtx));
71 static void emit_multi_reg_push PROTO ((int));
72 static void emit_sfm PROTO ((int, int));
73 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
74 static int const_ok_for_op RTX_CODE_PROTO ((HOST_WIDE_INT, Rcode));
76 /* True if we are currently building a constant table. */
77 int making_const_table;
79 /* Define the information needed to generate branch insns. This is
80 stored from the compare operation. */
81 rtx arm_compare_op0, arm_compare_op1;
83 /* What type of floating point are we tuning for? */
84 enum floating_point_type arm_fpu;
86 /* What type of floating point instructions are available? */
87 enum floating_point_type arm_fpu_arch;
89 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
90 enum prog_mode_type arm_prgmode;
92 /* Set by the -mfp=... option */
93 const char * target_fp_name = NULL;
95 /* Used to parse -mstructure_size_boundary command line option. */
96 const char * structure_size_string = NULL;
97 int arm_structure_size_boundary = 32; /* Used to be 8 */
99 /* Bit values used to identify processor capabilities. */
100 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
101 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
102 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
103 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
104 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
105 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
106 #define FL_THUMB (1 << 6) /* Thumb aware */
107 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
108 #define FL_STRONG (1 << 8) /* StrongARM */
110 /* The bits in this mask specify which instructions we are allowed to
112 static int insn_flags = 0;
113 /* The bits in this mask specify which instruction scheduling options should
114 be used. Note - there is an overlap with the FL_FAST_MULT. For some
115 hardware we want to be able to generate the multiply instructions, but to
116 tune as if they were not present in the architecture. */
117 static int tune_flags = 0;
119 /* The following are used in the arm.md file as equivalents to bits
120 in the above two flag variables. */
122 /* Nonzero if this is an "M" variant of the processor. */
123 int arm_fast_multiply = 0;
125 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
128 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
131 /* Nonzero if this chip can benefit from load scheduling. */
132 int arm_ld_sched = 0;
134 /* Nonzero if this chip is a StrongARM. */
135 int arm_is_strong = 0;
137 /* Nonzero if this chip is a an ARM6 or an ARM7. */
138 int arm_is_6_or_7 = 0;
140 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
141 must report the mode of the memory reference from PRINT_OPERAND to
142 PRINT_OPERAND_ADDRESS. */
143 enum machine_mode output_memory_reference_mode;
145 /* Nonzero if the prologue must setup `fp'. */
146 int current_function_anonymous_args;
148 /* The register number to be used for the PIC offset register. */
149 const char * arm_pic_register_string = NULL;
150 int arm_pic_register = 9;
152 /* Set to one if we think that lr is only saved because of subroutine calls,
153 but all of these can be `put after' return insns */
154 int lr_save_eliminated;
156 /* Set to 1 when a return insn is output, this means that the epilogue
158 static int return_used_this_function;
160 /* Set to 1 after arm_reorg has started. Reset to start at the start of
161 the next function. */
162 static int after_arm_reorg = 0;
164 /* The maximum number of insns to be used when loading a constant. */
165 static int arm_constant_limit = 3;
167 /* For an explanation of these variables, see final_prescan_insn below. */
169 enum arm_cond_code arm_current_cc;
171 int arm_target_label;
173 /* The condition codes of the ARM, and the inverse function. */
174 char * arm_condition_codes[] =
176 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
177 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
180 static enum arm_cond_code get_arm_condition_code ();
182 #define streq(string1, string2) (strcmp (string1, string2) == 0)
184 /* Initialization code */
192 /* Not all of these give usefully different compilation alternatives,
193 but there is no simple way of generalizing them. */
194 static struct processors all_cores[] =
198 {"arm2", FL_CO_PROC | FL_MODE26 },
199 {"arm250", FL_CO_PROC | FL_MODE26 },
200 {"arm3", FL_CO_PROC | FL_MODE26 },
201 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
202 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
203 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
204 {"arm610", FL_MODE26 | FL_MODE32 },
205 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
206 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
207 /* arm7m doesn't exist on its own, but only with D, (and I), but
208 those don't alter the code, so arm7m is sometimes used. */
209 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
210 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
211 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
212 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
213 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
214 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
215 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
216 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
217 {"arm710", FL_MODE26 | FL_MODE32 },
218 {"arm710c", FL_MODE26 | FL_MODE32 },
219 {"arm7100", FL_MODE26 | FL_MODE32 },
220 {"arm7500", FL_MODE26 | FL_MODE32 },
221 /* Doesn't have an external co-proc, but does have embedded fpu. */
222 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
223 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
224 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
225 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
226 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
227 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
228 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
229 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
230 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
231 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
232 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
237 static struct processors all_architectures[] =
239 /* ARM Architectures */
241 { "armv2", FL_CO_PROC | FL_MODE26 },
242 { "armv2a", FL_CO_PROC | FL_MODE26 },
243 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
244 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
245 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
246 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
247 implementations that support it, so we will leave it out for now. */
248 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
249 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
253 /* This is a magic stucture. The 'string' field is magically filled in
254 with a pointer to the value specified by the user on the command line
255 assuming that the user has specified such a value. */
257 struct arm_cpu_select arm_select[] =
259 /* string name processors */
260 { NULL, "-mcpu=", all_cores },
261 { NULL, "-march=", all_architectures },
262 { NULL, "-mtune=", all_cores }
265 /* Return the number of bits set in value' */
270 unsigned int count = 0;
274 value &= ~(value & - value);
281 /* Fix up any incompatible options that the user has specified.
282 This has now turned into a maze. */
284 arm_override_options ()
288 /* Set up the flags based on the cpu/architecture selected by the user. */
289 for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
291 struct arm_cpu_select * ptr = arm_select + i;
293 if (ptr->string != NULL && ptr->string[0] != '\0')
295 const struct processors * sel;
297 for (sel = ptr->processors; sel->name != NULL; sel ++)
298 if (streq (ptr->string, sel->name))
301 tune_flags = sel->flags;
304 /* If we have been given an architecture and a processor
305 make sure that they are compatible. We only generate
306 a warning though, and we prefer the CPU over the
308 if (insn_flags != 0 && (insn_flags ^ sel->flags))
309 warning ("switch -mcpu=%s conflicts with -march= switch",
312 insn_flags = sel->flags;
318 if (sel->name == NULL)
319 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
323 /* If the user did not specify a processor, choose one for them. */
326 struct processors * sel;
328 static struct cpu_default
335 { TARGET_CPU_arm2, "arm2" },
336 { TARGET_CPU_arm6, "arm6" },
337 { TARGET_CPU_arm610, "arm610" },
338 { TARGET_CPU_arm710, "arm710" },
339 { TARGET_CPU_arm7m, "arm7m" },
340 { TARGET_CPU_arm7500fe, "arm7500fe" },
341 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
342 { TARGET_CPU_arm8, "arm8" },
343 { TARGET_CPU_arm810, "arm810" },
344 { TARGET_CPU_arm9, "arm9" },
345 { TARGET_CPU_strongarm, "strongarm" },
346 { TARGET_CPU_generic, "arm" },
349 struct cpu_default * def;
351 /* Find the default. */
352 for (def = cpu_defaults; def->name; def ++)
353 if (def->cpu == TARGET_CPU_DEFAULT)
356 /* Make sure we found the default CPU. */
357 if (def->name == NULL)
360 /* Find the default CPU's flags. */
361 for (sel = all_cores; sel->name != NULL; sel ++)
362 if (streq (def->name, sel->name))
365 if (sel->name == NULL)
368 insn_flags = sel->flags;
370 /* Now check to see if the user has specified some command line
371 switch that require certain abilities from the cpu. */
374 if (TARGET_INTERWORK)
376 sought |= (FL_THUMB | FL_MODE32);
378 /* Force apcs-32 to be used for interworking. */
379 target_flags |= ARM_FLAG_APCS_32;
381 /* There are no ARM processor that supports both APCS-26 and
382 interworking. Therefore we force FL_MODE26 to be removed
383 from insn_flags here (if it was set), so that the search
384 below will always be able to find a compatible processor. */
385 insn_flags &= ~ FL_MODE26;
388 if (! TARGET_APCS_32)
391 if (sought != 0 && ((sought & insn_flags) != sought))
393 /* Try to locate a CPU type that supports all of the abilities
394 of the default CPU, plus the extra abilities requested by
396 for (sel = all_cores; sel->name != NULL; sel ++)
397 if ((sel->flags & sought) == (sought | insn_flags))
400 if (sel->name == NULL)
402 unsigned int current_bit_count = 0;
403 struct processors * best_fit = NULL;
405 /* Ideally we would like to issue an error message here
406 saying that it was not possible to find a CPU compatible
407 with the default CPU, but which also supports the command
408 line options specified by the programmer, and so they
409 ought to use the -mcpu=<name> command line option to
410 override the default CPU type.
412 Unfortunately this does not work with multilibing. We
413 need to be able to support multilibs for -mapcs-26 and for
414 -mthumb-interwork and there is no CPU that can support both
415 options. Instead if we cannot find a cpu that has both the
416 characteristics of the default cpu and the given command line
417 options we scan the array again looking for a best match. */
418 for (sel = all_cores; sel->name != NULL; sel ++)
419 if ((sel->flags & sought) == sought)
423 count = bit_count (sel->flags & insn_flags);
425 if (count >= current_bit_count)
428 current_bit_count = count;
432 if (best_fit == NULL)
438 insn_flags = sel->flags;
442 /* If tuning has not been specified, tune for whichever processor or
443 architecture has been selected. */
445 tune_flags = insn_flags;
447 /* Make sure that the processor choice does not conflict with any of the
448 other command line choices. */
449 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
451 /* If APCS-32 was not the default then it must have been set by the
452 user, so issue a warning message. If the user has specified
453 "-mapcs-32 -mcpu=arm2" then we loose here. */
454 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
455 warning ("target CPU does not support APCS-32" );
456 target_flags &= ~ ARM_FLAG_APCS_32;
458 else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
460 warning ("target CPU does not support APCS-26" );
461 target_flags |= ARM_FLAG_APCS_32;
464 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
466 warning ("target CPU does not support interworking" );
467 target_flags &= ~ARM_FLAG_INTERWORK;
470 /* If interworking is enabled then APCS-32 must be selected as well. */
471 if (TARGET_INTERWORK)
473 if (! TARGET_APCS_32)
474 warning ("interworking forces APCS-32 to be used" );
475 target_flags |= ARM_FLAG_APCS_32;
478 if (TARGET_APCS_STACK && ! TARGET_APCS)
480 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
481 target_flags |= ARM_FLAG_APCS_FRAME;
484 if (TARGET_POKE_FUNCTION_NAME)
485 target_flags |= ARM_FLAG_APCS_FRAME;
487 if (TARGET_APCS_REENT && flag_pic)
488 fatal ("-fpic and -mapcs-reent are incompatible");
490 if (TARGET_APCS_REENT)
491 warning ("APCS reentrant code not supported. Ignored");
493 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
494 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
496 /* If stack checking is disabled, we can use r10 as the PIC register,
497 which keeps r9 available. */
498 if (flag_pic && ! TARGET_APCS_STACK)
499 arm_pic_register = 10;
501 if (TARGET_APCS_FLOAT)
502 warning ("Passing floating point arguments in fp regs not yet supported");
504 /* Initialise boolean versions of the flags, for use in the arm.md file. */
505 arm_fast_multiply = insn_flags & FL_FAST_MULT;
506 arm_arch4 = insn_flags & FL_ARCH4;
507 arm_arch5 = insn_flags & FL_ARCH5;
509 arm_ld_sched = tune_flags & FL_LDSCHED;
510 arm_is_strong = tune_flags & FL_STRONG;
511 arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
512 && !(tune_flags & FL_ARCH4));
514 /* Default value for floating point code... if no co-processor
515 bus, then schedule for emulated floating point. Otherwise,
516 assume the user has an FPA.
517 Note: this does not prevent use of floating point instructions,
518 -msoft-float does that. */
519 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
523 if (streq (target_fp_name, "2"))
524 arm_fpu_arch = FP_SOFT2;
525 else if (streq (target_fp_name, "3"))
526 arm_fpu_arch = FP_SOFT3;
528 fatal ("Invalid floating point emulation option: -mfpe-%s",
532 arm_fpu_arch = FP_DEFAULT;
534 if (TARGET_FPE && arm_fpu != FP_HARD)
537 /* For arm2/3 there is no need to do any scheduling if there is only
538 a floating point emulator, or we are doing software floating-point. */
539 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
540 && (tune_flags & FL_MODE32) == 0)
541 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
543 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
545 if (structure_size_string != NULL)
547 int size = strtol (structure_size_string, NULL, 0);
549 if (size == 8 || size == 32)
550 arm_structure_size_boundary = size;
552 warning ("Structure size boundary can only be set to 8 or 32");
555 if (arm_pic_register_string != NULL)
560 warning ("-mpic-register= is useless without -fpic");
562 pic_register = decode_reg_name (arm_pic_register_string);
564 /* Prevent the user from choosing an obviously stupid PIC register. */
565 if (pic_register < 0 || call_used_regs[pic_register]
566 || pic_register == HARD_FRAME_POINTER_REGNUM
567 || pic_register == STACK_POINTER_REGNUM
568 || pic_register >= PC_REGNUM)
569 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
571 arm_pic_register = pic_register;
574 /* If optimizing for space, don't synthesize constants.
575 For processors with load scheduling, it never costs more than 2 cycles
576 to load a constant, and the load scheduler may well reduce that to 1. */
577 if (optimize_size || (tune_flags & FL_LDSCHED))
578 arm_constant_limit = 1;
580 /* If optimizing for size, bump the number of instructions that we
581 are prepared to conditionally execute (even on a StrongARM).
582 Otherwise for the StrongARM, which has early execution of branches,
583 a sequence that is worth skipping is shorter. */
585 max_insns_skipped = 6;
586 else if (arm_is_strong)
587 max_insns_skipped = 3;
590 /* Return 1 if it is possible to return using a single instruction */
593 use_return_insn (iscond)
598 if (!reload_completed
599 || current_function_pretend_args_size
600 || current_function_anonymous_args
601 || ((get_frame_size () + current_function_outgoing_args_size != 0)
602 && !(TARGET_APCS && frame_pointer_needed)))
605 /* Can't be done if interworking with Thumb, and any registers have been
606 stacked. Similarly, on StrongARM, conditional returns are expensive
607 if they aren't taken and registers have been stacked. */
608 if (iscond && arm_is_strong && frame_pointer_needed)
610 if ((iscond && arm_is_strong)
613 for (regno = 0; regno < 16; regno++)
614 if (regs_ever_live[regno] && ! call_used_regs[regno])
617 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
621 /* Can't be done if any of the FPU regs are pushed, since this also
623 for (regno = 16; regno < 24; regno++)
624 if (regs_ever_live[regno] && ! call_used_regs[regno])
627 /* If a function is naked, don't use the "return" insn. */
628 if (arm_naked_function_p (current_function_decl))
634 /* Return TRUE if int I is a valid immediate ARM constant. */
640 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
642 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
643 be all zero, or all one. */
644 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
645 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
646 != ((~(unsigned HOST_WIDE_INT) 0)
647 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
650 /* Fast return for 0 and powers of 2 */
651 if ((i & (i - 1)) == 0)
656 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
659 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
660 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
661 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
666 /* Return true if I is a valid constant for the operation CODE. */
668 const_ok_for_op (i, code)
672 if (const_ok_for_arm (i))
678 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
680 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
686 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
693 /* Emit a sequence of insns to handle a large constant.
694 CODE is the code of the operation required, it can be any of SET, PLUS,
695 IOR, AND, XOR, MINUS;
696 MODE is the mode in which the operation is being performed;
697 VAL is the integer to operate on;
698 SOURCE is the other operand (a register, or a null-pointer for SET);
699 SUBTARGETS means it is safe to create scratch registers if that will
700 either produce a simpler sequence, or we will want to cse the values.
701 Return value is the number of insns emitted. */
704 arm_split_constant (code, mode, val, target, source, subtargets)
706 enum machine_mode mode;
712 if (subtargets || code == SET
713 || (GET_CODE (target) == REG && GET_CODE (source) == REG
714 && REGNO (target) != REGNO (source)))
716 /* After arm_reorg has been called, we can't fix up expensive
717 constants by pushing them into memory so we must synthesise
718 them in-line, regardless of the cost. This is only likely to
719 be more costly on chips that have load delay slots and we are
720 compiling without running the scheduler (so no splitting
721 occurred before the final instruction emission).
723 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
725 if (! after_arm_reorg
726 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
727 > arm_constant_limit + (code != SET)))
731 /* Currently SET is the only monadic value for CODE, all
732 the rest are diadic. */
733 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
738 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
740 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
741 /* For MINUS, the value is subtracted from, since we never
742 have subtraction of a constant. */
744 emit_insn (gen_rtx_SET (VOIDmode, target,
745 gen_rtx (code, mode, temp, source)));
747 emit_insn (gen_rtx_SET (VOIDmode, target,
748 gen_rtx (code, mode, source, temp)));
754 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
757 /* As above, but extra parameter GENERATE which, if clear, suppresses
760 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
762 enum machine_mode mode;
771 int can_negate_initial = 0;
774 int num_bits_set = 0;
775 int set_sign_bit_copies = 0;
776 int clear_sign_bit_copies = 0;
777 int clear_zero_bit_copies = 0;
778 int set_zero_bit_copies = 0;
780 unsigned HOST_WIDE_INT temp1, temp2;
781 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
783 /* find out which operations are safe for a given CODE. Also do a quick
784 check for degenerate cases; these can occur when DImode operations
796 can_negate_initial = 1;
800 if (remainder == 0xffffffff)
803 emit_insn (gen_rtx_SET (VOIDmode, target,
804 GEN_INT (ARM_SIGN_EXTEND (val))));
809 if (reload_completed && rtx_equal_p (target, source))
812 emit_insn (gen_rtx_SET (VOIDmode, target, source));
821 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
824 if (remainder == 0xffffffff)
826 if (reload_completed && rtx_equal_p (target, source))
829 emit_insn (gen_rtx_SET (VOIDmode, target, source));
838 if (reload_completed && rtx_equal_p (target, source))
841 emit_insn (gen_rtx_SET (VOIDmode, target, source));
844 if (remainder == 0xffffffff)
847 emit_insn (gen_rtx_SET (VOIDmode, target,
848 gen_rtx_NOT (mode, source)));
852 /* We don't know how to handle this yet below. */
856 /* We treat MINUS as (val - source), since (source - val) is always
857 passed as (source + (-val)). */
861 emit_insn (gen_rtx_SET (VOIDmode, target,
862 gen_rtx_NEG (mode, source)));
865 if (const_ok_for_arm (val))
868 emit_insn (gen_rtx_SET (VOIDmode, target,
869 gen_rtx_MINUS (mode, GEN_INT (val),
881 /* If we can do it in one insn get out quickly */
882 if (const_ok_for_arm (val)
883 || (can_negate_initial && const_ok_for_arm (-val))
884 || (can_invert && const_ok_for_arm (~val)))
887 emit_insn (gen_rtx_SET (VOIDmode, target,
888 (source ? gen_rtx (code, mode, source,
895 /* Calculate a few attributes that may be useful for specific
898 for (i = 31; i >= 0; i--)
900 if ((remainder & (1 << i)) == 0)
901 clear_sign_bit_copies++;
906 for (i = 31; i >= 0; i--)
908 if ((remainder & (1 << i)) != 0)
909 set_sign_bit_copies++;
914 for (i = 0; i <= 31; i++)
916 if ((remainder & (1 << i)) == 0)
917 clear_zero_bit_copies++;
922 for (i = 0; i <= 31; i++)
924 if ((remainder & (1 << i)) != 0)
925 set_zero_bit_copies++;
933 /* See if we can do this by sign_extending a constant that is known
934 to be negative. This is a good, way of doing it, since the shift
935 may well merge into a subsequent insn. */
936 if (set_sign_bit_copies > 1)
939 (temp1 = ARM_SIGN_EXTEND (remainder
940 << (set_sign_bit_copies - 1))))
944 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
945 emit_insn (gen_rtx_SET (VOIDmode, new_src,
947 emit_insn (gen_ashrsi3 (target, new_src,
948 GEN_INT (set_sign_bit_copies - 1)));
952 /* For an inverted constant, we will need to set the low bits,
953 these will be shifted out of harm's way. */
954 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
955 if (const_ok_for_arm (~temp1))
959 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
960 emit_insn (gen_rtx_SET (VOIDmode, new_src,
962 emit_insn (gen_ashrsi3 (target, new_src,
963 GEN_INT (set_sign_bit_copies - 1)));
969 /* See if we can generate this by setting the bottom (or the top)
970 16 bits, and then shifting these into the other half of the
971 word. We only look for the simplest cases, to do more would cost
972 too much. Be careful, however, not to generate this when the
973 alternative would take fewer insns. */
974 if (val & 0xffff0000)
976 temp1 = remainder & 0xffff0000;
977 temp2 = remainder & 0x0000ffff;
979 /* Overlaps outside this range are best done using other methods. */
980 for (i = 9; i < 24; i++)
982 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
983 && ! const_ok_for_arm (temp2))
985 rtx new_src = (subtargets
986 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
988 insns = arm_gen_constant (code, mode, temp2, new_src,
989 source, subtargets, generate);
992 emit_insn (gen_rtx_SET
995 gen_rtx_ASHIFT (mode, source,
1002 /* Don't duplicate cases already considered. */
1003 for (i = 17; i < 24; i++)
1005 if (((temp1 | (temp1 >> i)) == remainder)
1006 && ! const_ok_for_arm (temp1))
1008 rtx new_src = (subtargets
1009 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1011 insns = arm_gen_constant (code, mode, temp1, new_src,
1012 source, subtargets, generate);
1016 (gen_rtx_SET (VOIDmode, target,
1019 gen_rtx_LSHIFTRT (mode, source,
1030 /* If we have IOR or XOR, and the constant can be loaded in a
1031 single instruction, and we can find a temporary to put it in,
1032 then this can be done in two instructions instead of 3-4. */
1034 /* TARGET can't be NULL if SUBTARGETS is 0 */
1035 || (reload_completed && ! reg_mentioned_p (target, source)))
1037 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
1041 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1043 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1044 emit_insn (gen_rtx_SET (VOIDmode, target,
1045 gen_rtx (code, mode, source, sub)));
1054 if (set_sign_bit_copies > 8
1055 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1059 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1060 rtx shift = GEN_INT (set_sign_bit_copies);
1062 emit_insn (gen_rtx_SET (VOIDmode, sub,
1064 gen_rtx_ASHIFT (mode,
1067 emit_insn (gen_rtx_SET (VOIDmode, target,
1069 gen_rtx_LSHIFTRT (mode, sub,
1075 if (set_zero_bit_copies > 8
1076 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1080 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1081 rtx shift = GEN_INT (set_zero_bit_copies);
1083 emit_insn (gen_rtx_SET (VOIDmode, sub,
1085 gen_rtx_LSHIFTRT (mode,
1088 emit_insn (gen_rtx_SET (VOIDmode, target,
1090 gen_rtx_ASHIFT (mode, sub,
1096 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
1100 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1101 emit_insn (gen_rtx_SET (VOIDmode, sub,
1102 gen_rtx_NOT (mode, source)));
1105 sub = gen_reg_rtx (mode);
1106 emit_insn (gen_rtx_SET (VOIDmode, sub,
1107 gen_rtx_AND (mode, source,
1109 emit_insn (gen_rtx_SET (VOIDmode, target,
1110 gen_rtx_NOT (mode, sub)));
1117 /* See if two shifts will do 2 or more insn's worth of work. */
1118 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1120 HOST_WIDE_INT shift_mask = ((0xffffffff
1121 << (32 - clear_sign_bit_copies))
1124 if ((remainder | shift_mask) != 0xffffffff)
1128 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1129 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1130 new_src, source, subtargets, 1);
1135 rtx targ = subtargets ? NULL_RTX : target;
1136 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1137 targ, source, subtargets, 0);
1143 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1144 rtx shift = GEN_INT (clear_sign_bit_copies);
1146 emit_insn (gen_ashlsi3 (new_src, source, shift));
1147 emit_insn (gen_lshrsi3 (target, new_src, shift));
1153 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1155 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1157 if ((remainder | shift_mask) != 0xffffffff)
1161 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1163 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1164 new_src, source, subtargets, 1);
1169 rtx targ = subtargets ? NULL_RTX : target;
1171 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1172 targ, source, subtargets, 0);
1178 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1179 rtx shift = GEN_INT (clear_zero_bit_copies);
1181 emit_insn (gen_lshrsi3 (new_src, source, shift));
1182 emit_insn (gen_ashlsi3 (target, new_src, shift));
1194 for (i = 0; i < 32; i++)
1195 if (remainder & (1 << i))
1198 if (code == AND || (can_invert && num_bits_set > 16))
1199 remainder = (~remainder) & 0xffffffff;
1200 else if (code == PLUS && num_bits_set > 16)
1201 remainder = (-remainder) & 0xffffffff;
1208 /* Now try and find a way of doing the job in either two or three
1210 We start by looking for the largest block of zeros that are aligned on
1211 a 2-bit boundary, we then fill up the temps, wrapping around to the
1212 top of the word when we drop off the bottom.
1213 In the worst case this code should produce no more than four insns. */
1216 int best_consecutive_zeros = 0;
1218 for (i = 0; i < 32; i += 2)
1220 int consecutive_zeros = 0;
1222 if (! (remainder & (3 << i)))
1224 while ((i < 32) && ! (remainder & (3 << i)))
1226 consecutive_zeros += 2;
1229 if (consecutive_zeros > best_consecutive_zeros)
1231 best_consecutive_zeros = consecutive_zeros;
1232 best_start = i - consecutive_zeros;
1238 /* Now start emitting the insns, starting with the one with the highest
1239 bit set: we do this so that the smallest number will be emitted last;
1240 this is more likely to be combinable with addressing insns. */
1248 if (remainder & (3 << (i - 2)))
1253 temp1 = remainder & ((0x0ff << end)
1254 | ((i < end) ? (0xff >> (32 - end)) : 0));
1255 remainder &= ~temp1;
1262 emit_insn (gen_rtx_SET (VOIDmode,
1263 new_src = (subtargets
1264 ? gen_reg_rtx (mode)
1267 ? ~temp1 : temp1)));
1268 else if (code == MINUS)
1269 emit_insn (gen_rtx_SET (VOIDmode,
1270 new_src = (subtargets
1271 ? gen_reg_rtx (mode)
1273 gen_rtx (code, mode, GEN_INT (temp1),
1276 emit_insn (gen_rtx_SET (VOIDmode,
1277 new_src = (remainder
1279 ? gen_reg_rtx (mode)
1282 gen_rtx (code, mode, source,
1283 GEN_INT (can_invert ? ~temp1
1295 else if (code == MINUS)
1302 } while (remainder);
1307 /* Canonicalize a comparison so that we are more likely to recognize it.
1308 This can be done for a few constant compares, where we can make the
1309 immediate value easier to load. */
1311 arm_canonicalize_comparison (code, op1)
1315 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1325 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1327 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1329 *op1 = GEN_INT (i+1);
1330 return code == GT ? GE : LT;
1336 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1337 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1339 *op1 = GEN_INT (i-1);
1340 return code == GE ? GT : LE;
1346 if (i != ~((unsigned HOST_WIDE_INT) 0)
1347 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1349 *op1 = GEN_INT (i + 1);
1350 return code == GTU ? GEU : LTU;
1357 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1359 *op1 = GEN_INT (i - 1);
1360 return code == GEU ? GTU : LEU;
1371 /* Decide whether a type should be returned in memory (true)
1372 or in a register (false). This is called by the macro
1373 RETURN_IN_MEMORY. */
1375 arm_return_in_memory (type)
1378 if (! AGGREGATE_TYPE_P (type))
1380 /* All simple types are returned in registers. */
1383 else if (int_size_in_bytes (type) > 4)
1385 /* All structures/unions bigger than one word are returned in memory. */
1388 else if (TREE_CODE (type) == RECORD_TYPE)
1392 /* For a struct the APCS says that we must return in a register if
1393 every addressable element has an offset of zero. For practical
1394 purposes this means that the structure can have at most one non
1395 bit-field element and that this element must be the first one in
1398 /* Find the first field, ignoring non FIELD_DECL things which will
1399 have been created by C++. */
1400 for (field = TYPE_FIELDS (type);
1401 field && TREE_CODE (field) != FIELD_DECL;
1402 field = TREE_CHAIN (field))
1406 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1408 /* Now check the remaining fields, if any. */
1409 for (field = TREE_CHAIN (field);
1411 field = TREE_CHAIN (field))
1413 if (TREE_CODE (field) != FIELD_DECL)
1416 if (! DECL_BIT_FIELD_TYPE (field))
1422 else if (TREE_CODE (type) == UNION_TYPE)
1426 /* Unions can be returned in registers if every element is
1427 integral, or can be returned in an integer register. */
1428 for (field = TYPE_FIELDS (type);
1430 field = TREE_CHAIN (field))
1432 if (TREE_CODE (field) != FIELD_DECL)
1435 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1438 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1445 /* XXX Not sure what should be done for other aggregates, so put them in
1451 legitimate_pic_operand_p (x)
1454 if (CONSTANT_P (x) && flag_pic
1455 && (GET_CODE (x) == SYMBOL_REF
1456 || (GET_CODE (x) == CONST
1457 && GET_CODE (XEXP (x, 0)) == PLUS
1458 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1465 legitimize_pic_address (orig, mode, reg)
1467 enum machine_mode mode;
1470 if (GET_CODE (orig) == SYMBOL_REF)
1472 rtx pic_ref, address;
1478 if (reload_in_progress || reload_completed)
1481 reg = gen_reg_rtx (Pmode);
1486 #ifdef AOF_ASSEMBLER
1487 /* The AOF assembler can generate relocations for these directly, and
1488 understands that the PIC register has to be added into the offset.
1490 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1493 address = gen_reg_rtx (Pmode);
1497 emit_insn (gen_pic_load_addr (address, orig));
1499 pic_ref = gen_rtx_MEM (Pmode,
1500 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
1502 RTX_UNCHANGING_P (pic_ref) = 1;
1503 insn = emit_move_insn (reg, pic_ref);
1505 current_function_uses_pic_offset_table = 1;
1506 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1508 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1512 else if (GET_CODE (orig) == CONST)
1516 if (GET_CODE (XEXP (orig, 0)) == PLUS
1517 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1522 if (reload_in_progress || reload_completed)
1525 reg = gen_reg_rtx (Pmode);
1528 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1530 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1531 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1532 base == reg ? 0 : reg);
1537 if (GET_CODE (offset) == CONST_INT)
1539 /* The base register doesn't really matter, we only want to
1540 test the index for the appropriate mode. */
1541 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1543 if (! reload_in_progress && ! reload_completed)
1544 offset = force_reg (Pmode, offset);
1549 if (GET_CODE (offset) == CONST_INT)
1550 return plus_constant_for_output (base, INTVAL (offset));
1553 if (GET_MODE_SIZE (mode) > 4
1554 && (GET_MODE_CLASS (mode) == MODE_INT
1555 || TARGET_SOFT_FLOAT))
1557 emit_insn (gen_addsi3 (reg, base, offset));
1561 return gen_rtx_PLUS (Pmode, base, offset);
1563 else if (GET_CODE (orig) == LABEL_REF)
1564 current_function_uses_pic_offset_table = 1;
1583 #ifndef AOF_ASSEMBLER
1584 rtx l1, pic_tmp, pic_tmp2, seq;
1585 rtx global_offset_table;
1587 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
1594 l1 = gen_label_rtx ();
1596 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1597 /* On the ARM the PC register contains 'dot + 8' at the time of the
1599 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
1601 pic_tmp2 = gen_rtx_CONST (VOIDmode,
1602 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
1604 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
1606 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
1608 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1609 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
1611 seq = gen_sequence ();
1613 emit_insn_after (seq, get_insns ());
1615 /* Need to emit this whether or not we obey regdecls,
1616 since setjmp/longjmp can cause life info to screw up. */
1617 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1618 #endif /* AOF_ASSEMBLER */
1621 #define REG_OR_SUBREG_REG(X) \
1622 (GET_CODE (X) == REG \
1623 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1625 #define REG_OR_SUBREG_RTX(X) \
1626 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1628 #define ARM_FRAME_RTX(X) \
1629 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1630 || (X) == arg_pointer_rtx)
1633 arm_rtx_costs (x, code)
1637 enum machine_mode mode = GET_MODE (x);
1638 enum rtx_code subcode;
1644 /* Memory costs quite a lot for the first word, but subsequent words
1645 load at the equivalent of a single insn each. */
1646 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1647 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1654 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1661 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1663 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1664 + ((GET_CODE (XEXP (x, 0)) == REG
1665 || (GET_CODE (XEXP (x, 0)) == SUBREG
1666 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1668 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1669 || (GET_CODE (XEXP (x, 0)) == SUBREG
1670 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1672 + ((GET_CODE (XEXP (x, 1)) == REG
1673 || (GET_CODE (XEXP (x, 1)) == SUBREG
1674 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1675 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1680 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1681 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1682 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1683 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1686 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1687 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1688 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1689 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1691 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1692 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1693 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1696 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1697 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1698 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1699 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1700 || subcode == ASHIFTRT || subcode == LSHIFTRT
1701 || subcode == ROTATE || subcode == ROTATERT
1703 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1704 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1705 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1706 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1707 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1708 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1709 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1714 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1715 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1716 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1717 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1718 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1722 case AND: case XOR: case IOR:
1725 /* Normally the frame registers will be spilt into reg+const during
1726 reload, so it is a bad idea to combine them with other instructions,
1727 since then they might not be moved outside of loops. As a compromise
1728 we allow integration with ops that have a constant as their second
1730 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1731 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1732 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1733 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1734 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1738 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1739 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1740 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1741 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1744 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1745 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1746 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1747 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1748 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
1751 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1752 return (1 + extra_cost
1753 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1754 || subcode == LSHIFTRT || subcode == ASHIFTRT
1755 || subcode == ROTATE || subcode == ROTATERT
1757 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1758 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1759 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1760 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1761 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1762 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1768 /* There is no point basing this on the tuning, since it is always the
1769 fast variant if it exists at all */
1770 if (arm_fast_multiply && mode == DImode
1771 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1772 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1773 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1776 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1780 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1782 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1783 & (unsigned HOST_WIDE_INT) 0xffffffff);
1784 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1786 /* Tune as appropriate */
1787 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1789 for (j = 0; i && j < 32; j += booth_unit_size)
1791 i >>= booth_unit_size;
1798 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1799 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1800 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1803 if (arm_fast_multiply && mode == SImode
1804 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1805 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1806 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1807 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1808 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1809 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1814 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1815 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1819 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1821 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1824 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1832 return 4 + (mode == DImode ? 4 : 0);
1835 if (GET_MODE (XEXP (x, 0)) == QImode)
1836 return (4 + (mode == DImode ? 4 : 0)
1837 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1840 switch (GET_MODE (XEXP (x, 0)))
1843 return (1 + (mode == DImode ? 4 : 0)
1844 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1847 return (4 + (mode == DImode ? 4 : 0)
1848 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1851 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1864 arm_adjust_cost (insn, link, dep, cost)
1872 /* XXX This is not strictly true for the FPA. */
1873 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
1874 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
1877 if ((i_pat = single_set (insn)) != NULL
1878 && GET_CODE (SET_SRC (i_pat)) == MEM
1879 && (d_pat = single_set (dep)) != NULL
1880 && GET_CODE (SET_DEST (d_pat)) == MEM)
1882 /* This is a load after a store, there is no conflict if the load reads
1883 from a cached area. Assume that loads from the stack, and from the
1884 constant pool are cached, and that others will miss. This is a
1887 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1888 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1889 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1890 || reg_mentioned_p (hard_frame_pointer_rtx,
1891 XEXP (SET_SRC (i_pat), 0)))
1898 /* This code has been fixed for cross compilation. */
1900 static int fpa_consts_inited = 0;
1902 char * strings_fpa[8] =
1905 "4", "5", "0.5", "10"
1908 static REAL_VALUE_TYPE values_fpa[8];
1916 for (i = 0; i < 8; i++)
1918 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1922 fpa_consts_inited = 1;
1925 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1928 const_double_rtx_ok_for_fpu (x)
1934 if (!fpa_consts_inited)
1937 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1938 if (REAL_VALUE_MINUS_ZERO (r))
1941 for (i = 0; i < 8; i++)
1942 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1948 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1951 neg_const_double_rtx_ok_for_fpu (x)
1957 if (!fpa_consts_inited)
1960 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1961 r = REAL_VALUE_NEGATE (r);
1962 if (REAL_VALUE_MINUS_ZERO (r))
1965 for (i = 0; i < 8; i++)
1966 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1972 /* Predicates for `match_operand' and `match_operator'. */
1974 /* s_register_operand is the same as register_operand, but it doesn't accept
1977 This function exists because at the time it was put in it led to better
1978 code. SUBREG(MEM) always needs a reload in the places where
1979 s_register_operand is used, and this seemed to lead to excessive
1983 s_register_operand (op, mode)
1985 enum machine_mode mode;
1987 if (GET_MODE (op) != mode && mode != VOIDmode)
1990 if (GET_CODE (op) == SUBREG)
1991 op = SUBREG_REG (op);
1993 /* We don't consider registers whose class is NO_REGS
1994 to be a register operand. */
1995 return (GET_CODE (op) == REG
1996 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1997 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2000 /* Only accept reg, subreg(reg), const_int. */
2003 reg_or_int_operand (op, mode)
2005 enum machine_mode mode;
2007 if (GET_CODE (op) == CONST_INT)
2010 if (GET_MODE (op) != mode && mode != VOIDmode)
2013 if (GET_CODE (op) == SUBREG)
2014 op = SUBREG_REG (op);
2016 /* We don't consider registers whose class is NO_REGS
2017 to be a register operand. */
2018 return (GET_CODE (op) == REG
2019 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2020 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2023 /* Return 1 if OP is an item in memory, given that we are in reload. */
2026 reload_memory_operand (op, mode)
2028 enum machine_mode mode ATTRIBUTE_UNUSED;
2030 int regno = true_regnum (op);
2032 return (! CONSTANT_P (op)
2034 || (GET_CODE (op) == REG
2035 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2038 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2039 memory access (architecture V4) */
2041 bad_signed_byte_operand (op, mode)
2043 enum machine_mode mode;
2045 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
2050 /* A sum of anything more complex than reg + reg or reg + const is bad */
2051 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2052 && (! s_register_operand (XEXP (op, 0), VOIDmode)
2053 || (! s_register_operand (XEXP (op, 1), VOIDmode)
2054 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2057 /* Big constants are also bad */
2058 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2059 && (INTVAL (XEXP (op, 1)) > 0xff
2060 || -INTVAL (XEXP (op, 1)) > 0xff))
2063 /* Everything else is good, or can will automatically be made so. */
2067 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2070 arm_rhs_operand (op, mode)
2072 enum machine_mode mode;
2074 return (s_register_operand (op, mode)
2075 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
2078 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2082 arm_rhsm_operand (op, mode)
2084 enum machine_mode mode;
2086 return (s_register_operand (op, mode)
2087 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
2088 || memory_operand (op, mode));
2091 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2092 constant that is valid when negated. */
2095 arm_add_operand (op, mode)
2097 enum machine_mode mode;
2099 return (s_register_operand (op, mode)
2100 || (GET_CODE (op) == CONST_INT
2101 && (const_ok_for_arm (INTVAL (op))
2102 || const_ok_for_arm (-INTVAL (op)))));
2106 arm_not_operand (op, mode)
2108 enum machine_mode mode;
2110 return (s_register_operand (op, mode)
2111 || (GET_CODE (op) == CONST_INT
2112 && (const_ok_for_arm (INTVAL (op))
2113 || const_ok_for_arm (~INTVAL (op)))));
2116 /* Return TRUE if the operand is a memory reference which contains an
2117 offsettable address. */
2119 offsettable_memory_operand (op, mode)
2121 enum machine_mode mode;
2123 if (mode == VOIDmode)
2124 mode = GET_MODE (op);
2126 return (mode == GET_MODE (op)
2127 && GET_CODE (op) == MEM
2128 && offsettable_address_p (reload_completed | reload_in_progress,
2129 mode, XEXP (op, 0)));
2132 /* Return TRUE if the operand is a memory reference which is, or can be
2133 made word aligned by adjusting the offset. */
2135 alignable_memory_operand (op, mode)
2137 enum machine_mode mode;
2141 if (mode == VOIDmode)
2142 mode = GET_MODE (op);
2144 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
2149 return ((GET_CODE (reg = op) == REG
2150 || (GET_CODE (op) == SUBREG
2151 && GET_CODE (reg = SUBREG_REG (op)) == REG)
2152 || (GET_CODE (op) == PLUS
2153 && GET_CODE (XEXP (op, 1)) == CONST_INT
2154 && (GET_CODE (reg = XEXP (op, 0)) == REG
2155 || (GET_CODE (XEXP (op, 0)) == SUBREG
2156 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
2157 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
2160 /* Similar to s_register_operand, but does not allow hard integer
2163 f_register_operand (op, mode)
2165 enum machine_mode mode;
2167 if (GET_MODE (op) != mode && mode != VOIDmode)
2170 if (GET_CODE (op) == SUBREG)
2171 op = SUBREG_REG (op);
2173 /* We don't consider registers whose class is NO_REGS
2174 to be a register operand. */
2175 return (GET_CODE (op) == REG
2176 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2177 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
2180 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2183 fpu_rhs_operand (op, mode)
2185 enum machine_mode mode;
2187 if (s_register_operand (op, mode))
2189 else if (GET_CODE (op) == CONST_DOUBLE)
2190 return (const_double_rtx_ok_for_fpu (op));
2196 fpu_add_operand (op, mode)
2198 enum machine_mode mode;
2200 if (s_register_operand (op, mode))
2202 else if (GET_CODE (op) == CONST_DOUBLE)
2203 return (const_double_rtx_ok_for_fpu (op)
2204 || neg_const_double_rtx_ok_for_fpu (op));
2209 /* Return nonzero if OP is a constant power of two. */
2212 power_of_two_operand (op, mode)
2214 enum machine_mode mode ATTRIBUTE_UNUSED;
2216 if (GET_CODE (op) == CONST_INT)
2218 HOST_WIDE_INT value = INTVAL(op);
2219 return value != 0 && (value & (value - 1)) == 0;
2224 /* Return TRUE for a valid operand of a DImode operation.
2225 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2226 Note that this disallows MEM(REG+REG), but allows
2227 MEM(PRE/POST_INC/DEC(REG)). */
2230 di_operand (op, mode)
2232 enum machine_mode mode;
2234 if (s_register_operand (op, mode))
2237 if (GET_CODE (op) == SUBREG)
2238 op = SUBREG_REG (op);
2240 switch (GET_CODE (op))
2247 return memory_address_p (DImode, XEXP (op, 0));
2254 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2255 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2256 Note that this disallows MEM(REG+REG), but allows
2257 MEM(PRE/POST_INC/DEC(REG)). */
2260 soft_df_operand (op, mode)
2262 enum machine_mode mode;
2264 if (s_register_operand (op, mode))
2267 if (GET_CODE (op) == SUBREG)
2268 op = SUBREG_REG (op);
2270 switch (GET_CODE (op))
2276 return memory_address_p (DFmode, XEXP (op, 0));
2283 /* Return TRUE for valid index operands. */
2286 index_operand (op, mode)
2288 enum machine_mode mode;
2290 return (s_register_operand(op, mode)
2291 || (immediate_operand (op, mode)
2292 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2295 /* Return TRUE for valid shifts by a constant. This also accepts any
2296 power of two on the (somewhat overly relaxed) assumption that the
2297 shift operator in this case was a mult. */
2300 const_shift_operand (op, mode)
2302 enum machine_mode mode;
2304 return (power_of_two_operand (op, mode)
2305 || (immediate_operand (op, mode)
2306 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2309 /* Return TRUE for arithmetic operators which can be combined with a multiply
2313 shiftable_operator (x, mode)
2315 enum machine_mode mode;
2317 if (GET_MODE (x) != mode)
2321 enum rtx_code code = GET_CODE (x);
2323 return (code == PLUS || code == MINUS
2324 || code == IOR || code == XOR || code == AND);
2328 /* Return TRUE for shift operators. */
2331 shift_operator (x, mode)
2333 enum machine_mode mode;
2335 if (GET_MODE (x) != mode)
2339 enum rtx_code code = GET_CODE (x);
2342 return power_of_two_operand (XEXP (x, 1), mode);
2344 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2345 || code == ROTATERT);
2349 int equality_operator (x, mode)
2351 enum machine_mode mode ATTRIBUTE_UNUSED;
2353 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2356 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2359 minmax_operator (x, mode)
2361 enum machine_mode mode;
2363 enum rtx_code code = GET_CODE (x);
2365 if (GET_MODE (x) != mode)
2368 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2371 /* return TRUE if x is EQ or NE */
2373 /* Return TRUE if this is the condition code register, if we aren't given
2374 a mode, accept any class CCmode register */
2377 cc_register (x, mode)
2379 enum machine_mode mode;
2381 if (mode == VOIDmode)
2383 mode = GET_MODE (x);
2384 if (GET_MODE_CLASS (mode) != MODE_CC)
2388 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2394 /* Return TRUE if this is the condition code register, if we aren't given
2395 a mode, accept any class CCmode register which indicates a dominance
2399 dominant_cc_register (x, mode)
2401 enum machine_mode mode;
2403 if (mode == VOIDmode)
2405 mode = GET_MODE (x);
2406 if (GET_MODE_CLASS (mode) != MODE_CC)
2410 if (mode != CC_DNEmode && mode != CC_DEQmode
2411 && mode != CC_DLEmode && mode != CC_DLTmode
2412 && mode != CC_DGEmode && mode != CC_DGTmode
2413 && mode != CC_DLEUmode && mode != CC_DLTUmode
2414 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2417 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2423 /* Return TRUE if X references a SYMBOL_REF. */
2425 symbol_mentioned_p (x)
2428 register char * fmt;
2431 if (GET_CODE (x) == SYMBOL_REF)
2434 fmt = GET_RTX_FORMAT (GET_CODE (x));
2435 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2441 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2442 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2445 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2452 /* Return TRUE if X references a LABEL_REF. */
2454 label_mentioned_p (x)
2457 register char * fmt;
2460 if (GET_CODE (x) == LABEL_REF)
2463 fmt = GET_RTX_FORMAT (GET_CODE (x));
2464 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2470 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2471 if (label_mentioned_p (XVECEXP (x, i, j)))
2474 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2485 enum rtx_code code = GET_CODE (x);
2489 else if (code == SMIN)
2491 else if (code == UMIN)
2493 else if (code == UMAX)
2499 /* Return 1 if memory locations are adjacent */
2502 adjacent_mem_locations (a, b)
2505 int val0 = 0, val1 = 0;
2508 if ((GET_CODE (XEXP (a, 0)) == REG
2509 || (GET_CODE (XEXP (a, 0)) == PLUS
2510 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2511 && (GET_CODE (XEXP (b, 0)) == REG
2512 || (GET_CODE (XEXP (b, 0)) == PLUS
2513 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2515 if (GET_CODE (XEXP (a, 0)) == PLUS)
2517 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2518 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2521 reg0 = REGNO (XEXP (a, 0));
2522 if (GET_CODE (XEXP (b, 0)) == PLUS)
2524 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2525 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2528 reg1 = REGNO (XEXP (b, 0));
2529 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2534 /* Return 1 if OP is a load multiple operation. It is known to be
2535 parallel and the first section will be tested. */
2538 load_multiple_operation (op, mode)
2540 enum machine_mode mode ATTRIBUTE_UNUSED;
2542 HOST_WIDE_INT count = XVECLEN (op, 0);
2545 HOST_WIDE_INT i = 1, base = 0;
2549 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2552 /* Check to see if this might be a write-back */
2553 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2558 /* Now check it more carefully */
2559 if (GET_CODE (SET_DEST (elt)) != REG
2560 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2561 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2562 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2563 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2564 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2565 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2566 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2567 != REGNO (SET_DEST (elt)))
2573 /* Perform a quick check so we don't blow up below. */
2575 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2576 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2577 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2580 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2581 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2583 for (; i < count; i++)
2585 elt = XVECEXP (op, 0, i);
2587 if (GET_CODE (elt) != SET
2588 || GET_CODE (SET_DEST (elt)) != REG
2589 || GET_MODE (SET_DEST (elt)) != SImode
2590 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2591 || GET_CODE (SET_SRC (elt)) != MEM
2592 || GET_MODE (SET_SRC (elt)) != SImode
2593 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2594 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2595 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2596 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2603 /* Return 1 if OP is a store multiple operation. It is known to be
2604 parallel and the first section will be tested. */
2607 store_multiple_operation (op, mode)
2609 enum machine_mode mode ATTRIBUTE_UNUSED;
2611 HOST_WIDE_INT count = XVECLEN (op, 0);
2614 HOST_WIDE_INT i = 1, base = 0;
2618 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2621 /* Check to see if this might be a write-back */
2622 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2627 /* Now check it more carefully */
2628 if (GET_CODE (SET_DEST (elt)) != REG
2629 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2630 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2631 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2632 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2633 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2634 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2635 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2636 != REGNO (SET_DEST (elt)))
2642 /* Perform a quick check so we don't blow up below. */
2644 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2645 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2646 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2649 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2650 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2652 for (; i < count; i++)
2654 elt = XVECEXP (op, 0, i);
2656 if (GET_CODE (elt) != SET
2657 || GET_CODE (SET_SRC (elt)) != REG
2658 || GET_MODE (SET_SRC (elt)) != SImode
2659 || REGNO (SET_SRC (elt)) != src_regno + i - base
2660 || GET_CODE (SET_DEST (elt)) != MEM
2661 || GET_MODE (SET_DEST (elt)) != SImode
2662 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2663 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2664 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2665 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2673 load_multiple_sequence (operands, nops, regs, base, load_offset)
2678 HOST_WIDE_INT * load_offset;
2680 int unsorted_regs[4];
2681 HOST_WIDE_INT unsorted_offsets[4];
2686 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2687 extended if required. */
2688 if (nops < 2 || nops > 4)
2691 /* Loop over the operands and check that the memory references are
2692 suitable (ie immediate offsets from the same base register). At
2693 the same time, extract the target register, and the memory
2695 for (i = 0; i < nops; i++)
2700 /* Convert a subreg of a mem into the mem itself. */
2701 if (GET_CODE (operands[nops + i]) == SUBREG)
2702 operands[nops + i] = alter_subreg(operands[nops + i]);
2704 if (GET_CODE (operands[nops + i]) != MEM)
2707 /* Don't reorder volatile memory references; it doesn't seem worth
2708 looking for the case where the order is ok anyway. */
2709 if (MEM_VOLATILE_P (operands[nops + i]))
2712 offset = const0_rtx;
2714 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2715 || (GET_CODE (reg) == SUBREG
2716 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2717 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2718 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2720 || (GET_CODE (reg) == SUBREG
2721 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2722 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2727 base_reg = REGNO(reg);
2728 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2729 ? REGNO (operands[i])
2730 : REGNO (SUBREG_REG (operands[i])));
2735 if (base_reg != REGNO (reg))
2736 /* Not addressed from the same base register. */
2739 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2740 ? REGNO (operands[i])
2741 : REGNO (SUBREG_REG (operands[i])));
2742 if (unsorted_regs[i] < unsorted_regs[order[0]])
2746 /* If it isn't an integer register, or if it overwrites the
2747 base register but isn't the last insn in the list, then
2748 we can't do this. */
2749 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2750 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2753 unsorted_offsets[i] = INTVAL (offset);
2756 /* Not a suitable memory address. */
2760 /* All the useful information has now been extracted from the
2761 operands into unsorted_regs and unsorted_offsets; additionally,
2762 order[0] has been set to the lowest numbered register in the
2763 list. Sort the registers into order, and check that the memory
2764 offsets are ascending and adjacent. */
2766 for (i = 1; i < nops; i++)
2770 order[i] = order[i - 1];
2771 for (j = 0; j < nops; j++)
2772 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2773 && (order[i] == order[i - 1]
2774 || unsorted_regs[j] < unsorted_regs[order[i]]))
2777 /* Have we found a suitable register? if not, one must be used more
2779 if (order[i] == order[i - 1])
2782 /* Is the memory address adjacent and ascending? */
2783 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2791 for (i = 0; i < nops; i++)
2792 regs[i] = unsorted_regs[order[i]];
2794 *load_offset = unsorted_offsets[order[0]];
2797 if (unsorted_offsets[order[0]] == 0)
2798 return 1; /* ldmia */
2800 if (unsorted_offsets[order[0]] == 4)
2801 return 2; /* ldmib */
2803 if (unsorted_offsets[order[nops - 1]] == 0)
2804 return 3; /* ldmda */
2806 if (unsorted_offsets[order[nops - 1]] == -4)
2807 return 4; /* ldmdb */
2809 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
2810 if the offset isn't small enough. The reason 2 ldrs are faster
2811 is because these ARMs are able to do more than one cache access
2812 in a single cycle. The ARM9 and StrongARM have Harvard caches,
2813 whilst the ARM8 has a double bandwidth cache. This means that
2814 these cores can do both an instruction fetch and a data fetch in
2815 a single cycle, so the trick of calculating the address into a
2816 scratch register (one of the result regs) and then doing a load
2817 multiple actually becomes slower (and no smaller in code size).
2818 That is the transformation
2820 ldr rd1, [rbase + offset]
2821 ldr rd2, [rbase + offset + 4]
2825 add rd1, rbase, offset
2826 ldmia rd1, {rd1, rd2}
2828 produces worse code -- '3 cycles + any stalls on rd2' instead of
2829 '2 cycles + any stalls on rd2'. On ARMs with only one cache
2830 access per cycle, the first sequence could never complete in less
2831 than 6 cycles, whereas the ldm sequence would only take 5 and
2832 would make better use of sequential accesses if not hitting the
2835 We cheat here and test 'arm_ld_sched' which we currently know to
2836 only be true for the ARM8, ARM9 and StrongARM. If this ever
2837 changes, then the test below needs to be reworked. */
2838 if (nops == 2 && arm_ld_sched)
2841 /* Can't do it without setting up the offset, only do this if it takes
2842 no more than one insn. */
2843 return (const_ok_for_arm (unsorted_offsets[order[0]])
2844 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2848 emit_ldm_seq (operands, nops)
2854 HOST_WIDE_INT offset;
2858 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2861 strcpy (buf, "ldm%?ia\t");
2865 strcpy (buf, "ldm%?ib\t");
2869 strcpy (buf, "ldm%?da\t");
2873 strcpy (buf, "ldm%?db\t");
2878 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2879 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2882 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2883 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2885 output_asm_insn (buf, operands);
2887 strcpy (buf, "ldm%?ia\t");
2894 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2895 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2897 for (i = 1; i < nops; i++)
2898 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2899 reg_names[regs[i]]);
2901 strcat (buf, "}\t%@ phole ldm");
2903 output_asm_insn (buf, operands);
2908 store_multiple_sequence (operands, nops, regs, base, load_offset)
2913 HOST_WIDE_INT * load_offset;
2915 int unsorted_regs[4];
2916 HOST_WIDE_INT unsorted_offsets[4];
2921 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2922 extended if required. */
2923 if (nops < 2 || nops > 4)
2926 /* Loop over the operands and check that the memory references are
2927 suitable (ie immediate offsets from the same base register). At
2928 the same time, extract the target register, and the memory
2930 for (i = 0; i < nops; i++)
2935 /* Convert a subreg of a mem into the mem itself. */
2936 if (GET_CODE (operands[nops + i]) == SUBREG)
2937 operands[nops + i] = alter_subreg(operands[nops + i]);
2939 if (GET_CODE (operands[nops + i]) != MEM)
2942 /* Don't reorder volatile memory references; it doesn't seem worth
2943 looking for the case where the order is ok anyway. */
2944 if (MEM_VOLATILE_P (operands[nops + i]))
2947 offset = const0_rtx;
2949 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2950 || (GET_CODE (reg) == SUBREG
2951 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2952 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2953 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2955 || (GET_CODE (reg) == SUBREG
2956 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2957 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2962 base_reg = REGNO (reg);
2963 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2964 ? REGNO (operands[i])
2965 : REGNO (SUBREG_REG (operands[i])));
2970 if (base_reg != REGNO (reg))
2971 /* Not addressed from the same base register. */
2974 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2975 ? REGNO (operands[i])
2976 : REGNO (SUBREG_REG (operands[i])));
2977 if (unsorted_regs[i] < unsorted_regs[order[0]])
2981 /* If it isn't an integer register, then we can't do this. */
2982 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2985 unsorted_offsets[i] = INTVAL (offset);
2988 /* Not a suitable memory address. */
2992 /* All the useful information has now been extracted from the
2993 operands into unsorted_regs and unsorted_offsets; additionally,
2994 order[0] has been set to the lowest numbered register in the
2995 list. Sort the registers into order, and check that the memory
2996 offsets are ascending and adjacent. */
2998 for (i = 1; i < nops; i++)
3002 order[i] = order[i - 1];
3003 for (j = 0; j < nops; j++)
3004 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3005 && (order[i] == order[i - 1]
3006 || unsorted_regs[j] < unsorted_regs[order[i]]))
3009 /* Have we found a suitable register? if not, one must be used more
3011 if (order[i] == order[i - 1])
3014 /* Is the memory address adjacent and ascending? */
3015 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3023 for (i = 0; i < nops; i++)
3024 regs[i] = unsorted_regs[order[i]];
3026 *load_offset = unsorted_offsets[order[0]];
3029 if (unsorted_offsets[order[0]] == 0)
3030 return 1; /* stmia */
3032 if (unsorted_offsets[order[0]] == 4)
3033 return 2; /* stmib */
3035 if (unsorted_offsets[order[nops - 1]] == 0)
3036 return 3; /* stmda */
3038 if (unsorted_offsets[order[nops - 1]] == -4)
3039 return 4; /* stmdb */
3045 emit_stm_seq (operands, nops)
3051 HOST_WIDE_INT offset;
3055 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3058 strcpy (buf, "stm%?ia\t");
3062 strcpy (buf, "stm%?ib\t");
3066 strcpy (buf, "stm%?da\t");
3070 strcpy (buf, "stm%?db\t");
3077 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3078 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3080 for (i = 1; i < nops; i++)
3081 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3082 reg_names[regs[i]]);
3084 strcat (buf, "}\t%@ phole stm");
3086 output_asm_insn (buf, operands);
3091 multi_register_push (op, mode)
3093 enum machine_mode mode ATTRIBUTE_UNUSED;
3095 if (GET_CODE (op) != PARALLEL
3096 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
3097 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
3098 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
3105 /* Routines for use with attributes */
3107 /* Return nonzero if ATTR is a valid attribute for DECL.
3108 ATTRIBUTES are any existing attributes and ARGS are the arguments
3111 Supported attributes:
3113 naked: don't output any prologue or epilogue code, the user is assumed
3114 to do the right thing. */
3117 arm_valid_machine_decl_attribute (decl, attr, args)
3122 if (args != NULL_TREE)
3125 if (is_attribute_p ("naked", attr))
3126 return TREE_CODE (decl) == FUNCTION_DECL;
3130 /* Return non-zero if FUNC is a naked function. */
3133 arm_naked_function_p (func)
3138 if (TREE_CODE (func) != FUNCTION_DECL)
3141 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
3142 return a != NULL_TREE;
3145 /* Routines for use in generating RTL */
3148 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
3149 in_struct_p, scalar_p)
3161 int sign = up ? 1 : -1;
3164 result = gen_rtx_PARALLEL (VOIDmode,
3165 rtvec_alloc (count + (write_back ? 2 : 0)));
3168 XVECEXP (result, 0, 0)
3169 = gen_rtx_SET (GET_MODE (from), from,
3170 plus_constant (from, count * 4 * sign));
3175 for (j = 0; i < count; i++, j++)
3177 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
3178 RTX_UNCHANGING_P (mem) = unchanging_p;
3179 MEM_IN_STRUCT_P (mem) = in_struct_p;
3180 MEM_SCALAR_P (mem) = scalar_p;
3181 XVECEXP (result, 0, i)
3182 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
3186 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, from);
3192 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
3193 in_struct_p, scalar_p)
3205 int sign = up ? 1 : -1;
3208 result = gen_rtx_PARALLEL (VOIDmode,
3209 rtvec_alloc (count + (write_back ? 2 : 0)));
3212 XVECEXP (result, 0, 0)
3213 = gen_rtx_SET (GET_MODE (to), to,
3214 plus_constant (to, count * 4 * sign));
3219 for (j = 0; i < count; i++, j++)
3221 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
3222 RTX_UNCHANGING_P (mem) = unchanging_p;
3223 MEM_IN_STRUCT_P (mem) = in_struct_p;
3224 MEM_SCALAR_P (mem) = scalar_p;
3226 XVECEXP (result, 0, i)
3227 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
3231 XVECEXP (result, 0, i) = gen_rtx_CLOBBER (SImode, to);
3237 arm_gen_movstrqi (operands)
3240 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3243 rtx st_src, st_dst, fin_src, fin_dst;
3244 rtx part_bytes_reg = NULL;
3246 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3247 int dst_scalar_p, src_scalar_p;
3249 if (GET_CODE (operands[2]) != CONST_INT
3250 || GET_CODE (operands[3]) != CONST_INT
3251 || INTVAL (operands[2]) > 64
3252 || INTVAL (operands[3]) & 3)
3255 st_dst = XEXP (operands[0], 0);
3256 st_src = XEXP (operands[1], 0);
3258 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3259 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3260 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3261 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3262 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3263 src_scalar_p = MEM_SCALAR_P (operands[1]);
3265 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3266 fin_src = src = copy_to_mode_reg (SImode, st_src);
3268 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3269 out_words_to_go = INTVAL (operands[2]) / 4;
3270 last_bytes = INTVAL (operands[2]) & 3;
3272 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3273 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
3275 for (i = 0; in_words_to_go >= 2; i+=4)
3277 if (in_words_to_go > 4)
3278 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3283 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3284 FALSE, src_unchanging_p,
3285 src_in_struct_p, src_scalar_p));
3287 if (out_words_to_go)
3289 if (out_words_to_go > 4)
3290 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3294 else if (out_words_to_go != 1)
3295 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3304 mem = gen_rtx_MEM (SImode, dst);
3305 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3306 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3307 MEM_SCALAR_P (mem) = dst_scalar_p;
3308 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
3309 if (last_bytes != 0)
3310 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3314 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3315 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3318 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3319 if (out_words_to_go)
3323 mem = gen_rtx_MEM (SImode, src);
3324 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3325 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3326 MEM_SCALAR_P (mem) = src_scalar_p;
3327 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3328 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3330 mem = gen_rtx_MEM (SImode, dst);
3331 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3332 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3333 MEM_SCALAR_P (mem) = dst_scalar_p;
3334 emit_move_insn (mem, sreg);
3335 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3338 if (in_words_to_go) /* Sanity check */
3344 if (in_words_to_go < 0)
3347 mem = gen_rtx_MEM (SImode, src);
3348 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3349 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3350 MEM_SCALAR_P (mem) = src_scalar_p;
3351 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3354 if (BYTES_BIG_ENDIAN && last_bytes)
3356 rtx tmp = gen_reg_rtx (SImode);
3358 if (part_bytes_reg == NULL)
3361 /* The bytes we want are in the top end of the word */
3362 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3363 GEN_INT (8 * (4 - last_bytes))));
3364 part_bytes_reg = tmp;
3368 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
3369 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3370 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3371 MEM_SCALAR_P (mem) = dst_scalar_p;
3372 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3376 tmp = gen_reg_rtx (SImode);
3377 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3378 part_bytes_reg = tmp;
3387 if (part_bytes_reg == NULL)
3390 mem = gen_rtx_MEM (QImode, dst);
3391 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3392 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3393 MEM_SCALAR_P (mem) = dst_scalar_p;
3394 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
3398 rtx tmp = gen_reg_rtx (SImode);
3400 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3401 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3402 part_bytes_reg = tmp;
3410 /* Generate a memory reference for a half word, such that it will be loaded
3411 into the top 16 bits of the word. We can assume that the address is
3412 known to be alignable and of the form reg, or plus (reg, const). */
3414 gen_rotated_half_load (memref)
3417 HOST_WIDE_INT offset = 0;
3418 rtx base = XEXP (memref, 0);
3420 if (GET_CODE (base) == PLUS)
3422 offset = INTVAL (XEXP (base, 1));
3423 base = XEXP (base, 0);
3426 /* If we aren't allowed to generate unaligned addresses, then fail. */
3427 if (TARGET_SHORT_BY_BYTES
3428 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3431 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
3433 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3436 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
3439 static enum machine_mode
3440 select_dominance_cc_mode (x, y, cond_or)
3443 HOST_WIDE_INT cond_or;
3445 enum rtx_code cond1, cond2;
3448 /* Currently we will probably get the wrong result if the individual
3449 comparisons are not simple. This also ensures that it is safe to
3450 reverse a comparison if necessary. */
3451 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3453 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3458 cond1 = reverse_condition (cond1);
3460 /* If the comparisons are not equal, and one doesn't dominate the other,
3461 then we can't do this. */
3463 && ! comparison_dominates_p (cond1, cond2)
3464 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3469 enum rtx_code temp = cond1;
3477 if (cond2 == EQ || ! cond_or)
3482 case LE: return CC_DLEmode;
3483 case LEU: return CC_DLEUmode;
3484 case GE: return CC_DGEmode;
3485 case GEU: return CC_DGEUmode;
3492 if (cond2 == LT || ! cond_or)
3501 if (cond2 == GT || ! cond_or)
3510 if (cond2 == LTU || ! cond_or)
3519 if (cond2 == GTU || ! cond_or)
3527 /* The remaining cases only occur when both comparisons are the
3552 arm_select_cc_mode (op, x, y)
3557 /* All floating point compares return CCFP if it is an equality
3558 comparison, and CCFPE otherwise. */
3559 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3560 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3562 /* A compare with a shifted operand. Because of canonicalization, the
3563 comparison will have to be swapped when we emit the assembler. */
3564 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3565 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3566 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3567 || GET_CODE (x) == ROTATERT))
3570 /* This is a special case that is used by combine to allow a
3571 comparison of a shifted byte load to be split into a zero-extend
3572 followed by a comparison of the shifted integer (only valid for
3573 equalities and unsigned inequalities). */
3574 if (GET_MODE (x) == SImode
3575 && GET_CODE (x) == ASHIFT
3576 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3577 && GET_CODE (XEXP (x, 0)) == SUBREG
3578 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3579 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3580 && (op == EQ || op == NE
3581 || op == GEU || op == GTU || op == LTU || op == LEU)
3582 && GET_CODE (y) == CONST_INT)
3585 /* An operation that sets the condition codes as a side-effect, the
3586 V flag is not set correctly, so we can only use comparisons where
3587 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3589 if (GET_MODE (x) == SImode
3591 && (op == EQ || op == NE || op == LT || op == GE)
3592 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3593 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3594 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3595 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3596 || GET_CODE (x) == LSHIFTRT
3597 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3598 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3601 /* A construct for a conditional compare, if the false arm contains
3602 0, then both conditions must be true, otherwise either condition
3603 must be true. Not all conditions are possible, so CCmode is
3604 returned if it can't be done. */
3605 if (GET_CODE (x) == IF_THEN_ELSE
3606 && (XEXP (x, 2) == const0_rtx
3607 || XEXP (x, 2) == const1_rtx)
3608 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3609 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3610 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3611 INTVAL (XEXP (x, 2)));
3613 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3616 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3617 && GET_CODE (x) == PLUS
3618 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3624 /* X and Y are two things to compare using CODE. Emit the compare insn and
3625 return the rtx for register 0 in the proper mode. FP means this is a
3626 floating point compare: I don't think that it is needed on the arm. */
3629 gen_compare_reg (code, x, y)
3633 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3634 rtx cc_reg = gen_rtx_REG (mode, 24);
3636 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
3637 gen_rtx_COMPARE (mode, x, y)));
3643 arm_reload_in_hi (operands)
3646 rtx ref = operands[1];
3648 HOST_WIDE_INT offset = 0;
3650 if (GET_CODE (ref) == SUBREG)
3652 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3653 if (BYTES_BIG_ENDIAN)
3654 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3655 - MIN (UNITS_PER_WORD,
3656 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3657 ref = SUBREG_REG (ref);
3660 if (GET_CODE (ref) == REG)
3662 /* We have a pseudo which has been spilt onto the stack; there
3663 are two cases here: the first where there is a simple
3664 stack-slot replacement and a second where the stack-slot is
3665 out of range, or is used as a subreg. */
3666 if (reg_equiv_mem[REGNO (ref)])
3668 ref = reg_equiv_mem[REGNO (ref)];
3669 base = find_replacement (&XEXP (ref, 0));
3672 /* The slot is out of range, or was dressed up in a SUBREG */
3673 base = reg_equiv_address[REGNO (ref)];
3676 base = find_replacement (&XEXP (ref, 0));
3678 /* Handle the case where the address is too complex to be offset by 1. */
3679 if (GET_CODE (base) == MINUS
3680 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3682 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3684 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3687 else if (GET_CODE (base) == PLUS)
3689 /* The addend must be CONST_INT, or we would have dealt with it above */
3690 HOST_WIDE_INT hi, lo;
3692 offset += INTVAL (XEXP (base, 1));
3693 base = XEXP (base, 0);
3695 /* Rework the address into a legal sequence of insns */
3696 /* Valid range for lo is -4095 -> 4095 */
3699 : -((-offset) & 0xfff));
3701 /* Corner case, if lo is the max offset then we would be out of range
3702 once we have added the additional 1 below, so bump the msb into the
3703 pre-loading insn(s). */
3707 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3708 ^ (HOST_WIDE_INT) 0x80000000)
3709 - (HOST_WIDE_INT) 0x80000000);
3711 if (hi + lo != offset)
3716 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3718 /* Get the base address; addsi3 knows how to handle constants
3719 that require more than one insn */
3720 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3726 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3727 emit_insn (gen_zero_extendqisi2 (scratch,
3728 gen_rtx_MEM (QImode,
3729 plus_constant (base,
3731 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
3732 gen_rtx_MEM (QImode,
3733 plus_constant (base,
3735 if (! BYTES_BIG_ENDIAN)
3736 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3737 gen_rtx_IOR (SImode,
3740 gen_rtx_SUBREG (SImode, operands[0], 0),
3744 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
3745 gen_rtx_IOR (SImode,
3746 gen_rtx_ASHIFT (SImode, scratch,
3748 gen_rtx_SUBREG (SImode, operands[0],
3752 /* Handle storing a half-word to memory during reload by synthesising as two
3753 byte stores. Take care not to clobber the input values until after we
3754 have moved them somewhere safe. This code assumes that if the DImode
3755 scratch in operands[2] overlaps either the input value or output address
3756 in some way, then that value must die in this insn (we absolutely need
3757 two scratch registers for some corner cases). */
3759 arm_reload_out_hi (operands)
3762 rtx ref = operands[0];
3763 rtx outval = operands[1];
3765 HOST_WIDE_INT offset = 0;
3767 if (GET_CODE (ref) == SUBREG)
3769 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
3770 if (BYTES_BIG_ENDIAN)
3771 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
3772 - MIN (UNITS_PER_WORD,
3773 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
3774 ref = SUBREG_REG (ref);
3778 if (GET_CODE (ref) == REG)
3780 /* We have a pseudo which has been spilt onto the stack; there
3781 are two cases here: the first where there is a simple
3782 stack-slot replacement and a second where the stack-slot is
3783 out of range, or is used as a subreg. */
3784 if (reg_equiv_mem[REGNO (ref)])
3786 ref = reg_equiv_mem[REGNO (ref)];
3787 base = find_replacement (&XEXP (ref, 0));
3790 /* The slot is out of range, or was dressed up in a SUBREG */
3791 base = reg_equiv_address[REGNO (ref)];
3794 base = find_replacement (&XEXP (ref, 0));
3796 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
3798 /* Handle the case where the address is too complex to be offset by 1. */
3799 if (GET_CODE (base) == MINUS
3800 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3802 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3804 /* Be careful not to destroy OUTVAL. */
3805 if (reg_overlap_mentioned_p (base_plus, outval))
3807 /* Updating base_plus might destroy outval, see if we can
3808 swap the scratch and base_plus. */
3809 if (! reg_overlap_mentioned_p (scratch, outval))
3812 scratch = base_plus;
3817 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3819 /* Be conservative and copy OUTVAL into the scratch now,
3820 this should only be necessary if outval is a subreg
3821 of something larger than a word. */
3822 /* XXX Might this clobber base? I can't see how it can,
3823 since scratch is known to overlap with OUTVAL, and
3824 must be wider than a word. */
3825 emit_insn (gen_movhi (scratch_hi, outval));
3826 outval = scratch_hi;
3830 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
3833 else if (GET_CODE (base) == PLUS)
3835 /* The addend must be CONST_INT, or we would have dealt with it above */
3836 HOST_WIDE_INT hi, lo;
3838 offset += INTVAL (XEXP (base, 1));
3839 base = XEXP (base, 0);
3841 /* Rework the address into a legal sequence of insns */
3842 /* Valid range for lo is -4095 -> 4095 */
3845 : -((-offset) & 0xfff));
3847 /* Corner case, if lo is the max offset then we would be out of range
3848 once we have added the additional 1 below, so bump the msb into the
3849 pre-loading insn(s). */
3853 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFF)
3854 ^ (HOST_WIDE_INT) 0x80000000)
3855 - (HOST_WIDE_INT) 0x80000000);
3857 if (hi + lo != offset)
3862 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
3864 /* Be careful not to destroy OUTVAL. */
3865 if (reg_overlap_mentioned_p (base_plus, outval))
3867 /* Updating base_plus might destroy outval, see if we
3868 can swap the scratch and base_plus. */
3869 if (! reg_overlap_mentioned_p (scratch, outval))
3872 scratch = base_plus;
3877 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
3879 /* Be conservative and copy outval into scratch now,
3880 this should only be necessary if outval is a
3881 subreg of something larger than a word. */
3882 /* XXX Might this clobber base? I can't see how it
3883 can, since scratch is known to overlap with
3885 emit_insn (gen_movhi (scratch_hi, outval));
3886 outval = scratch_hi;
3890 /* Get the base address; addsi3 knows how to handle constants
3891 that require more than one insn */
3892 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
3898 if (BYTES_BIG_ENDIAN)
3900 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3901 plus_constant (base, offset + 1)),
3902 gen_rtx_SUBREG (QImode, outval, 0)));
3903 emit_insn (gen_lshrsi3 (scratch,
3904 gen_rtx_SUBREG (SImode, outval, 0),
3906 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3907 gen_rtx_SUBREG (QImode, scratch, 0)));
3911 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
3912 gen_rtx_SUBREG (QImode, outval, 0)));
3913 emit_insn (gen_lshrsi3 (scratch,
3914 gen_rtx_SUBREG (SImode, outval, 0),
3916 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
3917 plus_constant (base, offset + 1)),
3918 gen_rtx_SUBREG (QImode, scratch, 0)));
3922 /* Routines for manipulation of the constant pool. */
3924 /* Arm instructions cannot load a large constant directly into a
3925 register; they have to come from a pc relative load. The constant
3926 must therefore be placed in the addressable range of the pc
3927 relative load. Depending on the precise pc relative load
3928 instruction the range is somewhere between 256 bytes and 4k. This
3929 means that we often have to dump a constant inside a function, and
3930 generate code to branch around it.
3932 It is important to minimize this, since the branches will slow
3933 things down and make the code larger.
3935 Normally we can hide the table after an existing unconditional
3936 branch so that there is no interruption of the flow, but in the
3937 worst case the code looks like this:
3955 We fix this by performing a scan after scheduling, which notices
3956 which instructions need to have their operands fetched from the
3957 constant table and builds the table.
3959 The algorithm starts by building a table of all the constants that
3960 need fixing up and all the natural barriers in the function (places
3961 where a constant table can be dropped without breaking the flow).
3962 For each fixup we note how far the pc-relative replacement will be
3963 able to reach and the offset of the instruction into the function.
3965 Having built the table we then group the fixes together to form
3966 tables that are as large as possible (subject to addressing
3967 constraints) and emit each table of constants after the last
3968 barrier that is within range of all the instructions in the group.
3969 If a group does not contain a barrier, then we forcibly create one
3970 by inserting a jump instruction into the flow. Once the table has
3971 been inserted, the insns are then modified to reference the
3972 relevant entry in the pool.
3974 Possible enhancements to the alogorithm (not implemented) are:
3976 1) ARM instructions (but not thumb) can use negative offsets, so we
3977 could reference back to a previous pool rather than forwards to a
3978 new one. For large functions this may reduce the number of pools
3981 2) For some processors and object formats, there may be benefit in
3982 aligning the pools to the start of cache lines; this alignment
3983 would need to be taken into account when calculating addressability
3990 rtx value; /* Value in table */
3991 HOST_WIDE_INT next_offset;
3992 enum machine_mode mode; /* Mode of value */
3995 /* The maximum number of constants that can fit into one pool, since
3996 the pc relative range is 0...4092 bytes and constants are at least 4
3999 #define MAX_MINIPOOL_SIZE (4092/4)
4000 static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
4001 static int minipool_size;
4002 static rtx minipool_vector_label;
4004 /* Add a constant to the pool and return its offset within the current
4007 X is the rtx we want to replace. MODE is its mode. On return,
4008 ADDRESS_ONLY will be non-zero if we really want the address of such
4009 a constant, not the constant itself. */
4010 static HOST_WIDE_INT
4011 add_minipool_constant (x, mode)
4013 enum machine_mode mode;
4016 HOST_WIDE_INT offset;
4018 /* First, see if we've already got it. */
4019 for (i = 0; i < minipool_size; i++)
4021 if (GET_CODE (x) == minipool_vector[i].value->code
4022 && mode == minipool_vector[i].mode)
4024 if (GET_CODE (x) == CODE_LABEL)
4026 if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
4029 if (rtx_equal_p (x, minipool_vector[i].value))
4030 return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
4034 /* Need a new one */
4035 minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
4037 if (minipool_size == 0)
4038 minipool_vector_label = gen_label_rtx ();
4040 minipool_vector[minipool_size].next_offset
4041 += (offset = minipool_vector[minipool_size - 1].next_offset);
4043 minipool_vector[minipool_size].value = x;
4044 minipool_vector[minipool_size].mode = mode;
4049 /* Output the literal table */
4051 dump_minipool (scan)
4056 scan = emit_label_after (gen_label_rtx (), scan);
4057 scan = emit_insn_after (gen_align_4 (), scan);
4058 scan = emit_label_after (minipool_vector_label, scan);
4060 for (i = 0; i < minipool_size; i++)
4062 minipool_node *p = minipool_vector + i;
4064 switch (GET_MODE_SIZE (p->mode))
4067 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
4071 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
4080 scan = emit_insn_after (gen_consttable_end (), scan);
4081 scan = emit_barrier_after (scan);
4085 /* Find the last barrier less than MAX_COUNT bytes from FROM, or
4088 find_barrier (from, max_count)
4093 rtx found_barrier = 0;
4096 while (from && count < max_count)
4100 if (GET_CODE (from) == BARRIER)
4101 found_barrier = from;
4103 /* Count the length of this insn */
4104 if (GET_CODE (from) == JUMP_INSN
4105 && JUMP_LABEL (from) != 0
4106 && ((tmp = next_real_insn (JUMP_LABEL (from)))
4107 == next_real_insn (from))
4109 && GET_CODE (tmp) == JUMP_INSN
4110 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
4111 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
4113 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
4114 count += (get_attr_length (from)
4115 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
4116 /* Continue after the dispatch table. */
4118 from = NEXT_INSN (tmp);
4122 count += get_attr_length (from);
4125 from = NEXT_INSN (from);
4128 if (! found_barrier)
4130 /* We didn't find a barrier in time to
4131 dump our stuff, so we'll make one. */
4132 rtx label = gen_label_rtx ();
4135 from = PREV_INSN (last);
4137 from = get_last_insn ();
4139 /* Walk back to be just before any jump. */
4140 while (GET_CODE (from) == JUMP_INSN
4141 || GET_CODE (from) == NOTE
4142 || GET_CODE (from) == CODE_LABEL)
4143 from = PREV_INSN (from);
4145 from = emit_jump_insn_after (gen_jump (label), from);
4146 JUMP_LABEL (from) = label;
4147 found_barrier = emit_barrier_after (from);
4148 emit_label_after (label, found_barrier);
4151 return found_barrier;
4154 struct minipool_fixup
4156 struct minipool_fixup *next;
4160 enum machine_mode mode;
4165 struct minipool_fixup *minipool_fix_head;
4166 struct minipool_fixup *minipool_fix_tail;
4169 push_minipool_barrier (insn, address)
4173 struct minipool_fixup *fix
4174 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4177 fix->address = address;
4180 if (minipool_fix_head != NULL)
4181 minipool_fix_tail->next = fix;
4183 minipool_fix_head = fix;
4185 minipool_fix_tail = fix;
4189 push_minipool_fix (insn, address, loc, mode, value)
4193 enum machine_mode mode;
4196 struct minipool_fixup *fix
4197 = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
4199 #ifdef AOF_ASSEMBLER
4200 /* PIC symbol refereneces need to be converted into offsets into the
4202 if (flag_pic && GET_MODE == SYMBOL_REF)
4203 value = aof_pic_entry (value);
4204 #endif /* AOF_ASSEMBLER */
4207 fix->address = address;
4211 fix->range = get_attr_pool_range (insn);
4213 /* If an insn doesn't have a range defined for it, then it isn't
4214 expecting to be reworked by this code. Better to abort now than
4215 to generate duff assembly code. */
4216 if (fix->range == 0)
4219 /* Add it to the chain of fixes */
4221 if (minipool_fix_head != NULL)
4222 minipool_fix_tail->next = fix;
4224 minipool_fix_head = fix;
4226 minipool_fix_tail = fix;
4230 note_invalid_constants (insn, address)
4236 /* Extract the operands of the insn */
4239 /* If this is an asm, we can't do anything about it (or can we?) */
4240 if (INSN_CODE (insn) < 0)
4243 /* Find the alternative selected */
4244 if (! constrain_operands (1))
4245 fatal_insn_not_found (insn);
4247 /* Preprocess the constraints, to extract some useful information. */
4248 preprocess_constraints ();
4250 for (opno = 0; opno < recog_n_operands; opno++)
4252 /* Things we need to fix can only occur in inputs */
4253 if (recog_op_type[opno] != OP_IN)
4256 /* If this alternative is a memory reference, then any mention
4257 of constants in this alternative is really to fool reload
4258 into allowing us to accept one there. We need to fix them up
4259 now so that we output the right code. */
4260 if (recog_op_alt[opno][which_alternative].memory_ok)
4262 rtx op = recog_operand[opno];
4264 if (CONSTANT_P (op))
4265 push_minipool_fix (insn, address, recog_operand_loc[opno],
4266 recog_operand_mode[opno], op);
4267 #ifndef AOF_ASSEMBLER
4268 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
4269 push_minipool_fix (insn, address, recog_operand_loc[opno],
4270 recog_operand_mode[opno], XVECEXP (op, 0, 0));
4272 else if (recog_operand_mode[opno] == SImode
4273 && GET_CODE (op) == MEM
4274 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
4275 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4276 push_minipool_fix (insn, address, recog_operand_loc[opno],
4277 recog_operand_mode[opno],
4278 get_pool_constant (XEXP (op, 0)));
4289 struct minipool_fixup *fix;
4291 minipool_fix_head = minipool_fix_tail = NULL;
4293 /* The first insn must always be a note, or the code below won't
4294 scan it properly. */
4295 if (GET_CODE (first) != NOTE)
4298 /* Scan all the insns and record the operands that will need fixing. */
4299 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
4302 if (GET_CODE (insn) == BARRIER)
4303 push_minipool_barrier(insn, address);
4304 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
4305 || GET_CODE (insn) == JUMP_INSN)
4309 note_invalid_constants (insn, address);
4310 address += get_attr_length (insn);
4311 /* If the insn is a vector jump, add the size of the table
4312 and skip the table. */
4313 if (GET_CODE (insn) == JUMP_INSN
4314 && JUMP_LABEL (insn) != NULL
4315 && ((table = next_real_insn (JUMP_LABEL (insn)))
4316 == next_real_insn (insn))
4318 && GET_CODE (table) == JUMP_INSN
4319 && (GET_CODE (PATTERN (table)) == ADDR_VEC
4320 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
4322 int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
4324 address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
4331 /* Now scan the fixups and perform the required changes. */
4332 for (fix = minipool_fix_head; fix; fix = fix->next)
4334 struct minipool_fixup *ftmp;
4335 struct minipool_fixup *last_barrier = NULL;
4338 struct minipool_fixup *this_fix;
4339 int new_minipool_size = 0;
4341 /* Skip any further barriers before the next fix. */
4342 while (fix && GET_CODE (fix->insn) == BARRIER)
4349 max_range = fix->address + fix->range;
4351 /* Find all the other fixes that can live in the same pool. */
4352 while (ftmp->next && ftmp->next->address < max_range
4353 && (GET_CODE (ftmp->next->insn) == BARRIER
4354 /* Ensure we can reach the constant inside the pool. */
4355 || ftmp->next->range > new_minipool_size))
4358 if (GET_CODE (ftmp->insn) == BARRIER)
4359 last_barrier = ftmp;
4362 /* Does this fix constrain the range we can search? */
4363 if (ftmp->address + ftmp->range - new_minipool_size < max_range)
4364 max_range = ftmp->address + ftmp->range - new_minipool_size;
4366 new_minipool_size += GET_MODE_SIZE (ftmp->mode);
4370 /* If we found a barrier, drop back to that; any fixes that we could
4371 have reached but come after the barrier will now go in the next
4373 if (last_barrier != NULL)
4375 barrier = last_barrier->insn;
4376 ftmp = last_barrier;
4379 /* ftmp is last fix that we can fit into this pool and we
4380 failed to find a barrier that we could use. Insert a new
4381 barrier in the code and arrange to jump around it. */
4382 barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
4384 /* Scan over the fixes we have identified for this pool, fixing them
4385 up and adding the constants to the pool itself. */
4386 for (this_fix = fix; this_fix && ftmp->next != this_fix;
4387 this_fix = this_fix->next)
4388 if (GET_CODE (this_fix->insn) != BARRIER)
4390 int offset = add_minipool_constant (this_fix->value,
4393 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
4394 minipool_vector_label),
4396 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
4399 dump_minipool (barrier);
4403 /* From now on we must synthesize any constants that we can't handle
4404 directly. This can happen if the RTL gets split during final
4405 instruction generation. */
4406 after_arm_reorg = 1;
4410 /* Routines to output assembly language. */
4412 /* If the rtx is the correct value then return the string of the number.
4413 In this way we can ensure that valid double constants are generated even
4414 when cross compiling. */
4416 fp_immediate_constant (x)
4422 if (!fpa_consts_inited)
4425 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4426 for (i = 0; i < 8; i++)
4427 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
4428 return strings_fpa[i];
4433 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
4435 fp_const_from_val (r)
4436 REAL_VALUE_TYPE * r;
4440 if (! fpa_consts_inited)
4443 for (i = 0; i < 8; i++)
4444 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
4445 return strings_fpa[i];
4450 /* Output the operands of a LDM/STM instruction to STREAM.
4451 MASK is the ARM register set mask of which only bits 0-15 are important.
4452 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
4453 must follow the register list. */
4456 print_multi_reg (stream, instr, reg, mask, hat)
4464 int not_first = FALSE;
4466 fputc ('\t', stream);
4467 asm_fprintf (stream, instr, reg);
4468 fputs (", {", stream);
4470 for (i = 0; i < 16; i++)
4471 if (mask & (1 << i))
4474 fprintf (stream, ", ");
4476 asm_fprintf (stream, "%r", i);
4480 fprintf (stream, "}%s\n", hat ? "^" : "");
4483 /* Output a 'call' insn. */
4486 output_call (operands)
4489 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
4491 if (REGNO (operands[0]) == LR_REGNUM)
4493 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
4494 output_asm_insn ("mov%?\t%0, %|lr", operands);
4497 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4499 if (TARGET_INTERWORK)
4500 output_asm_insn ("bx%?\t%0", operands);
4502 output_asm_insn ("mov%?\t%|pc, %0", operands);
4511 int something_changed = 0;
4513 int code = GET_CODE (x0);
4515 register char * fmt;
4520 if (REGNO (x0) == LR_REGNUM)
4522 *x = gen_rtx_REG (SImode, IP_REGNUM);
4527 /* Scan through the sub-elements and change any references there */
4528 fmt = GET_RTX_FORMAT (code);
4530 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4532 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4533 else if (fmt[i] == 'E')
4534 for (j = 0; j < XVECLEN (x0, i); j++)
4535 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4537 return something_changed;
4541 /* Output a 'call' insn that is a reference in memory. */
4544 output_call_mem (operands)
4547 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4548 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4550 if (eliminate_lr2ip (&operands[0]))
4551 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4553 if (TARGET_INTERWORK)
4555 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4556 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4557 output_asm_insn ("bx%?\t%|ip", operands);
4561 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4562 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4569 /* Output a move from arm registers to an fpu registers.
4570 OPERANDS[0] is an fpu register.
4571 OPERANDS[1] is the first registers of an arm register pair. */
4574 output_mov_long_double_fpu_from_arm (operands)
4577 int arm_reg0 = REGNO (operands[1]);
4580 if (arm_reg0 == IP_REGNUM)
4583 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4584 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4585 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4587 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4588 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4593 /* Output a move from an fpu register to arm registers.
4594 OPERANDS[0] is the first registers of an arm register pair.
4595 OPERANDS[1] is an fpu register. */
4598 output_mov_long_double_arm_from_fpu (operands)
4601 int arm_reg0 = REGNO (operands[0]);
4604 if (arm_reg0 == IP_REGNUM)
4607 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4608 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4609 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
4611 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4612 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4616 /* Output a move from arm registers to arm registers of a long double
4617 OPERANDS[0] is the destination.
4618 OPERANDS[1] is the source. */
4620 output_mov_long_double_arm_from_arm (operands)
4623 /* We have to be careful here because the two might overlap */
4624 int dest_start = REGNO (operands[0]);
4625 int src_start = REGNO (operands[1]);
4629 if (dest_start < src_start)
4631 for (i = 0; i < 3; i++)
4633 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4634 ops[1] = gen_rtx_REG (SImode, src_start + i);
4635 output_asm_insn ("mov%?\t%0, %1", ops);
4640 for (i = 2; i >= 0; i--)
4642 ops[0] = gen_rtx_REG (SImode, dest_start + i);
4643 ops[1] = gen_rtx_REG (SImode, src_start + i);
4644 output_asm_insn ("mov%?\t%0, %1", ops);
4652 /* Output a move from arm registers to an fpu registers.
4653 OPERANDS[0] is an fpu register.
4654 OPERANDS[1] is the first registers of an arm register pair. */
4657 output_mov_double_fpu_from_arm (operands)
4660 int arm_reg0 = REGNO (operands[1]);
4663 if (arm_reg0 == IP_REGNUM)
4666 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4667 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4668 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4669 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4673 /* Output a move from an fpu register to arm registers.
4674 OPERANDS[0] is the first registers of an arm register pair.
4675 OPERANDS[1] is an fpu register. */
4678 output_mov_double_arm_from_fpu (operands)
4681 int arm_reg0 = REGNO (operands[0]);
4684 if (arm_reg0 == IP_REGNUM)
4687 ops[0] = gen_rtx_REG (SImode, arm_reg0);
4688 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
4689 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4690 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4694 /* Output a move between double words.
4695 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4696 or MEM<-REG and all MEMs must be offsettable addresses. */
4699 output_move_double (operands)
4702 enum rtx_code code0 = GET_CODE (operands[0]);
4703 enum rtx_code code1 = GET_CODE (operands[1]);
4708 int reg0 = REGNO (operands[0]);
4710 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
4714 int reg1 = REGNO (operands[1]);
4715 if (reg1 == IP_REGNUM)
4718 /* Ensure the second source is not overwritten */
4719 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4720 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4722 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4724 else if (code1 == CONST_DOUBLE)
4726 if (GET_MODE (operands[1]) == DFmode)
4729 union real_extract u;
4731 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4733 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4734 otherops[1] = GEN_INT(l[1]);
4735 operands[1] = GEN_INT(l[0]);
4737 else if (GET_MODE (operands[1]) != VOIDmode)
4739 else if (WORDS_BIG_ENDIAN)
4742 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4743 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4748 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4749 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4752 output_mov_immediate (operands);
4753 output_mov_immediate (otherops);
4755 else if (code1 == CONST_INT)
4757 #if HOST_BITS_PER_WIDE_INT > 32
4758 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4759 what the upper word is. */
4760 if (WORDS_BIG_ENDIAN)
4762 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4763 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4767 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4768 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4771 /* Sign extend the intval into the high-order word */
4772 if (WORDS_BIG_ENDIAN)
4774 otherops[1] = operands[1];
4775 operands[1] = (INTVAL (operands[1]) < 0
4776 ? constm1_rtx : const0_rtx);
4779 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4781 output_mov_immediate (otherops);
4782 output_mov_immediate (operands);
4784 else if (code1 == MEM)
4786 switch (GET_CODE (XEXP (operands[1], 0)))
4789 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4793 abort (); /* Should never happen now */
4797 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4801 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4805 abort (); /* Should never happen now */
4810 output_asm_insn ("adr%?\t%0, %1", operands);
4811 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4815 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
4816 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
4818 otherops[0] = operands[0];
4819 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4820 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4821 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4823 if (GET_CODE (otherops[2]) == CONST_INT)
4825 switch (INTVAL (otherops[2]))
4828 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4831 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4834 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4837 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4838 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4840 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4843 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4846 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4848 return "ldm%?ia\t%0, %M0";
4852 otherops[1] = adj_offsettable_operand (operands[1], 4);
4853 /* Take care of overlapping base/data reg. */
4854 if (reg_mentioned_p (operands[0], operands[1]))
4856 output_asm_insn ("ldr%?\t%0, %1", otherops);
4857 output_asm_insn ("ldr%?\t%0, %1", operands);
4861 output_asm_insn ("ldr%?\t%0, %1", operands);
4862 output_asm_insn ("ldr%?\t%0, %1", otherops);
4868 abort (); /* Constraints should prevent this */
4870 else if (code0 == MEM && code1 == REG)
4872 if (REGNO (operands[1]) == IP_REGNUM)
4875 switch (GET_CODE (XEXP (operands[0], 0)))
4878 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4882 abort (); /* Should never happen now */
4886 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4890 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4894 abort (); /* Should never happen now */
4898 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4900 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4903 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4907 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4911 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4918 otherops[0] = adj_offsettable_operand (operands[0], 4);
4919 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
4920 output_asm_insn ("str%?\t%1, %0", operands);
4921 output_asm_insn ("str%?\t%1, %0", otherops);
4925 abort (); /* Constraints should prevent this */
4931 /* Output an arbitrary MOV reg, #n.
4932 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4935 output_mov_immediate (operands)
4938 HOST_WIDE_INT n = INTVAL (operands[1]);
4942 /* Try to use one MOV */
4943 if (const_ok_for_arm (n))
4945 output_asm_insn ("mov%?\t%0, %1", operands);
4949 /* Try to use one MVN */
4950 if (const_ok_for_arm (~n))
4952 operands[1] = GEN_INT (~n);
4953 output_asm_insn ("mvn%?\t%0, %1", operands);
4957 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4959 for (i=0; i < 32; i++)
4963 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4964 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4967 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4974 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4975 adding zero to one register, output nothing. */
4978 output_add_immediate (operands)
4981 HOST_WIDE_INT n = INTVAL (operands[2]);
4983 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4986 output_multi_immediate (operands,
4987 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4990 output_multi_immediate (operands,
4991 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4998 /* Output a multiple immediate operation.
4999 OPERANDS is the vector of operands referred to in the output patterns.
5000 INSTR1 is the output pattern to use for the first constant.
5001 INSTR2 is the output pattern to use for subsequent constants.
5002 IMMED_OP is the index of the constant slot in OPERANDS.
5003 N is the constant value. */
5006 output_multi_immediate (operands, instr1, instr2, immed_op, n)
5008 char * instr1, * instr2;
5012 #if HOST_BITS_PER_WIDE_INT > 32
5018 operands[immed_op] = const0_rtx;
5019 output_asm_insn (instr1, operands); /* Quick and easy output */
5024 char *instr = instr1;
5026 /* Note that n is never zero here (which would give no output) */
5027 for (i = 0; i < 32; i += 2)
5031 operands[immed_op] = GEN_INT (n & (255 << i));
5032 output_asm_insn (instr, operands);
5042 /* Return the appropriate ARM instruction for the operation code.
5043 The returned result should not be overwritten. OP is the rtx of the
5044 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
5048 arithmetic_instr (op, shift_first_arg)
5050 int shift_first_arg;
5052 switch (GET_CODE (op))
5058 return shift_first_arg ? "rsb" : "sub";
5075 /* Ensure valid constant shifts and return the appropriate shift mnemonic
5076 for the operation code. The returned result should not be overwritten.
5077 OP is the rtx code of the shift.
5078 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
5082 shift_op (op, amountp)
5084 HOST_WIDE_INT *amountp;
5087 enum rtx_code code = GET_CODE (op);
5089 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
5091 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
5092 *amountp = INTVAL (XEXP (op, 1));
5115 /* We never have to worry about the amount being other than a
5116 power of 2, since this case can never be reloaded from a reg. */
5118 *amountp = int_log2 (*amountp);
5129 /* This is not 100% correct, but follows from the desire to merge
5130 multiplication by a power of 2 with the recognizer for a
5131 shift. >=32 is not a valid shift for "asl", so we must try and
5132 output a shift that produces the correct arithmetical result.
5133 Using lsr #32 is identical except for the fact that the carry bit
5134 is not set correctly if we set the flags; but we never use the
5135 carry bit from such an operation, so we can ignore that. */
5136 if (code == ROTATERT)
5137 *amountp &= 31; /* Rotate is just modulo 32 */
5138 else if (*amountp != (*amountp & 31))
5145 /* Shifts of 0 are no-ops. */
5154 /* Obtain the shift from the POWER of two. */
5156 static HOST_WIDE_INT
5158 HOST_WIDE_INT power;
5160 HOST_WIDE_INT shift = 0;
5162 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
5172 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
5173 /bin/as is horribly restrictive. */
5174 #define MAX_ASCII_LEN 51
5177 output_ascii_pseudo_op (stream, p, len)
5185 fputs ("\t.ascii\t\"", stream);
5187 for (i = 0; i < len; i++)
5189 register int c = p[i];
5191 if (len_so_far >= MAX_ASCII_LEN)
5193 fputs ("\"\n\t.ascii\t\"", stream);
5200 fputs ("\\t", stream);
5205 fputs ("\\f", stream);
5210 fputs ("\\b", stream);
5215 fputs ("\\r", stream);
5219 case TARGET_NEWLINE:
5220 fputs ("\\n", stream);
5222 if ((c >= ' ' && c <= '~')
5224 /* This is a good place for a line break. */
5225 len_so_far = MAX_ASCII_LEN;
5232 putc ('\\', stream);
5237 if (c >= ' ' && c <= '~')
5244 fprintf (stream, "\\%03o", c);
5251 fputs ("\"\n", stream);
5255 /* Try to determine whether a pattern really clobbers the link register.
5256 This information is useful when peepholing, so that lr need not be pushed
5257 if we combine a call followed by a return.
5258 NOTE: This code does not check for side-effect expressions in a SET_SRC:
5259 such a check should not be needed because these only update an existing
5260 value within a register; the register must still be set elsewhere within
5264 pattern_really_clobbers_lr (x)
5269 switch (GET_CODE (x))
5272 switch (GET_CODE (SET_DEST (x)))
5275 return REGNO (SET_DEST (x)) == LR_REGNUM;
5278 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
5279 return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
5281 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
5290 for (i = 0; i < XVECLEN (x, 0); i++)
5291 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
5296 switch (GET_CODE (XEXP (x, 0)))
5299 return REGNO (XEXP (x, 0)) == LR_REGNUM;
5302 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
5303 return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
5319 function_really_clobbers_lr (first)
5324 for (insn = first; insn; insn = next_nonnote_insn (insn))
5326 switch (GET_CODE (insn))
5331 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
5336 if (pattern_really_clobbers_lr (PATTERN (insn)))
5341 /* Don't yet know how to handle those calls that are not to a
5343 if (GET_CODE (PATTERN (insn)) != PARALLEL)
5346 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
5349 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
5355 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
5361 default: /* Don't recognize it, be safe */
5365 /* A call can be made (by peepholing) not to clobber lr iff it is
5366 followed by a return. There may, however, be a use insn iff
5367 we are returning the result of the call.
5368 If we run off the end of the insn chain, then that means the
5369 call was at the end of the function. Unfortunately we don't
5370 have a return insn for the peephole to recognize, so we
5371 must reject this. (Can this be fixed by adding our own insn?) */
5372 if ((next = next_nonnote_insn (insn)) == NULL)
5375 /* No need to worry about lr if the call never returns */
5376 if (GET_CODE (next) == BARRIER)
5379 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
5380 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
5381 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
5382 == REGNO (XEXP (PATTERN (next), 0))))
5383 if ((next = next_nonnote_insn (next)) == NULL)
5386 if (GET_CODE (next) == JUMP_INSN
5387 && GET_CODE (PATTERN (next)) == RETURN)
5396 /* We have reached the end of the chain so lr was _not_ clobbered */
5401 output_return_instruction (operand, really_return, reverse)
5407 int reg, live_regs = 0;
5408 int volatile_func = (optimize > 0
5409 && TREE_THIS_VOLATILE (current_function_decl));
5411 return_used_this_function = 1;
5413 if (TARGET_ABORT_NORETURN && volatile_func)
5416 /* If this function was declared non-returning, and we have found a tail
5417 call, then we have to trust that the called function won't return. */
5418 if (! really_return)
5421 /* Otherwise, trap an attempted return by aborting. */
5423 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
5425 assemble_external_libcall (ops[1]);
5426 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
5430 if (current_function_calls_alloca && ! really_return)
5433 for (reg = 0; reg <= 10; reg++)
5434 if (regs_ever_live[reg] && ! call_used_regs[reg])
5437 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5438 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5441 if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
5444 if (frame_pointer_needed)
5449 if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
5452 if (frame_pointer_needed)
5454 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
5457 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
5459 for (reg = 0; reg <= 10; reg++)
5460 if (regs_ever_live[reg]
5461 && (! call_used_regs[reg]
5462 || (flag_pic && ! TARGET_SINGLE_PIC_BASE
5463 && reg == PIC_OFFSET_TABLE_REGNUM)))
5465 strcat (instr, "%|");
5466 strcat (instr, reg_names[reg]);
5468 strcat (instr, ", ");
5471 if (frame_pointer_needed)
5473 strcat (instr, "%|");
5474 strcat (instr, reg_names[11]);
5475 strcat (instr, ", ");
5476 strcat (instr, "%|");
5477 strcat (instr, reg_names[13]);
5478 strcat (instr, ", ");
5479 strcat (instr, "%|");
5480 strcat (instr, TARGET_INTERWORK || (! really_return)
5481 ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
5485 strcat (instr, "%|");
5486 if (TARGET_INTERWORK && really_return)
5487 strcat (instr, reg_names[IP_REGNUM]);
5489 strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
5491 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
5492 output_asm_insn (instr, &operand);
5494 if (TARGET_INTERWORK && really_return)
5496 strcpy (instr, "bx%?");
5497 strcat (instr, reverse ? "%D0" : "%d0");
5498 strcat (instr, "\t%|");
5499 strcat (instr, frame_pointer_needed ? "lr" : "ip");
5501 output_asm_insn (instr, & operand);
5504 else if (really_return)
5506 if (TARGET_INTERWORK)
5507 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
5509 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
5510 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
5512 output_asm_insn (instr, & operand);
5518 /* Return nonzero if optimizing and the current function is volatile.
5519 Such functions never return, and many memory cycles can be saved
5520 by not storing register values that will never be needed again.
5521 This optimization was added to speed up context switching in a
5522 kernel application. */
5525 arm_volatile_func ()
5527 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
5530 /* Write the function name into the code section, directly preceding
5531 the function prologue.
5533 Code will be output similar to this:
5535 .ascii "arm_poke_function_name", 0
5538 .word 0xff000000 + (t1 - t0)
5539 arm_poke_function_name
5541 stmfd sp!, {fp, ip, lr, pc}
5544 When performing a stack backtrace, code can inspect the value
5545 of 'pc' stored at 'fp' + 0. If the trace function then looks
5546 at location pc - 12 and the top 8 bits are set, then we know
5547 that there is a function name embedded immediately preceding this
5548 location and has length ((pc[-3]) & 0xff000000).
5550 We assume that pc is declared as a pointer to an unsigned long.
5552 It is of no benefit to output the function name if we are assembling
5553 a leaf function. These function types will not contain a stack
5554 backtrace structure, therefore it is not possible to determine the
5558 arm_poke_function_name (stream, name)
5562 unsigned long alignlength;
5563 unsigned long length;
5566 length = strlen (name) + 1;
5567 alignlength = (length + 3) & ~3;
5569 ASM_OUTPUT_ASCII (stream, name, length);
5570 ASM_OUTPUT_ALIGN (stream, 2);
5571 x = GEN_INT (0xff000000UL + alignlength);
5572 ASM_OUTPUT_INT (stream, x);
5575 /* The amount of stack adjustment that happens here, in output_return and in
5576 output_epilogue must be exactly the same as was calculated during reload,
5577 or things will point to the wrong place. The only time we can safely
5578 ignore this constraint is when a function has no arguments on the stack,
5579 no stack frame requirement and no live registers execpt for `lr'. If we
5580 can guarantee that by making all function calls into tail calls and that
5581 lr is not clobbered in any other way, then there is no need to push lr
5585 output_func_prologue (f, frame_size)
5589 int reg, live_regs_mask = 0;
5590 int volatile_func = (optimize > 0
5591 && TREE_THIS_VOLATILE (current_function_decl));
5593 /* Nonzero if we must stuff some register arguments onto the stack as if
5594 they were passed there. */
5595 int store_arg_regs = 0;
5597 if (arm_ccfsm_state || arm_target_insn)
5598 abort (); /* Sanity check */
5600 if (arm_naked_function_p (current_function_decl))
5603 return_used_this_function = 0;
5604 lr_save_eliminated = 0;
5606 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
5607 current_function_args_size,
5608 current_function_pretend_args_size, frame_size);
5609 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
5610 frame_pointer_needed,
5611 current_function_anonymous_args);
5614 asm_fprintf (f, "\t%@ Volatile function.\n");
5616 if (current_function_anonymous_args && current_function_pretend_args_size)
5619 for (reg = 0; reg <= 10; reg++)
5620 if (regs_ever_live[reg] && ! call_used_regs[reg])
5621 live_regs_mask |= (1 << reg);
5623 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5624 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5625 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5627 if (frame_pointer_needed)
5628 live_regs_mask |= 0xD800;
5629 else if (regs_ever_live[LR_REGNUM])
5631 if (! current_function_args_size
5632 && ! function_really_clobbers_lr (get_insns ()))
5633 lr_save_eliminated = 1;
5635 live_regs_mask |= 1 << LR_REGNUM;
5640 /* if a di mode load/store multiple is used, and the base register
5641 is r3, then r4 can become an ever live register without lr
5642 doing so, in this case we need to push lr as well, or we
5643 will fail to get a proper return. */
5645 live_regs_mask |= 1 << LR_REGNUM;
5646 lr_save_eliminated = 0;
5650 if (lr_save_eliminated)
5651 asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
5653 #ifdef AOF_ASSEMBLER
5655 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
5660 arm_output_epilogue ()
5663 int live_regs_mask = 0;
5664 /* If we need this, then it will always be at least this much */
5665 int floats_offset = 12;
5667 int frame_size = get_frame_size ();
5668 FILE *f = asm_out_file;
5669 int volatile_func = (optimize > 0
5670 && TREE_THIS_VOLATILE (current_function_decl));
5672 if (use_return_insn (FALSE) && return_used_this_function)
5675 /* Naked functions don't have epilogues. */
5676 if (arm_naked_function_p (current_function_decl))
5679 /* A volatile function should never return. Call abort. */
5680 if (TARGET_ABORT_NORETURN && volatile_func)
5683 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
5684 assemble_external_libcall (op);
5685 output_asm_insn ("bl\t%a0", &op);
5689 for (reg = 0; reg <= 10; reg++)
5690 if (regs_ever_live[reg] && ! call_used_regs[reg])
5692 live_regs_mask |= (1 << reg);
5696 /* If we aren't loading the PIC register, don't stack it even though it may
5698 if (flag_pic && ! TARGET_SINGLE_PIC_BASE
5699 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5701 live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
5705 if (frame_pointer_needed)
5707 if (arm_fpu_arch == FP_SOFT2)
5709 for (reg = 23; reg > 15; reg--)
5710 if (regs_ever_live[reg] && ! call_used_regs[reg])
5712 floats_offset += 12;
5713 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
5714 reg, FP_REGNUM, floats_offset);
5721 for (reg = 23; reg > 15; reg--)
5723 if (regs_ever_live[reg] && ! call_used_regs[reg])
5725 floats_offset += 12;
5727 /* We can't unstack more than four registers at once */
5728 if (start_reg - reg == 3)
5730 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
5731 reg, FP_REGNUM, floats_offset);
5732 start_reg = reg - 1;
5737 if (reg != start_reg)
5738 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
5739 reg + 1, start_reg - reg,
5740 FP_REGNUM, floats_offset);
5741 start_reg = reg - 1;
5745 /* Just in case the last register checked also needs unstacking. */
5746 if (reg != start_reg)
5747 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
5748 reg + 1, start_reg - reg,
5749 FP_REGNUM, floats_offset);
5752 if (TARGET_INTERWORK)
5754 live_regs_mask |= 0x6800;
5755 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
5756 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
5760 live_regs_mask |= 0xA800;
5761 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
5762 TARGET_APCS_32 ? FALSE : TRUE);
5767 /* Restore stack pointer if necessary. */
5768 if (frame_size + current_function_outgoing_args_size != 0)
5770 operands[0] = operands[1] = stack_pointer_rtx;
5771 operands[2] = GEN_INT (frame_size
5772 + current_function_outgoing_args_size);
5773 output_add_immediate (operands);
5776 if (arm_fpu_arch == FP_SOFT2)
5778 for (reg = 16; reg < 24; reg++)
5779 if (regs_ever_live[reg] && ! call_used_regs[reg])
5780 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
5787 for (reg = 16; reg < 24; reg++)
5789 if (regs_ever_live[reg] && ! call_used_regs[reg])
5791 if (reg - start_reg == 3)
5793 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
5794 start_reg, SP_REGNUM);
5795 start_reg = reg + 1;
5800 if (reg != start_reg)
5801 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
5802 start_reg, reg - start_reg,
5805 start_reg = reg + 1;
5809 /* Just in case the last register checked also needs unstacking. */
5810 if (reg != start_reg)
5811 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
5812 start_reg, reg - start_reg, SP_REGNUM);
5815 if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
5817 if (TARGET_INTERWORK)
5819 if (! lr_save_eliminated)
5820 live_regs_mask |= 1 << LR_REGNUM;
5822 if (live_regs_mask != 0)
5823 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
5825 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
5827 else if (lr_save_eliminated)
5828 asm_fprintf (f, "\tmov%c\t%r, %r\n",
5829 TARGET_APCS_32 ? ' ' : 's',
5830 PC_REGNUM, LR_REGNUM);
5832 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
5833 TARGET_APCS_32 ? FALSE : TRUE);
5837 if (live_regs_mask || regs_ever_live[LR_REGNUM])
5839 /* Restore the integer regs, and the return address into lr */
5840 if (! lr_save_eliminated)
5841 live_regs_mask |= 1 << LR_REGNUM;
5843 if (live_regs_mask != 0)
5844 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
5847 if (current_function_pretend_args_size)
5849 /* Unwind the pre-pushed regs */
5850 operands[0] = operands[1] = stack_pointer_rtx;
5851 operands[2] = GEN_INT (current_function_pretend_args_size);
5852 output_add_immediate (operands);
5854 /* And finally, go home */
5855 if (TARGET_INTERWORK)
5856 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
5857 else if (TARGET_APCS_32)
5858 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
5860 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
5868 output_func_epilogue (f, frame_size)
5869 FILE *f ATTRIBUTE_UNUSED;
5872 if (use_return_insn (FALSE) && return_used_this_function
5873 && (frame_size + current_function_outgoing_args_size) != 0
5874 && ! (frame_pointer_needed && TARGET_APCS))
5877 /* Reset the ARM-specific per-function variables. */
5878 current_function_anonymous_args = 0;
5879 after_arm_reorg = 0;
5883 emit_multi_reg_push (mask)
5890 for (i = 0; i < 16; i++)
5891 if (mask & (1 << i))
5894 if (num_regs == 0 || num_regs > 16)
5897 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
5899 for (i = 0; i < 16; i++)
5901 if (mask & (1 << i))
5904 = gen_rtx_SET (VOIDmode,
5905 gen_rtx_MEM (BLKmode,
5906 gen_rtx_PRE_DEC (BLKmode,
5907 stack_pointer_rtx)),
5908 gen_rtx_UNSPEC (BLKmode,
5910 gen_rtx_REG (SImode, i)),
5916 for (j = 1, i++; j < num_regs; i++)
5918 if (mask & (1 << i))
5921 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
5930 emit_sfm (base_reg, count)
5937 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
5940 = gen_rtx_SET (VOIDmode,
5941 gen_rtx_MEM (BLKmode,
5942 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
5943 gen_rtx_UNSPEC (BLKmode,
5944 gen_rtvec (1, gen_rtx_REG (XFmode,
5947 for (i = 1; i < count; i++)
5948 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
5949 gen_rtx_REG (XFmode, base_reg++));
5955 arm_expand_prologue ()
5958 rtx amount = GEN_INT (-(get_frame_size ()
5959 + current_function_outgoing_args_size));
5960 int live_regs_mask = 0;
5961 int store_arg_regs = 0;
5962 /* If this function doesn't return, then there is no need to push
5963 the call-saved regs. */
5964 int volatile_func = (optimize > 0
5965 && TREE_THIS_VOLATILE (current_function_decl));
5967 /* Naked functions don't have prologues. */
5968 if (arm_naked_function_p (current_function_decl))
5971 if (current_function_anonymous_args && current_function_pretend_args_size)
5974 if (! volatile_func)
5976 for (reg = 0; reg <= 10; reg++)
5977 if (regs_ever_live[reg] && ! call_used_regs[reg])
5978 live_regs_mask |= 1 << reg;
5980 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
5981 live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
5983 if (regs_ever_live[LR_REGNUM])
5984 live_regs_mask |= 1 << LR_REGNUM;
5987 if (frame_pointer_needed)
5989 live_regs_mask |= 0xD800;
5990 emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
5991 stack_pointer_rtx));
5994 if (current_function_pretend_args_size)
5997 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
6000 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6001 GEN_INT (-current_function_pretend_args_size)));
6006 /* If we have to push any regs, then we must push lr as well, or
6007 we won't get a proper return. */
6008 live_regs_mask |= 1 << LR_REGNUM;
6009 emit_multi_reg_push (live_regs_mask);
6012 /* For now the integer regs are still pushed in output_func_epilogue (). */
6014 if (! volatile_func)
6016 if (arm_fpu_arch == FP_SOFT2)
6018 for (reg = 23; reg > 15; reg--)
6019 if (regs_ever_live[reg] && ! call_used_regs[reg])
6020 emit_insn (gen_rtx_SET
6022 gen_rtx_MEM (XFmode,
6023 gen_rtx_PRE_DEC (XFmode,
6024 stack_pointer_rtx)),
6025 gen_rtx_REG (XFmode, reg)));
6031 for (reg = 23; reg > 15; reg--)
6033 if (regs_ever_live[reg] && ! call_used_regs[reg])
6035 if (start_reg - reg == 3)
6038 start_reg = reg - 1;
6043 if (start_reg != reg)
6044 emit_sfm (reg + 1, start_reg - reg);
6045 start_reg = reg - 1;
6049 if (start_reg != reg)
6050 emit_sfm (reg + 1, start_reg - reg);
6054 if (frame_pointer_needed)
6055 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, IP_REGNUM),
6057 (-(4 + current_function_pretend_args_size)))));
6059 if (amount != const0_rtx)
6061 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
6062 emit_insn (gen_rtx_CLOBBER (VOIDmode,
6063 gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
6066 /* If we are profiling, make sure no instructions are scheduled before
6067 the call to mcount. Similarly if the user has requested no
6068 scheduling in the prolog. */
6069 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
6070 emit_insn (gen_blockage ());
6074 /* If CODE is 'd', then the X is a condition operand and the instruction
6075 should only be executed if the condition is true.
6076 if CODE is 'D', then the X is a condition operand and the instruction
6077 should only be executed if the condition is false: however, if the mode
6078 of the comparison is CCFPEmode, then always execute the instruction -- we
6079 do this because in these circumstances !GE does not necessarily imply LT;
6080 in these cases the instruction pattern will take care to make sure that
6081 an instruction containing %d will follow, thereby undoing the effects of
6082 doing this instruction unconditionally.
6083 If CODE is 'N' then X is a floating point operand that must be negated
6085 If CODE is 'B' then output a bitwise inverted value of X (a const int).
6086 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
6089 arm_print_operand (stream, x, code)
6097 fputs (ASM_COMMENT_START, stream);
6101 fputs (REGISTER_PREFIX, stream);
6105 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
6106 fputs (arm_condition_codes[arm_current_cc], stream);
6112 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6113 r = REAL_VALUE_NEGATE (r);
6114 fprintf (stream, "%s", fp_const_from_val (&r));
6119 if (GET_CODE (x) == CONST_INT)
6122 val = ARM_SIGN_EXTEND (~ INTVAL (x));
6123 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6128 output_addr_const (stream, x);
6133 fprintf (stream, "%s", arithmetic_instr (x, 1));
6137 fprintf (stream, "%s", arithmetic_instr (x, 0));
6143 char * shift = shift_op (x, & val);
6147 fprintf (stream, ", %s ", shift_op (x, & val));
6149 arm_print_operand (stream, XEXP (x, 1), 0);
6152 fputc ('#', stream);
6153 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
6162 fputs (REGISTER_PREFIX, stream);
6163 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
6169 fputs (REGISTER_PREFIX, stream);
6170 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
6174 fputs (REGISTER_PREFIX, stream);
6175 if (GET_CODE (XEXP (x, 0)) == REG)
6176 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
6178 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
6182 asm_fprintf (stream, "{%r-%r}",
6183 REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
6188 fputs (arm_condition_codes[get_arm_condition_code (x)],
6194 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
6195 (get_arm_condition_code (x))],
6203 if (GET_CODE (x) == REG)
6205 fputs (REGISTER_PREFIX, stream);
6206 fputs (reg_names[REGNO (x)], stream);
6208 else if (GET_CODE (x) == MEM)
6210 output_memory_reference_mode = GET_MODE (x);
6211 output_address (XEXP (x, 0));
6213 else if (GET_CODE (x) == CONST_DOUBLE)
6214 fprintf (stream, "#%s", fp_immediate_constant (x));
6215 else if (GET_CODE (x) == NEG)
6216 abort (); /* This should never happen now. */
6219 fputc ('#', stream);
6220 output_addr_const (stream, x);
6225 /* A finite state machine takes care of noticing whether or not instructions
6226 can be conditionally executed, and thus decrease execution time and code
6227 size by deleting branch instructions. The fsm is controlled by
6228 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
6230 /* The state of the fsm controlling condition codes are:
6231 0: normal, do nothing special
6232 1: make ASM_OUTPUT_OPCODE not output this instruction
6233 2: make ASM_OUTPUT_OPCODE not output this instruction
6234 3: make instructions conditional
6235 4: make instructions conditional
6237 State transitions (state->state by whom under condition):
6238 0 -> 1 final_prescan_insn if the `target' is a label
6239 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
6240 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
6241 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
6242 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
6243 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
6244 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
6245 (the target insn is arm_target_insn).
6247 If the jump clobbers the conditions then we use states 2 and 4.
6249 A similar thing can be done with conditional return insns.
6251 XXX In case the `target' is an unconditional branch, this conditionalising
6252 of the instructions always reduces code size, but not always execution
6253 time. But then, I want to reduce the code size to somewhere near what
6254 /bin/cc produces. */
6256 /* Returns the index of the ARM condition code string in
6257 `arm_condition_codes'. COMPARISON should be an rtx like
6258 `(eq (...) (...))'. */
6260 static enum arm_cond_code
6261 get_arm_condition_code (comparison)
6264 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
6266 register enum rtx_code comp_code = GET_CODE (comparison);
6268 if (GET_MODE_CLASS (mode) != MODE_CC)
6269 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
6270 XEXP (comparison, 1));
6274 case CC_DNEmode: code = ARM_NE; goto dominance;
6275 case CC_DEQmode: code = ARM_EQ; goto dominance;
6276 case CC_DGEmode: code = ARM_GE; goto dominance;
6277 case CC_DGTmode: code = ARM_GT; goto dominance;
6278 case CC_DLEmode: code = ARM_LE; goto dominance;
6279 case CC_DLTmode: code = ARM_LT; goto dominance;
6280 case CC_DGEUmode: code = ARM_CS; goto dominance;
6281 case CC_DGTUmode: code = ARM_HI; goto dominance;
6282 case CC_DLEUmode: code = ARM_LS; goto dominance;
6283 case CC_DLTUmode: code = ARM_CC;
6286 if (comp_code != EQ && comp_code != NE)
6289 if (comp_code == EQ)
6290 return ARM_INVERSE_CONDITION_CODE (code);
6296 case NE: return ARM_NE;
6297 case EQ: return ARM_EQ;
6298 case GE: return ARM_PL;
6299 case LT: return ARM_MI;
6307 case NE: return ARM_NE;
6308 case EQ: return ARM_EQ;
6315 case GE: return ARM_GE;
6316 case GT: return ARM_GT;
6317 case LE: return ARM_LS;
6318 case LT: return ARM_MI;
6325 case NE: return ARM_NE;
6326 case EQ: return ARM_EQ;
6327 case GE: return ARM_LE;
6328 case GT: return ARM_LT;
6329 case LE: return ARM_GE;
6330 case LT: return ARM_GT;
6331 case GEU: return ARM_LS;
6332 case GTU: return ARM_CC;
6333 case LEU: return ARM_CS;
6334 case LTU: return ARM_HI;
6341 case LTU: return ARM_CS;
6342 case GEU: return ARM_CC;
6349 case NE: return ARM_NE;
6350 case EQ: return ARM_EQ;
6351 case GE: return ARM_GE;
6352 case GT: return ARM_GT;
6353 case LE: return ARM_LE;
6354 case LT: return ARM_LT;
6355 case GEU: return ARM_CS;
6356 case GTU: return ARM_HI;
6357 case LEU: return ARM_LS;
6358 case LTU: return ARM_CC;
6370 arm_final_prescan_insn (insn)
6373 /* BODY will hold the body of INSN. */
6374 register rtx body = PATTERN (insn);
6376 /* This will be 1 if trying to repeat the trick, and things need to be
6377 reversed if it appears to fail. */
6380 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
6381 taken are clobbered, even if the rtl suggests otherwise. It also
6382 means that we have to grub around within the jump expression to find
6383 out what the conditions are when the jump isn't taken. */
6384 int jump_clobbers = 0;
6386 /* If we start with a return insn, we only succeed if we find another one. */
6387 int seeking_return = 0;
6389 /* START_INSN will hold the insn from where we start looking. This is the
6390 first insn after the following code_label if REVERSE is true. */
6391 rtx start_insn = insn;
6393 /* If in state 4, check if the target branch is reached, in order to
6394 change back to state 0. */
6395 if (arm_ccfsm_state == 4)
6397 if (insn == arm_target_insn)
6399 arm_target_insn = NULL;
6400 arm_ccfsm_state = 0;
6405 /* If in state 3, it is possible to repeat the trick, if this insn is an
6406 unconditional branch to a label, and immediately following this branch
6407 is the previous target label which is only used once, and the label this
6408 branch jumps to is not too far off. */
6409 if (arm_ccfsm_state == 3)
6411 if (simplejump_p (insn))
6413 start_insn = next_nonnote_insn (start_insn);
6414 if (GET_CODE (start_insn) == BARRIER)
6416 /* XXX Isn't this always a barrier? */
6417 start_insn = next_nonnote_insn (start_insn);
6419 if (GET_CODE (start_insn) == CODE_LABEL
6420 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6421 && LABEL_NUSES (start_insn) == 1)
6426 else if (GET_CODE (body) == RETURN)
6428 start_insn = next_nonnote_insn (start_insn);
6429 if (GET_CODE (start_insn) == BARRIER)
6430 start_insn = next_nonnote_insn (start_insn);
6431 if (GET_CODE (start_insn) == CODE_LABEL
6432 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
6433 && LABEL_NUSES (start_insn) == 1)
6445 if (arm_ccfsm_state != 0 && !reverse)
6447 if (GET_CODE (insn) != JUMP_INSN)
6450 /* This jump might be paralleled with a clobber of the condition codes
6451 the jump should always come first */
6452 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6453 body = XVECEXP (body, 0, 0);
6456 /* If this is a conditional return then we don't want to know */
6457 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6458 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
6459 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
6460 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
6465 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
6466 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
6469 int fail = FALSE, succeed = FALSE;
6470 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
6471 int then_not_else = TRUE;
6472 rtx this_insn = start_insn, label = 0;
6474 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
6476 /* The code below is wrong for these, and I haven't time to
6477 fix it now. So we just do the safe thing and return. This
6478 whole function needs re-writing anyway. */
6483 /* Register the insn jumped to. */
6486 if (!seeking_return)
6487 label = XEXP (SET_SRC (body), 0);
6489 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
6490 label = XEXP (XEXP (SET_SRC (body), 1), 0);
6491 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
6493 label = XEXP (XEXP (SET_SRC (body), 2), 0);
6494 then_not_else = FALSE;
6496 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
6498 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
6501 then_not_else = FALSE;
6506 /* See how many insns this branch skips, and what kind of insns. If all
6507 insns are okay, and the label or unconditional branch to the same
6508 label is not too far away, succeed. */
6509 for (insns_skipped = 0;
6510 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
6514 this_insn = next_nonnote_insn (this_insn);
6518 switch (GET_CODE (this_insn))
6521 /* Succeed if it is the target label, otherwise fail since
6522 control falls in from somewhere else. */
6523 if (this_insn == label)
6527 arm_ccfsm_state = 2;
6528 this_insn = next_nonnote_insn (this_insn);
6531 arm_ccfsm_state = 1;
6539 /* Succeed if the following insn is the target label.
6541 If return insns are used then the last insn in a function
6542 will be a barrier. */
6543 this_insn = next_nonnote_insn (this_insn);
6544 if (this_insn && this_insn == label)
6548 arm_ccfsm_state = 2;
6549 this_insn = next_nonnote_insn (this_insn);
6552 arm_ccfsm_state = 1;
6560 /* If using 32-bit addresses the cc is not preserved over
6564 /* Succeed if the following insn is the target label,
6565 or if the following two insns are a barrier and
6566 the target label. */
6567 this_insn = next_nonnote_insn (this_insn);
6568 if (this_insn && GET_CODE (this_insn) == BARRIER)
6569 this_insn = next_nonnote_insn (this_insn);
6571 if (this_insn && this_insn == label
6572 && insns_skipped < max_insns_skipped)
6576 arm_ccfsm_state = 2;
6577 this_insn = next_nonnote_insn (this_insn);
6580 arm_ccfsm_state = 1;
6589 /* If this is an unconditional branch to the same label, succeed.
6590 If it is to another label, do nothing. If it is conditional,
6592 /* XXX Probably, the tests for SET and the PC are unnecessary. */
6594 scanbody = PATTERN (this_insn);
6595 if (GET_CODE (scanbody) == SET
6596 && GET_CODE (SET_DEST (scanbody)) == PC)
6598 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
6599 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
6601 arm_ccfsm_state = 2;
6604 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
6607 /* Fail if a conditional return is undesirable (eg on a
6608 StrongARM), but still allow this if optimizing for size. */
6609 else if (GET_CODE (scanbody) == RETURN
6610 && ! use_return_insn (TRUE)
6613 else if (GET_CODE (scanbody) == RETURN
6616 arm_ccfsm_state = 2;
6619 else if (GET_CODE (scanbody) == PARALLEL)
6621 switch (get_attr_conds (this_insn))
6633 /* Instructions using or affecting the condition codes make it
6635 scanbody = PATTERN (this_insn);
6636 if (! (GET_CODE (scanbody) == SET
6637 || GET_CODE (scanbody) == PARALLEL)
6638 || get_attr_conds (this_insn) != CONDS_NOCOND)
6648 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
6649 arm_target_label = CODE_LABEL_NUMBER (label);
6650 else if (seeking_return || arm_ccfsm_state == 2)
6652 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
6654 this_insn = next_nonnote_insn (this_insn);
6655 if (this_insn && (GET_CODE (this_insn) == BARRIER
6656 || GET_CODE (this_insn) == CODE_LABEL))
6661 /* Oh, dear! we ran off the end.. give up */
6662 recog (PATTERN (insn), insn, NULL_PTR);
6663 arm_ccfsm_state = 0;
6664 arm_target_insn = NULL;
6667 arm_target_insn = this_insn;
6676 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
6678 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
6679 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6680 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
6681 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6685 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6688 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
6692 if (reverse || then_not_else)
6693 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6695 /* restore recog_operand (getting the attributes of other insns can
6696 destroy this array, but final.c assumes that it remains intact
6697 across this call; since the insn has been recognized already we
6698 call recog direct). */
6699 recog (PATTERN (insn), insn, NULL_PTR);
6703 #ifdef AOF_ASSEMBLER
6704 /* Special functions only needed when producing AOF syntax assembler. */
6706 rtx aof_pic_label = NULL_RTX;
6709 struct pic_chain * next;
6713 static struct pic_chain * aof_pic_chain = NULL;
6719 struct pic_chain ** chainp;
6722 if (aof_pic_label == NULL_RTX)
6724 /* This needs to persist throughout the compilation. */
6725 end_temporary_allocation ();
6726 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
6727 resume_temporary_allocation ();
6730 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6731 offset += 4, chainp = &(*chainp)->next)
6732 if ((*chainp)->symname == XSTR (x, 0))
6733 return plus_constant (aof_pic_label, offset);
6735 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6736 (*chainp)->next = NULL;
6737 (*chainp)->symname = XSTR (x, 0);
6738 return plus_constant (aof_pic_label, offset);
6742 aof_dump_pic_table (f)
6745 struct pic_chain * chain;
6747 if (aof_pic_chain == NULL)
6750 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
6751 PIC_OFFSET_TABLE_REGNUM,
6752 PIC_OFFSET_TABLE_REGNUM);
6753 fputs ("|x$adcons|\n", f);
6755 for (chain = aof_pic_chain; chain; chain = chain->next)
6757 fputs ("\tDCD\t", f);
6758 assemble_name (f, chain->symname);
6763 int arm_text_section_count = 1;
6768 static char buf[100];
6769 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6770 arm_text_section_count++);
6772 strcat (buf, ", PIC, REENTRANT");
6776 static int arm_data_section_count = 1;
6781 static char buf[100];
6782 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6786 /* The AOF assembler is religiously strict about declarations of
6787 imported and exported symbols, so that it is impossible to declare
6788 a function as imported near the beginning of the file, and then to
6789 export it later on. It is, however, possible to delay the decision
6790 until all the functions in the file have been compiled. To get
6791 around this, we maintain a list of the imports and exports, and
6792 delete from it any that are subsequently defined. At the end of
6793 compilation we spit the remainder of the list out before the END
6798 struct import * next;
6802 static struct import * imports_list = NULL;
6805 aof_add_import (name)
6808 struct import * new;
6810 for (new = imports_list; new; new = new->next)
6811 if (new->name == name)
6814 new = (struct import *) xmalloc (sizeof (struct import));
6815 new->next = imports_list;
6821 aof_delete_import (name)
6824 struct import ** old;
6826 for (old = &imports_list; *old; old = & (*old)->next)
6828 if ((*old)->name == name)
6830 *old = (*old)->next;
6836 int arm_main_function = 0;
6839 aof_dump_imports (f)
6842 /* The AOF assembler needs this to cause the startup code to be extracted
6843 from the library. Brining in __main causes the whole thing to work
6845 if (arm_main_function)
6848 fputs ("\tIMPORT __main\n", f);
6849 fputs ("\tDCD __main\n", f);
6852 /* Now dump the remaining imports. */
6853 while (imports_list)
6855 fprintf (f, "\tIMPORT\t");
6856 assemble_name (f, imports_list->name);
6858 imports_list = imports_list->next;
6861 #endif /* AOF_ASSEMBLER */