1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 /* The maximum number of insns skipped which will be conditionalised if
44 static int max_insns_skipped = 5;
46 /* Some function declarations. */
47 extern FILE *asm_out_file;
49 static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
50 static char *output_multi_immediate PROTO ((rtx *, char *, char *, int,
52 static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
53 HOST_WIDE_INT, rtx, rtx, int, int));
54 static int arm_naked_function_p PROTO ((tree));
55 static void init_fpa_table PROTO ((void));
56 static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
58 static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
59 static void dump_table PROTO ((rtx));
60 static int fixit PROTO ((rtx, enum machine_mode, int));
61 static rtx find_barrier PROTO ((rtx, int));
62 static int broken_move PROTO ((rtx));
63 static char *fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
64 static int eliminate_lr2ip PROTO ((rtx *));
65 static char *shift_op PROTO ((rtx, HOST_WIDE_INT *));
66 static int pattern_really_clobbers_lr PROTO ((rtx));
67 static int function_really_clobbers_lr PROTO ((rtx));
68 static void emit_multi_reg_push PROTO ((int));
69 static void emit_sfm PROTO ((int, int));
70 static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
72 /* Define the information needed to generate branch insns. This is
73 stored from the compare operation. */
75 rtx arm_compare_op0, arm_compare_op1;
78 /* What type of cpu are we compiling for? */
79 enum processor_type arm_cpu;
81 /* What type of floating point are we tuning for? */
82 enum floating_point_type arm_fpu;
84 /* What type of floating point instructions are available? */
85 enum floating_point_type arm_fpu_arch;
87 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
88 enum prog_mode_type arm_prgmode;
90 /* Set by the -mfp=... option */
91 char *target_fp_name = NULL;
93 /* Used to parse -mstructure_size_boundary command line option. */
94 char * structure_size_string = NULL;
95 int arm_structure_size_boundary = 32; /* Used to be 8 */
97 /* Nonzero if this is an "M" variant of the processor. */
98 int arm_fast_multiply = 0;
100 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
103 /* Set to the features we should tune the code for (multiply speed etc). */
106 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
107 must report the mode of the memory reference from PRINT_OPERAND to
108 PRINT_OPERAND_ADDRESS. */
109 enum machine_mode output_memory_reference_mode;
111 /* Nonzero if the prologue must setup `fp'. */
112 int current_function_anonymous_args;
114 /* The register number to be used for the PIC offset register. */
115 int arm_pic_register = 9;
117 /* Location counter of .text segment. */
118 int arm_text_location = 0;
120 /* Set to one if we think that lr is only saved because of subroutine calls,
121 but all of these can be `put after' return insns */
122 int lr_save_eliminated;
124 /* Set to 1 when a return insn is output, this means that the epilogue
127 static int return_used_this_function;
129 static int arm_constant_limit = 3;
131 /* For an explanation of these variables, see final_prescan_insn below. */
133 enum arm_cond_code arm_current_cc;
135 int arm_target_label;
137 /* The condition codes of the ARM, and the inverse function. */
138 char *arm_condition_codes[] =
140 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
141 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
144 static enum arm_cond_code get_arm_condition_code ();
147 /* Initialization code */
149 struct arm_cpu_select arm_select[4] =
151 /* switch name, tune arch */
152 { (char *)0, "--with-cpu=", 1, 1 },
153 { (char *)0, "-mcpu=", 1, 1 },
154 { (char *)0, "-march=", 0, 1 },
155 { (char *)0, "-mtune=", 1, 0 },
158 #define FL_CO_PROC 0x01 /* Has external co-processor bus */
159 #define FL_FAST_MULT 0x02 /* Fast multiply */
160 #define FL_MODE26 0x04 /* 26-bit mode support */
161 #define FL_MODE32 0x08 /* 32-bit mode support */
162 #define FL_ARCH4 0x10 /* Architecture rel 4 */
163 #define FL_THUMB 0x20 /* Thumb aware */
168 enum processor_type type;
172 /* Not all of these give usefully different compilation alternatives,
173 but there is no simple way of generalizing them. */
174 static struct processors all_procs[] =
176 {"arm2", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
177 {"arm250", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
178 {"arm3", PROCESSOR_ARM2, FL_CO_PROC | FL_MODE26},
179 {"arm6", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
180 {"arm600", PROCESSOR_ARM6, FL_CO_PROC | FL_MODE32 | FL_MODE26},
181 {"arm610", PROCESSOR_ARM6, FL_MODE32 | FL_MODE26},
182 {"arm7", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
183 /* arm7m doesn't exist on its own, only in conjunction with D, (and I), but
184 those don't alter the code, so it is sometimes known as the arm7m */
185 {"arm7m", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
187 {"arm7dm", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
189 {"arm7dmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
191 {"arm700", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
192 {"arm710", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
193 {"arm7100", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
194 {"arm7500", PROCESSOR_ARM7, FL_MODE32 | FL_MODE26},
195 /* Doesn't really have an external co-proc, but does have embedded fpu */
196 {"arm7500fe", PROCESSOR_ARM7, FL_CO_PROC | FL_MODE32 | FL_MODE26},
197 {"arm7tdmi", PROCESSOR_ARM7, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
198 | FL_ARCH4 | FL_THUMB)},
199 {"arm8", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
201 {"arm810", PROCESSOR_ARM8, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
203 /* The next two are the same, but arm9 only exists in the thumb variant */
204 {"arm9", PROCESSOR_ARM9, (FL_FAST_MULT | FL_MODE32 | FL_ARCH4
206 {"arm9tdmi", PROCESSOR_ARM9, (FL_FAST_MULT | FL_MODE32 | FL_ARCH4
208 {"strongarm", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
210 {"strongarm110", PROCESSOR_STARM, (FL_FAST_MULT | FL_MODE32 | FL_MODE26
212 {"armv2", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
213 {"armv2a", PROCESSOR_NONE, FL_CO_PROC | FL_MODE26},
214 {"armv3", PROCESSOR_NONE, FL_CO_PROC | FL_MODE32 | FL_MODE26},
215 {"armv3m", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
217 {"armv4", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
218 | FL_MODE26 | FL_ARCH4)},
219 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
220 implementations that support it, so we will leave it out for now. */
221 {"armv4t", PROCESSOR_NONE, (FL_CO_PROC | FL_FAST_MULT | FL_MODE32
226 /* Fix up any incompatible options that the user has specified.
227 This has now turned into a maze. */
229 arm_override_options ()
231 int arm_thumb_aware = 0;
234 struct arm_cpu_select * ptr;
235 static struct cpu_default
242 { TARGET_CPU_arm2, "arm2" },
243 { TARGET_CPU_arm6, "arm6" },
244 { TARGET_CPU_arm610, "arm610" },
245 { TARGET_CPU_arm7dm, "arm7dm" },
246 { TARGET_CPU_arm7500fe, "arm7500fe" },
247 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
248 { TARGET_CPU_arm8, "arm8" },
249 { TARGET_CPU_arm810, "arm810" },
250 { TARGET_CPU_strongarm, "strongarm" },
253 struct cpu_default *def;
255 /* Set the default. */
256 for (def = &cpu_defaults[0]; def->name; ++def)
257 if (def->cpu == TARGET_CPU_DEFAULT)
262 arm_select[0].string = def->name;
264 for (i = 0; i < sizeof (arm_select) / sizeof (arm_select[0]); i++)
266 ptr = &arm_select[i];
267 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
269 struct processors *sel;
271 for (sel = all_procs; sel->name != NULL; sel++)
272 if (! strcmp (ptr->string, sel->name))
274 /* -march= is the only flag that can take an architecture
275 type, so if we match when the tune bit is set, the
276 option was invalid. */
279 if (sel->type == PROCESSOR_NONE)
280 continue; /* Its an architecture, not a cpu */
283 tune_flags = sel->flags;
292 if (sel->name == NULL)
293 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
297 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
298 warning ("-g with -fomit-frame-pointer may not give sensible debugging");
300 if (TARGET_POKE_FUNCTION_NAME)
301 target_flags |= ARM_FLAG_APCS_FRAME;
304 warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
307 warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
309 if (TARGET_APCS_REENT && flag_pic)
310 fatal ("-fpic and -mapcs-reent are incompatible");
312 if (TARGET_APCS_REENT)
313 warning ("APCS reentrant code not supported.");
315 /* If stack checking is disabled, we can use r10 as the PIC register,
316 which keeps r9 available. */
317 if (flag_pic && ! TARGET_APCS_STACK)
318 arm_pic_register = 10;
320 /* Well, I'm about to have a go, but pic is NOT going to be compatible
321 with APCS reentrancy, since that requires too much support in the
322 assembler and linker, and the ARMASM assembler seems to lack some
323 required directives. */
325 warning ("Position independent code not supported");
327 if (TARGET_APCS_FLOAT)
328 warning ("Passing floating point arguments in fp regs not yet supported");
330 if (TARGET_APCS_STACK && ! TARGET_APCS)
332 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
333 target_flags |= ARM_FLAG_APCS_FRAME;
336 /* Default is to tune for an FPA */
339 /* Default value for floating point code... if no co-processor
340 bus, then schedule for emulated floating point. Otherwise,
341 assume the user has an FPA.
342 Note: this does not prevent use of floating point instructions,
343 -msoft-float does that. */
344 if ((tune_flags & FL_CO_PROC) == 0)
347 arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
348 arm_arch4 = (flags & FL_ARCH4) != 0;
349 arm_thumb_aware = (flags & FL_THUMB) != 0;
353 if (strcmp (target_fp_name, "2") == 0)
354 arm_fpu_arch = FP_SOFT2;
355 else if (strcmp (target_fp_name, "3") == 0)
356 arm_fpu_arch = FP_HARD;
358 fatal ("Invalid floating point emulation option: -mfpe=%s",
362 arm_fpu_arch = FP_DEFAULT;
364 if (TARGET_THUMB_INTERWORK && ! arm_thumb_aware)
366 warning ("This processor variant does not support Thumb interworking");
367 target_flags &= ~ARM_FLAG_THUMB;
370 if (TARGET_FPE && arm_fpu == FP_HARD)
373 /* If optimizing for space, don't synthesize constants */
375 arm_constant_limit = 1;
377 /* Override a few things based on the tuning pararmeters. */
382 /* For arm2/3 there is no need to do any scheduling if there is
383 only a floating point emulator, or we are doing software
385 if (TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
386 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
395 /* For these processors, it never costs more than 2 cycles to load a
396 constant, and the load scheduler may well reduce that to 1. */
397 arm_constant_limit = 1;
400 case PROCESSOR_STARM:
402 arm_constant_limit = 1;
403 /* StrongARM has early execution of branches, a sequence that is worth
404 skipping is shorter. */
405 max_insns_skipped = 3;
409 fatal ("Unknown cpu type selected");
413 /* If optimizing for size, bump the number of instructions that we
414 are prepared to conditionally execute (even on a StrongARM). */
416 max_insns_skipped = 6;
418 arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
420 if (structure_size_string != NULL)
422 int size = strtol (structure_size_string, NULL, 0);
424 if (size == 8 || size == 32)
425 arm_structure_size_boundary = size;
427 warning ("Structure size boundary can only be set to 8 or 32");
431 /* Return 1 if it is possible to return using a single instruction */
434 use_return_insn (iscond)
439 if (!reload_completed ||current_function_pretend_args_size
440 || current_function_anonymous_args
441 || ((get_frame_size () + current_function_outgoing_args_size != 0)
442 && !(TARGET_APCS || frame_pointer_needed)))
445 /* Can't be done if interworking with Thumb, and any registers have been
446 stacked. Similarly, on StrongARM, conditional returns are expensive
447 if they aren't taken and registers have been stacked. */
448 if (iscond && arm_cpu == PROCESSOR_STARM && frame_pointer_needed)
450 else if ((iscond && arm_cpu == PROCESSOR_STARM)
451 || TARGET_THUMB_INTERWORK)
452 for (regno = 0; regno < 16; regno++)
453 if (regs_ever_live[regno] && ! call_used_regs[regno])
456 /* Can't be done if any of the FPU regs are pushed, since this also
458 for (regno = 16; regno < 24; regno++)
459 if (regs_ever_live[regno] && ! call_used_regs[regno])
462 /* If a function is naked, don't use the "return" insn. */
463 if (arm_naked_function_p (current_function_decl))
469 /* Return TRUE if int I is a valid immediate ARM constant. */
475 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
477 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
478 be all zero, or all one. */
479 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
480 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
481 != ((~(unsigned HOST_WIDE_INT) 0)
482 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
485 /* Fast return for 0 and powers of 2 */
486 if ((i & (i - 1)) == 0)
491 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
494 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
495 >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
496 } while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
501 /* Return true if I is a valid constant for the operation CODE. */
503 const_ok_for_op (i, code, mode)
506 enum machine_mode mode;
508 if (const_ok_for_arm (i))
514 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
516 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
522 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
529 /* Emit a sequence of insns to handle a large constant.
530 CODE is the code of the operation required, it can be any of SET, PLUS,
531 IOR, AND, XOR, MINUS;
532 MODE is the mode in which the operation is being performed;
533 VAL is the integer to operate on;
534 SOURCE is the other operand (a register, or a null-pointer for SET);
535 SUBTARGETS means it is safe to create scratch registers if that will
536 either produce a simpler sequence, or we will want to cse the values.
537 Return value is the number of insns emitted. */
540 arm_split_constant (code, mode, val, target, source, subtargets)
542 enum machine_mode mode;
548 if (subtargets || code == SET
549 || (GET_CODE (target) == REG && GET_CODE (source) == REG
550 && REGNO (target) != REGNO (source)))
552 if (arm_gen_constant (code, mode, val, target, source, 1, 0)
553 > arm_constant_limit + (code != SET))
557 /* Currently SET is the only monadic value for CODE, all
558 the rest are diadic. */
559 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (val)));
564 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
566 emit_insn (gen_rtx (SET, VOIDmode, temp, GEN_INT (val)));
567 /* For MINUS, the value is subtracted from, since we never
568 have subtraction of a constant. */
570 emit_insn (gen_rtx (SET, VOIDmode, target,
571 gen_rtx (code, mode, temp, source)));
573 emit_insn (gen_rtx (SET, VOIDmode, target,
574 gen_rtx (code, mode, source, temp)));
580 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
583 /* As above, but extra parameter GENERATE which, if clear, suppresses
586 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
588 enum machine_mode mode;
597 int can_negate_initial = 0;
600 int num_bits_set = 0;
601 int set_sign_bit_copies = 0;
602 int clear_sign_bit_copies = 0;
603 int clear_zero_bit_copies = 0;
604 int set_zero_bit_copies = 0;
606 unsigned HOST_WIDE_INT temp1, temp2;
607 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
609 /* find out which operations are safe for a given CODE. Also do a quick
610 check for degenerate cases; these can occur when DImode operations
622 can_negate_initial = 1;
626 if (remainder == 0xffffffff)
629 emit_insn (gen_rtx (SET, VOIDmode, target,
630 GEN_INT (ARM_SIGN_EXTEND (val))));
635 if (reload_completed && rtx_equal_p (target, source))
638 emit_insn (gen_rtx (SET, VOIDmode, target, source));
647 emit_insn (gen_rtx (SET, VOIDmode, target, const0_rtx));
650 if (remainder == 0xffffffff)
652 if (reload_completed && rtx_equal_p (target, source))
655 emit_insn (gen_rtx (SET, VOIDmode, target, source));
664 if (reload_completed && rtx_equal_p (target, source))
667 emit_insn (gen_rtx (SET, VOIDmode, target, source));
670 if (remainder == 0xffffffff)
673 emit_insn (gen_rtx (SET, VOIDmode, target,
674 gen_rtx (NOT, mode, source)));
678 /* We don't know how to handle this yet below. */
682 /* We treat MINUS as (val - source), since (source - val) is always
683 passed as (source + (-val)). */
687 emit_insn (gen_rtx (SET, VOIDmode, target,
688 gen_rtx (NEG, mode, source)));
691 if (const_ok_for_arm (val))
694 emit_insn (gen_rtx (SET, VOIDmode, target,
695 gen_rtx (MINUS, mode, GEN_INT (val), source)));
706 /* If we can do it in one insn get out quickly */
707 if (const_ok_for_arm (val)
708 || (can_negate_initial && const_ok_for_arm (-val))
709 || (can_invert && const_ok_for_arm (~val)))
712 emit_insn (gen_rtx (SET, VOIDmode, target,
713 (source ? gen_rtx (code, mode, source,
720 /* Calculate a few attributes that may be useful for specific
723 for (i = 31; i >= 0; i--)
725 if ((remainder & (1 << i)) == 0)
726 clear_sign_bit_copies++;
731 for (i = 31; i >= 0; i--)
733 if ((remainder & (1 << i)) != 0)
734 set_sign_bit_copies++;
739 for (i = 0; i <= 31; i++)
741 if ((remainder & (1 << i)) == 0)
742 clear_zero_bit_copies++;
747 for (i = 0; i <= 31; i++)
749 if ((remainder & (1 << i)) != 0)
750 set_zero_bit_copies++;
758 /* See if we can do this by sign_extending a constant that is known
759 to be negative. This is a good, way of doing it, since the shift
760 may well merge into a subsequent insn. */
761 if (set_sign_bit_copies > 1)
764 (temp1 = ARM_SIGN_EXTEND (remainder
765 << (set_sign_bit_copies - 1))))
769 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
770 emit_insn (gen_rtx (SET, VOIDmode, new_src,
772 emit_insn (gen_ashrsi3 (target, new_src,
773 GEN_INT (set_sign_bit_copies - 1)));
777 /* For an inverted constant, we will need to set the low bits,
778 these will be shifted out of harm's way. */
779 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
780 if (const_ok_for_arm (~temp1))
784 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
785 emit_insn (gen_rtx (SET, VOIDmode, new_src,
787 emit_insn (gen_ashrsi3 (target, new_src,
788 GEN_INT (set_sign_bit_copies - 1)));
794 /* See if we can generate this by setting the bottom (or the top)
795 16 bits, and then shifting these into the other half of the
796 word. We only look for the simplest cases, to do more would cost
797 too much. Be careful, however, not to generate this when the
798 alternative would take fewer insns. */
799 if (val & 0xffff0000)
801 temp1 = remainder & 0xffff0000;
802 temp2 = remainder & 0x0000ffff;
804 /* Overlaps outside this range are best done using other methods. */
805 for (i = 9; i < 24; i++)
807 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
808 && ! const_ok_for_arm (temp2))
810 rtx new_src = (subtargets
811 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
813 insns = arm_gen_constant (code, mode, temp2, new_src,
814 source, subtargets, generate);
817 emit_insn (gen_rtx (SET, VOIDmode, target,
819 gen_rtx (ASHIFT, mode, source,
826 /* Don't duplicate cases already considered. */
827 for (i = 17; i < 24; i++)
829 if (((temp1 | (temp1 >> i)) == remainder)
830 && ! const_ok_for_arm (temp1))
832 rtx new_src = (subtargets
833 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
835 insns = arm_gen_constant (code, mode, temp1, new_src,
836 source, subtargets, generate);
839 emit_insn (gen_rtx (SET, VOIDmode, target,
841 gen_rtx (LSHIFTRT, mode,
842 source, GEN_INT (i)),
852 /* If we have IOR or XOR, and the constant can be loaded in a
853 single instruction, and we can find a temporary to put it in,
854 then this can be done in two instructions instead of 3-4. */
856 /* TARGET can't be NULL if SUBTARGETS is 0 */
857 || (reload_completed && ! reg_mentioned_p (target, source)))
859 if (const_ok_for_arm (ARM_SIGN_EXTEND (~ val)))
863 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
865 emit_insn (gen_rtx (SET, VOIDmode, sub, GEN_INT (val)));
866 emit_insn (gen_rtx (SET, VOIDmode, target,
867 gen_rtx (code, mode, source, sub)));
876 if (set_sign_bit_copies > 8
877 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
881 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
882 rtx shift = GEN_INT (set_sign_bit_copies);
884 emit_insn (gen_rtx (SET, VOIDmode, sub,
886 gen_rtx (ASHIFT, mode, source,
888 emit_insn (gen_rtx (SET, VOIDmode, target,
890 gen_rtx (LSHIFTRT, mode, sub,
896 if (set_zero_bit_copies > 8
897 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
901 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
902 rtx shift = GEN_INT (set_zero_bit_copies);
904 emit_insn (gen_rtx (SET, VOIDmode, sub,
906 gen_rtx (LSHIFTRT, mode, source,
908 emit_insn (gen_rtx (SET, VOIDmode, target,
910 gen_rtx (ASHIFT, mode, sub,
916 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~ val)))
920 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
921 emit_insn (gen_rtx (SET, VOIDmode, sub,
922 gen_rtx (NOT, mode, source)));
925 sub = gen_reg_rtx (mode);
926 emit_insn (gen_rtx (SET, VOIDmode, sub,
927 gen_rtx (AND, mode, source,
929 emit_insn (gen_rtx (SET, VOIDmode, target,
930 gen_rtx (NOT, mode, sub)));
937 /* See if two shifts will do 2 or more insn's worth of work. */
938 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
940 HOST_WIDE_INT shift_mask = ((0xffffffff
941 << (32 - clear_sign_bit_copies))
944 if ((remainder | shift_mask) != 0xffffffff)
948 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
949 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
950 new_src, source, subtargets, 1);
955 rtx targ = subtargets ? NULL_RTX : target;
956 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
957 targ, source, subtargets, 0);
963 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
964 rtx shift = GEN_INT (clear_sign_bit_copies);
966 emit_insn (gen_ashlsi3 (new_src, source, shift));
967 emit_insn (gen_lshrsi3 (target, new_src, shift));
973 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
975 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
977 if ((remainder | shift_mask) != 0xffffffff)
981 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
983 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
984 new_src, source, subtargets, 1);
989 rtx targ = subtargets ? NULL_RTX : target;
991 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
992 targ, source, subtargets, 0);
998 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
999 rtx shift = GEN_INT (clear_zero_bit_copies);
1001 emit_insn (gen_lshrsi3 (new_src, source, shift));
1002 emit_insn (gen_ashlsi3 (target, new_src, shift));
1014 for (i = 0; i < 32; i++)
1015 if (remainder & (1 << i))
1018 if (code == AND || (can_invert && num_bits_set > 16))
1019 remainder = (~remainder) & 0xffffffff;
1020 else if (code == PLUS && num_bits_set > 16)
1021 remainder = (-remainder) & 0xffffffff;
1028 /* Now try and find a way of doing the job in either two or three
1030 We start by looking for the largest block of zeros that are aligned on
1031 a 2-bit boundary, we then fill up the temps, wrapping around to the
1032 top of the word when we drop off the bottom.
1033 In the worst case this code should produce no more than four insns. */
1036 int best_consecutive_zeros = 0;
1038 for (i = 0; i < 32; i += 2)
1040 int consecutive_zeros = 0;
1042 if (! (remainder & (3 << i)))
1044 while ((i < 32) && ! (remainder & (3 << i)))
1046 consecutive_zeros += 2;
1049 if (consecutive_zeros > best_consecutive_zeros)
1051 best_consecutive_zeros = consecutive_zeros;
1052 best_start = i - consecutive_zeros;
1058 /* Now start emitting the insns, starting with the one with the highest
1059 bit set: we do this so that the smallest number will be emitted last;
1060 this is more likely to be combinable with addressing insns. */
1068 if (remainder & (3 << (i - 2)))
1073 temp1 = remainder & ((0x0ff << end)
1074 | ((i < end) ? (0xff >> (32 - end)) : 0));
1075 remainder &= ~temp1;
1082 emit_insn (gen_rtx (SET, VOIDmode,
1083 new_src = (subtargets
1084 ? gen_reg_rtx (mode)
1086 GEN_INT (can_invert ? ~temp1 : temp1)));
1087 else if (code == MINUS)
1088 emit_insn (gen_rtx (SET, VOIDmode,
1089 new_src = (subtargets
1090 ? gen_reg_rtx (mode)
1092 gen_rtx (code, mode, GEN_INT (temp1),
1095 emit_insn (gen_rtx (SET, VOIDmode,
1096 new_src = (remainder
1098 ? gen_reg_rtx (mode)
1101 gen_rtx (code, mode, source,
1102 GEN_INT (can_invert ? ~temp1
1114 else if (code == MINUS)
1121 } while (remainder);
1126 /* Canonicalize a comparison so that we are more likely to recognize it.
1127 This can be done for a few constant compares, where we can make the
1128 immediate value easier to load. */
1130 arm_canonicalize_comparison (code, op1)
1134 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1144 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1146 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1148 *op1 = GEN_INT (i+1);
1149 return code == GT ? GE : LT;
1155 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1156 && (const_ok_for_arm (i-1) || const_ok_for_arm (- (i-1))))
1158 *op1 = GEN_INT (i-1);
1159 return code == GE ? GT : LE;
1165 if (i != ~((unsigned HOST_WIDE_INT) 0)
1166 && (const_ok_for_arm (i+1) || const_ok_for_arm (- (i+1))))
1168 *op1 = GEN_INT (i + 1);
1169 return code == GTU ? GEU : LTU;
1176 && (const_ok_for_arm (i - 1) || const_ok_for_arm (- (i - 1))))
1178 *op1 = GEN_INT (i - 1);
1179 return code == GEU ? GTU : LEU;
1191 /* Handle aggregates that are not laid out in a BLKmode element.
1192 This is a sub-element of RETURN_IN_MEMORY. */
1194 arm_return_in_memory (type)
1197 if (TREE_CODE (type) == RECORD_TYPE)
1201 /* For a struct, we can return in a register if every element was a
1203 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1204 if (TREE_CODE (field) != FIELD_DECL
1205 || ! DECL_BIT_FIELD_TYPE (field))
1210 else if (TREE_CODE (type) == UNION_TYPE)
1214 /* Unions can be returned in registers if every element is
1215 integral, or can be returned in an integer register. */
1216 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
1218 if (TREE_CODE (field) != FIELD_DECL
1219 || (AGGREGATE_TYPE_P (TREE_TYPE (field))
1220 && RETURN_IN_MEMORY (TREE_TYPE (field)))
1221 || FLOAT_TYPE_P (TREE_TYPE (field)))
1226 /* XXX Not sure what should be done for other aggregates, so put them in
1232 legitimate_pic_operand_p (x)
1235 if (CONSTANT_P (x) && flag_pic
1236 && (GET_CODE (x) == SYMBOL_REF
1237 || (GET_CODE (x) == CONST
1238 && GET_CODE (XEXP (x, 0)) == PLUS
1239 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
1246 legitimize_pic_address (orig, mode, reg)
1248 enum machine_mode mode;
1251 if (GET_CODE (orig) == SYMBOL_REF)
1253 rtx pic_ref, address;
1259 if (reload_in_progress || reload_completed)
1262 reg = gen_reg_rtx (Pmode);
1267 #ifdef AOF_ASSEMBLER
1268 /* The AOF assembler can generate relocations for these directly, and
1269 understands that the PIC register has to be added into the offset.
1271 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
1274 address = gen_reg_rtx (Pmode);
1278 emit_insn (gen_pic_load_addr (address, orig));
1280 pic_ref = gen_rtx (MEM, Pmode,
1281 gen_rtx (PLUS, Pmode, pic_offset_table_rtx, address));
1282 RTX_UNCHANGING_P (pic_ref) = 1;
1283 insn = emit_move_insn (reg, pic_ref);
1285 current_function_uses_pic_offset_table = 1;
1286 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1288 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
1292 else if (GET_CODE (orig) == CONST)
1296 if (GET_CODE (XEXP (orig, 0)) == PLUS
1297 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1302 if (reload_in_progress || reload_completed)
1305 reg = gen_reg_rtx (Pmode);
1308 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1310 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1311 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1312 base == reg ? 0 : reg);
1317 if (GET_CODE (offset) == CONST_INT)
1319 /* The base register doesn't really matter, we only want to
1320 test the index for the appropriate mode. */
1321 GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
1323 if (! reload_in_progress && ! reload_completed)
1324 offset = force_reg (Pmode, offset);
1329 if (GET_CODE (offset) == CONST_INT)
1330 return plus_constant_for_output (base, INTVAL (offset));
1333 if (GET_MODE_SIZE (mode) > 4
1334 && (GET_MODE_CLASS (mode) == MODE_INT
1335 || TARGET_SOFT_FLOAT))
1337 emit_insn (gen_addsi3 (reg, base, offset));
1341 return gen_rtx (PLUS, Pmode, base, offset);
1343 else if (GET_CODE (orig) == LABEL_REF)
1344 current_function_uses_pic_offset_table = 1;
1363 #ifndef AOF_ASSEMBLER
1364 rtx l1, pic_tmp, pic_tmp2, seq;
1365 rtx global_offset_table;
1367 if (current_function_uses_pic_offset_table == 0)
1374 l1 = gen_label_rtx ();
1376 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
1377 /* The PC contains 'dot'+8, but the label L1 is on the next
1378 instruction, so the offset is only 'dot'+4. */
1379 pic_tmp = gen_rtx (CONST, VOIDmode,
1380 gen_rtx (PLUS, Pmode,
1381 gen_rtx (LABEL_REF, VOIDmode, l1),
1383 pic_tmp2 = gen_rtx (CONST, VOIDmode,
1384 gen_rtx (PLUS, Pmode,
1385 global_offset_table,
1388 pic_rtx = gen_rtx (CONST, Pmode,
1389 gen_rtx (MINUS, Pmode, pic_tmp2, pic_tmp));
1391 emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
1392 emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx));
1395 seq = gen_sequence ();
1397 emit_insn_after (seq, get_insns ());
1399 /* Need to emit this whether or not we obey regdecls,
1400 since setjmp/longjmp can cause life info to screw up. */
1401 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
1402 #endif /* AOF_ASSEMBLER */
1405 #define REG_OR_SUBREG_REG(X) \
1406 (GET_CODE (X) == REG \
1407 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
1409 #define REG_OR_SUBREG_RTX(X) \
1410 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
1412 #define ARM_FRAME_RTX(X) \
1413 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1414 || (X) == arg_pointer_rtx)
1417 arm_rtx_costs (x, code, outer_code)
1419 enum rtx_code code, outer_code;
1421 enum machine_mode mode = GET_MODE (x);
1422 enum rtx_code subcode;
1428 /* Memory costs quite a lot for the first word, but subsequent words
1429 load at the equivalent of a single insn each. */
1430 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
1431 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
1438 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
1445 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
1447 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
1448 + ((GET_CODE (XEXP (x, 0)) == REG
1449 || (GET_CODE (XEXP (x, 0)) == SUBREG
1450 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1452 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
1453 || (GET_CODE (XEXP (x, 0)) == SUBREG
1454 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
1456 + ((GET_CODE (XEXP (x, 1)) == REG
1457 || (GET_CODE (XEXP (x, 1)) == SUBREG
1458 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
1459 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
1464 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
1465 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1466 || (GET_CODE (XEXP (x, 0)) == CONST_INT
1467 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
1470 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1471 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1472 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1473 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1475 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
1476 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
1477 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
1480 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
1481 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
1482 && REG_OR_SUBREG_REG (XEXP (x, 1))))
1483 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
1484 || subcode == ASHIFTRT || subcode == LSHIFTRT
1485 || subcode == ROTATE || subcode == ROTATERT
1487 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
1488 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
1489 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
1490 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
1491 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
1492 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1493 && REG_OR_SUBREG_REG (XEXP (x, 0))))
1498 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1499 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1500 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1501 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
1502 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
1506 case AND: case XOR: case IOR:
1509 /* Normally the frame registers will be spilt into reg+const during
1510 reload, so it is a bad idea to combine them with other instructions,
1511 since then they might not be moved outside of loops. As a compromise
1512 we allow integration with ops that have a constant as their second
1514 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
1515 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
1516 && GET_CODE (XEXP (x, 1)) != CONST_INT)
1517 || (REG_OR_SUBREG_REG (XEXP (x, 0))
1518 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
1522 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
1523 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1524 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1525 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1528 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
1529 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
1530 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
1531 || (GET_CODE (XEXP (x, 1)) == CONST_INT
1532 && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
1535 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
1536 return (1 + extra_cost
1537 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
1538 || subcode == LSHIFTRT || subcode == ASHIFTRT
1539 || subcode == ROTATE || subcode == ROTATERT
1541 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1542 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
1543 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
1544 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
1545 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
1546 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1552 /* There is no point basing this on the tuning, since it is always the
1553 fast variant if it exists at all */
1554 if (arm_fast_multiply && mode == DImode
1555 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
1556 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1557 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
1560 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1564 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1566 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
1567 & (unsigned HOST_WIDE_INT) 0xffffffff);
1568 int add_cost = const_ok_for_arm (i) ? 4 : 8;
1570 /* Tune as appropriate */
1571 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
1573 for (j = 0; i && j < 32; j += booth_unit_size)
1575 i >>= booth_unit_size;
1582 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
1583 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
1584 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
1587 if (arm_fast_multiply && mode == SImode
1588 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
1589 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1590 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
1591 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1592 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
1593 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
1598 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1599 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
1603 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1605 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
1608 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
1616 return 4 + (mode == DImode ? 4 : 0);
1619 if (GET_MODE (XEXP (x, 0)) == QImode)
1620 return (4 + (mode == DImode ? 4 : 0)
1621 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1624 switch (GET_MODE (XEXP (x, 0)))
1627 return (1 + (mode == DImode ? 4 : 0)
1628 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1631 return (4 + (mode == DImode ? 4 : 0)
1632 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1635 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
1648 arm_adjust_cost (insn, link, dep, cost)
1656 /* XXX This is not strictly true for the FPA. */
1657 if (REG_NOTE_KIND(link) == REG_DEP_ANTI
1658 || REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
1661 if ((i_pat = single_set (insn)) != NULL
1662 && GET_CODE (SET_SRC (i_pat)) == MEM
1663 && (d_pat = single_set (dep)) != NULL
1664 && GET_CODE (SET_DEST (d_pat)) == MEM)
1666 /* This is a load after a store, there is no conflict if the load reads
1667 from a cached area. Assume that loads from the stack, and from the
1668 constant pool are cached, and that others will miss. This is a
1671 /* debug_rtx (insn);
1674 fprintf (stderr, "costs %d\n", cost); */
1676 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
1677 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1678 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
1679 || reg_mentioned_p (hard_frame_pointer_rtx,
1680 XEXP (SET_SRC (i_pat), 0)))
1682 /* fprintf (stderr, "***** Now 1\n"); */
1690 /* This code has been fixed for cross compilation. */
1692 static int fpa_consts_inited = 0;
1694 char *strings_fpa[8] = {
1696 "4", "5", "0.5", "10"
1699 static REAL_VALUE_TYPE values_fpa[8];
1707 for (i = 0; i < 8; i++)
1709 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
1713 fpa_consts_inited = 1;
1716 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1719 const_double_rtx_ok_for_fpu (x)
1725 if (!fpa_consts_inited)
1728 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1729 if (REAL_VALUE_MINUS_ZERO (r))
1732 for (i = 0; i < 8; i++)
1733 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1739 /* Return TRUE if rtx X is a valid immediate FPU constant. */
1742 neg_const_double_rtx_ok_for_fpu (x)
1748 if (!fpa_consts_inited)
1751 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
1752 r = REAL_VALUE_NEGATE (r);
1753 if (REAL_VALUE_MINUS_ZERO (r))
1756 for (i = 0; i < 8; i++)
1757 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
1763 /* Predicates for `match_operand' and `match_operator'. */
1765 /* s_register_operand is the same as register_operand, but it doesn't accept
1768 This function exists because at the time it was put in it led to better
1769 code. SUBREG(MEM) always needs a reload in the places where
1770 s_register_operand is used, and this seemed to lead to excessive
1774 s_register_operand (op, mode)
1776 enum machine_mode mode;
1778 if (GET_MODE (op) != mode && mode != VOIDmode)
1781 if (GET_CODE (op) == SUBREG)
1782 op = SUBREG_REG (op);
1784 /* We don't consider registers whose class is NO_REGS
1785 to be a register operand. */
1786 return (GET_CODE (op) == REG
1787 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1788 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1791 /* Only accept reg, subreg(reg), const_int. */
1794 reg_or_int_operand (op, mode)
1796 enum machine_mode mode;
1798 if (GET_CODE (op) == CONST_INT)
1801 if (GET_MODE (op) != mode && mode != VOIDmode)
1804 if (GET_CODE (op) == SUBREG)
1805 op = SUBREG_REG (op);
1807 /* We don't consider registers whose class is NO_REGS
1808 to be a register operand. */
1809 return (GET_CODE (op) == REG
1810 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1811 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1814 /* Return 1 if OP is an item in memory, given that we are in reload. */
1817 reload_memory_operand (op, mode)
1819 enum machine_mode mode;
1821 int regno = true_regnum (op);
1823 return (! CONSTANT_P (op)
1825 || (GET_CODE (op) == REG
1826 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
1829 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
1830 memory access (architecture V4) */
1832 bad_signed_byte_operand (op, mode)
1834 enum machine_mode mode;
1836 if (! memory_operand (op, mode) || GET_CODE (op) != MEM)
1841 /* A sum of anything more complex than reg + reg or reg + const is bad */
1842 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
1843 && (! s_register_operand (XEXP (op, 0), VOIDmode)
1844 || (! s_register_operand (XEXP (op, 1), VOIDmode)
1845 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
1848 /* Big constants are also bad */
1849 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
1850 && (INTVAL (XEXP (op, 1)) > 0xff
1851 || -INTVAL (XEXP (op, 1)) > 0xff))
1854 /* Everything else is good, or can will automatically be made so. */
1858 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
1861 arm_rhs_operand (op, mode)
1863 enum machine_mode mode;
1865 return (s_register_operand (op, mode)
1866 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
1869 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
1873 arm_rhsm_operand (op, mode)
1875 enum machine_mode mode;
1877 return (s_register_operand (op, mode)
1878 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
1879 || memory_operand (op, mode));
1882 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
1883 constant that is valid when negated. */
1886 arm_add_operand (op, mode)
1888 enum machine_mode mode;
1890 return (s_register_operand (op, mode)
1891 || (GET_CODE (op) == CONST_INT
1892 && (const_ok_for_arm (INTVAL (op))
1893 || const_ok_for_arm (-INTVAL (op)))));
1897 arm_not_operand (op, mode)
1899 enum machine_mode mode;
1901 return (s_register_operand (op, mode)
1902 || (GET_CODE (op) == CONST_INT
1903 && (const_ok_for_arm (INTVAL (op))
1904 || const_ok_for_arm (~INTVAL (op)))));
1907 /* Return TRUE if the operand is a memory reference which contains an
1908 offsettable address. */
1910 offsettable_memory_operand (op, mode)
1912 enum machine_mode mode;
1914 if (mode == VOIDmode)
1915 mode = GET_MODE (op);
1917 return (mode == GET_MODE (op)
1918 && GET_CODE (op) == MEM
1919 && offsettable_address_p (reload_completed | reload_in_progress,
1920 mode, XEXP (op, 0)));
1923 /* Return TRUE if the operand is a memory reference which is, or can be
1924 made word aligned by adjusting the offset. */
1926 alignable_memory_operand (op, mode)
1928 enum machine_mode mode;
1932 if (mode == VOIDmode)
1933 mode = GET_MODE (op);
1935 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
1940 return ((GET_CODE (reg = op) == REG
1941 || (GET_CODE (op) == SUBREG
1942 && GET_CODE (reg = SUBREG_REG (op)) == REG)
1943 || (GET_CODE (op) == PLUS
1944 && GET_CODE (XEXP (op, 1)) == CONST_INT
1945 && (GET_CODE (reg = XEXP (op, 0)) == REG
1946 || (GET_CODE (XEXP (op, 0)) == SUBREG
1947 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
1948 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 4);
1951 /* Similar to s_register_operand, but does not allow hard integer
1954 f_register_operand (op, mode)
1956 enum machine_mode mode;
1958 if (GET_MODE (op) != mode && mode != VOIDmode)
1961 if (GET_CODE (op) == SUBREG)
1962 op = SUBREG_REG (op);
1964 /* We don't consider registers whose class is NO_REGS
1965 to be a register operand. */
1966 return (GET_CODE (op) == REG
1967 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1968 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
1971 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
1974 fpu_rhs_operand (op, mode)
1976 enum machine_mode mode;
1978 if (s_register_operand (op, mode))
1980 else if (GET_CODE (op) == CONST_DOUBLE)
1981 return (const_double_rtx_ok_for_fpu (op));
1987 fpu_add_operand (op, mode)
1989 enum machine_mode mode;
1991 if (s_register_operand (op, mode))
1993 else if (GET_CODE (op) == CONST_DOUBLE)
1994 return (const_double_rtx_ok_for_fpu (op)
1995 || neg_const_double_rtx_ok_for_fpu (op));
2000 /* Return nonzero if OP is a constant power of two. */
2003 power_of_two_operand (op, mode)
2005 enum machine_mode mode;
2007 if (GET_CODE (op) == CONST_INT)
2009 HOST_WIDE_INT value = INTVAL(op);
2010 return value != 0 && (value & (value - 1)) == 0;
2015 /* Return TRUE for a valid operand of a DImode operation.
2016 Either: REG, CONST_DOUBLE or MEM(DImode_address).
2017 Note that this disallows MEM(REG+REG), but allows
2018 MEM(PRE/POST_INC/DEC(REG)). */
2021 di_operand (op, mode)
2023 enum machine_mode mode;
2025 if (s_register_operand (op, mode))
2028 switch (GET_CODE (op))
2035 return memory_address_p (DImode, XEXP (op, 0));
2042 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2043 Either: REG, CONST_DOUBLE or MEM(DImode_address).
2044 Note that this disallows MEM(REG+REG), but allows
2045 MEM(PRE/POST_INC/DEC(REG)). */
2048 soft_df_operand (op, mode)
2050 enum machine_mode mode;
2052 if (s_register_operand (op, mode))
2055 switch (GET_CODE (op))
2061 return memory_address_p (DFmode, XEXP (op, 0));
2068 /* Return TRUE for valid index operands. */
2071 index_operand (op, mode)
2073 enum machine_mode mode;
2075 return (s_register_operand(op, mode)
2076 || (immediate_operand (op, mode)
2077 && INTVAL (op) < 4096 && INTVAL (op) > -4096));
2080 /* Return TRUE for valid shifts by a constant. This also accepts any
2081 power of two on the (somewhat overly relaxed) assumption that the
2082 shift operator in this case was a mult. */
2085 const_shift_operand (op, mode)
2087 enum machine_mode mode;
2089 return (power_of_two_operand (op, mode)
2090 || (immediate_operand (op, mode)
2091 && (INTVAL (op) < 32 && INTVAL (op) > 0)));
2094 /* Return TRUE for arithmetic operators which can be combined with a multiply
2098 shiftable_operator (x, mode)
2100 enum machine_mode mode;
2102 if (GET_MODE (x) != mode)
2106 enum rtx_code code = GET_CODE (x);
2108 return (code == PLUS || code == MINUS
2109 || code == IOR || code == XOR || code == AND);
2113 /* Return TRUE for shift operators. */
2116 shift_operator (x, mode)
2118 enum machine_mode mode;
2120 if (GET_MODE (x) != mode)
2124 enum rtx_code code = GET_CODE (x);
2127 return power_of_two_operand (XEXP (x, 1));
2129 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
2130 || code == ROTATERT);
2134 int equality_operator (x, mode)
2136 enum machine_mode mode;
2138 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
2141 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
2144 minmax_operator (x, mode)
2146 enum machine_mode mode;
2148 enum rtx_code code = GET_CODE (x);
2150 if (GET_MODE (x) != mode)
2153 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
2156 /* return TRUE if x is EQ or NE */
2158 /* Return TRUE if this is the condition code register, if we aren't given
2159 a mode, accept any class CCmode register */
2162 cc_register (x, mode)
2164 enum machine_mode mode;
2166 if (mode == VOIDmode)
2168 mode = GET_MODE (x);
2169 if (GET_MODE_CLASS (mode) != MODE_CC)
2173 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2179 /* Return TRUE if this is the condition code register, if we aren't given
2180 a mode, accept any class CCmode register which indicates a dominance
2184 dominant_cc_register (x, mode)
2186 enum machine_mode mode;
2188 if (mode == VOIDmode)
2190 mode = GET_MODE (x);
2191 if (GET_MODE_CLASS (mode) != MODE_CC)
2195 if (mode != CC_DNEmode && mode != CC_DEQmode
2196 && mode != CC_DLEmode && mode != CC_DLTmode
2197 && mode != CC_DGEmode && mode != CC_DGTmode
2198 && mode != CC_DLEUmode && mode != CC_DLTUmode
2199 && mode != CC_DGEUmode && mode != CC_DGTUmode)
2202 if (mode == GET_MODE (x) && GET_CODE (x) == REG && REGNO (x) == 24)
2208 /* Return TRUE if X references a SYMBOL_REF. */
2210 symbol_mentioned_p (x)
2216 if (GET_CODE (x) == SYMBOL_REF)
2219 fmt = GET_RTX_FORMAT (GET_CODE (x));
2220 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2226 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2227 if (symbol_mentioned_p (XVECEXP (x, i, j)))
2230 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
2237 /* Return TRUE if X references a LABEL_REF. */
2239 label_mentioned_p (x)
2245 if (GET_CODE (x) == LABEL_REF)
2248 fmt = GET_RTX_FORMAT (GET_CODE (x));
2249 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2255 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2256 if (label_mentioned_p (XVECEXP (x, i, j)))
2259 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
2270 enum rtx_code code = GET_CODE (x);
2274 else if (code == SMIN)
2276 else if (code == UMIN)
2278 else if (code == UMAX)
2284 /* Return 1 if memory locations are adjacent */
2287 adjacent_mem_locations (a, b)
2290 int val0 = 0, val1 = 0;
2293 if ((GET_CODE (XEXP (a, 0)) == REG
2294 || (GET_CODE (XEXP (a, 0)) == PLUS
2295 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
2296 && (GET_CODE (XEXP (b, 0)) == REG
2297 || (GET_CODE (XEXP (b, 0)) == PLUS
2298 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
2300 if (GET_CODE (XEXP (a, 0)) == PLUS)
2302 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
2303 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
2306 reg0 = REGNO (XEXP (a, 0));
2307 if (GET_CODE (XEXP (b, 0)) == PLUS)
2309 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
2310 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
2313 reg1 = REGNO (XEXP (b, 0));
2314 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
2319 /* Return 1 if OP is a load multiple operation. It is known to be
2320 parallel and the first section will be tested. */
2323 load_multiple_operation (op, mode)
2325 enum machine_mode mode;
2327 HOST_WIDE_INT count = XVECLEN (op, 0);
2330 HOST_WIDE_INT i = 1, base = 0;
2334 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2337 /* Check to see if this might be a write-back */
2338 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2343 /* Now check it more carefully */
2344 if (GET_CODE (SET_DEST (elt)) != REG
2345 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2346 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2347 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2348 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2349 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2350 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2351 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2352 != REGNO (SET_DEST (elt)))
2358 /* Perform a quick check so we don't blow up below. */
2360 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2361 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
2362 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
2365 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
2366 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
2368 for (; i < count; i++)
2370 elt = XVECEXP (op, 0, i);
2372 if (GET_CODE (elt) != SET
2373 || GET_CODE (SET_DEST (elt)) != REG
2374 || GET_MODE (SET_DEST (elt)) != SImode
2375 || REGNO (SET_DEST (elt)) != dest_regno + i - base
2376 || GET_CODE (SET_SRC (elt)) != MEM
2377 || GET_MODE (SET_SRC (elt)) != SImode
2378 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
2379 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
2380 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
2381 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
2388 /* Return 1 if OP is a store multiple operation. It is known to be
2389 parallel and the first section will be tested. */
2392 store_multiple_operation (op, mode)
2394 enum machine_mode mode;
2396 HOST_WIDE_INT count = XVECLEN (op, 0);
2399 HOST_WIDE_INT i = 1, base = 0;
2403 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
2406 /* Check to see if this might be a write-back */
2407 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
2412 /* Now check it more carefully */
2413 if (GET_CODE (SET_DEST (elt)) != REG
2414 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
2415 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
2416 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
2417 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 2) * 4
2418 || GET_CODE (XVECEXP (op, 0, count - 1)) != CLOBBER
2419 || GET_CODE (XEXP (XVECEXP (op, 0, count - 1), 0)) != REG
2420 || REGNO (XEXP (XVECEXP (op, 0, count - 1), 0))
2421 != REGNO (SET_DEST (elt)))
2427 /* Perform a quick check so we don't blow up below. */
2429 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
2430 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
2431 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
2434 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
2435 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
2437 for (; i < count; i++)
2439 elt = XVECEXP (op, 0, i);
2441 if (GET_CODE (elt) != SET
2442 || GET_CODE (SET_SRC (elt)) != REG
2443 || GET_MODE (SET_SRC (elt)) != SImode
2444 || REGNO (SET_SRC (elt)) != src_regno + i - base
2445 || GET_CODE (SET_DEST (elt)) != MEM
2446 || GET_MODE (SET_DEST (elt)) != SImode
2447 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
2448 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
2449 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
2450 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
2458 load_multiple_sequence (operands, nops, regs, base, load_offset)
2463 HOST_WIDE_INT *load_offset;
2465 int unsorted_regs[4];
2466 HOST_WIDE_INT unsorted_offsets[4];
2471 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2472 extended if required. */
2473 if (nops < 2 || nops > 4)
2476 /* Loop over the operands and check that the memory references are
2477 suitable (ie immediate offsets from the same base register). At
2478 the same time, extract the target register, and the memory
2480 for (i = 0; i < nops; i++)
2485 /* Convert a subreg of a mem into the mem itself. */
2486 if (GET_CODE (operands[nops + i]) == SUBREG)
2487 operands[nops + i] = alter_subreg(operands[nops + i]);
2489 if (GET_CODE (operands[nops + i]) != MEM)
2492 /* Don't reorder volatile memory references; it doesn't seem worth
2493 looking for the case where the order is ok anyway. */
2494 if (MEM_VOLATILE_P (operands[nops + i]))
2497 offset = const0_rtx;
2499 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2500 || (GET_CODE (reg) == SUBREG
2501 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2502 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2503 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2505 || (GET_CODE (reg) == SUBREG
2506 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2507 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2512 base_reg = REGNO(reg);
2513 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2514 ? REGNO (operands[i])
2515 : REGNO (SUBREG_REG (operands[i])));
2520 if (base_reg != REGNO (reg))
2521 /* Not addressed from the same base register. */
2524 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2525 ? REGNO (operands[i])
2526 : REGNO (SUBREG_REG (operands[i])));
2527 if (unsorted_regs[i] < unsorted_regs[order[0]])
2531 /* If it isn't an integer register, or if it overwrites the
2532 base register but isn't the last insn in the list, then
2533 we can't do this. */
2534 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
2535 || (i != nops - 1 && unsorted_regs[i] == base_reg))
2538 unsorted_offsets[i] = INTVAL (offset);
2541 /* Not a suitable memory address. */
2545 /* All the useful information has now been extracted from the
2546 operands into unsorted_regs and unsorted_offsets; additionally,
2547 order[0] has been set to the lowest numbered register in the
2548 list. Sort the registers into order, and check that the memory
2549 offsets are ascending and adjacent. */
2551 for (i = 1; i < nops; i++)
2555 order[i] = order[i - 1];
2556 for (j = 0; j < nops; j++)
2557 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2558 && (order[i] == order[i - 1]
2559 || unsorted_regs[j] < unsorted_regs[order[i]]))
2562 /* Have we found a suitable register? if not, one must be used more
2564 if (order[i] == order[i - 1])
2567 /* Is the memory address adjacent and ascending? */
2568 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2576 for (i = 0; i < nops; i++)
2577 regs[i] = unsorted_regs[order[i]];
2579 *load_offset = unsorted_offsets[order[0]];
2582 if (unsorted_offsets[order[0]] == 0)
2583 return 1; /* ldmia */
2585 if (unsorted_offsets[order[0]] == 4)
2586 return 2; /* ldmib */
2588 if (unsorted_offsets[order[nops - 1]] == 0)
2589 return 3; /* ldmda */
2591 if (unsorted_offsets[order[nops - 1]] == -4)
2592 return 4; /* ldmdb */
2594 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if
2595 the offset isn't small enough */
2597 && (arm_cpu == PROCESSOR_ARM8 || arm_cpu == PROCESSOR_ARM9
2598 || arm_cpu == PROCESSOR_STARM))
2601 /* Can't do it without setting up the offset, only do this if it takes
2602 no more than one insn. */
2603 return (const_ok_for_arm (unsorted_offsets[order[0]])
2604 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
2608 emit_ldm_seq (operands, nops)
2614 HOST_WIDE_INT offset;
2618 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2621 strcpy (buf, "ldm%?ia\t");
2625 strcpy (buf, "ldm%?ib\t");
2629 strcpy (buf, "ldm%?da\t");
2633 strcpy (buf, "ldm%?db\t");
2638 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2639 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2642 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
2643 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
2645 output_asm_insn (buf, operands);
2647 strcpy (buf, "ldm%?ia\t");
2654 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2655 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2657 for (i = 1; i < nops; i++)
2658 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2659 reg_names[regs[i]]);
2661 strcat (buf, "}\t%@ phole ldm");
2663 output_asm_insn (buf, operands);
2668 store_multiple_sequence (operands, nops, regs, base, load_offset)
2673 HOST_WIDE_INT *load_offset;
2675 int unsorted_regs[4];
2676 HOST_WIDE_INT unsorted_offsets[4];
2681 /* Can only handle 2, 3, or 4 insns at present, though could be easily
2682 extended if required. */
2683 if (nops < 2 || nops > 4)
2686 /* Loop over the operands and check that the memory references are
2687 suitable (ie immediate offsets from the same base register). At
2688 the same time, extract the target register, and the memory
2690 for (i = 0; i < nops; i++)
2695 /* Convert a subreg of a mem into the mem itself. */
2696 if (GET_CODE (operands[nops + i]) == SUBREG)
2697 operands[nops + i] = alter_subreg(operands[nops + i]);
2699 if (GET_CODE (operands[nops + i]) != MEM)
2702 /* Don't reorder volatile memory references; it doesn't seem worth
2703 looking for the case where the order is ok anyway. */
2704 if (MEM_VOLATILE_P (operands[nops + i]))
2707 offset = const0_rtx;
2709 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
2710 || (GET_CODE (reg) == SUBREG
2711 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2712 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
2713 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
2715 || (GET_CODE (reg) == SUBREG
2716 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
2717 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
2722 base_reg = REGNO(reg);
2723 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
2724 ? REGNO (operands[i])
2725 : REGNO (SUBREG_REG (operands[i])));
2730 if (base_reg != REGNO (reg))
2731 /* Not addressed from the same base register. */
2734 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
2735 ? REGNO (operands[i])
2736 : REGNO (SUBREG_REG (operands[i])));
2737 if (unsorted_regs[i] < unsorted_regs[order[0]])
2741 /* If it isn't an integer register, then we can't do this. */
2742 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
2745 unsorted_offsets[i] = INTVAL (offset);
2748 /* Not a suitable memory address. */
2752 /* All the useful information has now been extracted from the
2753 operands into unsorted_regs and unsorted_offsets; additionally,
2754 order[0] has been set to the lowest numbered register in the
2755 list. Sort the registers into order, and check that the memory
2756 offsets are ascending and adjacent. */
2758 for (i = 1; i < nops; i++)
2762 order[i] = order[i - 1];
2763 for (j = 0; j < nops; j++)
2764 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
2765 && (order[i] == order[i - 1]
2766 || unsorted_regs[j] < unsorted_regs[order[i]]))
2769 /* Have we found a suitable register? if not, one must be used more
2771 if (order[i] == order[i - 1])
2774 /* Is the memory address adjacent and ascending? */
2775 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
2783 for (i = 0; i < nops; i++)
2784 regs[i] = unsorted_regs[order[i]];
2786 *load_offset = unsorted_offsets[order[0]];
2789 if (unsorted_offsets[order[0]] == 0)
2790 return 1; /* stmia */
2792 if (unsorted_offsets[order[0]] == 4)
2793 return 2; /* stmib */
2795 if (unsorted_offsets[order[nops - 1]] == 0)
2796 return 3; /* stmda */
2798 if (unsorted_offsets[order[nops - 1]] == -4)
2799 return 4; /* stmdb */
2805 emit_stm_seq (operands, nops)
2811 HOST_WIDE_INT offset;
2815 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
2818 strcpy (buf, "stm%?ia\t");
2822 strcpy (buf, "stm%?ib\t");
2826 strcpy (buf, "stm%?da\t");
2830 strcpy (buf, "stm%?db\t");
2837 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
2838 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
2840 for (i = 1; i < nops; i++)
2841 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
2842 reg_names[regs[i]]);
2844 strcat (buf, "}\t%@ phole stm");
2846 output_asm_insn (buf, operands);
2851 multi_register_push (op, mode)
2853 enum machine_mode mode;
2855 if (GET_CODE (op) != PARALLEL
2856 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
2857 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
2858 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != 2))
2865 /* Routines for use with attributes */
2867 /* Return nonzero if ATTR is a valid attribute for DECL.
2868 ATTRIBUTES are any existing attributes and ARGS are the arguments
2871 Supported attributes:
2873 naked: don't output any prologue or epilogue code, the user is assumed
2874 to do the right thing. */
2877 arm_valid_machine_decl_attribute (decl, attributes, attr, args)
2883 if (args != NULL_TREE)
2886 if (is_attribute_p ("naked", attr))
2887 return TREE_CODE (decl) == FUNCTION_DECL;
2891 /* Return non-zero if FUNC is a naked function. */
2894 arm_naked_function_p (func)
2899 if (TREE_CODE (func) != FUNCTION_DECL)
2902 a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
2903 return a != NULL_TREE;
2906 /* Routines for use in generating RTL */
2909 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
2910 in_struct_p, scalar_p)
2922 int sign = up ? 1 : -1;
2925 result = gen_rtx (PARALLEL, VOIDmode,
2926 rtvec_alloc (count + (write_back ? 2 : 0)));
2929 XVECEXP (result, 0, 0)
2930 = gen_rtx (SET, GET_MODE (from), from,
2931 plus_constant (from, count * 4 * sign));
2936 for (j = 0; i < count; i++, j++)
2938 mem = gen_rtx (MEM, SImode, plus_constant (from, j * 4 * sign));
2939 RTX_UNCHANGING_P (mem) = unchanging_p;
2940 MEM_IN_STRUCT_P (mem) = in_struct_p;
2941 MEM_SCALAR_P (mem) = scalar_p;
2942 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode,
2943 gen_rtx (REG, SImode, base_regno + j),
2948 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, from);
2954 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
2955 in_struct_p, scalar_p)
2967 int sign = up ? 1 : -1;
2970 result = gen_rtx (PARALLEL, VOIDmode,
2971 rtvec_alloc (count + (write_back ? 2 : 0)));
2974 XVECEXP (result, 0, 0)
2975 = gen_rtx (SET, GET_MODE (to), to,
2976 plus_constant (to, count * 4 * sign));
2981 for (j = 0; i < count; i++, j++)
2983 mem = gen_rtx (MEM, SImode, plus_constant (to, j * 4 * sign));
2984 RTX_UNCHANGING_P (mem) = unchanging_p;
2985 MEM_IN_STRUCT_P (mem) = in_struct_p;
2986 MEM_SCALAR_P (mem) = scalar_p;
2988 XVECEXP (result, 0, i) = gen_rtx (SET, VOIDmode, mem,
2989 gen_rtx (REG, SImode, base_regno + j));
2993 XVECEXP (result, 0, i) = gen_rtx (CLOBBER, SImode, to);
2999 arm_gen_movstrqi (operands)
3002 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
3005 rtx st_src, st_dst, fin_src, fin_dst;
3006 rtx part_bytes_reg = NULL;
3008 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
3009 int dst_scalar_p, src_scalar_p;
3011 if (GET_CODE (operands[2]) != CONST_INT
3012 || GET_CODE (operands[3]) != CONST_INT
3013 || INTVAL (operands[2]) > 64
3014 || INTVAL (operands[3]) & 3)
3017 st_dst = XEXP (operands[0], 0);
3018 st_src = XEXP (operands[1], 0);
3020 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
3021 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
3022 dst_scalar_p = MEM_SCALAR_P (operands[0]);
3023 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
3024 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
3025 src_scalar_p = MEM_SCALAR_P (operands[1]);
3027 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
3028 fin_src = src = copy_to_mode_reg (SImode, st_src);
3030 in_words_to_go = (INTVAL (operands[2]) + 3) / 4;
3031 out_words_to_go = INTVAL (operands[2]) / 4;
3032 last_bytes = INTVAL (operands[2]) & 3;
3034 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
3035 part_bytes_reg = gen_rtx (REG, SImode, (in_words_to_go - 1) & 3);
3037 for (i = 0; in_words_to_go >= 2; i+=4)
3039 if (in_words_to_go > 4)
3040 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
3045 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
3046 FALSE, src_unchanging_p,
3047 src_in_struct_p, src_scalar_p));
3049 if (out_words_to_go)
3051 if (out_words_to_go > 4)
3052 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
3056 else if (out_words_to_go != 1)
3057 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
3066 mem = gen_rtx (MEM, SImode, dst);
3067 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3068 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3069 MEM_SCALAR_P (mem) = dst_scalar_p;
3070 emit_move_insn (mem, gen_rtx (REG, SImode, 0));
3071 if (last_bytes != 0)
3072 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
3076 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
3077 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
3080 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3081 if (out_words_to_go)
3085 mem = gen_rtx (MEM, SImode, src);
3086 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3087 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3088 MEM_SCALAR_P (mem) = src_scalar_p;
3089 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
3090 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
3092 mem = gen_rtx (MEM, SImode, dst);
3093 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3094 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3095 MEM_SCALAR_P (mem) = dst_scalar_p;
3096 emit_move_insn (mem, sreg);
3097 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
3100 if (in_words_to_go) /* Sanity check */
3106 if (in_words_to_go < 0)
3109 mem = gen_rtx (MEM, SImode, src);
3110 RTX_UNCHANGING_P (mem) = src_unchanging_p;
3111 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
3112 MEM_SCALAR_P (mem) = src_scalar_p;
3113 part_bytes_reg = copy_to_mode_reg (SImode, mem);
3116 if (BYTES_BIG_ENDIAN && last_bytes)
3118 rtx tmp = gen_reg_rtx (SImode);
3120 if (part_bytes_reg == NULL)
3123 /* The bytes we want are in the top end of the word */
3124 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
3125 GEN_INT (8 * (4 - last_bytes))));
3126 part_bytes_reg = tmp;
3130 mem = gen_rtx (MEM, QImode, plus_constant (dst, last_bytes - 1));
3131 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3132 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3133 MEM_SCALAR_P (mem) = dst_scalar_p;
3134 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3137 tmp = gen_reg_rtx (SImode);
3138 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3139 part_bytes_reg = tmp;
3148 if (part_bytes_reg == NULL)
3151 mem = gen_rtx (MEM, QImode, dst);
3152 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
3153 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
3154 MEM_SCALAR_P (mem) = dst_scalar_p;
3155 emit_move_insn (mem, gen_rtx (SUBREG, QImode, part_bytes_reg, 0));
3158 rtx tmp = gen_reg_rtx (SImode);
3160 emit_insn (gen_addsi3 (dst, dst, const1_rtx));
3161 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
3162 part_bytes_reg = tmp;
3170 /* Generate a memory reference for a half word, such that it will be loaded
3171 into the top 16 bits of the word. We can assume that the address is
3172 known to be alignable and of the form reg, or plus (reg, const). */
3174 gen_rotated_half_load (memref)
3177 HOST_WIDE_INT offset = 0;
3178 rtx base = XEXP (memref, 0);
3180 if (GET_CODE (base) == PLUS)
3182 offset = INTVAL (XEXP (base, 1));
3183 base = XEXP (base, 0);
3186 /* If we aren't allowed to generate unaligned addresses, then fail. */
3187 if (TARGET_SHORT_BY_BYTES
3188 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
3191 base = gen_rtx (MEM, SImode, plus_constant (base, offset & ~2));
3193 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
3196 return gen_rtx (ROTATE, SImode, base, GEN_INT (16));
3199 static enum machine_mode
3200 select_dominance_cc_mode (op, x, y, cond_or)
3204 HOST_WIDE_INT cond_or;
3206 enum rtx_code cond1, cond2;
3209 /* Currently we will probably get the wrong result if the individual
3210 comparisons are not simple. This also ensures that it is safe to
3211 reverse a comparison if necessary. */
3212 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
3214 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
3219 cond1 = reverse_condition (cond1);
3221 /* If the comparisons are not equal, and one doesn't dominate the other,
3222 then we can't do this. */
3224 && ! comparison_dominates_p (cond1, cond2)
3225 && (swapped = 1, ! comparison_dominates_p (cond2, cond1)))
3230 enum rtx_code temp = cond1;
3238 if (cond2 == EQ || ! cond_or)
3243 case LE: return CC_DLEmode;
3244 case LEU: return CC_DLEUmode;
3245 case GE: return CC_DGEmode;
3246 case GEU: return CC_DGEUmode;
3253 if (cond2 == LT || ! cond_or)
3262 if (cond2 == GT || ! cond_or)
3271 if (cond2 == LTU || ! cond_or)
3280 if (cond2 == GTU || ! cond_or)
3288 /* The remaining cases only occur when both comparisons are the
3313 arm_select_cc_mode (op, x, y)
3318 /* All floating point compares return CCFP if it is an equality
3319 comparison, and CCFPE otherwise. */
3320 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3321 return (op == EQ || op == NE) ? CCFPmode : CCFPEmode;
3323 /* A compare with a shifted operand. Because of canonicalization, the
3324 comparison will have to be swapped when we emit the assembler. */
3325 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
3326 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3327 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
3328 || GET_CODE (x) == ROTATERT))
3331 /* This is a special case that is used by combine to allow a
3332 comparison of a shifted byte load to be split into a zero-extend
3333 followed by a comparison of the shifted integer (only valid for
3334 equalities and unsigned inequalities). */
3335 if (GET_MODE (x) == SImode
3336 && GET_CODE (x) == ASHIFT
3337 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
3338 && GET_CODE (XEXP (x, 0)) == SUBREG
3339 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
3340 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
3341 && (op == EQ || op == NE
3342 || op == GEU || op == GTU || op == LTU || op == LEU)
3343 && GET_CODE (y) == CONST_INT)
3346 /* An operation that sets the condition codes as a side-effect, the
3347 V flag is not set correctly, so we can only use comparisons where
3348 this doesn't matter. (For LT and GE we can use "mi" and "pl"
3350 if (GET_MODE (x) == SImode
3352 && (op == EQ || op == NE || op == LT || op == GE)
3353 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
3354 || GET_CODE (x) == AND || GET_CODE (x) == IOR
3355 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
3356 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
3357 || GET_CODE (x) == LSHIFTRT
3358 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
3359 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
3362 /* A construct for a conditional compare, if the false arm contains
3363 0, then both conditions must be true, otherwise either condition
3364 must be true. Not all conditions are possible, so CCmode is
3365 returned if it can't be done. */
3366 if (GET_CODE (x) == IF_THEN_ELSE
3367 && (XEXP (x, 2) == const0_rtx
3368 || XEXP (x, 2) == const1_rtx)
3369 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3370 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
3371 return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
3372 INTVAL (XEXP (x, 2)));
3374 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
3377 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
3378 && GET_CODE (x) == PLUS
3379 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
3385 /* X and Y are two things to compare using CODE. Emit the compare insn and
3386 return the rtx for register 0 in the proper mode. FP means this is a
3387 floating point compare: I don't think that it is needed on the arm. */
3390 gen_compare_reg (code, x, y, fp)
3395 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
3396 rtx cc_reg = gen_rtx (REG, mode, 24);
3398 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
3399 gen_rtx (COMPARE, mode, x, y)));
3405 arm_reload_in_hi (operands)
3408 rtx base = find_replacement (&XEXP (operands[1], 0));
3410 emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx (MEM, QImode, base)));
3411 /* Handle the case where the address is too complex to be offset by 1. */
3412 if (GET_CODE (base) == MINUS
3413 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
3415 rtx base_plus = gen_rtx (REG, SImode, REGNO (operands[0]));
3417 emit_insn (gen_rtx (SET, VOIDmode, base_plus, base));
3421 emit_insn (gen_zero_extendqisi2 (gen_rtx (SUBREG, SImode, operands[0], 0),
3422 gen_rtx (MEM, QImode,
3423 plus_constant (base, 1))));
3424 if (BYTES_BIG_ENDIAN)
3425 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3427 gen_rtx (IOR, SImode,
3428 gen_rtx (ASHIFT, SImode,
3429 gen_rtx (SUBREG, SImode,
3434 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode,
3436 gen_rtx (IOR, SImode,
3437 gen_rtx (ASHIFT, SImode,
3440 gen_rtx (SUBREG, SImode, operands[0], 0))));
3444 arm_reload_out_hi (operands)
3447 rtx base = find_replacement (&XEXP (operands[0], 0));
3449 if (BYTES_BIG_ENDIAN)
3451 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3452 gen_rtx (SUBREG, QImode, operands[1], 0)));
3453 emit_insn (gen_lshrsi3 (operands[2],
3454 gen_rtx (SUBREG, SImode, operands[1], 0),
3456 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3457 gen_rtx (SUBREG, QImode, operands[2], 0)));
3461 emit_insn (gen_movqi (gen_rtx (MEM, QImode, base),
3462 gen_rtx (SUBREG, QImode, operands[1], 0)));
3463 emit_insn (gen_lshrsi3 (operands[2],
3464 gen_rtx (SUBREG, SImode, operands[1], 0),
3466 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (base, 1)),
3467 gen_rtx (SUBREG, QImode, operands[2], 0)));
3471 /* Routines for manipulation of the constant pool. */
3472 /* This is unashamedly hacked from the version in sh.c, since the problem is
3473 extremely similar. */
3475 /* Arm instructions cannot load a large constant into a register,
3476 constants have to come from a pc relative load. The reference of a pc
3477 relative load instruction must be less than 1k infront of the instruction.
3478 This means that we often have to dump a constant inside a function, and
3479 generate code to branch around it.
3481 It is important to minimize this, since the branches will slow things
3482 down and make things bigger.
3484 Worst case code looks like:
3500 We fix this by performing a scan before scheduling, which notices which
3501 instructions need to have their operands fetched from the constant table
3502 and builds the table.
3507 scan, find an instruction which needs a pcrel move. Look forward, find th
3508 last barrier which is within MAX_COUNT bytes of the requirement.
3509 If there isn't one, make one. Process all the instructions between
3510 the find and the barrier.
3512 In the above example, we can tell that L3 is within 1k of L1, so
3513 the first move can be shrunk from the 2 insn+constant sequence into
3514 just 1 insn, and the constant moved to L3 to make:
3525 Then the second move becomes the target for the shortening process.
3531 rtx value; /* Value in table */
3532 HOST_WIDE_INT next_offset;
3533 enum machine_mode mode; /* Mode of value */
3536 /* The maximum number of constants that can fit into one pool, since
3537 the pc relative range is 0...1020 bytes and constants are at least 4
3540 #define MAX_POOL_SIZE (1020/4)
3541 static pool_node pool_vector[MAX_POOL_SIZE];
3542 static int pool_size;
3543 static rtx pool_vector_label;
3545 /* Add a constant to the pool and return its offset within the current
3548 X is the rtx we want to replace. MODE is its mode. On return,
3549 ADDRESS_ONLY will be non-zero if we really want the address of such
3550 a constant, not the constant itself. */
3551 static HOST_WIDE_INT
3552 add_constant (x, mode, address_only)
3554 enum machine_mode mode;
3558 HOST_WIDE_INT offset;
3562 if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
3563 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3564 x = get_pool_constant (XEXP (x, 0));
3565 else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
3568 mode = get_pool_mode (x);
3569 x = get_pool_constant (x);
3571 #ifndef AOF_ASSEMBLER
3572 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
3573 x = XVECEXP (x, 0, 0);
3576 #ifdef AOF_ASSEMBLER
3577 /* PIC Symbol references need to be converted into offsets into the
3579 if (flag_pic && GET_CODE (x) == SYMBOL_REF)
3580 x = aof_pic_entry (x);
3581 #endif /* AOF_ASSEMBLER */
3583 /* First see if we've already got it */
3584 for (i = 0; i < pool_size; i++)
3586 if (GET_CODE (x) == pool_vector[i].value->code
3587 && mode == pool_vector[i].mode)
3589 if (GET_CODE (x) == CODE_LABEL)
3591 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
3594 if (rtx_equal_p (x, pool_vector[i].value))
3595 return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
3599 /* Need a new one */
3600 pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
3603 pool_vector_label = gen_label_rtx ();
3605 pool_vector[pool_size].next_offset
3606 += (offset = pool_vector[pool_size - 1].next_offset);
3608 pool_vector[pool_size].value = x;
3609 pool_vector[pool_size].mode = mode;
3614 /* Output the literal table */
3621 scan = emit_label_after (gen_label_rtx (), scan);
3622 scan = emit_insn_after (gen_align_4 (), scan);
3623 scan = emit_label_after (pool_vector_label, scan);
3625 for (i = 0; i < pool_size; i++)
3627 pool_node *p = pool_vector + i;
3629 switch (GET_MODE_SIZE (p->mode))
3632 scan = emit_insn_after (gen_consttable_4 (p->value), scan);
3636 scan = emit_insn_after (gen_consttable_8 (p->value), scan);
3645 scan = emit_insn_after (gen_consttable_end (), scan);
3646 scan = emit_barrier_after (scan);
3650 /* Non zero if the src operand needs to be fixed up */
3652 fixit (src, mode, destreg)
3654 enum machine_mode mode;
3657 if (CONSTANT_P (src))
3659 if (GET_CODE (src) == CONST_INT)
3660 return (! const_ok_for_arm (INTVAL (src))
3661 && ! const_ok_for_arm (~INTVAL (src)));
3662 if (GET_CODE (src) == CONST_DOUBLE)
3663 return (GET_MODE (src) == VOIDmode
3665 || (! const_double_rtx_ok_for_fpu (src)
3666 && ! neg_const_double_rtx_ok_for_fpu (src)));
3667 return symbol_mentioned_p (src);
3669 #ifndef AOF_ASSEMBLER
3670 else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
3674 return (mode == SImode && GET_CODE (src) == MEM
3675 && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
3676 && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
3679 /* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
3681 find_barrier (from, max_count)
3686 rtx found_barrier = 0;
3689 while (from && count < max_count)
3693 if (GET_CODE (from) == BARRIER)
3694 found_barrier = from;
3696 /* Count the length of this insn */
3697 if (GET_CODE (from) == INSN
3698 && GET_CODE (PATTERN (from)) == SET
3699 && CONSTANT_P (SET_SRC (PATTERN (from)))
3700 && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
3702 /* Handle table jumps as a single entity. */
3703 else if (GET_CODE (from) == JUMP_INSN
3704 && JUMP_LABEL (from) != 0
3705 && ((tmp = next_real_insn (JUMP_LABEL (from)))
3706 == next_real_insn (from))
3708 && GET_CODE (tmp) == JUMP_INSN
3709 && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
3710 || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
3712 int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
3713 count += (get_attr_length (from)
3714 + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
3715 /* Continue after the dispatch table. */
3717 from = NEXT_INSN (tmp);
3721 count += get_attr_length (from);
3724 from = NEXT_INSN (from);
3727 if (! found_barrier)
3729 /* We didn't find a barrier in time to
3730 dump our stuff, so we'll make one. */
3731 rtx label = gen_label_rtx ();
3734 from = PREV_INSN (last);
3736 from = get_last_insn ();
3738 /* Walk back to be just before any jump. */
3739 while (GET_CODE (from) == JUMP_INSN
3740 || GET_CODE (from) == NOTE
3741 || GET_CODE (from) == CODE_LABEL)
3742 from = PREV_INSN (from);
3744 from = emit_jump_insn_after (gen_jump (label), from);
3745 JUMP_LABEL (from) = label;
3746 found_barrier = emit_barrier_after (from);
3747 emit_label_after (label, found_barrier);
3750 return found_barrier;
3753 /* Non zero if the insn is a move instruction which needs to be fixed. */
3758 if (!INSN_DELETED_P (insn)
3759 && GET_CODE (insn) == INSN
3760 && GET_CODE (PATTERN (insn)) == SET)
3762 rtx pat = PATTERN (insn);
3763 rtx src = SET_SRC (pat);
3764 rtx dst = SET_DEST (pat);
3766 enum machine_mode mode = GET_MODE (dst);
3771 if (GET_CODE (dst) == REG)
3772 destreg = REGNO (dst);
3773 else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
3774 destreg = REGNO (SUBREG_REG (dst));
3778 return fixit (src, mode, destreg);
3791 /* The ldr instruction can work with up to a 4k offset, and most constants
3792 will be loaded with one of these instructions; however, the adr
3793 instruction and the ldf instructions only work with a 1k offset. This
3794 code needs to be rewritten to use the 4k offset when possible, and to
3795 adjust when a 1k offset is needed. For now we just use a 1k offset
3799 /* Floating point operands can't work further than 1024 bytes from the
3800 PC, so to make things simple we restrict all loads for such functions.
3802 if (TARGET_HARD_FLOAT)
3806 for (regno = 16; regno < 24; regno++)
3807 if (regs_ever_live[regno])
3817 for (insn = first; insn; insn = NEXT_INSN (insn))
3819 if (broken_move (insn))
3821 /* This is a broken move instruction, scan ahead looking for
3822 a barrier to stick the constant table behind */
3824 rtx barrier = find_barrier (insn, count_size);
3826 /* Now find all the moves between the points and modify them */
3827 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3829 if (broken_move (scan))
3831 /* This is a broken move instruction, add it to the pool */
3832 rtx pat = PATTERN (scan);
3833 rtx src = SET_SRC (pat);
3834 rtx dst = SET_DEST (pat);
3835 enum machine_mode mode = GET_MODE (dst);
3836 HOST_WIDE_INT offset;
3843 /* If this is an HImode constant load, convert it into
3844 an SImode constant load. Since the register is always
3845 32 bits this is safe. We have to do this, since the
3846 load pc-relative instruction only does a 32-bit load. */
3850 if (GET_CODE (dst) != REG)
3852 PUT_MODE (dst, SImode);
3855 offset = add_constant (src, mode, &address_only);
3856 addr = plus_constant (gen_rtx (LABEL_REF, VOIDmode,
3860 /* If we only want the address of the pool entry, or
3861 for wide moves to integer regs we need to split
3862 the address calculation off into a separate insn.
3863 If necessary, the load can then be done with a
3864 load-multiple. This is safe, since we have
3865 already noted the length of such insns to be 8,
3866 and we are immediately over-writing the scratch
3867 we have grabbed with the final result. */
3868 if ((address_only || GET_MODE_SIZE (mode) > 4)
3869 && (scratch = REGNO (dst)) < 16)
3876 reg = gen_rtx (REG, SImode, scratch);
3878 newinsn = emit_insn_after (gen_movaddr (reg, addr),
3885 newsrc = gen_rtx (MEM, mode, addr);
3887 /* XXX Fixme -- I think the following is bogus. */
3888 /* Build a jump insn wrapper around the move instead
3889 of an ordinary insn, because we want to have room for
3890 the target label rtx in fld[7], which an ordinary
3891 insn doesn't have. */
3892 newinsn = emit_jump_insn_after
3893 (gen_rtx (SET, VOIDmode, dst, newsrc), newinsn);
3894 JUMP_LABEL (newinsn) = pool_vector_label;
3896 /* But it's still an ordinary insn */
3897 PUT_CODE (newinsn, INSN);
3905 dump_table (barrier);
3912 /* Routines to output assembly language. */
3914 /* If the rtx is the correct value then return the string of the number.
3915 In this way we can ensure that valid double constants are generated even
3916 when cross compiling. */
3918 fp_immediate_constant (x)
3924 if (!fpa_consts_inited)
3927 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3928 for (i = 0; i < 8; i++)
3929 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3930 return strings_fpa[i];
3935 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
3937 fp_const_from_val (r)
3942 if (! fpa_consts_inited)
3945 for (i = 0; i < 8; i++)
3946 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
3947 return strings_fpa[i];
3952 /* Output the operands of a LDM/STM instruction to STREAM.
3953 MASK is the ARM register set mask of which only bits 0-15 are important.
3954 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
3955 must follow the register list. */
3958 print_multi_reg (stream, instr, mask, hat)
3964 int not_first = FALSE;
3966 fputc ('\t', stream);
3967 fprintf (stream, instr, REGISTER_PREFIX);
3968 fputs (", {", stream);
3969 for (i = 0; i < 16; i++)
3970 if (mask & (1 << i))
3973 fprintf (stream, ", ");
3974 fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
3978 fprintf (stream, "}%s\n", hat ? "^" : "");
3981 /* Output a 'call' insn. */
3984 output_call (operands)
3987 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
3989 if (REGNO (operands[0]) == 14)
3991 operands[0] = gen_rtx (REG, SImode, 12);
3992 output_asm_insn ("mov%?\t%0, %|lr", operands);
3994 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
3996 if (TARGET_THUMB_INTERWORK)
3997 output_asm_insn ("bx%?\t%0", operands);
3999 output_asm_insn ("mov%?\t%|pc, %0", operands);
4008 int something_changed = 0;
4010 int code = GET_CODE (x0);
4017 if (REGNO (x0) == 14)
4019 *x = gen_rtx (REG, SImode, 12);
4024 /* Scan through the sub-elements and change any references there */
4025 fmt = GET_RTX_FORMAT (code);
4026 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4028 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
4029 else if (fmt[i] == 'E')
4030 for (j = 0; j < XVECLEN (x0, i); j++)
4031 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
4032 return something_changed;
4036 /* Output a 'call' insn that is a reference in memory. */
4039 output_call_mem (operands)
4042 operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
4043 /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
4045 if (eliminate_lr2ip (&operands[0]))
4046 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
4048 if (TARGET_THUMB_INTERWORK)
4050 output_asm_insn ("ldr%?\t%|ip, %0", operands);
4051 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4052 output_asm_insn ("bx%?\t%|ip", operands);
4056 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
4057 output_asm_insn ("ldr%?\t%|pc, %0", operands);
4064 /* Output a move from arm registers to an fpu registers.
4065 OPERANDS[0] is an fpu register.
4066 OPERANDS[1] is the first registers of an arm register pair. */
4069 output_mov_long_double_fpu_from_arm (operands)
4072 int arm_reg0 = REGNO (operands[1]);
4078 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4079 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4080 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
4082 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
4083 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
4087 /* Output a move from an fpu register to arm registers.
4088 OPERANDS[0] is the first registers of an arm register pair.
4089 OPERANDS[1] is an fpu register. */
4092 output_mov_long_double_arm_from_fpu (operands)
4095 int arm_reg0 = REGNO (operands[0]);
4101 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4102 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4103 ops[2] = gen_rtx (REG, SImode, 2 + arm_reg0);
4105 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
4106 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
4110 /* Output a move from arm registers to arm registers of a long double
4111 OPERANDS[0] is the destination.
4112 OPERANDS[1] is the source. */
4114 output_mov_long_double_arm_from_arm (operands)
4117 /* We have to be careful here because the two might overlap */
4118 int dest_start = REGNO (operands[0]);
4119 int src_start = REGNO (operands[1]);
4123 if (dest_start < src_start)
4125 for (i = 0; i < 3; i++)
4127 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4128 ops[1] = gen_rtx (REG, SImode, src_start + i);
4129 output_asm_insn ("mov%?\t%0, %1", ops);
4134 for (i = 2; i >= 0; i--)
4136 ops[0] = gen_rtx (REG, SImode, dest_start + i);
4137 ops[1] = gen_rtx (REG, SImode, src_start + i);
4138 output_asm_insn ("mov%?\t%0, %1", ops);
4146 /* Output a move from arm registers to an fpu registers.
4147 OPERANDS[0] is an fpu register.
4148 OPERANDS[1] is the first registers of an arm register pair. */
4151 output_mov_double_fpu_from_arm (operands)
4154 int arm_reg0 = REGNO (operands[1]);
4159 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4160 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4161 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
4162 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
4166 /* Output a move from an fpu register to arm registers.
4167 OPERANDS[0] is the first registers of an arm register pair.
4168 OPERANDS[1] is an fpu register. */
4171 output_mov_double_arm_from_fpu (operands)
4174 int arm_reg0 = REGNO (operands[0]);
4180 ops[0] = gen_rtx (REG, SImode, arm_reg0);
4181 ops[1] = gen_rtx (REG, SImode, 1 + arm_reg0);
4182 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
4183 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
4187 /* Output a move between double words.
4188 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
4189 or MEM<-REG and all MEMs must be offsettable addresses. */
4192 output_move_double (operands)
4195 enum rtx_code code0 = GET_CODE (operands[0]);
4196 enum rtx_code code1 = GET_CODE (operands[1]);
4201 int reg0 = REGNO (operands[0]);
4203 otherops[0] = gen_rtx (REG, SImode, 1 + reg0);
4206 int reg1 = REGNO (operands[1]);
4210 /* Ensure the second source is not overwritten */
4211 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
4212 output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
4214 output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
4216 else if (code1 == CONST_DOUBLE)
4218 if (GET_MODE (operands[1]) == DFmode)
4221 union real_extract u;
4223 bcopy ((char *) &CONST_DOUBLE_LOW (operands[1]), (char *) &u,
4225 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
4226 otherops[1] = GEN_INT(l[1]);
4227 operands[1] = GEN_INT(l[0]);
4229 else if (GET_MODE (operands[1]) != VOIDmode)
4231 else if (WORDS_BIG_ENDIAN)
4234 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4235 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4240 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
4241 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4243 output_mov_immediate (operands);
4244 output_mov_immediate (otherops);
4246 else if (code1 == CONST_INT)
4248 #if HOST_BITS_PER_WIDE_INT > 32
4249 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
4250 what the upper word is. */
4251 if (WORDS_BIG_ENDIAN)
4253 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4254 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4258 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
4259 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
4262 /* Sign extend the intval into the high-order word */
4263 if (WORDS_BIG_ENDIAN)
4265 otherops[1] = operands[1];
4266 operands[1] = (INTVAL (operands[1]) < 0
4267 ? constm1_rtx : const0_rtx);
4270 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
4272 output_mov_immediate (otherops);
4273 output_mov_immediate (operands);
4275 else if (code1 == MEM)
4277 switch (GET_CODE (XEXP (operands[1], 0)))
4280 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
4284 abort (); /* Should never happen now */
4288 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
4292 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
4296 abort (); /* Should never happen now */
4301 output_asm_insn ("adr%?\t%0, %1", operands);
4302 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
4306 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
4308 otherops[0] = operands[0];
4309 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
4310 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
4311 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
4313 if (GET_CODE (otherops[2]) == CONST_INT)
4315 switch (INTVAL (otherops[2]))
4318 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
4321 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
4324 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
4327 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
4328 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
4330 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4333 output_asm_insn ("add%?\t%0, %1, %2", otherops);
4336 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
4337 return "ldm%?ia\t%0, %M0";
4341 otherops[1] = adj_offsettable_operand (operands[1], 4);
4342 /* Take care of overlapping base/data reg. */
4343 if (reg_mentioned_p (operands[0], operands[1]))
4345 output_asm_insn ("ldr%?\t%0, %1", otherops);
4346 output_asm_insn ("ldr%?\t%0, %1", operands);
4350 output_asm_insn ("ldr%?\t%0, %1", operands);
4351 output_asm_insn ("ldr%?\t%0, %1", otherops);
4357 abort(); /* Constraints should prevent this */
4359 else if (code0 == MEM && code1 == REG)
4361 if (REGNO (operands[1]) == 12)
4364 switch (GET_CODE (XEXP (operands[0], 0)))
4367 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
4371 abort (); /* Should never happen now */
4375 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
4379 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
4383 abort (); /* Should never happen now */
4387 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
4389 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
4392 output_asm_insn ("stm%?db\t%m0, %M1", operands);
4396 output_asm_insn ("stm%?da\t%m0, %M1", operands);
4400 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
4407 otherops[0] = adj_offsettable_operand (operands[0], 4);
4408 otherops[1] = gen_rtx (REG, SImode, 1 + REGNO (operands[1]));
4409 output_asm_insn ("str%?\t%1, %0", operands);
4410 output_asm_insn ("str%?\t%1, %0", otherops);
4414 abort(); /* Constraints should prevent this */
4420 /* Output an arbitrary MOV reg, #n.
4421 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
4424 output_mov_immediate (operands)
4427 HOST_WIDE_INT n = INTVAL (operands[1]);
4431 /* Try to use one MOV */
4432 if (const_ok_for_arm (n))
4434 output_asm_insn ("mov%?\t%0, %1", operands);
4438 /* Try to use one MVN */
4439 if (const_ok_for_arm (~n))
4441 operands[1] = GEN_INT (~n);
4442 output_asm_insn ("mvn%?\t%0, %1", operands);
4446 /* If all else fails, make it out of ORRs or BICs as appropriate. */
4448 for (i=0; i < 32; i++)
4452 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
4453 output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
4456 output_multi_immediate(operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1,
4463 /* Output an ADD r, s, #n where n may be too big for one instruction. If
4464 adding zero to one register, output nothing. */
4467 output_add_immediate (operands)
4470 HOST_WIDE_INT n = INTVAL (operands[2]);
4472 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
4475 output_multi_immediate (operands,
4476 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
4479 output_multi_immediate (operands,
4480 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
4487 /* Output a multiple immediate operation.
4488 OPERANDS is the vector of operands referred to in the output patterns.
4489 INSTR1 is the output pattern to use for the first constant.
4490 INSTR2 is the output pattern to use for subsequent constants.
4491 IMMED_OP is the index of the constant slot in OPERANDS.
4492 N is the constant value. */
4495 output_multi_immediate (operands, instr1, instr2, immed_op, n)
4497 char *instr1, *instr2;
4501 #if HOST_BITS_PER_WIDE_INT > 32
4507 operands[immed_op] = const0_rtx;
4508 output_asm_insn (instr1, operands); /* Quick and easy output */
4513 char *instr = instr1;
4515 /* Note that n is never zero here (which would give no output) */
4516 for (i = 0; i < 32; i += 2)
4520 operands[immed_op] = GEN_INT (n & (255 << i));
4521 output_asm_insn (instr, operands);
4531 /* Return the appropriate ARM instruction for the operation code.
4532 The returned result should not be overwritten. OP is the rtx of the
4533 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
4537 arithmetic_instr (op, shift_first_arg)
4539 int shift_first_arg;
4541 switch (GET_CODE (op))
4547 return shift_first_arg ? "rsb" : "sub";
4564 /* Ensure valid constant shifts and return the appropriate shift mnemonic
4565 for the operation code. The returned result should not be overwritten.
4566 OP is the rtx code of the shift.
4567 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
4571 shift_op (op, amountp)
4573 HOST_WIDE_INT *amountp;
4576 enum rtx_code code = GET_CODE (op);
4578 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
4580 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
4581 *amountp = INTVAL (XEXP (op, 1));
4604 /* We never have to worry about the amount being other than a
4605 power of 2, since this case can never be reloaded from a reg. */
4607 *amountp = int_log2 (*amountp);
4618 /* This is not 100% correct, but follows from the desire to merge
4619 multiplication by a power of 2 with the recognizer for a
4620 shift. >=32 is not a valid shift for "asl", so we must try and
4621 output a shift that produces the correct arithmetical result.
4622 Using lsr #32 is identical except for the fact that the carry bit
4623 is not set correctly if we set the flags; but we never use the
4624 carry bit from such an operation, so we can ignore that. */
4625 if (code == ROTATERT)
4626 *amountp &= 31; /* Rotate is just modulo 32 */
4627 else if (*amountp != (*amountp & 31))
4634 /* Shifts of 0 are no-ops. */
4643 /* Obtain the shift from the POWER of two. */
4645 static HOST_WIDE_INT
4647 HOST_WIDE_INT power;
4649 HOST_WIDE_INT shift = 0;
4651 while (((((HOST_WIDE_INT) 1) << shift) & power) == 0)
4661 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
4662 /bin/as is horribly restrictive. */
4665 output_ascii_pseudo_op (stream, p, len)
4671 int len_so_far = 1000;
4672 int chars_so_far = 0;
4674 for (i = 0; i < len; i++)
4676 register int c = p[i];
4678 if (len_so_far > 50)
4681 fputs ("\"\n", stream);
4682 fputs ("\t.ascii\t\"", stream);
4687 if (c == '\"' || c == '\\')
4693 if (c >= ' ' && c < 0177)
4700 fprintf (stream, "\\%03o", c);
4707 fputs ("\"\n", stream);
4711 /* Try to determine whether a pattern really clobbers the link register.
4712 This information is useful when peepholing, so that lr need not be pushed
4713 if we combine a call followed by a return.
4714 NOTE: This code does not check for side-effect expressions in a SET_SRC:
4715 such a check should not be needed because these only update an existing
4716 value within a register; the register must still be set elsewhere within
4720 pattern_really_clobbers_lr (x)
4725 switch (GET_CODE (x))
4728 switch (GET_CODE (SET_DEST (x)))
4731 return REGNO (SET_DEST (x)) == 14;
4734 if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
4735 return REGNO (XEXP (SET_DEST (x), 0)) == 14;
4737 if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
4746 for (i = 0; i < XVECLEN (x, 0); i++)
4747 if (pattern_really_clobbers_lr (XVECEXP (x, 0, i)))
4752 switch (GET_CODE (XEXP (x, 0)))
4755 return REGNO (XEXP (x, 0)) == 14;
4758 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
4759 return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
4775 function_really_clobbers_lr (first)
4780 for (insn = first; insn; insn = next_nonnote_insn (insn))
4782 switch (GET_CODE (insn))
4787 case JUMP_INSN: /* Jump insns only change the PC (and conds) */
4792 if (pattern_really_clobbers_lr (PATTERN (insn)))
4797 /* Don't yet know how to handle those calls that are not to a
4799 if (GET_CODE (PATTERN (insn)) != PARALLEL)
4802 switch (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)))
4805 if (GET_CODE (XEXP (XEXP (XVECEXP (PATTERN (insn), 0, 0), 0), 0))
4811 if (GET_CODE (XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (insn),
4817 default: /* Don't recognize it, be safe */
4821 /* A call can be made (by peepholing) not to clobber lr iff it is
4822 followed by a return. There may, however, be a use insn iff
4823 we are returning the result of the call.
4824 If we run off the end of the insn chain, then that means the
4825 call was at the end of the function. Unfortunately we don't
4826 have a return insn for the peephole to recognize, so we
4827 must reject this. (Can this be fixed by adding our own insn?) */
4828 if ((next = next_nonnote_insn (insn)) == NULL)
4831 /* No need to worry about lr if the call never returns */
4832 if (GET_CODE (next) == BARRIER)
4835 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
4836 && (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4837 && (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
4838 == REGNO (XEXP (PATTERN (next), 0))))
4839 if ((next = next_nonnote_insn (next)) == NULL)
4842 if (GET_CODE (next) == JUMP_INSN
4843 && GET_CODE (PATTERN (next)) == RETURN)
4852 /* We have reached the end of the chain so lr was _not_ clobbered */
4857 output_return_instruction (operand, really_return, reverse)
4863 int reg, live_regs = 0;
4864 int volatile_func = (optimize > 0
4865 && TREE_THIS_VOLATILE (current_function_decl));
4867 return_used_this_function = 1;
4872 /* If this function was declared non-returning, and we have found a tail
4873 call, then we have to trust that the called function won't return. */
4874 if (! really_return)
4877 /* Otherwise, trap an attempted return by aborting. */
4879 ops[1] = gen_rtx (SYMBOL_REF, Pmode, "abort");
4880 assemble_external_libcall (ops[1]);
4881 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
4885 if (current_function_calls_alloca && ! really_return)
4888 for (reg = 0; reg <= 10; reg++)
4889 if (regs_ever_live[reg] && ! call_used_regs[reg])
4892 if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
4895 if (frame_pointer_needed)
4900 if (lr_save_eliminated || ! regs_ever_live[14])
4903 if (frame_pointer_needed)
4905 reverse ? "ldm%?%D0ea\t%|fp, {" : "ldm%?%d0ea\t%|fp, {");
4908 reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
4910 for (reg = 0; reg <= 10; reg++)
4911 if (regs_ever_live[reg] && ! call_used_regs[reg])
4913 strcat (instr, "%|");
4914 strcat (instr, reg_names[reg]);
4916 strcat (instr, ", ");
4919 if (frame_pointer_needed)
4921 strcat (instr, "%|");
4922 strcat (instr, reg_names[11]);
4923 strcat (instr, ", ");
4924 strcat (instr, "%|");
4925 strcat (instr, reg_names[13]);
4926 strcat (instr, ", ");
4927 strcat (instr, "%|");
4928 strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
4929 ? reg_names[14] : reg_names[15] );
4933 strcat (instr, "%|");
4934 if (TARGET_THUMB_INTERWORK && really_return)
4935 strcat (instr, reg_names[12]);
4937 strcat (instr, really_return ? reg_names[15] : reg_names[14]);
4939 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
4940 output_asm_insn (instr, &operand);
4942 if (TARGET_THUMB_INTERWORK && really_return)
4944 strcpy (instr, "bx%?");
4945 strcat (instr, reverse ? "%D0" : "%d0");
4946 strcat (instr, "\t%|");
4947 strcat (instr, frame_pointer_needed ? "lr" : "ip");
4949 output_asm_insn (instr, & operand);
4952 else if (really_return)
4954 if (TARGET_THUMB_INTERWORK)
4955 sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
4957 sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
4958 reverse ? "D" : "d", TARGET_APCS_32 ? "" : "s");
4960 output_asm_insn (instr, & operand);
4966 /* Return nonzero if optimizing and the current function is volatile.
4967 Such functions never return, and many memory cycles can be saved
4968 by not storing register values that will never be needed again.
4969 This optimization was added to speed up context switching in a
4970 kernel application. */
4973 arm_volatile_func ()
4975 return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
4978 /* The amount of stack adjustment that happens here, in output_return and in
4979 output_epilogue must be exactly the same as was calculated during reload,
4980 or things will point to the wrong place. The only time we can safely
4981 ignore this constraint is when a function has no arguments on the stack,
4982 no stack frame requirement and no live registers execpt for `lr'. If we
4983 can guarantee that by making all function calls into tail calls and that
4984 lr is not clobbered in any other way, then there is no need to push lr
4988 output_func_prologue (f, frame_size)
4992 int reg, live_regs_mask = 0;
4993 int volatile_func = (optimize > 0
4994 && TREE_THIS_VOLATILE (current_function_decl));
4996 /* Nonzero if we must stuff some register arguments onto the stack as if
4997 they were passed there. */
4998 int store_arg_regs = 0;
5000 if (arm_ccfsm_state || arm_target_insn)
5001 abort (); /* Sanity check */
5003 if (arm_naked_function_p (current_function_decl))
5006 return_used_this_function = 0;
5007 lr_save_eliminated = 0;
5009 fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
5010 ASM_COMMENT_START, current_function_args_size,
5011 current_function_pretend_args_size, frame_size);
5012 fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
5013 ASM_COMMENT_START, frame_pointer_needed,
5014 current_function_anonymous_args);
5017 fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
5019 if (current_function_anonymous_args && current_function_pretend_args_size)
5022 for (reg = 0; reg <= 10; reg++)
5023 if (regs_ever_live[reg] && ! call_used_regs[reg])
5024 live_regs_mask |= (1 << reg);
5026 if (frame_pointer_needed)
5027 live_regs_mask |= 0xD800;
5028 else if (regs_ever_live[14])
5030 if (! current_function_args_size
5031 && ! function_really_clobbers_lr (get_insns ()))
5032 lr_save_eliminated = 1;
5034 live_regs_mask |= 0x4000;
5039 /* if a di mode load/store multiple is used, and the base register
5040 is r3, then r4 can become an ever live register without lr
5041 doing so, in this case we need to push lr as well, or we
5042 will fail to get a proper return. */
5044 live_regs_mask |= 0x4000;
5045 lr_save_eliminated = 0;
5049 if (lr_save_eliminated)
5050 fprintf (f,"\t%s I don't think this function clobbers lr\n",
5053 #ifdef AOF_ASSEMBLER
5055 fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
5056 reg_names[PIC_OFFSET_TABLE_REGNUM]);
5062 output_func_epilogue (f, frame_size)
5066 int reg, live_regs_mask = 0;
5067 /* If we need this then it will always be at least this much */
5068 int floats_offset = 12;
5070 int volatile_func = (optimize > 0
5071 && TREE_THIS_VOLATILE (current_function_decl));
5073 if (use_return_insn (FALSE) && return_used_this_function)
5075 if ((frame_size + current_function_outgoing_args_size) != 0
5076 && !(frame_pointer_needed || TARGET_APCS))
5081 /* Naked functions don't have epilogues. */
5082 if (arm_naked_function_p (current_function_decl))
5085 /* A volatile function should never return. Call abort. */
5086 if (TARGET_ABORT_NORETURN && volatile_func)
5088 rtx op = gen_rtx (SYMBOL_REF, Pmode, "abort");
5089 assemble_external_libcall (op);
5090 output_asm_insn ("bl\t%a0", &op);
5094 for (reg = 0; reg <= 10; reg++)
5095 if (regs_ever_live[reg] && ! call_used_regs[reg])
5097 live_regs_mask |= (1 << reg);
5101 if (frame_pointer_needed)
5103 if (arm_fpu_arch == FP_SOFT2)
5105 for (reg = 23; reg > 15; reg--)
5106 if (regs_ever_live[reg] && ! call_used_regs[reg])
5108 floats_offset += 12;
5109 fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
5110 reg_names[reg], REGISTER_PREFIX, floats_offset);
5117 for (reg = 23; reg > 15; reg--)
5119 if (regs_ever_live[reg] && ! call_used_regs[reg])
5121 floats_offset += 12;
5122 /* We can't unstack more than four registers at once */
5123 if (start_reg - reg == 3)
5125 fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
5126 REGISTER_PREFIX, reg_names[reg],
5127 REGISTER_PREFIX, floats_offset);
5128 start_reg = reg - 1;
5133 if (reg != start_reg)
5134 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5135 REGISTER_PREFIX, reg_names[reg + 1],
5136 start_reg - reg, REGISTER_PREFIX, floats_offset);
5138 start_reg = reg - 1;
5142 /* Just in case the last register checked also needs unstacking. */
5143 if (reg != start_reg)
5144 fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
5145 REGISTER_PREFIX, reg_names[reg + 1],
5146 start_reg - reg, REGISTER_PREFIX, floats_offset);
5149 if (TARGET_THUMB_INTERWORK)
5151 live_regs_mask |= 0x6800;
5152 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
5153 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5157 live_regs_mask |= 0xA800;
5158 print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
5159 TARGET_APCS_32 ? FALSE : TRUE);
5164 /* Restore stack pointer if necessary. */
5165 if (frame_size + current_function_outgoing_args_size != 0)
5167 operands[0] = operands[1] = stack_pointer_rtx;
5168 operands[2] = GEN_INT (frame_size
5169 + current_function_outgoing_args_size);
5170 output_add_immediate (operands);
5173 if (arm_fpu_arch == FP_SOFT2)
5175 for (reg = 16; reg < 24; reg++)
5176 if (regs_ever_live[reg] && ! call_used_regs[reg])
5177 fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
5178 reg_names[reg], REGISTER_PREFIX);
5184 for (reg = 16; reg < 24; reg++)
5186 if (regs_ever_live[reg] && ! call_used_regs[reg])
5188 if (reg - start_reg == 3)
5190 fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
5191 REGISTER_PREFIX, reg_names[start_reg],
5193 start_reg = reg + 1;
5198 if (reg != start_reg)
5199 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5200 REGISTER_PREFIX, reg_names[start_reg],
5201 reg - start_reg, REGISTER_PREFIX);
5203 start_reg = reg + 1;
5207 /* Just in case the last register checked also needs unstacking. */
5208 if (reg != start_reg)
5209 fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
5210 REGISTER_PREFIX, reg_names[start_reg],
5211 reg - start_reg, REGISTER_PREFIX);
5214 if (current_function_pretend_args_size == 0 && regs_ever_live[14])
5216 if (TARGET_THUMB_INTERWORK)
5218 if (! lr_save_eliminated)
5219 print_multi_reg(f, "ldmfd\t%ssp!", live_regs_mask | 0x4000,
5222 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5224 else if (lr_save_eliminated)
5225 fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
5226 : "\tmovs\t%spc, %slr\n"),
5227 REGISTER_PREFIX, REGISTER_PREFIX, f);
5229 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
5230 TARGET_APCS_32 ? FALSE : TRUE);
5234 if (live_regs_mask || regs_ever_live[14])
5236 /* Restore the integer regs, and the return address into lr */
5237 if (! lr_save_eliminated)
5238 live_regs_mask |= 0x4000;
5240 if (live_regs_mask != 0)
5241 print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
5244 if (current_function_pretend_args_size)
5246 /* Unwind the pre-pushed regs */
5247 operands[0] = operands[1] = stack_pointer_rtx;
5248 operands[2] = GEN_INT (current_function_pretend_args_size);
5249 output_add_immediate (operands);
5251 /* And finally, go home */
5252 if (TARGET_THUMB_INTERWORK)
5253 fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
5254 else if (TARGET_APCS_32)
5255 fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5257 fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
5263 current_function_anonymous_args = 0;
5267 emit_multi_reg_push (mask)
5274 for (i = 0; i < 16; i++)
5275 if (mask & (1 << i))
5278 if (num_regs == 0 || num_regs > 16)
5281 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (num_regs));
5283 for (i = 0; i < 16; i++)
5285 if (mask & (1 << i))
5288 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, BLKmode,
5289 gen_rtx (PRE_DEC, BLKmode,
5290 stack_pointer_rtx)),
5291 gen_rtx (UNSPEC, BLKmode,
5292 gen_rtvec (1, gen_rtx (REG, SImode, i)),
5298 for (j = 1, i++; j < num_regs; i++)
5300 if (mask & (1 << i))
5303 = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, i));
5312 emit_sfm (base_reg, count)
5319 par = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5321 XVECEXP (par, 0, 0) = gen_rtx (SET, VOIDmode,
5322 gen_rtx (MEM, BLKmode,
5323 gen_rtx (PRE_DEC, BLKmode,
5324 stack_pointer_rtx)),
5325 gen_rtx (UNSPEC, BLKmode,
5326 gen_rtvec (1, gen_rtx (REG, XFmode,
5329 for (i = 1; i < count; i++)
5330 XVECEXP (par, 0, i) = gen_rtx (USE, VOIDmode,
5331 gen_rtx (REG, XFmode, base_reg++));
5337 arm_expand_prologue ()
5340 rtx amount = GEN_INT (-(get_frame_size ()
5341 + current_function_outgoing_args_size));
5342 int live_regs_mask = 0;
5343 int store_arg_regs = 0;
5344 int volatile_func = (optimize > 0
5345 && TREE_THIS_VOLATILE (current_function_decl));
5347 /* Naked functions don't have prologues. */
5348 if (arm_naked_function_p (current_function_decl))
5351 if (current_function_anonymous_args && current_function_pretend_args_size)
5354 if (! volatile_func)
5355 for (reg = 0; reg <= 10; reg++)
5356 if (regs_ever_live[reg] && ! call_used_regs[reg])
5357 live_regs_mask |= 1 << reg;
5359 if (! volatile_func && regs_ever_live[14])
5360 live_regs_mask |= 0x4000;
5362 if (frame_pointer_needed)
5364 live_regs_mask |= 0xD800;
5365 emit_insn (gen_movsi (gen_rtx (REG, SImode, 12),
5366 stack_pointer_rtx));
5369 if (current_function_pretend_args_size)
5372 emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
5375 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
5376 GEN_INT (-current_function_pretend_args_size)));
5381 /* If we have to push any regs, then we must push lr as well, or
5382 we won't get a proper return. */
5383 live_regs_mask |= 0x4000;
5384 emit_multi_reg_push (live_regs_mask);
5387 /* For now the integer regs are still pushed in output_func_epilogue (). */
5389 if (! volatile_func)
5391 if (arm_fpu_arch == FP_SOFT2)
5393 for (reg = 23; reg > 15; reg--)
5394 if (regs_ever_live[reg] && ! call_used_regs[reg])
5395 emit_insn (gen_rtx (SET, VOIDmode,
5396 gen_rtx (MEM, XFmode,
5397 gen_rtx (PRE_DEC, XFmode,
5398 stack_pointer_rtx)),
5399 gen_rtx (REG, XFmode, reg)));
5405 for (reg = 23; reg > 15; reg--)
5407 if (regs_ever_live[reg] && ! call_used_regs[reg])
5409 if (start_reg - reg == 3)
5412 start_reg = reg - 1;
5417 if (start_reg != reg)
5418 emit_sfm (reg + 1, start_reg - reg);
5419 start_reg = reg - 1;
5423 if (start_reg != reg)
5424 emit_sfm (reg + 1, start_reg - reg);
5428 if (frame_pointer_needed)
5429 emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx (REG, SImode, 12),
5431 (-(4 + current_function_pretend_args_size)))));
5433 if (amount != const0_rtx)
5435 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
5436 emit_insn (gen_rtx (CLOBBER, VOIDmode,
5437 gen_rtx (MEM, BLKmode, stack_pointer_rtx)));
5440 /* If we are profiling, make sure no instructions are scheduled before
5441 the call to mcount. */
5442 if (profile_flag || profile_block_flag)
5443 emit_insn (gen_blockage ());
5447 /* If CODE is 'd', then the X is a condition operand and the instruction
5448 should only be executed if the condition is true.
5449 if CODE is 'D', then the X is a condition operand and the instruction
5450 should only be executed if the condition is false: however, if the mode
5451 of the comparison is CCFPEmode, then always execute the instruction -- we
5452 do this because in these circumstances !GE does not necessarily imply LT;
5453 in these cases the instruction pattern will take care to make sure that
5454 an instruction containing %d will follow, thereby undoing the effects of
5455 doing this instruction unconditionally.
5456 If CODE is 'N' then X is a floating point operand that must be negated
5458 If CODE is 'B' then output a bitwise inverted value of X (a const int).
5459 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
5462 arm_print_operand (stream, x, code)
5470 fputs (ASM_COMMENT_START, stream);
5474 fputs (REGISTER_PREFIX, stream);
5478 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
5479 fputs (arm_condition_codes[arm_current_cc], stream);
5485 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5486 r = REAL_VALUE_NEGATE (r);
5487 fprintf (stream, "%s", fp_const_from_val (&r));
5492 if (GET_CODE (x) == CONST_INT)
5494 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5499 ARM_SIGN_EXTEND (~ INTVAL (x)));
5503 output_addr_const (stream, x);
5508 fprintf (stream, "%s", arithmetic_instr (x, 1));
5512 fprintf (stream, "%s", arithmetic_instr (x, 0));
5518 char *shift = shift_op (x, &val);
5522 fprintf (stream, ", %s ", shift_op (x, &val));
5524 arm_print_operand (stream, XEXP (x, 1), 0);
5527 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
5540 fputs (REGISTER_PREFIX, stream);
5541 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)], stream);
5547 fputs (REGISTER_PREFIX, stream);
5548 fputs (reg_names[REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)], stream);
5552 fputs (REGISTER_PREFIX, stream);
5553 if (GET_CODE (XEXP (x, 0)) == REG)
5554 fputs (reg_names[REGNO (XEXP (x, 0))], stream);
5556 fputs (reg_names[REGNO (XEXP (XEXP (x, 0), 0))], stream);
5560 fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
5561 REGISTER_PREFIX, reg_names[REGNO (x) - 1
5562 + ((GET_MODE_SIZE (GET_MODE (x))
5563 + GET_MODE_SIZE (SImode) - 1)
5564 / GET_MODE_SIZE (SImode))]);
5569 fputs (arm_condition_codes[get_arm_condition_code (x)],
5575 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
5576 (get_arm_condition_code (x))],
5584 if (GET_CODE (x) == REG)
5586 fputs (REGISTER_PREFIX, stream);
5587 fputs (reg_names[REGNO (x)], stream);
5589 else if (GET_CODE (x) == MEM)
5591 output_memory_reference_mode = GET_MODE (x);
5592 output_address (XEXP (x, 0));
5594 else if (GET_CODE (x) == CONST_DOUBLE)
5595 fprintf (stream, "#%s", fp_immediate_constant (x));
5596 else if (GET_CODE (x) == NEG)
5597 abort (); /* This should never happen now. */
5600 fputc ('#', stream);
5601 output_addr_const (stream, x);
5607 /* A finite state machine takes care of noticing whether or not instructions
5608 can be conditionally executed, and thus decrease execution time and code
5609 size by deleting branch instructions. The fsm is controlled by
5610 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
5612 /* The state of the fsm controlling condition codes are:
5613 0: normal, do nothing special
5614 1: make ASM_OUTPUT_OPCODE not output this instruction
5615 2: make ASM_OUTPUT_OPCODE not output this instruction
5616 3: make instructions conditional
5617 4: make instructions conditional
5619 State transitions (state->state by whom under condition):
5620 0 -> 1 final_prescan_insn if the `target' is a label
5621 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
5622 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
5623 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
5624 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
5625 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
5626 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
5627 (the target insn is arm_target_insn).
5629 If the jump clobbers the conditions then we use states 2 and 4.
5631 A similar thing can be done with conditional return insns.
5633 XXX In case the `target' is an unconditional branch, this conditionalising
5634 of the instructions always reduces code size, but not always execution
5635 time. But then, I want to reduce the code size to somewhere near what
5636 /bin/cc produces. */
5638 /* Returns the index of the ARM condition code string in
5639 `arm_condition_codes'. COMPARISON should be an rtx like
5640 `(eq (...) (...))'. */
5642 static enum arm_cond_code
5643 get_arm_condition_code (comparison)
5646 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
5648 register enum rtx_code comp_code = GET_CODE (comparison);
5650 if (GET_MODE_CLASS (mode) != MODE_CC)
5651 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
5652 XEXP (comparison, 1));
5656 case CC_DNEmode: code = ARM_NE; goto dominance;
5657 case CC_DEQmode: code = ARM_EQ; goto dominance;
5658 case CC_DGEmode: code = ARM_GE; goto dominance;
5659 case CC_DGTmode: code = ARM_GT; goto dominance;
5660 case CC_DLEmode: code = ARM_LE; goto dominance;
5661 case CC_DLTmode: code = ARM_LT; goto dominance;
5662 case CC_DGEUmode: code = ARM_CS; goto dominance;
5663 case CC_DGTUmode: code = ARM_HI; goto dominance;
5664 case CC_DLEUmode: code = ARM_LS; goto dominance;
5665 case CC_DLTUmode: code = ARM_CC;
5668 if (comp_code != EQ && comp_code != NE)
5671 if (comp_code == EQ)
5672 return ARM_INVERSE_CONDITION_CODE (code);
5678 case NE: return ARM_NE;
5679 case EQ: return ARM_EQ;
5680 case GE: return ARM_PL;
5681 case LT: return ARM_MI;
5689 case NE: return ARM_NE;
5690 case EQ: return ARM_EQ;
5697 case GE: return ARM_GE;
5698 case GT: return ARM_GT;
5699 case LE: return ARM_LS;
5700 case LT: return ARM_MI;
5707 case NE: return ARM_NE;
5708 case EQ: return ARM_EQ;
5709 case GE: return ARM_LE;
5710 case GT: return ARM_LT;
5711 case LE: return ARM_GE;
5712 case LT: return ARM_GT;
5713 case GEU: return ARM_LS;
5714 case GTU: return ARM_CC;
5715 case LEU: return ARM_CS;
5716 case LTU: return ARM_HI;
5723 case LTU: return ARM_CS;
5724 case GEU: return ARM_CC;
5731 case NE: return ARM_NE;
5732 case EQ: return ARM_EQ;
5733 case GE: return ARM_GE;
5734 case GT: return ARM_GT;
5735 case LE: return ARM_LE;
5736 case LT: return ARM_LT;
5737 case GEU: return ARM_CS;
5738 case GTU: return ARM_HI;
5739 case LEU: return ARM_LS;
5740 case LTU: return ARM_CC;
5752 final_prescan_insn (insn, opvec, noperands)
5757 /* BODY will hold the body of INSN. */
5758 register rtx body = PATTERN (insn);
5760 /* This will be 1 if trying to repeat the trick, and things need to be
5761 reversed if it appears to fail. */
5764 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
5765 taken are clobbered, even if the rtl suggests otherwise. It also
5766 means that we have to grub around within the jump expression to find
5767 out what the conditions are when the jump isn't taken. */
5768 int jump_clobbers = 0;
5770 /* If we start with a return insn, we only succeed if we find another one. */
5771 int seeking_return = 0;
5773 /* START_INSN will hold the insn from where we start looking. This is the
5774 first insn after the following code_label if REVERSE is true. */
5775 rtx start_insn = insn;
5777 /* If in state 4, check if the target branch is reached, in order to
5778 change back to state 0. */
5779 if (arm_ccfsm_state == 4)
5781 if (insn == arm_target_insn)
5783 arm_target_insn = NULL;
5784 arm_ccfsm_state = 0;
5789 /* If in state 3, it is possible to repeat the trick, if this insn is an
5790 unconditional branch to a label, and immediately following this branch
5791 is the previous target label which is only used once, and the label this
5792 branch jumps to is not too far off. */
5793 if (arm_ccfsm_state == 3)
5795 if (simplejump_p (insn))
5797 start_insn = next_nonnote_insn (start_insn);
5798 if (GET_CODE (start_insn) == BARRIER)
5800 /* XXX Isn't this always a barrier? */
5801 start_insn = next_nonnote_insn (start_insn);
5803 if (GET_CODE (start_insn) == CODE_LABEL
5804 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5805 && LABEL_NUSES (start_insn) == 1)
5810 else if (GET_CODE (body) == RETURN)
5812 start_insn = next_nonnote_insn (start_insn);
5813 if (GET_CODE (start_insn) == BARRIER)
5814 start_insn = next_nonnote_insn (start_insn);
5815 if (GET_CODE (start_insn) == CODE_LABEL
5816 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
5817 && LABEL_NUSES (start_insn) == 1)
5829 if (arm_ccfsm_state != 0 && !reverse)
5831 if (GET_CODE (insn) != JUMP_INSN)
5834 /* This jump might be paralleled with a clobber of the condition codes
5835 the jump should always come first */
5836 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5837 body = XVECEXP (body, 0, 0);
5840 /* If this is a conditional return then we don't want to know */
5841 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5842 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
5843 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
5844 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
5849 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
5850 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
5853 int fail = FALSE, succeed = FALSE;
5854 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
5855 int then_not_else = TRUE;
5856 rtx this_insn = start_insn, label = 0;
5858 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5860 /* The code below is wrong for these, and I haven't time to
5861 fix it now. So we just do the safe thing and return. This
5862 whole function needs re-writing anyway. */
5867 /* Register the insn jumped to. */
5870 if (!seeking_return)
5871 label = XEXP (SET_SRC (body), 0);
5873 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
5874 label = XEXP (XEXP (SET_SRC (body), 1), 0);
5875 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
5877 label = XEXP (XEXP (SET_SRC (body), 2), 0);
5878 then_not_else = FALSE;
5880 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
5882 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
5885 then_not_else = FALSE;
5890 /* See how many insns this branch skips, and what kind of insns. If all
5891 insns are okay, and the label or unconditional branch to the same
5892 label is not too far away, succeed. */
5893 for (insns_skipped = 0;
5894 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
5898 this_insn = next_nonnote_insn (this_insn);
5902 switch (GET_CODE (this_insn))
5905 /* Succeed if it is the target label, otherwise fail since
5906 control falls in from somewhere else. */
5907 if (this_insn == label)
5911 arm_ccfsm_state = 2;
5912 this_insn = next_nonnote_insn (this_insn);
5915 arm_ccfsm_state = 1;
5923 /* Succeed if the following insn is the target label.
5925 If return insns are used then the last insn in a function
5926 will be a barrier. */
5927 this_insn = next_nonnote_insn (this_insn);
5928 if (this_insn && this_insn == label)
5932 arm_ccfsm_state = 2;
5933 this_insn = next_nonnote_insn (this_insn);
5936 arm_ccfsm_state = 1;
5944 /* If using 32-bit addresses the cc is not preserved over
5948 /* Succeed if the following insn is the target label,
5949 or if the following two insns are a barrier and
5950 the target label. */
5951 this_insn = next_nonnote_insn (this_insn);
5952 if (this_insn && GET_CODE (this_insn) == BARRIER)
5953 this_insn = next_nonnote_insn (this_insn);
5955 if (this_insn && this_insn == label
5956 && insns_skipped < max_insns_skipped)
5960 arm_ccfsm_state = 2;
5961 this_insn = next_nonnote_insn (this_insn);
5964 arm_ccfsm_state = 1;
5973 /* If this is an unconditional branch to the same label, succeed.
5974 If it is to another label, do nothing. If it is conditional,
5976 /* XXX Probably, the tests for SET and the PC are unnecessary. */
5978 scanbody = PATTERN (this_insn);
5979 if (GET_CODE (scanbody) == SET
5980 && GET_CODE (SET_DEST (scanbody)) == PC)
5982 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
5983 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
5985 arm_ccfsm_state = 2;
5988 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
5991 /* Fail if a conditional return is undesirable (eg on a
5992 StrongARM), but still allow this if optimizing for size. */
5993 else if (GET_CODE (scanbody) == RETURN
5994 && ! use_return_insn (TRUE)
5997 else if (GET_CODE (scanbody) == RETURN
6000 arm_ccfsm_state = 2;
6003 else if (GET_CODE (scanbody) == PARALLEL)
6005 switch (get_attr_conds (this_insn))
6017 /* Instructions using or affecting the condition codes make it
6019 scanbody = PATTERN (this_insn);
6020 if (! (GET_CODE (scanbody) == SET
6021 || GET_CODE (scanbody) == PARALLEL)
6022 || get_attr_conds (this_insn) != CONDS_NOCOND)
6032 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
6033 arm_target_label = CODE_LABEL_NUMBER (label);
6034 else if (seeking_return || arm_ccfsm_state == 2)
6036 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
6038 this_insn = next_nonnote_insn (this_insn);
6039 if (this_insn && (GET_CODE (this_insn) == BARRIER
6040 || GET_CODE (this_insn) == CODE_LABEL))
6045 /* Oh, dear! we ran off the end.. give up */
6046 recog (PATTERN (insn), insn, NULL_PTR);
6047 arm_ccfsm_state = 0;
6048 arm_target_insn = NULL;
6051 arm_target_insn = this_insn;
6060 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
6062 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
6063 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6064 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
6065 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6069 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
6072 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
6076 if (reverse || then_not_else)
6077 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
6079 /* restore recog_operand (getting the attributes of other insns can
6080 destroy this array, but final.c assumes that it remains intact
6081 across this call; since the insn has been recognized already we
6082 call recog direct). */
6083 recog (PATTERN (insn), insn, NULL_PTR);
6087 #ifdef AOF_ASSEMBLER
6088 /* Special functions only needed when producing AOF syntax assembler. */
6090 rtx aof_pic_label = NULL_RTX;
6093 struct pic_chain *next;
6097 static struct pic_chain *aof_pic_chain = NULL;
6103 struct pic_chain **chainp;
6106 if (aof_pic_label == NULL_RTX)
6108 /* This needs to persist throughout the compilation. */
6109 end_temporary_allocation ();
6110 aof_pic_label = gen_rtx (SYMBOL_REF, Pmode, "x$adcons");
6111 resume_temporary_allocation ();
6114 for (offset = 0, chainp = &aof_pic_chain; *chainp;
6115 offset += 4, chainp = &(*chainp)->next)
6116 if ((*chainp)->symname == XSTR (x, 0))
6117 return plus_constant (aof_pic_label, offset);
6119 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
6120 (*chainp)->next = NULL;
6121 (*chainp)->symname = XSTR (x, 0);
6122 return plus_constant (aof_pic_label, offset);
6126 aof_dump_pic_table (f)
6129 struct pic_chain *chain;
6131 if (aof_pic_chain == NULL)
6134 fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
6135 reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
6136 reg_names[PIC_OFFSET_TABLE_REGNUM]);
6137 fputs ("|x$adcons|\n", f);
6139 for (chain = aof_pic_chain; chain; chain = chain->next)
6141 fputs ("\tDCD\t", f);
6142 assemble_name (f, chain->symname);
6147 int arm_text_section_count = 1;
6152 static char buf[100];
6153 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
6154 arm_text_section_count++);
6156 strcat (buf, ", PIC, REENTRANT");
6160 static int arm_data_section_count = 1;
6165 static char buf[100];
6166 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
6170 /* The AOF assembler is religiously strict about declarations of
6171 imported and exported symbols, so that it is impossible to declare
6172 a function as imported near the beginning of the file, and then to
6173 export it later on. It is, however, possible to delay the decision
6174 until all the functions in the file have been compiled. To get
6175 around this, we maintain a list of the imports and exports, and
6176 delete from it any that are subsequently defined. At the end of
6177 compilation we spit the remainder of the list out before the END
6182 struct import *next;
6186 static struct import *imports_list = NULL;
6189 aof_add_import (name)
6194 for (new = imports_list; new; new = new->next)
6195 if (new->name == name)
6198 new = (struct import *) xmalloc (sizeof (struct import));
6199 new->next = imports_list;
6205 aof_delete_import (name)
6208 struct import **old;
6210 for (old = &imports_list; *old; old = & (*old)->next)
6212 if ((*old)->name == name)
6214 *old = (*old)->next;
6220 int arm_main_function = 0;
6223 aof_dump_imports (f)
6226 /* The AOF assembler needs this to cause the startup code to be extracted
6227 from the library. Brining in __main causes the whole thing to work
6229 if (arm_main_function)
6232 fputs ("\tIMPORT __main\n", f);
6233 fputs ("\tDCD __main\n", f);
6236 /* Now dump the remaining imports. */
6237 while (imports_list)
6239 fprintf (f, "\tIMPORT\t");
6240 assemble_name (f, imports_list->name);
6242 imports_list = imports_list->next;
6245 #endif /* AOF_ASSEMBLER */