1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 /* Forward definitions of types. */
52 typedef struct minipool_node Mnode;
53 typedef struct minipool_fixup Mfix;
55 /* In order to improve the layout of the prototypes below
56 some short type abbreviations are defined here. */
57 #define Hint HOST_WIDE_INT
58 #define Mmode enum machine_mode
59 #define Ulong unsigned long
60 #define Ccstar const char *
62 /* Forward function declarations. */
63 static void arm_add_gc_roots PARAMS ((void));
64 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
65 static Ulong bit_count PARAMS ((signed int));
66 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
67 static int eliminate_lr2ip PARAMS ((rtx *));
68 static rtx emit_multi_reg_push PARAMS ((int));
69 static rtx emit_sfm PARAMS ((int, int));
70 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
71 static arm_cc get_arm_condition_code PARAMS ((rtx));
72 static void init_fpa_table PARAMS ((void));
73 static Hint int_log2 PARAMS ((Hint));
74 static rtx is_jump_table PARAMS ((rtx));
75 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
76 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
77 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
78 static Ccstar shift_op PARAMS ((rtx, Hint *));
79 static void arm_init_machine_status PARAMS ((struct function *));
80 static void arm_mark_machine_status PARAMS ((struct function *));
81 static void arm_free_machine_status PARAMS ((struct function *));
82 static int number_of_first_bit_set PARAMS ((int));
83 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
84 static void thumb_exit PARAMS ((FILE *, int, rtx));
85 static void thumb_pushpop PARAMS ((FILE *, int, int));
86 static Ccstar thumb_condition_code PARAMS ((rtx, int));
87 static rtx is_jump_table PARAMS ((rtx));
88 static Hint get_jump_table_size PARAMS ((rtx));
89 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
90 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
91 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
92 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
93 static void assign_minipool_offsets PARAMS ((Mfix *));
94 static void arm_print_value PARAMS ((FILE *, rtx));
95 static void dump_minipool PARAMS ((rtx));
96 static int arm_barrier_cost PARAMS ((rtx));
97 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
98 static void push_minipool_barrier PARAMS ((rtx, Hint));
99 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
100 static void note_invalid_constants PARAMS ((rtx, Hint));
101 static int current_file_function_operand PARAMS ((rtx));
102 static Ulong arm_compute_save_reg_mask PARAMS ((void));
103 static Ulong arm_isr_value PARAMS ((tree));
104 static Ulong arm_compute_func_type PARAMS ((void));
105 static int arm_valid_type_attribute_p PARAMS ((tree, tree,
107 static int arm_valid_decl_attribute_p PARAMS ((tree, tree,
109 static void arm_output_function_epilogue PARAMS ((FILE *,
111 static void arm_output_function_prologue PARAMS ((FILE *,
113 static void thumb_output_function_prologue PARAMS ((FILE *,
115 static int arm_comp_type_attributes PARAMS ((tree, tree));
116 static void arm_set_default_type_attributes PARAMS ((tree));
122 /* Initialize the GCC target structure. */
123 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
124 #undef TARGET_MERGE_DECL_ATTRIBUTES
125 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
128 #undef TARGET_VALID_TYPE_ATTRIBUTE
129 #define TARGET_VALID_TYPE_ATTRIBUTE arm_valid_type_attribute_p
131 #undef TARGET_VALID_DECL_ATTRIBUTE
133 static int arm_pe_valid_decl_attribute_p PARAMS ((tree, tree, tree, tree));
134 # define TARGET_VALID_DECL_ATTRIBUTE arm_pe_valid_decl_attribute_p
136 # define TARGET_VALID_DECL_ATTRIBUTE arm_valid_decl_attribute_p
139 #undef TARGET_ASM_FUNCTION_PROLOGUE
140 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
142 #undef TARGET_ASM_FUNCTION_EPILOGUE
143 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
145 #undef TARGET_COMP_TYPE_ATTRIBUTES
146 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
148 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
149 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
151 #undef TARGET_INIT_BUILTINS
152 #define TARGET_INIT_BUILTINS arm_init_builtins
154 #undef TARGET_EXPAND_BUILTIN
155 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
157 struct gcc_target targetm = TARGET_INITIALIZER;
159 /* Obstack for minipool constant handling. */
160 static struct obstack minipool_obstack;
161 static char *minipool_startobj;
163 #define obstack_chunk_alloc xmalloc
164 #define obstack_chunk_free free
166 /* The maximum number of insns skipped which will be conditionalised if
168 static int max_insns_skipped = 5;
170 extern FILE * asm_out_file;
172 /* True if we are currently building a constant table. */
173 int making_const_table;
175 /* Define the information needed to generate branch insns. This is
176 stored from the compare operation. */
177 rtx arm_compare_op0, arm_compare_op1;
179 /* What type of floating point are we tuning for? */
180 enum floating_point_type arm_fpu;
182 /* What type of floating point instructions are available? */
183 enum floating_point_type arm_fpu_arch;
185 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
186 enum prog_mode_type arm_prgmode;
188 /* Set by the -mfp=... option. */
189 const char * target_fp_name = NULL;
191 /* Used to parse -mstructure_size_boundary command line option. */
192 const char * structure_size_string = NULL;
193 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
195 /* Bit values used to identify processor capabilities. */
196 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
197 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
198 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
199 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
200 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
201 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
202 #define FL_THUMB (1 << 6) /* Thumb aware */
203 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
204 #define FL_STRONG (1 << 8) /* StrongARM */
205 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
206 #define FL_XSCALE (1 << 10) /* XScale */
208 /* The bits in this mask specify which instructions we are
209 allowed to generate. */
210 static int insn_flags = 0;
212 /* The bits in this mask specify which instruction scheduling options should
213 be used. Note - there is an overlap with the FL_FAST_MULT. For some
214 hardware we want to be able to generate the multiply instructions, but to
215 tune as if they were not present in the architecture. */
216 static int tune_flags = 0;
218 /* The following are used in the arm.md file as equivalents to bits
219 in the above two flag variables. */
221 /* Nonzero if this is an "M" variant of the processor. */
222 int arm_fast_multiply = 0;
224 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
227 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
230 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
233 /* Nonzero if this chip can benefit from load scheduling. */
234 int arm_ld_sched = 0;
236 /* Nonzero if this chip is a StrongARM. */
237 int arm_is_strong = 0;
239 /* Nonzero if this chip is an XScale. */
240 int arm_is_xscale = 0;
242 /* Nonzero if this chip is a an ARM6 or an ARM7. */
243 int arm_is_6_or_7 = 0;
245 /* Nonzero if generating Thumb instructions. */
248 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
249 must report the mode of the memory reference from PRINT_OPERAND to
250 PRINT_OPERAND_ADDRESS. */
251 enum machine_mode output_memory_reference_mode;
253 /* Nonzero if the prologue must setup `fp'. */
254 int current_function_anonymous_args;
256 /* The register number to be used for the PIC offset register. */
257 const char * arm_pic_register_string = NULL;
258 int arm_pic_register = 9;
260 /* Set to 1 when a return insn is output, this means that the epilogue
262 int return_used_this_function;
264 /* Set to 1 after arm_reorg has started. Reset to start at the start of
265 the next function. */
266 static int after_arm_reorg = 0;
268 /* The maximum number of insns to be used when loading a constant. */
269 static int arm_constant_limit = 3;
271 /* For an explanation of these variables, see final_prescan_insn below. */
273 enum arm_cond_code arm_current_cc;
275 int arm_target_label;
277 /* The condition codes of the ARM, and the inverse function. */
278 const char * arm_condition_codes[] =
280 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
281 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
284 #define streq(string1, string2) (strcmp (string1, string2) == 0)
286 /* Initialization code. */
294 /* Not all of these give usefully different compilation alternatives,
295 but there is no simple way of generalizing them. */
296 static struct processors all_cores[] =
300 {"arm2", FL_CO_PROC | FL_MODE26 },
301 {"arm250", FL_CO_PROC | FL_MODE26 },
302 {"arm3", FL_CO_PROC | FL_MODE26 },
303 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
304 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
305 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
306 {"arm610", FL_MODE26 | FL_MODE32 },
307 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
308 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
309 /* arm7m doesn't exist on its own, but only with D, (and I), but
310 those don't alter the code, so arm7m is sometimes used. */
311 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
312 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
313 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
314 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
315 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
316 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
317 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
318 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
319 {"arm710", FL_MODE26 | FL_MODE32 },
320 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
321 {"arm720", FL_MODE26 | FL_MODE32 },
322 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
323 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
324 {"arm710c", FL_MODE26 | FL_MODE32 },
325 {"arm7100", FL_MODE26 | FL_MODE32 },
326 {"arm7500", FL_MODE26 | FL_MODE32 },
327 /* Doesn't have an external co-proc, but does have embedded fpu. */
328 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
329 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
330 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
331 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
332 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
333 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
334 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
335 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
336 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
337 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
338 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
339 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
340 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
341 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
342 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
343 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
344 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
349 static struct processors all_architectures[] =
351 /* ARM Architectures */
353 { "armv2", FL_CO_PROC | FL_MODE26 },
354 { "armv2a", FL_CO_PROC | FL_MODE26 },
355 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
356 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
357 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
358 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
359 implementations that support it, so we will leave it out for now. */
360 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
361 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
362 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
363 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
367 /* This is a magic stucture. The 'string' field is magically filled in
368 with a pointer to the value specified by the user on the command line
369 assuming that the user has specified such a value. */
371 struct arm_cpu_select arm_select[] =
373 /* string name processors */
374 { NULL, "-mcpu=", all_cores },
375 { NULL, "-march=", all_architectures },
376 { NULL, "-mtune=", all_cores }
379 /* Return the number of bits set in value' */
384 unsigned long count = 0;
388 value &= ~(value & -value);
395 /* Fix up any incompatible options that the user has specified.
396 This has now turned into a maze. */
398 arm_override_options ()
402 /* Set up the flags based on the cpu/architecture selected by the user. */
403 for (i = ARRAY_SIZE (arm_select); i--;)
405 struct arm_cpu_select * ptr = arm_select + i;
407 if (ptr->string != NULL && ptr->string[0] != '\0')
409 const struct processors * sel;
411 for (sel = ptr->processors; sel->name != NULL; sel++)
412 if (streq (ptr->string, sel->name))
415 tune_flags = sel->flags;
418 /* If we have been given an architecture and a processor
419 make sure that they are compatible. We only generate
420 a warning though, and we prefer the CPU over the
422 if (insn_flags != 0 && (insn_flags ^ sel->flags))
423 warning ("switch -mcpu=%s conflicts with -march= switch",
426 insn_flags = sel->flags;
432 if (sel->name == NULL)
433 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
437 /* If the user did not specify a processor, choose one for them. */
440 struct processors * sel;
442 static struct cpu_default
449 { TARGET_CPU_arm2, "arm2" },
450 { TARGET_CPU_arm6, "arm6" },
451 { TARGET_CPU_arm610, "arm610" },
452 { TARGET_CPU_arm710, "arm710" },
453 { TARGET_CPU_arm7m, "arm7m" },
454 { TARGET_CPU_arm7500fe, "arm7500fe" },
455 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
456 { TARGET_CPU_arm8, "arm8" },
457 { TARGET_CPU_arm810, "arm810" },
458 { TARGET_CPU_arm9, "arm9" },
459 { TARGET_CPU_strongarm, "strongarm" },
460 { TARGET_CPU_xscale, "xscale" },
461 { TARGET_CPU_generic, "arm" },
464 struct cpu_default * def;
466 /* Find the default. */
467 for (def = cpu_defaults; def->name; def++)
468 if (def->cpu == TARGET_CPU_DEFAULT)
471 /* Make sure we found the default CPU. */
472 if (def->name == NULL)
475 /* Find the default CPU's flags. */
476 for (sel = all_cores; sel->name != NULL; sel++)
477 if (streq (def->name, sel->name))
480 if (sel->name == NULL)
483 insn_flags = sel->flags;
485 /* Now check to see if the user has specified some command line
486 switch that require certain abilities from the cpu. */
489 if (TARGET_INTERWORK || TARGET_THUMB)
491 sought |= (FL_THUMB | FL_MODE32);
493 /* Force apcs-32 to be used for interworking. */
494 target_flags |= ARM_FLAG_APCS_32;
496 /* There are no ARM processors that support both APCS-26 and
497 interworking. Therefore we force FL_MODE26 to be removed
498 from insn_flags here (if it was set), so that the search
499 below will always be able to find a compatible processor. */
500 insn_flags &= ~FL_MODE26;
502 else if (!TARGET_APCS_32)
505 if (sought != 0 && ((sought & insn_flags) != sought))
507 /* Try to locate a CPU type that supports all of the abilities
508 of the default CPU, plus the extra abilities requested by
510 for (sel = all_cores; sel->name != NULL; sel++)
511 if ((sel->flags & sought) == (sought | insn_flags))
514 if (sel->name == NULL)
516 unsigned int current_bit_count = 0;
517 struct processors * best_fit = NULL;
519 /* Ideally we would like to issue an error message here
520 saying that it was not possible to find a CPU compatible
521 with the default CPU, but which also supports the command
522 line options specified by the programmer, and so they
523 ought to use the -mcpu=<name> command line option to
524 override the default CPU type.
526 Unfortunately this does not work with multilibing. We
527 need to be able to support multilibs for -mapcs-26 and for
528 -mthumb-interwork and there is no CPU that can support both
529 options. Instead if we cannot find a cpu that has both the
530 characteristics of the default cpu and the given command line
531 options we scan the array again looking for a best match. */
532 for (sel = all_cores; sel->name != NULL; sel++)
533 if ((sel->flags & sought) == sought)
537 count = bit_count (sel->flags & insn_flags);
539 if (count >= current_bit_count)
542 current_bit_count = count;
546 if (best_fit == NULL)
552 insn_flags = sel->flags;
556 /* If tuning has not been specified, tune for whichever processor or
557 architecture has been selected. */
559 tune_flags = insn_flags;
561 /* Make sure that the processor choice does not conflict with any of the
562 other command line choices. */
563 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
565 /* If APCS-32 was not the default then it must have been set by the
566 user, so issue a warning message. If the user has specified
567 "-mapcs-32 -mcpu=arm2" then we loose here. */
568 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
569 warning ("target CPU does not support APCS-32" );
570 target_flags &= ~ARM_FLAG_APCS_32;
572 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
574 warning ("target CPU does not support APCS-26" );
575 target_flags |= ARM_FLAG_APCS_32;
578 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
580 warning ("target CPU does not support interworking" );
581 target_flags &= ~ARM_FLAG_INTERWORK;
584 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
586 warning ("target CPU does not support THUMB instructions.");
587 target_flags &= ~ARM_FLAG_THUMB;
590 if (TARGET_APCS_FRAME && TARGET_THUMB)
592 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
593 target_flags &= ~ARM_FLAG_APCS_FRAME;
596 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
597 from here where no function is being compiled currently. */
598 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
600 warning ("enabling backtrace support is only meaningful when compiling for the Thumb.");
602 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
603 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
605 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
606 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
608 /* If interworking is enabled then APCS-32 must be selected as well. */
609 if (TARGET_INTERWORK)
612 warning ("interworking forces APCS-32 to be used" );
613 target_flags |= ARM_FLAG_APCS_32;
616 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
618 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
619 target_flags |= ARM_FLAG_APCS_FRAME;
622 if (TARGET_POKE_FUNCTION_NAME)
623 target_flags |= ARM_FLAG_APCS_FRAME;
625 if (TARGET_APCS_REENT && flag_pic)
626 error ("-fpic and -mapcs-reent are incompatible");
628 if (TARGET_APCS_REENT)
629 warning ("APCS reentrant code not supported. Ignored");
631 /* If this target is normally configured to use APCS frames, warn if they
632 are turned off and debugging is turned on. */
634 && write_symbols != NO_DEBUG
635 && !TARGET_APCS_FRAME
636 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
637 warning ("-g with -mno-apcs-frame may not give sensible debugging");
639 /* If stack checking is disabled, we can use r10 as the PIC register,
640 which keeps r9 available. */
641 if (flag_pic && !TARGET_APCS_STACK)
642 arm_pic_register = 10;
644 if (TARGET_APCS_FLOAT)
645 warning ("Passing floating point arguments in fp regs not yet supported");
647 /* Initialise boolean versions of the flags, for use in the arm.md file. */
648 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
649 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
650 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
651 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
652 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
654 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
655 arm_is_strong = (tune_flags & FL_STRONG) != 0;
656 thumb_code = (TARGET_ARM == 0);
657 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
658 && !(tune_flags & FL_ARCH4))) != 0;
660 /* Default value for floating point code... if no co-processor
661 bus, then schedule for emulated floating point. Otherwise,
662 assume the user has an FPA.
663 Note: this does not prevent use of floating point instructions,
664 -msoft-float does that. */
665 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
669 if (streq (target_fp_name, "2"))
670 arm_fpu_arch = FP_SOFT2;
671 else if (streq (target_fp_name, "3"))
672 arm_fpu_arch = FP_SOFT3;
674 error ("Invalid floating point emulation option: -mfpe-%s",
678 arm_fpu_arch = FP_DEFAULT;
680 if (TARGET_FPE && arm_fpu != FP_HARD)
683 /* For arm2/3 there is no need to do any scheduling if there is only
684 a floating point emulator, or we are doing software floating-point. */
685 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
686 && (tune_flags & FL_MODE32) == 0)
687 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
689 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
691 if (structure_size_string != NULL)
693 int size = strtol (structure_size_string, NULL, 0);
695 if (size == 8 || size == 32)
696 arm_structure_size_boundary = size;
698 warning ("Structure size boundary can only be set to 8 or 32");
701 if (arm_pic_register_string != NULL)
706 warning ("-mpic-register= is useless without -fpic");
708 pic_register = decode_reg_name (arm_pic_register_string);
710 /* Prevent the user from choosing an obviously stupid PIC register. */
711 if (pic_register < 0 || call_used_regs[pic_register]
712 || pic_register == HARD_FRAME_POINTER_REGNUM
713 || pic_register == STACK_POINTER_REGNUM
714 || pic_register >= PC_REGNUM)
715 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
717 arm_pic_register = pic_register;
720 if (TARGET_THUMB && flag_schedule_insns)
722 /* Don't warn since it's on by default in -O2. */
723 flag_schedule_insns = 0;
726 /* If optimizing for space, don't synthesize constants.
727 For processors with load scheduling, it never costs more than 2 cycles
728 to load a constant, and the load scheduler may well reduce that to 1. */
729 if (optimize_size || (tune_flags & FL_LDSCHED))
730 arm_constant_limit = 1;
733 arm_constant_limit = 2;
735 /* If optimizing for size, bump the number of instructions that we
736 are prepared to conditionally execute (even on a StrongARM).
737 Otherwise for the StrongARM, which has early execution of branches,
738 a sequence that is worth skipping is shorter. */
740 max_insns_skipped = 6;
741 else if (arm_is_strong)
742 max_insns_skipped = 3;
744 /* Register global variables with the garbage collector. */
751 ggc_add_rtx_root (&arm_compare_op0, 1);
752 ggc_add_rtx_root (&arm_compare_op1, 1);
753 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */
755 gcc_obstack_init(&minipool_obstack);
756 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
759 /* A table of known ARM exception types.
760 For use with the interrupt function attribute. */
765 unsigned long return_value;
769 static isr_attribute_arg isr_attribute_args [] =
771 { "IRQ", ARM_FT_ISR },
772 { "irq", ARM_FT_ISR },
773 { "FIQ", ARM_FT_FIQ },
774 { "fiq", ARM_FT_FIQ },
775 { "ABORT", ARM_FT_ISR },
776 { "abort", ARM_FT_ISR },
777 { "ABORT", ARM_FT_ISR },
778 { "abort", ARM_FT_ISR },
779 { "UNDEF", ARM_FT_EXCEPTION },
780 { "undef", ARM_FT_EXCEPTION },
781 { "SWI", ARM_FT_EXCEPTION },
782 { "swi", ARM_FT_EXCEPTION },
783 { NULL, ARM_FT_NORMAL }
786 /* Returns the (interrupt) function type of the current
787 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
790 arm_isr_value (argument)
793 isr_attribute_arg * ptr;
796 /* No argument - default to IRQ. */
797 if (argument == NULL_TREE)
800 /* Get the value of the argument. */
801 if (TREE_VALUE (argument) == NULL_TREE
802 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
803 return ARM_FT_UNKNOWN;
805 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
807 /* Check it against the list of known arguments. */
808 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
809 if (strcmp (arg, ptr->arg) == 0)
810 return ptr->return_value;
812 /* An unrecognised interrupt type. */
813 return ARM_FT_UNKNOWN;
816 /* Computes the type of the current function. */
819 arm_compute_func_type ()
821 unsigned long type = ARM_FT_UNKNOWN;
825 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
828 /* Decide if the current function is volatile. Such functions
829 never return, and many memory cycles can be saved by not storing
830 register values that will never be needed again. This optimization
831 was added to speed up context switching in a kernel application. */
833 && current_function_nothrow
834 && TREE_THIS_VOLATILE (current_function_decl))
835 type |= ARM_FT_VOLATILE;
837 if (current_function_needs_context)
838 type |= ARM_FT_NESTED;
840 attr = DECL_MACHINE_ATTRIBUTES (current_function_decl);
842 a = lookup_attribute ("naked", attr);
844 type |= ARM_FT_NAKED;
846 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
847 type |= ARM_FT_EXCEPTION_HANDLER;
850 a = lookup_attribute ("isr", attr);
852 a = lookup_attribute ("interrupt", attr);
855 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
857 type |= arm_isr_value (TREE_VALUE (a));
863 /* Returns the type of the current function. */
866 arm_current_func_type ()
868 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
869 cfun->machine->func_type = arm_compute_func_type ();
871 return cfun->machine->func_type;
874 /* Return 1 if it is possible to return using a single instruction. */
877 use_return_insn (iscond)
881 unsigned int func_type;
883 /* Never use a return instruction before reload has run. */
884 if (!reload_completed)
887 func_type = arm_current_func_type ();
889 /* Naked functions, volatile functiond and interrupt
890 functions all need special consideration. */
891 if (func_type & (ARM_FT_INTERRUPT | ARM_FT_VOLATILE | ARM_FT_NAKED))
894 /* As do variadic functions. */
895 if (current_function_pretend_args_size
896 || current_function_anonymous_args
897 /* Of if the function calls __builtin_eh_return () */
898 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
899 /* Or if there is no frame pointer and there is a stack adjustment. */
900 || ((get_frame_size () + current_function_outgoing_args_size != 0)
901 && !frame_pointer_needed))
904 /* Can't be done if interworking with Thumb, and any registers have been
905 stacked. Similarly, on StrongARM, conditional returns are expensive
906 if they aren't taken and registers have been stacked. */
907 if (iscond && arm_is_strong && frame_pointer_needed)
910 if ((iscond && arm_is_strong)
913 for (regno = 0; regno <= LAST_ARM_REGNUM; regno++)
914 if (regs_ever_live[regno] && !call_used_regs[regno])
917 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
921 /* Can't be done if any of the FPU regs are pushed,
922 since this also requires an insn. */
923 if (TARGET_HARD_FLOAT)
924 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
925 if (regs_ever_live[regno] && !call_used_regs[regno])
931 /* Return TRUE if int I is a valid immediate ARM constant. */
937 unsigned HOST_WIDE_INT mask = ~HOST_UINT (0xFF);
939 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
940 be all zero, or all one. */
941 if ((i & ~HOST_UINT (0xffffffff)) != 0
942 && ((i & ~HOST_UINT (0xffffffff))
944 & ~HOST_UINT (0xffffffff))))
947 /* Fast return for 0 and powers of 2 */
948 if ((i & (i - 1)) == 0)
953 if ((i & mask & HOST_UINT (0xffffffff)) == 0)
956 (mask << 2) | ((mask & HOST_UINT (0xffffffff))
957 >> (32 - 2)) | ~(HOST_UINT (0xffffffff));
958 } while (mask != ~HOST_UINT (0xFF));
963 /* Return true if I is a valid constant for the operation CODE. */
965 const_ok_for_op (i, code)
969 if (const_ok_for_arm (i))
975 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
977 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
983 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
990 /* Emit a sequence of insns to handle a large constant.
991 CODE is the code of the operation required, it can be any of SET, PLUS,
992 IOR, AND, XOR, MINUS;
993 MODE is the mode in which the operation is being performed;
994 VAL is the integer to operate on;
995 SOURCE is the other operand (a register, or a null-pointer for SET);
996 SUBTARGETS means it is safe to create scratch registers if that will
997 either produce a simpler sequence, or we will want to cse the values.
998 Return value is the number of insns emitted. */
1001 arm_split_constant (code, mode, val, target, source, subtargets)
1003 enum machine_mode mode;
1009 if (subtargets || code == SET
1010 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1011 && REGNO (target) != REGNO (source)))
1013 /* After arm_reorg has been called, we can't fix up expensive
1014 constants by pushing them into memory so we must synthesise
1015 them in-line, regardless of the cost. This is only likely to
1016 be more costly on chips that have load delay slots and we are
1017 compiling without running the scheduler (so no splitting
1018 occurred before the final instruction emission).
1020 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1022 if (!after_arm_reorg
1023 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1024 > arm_constant_limit + (code != SET)))
1028 /* Currently SET is the only monadic value for CODE, all
1029 the rest are diadic. */
1030 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1035 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1037 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1038 /* For MINUS, the value is subtracted from, since we never
1039 have subtraction of a constant. */
1041 emit_insn (gen_rtx_SET (VOIDmode, target,
1042 gen_rtx_MINUS (mode, temp, source)));
1044 emit_insn (gen_rtx_SET (VOIDmode, target,
1045 gen_rtx (code, mode, source, temp)));
1051 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1055 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1057 HOST_WIDE_INT temp1;
1065 if (remainder & (3 << (i - 2)))
1070 temp1 = remainder & ((0x0ff << end)
1071 | ((i < end) ? (0xff >> (32 - end)) : 0));
1072 remainder &= ~temp1;
1077 } while (remainder);
1081 /* As above, but extra parameter GENERATE which, if clear, suppresses
1084 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1086 enum machine_mode mode;
1095 int can_negate_initial = 0;
1098 int num_bits_set = 0;
1099 int set_sign_bit_copies = 0;
1100 int clear_sign_bit_copies = 0;
1101 int clear_zero_bit_copies = 0;
1102 int set_zero_bit_copies = 0;
1104 unsigned HOST_WIDE_INT temp1, temp2;
1105 unsigned HOST_WIDE_INT remainder = val & HOST_UINT (0xffffffff);
1107 /* Find out which operations are safe for a given CODE. Also do a quick
1108 check for degenerate cases; these can occur when DImode operations
1120 can_negate_initial = 1;
1124 if (remainder == HOST_UINT (0xffffffff))
1127 emit_insn (gen_rtx_SET (VOIDmode, target,
1128 GEN_INT (ARM_SIGN_EXTEND (val))));
1133 if (reload_completed && rtx_equal_p (target, source))
1136 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1145 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1148 if (remainder == HOST_UINT (0xffffffff))
1150 if (reload_completed && rtx_equal_p (target, source))
1153 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1162 if (reload_completed && rtx_equal_p (target, source))
1165 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1168 if (remainder == HOST_UINT (0xffffffff))
1171 emit_insn (gen_rtx_SET (VOIDmode, target,
1172 gen_rtx_NOT (mode, source)));
1176 /* We don't know how to handle this yet below. */
1180 /* We treat MINUS as (val - source), since (source - val) is always
1181 passed as (source + (-val)). */
1185 emit_insn (gen_rtx_SET (VOIDmode, target,
1186 gen_rtx_NEG (mode, source)));
1189 if (const_ok_for_arm (val))
1192 emit_insn (gen_rtx_SET (VOIDmode, target,
1193 gen_rtx_MINUS (mode, GEN_INT (val),
1205 /* If we can do it in one insn get out quickly. */
1206 if (const_ok_for_arm (val)
1207 || (can_negate_initial && const_ok_for_arm (-val))
1208 || (can_invert && const_ok_for_arm (~val)))
1211 emit_insn (gen_rtx_SET (VOIDmode, target,
1212 (source ? gen_rtx (code, mode, source,
1218 /* Calculate a few attributes that may be useful for specific
1220 for (i = 31; i >= 0; i--)
1222 if ((remainder & (1 << i)) == 0)
1223 clear_sign_bit_copies++;
1228 for (i = 31; i >= 0; i--)
1230 if ((remainder & (1 << i)) != 0)
1231 set_sign_bit_copies++;
1236 for (i = 0; i <= 31; i++)
1238 if ((remainder & (1 << i)) == 0)
1239 clear_zero_bit_copies++;
1244 for (i = 0; i <= 31; i++)
1246 if ((remainder & (1 << i)) != 0)
1247 set_zero_bit_copies++;
1255 /* See if we can do this by sign_extending a constant that is known
1256 to be negative. This is a good, way of doing it, since the shift
1257 may well merge into a subsequent insn. */
1258 if (set_sign_bit_copies > 1)
1260 if (const_ok_for_arm
1261 (temp1 = ARM_SIGN_EXTEND (remainder
1262 << (set_sign_bit_copies - 1))))
1266 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1267 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1269 emit_insn (gen_ashrsi3 (target, new_src,
1270 GEN_INT (set_sign_bit_copies - 1)));
1274 /* For an inverted constant, we will need to set the low bits,
1275 these will be shifted out of harm's way. */
1276 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1277 if (const_ok_for_arm (~temp1))
1281 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1282 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1284 emit_insn (gen_ashrsi3 (target, new_src,
1285 GEN_INT (set_sign_bit_copies - 1)));
1291 /* See if we can generate this by setting the bottom (or the top)
1292 16 bits, and then shifting these into the other half of the
1293 word. We only look for the simplest cases, to do more would cost
1294 too much. Be careful, however, not to generate this when the
1295 alternative would take fewer insns. */
1296 if (val & HOST_UINT (0xffff0000))
1298 temp1 = remainder & HOST_UINT (0xffff0000);
1299 temp2 = remainder & 0x0000ffff;
1301 /* Overlaps outside this range are best done using other methods. */
1302 for (i = 9; i < 24; i++)
1304 if ((((temp2 | (temp2 << i))
1305 & HOST_UINT (0xffffffff)) == remainder)
1306 && !const_ok_for_arm (temp2))
1308 rtx new_src = (subtargets
1309 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1311 insns = arm_gen_constant (code, mode, temp2, new_src,
1312 source, subtargets, generate);
1315 emit_insn (gen_rtx_SET
1318 gen_rtx_ASHIFT (mode, source,
1325 /* Don't duplicate cases already considered. */
1326 for (i = 17; i < 24; i++)
1328 if (((temp1 | (temp1 >> i)) == remainder)
1329 && !const_ok_for_arm (temp1))
1331 rtx new_src = (subtargets
1332 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1334 insns = arm_gen_constant (code, mode, temp1, new_src,
1335 source, subtargets, generate);
1339 (gen_rtx_SET (VOIDmode, target,
1342 gen_rtx_LSHIFTRT (mode, source,
1353 /* If we have IOR or XOR, and the constant can be loaded in a
1354 single instruction, and we can find a temporary to put it in,
1355 then this can be done in two instructions instead of 3-4. */
1357 /* TARGET can't be NULL if SUBTARGETS is 0 */
1358 || (reload_completed && !reg_mentioned_p (target, source)))
1360 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1364 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1366 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1367 emit_insn (gen_rtx_SET (VOIDmode, target,
1368 gen_rtx (code, mode, source, sub)));
1377 if (set_sign_bit_copies > 8
1378 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1382 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1383 rtx shift = GEN_INT (set_sign_bit_copies);
1385 emit_insn (gen_rtx_SET (VOIDmode, sub,
1387 gen_rtx_ASHIFT (mode,
1390 emit_insn (gen_rtx_SET (VOIDmode, target,
1392 gen_rtx_LSHIFTRT (mode, sub,
1398 if (set_zero_bit_copies > 8
1399 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1403 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1404 rtx shift = GEN_INT (set_zero_bit_copies);
1406 emit_insn (gen_rtx_SET (VOIDmode, sub,
1408 gen_rtx_LSHIFTRT (mode,
1411 emit_insn (gen_rtx_SET (VOIDmode, target,
1413 gen_rtx_ASHIFT (mode, sub,
1419 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1423 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1424 emit_insn (gen_rtx_SET (VOIDmode, sub,
1425 gen_rtx_NOT (mode, source)));
1428 sub = gen_reg_rtx (mode);
1429 emit_insn (gen_rtx_SET (VOIDmode, sub,
1430 gen_rtx_AND (mode, source,
1432 emit_insn (gen_rtx_SET (VOIDmode, target,
1433 gen_rtx_NOT (mode, sub)));
1440 /* See if two shifts will do 2 or more insn's worth of work. */
1441 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1443 HOST_WIDE_INT shift_mask = (((HOST_UINT (0xffffffff))
1444 << (32 - clear_sign_bit_copies))
1445 & HOST_UINT (0xffffffff));
1447 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1451 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1452 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1453 new_src, source, subtargets, 1);
1458 rtx targ = subtargets ? NULL_RTX : target;
1459 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1460 targ, source, subtargets, 0);
1466 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1467 rtx shift = GEN_INT (clear_sign_bit_copies);
1469 emit_insn (gen_ashlsi3 (new_src, source, shift));
1470 emit_insn (gen_lshrsi3 (target, new_src, shift));
1476 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1478 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1480 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1484 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1486 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1487 new_src, source, subtargets, 1);
1492 rtx targ = subtargets ? NULL_RTX : target;
1494 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1495 targ, source, subtargets, 0);
1501 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1502 rtx shift = GEN_INT (clear_zero_bit_copies);
1504 emit_insn (gen_lshrsi3 (new_src, source, shift));
1505 emit_insn (gen_ashlsi3 (target, new_src, shift));
1517 for (i = 0; i < 32; i++)
1518 if (remainder & (1 << i))
1521 if (code == AND || (can_invert && num_bits_set > 16))
1522 remainder = (~remainder) & HOST_UINT (0xffffffff);
1523 else if (code == PLUS && num_bits_set > 16)
1524 remainder = (-remainder) & HOST_UINT (0xffffffff);
1531 /* Now try and find a way of doing the job in either two or three
1533 We start by looking for the largest block of zeros that are aligned on
1534 a 2-bit boundary, we then fill up the temps, wrapping around to the
1535 top of the word when we drop off the bottom.
1536 In the worst case this code should produce no more than four insns. */
1539 int best_consecutive_zeros = 0;
1541 for (i = 0; i < 32; i += 2)
1543 int consecutive_zeros = 0;
1545 if (!(remainder & (3 << i)))
1547 while ((i < 32) && !(remainder & (3 << i)))
1549 consecutive_zeros += 2;
1552 if (consecutive_zeros > best_consecutive_zeros)
1554 best_consecutive_zeros = consecutive_zeros;
1555 best_start = i - consecutive_zeros;
1561 /* So long as it won't require any more insns to do so, it's
1562 desirable to emit a small constant (in bits 0...9) in the last
1563 insn. This way there is more chance that it can be combined with
1564 a later addressing insn to form a pre-indexed load or store
1565 operation. Consider:
1567 *((volatile int *)0xe0000100) = 1;
1568 *((volatile int *)0xe0000110) = 2;
1570 We want this to wind up as:
1574 str rB, [rA, #0x100]
1576 str rB, [rA, #0x110]
1578 rather than having to synthesize both large constants from scratch.
1580 Therefore, we calculate how many insns would be required to emit
1581 the constant starting from `best_start', and also starting from
1582 zero (ie with bit 31 first to be output). If `best_start' doesn't
1583 yield a shorter sequence, we may as well use zero. */
1585 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1586 && (count_insns_for_constant (remainder, 0) <=
1587 count_insns_for_constant (remainder, best_start)))
1590 /* Now start emitting the insns. */
1598 if (remainder & (3 << (i - 2)))
1603 temp1 = remainder & ((0x0ff << end)
1604 | ((i < end) ? (0xff >> (32 - end)) : 0));
1605 remainder &= ~temp1;
1612 emit_insn (gen_rtx_SET (VOIDmode,
1613 new_src = (subtargets
1614 ? gen_reg_rtx (mode)
1617 ? ~temp1 : temp1)));
1618 else if (code == MINUS)
1619 emit_insn (gen_rtx_SET (VOIDmode,
1620 new_src = (subtargets
1621 ? gen_reg_rtx (mode)
1623 gen_rtx (code, mode, GEN_INT (temp1),
1626 emit_insn (gen_rtx_SET (VOIDmode,
1627 new_src = (remainder
1629 ? gen_reg_rtx (mode)
1632 gen_rtx (code, mode, source,
1633 GEN_INT (can_invert ? ~temp1
1645 else if (code == MINUS)
1652 } while (remainder);
1657 /* Canonicalize a comparison so that we are more likely to recognize it.
1658 This can be done for a few constant compares, where we can make the
1659 immediate value easier to load. */
1661 arm_canonicalize_comparison (code, op1)
1665 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1675 if (i != (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1676 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1678 *op1 = GEN_INT (i + 1);
1679 return code == GT ? GE : LT;
1685 if (i != ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1))
1686 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1688 *op1 = GEN_INT (i - 1);
1689 return code == GE ? GT : LE;
1695 if (i != ~(HOST_UINT (0))
1696 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1698 *op1 = GEN_INT (i + 1);
1699 return code == GTU ? GEU : LTU;
1706 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1708 *op1 = GEN_INT (i - 1);
1709 return code == GEU ? GTU : LEU;
1720 /* Decide whether a type should be returned in memory (true)
1721 or in a register (false). This is called by the macro
1722 RETURN_IN_MEMORY. */
1724 arm_return_in_memory (type)
1727 if (!AGGREGATE_TYPE_P (type))
1728 /* All simple types are returned in registers. */
1731 /* For the arm-wince targets we choose to be compitable with Microsoft's
1732 ARM and Thumb compilers, which always return aggregates in memory. */
1735 if (int_size_in_bytes (type) > 4)
1736 /* All structures/unions bigger than one word are returned in memory. */
1739 if (TREE_CODE (type) == RECORD_TYPE)
1743 /* For a struct the APCS says that we only return in a register
1744 if the type is 'integer like' and every addressable element
1745 has an offset of zero. For practical purposes this means
1746 that the structure can have at most one non bit-field element
1747 and that this element must be the first one in the structure. */
1749 /* Find the first field, ignoring non FIELD_DECL things which will
1750 have been created by C++. */
1751 for (field = TYPE_FIELDS (type);
1752 field && TREE_CODE (field) != FIELD_DECL;
1753 field = TREE_CHAIN (field))
1757 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1759 /* Check that the first field is valid for returning in a register. */
1761 /* ... Floats are not allowed */
1762 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1765 /* ... Aggregates that are not themselves valid for returning in
1766 a register are not allowed. */
1767 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1770 /* Now check the remaining fields, if any. Only bitfields are allowed,
1771 since they are not addressable. */
1772 for (field = TREE_CHAIN (field);
1774 field = TREE_CHAIN (field))
1776 if (TREE_CODE (field) != FIELD_DECL)
1779 if (!DECL_BIT_FIELD_TYPE (field))
1786 if (TREE_CODE (type) == UNION_TYPE)
1790 /* Unions can be returned in registers if every element is
1791 integral, or can be returned in an integer register. */
1792 for (field = TYPE_FIELDS (type);
1794 field = TREE_CHAIN (field))
1796 if (TREE_CODE (field) != FIELD_DECL)
1799 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1802 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1808 #endif /* not ARM_WINCE */
1810 /* Return all other types in memory. */
1814 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1815 for a call to a function whose data type is FNTYPE.
1816 For a library call, FNTYPE is NULL. */
1818 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1819 CUMULATIVE_ARGS * pcum;
1821 rtx libname ATTRIBUTE_UNUSED;
1822 int indirect ATTRIBUTE_UNUSED;
1824 /* On the ARM, the offset starts at 0. */
1825 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1827 pcum->call_cookie = CALL_NORMAL;
1829 if (TARGET_LONG_CALLS)
1830 pcum->call_cookie = CALL_LONG;
1832 /* Check for long call/short call attributes. The attributes
1833 override any command line option. */
1836 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1837 pcum->call_cookie = CALL_SHORT;
1838 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1839 pcum->call_cookie = CALL_LONG;
1843 /* Determine where to put an argument to a function.
1844 Value is zero to push the argument on the stack,
1845 or a hard register in which to store the argument.
1847 MODE is the argument's machine mode.
1848 TYPE is the data type of the argument (as a tree).
1849 This is null for libcalls where that information may
1851 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1852 the preceding args and about the function being called.
1853 NAMED is nonzero if this argument is a named parameter
1854 (otherwise it is an extra parameter matching an ellipsis). */
1856 arm_function_arg (pcum, mode, type, named)
1857 CUMULATIVE_ARGS * pcum;
1858 enum machine_mode mode;
1859 tree type ATTRIBUTE_UNUSED;
1862 if (mode == VOIDmode)
1863 /* Compute operand 2 of the call insn. */
1864 return GEN_INT (pcum->call_cookie);
1866 if (!named || pcum->nregs >= NUM_ARG_REGS)
1869 return gen_rtx_REG (mode, pcum->nregs);
1872 /* Encode the current state of the #pragma [no_]long_calls. */
1875 OFF, /* No #pramgma [no_]long_calls is in effect. */
1876 LONG, /* #pragma long_calls is in effect. */
1877 SHORT /* #pragma no_long_calls is in effect. */
1880 static arm_pragma_enum arm_pragma_long_calls = OFF;
1883 arm_pr_long_calls (pfile)
1884 cpp_reader *pfile ATTRIBUTE_UNUSED;
1886 arm_pragma_long_calls = LONG;
1890 arm_pr_no_long_calls (pfile)
1891 cpp_reader *pfile ATTRIBUTE_UNUSED;
1893 arm_pragma_long_calls = SHORT;
1897 arm_pr_long_calls_off (pfile)
1898 cpp_reader *pfile ATTRIBUTE_UNUSED;
1900 arm_pragma_long_calls = OFF;
1904 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine
1905 specific attribute for TYPE. The attributes in ATTRIBUTES have
1906 previously been assigned to TYPE. */
1908 arm_valid_type_attribute_p (type, attributes, identifier, args)
1910 tree attributes ATTRIBUTE_UNUSED;
1914 if ( TREE_CODE (type) != FUNCTION_TYPE
1915 && TREE_CODE (type) != METHOD_TYPE
1916 && TREE_CODE (type) != FIELD_DECL
1917 && TREE_CODE (type) != TYPE_DECL)
1920 /* Function calls made to this symbol must be done indirectly, because
1921 it may lie outside of the 26 bit addressing range of a normal function
1923 if (is_attribute_p ("long_call", identifier))
1924 return (args == NULL_TREE);
1926 /* Whereas these functions are always known to reside within the 26 bit
1927 addressing range. */
1928 if (is_attribute_p ("short_call", identifier))
1929 return (args == NULL_TREE);
1931 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1932 if (is_attribute_p ("isr", identifier)
1933 || is_attribute_p ("interrupt", identifier))
1934 return arm_isr_value (args);
1939 /* Return 0 if the attributes for two types are incompatible, 1 if they
1940 are compatible, and 2 if they are nearly compatible (which causes a
1941 warning to be generated). */
1943 arm_comp_type_attributes (type1, type2)
1949 /* Check for mismatch of non-default calling convention. */
1950 if (TREE_CODE (type1) != FUNCTION_TYPE)
1953 /* Check for mismatched call attributes. */
1954 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1955 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1956 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1957 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1959 /* Only bother to check if an attribute is defined. */
1960 if (l1 | l2 | s1 | s2)
1962 /* If one type has an attribute, the other must have the same attribute. */
1963 if ((l1 != l2) || (s1 != s2))
1966 /* Disallow mixed attributes. */
1967 if ((l1 & s2) || (l2 & s1))
1971 /* Check for mismatched ISR attribute. */
1972 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
1974 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
1975 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
1977 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
1984 /* Encode long_call or short_call attribute by prefixing
1985 symbol name in DECL with a special character FLAG. */
1987 arm_encode_call_attribute (decl, flag)
1991 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1992 int len = strlen (str);
1995 if (TREE_CODE (decl) != FUNCTION_DECL)
1998 /* Do not allow weak functions to be treated as short call. */
1999 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2002 newstr = alloca (len + 2);
2004 strcpy (newstr + 1, str);
2006 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2007 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2010 /* Assigns default attributes to newly defined type. This is used to
2011 set short_call/long_call attributes for function types of
2012 functions defined inside corresponding #pragma scopes. */
2014 arm_set_default_type_attributes (type)
2017 /* Add __attribute__ ((long_call)) to all functions, when
2018 inside #pragma long_calls or __attribute__ ((short_call)),
2019 when inside #pragma no_long_calls. */
2020 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2022 tree type_attr_list, attr_name;
2023 type_attr_list = TYPE_ATTRIBUTES (type);
2025 if (arm_pragma_long_calls == LONG)
2026 attr_name = get_identifier ("long_call");
2027 else if (arm_pragma_long_calls == SHORT)
2028 attr_name = get_identifier ("short_call");
2032 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2033 TYPE_ATTRIBUTES (type) = type_attr_list;
2037 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2038 defined within the current compilation unit. If this caanot be
2039 determined, then 0 is returned. */
2041 current_file_function_operand (sym_ref)
2044 /* This is a bit of a fib. A function will have a short call flag
2045 applied to its name if it has the short call attribute, or it has
2046 already been defined within the current compilation unit. */
2047 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2050 /* The current function is always defined within the current compilation
2051 unit. if it s a weak defintion however, then this may not be the real
2052 defintion of the function, and so we have to say no. */
2053 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2054 && !DECL_WEAK (current_function_decl))
2057 /* We cannot make the determination - default to returning 0. */
2061 /* Return non-zero if a 32 bit "long_call" should be generated for
2062 this call. We generate a long_call if the function:
2064 a. has an __attribute__((long call))
2065 or b. is within the scope of a #pragma long_calls
2066 or c. the -mlong-calls command line switch has been specified
2068 However we do not generate a long call if the function:
2070 d. has an __attribute__ ((short_call))
2071 or e. is inside the scope of a #pragma no_long_calls
2072 or f. has an __attribute__ ((section))
2073 or g. is defined within the current compilation unit.
2075 This function will be called by C fragments contained in the machine
2076 description file. CALL_REF and CALL_COOKIE correspond to the matched
2077 rtl operands. CALL_SYMBOL is used to distinguish between
2078 two different callers of the function. It is set to 1 in the
2079 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2080 and "call_value" patterns. This is because of the difference in the
2081 SYM_REFs passed by these patterns. */
2083 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2090 if (GET_CODE (sym_ref) != MEM)
2093 sym_ref = XEXP (sym_ref, 0);
2096 if (GET_CODE (sym_ref) != SYMBOL_REF)
2099 if (call_cookie & CALL_SHORT)
2102 if (TARGET_LONG_CALLS && flag_function_sections)
2105 if (current_file_function_operand (sym_ref))
2108 return (call_cookie & CALL_LONG)
2109 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2110 || TARGET_LONG_CALLS;
2113 /* Return non-zero if it is ok to make a tail-call to DECL. */
2115 arm_function_ok_for_sibcall (decl)
2118 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2120 /* Never tailcall something for which we have no decl, or if we
2121 are in Thumb mode. */
2122 if (decl == NULL || TARGET_THUMB)
2125 /* Get the calling method. */
2126 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2127 call_type = CALL_SHORT;
2128 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2129 call_type = CALL_LONG;
2131 /* Cannot tail-call to long calls, since these are out of range of
2132 a branch instruction. However, if not compiling PIC, we know
2133 we can reach the symbol if it is in this compilation unit. */
2134 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2137 /* If we are interworking and the function is not declared static
2138 then we can't tail-call it unless we know that it exists in this
2139 compilation unit (since it might be a Thumb routine). */
2140 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2143 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2144 if (IS_INTERRUPT (arm_current_func_type ()))
2147 /* Everything else is ok. */
2153 legitimate_pic_operand_p (x)
2158 && (GET_CODE (x) == SYMBOL_REF
2159 || (GET_CODE (x) == CONST
2160 && GET_CODE (XEXP (x, 0)) == PLUS
2161 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2168 legitimize_pic_address (orig, mode, reg)
2170 enum machine_mode mode;
2173 if (GET_CODE (orig) == SYMBOL_REF)
2175 rtx pic_ref, address;
2184 reg = gen_reg_rtx (Pmode);
2189 #ifdef AOF_ASSEMBLER
2190 /* The AOF assembler can generate relocations for these directly, and
2191 understands that the PIC register has to be added into the offset. */
2192 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2195 address = gen_reg_rtx (Pmode);
2200 emit_insn (gen_pic_load_addr_arm (address, orig));
2202 emit_insn (gen_pic_load_addr_thumb (address, orig));
2204 pic_ref = gen_rtx_MEM (Pmode,
2205 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2207 RTX_UNCHANGING_P (pic_ref) = 1;
2208 insn = emit_move_insn (reg, pic_ref);
2210 current_function_uses_pic_offset_table = 1;
2211 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2213 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2217 else if (GET_CODE (orig) == CONST)
2221 if (GET_CODE (XEXP (orig, 0)) == PLUS
2222 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2230 reg = gen_reg_rtx (Pmode);
2233 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2235 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2236 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2237 base == reg ? 0 : reg);
2242 if (GET_CODE (offset) == CONST_INT)
2244 /* The base register doesn't really matter, we only want to
2245 test the index for the appropriate mode. */
2246 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
2248 if (!no_new_pseudos)
2249 offset = force_reg (Pmode, offset);
2254 if (GET_CODE (offset) == CONST_INT)
2255 return plus_constant (base, INTVAL (offset));
2258 if (GET_MODE_SIZE (mode) > 4
2259 && (GET_MODE_CLASS (mode) == MODE_INT
2260 || TARGET_SOFT_FLOAT))
2262 emit_insn (gen_addsi3 (reg, base, offset));
2266 return gen_rtx_PLUS (Pmode, base, offset);
2268 else if (GET_CODE (orig) == LABEL_REF)
2270 current_function_uses_pic_offset_table = 1;
2274 rtx pic_ref, address = gen_reg_rtx (Pmode);
2277 emit_insn (gen_pic_load_addr_arm (address, orig));
2279 emit_insn (gen_pic_load_addr_thumb (address, orig));
2281 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2283 emit_move_insn (address, pic_ref);
2291 /* Generate code to load the PIC register. PROLOGUE is true if
2292 called from arm_expand_prologue (in which case we want the
2293 generated insns at the start of the function); false if called
2294 by an exception receiver that needs the PIC register reloaded
2295 (in which case the insns are just dumped at the current location). */
2298 arm_finalize_pic (prologue)
2301 #ifndef AOF_ASSEMBLER
2302 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2303 rtx global_offset_table;
2305 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2312 l1 = gen_label_rtx ();
2314 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2315 /* On the ARM the PC register contains 'dot + 8' at the time of the
2316 addition, on the Thumb it is 'dot + 4'. */
2317 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2319 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2320 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2322 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2324 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2328 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2329 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2333 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2334 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2337 seq = gen_sequence ();
2340 emit_insn_after (seq, get_insns ());
2344 /* Need to emit this whether or not we obey regdecls,
2345 since setjmp/longjmp can cause life info to screw up. */
2346 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2347 #endif /* AOF_ASSEMBLER */
2350 #define REG_OR_SUBREG_REG(X) \
2351 (GET_CODE (X) == REG \
2352 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2354 #define REG_OR_SUBREG_RTX(X) \
2355 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2357 #ifndef COSTS_N_INSNS
2358 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2362 arm_rtx_costs (x, code, outer)
2365 enum rtx_code outer;
2367 enum machine_mode mode = GET_MODE (x);
2368 enum rtx_code subcode;
2384 return COSTS_N_INSNS (1);
2387 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2390 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2397 return COSTS_N_INSNS (2) + cycles;
2399 return COSTS_N_INSNS (1) + 16;
2402 return (COSTS_N_INSNS (1)
2403 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2404 + GET_CODE (SET_DEST (x)) == MEM));
2409 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2411 if (thumb_shiftable_const (INTVAL (x)))
2412 return COSTS_N_INSNS (2);
2413 return COSTS_N_INSNS (3);
2415 else if (outer == PLUS
2416 && INTVAL (x) < 256 && INTVAL (x) > -256)
2418 else if (outer == COMPARE
2419 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2421 else if (outer == ASHIFT || outer == ASHIFTRT
2422 || outer == LSHIFTRT)
2424 return COSTS_N_INSNS (2);
2430 return COSTS_N_INSNS (3);
2449 /* XXX another guess. */
2450 /* Memory costs quite a lot for the first word, but subsequent words
2451 load at the equivalent of a single insn each. */
2452 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2453 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2457 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2462 /* XXX still guessing. */
2463 switch (GET_MODE (XEXP (x, 0)))
2466 return (1 + (mode == DImode ? 4 : 0)
2467 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2470 return (4 + (mode == DImode ? 4 : 0)
2471 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2474 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2488 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2498 /* Memory costs quite a lot for the first word, but subsequent words
2499 load at the equivalent of a single insn each. */
2500 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2501 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2508 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2515 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2517 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2518 + ((GET_CODE (XEXP (x, 0)) == REG
2519 || (GET_CODE (XEXP (x, 0)) == SUBREG
2520 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2522 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2523 || (GET_CODE (XEXP (x, 0)) == SUBREG
2524 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2526 + ((GET_CODE (XEXP (x, 1)) == REG
2527 || (GET_CODE (XEXP (x, 1)) == SUBREG
2528 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2529 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2534 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2535 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2536 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2537 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2540 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2541 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2542 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2543 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2545 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2546 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2547 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2550 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2551 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2552 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2553 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2554 || subcode == ASHIFTRT || subcode == LSHIFTRT
2555 || subcode == ROTATE || subcode == ROTATERT
2557 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2558 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2559 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2560 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2561 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2562 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2563 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2568 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2569 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2570 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2571 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2572 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2576 case AND: case XOR: case IOR:
2579 /* Normally the frame registers will be spilt into reg+const during
2580 reload, so it is a bad idea to combine them with other instructions,
2581 since then they might not be moved outside of loops. As a compromise
2582 we allow integration with ops that have a constant as their second
2584 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2585 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2586 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2587 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2588 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2592 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2593 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2594 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2595 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2598 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2599 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2600 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2601 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2602 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2605 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2606 return (1 + extra_cost
2607 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2608 || subcode == LSHIFTRT || subcode == ASHIFTRT
2609 || subcode == ROTATE || subcode == ROTATERT
2611 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2612 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2613 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2614 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2615 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2616 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2622 /* There is no point basing this on the tuning, since it is always the
2623 fast variant if it exists at all. */
2624 if (arm_fast_multiply && mode == DImode
2625 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2626 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2627 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2630 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2634 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2636 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2637 & HOST_UINT (0xffffffff));
2638 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2641 /* Tune as appropriate. */
2642 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2644 for (j = 0; i && j < 32; j += booth_unit_size)
2646 i >>= booth_unit_size;
2653 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2654 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2655 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2658 if (arm_fast_multiply && mode == SImode
2659 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2660 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2661 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2662 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2663 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2664 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2669 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2670 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2674 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2676 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2679 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2687 return 4 + (mode == DImode ? 4 : 0);
2690 if (GET_MODE (XEXP (x, 0)) == QImode)
2691 return (4 + (mode == DImode ? 4 : 0)
2692 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2695 switch (GET_MODE (XEXP (x, 0)))
2698 return (1 + (mode == DImode ? 4 : 0)
2699 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2702 return (4 + (mode == DImode ? 4 : 0)
2703 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2706 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2714 if (const_ok_for_arm (INTVAL (x)))
2715 return outer == SET ? 2 : -1;
2716 else if (outer == AND
2717 && const_ok_for_arm (~INTVAL (x)))
2719 else if ((outer == COMPARE
2720 || outer == PLUS || outer == MINUS)
2721 && const_ok_for_arm (-INTVAL (x)))
2732 if (const_double_rtx_ok_for_fpu (x))
2733 return outer == SET ? 2 : -1;
2734 else if ((outer == COMPARE || outer == PLUS)
2735 && neg_const_double_rtx_ok_for_fpu (x))
2745 arm_adjust_cost (insn, link, dep, cost)
2753 /* Some true dependencies can have a higher cost depending
2754 on precisely how certain input operands are used. */
2756 && REG_NOTE_KIND (link) == 0
2757 && recog_memoized (insn) < 0
2758 && recog_memoized (dep) < 0)
2760 int shift_opnum = get_attr_shift (insn);
2761 enum attr_type attr_type = get_attr_type (dep);
2763 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2764 operand for INSN. If we have a shifted input operand and the
2765 instruction we depend on is another ALU instruction, then we may
2766 have to account for an additional stall. */
2767 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2769 rtx shifted_operand;
2772 /* Get the shifted operand. */
2773 extract_insn (insn);
2774 shifted_operand = recog_data.operand[shift_opnum];
2776 /* Iterate over all the operands in DEP. If we write an operand
2777 that overlaps with SHIFTED_OPERAND, then we have increase the
2778 cost of this dependency. */
2780 preprocess_constraints ();
2781 for (opno = 0; opno < recog_data.n_operands; opno++)
2783 /* We can ignore strict inputs. */
2784 if (recog_data.operand_type[opno] == OP_IN)
2787 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2794 /* XXX This is not strictly true for the FPA. */
2795 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2796 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2799 /* Call insns don't incur a stall, even if they follow a load. */
2800 if (REG_NOTE_KIND (link) == 0
2801 && GET_CODE (insn) == CALL_INSN)
2804 if ((i_pat = single_set (insn)) != NULL
2805 && GET_CODE (SET_SRC (i_pat)) == MEM
2806 && (d_pat = single_set (dep)) != NULL
2807 && GET_CODE (SET_DEST (d_pat)) == MEM)
2809 /* This is a load after a store, there is no conflict if the load reads
2810 from a cached area. Assume that loads from the stack, and from the
2811 constant pool are cached, and that others will miss. This is a
2814 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2815 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2816 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2817 || reg_mentioned_p (hard_frame_pointer_rtx,
2818 XEXP (SET_SRC (i_pat), 0)))
2825 /* This code has been fixed for cross compilation. */
2827 static int fpa_consts_inited = 0;
2829 static const char * strings_fpa[8] =
2832 "4", "5", "0.5", "10"
2835 static REAL_VALUE_TYPE values_fpa[8];
2843 for (i = 0; i < 8; i++)
2845 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2849 fpa_consts_inited = 1;
2852 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2855 const_double_rtx_ok_for_fpu (x)
2861 if (!fpa_consts_inited)
2864 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2865 if (REAL_VALUE_MINUS_ZERO (r))
2868 for (i = 0; i < 8; i++)
2869 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2875 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2878 neg_const_double_rtx_ok_for_fpu (x)
2884 if (!fpa_consts_inited)
2887 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2888 r = REAL_VALUE_NEGATE (r);
2889 if (REAL_VALUE_MINUS_ZERO (r))
2892 for (i = 0; i < 8; i++)
2893 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2899 /* Predicates for `match_operand' and `match_operator'. */
2901 /* s_register_operand is the same as register_operand, but it doesn't accept
2904 This function exists because at the time it was put in it led to better
2905 code. SUBREG(MEM) always needs a reload in the places where
2906 s_register_operand is used, and this seemed to lead to excessive
2910 s_register_operand (op, mode)
2912 enum machine_mode mode;
2914 if (GET_MODE (op) != mode && mode != VOIDmode)
2917 if (GET_CODE (op) == SUBREG)
2918 op = SUBREG_REG (op);
2920 /* We don't consider registers whose class is NO_REGS
2921 to be a register operand. */
2922 /* XXX might have to check for lo regs only for thumb ??? */
2923 return (GET_CODE (op) == REG
2924 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2925 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2928 /* A hard register operand (even before reload. */
2930 arm_hard_register_operand (op, mode)
2932 enum machine_mode mode;
2934 if (GET_MODE (op) != mode && mode != VOIDmode)
2937 return (GET_CODE (op) == REG
2938 && REGNO (op) < FIRST_PSEUDO_REGISTER);
2941 /* Only accept reg, subreg(reg), const_int. */
2944 reg_or_int_operand (op, mode)
2946 enum machine_mode mode;
2948 if (GET_CODE (op) == CONST_INT)
2951 if (GET_MODE (op) != mode && mode != VOIDmode)
2954 if (GET_CODE (op) == SUBREG)
2955 op = SUBREG_REG (op);
2957 /* We don't consider registers whose class is NO_REGS
2958 to be a register operand. */
2959 return (GET_CODE (op) == REG
2960 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2961 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2964 /* Return 1 if OP is an item in memory, given that we are in reload. */
2967 arm_reload_memory_operand (op, mode)
2969 enum machine_mode mode ATTRIBUTE_UNUSED;
2971 int regno = true_regnum (op);
2973 return (!CONSTANT_P (op)
2975 || (GET_CODE (op) == REG
2976 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2979 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2980 memory access (architecture V4).
2981 MODE is QImode if called when computing contraints, or VOIDmode when
2982 emitting patterns. In this latter case we cannot use memory_operand()
2983 because it will fail on badly formed MEMs, which is precisly what we are
2986 bad_signed_byte_operand (op, mode)
2988 enum machine_mode mode ATTRIBUTE_UNUSED;
2991 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
2994 if (GET_CODE (op) != MEM)
2999 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3000 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3001 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3002 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3003 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3006 /* Big constants are also bad. */
3007 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3008 && (INTVAL (XEXP (op, 1)) > 0xff
3009 || -INTVAL (XEXP (op, 1)) > 0xff))
3012 /* Everything else is good, or can will automatically be made so. */
3016 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3019 arm_rhs_operand (op, mode)
3021 enum machine_mode mode;
3023 return (s_register_operand (op, mode)
3024 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3027 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
3031 arm_rhsm_operand (op, mode)
3033 enum machine_mode mode;
3035 return (s_register_operand (op, mode)
3036 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3037 || memory_operand (op, mode));
3040 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3041 constant that is valid when negated. */
3044 arm_add_operand (op, mode)
3046 enum machine_mode mode;
3049 return thumb_cmp_operand (op, mode);
3051 return (s_register_operand (op, mode)
3052 || (GET_CODE (op) == CONST_INT
3053 && (const_ok_for_arm (INTVAL (op))
3054 || const_ok_for_arm (-INTVAL (op)))));
3058 arm_not_operand (op, mode)
3060 enum machine_mode mode;
3062 return (s_register_operand (op, mode)
3063 || (GET_CODE (op) == CONST_INT
3064 && (const_ok_for_arm (INTVAL (op))
3065 || const_ok_for_arm (~INTVAL (op)))));
3068 /* Return TRUE if the operand is a memory reference which contains an
3069 offsettable address. */
3071 offsettable_memory_operand (op, mode)
3073 enum machine_mode mode;
3075 if (mode == VOIDmode)
3076 mode = GET_MODE (op);
3078 return (mode == GET_MODE (op)
3079 && GET_CODE (op) == MEM
3080 && offsettable_address_p (reload_completed | reload_in_progress,
3081 mode, XEXP (op, 0)));
3084 /* Return TRUE if the operand is a memory reference which is, or can be
3085 made word aligned by adjusting the offset. */
3087 alignable_memory_operand (op, mode)
3089 enum machine_mode mode;
3093 if (mode == VOIDmode)
3094 mode = GET_MODE (op);
3096 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3101 return ((GET_CODE (reg = op) == REG
3102 || (GET_CODE (op) == SUBREG
3103 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3104 || (GET_CODE (op) == PLUS
3105 && GET_CODE (XEXP (op, 1)) == CONST_INT
3106 && (GET_CODE (reg = XEXP (op, 0)) == REG
3107 || (GET_CODE (XEXP (op, 0)) == SUBREG
3108 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3109 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3112 /* Similar to s_register_operand, but does not allow hard integer
3115 f_register_operand (op, mode)
3117 enum machine_mode mode;
3119 if (GET_MODE (op) != mode && mode != VOIDmode)
3122 if (GET_CODE (op) == SUBREG)
3123 op = SUBREG_REG (op);
3125 /* We don't consider registers whose class is NO_REGS
3126 to be a register operand. */
3127 return (GET_CODE (op) == REG
3128 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3129 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3132 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3135 fpu_rhs_operand (op, mode)
3137 enum machine_mode mode;
3139 if (s_register_operand (op, mode))
3142 if (GET_MODE (op) != mode && mode != VOIDmode)
3145 if (GET_CODE (op) == CONST_DOUBLE)
3146 return const_double_rtx_ok_for_fpu (op);
3152 fpu_add_operand (op, mode)
3154 enum machine_mode mode;
3156 if (s_register_operand (op, mode))
3159 if (GET_MODE (op) != mode && mode != VOIDmode)
3162 if (GET_CODE (op) == CONST_DOUBLE)
3163 return (const_double_rtx_ok_for_fpu (op)
3164 || neg_const_double_rtx_ok_for_fpu (op));
3169 /* Return nonzero if OP is a constant power of two. */
3172 power_of_two_operand (op, mode)
3174 enum machine_mode mode ATTRIBUTE_UNUSED;
3176 if (GET_CODE (op) == CONST_INT)
3178 HOST_WIDE_INT value = INTVAL (op);
3179 return value != 0 && (value & (value - 1)) == 0;
3184 /* Return TRUE for a valid operand of a DImode operation.
3185 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3186 Note that this disallows MEM(REG+REG), but allows
3187 MEM(PRE/POST_INC/DEC(REG)). */
3190 di_operand (op, mode)
3192 enum machine_mode mode;
3194 if (s_register_operand (op, mode))
3197 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3200 if (GET_CODE (op) == SUBREG)
3201 op = SUBREG_REG (op);
3203 switch (GET_CODE (op))
3210 return memory_address_p (DImode, XEXP (op, 0));
3217 /* Like di_operand, but don't accept constants. */
3219 nonimmediate_di_operand (op, mode)
3221 enum machine_mode mode;
3223 if (s_register_operand (op, mode))
3226 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3229 if (GET_CODE (op) == SUBREG)
3230 op = SUBREG_REG (op);
3232 if (GET_CODE (op) == MEM)
3233 return memory_address_p (DImode, XEXP (op, 0));
3238 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3239 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3240 Note that this disallows MEM(REG+REG), but allows
3241 MEM(PRE/POST_INC/DEC(REG)). */
3244 soft_df_operand (op, mode)
3246 enum machine_mode mode;
3248 if (s_register_operand (op, mode))
3251 if (mode != VOIDmode && GET_MODE (op) != mode)
3254 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
3257 if (GET_CODE (op) == SUBREG)
3258 op = SUBREG_REG (op);
3260 switch (GET_CODE (op))
3266 return memory_address_p (DFmode, XEXP (op, 0));
3273 /* Like soft_df_operand, but don't accept constants. */
3275 nonimmediate_soft_df_operand (op, mode)
3277 enum machine_mode mode;
3279 if (s_register_operand (op, mode))
3282 if (mode != VOIDmode && GET_MODE (op) != mode)
3285 if (GET_CODE (op) == SUBREG)
3286 op = SUBREG_REG (op);
3288 if (GET_CODE (op) == MEM)
3289 return memory_address_p (DFmode, XEXP (op, 0));
3293 /* Return TRUE for valid index operands. */
3295 index_operand (op, mode)
3297 enum machine_mode mode;
3299 return (s_register_operand (op, mode)
3300 || (immediate_operand (op, mode)
3301 && (GET_CODE (op) != CONST_INT
3302 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3305 /* Return TRUE for valid shifts by a constant. This also accepts any
3306 power of two on the (somewhat overly relaxed) assumption that the
3307 shift operator in this case was a mult. */
3310 const_shift_operand (op, mode)
3312 enum machine_mode mode;
3314 return (power_of_two_operand (op, mode)
3315 || (immediate_operand (op, mode)
3316 && (GET_CODE (op) != CONST_INT
3317 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3320 /* Return TRUE for arithmetic operators which can be combined with a multiply
3324 shiftable_operator (x, mode)
3326 enum machine_mode mode;
3328 if (GET_MODE (x) != mode)
3332 enum rtx_code code = GET_CODE (x);
3334 return (code == PLUS || code == MINUS
3335 || code == IOR || code == XOR || code == AND);
3339 /* Return TRUE for binary logical operators. */
3342 logical_binary_operator (x, mode)
3344 enum machine_mode mode;
3346 if (GET_MODE (x) != mode)
3350 enum rtx_code code = GET_CODE (x);
3352 return (code == IOR || code == XOR || code == AND);
3356 /* Return TRUE for shift operators. */
3359 shift_operator (x, mode)
3361 enum machine_mode mode;
3363 if (GET_MODE (x) != mode)
3367 enum rtx_code code = GET_CODE (x);
3370 return power_of_two_operand (XEXP (x, 1), mode);
3372 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3373 || code == ROTATERT);
3377 /* Return TRUE if x is EQ or NE. */
3379 equality_operator (x, mode)
3381 enum machine_mode mode ATTRIBUTE_UNUSED;
3383 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3386 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3388 arm_comparison_operator (x, mode)
3390 enum machine_mode mode;
3392 return (comparison_operator (x, mode)
3393 && GET_CODE (x) != LTGT
3394 && GET_CODE (x) != UNEQ);
3397 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3399 minmax_operator (x, mode)
3401 enum machine_mode mode;
3403 enum rtx_code code = GET_CODE (x);
3405 if (GET_MODE (x) != mode)
3408 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3411 /* Return TRUE if this is the condition code register, if we aren't given
3412 a mode, accept any class CCmode register. */
3414 cc_register (x, mode)
3416 enum machine_mode mode;
3418 if (mode == VOIDmode)
3420 mode = GET_MODE (x);
3422 if (GET_MODE_CLASS (mode) != MODE_CC)
3426 if ( GET_MODE (x) == mode
3427 && GET_CODE (x) == REG
3428 && REGNO (x) == CC_REGNUM)
3434 /* Return TRUE if this is the condition code register, if we aren't given
3435 a mode, accept any class CCmode register which indicates a dominance
3438 dominant_cc_register (x, mode)
3440 enum machine_mode mode;
3442 if (mode == VOIDmode)
3444 mode = GET_MODE (x);
3446 if (GET_MODE_CLASS (mode) != MODE_CC)
3450 if ( mode != CC_DNEmode && mode != CC_DEQmode
3451 && mode != CC_DLEmode && mode != CC_DLTmode
3452 && mode != CC_DGEmode && mode != CC_DGTmode
3453 && mode != CC_DLEUmode && mode != CC_DLTUmode
3454 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3457 return cc_register (x, mode);
3460 /* Return TRUE if X references a SYMBOL_REF. */
3462 symbol_mentioned_p (x)
3465 register const char * fmt;
3468 if (GET_CODE (x) == SYMBOL_REF)
3471 fmt = GET_RTX_FORMAT (GET_CODE (x));
3473 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3479 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3480 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3483 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3490 /* Return TRUE if X references a LABEL_REF. */
3492 label_mentioned_p (x)
3495 register const char * fmt;
3498 if (GET_CODE (x) == LABEL_REF)
3501 fmt = GET_RTX_FORMAT (GET_CODE (x));
3502 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3508 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3509 if (label_mentioned_p (XVECEXP (x, i, j)))
3512 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3523 enum rtx_code code = GET_CODE (x);
3527 else if (code == SMIN)
3529 else if (code == UMIN)
3531 else if (code == UMAX)
3537 /* Return 1 if memory locations are adjacent. */
3539 adjacent_mem_locations (a, b)
3542 int val0 = 0, val1 = 0;
3545 if ((GET_CODE (XEXP (a, 0)) == REG
3546 || (GET_CODE (XEXP (a, 0)) == PLUS
3547 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3548 && (GET_CODE (XEXP (b, 0)) == REG
3549 || (GET_CODE (XEXP (b, 0)) == PLUS
3550 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3552 if (GET_CODE (XEXP (a, 0)) == PLUS)
3554 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3555 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3558 reg0 = REGNO (XEXP (a, 0));
3559 if (GET_CODE (XEXP (b, 0)) == PLUS)
3561 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3562 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3565 reg1 = REGNO (XEXP (b, 0));
3566 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3571 /* Return 1 if OP is a load multiple operation. It is known to be
3572 parallel and the first section will be tested. */
3574 load_multiple_operation (op, mode)
3576 enum machine_mode mode ATTRIBUTE_UNUSED;
3578 HOST_WIDE_INT count = XVECLEN (op, 0);
3581 HOST_WIDE_INT i = 1, base = 0;
3585 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3588 /* Check to see if this might be a write-back. */
3589 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3594 /* Now check it more carefully. */
3595 if (GET_CODE (SET_DEST (elt)) != REG
3596 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3597 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3598 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3599 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3603 /* Perform a quick check so we don't blow up below. */
3605 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3606 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3607 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3610 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3611 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3613 for (; i < count; i++)
3615 elt = XVECEXP (op, 0, i);
3617 if (GET_CODE (elt) != SET
3618 || GET_CODE (SET_DEST (elt)) != REG
3619 || GET_MODE (SET_DEST (elt)) != SImode
3620 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3621 || GET_CODE (SET_SRC (elt)) != MEM
3622 || GET_MODE (SET_SRC (elt)) != SImode
3623 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3624 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3625 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3626 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3633 /* Return 1 if OP is a store multiple operation. It is known to be
3634 parallel and the first section will be tested. */
3636 store_multiple_operation (op, mode)
3638 enum machine_mode mode ATTRIBUTE_UNUSED;
3640 HOST_WIDE_INT count = XVECLEN (op, 0);
3643 HOST_WIDE_INT i = 1, base = 0;
3647 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3650 /* Check to see if this might be a write-back. */
3651 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3656 /* Now check it more carefully. */
3657 if (GET_CODE (SET_DEST (elt)) != REG
3658 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3659 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3660 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3661 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3665 /* Perform a quick check so we don't blow up below. */
3667 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3668 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3669 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3672 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3673 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3675 for (; i < count; i++)
3677 elt = XVECEXP (op, 0, i);
3679 if (GET_CODE (elt) != SET
3680 || GET_CODE (SET_SRC (elt)) != REG
3681 || GET_MODE (SET_SRC (elt)) != SImode
3682 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3683 || GET_CODE (SET_DEST (elt)) != MEM
3684 || GET_MODE (SET_DEST (elt)) != SImode
3685 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3686 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3687 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3688 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3696 load_multiple_sequence (operands, nops, regs, base, load_offset)
3701 HOST_WIDE_INT * load_offset;
3703 int unsorted_regs[4];
3704 HOST_WIDE_INT unsorted_offsets[4];
3709 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3710 extended if required. */
3711 if (nops < 2 || nops > 4)
3714 /* Loop over the operands and check that the memory references are
3715 suitable (ie immediate offsets from the same base register). At
3716 the same time, extract the target register, and the memory
3718 for (i = 0; i < nops; i++)
3723 /* Convert a subreg of a mem into the mem itself. */
3724 if (GET_CODE (operands[nops + i]) == SUBREG)
3725 operands[nops + i] = alter_subreg (operands[nops + i]);
3727 if (GET_CODE (operands[nops + i]) != MEM)
3730 /* Don't reorder volatile memory references; it doesn't seem worth
3731 looking for the case where the order is ok anyway. */
3732 if (MEM_VOLATILE_P (operands[nops + i]))
3735 offset = const0_rtx;
3737 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3738 || (GET_CODE (reg) == SUBREG
3739 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3740 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3741 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3743 || (GET_CODE (reg) == SUBREG
3744 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3745 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3750 base_reg = REGNO (reg);
3751 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3752 ? REGNO (operands[i])
3753 : REGNO (SUBREG_REG (operands[i])));
3758 if (base_reg != (int) REGNO (reg))
3759 /* Not addressed from the same base register. */
3762 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3763 ? REGNO (operands[i])
3764 : REGNO (SUBREG_REG (operands[i])));
3765 if (unsorted_regs[i] < unsorted_regs[order[0]])
3769 /* If it isn't an integer register, or if it overwrites the
3770 base register but isn't the last insn in the list, then
3771 we can't do this. */
3772 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3773 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3776 unsorted_offsets[i] = INTVAL (offset);
3779 /* Not a suitable memory address. */
3783 /* All the useful information has now been extracted from the
3784 operands into unsorted_regs and unsorted_offsets; additionally,
3785 order[0] has been set to the lowest numbered register in the
3786 list. Sort the registers into order, and check that the memory
3787 offsets are ascending and adjacent. */
3789 for (i = 1; i < nops; i++)
3793 order[i] = order[i - 1];
3794 for (j = 0; j < nops; j++)
3795 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3796 && (order[i] == order[i - 1]
3797 || unsorted_regs[j] < unsorted_regs[order[i]]))
3800 /* Have we found a suitable register? if not, one must be used more
3802 if (order[i] == order[i - 1])
3805 /* Is the memory address adjacent and ascending? */
3806 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3814 for (i = 0; i < nops; i++)
3815 regs[i] = unsorted_regs[order[i]];
3817 *load_offset = unsorted_offsets[order[0]];
3820 if (unsorted_offsets[order[0]] == 0)
3821 return 1; /* ldmia */
3823 if (unsorted_offsets[order[0]] == 4)
3824 return 2; /* ldmib */
3826 if (unsorted_offsets[order[nops - 1]] == 0)
3827 return 3; /* ldmda */
3829 if (unsorted_offsets[order[nops - 1]] == -4)
3830 return 4; /* ldmdb */
3832 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3833 if the offset isn't small enough. The reason 2 ldrs are faster
3834 is because these ARMs are able to do more than one cache access
3835 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3836 whilst the ARM8 has a double bandwidth cache. This means that
3837 these cores can do both an instruction fetch and a data fetch in
3838 a single cycle, so the trick of calculating the address into a
3839 scratch register (one of the result regs) and then doing a load
3840 multiple actually becomes slower (and no smaller in code size).
3841 That is the transformation
3843 ldr rd1, [rbase + offset]
3844 ldr rd2, [rbase + offset + 4]
3848 add rd1, rbase, offset
3849 ldmia rd1, {rd1, rd2}
3851 produces worse code -- '3 cycles + any stalls on rd2' instead of
3852 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3853 access per cycle, the first sequence could never complete in less
3854 than 6 cycles, whereas the ldm sequence would only take 5 and
3855 would make better use of sequential accesses if not hitting the
3858 We cheat here and test 'arm_ld_sched' which we currently know to
3859 only be true for the ARM8, ARM9 and StrongARM. If this ever
3860 changes, then the test below needs to be reworked. */
3861 if (nops == 2 && arm_ld_sched)
3864 /* Can't do it without setting up the offset, only do this if it takes
3865 no more than one insn. */
3866 return (const_ok_for_arm (unsorted_offsets[order[0]])
3867 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3871 emit_ldm_seq (operands, nops)
3877 HOST_WIDE_INT offset;
3881 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3884 strcpy (buf, "ldm%?ia\t");
3888 strcpy (buf, "ldm%?ib\t");
3892 strcpy (buf, "ldm%?da\t");
3896 strcpy (buf, "ldm%?db\t");
3901 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3902 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3905 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3906 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3908 output_asm_insn (buf, operands);
3910 strcpy (buf, "ldm%?ia\t");
3917 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3918 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3920 for (i = 1; i < nops; i++)
3921 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3922 reg_names[regs[i]]);
3924 strcat (buf, "}\t%@ phole ldm");
3926 output_asm_insn (buf, operands);
3931 store_multiple_sequence (operands, nops, regs, base, load_offset)
3936 HOST_WIDE_INT * load_offset;
3938 int unsorted_regs[4];
3939 HOST_WIDE_INT unsorted_offsets[4];
3944 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3945 extended if required. */
3946 if (nops < 2 || nops > 4)
3949 /* Loop over the operands and check that the memory references are
3950 suitable (ie immediate offsets from the same base register). At
3951 the same time, extract the target register, and the memory
3953 for (i = 0; i < nops; i++)
3958 /* Convert a subreg of a mem into the mem itself. */
3959 if (GET_CODE (operands[nops + i]) == SUBREG)
3960 operands[nops + i] = alter_subreg (operands[nops + i]);
3962 if (GET_CODE (operands[nops + i]) != MEM)
3965 /* Don't reorder volatile memory references; it doesn't seem worth
3966 looking for the case where the order is ok anyway. */
3967 if (MEM_VOLATILE_P (operands[nops + i]))
3970 offset = const0_rtx;
3972 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3973 || (GET_CODE (reg) == SUBREG
3974 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3975 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3976 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3978 || (GET_CODE (reg) == SUBREG
3979 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3980 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3985 base_reg = REGNO (reg);
3986 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3987 ? REGNO (operands[i])
3988 : REGNO (SUBREG_REG (operands[i])));
3993 if (base_reg != (int) REGNO (reg))
3994 /* Not addressed from the same base register. */
3997 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3998 ? REGNO (operands[i])
3999 : REGNO (SUBREG_REG (operands[i])));
4000 if (unsorted_regs[i] < unsorted_regs[order[0]])
4004 /* If it isn't an integer register, then we can't do this. */
4005 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
4008 unsorted_offsets[i] = INTVAL (offset);
4011 /* Not a suitable memory address. */
4015 /* All the useful information has now been extracted from the
4016 operands into unsorted_regs and unsorted_offsets; additionally,
4017 order[0] has been set to the lowest numbered register in the
4018 list. Sort the registers into order, and check that the memory
4019 offsets are ascending and adjacent. */
4021 for (i = 1; i < nops; i++)
4025 order[i] = order[i - 1];
4026 for (j = 0; j < nops; j++)
4027 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4028 && (order[i] == order[i - 1]
4029 || unsorted_regs[j] < unsorted_regs[order[i]]))
4032 /* Have we found a suitable register? if not, one must be used more
4034 if (order[i] == order[i - 1])
4037 /* Is the memory address adjacent and ascending? */
4038 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4046 for (i = 0; i < nops; i++)
4047 regs[i] = unsorted_regs[order[i]];
4049 *load_offset = unsorted_offsets[order[0]];
4052 if (unsorted_offsets[order[0]] == 0)
4053 return 1; /* stmia */
4055 if (unsorted_offsets[order[0]] == 4)
4056 return 2; /* stmib */
4058 if (unsorted_offsets[order[nops - 1]] == 0)
4059 return 3; /* stmda */
4061 if (unsorted_offsets[order[nops - 1]] == -4)
4062 return 4; /* stmdb */
4068 emit_stm_seq (operands, nops)
4074 HOST_WIDE_INT offset;
4078 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4081 strcpy (buf, "stm%?ia\t");
4085 strcpy (buf, "stm%?ib\t");
4089 strcpy (buf, "stm%?da\t");
4093 strcpy (buf, "stm%?db\t");
4100 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4101 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4103 for (i = 1; i < nops; i++)
4104 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4105 reg_names[regs[i]]);
4107 strcat (buf, "}\t%@ phole stm");
4109 output_asm_insn (buf, operands);
4114 multi_register_push (op, mode)
4116 enum machine_mode mode ATTRIBUTE_UNUSED;
4118 if (GET_CODE (op) != PARALLEL
4119 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
4120 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
4121 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
4127 /* Routines for use with attributes. */
4129 /* Return nonzero if ATTR is a valid attribute for DECL.
4130 ATTRIBUTES are any existing attributes and ARGS are
4131 the arguments supplied with ATTR.
4133 Supported attributes:
4136 don't output any prologue or epilogue code, the user is assumed
4137 to do the right thing.
4140 Interrupt Service Routine.
4143 Always assume that this function will be entered in ARM mode,
4144 not Thumb mode, and that the caller wishes to be returned to in
4147 arm_valid_decl_attribute_p (decl, attributes, attr, args)
4149 tree attributes ATTRIBUTE_UNUSED;
4153 /* The interrupt attribute can take args, so check for it before
4154 rejecting other attributes on the grounds that they did have args. */
4155 if (is_attribute_p ("isr", attr)
4156 || is_attribute_p ("interrupt", attr))
4157 return TREE_CODE (decl) == FUNCTION_DECL;
4159 if (args != NULL_TREE)
4162 if (is_attribute_p ("naked", attr))
4163 return TREE_CODE (decl) == FUNCTION_DECL;
4166 if (is_attribute_p ("interfacearm", attr))
4167 return TREE_CODE (decl) == FUNCTION_DECL;
4175 /* ARM/PE has three new attributes:
4176 naked - for interrupt functions
4177 dllexport - for exporting a function/variable that will live in a dll
4178 dllimport - for importing a function/variable from a dll
4180 Microsoft allows multiple declspecs in one __declspec, separating
4181 them with spaces. We do NOT support this. Instead, use __declspec
4186 arm_pe_valid_decl_attribute_p (decl, attributes, attr, args)
4192 if (args != NULL_TREE)
4195 if (is_attribute_p ("dllexport", attr))
4198 if (is_attribute_p ("dllimport", attr))
4201 return arm_valid_decl_attribute_p (decl, attributes, attr, args);
4206 /* Routines for use in generating RTL. */
4208 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
4209 in_struct_p, scalar_p)
4221 int sign = up ? 1 : -1;
4224 /* XScale has load-store double instructions, but they have stricter
4225 alignment requirements than load-store multiple, so we can not
4228 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4229 the pipeline until completion.
4237 An ldr instruction takes 1-3 cycles, but does not block the
4246 Best case ldr will always win. However, the more ldr instructions
4247 we issue, the less likely we are to be able to schedule them well.
4248 Using ldr instructions also increases code size.
4250 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4251 for counts of 3 or 4 regs. */
4252 if (arm_is_xscale && count <= 2 && ! optimize_size)
4258 for (i = 0; i < count; i++)
4260 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
4261 RTX_UNCHANGING_P (mem) = unchanging_p;
4262 MEM_IN_STRUCT_P (mem) = in_struct_p;
4263 MEM_SCALAR_P (mem) = scalar_p;
4264 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
4268 emit_move_insn (from, plus_constant (from, count * 4 * sign));
4270 seq = gen_sequence ();
4276 result = gen_rtx_PARALLEL (VOIDmode,
4277 rtvec_alloc (count + (write_back ? 1 : 0)));
4280 XVECEXP (result, 0, 0)
4281 = gen_rtx_SET (GET_MODE (from), from,
4282 plus_constant (from, count * 4 * sign));
4287 for (j = 0; i < count; i++, j++)
4289 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
4290 RTX_UNCHANGING_P (mem) = unchanging_p;
4291 MEM_IN_STRUCT_P (mem) = in_struct_p;
4292 MEM_SCALAR_P (mem) = scalar_p;
4293 XVECEXP (result, 0, i)
4294 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
4301 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
4302 in_struct_p, scalar_p)
4314 int sign = up ? 1 : -1;
4317 /* See arm_gen_load_multiple for discussion of
4318 the pros/cons of ldm/stm usage for XScale. */
4319 if (arm_is_xscale && count <= 2 && ! optimize_size)
4325 for (i = 0; i < count; i++)
4327 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4328 RTX_UNCHANGING_P (mem) = unchanging_p;
4329 MEM_IN_STRUCT_P (mem) = in_struct_p;
4330 MEM_SCALAR_P (mem) = scalar_p;
4331 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4335 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4337 seq = gen_sequence ();
4343 result = gen_rtx_PARALLEL (VOIDmode,
4344 rtvec_alloc (count + (write_back ? 1 : 0)));
4347 XVECEXP (result, 0, 0)
4348 = gen_rtx_SET (GET_MODE (to), to,
4349 plus_constant (to, count * 4 * sign));
4354 for (j = 0; i < count; i++, j++)
4356 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4357 RTX_UNCHANGING_P (mem) = unchanging_p;
4358 MEM_IN_STRUCT_P (mem) = in_struct_p;
4359 MEM_SCALAR_P (mem) = scalar_p;
4361 XVECEXP (result, 0, i)
4362 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4369 arm_gen_movstrqi (operands)
4372 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4375 rtx st_src, st_dst, fin_src, fin_dst;
4376 rtx part_bytes_reg = NULL;
4378 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4379 int dst_scalar_p, src_scalar_p;
4381 if (GET_CODE (operands[2]) != CONST_INT
4382 || GET_CODE (operands[3]) != CONST_INT
4383 || INTVAL (operands[2]) > 64
4384 || INTVAL (operands[3]) & 3)
4387 st_dst = XEXP (operands[0], 0);
4388 st_src = XEXP (operands[1], 0);
4390 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4391 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4392 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4393 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4394 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4395 src_scalar_p = MEM_SCALAR_P (operands[1]);
4397 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4398 fin_src = src = copy_to_mode_reg (SImode, st_src);
4400 in_words_to_go = NUM_INTS (INTVAL (operands[2]));
4401 out_words_to_go = INTVAL (operands[2]) / 4;
4402 last_bytes = INTVAL (operands[2]) & 3;
4404 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4405 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4407 for (i = 0; in_words_to_go >= 2; i+=4)
4409 if (in_words_to_go > 4)
4410 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4415 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4416 FALSE, src_unchanging_p,
4417 src_in_struct_p, src_scalar_p));
4419 if (out_words_to_go)
4421 if (out_words_to_go > 4)
4422 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4426 else if (out_words_to_go != 1)
4427 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4436 mem = gen_rtx_MEM (SImode, dst);
4437 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4438 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4439 MEM_SCALAR_P (mem) = dst_scalar_p;
4440 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4441 if (last_bytes != 0)
4442 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4446 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4447 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4450 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4451 if (out_words_to_go)
4455 mem = gen_rtx_MEM (SImode, src);
4456 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4457 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4458 MEM_SCALAR_P (mem) = src_scalar_p;
4459 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4460 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4462 mem = gen_rtx_MEM (SImode, dst);
4463 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4464 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4465 MEM_SCALAR_P (mem) = dst_scalar_p;
4466 emit_move_insn (mem, sreg);
4467 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4470 if (in_words_to_go) /* Sanity check */
4476 if (in_words_to_go < 0)
4479 mem = gen_rtx_MEM (SImode, src);
4480 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4481 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4482 MEM_SCALAR_P (mem) = src_scalar_p;
4483 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4486 if (last_bytes && part_bytes_reg == NULL)
4489 if (BYTES_BIG_ENDIAN && last_bytes)
4491 rtx tmp = gen_reg_rtx (SImode);
4493 /* The bytes we want are in the top end of the word. */
4494 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4495 GEN_INT (8 * (4 - last_bytes))));
4496 part_bytes_reg = tmp;
4500 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4501 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4502 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4503 MEM_SCALAR_P (mem) = dst_scalar_p;
4504 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4508 tmp = gen_reg_rtx (SImode);
4509 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4510 part_bytes_reg = tmp;
4519 mem = gen_rtx_MEM (HImode, dst);
4520 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4521 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4522 MEM_SCALAR_P (mem) = dst_scalar_p;
4523 emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
4527 rtx tmp = gen_reg_rtx (SImode);
4529 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4530 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4531 part_bytes_reg = tmp;
4537 mem = gen_rtx_MEM (QImode, dst);
4538 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4539 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4540 MEM_SCALAR_P (mem) = dst_scalar_p;
4541 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4548 /* Generate a memory reference for a half word, such that it will be loaded
4549 into the top 16 bits of the word. We can assume that the address is
4550 known to be alignable and of the form reg, or plus (reg, const). */
4552 arm_gen_rotated_half_load (memref)
4555 HOST_WIDE_INT offset = 0;
4556 rtx base = XEXP (memref, 0);
4558 if (GET_CODE (base) == PLUS)
4560 offset = INTVAL (XEXP (base, 1));
4561 base = XEXP (base, 0);
4564 /* If we aren't allowed to generate unaligned addresses, then fail. */
4565 if (TARGET_MMU_TRAPS
4566 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4569 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4571 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4574 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4577 /* Select a dominance comparison mode if possible. We support three forms.
4578 COND_OR == 0 => (X && Y)
4579 COND_OR == 1 => ((! X( || Y)
4580 COND_OR == 2 => (X || Y)
4581 If we are unable to support a dominance comparsison we return CC mode.
4582 This will then fail to match for the RTL expressions that generate this
4585 static enum machine_mode
4586 select_dominance_cc_mode (x, y, cond_or)
4589 HOST_WIDE_INT cond_or;
4591 enum rtx_code cond1, cond2;
4594 /* Currently we will probably get the wrong result if the individual
4595 comparisons are not simple. This also ensures that it is safe to
4596 reverse a comparison if necessary. */
4597 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4599 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4603 /* The if_then_else variant of this tests the second condition if the
4604 first passes, but is true if the first fails. Reverse the first
4605 condition to get a true "inclusive-or" expression. */
4607 cond1 = reverse_condition (cond1);
4609 /* If the comparisons are not equal, and one doesn't dominate the other,
4610 then we can't do this. */
4612 && !comparison_dominates_p (cond1, cond2)
4613 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4618 enum rtx_code temp = cond1;
4626 if (cond2 == EQ || !cond_or)
4631 case LE: return CC_DLEmode;
4632 case LEU: return CC_DLEUmode;
4633 case GE: return CC_DGEmode;
4634 case GEU: return CC_DGEUmode;
4641 if (cond2 == LT || !cond_or)
4650 if (cond2 == GT || !cond_or)
4659 if (cond2 == LTU || !cond_or)
4668 if (cond2 == GTU || !cond_or)
4676 /* The remaining cases only occur when both comparisons are the
4701 arm_select_cc_mode (op, x, y)
4706 /* All floating point compares return CCFP if it is an equality
4707 comparison, and CCFPE otherwise. */
4708 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4735 /* A compare with a shifted operand. Because of canonicalization, the
4736 comparison will have to be swapped when we emit the assembler. */
4737 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4738 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4739 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4740 || GET_CODE (x) == ROTATERT))
4743 /* This is a special case that is used by combine to allow a
4744 comparison of a shifted byte load to be split into a zero-extend
4745 followed by a comparison of the shifted integer (only valid for
4746 equalities and unsigned inequalities). */
4747 if (GET_MODE (x) == SImode
4748 && GET_CODE (x) == ASHIFT
4749 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4750 && GET_CODE (XEXP (x, 0)) == SUBREG
4751 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4752 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4753 && (op == EQ || op == NE
4754 || op == GEU || op == GTU || op == LTU || op == LEU)
4755 && GET_CODE (y) == CONST_INT)
4758 /* A construct for a conditional compare, if the false arm contains
4759 0, then both conditions must be true, otherwise either condition
4760 must be true. Not all conditions are possible, so CCmode is
4761 returned if it can't be done. */
4762 if (GET_CODE (x) == IF_THEN_ELSE
4763 && (XEXP (x, 2) == const0_rtx
4764 || XEXP (x, 2) == const1_rtx)
4765 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4766 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4767 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4768 INTVAL (XEXP (x, 2)));
4770 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4771 if (GET_CODE (x) == AND
4772 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4773 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4774 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4776 if (GET_CODE (x) == IOR
4777 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4778 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4779 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4781 /* An operation that sets the condition codes as a side-effect, the
4782 V flag is not set correctly, so we can only use comparisons where
4783 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4785 if (GET_MODE (x) == SImode
4787 && (op == EQ || op == NE || op == LT || op == GE)
4788 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4789 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4790 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4791 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4792 || GET_CODE (x) == LSHIFTRT
4793 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4794 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4797 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4800 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4801 && GET_CODE (x) == PLUS
4802 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4808 /* X and Y are two things to compare using CODE. Emit the compare insn and
4809 return the rtx for register 0 in the proper mode. FP means this is a
4810 floating point compare: I don't think that it is needed on the arm. */
4813 arm_gen_compare_reg (code, x, y)
4817 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4818 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4820 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4821 gen_rtx_COMPARE (mode, x, y)));
4827 arm_reload_in_hi (operands)
4830 rtx ref = operands[1];
4832 HOST_WIDE_INT offset = 0;
4834 if (GET_CODE (ref) == SUBREG)
4836 offset = SUBREG_BYTE (ref);
4837 ref = SUBREG_REG (ref);
4840 if (GET_CODE (ref) == REG)
4842 /* We have a pseudo which has been spilt onto the stack; there
4843 are two cases here: the first where there is a simple
4844 stack-slot replacement and a second where the stack-slot is
4845 out of range, or is used as a subreg. */
4846 if (reg_equiv_mem[REGNO (ref)])
4848 ref = reg_equiv_mem[REGNO (ref)];
4849 base = find_replacement (&XEXP (ref, 0));
4852 /* The slot is out of range, or was dressed up in a SUBREG. */
4853 base = reg_equiv_address[REGNO (ref)];
4856 base = find_replacement (&XEXP (ref, 0));
4858 /* Handle the case where the address is too complex to be offset by 1. */
4859 if (GET_CODE (base) == MINUS
4860 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4862 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4864 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4867 else if (GET_CODE (base) == PLUS)
4869 /* The addend must be CONST_INT, or we would have dealt with it above. */
4870 HOST_WIDE_INT hi, lo;
4872 offset += INTVAL (XEXP (base, 1));
4873 base = XEXP (base, 0);
4875 /* Rework the address into a legal sequence of insns. */
4876 /* Valid range for lo is -4095 -> 4095 */
4879 : -((-offset) & 0xfff));
4881 /* Corner case, if lo is the max offset then we would be out of range
4882 once we have added the additional 1 below, so bump the msb into the
4883 pre-loading insn(s). */
4887 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4888 ^ HOST_INT (0x80000000))
4889 - HOST_INT (0x80000000));
4891 if (hi + lo != offset)
4896 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4898 /* Get the base address; addsi3 knows how to handle constants
4899 that require more than one insn. */
4900 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4906 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4907 emit_insn (gen_zero_extendqisi2 (scratch,
4908 gen_rtx_MEM (QImode,
4909 plus_constant (base,
4911 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4912 gen_rtx_MEM (QImode,
4913 plus_constant (base,
4915 if (!BYTES_BIG_ENDIAN)
4916 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4917 gen_rtx_IOR (SImode,
4920 gen_rtx_SUBREG (SImode, operands[0], 0),
4924 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4925 gen_rtx_IOR (SImode,
4926 gen_rtx_ASHIFT (SImode, scratch,
4928 gen_rtx_SUBREG (SImode, operands[0],
4932 /* Handle storing a half-word to memory during reload by synthesising as two
4933 byte stores. Take care not to clobber the input values until after we
4934 have moved them somewhere safe. This code assumes that if the DImode
4935 scratch in operands[2] overlaps either the input value or output address
4936 in some way, then that value must die in this insn (we absolutely need
4937 two scratch registers for some corner cases). */
4939 arm_reload_out_hi (operands)
4942 rtx ref = operands[0];
4943 rtx outval = operands[1];
4945 HOST_WIDE_INT offset = 0;
4947 if (GET_CODE (ref) == SUBREG)
4949 offset = SUBREG_BYTE (ref);
4950 ref = SUBREG_REG (ref);
4954 if (GET_CODE (ref) == REG)
4956 /* We have a pseudo which has been spilt onto the stack; there
4957 are two cases here: the first where there is a simple
4958 stack-slot replacement and a second where the stack-slot is
4959 out of range, or is used as a subreg. */
4960 if (reg_equiv_mem[REGNO (ref)])
4962 ref = reg_equiv_mem[REGNO (ref)];
4963 base = find_replacement (&XEXP (ref, 0));
4966 /* The slot is out of range, or was dressed up in a SUBREG. */
4967 base = reg_equiv_address[REGNO (ref)];
4970 base = find_replacement (&XEXP (ref, 0));
4972 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4974 /* Handle the case where the address is too complex to be offset by 1. */
4975 if (GET_CODE (base) == MINUS
4976 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4978 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4980 /* Be careful not to destroy OUTVAL. */
4981 if (reg_overlap_mentioned_p (base_plus, outval))
4983 /* Updating base_plus might destroy outval, see if we can
4984 swap the scratch and base_plus. */
4985 if (!reg_overlap_mentioned_p (scratch, outval))
4988 scratch = base_plus;
4993 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4995 /* Be conservative and copy OUTVAL into the scratch now,
4996 this should only be necessary if outval is a subreg
4997 of something larger than a word. */
4998 /* XXX Might this clobber base? I can't see how it can,
4999 since scratch is known to overlap with OUTVAL, and
5000 must be wider than a word. */
5001 emit_insn (gen_movhi (scratch_hi, outval));
5002 outval = scratch_hi;
5006 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5009 else if (GET_CODE (base) == PLUS)
5011 /* The addend must be CONST_INT, or we would have dealt with it above. */
5012 HOST_WIDE_INT hi, lo;
5014 offset += INTVAL (XEXP (base, 1));
5015 base = XEXP (base, 0);
5017 /* Rework the address into a legal sequence of insns. */
5018 /* Valid range for lo is -4095 -> 4095 */
5021 : -((-offset) & 0xfff));
5023 /* Corner case, if lo is the max offset then we would be out of range
5024 once we have added the additional 1 below, so bump the msb into the
5025 pre-loading insn(s). */
5029 hi = ((((offset - lo) & HOST_INT (0xffffffff))
5030 ^ HOST_INT (0x80000000))
5031 - HOST_INT (0x80000000));
5033 if (hi + lo != offset)
5038 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5040 /* Be careful not to destroy OUTVAL. */
5041 if (reg_overlap_mentioned_p (base_plus, outval))
5043 /* Updating base_plus might destroy outval, see if we
5044 can swap the scratch and base_plus. */
5045 if (!reg_overlap_mentioned_p (scratch, outval))
5048 scratch = base_plus;
5053 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5055 /* Be conservative and copy outval into scratch now,
5056 this should only be necessary if outval is a
5057 subreg of something larger than a word. */
5058 /* XXX Might this clobber base? I can't see how it
5059 can, since scratch is known to overlap with
5061 emit_insn (gen_movhi (scratch_hi, outval));
5062 outval = scratch_hi;
5066 /* Get the base address; addsi3 knows how to handle constants
5067 that require more than one insn. */
5068 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5074 if (BYTES_BIG_ENDIAN)
5076 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5077 plus_constant (base, offset + 1)),
5078 gen_rtx_SUBREG (QImode, outval, 0)));
5079 emit_insn (gen_lshrsi3 (scratch,
5080 gen_rtx_SUBREG (SImode, outval, 0),
5082 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5083 gen_rtx_SUBREG (QImode, scratch, 0)));
5087 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5088 gen_rtx_SUBREG (QImode, outval, 0)));
5089 emit_insn (gen_lshrsi3 (scratch,
5090 gen_rtx_SUBREG (SImode, outval, 0),
5092 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5093 plus_constant (base, offset + 1)),
5094 gen_rtx_SUBREG (QImode, scratch, 0)));
5098 /* Print a symbolic form of X to the debug file, F. */
5100 arm_print_value (f, x)
5104 switch (GET_CODE (x))
5107 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5111 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5115 fprintf (f, "\"%s\"", XSTR (x, 0));
5119 fprintf (f, "`%s'", XSTR (x, 0));
5123 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5127 arm_print_value (f, XEXP (x, 0));
5131 arm_print_value (f, XEXP (x, 0));
5133 arm_print_value (f, XEXP (x, 1));
5141 fprintf (f, "????");
5146 /* Routines for manipulation of the constant pool. */
5148 /* Arm instructions cannot load a large constant directly into a
5149 register; they have to come from a pc relative load. The constant
5150 must therefore be placed in the addressable range of the pc
5151 relative load. Depending on the precise pc relative load
5152 instruction the range is somewhere between 256 bytes and 4k. This
5153 means that we often have to dump a constant inside a function, and
5154 generate code to branch around it.
5156 It is important to minimize this, since the branches will slow
5157 things down and make the code larger.
5159 Normally we can hide the table after an existing unconditional
5160 branch so that there is no interruption of the flow, but in the
5161 worst case the code looks like this:
5179 We fix this by performing a scan after scheduling, which notices
5180 which instructions need to have their operands fetched from the
5181 constant table and builds the table.
5183 The algorithm starts by building a table of all the constants that
5184 need fixing up and all the natural barriers in the function (places
5185 where a constant table can be dropped without breaking the flow).
5186 For each fixup we note how far the pc-relative replacement will be
5187 able to reach and the offset of the instruction into the function.
5189 Having built the table we then group the fixes together to form
5190 tables that are as large as possible (subject to addressing
5191 constraints) and emit each table of constants after the last
5192 barrier that is within range of all the instructions in the group.
5193 If a group does not contain a barrier, then we forcibly create one
5194 by inserting a jump instruction into the flow. Once the table has
5195 been inserted, the insns are then modified to reference the
5196 relevant entry in the pool.
5198 Possible enhancements to the algorithm (not implemented) are:
5200 1) For some processors and object formats, there may be benefit in
5201 aligning the pools to the start of cache lines; this alignment
5202 would need to be taken into account when calculating addressability
5205 /* These typedefs are located at the start of this file, so that
5206 they can be used in the prototypes there. This comment is to
5207 remind readers of that fact so that the following structures
5208 can be understood more easily.
5210 typedef struct minipool_node Mnode;
5211 typedef struct minipool_fixup Mfix; */
5213 struct minipool_node
5215 /* Doubly linked chain of entries. */
5218 /* The maximum offset into the code that this entry can be placed. While
5219 pushing fixes for forward references, all entries are sorted in order
5220 of increasing max_address. */
5221 HOST_WIDE_INT max_address;
5222 /* Similarly for a entry inserted for a backwards ref. */
5223 HOST_WIDE_INT min_address;
5224 /* The number of fixes referencing this entry. This can become zero
5225 if we "unpush" an entry. In this case we ignore the entry when we
5226 come to emit the code. */
5228 /* The offset from the start of the minipool. */
5229 HOST_WIDE_INT offset;
5230 /* The value in table. */
5232 /* The mode of value. */
5233 enum machine_mode mode;
5237 struct minipool_fixup
5241 HOST_WIDE_INT address;
5243 enum machine_mode mode;
5247 HOST_WIDE_INT forwards;
5248 HOST_WIDE_INT backwards;
5251 /* Fixes less than a word need padding out to a word boundary. */
5252 #define MINIPOOL_FIX_SIZE(mode) \
5253 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5255 static Mnode * minipool_vector_head;
5256 static Mnode * minipool_vector_tail;
5257 static rtx minipool_vector_label;
5259 /* The linked list of all minipool fixes required for this function. */
5260 Mfix * minipool_fix_head;
5261 Mfix * minipool_fix_tail;
5262 /* The fix entry for the current minipool, once it has been placed. */
5263 Mfix * minipool_barrier;
5265 /* Determines if INSN is the start of a jump table. Returns the end
5266 of the TABLE or NULL_RTX. */
5268 is_jump_table (insn)
5273 if (GET_CODE (insn) == JUMP_INSN
5274 && JUMP_LABEL (insn) != NULL
5275 && ((table = next_real_insn (JUMP_LABEL (insn)))
5276 == next_real_insn (insn))
5278 && GET_CODE (table) == JUMP_INSN
5279 && (GET_CODE (PATTERN (table)) == ADDR_VEC
5280 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5286 static HOST_WIDE_INT
5287 get_jump_table_size (insn)
5290 rtx body = PATTERN (insn);
5291 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5293 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5296 /* Move a minipool fix MP from its current location to before MAX_MP.
5297 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5298 contrains may need updating. */
5300 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5303 HOST_WIDE_INT max_address;
5305 /* This should never be true and the code below assumes these are
5312 if (max_address < mp->max_address)
5313 mp->max_address = max_address;
5317 if (max_address > max_mp->max_address - mp->fix_size)
5318 mp->max_address = max_mp->max_address - mp->fix_size;
5320 mp->max_address = max_address;
5322 /* Unlink MP from its current position. Since max_mp is non-null,
5323 mp->prev must be non-null. */
5324 mp->prev->next = mp->next;
5325 if (mp->next != NULL)
5326 mp->next->prev = mp->prev;
5328 minipool_vector_tail = mp->prev;
5330 /* Re-insert it before MAX_MP. */
5332 mp->prev = max_mp->prev;
5335 if (mp->prev != NULL)
5336 mp->prev->next = mp;
5338 minipool_vector_head = mp;
5341 /* Save the new entry. */
5344 /* Scan over the preceeding entries and adjust their addresses as
5346 while (mp->prev != NULL
5347 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5349 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5356 /* Add a constant to the minipool for a forward reference. Returns the
5357 node added or NULL if the constant will not fit in this pool. */
5359 add_minipool_forward_ref (fix)
5362 /* If set, max_mp is the first pool_entry that has a lower
5363 constraint than the one we are trying to add. */
5364 Mnode * max_mp = NULL;
5365 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5368 /* If this fix's address is greater than the address of the first
5369 entry, then we can't put the fix in this pool. We subtract the
5370 size of the current fix to ensure that if the table is fully
5371 packed we still have enough room to insert this value by suffling
5372 the other fixes forwards. */
5373 if (minipool_vector_head &&
5374 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5377 /* Scan the pool to see if a constant with the same value has
5378 already been added. While we are doing this, also note the
5379 location where we must insert the constant if it doesn't already
5381 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5383 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5384 && fix->mode == mp->mode
5385 && (GET_CODE (fix->value) != CODE_LABEL
5386 || (CODE_LABEL_NUMBER (fix->value)
5387 == CODE_LABEL_NUMBER (mp->value)))
5388 && rtx_equal_p (fix->value, mp->value))
5390 /* More than one fix references this entry. */
5392 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5395 /* Note the insertion point if necessary. */
5397 && mp->max_address > max_address)
5401 /* The value is not currently in the minipool, so we need to create
5402 a new entry for it. If MAX_MP is NULL, the entry will be put on
5403 the end of the list since the placement is less constrained than
5404 any existing entry. Otherwise, we insert the new fix before
5405 MAX_MP and, if neceesary, adjust the constraints on the other
5407 mp = xmalloc (sizeof (* mp));
5408 mp->fix_size = fix->fix_size;
5409 mp->mode = fix->mode;
5410 mp->value = fix->value;
5412 /* Not yet required for a backwards ref. */
5413 mp->min_address = -65536;
5417 mp->max_address = max_address;
5419 mp->prev = minipool_vector_tail;
5421 if (mp->prev == NULL)
5423 minipool_vector_head = mp;
5424 minipool_vector_label = gen_label_rtx ();
5427 mp->prev->next = mp;
5429 minipool_vector_tail = mp;
5433 if (max_address > max_mp->max_address - mp->fix_size)
5434 mp->max_address = max_mp->max_address - mp->fix_size;
5436 mp->max_address = max_address;
5439 mp->prev = max_mp->prev;
5441 if (mp->prev != NULL)
5442 mp->prev->next = mp;
5444 minipool_vector_head = mp;
5447 /* Save the new entry. */
5450 /* Scan over the preceeding entries and adjust their addresses as
5452 while (mp->prev != NULL
5453 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5455 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5463 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5466 HOST_WIDE_INT min_address;
5468 HOST_WIDE_INT offset;
5470 /* This should never be true, and the code below assumes these are
5477 if (min_address > mp->min_address)
5478 mp->min_address = min_address;
5482 /* We will adjust this below if it is too loose. */
5483 mp->min_address = min_address;
5485 /* Unlink MP from its current position. Since min_mp is non-null,
5486 mp->next must be non-null. */
5487 mp->next->prev = mp->prev;
5488 if (mp->prev != NULL)
5489 mp->prev->next = mp->next;
5491 minipool_vector_head = mp->next;
5493 /* Reinsert it after MIN_MP. */
5495 mp->next = min_mp->next;
5497 if (mp->next != NULL)
5498 mp->next->prev = mp;
5500 minipool_vector_tail = mp;
5506 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5508 mp->offset = offset;
5509 if (mp->refcount > 0)
5510 offset += mp->fix_size;
5512 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5513 mp->next->min_address = mp->min_address + mp->fix_size;
5519 /* Add a constant to the minipool for a backward reference. Returns the
5520 node added or NULL if the constant will not fit in this pool.
5522 Note that the code for insertion for a backwards reference can be
5523 somewhat confusing because the calculated offsets for each fix do
5524 not take into account the size of the pool (which is still under
5527 add_minipool_backward_ref (fix)
5530 /* If set, min_mp is the last pool_entry that has a lower constraint
5531 than the one we are trying to add. */
5532 Mnode * min_mp = NULL;
5533 /* This can be negative, since it is only a constraint. */
5534 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5537 /* If we can't reach the current pool from this insn, or if we can't
5538 insert this entry at the end of the pool without pushing other
5539 fixes out of range, then we don't try. This ensures that we
5540 can't fail later on. */
5541 if (min_address >= minipool_barrier->address
5542 || (minipool_vector_tail->min_address + fix->fix_size
5543 >= minipool_barrier->address))
5546 /* Scan the pool to see if a constant with the same value has
5547 already been added. While we are doing this, also note the
5548 location where we must insert the constant if it doesn't already
5550 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5552 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5553 && fix->mode == mp->mode
5554 && (GET_CODE (fix->value) != CODE_LABEL
5555 || (CODE_LABEL_NUMBER (fix->value)
5556 == CODE_LABEL_NUMBER (mp->value)))
5557 && rtx_equal_p (fix->value, mp->value)
5558 /* Check that there is enough slack to move this entry to the
5559 end of the table (this is conservative). */
5561 > (minipool_barrier->address
5562 + minipool_vector_tail->offset
5563 + minipool_vector_tail->fix_size)))
5566 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5570 mp->min_address += fix->fix_size;
5573 /* Note the insertion point if necessary. */
5574 if (mp->min_address < min_address)
5576 else if (mp->max_address
5577 < minipool_barrier->address + mp->offset + fix->fix_size)
5579 /* Inserting before this entry would push the fix beyond
5580 its maximum address (which can happen if we have
5581 re-located a forwards fix); force the new fix to come
5584 min_address = mp->min_address + fix->fix_size;
5589 /* We need to create a new entry. */
5590 mp = xmalloc (sizeof (* mp));
5591 mp->fix_size = fix->fix_size;
5592 mp->mode = fix->mode;
5593 mp->value = fix->value;
5595 mp->max_address = minipool_barrier->address + 65536;
5597 mp->min_address = min_address;
5602 mp->next = minipool_vector_head;
5604 if (mp->next == NULL)
5606 minipool_vector_tail = mp;
5607 minipool_vector_label = gen_label_rtx ();
5610 mp->next->prev = mp;
5612 minipool_vector_head = mp;
5616 mp->next = min_mp->next;
5620 if (mp->next != NULL)
5621 mp->next->prev = mp;
5623 minipool_vector_tail = mp;
5626 /* Save the new entry. */
5634 /* Scan over the following entries and adjust their offsets. */
5635 while (mp->next != NULL)
5637 if (mp->next->min_address < mp->min_address + mp->fix_size)
5638 mp->next->min_address = mp->min_address + mp->fix_size;
5641 mp->next->offset = mp->offset + mp->fix_size;
5643 mp->next->offset = mp->offset;
5652 assign_minipool_offsets (barrier)
5655 HOST_WIDE_INT offset = 0;
5658 minipool_barrier = barrier;
5660 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5662 mp->offset = offset;
5664 if (mp->refcount > 0)
5665 offset += mp->fix_size;
5669 /* Output the literal table */
5671 dump_minipool (scan)
5678 fprintf (rtl_dump_file,
5679 ";; Emitting minipool after insn %u; address %ld\n",
5680 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5682 scan = emit_label_after (gen_label_rtx (), scan);
5683 scan = emit_insn_after (gen_align_4 (), scan);
5684 scan = emit_label_after (minipool_vector_label, scan);
5686 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5688 if (mp->refcount > 0)
5692 fprintf (rtl_dump_file,
5693 ";; Offset %u, min %ld, max %ld ",
5694 (unsigned) mp->offset, (unsigned long) mp->min_address,
5695 (unsigned long) mp->max_address);
5696 arm_print_value (rtl_dump_file, mp->value);
5697 fputc ('\n', rtl_dump_file);
5700 switch (mp->fix_size)
5702 #ifdef HAVE_consttable_1
5704 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5708 #ifdef HAVE_consttable_2
5710 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5714 #ifdef HAVE_consttable_4
5716 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5720 #ifdef HAVE_consttable_8
5722 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5736 minipool_vector_head = minipool_vector_tail = NULL;
5737 scan = emit_insn_after (gen_consttable_end (), scan);
5738 scan = emit_barrier_after (scan);
5741 /* Return the cost of forcibly inserting a barrier after INSN. */
5743 arm_barrier_cost (insn)
5746 /* Basing the location of the pool on the loop depth is preferable,
5747 but at the moment, the basic block information seems to be
5748 corrupt by this stage of the compilation. */
5750 rtx next = next_nonnote_insn (insn);
5752 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5755 switch (GET_CODE (insn))
5758 /* It will always be better to place the table before the label, rather
5767 return base_cost - 10;
5770 return base_cost + 10;
5774 /* Find the best place in the insn stream in the range
5775 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5776 Create the barrier by inserting a jump and add a new fix entry for
5779 create_fix_barrier (fix, max_address)
5781 HOST_WIDE_INT max_address;
5783 HOST_WIDE_INT count = 0;
5785 rtx from = fix->insn;
5786 rtx selected = from;
5788 HOST_WIDE_INT selected_address;
5790 HOST_WIDE_INT max_count = max_address - fix->address;
5791 rtx label = gen_label_rtx ();
5793 selected_cost = arm_barrier_cost (from);
5794 selected_address = fix->address;
5796 while (from && count < max_count)
5801 /* This code shouldn't have been called if there was a natural barrier
5803 if (GET_CODE (from) == BARRIER)
5806 /* Count the length of this insn. */
5807 count += get_attr_length (from);
5809 /* If there is a jump table, add its length. */
5810 tmp = is_jump_table (from);
5813 count += get_jump_table_size (tmp);
5815 /* Jump tables aren't in a basic block, so base the cost on
5816 the dispatch insn. If we select this location, we will
5817 still put the pool after the table. */
5818 new_cost = arm_barrier_cost (from);
5820 if (count < max_count && new_cost <= selected_cost)
5823 selected_cost = new_cost;
5824 selected_address = fix->address + count;
5827 /* Continue after the dispatch table. */
5828 from = NEXT_INSN (tmp);
5832 new_cost = arm_barrier_cost (from);
5834 if (count < max_count && new_cost <= selected_cost)
5837 selected_cost = new_cost;
5838 selected_address = fix->address + count;
5841 from = NEXT_INSN (from);
5844 /* Create a new JUMP_INSN that branches around a barrier. */
5845 from = emit_jump_insn_after (gen_jump (label), selected);
5846 JUMP_LABEL (from) = label;
5847 barrier = emit_barrier_after (from);
5848 emit_label_after (label, barrier);
5850 /* Create a minipool barrier entry for the new barrier. */
5851 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
5852 new_fix->insn = barrier;
5853 new_fix->address = selected_address;
5854 new_fix->next = fix->next;
5855 fix->next = new_fix;
5860 /* Record that there is a natural barrier in the insn stream at
5863 push_minipool_barrier (insn, address)
5865 HOST_WIDE_INT address;
5867 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5870 fix->address = address;
5873 if (minipool_fix_head != NULL)
5874 minipool_fix_tail->next = fix;
5876 minipool_fix_head = fix;
5878 minipool_fix_tail = fix;
5881 /* Record INSN, which will need fixing up to load a value from the
5882 minipool. ADDRESS is the offset of the insn since the start of the
5883 function; LOC is a pointer to the part of the insn which requires
5884 fixing; VALUE is the constant that must be loaded, which is of type
5887 push_minipool_fix (insn, address, loc, mode, value)
5889 HOST_WIDE_INT address;
5891 enum machine_mode mode;
5894 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5896 #ifdef AOF_ASSEMBLER
5897 /* PIC symbol refereneces need to be converted into offsets into the
5899 /* XXX This shouldn't be done here. */
5900 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
5901 value = aof_pic_entry (value);
5902 #endif /* AOF_ASSEMBLER */
5905 fix->address = address;
5908 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
5910 fix->forwards = get_attr_pool_range (insn);
5911 fix->backwards = get_attr_neg_pool_range (insn);
5912 fix->minipool = NULL;
5914 /* If an insn doesn't have a range defined for it, then it isn't
5915 expecting to be reworked by this code. Better to abort now than
5916 to generate duff assembly code. */
5917 if (fix->forwards == 0 && fix->backwards == 0)
5922 fprintf (rtl_dump_file,
5923 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5924 GET_MODE_NAME (mode),
5925 INSN_UID (insn), (unsigned long) address,
5926 -1 * (long)fix->backwards, (long)fix->forwards);
5927 arm_print_value (rtl_dump_file, fix->value);
5928 fprintf (rtl_dump_file, "\n");
5931 /* Add it to the chain of fixes. */
5934 if (minipool_fix_head != NULL)
5935 minipool_fix_tail->next = fix;
5937 minipool_fix_head = fix;
5939 minipool_fix_tail = fix;
5942 /* Scan INSN and note any of its operands that need fixing. */
5944 note_invalid_constants (insn, address)
5946 HOST_WIDE_INT address;
5950 extract_insn (insn);
5952 if (!constrain_operands (1))
5953 fatal_insn_not_found (insn);
5955 /* Fill in recog_op_alt with information about the constraints of this
5957 preprocess_constraints ();
5959 for (opno = 0; opno < recog_data.n_operands; opno++)
5961 /* Things we need to fix can only occur in inputs. */
5962 if (recog_data.operand_type[opno] != OP_IN)
5965 /* If this alternative is a memory reference, then any mention
5966 of constants in this alternative is really to fool reload
5967 into allowing us to accept one there. We need to fix them up
5968 now so that we output the right code. */
5969 if (recog_op_alt[opno][which_alternative].memory_ok)
5971 rtx op = recog_data.operand[opno];
5973 if (CONSTANT_P (op))
5974 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5975 recog_data.operand_mode[opno], op);
5977 /* RWE: Now we look correctly at the operands for the insn,
5978 this shouldn't be needed any more. */
5979 #ifndef AOF_ASSEMBLER
5980 /* XXX Is this still needed? */
5981 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
5982 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5983 recog_data.operand_mode[opno],
5984 XVECEXP (op, 0, 0));
5987 else if (GET_CODE (op) == MEM
5988 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5989 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
5990 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5991 recog_data.operand_mode[opno],
5992 get_pool_constant (XEXP (op, 0)));
6002 HOST_WIDE_INT address = 0;
6005 minipool_fix_head = minipool_fix_tail = NULL;
6007 /* The first insn must always be a note, or the code below won't
6008 scan it properly. */
6009 if (GET_CODE (first) != NOTE)
6012 /* Scan all the insns and record the operands that will need fixing. */
6013 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
6015 if (GET_CODE (insn) == BARRIER)
6016 push_minipool_barrier (insn, address);
6017 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
6018 || GET_CODE (insn) == JUMP_INSN)
6022 note_invalid_constants (insn, address);
6023 address += get_attr_length (insn);
6025 /* If the insn is a vector jump, add the size of the table
6026 and skip the table. */
6027 if ((table = is_jump_table (insn)) != NULL)
6029 address += get_jump_table_size (table);
6035 fix = minipool_fix_head;
6037 /* Now scan the fixups and perform the required changes. */
6042 Mfix * last_added_fix;
6043 Mfix * last_barrier = NULL;
6046 /* Skip any further barriers before the next fix. */
6047 while (fix && GET_CODE (fix->insn) == BARRIER)
6050 /* No more fixes. */
6054 last_added_fix = NULL;
6056 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6058 if (GET_CODE (ftmp->insn) == BARRIER)
6060 if (ftmp->address >= minipool_vector_head->max_address)
6063 last_barrier = ftmp;
6065 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
6068 last_added_fix = ftmp; /* Keep track of the last fix added. */
6071 /* If we found a barrier, drop back to that; any fixes that we
6072 could have reached but come after the barrier will now go in
6073 the next mini-pool. */
6074 if (last_barrier != NULL)
6076 /* Reduce the refcount for those fixes that won't go into this
6078 for (fdel = last_barrier->next;
6079 fdel && fdel != ftmp;
6082 fdel->minipool->refcount--;
6083 fdel->minipool = NULL;
6086 ftmp = last_barrier;
6090 /* ftmp is first fix that we can't fit into this pool and
6091 there no natural barriers that we could use. Insert a
6092 new barrier in the code somewhere between the previous
6093 fix and this one, and arrange to jump around it. */
6094 HOST_WIDE_INT max_address;
6096 /* The last item on the list of fixes must be a barrier, so
6097 we can never run off the end of the list of fixes without
6098 last_barrier being set. */
6102 max_address = minipool_vector_head->max_address;
6103 /* Check that there isn't another fix that is in range that
6104 we couldn't fit into this pool because the pool was
6105 already too large: we need to put the pool before such an
6107 if (ftmp->address < max_address)
6108 max_address = ftmp->address;
6110 last_barrier = create_fix_barrier (last_added_fix, max_address);
6113 assign_minipool_offsets (last_barrier);
6117 if (GET_CODE (ftmp->insn) != BARRIER
6118 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
6125 /* Scan over the fixes we have identified for this pool, fixing them
6126 up and adding the constants to the pool itself. */
6127 for (this_fix = fix; this_fix && ftmp != this_fix;
6128 this_fix = this_fix->next)
6129 if (GET_CODE (this_fix->insn) != BARRIER)
6132 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
6133 minipool_vector_label),
6134 this_fix->minipool->offset);
6135 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
6138 dump_minipool (last_barrier->insn);
6142 /* From now on we must synthesize any constants that we can't handle
6143 directly. This can happen if the RTL gets split during final
6144 instruction generation. */
6145 after_arm_reorg = 1;
6147 /* Free the minipool memory. */
6148 obstack_free (&minipool_obstack, minipool_startobj);
6151 /* Routines to output assembly language. */
6153 /* If the rtx is the correct value then return the string of the number.
6154 In this way we can ensure that valid double constants are generated even
6155 when cross compiling. */
6157 fp_immediate_constant (x)
6163 if (!fpa_consts_inited)
6166 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6167 for (i = 0; i < 8; i++)
6168 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
6169 return strings_fpa[i];
6174 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6176 fp_const_from_val (r)
6177 REAL_VALUE_TYPE * r;
6181 if (!fpa_consts_inited)
6184 for (i = 0; i < 8; i++)
6185 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
6186 return strings_fpa[i];
6191 /* Output the operands of a LDM/STM instruction to STREAM.
6192 MASK is the ARM register set mask of which only bits 0-15 are important.
6193 REG is the base register, either the frame pointer or the stack pointer,
6194 INSTR is the possibly suffixed load or store instruction. */
6197 print_multi_reg (stream, instr, reg, mask)
6204 int not_first = FALSE;
6206 fputc ('\t', stream);
6207 asm_fprintf (stream, instr, reg);
6208 fputs (", {", stream);
6210 for (i = 0; i <= LAST_ARM_REGNUM; i++)
6211 if (mask & (1 << i))
6214 fprintf (stream, ", ");
6216 asm_fprintf (stream, "%r", i);
6220 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
6223 /* Output a 'call' insn. */
6226 output_call (operands)
6229 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6231 if (REGNO (operands[0]) == LR_REGNUM)
6233 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
6234 output_asm_insn ("mov%?\t%0, %|lr", operands);
6237 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6239 if (TARGET_INTERWORK)
6240 output_asm_insn ("bx%?\t%0", operands);
6242 output_asm_insn ("mov%?\t%|pc, %0", operands);
6251 int something_changed = 0;
6253 int code = GET_CODE (x0);
6255 register const char * fmt;
6260 if (REGNO (x0) == LR_REGNUM)
6262 *x = gen_rtx_REG (SImode, IP_REGNUM);
6267 /* Scan through the sub-elements and change any references there. */
6268 fmt = GET_RTX_FORMAT (code);
6270 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6272 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
6273 else if (fmt[i] == 'E')
6274 for (j = 0; j < XVECLEN (x0, i); j++)
6275 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
6277 return something_changed;
6281 /* Output a 'call' insn that is a reference in memory. */
6284 output_call_mem (operands)
6287 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
6288 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6289 if (eliminate_lr2ip (&operands[0]))
6290 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
6292 if (TARGET_INTERWORK)
6294 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6295 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6296 output_asm_insn ("bx%?\t%|ip", operands);
6300 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6301 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6308 /* Output a move from arm registers to an fpu registers.
6309 OPERANDS[0] is an fpu register.
6310 OPERANDS[1] is the first registers of an arm register pair. */
6313 output_mov_long_double_fpu_from_arm (operands)
6316 int arm_reg0 = REGNO (operands[1]);
6319 if (arm_reg0 == IP_REGNUM)
6322 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6323 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6324 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6326 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6327 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6332 /* Output a move from an fpu register to arm registers.
6333 OPERANDS[0] is the first registers of an arm register pair.
6334 OPERANDS[1] is an fpu register. */
6337 output_mov_long_double_arm_from_fpu (operands)
6340 int arm_reg0 = REGNO (operands[0]);
6343 if (arm_reg0 == IP_REGNUM)
6346 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6347 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6348 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6350 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6351 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6355 /* Output a move from arm registers to arm registers of a long double
6356 OPERANDS[0] is the destination.
6357 OPERANDS[1] is the source. */
6359 output_mov_long_double_arm_from_arm (operands)
6362 /* We have to be careful here because the two might overlap. */
6363 int dest_start = REGNO (operands[0]);
6364 int src_start = REGNO (operands[1]);
6368 if (dest_start < src_start)
6370 for (i = 0; i < 3; i++)
6372 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6373 ops[1] = gen_rtx_REG (SImode, src_start + i);
6374 output_asm_insn ("mov%?\t%0, %1", ops);
6379 for (i = 2; i >= 0; i--)
6381 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6382 ops[1] = gen_rtx_REG (SImode, src_start + i);
6383 output_asm_insn ("mov%?\t%0, %1", ops);
6391 /* Output a move from arm registers to an fpu registers.
6392 OPERANDS[0] is an fpu register.
6393 OPERANDS[1] is the first registers of an arm register pair. */
6396 output_mov_double_fpu_from_arm (operands)
6399 int arm_reg0 = REGNO (operands[1]);
6402 if (arm_reg0 == IP_REGNUM)
6405 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6406 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6407 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6408 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6412 /* Output a move from an fpu register to arm registers.
6413 OPERANDS[0] is the first registers of an arm register pair.
6414 OPERANDS[1] is an fpu register. */
6417 output_mov_double_arm_from_fpu (operands)
6420 int arm_reg0 = REGNO (operands[0]);
6423 if (arm_reg0 == IP_REGNUM)
6426 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6427 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6428 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6429 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6433 /* Output a move between double words.
6434 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6435 or MEM<-REG and all MEMs must be offsettable addresses. */
6438 output_move_double (operands)
6441 enum rtx_code code0 = GET_CODE (operands[0]);
6442 enum rtx_code code1 = GET_CODE (operands[1]);
6447 int reg0 = REGNO (operands[0]);
6449 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6453 int reg1 = REGNO (operands[1]);
6454 if (reg1 == IP_REGNUM)
6457 /* Ensure the second source is not overwritten. */
6458 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6459 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6461 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6463 else if (code1 == CONST_DOUBLE)
6465 if (GET_MODE (operands[1]) == DFmode)
6468 union real_extract u;
6470 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u));
6471 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
6472 otherops[1] = GEN_INT (l[1]);
6473 operands[1] = GEN_INT (l[0]);
6475 else if (GET_MODE (operands[1]) != VOIDmode)
6477 else if (WORDS_BIG_ENDIAN)
6480 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6481 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6486 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6487 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6490 output_mov_immediate (operands);
6491 output_mov_immediate (otherops);
6493 else if (code1 == CONST_INT)
6495 #if HOST_BITS_PER_WIDE_INT > 32
6496 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6497 what the upper word is. */
6498 if (WORDS_BIG_ENDIAN)
6500 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6501 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6505 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6506 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6509 /* Sign extend the intval into the high-order word. */
6510 if (WORDS_BIG_ENDIAN)
6512 otherops[1] = operands[1];
6513 operands[1] = (INTVAL (operands[1]) < 0
6514 ? constm1_rtx : const0_rtx);
6517 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6519 output_mov_immediate (otherops);
6520 output_mov_immediate (operands);
6522 else if (code1 == MEM)
6524 switch (GET_CODE (XEXP (operands[1], 0)))
6527 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6531 abort (); /* Should never happen now. */
6535 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6539 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6543 abort (); /* Should never happen now. */
6548 output_asm_insn ("adr%?\t%0, %1", operands);
6549 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6553 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6554 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6556 otherops[0] = operands[0];
6557 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6558 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6559 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6561 if (GET_CODE (otherops[2]) == CONST_INT)
6563 switch (INTVAL (otherops[2]))
6566 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6569 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6572 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6575 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6576 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6578 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6581 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6584 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6586 return "ldm%?ia\t%0, %M0";
6590 otherops[1] = adjust_address (operands[1], VOIDmode, 4);
6591 /* Take care of overlapping base/data reg. */
6592 if (reg_mentioned_p (operands[0], operands[1]))
6594 output_asm_insn ("ldr%?\t%0, %1", otherops);
6595 output_asm_insn ("ldr%?\t%0, %1", operands);
6599 output_asm_insn ("ldr%?\t%0, %1", operands);
6600 output_asm_insn ("ldr%?\t%0, %1", otherops);
6606 abort (); /* Constraints should prevent this. */
6608 else if (code0 == MEM && code1 == REG)
6610 if (REGNO (operands[1]) == IP_REGNUM)
6613 switch (GET_CODE (XEXP (operands[0], 0)))
6616 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6620 abort (); /* Should never happen now. */
6624 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6628 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6632 abort (); /* Should never happen now. */
6636 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6638 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6641 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6645 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6649 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6656 otherops[0] = adjust_address (operands[0], VOIDmode, 4);
6657 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6658 output_asm_insn ("str%?\t%1, %0", operands);
6659 output_asm_insn ("str%?\t%1, %0", otherops);
6663 abort (); /* Constraints should prevent this */
6669 /* Output an arbitrary MOV reg, #n.
6670 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6673 output_mov_immediate (operands)
6676 HOST_WIDE_INT n = INTVAL (operands[1]);
6680 /* Try to use one MOV */
6681 if (const_ok_for_arm (n))
6683 output_asm_insn ("mov%?\t%0, %1", operands);
6687 /* Try to use one MVN */
6688 if (const_ok_for_arm (~n))
6690 operands[1] = GEN_INT (~n);
6691 output_asm_insn ("mvn%?\t%0, %1", operands);
6695 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6697 for (i=0; i < 32; i++)
6701 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6702 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n);
6704 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6710 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6711 adding zero to one register, output nothing. */
6714 output_add_immediate (operands)
6717 HOST_WIDE_INT n = INTVAL (operands[2]);
6719 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6722 output_multi_immediate (operands,
6723 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6726 output_multi_immediate (operands,
6727 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6734 /* Output a multiple immediate operation.
6735 OPERANDS is the vector of operands referred to in the output patterns.
6736 INSTR1 is the output pattern to use for the first constant.
6737 INSTR2 is the output pattern to use for subsequent constants.
6738 IMMED_OP is the index of the constant slot in OPERANDS.
6739 N is the constant value. */
6742 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6744 const char * instr1;
6745 const char * instr2;
6749 #if HOST_BITS_PER_WIDE_INT > 32
6750 n &= HOST_UINT (0xffffffff);
6755 operands[immed_op] = const0_rtx;
6756 output_asm_insn (instr1, operands); /* Quick and easy output. */
6761 const char * instr = instr1;
6763 /* Note that n is never zero here (which would give no output). */
6764 for (i = 0; i < 32; i += 2)
6768 operands[immed_op] = GEN_INT (n & (255 << i));
6769 output_asm_insn (instr, operands);
6780 /* Return the appropriate ARM instruction for the operation code.
6781 The returned result should not be overwritten. OP is the rtx of the
6782 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6786 arithmetic_instr (op, shift_first_arg)
6788 int shift_first_arg;
6790 switch (GET_CODE (op))
6796 return shift_first_arg ? "rsb" : "sub";
6813 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6814 for the operation code. The returned result should not be overwritten.
6815 OP is the rtx code of the shift.
6816 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6820 shift_op (op, amountp)
6822 HOST_WIDE_INT *amountp;
6825 enum rtx_code code = GET_CODE (op);
6827 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6829 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6830 *amountp = INTVAL (XEXP (op, 1));
6853 /* We never have to worry about the amount being other than a
6854 power of 2, since this case can never be reloaded from a reg. */
6856 *amountp = int_log2 (*amountp);
6867 /* This is not 100% correct, but follows from the desire to merge
6868 multiplication by a power of 2 with the recognizer for a
6869 shift. >=32 is not a valid shift for "asl", so we must try and
6870 output a shift that produces the correct arithmetical result.
6871 Using lsr #32 is identical except for the fact that the carry bit
6872 is not set correctly if we set the flags; but we never use the
6873 carry bit from such an operation, so we can ignore that. */
6874 if (code == ROTATERT)
6875 *amountp &= 31; /* Rotate is just modulo 32 */
6876 else if (*amountp != (*amountp & 31))
6883 /* Shifts of 0 are no-ops. */
6892 /* Obtain the shift from the POWER of two. */
6893 static HOST_WIDE_INT
6895 HOST_WIDE_INT power;
6897 HOST_WIDE_INT shift = 0;
6899 while ((((HOST_INT (1)) << shift) & power) == 0)
6909 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6910 /bin/as is horribly restrictive. */
6911 #define MAX_ASCII_LEN 51
6914 output_ascii_pseudo_op (stream, p, len)
6916 const unsigned char * p;
6922 fputs ("\t.ascii\t\"", stream);
6924 for (i = 0; i < len; i++)
6926 register int c = p[i];
6928 if (len_so_far >= MAX_ASCII_LEN)
6930 fputs ("\"\n\t.ascii\t\"", stream);
6937 fputs ("\\t", stream);
6942 fputs ("\\f", stream);
6947 fputs ("\\b", stream);
6952 fputs ("\\r", stream);
6956 case TARGET_NEWLINE:
6957 fputs ("\\n", stream);
6959 if ((c >= ' ' && c <= '~')
6961 /* This is a good place for a line break. */
6962 len_so_far = MAX_ASCII_LEN;
6969 putc ('\\', stream);
6974 if (c >= ' ' && c <= '~')
6981 fprintf (stream, "\\%03o", c);
6988 fputs ("\"\n", stream);
6991 /* Compute a bit mask of which registers need to be
6992 saved on the stack for the current function. */
6994 static unsigned long
6995 arm_compute_save_reg_mask ()
6997 unsigned int save_reg_mask = 0;
6999 unsigned long func_type = arm_current_func_type ();
7001 if (IS_NAKED (func_type))
7002 /* This should never really happen. */
7005 /* If we are creating a stack frame, then we must save the frame pointer,
7006 IP (which will hold the old stack pointer), LR and the PC. */
7007 if (frame_pointer_needed)
7009 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
7014 /* Volatile functions do not return, so there
7015 is no need to save any other registers. */
7016 if (IS_VOLATILE (func_type))
7017 return save_reg_mask;
7019 if (IS_INTERRUPT (func_type))
7021 unsigned int max_reg;
7023 /* Interrupt functions must not corrupt any registers,
7024 even call clobbered ones. If this is a leaf function
7025 we can just examine the registers used by the RTL, but
7026 otherwise we have to assume that whatever function is
7027 called might clobber anything, and so we have to save
7028 all the call-clobbered registers as well. */
7029 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7030 /* FIQ handlers have registers r8 - r12 banked, so
7031 we only need to check r0 - r7, Normal ISRs only
7032 bank r14 and r15, so ew must check up to r12.
7033 r13 is the stack pointer which is always preserved,
7034 so we do not need to consider it here. */
7039 for (reg = 0; reg <= max_reg; reg++)
7040 if (regs_ever_live[reg]
7041 || (! current_function_is_leaf && call_used_regs [reg]))
7042 save_reg_mask |= (1 << reg);
7046 /* In the normal case we only need to save those registers
7047 which are call saved and which are used by this function. */
7048 for (reg = 0; reg <= 10; reg++)
7049 if (regs_ever_live[reg] && ! call_used_regs [reg])
7050 save_reg_mask |= (1 << reg);
7052 /* Handle the frame pointer as a special case. */
7053 if (! TARGET_APCS_FRAME
7054 && ! frame_pointer_needed
7055 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7056 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7057 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7059 /* If we aren't loading the PIC register,
7060 don't stack it even though it may be live. */
7062 && ! TARGET_SINGLE_PIC_BASE
7063 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7064 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7067 /* Decide if we need to save the link register.
7068 Interrupt routines have their own banked link register,
7069 so they never need to save it.
7070 Otheriwse if we do not use the link register we do not need to save
7071 it. If we are pushing other registers onto the stack however, we
7072 can save an instruction in the epilogue by pushing the link register
7073 now and then popping it back into the PC. This incurs extra memory
7074 accesses though, so we only do it when optimising for size, and only
7075 if we know that we will not need a fancy return sequence. */
7076 if (! IS_INTERRUPT (func_type)
7077 && (regs_ever_live [LR_REGNUM]
7080 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)))
7081 save_reg_mask |= 1 << LR_REGNUM;
7083 if (cfun->machine->lr_save_eliminated)
7084 save_reg_mask &= ~ (1 << LR_REGNUM);
7086 return save_reg_mask;
7089 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7090 everything bar the final return instruction. */
7093 output_return_instruction (operand, really_return, reverse)
7098 char conditional[10];
7101 unsigned long live_regs_mask;
7102 unsigned long func_type;
7104 func_type = arm_current_func_type ();
7106 if (IS_NAKED (func_type))
7109 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7111 /* If this function was declared non-returning, and we have found a tail
7112 call, then we have to trust that the called function won't return. */
7117 /* Otherwise, trap an attempted return by aborting. */
7119 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
7121 assemble_external_libcall (ops[1]);
7122 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
7128 if (current_function_calls_alloca && !really_return)
7131 /* Construct the conditional part of the instruction(s) to be emitted. */
7132 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
7134 return_used_this_function = 1;
7136 live_regs_mask = arm_compute_save_reg_mask ();
7138 /* On some ARM architectures it is faster to use LDR rather than LDM to
7139 load a single register. On other architectures, the cost is the same.
7140 In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */
7141 if ((live_regs_mask == (1 << LR_REGNUM))
7142 && ! TARGET_INTERWORK
7143 && ! IS_INTERRUPT (func_type)
7144 && (! really_return || TARGET_APCS_32))
7146 if (! really_return)
7147 sprintf (instr, "ldr%s\t%%|lr, [%%|sp], #4", conditional);
7149 sprintf (instr, "ldr%s\t%%|pc, [%%|sp], #4", conditional);
7151 else if (live_regs_mask)
7153 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
7154 /* There are two possible reasons for the IP register being saved.
7155 Either a stack frame was created, in which case IP contains the
7156 old stack pointer, or an ISR routine corrupted it. If this in an
7157 ISR routine then just restore IP, otherwise restore IP into SP. */
7158 if (! IS_INTERRUPT (func_type))
7160 live_regs_mask &= ~ (1 << IP_REGNUM);
7161 live_regs_mask |= (1 << SP_REGNUM);
7164 /* Generate the load multiple instruction to restore the registers. */
7165 if (frame_pointer_needed)
7166 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
7168 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
7170 for (reg = 0; reg <= SP_REGNUM; reg++)
7171 if (live_regs_mask & (1 << reg))
7173 strcat (instr, "%|");
7174 strcat (instr, reg_names[reg]);
7175 strcat (instr, ", ");
7178 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7180 /* If we are not restoring the LR register then we will
7181 have added one too many commas to the list above.
7182 Replace it with a closing brace. */
7183 instr [strlen (instr) - 2] = '}';
7187 strcat (instr, "%|");
7189 /* At this point there should only be one or two registers left in
7190 live_regs_mask: always LR, and possibly PC if we created a stack
7191 frame. LR contains the return address. If we do not have any
7192 special requirements for function exit (eg interworking, or ISR)
7193 then we can load this value directly into the PC and save an
7195 if (! TARGET_INTERWORK
7196 && ! IS_INTERRUPT (func_type)
7198 strcat (instr, reg_names [PC_REGNUM]);
7200 strcat (instr, reg_names [LR_REGNUM]);
7202 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
7207 /* See if we need to generate an extra instruction to
7208 perform the actual function return. */
7209 switch ((int) ARM_FUNC_TYPE (func_type))
7213 output_asm_insn (instr, & operand);
7215 strcpy (instr, "sub");
7216 strcat (instr, conditional);
7217 strcat (instr, "s\t%|pc, %|lr, #4");
7220 case ARM_FT_EXCEPTION:
7221 output_asm_insn (instr, & operand);
7223 strcpy (instr, "mov");
7224 strcat (instr, conditional);
7225 strcat (instr, "s\t%|pc, %|lr");
7228 case ARM_FT_INTERWORKED:
7229 output_asm_insn (instr, & operand);
7231 strcpy (instr, "bx");
7232 strcat (instr, conditional);
7233 strcat (instr, "\t%|lr");
7237 /* The return has already been handled
7238 by loading the LR into the PC. */
7239 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7241 output_asm_insn (instr, & operand);
7243 strcpy (instr, "mov");
7244 strcat (instr, conditional);
7245 if (! TARGET_APCS_32)
7246 strcat (instr, "s");
7247 strcat (instr, "\t%|pc, %|lr");
7253 else if (really_return)
7255 switch ((int) ARM_FUNC_TYPE (func_type))
7259 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
7262 case ARM_FT_INTERWORKED:
7263 sprintf (instr, "bx%s\t%%|lr", conditional);
7266 case ARM_FT_EXCEPTION:
7267 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
7271 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
7272 conditional, TARGET_APCS_32 ? "" : "s");
7277 /* Nothing to load off the stack, and
7278 no return instruction to generate. */
7281 output_asm_insn (instr, & operand);
7286 /* Write the function name into the code section, directly preceding
7287 the function prologue.
7289 Code will be output similar to this:
7291 .ascii "arm_poke_function_name", 0
7294 .word 0xff000000 + (t1 - t0)
7295 arm_poke_function_name
7297 stmfd sp!, {fp, ip, lr, pc}
7300 When performing a stack backtrace, code can inspect the value
7301 of 'pc' stored at 'fp' + 0. If the trace function then looks
7302 at location pc - 12 and the top 8 bits are set, then we know
7303 that there is a function name embedded immediately preceding this
7304 location and has length ((pc[-3]) & 0xff000000).
7306 We assume that pc is declared as a pointer to an unsigned long.
7308 It is of no benefit to output the function name if we are assembling
7309 a leaf function. These function types will not contain a stack
7310 backtrace structure, therefore it is not possible to determine the
7314 arm_poke_function_name (stream, name)
7318 unsigned long alignlength;
7319 unsigned long length;
7322 length = strlen (name) + 1;
7323 alignlength = ROUND_UP (length);
7325 ASM_OUTPUT_ASCII (stream, name, length);
7326 ASM_OUTPUT_ALIGN (stream, 2);
7327 x = GEN_INT (HOST_UINT(0xff000000) + alignlength);
7328 ASM_OUTPUT_INT (stream, x);
7331 /* Place some comments into the assembler stream
7332 describing the current function. */
7335 arm_output_function_prologue (f, frame_size)
7337 HOST_WIDE_INT frame_size;
7339 unsigned long func_type;
7343 thumb_output_function_prologue (f, frame_size);
7348 if (arm_ccfsm_state || arm_target_insn)
7351 func_type = arm_current_func_type ();
7353 switch ((int) ARM_FUNC_TYPE (func_type))
7358 case ARM_FT_INTERWORKED:
7359 asm_fprintf (f, "\t%@ Function supports interworking.\n");
7361 case ARM_FT_EXCEPTION_HANDLER:
7362 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
7365 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
7368 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
7370 case ARM_FT_EXCEPTION:
7371 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
7375 if (IS_NAKED (func_type))
7376 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7378 if (IS_VOLATILE (func_type))
7379 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
7381 if (IS_NESTED (func_type))
7382 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
7384 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
7385 current_function_args_size,
7386 current_function_pretend_args_size, frame_size);
7388 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
7389 frame_pointer_needed,
7390 current_function_anonymous_args);
7392 if (cfun->machine->lr_save_eliminated)
7393 asm_fprintf (f, "\t%@ link register save eliminated.\n");
7395 #ifdef AOF_ASSEMBLER
7397 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
7400 return_used_this_function = 0;
7404 arm_output_epilogue (really_return)
7408 unsigned long saved_regs_mask;
7409 unsigned long func_type;
7410 /* If we need this, then it will always be at least this much. */
7411 int floats_offset = 12;
7413 int frame_size = get_frame_size ();
7414 FILE * f = asm_out_file;
7415 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
7417 /* If we have already generated the return instruction
7418 then it is futile to generate anything else. */
7419 if (use_return_insn (FALSE) && return_used_this_function)
7422 func_type = arm_current_func_type ();
7424 if (IS_NAKED (func_type))
7425 /* Naked functions don't have epilogues. */
7428 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7432 /* A volatile function should never return. Call abort. */
7433 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7434 assemble_external_libcall (op);
7435 output_asm_insn ("bl\t%a0", &op);
7440 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
7442 /* If we are throwing an exception, then we really must
7443 be doing a return, so we can't tail-call. */
7446 saved_regs_mask = arm_compute_save_reg_mask ();
7448 /* Compute how far away the floats will be. */
7449 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
7450 if (saved_regs_mask & (1 << reg))
7453 if (frame_pointer_needed)
7455 if (arm_fpu_arch == FP_SOFT2)
7457 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7458 if (regs_ever_live[reg] && !call_used_regs[reg])
7460 floats_offset += 12;
7461 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7462 reg, FP_REGNUM, floats_offset);
7467 int start_reg = LAST_ARM_FP_REGNUM;
7469 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7471 if (regs_ever_live[reg] && !call_used_regs[reg])
7473 floats_offset += 12;
7475 /* We can't unstack more than four registers at once. */
7476 if (start_reg - reg == 3)
7478 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7479 reg, FP_REGNUM, floats_offset);
7480 start_reg = reg - 1;
7485 if (reg != start_reg)
7486 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7487 reg + 1, start_reg - reg,
7488 FP_REGNUM, floats_offset);
7489 start_reg = reg - 1;
7493 /* Just in case the last register checked also needs unstacking. */
7494 if (reg != start_reg)
7495 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7496 reg + 1, start_reg - reg,
7497 FP_REGNUM, floats_offset);
7500 /* saved_regs_mask should contain the IP, which at the time of stack
7501 frame generation actually contains the old stack pointer. So a
7502 quick way to unwind the stack is just pop the IP register directly
7503 into the stack pointer. */
7504 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
7506 saved_regs_mask &= ~ (1 << IP_REGNUM);
7507 saved_regs_mask |= (1 << SP_REGNUM);
7509 /* There are two registers left in saved_regs_mask - LR and PC. We
7510 only need to restore the LR register (the return address), but to
7511 save time we can load it directly into the PC, unless we need a
7512 special function exit sequence, or we are not really returning. */
7513 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
7514 /* Delete the LR from the register mask, so that the LR on
7515 the stack is loaded into the PC in the register mask. */
7516 saved_regs_mask &= ~ (1 << LR_REGNUM);
7518 saved_regs_mask &= ~ (1 << PC_REGNUM);
7520 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
7522 if (IS_INTERRUPT (func_type))
7523 /* Interrupt handlers will have pushed the
7524 IP onto the stack, so restore it now. */
7525 print_multi_reg (f, "ldmea\t%r", SP_REGNUM, 1 << IP_REGNUM);
7529 /* Restore stack pointer if necessary. */
7530 if (frame_size + current_function_outgoing_args_size != 0)
7532 operands[0] = operands[1] = stack_pointer_rtx;
7533 operands[2] = GEN_INT (frame_size
7534 + current_function_outgoing_args_size);
7535 output_add_immediate (operands);
7538 if (arm_fpu_arch == FP_SOFT2)
7540 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7541 if (regs_ever_live[reg] && !call_used_regs[reg])
7542 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7547 int start_reg = FIRST_ARM_FP_REGNUM;
7549 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7551 if (regs_ever_live[reg] && !call_used_regs[reg])
7553 if (reg - start_reg == 3)
7555 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7556 start_reg, SP_REGNUM);
7557 start_reg = reg + 1;
7562 if (reg != start_reg)
7563 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7564 start_reg, reg - start_reg,
7567 start_reg = reg + 1;
7571 /* Just in case the last register checked also needs unstacking. */
7572 if (reg != start_reg)
7573 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7574 start_reg, reg - start_reg, SP_REGNUM);
7577 /* If we can, restore the LR into the PC. */
7578 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7580 && current_function_pretend_args_size == 0
7581 && saved_regs_mask & (1 << LR_REGNUM))
7583 saved_regs_mask &= ~ (1 << LR_REGNUM);
7584 saved_regs_mask |= (1 << PC_REGNUM);
7587 /* Load the registers off the stack. If we only have one register
7588 to load use the LDR instruction - it is faster. */
7589 if (saved_regs_mask == (1 << LR_REGNUM))
7591 /* The excpetion handler ignores the LR, so we do
7592 not really need to load it off the stack. */
7594 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7596 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7598 else if (saved_regs_mask)
7599 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
7601 if (current_function_pretend_args_size)
7603 /* Unwind the pre-pushed regs. */
7604 operands[0] = operands[1] = stack_pointer_rtx;
7605 operands[2] = GEN_INT (current_function_pretend_args_size);
7606 output_add_immediate (operands);
7611 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
7612 /* Adjust the stack to remove the exception handler stuff. */
7613 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7617 if (! really_return)
7620 /* Generate the return instruction. */
7621 switch ((int) ARM_FUNC_TYPE (func_type))
7623 case ARM_FT_EXCEPTION_HANDLER:
7624 /* Even in 26-bit mode we do a mov (rather than a movs)
7625 because we don't have the PSR bits set in the address. */
7626 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
7631 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
7634 case ARM_FT_EXCEPTION:
7635 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7638 case ARM_FT_INTERWORKED:
7639 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
7643 if (frame_pointer_needed)
7644 /* If we used the frame pointer then the return adddress
7645 will have been loaded off the stack directly into the
7646 PC, so there is no need to issue a MOV instruction
7649 else if (current_function_pretend_args_size == 0
7650 && (saved_regs_mask & (1 << LR_REGNUM)))
7651 /* Similarly we may have been able to load LR into the PC
7652 even if we did not create a stack frame. */
7654 else if (TARGET_APCS_32)
7655 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7657 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7665 arm_output_function_epilogue (file, frame_size)
7666 FILE *file ATTRIBUTE_UNUSED;
7667 HOST_WIDE_INT frame_size;
7671 /* ??? Probably not safe to set this here, since it assumes that a
7672 function will be emitted as assembly immediately after we generate
7673 RTL for it. This does not happen for inline functions. */
7674 return_used_this_function = 0;
7678 if (use_return_insn (FALSE)
7679 && return_used_this_function
7680 && (frame_size + current_function_outgoing_args_size) != 0
7681 && !frame_pointer_needed)
7684 /* Reset the ARM-specific per-function variables. */
7685 current_function_anonymous_args = 0;
7686 after_arm_reorg = 0;
7690 /* Generate and emit an insn that we will recognize as a push_multi.
7691 Unfortunately, since this insn does not reflect very well the actual
7692 semantics of the operation, we need to annotate the insn for the benefit
7693 of DWARF2 frame unwind information. */
7696 emit_multi_reg_push (mask)
7704 int dwarf_par_index;
7707 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7708 if (mask & (1 << i))
7711 if (num_regs == 0 || num_regs > 16)
7714 /* We don't record the PC in the dwarf frame information. */
7715 num_dwarf_regs = num_regs;
7716 if (mask & (1 << PC_REGNUM))
7719 /* For the body of the insn we are going to generate an UNSPEC in
7720 parallel with several USEs. This allows the insn to be recognised
7721 by the push_multi pattern in the arm.md file. The insn looks
7722 something like this:
7725 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7726 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7727 (use (reg:SI 11 fp))
7728 (use (reg:SI 12 ip))
7729 (use (reg:SI 14 lr))
7730 (use (reg:SI 15 pc))
7733 For the frame note however, we try to be more explicit and actually
7734 show each register being stored into the stack frame, plus a (single)
7735 decrement of the stack pointer. We do it this way in order to be
7736 friendly to the stack unwinding code, which only wants to see a single
7737 stack decrement per instruction. The RTL we generate for the note looks
7738 something like this:
7741 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7742 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7743 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7744 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7745 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7748 This sequence is used both by the code to support stack unwinding for
7749 exceptions handlers and the code to generate dwarf2 frame debugging. */
7751 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7752 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
7753 RTX_FRAME_RELATED_P (dwarf) = 1;
7754 dwarf_par_index = 1;
7756 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7758 if (mask & (1 << i))
7760 reg = gen_rtx_REG (SImode, i);
7763 = gen_rtx_SET (VOIDmode,
7764 gen_rtx_MEM (BLKmode,
7765 gen_rtx_PRE_DEC (BLKmode,
7766 stack_pointer_rtx)),
7767 gen_rtx_UNSPEC (BLKmode,
7773 tmp = gen_rtx_SET (VOIDmode,
7774 gen_rtx_MEM (SImode, stack_pointer_rtx),
7776 RTX_FRAME_RELATED_P (tmp) = 1;
7777 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7785 for (j = 1, i++; j < num_regs; i++)
7787 if (mask & (1 << i))
7789 reg = gen_rtx_REG (SImode, i);
7791 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7795 tmp = gen_rtx_SET (VOIDmode,
7796 gen_rtx_MEM (SImode,
7797 plus_constant (stack_pointer_rtx,
7800 RTX_FRAME_RELATED_P (tmp) = 1;
7801 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
7808 par = emit_insn (par);
7810 tmp = gen_rtx_SET (SImode,
7812 gen_rtx_PLUS (SImode,
7814 GEN_INT (-4 * num_regs)));
7815 RTX_FRAME_RELATED_P (tmp) = 1;
7816 XVECEXP (dwarf, 0, 0) = tmp;
7818 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7824 emit_sfm (base_reg, count)
7833 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7834 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7835 RTX_FRAME_RELATED_P (dwarf) = 1;
7837 reg = gen_rtx_REG (XFmode, base_reg++);
7840 = gen_rtx_SET (VOIDmode,
7841 gen_rtx_MEM (BLKmode,
7842 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7843 gen_rtx_UNSPEC (BLKmode,
7847 = gen_rtx_SET (VOIDmode,
7848 gen_rtx_MEM (XFmode,
7849 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7851 RTX_FRAME_RELATED_P (tmp) = 1;
7852 XVECEXP (dwarf, 0, count - 1) = tmp;
7854 for (i = 1; i < count; i++)
7856 reg = gen_rtx_REG (XFmode, base_reg++);
7857 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7859 tmp = gen_rtx_SET (VOIDmode,
7860 gen_rtx_MEM (XFmode,
7861 gen_rtx_PRE_DEC (BLKmode,
7862 stack_pointer_rtx)),
7864 RTX_FRAME_RELATED_P (tmp) = 1;
7865 XVECEXP (dwarf, 0, count - i - 1) = tmp;
7868 par = emit_insn (par);
7869 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7874 /* Generate the prologue instructions for entry into an ARM function. */
7877 arm_expand_prologue ()
7883 unsigned long live_regs_mask;
7884 unsigned long func_type;
7887 func_type = arm_current_func_type ();
7889 /* Naked functions don't have prologues. */
7890 if (IS_NAKED (func_type))
7893 /* Compute which register we will have to save onto the stack. */
7894 live_regs_mask = arm_compute_save_reg_mask ();
7896 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
7898 if (frame_pointer_needed)
7900 if (IS_INTERRUPT (func_type))
7902 /* Interrupt functions must not corrupt any registers.
7903 Creating a frame pointer however, corrupts the IP
7904 register, so we must push it first. */
7905 insn = emit_multi_reg_push (1 << IP_REGNUM);
7906 RTX_FRAME_RELATED_P (insn) = 1;
7908 else if (IS_NESTED (func_type))
7910 /* The Static chain register is the same as the IP register
7911 used as a scratch register during stack frame creation.
7912 To get around this need to find somewhere to store IP
7913 whilst the frame is being created. We try the following
7916 1. The last argument register.
7917 2. A slot on the stack above the frame. (This only
7918 works if the function is not a varargs function).
7920 If neither of these places is available, we abort (for now).
7922 Note - we only need to tell the dwarf2 backend about the SP
7923 adjustment in the second variant; the static chain register
7924 doesn't need to be unwound, as it doesn't contain a value
7925 inherited from the caller. */
7927 if (regs_ever_live[3] == 0)
7929 insn = gen_rtx_REG (SImode, 3);
7930 insn = gen_rtx_SET (SImode, insn, ip_rtx);
7931 insn = emit_insn (insn);
7933 else if (current_function_pretend_args_size == 0)
7936 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
7937 insn = gen_rtx_MEM (SImode, insn);
7938 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
7939 insn = emit_insn (insn);
7943 /* Just tell the dwarf backend that we adjusted SP. */
7944 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7945 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7946 GEN_INT (-fp_offset)));
7947 RTX_FRAME_RELATED_P (insn) = 1;
7948 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7949 dwarf, REG_NOTES (insn));
7952 /* FIXME - the way to handle this situation is to allow
7953 the pretend args to be dumped onto the stack, then
7954 reuse r3 to save IP. This would involve moving the
7955 copying of SP into IP until after the pretend args
7956 have been dumped, but this is not too hard. */
7957 /* [See e.g. gcc.c-torture/execute/nest-stdar-1.c.] */
7958 error ("Unable to find a temporary location for static chain register");
7963 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
7964 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7967 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
7969 insn = emit_insn (insn);
7970 RTX_FRAME_RELATED_P (insn) = 1;
7973 if (current_function_pretend_args_size)
7975 /* Push the argument registers, or reserve space for them. */
7976 if (current_function_anonymous_args)
7977 insn = emit_multi_reg_push
7978 ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
7981 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7982 GEN_INT (-current_function_pretend_args_size)));
7983 RTX_FRAME_RELATED_P (insn) = 1;
7988 insn = emit_multi_reg_push (live_regs_mask);
7989 RTX_FRAME_RELATED_P (insn) = 1;
7992 if (! IS_VOLATILE (func_type))
7994 /* Save any floating point call-saved registers used by this function. */
7995 if (arm_fpu_arch == FP_SOFT2)
7997 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7998 if (regs_ever_live[reg] && !call_used_regs[reg])
8000 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
8001 insn = gen_rtx_MEM (XFmode, insn);
8002 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
8003 gen_rtx_REG (XFmode, reg)));
8004 RTX_FRAME_RELATED_P (insn) = 1;
8009 int start_reg = LAST_ARM_FP_REGNUM;
8011 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
8013 if (regs_ever_live[reg] && !call_used_regs[reg])
8015 if (start_reg - reg == 3)
8017 insn = emit_sfm (reg, 4);
8018 RTX_FRAME_RELATED_P (insn) = 1;
8019 start_reg = reg - 1;
8024 if (start_reg != reg)
8026 insn = emit_sfm (reg + 1, start_reg - reg);
8027 RTX_FRAME_RELATED_P (insn) = 1;
8029 start_reg = reg - 1;
8033 if (start_reg != reg)
8035 insn = emit_sfm (reg + 1, start_reg - reg);
8036 RTX_FRAME_RELATED_P (insn) = 1;
8041 if (frame_pointer_needed)
8043 /* Create the new frame pointer. */
8044 insn = GEN_INT (-(4 + current_function_pretend_args_size + fp_offset));
8045 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
8046 RTX_FRAME_RELATED_P (insn) = 1;
8048 if (IS_NESTED (func_type))
8050 /* Recover the static chain register. */
8051 if (regs_ever_live [3] == 0)
8053 insn = gen_rtx_REG (SImode, 3);
8054 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8055 insn = emit_insn (insn);
8057 else /* if (current_function_pretend_args_size == 0) */
8059 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
8060 insn = gen_rtx_MEM (SImode, insn);
8061 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8062 insn = emit_insn (insn);
8067 amount = GEN_INT (-(get_frame_size ()
8068 + current_function_outgoing_args_size));
8070 if (amount != const0_rtx)
8072 /* This add can produce multiple insns for a large constant, so we
8073 need to get tricky. */
8074 rtx last = get_last_insn ();
8075 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8079 last = last ? NEXT_INSN (last) : get_insns ();
8080 RTX_FRAME_RELATED_P (last) = 1;
8082 while (last != insn);
8084 /* If the frame pointer is needed, emit a special barrier that
8085 will prevent the scheduler from moving stores to the frame
8086 before the stack adjustment. */
8087 if (frame_pointer_needed)
8089 rtx unspec = gen_rtx_UNSPEC (SImode,
8090 gen_rtvec (2, stack_pointer_rtx,
8091 hard_frame_pointer_rtx),
8094 insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
8095 gen_rtx_MEM (BLKmode, unspec)));
8099 /* If we are profiling, make sure no instructions are scheduled before
8100 the call to mcount. Similarly if the user has requested no
8101 scheduling in the prolog. */
8102 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
8103 emit_insn (gen_blockage ());
8105 /* If the link register is being kept alive, with the return address in it,
8106 then make sure that it does not get reused by the ce2 pass. */
8107 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
8109 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
8110 cfun->machine->lr_save_eliminated = 1;
8114 /* If CODE is 'd', then the X is a condition operand and the instruction
8115 should only be executed if the condition is true.
8116 if CODE is 'D', then the X is a condition operand and the instruction
8117 should only be executed if the condition is false: however, if the mode
8118 of the comparison is CCFPEmode, then always execute the instruction -- we
8119 do this because in these circumstances !GE does not necessarily imply LT;
8120 in these cases the instruction pattern will take care to make sure that
8121 an instruction containing %d will follow, thereby undoing the effects of
8122 doing this instruction unconditionally.
8123 If CODE is 'N' then X is a floating point operand that must be negated
8125 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8126 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8129 arm_print_operand (stream, x, code)
8137 fputs (ASM_COMMENT_START, stream);
8141 fputs (user_label_prefix, stream);
8145 fputs (REGISTER_PREFIX, stream);
8149 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
8151 if (TARGET_THUMB || current_insn_predicate != NULL)
8154 fputs (arm_condition_codes[arm_current_cc], stream);
8156 else if (current_insn_predicate)
8158 enum arm_cond_code code;
8163 code = get_arm_condition_code (current_insn_predicate);
8164 fputs (arm_condition_codes[code], stream);
8171 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8172 r = REAL_VALUE_NEGATE (r);
8173 fprintf (stream, "%s", fp_const_from_val (&r));
8178 if (GET_CODE (x) == CONST_INT)
8181 val = ARM_SIGN_EXTEND (~INTVAL (x));
8182 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8187 output_addr_const (stream, x);
8192 fprintf (stream, "%s", arithmetic_instr (x, 1));
8196 fprintf (stream, "%s", arithmetic_instr (x, 0));
8202 const char * shift = shift_op (x, &val);
8206 fprintf (stream, ", %s ", shift_op (x, &val));
8208 arm_print_operand (stream, XEXP (x, 1), 0);
8211 fputc ('#', stream);
8212 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8218 /* An explanation of the 'Q', 'R' and 'H' register operands:
8220 In a pair of registers containing a DI or DF value the 'Q'
8221 operand returns the register number of the register containing
8222 the least signficant part of the value. The 'R' operand returns
8223 the register number of the register containing the most
8224 significant part of the value.
8226 The 'H' operand returns the higher of the two register numbers.
8227 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8228 same as the 'Q' operand, since the most signficant part of the
8229 value is held in the lower number register. The reverse is true
8230 on systems where WORDS_BIG_ENDIAN is false.
8232 The purpose of these operands is to distinguish between cases
8233 where the endian-ness of the values is important (for example
8234 when they are added together), and cases where the endian-ness
8235 is irrelevant, but the order of register operations is important.
8236 For example when loading a value from memory into a register
8237 pair, the endian-ness does not matter. Provided that the value
8238 from the lower memory address is put into the lower numbered
8239 register, and the value from the higher address is put into the
8240 higher numbered register, the load will work regardless of whether
8241 the value being loaded is big-wordian or little-wordian. The
8242 order of the two register loads can matter however, if the address
8243 of the memory location is actually held in one of the registers
8244 being overwritten by the load. */
8246 if (REGNO (x) > LAST_ARM_REGNUM)
8248 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
8252 if (REGNO (x) > LAST_ARM_REGNUM)
8254 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
8258 if (REGNO (x) > LAST_ARM_REGNUM)
8260 asm_fprintf (stream, "%r", REGNO (x) + 1);
8264 asm_fprintf (stream, "%r",
8265 GET_CODE (XEXP (x, 0)) == REG
8266 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
8270 asm_fprintf (stream, "{%r-%r}",
8272 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
8280 fputs (arm_condition_codes[get_arm_condition_code (x)],
8283 fputs (thumb_condition_code (x, 0), stream);
8291 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
8292 (get_arm_condition_code (x))],
8295 fputs (thumb_condition_code (x, 1), stream);
8302 if (GET_CODE (x) == REG)
8303 asm_fprintf (stream, "%r", REGNO (x));
8304 else if (GET_CODE (x) == MEM)
8306 output_memory_reference_mode = GET_MODE (x);
8307 output_address (XEXP (x, 0));
8309 else if (GET_CODE (x) == CONST_DOUBLE)
8310 fprintf (stream, "#%s", fp_immediate_constant (x));
8311 else if (GET_CODE (x) == NEG)
8312 abort (); /* This should never happen now. */
8315 fputc ('#', stream);
8316 output_addr_const (stream, x);
8321 /* A finite state machine takes care of noticing whether or not instructions
8322 can be conditionally executed, and thus decrease execution time and code
8323 size by deleting branch instructions. The fsm is controlled by
8324 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8326 /* The state of the fsm controlling condition codes are:
8327 0: normal, do nothing special
8328 1: make ASM_OUTPUT_OPCODE not output this instruction
8329 2: make ASM_OUTPUT_OPCODE not output this instruction
8330 3: make instructions conditional
8331 4: make instructions conditional
8333 State transitions (state->state by whom under condition):
8334 0 -> 1 final_prescan_insn if the `target' is a label
8335 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8336 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8337 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8338 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8339 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8340 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8341 (the target insn is arm_target_insn).
8343 If the jump clobbers the conditions then we use states 2 and 4.
8345 A similar thing can be done with conditional return insns.
8347 XXX In case the `target' is an unconditional branch, this conditionalising
8348 of the instructions always reduces code size, but not always execution
8349 time. But then, I want to reduce the code size to somewhere near what
8350 /bin/cc produces. */
8352 /* Returns the index of the ARM condition code string in
8353 `arm_condition_codes'. COMPARISON should be an rtx like
8354 `(eq (...) (...))'. */
8356 static enum arm_cond_code
8357 get_arm_condition_code (comparison)
8360 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
8362 register enum rtx_code comp_code = GET_CODE (comparison);
8364 if (GET_MODE_CLASS (mode) != MODE_CC)
8365 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
8366 XEXP (comparison, 1));
8370 case CC_DNEmode: code = ARM_NE; goto dominance;
8371 case CC_DEQmode: code = ARM_EQ; goto dominance;
8372 case CC_DGEmode: code = ARM_GE; goto dominance;
8373 case CC_DGTmode: code = ARM_GT; goto dominance;
8374 case CC_DLEmode: code = ARM_LE; goto dominance;
8375 case CC_DLTmode: code = ARM_LT; goto dominance;
8376 case CC_DGEUmode: code = ARM_CS; goto dominance;
8377 case CC_DGTUmode: code = ARM_HI; goto dominance;
8378 case CC_DLEUmode: code = ARM_LS; goto dominance;
8379 case CC_DLTUmode: code = ARM_CC;
8382 if (comp_code != EQ && comp_code != NE)
8385 if (comp_code == EQ)
8386 return ARM_INVERSE_CONDITION_CODE (code);
8392 case NE: return ARM_NE;
8393 case EQ: return ARM_EQ;
8394 case GE: return ARM_PL;
8395 case LT: return ARM_MI;
8402 case NE: return ARM_NE;
8403 case EQ: return ARM_EQ;
8409 /* These encodings assume that AC=1 in the FPA system control
8410 byte. This allows us to handle all cases except UNEQ and
8414 case GE: return ARM_GE;
8415 case GT: return ARM_GT;
8416 case LE: return ARM_LS;
8417 case LT: return ARM_MI;
8418 case NE: return ARM_NE;
8419 case EQ: return ARM_EQ;
8420 case ORDERED: return ARM_VC;
8421 case UNORDERED: return ARM_VS;
8422 case UNLT: return ARM_LT;
8423 case UNLE: return ARM_LE;
8424 case UNGT: return ARM_HI;
8425 case UNGE: return ARM_PL;
8426 /* UNEQ and LTGT do not have a representation. */
8427 case UNEQ: /* Fall through. */
8428 case LTGT: /* Fall through. */
8435 case NE: return ARM_NE;
8436 case EQ: return ARM_EQ;
8437 case GE: return ARM_LE;
8438 case GT: return ARM_LT;
8439 case LE: return ARM_GE;
8440 case LT: return ARM_GT;
8441 case GEU: return ARM_LS;
8442 case GTU: return ARM_CC;
8443 case LEU: return ARM_CS;
8444 case LTU: return ARM_HI;
8451 case LTU: return ARM_CS;
8452 case GEU: return ARM_CC;
8459 case NE: return ARM_NE;
8460 case EQ: return ARM_EQ;
8461 case GE: return ARM_GE;
8462 case GT: return ARM_GT;
8463 case LE: return ARM_LE;
8464 case LT: return ARM_LT;
8465 case GEU: return ARM_CS;
8466 case GTU: return ARM_HI;
8467 case LEU: return ARM_LS;
8468 case LTU: return ARM_CC;
8480 arm_final_prescan_insn (insn)
8483 /* BODY will hold the body of INSN. */
8484 register rtx body = PATTERN (insn);
8486 /* This will be 1 if trying to repeat the trick, and things need to be
8487 reversed if it appears to fail. */
8490 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8491 taken are clobbered, even if the rtl suggests otherwise. It also
8492 means that we have to grub around within the jump expression to find
8493 out what the conditions are when the jump isn't taken. */
8494 int jump_clobbers = 0;
8496 /* If we start with a return insn, we only succeed if we find another one. */
8497 int seeking_return = 0;
8499 /* START_INSN will hold the insn from where we start looking. This is the
8500 first insn after the following code_label if REVERSE is true. */
8501 rtx start_insn = insn;
8503 /* If in state 4, check if the target branch is reached, in order to
8504 change back to state 0. */
8505 if (arm_ccfsm_state == 4)
8507 if (insn == arm_target_insn)
8509 arm_target_insn = NULL;
8510 arm_ccfsm_state = 0;
8515 /* If in state 3, it is possible to repeat the trick, if this insn is an
8516 unconditional branch to a label, and immediately following this branch
8517 is the previous target label which is only used once, and the label this
8518 branch jumps to is not too far off. */
8519 if (arm_ccfsm_state == 3)
8521 if (simplejump_p (insn))
8523 start_insn = next_nonnote_insn (start_insn);
8524 if (GET_CODE (start_insn) == BARRIER)
8526 /* XXX Isn't this always a barrier? */
8527 start_insn = next_nonnote_insn (start_insn);
8529 if (GET_CODE (start_insn) == CODE_LABEL
8530 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8531 && LABEL_NUSES (start_insn) == 1)
8536 else if (GET_CODE (body) == RETURN)
8538 start_insn = next_nonnote_insn (start_insn);
8539 if (GET_CODE (start_insn) == BARRIER)
8540 start_insn = next_nonnote_insn (start_insn);
8541 if (GET_CODE (start_insn) == CODE_LABEL
8542 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8543 && LABEL_NUSES (start_insn) == 1)
8555 if (arm_ccfsm_state != 0 && !reverse)
8557 if (GET_CODE (insn) != JUMP_INSN)
8560 /* This jump might be paralleled with a clobber of the condition codes
8561 the jump should always come first */
8562 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
8563 body = XVECEXP (body, 0, 0);
8566 /* If this is a conditional return then we don't want to know */
8567 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8568 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
8569 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
8570 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
8575 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8576 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
8579 int fail = FALSE, succeed = FALSE;
8580 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8581 int then_not_else = TRUE;
8582 rtx this_insn = start_insn, label = 0;
8584 /* If the jump cannot be done with one instruction, we cannot
8585 conditionally execute the instruction in the inverse case. */
8586 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
8592 /* Register the insn jumped to. */
8595 if (!seeking_return)
8596 label = XEXP (SET_SRC (body), 0);
8598 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
8599 label = XEXP (XEXP (SET_SRC (body), 1), 0);
8600 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
8602 label = XEXP (XEXP (SET_SRC (body), 2), 0);
8603 then_not_else = FALSE;
8605 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
8607 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
8610 then_not_else = FALSE;
8615 /* See how many insns this branch skips, and what kind of insns. If all
8616 insns are okay, and the label or unconditional branch to the same
8617 label is not too far away, succeed. */
8618 for (insns_skipped = 0;
8619 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8623 this_insn = next_nonnote_insn (this_insn);
8627 switch (GET_CODE (this_insn))
8630 /* Succeed if it is the target label, otherwise fail since
8631 control falls in from somewhere else. */
8632 if (this_insn == label)
8636 arm_ccfsm_state = 2;
8637 this_insn = next_nonnote_insn (this_insn);
8640 arm_ccfsm_state = 1;
8648 /* Succeed if the following insn is the target label.
8650 If return insns are used then the last insn in a function
8651 will be a barrier. */
8652 this_insn = next_nonnote_insn (this_insn);
8653 if (this_insn && this_insn == label)
8657 arm_ccfsm_state = 2;
8658 this_insn = next_nonnote_insn (this_insn);
8661 arm_ccfsm_state = 1;
8669 /* If using 32-bit addresses the cc is not preserved over
8673 /* Succeed if the following insn is the target label,
8674 or if the following two insns are a barrier and
8675 the target label. */
8676 this_insn = next_nonnote_insn (this_insn);
8677 if (this_insn && GET_CODE (this_insn) == BARRIER)
8678 this_insn = next_nonnote_insn (this_insn);
8680 if (this_insn && this_insn == label
8681 && insns_skipped < max_insns_skipped)
8685 arm_ccfsm_state = 2;
8686 this_insn = next_nonnote_insn (this_insn);
8689 arm_ccfsm_state = 1;
8698 /* If this is an unconditional branch to the same label, succeed.
8699 If it is to another label, do nothing. If it is conditional,
8701 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8703 scanbody = PATTERN (this_insn);
8704 if (GET_CODE (scanbody) == SET
8705 && GET_CODE (SET_DEST (scanbody)) == PC)
8707 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
8708 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
8710 arm_ccfsm_state = 2;
8713 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
8716 /* Fail if a conditional return is undesirable (eg on a
8717 StrongARM), but still allow this if optimizing for size. */
8718 else if (GET_CODE (scanbody) == RETURN
8719 && !use_return_insn (TRUE)
8722 else if (GET_CODE (scanbody) == RETURN
8725 arm_ccfsm_state = 2;
8728 else if (GET_CODE (scanbody) == PARALLEL)
8730 switch (get_attr_conds (this_insn))
8740 fail = TRUE; /* Unrecognized jump (eg epilogue). */
8745 /* Instructions using or affecting the condition codes make it
8747 scanbody = PATTERN (this_insn);
8748 if (!(GET_CODE (scanbody) == SET
8749 || GET_CODE (scanbody) == PARALLEL)
8750 || get_attr_conds (this_insn) != CONDS_NOCOND)
8760 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8761 arm_target_label = CODE_LABEL_NUMBER (label);
8762 else if (seeking_return || arm_ccfsm_state == 2)
8764 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
8766 this_insn = next_nonnote_insn (this_insn);
8767 if (this_insn && (GET_CODE (this_insn) == BARRIER
8768 || GET_CODE (this_insn) == CODE_LABEL))
8773 /* Oh, dear! we ran off the end.. give up */
8774 recog (PATTERN (insn), insn, NULL);
8775 arm_ccfsm_state = 0;
8776 arm_target_insn = NULL;
8779 arm_target_insn = this_insn;
8788 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
8790 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
8791 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8792 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
8793 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8797 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8800 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
8804 if (reverse || then_not_else)
8805 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8808 /* Restore recog_data (getting the attributes of other insns can
8809 destroy this array, but final.c assumes that it remains intact
8810 across this call; since the insn has been recognized already we
8811 call recog direct). */
8812 recog (PATTERN (insn), insn, NULL);
8817 arm_regno_class (regno)
8822 if (regno == STACK_POINTER_REGNUM)
8824 if (regno == CC_REGNUM)
8831 if ( regno <= LAST_ARM_REGNUM
8832 || regno == FRAME_POINTER_REGNUM
8833 || regno == ARG_POINTER_REGNUM)
8834 return GENERAL_REGS;
8836 if (regno == CC_REGNUM)
8842 /* Handle a special case when computing the offset
8843 of an argument from the frame pointer. */
8845 arm_debugger_arg_offset (value, addr)
8851 /* We are only interested if dbxout_parms() failed to compute the offset. */
8855 /* We can only cope with the case where the address is held in a register. */
8856 if (GET_CODE (addr) != REG)
8859 /* If we are using the frame pointer to point at the argument, then
8860 an offset of 0 is correct. */
8861 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
8864 /* If we are using the stack pointer to point at the
8865 argument, then an offset of 0 is correct. */
8866 if ((TARGET_THUMB || !frame_pointer_needed)
8867 && REGNO (addr) == SP_REGNUM)
8870 /* Oh dear. The argument is pointed to by a register rather
8871 than being held in a register, or being stored at a known
8872 offset from the frame pointer. Since GDB only understands
8873 those two kinds of argument we must translate the address
8874 held in the register into an offset from the frame pointer.
8875 We do this by searching through the insns for the function
8876 looking to see where this register gets its value. If the
8877 register is initialised from the frame pointer plus an offset
8878 then we are in luck and we can continue, otherwise we give up.
8880 This code is exercised by producing debugging information
8881 for a function with arguments like this:
8883 double func (double a, double b, int c, double d) {return d;}
8885 Without this code the stab for parameter 'd' will be set to
8886 an offset of 0 from the frame pointer, rather than 8. */
8888 /* The if() statement says:
8890 If the insn is a normal instruction
8891 and if the insn is setting the value in a register
8892 and if the register being set is the register holding the address of the argument
8893 and if the address is computing by an addition
8894 that involves adding to a register
8895 which is the frame pointer
8900 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8902 if ( GET_CODE (insn) == INSN
8903 && GET_CODE (PATTERN (insn)) == SET
8904 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
8905 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
8906 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
8907 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
8908 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
8911 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
8920 warning ("Unable to compute real location of stacked parameter");
8921 value = 8; /* XXX magic hack */
8927 #define def_builtin(NAME, TYPE, CODE) \
8928 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
8931 arm_init_builtins ()
8933 tree endlink = void_list_node;
8934 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
8935 tree pchar_type_node = build_pointer_type (char_type_node);
8937 tree int_ftype_int, void_ftype_pchar;
8939 /* void func (void *) */
8941 = build_function_type (void_type_node,
8942 tree_cons (NULL_TREE, pchar_type_node, endlink));
8944 /* int func (int) */
8946 = build_function_type (integer_type_node, int_endlink);
8948 /* Initialize arm V5 builtins. */
8950 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
8952 /* Initialize arm V5E builtins. */
8954 def_builtin ("__builtin_prefetch", void_ftype_pchar,
8955 ARM_BUILTIN_PREFETCH);
8958 /* Expand an expression EXP that calls a built-in function,
8959 with result going to TARGET if that's convenient
8960 (and in mode MODE if that's convenient).
8961 SUBTARGET may be used as the target for computing one of EXP's operands.
8962 IGNORE is nonzero if the value is to be ignored. */
8965 arm_expand_builtin (exp, target, subtarget, mode, ignore)
8968 rtx subtarget ATTRIBUTE_UNUSED;
8969 enum machine_mode mode ATTRIBUTE_UNUSED;
8970 int ignore ATTRIBUTE_UNUSED;
8972 enum insn_code icode;
8973 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8974 tree arglist = TREE_OPERAND (exp, 1);
8977 enum machine_mode tmode, mode0;
8978 int fcode = DECL_FUNCTION_CODE (fndecl);
8985 case ARM_BUILTIN_CLZ:
8986 icode = CODE_FOR_clz;
8987 arg0 = TREE_VALUE (arglist);
8988 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8989 tmode = insn_data[icode].operand[0].mode;
8990 mode0 = insn_data[icode].operand[1].mode;
8992 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8993 op0 = copy_to_mode_reg (mode0, op0);
8995 || GET_MODE (target) != tmode
8996 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8997 target = gen_reg_rtx (tmode);
8998 pat = GEN_FCN (icode) (target, op0);
9004 case ARM_BUILTIN_PREFETCH:
9005 icode = CODE_FOR_prefetch;
9006 arg0 = TREE_VALUE (arglist);
9007 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
9009 op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (Pmode, op0));
9011 pat = GEN_FCN (icode) (op0);
9018 /* @@@ Should really do something sensible here. */
9022 /* Recursively search through all of the blocks in a function
9023 checking to see if any of the variables created in that
9024 function match the RTX called 'orig'. If they do then
9025 replace them with the RTX called 'new'. */
9028 replace_symbols_in_block (block, orig, new)
9033 for (; block; block = BLOCK_CHAIN (block))
9037 if (!TREE_USED (block))
9040 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
9042 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
9043 || DECL_IGNORED_P (sym)
9044 || TREE_CODE (sym) != VAR_DECL
9045 || DECL_EXTERNAL (sym)
9046 || !rtx_equal_p (DECL_RTL (sym), orig)
9050 SET_DECL_RTL (sym, new);
9053 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
9057 /* Return the number (counting from 0) of the least significant set
9063 number_of_first_bit_set (mask)
9069 (mask & (1 << bit)) == 0;
9076 /* Generate code to return from a thumb function.
9077 If 'reg_containing_return_addr' is -1, then the return address is
9078 actually on the stack, at the stack pointer. */
9080 thumb_exit (f, reg_containing_return_addr, eh_ofs)
9082 int reg_containing_return_addr;
9085 unsigned regs_available_for_popping;
9086 unsigned regs_to_pop;
9092 int restore_a4 = FALSE;
9094 /* Compute the registers we need to pop. */
9098 /* There is an assumption here, that if eh_ofs is not NULL, the
9099 normal return address will have been pushed. */
9100 if (reg_containing_return_addr == -1 || eh_ofs)
9102 /* When we are generating a return for __builtin_eh_return,
9103 reg_containing_return_addr must specify the return regno. */
9104 if (eh_ofs && reg_containing_return_addr == -1)
9107 regs_to_pop |= 1 << LR_REGNUM;
9111 if (TARGET_BACKTRACE)
9113 /* Restore the (ARM) frame pointer and stack pointer. */
9114 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
9118 /* If there is nothing to pop then just emit the BX instruction and
9120 if (pops_needed == 0)
9123 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9125 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9128 /* Otherwise if we are not supporting interworking and we have not created
9129 a backtrace structure and the function was not entered in ARM mode then
9130 just pop the return address straight into the PC. */
9131 else if (!TARGET_INTERWORK
9132 && !TARGET_BACKTRACE
9133 && !is_called_in_ARM_mode (current_function_decl))
9137 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
9138 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9139 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9142 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
9147 /* Find out how many of the (return) argument registers we can corrupt. */
9148 regs_available_for_popping = 0;
9150 /* If returning via __builtin_eh_return, the bottom three registers
9151 all contain information needed for the return. */
9157 /* If we can deduce the registers used from the function's
9158 return value. This is more reliable that examining
9159 regs_ever_live[] because that will be set if the register is
9160 ever used in the function, not just if the register is used
9161 to hold a return value. */
9163 if (current_function_return_rtx != 0)
9164 mode = GET_MODE (current_function_return_rtx);
9167 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9169 size = GET_MODE_SIZE (mode);
9173 /* In a void function we can use any argument register.
9174 In a function that returns a structure on the stack
9175 we can use the second and third argument registers. */
9176 if (mode == VOIDmode)
9177 regs_available_for_popping =
9178 (1 << ARG_REGISTER (1))
9179 | (1 << ARG_REGISTER (2))
9180 | (1 << ARG_REGISTER (3));
9182 regs_available_for_popping =
9183 (1 << ARG_REGISTER (2))
9184 | (1 << ARG_REGISTER (3));
9187 regs_available_for_popping =
9188 (1 << ARG_REGISTER (2))
9189 | (1 << ARG_REGISTER (3));
9191 regs_available_for_popping =
9192 (1 << ARG_REGISTER (3));
9195 /* Match registers to be popped with registers into which we pop them. */
9196 for (available = regs_available_for_popping,
9197 required = regs_to_pop;
9198 required != 0 && available != 0;
9199 available &= ~(available & - available),
9200 required &= ~(required & - required))
9203 /* If we have any popping registers left over, remove them. */
9205 regs_available_for_popping &= ~available;
9207 /* Otherwise if we need another popping register we can use
9208 the fourth argument register. */
9209 else if (pops_needed)
9211 /* If we have not found any free argument registers and
9212 reg a4 contains the return address, we must move it. */
9213 if (regs_available_for_popping == 0
9214 && reg_containing_return_addr == LAST_ARG_REGNUM)
9216 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9217 reg_containing_return_addr = LR_REGNUM;
9221 /* Register a4 is being used to hold part of the return value,
9222 but we have dire need of a free, low register. */
9225 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
9228 if (reg_containing_return_addr != LAST_ARG_REGNUM)
9230 /* The fourth argument register is available. */
9231 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9237 /* Pop as many registers as we can. */
9238 thumb_pushpop (f, regs_available_for_popping, FALSE);
9240 /* Process the registers we popped. */
9241 if (reg_containing_return_addr == -1)
9243 /* The return address was popped into the lowest numbered register. */
9244 regs_to_pop &= ~(1 << LR_REGNUM);
9246 reg_containing_return_addr =
9247 number_of_first_bit_set (regs_available_for_popping);
9249 /* Remove this register for the mask of available registers, so that
9250 the return address will not be corrupted by futher pops. */
9251 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
9254 /* If we popped other registers then handle them here. */
9255 if (regs_available_for_popping)
9259 /* Work out which register currently contains the frame pointer. */
9260 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
9262 /* Move it into the correct place. */
9263 asm_fprintf (f, "\tmov\t%r, %r\n",
9264 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
9266 /* (Temporarily) remove it from the mask of popped registers. */
9267 regs_available_for_popping &= ~(1 << frame_pointer);
9268 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9270 if (regs_available_for_popping)
9274 /* We popped the stack pointer as well,
9275 find the register that contains it. */
9276 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
9278 /* Move it into the stack register. */
9279 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9281 /* At this point we have popped all necessary registers, so
9282 do not worry about restoring regs_available_for_popping
9283 to its correct value:
9285 assert (pops_needed == 0)
9286 assert (regs_available_for_popping == (1 << frame_pointer))
9287 assert (regs_to_pop == (1 << STACK_POINTER)) */
9291 /* Since we have just move the popped value into the frame
9292 pointer, the popping register is available for reuse, and
9293 we know that we still have the stack pointer left to pop. */
9294 regs_available_for_popping |= (1 << frame_pointer);
9298 /* If we still have registers left on the stack, but we no longer have
9299 any registers into which we can pop them, then we must move the return
9300 address into the link register and make available the register that
9302 if (regs_available_for_popping == 0 && pops_needed > 0)
9304 regs_available_for_popping |= 1 << reg_containing_return_addr;
9306 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
9307 reg_containing_return_addr);
9309 reg_containing_return_addr = LR_REGNUM;
9312 /* If we have registers left on the stack then pop some more.
9313 We know that at most we will want to pop FP and SP. */
9314 if (pops_needed > 0)
9319 thumb_pushpop (f, regs_available_for_popping, FALSE);
9321 /* We have popped either FP or SP.
9322 Move whichever one it is into the correct register. */
9323 popped_into = number_of_first_bit_set (regs_available_for_popping);
9324 move_to = number_of_first_bit_set (regs_to_pop);
9326 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
9328 regs_to_pop &= ~(1 << move_to);
9333 /* If we still have not popped everything then we must have only
9334 had one register available to us and we are now popping the SP. */
9335 if (pops_needed > 0)
9339 thumb_pushpop (f, regs_available_for_popping, FALSE);
9341 popped_into = number_of_first_bit_set (regs_available_for_popping);
9343 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
9345 assert (regs_to_pop == (1 << STACK_POINTER))
9346 assert (pops_needed == 1)
9350 /* If necessary restore the a4 register. */
9353 if (reg_containing_return_addr != LR_REGNUM)
9355 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9356 reg_containing_return_addr = LR_REGNUM;
9359 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9363 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9365 /* Return to caller. */
9366 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9369 /* Emit code to push or pop registers to or from the stack. */
9371 thumb_pushpop (f, mask, push)
9377 int lo_mask = mask & 0xFF;
9379 if (lo_mask == 0 && !push && (mask & (1 << 15)))
9381 /* Special case. Do not generate a POP PC statement here, do it in
9383 thumb_exit (f, -1, NULL_RTX);
9387 fprintf (f, "\t%s\t{", push ? "push" : "pop");
9389 /* Look at the low registers first. */
9390 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
9394 asm_fprintf (f, "%r", regno);
9396 if ((lo_mask & ~1) != 0)
9401 if (push && (mask & (1 << LR_REGNUM)))
9403 /* Catch pushing the LR. */
9407 asm_fprintf (f, "%r", LR_REGNUM);
9409 else if (!push && (mask & (1 << PC_REGNUM)))
9411 /* Catch popping the PC. */
9412 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9414 /* The PC is never poped directly, instead
9415 it is popped into r3 and then BX is used. */
9418 thumb_exit (f, -1, NULL_RTX);
9427 asm_fprintf (f, "%r", PC_REGNUM);
9435 thumb_final_prescan_insn (insn)
9438 if (flag_print_asm_name)
9439 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9440 INSN_ADDRESSES (INSN_UID (insn)));
9444 thumb_shiftable_const (val)
9445 unsigned HOST_WIDE_INT val;
9447 unsigned HOST_WIDE_INT mask = 0xff;
9450 if (val == 0) /* XXX */
9453 for (i = 0; i < 25; i++)
9454 if ((val & (mask << i)) == val)
9460 /* Returns non-zero if the current function contains,
9461 or might contain a far jump. */
9463 thumb_far_jump_used_p (int in_prologue)
9467 /* This test is only important for leaf functions. */
9468 /* assert (!leaf_function_p ()); */
9470 /* If we have already decided that far jumps may be used,
9471 do not bother checking again, and always return true even if
9472 it turns out that they are not being used. Once we have made
9473 the decision that far jumps are present (and that hence the link
9474 register will be pushed onto the stack) we cannot go back on it. */
9475 if (cfun->machine->far_jump_used)
9478 /* If this function is not being called from the prologue/epilogue
9479 generation code then it must be being called from the
9480 INITIAL_ELIMINATION_OFFSET macro. */
9483 /* In this case we know that we are being asked about the elimination
9484 of the arg pointer register. If that register is not being used,
9485 then there are no arguments on the stack, and we do not have to
9486 worry that a far jump might force the prologue to push the link
9487 register, changing the stack offsets. In this case we can just
9488 return false, since the presence of far jumps in the function will
9489 not affect stack offsets.
9491 If the arg pointer is live (or if it was live, but has now been
9492 eliminated and so set to dead) then we do have to test to see if
9493 the function might contain a far jump. This test can lead to some
9494 false negatives, since before reload is completed, then length of
9495 branch instructions is not known, so gcc defaults to returning their
9496 longest length, which in turn sets the far jump attribute to true.
9498 A false negative will not result in bad code being generated, but it
9499 will result in a needless push and pop of the link register. We
9500 hope that this does not occur too often. */
9501 if (regs_ever_live [ARG_POINTER_REGNUM])
9502 cfun->machine->arg_pointer_live = 1;
9503 else if (!cfun->machine->arg_pointer_live)
9507 /* Check to see if the function contains a branch
9508 insn with the far jump attribute set. */
9509 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9511 if (GET_CODE (insn) == JUMP_INSN
9512 /* Ignore tablejump patterns. */
9513 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9514 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9515 && get_attr_far_jump (insn) == FAR_JUMP_YES
9518 /* Record the fact that we have decied that
9519 the function does use far jumps. */
9520 cfun->machine->far_jump_used = 1;
9528 /* Return non-zero if FUNC must be entered in ARM mode. */
9530 is_called_in_ARM_mode (func)
9533 if (TREE_CODE (func) != FUNCTION_DECL)
9536 /* Ignore the problem about functions whoes address is taken. */
9537 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
9541 return lookup_attribute ("interfacearm", DECL_MACHINE_ATTRIBUTES (func)) != NULL_TREE;
9547 /* The bits which aren't usefully expanded as rtl. */
9550 thumb_unexpanded_epilogue ()
9553 int live_regs_mask = 0;
9554 int high_regs_pushed = 0;
9555 int leaf_function = leaf_function_p ();
9557 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9559 if (return_used_this_function)
9562 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9563 if (regs_ever_live[regno] && !call_used_regs[regno]
9564 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9565 live_regs_mask |= 1 << regno;
9567 for (regno = 8; regno < 13; regno++)
9569 if (regs_ever_live[regno] && !call_used_regs[regno]
9570 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9574 /* The prolog may have pushed some high registers to use as
9575 work registers. eg the testuite file:
9576 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9577 compiles to produce:
9578 push {r4, r5, r6, r7, lr}
9582 as part of the prolog. We have to undo that pushing here. */
9584 if (high_regs_pushed)
9586 int mask = live_regs_mask;
9592 /* If we can deduce the registers used from the function's return value.
9593 This is more reliable that examining regs_ever_live[] because that
9594 will be set if the register is ever used in the function, not just if
9595 the register is used to hold a return value. */
9597 if (current_function_return_rtx != 0)
9598 mode = GET_MODE (current_function_return_rtx);
9601 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9603 size = GET_MODE_SIZE (mode);
9605 /* Unless we are returning a type of size > 12 register r3 is
9611 /* Oh dear! We have no low registers into which we can pop
9614 ("no low registers available for popping high registers");
9616 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
9617 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9618 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register)))
9621 while (high_regs_pushed)
9623 /* Find lo register(s) into which the high register(s) can
9625 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9627 if (mask & (1 << regno))
9629 if (high_regs_pushed == 0)
9633 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
9635 /* Pop the values into the low register(s). */
9636 thumb_pushpop (asm_out_file, mask, 0);
9638 /* Move the value(s) into the high registers. */
9639 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9641 if (mask & (1 << regno))
9643 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
9646 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
9647 if (regs_ever_live[next_hi_reg]
9648 && !call_used_regs[next_hi_reg]
9649 && !(TARGET_SINGLE_PIC_BASE
9650 && (next_hi_reg == arm_pic_register)))
9657 had_to_push_lr = (live_regs_mask || !leaf_function
9658 || thumb_far_jump_used_p (1));
9660 if (TARGET_BACKTRACE
9661 && ((live_regs_mask & 0xFF) == 0)
9662 && regs_ever_live [LAST_ARG_REGNUM] != 0)
9664 /* The stack backtrace structure creation code had to
9665 push R7 in order to get a work register, so we pop
9667 live_regs_mask |= (1 << LAST_LO_REGNUM);
9670 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
9673 && !is_called_in_ARM_mode (current_function_decl)
9675 live_regs_mask |= 1 << PC_REGNUM;
9677 /* Either no argument registers were pushed or a backtrace
9678 structure was created which includes an adjusted stack
9679 pointer, so just pop everything. */
9681 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9684 thumb_exit (asm_out_file, 2, eh_ofs);
9685 /* We have either just popped the return address into the
9686 PC or it is was kept in LR for the entire function or
9687 it is still on the stack because we do not want to
9688 return by doing a pop {pc}. */
9689 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
9690 thumb_exit (asm_out_file,
9692 && is_called_in_ARM_mode (current_function_decl)) ?
9693 -1 : LR_REGNUM, NULL_RTX);
9697 /* Pop everything but the return address. */
9698 live_regs_mask &= ~(1 << PC_REGNUM);
9701 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9704 /* Get the return address into a temporary register. */
9705 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
9707 /* Remove the argument registers that were pushed onto the stack. */
9708 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
9709 SP_REGNUM, SP_REGNUM,
9710 current_function_pretend_args_size);
9713 thumb_exit (asm_out_file, 2, eh_ofs);
9715 thumb_exit (asm_out_file,
9716 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
9722 /* Functions to save and restore machine-specific function data. */
9725 arm_mark_machine_status (p)
9726 struct function * p;
9728 machine_function *machine = p->machine;
9731 ggc_mark_rtx (machine->eh_epilogue_sp_ofs);
9735 arm_init_machine_status (p)
9736 struct function * p;
9739 (machine_function *) xcalloc (1, sizeof (machine_function));
9741 #if ARM_FT_UNKNOWWN != 0
9742 ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN;
9747 arm_free_machine_status (p)
9748 struct function * p;
9757 /* Return an RTX indicating where the return address to the
9758 calling function can be found. */
9760 arm_return_addr (count, frame)
9762 rtx frame ATTRIBUTE_UNUSED;
9768 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
9771 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
9772 GEN_INT (RETURN_ADDR_MASK26));
9773 return get_func_hard_reg_initial_val (cfun, lr);
9777 /* Do anything needed before RTL is emitted for each function. */
9779 arm_init_expanders ()
9781 /* Arrange to initialize and mark the machine per-function status. */
9782 init_machine_status = arm_init_machine_status;
9783 mark_machine_status = arm_mark_machine_status;
9784 free_machine_status = arm_free_machine_status;
9787 /* Generate the rest of a function's prologue. */
9789 thumb_expand_prologue ()
9791 HOST_WIDE_INT amount = (get_frame_size ()
9792 + current_function_outgoing_args_size);
9793 unsigned long func_type;
9795 func_type = arm_current_func_type ();
9797 /* Naked functions don't have prologues. */
9798 if (IS_NAKED (func_type))
9801 if (IS_INTERRUPT (func_type))
9803 error ("Interrupt Service Routines cannot be coded in Thumb mode.");
9807 if (frame_pointer_needed)
9808 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
9812 amount = ROUND_UP (amount);
9815 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9816 GEN_INT (-amount)));
9822 /* The stack decrement is too big for an immediate value in a single
9823 insn. In theory we could issue multiple subtracts, but after
9824 three of them it becomes more space efficient to place the full
9825 value in the constant pool and load into a register. (Also the
9826 ARM debugger really likes to see only one stack decrement per
9827 function). So instead we look for a scratch register into which
9828 we can load the decrement, and then we subtract this from the
9829 stack pointer. Unfortunately on the thumb the only available
9830 scratch registers are the argument registers, and we cannot use
9831 these as they may hold arguments to the function. Instead we
9832 attempt to locate a call preserved register which is used by this
9833 function. If we can find one, then we know that it will have
9834 been pushed at the start of the prologue and so we can corrupt
9836 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
9837 if (regs_ever_live[regno]
9838 && !call_used_regs[regno] /* Paranoia */
9839 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))
9840 && !(frame_pointer_needed
9841 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
9844 if (regno > LAST_LO_REGNUM) /* Very unlikely */
9846 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
9848 /* Choose an arbitary, non-argument low register. */
9849 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
9851 /* Save it by copying it into a high, scratch register. */
9852 emit_insn (gen_movsi (spare, reg));
9854 /* Decrement the stack. */
9855 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9856 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9859 /* Restore the low register's original value. */
9860 emit_insn (gen_movsi (reg, spare));
9862 /* Emit a USE of the restored scratch register, so that flow
9863 analysis will not consider the restore redundant. The
9864 register won't be used again in this function and isn't
9865 restored by the epilogue. */
9866 emit_insn (gen_rtx_USE (VOIDmode, reg));
9870 reg = gen_rtx (REG, SImode, regno);
9872 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9873 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9879 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9880 emit_insn (gen_blockage ());
9884 thumb_expand_epilogue ()
9886 HOST_WIDE_INT amount = (get_frame_size ()
9887 + current_function_outgoing_args_size);
9889 /* Naked functions don't have prologues. */
9890 if (IS_NAKED (arm_current_func_type ()))
9893 if (frame_pointer_needed)
9894 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
9897 amount = ROUND_UP (amount);
9900 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9904 /* r3 is always free in the epilogue. */
9905 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
9907 emit_insn (gen_movsi (reg, GEN_INT (amount)));
9908 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
9912 /* Emit a USE (stack_pointer_rtx), so that
9913 the stack adjustment will not be deleted. */
9914 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9916 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9917 emit_insn (gen_blockage ());
9921 thumb_output_function_prologue (f, size)
9923 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
9925 int live_regs_mask = 0;
9926 int high_regs_pushed = 0;
9929 if (IS_NAKED (arm_current_func_type ()))
9932 if (is_called_in_ARM_mode (current_function_decl))
9936 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
9938 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
9940 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9942 /* Generate code sequence to switch us into Thumb mode. */
9943 /* The .code 32 directive has already been emitted by
9944 ASM_DECLARE_FUNCTION_NAME. */
9945 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
9946 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
9948 /* Generate a label, so that the debugger will notice the
9949 change in instruction sets. This label is also used by
9950 the assembler to bypass the ARM code when this function
9951 is called from a Thumb encoded function elsewhere in the
9952 same file. Hence the definition of STUB_NAME here must
9953 agree with the definition in gas/config/tc-arm.c */
9955 #define STUB_NAME ".real_start_of"
9957 asm_fprintf (f, "\t.code\t16\n");
9959 if (arm_dllexport_name_p (name))
9960 name = arm_strip_name_encoding (name);
9962 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
9963 asm_fprintf (f, "\t.thumb_func\n");
9964 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
9967 if (current_function_pretend_args_size)
9969 if (current_function_anonymous_args)
9973 asm_fprintf (f, "\tpush\t{");
9975 num_pushes = NUM_INTS (current_function_pretend_args_size);
9977 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
9978 regno <= LAST_ARG_REGNUM;
9980 asm_fprintf (f, "%r%s", regno,
9981 regno == LAST_ARG_REGNUM ? "" : ", ");
9983 asm_fprintf (f, "}\n");
9986 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
9987 SP_REGNUM, SP_REGNUM,
9988 current_function_pretend_args_size);
9991 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9992 if (regs_ever_live[regno] && !call_used_regs[regno]
9993 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9994 live_regs_mask |= 1 << regno;
9996 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
9997 live_regs_mask |= 1 << LR_REGNUM;
9999 if (TARGET_BACKTRACE)
10002 int work_register = 0;
10005 /* We have been asked to create a stack backtrace structure.
10006 The code looks like this:
10010 0 sub SP, #16 Reserve space for 4 registers.
10011 2 push {R7} Get a work register.
10012 4 add R7, SP, #20 Get the stack pointer before the push.
10013 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10014 8 mov R7, PC Get hold of the start of this code plus 12.
10015 10 str R7, [SP, #16] Store it.
10016 12 mov R7, FP Get hold of the current frame pointer.
10017 14 str R7, [SP, #4] Store it.
10018 16 mov R7, LR Get hold of the current return address.
10019 18 str R7, [SP, #12] Store it.
10020 20 add R7, SP, #16 Point at the start of the backtrace structure.
10021 22 mov FP, R7 Put this value into the frame pointer. */
10023 if ((live_regs_mask & 0xFF) == 0)
10025 /* See if the a4 register is free. */
10027 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
10028 work_register = LAST_ARG_REGNUM;
10029 else /* We must push a register of our own */
10030 live_regs_mask |= (1 << LAST_LO_REGNUM);
10033 if (work_register == 0)
10035 /* Select a register from the list that will be pushed to
10036 use as our work register. */
10037 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
10038 if ((1 << work_register) & live_regs_mask)
10043 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10044 SP_REGNUM, SP_REGNUM);
10046 if (live_regs_mask)
10047 thumb_pushpop (f, live_regs_mask, 1);
10049 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
10050 if (wr & live_regs_mask)
10053 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10054 offset + 16 + current_function_pretend_args_size);
10056 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10059 /* Make sure that the instruction fetching the PC is in the right place
10060 to calculate "start of backtrace creation code + 12". */
10061 if (live_regs_mask)
10063 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10064 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10066 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10067 ARM_HARD_FRAME_POINTER_REGNUM);
10068 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10073 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10074 ARM_HARD_FRAME_POINTER_REGNUM);
10075 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10077 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10078 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10082 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
10083 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10085 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10087 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10088 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
10090 else if (live_regs_mask)
10091 thumb_pushpop (f, live_regs_mask, 1);
10093 for (regno = 8; regno < 13; regno++)
10095 if (regs_ever_live[regno] && !call_used_regs[regno]
10096 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
10097 high_regs_pushed++;
10100 if (high_regs_pushed)
10102 int pushable_regs = 0;
10103 int mask = live_regs_mask & 0xff;
10106 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
10108 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
10109 && !(TARGET_SINGLE_PIC_BASE
10110 && (next_hi_reg == arm_pic_register)))
10114 pushable_regs = mask;
10116 if (pushable_regs == 0)
10118 /* Desperation time -- this probably will never happen. */
10119 if (regs_ever_live[LAST_ARG_REGNUM]
10120 || !call_used_regs[LAST_ARG_REGNUM])
10121 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
10122 mask = 1 << LAST_ARG_REGNUM;
10125 while (high_regs_pushed > 0)
10127 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
10129 if (mask & (1 << regno))
10131 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
10133 high_regs_pushed--;
10135 if (high_regs_pushed)
10136 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
10139 if (regs_ever_live[next_hi_reg]
10140 && !call_used_regs[next_hi_reg]
10141 && !(TARGET_SINGLE_PIC_BASE
10142 && (next_hi_reg == arm_pic_register)))
10147 mask &= ~((1 << regno) - 1);
10153 thumb_pushpop (f, mask, 1);
10156 if (pushable_regs == 0
10157 && (regs_ever_live[LAST_ARG_REGNUM]
10158 || !call_used_regs[LAST_ARG_REGNUM]))
10159 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10163 /* Handle the case of a double word load into a low register from
10164 a computed memory address. The computed address may involve a
10165 register which is overwritten by the load. */
10168 thumb_load_double_from_address (operands)
10177 if (GET_CODE (operands[0]) != REG)
10180 if (GET_CODE (operands[1]) != MEM)
10183 /* Get the memory address. */
10184 addr = XEXP (operands[1], 0);
10186 /* Work out how the memory address is computed. */
10187 switch (GET_CODE (addr))
10190 operands[2] = gen_rtx (MEM, SImode,
10191 plus_constant (XEXP (operands[1], 0), 4));
10193 if (REGNO (operands[0]) == REGNO (addr))
10195 output_asm_insn ("ldr\t%H0, %2", operands);
10196 output_asm_insn ("ldr\t%0, %1", operands);
10200 output_asm_insn ("ldr\t%0, %1", operands);
10201 output_asm_insn ("ldr\t%H0, %2", operands);
10206 /* Compute <address> + 4 for the high order load. */
10207 operands[2] = gen_rtx (MEM, SImode,
10208 plus_constant (XEXP (operands[1], 0), 4));
10210 output_asm_insn ("ldr\t%0, %1", operands);
10211 output_asm_insn ("ldr\t%H0, %2", operands);
10215 arg1 = XEXP (addr, 0);
10216 arg2 = XEXP (addr, 1);
10218 if (CONSTANT_P (arg1))
10219 base = arg2, offset = arg1;
10221 base = arg1, offset = arg2;
10223 if (GET_CODE (base) != REG)
10226 /* Catch the case of <address> = <reg> + <reg> */
10227 if (GET_CODE (offset) == REG)
10229 int reg_offset = REGNO (offset);
10230 int reg_base = REGNO (base);
10231 int reg_dest = REGNO (operands[0]);
10233 /* Add the base and offset registers together into the
10234 higher destination register. */
10235 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
10236 reg_dest + 1, reg_base, reg_offset);
10238 /* Load the lower destination register from the address in
10239 the higher destination register. */
10240 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
10241 reg_dest, reg_dest + 1);
10243 /* Load the higher destination register from its own address
10245 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
10246 reg_dest + 1, reg_dest + 1);
10250 /* Compute <address> + 4 for the high order load. */
10251 operands[2] = gen_rtx (MEM, SImode,
10252 plus_constant (XEXP (operands[1], 0), 4));
10254 /* If the computed address is held in the low order register
10255 then load the high order register first, otherwise always
10256 load the low order register first. */
10257 if (REGNO (operands[0]) == REGNO (base))
10259 output_asm_insn ("ldr\t%H0, %2", operands);
10260 output_asm_insn ("ldr\t%0, %1", operands);
10264 output_asm_insn ("ldr\t%0, %1", operands);
10265 output_asm_insn ("ldr\t%H0, %2", operands);
10271 /* With no registers to worry about we can just load the value
10273 operands[2] = gen_rtx (MEM, SImode,
10274 plus_constant (XEXP (operands[1], 0), 4));
10276 output_asm_insn ("ldr\t%H0, %2", operands);
10277 output_asm_insn ("ldr\t%0, %1", operands);
10290 thumb_output_move_mem_multiple (n, operands)
10299 if (REGNO (operands[4]) > REGNO (operands[5]))
10302 operands[4] = operands[5];
10305 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
10306 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
10310 if (REGNO (operands[4]) > REGNO (operands[5]))
10313 operands[4] = operands[5];
10316 if (REGNO (operands[5]) > REGNO (operands[6]))
10319 operands[5] = operands[6];
10322 if (REGNO (operands[4]) > REGNO (operands[5]))
10325 operands[4] = operands[5];
10329 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
10330 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
10340 /* Routines for generating rtl */
10343 thumb_expand_movstrqi (operands)
10346 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
10347 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
10348 HOST_WIDE_INT len = INTVAL (operands[2]);
10349 HOST_WIDE_INT offset = 0;
10353 emit_insn (gen_movmem12b (out, in, out, in));
10359 emit_insn (gen_movmem8b (out, in, out, in));
10365 rtx reg = gen_reg_rtx (SImode);
10366 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
10367 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
10374 rtx reg = gen_reg_rtx (HImode);
10375 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
10376 plus_constant (in, offset))));
10377 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
10385 rtx reg = gen_reg_rtx (QImode);
10386 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
10387 plus_constant (in, offset))));
10388 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
10394 thumb_cmp_operand (op, mode)
10396 enum machine_mode mode;
10398 return ((GET_CODE (op) == CONST_INT
10399 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
10400 || register_operand (op, mode));
10403 static const char *
10404 thumb_condition_code (x, invert)
10408 static const char * conds[] =
10410 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10411 "hi", "ls", "ge", "lt", "gt", "le"
10415 switch (GET_CODE (x))
10417 case EQ: val = 0; break;
10418 case NE: val = 1; break;
10419 case GEU: val = 2; break;
10420 case LTU: val = 3; break;
10421 case GTU: val = 8; break;
10422 case LEU: val = 9; break;
10423 case GE: val = 10; break;
10424 case LT: val = 11; break;
10425 case GT: val = 12; break;
10426 case LE: val = 13; break;
10431 return conds[val ^ invert];
10434 /* Handle storing a half-word to memory during reload. */
10436 thumb_reload_out_hi (operands)
10439 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
10442 /* Handle storing a half-word to memory during reload. */
10444 thumb_reload_in_hi (operands)
10445 rtx * operands ATTRIBUTE_UNUSED;
10450 /* Return the length of a function name prefix
10451 that starts with the character 'c'. */
10453 arm_get_strip_length (char c)
10457 ARM_NAME_ENCODING_LENGTHS
10462 /* Return a pointer to a function's name with any
10463 and all prefix encodings stripped from it. */
10465 arm_strip_name_encoding (const char * name)
10469 while ((skip = arm_get_strip_length (* name)))
10475 #ifdef AOF_ASSEMBLER
10476 /* Special functions only needed when producing AOF syntax assembler. */
10478 rtx aof_pic_label = NULL_RTX;
10481 struct pic_chain * next;
10485 static struct pic_chain * aof_pic_chain = NULL;
10491 struct pic_chain ** chainp;
10494 if (aof_pic_label == NULL_RTX)
10496 /* We mark this here and not in arm_add_gc_roots() to avoid
10497 polluting even more code with ifdefs, and because it never
10498 contains anything useful until we assign to it here. */
10499 ggc_add_rtx_root (&aof_pic_label, 1);
10500 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
10503 for (offset = 0, chainp = &aof_pic_chain; *chainp;
10504 offset += 4, chainp = &(*chainp)->next)
10505 if ((*chainp)->symname == XSTR (x, 0))
10506 return plus_constant (aof_pic_label, offset);
10508 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
10509 (*chainp)->next = NULL;
10510 (*chainp)->symname = XSTR (x, 0);
10511 return plus_constant (aof_pic_label, offset);
10515 aof_dump_pic_table (f)
10518 struct pic_chain * chain;
10520 if (aof_pic_chain == NULL)
10523 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
10524 PIC_OFFSET_TABLE_REGNUM,
10525 PIC_OFFSET_TABLE_REGNUM);
10526 fputs ("|x$adcons|\n", f);
10528 for (chain = aof_pic_chain; chain; chain = chain->next)
10530 fputs ("\tDCD\t", f);
10531 assemble_name (f, chain->symname);
10536 int arm_text_section_count = 1;
10539 aof_text_section ()
10541 static char buf[100];
10542 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
10543 arm_text_section_count++);
10545 strcat (buf, ", PIC, REENTRANT");
10549 static int arm_data_section_count = 1;
10552 aof_data_section ()
10554 static char buf[100];
10555 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
10559 /* The AOF assembler is religiously strict about declarations of
10560 imported and exported symbols, so that it is impossible to declare
10561 a function as imported near the beginning of the file, and then to
10562 export it later on. It is, however, possible to delay the decision
10563 until all the functions in the file have been compiled. To get
10564 around this, we maintain a list of the imports and exports, and
10565 delete from it any that are subsequently defined. At the end of
10566 compilation we spit the remainder of the list out before the END
10571 struct import * next;
10575 static struct import * imports_list = NULL;
10578 aof_add_import (name)
10581 struct import * new;
10583 for (new = imports_list; new; new = new->next)
10584 if (new->name == name)
10587 new = (struct import *) xmalloc (sizeof (struct import));
10588 new->next = imports_list;
10589 imports_list = new;
10594 aof_delete_import (name)
10597 struct import ** old;
10599 for (old = &imports_list; *old; old = & (*old)->next)
10601 if ((*old)->name == name)
10603 *old = (*old)->next;
10609 int arm_main_function = 0;
10612 aof_dump_imports (f)
10615 /* The AOF assembler needs this to cause the startup code to be extracted
10616 from the library. Brining in __main causes the whole thing to work
10618 if (arm_main_function)
10621 fputs ("\tIMPORT __main\n", f);
10622 fputs ("\tDCD __main\n", f);
10625 /* Now dump the remaining imports. */
10626 while (imports_list)
10628 fprintf (f, "\tIMPORT\t");
10629 assemble_name (f, imports_list->name);
10631 imports_list = imports_list->next;
10634 #endif /* AOF_ASSEMBLER */