1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx, int, int, int *);
132 static int arm_address_cost (rtx);
133 static bool arm_memory_load_p (rtx);
134 static bool arm_cirrus_insn_p (rtx);
135 static void cirrus_reorg (rtx);
136 static void arm_init_builtins (void);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx safe_vector_operand (rtx, enum machine_mode);
140 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
141 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
142 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 #ifdef OBJECT_FORMAT_ELF
145 static void arm_elf_asm_named_section (const char *, unsigned int);
148 static void arm_encode_section_info (tree, rtx, int);
151 static void aof_globalize_label (FILE *, const char *);
152 static void aof_dump_imports (FILE *);
153 static void aof_dump_pic_table (FILE *);
154 static void aof_file_start (void);
155 static void aof_file_end (void);
157 static rtx arm_struct_value_rtx (tree, int);
158 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
162 /* Initialize the GCC target structure. */
163 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
164 #undef TARGET_MERGE_DECL_ATTRIBUTES
165 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
168 #undef TARGET_ATTRIBUTE_TABLE
169 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
172 #undef TARGET_ASM_BYTE_OP
173 #define TARGET_ASM_BYTE_OP "\tDCB\t"
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
178 #undef TARGET_ASM_GLOBALIZE_LABEL
179 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
180 #undef TARGET_ASM_FILE_START
181 #define TARGET_ASM_FILE_START aof_file_start
182 #undef TARGET_ASM_FILE_END
183 #define TARGET_ASM_FILE_END aof_file_end
185 #undef TARGET_ASM_ALIGNED_SI_OP
186 #define TARGET_ASM_ALIGNED_SI_OP NULL
187 #undef TARGET_ASM_INTEGER
188 #define TARGET_ASM_INTEGER arm_assemble_integer
191 #undef TARGET_ASM_FUNCTION_PROLOGUE
192 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
194 #undef TARGET_ASM_FUNCTION_EPILOGUE
195 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
197 #undef TARGET_COMP_TYPE_ATTRIBUTES
198 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
200 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
201 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
203 #undef TARGET_SCHED_ADJUST_COST
204 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
206 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
207 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
209 #undef TARGET_ENCODE_SECTION_INFO
211 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
213 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
216 #undef TARGET_STRIP_NAME_ENCODING
217 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
219 #undef TARGET_ASM_INTERNAL_LABEL
220 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
222 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
223 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
225 #undef TARGET_ASM_OUTPUT_MI_THUNK
226 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
227 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
228 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
230 /* This will be overridden in arm_override_options. */
231 #undef TARGET_RTX_COSTS
232 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
233 #undef TARGET_ADDRESS_COST
234 #define TARGET_ADDRESS_COST arm_address_cost
236 #undef TARGET_MACHINE_DEPENDENT_REORG
237 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
239 #undef TARGET_INIT_BUILTINS
240 #define TARGET_INIT_BUILTINS arm_init_builtins
241 #undef TARGET_EXPAND_BUILTIN
242 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
244 #undef TARGET_PROMOTE_FUNCTION_ARGS
245 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
246 #undef TARGET_PROMOTE_PROTOTYPES
247 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
249 #undef TARGET_STRUCT_VALUE_RTX
250 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
252 #undef TARGET_SETUP_INCOMING_VARARGS
253 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
255 struct gcc_target targetm = TARGET_INITIALIZER;
257 /* Obstack for minipool constant handling. */
258 static struct obstack minipool_obstack;
259 static char * minipool_startobj;
261 /* The maximum number of insns skipped which
262 will be conditionalised if possible. */
263 static int max_insns_skipped = 5;
265 extern FILE * asm_out_file;
267 /* True if we are currently building a constant table. */
268 int making_const_table;
270 /* Define the information needed to generate branch insns. This is
271 stored from the compare operation. */
272 rtx arm_compare_op0, arm_compare_op1;
274 /* The processor for which instructions should be scheduled. */
275 enum processor_type arm_tune = arm_none;
277 /* Which floating point model to use. */
278 enum arm_fp_model arm_fp_model;
280 /* Which floating point hardware is available. */
281 enum fputype arm_fpu_arch;
283 /* Which floating point hardware to schedule for. */
284 enum fputype arm_fpu_tune;
286 /* Whether to use floating point hardware. */
287 enum float_abi_type arm_float_abi;
289 /* Which ABI to use. */
290 enum arm_abi_type arm_abi;
292 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
293 enum prog_mode_type arm_prgmode;
295 /* Set by the -mfpu=... option. */
296 const char * target_fpu_name = NULL;
298 /* Set by the -mfpe=... option. */
299 const char * target_fpe_name = NULL;
301 /* Set by the -mfloat-abi=... option. */
302 const char * target_float_abi_name = NULL;
304 /* Set by the -mabi=... option. */
305 const char * target_abi_name = NULL;
307 /* Used to parse -mstructure_size_boundary command line option. */
308 const char * structure_size_string = NULL;
309 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
311 /* Bit values used to identify processor capabilities. */
312 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
313 #define FL_ARCH3M (1 << 1) /* Extended multiply */
314 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
315 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
316 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
317 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
318 #define FL_THUMB (1 << 6) /* Thumb aware */
319 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
320 #define FL_STRONG (1 << 8) /* StrongARM */
321 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
322 #define FL_XSCALE (1 << 10) /* XScale */
323 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
324 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
325 media instructions. */
326 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
328 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
330 /* The bits in this mask specify which
331 instructions we are allowed to generate. */
332 static unsigned long insn_flags = 0;
334 /* The bits in this mask specify which instruction scheduling options should
336 static unsigned long tune_flags = 0;
338 /* The following are used in the arm.md file as equivalents to bits
339 in the above two flag variables. */
341 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
344 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
347 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
350 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
353 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
356 /* Nonzero if this chip can benefit from load scheduling. */
357 int arm_ld_sched = 0;
359 /* Nonzero if this chip is a StrongARM. */
360 int arm_is_strong = 0;
362 /* Nonzero if this chip supports Intel Wireless MMX technology. */
363 int arm_arch_iwmmxt = 0;
365 /* Nonzero if this chip is an XScale. */
366 int arm_arch_xscale = 0;
368 /* Nonzero if tuning for XScale */
369 int arm_tune_xscale = 0;
371 /* Nonzero if this chip is an ARM6 or an ARM7. */
372 int arm_is_6_or_7 = 0;
374 /* Nonzero if generating Thumb instructions. */
377 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
378 must report the mode of the memory reference from PRINT_OPERAND to
379 PRINT_OPERAND_ADDRESS. */
380 enum machine_mode output_memory_reference_mode;
382 /* The register number to be used for the PIC offset register. */
383 const char * arm_pic_register_string = NULL;
384 int arm_pic_register = INVALID_REGNUM;
386 /* Set to 1 when a return insn is output, this means that the epilogue
388 int return_used_this_function;
390 /* Set to 1 after arm_reorg has started. Reset to start at the start of
391 the next function. */
392 static int after_arm_reorg = 0;
394 /* The maximum number of insns to be used when loading a constant. */
395 static int arm_constant_limit = 3;
397 /* For an explanation of these variables, see final_prescan_insn below. */
399 enum arm_cond_code arm_current_cc;
401 int arm_target_label;
403 /* The condition codes of the ARM, and the inverse function. */
404 static const char * const arm_condition_codes[] =
406 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
407 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
410 #define streq(string1, string2) (strcmp (string1, string2) == 0)
412 /* Initialization code. */
416 const char *const name;
417 enum processor_type core;
418 const unsigned long flags;
419 bool (* rtx_costs) (rtx, int, int, int *);
422 /* Not all of these give usefully different compilation alternatives,
423 but there is no simple way of generalizing them. */
424 static const struct processors all_cores[] =
427 #define ARM_CORE(NAME, FLAGS, COSTS) \
428 {#NAME, arm_none, FLAGS, arm_##COSTS##_rtx_costs},
429 #include "arm-cores.def"
431 {NULL, arm_none, 0, NULL}
434 static const struct processors all_architectures[] =
436 /* ARM Architectures */
437 /* We don't specify rtx_costs here as it will be figured out
440 { "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL},
441 { "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL},
442 { "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL},
443 { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M , NULL},
444 { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 , NULL},
445 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
446 implementations that support it, so we will leave it out for now. */
447 { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB , NULL},
448 { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
449 { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
450 { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL},
451 { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
452 { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
453 { "ep9312", ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL},
454 {"iwmmxt", iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL},
455 { NULL, arm_none, 0 , NULL}
458 /* This is a magic structure. The 'string' field is magically filled in
459 with a pointer to the value specified by the user on the command line
460 assuming that the user has specified such a value. */
462 struct arm_cpu_select arm_select[] =
464 /* string name processors */
465 { NULL, "-mcpu=", all_cores },
466 { NULL, "-march=", all_architectures },
467 { NULL, "-mtune=", all_cores }
477 /* Available values for for -mfpu=. */
479 static const struct fpu_desc all_fpus[] =
481 {"fpa", FPUTYPE_FPA},
482 {"fpe2", FPUTYPE_FPA_EMU2},
483 {"fpe3", FPUTYPE_FPA_EMU2},
484 {"maverick", FPUTYPE_MAVERICK},
489 /* Floating point models used by the different hardware.
490 See fputype in arm.h. */
492 static const enum fputype fp_model_for_fpu[] =
494 /* No FP hardware. */
495 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
496 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
497 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
498 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
499 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
500 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
507 enum float_abi_type abi_type;
511 /* Available values for -mfloat-abi=. */
513 static const struct float_abi all_float_abis[] =
515 {"soft", ARM_FLOAT_ABI_SOFT},
516 {"softfp", ARM_FLOAT_ABI_SOFTFP},
517 {"hard", ARM_FLOAT_ABI_HARD}
524 enum arm_abi_type abi_type;
528 /* Available values for -mabi=. */
530 static const struct abi_name arm_all_abis[] =
532 {"apcs-gnu", ARM_ABI_APCS},
533 {"atpcs", ARM_ABI_ATPCS},
534 {"aapcs", ARM_ABI_AAPCS},
535 {"iwmmxt", ARM_ABI_IWMMXT}
538 /* Return the number of bits set in VALUE. */
540 bit_count (unsigned long value)
542 unsigned long count = 0;
547 value &= value - 1; /* Clear the least-significant set bit. */
553 /* Fix up any incompatible options that the user has specified.
554 This has now turned into a maze. */
556 arm_override_options (void)
560 /* Set up the flags based on the cpu/architecture selected by the user. */
561 for (i = ARRAY_SIZE (arm_select); i--;)
563 struct arm_cpu_select * ptr = arm_select + i;
565 if (ptr->string != NULL && ptr->string[0] != '\0')
567 const struct processors * sel;
569 for (sel = ptr->processors; sel->name != NULL; sel++)
570 if (streq (ptr->string, sel->name))
572 /* Determine the processor core for which we should
573 tune code-generation. */
574 if (/* -mcpu= is a sensible default. */
576 /* If -march= is used, and -mcpu= has not been used,
577 assume that we should tune for a representative
578 CPU from that architecture. */
580 /* -mtune= overrides -mcpu= and -march=. */
582 arm_tune = (enum processor_type) (sel - ptr->processors);
586 /* If we have been given an architecture and a processor
587 make sure that they are compatible. We only generate
588 a warning though, and we prefer the CPU over the
590 if (insn_flags != 0 && (insn_flags ^ sel->flags))
591 warning ("switch -mcpu=%s conflicts with -march= switch",
594 insn_flags = sel->flags;
600 if (sel->name == NULL)
601 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
605 /* If the user did not specify a processor, choose one for them. */
608 const struct processors * sel;
610 static const struct cpu_default
613 const char *const name;
617 { TARGET_CPU_arm2, "arm2" },
618 { TARGET_CPU_arm6, "arm6" },
619 { TARGET_CPU_arm610, "arm610" },
620 { TARGET_CPU_arm710, "arm710" },
621 { TARGET_CPU_arm7m, "arm7m" },
622 { TARGET_CPU_arm7500fe, "arm7500fe" },
623 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
624 { TARGET_CPU_arm8, "arm8" },
625 { TARGET_CPU_arm810, "arm810" },
626 { TARGET_CPU_arm9, "arm9" },
627 { TARGET_CPU_strongarm, "strongarm" },
628 { TARGET_CPU_xscale, "xscale" },
629 { TARGET_CPU_ep9312, "ep9312" },
630 { TARGET_CPU_iwmmxt, "iwmmxt" },
631 { TARGET_CPU_arm926ejs, "arm926ejs" },
632 { TARGET_CPU_arm1026ejs, "arm1026ejs" },
633 { TARGET_CPU_arm1136js, "arm1136js" },
634 { TARGET_CPU_arm1136jfs, "arm1136jfs" },
635 { TARGET_CPU_generic, "arm" },
638 const struct cpu_default * def;
640 /* Find the default. */
641 for (def = cpu_defaults; def->name; def++)
642 if (def->cpu == TARGET_CPU_DEFAULT)
645 /* Make sure we found the default CPU. */
646 if (def->name == NULL)
649 /* Find the default CPU's flags. */
650 for (sel = all_cores; sel->name != NULL; sel++)
651 if (streq (def->name, sel->name))
654 if (sel->name == NULL)
657 insn_flags = sel->flags;
659 /* Now check to see if the user has specified some command line
660 switch that require certain abilities from the cpu. */
663 if (TARGET_INTERWORK || TARGET_THUMB)
665 sought |= (FL_THUMB | FL_MODE32);
667 /* Force apcs-32 to be used for interworking. */
668 target_flags |= ARM_FLAG_APCS_32;
670 /* There are no ARM processors that support both APCS-26 and
671 interworking. Therefore we force FL_MODE26 to be removed
672 from insn_flags here (if it was set), so that the search
673 below will always be able to find a compatible processor. */
674 insn_flags &= ~FL_MODE26;
676 else if (!TARGET_APCS_32)
679 if (sought != 0 && ((sought & insn_flags) != sought))
681 /* Try to locate a CPU type that supports all of the abilities
682 of the default CPU, plus the extra abilities requested by
684 for (sel = all_cores; sel->name != NULL; sel++)
685 if ((sel->flags & sought) == (sought | insn_flags))
688 if (sel->name == NULL)
690 unsigned current_bit_count = 0;
691 const struct processors * best_fit = NULL;
693 /* Ideally we would like to issue an error message here
694 saying that it was not possible to find a CPU compatible
695 with the default CPU, but which also supports the command
696 line options specified by the programmer, and so they
697 ought to use the -mcpu=<name> command line option to
698 override the default CPU type.
700 Unfortunately this does not work with multilibing. We
701 need to be able to support multilibs for -mapcs-26 and for
702 -mthumb-interwork and there is no CPU that can support both
703 options. Instead if we cannot find a cpu that has both the
704 characteristics of the default cpu and the given command line
705 options we scan the array again looking for a best match. */
706 for (sel = all_cores; sel->name != NULL; sel++)
707 if ((sel->flags & sought) == sought)
711 count = bit_count (sel->flags & insn_flags);
713 if (count >= current_bit_count)
716 current_bit_count = count;
720 if (best_fit == NULL)
726 insn_flags = sel->flags;
728 if (arm_tune == arm_none)
729 arm_tune = (enum processor_type) (sel - all_cores);
732 /* The processor for which we should tune should now have been
734 if (arm_tune == arm_none)
737 tune_flags = all_cores[(int)arm_tune].flags;
738 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
740 /* Make sure that the processor choice does not conflict with any of the
741 other command line choices. */
742 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
744 /* If APCS-32 was not the default then it must have been set by the
745 user, so issue a warning message. If the user has specified
746 "-mapcs-32 -mcpu=arm2" then we loose here. */
747 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
748 warning ("target CPU does not support APCS-32" );
749 target_flags &= ~ARM_FLAG_APCS_32;
751 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
753 warning ("target CPU does not support APCS-26" );
754 target_flags |= ARM_FLAG_APCS_32;
757 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
759 warning ("target CPU does not support interworking" );
760 target_flags &= ~ARM_FLAG_INTERWORK;
763 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
765 warning ("target CPU does not support THUMB instructions");
766 target_flags &= ~ARM_FLAG_THUMB;
769 if (TARGET_APCS_FRAME && TARGET_THUMB)
771 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
772 target_flags &= ~ARM_FLAG_APCS_FRAME;
775 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
776 from here where no function is being compiled currently. */
777 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
779 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
781 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
782 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
784 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
785 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
787 /* If interworking is enabled then APCS-32 must be selected as well. */
788 if (TARGET_INTERWORK)
791 warning ("interworking forces APCS-32 to be used" );
792 target_flags |= ARM_FLAG_APCS_32;
795 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
797 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
798 target_flags |= ARM_FLAG_APCS_FRAME;
801 if (TARGET_POKE_FUNCTION_NAME)
802 target_flags |= ARM_FLAG_APCS_FRAME;
804 if (TARGET_APCS_REENT && flag_pic)
805 error ("-fpic and -mapcs-reent are incompatible");
807 if (TARGET_APCS_REENT)
808 warning ("APCS reentrant code not supported. Ignored");
810 /* If this target is normally configured to use APCS frames, warn if they
811 are turned off and debugging is turned on. */
813 && write_symbols != NO_DEBUG
814 && !TARGET_APCS_FRAME
815 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
816 warning ("-g with -mno-apcs-frame may not give sensible debugging");
818 /* If stack checking is disabled, we can use r10 as the PIC register,
819 which keeps r9 available. */
821 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
823 if (TARGET_APCS_FLOAT)
824 warning ("passing floating point arguments in fp regs not yet supported");
826 /* Initialize boolean versions of the flags, for use in the arm.md file. */
827 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
828 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
829 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
830 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
831 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
832 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
834 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
835 arm_is_strong = (tune_flags & FL_STRONG) != 0;
836 thumb_code = (TARGET_ARM == 0);
837 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
838 && !(tune_flags & FL_ARCH4))) != 0;
839 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
840 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
844 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
846 if (streq (arm_all_abis[i].name, target_abi_name))
848 arm_abi = arm_all_abis[i].abi_type;
852 if (i == ARRAY_SIZE (arm_all_abis))
853 error ("invalid ABI option: -mabi=%s", target_abi_name);
856 arm_abi = ARM_DEFAULT_ABI;
858 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
859 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
861 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
862 error ("iwmmxt abi requires an iwmmxt capable cpu");
864 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
865 if (target_fpu_name == NULL && target_fpe_name != NULL)
867 if (streq (target_fpe_name, "2"))
868 target_fpu_name = "fpe2";
869 else if (streq (target_fpe_name, "3"))
870 target_fpu_name = "fpe3";
872 error ("invalid floating point emulation option: -mfpe=%s",
875 if (target_fpu_name != NULL)
877 /* The user specified a FPU. */
878 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
880 if (streq (all_fpus[i].name, target_fpu_name))
882 arm_fpu_arch = all_fpus[i].fpu;
883 arm_fpu_tune = arm_fpu_arch;
884 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
888 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
889 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
893 #ifdef FPUTYPE_DEFAULT
894 /* Use the default is it is specified for this platform. */
895 arm_fpu_arch = FPUTYPE_DEFAULT;
896 arm_fpu_tune = FPUTYPE_DEFAULT;
898 /* Pick one based on CPU type. */
899 if ((insn_flags & FL_VFP) != 0)
900 arm_fpu_arch = FPUTYPE_VFP;
901 else if (insn_flags & FL_CIRRUS)
902 arm_fpu_arch = FPUTYPE_MAVERICK;
904 arm_fpu_arch = FPUTYPE_FPA_EMU2;
906 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
907 arm_fpu_tune = FPUTYPE_FPA;
909 arm_fpu_tune = arm_fpu_arch;
910 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
911 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
915 if (target_float_abi_name != NULL)
917 /* The user specified a FP ABI. */
918 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
920 if (streq (all_float_abis[i].name, target_float_abi_name))
922 arm_float_abi = all_float_abis[i].abi_type;
926 if (i == ARRAY_SIZE (all_float_abis))
927 error ("invalid floating point abi: -mfloat-abi=%s",
928 target_float_abi_name);
932 /* Use soft-float target flag. */
933 if (target_flags & ARM_FLAG_SOFT_FLOAT)
934 arm_float_abi = ARM_FLOAT_ABI_SOFT;
936 arm_float_abi = ARM_FLOAT_ABI_HARD;
939 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
940 sorry ("-mfloat-abi=softfp");
941 /* If soft-float is specified then don't use FPU. */
942 if (TARGET_SOFT_FLOAT)
943 arm_fpu_arch = FPUTYPE_NONE;
945 /* For arm2/3 there is no need to do any scheduling if there is only
946 a floating point emulator, or we are doing software floating-point. */
947 if ((TARGET_SOFT_FLOAT
948 || arm_fpu_tune == FPUTYPE_FPA_EMU2
949 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
950 && (tune_flags & FL_MODE32) == 0)
951 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
953 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
955 /* Override the default structure alignment for AAPCS ABI. */
956 if (arm_abi == ARM_ABI_AAPCS)
957 arm_structure_size_boundary = 8;
959 if (structure_size_string != NULL)
961 int size = strtol (structure_size_string, NULL, 0);
963 if (size == 8 || size == 32
964 || (ARM_DOUBLEWORD_ALIGN && size == 64))
965 arm_structure_size_boundary = size;
967 warning ("structure size boundary can only be set to %s",
968 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
971 if (arm_pic_register_string != NULL)
973 int pic_register = decode_reg_name (arm_pic_register_string);
976 warning ("-mpic-register= is useless without -fpic");
978 /* Prevent the user from choosing an obviously stupid PIC register. */
979 else if (pic_register < 0 || call_used_regs[pic_register]
980 || pic_register == HARD_FRAME_POINTER_REGNUM
981 || pic_register == STACK_POINTER_REGNUM
982 || pic_register >= PC_REGNUM)
983 error ("unable to use '%s' for PIC register", arm_pic_register_string);
985 arm_pic_register = pic_register;
988 if (TARGET_THUMB && flag_schedule_insns)
990 /* Don't warn since it's on by default in -O2. */
991 flag_schedule_insns = 0;
996 /* There's some dispute as to whether this should be 1 or 2. However,
997 experiments seem to show that in pathological cases a setting of
998 1 degrades less severely than a setting of 2. This could change if
999 other parts of the compiler change their behavior. */
1000 arm_constant_limit = 1;
1002 /* If optimizing for size, bump the number of instructions that we
1003 are prepared to conditionally execute (even on a StrongARM). */
1004 max_insns_skipped = 6;
1008 /* For processors with load scheduling, it never costs more than
1009 2 cycles to load a constant, and the load scheduler may well
1010 reduce that to 1. */
1011 if (tune_flags & FL_LDSCHED)
1012 arm_constant_limit = 1;
1014 /* On XScale the longer latency of a load makes it more difficult
1015 to achieve a good schedule, so it's faster to synthesize
1016 constants that can be done in two insns. */
1017 if (arm_tune_xscale)
1018 arm_constant_limit = 2;
1020 /* StrongARM has early execution of branches, so a sequence
1021 that is worth skipping is shorter. */
1023 max_insns_skipped = 3;
1026 /* Register global variables with the garbage collector. */
1027 arm_add_gc_roots ();
1031 arm_add_gc_roots (void)
1033 gcc_obstack_init(&minipool_obstack);
1034 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1037 /* A table of known ARM exception types.
1038 For use with the interrupt function attribute. */
1042 const char *const arg;
1043 const unsigned long return_value;
1047 static const isr_attribute_arg isr_attribute_args [] =
1049 { "IRQ", ARM_FT_ISR },
1050 { "irq", ARM_FT_ISR },
1051 { "FIQ", ARM_FT_FIQ },
1052 { "fiq", ARM_FT_FIQ },
1053 { "ABORT", ARM_FT_ISR },
1054 { "abort", ARM_FT_ISR },
1055 { "ABORT", ARM_FT_ISR },
1056 { "abort", ARM_FT_ISR },
1057 { "UNDEF", ARM_FT_EXCEPTION },
1058 { "undef", ARM_FT_EXCEPTION },
1059 { "SWI", ARM_FT_EXCEPTION },
1060 { "swi", ARM_FT_EXCEPTION },
1061 { NULL, ARM_FT_NORMAL }
1064 /* Returns the (interrupt) function type of the current
1065 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1067 static unsigned long
1068 arm_isr_value (tree argument)
1070 const isr_attribute_arg * ptr;
1073 /* No argument - default to IRQ. */
1074 if (argument == NULL_TREE)
1077 /* Get the value of the argument. */
1078 if (TREE_VALUE (argument) == NULL_TREE
1079 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1080 return ARM_FT_UNKNOWN;
1082 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1084 /* Check it against the list of known arguments. */
1085 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1086 if (streq (arg, ptr->arg))
1087 return ptr->return_value;
1089 /* An unrecognized interrupt type. */
1090 return ARM_FT_UNKNOWN;
1093 /* Computes the type of the current function. */
1095 static unsigned long
1096 arm_compute_func_type (void)
1098 unsigned long type = ARM_FT_UNKNOWN;
1102 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1105 /* Decide if the current function is volatile. Such functions
1106 never return, and many memory cycles can be saved by not storing
1107 register values that will never be needed again. This optimization
1108 was added to speed up context switching in a kernel application. */
1110 && current_function_nothrow
1111 && TREE_THIS_VOLATILE (current_function_decl))
1112 type |= ARM_FT_VOLATILE;
1114 if (current_function_needs_context)
1115 type |= ARM_FT_NESTED;
1117 attr = DECL_ATTRIBUTES (current_function_decl);
1119 a = lookup_attribute ("naked", attr);
1121 type |= ARM_FT_NAKED;
1123 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1124 type |= ARM_FT_EXCEPTION_HANDLER;
1127 a = lookup_attribute ("isr", attr);
1129 a = lookup_attribute ("interrupt", attr);
1132 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1134 type |= arm_isr_value (TREE_VALUE (a));
1140 /* Returns the type of the current function. */
1143 arm_current_func_type (void)
1145 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1146 cfun->machine->func_type = arm_compute_func_type ();
1148 return cfun->machine->func_type;
1151 /* Return 1 if it is possible to return using a single instruction.
1152 If SIBLING is non-null, this is a test for a return before a sibling
1153 call. SIBLING is the call insn, so we can examine its register usage. */
1156 use_return_insn (int iscond, rtx sibling)
1159 unsigned int func_type;
1160 unsigned long saved_int_regs;
1161 unsigned HOST_WIDE_INT stack_adjust;
1162 arm_stack_offsets *offsets;
1164 /* Never use a return instruction before reload has run. */
1165 if (!reload_completed)
1168 func_type = arm_current_func_type ();
1170 /* Naked functions and volatile functions need special
1172 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1175 /* So do interrupt functions that use the frame pointer. */
1176 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1179 offsets = arm_get_frame_offsets ();
1180 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1182 /* As do variadic functions. */
1183 if (current_function_pretend_args_size
1184 || cfun->machine->uses_anonymous_args
1185 /* Or if the function calls __builtin_eh_return () */
1186 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1187 /* Or if the function calls alloca */
1188 || current_function_calls_alloca
1189 /* Or if there is a stack adjustment. However, if the stack pointer
1190 is saved on the stack, we can use a pre-incrementing stack load. */
1191 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1194 saved_int_regs = arm_compute_save_reg_mask ();
1196 /* Unfortunately, the insn
1198 ldmib sp, {..., sp, ...}
1200 triggers a bug on most SA-110 based devices, such that the stack
1201 pointer won't be correctly restored if the instruction takes a
1202 page fault. We work around this problem by popping r3 along with
1203 the other registers, since that is never slower than executing
1204 another instruction.
1206 We test for !arm_arch5 here, because code for any architecture
1207 less than this could potentially be run on one of the buggy
1209 if (stack_adjust == 4 && !arm_arch5)
1211 /* Validate that r3 is a call-clobbered register (always true in
1212 the default abi) ... */
1213 if (!call_used_regs[3])
1216 /* ... that it isn't being used for a return value (always true
1217 until we implement return-in-regs), or for a tail-call
1221 if (GET_CODE (sibling) != CALL_INSN)
1224 if (find_regno_fusage (sibling, USE, 3))
1228 /* ... and that there are no call-saved registers in r0-r2
1229 (always true in the default ABI). */
1230 if (saved_int_regs & 0x7)
1234 /* Can't be done if interworking with Thumb, and any registers have been
1236 if (TARGET_INTERWORK && saved_int_regs != 0)
1239 /* On StrongARM, conditional returns are expensive if they aren't
1240 taken and multiple registers have been stacked. */
1241 if (iscond && arm_is_strong)
1243 /* Conditional return when just the LR is stored is a simple
1244 conditional-load instruction, that's not expensive. */
1245 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1248 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1252 /* If there are saved registers but the LR isn't saved, then we need
1253 two instructions for the return. */
1254 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1257 /* Can't be done if any of the FPA regs are pushed,
1258 since this also requires an insn. */
1259 if (TARGET_HARD_FLOAT && TARGET_FPA)
1260 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1261 if (regs_ever_live[regno] && !call_used_regs[regno])
1264 /* Likewise VFP regs. */
1265 if (TARGET_HARD_FLOAT && TARGET_VFP)
1266 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1267 if (regs_ever_live[regno] && !call_used_regs[regno])
1270 if (TARGET_REALLY_IWMMXT)
1271 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1272 if (regs_ever_live[regno] && ! call_used_regs [regno])
1278 /* Return TRUE if int I is a valid immediate ARM constant. */
1281 const_ok_for_arm (HOST_WIDE_INT i)
1283 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1285 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1286 be all zero, or all one. */
1287 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1288 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1289 != ((~(unsigned HOST_WIDE_INT) 0)
1290 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1293 /* Fast return for 0 and powers of 2 */
1294 if ((i & (i - 1)) == 0)
1299 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1302 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1303 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1305 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1310 /* Return true if I is a valid constant for the operation CODE. */
1312 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1314 if (const_ok_for_arm (i))
1320 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1322 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1328 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1335 /* Emit a sequence of insns to handle a large constant.
1336 CODE is the code of the operation required, it can be any of SET, PLUS,
1337 IOR, AND, XOR, MINUS;
1338 MODE is the mode in which the operation is being performed;
1339 VAL is the integer to operate on;
1340 SOURCE is the other operand (a register, or a null-pointer for SET);
1341 SUBTARGETS means it is safe to create scratch registers if that will
1342 either produce a simpler sequence, or we will want to cse the values.
1343 Return value is the number of insns emitted. */
1346 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1347 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1349 if (subtargets || code == SET
1350 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1351 && REGNO (target) != REGNO (source)))
1353 /* After arm_reorg has been called, we can't fix up expensive
1354 constants by pushing them into memory so we must synthesize
1355 them in-line, regardless of the cost. This is only likely to
1356 be more costly on chips that have load delay slots and we are
1357 compiling without running the scheduler (so no splitting
1358 occurred before the final instruction emission).
1360 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1362 if (!after_arm_reorg
1363 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1364 > arm_constant_limit + (code != SET)))
1368 /* Currently SET is the only monadic value for CODE, all
1369 the rest are diadic. */
1370 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1375 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1377 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1378 /* For MINUS, the value is subtracted from, since we never
1379 have subtraction of a constant. */
1381 emit_insn (gen_rtx_SET (VOIDmode, target,
1382 gen_rtx_MINUS (mode, temp, source)));
1384 emit_insn (gen_rtx_SET (VOIDmode, target,
1385 gen_rtx_fmt_ee (code, mode, source, temp)));
1391 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1395 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1397 HOST_WIDE_INT temp1;
1405 if (remainder & (3 << (i - 2)))
1410 temp1 = remainder & ((0x0ff << end)
1411 | ((i < end) ? (0xff >> (32 - end)) : 0));
1412 remainder &= ~temp1;
1417 } while (remainder);
1421 /* As above, but extra parameter GENERATE which, if clear, suppresses
1425 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1426 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1431 int can_negate_initial = 0;
1434 int num_bits_set = 0;
1435 int set_sign_bit_copies = 0;
1436 int clear_sign_bit_copies = 0;
1437 int clear_zero_bit_copies = 0;
1438 int set_zero_bit_copies = 0;
1440 unsigned HOST_WIDE_INT temp1, temp2;
1441 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1443 /* Find out which operations are safe for a given CODE. Also do a quick
1444 check for degenerate cases; these can occur when DImode operations
1456 can_negate_initial = 1;
1460 if (remainder == 0xffffffff)
1463 emit_insn (gen_rtx_SET (VOIDmode, target,
1464 GEN_INT (ARM_SIGN_EXTEND (val))));
1469 if (reload_completed && rtx_equal_p (target, source))
1472 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1481 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1484 if (remainder == 0xffffffff)
1486 if (reload_completed && rtx_equal_p (target, source))
1489 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1498 if (reload_completed && rtx_equal_p (target, source))
1501 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1504 if (remainder == 0xffffffff)
1507 emit_insn (gen_rtx_SET (VOIDmode, target,
1508 gen_rtx_NOT (mode, source)));
1512 /* We don't know how to handle this yet below. */
1516 /* We treat MINUS as (val - source), since (source - val) is always
1517 passed as (source + (-val)). */
1521 emit_insn (gen_rtx_SET (VOIDmode, target,
1522 gen_rtx_NEG (mode, source)));
1525 if (const_ok_for_arm (val))
1528 emit_insn (gen_rtx_SET (VOIDmode, target,
1529 gen_rtx_MINUS (mode, GEN_INT (val),
1541 /* If we can do it in one insn get out quickly. */
1542 if (const_ok_for_arm (val)
1543 || (can_negate_initial && const_ok_for_arm (-val))
1544 || (can_invert && const_ok_for_arm (~val)))
1547 emit_insn (gen_rtx_SET (VOIDmode, target,
1548 (source ? gen_rtx_fmt_ee (code, mode, source,
1554 /* Calculate a few attributes that may be useful for specific
1556 for (i = 31; i >= 0; i--)
1558 if ((remainder & (1 << i)) == 0)
1559 clear_sign_bit_copies++;
1564 for (i = 31; i >= 0; i--)
1566 if ((remainder & (1 << i)) != 0)
1567 set_sign_bit_copies++;
1572 for (i = 0; i <= 31; i++)
1574 if ((remainder & (1 << i)) == 0)
1575 clear_zero_bit_copies++;
1580 for (i = 0; i <= 31; i++)
1582 if ((remainder & (1 << i)) != 0)
1583 set_zero_bit_copies++;
1591 /* See if we can do this by sign_extending a constant that is known
1592 to be negative. This is a good, way of doing it, since the shift
1593 may well merge into a subsequent insn. */
1594 if (set_sign_bit_copies > 1)
1596 if (const_ok_for_arm
1597 (temp1 = ARM_SIGN_EXTEND (remainder
1598 << (set_sign_bit_copies - 1))))
1602 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1603 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1605 emit_insn (gen_ashrsi3 (target, new_src,
1606 GEN_INT (set_sign_bit_copies - 1)));
1610 /* For an inverted constant, we will need to set the low bits,
1611 these will be shifted out of harm's way. */
1612 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1613 if (const_ok_for_arm (~temp1))
1617 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1618 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1620 emit_insn (gen_ashrsi3 (target, new_src,
1621 GEN_INT (set_sign_bit_copies - 1)));
1627 /* See if we can generate this by setting the bottom (or the top)
1628 16 bits, and then shifting these into the other half of the
1629 word. We only look for the simplest cases, to do more would cost
1630 too much. Be careful, however, not to generate this when the
1631 alternative would take fewer insns. */
1632 if (val & 0xffff0000)
1634 temp1 = remainder & 0xffff0000;
1635 temp2 = remainder & 0x0000ffff;
1637 /* Overlaps outside this range are best done using other methods. */
1638 for (i = 9; i < 24; i++)
1640 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1641 && !const_ok_for_arm (temp2))
1643 rtx new_src = (subtargets
1644 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1646 insns = arm_gen_constant (code, mode, temp2, new_src,
1647 source, subtargets, generate);
1650 emit_insn (gen_rtx_SET
1653 gen_rtx_ASHIFT (mode, source,
1660 /* Don't duplicate cases already considered. */
1661 for (i = 17; i < 24; i++)
1663 if (((temp1 | (temp1 >> i)) == remainder)
1664 && !const_ok_for_arm (temp1))
1666 rtx new_src = (subtargets
1667 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1669 insns = arm_gen_constant (code, mode, temp1, new_src,
1670 source, subtargets, generate);
1674 (gen_rtx_SET (VOIDmode, target,
1677 gen_rtx_LSHIFTRT (mode, source,
1688 /* If we have IOR or XOR, and the constant can be loaded in a
1689 single instruction, and we can find a temporary to put it in,
1690 then this can be done in two instructions instead of 3-4. */
1692 /* TARGET can't be NULL if SUBTARGETS is 0 */
1693 || (reload_completed && !reg_mentioned_p (target, source)))
1695 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1699 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1701 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1702 emit_insn (gen_rtx_SET (VOIDmode, target,
1703 gen_rtx_fmt_ee (code, mode, source, sub)));
1712 if (set_sign_bit_copies > 8
1713 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1717 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1718 rtx shift = GEN_INT (set_sign_bit_copies);
1720 emit_insn (gen_rtx_SET (VOIDmode, sub,
1722 gen_rtx_ASHIFT (mode,
1725 emit_insn (gen_rtx_SET (VOIDmode, target,
1727 gen_rtx_LSHIFTRT (mode, sub,
1733 if (set_zero_bit_copies > 8
1734 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1738 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1739 rtx shift = GEN_INT (set_zero_bit_copies);
1741 emit_insn (gen_rtx_SET (VOIDmode, sub,
1743 gen_rtx_LSHIFTRT (mode,
1746 emit_insn (gen_rtx_SET (VOIDmode, target,
1748 gen_rtx_ASHIFT (mode, sub,
1754 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1758 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1759 emit_insn (gen_rtx_SET (VOIDmode, sub,
1760 gen_rtx_NOT (mode, source)));
1763 sub = gen_reg_rtx (mode);
1764 emit_insn (gen_rtx_SET (VOIDmode, sub,
1765 gen_rtx_AND (mode, source,
1767 emit_insn (gen_rtx_SET (VOIDmode, target,
1768 gen_rtx_NOT (mode, sub)));
1775 /* See if two shifts will do 2 or more insn's worth of work. */
1776 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1778 HOST_WIDE_INT shift_mask = ((0xffffffff
1779 << (32 - clear_sign_bit_copies))
1782 if ((remainder | shift_mask) != 0xffffffff)
1786 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1787 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1788 new_src, source, subtargets, 1);
1793 rtx targ = subtargets ? NULL_RTX : target;
1794 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1795 targ, source, subtargets, 0);
1801 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1802 rtx shift = GEN_INT (clear_sign_bit_copies);
1804 emit_insn (gen_ashlsi3 (new_src, source, shift));
1805 emit_insn (gen_lshrsi3 (target, new_src, shift));
1811 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1813 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1815 if ((remainder | shift_mask) != 0xffffffff)
1819 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1821 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1822 new_src, source, subtargets, 1);
1827 rtx targ = subtargets ? NULL_RTX : target;
1829 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1830 targ, source, subtargets, 0);
1836 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1837 rtx shift = GEN_INT (clear_zero_bit_copies);
1839 emit_insn (gen_lshrsi3 (new_src, source, shift));
1840 emit_insn (gen_ashlsi3 (target, new_src, shift));
1852 for (i = 0; i < 32; i++)
1853 if (remainder & (1 << i))
1856 if (code == AND || (can_invert && num_bits_set > 16))
1857 remainder = (~remainder) & 0xffffffff;
1858 else if (code == PLUS && num_bits_set > 16)
1859 remainder = (-remainder) & 0xffffffff;
1866 /* Now try and find a way of doing the job in either two or three
1868 We start by looking for the largest block of zeros that are aligned on
1869 a 2-bit boundary, we then fill up the temps, wrapping around to the
1870 top of the word when we drop off the bottom.
1871 In the worst case this code should produce no more than four insns. */
1874 int best_consecutive_zeros = 0;
1876 for (i = 0; i < 32; i += 2)
1878 int consecutive_zeros = 0;
1880 if (!(remainder & (3 << i)))
1882 while ((i < 32) && !(remainder & (3 << i)))
1884 consecutive_zeros += 2;
1887 if (consecutive_zeros > best_consecutive_zeros)
1889 best_consecutive_zeros = consecutive_zeros;
1890 best_start = i - consecutive_zeros;
1896 /* So long as it won't require any more insns to do so, it's
1897 desirable to emit a small constant (in bits 0...9) in the last
1898 insn. This way there is more chance that it can be combined with
1899 a later addressing insn to form a pre-indexed load or store
1900 operation. Consider:
1902 *((volatile int *)0xe0000100) = 1;
1903 *((volatile int *)0xe0000110) = 2;
1905 We want this to wind up as:
1909 str rB, [rA, #0x100]
1911 str rB, [rA, #0x110]
1913 rather than having to synthesize both large constants from scratch.
1915 Therefore, we calculate how many insns would be required to emit
1916 the constant starting from `best_start', and also starting from
1917 zero (ie with bit 31 first to be output). If `best_start' doesn't
1918 yield a shorter sequence, we may as well use zero. */
1920 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1921 && (count_insns_for_constant (remainder, 0) <=
1922 count_insns_for_constant (remainder, best_start)))
1925 /* Now start emitting the insns. */
1933 if (remainder & (3 << (i - 2)))
1938 temp1 = remainder & ((0x0ff << end)
1939 | ((i < end) ? (0xff >> (32 - end)) : 0));
1940 remainder &= ~temp1;
1944 rtx new_src, temp1_rtx;
1946 if (code == SET || code == MINUS)
1948 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1949 if (can_invert && code != MINUS)
1954 if (remainder && subtargets)
1955 new_src = gen_reg_rtx (mode);
1960 else if (can_negate)
1964 temp1 = trunc_int_for_mode (temp1, mode);
1965 temp1_rtx = GEN_INT (temp1);
1969 else if (code == MINUS)
1970 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1972 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1974 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1983 else if (code == MINUS)
1997 /* Canonicalize a comparison so that we are more likely to recognize it.
1998 This can be done for a few constant compares, where we can make the
1999 immediate value easier to load. */
2002 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2004 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2014 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2015 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2017 *op1 = GEN_INT (i + 1);
2018 return code == GT ? GE : LT;
2024 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2025 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2027 *op1 = GEN_INT (i - 1);
2028 return code == GE ? GT : LE;
2034 if (i != ~((unsigned HOST_WIDE_INT) 0)
2035 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2037 *op1 = GEN_INT (i + 1);
2038 return code == GTU ? GEU : LTU;
2045 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2047 *op1 = GEN_INT (i - 1);
2048 return code == GEU ? GTU : LEU;
2059 /* Decide whether a type should be returned in memory (true)
2060 or in a register (false). This is called by the macro
2061 RETURN_IN_MEMORY. */
2063 arm_return_in_memory (tree type)
2067 if (!AGGREGATE_TYPE_P (type))
2068 /* All simple types are returned in registers. */
2071 size = int_size_in_bytes (type);
2073 if (arm_abi != ARM_ABI_APCS)
2075 /* ATPCS and later return aggregate types in memory only if they are
2076 larger than a word (or are variable size). */
2077 return (size < 0 || size > UNITS_PER_WORD);
2080 /* For the arm-wince targets we choose to be compatible with Microsoft's
2081 ARM and Thumb compilers, which always return aggregates in memory. */
2083 /* All structures/unions bigger than one word are returned in memory.
2084 Also catch the case where int_size_in_bytes returns -1. In this case
2085 the aggregate is either huge or of variable size, and in either case
2086 we will want to return it via memory and not in a register. */
2087 if (size < 0 || size > UNITS_PER_WORD)
2090 if (TREE_CODE (type) == RECORD_TYPE)
2094 /* For a struct the APCS says that we only return in a register
2095 if the type is 'integer like' and every addressable element
2096 has an offset of zero. For practical purposes this means
2097 that the structure can have at most one non bit-field element
2098 and that this element must be the first one in the structure. */
2100 /* Find the first field, ignoring non FIELD_DECL things which will
2101 have been created by C++. */
2102 for (field = TYPE_FIELDS (type);
2103 field && TREE_CODE (field) != FIELD_DECL;
2104 field = TREE_CHAIN (field))
2108 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2110 /* Check that the first field is valid for returning in a register. */
2112 /* ... Floats are not allowed */
2113 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2116 /* ... Aggregates that are not themselves valid for returning in
2117 a register are not allowed. */
2118 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2121 /* Now check the remaining fields, if any. Only bitfields are allowed,
2122 since they are not addressable. */
2123 for (field = TREE_CHAIN (field);
2125 field = TREE_CHAIN (field))
2127 if (TREE_CODE (field) != FIELD_DECL)
2130 if (!DECL_BIT_FIELD_TYPE (field))
2137 if (TREE_CODE (type) == UNION_TYPE)
2141 /* Unions can be returned in registers if every element is
2142 integral, or can be returned in an integer register. */
2143 for (field = TYPE_FIELDS (type);
2145 field = TREE_CHAIN (field))
2147 if (TREE_CODE (field) != FIELD_DECL)
2150 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2153 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2159 #endif /* not ARM_WINCE */
2161 /* Return all other types in memory. */
2165 /* Indicate whether or not words of a double are in big-endian order. */
2168 arm_float_words_big_endian (void)
2170 if (TARGET_MAVERICK)
2173 /* For FPA, float words are always big-endian. For VFP, floats words
2174 follow the memory system mode. */
2182 return (TARGET_BIG_END ? 1 : 0);
2187 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2188 for a call to a function whose data type is FNTYPE.
2189 For a library call, FNTYPE is NULL. */
2191 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2192 rtx libname ATTRIBUTE_UNUSED,
2193 tree fndecl ATTRIBUTE_UNUSED)
2195 /* On the ARM, the offset starts at 0. */
2196 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2197 pcum->iwmmxt_nregs = 0;
2198 pcum->can_split = true;
2200 pcum->call_cookie = CALL_NORMAL;
2202 if (TARGET_LONG_CALLS)
2203 pcum->call_cookie = CALL_LONG;
2205 /* Check for long call/short call attributes. The attributes
2206 override any command line option. */
2209 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2210 pcum->call_cookie = CALL_SHORT;
2211 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2212 pcum->call_cookie = CALL_LONG;
2215 /* Varargs vectors are treated the same as long long.
2216 named_count avoids having to change the way arm handles 'named' */
2217 pcum->named_count = 0;
2220 if (TARGET_REALLY_IWMMXT && fntype)
2224 for (fn_arg = TYPE_ARG_TYPES (fntype);
2226 fn_arg = TREE_CHAIN (fn_arg))
2227 pcum->named_count += 1;
2229 if (! pcum->named_count)
2230 pcum->named_count = INT_MAX;
2235 /* Return true if mode/type need doubleword alignment. */
2237 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2239 return (mode == DImode
2241 || VECTOR_MODE_SUPPORTED_P (mode)
2243 && TYPE_ALIGN (type) > PARM_BOUNDARY));
2247 /* Determine where to put an argument to a function.
2248 Value is zero to push the argument on the stack,
2249 or a hard register in which to store the argument.
2251 MODE is the argument's machine mode.
2252 TYPE is the data type of the argument (as a tree).
2253 This is null for libcalls where that information may
2255 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2256 the preceding args and about the function being called.
2257 NAMED is nonzero if this argument is a named parameter
2258 (otherwise it is an extra parameter matching an ellipsis). */
2261 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2262 tree type, int named)
2266 /* Varargs vectors are treated the same as long long.
2267 named_count avoids having to change the way arm handles 'named' */
2268 if (TARGET_IWMMXT_ABI
2269 && VECTOR_MODE_SUPPORTED_P (mode)
2270 && pcum->named_count > pcum->nargs + 1)
2272 if (pcum->iwmmxt_nregs <= 9)
2273 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2276 pcum->can_split = false;
2281 /* Put doubleword aligned quantities in even register pairs. */
2283 && ARM_DOUBLEWORD_ALIGN
2284 && arm_needs_doubleword_align (mode, type))
2287 if (mode == VOIDmode)
2288 /* Compute operand 2 of the call insn. */
2289 return GEN_INT (pcum->call_cookie);
2291 /* Only allow splitting an arg between regs and memory if all preceding
2292 args were allocated to regs. For args passed by reference we only count
2293 the reference pointer. */
2294 if (pcum->can_split)
2297 nregs = ARM_NUM_REGS2 (mode, type);
2299 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2302 return gen_rtx_REG (mode, pcum->nregs);
2305 /* Variable sized types are passed by reference. This is a GCC
2306 extension to the ARM ABI. */
2309 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2310 enum machine_mode mode ATTRIBUTE_UNUSED,
2311 tree type, int named ATTRIBUTE_UNUSED)
2313 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2316 /* Implement va_arg. */
2319 arm_va_arg (tree valist, tree type)
2323 /* Variable sized types are passed by reference. */
2324 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2326 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2327 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2330 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2331 if (align > PARM_BOUNDARY)
2336 /* Maintain 64-bit alignment of the valist pointer by
2337 constructing: valist = ((valist + (8 - 1)) & -8). */
2338 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2339 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2340 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2341 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2342 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2343 TREE_SIDE_EFFECTS (t) = 1;
2344 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2346 /* This is to stop the combine pass optimizing
2347 away the alignment adjustment. */
2348 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2351 return std_expand_builtin_va_arg (valist, type);
2354 /* Encode the current state of the #pragma [no_]long_calls. */
2357 OFF, /* No #pramgma [no_]long_calls is in effect. */
2358 LONG, /* #pragma long_calls is in effect. */
2359 SHORT /* #pragma no_long_calls is in effect. */
2362 static arm_pragma_enum arm_pragma_long_calls = OFF;
2365 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2367 arm_pragma_long_calls = LONG;
2371 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2373 arm_pragma_long_calls = SHORT;
2377 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2379 arm_pragma_long_calls = OFF;
2382 /* Table of machine attributes. */
2383 const struct attribute_spec arm_attribute_table[] =
2385 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2386 /* Function calls made to this symbol must be done indirectly, because
2387 it may lie outside of the 26 bit addressing range of a normal function
2389 { "long_call", 0, 0, false, true, true, NULL },
2390 /* Whereas these functions are always known to reside within the 26 bit
2391 addressing range. */
2392 { "short_call", 0, 0, false, true, true, NULL },
2393 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2394 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2395 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2396 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2398 /* ARM/PE has three new attributes:
2400 dllexport - for exporting a function/variable that will live in a dll
2401 dllimport - for importing a function/variable from a dll
2403 Microsoft allows multiple declspecs in one __declspec, separating
2404 them with spaces. We do NOT support this. Instead, use __declspec
2407 { "dllimport", 0, 0, true, false, false, NULL },
2408 { "dllexport", 0, 0, true, false, false, NULL },
2409 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2411 { NULL, 0, 0, false, false, false, NULL }
2414 /* Handle an attribute requiring a FUNCTION_DECL;
2415 arguments as in struct attribute_spec.handler. */
2417 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2418 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2420 if (TREE_CODE (*node) != FUNCTION_DECL)
2422 warning ("`%s' attribute only applies to functions",
2423 IDENTIFIER_POINTER (name));
2424 *no_add_attrs = true;
2430 /* Handle an "interrupt" or "isr" attribute;
2431 arguments as in struct attribute_spec.handler. */
2433 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2438 if (TREE_CODE (*node) != FUNCTION_DECL)
2440 warning ("`%s' attribute only applies to functions",
2441 IDENTIFIER_POINTER (name));
2442 *no_add_attrs = true;
2444 /* FIXME: the argument if any is checked for type attributes;
2445 should it be checked for decl ones? */
2449 if (TREE_CODE (*node) == FUNCTION_TYPE
2450 || TREE_CODE (*node) == METHOD_TYPE)
2452 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2454 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2455 *no_add_attrs = true;
2458 else if (TREE_CODE (*node) == POINTER_TYPE
2459 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2460 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2461 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2463 *node = build_type_copy (*node);
2464 TREE_TYPE (*node) = build_type_attribute_variant
2466 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2467 *no_add_attrs = true;
2471 /* Possibly pass this attribute on from the type to a decl. */
2472 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2473 | (int) ATTR_FLAG_FUNCTION_NEXT
2474 | (int) ATTR_FLAG_ARRAY_NEXT))
2476 *no_add_attrs = true;
2477 return tree_cons (name, args, NULL_TREE);
2481 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2489 /* Return 0 if the attributes for two types are incompatible, 1 if they
2490 are compatible, and 2 if they are nearly compatible (which causes a
2491 warning to be generated). */
2493 arm_comp_type_attributes (tree type1, tree type2)
2497 /* Check for mismatch of non-default calling convention. */
2498 if (TREE_CODE (type1) != FUNCTION_TYPE)
2501 /* Check for mismatched call attributes. */
2502 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2503 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2504 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2505 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2507 /* Only bother to check if an attribute is defined. */
2508 if (l1 | l2 | s1 | s2)
2510 /* If one type has an attribute, the other must have the same attribute. */
2511 if ((l1 != l2) || (s1 != s2))
2514 /* Disallow mixed attributes. */
2515 if ((l1 & s2) || (l2 & s1))
2519 /* Check for mismatched ISR attribute. */
2520 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2522 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2523 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2525 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2532 /* Encode long_call or short_call attribute by prefixing
2533 symbol name in DECL with a special character FLAG. */
2535 arm_encode_call_attribute (tree decl, int flag)
2537 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2538 int len = strlen (str);
2541 /* Do not allow weak functions to be treated as short call. */
2542 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2545 newstr = alloca (len + 2);
2547 strcpy (newstr + 1, str);
2549 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2550 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2553 /* Assigns default attributes to newly defined type. This is used to
2554 set short_call/long_call attributes for function types of
2555 functions defined inside corresponding #pragma scopes. */
2557 arm_set_default_type_attributes (tree type)
2559 /* Add __attribute__ ((long_call)) to all functions, when
2560 inside #pragma long_calls or __attribute__ ((short_call)),
2561 when inside #pragma no_long_calls. */
2562 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2564 tree type_attr_list, attr_name;
2565 type_attr_list = TYPE_ATTRIBUTES (type);
2567 if (arm_pragma_long_calls == LONG)
2568 attr_name = get_identifier ("long_call");
2569 else if (arm_pragma_long_calls == SHORT)
2570 attr_name = get_identifier ("short_call");
2574 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2575 TYPE_ATTRIBUTES (type) = type_attr_list;
2579 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2580 defined within the current compilation unit. If this cannot be
2581 determined, then 0 is returned. */
2583 current_file_function_operand (rtx sym_ref)
2585 /* This is a bit of a fib. A function will have a short call flag
2586 applied to its name if it has the short call attribute, or it has
2587 already been defined within the current compilation unit. */
2588 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2591 /* The current function is always defined within the current compilation
2592 unit. if it s a weak definition however, then this may not be the real
2593 definition of the function, and so we have to say no. */
2594 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2595 && !DECL_WEAK (current_function_decl))
2598 /* We cannot make the determination - default to returning 0. */
2602 /* Return nonzero if a 32 bit "long_call" should be generated for
2603 this call. We generate a long_call if the function:
2605 a. has an __attribute__((long call))
2606 or b. is within the scope of a #pragma long_calls
2607 or c. the -mlong-calls command line switch has been specified
2609 However we do not generate a long call if the function:
2611 d. has an __attribute__ ((short_call))
2612 or e. is inside the scope of a #pragma no_long_calls
2613 or f. has an __attribute__ ((section))
2614 or g. is defined within the current compilation unit.
2616 This function will be called by C fragments contained in the machine
2617 description file. CALL_REF and CALL_COOKIE correspond to the matched
2618 rtl operands. CALL_SYMBOL is used to distinguish between
2619 two different callers of the function. It is set to 1 in the
2620 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2621 and "call_value" patterns. This is because of the difference in the
2622 SYM_REFs passed by these patterns. */
2624 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2628 if (GET_CODE (sym_ref) != MEM)
2631 sym_ref = XEXP (sym_ref, 0);
2634 if (GET_CODE (sym_ref) != SYMBOL_REF)
2637 if (call_cookie & CALL_SHORT)
2640 if (TARGET_LONG_CALLS && flag_function_sections)
2643 if (current_file_function_operand (sym_ref))
2646 return (call_cookie & CALL_LONG)
2647 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2648 || TARGET_LONG_CALLS;
2651 /* Return nonzero if it is ok to make a tail-call to DECL. */
2653 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2655 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2657 if (cfun->machine->sibcall_blocked)
2660 /* Never tailcall something for which we have no decl, or if we
2661 are in Thumb mode. */
2662 if (decl == NULL || TARGET_THUMB)
2665 /* Get the calling method. */
2666 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2667 call_type = CALL_SHORT;
2668 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2669 call_type = CALL_LONG;
2671 /* Cannot tail-call to long calls, since these are out of range of
2672 a branch instruction. However, if not compiling PIC, we know
2673 we can reach the symbol if it is in this compilation unit. */
2674 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2677 /* If we are interworking and the function is not declared static
2678 then we can't tail-call it unless we know that it exists in this
2679 compilation unit (since it might be a Thumb routine). */
2680 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2683 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2684 if (IS_INTERRUPT (arm_current_func_type ()))
2687 /* Everything else is ok. */
2692 /* Addressing mode support functions. */
2694 /* Return nonzero if X is a legitimate immediate operand when compiling
2697 legitimate_pic_operand_p (rtx x)
2701 && (GET_CODE (x) == SYMBOL_REF
2702 || (GET_CODE (x) == CONST
2703 && GET_CODE (XEXP (x, 0)) == PLUS
2704 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2711 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2713 if (GET_CODE (orig) == SYMBOL_REF
2714 || GET_CODE (orig) == LABEL_REF)
2716 #ifndef AOF_ASSEMBLER
2717 rtx pic_ref, address;
2727 reg = gen_reg_rtx (Pmode);
2732 #ifdef AOF_ASSEMBLER
2733 /* The AOF assembler can generate relocations for these directly, and
2734 understands that the PIC register has to be added into the offset. */
2735 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2738 address = gen_reg_rtx (Pmode);
2743 emit_insn (gen_pic_load_addr_arm (address, orig));
2745 emit_insn (gen_pic_load_addr_thumb (address, orig));
2747 if ((GET_CODE (orig) == LABEL_REF
2748 || (GET_CODE (orig) == SYMBOL_REF &&
2749 SYMBOL_REF_LOCAL_P (orig)))
2751 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2754 pic_ref = gen_rtx_MEM (Pmode,
2755 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2757 RTX_UNCHANGING_P (pic_ref) = 1;
2760 insn = emit_move_insn (reg, pic_ref);
2762 current_function_uses_pic_offset_table = 1;
2763 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2765 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2769 else if (GET_CODE (orig) == CONST)
2773 if (GET_CODE (XEXP (orig, 0)) == PLUS
2774 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2782 reg = gen_reg_rtx (Pmode);
2785 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2787 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2788 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2789 base == reg ? 0 : reg);
2794 if (GET_CODE (offset) == CONST_INT)
2796 /* The base register doesn't really matter, we only want to
2797 test the index for the appropriate mode. */
2798 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2800 if (!no_new_pseudos)
2801 offset = force_reg (Pmode, offset);
2806 if (GET_CODE (offset) == CONST_INT)
2807 return plus_constant (base, INTVAL (offset));
2810 if (GET_MODE_SIZE (mode) > 4
2811 && (GET_MODE_CLASS (mode) == MODE_INT
2812 || TARGET_SOFT_FLOAT))
2814 emit_insn (gen_addsi3 (reg, base, offset));
2818 return gen_rtx_PLUS (Pmode, base, offset);
2824 /* Generate code to load the PIC register. PROLOGUE is true if
2825 called from arm_expand_prologue (in which case we want the
2826 generated insns at the start of the function); false if called
2827 by an exception receiver that needs the PIC register reloaded
2828 (in which case the insns are just dumped at the current location). */
2830 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2832 #ifndef AOF_ASSEMBLER
2833 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2834 rtx global_offset_table;
2836 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2843 l1 = gen_label_rtx ();
2845 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2846 /* On the ARM the PC register contains 'dot + 8' at the time of the
2847 addition, on the Thumb it is 'dot + 4'. */
2848 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2850 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2851 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2853 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2855 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2859 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2860 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2864 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2865 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2871 emit_insn_after (seq, get_insns ());
2875 /* Need to emit this whether or not we obey regdecls,
2876 since setjmp/longjmp can cause life info to screw up. */
2877 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2878 #endif /* AOF_ASSEMBLER */
2881 /* Return nonzero if X is valid as an ARM state addressing register. */
2883 arm_address_register_rtx_p (rtx x, int strict_p)
2887 if (GET_CODE (x) != REG)
2893 return ARM_REGNO_OK_FOR_BASE_P (regno);
2895 return (regno <= LAST_ARM_REGNUM
2896 || regno >= FIRST_PSEUDO_REGISTER
2897 || regno == FRAME_POINTER_REGNUM
2898 || regno == ARG_POINTER_REGNUM);
2901 /* Return nonzero if X is a valid ARM state address operand. */
2903 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2906 if (arm_address_register_rtx_p (x, strict_p))
2909 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2910 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2912 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2913 && GET_MODE_SIZE (mode) <= 4
2914 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2915 && GET_CODE (XEXP (x, 1)) == PLUS
2916 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2917 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), outer,
2920 /* After reload constants split into minipools will have addresses
2921 from a LABEL_REF. */
2922 else if (reload_completed
2923 && (GET_CODE (x) == LABEL_REF
2924 || (GET_CODE (x) == CONST
2925 && GET_CODE (XEXP (x, 0)) == PLUS
2926 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2930 else if (mode == TImode)
2933 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2935 if (GET_CODE (x) == PLUS
2936 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2937 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2939 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2941 if (val == 4 || val == -4 || val == -8)
2946 else if (TARGET_HARD_FLOAT && TARGET_VFP && mode == DFmode)
2948 if (GET_CODE (x) == PLUS
2949 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2950 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2952 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2954 /* ??? valid arm offsets are a subset of VFP offsets.
2955 For now only allow this subset. Proper fix is to add an
2956 additional memory constraint for arm address modes.
2957 Alternatively allow full vfp addressing and let
2958 output_move_double fix it up with a sub-optimal sequence. */
2959 if (val == 4 || val == -4 || val == -8)
2964 else if (GET_CODE (x) == PLUS)
2966 rtx xop0 = XEXP (x, 0);
2967 rtx xop1 = XEXP (x, 1);
2969 return ((arm_address_register_rtx_p (xop0, strict_p)
2970 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
2971 || (arm_address_register_rtx_p (xop1, strict_p)
2972 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
2976 /* Reload currently can't handle MINUS, so disable this for now */
2977 else if (GET_CODE (x) == MINUS)
2979 rtx xop0 = XEXP (x, 0);
2980 rtx xop1 = XEXP (x, 1);
2982 return (arm_address_register_rtx_p (xop0, strict_p)
2983 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
2987 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2988 && GET_CODE (x) == SYMBOL_REF
2989 && CONSTANT_POOL_ADDRESS_P (x)
2991 && symbol_mentioned_p (get_pool_constant (x))))
2994 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2995 && (GET_MODE_SIZE (mode) <= 4)
2996 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
3002 /* Return nonzero if INDEX is valid for an address index operand in
3005 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3008 HOST_WIDE_INT range;
3009 enum rtx_code code = GET_CODE (index);
3011 if (TARGET_HARD_FLOAT && TARGET_FPA && GET_MODE_CLASS (mode) == MODE_FLOAT)
3012 return (code == CONST_INT && INTVAL (index) < 1024
3013 && INTVAL (index) > -1024
3014 && (INTVAL (index) & 3) == 0);
3016 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
3017 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
3018 return (code == CONST_INT
3019 && INTVAL (index) < 255
3020 && INTVAL (index) > -255);
3022 if (arm_address_register_rtx_p (index, strict_p)
3023 && GET_MODE_SIZE (mode) <= 4)
3026 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3027 return (code == CONST_INT
3028 && INTVAL (index) < 256
3029 && INTVAL (index) > -256);
3031 if (GET_MODE_SIZE (mode) <= 4
3034 || (mode == QImode && outer == SIGN_EXTEND))))
3038 rtx xiop0 = XEXP (index, 0);
3039 rtx xiop1 = XEXP (index, 1);
3041 return ((arm_address_register_rtx_p (xiop0, strict_p)
3042 && power_of_two_operand (xiop1, SImode))
3043 || (arm_address_register_rtx_p (xiop1, strict_p)
3044 && power_of_two_operand (xiop0, SImode)));
3046 else if (code == LSHIFTRT || code == ASHIFTRT
3047 || code == ASHIFT || code == ROTATERT)
3049 rtx op = XEXP (index, 1);
3051 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3052 && GET_CODE (op) == CONST_INT
3054 && INTVAL (op) <= 31);
3058 /* For ARM v4 we may be doing a sign-extend operation during the
3062 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3068 range = (mode == HImode) ? 4095 : 4096;
3070 return (code == CONST_INT
3071 && INTVAL (index) < range
3072 && INTVAL (index) > -range);
3075 /* Return nonzero if X is valid as a Thumb state base register. */
3077 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3081 if (GET_CODE (x) != REG)
3087 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3089 return (regno <= LAST_LO_REGNUM
3090 || regno > LAST_VIRTUAL_REGISTER
3091 || regno == FRAME_POINTER_REGNUM
3092 || (GET_MODE_SIZE (mode) >= 4
3093 && (regno == STACK_POINTER_REGNUM
3094 || regno >= FIRST_PSEUDO_REGISTER
3095 || x == hard_frame_pointer_rtx
3096 || x == arg_pointer_rtx)));
3099 /* Return nonzero if x is a legitimate index register. This is the case
3100 for any base register that can access a QImode object. */
3102 thumb_index_register_rtx_p (rtx x, int strict_p)
3104 return thumb_base_register_rtx_p (x, QImode, strict_p);
3107 /* Return nonzero if x is a legitimate Thumb-state address.
3109 The AP may be eliminated to either the SP or the FP, so we use the
3110 least common denominator, e.g. SImode, and offsets from 0 to 64.
3112 ??? Verify whether the above is the right approach.
3114 ??? Also, the FP may be eliminated to the SP, so perhaps that
3115 needs special handling also.
3117 ??? Look at how the mips16 port solves this problem. It probably uses
3118 better ways to solve some of these problems.
3120 Although it is not incorrect, we don't accept QImode and HImode
3121 addresses based on the frame pointer or arg pointer until the
3122 reload pass starts. This is so that eliminating such addresses
3123 into stack based ones won't produce impossible code. */
3125 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3127 /* ??? Not clear if this is right. Experiment. */
3128 if (GET_MODE_SIZE (mode) < 4
3129 && !(reload_in_progress || reload_completed)
3130 && (reg_mentioned_p (frame_pointer_rtx, x)
3131 || reg_mentioned_p (arg_pointer_rtx, x)
3132 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3133 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3134 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3135 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3138 /* Accept any base register. SP only in SImode or larger. */
3139 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3142 /* This is PC relative data before arm_reorg runs. */
3143 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3144 && GET_CODE (x) == SYMBOL_REF
3145 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3148 /* This is PC relative data after arm_reorg runs. */
3149 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3150 && (GET_CODE (x) == LABEL_REF
3151 || (GET_CODE (x) == CONST
3152 && GET_CODE (XEXP (x, 0)) == PLUS
3153 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3157 /* Post-inc indexing only supported for SImode and larger. */
3158 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3159 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3162 else if (GET_CODE (x) == PLUS)
3164 /* REG+REG address can be any two index registers. */
3165 /* We disallow FRAME+REG addressing since we know that FRAME
3166 will be replaced with STACK, and SP relative addressing only
3167 permits SP+OFFSET. */
3168 if (GET_MODE_SIZE (mode) <= 4
3169 && XEXP (x, 0) != frame_pointer_rtx
3170 && XEXP (x, 1) != frame_pointer_rtx
3171 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3172 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3175 /* REG+const has 5-7 bit offset for non-SP registers. */
3176 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3177 || XEXP (x, 0) == arg_pointer_rtx)
3178 && GET_CODE (XEXP (x, 1)) == CONST_INT
3179 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3182 /* REG+const has 10 bit offset for SP, but only SImode and
3183 larger is supported. */
3184 /* ??? Should probably check for DI/DFmode overflow here
3185 just like GO_IF_LEGITIMATE_OFFSET does. */
3186 else if (GET_CODE (XEXP (x, 0)) == REG
3187 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3188 && GET_MODE_SIZE (mode) >= 4
3189 && GET_CODE (XEXP (x, 1)) == CONST_INT
3190 && INTVAL (XEXP (x, 1)) >= 0
3191 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3192 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3195 else if (GET_CODE (XEXP (x, 0)) == REG
3196 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3197 && GET_MODE_SIZE (mode) >= 4
3198 && GET_CODE (XEXP (x, 1)) == CONST_INT
3199 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3203 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3204 && GET_MODE_SIZE (mode) == 4
3205 && GET_CODE (x) == SYMBOL_REF
3206 && CONSTANT_POOL_ADDRESS_P (x)
3208 && symbol_mentioned_p (get_pool_constant (x))))
3214 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3215 instruction of mode MODE. */
3217 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3219 switch (GET_MODE_SIZE (mode))
3222 return val >= 0 && val < 32;
3225 return val >= 0 && val < 64 && (val & 1) == 0;
3229 && (val + GET_MODE_SIZE (mode)) <= 128
3234 /* Try machine-dependent ways of modifying an illegitimate address
3235 to be legitimate. If we find one, return the new, valid address. */
3237 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3239 if (GET_CODE (x) == PLUS)
3241 rtx xop0 = XEXP (x, 0);
3242 rtx xop1 = XEXP (x, 1);
3244 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3245 xop0 = force_reg (SImode, xop0);
3247 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3248 xop1 = force_reg (SImode, xop1);
3250 if (ARM_BASE_REGISTER_RTX_P (xop0)
3251 && GET_CODE (xop1) == CONST_INT)
3253 HOST_WIDE_INT n, low_n;
3257 /* VFP addressing modes actually allow greater offsets, but for
3258 now we just stick with the lowest common denominator. */
3260 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3272 low_n = ((mode) == TImode ? 0
3273 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3277 base_reg = gen_reg_rtx (SImode);
3278 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3279 GEN_INT (n)), NULL_RTX);
3280 emit_move_insn (base_reg, val);
3281 x = (low_n == 0 ? base_reg
3282 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3284 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3285 x = gen_rtx_PLUS (SImode, xop0, xop1);
3288 /* XXX We don't allow MINUS any more -- see comment in
3289 arm_legitimate_address_p (). */
3290 else if (GET_CODE (x) == MINUS)
3292 rtx xop0 = XEXP (x, 0);
3293 rtx xop1 = XEXP (x, 1);
3295 if (CONSTANT_P (xop0))
3296 xop0 = force_reg (SImode, xop0);
3298 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3299 xop1 = force_reg (SImode, xop1);
3301 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3302 x = gen_rtx_MINUS (SImode, xop0, xop1);
3307 /* We need to find and carefully transform any SYMBOL and LABEL
3308 references; so go back to the original address expression. */
3309 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3311 if (new_x != orig_x)
3319 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3320 to be legitimate. If we find one, return the new, valid address. */
3322 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3324 if (GET_CODE (x) == PLUS
3325 && GET_CODE (XEXP (x, 1)) == CONST_INT
3326 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3327 || INTVAL (XEXP (x, 1)) < 0))
3329 rtx xop0 = XEXP (x, 0);
3330 rtx xop1 = XEXP (x, 1);
3331 HOST_WIDE_INT offset = INTVAL (xop1);
3333 /* Try and fold the offset into a biasing of the base register and
3334 then offsetting that. Don't do this when optimizing for space
3335 since it can cause too many CSEs. */
3336 if (optimize_size && offset >= 0
3337 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3339 HOST_WIDE_INT delta;
3342 delta = offset - (256 - GET_MODE_SIZE (mode));
3343 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3344 delta = 31 * GET_MODE_SIZE (mode);
3346 delta = offset & (~31 * GET_MODE_SIZE (mode));
3348 xop0 = force_operand (plus_constant (xop0, offset - delta),
3350 x = plus_constant (xop0, delta);
3352 else if (offset < 0 && offset > -256)
3353 /* Small negative offsets are best done with a subtract before the
3354 dereference, forcing these into a register normally takes two
3356 x = force_operand (x, NULL_RTX);
3359 /* For the remaining cases, force the constant into a register. */
3360 xop1 = force_reg (SImode, xop1);
3361 x = gen_rtx_PLUS (SImode, xop0, xop1);
3364 else if (GET_CODE (x) == PLUS
3365 && s_register_operand (XEXP (x, 1), SImode)
3366 && !s_register_operand (XEXP (x, 0), SImode))
3368 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3370 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3375 /* We need to find and carefully transform any SYMBOL and LABEL
3376 references; so go back to the original address expression. */
3377 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3379 if (new_x != orig_x)
3388 #define REG_OR_SUBREG_REG(X) \
3389 (GET_CODE (X) == REG \
3390 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3392 #define REG_OR_SUBREG_RTX(X) \
3393 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3395 #ifndef COSTS_N_INSNS
3396 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3399 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3401 enum machine_mode mode = GET_MODE (x);
3414 return COSTS_N_INSNS (1);
3417 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3420 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3427 return COSTS_N_INSNS (2) + cycles;
3429 return COSTS_N_INSNS (1) + 16;
3432 return (COSTS_N_INSNS (1)
3433 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3434 + GET_CODE (SET_DEST (x)) == MEM));
3439 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3441 if (thumb_shiftable_const (INTVAL (x)))
3442 return COSTS_N_INSNS (2);
3443 return COSTS_N_INSNS (3);
3445 else if ((outer == PLUS || outer == COMPARE)
3446 && INTVAL (x) < 256 && INTVAL (x) > -256)
3448 else if (outer == AND
3449 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3450 return COSTS_N_INSNS (1);
3451 else if (outer == ASHIFT || outer == ASHIFTRT
3452 || outer == LSHIFTRT)
3454 return COSTS_N_INSNS (2);
3460 return COSTS_N_INSNS (3);
3479 /* XXX another guess. */
3480 /* Memory costs quite a lot for the first word, but subsequent words
3481 load at the equivalent of a single insn each. */
3482 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3483 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3488 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3493 /* XXX still guessing. */
3494 switch (GET_MODE (XEXP (x, 0)))
3497 return (1 + (mode == DImode ? 4 : 0)
3498 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3501 return (4 + (mode == DImode ? 4 : 0)
3502 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3505 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3517 /* Worker routine for arm_rtx_costs. */
3519 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3521 enum machine_mode mode = GET_MODE (x);
3522 enum rtx_code subcode;
3528 /* Memory costs quite a lot for the first word, but subsequent words
3529 load at the equivalent of a single insn each. */
3530 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3531 + (GET_CODE (x) == SYMBOL_REF
3532 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3538 return optimize_size ? COSTS_N_INSNS (2) : 100;
3541 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3548 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3550 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3551 + ((GET_CODE (XEXP (x, 0)) == REG
3552 || (GET_CODE (XEXP (x, 0)) == SUBREG
3553 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3555 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3556 || (GET_CODE (XEXP (x, 0)) == SUBREG
3557 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3559 + ((GET_CODE (XEXP (x, 1)) == REG
3560 || (GET_CODE (XEXP (x, 1)) == SUBREG
3561 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3562 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3567 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3568 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3569 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3570 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3573 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3574 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3575 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3576 && arm_const_double_rtx (XEXP (x, 1))))
3578 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3579 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3580 && arm_const_double_rtx (XEXP (x, 0))))
3583 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3584 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3585 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3586 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3587 || subcode == ASHIFTRT || subcode == LSHIFTRT
3588 || subcode == ROTATE || subcode == ROTATERT
3590 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3591 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3592 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3593 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3594 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3595 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3596 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3601 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3602 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3603 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3604 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3605 && arm_const_double_rtx (XEXP (x, 1))))
3609 case AND: case XOR: case IOR:
3612 /* Normally the frame registers will be spilt into reg+const during
3613 reload, so it is a bad idea to combine them with other instructions,
3614 since then they might not be moved outside of loops. As a compromise
3615 we allow integration with ops that have a constant as their second
3617 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3618 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3619 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3620 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3621 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3625 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3626 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3627 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3628 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3631 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3632 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3633 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3634 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3635 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3638 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3639 return (1 + extra_cost
3640 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3641 || subcode == LSHIFTRT || subcode == ASHIFTRT
3642 || subcode == ROTATE || subcode == ROTATERT
3644 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3645 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3646 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3647 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3648 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3649 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3655 /* This should have been handled by the CPU specific routines. */
3659 if (arm_arch3m && mode == SImode
3660 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3661 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3662 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3663 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3664 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3665 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3670 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3671 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3675 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3677 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3680 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3688 return 4 + (mode == DImode ? 4 : 0);
3691 if (GET_MODE (XEXP (x, 0)) == QImode)
3692 return (4 + (mode == DImode ? 4 : 0)
3693 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3696 switch (GET_MODE (XEXP (x, 0)))
3699 return (1 + (mode == DImode ? 4 : 0)
3700 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3703 return (4 + (mode == DImode ? 4 : 0)
3704 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3707 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3722 if (const_ok_for_arm (INTVAL (x)))
3723 return outer == SET ? 2 : -1;
3724 else if (outer == AND
3725 && const_ok_for_arm (~INTVAL (x)))
3727 else if ((outer == COMPARE
3728 || outer == PLUS || outer == MINUS)
3729 && const_ok_for_arm (-INTVAL (x)))
3740 if (arm_const_double_rtx (x))
3741 return outer == SET ? 2 : -1;
3742 else if ((outer == COMPARE || outer == PLUS)
3743 && neg_const_double_rtx_ok_for_fpa (x))
3752 /* RTX costs for cores with a slow MUL implementation. */
3755 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3757 enum machine_mode mode = GET_MODE (x);
3761 *total = thumb_rtx_costs (x, code, outer_code);
3768 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3775 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3777 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3778 & (unsigned HOST_WIDE_INT) 0xffffffff);
3779 int cost, const_ok = const_ok_for_arm (i);
3780 int j, booth_unit_size;
3782 /* Tune as appropriate. */
3783 cost = const_ok ? 4 : 8;
3784 booth_unit_size = 2;
3785 for (j = 0; i && j < 32; j += booth_unit_size)
3787 i >>= booth_unit_size;
3795 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3796 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3800 *total = arm_rtx_costs_1 (x, code, outer_code);
3806 /* RTX cost for cores with a fast multiply unit (M variants). */
3809 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3811 enum machine_mode mode = GET_MODE (x);
3815 *total = thumb_rtx_costs (x, code, outer_code);
3822 /* There is no point basing this on the tuning, since it is always the
3823 fast variant if it exists at all. */
3825 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3826 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3827 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3834 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3841 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3843 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3844 & (unsigned HOST_WIDE_INT) 0xffffffff);
3845 int cost, const_ok = const_ok_for_arm (i);
3846 int j, booth_unit_size;
3848 /* Tune as appropriate. */
3849 cost = const_ok ? 4 : 8;
3850 booth_unit_size = 8;
3851 for (j = 0; i && j < 32; j += booth_unit_size)
3853 i >>= booth_unit_size;
3861 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3862 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3866 *total = arm_rtx_costs_1 (x, code, outer_code);
3872 /* RTX cost for XScale CPUs. */
3875 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3877 enum machine_mode mode = GET_MODE (x);
3881 *total = thumb_rtx_costs (x, code, outer_code);
3888 /* There is no point basing this on the tuning, since it is always the
3889 fast variant if it exists at all. */
3891 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3892 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3893 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3900 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3907 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3909 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3910 & (unsigned HOST_WIDE_INT) 0xffffffff);
3911 int cost, const_ok = const_ok_for_arm (i);
3912 unsigned HOST_WIDE_INT masked_const;
3914 /* The cost will be related to two insns.
3915 First a load of the constant (MOV or LDR), then a multiply. */
3918 cost += 1; /* LDR is probably more expensive because
3919 of longer result latency. */
3920 masked_const = i & 0xffff8000;
3921 if (masked_const != 0 && masked_const != 0xffff8000)
3923 masked_const = i & 0xf8000000;
3924 if (masked_const == 0 || masked_const == 0xf8000000)
3933 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3934 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3938 *total = arm_rtx_costs_1 (x, code, outer_code);
3944 /* RTX costs for 9e (and later) cores. */
3947 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
3949 enum machine_mode mode = GET_MODE (x);
3958 *total = COSTS_N_INSNS (3);
3962 *total = thumb_rtx_costs (x, code, outer_code);
3970 /* There is no point basing this on the tuning, since it is always the
3971 fast variant if it exists at all. */
3973 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3974 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3975 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3982 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3999 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4000 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4004 *total = arm_rtx_costs_1 (x, code, outer_code);
4008 /* All address computations that can be done are free, but rtx cost returns
4009 the same for practically all of them. So we weight the different types
4010 of address here in the order (most pref first):
4011 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4013 arm_arm_address_cost (rtx x)
4015 enum rtx_code c = GET_CODE (x);
4017 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4019 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4022 if (c == PLUS || c == MINUS)
4024 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4027 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4037 arm_thumb_address_cost (rtx x)
4039 enum rtx_code c = GET_CODE (x);
4044 && GET_CODE (XEXP (x, 0)) == REG
4045 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4052 arm_address_cost (rtx x)
4054 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4058 arm_use_dfa_pipeline_interface (void)
4064 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4068 /* Some true dependencies can have a higher cost depending
4069 on precisely how certain input operands are used. */
4071 && REG_NOTE_KIND (link) == 0
4072 && recog_memoized (insn) >= 0
4073 && recog_memoized (dep) >= 0)
4075 int shift_opnum = get_attr_shift (insn);
4076 enum attr_type attr_type = get_attr_type (dep);
4078 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4079 operand for INSN. If we have a shifted input operand and the
4080 instruction we depend on is another ALU instruction, then we may
4081 have to account for an additional stall. */
4082 if (shift_opnum != 0
4083 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4085 rtx shifted_operand;
4088 /* Get the shifted operand. */
4089 extract_insn (insn);
4090 shifted_operand = recog_data.operand[shift_opnum];
4092 /* Iterate over all the operands in DEP. If we write an operand
4093 that overlaps with SHIFTED_OPERAND, then we have increase the
4094 cost of this dependency. */
4096 preprocess_constraints ();
4097 for (opno = 0; opno < recog_data.n_operands; opno++)
4099 /* We can ignore strict inputs. */
4100 if (recog_data.operand_type[opno] == OP_IN)
4103 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4110 /* XXX This is not strictly true for the FPA. */
4111 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4112 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4115 /* Call insns don't incur a stall, even if they follow a load. */
4116 if (REG_NOTE_KIND (link) == 0
4117 && GET_CODE (insn) == CALL_INSN)
4120 if ((i_pat = single_set (insn)) != NULL
4121 && GET_CODE (SET_SRC (i_pat)) == MEM
4122 && (d_pat = single_set (dep)) != NULL
4123 && GET_CODE (SET_DEST (d_pat)) == MEM)
4125 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4126 /* This is a load after a store, there is no conflict if the load reads
4127 from a cached area. Assume that loads from the stack, and from the
4128 constant pool are cached, and that others will miss. This is a
4131 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4132 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4133 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4134 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4141 static int fp_consts_inited = 0;
4143 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4144 static const char * const strings_fp[8] =
4147 "4", "5", "0.5", "10"
4150 static REAL_VALUE_TYPE values_fp[8];
4153 init_fp_table (void)
4159 fp_consts_inited = 1;
4161 fp_consts_inited = 8;
4163 for (i = 0; i < fp_consts_inited; i++)
4165 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4170 /* Return TRUE if rtx X is a valid immediate FP constant. */
4172 arm_const_double_rtx (rtx x)
4177 if (!fp_consts_inited)
4180 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4181 if (REAL_VALUE_MINUS_ZERO (r))
4184 for (i = 0; i < fp_consts_inited; i++)
4185 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4191 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4193 neg_const_double_rtx_ok_for_fpa (rtx x)
4198 if (!fp_consts_inited)
4201 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4202 r = REAL_VALUE_NEGATE (r);
4203 if (REAL_VALUE_MINUS_ZERO (r))
4206 for (i = 0; i < 8; i++)
4207 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4213 /* Predicates for `match_operand' and `match_operator'. */
4215 /* s_register_operand is the same as register_operand, but it doesn't accept
4218 This function exists because at the time it was put in it led to better
4219 code. SUBREG(MEM) always needs a reload in the places where
4220 s_register_operand is used, and this seemed to lead to excessive
4223 s_register_operand (rtx op, enum machine_mode mode)
4225 if (GET_MODE (op) != mode && mode != VOIDmode)
4228 if (GET_CODE (op) == SUBREG)
4229 op = SUBREG_REG (op);
4231 /* We don't consider registers whose class is NO_REGS
4232 to be a register operand. */
4233 /* XXX might have to check for lo regs only for thumb ??? */
4234 return (GET_CODE (op) == REG
4235 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4236 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4239 /* A hard register operand (even before reload. */
4241 arm_hard_register_operand (rtx op, enum machine_mode mode)
4243 if (GET_MODE (op) != mode && mode != VOIDmode)
4246 return (GET_CODE (op) == REG
4247 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4250 /* An arm register operand. */
4252 arm_general_register_operand (rtx op, enum machine_mode mode)
4254 if (GET_MODE (op) != mode && mode != VOIDmode)
4257 if (GET_CODE (op) == SUBREG)
4258 op = SUBREG_REG (op);
4260 return (GET_CODE (op) == REG
4261 && (REGNO (op) <= LAST_ARM_REGNUM
4262 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4265 /* Only accept reg, subreg(reg), const_int. */
4267 reg_or_int_operand (rtx op, enum machine_mode mode)
4269 if (GET_CODE (op) == CONST_INT)
4272 if (GET_MODE (op) != mode && mode != VOIDmode)
4275 if (GET_CODE (op) == SUBREG)
4276 op = SUBREG_REG (op);
4278 /* We don't consider registers whose class is NO_REGS
4279 to be a register operand. */
4280 return (GET_CODE (op) == REG
4281 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4282 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4285 /* Return 1 if OP is an item in memory, given that we are in reload. */
4287 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4289 int regno = true_regnum (op);
4291 return (!CONSTANT_P (op)
4293 || (GET_CODE (op) == REG
4294 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4297 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4299 arm_rhs_operand (rtx op, enum machine_mode mode)
4301 return (s_register_operand (op, mode)
4302 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4305 /* Return TRUE for valid operands for the
4306 rhs of an ARM instruction, or a load. */
4308 arm_rhsm_operand (rtx op, enum machine_mode mode)
4310 return (s_register_operand (op, mode)
4311 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4312 || memory_operand (op, mode));
4315 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4316 constant that is valid when negated. */
4318 arm_add_operand (rtx op, enum machine_mode mode)
4321 return thumb_cmp_operand (op, mode);
4323 return (s_register_operand (op, mode)
4324 || (GET_CODE (op) == CONST_INT
4325 && (const_ok_for_arm (INTVAL (op))
4326 || const_ok_for_arm (-INTVAL (op)))));
4329 /* Return TRUE for valid ARM constants (or when valid if negated). */
4331 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4333 return (GET_CODE (op) == CONST_INT
4334 && (const_ok_for_arm (INTVAL (op))
4335 || const_ok_for_arm (-INTVAL (op))));
4339 arm_not_operand (rtx op, enum machine_mode mode)
4341 return (s_register_operand (op, mode)
4342 || (GET_CODE (op) == CONST_INT
4343 && (const_ok_for_arm (INTVAL (op))
4344 || const_ok_for_arm (~INTVAL (op)))));
4347 /* Return TRUE if the operand is a memory reference which contains an
4348 offsettable address. */
4350 offsettable_memory_operand (rtx op, enum machine_mode mode)
4352 if (mode == VOIDmode)
4353 mode = GET_MODE (op);
4355 return (mode == GET_MODE (op)
4356 && GET_CODE (op) == MEM
4357 && offsettable_address_p (reload_completed | reload_in_progress,
4358 mode, XEXP (op, 0)));
4361 /* Return TRUE if the operand is a memory reference which is, or can be
4362 made word aligned by adjusting the offset. */
4364 alignable_memory_operand (rtx op, enum machine_mode mode)
4368 if (mode == VOIDmode)
4369 mode = GET_MODE (op);
4371 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4376 return ((GET_CODE (reg = op) == REG
4377 || (GET_CODE (op) == SUBREG
4378 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4379 || (GET_CODE (op) == PLUS
4380 && GET_CODE (XEXP (op, 1)) == CONST_INT
4381 && (GET_CODE (reg = XEXP (op, 0)) == REG
4382 || (GET_CODE (XEXP (op, 0)) == SUBREG
4383 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4384 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4387 /* Similar to s_register_operand, but does not allow hard integer
4390 f_register_operand (rtx op, enum machine_mode mode)
4392 if (GET_MODE (op) != mode && mode != VOIDmode)
4395 if (GET_CODE (op) == SUBREG)
4396 op = SUBREG_REG (op);
4398 /* We don't consider registers whose class is NO_REGS
4399 to be a register operand. */
4400 return (GET_CODE (op) == REG
4401 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4402 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4405 /* Return TRUE for valid operands for the rhs of an floating point insns.
4406 Allows regs or certain consts on FPA, just regs for everything else. */
4408 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4410 if (s_register_operand (op, mode))
4413 if (GET_MODE (op) != mode && mode != VOIDmode)
4416 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4417 return arm_const_double_rtx (op);
4423 arm_float_add_operand (rtx op, enum machine_mode mode)
4425 if (s_register_operand (op, mode))
4428 if (GET_MODE (op) != mode && mode != VOIDmode)
4431 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4432 return (arm_const_double_rtx (op)
4433 || neg_const_double_rtx_ok_for_fpa (op));
4439 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4440 Depends which fpu we are targeting. */
4443 arm_float_compare_operand (rtx op, enum machine_mode mode)
4446 return vfp_compare_operand (op, mode);
4448 return arm_float_rhs_operand (op, mode);
4452 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4454 cirrus_memory_offset (rtx op)
4456 /* Reject eliminable registers. */
4457 if (! (reload_in_progress || reload_completed)
4458 && ( reg_mentioned_p (frame_pointer_rtx, op)
4459 || reg_mentioned_p (arg_pointer_rtx, op)
4460 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4461 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4462 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4463 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4466 if (GET_CODE (op) == MEM)
4472 /* Match: (mem (reg)). */
4473 if (GET_CODE (ind) == REG)
4479 if (GET_CODE (ind) == PLUS
4480 && GET_CODE (XEXP (ind, 0)) == REG
4481 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4482 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4490 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4492 if (!memory_operand (op, mode))
4495 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4498 /* Return nonzero if OP is a Cirrus or general register. */
4500 cirrus_register_operand (rtx op, enum machine_mode mode)
4502 if (GET_MODE (op) != mode && mode != VOIDmode)
4505 if (GET_CODE (op) == SUBREG)
4506 op = SUBREG_REG (op);
4508 return (GET_CODE (op) == REG
4509 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4510 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4513 /* Return nonzero if OP is a cirrus FP register. */
4515 cirrus_fp_register (rtx op, enum machine_mode mode)
4517 if (GET_MODE (op) != mode && mode != VOIDmode)
4520 if (GET_CODE (op) == SUBREG)
4521 op = SUBREG_REG (op);
4523 return (GET_CODE (op) == REG
4524 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4525 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4528 /* Return nonzero if OP is a 6bit constant (0..63). */
4530 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4532 return (GET_CODE (op) == CONST_INT
4534 && INTVAL (op) < 64);
4538 /* Return TRUE if OP is a valid VFP memory address pattern. */
4539 /* Copied from cirrus_memory_offset but with restricted offset range. */
4542 vfp_mem_operand (rtx op)
4544 /* Reject eliminable registers. */
4546 if (! (reload_in_progress || reload_completed)
4547 && ( reg_mentioned_p (frame_pointer_rtx, op)
4548 || reg_mentioned_p (arg_pointer_rtx, op)
4549 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4550 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4551 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4552 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4555 /* Constants are converted into offsets from labels. */
4556 if (GET_CODE (op) == MEM)
4562 if (reload_completed
4563 && (GET_CODE (ind) == LABEL_REF
4564 || (GET_CODE (ind) == CONST
4565 && GET_CODE (XEXP (ind, 0)) == PLUS
4566 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4567 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4570 /* Match: (mem (reg)). */
4571 if (GET_CODE (ind) == REG)
4572 return arm_address_register_rtx_p (ind, 0);
4577 if (GET_CODE (ind) == PLUS
4578 && GET_CODE (XEXP (ind, 0)) == REG
4579 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4580 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4581 && INTVAL (XEXP (ind, 1)) > -1024
4582 && INTVAL (XEXP (ind, 1)) < 1024)
4590 /* Return TRUE if OP is a REG or constant zero. */
4592 vfp_compare_operand (rtx op, enum machine_mode mode)
4594 if (s_register_operand (op, mode))
4597 return (GET_CODE (op) == CONST_DOUBLE
4598 && arm_const_double_rtx (op));
4602 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4603 VFP registers. Otherwise return NO_REGS. */
4606 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4608 if (vfp_mem_operand (x) || s_register_operand (x, mode))
4611 return GENERAL_REGS;
4615 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4616 Use by the Cirrus Maverick code which has to workaround
4617 a hardware bug triggered by such instructions. */
4619 arm_memory_load_p (rtx insn)
4621 rtx body, lhs, rhs;;
4623 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4626 body = PATTERN (insn);
4628 if (GET_CODE (body) != SET)
4631 lhs = XEXP (body, 0);
4632 rhs = XEXP (body, 1);
4634 lhs = REG_OR_SUBREG_RTX (lhs);
4636 /* If the destination is not a general purpose
4637 register we do not have to worry. */
4638 if (GET_CODE (lhs) != REG
4639 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4642 /* As well as loads from memory we also have to react
4643 to loads of invalid constants which will be turned
4644 into loads from the minipool. */
4645 return (GET_CODE (rhs) == MEM
4646 || GET_CODE (rhs) == SYMBOL_REF
4647 || note_invalid_constants (insn, -1, false));
4650 /* Return TRUE if INSN is a Cirrus instruction. */
4652 arm_cirrus_insn_p (rtx insn)
4654 enum attr_cirrus attr;
4656 /* get_attr aborts on USE and CLOBBER. */
4658 || GET_CODE (insn) != INSN
4659 || GET_CODE (PATTERN (insn)) == USE
4660 || GET_CODE (PATTERN (insn)) == CLOBBER)
4663 attr = get_attr_cirrus (insn);
4665 return attr != CIRRUS_NOT;
4668 /* Cirrus reorg for invalid instruction combinations. */
4670 cirrus_reorg (rtx first)
4672 enum attr_cirrus attr;
4673 rtx body = PATTERN (first);
4677 /* Any branch must be followed by 2 non Cirrus instructions. */
4678 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4681 t = next_nonnote_insn (first);
4683 if (arm_cirrus_insn_p (t))
4686 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4690 emit_insn_after (gen_nop (), first);
4695 /* (float (blah)) is in parallel with a clobber. */
4696 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4697 body = XVECEXP (body, 0, 0);
4699 if (GET_CODE (body) == SET)
4701 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4703 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4704 be followed by a non Cirrus insn. */
4705 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4707 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4708 emit_insn_after (gen_nop (), first);
4712 else if (arm_memory_load_p (first))
4714 unsigned int arm_regno;
4716 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4717 ldr/cfmv64hr combination where the Rd field is the same
4718 in both instructions must be split with a non Cirrus
4725 /* Get Arm register number for ldr insn. */
4726 if (GET_CODE (lhs) == REG)
4727 arm_regno = REGNO (lhs);
4728 else if (GET_CODE (rhs) == REG)
4729 arm_regno = REGNO (rhs);
4734 first = next_nonnote_insn (first);
4736 if (! arm_cirrus_insn_p (first))
4739 body = PATTERN (first);
4741 /* (float (blah)) is in parallel with a clobber. */
4742 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4743 body = XVECEXP (body, 0, 0);
4745 if (GET_CODE (body) == FLOAT)
4746 body = XEXP (body, 0);
4748 if (get_attr_cirrus (first) == CIRRUS_MOVE
4749 && GET_CODE (XEXP (body, 1)) == REG
4750 && arm_regno == REGNO (XEXP (body, 1)))
4751 emit_insn_after (gen_nop (), first);
4757 /* get_attr aborts on USE and CLOBBER. */
4759 || GET_CODE (first) != INSN
4760 || GET_CODE (PATTERN (first)) == USE
4761 || GET_CODE (PATTERN (first)) == CLOBBER)
4764 attr = get_attr_cirrus (first);
4766 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4767 must be followed by a non-coprocessor instruction. */
4768 if (attr == CIRRUS_COMPARE)
4772 t = next_nonnote_insn (first);
4774 if (arm_cirrus_insn_p (t))
4777 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4781 emit_insn_after (gen_nop (), first);
4787 /* Return nonzero if OP is a constant power of two. */
4789 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4791 if (GET_CODE (op) == CONST_INT)
4793 HOST_WIDE_INT value = INTVAL (op);
4795 return value != 0 && (value & (value - 1)) == 0;
4801 /* Return TRUE for a valid operand of a DImode operation.
4802 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4803 Note that this disallows MEM(REG+REG), but allows
4804 MEM(PRE/POST_INC/DEC(REG)). */
4806 di_operand (rtx op, enum machine_mode mode)
4808 if (s_register_operand (op, mode))
4811 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4814 if (GET_CODE (op) == SUBREG)
4815 op = SUBREG_REG (op);
4817 switch (GET_CODE (op))
4824 return memory_address_p (DImode, XEXP (op, 0));
4831 /* Like di_operand, but don't accept constants. */
4833 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4835 if (s_register_operand (op, mode))
4838 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4841 if (GET_CODE (op) == SUBREG)
4842 op = SUBREG_REG (op);
4844 if (GET_CODE (op) == MEM)
4845 return memory_address_p (DImode, XEXP (op, 0));
4850 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4851 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4852 Note that this disallows MEM(REG+REG), but allows
4853 MEM(PRE/POST_INC/DEC(REG)). */
4855 soft_df_operand (rtx op, enum machine_mode mode)
4857 if (s_register_operand (op, mode))
4860 if (mode != VOIDmode && GET_MODE (op) != mode)
4863 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4866 if (GET_CODE (op) == SUBREG)
4867 op = SUBREG_REG (op);
4869 switch (GET_CODE (op))
4875 return memory_address_p (DFmode, XEXP (op, 0));
4882 /* Like soft_df_operand, but don't accept constants. */
4884 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4886 if (s_register_operand (op, mode))
4889 if (mode != VOIDmode && GET_MODE (op) != mode)
4892 if (GET_CODE (op) == SUBREG)
4893 op = SUBREG_REG (op);
4895 if (GET_CODE (op) == MEM)
4896 return memory_address_p (DFmode, XEXP (op, 0));
4900 /* Return TRUE for valid index operands. */
4902 index_operand (rtx op, enum machine_mode mode)
4904 return (s_register_operand (op, mode)
4905 || (immediate_operand (op, mode)
4906 && (GET_CODE (op) != CONST_INT
4907 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4910 /* Return TRUE for valid shifts by a constant. This also accepts any
4911 power of two on the (somewhat overly relaxed) assumption that the
4912 shift operator in this case was a mult. */
4914 const_shift_operand (rtx op, enum machine_mode mode)
4916 return (power_of_two_operand (op, mode)
4917 || (immediate_operand (op, mode)
4918 && (GET_CODE (op) != CONST_INT
4919 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4922 /* Return TRUE for arithmetic operators which can be combined with a multiply
4925 shiftable_operator (rtx x, enum machine_mode mode)
4929 if (GET_MODE (x) != mode)
4932 code = GET_CODE (x);
4934 return (code == PLUS || code == MINUS
4935 || code == IOR || code == XOR || code == AND);
4938 /* Return TRUE for binary logical operators. */
4940 logical_binary_operator (rtx x, enum machine_mode mode)
4944 if (GET_MODE (x) != mode)
4947 code = GET_CODE (x);
4949 return (code == IOR || code == XOR || code == AND);
4952 /* Return TRUE for shift operators. */
4954 shift_operator (rtx x,enum machine_mode mode)
4958 if (GET_MODE (x) != mode)
4961 code = GET_CODE (x);
4964 return power_of_two_operand (XEXP (x, 1), mode);
4966 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4967 || code == ROTATERT);
4970 /* Return TRUE if x is EQ or NE. */
4972 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4974 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4977 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4979 arm_comparison_operator (rtx x, enum machine_mode mode)
4981 return (comparison_operator (x, mode)
4982 && GET_CODE (x) != LTGT
4983 && GET_CODE (x) != UNEQ);
4986 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4988 minmax_operator (rtx x, enum machine_mode mode)
4990 enum rtx_code code = GET_CODE (x);
4992 if (GET_MODE (x) != mode)
4995 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4998 /* Return TRUE if this is the condition code register, if we aren't given
4999 a mode, accept any class CCmode register. */
5001 cc_register (rtx x, enum machine_mode mode)
5003 if (mode == VOIDmode)
5005 mode = GET_MODE (x);
5007 if (GET_MODE_CLASS (mode) != MODE_CC)
5011 if ( GET_MODE (x) == mode
5012 && GET_CODE (x) == REG
5013 && REGNO (x) == CC_REGNUM)
5019 /* Return TRUE if this is the condition code register, if we aren't given
5020 a mode, accept any class CCmode register which indicates a dominance
5023 dominant_cc_register (rtx x, enum machine_mode mode)
5025 if (mode == VOIDmode)
5027 mode = GET_MODE (x);
5029 if (GET_MODE_CLASS (mode) != MODE_CC)
5033 if (mode != CC_DNEmode && mode != CC_DEQmode
5034 && mode != CC_DLEmode && mode != CC_DLTmode
5035 && mode != CC_DGEmode && mode != CC_DGTmode
5036 && mode != CC_DLEUmode && mode != CC_DLTUmode
5037 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5040 return cc_register (x, mode);
5043 /* Return TRUE if X references a SYMBOL_REF. */
5045 symbol_mentioned_p (rtx x)
5050 if (GET_CODE (x) == SYMBOL_REF)
5053 fmt = GET_RTX_FORMAT (GET_CODE (x));
5055 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5061 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5062 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5065 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5072 /* Return TRUE if X references a LABEL_REF. */
5074 label_mentioned_p (rtx x)
5079 if (GET_CODE (x) == LABEL_REF)
5082 fmt = GET_RTX_FORMAT (GET_CODE (x));
5083 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5089 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5090 if (label_mentioned_p (XVECEXP (x, i, j)))
5093 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5103 enum rtx_code code = GET_CODE (x);
5107 else if (code == SMIN)
5109 else if (code == UMIN)
5111 else if (code == UMAX)
5117 /* Return 1 if memory locations are adjacent. */
5119 adjacent_mem_locations (rtx a, rtx b)
5121 if ((GET_CODE (XEXP (a, 0)) == REG
5122 || (GET_CODE (XEXP (a, 0)) == PLUS
5123 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5124 && (GET_CODE (XEXP (b, 0)) == REG
5125 || (GET_CODE (XEXP (b, 0)) == PLUS
5126 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5128 int val0 = 0, val1 = 0;
5131 if (GET_CODE (XEXP (a, 0)) == PLUS)
5133 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5134 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5137 reg0 = REGNO (XEXP (a, 0));
5139 if (GET_CODE (XEXP (b, 0)) == PLUS)
5141 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5142 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5145 reg1 = REGNO (XEXP (b, 0));
5147 /* Don't accept any offset that will require multiple
5148 instructions to handle, since this would cause the
5149 arith_adjacentmem pattern to output an overlong sequence. */
5150 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5153 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5158 /* Return 1 if OP is a load multiple operation. It is known to be
5159 parallel and the first section will be tested. */
5161 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5163 HOST_WIDE_INT count = XVECLEN (op, 0);
5166 HOST_WIDE_INT i = 1, base = 0;
5170 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5173 /* Check to see if this might be a write-back. */
5174 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5179 /* Now check it more carefully. */
5180 if (GET_CODE (SET_DEST (elt)) != REG
5181 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5182 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5183 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5187 /* Perform a quick check so we don't blow up below. */
5189 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5190 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5191 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5194 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5195 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5197 for (; i < count; i++)
5199 elt = XVECEXP (op, 0, i);
5201 if (GET_CODE (elt) != SET
5202 || GET_CODE (SET_DEST (elt)) != REG
5203 || GET_MODE (SET_DEST (elt)) != SImode
5204 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5205 || GET_CODE (SET_SRC (elt)) != MEM
5206 || GET_MODE (SET_SRC (elt)) != SImode
5207 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5208 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5209 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5210 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5217 /* Return 1 if OP is a store multiple operation. It is known to be
5218 parallel and the first section will be tested. */
5220 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5222 HOST_WIDE_INT count = XVECLEN (op, 0);
5225 HOST_WIDE_INT i = 1, base = 0;
5229 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5232 /* Check to see if this might be a write-back. */
5233 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5238 /* Now check it more carefully. */
5239 if (GET_CODE (SET_DEST (elt)) != REG
5240 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5241 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5242 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5246 /* Perform a quick check so we don't blow up below. */
5248 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5249 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5250 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5253 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5254 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5256 for (; i < count; i++)
5258 elt = XVECEXP (op, 0, i);
5260 if (GET_CODE (elt) != SET
5261 || GET_CODE (SET_SRC (elt)) != REG
5262 || GET_MODE (SET_SRC (elt)) != SImode
5263 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5264 || GET_CODE (SET_DEST (elt)) != MEM
5265 || GET_MODE (SET_DEST (elt)) != SImode
5266 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5267 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5268 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5269 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5277 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5278 HOST_WIDE_INT *load_offset)
5280 int unsorted_regs[4];
5281 HOST_WIDE_INT unsorted_offsets[4];
5286 /* Can only handle 2, 3, or 4 insns at present,
5287 though could be easily extended if required. */
5288 if (nops < 2 || nops > 4)
5291 /* Loop over the operands and check that the memory references are
5292 suitable (ie immediate offsets from the same base register). At
5293 the same time, extract the target register, and the memory
5295 for (i = 0; i < nops; i++)
5300 /* Convert a subreg of a mem into the mem itself. */
5301 if (GET_CODE (operands[nops + i]) == SUBREG)
5302 operands[nops + i] = alter_subreg (operands + (nops + i));
5304 if (GET_CODE (operands[nops + i]) != MEM)
5307 /* Don't reorder volatile memory references; it doesn't seem worth
5308 looking for the case where the order is ok anyway. */
5309 if (MEM_VOLATILE_P (operands[nops + i]))
5312 offset = const0_rtx;
5314 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5315 || (GET_CODE (reg) == SUBREG
5316 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5317 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5318 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5320 || (GET_CODE (reg) == SUBREG
5321 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5322 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5327 base_reg = REGNO (reg);
5328 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5329 ? REGNO (operands[i])
5330 : REGNO (SUBREG_REG (operands[i])));
5335 if (base_reg != (int) REGNO (reg))
5336 /* Not addressed from the same base register. */
5339 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5340 ? REGNO (operands[i])
5341 : REGNO (SUBREG_REG (operands[i])));
5342 if (unsorted_regs[i] < unsorted_regs[order[0]])
5346 /* If it isn't an integer register, or if it overwrites the
5347 base register but isn't the last insn in the list, then
5348 we can't do this. */
5349 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5350 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5353 unsorted_offsets[i] = INTVAL (offset);
5356 /* Not a suitable memory address. */
5360 /* All the useful information has now been extracted from the
5361 operands into unsorted_regs and unsorted_offsets; additionally,
5362 order[0] has been set to the lowest numbered register in the
5363 list. Sort the registers into order, and check that the memory
5364 offsets are ascending and adjacent. */
5366 for (i = 1; i < nops; i++)
5370 order[i] = order[i - 1];
5371 for (j = 0; j < nops; j++)
5372 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5373 && (order[i] == order[i - 1]
5374 || unsorted_regs[j] < unsorted_regs[order[i]]))
5377 /* Have we found a suitable register? if not, one must be used more
5379 if (order[i] == order[i - 1])
5382 /* Is the memory address adjacent and ascending? */
5383 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5391 for (i = 0; i < nops; i++)
5392 regs[i] = unsorted_regs[order[i]];
5394 *load_offset = unsorted_offsets[order[0]];
5397 if (unsorted_offsets[order[0]] == 0)
5398 return 1; /* ldmia */
5400 if (unsorted_offsets[order[0]] == 4)
5401 return 2; /* ldmib */
5403 if (unsorted_offsets[order[nops - 1]] == 0)
5404 return 3; /* ldmda */
5406 if (unsorted_offsets[order[nops - 1]] == -4)
5407 return 4; /* ldmdb */
5409 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5410 if the offset isn't small enough. The reason 2 ldrs are faster
5411 is because these ARMs are able to do more than one cache access
5412 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5413 whilst the ARM8 has a double bandwidth cache. This means that
5414 these cores can do both an instruction fetch and a data fetch in
5415 a single cycle, so the trick of calculating the address into a
5416 scratch register (one of the result regs) and then doing a load
5417 multiple actually becomes slower (and no smaller in code size).
5418 That is the transformation
5420 ldr rd1, [rbase + offset]
5421 ldr rd2, [rbase + offset + 4]
5425 add rd1, rbase, offset
5426 ldmia rd1, {rd1, rd2}
5428 produces worse code -- '3 cycles + any stalls on rd2' instead of
5429 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5430 access per cycle, the first sequence could never complete in less
5431 than 6 cycles, whereas the ldm sequence would only take 5 and
5432 would make better use of sequential accesses if not hitting the
5435 We cheat here and test 'arm_ld_sched' which we currently know to
5436 only be true for the ARM8, ARM9 and StrongARM. If this ever
5437 changes, then the test below needs to be reworked. */
5438 if (nops == 2 && arm_ld_sched)
5441 /* Can't do it without setting up the offset, only do this if it takes
5442 no more than one insn. */
5443 return (const_ok_for_arm (unsorted_offsets[order[0]])
5444 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5448 emit_ldm_seq (rtx *operands, int nops)
5452 HOST_WIDE_INT offset;
5456 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5459 strcpy (buf, "ldm%?ia\t");
5463 strcpy (buf, "ldm%?ib\t");
5467 strcpy (buf, "ldm%?da\t");
5471 strcpy (buf, "ldm%?db\t");
5476 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5477 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5480 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5481 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5483 output_asm_insn (buf, operands);
5485 strcpy (buf, "ldm%?ia\t");
5492 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5493 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5495 for (i = 1; i < nops; i++)
5496 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5497 reg_names[regs[i]]);
5499 strcat (buf, "}\t%@ phole ldm");
5501 output_asm_insn (buf, operands);
5506 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5507 HOST_WIDE_INT * load_offset)
5509 int unsorted_regs[4];
5510 HOST_WIDE_INT unsorted_offsets[4];
5515 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5516 extended if required. */
5517 if (nops < 2 || nops > 4)
5520 /* Loop over the operands and check that the memory references are
5521 suitable (ie immediate offsets from the same base register). At
5522 the same time, extract the target register, and the memory
5524 for (i = 0; i < nops; i++)
5529 /* Convert a subreg of a mem into the mem itself. */
5530 if (GET_CODE (operands[nops + i]) == SUBREG)
5531 operands[nops + i] = alter_subreg (operands + (nops + i));
5533 if (GET_CODE (operands[nops + i]) != MEM)
5536 /* Don't reorder volatile memory references; it doesn't seem worth
5537 looking for the case where the order is ok anyway. */
5538 if (MEM_VOLATILE_P (operands[nops + i]))
5541 offset = const0_rtx;
5543 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5544 || (GET_CODE (reg) == SUBREG
5545 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5546 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5547 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5549 || (GET_CODE (reg) == SUBREG
5550 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5551 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5556 base_reg = REGNO (reg);
5557 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5558 ? REGNO (operands[i])
5559 : REGNO (SUBREG_REG (operands[i])));
5564 if (base_reg != (int) REGNO (reg))
5565 /* Not addressed from the same base register. */
5568 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5569 ? REGNO (operands[i])
5570 : REGNO (SUBREG_REG (operands[i])));
5571 if (unsorted_regs[i] < unsorted_regs[order[0]])
5575 /* If it isn't an integer register, then we can't do this. */
5576 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5579 unsorted_offsets[i] = INTVAL (offset);
5582 /* Not a suitable memory address. */
5586 /* All the useful information has now been extracted from the
5587 operands into unsorted_regs and unsorted_offsets; additionally,
5588 order[0] has been set to the lowest numbered register in the
5589 list. Sort the registers into order, and check that the memory
5590 offsets are ascending and adjacent. */
5592 for (i = 1; i < nops; i++)
5596 order[i] = order[i - 1];
5597 for (j = 0; j < nops; j++)
5598 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5599 && (order[i] == order[i - 1]
5600 || unsorted_regs[j] < unsorted_regs[order[i]]))
5603 /* Have we found a suitable register? if not, one must be used more
5605 if (order[i] == order[i - 1])
5608 /* Is the memory address adjacent and ascending? */
5609 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5617 for (i = 0; i < nops; i++)
5618 regs[i] = unsorted_regs[order[i]];
5620 *load_offset = unsorted_offsets[order[0]];
5623 if (unsorted_offsets[order[0]] == 0)
5624 return 1; /* stmia */
5626 if (unsorted_offsets[order[0]] == 4)
5627 return 2; /* stmib */
5629 if (unsorted_offsets[order[nops - 1]] == 0)
5630 return 3; /* stmda */
5632 if (unsorted_offsets[order[nops - 1]] == -4)
5633 return 4; /* stmdb */
5639 emit_stm_seq (rtx *operands, int nops)
5643 HOST_WIDE_INT offset;
5647 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5650 strcpy (buf, "stm%?ia\t");
5654 strcpy (buf, "stm%?ib\t");
5658 strcpy (buf, "stm%?da\t");
5662 strcpy (buf, "stm%?db\t");
5669 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5670 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5672 for (i = 1; i < nops; i++)
5673 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5674 reg_names[regs[i]]);
5676 strcat (buf, "}\t%@ phole stm");
5678 output_asm_insn (buf, operands);
5683 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5685 if (GET_CODE (op) != PARALLEL
5686 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5687 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5688 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5694 /* Routines for use in generating RTL. */
5697 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5698 int write_back, int unchanging_p, int in_struct_p,
5703 int sign = up ? 1 : -1;
5706 /* XScale has load-store double instructions, but they have stricter
5707 alignment requirements than load-store multiple, so we can not
5710 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5711 the pipeline until completion.
5719 An ldr instruction takes 1-3 cycles, but does not block the
5728 Best case ldr will always win. However, the more ldr instructions
5729 we issue, the less likely we are to be able to schedule them well.
5730 Using ldr instructions also increases code size.
5732 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5733 for counts of 3 or 4 regs. */
5734 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5740 for (i = 0; i < count; i++)
5742 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5743 RTX_UNCHANGING_P (mem) = unchanging_p;
5744 MEM_IN_STRUCT_P (mem) = in_struct_p;
5745 MEM_SCALAR_P (mem) = scalar_p;
5746 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5750 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5758 result = gen_rtx_PARALLEL (VOIDmode,
5759 rtvec_alloc (count + (write_back ? 1 : 0)));
5762 XVECEXP (result, 0, 0)
5763 = gen_rtx_SET (GET_MODE (from), from,
5764 plus_constant (from, count * 4 * sign));
5769 for (j = 0; i < count; i++, j++)
5771 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5772 RTX_UNCHANGING_P (mem) = unchanging_p;
5773 MEM_IN_STRUCT_P (mem) = in_struct_p;
5774 MEM_SCALAR_P (mem) = scalar_p;
5775 XVECEXP (result, 0, i)
5776 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5783 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5784 int write_back, int unchanging_p, int in_struct_p,
5789 int sign = up ? 1 : -1;
5792 /* See arm_gen_load_multiple for discussion of
5793 the pros/cons of ldm/stm usage for XScale. */
5794 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5800 for (i = 0; i < count; i++)
5802 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5803 RTX_UNCHANGING_P (mem) = unchanging_p;
5804 MEM_IN_STRUCT_P (mem) = in_struct_p;
5805 MEM_SCALAR_P (mem) = scalar_p;
5806 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5810 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5818 result = gen_rtx_PARALLEL (VOIDmode,
5819 rtvec_alloc (count + (write_back ? 1 : 0)));
5822 XVECEXP (result, 0, 0)
5823 = gen_rtx_SET (GET_MODE (to), to,
5824 plus_constant (to, count * 4 * sign));
5829 for (j = 0; i < count; i++, j++)
5831 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5832 RTX_UNCHANGING_P (mem) = unchanging_p;
5833 MEM_IN_STRUCT_P (mem) = in_struct_p;
5834 MEM_SCALAR_P (mem) = scalar_p;
5836 XVECEXP (result, 0, i)
5837 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5844 arm_gen_movstrqi (rtx *operands)
5846 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5849 rtx st_src, st_dst, fin_src, fin_dst;
5850 rtx part_bytes_reg = NULL;
5852 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5853 int dst_scalar_p, src_scalar_p;
5855 if (GET_CODE (operands[2]) != CONST_INT
5856 || GET_CODE (operands[3]) != CONST_INT
5857 || INTVAL (operands[2]) > 64
5858 || INTVAL (operands[3]) & 3)
5861 st_dst = XEXP (operands[0], 0);
5862 st_src = XEXP (operands[1], 0);
5864 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5865 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5866 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5867 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5868 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5869 src_scalar_p = MEM_SCALAR_P (operands[1]);
5871 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5872 fin_src = src = copy_to_mode_reg (SImode, st_src);
5874 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5875 out_words_to_go = INTVAL (operands[2]) / 4;
5876 last_bytes = INTVAL (operands[2]) & 3;
5878 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5879 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5881 for (i = 0; in_words_to_go >= 2; i+=4)
5883 if (in_words_to_go > 4)
5884 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5889 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5890 FALSE, src_unchanging_p,
5891 src_in_struct_p, src_scalar_p));
5893 if (out_words_to_go)
5895 if (out_words_to_go > 4)
5896 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5900 else if (out_words_to_go != 1)
5901 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5910 mem = gen_rtx_MEM (SImode, dst);
5911 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5912 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5913 MEM_SCALAR_P (mem) = dst_scalar_p;
5914 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5915 if (last_bytes != 0)
5916 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5920 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5921 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5924 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5925 if (out_words_to_go)
5929 mem = gen_rtx_MEM (SImode, src);
5930 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5931 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5932 MEM_SCALAR_P (mem) = src_scalar_p;
5933 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5934 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5936 mem = gen_rtx_MEM (SImode, dst);
5937 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5938 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5939 MEM_SCALAR_P (mem) = dst_scalar_p;
5940 emit_move_insn (mem, sreg);
5941 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5944 if (in_words_to_go) /* Sanity check */
5950 if (in_words_to_go < 0)
5953 mem = gen_rtx_MEM (SImode, src);
5954 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5955 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5956 MEM_SCALAR_P (mem) = src_scalar_p;
5957 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5960 if (last_bytes && part_bytes_reg == NULL)
5963 if (BYTES_BIG_ENDIAN && last_bytes)
5965 rtx tmp = gen_reg_rtx (SImode);
5967 /* The bytes we want are in the top end of the word. */
5968 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5969 GEN_INT (8 * (4 - last_bytes))));
5970 part_bytes_reg = tmp;
5974 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5975 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5976 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5977 MEM_SCALAR_P (mem) = dst_scalar_p;
5978 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5982 tmp = gen_reg_rtx (SImode);
5983 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5984 part_bytes_reg = tmp;
5993 mem = gen_rtx_MEM (HImode, dst);
5994 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5995 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5996 MEM_SCALAR_P (mem) = dst_scalar_p;
5997 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6001 rtx tmp = gen_reg_rtx (SImode);
6003 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6004 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6005 part_bytes_reg = tmp;
6011 mem = gen_rtx_MEM (QImode, dst);
6012 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6013 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6014 MEM_SCALAR_P (mem) = dst_scalar_p;
6015 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6022 /* Generate a memory reference for a half word, such that it will be loaded
6023 into the top 16 bits of the word. We can assume that the address is
6024 known to be alignable and of the form reg, or plus (reg, const). */
6027 arm_gen_rotated_half_load (rtx memref)
6029 HOST_WIDE_INT offset = 0;
6030 rtx base = XEXP (memref, 0);
6032 if (GET_CODE (base) == PLUS)
6034 offset = INTVAL (XEXP (base, 1));
6035 base = XEXP (base, 0);
6038 /* If we aren't allowed to generate unaligned addresses, then fail. */
6039 if (TARGET_MMU_TRAPS
6040 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
6043 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6045 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6048 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6051 /* Select a dominance comparison mode if possible for a test of the general
6052 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6053 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6054 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6055 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6056 In all cases OP will be either EQ or NE, but we don't need to know which
6057 here. If we are unable to support a dominance comparison we return
6058 CC mode. This will then fail to match for the RTL expressions that
6059 generate this call. */
6061 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6063 enum rtx_code cond1, cond2;
6066 /* Currently we will probably get the wrong result if the individual
6067 comparisons are not simple. This also ensures that it is safe to
6068 reverse a comparison if necessary. */
6069 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6071 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6075 /* The if_then_else variant of this tests the second condition if the
6076 first passes, but is true if the first fails. Reverse the first
6077 condition to get a true "inclusive-or" expression. */
6078 if (cond_or == DOM_CC_NX_OR_Y)
6079 cond1 = reverse_condition (cond1);
6081 /* If the comparisons are not equal, and one doesn't dominate the other,
6082 then we can't do this. */
6084 && !comparison_dominates_p (cond1, cond2)
6085 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6090 enum rtx_code temp = cond1;
6098 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6103 case LE: return CC_DLEmode;
6104 case LEU: return CC_DLEUmode;
6105 case GE: return CC_DGEmode;
6106 case GEU: return CC_DGEUmode;
6113 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6122 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6131 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6140 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6148 /* The remaining cases only occur when both comparisons are the
6173 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6175 /* All floating point compares return CCFP if it is an equality
6176 comparison, and CCFPE otherwise. */
6177 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6197 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6206 /* A compare with a shifted operand. Because of canonicalization, the
6207 comparison will have to be swapped when we emit the assembler. */
6208 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6209 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6210 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6211 || GET_CODE (x) == ROTATERT))
6214 /* This is a special case that is used by combine to allow a
6215 comparison of a shifted byte load to be split into a zero-extend
6216 followed by a comparison of the shifted integer (only valid for
6217 equalities and unsigned inequalities). */
6218 if (GET_MODE (x) == SImode
6219 && GET_CODE (x) == ASHIFT
6220 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6221 && GET_CODE (XEXP (x, 0)) == SUBREG
6222 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6223 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6224 && (op == EQ || op == NE
6225 || op == GEU || op == GTU || op == LTU || op == LEU)
6226 && GET_CODE (y) == CONST_INT)
6229 /* A construct for a conditional compare, if the false arm contains
6230 0, then both conditions must be true, otherwise either condition
6231 must be true. Not all conditions are possible, so CCmode is
6232 returned if it can't be done. */
6233 if (GET_CODE (x) == IF_THEN_ELSE
6234 && (XEXP (x, 2) == const0_rtx
6235 || XEXP (x, 2) == const1_rtx)
6236 && COMPARISON_P (XEXP (x, 0))
6237 && COMPARISON_P (XEXP (x, 1)))
6238 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6239 INTVAL (XEXP (x, 2)));
6241 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6242 if (GET_CODE (x) == AND
6243 && COMPARISON_P (XEXP (x, 0))
6244 && COMPARISON_P (XEXP (x, 1)))
6245 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6248 if (GET_CODE (x) == IOR
6249 && COMPARISON_P (XEXP (x, 0))
6250 && COMPARISON_P (XEXP (x, 1)))
6251 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6254 /* An operation (on Thumb) where we want to test for a single bit.
6255 This is done by shifting that bit up into the top bit of a
6256 scratch register; we can then branch on the sign bit. */
6258 && GET_MODE (x) == SImode
6259 && (op == EQ || op == NE)
6260 && (GET_CODE (x) == ZERO_EXTRACT))
6263 /* An operation that sets the condition codes as a side-effect, the
6264 V flag is not set correctly, so we can only use comparisons where
6265 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6267 if (GET_MODE (x) == SImode
6269 && (op == EQ || op == NE || op == LT || op == GE)
6270 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6271 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6272 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6273 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6274 || GET_CODE (x) == LSHIFTRT
6275 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6276 || GET_CODE (x) == ROTATERT
6277 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6280 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6283 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6284 && GET_CODE (x) == PLUS
6285 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6291 /* X and Y are two things to compare using CODE. Emit the compare insn and
6292 return the rtx for register 0 in the proper mode. FP means this is a
6293 floating point compare: I don't think that it is needed on the arm. */
6295 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6297 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6298 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6300 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6301 gen_rtx_COMPARE (mode, x, y)));
6306 /* Generate a sequence of insns that will generate the correct return
6307 address mask depending on the physical architecture that the program
6310 arm_gen_return_addr_mask (void)
6312 rtx reg = gen_reg_rtx (Pmode);
6314 emit_insn (gen_return_addr_mask (reg));
6319 arm_reload_in_hi (rtx *operands)
6321 rtx ref = operands[1];
6323 HOST_WIDE_INT offset = 0;
6325 if (GET_CODE (ref) == SUBREG)
6327 offset = SUBREG_BYTE (ref);
6328 ref = SUBREG_REG (ref);
6331 if (GET_CODE (ref) == REG)
6333 /* We have a pseudo which has been spilt onto the stack; there
6334 are two cases here: the first where there is a simple
6335 stack-slot replacement and a second where the stack-slot is
6336 out of range, or is used as a subreg. */
6337 if (reg_equiv_mem[REGNO (ref)])
6339 ref = reg_equiv_mem[REGNO (ref)];
6340 base = find_replacement (&XEXP (ref, 0));
6343 /* The slot is out of range, or was dressed up in a SUBREG. */
6344 base = reg_equiv_address[REGNO (ref)];
6347 base = find_replacement (&XEXP (ref, 0));
6349 /* Handle the case where the address is too complex to be offset by 1. */
6350 if (GET_CODE (base) == MINUS
6351 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6353 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6355 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6358 else if (GET_CODE (base) == PLUS)
6360 /* The addend must be CONST_INT, or we would have dealt with it above. */
6361 HOST_WIDE_INT hi, lo;
6363 offset += INTVAL (XEXP (base, 1));
6364 base = XEXP (base, 0);
6366 /* Rework the address into a legal sequence of insns. */
6367 /* Valid range for lo is -4095 -> 4095 */
6370 : -((-offset) & 0xfff));
6372 /* Corner case, if lo is the max offset then we would be out of range
6373 once we have added the additional 1 below, so bump the msb into the
6374 pre-loading insn(s). */
6378 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6379 ^ (HOST_WIDE_INT) 0x80000000)
6380 - (HOST_WIDE_INT) 0x80000000);
6382 if (hi + lo != offset)
6387 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6389 /* Get the base address; addsi3 knows how to handle constants
6390 that require more than one insn. */
6391 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6397 /* Operands[2] may overlap operands[0] (though it won't overlap
6398 operands[1]), that's why we asked for a DImode reg -- so we can
6399 use the bit that does not overlap. */
6400 if (REGNO (operands[2]) == REGNO (operands[0]))
6401 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6403 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6405 emit_insn (gen_zero_extendqisi2 (scratch,
6406 gen_rtx_MEM (QImode,
6407 plus_constant (base,
6409 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6410 gen_rtx_MEM (QImode,
6411 plus_constant (base,
6413 if (!BYTES_BIG_ENDIAN)
6414 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6415 gen_rtx_IOR (SImode,
6418 gen_rtx_SUBREG (SImode, operands[0], 0),
6422 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6423 gen_rtx_IOR (SImode,
6424 gen_rtx_ASHIFT (SImode, scratch,
6426 gen_rtx_SUBREG (SImode, operands[0],
6430 /* Handle storing a half-word to memory during reload by synthesizing as two
6431 byte stores. Take care not to clobber the input values until after we
6432 have moved them somewhere safe. This code assumes that if the DImode
6433 scratch in operands[2] overlaps either the input value or output address
6434 in some way, then that value must die in this insn (we absolutely need
6435 two scratch registers for some corner cases). */
6437 arm_reload_out_hi (rtx *operands)
6439 rtx ref = operands[0];
6440 rtx outval = operands[1];
6442 HOST_WIDE_INT offset = 0;
6444 if (GET_CODE (ref) == SUBREG)
6446 offset = SUBREG_BYTE (ref);
6447 ref = SUBREG_REG (ref);
6450 if (GET_CODE (ref) == REG)
6452 /* We have a pseudo which has been spilt onto the stack; there
6453 are two cases here: the first where there is a simple
6454 stack-slot replacement and a second where the stack-slot is
6455 out of range, or is used as a subreg. */
6456 if (reg_equiv_mem[REGNO (ref)])
6458 ref = reg_equiv_mem[REGNO (ref)];
6459 base = find_replacement (&XEXP (ref, 0));
6462 /* The slot is out of range, or was dressed up in a SUBREG. */
6463 base = reg_equiv_address[REGNO (ref)];
6466 base = find_replacement (&XEXP (ref, 0));
6468 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6470 /* Handle the case where the address is too complex to be offset by 1. */
6471 if (GET_CODE (base) == MINUS
6472 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6474 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6476 /* Be careful not to destroy OUTVAL. */
6477 if (reg_overlap_mentioned_p (base_plus, outval))
6479 /* Updating base_plus might destroy outval, see if we can
6480 swap the scratch and base_plus. */
6481 if (!reg_overlap_mentioned_p (scratch, outval))
6484 scratch = base_plus;
6489 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6491 /* Be conservative and copy OUTVAL into the scratch now,
6492 this should only be necessary if outval is a subreg
6493 of something larger than a word. */
6494 /* XXX Might this clobber base? I can't see how it can,
6495 since scratch is known to overlap with OUTVAL, and
6496 must be wider than a word. */
6497 emit_insn (gen_movhi (scratch_hi, outval));
6498 outval = scratch_hi;
6502 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6505 else if (GET_CODE (base) == PLUS)
6507 /* The addend must be CONST_INT, or we would have dealt with it above. */
6508 HOST_WIDE_INT hi, lo;
6510 offset += INTVAL (XEXP (base, 1));
6511 base = XEXP (base, 0);
6513 /* Rework the address into a legal sequence of insns. */
6514 /* Valid range for lo is -4095 -> 4095 */
6517 : -((-offset) & 0xfff));
6519 /* Corner case, if lo is the max offset then we would be out of range
6520 once we have added the additional 1 below, so bump the msb into the
6521 pre-loading insn(s). */
6525 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6526 ^ (HOST_WIDE_INT) 0x80000000)
6527 - (HOST_WIDE_INT) 0x80000000);
6529 if (hi + lo != offset)
6534 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6536 /* Be careful not to destroy OUTVAL. */
6537 if (reg_overlap_mentioned_p (base_plus, outval))
6539 /* Updating base_plus might destroy outval, see if we
6540 can swap the scratch and base_plus. */
6541 if (!reg_overlap_mentioned_p (scratch, outval))
6544 scratch = base_plus;
6549 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6551 /* Be conservative and copy outval into scratch now,
6552 this should only be necessary if outval is a
6553 subreg of something larger than a word. */
6554 /* XXX Might this clobber base? I can't see how it
6555 can, since scratch is known to overlap with
6557 emit_insn (gen_movhi (scratch_hi, outval));
6558 outval = scratch_hi;
6562 /* Get the base address; addsi3 knows how to handle constants
6563 that require more than one insn. */
6564 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6570 if (BYTES_BIG_ENDIAN)
6572 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6573 plus_constant (base, offset + 1)),
6574 gen_lowpart (QImode, outval)));
6575 emit_insn (gen_lshrsi3 (scratch,
6576 gen_rtx_SUBREG (SImode, outval, 0),
6578 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6579 gen_lowpart (QImode, scratch)));
6583 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6584 gen_lowpart (QImode, outval)));
6585 emit_insn (gen_lshrsi3 (scratch,
6586 gen_rtx_SUBREG (SImode, outval, 0),
6588 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6589 plus_constant (base, offset + 1)),
6590 gen_lowpart (QImode, scratch)));
6594 /* Print a symbolic form of X to the debug file, F. */
6596 arm_print_value (FILE *f, rtx x)
6598 switch (GET_CODE (x))
6601 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6605 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6613 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6615 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6616 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6624 fprintf (f, "\"%s\"", XSTR (x, 0));
6628 fprintf (f, "`%s'", XSTR (x, 0));
6632 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6636 arm_print_value (f, XEXP (x, 0));
6640 arm_print_value (f, XEXP (x, 0));
6642 arm_print_value (f, XEXP (x, 1));
6650 fprintf (f, "????");
6655 /* Routines for manipulation of the constant pool. */
6657 /* Arm instructions cannot load a large constant directly into a
6658 register; they have to come from a pc relative load. The constant
6659 must therefore be placed in the addressable range of the pc
6660 relative load. Depending on the precise pc relative load
6661 instruction the range is somewhere between 256 bytes and 4k. This
6662 means that we often have to dump a constant inside a function, and
6663 generate code to branch around it.
6665 It is important to minimize this, since the branches will slow
6666 things down and make the code larger.
6668 Normally we can hide the table after an existing unconditional
6669 branch so that there is no interruption of the flow, but in the
6670 worst case the code looks like this:
6688 We fix this by performing a scan after scheduling, which notices
6689 which instructions need to have their operands fetched from the
6690 constant table and builds the table.
6692 The algorithm starts by building a table of all the constants that
6693 need fixing up and all the natural barriers in the function (places
6694 where a constant table can be dropped without breaking the flow).
6695 For each fixup we note how far the pc-relative replacement will be
6696 able to reach and the offset of the instruction into the function.
6698 Having built the table we then group the fixes together to form
6699 tables that are as large as possible (subject to addressing
6700 constraints) and emit each table of constants after the last
6701 barrier that is within range of all the instructions in the group.
6702 If a group does not contain a barrier, then we forcibly create one
6703 by inserting a jump instruction into the flow. Once the table has
6704 been inserted, the insns are then modified to reference the
6705 relevant entry in the pool.
6707 Possible enhancements to the algorithm (not implemented) are:
6709 1) For some processors and object formats, there may be benefit in
6710 aligning the pools to the start of cache lines; this alignment
6711 would need to be taken into account when calculating addressability
6714 /* These typedefs are located at the start of this file, so that
6715 they can be used in the prototypes there. This comment is to
6716 remind readers of that fact so that the following structures
6717 can be understood more easily.
6719 typedef struct minipool_node Mnode;
6720 typedef struct minipool_fixup Mfix; */
6722 struct minipool_node
6724 /* Doubly linked chain of entries. */
6727 /* The maximum offset into the code that this entry can be placed. While
6728 pushing fixes for forward references, all entries are sorted in order
6729 of increasing max_address. */
6730 HOST_WIDE_INT max_address;
6731 /* Similarly for an entry inserted for a backwards ref. */
6732 HOST_WIDE_INT min_address;
6733 /* The number of fixes referencing this entry. This can become zero
6734 if we "unpush" an entry. In this case we ignore the entry when we
6735 come to emit the code. */
6737 /* The offset from the start of the minipool. */
6738 HOST_WIDE_INT offset;
6739 /* The value in table. */
6741 /* The mode of value. */
6742 enum machine_mode mode;
6743 /* The size of the value. With iWMMXt enabled
6744 sizes > 4 also imply an alignment of 8-bytes. */
6748 struct minipool_fixup
6752 HOST_WIDE_INT address;
6754 enum machine_mode mode;
6758 HOST_WIDE_INT forwards;
6759 HOST_WIDE_INT backwards;
6762 /* Fixes less than a word need padding out to a word boundary. */
6763 #define MINIPOOL_FIX_SIZE(mode) \
6764 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6766 static Mnode * minipool_vector_head;
6767 static Mnode * minipool_vector_tail;
6768 static rtx minipool_vector_label;
6770 /* The linked list of all minipool fixes required for this function. */
6771 Mfix * minipool_fix_head;
6772 Mfix * minipool_fix_tail;
6773 /* The fix entry for the current minipool, once it has been placed. */
6774 Mfix * minipool_barrier;
6776 /* Determines if INSN is the start of a jump table. Returns the end
6777 of the TABLE or NULL_RTX. */
6779 is_jump_table (rtx insn)
6783 if (GET_CODE (insn) == JUMP_INSN
6784 && JUMP_LABEL (insn) != NULL
6785 && ((table = next_real_insn (JUMP_LABEL (insn)))
6786 == next_real_insn (insn))
6788 && GET_CODE (table) == JUMP_INSN
6789 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6790 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6796 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6797 #define JUMP_TABLES_IN_TEXT_SECTION 0
6800 static HOST_WIDE_INT
6801 get_jump_table_size (rtx insn)
6803 /* ADDR_VECs only take room if read-only data does into the text
6805 if (JUMP_TABLES_IN_TEXT_SECTION
6806 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6811 rtx body = PATTERN (insn);
6812 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6814 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6820 /* Move a minipool fix MP from its current location to before MAX_MP.
6821 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6822 constraints may need updating. */
6824 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6825 HOST_WIDE_INT max_address)
6827 /* This should never be true and the code below assumes these are
6834 if (max_address < mp->max_address)
6835 mp->max_address = max_address;
6839 if (max_address > max_mp->max_address - mp->fix_size)
6840 mp->max_address = max_mp->max_address - mp->fix_size;
6842 mp->max_address = max_address;
6844 /* Unlink MP from its current position. Since max_mp is non-null,
6845 mp->prev must be non-null. */
6846 mp->prev->next = mp->next;
6847 if (mp->next != NULL)
6848 mp->next->prev = mp->prev;
6850 minipool_vector_tail = mp->prev;
6852 /* Re-insert it before MAX_MP. */
6854 mp->prev = max_mp->prev;
6857 if (mp->prev != NULL)
6858 mp->prev->next = mp;
6860 minipool_vector_head = mp;
6863 /* Save the new entry. */
6866 /* Scan over the preceding entries and adjust their addresses as
6868 while (mp->prev != NULL
6869 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6871 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6878 /* Add a constant to the minipool for a forward reference. Returns the
6879 node added or NULL if the constant will not fit in this pool. */
6881 add_minipool_forward_ref (Mfix *fix)
6883 /* If set, max_mp is the first pool_entry that has a lower
6884 constraint than the one we are trying to add. */
6885 Mnode * max_mp = NULL;
6886 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6889 /* If this fix's address is greater than the address of the first
6890 entry, then we can't put the fix in this pool. We subtract the
6891 size of the current fix to ensure that if the table is fully
6892 packed we still have enough room to insert this value by suffling
6893 the other fixes forwards. */
6894 if (minipool_vector_head &&
6895 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6898 /* Scan the pool to see if a constant with the same value has
6899 already been added. While we are doing this, also note the
6900 location where we must insert the constant if it doesn't already
6902 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6904 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6905 && fix->mode == mp->mode
6906 && (GET_CODE (fix->value) != CODE_LABEL
6907 || (CODE_LABEL_NUMBER (fix->value)
6908 == CODE_LABEL_NUMBER (mp->value)))
6909 && rtx_equal_p (fix->value, mp->value))
6911 /* More than one fix references this entry. */
6913 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6916 /* Note the insertion point if necessary. */
6918 && mp->max_address > max_address)
6921 /* If we are inserting an 8-bytes aligned quantity and
6922 we have not already found an insertion point, then
6923 make sure that all such 8-byte aligned quantities are
6924 placed at the start of the pool. */
6925 if (ARM_DOUBLEWORD_ALIGN
6927 && fix->fix_size == 8
6928 && mp->fix_size != 8)
6931 max_address = mp->max_address;
6935 /* The value is not currently in the minipool, so we need to create
6936 a new entry for it. If MAX_MP is NULL, the entry will be put on
6937 the end of the list since the placement is less constrained than
6938 any existing entry. Otherwise, we insert the new fix before
6939 MAX_MP and, if necessary, adjust the constraints on the other
6941 mp = xmalloc (sizeof (* mp));
6942 mp->fix_size = fix->fix_size;
6943 mp->mode = fix->mode;
6944 mp->value = fix->value;
6946 /* Not yet required for a backwards ref. */
6947 mp->min_address = -65536;
6951 mp->max_address = max_address;
6953 mp->prev = minipool_vector_tail;
6955 if (mp->prev == NULL)
6957 minipool_vector_head = mp;
6958 minipool_vector_label = gen_label_rtx ();
6961 mp->prev->next = mp;
6963 minipool_vector_tail = mp;
6967 if (max_address > max_mp->max_address - mp->fix_size)
6968 mp->max_address = max_mp->max_address - mp->fix_size;
6970 mp->max_address = max_address;
6973 mp->prev = max_mp->prev;
6975 if (mp->prev != NULL)
6976 mp->prev->next = mp;
6978 minipool_vector_head = mp;
6981 /* Save the new entry. */
6984 /* Scan over the preceding entries and adjust their addresses as
6986 while (mp->prev != NULL
6987 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6989 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6997 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6998 HOST_WIDE_INT min_address)
7000 HOST_WIDE_INT offset;
7002 /* This should never be true, and the code below assumes these are
7009 if (min_address > mp->min_address)
7010 mp->min_address = min_address;
7014 /* We will adjust this below if it is too loose. */
7015 mp->min_address = min_address;
7017 /* Unlink MP from its current position. Since min_mp is non-null,
7018 mp->next must be non-null. */
7019 mp->next->prev = mp->prev;
7020 if (mp->prev != NULL)
7021 mp->prev->next = mp->next;
7023 minipool_vector_head = mp->next;
7025 /* Reinsert it after MIN_MP. */
7027 mp->next = min_mp->next;
7029 if (mp->next != NULL)
7030 mp->next->prev = mp;
7032 minipool_vector_tail = mp;
7038 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7040 mp->offset = offset;
7041 if (mp->refcount > 0)
7042 offset += mp->fix_size;
7044 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7045 mp->next->min_address = mp->min_address + mp->fix_size;
7051 /* Add a constant to the minipool for a backward reference. Returns the
7052 node added or NULL if the constant will not fit in this pool.
7054 Note that the code for insertion for a backwards reference can be
7055 somewhat confusing because the calculated offsets for each fix do
7056 not take into account the size of the pool (which is still under
7059 add_minipool_backward_ref (Mfix *fix)
7061 /* If set, min_mp is the last pool_entry that has a lower constraint
7062 than the one we are trying to add. */
7063 Mnode *min_mp = NULL;
7064 /* This can be negative, since it is only a constraint. */
7065 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7068 /* If we can't reach the current pool from this insn, or if we can't
7069 insert this entry at the end of the pool without pushing other
7070 fixes out of range, then we don't try. This ensures that we
7071 can't fail later on. */
7072 if (min_address >= minipool_barrier->address
7073 || (minipool_vector_tail->min_address + fix->fix_size
7074 >= minipool_barrier->address))
7077 /* Scan the pool to see if a constant with the same value has
7078 already been added. While we are doing this, also note the
7079 location where we must insert the constant if it doesn't already
7081 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7083 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7084 && fix->mode == mp->mode
7085 && (GET_CODE (fix->value) != CODE_LABEL
7086 || (CODE_LABEL_NUMBER (fix->value)
7087 == CODE_LABEL_NUMBER (mp->value)))
7088 && rtx_equal_p (fix->value, mp->value)
7089 /* Check that there is enough slack to move this entry to the
7090 end of the table (this is conservative). */
7092 > (minipool_barrier->address
7093 + minipool_vector_tail->offset
7094 + minipool_vector_tail->fix_size)))
7097 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7101 mp->min_address += fix->fix_size;
7104 /* Note the insertion point if necessary. */
7105 if (mp->min_address < min_address)
7107 /* For now, we do not allow the insertion of 8-byte alignment
7108 requiring nodes anywhere but at the start of the pool. */
7109 if (ARM_DOUBLEWORD_ALIGN
7110 && fix->fix_size == 8 && mp->fix_size != 8)
7115 else if (mp->max_address
7116 < minipool_barrier->address + mp->offset + fix->fix_size)
7118 /* Inserting before this entry would push the fix beyond
7119 its maximum address (which can happen if we have
7120 re-located a forwards fix); force the new fix to come
7123 min_address = mp->min_address + fix->fix_size;
7125 /* If we are inserting an 8-bytes aligned quantity and
7126 we have not already found an insertion point, then
7127 make sure that all such 8-byte aligned quantities are
7128 placed at the start of the pool. */
7129 else if (ARM_DOUBLEWORD_ALIGN
7131 && fix->fix_size == 8
7132 && mp->fix_size < 8)
7135 min_address = mp->min_address + fix->fix_size;
7140 /* We need to create a new entry. */
7141 mp = xmalloc (sizeof (* mp));
7142 mp->fix_size = fix->fix_size;
7143 mp->mode = fix->mode;
7144 mp->value = fix->value;
7146 mp->max_address = minipool_barrier->address + 65536;
7148 mp->min_address = min_address;
7153 mp->next = minipool_vector_head;
7155 if (mp->next == NULL)
7157 minipool_vector_tail = mp;
7158 minipool_vector_label = gen_label_rtx ();
7161 mp->next->prev = mp;
7163 minipool_vector_head = mp;
7167 mp->next = min_mp->next;
7171 if (mp->next != NULL)
7172 mp->next->prev = mp;
7174 minipool_vector_tail = mp;
7177 /* Save the new entry. */
7185 /* Scan over the following entries and adjust their offsets. */
7186 while (mp->next != NULL)
7188 if (mp->next->min_address < mp->min_address + mp->fix_size)
7189 mp->next->min_address = mp->min_address + mp->fix_size;
7192 mp->next->offset = mp->offset + mp->fix_size;
7194 mp->next->offset = mp->offset;
7203 assign_minipool_offsets (Mfix *barrier)
7205 HOST_WIDE_INT offset = 0;
7208 minipool_barrier = barrier;
7210 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7212 mp->offset = offset;
7214 if (mp->refcount > 0)
7215 offset += mp->fix_size;
7219 /* Output the literal table */
7221 dump_minipool (rtx scan)
7227 if (ARM_DOUBLEWORD_ALIGN)
7228 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7229 if (mp->refcount > 0 && mp->fix_size == 8)
7237 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7238 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7240 scan = emit_label_after (gen_label_rtx (), scan);
7241 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7242 scan = emit_label_after (minipool_vector_label, scan);
7244 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7246 if (mp->refcount > 0)
7251 ";; Offset %u, min %ld, max %ld ",
7252 (unsigned) mp->offset, (unsigned long) mp->min_address,
7253 (unsigned long) mp->max_address);
7254 arm_print_value (dump_file, mp->value);
7255 fputc ('\n', dump_file);
7258 switch (mp->fix_size)
7260 #ifdef HAVE_consttable_1
7262 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7266 #ifdef HAVE_consttable_2
7268 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7272 #ifdef HAVE_consttable_4
7274 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7278 #ifdef HAVE_consttable_8
7280 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7294 minipool_vector_head = minipool_vector_tail = NULL;
7295 scan = emit_insn_after (gen_consttable_end (), scan);
7296 scan = emit_barrier_after (scan);
7299 /* Return the cost of forcibly inserting a barrier after INSN. */
7301 arm_barrier_cost (rtx insn)
7303 /* Basing the location of the pool on the loop depth is preferable,
7304 but at the moment, the basic block information seems to be
7305 corrupt by this stage of the compilation. */
7307 rtx next = next_nonnote_insn (insn);
7309 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7312 switch (GET_CODE (insn))
7315 /* It will always be better to place the table before the label, rather
7324 return base_cost - 10;
7327 return base_cost + 10;
7331 /* Find the best place in the insn stream in the range
7332 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7333 Create the barrier by inserting a jump and add a new fix entry for
7336 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7338 HOST_WIDE_INT count = 0;
7340 rtx from = fix->insn;
7341 rtx selected = from;
7343 HOST_WIDE_INT selected_address;
7345 HOST_WIDE_INT max_count = max_address - fix->address;
7346 rtx label = gen_label_rtx ();
7348 selected_cost = arm_barrier_cost (from);
7349 selected_address = fix->address;
7351 while (from && count < max_count)
7356 /* This code shouldn't have been called if there was a natural barrier
7358 if (GET_CODE (from) == BARRIER)
7361 /* Count the length of this insn. */
7362 count += get_attr_length (from);
7364 /* If there is a jump table, add its length. */
7365 tmp = is_jump_table (from);
7368 count += get_jump_table_size (tmp);
7370 /* Jump tables aren't in a basic block, so base the cost on
7371 the dispatch insn. If we select this location, we will
7372 still put the pool after the table. */
7373 new_cost = arm_barrier_cost (from);
7375 if (count < max_count && new_cost <= selected_cost)
7378 selected_cost = new_cost;
7379 selected_address = fix->address + count;
7382 /* Continue after the dispatch table. */
7383 from = NEXT_INSN (tmp);
7387 new_cost = arm_barrier_cost (from);
7389 if (count < max_count && new_cost <= selected_cost)
7392 selected_cost = new_cost;
7393 selected_address = fix->address + count;
7396 from = NEXT_INSN (from);
7399 /* Create a new JUMP_INSN that branches around a barrier. */
7400 from = emit_jump_insn_after (gen_jump (label), selected);
7401 JUMP_LABEL (from) = label;
7402 barrier = emit_barrier_after (from);
7403 emit_label_after (label, barrier);
7405 /* Create a minipool barrier entry for the new barrier. */
7406 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7407 new_fix->insn = barrier;
7408 new_fix->address = selected_address;
7409 new_fix->next = fix->next;
7410 fix->next = new_fix;
7415 /* Record that there is a natural barrier in the insn stream at
7418 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7420 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7423 fix->address = address;
7426 if (minipool_fix_head != NULL)
7427 minipool_fix_tail->next = fix;
7429 minipool_fix_head = fix;
7431 minipool_fix_tail = fix;
7434 /* Record INSN, which will need fixing up to load a value from the
7435 minipool. ADDRESS is the offset of the insn since the start of the
7436 function; LOC is a pointer to the part of the insn which requires
7437 fixing; VALUE is the constant that must be loaded, which is of type
7440 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7441 enum machine_mode mode, rtx value)
7443 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7445 #ifdef AOF_ASSEMBLER
7446 /* PIC symbol references need to be converted into offsets into the
7448 /* XXX This shouldn't be done here. */
7449 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7450 value = aof_pic_entry (value);
7451 #endif /* AOF_ASSEMBLER */
7454 fix->address = address;
7457 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7459 fix->forwards = get_attr_pool_range (insn);
7460 fix->backwards = get_attr_neg_pool_range (insn);
7461 fix->minipool = NULL;
7463 /* If an insn doesn't have a range defined for it, then it isn't
7464 expecting to be reworked by this code. Better to abort now than
7465 to generate duff assembly code. */
7466 if (fix->forwards == 0 && fix->backwards == 0)
7469 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7470 So there might be an empty word before the start of the pool.
7471 Hence we reduce the forward range by 4 to allow for this
7473 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7479 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7480 GET_MODE_NAME (mode),
7481 INSN_UID (insn), (unsigned long) address,
7482 -1 * (long)fix->backwards, (long)fix->forwards);
7483 arm_print_value (dump_file, fix->value);
7484 fprintf (dump_file, "\n");
7487 /* Add it to the chain of fixes. */
7490 if (minipool_fix_head != NULL)
7491 minipool_fix_tail->next = fix;
7493 minipool_fix_head = fix;
7495 minipool_fix_tail = fix;
7498 /* Scan INSN and note any of its operands that need fixing.
7499 If DO_PUSHES is false we do not actually push any of the fixups
7500 needed. The function returns TRUE is any fixups were needed/pushed.
7501 This is used by arm_memory_load_p() which needs to know about loads
7502 of constants that will be converted into minipool loads. */
7504 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7506 bool result = false;
7509 extract_insn (insn);
7511 if (!constrain_operands (1))
7512 fatal_insn_not_found (insn);
7514 if (recog_data.n_alternatives == 0)
7517 /* Fill in recog_op_alt with information about the constraints of this insn. */
7518 preprocess_constraints ();
7520 for (opno = 0; opno < recog_data.n_operands; opno++)
7522 /* Things we need to fix can only occur in inputs. */
7523 if (recog_data.operand_type[opno] != OP_IN)
7526 /* If this alternative is a memory reference, then any mention
7527 of constants in this alternative is really to fool reload
7528 into allowing us to accept one there. We need to fix them up
7529 now so that we output the right code. */
7530 if (recog_op_alt[opno][which_alternative].memory_ok)
7532 rtx op = recog_data.operand[opno];
7534 if (CONSTANT_P (op))
7537 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7538 recog_data.operand_mode[opno], op);
7541 else if (GET_CODE (op) == MEM
7542 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7543 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7547 rtx cop = avoid_constant_pool_reference (op);
7549 /* Casting the address of something to a mode narrower
7550 than a word can cause avoid_constant_pool_reference()
7551 to return the pool reference itself. That's no good to
7552 us here. Lets just hope that we can use the
7553 constant pool value directly. */
7555 cop = get_pool_constant (XEXP (op, 0));
7557 push_minipool_fix (insn, address,
7558 recog_data.operand_loc[opno],
7559 recog_data.operand_mode[opno], cop);
7570 /* Gcc puts the pool in the wrong place for ARM, since we can only
7571 load addresses a limited distance around the pc. We do some
7572 special munging to move the constant pool values to the correct
7573 point in the code. */
7578 HOST_WIDE_INT address = 0;
7581 minipool_fix_head = minipool_fix_tail = NULL;
7583 /* The first insn must always be a note, or the code below won't
7584 scan it properly. */
7585 insn = get_insns ();
7586 if (GET_CODE (insn) != NOTE)
7589 /* Scan all the insns and record the operands that will need fixing. */
7590 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7592 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7593 && (arm_cirrus_insn_p (insn)
7594 || GET_CODE (insn) == JUMP_INSN
7595 || arm_memory_load_p (insn)))
7596 cirrus_reorg (insn);
7598 if (GET_CODE (insn) == BARRIER)
7599 push_minipool_barrier (insn, address);
7600 else if (INSN_P (insn))
7604 note_invalid_constants (insn, address, true);
7605 address += get_attr_length (insn);
7607 /* If the insn is a vector jump, add the size of the table
7608 and skip the table. */
7609 if ((table = is_jump_table (insn)) != NULL)
7611 address += get_jump_table_size (table);
7617 fix = minipool_fix_head;
7619 /* Now scan the fixups and perform the required changes. */
7624 Mfix * last_added_fix;
7625 Mfix * last_barrier = NULL;
7628 /* Skip any further barriers before the next fix. */
7629 while (fix && GET_CODE (fix->insn) == BARRIER)
7632 /* No more fixes. */
7636 last_added_fix = NULL;
7638 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7640 if (GET_CODE (ftmp->insn) == BARRIER)
7642 if (ftmp->address >= minipool_vector_head->max_address)
7645 last_barrier = ftmp;
7647 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7650 last_added_fix = ftmp; /* Keep track of the last fix added. */
7653 /* If we found a barrier, drop back to that; any fixes that we
7654 could have reached but come after the barrier will now go in
7655 the next mini-pool. */
7656 if (last_barrier != NULL)
7658 /* Reduce the refcount for those fixes that won't go into this
7660 for (fdel = last_barrier->next;
7661 fdel && fdel != ftmp;
7664 fdel->minipool->refcount--;
7665 fdel->minipool = NULL;
7668 ftmp = last_barrier;
7672 /* ftmp is first fix that we can't fit into this pool and
7673 there no natural barriers that we could use. Insert a
7674 new barrier in the code somewhere between the previous
7675 fix and this one, and arrange to jump around it. */
7676 HOST_WIDE_INT max_address;
7678 /* The last item on the list of fixes must be a barrier, so
7679 we can never run off the end of the list of fixes without
7680 last_barrier being set. */
7684 max_address = minipool_vector_head->max_address;
7685 /* Check that there isn't another fix that is in range that
7686 we couldn't fit into this pool because the pool was
7687 already too large: we need to put the pool before such an
7689 if (ftmp->address < max_address)
7690 max_address = ftmp->address;
7692 last_barrier = create_fix_barrier (last_added_fix, max_address);
7695 assign_minipool_offsets (last_barrier);
7699 if (GET_CODE (ftmp->insn) != BARRIER
7700 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7707 /* Scan over the fixes we have identified for this pool, fixing them
7708 up and adding the constants to the pool itself. */
7709 for (this_fix = fix; this_fix && ftmp != this_fix;
7710 this_fix = this_fix->next)
7711 if (GET_CODE (this_fix->insn) != BARRIER)
7714 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7715 minipool_vector_label),
7716 this_fix->minipool->offset);
7717 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7720 dump_minipool (last_barrier->insn);
7724 /* From now on we must synthesize any constants that we can't handle
7725 directly. This can happen if the RTL gets split during final
7726 instruction generation. */
7727 after_arm_reorg = 1;
7729 /* Free the minipool memory. */
7730 obstack_free (&minipool_obstack, minipool_startobj);
7733 /* Routines to output assembly language. */
7735 /* If the rtx is the correct value then return the string of the number.
7736 In this way we can ensure that valid double constants are generated even
7737 when cross compiling. */
7739 fp_immediate_constant (rtx x)
7744 if (!fp_consts_inited)
7747 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7748 for (i = 0; i < 8; i++)
7749 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7750 return strings_fp[i];
7755 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7757 fp_const_from_val (REAL_VALUE_TYPE *r)
7761 if (!fp_consts_inited)
7764 for (i = 0; i < 8; i++)
7765 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7766 return strings_fp[i];
7771 /* Output the operands of a LDM/STM instruction to STREAM.
7772 MASK is the ARM register set mask of which only bits 0-15 are important.
7773 REG is the base register, either the frame pointer or the stack pointer,
7774 INSTR is the possibly suffixed load or store instruction. */
7776 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7779 int not_first = FALSE;
7781 fputc ('\t', stream);
7782 asm_fprintf (stream, instr, reg);
7783 fputs (", {", stream);
7785 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7786 if (mask & (1 << i))
7789 fprintf (stream, ", ");
7791 asm_fprintf (stream, "%r", i);
7795 fprintf (stream, "}");
7797 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7798 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7799 Strictly speaking the instruction would be unpredicatble only if
7800 we were writing back the base register as well, but since we never
7801 want to generate an LDM type 2 instruction (register bank switching)
7802 which is what you get if the PC is not being loaded, we do not need
7803 to check for writeback. */
7804 if (! TARGET_APCS_32
7805 && ((mask & (1 << PC_REGNUM)) != 0))
7806 fprintf (stream, "^");
7808 fprintf (stream, "\n");
7812 /* Output a FLDMX instruction to STREAM.
7813 BASE if the register containing the address.
7814 REG and COUNT specify the register range.
7815 Extra registers may be added to avoid hardware bugs. */
7818 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7822 /* Workaround ARM10 VFPr1 bug. */
7823 if (count == 2 && !arm_arch6)
7830 fputc ('\t', stream);
7831 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7833 for (i = reg; i < reg + count; i++)
7836 fputs (", ", stream);
7837 asm_fprintf (stream, "d%d", i);
7839 fputs ("}\n", stream);
7844 /* Output the assembly for a store multiple. */
7847 vfp_output_fstmx (rtx * operands)
7854 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7855 p = strlen (pattern);
7857 if (GET_CODE (operands[1]) != REG)
7860 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7861 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7863 p += sprintf (&pattern[p], ", d%d", base + i);
7865 strcpy (&pattern[p], "}");
7867 output_asm_insn (pattern, operands);
7872 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7873 number of bytes pushed. */
7876 vfp_emit_fstmx (int base_reg, int count)
7883 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7884 register pairs are stored by a store multiple insn. We avoid this
7885 by pushing an extra pair. */
7886 if (count == 2 && !arm_arch6)
7888 if (base_reg == LAST_VFP_REGNUM - 3)
7893 /* ??? The frame layout is implementation defined. We describe
7894 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7895 We really need some way of representing the whole block so that the
7896 unwinder can figure it out at runtime. */
7897 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7898 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7900 reg = gen_rtx_REG (DFmode, base_reg);
7904 = gen_rtx_SET (VOIDmode,
7905 gen_rtx_MEM (BLKmode,
7906 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7907 gen_rtx_UNSPEC (BLKmode,
7911 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7912 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7913 GEN_INT (-(count * 8 + 4))));
7914 RTX_FRAME_RELATED_P (tmp) = 1;
7915 XVECEXP (dwarf, 0, 0) = tmp;
7917 tmp = gen_rtx_SET (VOIDmode,
7918 gen_rtx_MEM (DFmode, stack_pointer_rtx),
7920 RTX_FRAME_RELATED_P (tmp) = 1;
7921 XVECEXP (dwarf, 0, 1) = tmp;
7923 for (i = 1; i < count; i++)
7925 reg = gen_rtx_REG (DFmode, base_reg);
7927 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7929 tmp = gen_rtx_SET (VOIDmode,
7930 gen_rtx_MEM (DFmode,
7931 gen_rtx_PLUS (SImode,
7935 RTX_FRAME_RELATED_P (tmp) = 1;
7936 XVECEXP (dwarf, 0, i + 1) = tmp;
7939 par = emit_insn (par);
7940 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7942 RTX_FRAME_RELATED_P (par) = 1;
7944 return count * 8 + 4;
7948 /* Output a 'call' insn. */
7950 output_call (rtx *operands)
7952 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7954 if (REGNO (operands[0]) == LR_REGNUM)
7956 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7957 output_asm_insn ("mov%?\t%0, %|lr", operands);
7960 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7962 if (TARGET_INTERWORK)
7963 output_asm_insn ("bx%?\t%0", operands);
7965 output_asm_insn ("mov%?\t%|pc, %0", operands);
7970 /* Output a 'call' insn that is a reference in memory. */
7972 output_call_mem (rtx *operands)
7974 if (TARGET_INTERWORK)
7976 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7977 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7978 output_asm_insn ("bx%?\t%|ip", operands);
7980 else if (regno_use_in (LR_REGNUM, operands[0]))
7982 /* LR is used in the memory address. We load the address in the
7983 first instruction. It's safe to use IP as the target of the
7984 load since the call will kill it anyway. */
7985 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7986 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7987 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7991 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7992 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7999 /* Output a move from arm registers to an fpa registers.
8000 OPERANDS[0] is an fpa register.
8001 OPERANDS[1] is the first registers of an arm register pair. */
8003 output_mov_long_double_fpa_from_arm (rtx *operands)
8005 int arm_reg0 = REGNO (operands[1]);
8008 if (arm_reg0 == IP_REGNUM)
8011 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8012 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8013 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8015 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8016 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8021 /* Output a move from an fpa register to arm registers.
8022 OPERANDS[0] is the first registers of an arm register pair.
8023 OPERANDS[1] is an fpa register. */
8025 output_mov_long_double_arm_from_fpa (rtx *operands)
8027 int arm_reg0 = REGNO (operands[0]);
8030 if (arm_reg0 == IP_REGNUM)
8033 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8034 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8035 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8037 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8038 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8042 /* Output a move from arm registers to arm registers of a long double
8043 OPERANDS[0] is the destination.
8044 OPERANDS[1] is the source. */
8046 output_mov_long_double_arm_from_arm (rtx *operands)
8048 /* We have to be careful here because the two might overlap. */
8049 int dest_start = REGNO (operands[0]);
8050 int src_start = REGNO (operands[1]);
8054 if (dest_start < src_start)
8056 for (i = 0; i < 3; i++)
8058 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8059 ops[1] = gen_rtx_REG (SImode, src_start + i);
8060 output_asm_insn ("mov%?\t%0, %1", ops);
8065 for (i = 2; i >= 0; i--)
8067 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8068 ops[1] = gen_rtx_REG (SImode, src_start + i);
8069 output_asm_insn ("mov%?\t%0, %1", ops);
8077 /* Output a move from arm registers to an fpa registers.
8078 OPERANDS[0] is an fpa register.
8079 OPERANDS[1] is the first registers of an arm register pair. */
8081 output_mov_double_fpa_from_arm (rtx *operands)
8083 int arm_reg0 = REGNO (operands[1]);
8086 if (arm_reg0 == IP_REGNUM)
8089 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8090 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8091 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8092 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8096 /* Output a move from an fpa register to arm registers.
8097 OPERANDS[0] is the first registers of an arm register pair.
8098 OPERANDS[1] is an fpa register. */
8100 output_mov_double_arm_from_fpa (rtx *operands)
8102 int arm_reg0 = REGNO (operands[0]);
8105 if (arm_reg0 == IP_REGNUM)
8108 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8109 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8110 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8111 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8115 /* Output a move between double words.
8116 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8117 or MEM<-REG and all MEMs must be offsettable addresses. */
8119 output_move_double (rtx *operands)
8121 enum rtx_code code0 = GET_CODE (operands[0]);
8122 enum rtx_code code1 = GET_CODE (operands[1]);
8127 int reg0 = REGNO (operands[0]);
8129 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8133 int reg1 = REGNO (operands[1]);
8134 if (reg1 == IP_REGNUM)
8137 /* Ensure the second source is not overwritten. */
8138 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8139 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8141 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8143 else if (code1 == CONST_VECTOR)
8145 HOST_WIDE_INT hint = 0;
8147 switch (GET_MODE (operands[1]))
8150 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8151 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8155 if (BYTES_BIG_ENDIAN)
8157 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8159 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8163 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8165 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8168 otherops[1] = GEN_INT (hint);
8171 if (BYTES_BIG_ENDIAN)
8173 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8175 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8179 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8181 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8184 operands[1] = GEN_INT (hint);
8188 if (BYTES_BIG_ENDIAN)
8190 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8192 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8194 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8196 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8200 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8202 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8204 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8206 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8209 otherops[1] = GEN_INT (hint);
8212 if (BYTES_BIG_ENDIAN)
8214 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8216 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8218 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8220 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8224 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8226 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8228 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8230 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8233 operands[1] = GEN_INT (hint);
8239 output_mov_immediate (operands);
8240 output_mov_immediate (otherops);
8242 else if (code1 == CONST_DOUBLE)
8244 if (GET_MODE (operands[1]) == DFmode)
8249 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8250 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8251 otherops[1] = GEN_INT (l[1]);
8252 operands[1] = GEN_INT (l[0]);
8254 else if (GET_MODE (operands[1]) != VOIDmode)
8256 else if (WORDS_BIG_ENDIAN)
8258 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8259 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8263 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8264 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8267 output_mov_immediate (operands);
8268 output_mov_immediate (otherops);
8270 else if (code1 == CONST_INT)
8272 #if HOST_BITS_PER_WIDE_INT > 32
8273 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8274 what the upper word is. */
8275 if (WORDS_BIG_ENDIAN)
8277 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8278 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8282 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8283 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8286 /* Sign extend the intval into the high-order word. */
8287 if (WORDS_BIG_ENDIAN)
8289 otherops[1] = operands[1];
8290 operands[1] = (INTVAL (operands[1]) < 0
8291 ? constm1_rtx : const0_rtx);
8294 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8296 output_mov_immediate (otherops);
8297 output_mov_immediate (operands);
8299 else if (code1 == MEM)
8301 switch (GET_CODE (XEXP (operands[1], 0)))
8304 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8308 abort (); /* Should never happen now. */
8312 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8316 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8320 abort (); /* Should never happen now. */
8325 output_asm_insn ("adr%?\t%0, %1", operands);
8326 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8330 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8331 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8333 otherops[0] = operands[0];
8334 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8335 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8337 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8339 if (GET_CODE (otherops[2]) == CONST_INT)
8341 switch ((int) INTVAL (otherops[2]))
8344 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8347 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8350 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8354 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8355 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8357 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8360 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8363 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8365 return "ldm%?ia\t%0, %M0";
8369 otherops[1] = adjust_address (operands[1], SImode, 4);
8370 /* Take care of overlapping base/data reg. */
8371 if (reg_mentioned_p (operands[0], operands[1]))
8373 output_asm_insn ("ldr%?\t%0, %1", otherops);
8374 output_asm_insn ("ldr%?\t%0, %1", operands);
8378 output_asm_insn ("ldr%?\t%0, %1", operands);
8379 output_asm_insn ("ldr%?\t%0, %1", otherops);
8385 abort (); /* Constraints should prevent this. */
8387 else if (code0 == MEM && code1 == REG)
8389 if (REGNO (operands[1]) == IP_REGNUM)
8392 switch (GET_CODE (XEXP (operands[0], 0)))
8395 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8399 abort (); /* Should never happen now. */
8403 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8407 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8411 abort (); /* Should never happen now. */
8415 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
8417 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8420 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8424 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8428 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8435 otherops[0] = adjust_address (operands[0], SImode, 4);
8436 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8437 output_asm_insn ("str%?\t%1, %0", operands);
8438 output_asm_insn ("str%?\t%1, %0", otherops);
8442 /* Constraints should prevent this. */
8449 /* Output an arbitrary MOV reg, #n.
8450 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8452 output_mov_immediate (rtx *operands)
8454 HOST_WIDE_INT n = INTVAL (operands[1]);
8456 /* Try to use one MOV. */
8457 if (const_ok_for_arm (n))
8458 output_asm_insn ("mov%?\t%0, %1", operands);
8460 /* Try to use one MVN. */
8461 else if (const_ok_for_arm (~n))
8463 operands[1] = GEN_INT (~n);
8464 output_asm_insn ("mvn%?\t%0, %1", operands);
8471 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8472 for (i = 0; i < 32; i++)
8476 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8477 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8479 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8485 /* Output an ADD r, s, #n where n may be too big for one instruction.
8486 If adding zero to one register, output nothing. */
8488 output_add_immediate (rtx *operands)
8490 HOST_WIDE_INT n = INTVAL (operands[2]);
8492 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8495 output_multi_immediate (operands,
8496 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8499 output_multi_immediate (operands,
8500 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8507 /* Output a multiple immediate operation.
8508 OPERANDS is the vector of operands referred to in the output patterns.
8509 INSTR1 is the output pattern to use for the first constant.
8510 INSTR2 is the output pattern to use for subsequent constants.
8511 IMMED_OP is the index of the constant slot in OPERANDS.
8512 N is the constant value. */
8514 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8515 int immed_op, HOST_WIDE_INT n)
8517 #if HOST_BITS_PER_WIDE_INT > 32
8523 /* Quick and easy output. */
8524 operands[immed_op] = const0_rtx;
8525 output_asm_insn (instr1, operands);
8530 const char * instr = instr1;
8532 /* Note that n is never zero here (which would give no output). */
8533 for (i = 0; i < 32; i += 2)
8537 operands[immed_op] = GEN_INT (n & (255 << i));
8538 output_asm_insn (instr, operands);
8548 /* Return the appropriate ARM instruction for the operation code.
8549 The returned result should not be overwritten. OP is the rtx of the
8550 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8553 arithmetic_instr (rtx op, int shift_first_arg)
8555 switch (GET_CODE (op))
8561 return shift_first_arg ? "rsb" : "sub";
8577 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8578 for the operation code. The returned result should not be overwritten.
8579 OP is the rtx code of the shift.
8580 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8583 shift_op (rtx op, HOST_WIDE_INT *amountp)
8586 enum rtx_code code = GET_CODE (op);
8588 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8590 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8591 *amountp = INTVAL (XEXP (op, 1));
8614 /* We never have to worry about the amount being other than a
8615 power of 2, since this case can never be reloaded from a reg. */
8617 *amountp = int_log2 (*amountp);
8628 /* This is not 100% correct, but follows from the desire to merge
8629 multiplication by a power of 2 with the recognizer for a
8630 shift. >=32 is not a valid shift for "asl", so we must try and
8631 output a shift that produces the correct arithmetical result.
8632 Using lsr #32 is identical except for the fact that the carry bit
8633 is not set correctly if we set the flags; but we never use the
8634 carry bit from such an operation, so we can ignore that. */
8635 if (code == ROTATERT)
8636 /* Rotate is just modulo 32. */
8638 else if (*amountp != (*amountp & 31))
8645 /* Shifts of 0 are no-ops. */
8653 /* Obtain the shift from the POWER of two. */
8655 static HOST_WIDE_INT
8656 int_log2 (HOST_WIDE_INT power)
8658 HOST_WIDE_INT shift = 0;
8660 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8670 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8671 /bin/as is horribly restrictive. */
8672 #define MAX_ASCII_LEN 51
8675 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8680 fputs ("\t.ascii\t\"", stream);
8682 for (i = 0; i < len; i++)
8686 if (len_so_far >= MAX_ASCII_LEN)
8688 fputs ("\"\n\t.ascii\t\"", stream);
8695 fputs ("\\t", stream);
8700 fputs ("\\f", stream);
8705 fputs ("\\b", stream);
8710 fputs ("\\r", stream);
8714 case TARGET_NEWLINE:
8715 fputs ("\\n", stream);
8717 if ((c >= ' ' && c <= '~')
8719 /* This is a good place for a line break. */
8720 len_so_far = MAX_ASCII_LEN;
8727 putc ('\\', stream);
8732 if (c >= ' ' && c <= '~')
8739 fprintf (stream, "\\%03o", c);
8746 fputs ("\"\n", stream);
8749 /* Compute the register sabe mask for registers 0 through 12
8750 inclusive. This code is used by arm_compute_save_reg_mask. */
8751 static unsigned long
8752 arm_compute_save_reg0_reg12_mask (void)
8754 unsigned long func_type = arm_current_func_type ();
8755 unsigned int save_reg_mask = 0;
8758 if (IS_INTERRUPT (func_type))
8760 unsigned int max_reg;
8761 /* Interrupt functions must not corrupt any registers,
8762 even call clobbered ones. If this is a leaf function
8763 we can just examine the registers used by the RTL, but
8764 otherwise we have to assume that whatever function is
8765 called might clobber anything, and so we have to save
8766 all the call-clobbered registers as well. */
8767 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8768 /* FIQ handlers have registers r8 - r12 banked, so
8769 we only need to check r0 - r7, Normal ISRs only
8770 bank r14 and r15, so we must check up to r12.
8771 r13 is the stack pointer which is always preserved,
8772 so we do not need to consider it here. */
8777 for (reg = 0; reg <= max_reg; reg++)
8778 if (regs_ever_live[reg]
8779 || (! current_function_is_leaf && call_used_regs [reg]))
8780 save_reg_mask |= (1 << reg);
8784 /* In the normal case we only need to save those registers
8785 which are call saved and which are used by this function. */
8786 for (reg = 0; reg <= 10; reg++)
8787 if (regs_ever_live[reg] && ! call_used_regs [reg])
8788 save_reg_mask |= (1 << reg);
8790 /* Handle the frame pointer as a special case. */
8791 if (! TARGET_APCS_FRAME
8792 && ! frame_pointer_needed
8793 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8794 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8795 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8797 /* If we aren't loading the PIC register,
8798 don't stack it even though it may be live. */
8800 && ! TARGET_SINGLE_PIC_BASE
8801 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8802 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8805 return save_reg_mask;
8808 /* Compute a bit mask of which registers need to be
8809 saved on the stack for the current function. */
8811 static unsigned long
8812 arm_compute_save_reg_mask (void)
8814 unsigned int save_reg_mask = 0;
8815 unsigned long func_type = arm_current_func_type ();
8817 if (IS_NAKED (func_type))
8818 /* This should never really happen. */
8821 /* If we are creating a stack frame, then we must save the frame pointer,
8822 IP (which will hold the old stack pointer), LR and the PC. */
8823 if (frame_pointer_needed)
8825 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8830 /* Volatile functions do not return, so there
8831 is no need to save any other registers. */
8832 if (IS_VOLATILE (func_type))
8833 return save_reg_mask;
8835 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8837 /* Decide if we need to save the link register.
8838 Interrupt routines have their own banked link register,
8839 so they never need to save it.
8840 Otherwise if we do not use the link register we do not need to save
8841 it. If we are pushing other registers onto the stack however, we
8842 can save an instruction in the epilogue by pushing the link register
8843 now and then popping it back into the PC. This incurs extra memory
8844 accesses though, so we only do it when optimizing for size, and only
8845 if we know that we will not need a fancy return sequence. */
8846 if (regs_ever_live [LR_REGNUM]
8849 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8850 save_reg_mask |= 1 << LR_REGNUM;
8852 if (cfun->machine->lr_save_eliminated)
8853 save_reg_mask &= ~ (1 << LR_REGNUM);
8855 if (TARGET_REALLY_IWMMXT
8856 && ((bit_count (save_reg_mask)
8857 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8861 /* The total number of registers that are going to be pushed
8862 onto the stack is odd. We need to ensure that the stack
8863 is 64-bit aligned before we start to save iWMMXt registers,
8864 and also before we start to create locals. (A local variable
8865 might be a double or long long which we will load/store using
8866 an iWMMXt instruction). Therefore we need to push another
8867 ARM register, so that the stack will be 64-bit aligned. We
8868 try to avoid using the arg registers (r0 -r3) as they might be
8869 used to pass values in a tail call. */
8870 for (reg = 4; reg <= 12; reg++)
8871 if ((save_reg_mask & (1 << reg)) == 0)
8875 save_reg_mask |= (1 << reg);
8878 cfun->machine->sibcall_blocked = 1;
8879 save_reg_mask |= (1 << 3);
8883 return save_reg_mask;
8887 /* Return the number of bytes required to save VFP registers. */
8889 arm_get_vfp_saved_size (void)
8896 /* Space for saved VFP registers. */
8897 if (TARGET_HARD_FLOAT && TARGET_VFP)
8900 for (regno = FIRST_VFP_REGNUM;
8901 regno < LAST_VFP_REGNUM;
8904 if ((!regs_ever_live[regno] || call_used_regs[regno])
8905 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8909 /* Workaround ARM10 VFPr1 bug. */
8910 if (count == 2 && !arm_arch6)
8912 saved += count * 8 + 4;
8921 if (count == 2 && !arm_arch6)
8923 saved += count * 8 + 4;
8930 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8931 everything bar the final return instruction. */
8933 output_return_instruction (rtx operand, int really_return, int reverse)
8935 char conditional[10];
8938 unsigned long live_regs_mask;
8939 unsigned long func_type;
8940 arm_stack_offsets *offsets;
8942 func_type = arm_current_func_type ();
8944 if (IS_NAKED (func_type))
8947 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8949 /* If this function was declared non-returning, and we have
8950 found a tail call, then we have to trust that the called
8951 function won't return. */
8956 /* Otherwise, trap an attempted return by aborting. */
8958 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8960 assemble_external_libcall (ops[1]);
8961 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8967 if (current_function_calls_alloca && !really_return)
8970 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8972 return_used_this_function = 1;
8974 live_regs_mask = arm_compute_save_reg_mask ();
8978 const char * return_reg;
8980 /* If we do not have any special requirements for function exit
8981 (eg interworking, or ISR) then we can load the return address
8982 directly into the PC. Otherwise we must load it into LR. */
8984 && ! TARGET_INTERWORK)
8985 return_reg = reg_names[PC_REGNUM];
8987 return_reg = reg_names[LR_REGNUM];
8989 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8991 /* There are three possible reasons for the IP register
8992 being saved. 1) a stack frame was created, in which case
8993 IP contains the old stack pointer, or 2) an ISR routine
8994 corrupted it, or 3) it was saved to align the stack on
8995 iWMMXt. In case 1, restore IP into SP, otherwise just
8997 if (frame_pointer_needed)
8999 live_regs_mask &= ~ (1 << IP_REGNUM);
9000 live_regs_mask |= (1 << SP_REGNUM);
9004 if (! IS_INTERRUPT (func_type)
9005 && ! TARGET_REALLY_IWMMXT)
9010 /* On some ARM architectures it is faster to use LDR rather than
9011 LDM to load a single register. On other architectures, the
9012 cost is the same. In 26 bit mode, or for exception handlers,
9013 we have to use LDM to load the PC so that the CPSR is also
9015 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9017 if (live_regs_mask == (unsigned int)(1 << reg))
9020 if (reg <= LAST_ARM_REGNUM
9021 && (reg != LR_REGNUM
9023 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
9025 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9026 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9033 /* Generate the load multiple instruction to restore the
9034 registers. Note we can get here, even if
9035 frame_pointer_needed is true, but only if sp already
9036 points to the base of the saved core registers. */
9037 if (live_regs_mask & (1 << SP_REGNUM))
9039 unsigned HOST_WIDE_INT stack_adjust;
9041 offsets = arm_get_frame_offsets ();
9042 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9043 if (stack_adjust != 0 && stack_adjust != 4)
9046 if (stack_adjust && arm_arch5)
9047 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9050 /* If we can't use ldmib (SA110 bug), then try to pop r3
9053 live_regs_mask |= 1 << 3;
9054 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9058 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9060 p = instr + strlen (instr);
9062 for (reg = 0; reg <= SP_REGNUM; reg++)
9063 if (live_regs_mask & (1 << reg))
9065 int l = strlen (reg_names[reg]);
9071 memcpy (p, ", ", 2);
9075 memcpy (p, "%|", 2);
9076 memcpy (p + 2, reg_names[reg], l);
9080 if (live_regs_mask & (1 << LR_REGNUM))
9082 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9083 /* Decide if we need to add the ^ symbol to the end of the
9084 register list. This causes the saved condition codes
9085 register to be copied into the current condition codes
9086 register. We do the copy if we are conforming to the 32-bit
9087 ABI and this is an interrupt function, or if we are
9088 conforming to the 26-bit ABI. There is a special case for
9089 the 26-bit ABI however, which is if we are writing back the
9090 stack pointer but not loading the PC. In this case adding
9091 the ^ symbol would create a type 2 LDM instruction, where
9092 writeback is UNPREDICTABLE. We are safe in leaving the ^
9093 character off in this case however, since the actual return
9094 instruction will be a MOVS which will restore the CPSR. */
9095 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
9096 || (! TARGET_APCS_32 && really_return))
9103 output_asm_insn (instr, & operand);
9105 /* See if we need to generate an extra instruction to
9106 perform the actual function return. */
9108 && func_type != ARM_FT_INTERWORKED
9109 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9111 /* The return has already been handled
9112 by loading the LR into the PC. */
9119 switch ((int) ARM_FUNC_TYPE (func_type))
9123 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9126 case ARM_FT_INTERWORKED:
9127 sprintf (instr, "bx%s\t%%|lr", conditional);
9130 case ARM_FT_EXCEPTION:
9131 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9135 /* ARMv5 implementations always provide BX, so interworking
9136 is the default unless APCS-26 is in use. */
9137 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
9138 sprintf (instr, "bx%s\t%%|lr", conditional);
9140 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
9141 conditional, TARGET_APCS_32 ? "" : "s");
9145 output_asm_insn (instr, & operand);
9151 /* Write the function name into the code section, directly preceding
9152 the function prologue.
9154 Code will be output similar to this:
9156 .ascii "arm_poke_function_name", 0
9159 .word 0xff000000 + (t1 - t0)
9160 arm_poke_function_name
9162 stmfd sp!, {fp, ip, lr, pc}
9165 When performing a stack backtrace, code can inspect the value
9166 of 'pc' stored at 'fp' + 0. If the trace function then looks
9167 at location pc - 12 and the top 8 bits are set, then we know
9168 that there is a function name embedded immediately preceding this
9169 location and has length ((pc[-3]) & 0xff000000).
9171 We assume that pc is declared as a pointer to an unsigned long.
9173 It is of no benefit to output the function name if we are assembling
9174 a leaf function. These function types will not contain a stack
9175 backtrace structure, therefore it is not possible to determine the
9178 arm_poke_function_name (FILE *stream, const char *name)
9180 unsigned long alignlength;
9181 unsigned long length;
9184 length = strlen (name) + 1;
9185 alignlength = ROUND_UP_WORD (length);
9187 ASM_OUTPUT_ASCII (stream, name, length);
9188 ASM_OUTPUT_ALIGN (stream, 2);
9189 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9190 assemble_aligned_integer (UNITS_PER_WORD, x);
9193 /* Place some comments into the assembler stream
9194 describing the current function. */
9196 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9198 unsigned long func_type;
9202 thumb_output_function_prologue (f, frame_size);
9207 if (arm_ccfsm_state || arm_target_insn)
9210 func_type = arm_current_func_type ();
9212 switch ((int) ARM_FUNC_TYPE (func_type))
9217 case ARM_FT_INTERWORKED:
9218 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9220 case ARM_FT_EXCEPTION_HANDLER:
9221 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9224 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9227 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9229 case ARM_FT_EXCEPTION:
9230 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9234 if (IS_NAKED (func_type))
9235 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9237 if (IS_VOLATILE (func_type))
9238 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9240 if (IS_NESTED (func_type))
9241 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9243 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9244 current_function_args_size,
9245 current_function_pretend_args_size, frame_size);
9247 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9248 frame_pointer_needed,
9249 cfun->machine->uses_anonymous_args);
9251 if (cfun->machine->lr_save_eliminated)
9252 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9254 #ifdef AOF_ASSEMBLER
9256 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9259 return_used_this_function = 0;
9263 arm_output_epilogue (rtx sibling)
9266 unsigned long saved_regs_mask;
9267 unsigned long func_type;
9268 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9269 frame that is $fp + 4 for a non-variadic function. */
9270 int floats_offset = 0;
9272 FILE * f = asm_out_file;
9273 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9274 unsigned int lrm_count = 0;
9275 int really_return = (sibling == NULL);
9277 arm_stack_offsets *offsets;
9279 /* If we have already generated the return instruction
9280 then it is futile to generate anything else. */
9281 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9284 func_type = arm_current_func_type ();
9286 if (IS_NAKED (func_type))
9287 /* Naked functions don't have epilogues. */
9290 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9294 /* A volatile function should never return. Call abort. */
9295 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9296 assemble_external_libcall (op);
9297 output_asm_insn ("bl\t%a0", &op);
9302 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9304 /* If we are throwing an exception, then we really must
9305 be doing a return, so we can't tail-call. */
9308 offsets = arm_get_frame_offsets ();
9309 saved_regs_mask = arm_compute_save_reg_mask ();
9312 lrm_count = bit_count (saved_regs_mask);
9314 floats_offset = offsets->saved_args;
9315 /* Compute how far away the floats will be. */
9316 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9317 if (saved_regs_mask & (1 << reg))
9320 if (frame_pointer_needed)
9322 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9323 int vfp_offset = offsets->frame;
9325 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9327 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9328 if (regs_ever_live[reg] && !call_used_regs[reg])
9330 floats_offset += 12;
9331 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9332 reg, FP_REGNUM, floats_offset - vfp_offset);
9337 start_reg = LAST_FPA_REGNUM;
9339 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9341 if (regs_ever_live[reg] && !call_used_regs[reg])
9343 floats_offset += 12;
9345 /* We can't unstack more than four registers at once. */
9346 if (start_reg - reg == 3)
9348 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9349 reg, FP_REGNUM, floats_offset - vfp_offset);
9350 start_reg = reg - 1;
9355 if (reg != start_reg)
9356 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9357 reg + 1, start_reg - reg,
9358 FP_REGNUM, floats_offset - vfp_offset);
9359 start_reg = reg - 1;
9363 /* Just in case the last register checked also needs unstacking. */
9364 if (reg != start_reg)
9365 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9366 reg + 1, start_reg - reg,
9367 FP_REGNUM, floats_offset - vfp_offset);
9370 if (TARGET_HARD_FLOAT && TARGET_VFP)
9374 /* The fldmx insn does not have base+offset addressing modes,
9375 so we use IP to hold the address. */
9376 saved_size = arm_get_vfp_saved_size ();
9380 floats_offset += saved_size;
9381 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9382 FP_REGNUM, floats_offset - vfp_offset);
9384 start_reg = FIRST_VFP_REGNUM;
9385 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9387 if ((!regs_ever_live[reg] || call_used_regs[reg])
9388 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9390 if (start_reg != reg)
9391 arm_output_fldmx (f, IP_REGNUM,
9392 (start_reg - FIRST_VFP_REGNUM) / 2,
9393 (reg - start_reg) / 2);
9394 start_reg = reg + 2;
9397 if (start_reg != reg)
9398 arm_output_fldmx (f, IP_REGNUM,
9399 (start_reg - FIRST_VFP_REGNUM) / 2,
9400 (reg - start_reg) / 2);
9405 /* The frame pointer is guaranteed to be non-double-word aligned.
9406 This is because it is set to (old_stack_pointer - 4) and the
9407 old_stack_pointer was double word aligned. Thus the offset to
9408 the iWMMXt registers to be loaded must also be non-double-word
9409 sized, so that the resultant address *is* double-word aligned.
9410 We can ignore floats_offset since that was already included in
9411 the live_regs_mask. */
9412 lrm_count += (lrm_count % 2 ? 2 : 1);
9414 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9415 if (regs_ever_live[reg] && !call_used_regs[reg])
9417 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9418 reg, FP_REGNUM, lrm_count * 4);
9423 /* saved_regs_mask should contain the IP, which at the time of stack
9424 frame generation actually contains the old stack pointer. So a
9425 quick way to unwind the stack is just pop the IP register directly
9426 into the stack pointer. */
9427 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9429 saved_regs_mask &= ~ (1 << IP_REGNUM);
9430 saved_regs_mask |= (1 << SP_REGNUM);
9432 /* There are two registers left in saved_regs_mask - LR and PC. We
9433 only need to restore the LR register (the return address), but to
9434 save time we can load it directly into the PC, unless we need a
9435 special function exit sequence, or we are not really returning. */
9436 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9437 /* Delete the LR from the register mask, so that the LR on
9438 the stack is loaded into the PC in the register mask. */
9439 saved_regs_mask &= ~ (1 << LR_REGNUM);
9441 saved_regs_mask &= ~ (1 << PC_REGNUM);
9443 /* We must use SP as the base register, because SP is one of the
9444 registers being restored. If an interrupt or page fault
9445 happens in the ldm instruction, the SP might or might not
9446 have been restored. That would be bad, as then SP will no
9447 longer indicate the safe area of stack, and we can get stack
9448 corruption. Using SP as the base register means that it will
9449 be reset correctly to the original value, should an interrupt
9450 occur. If the stack pointer already points at the right
9451 place, then omit the subtraction. */
9452 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9453 || current_function_calls_alloca)
9454 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9455 4 * bit_count (saved_regs_mask));
9456 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9458 if (IS_INTERRUPT (func_type))
9459 /* Interrupt handlers will have pushed the
9460 IP onto the stack, so restore it now. */
9461 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9465 /* Restore stack pointer if necessary. */
9466 if (offsets->outgoing_args != offsets->saved_regs)
9468 operands[0] = operands[1] = stack_pointer_rtx;
9469 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9470 output_add_immediate (operands);
9473 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9475 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9476 if (regs_ever_live[reg] && !call_used_regs[reg])
9477 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9482 start_reg = FIRST_FPA_REGNUM;
9484 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9486 if (regs_ever_live[reg] && !call_used_regs[reg])
9488 if (reg - start_reg == 3)
9490 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9491 start_reg, SP_REGNUM);
9492 start_reg = reg + 1;
9497 if (reg != start_reg)
9498 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9499 start_reg, reg - start_reg,
9502 start_reg = reg + 1;
9506 /* Just in case the last register checked also needs unstacking. */
9507 if (reg != start_reg)
9508 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9509 start_reg, reg - start_reg, SP_REGNUM);
9512 if (TARGET_HARD_FLOAT && TARGET_VFP)
9514 start_reg = FIRST_VFP_REGNUM;
9515 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9517 if ((!regs_ever_live[reg] || call_used_regs[reg])
9518 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9520 if (start_reg != reg)
9521 arm_output_fldmx (f, SP_REGNUM,
9522 (start_reg - FIRST_VFP_REGNUM) / 2,
9523 (reg - start_reg) / 2);
9524 start_reg = reg + 2;
9527 if (start_reg != reg)
9528 arm_output_fldmx (f, SP_REGNUM,
9529 (start_reg - FIRST_VFP_REGNUM) / 2,
9530 (reg - start_reg) / 2);
9533 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9534 if (regs_ever_live[reg] && !call_used_regs[reg])
9535 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
9537 /* If we can, restore the LR into the PC. */
9538 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9540 && current_function_pretend_args_size == 0
9541 && saved_regs_mask & (1 << LR_REGNUM))
9543 saved_regs_mask &= ~ (1 << LR_REGNUM);
9544 saved_regs_mask |= (1 << PC_REGNUM);
9547 /* Load the registers off the stack. If we only have one register
9548 to load use the LDR instruction - it is faster. */
9549 if (saved_regs_mask == (1 << LR_REGNUM))
9551 /* The exception handler ignores the LR, so we do
9552 not really need to load it off the stack. */
9554 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9556 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9558 else if (saved_regs_mask)
9560 if (saved_regs_mask & (1 << SP_REGNUM))
9561 /* Note - write back to the stack register is not enabled
9562 (ie "ldmfd sp!..."). We know that the stack pointer is
9563 in the list of registers and if we add writeback the
9564 instruction becomes UNPREDICTABLE. */
9565 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9567 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9570 if (current_function_pretend_args_size)
9572 /* Unwind the pre-pushed regs. */
9573 operands[0] = operands[1] = stack_pointer_rtx;
9574 operands[2] = GEN_INT (current_function_pretend_args_size);
9575 output_add_immediate (operands);
9580 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9581 && current_function_pretend_args_size == 0
9582 && saved_regs_mask & (1 << PC_REGNUM)))
9585 /* Generate the return instruction. */
9586 switch ((int) ARM_FUNC_TYPE (func_type))
9588 case ARM_FT_EXCEPTION_HANDLER:
9589 /* Even in 26-bit mode we do a mov (rather than a movs)
9590 because we don't have the PSR bits set in the address. */
9591 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9596 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9599 case ARM_FT_EXCEPTION:
9600 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9603 case ARM_FT_INTERWORKED:
9604 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9608 if (frame_pointer_needed)
9609 /* If we used the frame pointer then the return address
9610 will have been loaded off the stack directly into the
9611 PC, so there is no need to issue a MOV instruction
9614 else if (current_function_pretend_args_size == 0
9615 && (saved_regs_mask & (1 << LR_REGNUM)))
9616 /* Similarly we may have been able to load LR into the PC
9617 even if we did not create a stack frame. */
9619 else if (TARGET_APCS_32)
9620 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9622 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9630 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9631 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9633 arm_stack_offsets *offsets;
9637 /* ??? Probably not safe to set this here, since it assumes that a
9638 function will be emitted as assembly immediately after we generate
9639 RTL for it. This does not happen for inline functions. */
9640 return_used_this_function = 0;
9644 /* We need to take into account any stack-frame rounding. */
9645 offsets = arm_get_frame_offsets ();
9647 if (use_return_insn (FALSE, NULL)
9648 && return_used_this_function
9649 && offsets->saved_regs != offsets->outgoing_args
9650 && !frame_pointer_needed)
9653 /* Reset the ARM-specific per-function variables. */
9654 after_arm_reorg = 0;
9658 /* Generate and emit an insn that we will recognize as a push_multi.
9659 Unfortunately, since this insn does not reflect very well the actual
9660 semantics of the operation, we need to annotate the insn for the benefit
9661 of DWARF2 frame unwind information. */
9663 emit_multi_reg_push (int mask)
9670 int dwarf_par_index;
9673 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9674 if (mask & (1 << i))
9677 if (num_regs == 0 || num_regs > 16)
9680 /* We don't record the PC in the dwarf frame information. */
9681 num_dwarf_regs = num_regs;
9682 if (mask & (1 << PC_REGNUM))
9685 /* For the body of the insn we are going to generate an UNSPEC in
9686 parallel with several USEs. This allows the insn to be recognized
9687 by the push_multi pattern in the arm.md file. The insn looks
9688 something like this:
9691 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9692 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9693 (use (reg:SI 11 fp))
9694 (use (reg:SI 12 ip))
9695 (use (reg:SI 14 lr))
9696 (use (reg:SI 15 pc))
9699 For the frame note however, we try to be more explicit and actually
9700 show each register being stored into the stack frame, plus a (single)
9701 decrement of the stack pointer. We do it this way in order to be
9702 friendly to the stack unwinding code, which only wants to see a single
9703 stack decrement per instruction. The RTL we generate for the note looks
9704 something like this:
9707 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9708 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9709 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9710 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9711 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9714 This sequence is used both by the code to support stack unwinding for
9715 exceptions handlers and the code to generate dwarf2 frame debugging. */
9717 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9718 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9719 dwarf_par_index = 1;
9721 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9723 if (mask & (1 << i))
9725 reg = gen_rtx_REG (SImode, i);
9728 = gen_rtx_SET (VOIDmode,
9729 gen_rtx_MEM (BLKmode,
9730 gen_rtx_PRE_DEC (BLKmode,
9731 stack_pointer_rtx)),
9732 gen_rtx_UNSPEC (BLKmode,
9738 tmp = gen_rtx_SET (VOIDmode,
9739 gen_rtx_MEM (SImode, stack_pointer_rtx),
9741 RTX_FRAME_RELATED_P (tmp) = 1;
9742 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9750 for (j = 1, i++; j < num_regs; i++)
9752 if (mask & (1 << i))
9754 reg = gen_rtx_REG (SImode, i);
9756 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9760 tmp = gen_rtx_SET (VOIDmode,
9761 gen_rtx_MEM (SImode,
9762 plus_constant (stack_pointer_rtx,
9765 RTX_FRAME_RELATED_P (tmp) = 1;
9766 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9773 par = emit_insn (par);
9775 tmp = gen_rtx_SET (SImode,
9777 gen_rtx_PLUS (SImode,
9779 GEN_INT (-4 * num_regs)));
9780 RTX_FRAME_RELATED_P (tmp) = 1;
9781 XVECEXP (dwarf, 0, 0) = tmp;
9783 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9789 emit_sfm (int base_reg, int count)
9796 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9797 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9799 reg = gen_rtx_REG (XFmode, base_reg++);
9802 = gen_rtx_SET (VOIDmode,
9803 gen_rtx_MEM (BLKmode,
9804 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9805 gen_rtx_UNSPEC (BLKmode,
9809 = gen_rtx_SET (VOIDmode,
9810 gen_rtx_MEM (XFmode,
9811 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9813 RTX_FRAME_RELATED_P (tmp) = 1;
9814 XVECEXP (dwarf, 0, count - 1) = tmp;
9816 for (i = 1; i < count; i++)
9818 reg = gen_rtx_REG (XFmode, base_reg++);
9819 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9821 tmp = gen_rtx_SET (VOIDmode,
9822 gen_rtx_MEM (XFmode,
9823 gen_rtx_PRE_DEC (BLKmode,
9824 stack_pointer_rtx)),
9826 RTX_FRAME_RELATED_P (tmp) = 1;
9827 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9830 par = emit_insn (par);
9831 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9837 /* Compute the distance from register FROM to register TO.
9838 These can be the arg pointer (26), the soft frame pointer (25),
9839 the stack pointer (13) or the hard frame pointer (11).
9840 Typical stack layout looks like this:
9842 old stack pointer -> | |
9845 | | saved arguments for
9846 | | vararg functions
9849 hard FP & arg pointer -> | | \
9857 soft frame pointer -> | | /
9867 current stack pointer -> | | /
9870 For a given function some or all of these stack components
9871 may not be needed, giving rise to the possibility of
9872 eliminating some of the registers.
9874 The values returned by this function must reflect the behavior
9875 of arm_expand_prologue() and arm_compute_save_reg_mask().
9877 The sign of the number returned reflects the direction of stack
9878 growth, so the values are positive for all eliminations except
9879 from the soft frame pointer to the hard frame pointer.
9881 SFP may point just inside the local variables block to ensure correct
9885 /* Calculate stack offsets. These are used to calculate register elimination
9886 offsets and in prologue/epilogue code. */
9888 static arm_stack_offsets *
9889 arm_get_frame_offsets (void)
9891 struct arm_stack_offsets *offsets;
9892 unsigned long func_type;
9895 HOST_WIDE_INT frame_size;
9897 offsets = &cfun->machine->stack_offsets;
9899 /* We need to know if we are a leaf function. Unfortunately, it
9900 is possible to be called after start_sequence has been called,
9901 which causes get_insns to return the insns for the sequence,
9902 not the function, which will cause leaf_function_p to return
9903 the incorrect result.
9905 to know about leaf functions once reload has completed, and the
9906 frame size cannot be changed after that time, so we can safely
9907 use the cached value. */
9909 if (reload_completed)
9912 /* Initially this is the size of the local variables. It will translated
9913 into an offset once we have determined the size of preceding data. */
9914 frame_size = ROUND_UP_WORD (get_frame_size ());
9916 leaf = leaf_function_p ();
9918 /* Space for variadic functions. */
9919 offsets->saved_args = current_function_pretend_args_size;
9921 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
9927 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
9929 /* We know that SP will be doubleword aligned on entry, and we must
9930 preserve that condition at any subroutine call. We also require the
9931 soft frame pointer to be doubleword aligned. */
9933 if (TARGET_REALLY_IWMMXT)
9935 /* Check for the call-saved iWMMXt registers. */
9936 for (regno = FIRST_IWMMXT_REGNUM;
9937 regno <= LAST_IWMMXT_REGNUM;
9939 if (regs_ever_live [regno] && ! call_used_regs [regno])
9943 func_type = arm_current_func_type ();
9944 if (! IS_VOLATILE (func_type))
9946 /* Space for saved FPA registers. */
9947 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
9948 if (regs_ever_live[regno] && ! call_used_regs[regno])
9951 /* Space for saved VFP registers. */
9952 if (TARGET_HARD_FLOAT && TARGET_VFP)
9953 saved += arm_get_vfp_saved_size ();
9956 else /* TARGET_THUMB */
9963 for (reg = 8; reg < 13; reg ++)
9964 if (THUMB_REG_PUSHED_P (reg))
9967 saved += 4 * count_regs;
9969 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
9970 if (THUMB_REG_PUSHED_P (reg))
9972 if (count_regs || ! leaf_function_p ()
9973 || thumb_far_jump_used_p ())
9974 saved += 4 * (count_regs + 1);
9975 if (TARGET_BACKTRACE)
9977 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
9984 /* Saved registers include the stack frame. */
9985 offsets->saved_regs = offsets->saved_args + saved;
9986 offsets->soft_frame = offsets->saved_regs;
9987 /* A leaf function does not need any stack alignment if it has nothing
9989 if (leaf && frame_size == 0)
9991 offsets->outgoing_args = offsets->soft_frame;
9995 /* Ensure SFP has the correct alignment. */
9996 if (ARM_DOUBLEWORD_ALIGN
9997 && (offsets->soft_frame & 7))
9998 offsets->soft_frame += 4;
10000 offsets->outgoing_args = offsets->soft_frame + frame_size
10001 + current_function_outgoing_args_size;
10003 if (ARM_DOUBLEWORD_ALIGN)
10005 /* Ensure SP remains doubleword aligned. */
10006 if (offsets->outgoing_args & 7)
10007 offsets->outgoing_args += 4;
10008 if (offsets->outgoing_args & 7)
10016 /* Calculate the relative offsets for the different stack pointers. Positive
10017 offsets are in the direction of stack growth. */
10020 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10022 arm_stack_offsets *offsets;
10024 offsets = arm_get_frame_offsets ();
10026 /* OK, now we have enough information to compute the distances.
10027 There must be an entry in these switch tables for each pair
10028 of registers in ELIMINABLE_REGS, even if some of the entries
10029 seem to be redundant or useless. */
10032 case ARG_POINTER_REGNUM:
10035 case THUMB_HARD_FRAME_POINTER_REGNUM:
10038 case FRAME_POINTER_REGNUM:
10039 /* This is the reverse of the soft frame pointer
10040 to hard frame pointer elimination below. */
10041 return offsets->soft_frame - offsets->saved_args;
10043 case ARM_HARD_FRAME_POINTER_REGNUM:
10044 /* If there is no stack frame then the hard
10045 frame pointer and the arg pointer coincide. */
10046 if (offsets->frame == offsets->saved_regs)
10048 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10049 return (frame_pointer_needed
10050 && current_function_needs_context
10051 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10053 case STACK_POINTER_REGNUM:
10054 /* If nothing has been pushed on the stack at all
10055 then this will return -4. This *is* correct! */
10056 return offsets->outgoing_args - (offsets->saved_args + 4);
10063 case FRAME_POINTER_REGNUM:
10066 case THUMB_HARD_FRAME_POINTER_REGNUM:
10069 case ARM_HARD_FRAME_POINTER_REGNUM:
10070 /* The hard frame pointer points to the top entry in the
10071 stack frame. The soft frame pointer to the bottom entry
10072 in the stack frame. If there is no stack frame at all,
10073 then they are identical. */
10075 return offsets->frame - offsets->soft_frame;
10077 case STACK_POINTER_REGNUM:
10078 return offsets->outgoing_args - offsets->soft_frame;
10086 /* You cannot eliminate from the stack pointer.
10087 In theory you could eliminate from the hard frame
10088 pointer to the stack pointer, but this will never
10089 happen, since if a stack frame is not needed the
10090 hard frame pointer will never be used. */
10096 /* Generate the prologue instructions for entry into an ARM function. */
10098 arm_expand_prologue (void)
10104 unsigned long live_regs_mask;
10105 unsigned long func_type;
10107 int saved_pretend_args = 0;
10108 int saved_regs = 0;
10109 unsigned int args_to_push;
10110 arm_stack_offsets *offsets;
10112 func_type = arm_current_func_type ();
10114 /* Naked functions don't have prologues. */
10115 if (IS_NAKED (func_type))
10118 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10119 args_to_push = current_function_pretend_args_size;
10121 /* Compute which register we will have to save onto the stack. */
10122 live_regs_mask = arm_compute_save_reg_mask ();
10124 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10126 if (frame_pointer_needed)
10128 if (IS_INTERRUPT (func_type))
10130 /* Interrupt functions must not corrupt any registers.
10131 Creating a frame pointer however, corrupts the IP
10132 register, so we must push it first. */
10133 insn = emit_multi_reg_push (1 << IP_REGNUM);
10135 /* Do not set RTX_FRAME_RELATED_P on this insn.
10136 The dwarf stack unwinding code only wants to see one
10137 stack decrement per function, and this is not it. If
10138 this instruction is labeled as being part of the frame
10139 creation sequence then dwarf2out_frame_debug_expr will
10140 abort when it encounters the assignment of IP to FP
10141 later on, since the use of SP here establishes SP as
10142 the CFA register and not IP.
10144 Anyway this instruction is not really part of the stack
10145 frame creation although it is part of the prologue. */
10147 else if (IS_NESTED (func_type))
10149 /* The Static chain register is the same as the IP register
10150 used as a scratch register during stack frame creation.
10151 To get around this need to find somewhere to store IP
10152 whilst the frame is being created. We try the following
10155 1. The last argument register.
10156 2. A slot on the stack above the frame. (This only
10157 works if the function is not a varargs function).
10158 3. Register r3, after pushing the argument registers
10161 Note - we only need to tell the dwarf2 backend about the SP
10162 adjustment in the second variant; the static chain register
10163 doesn't need to be unwound, as it doesn't contain a value
10164 inherited from the caller. */
10166 if (regs_ever_live[3] == 0)
10168 insn = gen_rtx_REG (SImode, 3);
10169 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10170 insn = emit_insn (insn);
10172 else if (args_to_push == 0)
10175 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10176 insn = gen_rtx_MEM (SImode, insn);
10177 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10178 insn = emit_insn (insn);
10182 /* Just tell the dwarf backend that we adjusted SP. */
10183 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10184 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10185 GEN_INT (-fp_offset)));
10186 RTX_FRAME_RELATED_P (insn) = 1;
10187 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10188 dwarf, REG_NOTES (insn));
10192 /* Store the args on the stack. */
10193 if (cfun->machine->uses_anonymous_args)
10194 insn = emit_multi_reg_push
10195 ((0xf0 >> (args_to_push / 4)) & 0xf);
10198 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10199 GEN_INT (- args_to_push)));
10201 RTX_FRAME_RELATED_P (insn) = 1;
10203 saved_pretend_args = 1;
10204 fp_offset = args_to_push;
10207 /* Now reuse r3 to preserve IP. */
10208 insn = gen_rtx_REG (SImode, 3);
10209 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10210 (void) emit_insn (insn);
10216 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10217 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10220 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10222 insn = emit_insn (insn);
10223 RTX_FRAME_RELATED_P (insn) = 1;
10228 /* Push the argument registers, or reserve space for them. */
10229 if (cfun->machine->uses_anonymous_args)
10230 insn = emit_multi_reg_push
10231 ((0xf0 >> (args_to_push / 4)) & 0xf);
10234 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10235 GEN_INT (- args_to_push)));
10236 RTX_FRAME_RELATED_P (insn) = 1;
10239 /* If this is an interrupt service routine, and the link register
10240 is going to be pushed, and we are not creating a stack frame,
10241 (which would involve an extra push of IP and a pop in the epilogue)
10242 subtracting four from LR now will mean that the function return
10243 can be done with a single instruction. */
10244 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10245 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10246 && ! frame_pointer_needed)
10247 emit_insn (gen_rtx_SET (SImode,
10248 gen_rtx_REG (SImode, LR_REGNUM),
10249 gen_rtx_PLUS (SImode,
10250 gen_rtx_REG (SImode, LR_REGNUM),
10253 if (live_regs_mask)
10255 insn = emit_multi_reg_push (live_regs_mask);
10256 saved_regs += bit_count (live_regs_mask) * 4;
10257 RTX_FRAME_RELATED_P (insn) = 1;
10261 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10262 if (regs_ever_live[reg] && ! call_used_regs [reg])
10264 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10265 insn = gen_rtx_MEM (V2SImode, insn);
10266 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10267 gen_rtx_REG (V2SImode, reg)));
10268 RTX_FRAME_RELATED_P (insn) = 1;
10272 if (! IS_VOLATILE (func_type))
10276 /* Save any floating point call-saved registers used by this
10278 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10280 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10281 if (regs_ever_live[reg] && !call_used_regs[reg])
10283 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10284 insn = gen_rtx_MEM (XFmode, insn);
10285 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10286 gen_rtx_REG (XFmode, reg)));
10287 RTX_FRAME_RELATED_P (insn) = 1;
10293 start_reg = LAST_FPA_REGNUM;
10295 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10297 if (regs_ever_live[reg] && !call_used_regs[reg])
10299 if (start_reg - reg == 3)
10301 insn = emit_sfm (reg, 4);
10302 RTX_FRAME_RELATED_P (insn) = 1;
10303 start_reg = reg - 1;
10308 if (start_reg != reg)
10310 insn = emit_sfm (reg + 1, start_reg - reg);
10311 RTX_FRAME_RELATED_P (insn) = 1;
10312 saved_regs += (reg - start_reg) * 12;
10314 start_reg = reg - 1;
10318 if (start_reg != reg)
10320 insn = emit_sfm (reg + 1, start_reg - reg);
10321 saved_regs += (reg - start_reg) * 12;
10322 RTX_FRAME_RELATED_P (insn) = 1;
10325 if (TARGET_HARD_FLOAT && TARGET_VFP)
10327 start_reg = FIRST_VFP_REGNUM;
10329 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10331 if ((!regs_ever_live[reg] || call_used_regs[reg])
10332 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10334 if (start_reg != reg)
10335 saved_regs += vfp_emit_fstmx (start_reg,
10336 (reg - start_reg) / 2);
10337 start_reg = reg + 2;
10340 if (start_reg != reg)
10341 saved_regs += vfp_emit_fstmx (start_reg,
10342 (reg - start_reg) / 2);
10346 if (frame_pointer_needed)
10348 /* Create the new frame pointer. */
10349 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10350 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10351 RTX_FRAME_RELATED_P (insn) = 1;
10353 if (IS_NESTED (func_type))
10355 /* Recover the static chain register. */
10356 if (regs_ever_live [3] == 0
10357 || saved_pretend_args)
10358 insn = gen_rtx_REG (SImode, 3);
10359 else /* if (current_function_pretend_args_size == 0) */
10361 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10363 insn = gen_rtx_MEM (SImode, insn);
10366 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10367 /* Add a USE to stop propagate_one_insn() from barfing. */
10368 emit_insn (gen_prologue_use (ip_rtx));
10372 offsets = arm_get_frame_offsets ();
10373 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10375 /* This add can produce multiple insns for a large constant, so we
10376 need to get tricky. */
10377 rtx last = get_last_insn ();
10379 amount = GEN_INT (offsets->saved_args + saved_regs
10380 - offsets->outgoing_args);
10382 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10386 last = last ? NEXT_INSN (last) : get_insns ();
10387 RTX_FRAME_RELATED_P (last) = 1;
10389 while (last != insn);
10391 /* If the frame pointer is needed, emit a special barrier that
10392 will prevent the scheduler from moving stores to the frame
10393 before the stack adjustment. */
10394 if (frame_pointer_needed)
10395 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10396 hard_frame_pointer_rtx));
10399 /* If we are profiling, make sure no instructions are scheduled before
10400 the call to mcount. Similarly if the user has requested no
10401 scheduling in the prolog. */
10402 if (current_function_profile || TARGET_NO_SCHED_PRO)
10403 emit_insn (gen_blockage ());
10405 /* If the link register is being kept alive, with the return address in it,
10406 then make sure that it does not get reused by the ce2 pass. */
10407 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10409 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10410 cfun->machine->lr_save_eliminated = 1;
10414 /* If CODE is 'd', then the X is a condition operand and the instruction
10415 should only be executed if the condition is true.
10416 if CODE is 'D', then the X is a condition operand and the instruction
10417 should only be executed if the condition is false: however, if the mode
10418 of the comparison is CCFPEmode, then always execute the instruction -- we
10419 do this because in these circumstances !GE does not necessarily imply LT;
10420 in these cases the instruction pattern will take care to make sure that
10421 an instruction containing %d will follow, thereby undoing the effects of
10422 doing this instruction unconditionally.
10423 If CODE is 'N' then X is a floating point operand that must be negated
10425 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10426 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10428 arm_print_operand (FILE *stream, rtx x, int code)
10433 fputs (ASM_COMMENT_START, stream);
10437 fputs (user_label_prefix, stream);
10441 fputs (REGISTER_PREFIX, stream);
10445 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10447 if (TARGET_THUMB || current_insn_predicate != NULL)
10450 fputs (arm_condition_codes[arm_current_cc], stream);
10452 else if (current_insn_predicate)
10454 enum arm_cond_code code;
10459 code = get_arm_condition_code (current_insn_predicate);
10460 fputs (arm_condition_codes[code], stream);
10467 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10468 r = REAL_VALUE_NEGATE (r);
10469 fprintf (stream, "%s", fp_const_from_val (&r));
10474 if (GET_CODE (x) == CONST_INT)
10477 val = ARM_SIGN_EXTEND (~INTVAL (x));
10478 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10482 putc ('~', stream);
10483 output_addr_const (stream, x);
10488 fprintf (stream, "%s", arithmetic_instr (x, 1));
10491 /* Truncate Cirrus shift counts. */
10493 if (GET_CODE (x) == CONST_INT)
10495 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10498 arm_print_operand (stream, x, 0);
10502 fprintf (stream, "%s", arithmetic_instr (x, 0));
10508 const char * shift = shift_op (x, &val);
10512 fprintf (stream, ", %s ", shift_op (x, &val));
10514 arm_print_operand (stream, XEXP (x, 1), 0);
10516 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10521 /* An explanation of the 'Q', 'R' and 'H' register operands:
10523 In a pair of registers containing a DI or DF value the 'Q'
10524 operand returns the register number of the register containing
10525 the least significant part of the value. The 'R' operand returns
10526 the register number of the register containing the most
10527 significant part of the value.
10529 The 'H' operand returns the higher of the two register numbers.
10530 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10531 same as the 'Q' operand, since the most significant part of the
10532 value is held in the lower number register. The reverse is true
10533 on systems where WORDS_BIG_ENDIAN is false.
10535 The purpose of these operands is to distinguish between cases
10536 where the endian-ness of the values is important (for example
10537 when they are added together), and cases where the endian-ness
10538 is irrelevant, but the order of register operations is important.
10539 For example when loading a value from memory into a register
10540 pair, the endian-ness does not matter. Provided that the value
10541 from the lower memory address is put into the lower numbered
10542 register, and the value from the higher address is put into the
10543 higher numbered register, the load will work regardless of whether
10544 the value being loaded is big-wordian or little-wordian. The
10545 order of the two register loads can matter however, if the address
10546 of the memory location is actually held in one of the registers
10547 being overwritten by the load. */
10549 if (REGNO (x) > LAST_ARM_REGNUM)
10551 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10555 if (REGNO (x) > LAST_ARM_REGNUM)
10557 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10561 if (REGNO (x) > LAST_ARM_REGNUM)
10563 asm_fprintf (stream, "%r", REGNO (x) + 1);
10567 asm_fprintf (stream, "%r",
10568 GET_CODE (XEXP (x, 0)) == REG
10569 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10573 asm_fprintf (stream, "{%r-%r}",
10575 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10579 /* CONST_TRUE_RTX means always -- that's the default. */
10580 if (x == const_true_rtx)
10583 fputs (arm_condition_codes[get_arm_condition_code (x)],
10588 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10589 want to do that. */
10590 if (x == const_true_rtx)
10593 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10594 (get_arm_condition_code (x))],
10598 /* Cirrus registers can be accessed in a variety of ways:
10599 single floating point (f)
10600 double floating point (d)
10602 64bit integer (dx). */
10603 case 'W': /* Cirrus register in F mode. */
10604 case 'X': /* Cirrus register in D mode. */
10605 case 'Y': /* Cirrus register in FX mode. */
10606 case 'Z': /* Cirrus register in DX mode. */
10607 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10610 fprintf (stream, "mv%s%s",
10612 : code == 'X' ? "d"
10613 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10617 /* Print cirrus register in the mode specified by the register's mode. */
10620 int mode = GET_MODE (x);
10622 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10625 fprintf (stream, "mv%s%s",
10626 mode == DFmode ? "d"
10627 : mode == SImode ? "fx"
10628 : mode == DImode ? "dx"
10629 : "f", reg_names[REGNO (x)] + 2);
10635 if (GET_CODE (x) != REG
10636 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10637 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10638 /* Bad value for wCG register number. */
10641 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10644 /* Print an iWMMXt control register name. */
10646 if (GET_CODE (x) != CONST_INT
10648 || INTVAL (x) >= 16)
10649 /* Bad value for wC register number. */
10653 static const char * wc_reg_names [16] =
10655 "wCID", "wCon", "wCSSF", "wCASF",
10656 "wC4", "wC5", "wC6", "wC7",
10657 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10658 "wC12", "wC13", "wC14", "wC15"
10661 fprintf (stream, wc_reg_names [INTVAL (x)]);
10665 /* Print a VFP double precision register name. */
10668 int mode = GET_MODE (x);
10671 if (mode != DImode && mode != DFmode)
10674 if (GET_CODE (x) != REG
10675 || !IS_VFP_REGNUM (REGNO (x)))
10678 num = REGNO(x) - FIRST_VFP_REGNUM;
10682 fprintf (stream, "d%d", num >> 1);
10690 if (GET_CODE (x) == REG)
10691 asm_fprintf (stream, "%r", REGNO (x));
10692 else if (GET_CODE (x) == MEM)
10694 output_memory_reference_mode = GET_MODE (x);
10695 output_address (XEXP (x, 0));
10697 else if (GET_CODE (x) == CONST_DOUBLE)
10698 fprintf (stream, "#%s", fp_immediate_constant (x));
10699 else if (GET_CODE (x) == NEG)
10700 abort (); /* This should never happen now. */
10703 fputc ('#', stream);
10704 output_addr_const (stream, x);
10709 #ifndef AOF_ASSEMBLER
10710 /* Target hook for assembling integer objects. The ARM version needs to
10711 handle word-sized values specially. */
10713 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10715 if (size == UNITS_PER_WORD && aligned_p)
10717 fputs ("\t.word\t", asm_out_file);
10718 output_addr_const (asm_out_file, x);
10720 /* Mark symbols as position independent. We only do this in the
10721 .text segment, not in the .data segment. */
10722 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10723 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10725 if (GET_CODE (x) == SYMBOL_REF
10726 && (CONSTANT_POOL_ADDRESS_P (x)
10727 || SYMBOL_REF_LOCAL_P (x)))
10728 fputs ("(GOTOFF)", asm_out_file);
10729 else if (GET_CODE (x) == LABEL_REF)
10730 fputs ("(GOTOFF)", asm_out_file);
10732 fputs ("(GOT)", asm_out_file);
10734 fputc ('\n', asm_out_file);
10738 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10742 if (GET_CODE (x) != CONST_VECTOR)
10745 units = CONST_VECTOR_NUNITS (x);
10747 switch (GET_MODE (x))
10749 case V2SImode: size = 4; break;
10750 case V4HImode: size = 2; break;
10751 case V8QImode: size = 1; break;
10756 for (i = 0; i < units; i++)
10760 elt = CONST_VECTOR_ELT (x, i);
10762 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10768 return default_assemble_integer (x, size, aligned_p);
10772 /* A finite state machine takes care of noticing whether or not instructions
10773 can be conditionally executed, and thus decrease execution time and code
10774 size by deleting branch instructions. The fsm is controlled by
10775 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10777 /* The state of the fsm controlling condition codes are:
10778 0: normal, do nothing special
10779 1: make ASM_OUTPUT_OPCODE not output this instruction
10780 2: make ASM_OUTPUT_OPCODE not output this instruction
10781 3: make instructions conditional
10782 4: make instructions conditional
10784 State transitions (state->state by whom under condition):
10785 0 -> 1 final_prescan_insn if the `target' is a label
10786 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10787 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10788 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10789 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10790 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10791 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10792 (the target insn is arm_target_insn).
10794 If the jump clobbers the conditions then we use states 2 and 4.
10796 A similar thing can be done with conditional return insns.
10798 XXX In case the `target' is an unconditional branch, this conditionalising
10799 of the instructions always reduces code size, but not always execution
10800 time. But then, I want to reduce the code size to somewhere near what
10801 /bin/cc produces. */
10803 /* Returns the index of the ARM condition code string in
10804 `arm_condition_codes'. COMPARISON should be an rtx like
10805 `(eq (...) (...))'. */
10806 static enum arm_cond_code
10807 get_arm_condition_code (rtx comparison)
10809 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10811 enum rtx_code comp_code = GET_CODE (comparison);
10813 if (GET_MODE_CLASS (mode) != MODE_CC)
10814 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10815 XEXP (comparison, 1));
10819 case CC_DNEmode: code = ARM_NE; goto dominance;
10820 case CC_DEQmode: code = ARM_EQ; goto dominance;
10821 case CC_DGEmode: code = ARM_GE; goto dominance;
10822 case CC_DGTmode: code = ARM_GT; goto dominance;
10823 case CC_DLEmode: code = ARM_LE; goto dominance;
10824 case CC_DLTmode: code = ARM_LT; goto dominance;
10825 case CC_DGEUmode: code = ARM_CS; goto dominance;
10826 case CC_DGTUmode: code = ARM_HI; goto dominance;
10827 case CC_DLEUmode: code = ARM_LS; goto dominance;
10828 case CC_DLTUmode: code = ARM_CC;
10831 if (comp_code != EQ && comp_code != NE)
10834 if (comp_code == EQ)
10835 return ARM_INVERSE_CONDITION_CODE (code);
10841 case NE: return ARM_NE;
10842 case EQ: return ARM_EQ;
10843 case GE: return ARM_PL;
10844 case LT: return ARM_MI;
10851 case NE: return ARM_NE;
10852 case EQ: return ARM_EQ;
10859 case NE: return ARM_MI;
10860 case EQ: return ARM_PL;
10866 /* These encodings assume that AC=1 in the FPA system control
10867 byte. This allows us to handle all cases except UNEQ and
10871 case GE: return ARM_GE;
10872 case GT: return ARM_GT;
10873 case LE: return ARM_LS;
10874 case LT: return ARM_MI;
10875 case NE: return ARM_NE;
10876 case EQ: return ARM_EQ;
10877 case ORDERED: return ARM_VC;
10878 case UNORDERED: return ARM_VS;
10879 case UNLT: return ARM_LT;
10880 case UNLE: return ARM_LE;
10881 case UNGT: return ARM_HI;
10882 case UNGE: return ARM_PL;
10883 /* UNEQ and LTGT do not have a representation. */
10884 case UNEQ: /* Fall through. */
10885 case LTGT: /* Fall through. */
10892 case NE: return ARM_NE;
10893 case EQ: return ARM_EQ;
10894 case GE: return ARM_LE;
10895 case GT: return ARM_LT;
10896 case LE: return ARM_GE;
10897 case LT: return ARM_GT;
10898 case GEU: return ARM_LS;
10899 case GTU: return ARM_CC;
10900 case LEU: return ARM_CS;
10901 case LTU: return ARM_HI;
10908 case LTU: return ARM_CS;
10909 case GEU: return ARM_CC;
10916 case NE: return ARM_NE;
10917 case EQ: return ARM_EQ;
10918 case GE: return ARM_GE;
10919 case GT: return ARM_GT;
10920 case LE: return ARM_LE;
10921 case LT: return ARM_LT;
10922 case GEU: return ARM_CS;
10923 case GTU: return ARM_HI;
10924 case LEU: return ARM_LS;
10925 case LTU: return ARM_CC;
10936 arm_final_prescan_insn (rtx insn)
10938 /* BODY will hold the body of INSN. */
10939 rtx body = PATTERN (insn);
10941 /* This will be 1 if trying to repeat the trick, and things need to be
10942 reversed if it appears to fail. */
10945 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10946 taken are clobbered, even if the rtl suggests otherwise. It also
10947 means that we have to grub around within the jump expression to find
10948 out what the conditions are when the jump isn't taken. */
10949 int jump_clobbers = 0;
10951 /* If we start with a return insn, we only succeed if we find another one. */
10952 int seeking_return = 0;
10954 /* START_INSN will hold the insn from where we start looking. This is the
10955 first insn after the following code_label if REVERSE is true. */
10956 rtx start_insn = insn;
10958 /* If in state 4, check if the target branch is reached, in order to
10959 change back to state 0. */
10960 if (arm_ccfsm_state == 4)
10962 if (insn == arm_target_insn)
10964 arm_target_insn = NULL;
10965 arm_ccfsm_state = 0;
10970 /* If in state 3, it is possible to repeat the trick, if this insn is an
10971 unconditional branch to a label, and immediately following this branch
10972 is the previous target label which is only used once, and the label this
10973 branch jumps to is not too far off. */
10974 if (arm_ccfsm_state == 3)
10976 if (simplejump_p (insn))
10978 start_insn = next_nonnote_insn (start_insn);
10979 if (GET_CODE (start_insn) == BARRIER)
10981 /* XXX Isn't this always a barrier? */
10982 start_insn = next_nonnote_insn (start_insn);
10984 if (GET_CODE (start_insn) == CODE_LABEL
10985 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10986 && LABEL_NUSES (start_insn) == 1)
10991 else if (GET_CODE (body) == RETURN)
10993 start_insn = next_nonnote_insn (start_insn);
10994 if (GET_CODE (start_insn) == BARRIER)
10995 start_insn = next_nonnote_insn (start_insn);
10996 if (GET_CODE (start_insn) == CODE_LABEL
10997 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10998 && LABEL_NUSES (start_insn) == 1)
11001 seeking_return = 1;
11010 if (arm_ccfsm_state != 0 && !reverse)
11012 if (GET_CODE (insn) != JUMP_INSN)
11015 /* This jump might be paralleled with a clobber of the condition codes
11016 the jump should always come first */
11017 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11018 body = XVECEXP (body, 0, 0);
11021 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11022 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11025 int fail = FALSE, succeed = FALSE;
11026 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11027 int then_not_else = TRUE;
11028 rtx this_insn = start_insn, label = 0;
11030 /* If the jump cannot be done with one instruction, we cannot
11031 conditionally execute the instruction in the inverse case. */
11032 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11038 /* Register the insn jumped to. */
11041 if (!seeking_return)
11042 label = XEXP (SET_SRC (body), 0);
11044 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11045 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11046 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11048 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11049 then_not_else = FALSE;
11051 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11052 seeking_return = 1;
11053 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11055 seeking_return = 1;
11056 then_not_else = FALSE;
11061 /* See how many insns this branch skips, and what kind of insns. If all
11062 insns are okay, and the label or unconditional branch to the same
11063 label is not too far away, succeed. */
11064 for (insns_skipped = 0;
11065 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11069 this_insn = next_nonnote_insn (this_insn);
11073 switch (GET_CODE (this_insn))
11076 /* Succeed if it is the target label, otherwise fail since
11077 control falls in from somewhere else. */
11078 if (this_insn == label)
11082 arm_ccfsm_state = 2;
11083 this_insn = next_nonnote_insn (this_insn);
11086 arm_ccfsm_state = 1;
11094 /* Succeed if the following insn is the target label.
11096 If return insns are used then the last insn in a function
11097 will be a barrier. */
11098 this_insn = next_nonnote_insn (this_insn);
11099 if (this_insn && this_insn == label)
11103 arm_ccfsm_state = 2;
11104 this_insn = next_nonnote_insn (this_insn);
11107 arm_ccfsm_state = 1;
11115 /* If using 32-bit addresses the cc is not preserved over
11117 if (TARGET_APCS_32)
11119 /* Succeed if the following insn is the target label,
11120 or if the following two insns are a barrier and
11121 the target label. */
11122 this_insn = next_nonnote_insn (this_insn);
11123 if (this_insn && GET_CODE (this_insn) == BARRIER)
11124 this_insn = next_nonnote_insn (this_insn);
11126 if (this_insn && this_insn == label
11127 && insns_skipped < max_insns_skipped)
11131 arm_ccfsm_state = 2;
11132 this_insn = next_nonnote_insn (this_insn);
11135 arm_ccfsm_state = 1;
11144 /* If this is an unconditional branch to the same label, succeed.
11145 If it is to another label, do nothing. If it is conditional,
11147 /* XXX Probably, the tests for SET and the PC are
11150 scanbody = PATTERN (this_insn);
11151 if (GET_CODE (scanbody) == SET
11152 && GET_CODE (SET_DEST (scanbody)) == PC)
11154 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11155 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11157 arm_ccfsm_state = 2;
11160 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11163 /* Fail if a conditional return is undesirable (eg on a
11164 StrongARM), but still allow this if optimizing for size. */
11165 else if (GET_CODE (scanbody) == RETURN
11166 && !use_return_insn (TRUE, NULL)
11169 else if (GET_CODE (scanbody) == RETURN
11172 arm_ccfsm_state = 2;
11175 else if (GET_CODE (scanbody) == PARALLEL)
11177 switch (get_attr_conds (this_insn))
11187 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11192 /* Instructions using or affecting the condition codes make it
11194 scanbody = PATTERN (this_insn);
11195 if (!(GET_CODE (scanbody) == SET
11196 || GET_CODE (scanbody) == PARALLEL)
11197 || get_attr_conds (this_insn) != CONDS_NOCOND)
11200 /* A conditional cirrus instruction must be followed by
11201 a non Cirrus instruction. However, since we
11202 conditionalize instructions in this function and by
11203 the time we get here we can't add instructions
11204 (nops), because shorten_branches() has already been
11205 called, we will disable conditionalizing Cirrus
11206 instructions to be safe. */
11207 if (GET_CODE (scanbody) != USE
11208 && GET_CODE (scanbody) != CLOBBER
11209 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11219 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11220 arm_target_label = CODE_LABEL_NUMBER (label);
11221 else if (seeking_return || arm_ccfsm_state == 2)
11223 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11225 this_insn = next_nonnote_insn (this_insn);
11226 if (this_insn && (GET_CODE (this_insn) == BARRIER
11227 || GET_CODE (this_insn) == CODE_LABEL))
11232 /* Oh, dear! we ran off the end.. give up. */
11233 recog (PATTERN (insn), insn, NULL);
11234 arm_ccfsm_state = 0;
11235 arm_target_insn = NULL;
11238 arm_target_insn = this_insn;
11247 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11249 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11250 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11251 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11252 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11256 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11259 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11263 if (reverse || then_not_else)
11264 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11267 /* Restore recog_data (getting the attributes of other insns can
11268 destroy this array, but final.c assumes that it remains intact
11269 across this call; since the insn has been recognized already we
11270 call recog direct). */
11271 recog (PATTERN (insn), insn, NULL);
11275 /* Returns true if REGNO is a valid register
11276 for holding a quantity of tyoe MODE. */
11278 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11280 if (GET_MODE_CLASS (mode) == MODE_CC)
11281 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11284 /* For the Thumb we only allow values bigger than SImode in
11285 registers 0 - 6, so that there is always a second low
11286 register available to hold the upper part of the value.
11287 We probably we ought to ensure that the register is the
11288 start of an even numbered register pair. */
11289 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11291 if (IS_CIRRUS_REGNUM (regno))
11292 /* We have outlawed SI values in Cirrus registers because they
11293 reside in the lower 32 bits, but SF values reside in the
11294 upper 32 bits. This causes gcc all sorts of grief. We can't
11295 even split the registers into pairs because Cirrus SI values
11296 get sign extended to 64bits-- aldyh. */
11297 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11299 if (IS_VFP_REGNUM (regno))
11301 if (mode == SFmode || mode == SImode)
11304 /* DFmode values are only valid in even register pairs. */
11305 if (mode == DFmode)
11306 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11310 if (IS_IWMMXT_GR_REGNUM (regno))
11311 return mode == SImode;
11313 if (IS_IWMMXT_REGNUM (regno))
11314 return VALID_IWMMXT_REG_MODE (mode);
11316 if (regno <= LAST_ARM_REGNUM)
11317 /* We allow any value to be stored in the general registers. */
11320 if ( regno == FRAME_POINTER_REGNUM
11321 || regno == ARG_POINTER_REGNUM)
11322 /* We only allow integers in the fake hard registers. */
11323 return GET_MODE_CLASS (mode) == MODE_INT;
11325 /* The only registers left are the FPA registers
11326 which we only allow to hold FP values. */
11327 return GET_MODE_CLASS (mode) == MODE_FLOAT
11328 && regno >= FIRST_FPA_REGNUM
11329 && regno <= LAST_FPA_REGNUM;
11333 arm_regno_class (int regno)
11337 if (regno == STACK_POINTER_REGNUM)
11339 if (regno == CC_REGNUM)
11346 if ( regno <= LAST_ARM_REGNUM
11347 || regno == FRAME_POINTER_REGNUM
11348 || regno == ARG_POINTER_REGNUM)
11349 return GENERAL_REGS;
11351 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11354 if (IS_CIRRUS_REGNUM (regno))
11355 return CIRRUS_REGS;
11357 if (IS_VFP_REGNUM (regno))
11360 if (IS_IWMMXT_REGNUM (regno))
11361 return IWMMXT_REGS;
11363 if (IS_IWMMXT_GR_REGNUM (regno))
11364 return IWMMXT_GR_REGS;
11369 /* Handle a special case when computing the offset
11370 of an argument from the frame pointer. */
11372 arm_debugger_arg_offset (int value, rtx addr)
11376 /* We are only interested if dbxout_parms() failed to compute the offset. */
11380 /* We can only cope with the case where the address is held in a register. */
11381 if (GET_CODE (addr) != REG)
11384 /* If we are using the frame pointer to point at the argument, then
11385 an offset of 0 is correct. */
11386 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11389 /* If we are using the stack pointer to point at the
11390 argument, then an offset of 0 is correct. */
11391 if ((TARGET_THUMB || !frame_pointer_needed)
11392 && REGNO (addr) == SP_REGNUM)
11395 /* Oh dear. The argument is pointed to by a register rather
11396 than being held in a register, or being stored at a known
11397 offset from the frame pointer. Since GDB only understands
11398 those two kinds of argument we must translate the address
11399 held in the register into an offset from the frame pointer.
11400 We do this by searching through the insns for the function
11401 looking to see where this register gets its value. If the
11402 register is initialized from the frame pointer plus an offset
11403 then we are in luck and we can continue, otherwise we give up.
11405 This code is exercised by producing debugging information
11406 for a function with arguments like this:
11408 double func (double a, double b, int c, double d) {return d;}
11410 Without this code the stab for parameter 'd' will be set to
11411 an offset of 0 from the frame pointer, rather than 8. */
11413 /* The if() statement says:
11415 If the insn is a normal instruction
11416 and if the insn is setting the value in a register
11417 and if the register being set is the register holding the address of the argument
11418 and if the address is computing by an addition
11419 that involves adding to a register
11420 which is the frame pointer
11425 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11427 if ( GET_CODE (insn) == INSN
11428 && GET_CODE (PATTERN (insn)) == SET
11429 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11430 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11431 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11432 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11433 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11436 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11445 warning ("unable to compute real location of stacked parameter");
11446 value = 8; /* XXX magic hack */
11452 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11455 if ((MASK) & insn_flags) \
11456 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11460 struct builtin_description
11462 const unsigned int mask;
11463 const enum insn_code icode;
11464 const char * const name;
11465 const enum arm_builtins code;
11466 const enum rtx_code comparison;
11467 const unsigned int flag;
11470 static const struct builtin_description bdesc_2arg[] =
11472 #define IWMMXT_BUILTIN(code, string, builtin) \
11473 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11474 ARM_BUILTIN_##builtin, 0, 0 },
11476 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11477 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11478 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11479 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11480 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11481 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11482 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11483 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11484 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11485 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11486 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11487 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11488 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11489 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11490 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11491 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11492 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11493 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11494 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11495 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11496 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11497 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11498 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11499 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11500 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11501 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11502 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11503 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11504 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11505 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11506 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11507 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11508 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11509 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11510 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11511 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11512 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11513 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11514 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11515 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11516 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11517 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11518 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11519 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11520 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11521 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11522 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11523 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11524 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11525 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11526 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11527 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11528 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11529 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11530 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11531 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11532 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11533 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11535 #define IWMMXT_BUILTIN2(code, builtin) \
11536 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11538 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11539 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11540 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11541 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11542 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11543 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11544 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11545 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11546 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11547 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11548 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11549 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11550 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11551 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11552 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11553 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11554 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11555 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11556 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11557 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11558 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11559 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11560 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11561 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11562 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11563 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11564 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11565 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11566 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11567 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11568 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11569 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11572 static const struct builtin_description bdesc_1arg[] =
11574 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11575 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11576 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11577 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11578 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11579 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11580 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11581 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11582 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11583 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11584 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11585 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11586 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11587 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11588 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11589 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11590 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11591 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11594 /* Set up all the iWMMXt builtins. This is
11595 not called if TARGET_IWMMXT is zero. */
11598 arm_init_iwmmxt_builtins (void)
11600 const struct builtin_description * d;
11602 tree endlink = void_list_node;
11604 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11605 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11606 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11609 = build_function_type (integer_type_node,
11610 tree_cons (NULL_TREE, integer_type_node, endlink));
11611 tree v8qi_ftype_v8qi_v8qi_int
11612 = build_function_type (V8QI_type_node,
11613 tree_cons (NULL_TREE, V8QI_type_node,
11614 tree_cons (NULL_TREE, V8QI_type_node,
11615 tree_cons (NULL_TREE,
11618 tree v4hi_ftype_v4hi_int
11619 = build_function_type (V4HI_type_node,
11620 tree_cons (NULL_TREE, V4HI_type_node,
11621 tree_cons (NULL_TREE, integer_type_node,
11623 tree v2si_ftype_v2si_int
11624 = build_function_type (V2SI_type_node,
11625 tree_cons (NULL_TREE, V2SI_type_node,
11626 tree_cons (NULL_TREE, integer_type_node,
11628 tree v2si_ftype_di_di
11629 = build_function_type (V2SI_type_node,
11630 tree_cons (NULL_TREE, long_long_integer_type_node,
11631 tree_cons (NULL_TREE, long_long_integer_type_node,
11633 tree di_ftype_di_int
11634 = build_function_type (long_long_integer_type_node,
11635 tree_cons (NULL_TREE, long_long_integer_type_node,
11636 tree_cons (NULL_TREE, integer_type_node,
11638 tree di_ftype_di_int_int
11639 = build_function_type (long_long_integer_type_node,
11640 tree_cons (NULL_TREE, long_long_integer_type_node,
11641 tree_cons (NULL_TREE, integer_type_node,
11642 tree_cons (NULL_TREE,
11645 tree int_ftype_v8qi
11646 = build_function_type (integer_type_node,
11647 tree_cons (NULL_TREE, V8QI_type_node,
11649 tree int_ftype_v4hi
11650 = build_function_type (integer_type_node,
11651 tree_cons (NULL_TREE, V4HI_type_node,
11653 tree int_ftype_v2si
11654 = build_function_type (integer_type_node,
11655 tree_cons (NULL_TREE, V2SI_type_node,
11657 tree int_ftype_v8qi_int
11658 = build_function_type (integer_type_node,
11659 tree_cons (NULL_TREE, V8QI_type_node,
11660 tree_cons (NULL_TREE, integer_type_node,
11662 tree int_ftype_v4hi_int
11663 = build_function_type (integer_type_node,
11664 tree_cons (NULL_TREE, V4HI_type_node,
11665 tree_cons (NULL_TREE, integer_type_node,
11667 tree int_ftype_v2si_int
11668 = build_function_type (integer_type_node,
11669 tree_cons (NULL_TREE, V2SI_type_node,
11670 tree_cons (NULL_TREE, integer_type_node,
11672 tree v8qi_ftype_v8qi_int_int
11673 = build_function_type (V8QI_type_node,
11674 tree_cons (NULL_TREE, V8QI_type_node,
11675 tree_cons (NULL_TREE, integer_type_node,
11676 tree_cons (NULL_TREE,
11679 tree v4hi_ftype_v4hi_int_int
11680 = build_function_type (V4HI_type_node,
11681 tree_cons (NULL_TREE, V4HI_type_node,
11682 tree_cons (NULL_TREE, integer_type_node,
11683 tree_cons (NULL_TREE,
11686 tree v2si_ftype_v2si_int_int
11687 = build_function_type (V2SI_type_node,
11688 tree_cons (NULL_TREE, V2SI_type_node,
11689 tree_cons (NULL_TREE, integer_type_node,
11690 tree_cons (NULL_TREE,
11693 /* Miscellaneous. */
11694 tree v8qi_ftype_v4hi_v4hi
11695 = build_function_type (V8QI_type_node,
11696 tree_cons (NULL_TREE, V4HI_type_node,
11697 tree_cons (NULL_TREE, V4HI_type_node,
11699 tree v4hi_ftype_v2si_v2si
11700 = build_function_type (V4HI_type_node,
11701 tree_cons (NULL_TREE, V2SI_type_node,
11702 tree_cons (NULL_TREE, V2SI_type_node,
11704 tree v2si_ftype_v4hi_v4hi
11705 = build_function_type (V2SI_type_node,
11706 tree_cons (NULL_TREE, V4HI_type_node,
11707 tree_cons (NULL_TREE, V4HI_type_node,
11709 tree v2si_ftype_v8qi_v8qi
11710 = build_function_type (V2SI_type_node,
11711 tree_cons (NULL_TREE, V8QI_type_node,
11712 tree_cons (NULL_TREE, V8QI_type_node,
11714 tree v4hi_ftype_v4hi_di
11715 = build_function_type (V4HI_type_node,
11716 tree_cons (NULL_TREE, V4HI_type_node,
11717 tree_cons (NULL_TREE,
11718 long_long_integer_type_node,
11720 tree v2si_ftype_v2si_di
11721 = build_function_type (V2SI_type_node,
11722 tree_cons (NULL_TREE, V2SI_type_node,
11723 tree_cons (NULL_TREE,
11724 long_long_integer_type_node,
11726 tree void_ftype_int_int
11727 = build_function_type (void_type_node,
11728 tree_cons (NULL_TREE, integer_type_node,
11729 tree_cons (NULL_TREE, integer_type_node,
11732 = build_function_type (long_long_unsigned_type_node, endlink);
11734 = build_function_type (long_long_integer_type_node,
11735 tree_cons (NULL_TREE, V8QI_type_node,
11738 = build_function_type (long_long_integer_type_node,
11739 tree_cons (NULL_TREE, V4HI_type_node,
11742 = build_function_type (long_long_integer_type_node,
11743 tree_cons (NULL_TREE, V2SI_type_node,
11745 tree v2si_ftype_v4hi
11746 = build_function_type (V2SI_type_node,
11747 tree_cons (NULL_TREE, V4HI_type_node,
11749 tree v4hi_ftype_v8qi
11750 = build_function_type (V4HI_type_node,
11751 tree_cons (NULL_TREE, V8QI_type_node,
11754 tree di_ftype_di_v4hi_v4hi
11755 = build_function_type (long_long_unsigned_type_node,
11756 tree_cons (NULL_TREE,
11757 long_long_unsigned_type_node,
11758 tree_cons (NULL_TREE, V4HI_type_node,
11759 tree_cons (NULL_TREE,
11763 tree di_ftype_v4hi_v4hi
11764 = build_function_type (long_long_unsigned_type_node,
11765 tree_cons (NULL_TREE, V4HI_type_node,
11766 tree_cons (NULL_TREE, V4HI_type_node,
11769 /* Normal vector binops. */
11770 tree v8qi_ftype_v8qi_v8qi
11771 = build_function_type (V8QI_type_node,
11772 tree_cons (NULL_TREE, V8QI_type_node,
11773 tree_cons (NULL_TREE, V8QI_type_node,
11775 tree v4hi_ftype_v4hi_v4hi
11776 = build_function_type (V4HI_type_node,
11777 tree_cons (NULL_TREE, V4HI_type_node,
11778 tree_cons (NULL_TREE, V4HI_type_node,
11780 tree v2si_ftype_v2si_v2si
11781 = build_function_type (V2SI_type_node,
11782 tree_cons (NULL_TREE, V2SI_type_node,
11783 tree_cons (NULL_TREE, V2SI_type_node,
11785 tree di_ftype_di_di
11786 = build_function_type (long_long_unsigned_type_node,
11787 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11788 tree_cons (NULL_TREE,
11789 long_long_unsigned_type_node,
11792 /* Add all builtins that are more or less simple operations on two
11794 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11796 /* Use one of the operands; the target can have a different mode for
11797 mask-generating compares. */
11798 enum machine_mode mode;
11804 mode = insn_data[d->icode].operand[1].mode;
11809 type = v8qi_ftype_v8qi_v8qi;
11812 type = v4hi_ftype_v4hi_v4hi;
11815 type = v2si_ftype_v2si_v2si;
11818 type = di_ftype_di_di;
11825 def_mbuiltin (d->mask, d->name, type, d->code);
11828 /* Add the remaining MMX insns with somewhat more complicated types. */
11829 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11830 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11831 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11833 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11834 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11835 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11836 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11837 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11838 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11840 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11841 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11842 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11843 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11844 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11845 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11847 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11848 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11849 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11850 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11851 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11852 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11854 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11855 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11856 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11857 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11858 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11859 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11861 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11863 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11864 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11865 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11866 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11868 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11869 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11870 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11871 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11872 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11873 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11874 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11875 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11876 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11878 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11879 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11880 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11882 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11883 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11884 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11886 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11887 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11888 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11889 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11890 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11891 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11893 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11894 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11895 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11896 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11897 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11898 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11899 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11900 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11901 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11902 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11903 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11904 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11906 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11907 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11908 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11909 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11911 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11912 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11913 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11914 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11915 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11916 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11917 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11921 arm_init_builtins (void)
11923 if (TARGET_REALLY_IWMMXT)
11924 arm_init_iwmmxt_builtins ();
11927 /* Errors in the source file can cause expand_expr to return const0_rtx
11928 where we expect a vector. To avoid crashing, use one of the vector
11929 clear instructions. */
11932 safe_vector_operand (rtx x, enum machine_mode mode)
11934 if (x != const0_rtx)
11936 x = gen_reg_rtx (mode);
11938 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11939 : gen_rtx_SUBREG (DImode, x, 0)));
11943 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11946 arm_expand_binop_builtin (enum insn_code icode,
11947 tree arglist, rtx target)
11950 tree arg0 = TREE_VALUE (arglist);
11951 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11952 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11953 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11954 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11955 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11956 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11958 if (VECTOR_MODE_P (mode0))
11959 op0 = safe_vector_operand (op0, mode0);
11960 if (VECTOR_MODE_P (mode1))
11961 op1 = safe_vector_operand (op1, mode1);
11964 || GET_MODE (target) != tmode
11965 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11966 target = gen_reg_rtx (tmode);
11968 /* In case the insn wants input operands in modes different from
11969 the result, abort. */
11970 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11973 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11974 op0 = copy_to_mode_reg (mode0, op0);
11975 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11976 op1 = copy_to_mode_reg (mode1, op1);
11978 pat = GEN_FCN (icode) (target, op0, op1);
11985 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11988 arm_expand_unop_builtin (enum insn_code icode,
11989 tree arglist, rtx target, int do_load)
11992 tree arg0 = TREE_VALUE (arglist);
11993 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11994 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11995 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11998 || GET_MODE (target) != tmode
11999 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12000 target = gen_reg_rtx (tmode);
12002 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12005 if (VECTOR_MODE_P (mode0))
12006 op0 = safe_vector_operand (op0, mode0);
12008 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12009 op0 = copy_to_mode_reg (mode0, op0);
12012 pat = GEN_FCN (icode) (target, op0);
12019 /* Expand an expression EXP that calls a built-in function,
12020 with result going to TARGET if that's convenient
12021 (and in mode MODE if that's convenient).
12022 SUBTARGET may be used as the target for computing one of EXP's operands.
12023 IGNORE is nonzero if the value is to be ignored. */
12026 arm_expand_builtin (tree exp,
12028 rtx subtarget ATTRIBUTE_UNUSED,
12029 enum machine_mode mode ATTRIBUTE_UNUSED,
12030 int ignore ATTRIBUTE_UNUSED)
12032 const struct builtin_description * d;
12033 enum insn_code icode;
12034 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12035 tree arglist = TREE_OPERAND (exp, 1);
12043 int fcode = DECL_FUNCTION_CODE (fndecl);
12045 enum machine_mode tmode;
12046 enum machine_mode mode0;
12047 enum machine_mode mode1;
12048 enum machine_mode mode2;
12052 case ARM_BUILTIN_TEXTRMSB:
12053 case ARM_BUILTIN_TEXTRMUB:
12054 case ARM_BUILTIN_TEXTRMSH:
12055 case ARM_BUILTIN_TEXTRMUH:
12056 case ARM_BUILTIN_TEXTRMSW:
12057 case ARM_BUILTIN_TEXTRMUW:
12058 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12059 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12060 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12061 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12062 : CODE_FOR_iwmmxt_textrmw);
12064 arg0 = TREE_VALUE (arglist);
12065 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12066 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12067 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12068 tmode = insn_data[icode].operand[0].mode;
12069 mode0 = insn_data[icode].operand[1].mode;
12070 mode1 = insn_data[icode].operand[2].mode;
12072 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12073 op0 = copy_to_mode_reg (mode0, op0);
12074 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12076 /* @@@ better error message */
12077 error ("selector must be an immediate");
12078 return gen_reg_rtx (tmode);
12081 || GET_MODE (target) != tmode
12082 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12083 target = gen_reg_rtx (tmode);
12084 pat = GEN_FCN (icode) (target, op0, op1);
12090 case ARM_BUILTIN_TINSRB:
12091 case ARM_BUILTIN_TINSRH:
12092 case ARM_BUILTIN_TINSRW:
12093 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12094 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12095 : CODE_FOR_iwmmxt_tinsrw);
12096 arg0 = TREE_VALUE (arglist);
12097 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12098 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12099 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12100 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12101 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12102 tmode = insn_data[icode].operand[0].mode;
12103 mode0 = insn_data[icode].operand[1].mode;
12104 mode1 = insn_data[icode].operand[2].mode;
12105 mode2 = insn_data[icode].operand[3].mode;
12107 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12108 op0 = copy_to_mode_reg (mode0, op0);
12109 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12110 op1 = copy_to_mode_reg (mode1, op1);
12111 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12113 /* @@@ better error message */
12114 error ("selector must be an immediate");
12118 || GET_MODE (target) != tmode
12119 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12120 target = gen_reg_rtx (tmode);
12121 pat = GEN_FCN (icode) (target, op0, op1, op2);
12127 case ARM_BUILTIN_SETWCX:
12128 arg0 = TREE_VALUE (arglist);
12129 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12130 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12131 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12132 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12135 case ARM_BUILTIN_GETWCX:
12136 arg0 = TREE_VALUE (arglist);
12137 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12138 target = gen_reg_rtx (SImode);
12139 emit_insn (gen_iwmmxt_tmrc (target, op0));
12142 case ARM_BUILTIN_WSHUFH:
12143 icode = CODE_FOR_iwmmxt_wshufh;
12144 arg0 = TREE_VALUE (arglist);
12145 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12146 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12147 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12148 tmode = insn_data[icode].operand[0].mode;
12149 mode1 = insn_data[icode].operand[1].mode;
12150 mode2 = insn_data[icode].operand[2].mode;
12152 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12153 op0 = copy_to_mode_reg (mode1, op0);
12154 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12156 /* @@@ better error message */
12157 error ("mask must be an immediate");
12161 || GET_MODE (target) != tmode
12162 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12163 target = gen_reg_rtx (tmode);
12164 pat = GEN_FCN (icode) (target, op0, op1);
12170 case ARM_BUILTIN_WSADB:
12171 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12172 case ARM_BUILTIN_WSADH:
12173 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12174 case ARM_BUILTIN_WSADBZ:
12175 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12176 case ARM_BUILTIN_WSADHZ:
12177 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12179 /* Several three-argument builtins. */
12180 case ARM_BUILTIN_WMACS:
12181 case ARM_BUILTIN_WMACU:
12182 case ARM_BUILTIN_WALIGN:
12183 case ARM_BUILTIN_TMIA:
12184 case ARM_BUILTIN_TMIAPH:
12185 case ARM_BUILTIN_TMIATT:
12186 case ARM_BUILTIN_TMIATB:
12187 case ARM_BUILTIN_TMIABT:
12188 case ARM_BUILTIN_TMIABB:
12189 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12190 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12191 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12192 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12193 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12194 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12195 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12196 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12197 : CODE_FOR_iwmmxt_walign);
12198 arg0 = TREE_VALUE (arglist);
12199 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12200 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12201 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12202 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12203 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12204 tmode = insn_data[icode].operand[0].mode;
12205 mode0 = insn_data[icode].operand[1].mode;
12206 mode1 = insn_data[icode].operand[2].mode;
12207 mode2 = insn_data[icode].operand[3].mode;
12209 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12210 op0 = copy_to_mode_reg (mode0, op0);
12211 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12212 op1 = copy_to_mode_reg (mode1, op1);
12213 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12214 op2 = copy_to_mode_reg (mode2, op2);
12216 || GET_MODE (target) != tmode
12217 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12218 target = gen_reg_rtx (tmode);
12219 pat = GEN_FCN (icode) (target, op0, op1, op2);
12225 case ARM_BUILTIN_WZERO:
12226 target = gen_reg_rtx (DImode);
12227 emit_insn (gen_iwmmxt_clrdi (target));
12234 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12235 if (d->code == (const enum arm_builtins) fcode)
12236 return arm_expand_binop_builtin (d->icode, arglist, target);
12238 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12239 if (d->code == (const enum arm_builtins) fcode)
12240 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12242 /* @@@ Should really do something sensible here. */
12246 /* Recursively search through all of the blocks in a function
12247 checking to see if any of the variables created in that
12248 function match the RTX called 'orig'. If they do then
12249 replace them with the RTX called 'new'. */
12251 replace_symbols_in_block (tree block, rtx orig, rtx new)
12253 for (; block; block = BLOCK_CHAIN (block))
12257 if (!TREE_USED (block))
12260 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12262 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12263 || DECL_IGNORED_P (sym)
12264 || TREE_CODE (sym) != VAR_DECL
12265 || DECL_EXTERNAL (sym)
12266 || !rtx_equal_p (DECL_RTL (sym), orig)
12270 SET_DECL_RTL (sym, new);
12273 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12277 /* Return the number (counting from 0) of
12278 the least significant set bit in MASK. */
12281 number_of_first_bit_set (int mask)
12286 (mask & (1 << bit)) == 0;
12293 /* Generate code to return from a thumb function.
12294 If 'reg_containing_return_addr' is -1, then the return address is
12295 actually on the stack, at the stack pointer. */
12297 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12299 unsigned regs_available_for_popping;
12300 unsigned regs_to_pop;
12302 unsigned available;
12306 int restore_a4 = FALSE;
12308 /* Compute the registers we need to pop. */
12312 /* There is an assumption here, that if eh_ofs is not NULL, the
12313 normal return address will have been pushed. */
12314 if (reg_containing_return_addr == -1 || eh_ofs)
12316 /* When we are generating a return for __builtin_eh_return,
12317 reg_containing_return_addr must specify the return regno. */
12318 if (eh_ofs && reg_containing_return_addr == -1)
12321 regs_to_pop |= 1 << LR_REGNUM;
12325 if (TARGET_BACKTRACE)
12327 /* Restore the (ARM) frame pointer and stack pointer. */
12328 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12332 /* If there is nothing to pop then just emit the BX instruction and
12334 if (pops_needed == 0)
12337 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12339 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12342 /* Otherwise if we are not supporting interworking and we have not created
12343 a backtrace structure and the function was not entered in ARM mode then
12344 just pop the return address straight into the PC. */
12345 else if (!TARGET_INTERWORK
12346 && !TARGET_BACKTRACE
12347 && !is_called_in_ARM_mode (current_function_decl))
12351 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12352 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12353 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12356 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12361 /* Find out how many of the (return) argument registers we can corrupt. */
12362 regs_available_for_popping = 0;
12364 /* If returning via __builtin_eh_return, the bottom three registers
12365 all contain information needed for the return. */
12371 /* If we can deduce the registers used from the function's
12372 return value. This is more reliable that examining
12373 regs_ever_live[] because that will be set if the register is
12374 ever used in the function, not just if the register is used
12375 to hold a return value. */
12377 if (current_function_return_rtx != 0)
12378 mode = GET_MODE (current_function_return_rtx);
12381 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12383 size = GET_MODE_SIZE (mode);
12387 /* In a void function we can use any argument register.
12388 In a function that returns a structure on the stack
12389 we can use the second and third argument registers. */
12390 if (mode == VOIDmode)
12391 regs_available_for_popping =
12392 (1 << ARG_REGISTER (1))
12393 | (1 << ARG_REGISTER (2))
12394 | (1 << ARG_REGISTER (3));
12396 regs_available_for_popping =
12397 (1 << ARG_REGISTER (2))
12398 | (1 << ARG_REGISTER (3));
12400 else if (size <= 4)
12401 regs_available_for_popping =
12402 (1 << ARG_REGISTER (2))
12403 | (1 << ARG_REGISTER (3));
12404 else if (size <= 8)
12405 regs_available_for_popping =
12406 (1 << ARG_REGISTER (3));
12409 /* Match registers to be popped with registers into which we pop them. */
12410 for (available = regs_available_for_popping,
12411 required = regs_to_pop;
12412 required != 0 && available != 0;
12413 available &= ~(available & - available),
12414 required &= ~(required & - required))
12417 /* If we have any popping registers left over, remove them. */
12419 regs_available_for_popping &= ~available;
12421 /* Otherwise if we need another popping register we can use
12422 the fourth argument register. */
12423 else if (pops_needed)
12425 /* If we have not found any free argument registers and
12426 reg a4 contains the return address, we must move it. */
12427 if (regs_available_for_popping == 0
12428 && reg_containing_return_addr == LAST_ARG_REGNUM)
12430 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12431 reg_containing_return_addr = LR_REGNUM;
12433 else if (size > 12)
12435 /* Register a4 is being used to hold part of the return value,
12436 but we have dire need of a free, low register. */
12439 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12442 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12444 /* The fourth argument register is available. */
12445 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12451 /* Pop as many registers as we can. */
12452 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12453 regs_available_for_popping);
12455 /* Process the registers we popped. */
12456 if (reg_containing_return_addr == -1)
12458 /* The return address was popped into the lowest numbered register. */
12459 regs_to_pop &= ~(1 << LR_REGNUM);
12461 reg_containing_return_addr =
12462 number_of_first_bit_set (regs_available_for_popping);
12464 /* Remove this register for the mask of available registers, so that
12465 the return address will not be corrupted by further pops. */
12466 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12469 /* If we popped other registers then handle them here. */
12470 if (regs_available_for_popping)
12474 /* Work out which register currently contains the frame pointer. */
12475 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12477 /* Move it into the correct place. */
12478 asm_fprintf (f, "\tmov\t%r, %r\n",
12479 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12481 /* (Temporarily) remove it from the mask of popped registers. */
12482 regs_available_for_popping &= ~(1 << frame_pointer);
12483 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12485 if (regs_available_for_popping)
12489 /* We popped the stack pointer as well,
12490 find the register that contains it. */
12491 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12493 /* Move it into the stack register. */
12494 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12496 /* At this point we have popped all necessary registers, so
12497 do not worry about restoring regs_available_for_popping
12498 to its correct value:
12500 assert (pops_needed == 0)
12501 assert (regs_available_for_popping == (1 << frame_pointer))
12502 assert (regs_to_pop == (1 << STACK_POINTER)) */
12506 /* Since we have just move the popped value into the frame
12507 pointer, the popping register is available for reuse, and
12508 we know that we still have the stack pointer left to pop. */
12509 regs_available_for_popping |= (1 << frame_pointer);
12513 /* If we still have registers left on the stack, but we no longer have
12514 any registers into which we can pop them, then we must move the return
12515 address into the link register and make available the register that
12517 if (regs_available_for_popping == 0 && pops_needed > 0)
12519 regs_available_for_popping |= 1 << reg_containing_return_addr;
12521 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12522 reg_containing_return_addr);
12524 reg_containing_return_addr = LR_REGNUM;
12527 /* If we have registers left on the stack then pop some more.
12528 We know that at most we will want to pop FP and SP. */
12529 if (pops_needed > 0)
12534 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12535 regs_available_for_popping);
12537 /* We have popped either FP or SP.
12538 Move whichever one it is into the correct register. */
12539 popped_into = number_of_first_bit_set (regs_available_for_popping);
12540 move_to = number_of_first_bit_set (regs_to_pop);
12542 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12544 regs_to_pop &= ~(1 << move_to);
12549 /* If we still have not popped everything then we must have only
12550 had one register available to us and we are now popping the SP. */
12551 if (pops_needed > 0)
12555 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12556 regs_available_for_popping);
12558 popped_into = number_of_first_bit_set (regs_available_for_popping);
12560 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12562 assert (regs_to_pop == (1 << STACK_POINTER))
12563 assert (pops_needed == 1)
12567 /* If necessary restore the a4 register. */
12570 if (reg_containing_return_addr != LR_REGNUM)
12572 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12573 reg_containing_return_addr = LR_REGNUM;
12576 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12580 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12582 /* Return to caller. */
12583 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12586 /* Emit code to push or pop registers to or from the stack. F is the
12587 assembly file. MASK is the registers to push or pop. PUSH is
12588 nonzero if we should push, and zero if we should pop. For debugging
12589 output, if pushing, adjust CFA_OFFSET by the amount of space added
12590 to the stack. REAL_REGS should have the same number of bits set as
12591 MASK, and will be used instead (in the same order) to describe which
12592 registers were saved - this is used to mark the save slots when we
12593 push high registers after moving them to low registers. */
12595 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12598 int lo_mask = mask & 0xFF;
12599 int pushed_words = 0;
12601 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12603 /* Special case. Do not generate a POP PC statement here, do it in
12605 thumb_exit (f, -1, NULL_RTX);
12609 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12611 /* Look at the low registers first. */
12612 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12616 asm_fprintf (f, "%r", regno);
12618 if ((lo_mask & ~1) != 0)
12625 if (push && (mask & (1 << LR_REGNUM)))
12627 /* Catch pushing the LR. */
12631 asm_fprintf (f, "%r", LR_REGNUM);
12635 else if (!push && (mask & (1 << PC_REGNUM)))
12637 /* Catch popping the PC. */
12638 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12640 /* The PC is never poped directly, instead
12641 it is popped into r3 and then BX is used. */
12642 fprintf (f, "}\n");
12644 thumb_exit (f, -1, NULL_RTX);
12653 asm_fprintf (f, "%r", PC_REGNUM);
12657 fprintf (f, "}\n");
12659 if (push && pushed_words && dwarf2out_do_frame ())
12661 char *l = dwarf2out_cfi_label ();
12662 int pushed_mask = real_regs;
12664 *cfa_offset += pushed_words * 4;
12665 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12668 pushed_mask = real_regs;
12669 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12671 if (pushed_mask & 1)
12672 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12678 thumb_final_prescan_insn (rtx insn)
12680 if (flag_print_asm_name)
12681 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12682 INSN_ADDRESSES (INSN_UID (insn)));
12686 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12688 unsigned HOST_WIDE_INT mask = 0xff;
12691 if (val == 0) /* XXX */
12694 for (i = 0; i < 25; i++)
12695 if ((val & (mask << i)) == val)
12701 /* Returns nonzero if the current function contains,
12702 or might contain a far jump. */
12704 thumb_far_jump_used_p (void)
12708 /* This test is only important for leaf functions. */
12709 /* assert (!leaf_function_p ()); */
12711 /* If we have already decided that far jumps may be used,
12712 do not bother checking again, and always return true even if
12713 it turns out that they are not being used. Once we have made
12714 the decision that far jumps are present (and that hence the link
12715 register will be pushed onto the stack) we cannot go back on it. */
12716 if (cfun->machine->far_jump_used)
12719 /* If this function is not being called from the prologue/epilogue
12720 generation code then it must be being called from the
12721 INITIAL_ELIMINATION_OFFSET macro. */
12722 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12724 /* In this case we know that we are being asked about the elimination
12725 of the arg pointer register. If that register is not being used,
12726 then there are no arguments on the stack, and we do not have to
12727 worry that a far jump might force the prologue to push the link
12728 register, changing the stack offsets. In this case we can just
12729 return false, since the presence of far jumps in the function will
12730 not affect stack offsets.
12732 If the arg pointer is live (or if it was live, but has now been
12733 eliminated and so set to dead) then we do have to test to see if
12734 the function might contain a far jump. This test can lead to some
12735 false negatives, since before reload is completed, then length of
12736 branch instructions is not known, so gcc defaults to returning their
12737 longest length, which in turn sets the far jump attribute to true.
12739 A false negative will not result in bad code being generated, but it
12740 will result in a needless push and pop of the link register. We
12741 hope that this does not occur too often.
12743 If we need doubleword stack alignment this could affect the other
12744 elimination offsets so we can't risk getting it wrong. */
12745 if (regs_ever_live [ARG_POINTER_REGNUM])
12746 cfun->machine->arg_pointer_live = 1;
12747 else if (!cfun->machine->arg_pointer_live)
12751 /* Check to see if the function contains a branch
12752 insn with the far jump attribute set. */
12753 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12755 if (GET_CODE (insn) == JUMP_INSN
12756 /* Ignore tablejump patterns. */
12757 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12758 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12759 && get_attr_far_jump (insn) == FAR_JUMP_YES
12762 /* Record the fact that we have decided that
12763 the function does use far jumps. */
12764 cfun->machine->far_jump_used = 1;
12772 /* Return nonzero if FUNC must be entered in ARM mode. */
12774 is_called_in_ARM_mode (tree func)
12776 if (TREE_CODE (func) != FUNCTION_DECL)
12779 /* Ignore the problem about functions whoes address is taken. */
12780 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12784 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12790 /* The bits which aren't usefully expanded as rtl. */
12792 thumb_unexpanded_epilogue (void)
12795 int live_regs_mask = 0;
12796 int high_regs_pushed = 0;
12797 int leaf_function = leaf_function_p ();
12798 int had_to_push_lr;
12799 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12801 if (return_used_this_function)
12804 if (IS_NAKED (arm_current_func_type ()))
12807 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12808 if (THUMB_REG_PUSHED_P (regno))
12809 live_regs_mask |= 1 << regno;
12811 for (regno = 8; regno < 13; regno++)
12812 if (THUMB_REG_PUSHED_P (regno))
12813 high_regs_pushed++;
12815 /* The prolog may have pushed some high registers to use as
12816 work registers. eg the testsuite file:
12817 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12818 compiles to produce:
12819 push {r4, r5, r6, r7, lr}
12823 as part of the prolog. We have to undo that pushing here. */
12825 if (high_regs_pushed)
12827 int mask = live_regs_mask;
12833 /* If we can deduce the registers used from the function's return value.
12834 This is more reliable that examining regs_ever_live[] because that
12835 will be set if the register is ever used in the function, not just if
12836 the register is used to hold a return value. */
12838 if (current_function_return_rtx != 0)
12839 mode = GET_MODE (current_function_return_rtx);
12842 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12844 size = GET_MODE_SIZE (mode);
12846 /* Unless we are returning a type of size > 12 register r3 is
12852 /* Oh dear! We have no low registers into which we can pop
12855 ("no low registers available for popping high registers");
12857 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12858 if (THUMB_REG_PUSHED_P (next_hi_reg))
12861 while (high_regs_pushed)
12863 /* Find lo register(s) into which the high register(s) can
12865 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12867 if (mask & (1 << regno))
12868 high_regs_pushed--;
12869 if (high_regs_pushed == 0)
12873 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12875 /* Pop the values into the low register(s). */
12876 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12878 /* Move the value(s) into the high registers. */
12879 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12881 if (mask & (1 << regno))
12883 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12886 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12887 if (THUMB_REG_PUSHED_P (next_hi_reg))
12894 had_to_push_lr = (live_regs_mask || !leaf_function
12895 || thumb_far_jump_used_p ());
12897 if (TARGET_BACKTRACE
12898 && ((live_regs_mask & 0xFF) == 0)
12899 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12901 /* The stack backtrace structure creation code had to
12902 push R7 in order to get a work register, so we pop
12904 live_regs_mask |= (1 << LAST_LO_REGNUM);
12907 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12910 && !is_called_in_ARM_mode (current_function_decl)
12912 live_regs_mask |= 1 << PC_REGNUM;
12914 /* Either no argument registers were pushed or a backtrace
12915 structure was created which includes an adjusted stack
12916 pointer, so just pop everything. */
12917 if (live_regs_mask)
12918 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12922 thumb_exit (asm_out_file, 2, eh_ofs);
12923 /* We have either just popped the return address into the
12924 PC or it is was kept in LR for the entire function or
12925 it is still on the stack because we do not want to
12926 return by doing a pop {pc}. */
12927 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
12928 thumb_exit (asm_out_file,
12930 && is_called_in_ARM_mode (current_function_decl)) ?
12931 -1 : LR_REGNUM, NULL_RTX);
12935 /* Pop everything but the return address. */
12936 live_regs_mask &= ~(1 << PC_REGNUM);
12938 if (live_regs_mask)
12939 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12942 if (had_to_push_lr)
12943 /* Get the return address into a temporary register. */
12944 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12945 1 << LAST_ARG_REGNUM);
12947 /* Remove the argument registers that were pushed onto the stack. */
12948 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12949 SP_REGNUM, SP_REGNUM,
12950 current_function_pretend_args_size);
12953 thumb_exit (asm_out_file, 2, eh_ofs);
12955 thumb_exit (asm_out_file,
12956 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
12962 /* Functions to save and restore machine-specific function data. */
12963 static struct machine_function *
12964 arm_init_machine_status (void)
12966 struct machine_function *machine;
12967 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12969 #if ARM_FT_UNKNOWN != 0
12970 machine->func_type = ARM_FT_UNKNOWN;
12975 /* Return an RTX indicating where the return address to the
12976 calling function can be found. */
12978 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12983 if (TARGET_APCS_32)
12984 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12987 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
12988 GEN_INT (RETURN_ADDR_MASK26));
12989 return get_func_hard_reg_initial_val (cfun, lr);
12993 /* Do anything needed before RTL is emitted for each function. */
12995 arm_init_expanders (void)
12997 /* Arrange to initialize and mark the machine per-function status. */
12998 init_machine_status = arm_init_machine_status;
13002 /* Like arm_compute_initial_elimination offset. Simpler because
13003 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13006 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13008 arm_stack_offsets *offsets;
13010 offsets = arm_get_frame_offsets ();
13014 case ARG_POINTER_REGNUM:
13017 case STACK_POINTER_REGNUM:
13018 return offsets->outgoing_args - offsets->saved_args;
13020 case FRAME_POINTER_REGNUM:
13021 return offsets->soft_frame - offsets->saved_args;
13023 case THUMB_HARD_FRAME_POINTER_REGNUM:
13024 case ARM_HARD_FRAME_POINTER_REGNUM:
13025 return offsets->saved_regs - offsets->saved_args;
13032 case FRAME_POINTER_REGNUM:
13035 case STACK_POINTER_REGNUM:
13036 return offsets->outgoing_args - offsets->soft_frame;
13038 case THUMB_HARD_FRAME_POINTER_REGNUM:
13039 case ARM_HARD_FRAME_POINTER_REGNUM:
13040 return offsets->saved_regs - offsets->soft_frame;
13053 /* Generate the rest of a function's prologue. */
13055 thumb_expand_prologue (void)
13059 HOST_WIDE_INT amount;
13060 arm_stack_offsets *offsets;
13061 unsigned long func_type;
13063 func_type = arm_current_func_type ();
13065 /* Naked functions don't have prologues. */
13066 if (IS_NAKED (func_type))
13069 if (IS_INTERRUPT (func_type))
13071 error ("interrupt Service Routines cannot be coded in Thumb mode");
13075 offsets = arm_get_frame_offsets ();
13077 if (frame_pointer_needed)
13079 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13080 stack_pointer_rtx));
13081 RTX_FRAME_RELATED_P (insn) = 1;
13084 amount = offsets->outgoing_args - offsets->saved_regs;
13089 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13090 GEN_INT (- amount)));
13091 RTX_FRAME_RELATED_P (insn) = 1;
13098 /* The stack decrement is too big for an immediate value in a single
13099 insn. In theory we could issue multiple subtracts, but after
13100 three of them it becomes more space efficient to place the full
13101 value in the constant pool and load into a register. (Also the
13102 ARM debugger really likes to see only one stack decrement per
13103 function). So instead we look for a scratch register into which
13104 we can load the decrement, and then we subtract this from the
13105 stack pointer. Unfortunately on the thumb the only available
13106 scratch registers are the argument registers, and we cannot use
13107 these as they may hold arguments to the function. Instead we
13108 attempt to locate a call preserved register which is used by this
13109 function. If we can find one, then we know that it will have
13110 been pushed at the start of the prologue and so we can corrupt
13112 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13113 if (THUMB_REG_PUSHED_P (regno)
13114 && !(frame_pointer_needed
13115 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13118 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13120 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13122 /* Choose an arbitrary, non-argument low register. */
13123 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13125 /* Save it by copying it into a high, scratch register. */
13126 emit_insn (gen_movsi (spare, reg));
13127 /* Add a USE to stop propagate_one_insn() from barfing. */
13128 emit_insn (gen_prologue_use (spare));
13130 /* Decrement the stack. */
13131 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13132 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13133 stack_pointer_rtx, reg));
13134 RTX_FRAME_RELATED_P (insn) = 1;
13135 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13136 plus_constant (stack_pointer_rtx,
13137 GEN_INT (- amount)));
13138 RTX_FRAME_RELATED_P (dwarf) = 1;
13140 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13143 /* Restore the low register's original value. */
13144 emit_insn (gen_movsi (reg, spare));
13146 /* Emit a USE of the restored scratch register, so that flow
13147 analysis will not consider the restore redundant. The
13148 register won't be used again in this function and isn't
13149 restored by the epilogue. */
13150 emit_insn (gen_prologue_use (reg));
13154 reg = gen_rtx_REG (SImode, regno);
13156 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13158 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13159 stack_pointer_rtx, reg));
13160 RTX_FRAME_RELATED_P (insn) = 1;
13161 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13162 plus_constant (stack_pointer_rtx,
13163 GEN_INT (- amount)));
13164 RTX_FRAME_RELATED_P (dwarf) = 1;
13166 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13170 /* If the frame pointer is needed, emit a special barrier that
13171 will prevent the scheduler from moving stores to the frame
13172 before the stack adjustment. */
13173 if (frame_pointer_needed)
13174 emit_insn (gen_stack_tie (stack_pointer_rtx,
13175 hard_frame_pointer_rtx));
13178 if (current_function_profile || TARGET_NO_SCHED_PRO)
13179 emit_insn (gen_blockage ());
13183 thumb_expand_epilogue (void)
13185 HOST_WIDE_INT amount;
13186 arm_stack_offsets *offsets;
13189 /* Naked functions don't have prologues. */
13190 if (IS_NAKED (arm_current_func_type ()))
13193 offsets = arm_get_frame_offsets ();
13194 amount = offsets->outgoing_args - offsets->saved_regs;
13196 if (frame_pointer_needed)
13197 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13201 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13202 GEN_INT (amount)));
13205 /* r3 is always free in the epilogue. */
13206 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13208 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13209 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13213 /* Emit a USE (stack_pointer_rtx), so that
13214 the stack adjustment will not be deleted. */
13215 emit_insn (gen_prologue_use (stack_pointer_rtx));
13217 if (current_function_profile || TARGET_NO_SCHED_PRO)
13218 emit_insn (gen_blockage ());
13220 /* Emit a clobber for each insn that will be restored in the epilogue,
13221 so that flow2 will get register lifetimes correct. */
13222 for (regno = 0; regno < 13; regno++)
13223 if (regs_ever_live[regno] && !call_used_regs[regno])
13224 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13226 if (! regs_ever_live[LR_REGNUM])
13227 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13231 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13233 int live_regs_mask = 0;
13234 int high_regs_pushed = 0;
13235 int cfa_offset = 0;
13238 if (IS_NAKED (arm_current_func_type ()))
13241 if (is_called_in_ARM_mode (current_function_decl))
13245 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13247 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13249 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13251 /* Generate code sequence to switch us into Thumb mode. */
13252 /* The .code 32 directive has already been emitted by
13253 ASM_DECLARE_FUNCTION_NAME. */
13254 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13255 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13257 /* Generate a label, so that the debugger will notice the
13258 change in instruction sets. This label is also used by
13259 the assembler to bypass the ARM code when this function
13260 is called from a Thumb encoded function elsewhere in the
13261 same file. Hence the definition of STUB_NAME here must
13262 agree with the definition in gas/config/tc-arm.c. */
13264 #define STUB_NAME ".real_start_of"
13266 fprintf (f, "\t.code\t16\n");
13268 if (arm_dllexport_name_p (name))
13269 name = arm_strip_name_encoding (name);
13271 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13272 fprintf (f, "\t.thumb_func\n");
13273 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13276 if (current_function_pretend_args_size)
13278 if (cfun->machine->uses_anonymous_args)
13282 fprintf (f, "\tpush\t{");
13284 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13286 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13287 regno <= LAST_ARG_REGNUM;
13289 asm_fprintf (f, "%r%s", regno,
13290 regno == LAST_ARG_REGNUM ? "" : ", ");
13292 fprintf (f, "}\n");
13295 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13296 SP_REGNUM, SP_REGNUM,
13297 current_function_pretend_args_size);
13299 /* We don't need to record the stores for unwinding (would it
13300 help the debugger any if we did?), but record the change in
13301 the stack pointer. */
13302 if (dwarf2out_do_frame ())
13304 char *l = dwarf2out_cfi_label ();
13305 cfa_offset = cfa_offset + current_function_pretend_args_size;
13306 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13310 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13311 if (THUMB_REG_PUSHED_P (regno))
13312 live_regs_mask |= 1 << regno;
13314 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p ())
13315 live_regs_mask |= 1 << LR_REGNUM;
13317 if (TARGET_BACKTRACE)
13320 int work_register = 0;
13323 /* We have been asked to create a stack backtrace structure.
13324 The code looks like this:
13328 0 sub SP, #16 Reserve space for 4 registers.
13329 2 push {R7} Get a work register.
13330 4 add R7, SP, #20 Get the stack pointer before the push.
13331 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13332 8 mov R7, PC Get hold of the start of this code plus 12.
13333 10 str R7, [SP, #16] Store it.
13334 12 mov R7, FP Get hold of the current frame pointer.
13335 14 str R7, [SP, #4] Store it.
13336 16 mov R7, LR Get hold of the current return address.
13337 18 str R7, [SP, #12] Store it.
13338 20 add R7, SP, #16 Point at the start of the backtrace structure.
13339 22 mov FP, R7 Put this value into the frame pointer. */
13341 if ((live_regs_mask & 0xFF) == 0)
13343 /* See if the a4 register is free. */
13345 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13346 work_register = LAST_ARG_REGNUM;
13347 else /* We must push a register of our own. */
13348 live_regs_mask |= (1 << LAST_LO_REGNUM);
13351 if (work_register == 0)
13353 /* Select a register from the list that will be pushed to
13354 use as our work register. */
13355 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13356 if ((1 << work_register) & live_regs_mask)
13361 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13362 SP_REGNUM, SP_REGNUM);
13364 if (dwarf2out_do_frame ())
13366 char *l = dwarf2out_cfi_label ();
13367 cfa_offset = cfa_offset + 16;
13368 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13371 if (live_regs_mask)
13372 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13374 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13375 if (wr & live_regs_mask)
13378 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13379 offset + 16 + current_function_pretend_args_size);
13381 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13384 /* Make sure that the instruction fetching the PC is in the right place
13385 to calculate "start of backtrace creation code + 12". */
13386 if (live_regs_mask)
13388 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13389 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13391 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13392 ARM_HARD_FRAME_POINTER_REGNUM);
13393 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13398 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13399 ARM_HARD_FRAME_POINTER_REGNUM);
13400 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13402 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13403 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13407 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13408 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13410 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13412 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13413 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13415 else if (live_regs_mask)
13416 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13418 for (regno = 8; regno < 13; regno++)
13419 if (THUMB_REG_PUSHED_P (regno))
13420 high_regs_pushed++;
13422 if (high_regs_pushed)
13424 int pushable_regs = 0;
13425 int mask = live_regs_mask & 0xff;
13428 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13429 if (THUMB_REG_PUSHED_P (next_hi_reg))
13432 pushable_regs = mask;
13434 if (pushable_regs == 0)
13436 /* Desperation time -- this probably will never happen. */
13437 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13438 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13439 mask = 1 << LAST_ARG_REGNUM;
13442 while (high_regs_pushed > 0)
13444 int real_regs_mask = 0;
13446 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13448 if (mask & (1 << regno))
13450 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13452 high_regs_pushed--;
13453 real_regs_mask |= (1 << next_hi_reg);
13455 if (high_regs_pushed)
13457 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13459 if (THUMB_REG_PUSHED_P (next_hi_reg))
13464 mask &= ~((1 << regno) - 1);
13470 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13473 if (pushable_regs == 0
13474 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13475 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13479 /* Handle the case of a double word load into a low register from
13480 a computed memory address. The computed address may involve a
13481 register which is overwritten by the load. */
13483 thumb_load_double_from_address (rtx *operands)
13491 if (GET_CODE (operands[0]) != REG)
13494 if (GET_CODE (operands[1]) != MEM)
13497 /* Get the memory address. */
13498 addr = XEXP (operands[1], 0);
13500 /* Work out how the memory address is computed. */
13501 switch (GET_CODE (addr))
13504 operands[2] = gen_rtx_MEM (SImode,
13505 plus_constant (XEXP (operands[1], 0), 4));
13507 if (REGNO (operands[0]) == REGNO (addr))
13509 output_asm_insn ("ldr\t%H0, %2", operands);
13510 output_asm_insn ("ldr\t%0, %1", operands);
13514 output_asm_insn ("ldr\t%0, %1", operands);
13515 output_asm_insn ("ldr\t%H0, %2", operands);
13520 /* Compute <address> + 4 for the high order load. */
13521 operands[2] = gen_rtx_MEM (SImode,
13522 plus_constant (XEXP (operands[1], 0), 4));
13524 output_asm_insn ("ldr\t%0, %1", operands);
13525 output_asm_insn ("ldr\t%H0, %2", operands);
13529 arg1 = XEXP (addr, 0);
13530 arg2 = XEXP (addr, 1);
13532 if (CONSTANT_P (arg1))
13533 base = arg2, offset = arg1;
13535 base = arg1, offset = arg2;
13537 if (GET_CODE (base) != REG)
13540 /* Catch the case of <address> = <reg> + <reg> */
13541 if (GET_CODE (offset) == REG)
13543 int reg_offset = REGNO (offset);
13544 int reg_base = REGNO (base);
13545 int reg_dest = REGNO (operands[0]);
13547 /* Add the base and offset registers together into the
13548 higher destination register. */
13549 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13550 reg_dest + 1, reg_base, reg_offset);
13552 /* Load the lower destination register from the address in
13553 the higher destination register. */
13554 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13555 reg_dest, reg_dest + 1);
13557 /* Load the higher destination register from its own address
13559 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13560 reg_dest + 1, reg_dest + 1);
13564 /* Compute <address> + 4 for the high order load. */
13565 operands[2] = gen_rtx_MEM (SImode,
13566 plus_constant (XEXP (operands[1], 0), 4));
13568 /* If the computed address is held in the low order register
13569 then load the high order register first, otherwise always
13570 load the low order register first. */
13571 if (REGNO (operands[0]) == REGNO (base))
13573 output_asm_insn ("ldr\t%H0, %2", operands);
13574 output_asm_insn ("ldr\t%0, %1", operands);
13578 output_asm_insn ("ldr\t%0, %1", operands);
13579 output_asm_insn ("ldr\t%H0, %2", operands);
13585 /* With no registers to worry about we can just load the value
13587 operands[2] = gen_rtx_MEM (SImode,
13588 plus_constant (XEXP (operands[1], 0), 4));
13590 output_asm_insn ("ldr\t%H0, %2", operands);
13591 output_asm_insn ("ldr\t%0, %1", operands);
13603 thumb_output_move_mem_multiple (int n, rtx *operands)
13610 if (REGNO (operands[4]) > REGNO (operands[5]))
13613 operands[4] = operands[5];
13616 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13617 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13621 if (REGNO (operands[4]) > REGNO (operands[5]))
13624 operands[4] = operands[5];
13627 if (REGNO (operands[5]) > REGNO (operands[6]))
13630 operands[5] = operands[6];
13633 if (REGNO (operands[4]) > REGNO (operands[5]))
13636 operands[4] = operands[5];
13640 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13641 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13651 /* Routines for generating rtl. */
13653 thumb_expand_movstrqi (rtx *operands)
13655 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13656 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13657 HOST_WIDE_INT len = INTVAL (operands[2]);
13658 HOST_WIDE_INT offset = 0;
13662 emit_insn (gen_movmem12b (out, in, out, in));
13668 emit_insn (gen_movmem8b (out, in, out, in));
13674 rtx reg = gen_reg_rtx (SImode);
13675 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13676 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13683 rtx reg = gen_reg_rtx (HImode);
13684 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13685 plus_constant (in, offset))));
13686 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13694 rtx reg = gen_reg_rtx (QImode);
13695 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13696 plus_constant (in, offset))));
13697 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13703 thumb_cmp_operand (rtx op, enum machine_mode mode)
13705 return ((GET_CODE (op) == CONST_INT
13706 && INTVAL (op) < 256
13707 && INTVAL (op) >= 0)
13708 || s_register_operand (op, mode));
13712 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13714 return (GET_CODE (op) == CONST_INT
13716 && INTVAL (op) > -256);
13719 /* Return TRUE if a result can be stored in OP without clobbering the
13720 condition code register. Prior to reload we only accept a
13721 register. After reload we have to be able to handle memory as
13722 well, since a pseudo may not get a hard reg and reload cannot
13723 handle output-reloads on jump insns.
13725 We could possibly handle mem before reload as well, but that might
13726 complicate things with the need to handle increment
13730 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13732 return (s_register_operand (op, mode)
13733 || ((reload_in_progress || reload_completed)
13734 && memory_operand (op, mode)));
13737 /* Handle storing a half-word to memory during reload. */
13739 thumb_reload_out_hi (rtx *operands)
13741 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13744 /* Handle reading a half-word from memory during reload. */
13746 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13751 /* Return the length of a function name prefix
13752 that starts with the character 'c'. */
13754 arm_get_strip_length (int c)
13758 ARM_NAME_ENCODING_LENGTHS
13763 /* Return a pointer to a function's name with any
13764 and all prefix encodings stripped from it. */
13766 arm_strip_name_encoding (const char *name)
13770 while ((skip = arm_get_strip_length (* name)))
13776 /* If there is a '*' anywhere in the name's prefix, then
13777 emit the stripped name verbatim, otherwise prepend an
13778 underscore if leading underscores are being used. */
13780 arm_asm_output_labelref (FILE *stream, const char *name)
13785 while ((skip = arm_get_strip_length (* name)))
13787 verbatim |= (*name == '*');
13792 fputs (name, stream);
13794 asm_fprintf (stream, "%U%s", name);
13799 #ifdef AOF_ASSEMBLER
13800 /* Special functions only needed when producing AOF syntax assembler. */
13804 struct pic_chain * next;
13805 const char * symname;
13808 static struct pic_chain * aof_pic_chain = NULL;
13811 aof_pic_entry (rtx x)
13813 struct pic_chain ** chainp;
13816 if (aof_pic_label == NULL_RTX)
13818 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13821 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13822 offset += 4, chainp = &(*chainp)->next)
13823 if ((*chainp)->symname == XSTR (x, 0))
13824 return plus_constant (aof_pic_label, offset);
13826 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13827 (*chainp)->next = NULL;
13828 (*chainp)->symname = XSTR (x, 0);
13829 return plus_constant (aof_pic_label, offset);
13833 aof_dump_pic_table (FILE *f)
13835 struct pic_chain * chain;
13837 if (aof_pic_chain == NULL)
13840 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13841 PIC_OFFSET_TABLE_REGNUM,
13842 PIC_OFFSET_TABLE_REGNUM);
13843 fputs ("|x$adcons|\n", f);
13845 for (chain = aof_pic_chain; chain; chain = chain->next)
13847 fputs ("\tDCD\t", f);
13848 assemble_name (f, chain->symname);
13853 int arm_text_section_count = 1;
13856 aof_text_section (void )
13858 static char buf[100];
13859 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13860 arm_text_section_count++);
13862 strcat (buf, ", PIC, REENTRANT");
13866 static int arm_data_section_count = 1;
13869 aof_data_section (void)
13871 static char buf[100];
13872 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13876 /* The AOF assembler is religiously strict about declarations of
13877 imported and exported symbols, so that it is impossible to declare
13878 a function as imported near the beginning of the file, and then to
13879 export it later on. It is, however, possible to delay the decision
13880 until all the functions in the file have been compiled. To get
13881 around this, we maintain a list of the imports and exports, and
13882 delete from it any that are subsequently defined. At the end of
13883 compilation we spit the remainder of the list out before the END
13888 struct import * next;
13892 static struct import * imports_list = NULL;
13895 aof_add_import (const char *name)
13897 struct import * new;
13899 for (new = imports_list; new; new = new->next)
13900 if (new->name == name)
13903 new = (struct import *) xmalloc (sizeof (struct import));
13904 new->next = imports_list;
13905 imports_list = new;
13910 aof_delete_import (const char *name)
13912 struct import ** old;
13914 for (old = &imports_list; *old; old = & (*old)->next)
13916 if ((*old)->name == name)
13918 *old = (*old)->next;
13924 int arm_main_function = 0;
13927 aof_dump_imports (FILE *f)
13929 /* The AOF assembler needs this to cause the startup code to be extracted
13930 from the library. Brining in __main causes the whole thing to work
13932 if (arm_main_function)
13935 fputs ("\tIMPORT __main\n", f);
13936 fputs ("\tDCD __main\n", f);
13939 /* Now dump the remaining imports. */
13940 while (imports_list)
13942 fprintf (f, "\tIMPORT\t");
13943 assemble_name (f, imports_list->name);
13945 imports_list = imports_list->next;
13950 aof_globalize_label (FILE *stream, const char *name)
13952 default_globalize_label (stream, name);
13953 if (! strcmp (name, "main"))
13954 arm_main_function = 1;
13958 aof_file_start (void)
13960 fputs ("__r0\tRN\t0\n", asm_out_file);
13961 fputs ("__a1\tRN\t0\n", asm_out_file);
13962 fputs ("__a2\tRN\t1\n", asm_out_file);
13963 fputs ("__a3\tRN\t2\n", asm_out_file);
13964 fputs ("__a4\tRN\t3\n", asm_out_file);
13965 fputs ("__v1\tRN\t4\n", asm_out_file);
13966 fputs ("__v2\tRN\t5\n", asm_out_file);
13967 fputs ("__v3\tRN\t6\n", asm_out_file);
13968 fputs ("__v4\tRN\t7\n", asm_out_file);
13969 fputs ("__v5\tRN\t8\n", asm_out_file);
13970 fputs ("__v6\tRN\t9\n", asm_out_file);
13971 fputs ("__sl\tRN\t10\n", asm_out_file);
13972 fputs ("__fp\tRN\t11\n", asm_out_file);
13973 fputs ("__ip\tRN\t12\n", asm_out_file);
13974 fputs ("__sp\tRN\t13\n", asm_out_file);
13975 fputs ("__lr\tRN\t14\n", asm_out_file);
13976 fputs ("__pc\tRN\t15\n", asm_out_file);
13977 fputs ("__f0\tFN\t0\n", asm_out_file);
13978 fputs ("__f1\tFN\t1\n", asm_out_file);
13979 fputs ("__f2\tFN\t2\n", asm_out_file);
13980 fputs ("__f3\tFN\t3\n", asm_out_file);
13981 fputs ("__f4\tFN\t4\n", asm_out_file);
13982 fputs ("__f5\tFN\t5\n", asm_out_file);
13983 fputs ("__f6\tFN\t6\n", asm_out_file);
13984 fputs ("__f7\tFN\t7\n", asm_out_file);
13989 aof_file_end (void)
13992 aof_dump_pic_table (asm_out_file);
13993 aof_dump_imports (asm_out_file);
13994 fputs ("\tEND\n", asm_out_file);
13996 #endif /* AOF_ASSEMBLER */
13998 #ifdef OBJECT_FORMAT_ELF
13999 /* Switch to an arbitrary section NAME with attributes as specified
14000 by FLAGS. ALIGN specifies any known alignment requirements for
14001 the section; 0 if the default should be used.
14003 Differs from the default elf version only in the prefix character
14004 used before the section type. */
14007 arm_elf_asm_named_section (const char *name, unsigned int flags)
14009 char flagchars[10], *f = flagchars;
14011 if (! named_section_first_declaration (name))
14013 fprintf (asm_out_file, "\t.section\t%s\n", name);
14017 if (!(flags & SECTION_DEBUG))
14019 if (flags & SECTION_WRITE)
14021 if (flags & SECTION_CODE)
14023 if (flags & SECTION_SMALL)
14025 if (flags & SECTION_MERGE)
14027 if (flags & SECTION_STRINGS)
14029 if (flags & SECTION_TLS)
14033 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14035 if (!(flags & SECTION_NOTYPE))
14039 if (flags & SECTION_BSS)
14044 fprintf (asm_out_file, ",%%%s", type);
14046 if (flags & SECTION_ENTSIZE)
14047 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14050 putc ('\n', asm_out_file);
14055 /* Symbols in the text segment can be accessed without indirecting via the
14056 constant pool; it may take an extra binary operation, but this is still
14057 faster than indirecting via memory. Don't do this when not optimizing,
14058 since we won't be calculating al of the offsets necessary to do this
14062 arm_encode_section_info (tree decl, rtx rtl, int first)
14064 /* This doesn't work with AOF syntax, since the string table may be in
14065 a different AREA. */
14066 #ifndef AOF_ASSEMBLER
14067 if (optimize > 0 && TREE_CONSTANT (decl))
14068 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14071 /* If we are referencing a function that is weak then encode a long call
14072 flag in the function name, otherwise if the function is static or
14073 or known to be defined in this file then encode a short call flag. */
14074 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14076 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14077 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14078 else if (! TREE_PUBLIC (decl))
14079 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14082 #endif /* !ARM_PE */
14085 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14087 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14088 && !strcmp (prefix, "L"))
14090 arm_ccfsm_state = 0;
14091 arm_target_insn = NULL;
14093 default_internal_label (stream, prefix, labelno);
14096 /* Output code to add DELTA to the first argument, and then jump
14097 to FUNCTION. Used for C++ multiple inheritance. */
14099 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14100 HOST_WIDE_INT delta,
14101 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14104 static int thunk_label = 0;
14106 int mi_delta = delta;
14107 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14109 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14112 mi_delta = - mi_delta;
14115 int labelno = thunk_label++;
14116 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14117 fputs ("\tldr\tr12, ", file);
14118 assemble_name (file, label);
14119 fputc ('\n', file);
14121 while (mi_delta != 0)
14123 if ((mi_delta & (3 << shift)) == 0)
14127 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14128 mi_op, this_regno, this_regno,
14129 mi_delta & (0xff << shift));
14130 mi_delta &= ~(0xff << shift);
14136 fprintf (file, "\tbx\tr12\n");
14137 ASM_OUTPUT_ALIGN (file, 2);
14138 assemble_name (file, label);
14139 fputs (":\n", file);
14140 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14144 fputs ("\tb\t", file);
14145 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14146 if (NEED_PLT_RELOC)
14147 fputs ("(PLT)", file);
14148 fputc ('\n', file);
14153 arm_emit_vector_const (FILE *file, rtx x)
14156 const char * pattern;
14158 if (GET_CODE (x) != CONST_VECTOR)
14161 switch (GET_MODE (x))
14163 case V2SImode: pattern = "%08x"; break;
14164 case V4HImode: pattern = "%04x"; break;
14165 case V8QImode: pattern = "%02x"; break;
14169 fprintf (file, "0x");
14170 for (i = CONST_VECTOR_NUNITS (x); i--;)
14174 element = CONST_VECTOR_ELT (x, i);
14175 fprintf (file, pattern, INTVAL (element));
14182 arm_output_load_gr (rtx *operands)
14189 if (GET_CODE (operands [1]) != MEM
14190 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14191 || GET_CODE (reg = XEXP (sum, 0)) != REG
14192 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14193 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14194 return "wldrw%?\t%0, %1";
14196 /* Fix up an out-of-range load of a GR register. */
14197 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14198 wcgr = operands[0];
14200 output_asm_insn ("ldr%?\t%0, %1", operands);
14202 operands[0] = wcgr;
14204 output_asm_insn ("tmcr%?\t%0, %1", operands);
14205 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14211 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14212 int incoming ATTRIBUTE_UNUSED)
14215 /* FIXME: The ARM backend has special code to handle structure
14216 returns, and will reserve its own hidden first argument. So
14217 if this macro is enabled a *second* hidden argument will be
14218 reserved, which will break binary compatibility with old
14219 toolchains and also thunk handling. One day this should be
14223 /* Register in which address to store a structure value
14224 is passed to a function. */
14225 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14229 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14231 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14232 named arg and all anonymous args onto the stack.
14233 XXX I know the prologue shouldn't be pushing registers, but it is faster
14237 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14238 enum machine_mode mode ATTRIBUTE_UNUSED,
14239 tree type ATTRIBUTE_UNUSED,
14241 int second_time ATTRIBUTE_UNUSED)
14243 cfun->machine->uses_anonymous_args = 1;
14244 if (cum->nregs < NUM_ARG_REGS)
14245 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14248 /* Return nonzero if the CONSUMER instruction (a store) does not need
14249 PRODUCER's value to calculate the address. */
14252 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14254 rtx value = PATTERN (producer);
14255 rtx addr = PATTERN (consumer);
14257 if (GET_CODE (value) == COND_EXEC)
14258 value = COND_EXEC_CODE (value);
14259 if (GET_CODE (value) == PARALLEL)
14260 value = XVECEXP (value, 0, 0);
14261 value = XEXP (value, 0);
14262 if (GET_CODE (addr) == COND_EXEC)
14263 addr = COND_EXEC_CODE (addr);
14264 if (GET_CODE (addr) == PARALLEL)
14265 addr = XVECEXP (addr, 0, 0);
14266 addr = XEXP (addr, 0);
14268 return !reg_overlap_mentioned_p (value, addr);
14271 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14272 have an early register shift value or amount dependency on the
14273 result of PRODUCER. */
14276 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14278 rtx value = PATTERN (producer);
14279 rtx op = PATTERN (consumer);
14282 if (GET_CODE (value) == COND_EXEC)
14283 value = COND_EXEC_CODE (value);
14284 if (GET_CODE (value) == PARALLEL)
14285 value = XVECEXP (value, 0, 0);
14286 value = XEXP (value, 0);
14287 if (GET_CODE (op) == COND_EXEC)
14288 op = COND_EXEC_CODE (op);
14289 if (GET_CODE (op) == PARALLEL)
14290 op = XVECEXP (op, 0, 0);
14293 early_op = XEXP (op, 0);
14294 /* This is either an actual independent shift, or a shift applied to
14295 the first operand of another operation. We want the whole shift
14297 if (GET_CODE (early_op) == REG)
14300 return !reg_overlap_mentioned_p (value, early_op);
14303 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14304 have an early register shift value dependency on the result of
14308 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14310 rtx value = PATTERN (producer);
14311 rtx op = PATTERN (consumer);
14314 if (GET_CODE (value) == COND_EXEC)
14315 value = COND_EXEC_CODE (value);
14316 if (GET_CODE (value) == PARALLEL)
14317 value = XVECEXP (value, 0, 0);
14318 value = XEXP (value, 0);
14319 if (GET_CODE (op) == COND_EXEC)
14320 op = COND_EXEC_CODE (op);
14321 if (GET_CODE (op) == PARALLEL)
14322 op = XVECEXP (op, 0, 0);
14325 early_op = XEXP (op, 0);
14327 /* This is either an actual independent shift, or a shift applied to
14328 the first operand of another operation. We want the value being
14329 shifted, in either case. */
14330 if (GET_CODE (early_op) != REG)
14331 early_op = XEXP (early_op, 0);
14333 return !reg_overlap_mentioned_p (value, early_op);
14336 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14337 have an early register mult dependency on the result of
14341 arm_no_early_mul_dep (rtx producer, rtx consumer)
14343 rtx value = PATTERN (producer);
14344 rtx op = PATTERN (consumer);
14346 if (GET_CODE (value) == COND_EXEC)
14347 value = COND_EXEC_CODE (value);
14348 if (GET_CODE (value) == PARALLEL)
14349 value = XVECEXP (value, 0, 0);
14350 value = XEXP (value, 0);
14351 if (GET_CODE (op) == COND_EXEC)
14352 op = COND_EXEC_CODE (op);
14353 if (GET_CODE (op) == PARALLEL)
14354 op = XVECEXP (op, 0, 0);
14357 return (GET_CODE (op) == PLUS
14358 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));