1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Define an insn type attribute. This is used in function unit delay
25 ;; computations, among other purposes. For the most part, we use the names
26 ;; defined in the EV4 documentation, but add a few that we have to know about
30 "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr"
31 (const_string "shiftcm"))
33 ;; We include four function units: ABOX, which computes the address,
34 ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
35 ;; used for FP operations.
37 ;; We assume that we have been successful in getting double issues and
38 ;; hence multiply all costs by two insns per cycle. The minimum time in
39 ;; a function unit is 2 cycle, which will tend to produce the double
42 ;; Memory delivers its result in three cycles.
43 (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2)
45 ;; Branches have no delay cost, but do tie up the unit for two cycles.
46 (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4)
48 ;; Arithmetic insns are normally have their results available after two
49 ;; cycles. There are a number of exceptions. They are encoded in
50 ;; ADJUST_COST. Some of the other insns have similar exceptions.
52 (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2)
54 ;; These really don't take up the integer pipeline, but they do occupy
55 ;; IBOX1; we approximate here.
57 (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2)
58 (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2)
60 (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38)
61 (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42)
63 (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2)
65 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0)
66 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0)
68 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60)
69 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118)
71 ;; First define the arithmetic insns. Note that the 32-bit forms also
74 ;; Note that we can do sign extensions in both FP and integer registers.
75 ;; However, the result must be in the same type of register as the input.
76 ;; The register preferencing code can't handle this case very well, so, for
77 ;; now, don't let the FP case show up here for preferencing. Also,
78 ;; sign-extends in FP registers take two instructions.
79 (define_insn "extendsidi2"
80 [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
81 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
86 cvtql %1,%0\;cvtlq %0,%0"
87 [(set_attr "type" "iaddlog,ld,fpop")])
89 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
90 ;; generates better code. We have the anonymous addsi3 pattern below in
91 ;; case combine wants to make it.
92 (define_expand "addsi3"
93 [(set (match_operand:SI 0 "register_operand" "")
94 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
95 (match_operand:SI 2 "add_operand" "")))]
98 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
99 gen_rtx (PLUS, DImode,
100 gen_lowpart (DImode, operands[1]),
101 gen_lowpart (DImode, operands[2]))));
106 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
107 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
108 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
115 [(set_attr "type" "iaddlog")])
118 [(set (match_operand:SI 0 "register_operand" "")
119 (plus:SI (match_operand:SI 1 "register_operand" "")
120 (match_operand:SI 2 "const_int_operand" "")))]
121 "! add_operand (operands[2], SImode)"
122 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
123 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
126 HOST_WIDE_INT val = INTVAL (operands[2]);
127 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
128 HOST_WIDE_INT rest = val - low;
130 operands[3] = GEN_INT (rest);
131 operands[4] = GEN_INT (low);
135 [(set (match_operand:DI 0 "register_operand" "=r,r")
137 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
138 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
143 [(set_attr "type" "iaddlog")])
146 [(set (match_operand:DI 0 "register_operand" "")
148 (plus:SI (match_operand:SI 1 "register_operand" "")
149 (match_operand:SI 2 "const_int_operand" ""))))
150 (clobber (match_operand:SI 3 "register_operand" ""))]
151 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
152 && INTVAL (operands[2]) % 4 == 0"
153 [(set (match_dup 3) (match_dup 4))
154 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
159 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
165 operands[4] = GEN_INT (val);
166 operands[5] = GEN_INT (mult);
170 [(set (match_operand:DI 0 "register_operand" "")
172 (plus:SI (match_operator:SI 1 "comparison_operator"
173 [(match_operand 2 "" "")
174 (match_operand 3 "" "")])
175 (match_operand:SI 4 "add_operand" ""))))
176 (clobber (match_operand:DI 5 "register_operand" ""))]
178 [(set (match_dup 5) (match_dup 6))
179 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
182 operands[6] = gen_rtx (GET_CODE (operands[1]), DImode,
183 operands[2], operands[3]);
184 operands[7] = gen_lowpart (SImode, operands[5]);
187 (define_insn "adddi3"
188 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
189 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
190 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
197 [(set_attr "type" "iaddlog")])
199 ;; Don't do this if we are adjusting SP since we don't want to do
202 [(set (match_operand:DI 0 "register_operand" "")
203 (plus:DI (match_operand:DI 1 "register_operand" "")
204 (match_operand:DI 2 "const_int_operand" "")))]
205 "! add_operand (operands[2], DImode)
206 && REGNO (operands[0]) != STACK_POINTER_REGNUM"
207 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
208 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
211 HOST_WIDE_INT val = INTVAL (operands[2]);
212 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
213 HOST_WIDE_INT rest = val - low;
215 operands[3] = GEN_INT (rest);
216 operands[4] = GEN_INT (low);
220 [(set (match_operand:SI 0 "register_operand" "=r,r")
221 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
222 (match_operand:SI 2 "const48_operand" "I,I"))
223 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
228 [(set_attr "type" "iaddlog")])
231 [(set (match_operand:DI 0 "register_operand" "=r,r")
233 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
234 (match_operand:SI 2 "const48_operand" "I,I"))
235 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
240 [(set_attr "type" "iaddlog")])
243 [(set (match_operand:DI 0 "register_operand" "")
245 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
246 [(match_operand 2 "" "")
247 (match_operand 3 "" "")])
248 (match_operand:SI 4 "const48_operand" ""))
249 (match_operand:SI 5 "add_operand" ""))))
250 (clobber (match_operand:DI 6 "register_operand" ""))]
252 [(set (match_dup 6) (match_dup 7))
254 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
258 operands[7] = gen_rtx (GET_CODE (operands[1]), DImode,
259 operands[2], operands[3]);
260 operands[8] = gen_lowpart (SImode, operands[6]);
264 [(set (match_operand:DI 0 "register_operand" "=r,r")
265 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
266 (match_operand:DI 2 "const48_operand" "I,I"))
267 (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))]
272 [(set_attr "type" "iaddlog")])
274 ;; These variants of the above insns can occur if the third operand
275 ;; is the frame pointer. This is a kludge, but there doesn't
276 ;; seem to be a way around it. Only recognize them while reloading.
279 [(set (match_operand:DI 0 "some_operand" "=&r")
280 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
281 (match_operand:DI 2 "some_operand" "r"))
282 (match_operand:DI 3 "some_operand" "rIOKL")))]
285 [(set_attr "type" "iaddlog")])
288 [(set (match_operand:DI 0 "register_operand" "")
289 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
290 (match_operand:DI 2 "register_operand" ""))
291 (match_operand:DI 3 "add_operand" "")))]
293 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
294 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
298 [(set (match_operand:SI 0 "some_operand" "=&r")
299 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
300 (match_operand:SI 2 "const48_operand" "I"))
301 (match_operand:SI 3 "some_operand" "r"))
302 (match_operand:SI 4 "some_operand" "rIOKL")))]
305 [(set_attr "type" "iaddlog")])
308 [(set (match_operand:SI 0 "register_operand" "r")
309 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
310 (match_operand:SI 2 "const48_operand" ""))
311 (match_operand:SI 3 "register_operand" ""))
312 (match_operand:SI 4 "add_operand" "rIOKL")))]
315 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
316 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
320 [(set (match_operand:DI 0 "some_operand" "=&r")
323 (mult:SI (match_operand:SI 1 "some_operand" "rJ")
324 (match_operand:SI 2 "const48_operand" "I"))
325 (match_operand:SI 3 "some_operand" "r"))
326 (match_operand:SI 4 "some_operand" "rIOKL"))))]
329 [(set_attr "type" "iaddlog")])
332 [(set (match_operand:DI 0 "register_operand" "")
335 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
336 (match_operand:SI 2 "const48_operand" ""))
337 (match_operand:SI 3 "register_operand" ""))
338 (match_operand:SI 4 "add_operand" ""))))]
341 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
342 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
344 { operands[5] = gen_lowpart (SImode, operands[0]);
348 [(set (match_operand:DI 0 "some_operand" "=&r")
349 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
350 (match_operand:DI 2 "const48_operand" "I"))
351 (match_operand:DI 3 "some_operand" "r"))
352 (match_operand:DI 4 "some_operand" "rIOKL")))]
355 [(set_attr "type" "iaddlog")])
358 [(set (match_operand:DI 0 "register_operand" "=")
359 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
360 (match_operand:DI 2 "const48_operand" ""))
361 (match_operand:DI 3 "register_operand" ""))
362 (match_operand:DI 4 "add_operand" "")))]
365 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
366 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
369 (define_insn "negsi2"
370 [(set (match_operand:SI 0 "register_operand" "=r")
371 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
374 [(set_attr "type" "iaddlog")])
377 [(set (match_operand:DI 0 "register_operand" "=r")
378 (sign_extend:DI (neg:SI
379 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
382 [(set_attr "type" "iaddlog")])
384 (define_insn "negdi2"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
389 [(set_attr "type" "iaddlog")])
391 (define_expand "subsi3"
392 [(set (match_operand:SI 0 "register_operand" "")
393 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
394 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
397 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
398 gen_rtx (MINUS, DImode,
399 gen_lowpart (DImode, operands[1]),
400 gen_lowpart (DImode, operands[2]))));
406 [(set (match_operand:SI 0 "register_operand" "=r")
407 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
408 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
411 [(set_attr "type" "iaddlog")])
414 [(set (match_operand:DI 0 "register_operand" "=r")
415 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
416 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
419 [(set_attr "type" "iaddlog")])
421 (define_insn "subdi3"
422 [(set (match_operand:DI 0 "register_operand" "=r")
423 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
424 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
427 [(set_attr "type" "iaddlog")])
430 [(set (match_operand:SI 0 "register_operand" "=r")
431 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
432 (match_operand:SI 2 "const48_operand" "I"))
433 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
436 [(set_attr "type" "iaddlog")])
439 [(set (match_operand:DI 0 "register_operand" "=r")
441 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
442 (match_operand:SI 2 "const48_operand" "I"))
443 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
446 [(set_attr "type" "iaddlog")])
449 [(set (match_operand:DI 0 "register_operand" "=r")
450 (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
451 (match_operand:DI 2 "const48_operand" "I"))
452 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
455 [(set_attr "type" "iaddlog")])
457 (define_insn "mulsi3"
458 [(set (match_operand:SI 0 "register_operand" "=r")
459 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
460 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
463 [(set_attr "type" "imull")])
466 [(set (match_operand:DI 0 "register_operand" "=r")
467 (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
468 (match_operand:SI 2 "reg_or_0_operand" "rJ"))))]
471 [(set_attr "type" "imull")])
473 (define_insn "muldi3"
474 [(set (match_operand:DI 0 "register_operand" "=r")
475 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
476 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
479 [(set_attr "type" "imulq")])
481 (define_insn "umuldi3_highpart"
482 [(set (match_operand:DI 0 "register_operand" "=r")
485 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
486 (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
490 [(set_attr "type" "imulq")])
493 [(set (match_operand:DI 0 "register_operand" "=r")
496 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
497 (match_operand:TI 2 "cint8_operand" "I"))
501 [(set_attr "type" "imulq")])
503 ;; The divide and remainder operations always take their inputs from
504 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
506 (define_expand "divsi3"
507 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
508 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
509 (parallel [(set (reg:SI 27)
512 (clobber (reg:DI 23))
513 (clobber (reg:DI 28))])
514 (set (match_operand:SI 0 "general_operand" "")
519 (define_expand "udivsi3"
520 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
521 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
522 (parallel [(set (reg:SI 27)
525 (clobber (reg:DI 23))
526 (clobber (reg:DI 28))])
527 (set (match_operand:SI 0 "general_operand" "")
532 (define_expand "modsi3"
533 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
534 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
535 (parallel [(set (reg:SI 27)
538 (clobber (reg:DI 23))
539 (clobber (reg:DI 28))])
540 (set (match_operand:SI 0 "general_operand" "")
545 (define_expand "umodsi3"
546 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
547 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
548 (parallel [(set (reg:SI 27)
551 (clobber (reg:DI 23))
552 (clobber (reg:DI 28))])
553 (set (match_operand:SI 0 "general_operand" "")
558 (define_expand "divdi3"
559 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
560 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
561 (parallel [(set (reg:DI 27)
564 (clobber (reg:DI 23))
565 (clobber (reg:DI 28))])
566 (set (match_operand:DI 0 "general_operand" "")
571 (define_expand "udivdi3"
572 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
573 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
574 (parallel [(set (reg:DI 27)
577 (clobber (reg:DI 23))
578 (clobber (reg:DI 28))])
579 (set (match_operand:DI 0 "general_operand" "")
584 (define_expand "moddi3"
585 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
586 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
587 (parallel [(set (reg:DI 27)
590 (clobber (reg:DI 23))
591 (clobber (reg:DI 28))])
592 (set (match_operand:DI 0 "general_operand" "")
597 (define_expand "umoddi3"
598 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
599 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
600 (parallel [(set (reg:DI 27)
603 (clobber (reg:DI 23))
604 (clobber (reg:DI 28))])
605 (set (match_operand:DI 0 "general_operand" "")
612 (match_operator:SI 1 "divmod_operator"
613 [(reg:SI 24) (reg:SI 25)]))
614 (clobber (reg:DI 23))
615 (clobber (reg:DI 28))]
618 [(set_attr "type" "isubr")])
622 (match_operator:DI 1 "divmod_operator"
623 [(reg:DI 24) (reg:DI 25)]))
624 (clobber (reg:DI 23))
625 (clobber (reg:DI 28))]
628 [(set_attr "type" "isubr")])
630 ;; Next are the basic logical operations. These only exist in DImode.
632 (define_insn "anddi3"
633 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
634 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
635 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
641 [(set_attr "type" "iaddlog,iaddlog,shiftcm")])
643 ;; There are times when we can split and AND into two AND insns. This occurs
644 ;; when we can first clear any bytes and then clear anything else. For
645 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
646 ;; Only to this when running on 64-bit host since the computations are
647 ;; too messy otherwise.
650 [(set (match_operand:DI 0 "register_operand" "")
651 (and:DI (match_operand:DI 1 "register_operand" "")
652 (match_operand:DI 2 "const_int_operand" "")))]
653 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
654 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
655 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
658 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
659 unsigned HOST_WIDE_INT mask2 = mask1;
662 /* For each byte that isn't all zeros, make it all ones. */
663 for (i = 0; i < 64; i += 8)
664 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
665 mask1 |= (HOST_WIDE_INT) 0xff << i;
667 /* Now turn on any bits we've just turned off. */
670 operands[3] = GEN_INT (mask1);
671 operands[4] = GEN_INT (mask2);
674 (define_insn "zero_extendqihi2"
675 [(set (match_operand:HI 0 "register_operand" "=r")
676 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
679 [(set_attr "type" "iaddlog")])
681 (define_insn "zero_extendqisi2"
682 [(set (match_operand:SI 0 "register_operand" "=r")
683 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
686 [(set_attr "type" "iaddlog")])
688 (define_insn "zero_extendqidi2"
689 [(set (match_operand:DI 0 "register_operand" "=r")
690 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
693 [(set_attr "type" "iaddlog")])
695 (define_insn "zero_extendhisi2"
696 [(set (match_operand:SI 0 "register_operand" "=r")
697 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
700 [(set_attr "type" "iaddlog")])
702 (define_insn "zero_extendhidi2"
703 [(set (match_operand:DI 0 "register_operand" "=r")
704 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
707 [(set_attr "type" "iaddlog")])
709 (define_insn "zero_extendsidi2"
710 [(set (match_operand:DI 0 "register_operand" "=r")
711 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
714 [(set_attr "type" "iaddlog")])
717 [(set (match_operand:DI 0 "register_operand" "=r")
718 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
719 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
722 [(set_attr "type" "iaddlog")])
724 (define_insn "iordi3"
725 [(set (match_operand:DI 0 "register_operand" "=r,r")
726 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
727 (match_operand:DI 2 "or_operand" "rI,N")))]
732 [(set_attr "type" "iaddlog")])
734 (define_insn "one_cmpldi2"
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
739 [(set_attr "type" "iaddlog")])
742 [(set (match_operand:DI 0 "register_operand" "=r")
743 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
744 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
747 [(set_attr "type" "iaddlog")])
749 (define_insn "xordi3"
750 [(set (match_operand:DI 0 "register_operand" "=r,r")
751 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
752 (match_operand:DI 2 "or_operand" "rI,N")))]
757 [(set_attr "type" "iaddlog")])
760 [(set (match_operand:DI 0 "register_operand" "=r")
761 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
762 (match_operand:DI 2 "register_operand" "rI"))))]
765 [(set_attr "type" "iaddlog")])
767 ;; Next come the shifts and the various extract and insert operations.
769 (define_insn "ashldi3"
770 [(set (match_operand:DI 0 "register_operand" "=r,r")
771 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
772 (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
776 switch (which_alternative)
779 if (operands[2] == const1_rtx)
780 return \"addq %r1,%r1,%0\";
782 return \"s%P2addq %r1,0,%0\";
784 return \"sll %r1,%2,%0\";
787 [(set_attr "type" "iaddlog,shiftcm")])
789 ;; ??? The following pattern is made by combine, but earlier phases
790 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
791 ;; with this in a better way at some point.
793 ;; [(set (match_operand:DI 0 "register_operand" "=r")
795 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
796 ;; (match_operand:DI 2 "const_int_operand" "P"))
798 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
801 ;; if (operands[2] == const1_rtx)
802 ;; return \"addl %r1,%r1,%0\";
804 ;; return \"s%P2addl %r1,0,%0\";
806 ;; [(set_attr "type" "iaddlog")])
808 (define_insn "lshrdi3"
809 [(set (match_operand:DI 0 "register_operand" "=r")
810 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
811 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
815 (define_insn "ashrdi3"
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
818 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
822 (define_expand "extendqihi2"
824 (ashift:DI (match_operand:QI 1 "register_operand" "")
826 (set (match_operand:HI 0 "register_operand" "")
827 (ashiftrt:DI (match_dup 2)
831 { operands[0] = gen_lowpart (DImode, operands[0]);
832 operands[1] = gen_lowpart (DImode, operands[1]);
833 operands[2] = gen_reg_rtx (DImode);
836 (define_expand "extendqisi2"
838 (ashift:DI (match_operand:QI 1 "register_operand" "")
840 (set (match_operand:SI 0 "register_operand" "")
841 (ashiftrt:DI (match_dup 2)
845 { operands[0] = gen_lowpart (DImode, operands[0]);
846 operands[1] = gen_lowpart (DImode, operands[1]);
847 operands[2] = gen_reg_rtx (DImode);
850 (define_expand "extendqidi2"
852 (ashift:DI (match_operand:QI 1 "register_operand" "")
854 (set (match_operand:DI 0 "register_operand" "")
855 (ashiftrt:DI (match_dup 2)
859 { operands[1] = gen_lowpart (DImode, operands[1]);
860 operands[2] = gen_reg_rtx (DImode);
863 (define_expand "extendhisi2"
865 (ashift:DI (match_operand:HI 1 "register_operand" "")
867 (set (match_operand:SI 0 "register_operand" "")
868 (ashiftrt:DI (match_dup 2)
872 { operands[0] = gen_lowpart (DImode, operands[0]);
873 operands[1] = gen_lowpart (DImode, operands[1]);
874 operands[2] = gen_reg_rtx (DImode);
877 (define_expand "extendhidi2"
879 (ashift:DI (match_operand:HI 1 "register_operand" "")
881 (set (match_operand:DI 0 "register_operand" "")
882 (ashiftrt:DI (match_dup 2)
886 { operands[1] = gen_lowpart (DImode, operands[1]);
887 operands[2] = gen_reg_rtx (DImode);
891 [(set (match_operand:DI 0 "register_operand" "=r")
892 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
893 (match_operand:DI 2 "mode_width_operand" "n")
894 (match_operand:DI 3 "mul8_operand" "I")))]
896 "ext%M2l %r1,%s3,%0")
899 [(set (match_operand:DI 0 "register_operand" "=r")
900 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
901 (match_operand:DI 2 "mode_width_operand" "n")
902 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
908 [(set (match_operand:DI 0 "register_operand" "=r")
910 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
914 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
922 [(set (match_operand:DI 0 "register_operand" "=r")
924 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
928 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
936 [(set (match_operand:DI 0 "register_operand" "=r")
938 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
942 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
949 ;; This converts an extXl into an extXh with an appropriate adjustment
950 ;; to the address calculation.
953 [(set (match_operand:DI 0 "register_operand" "")
954 (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
955 (match_operand:DI 2 "mode_width_operand" "")
956 (ashift:DI (match_operand:DI 3 "" "")
958 (match_operand:DI 4 "const_int_operand" "")))
959 (clobber (match_operand:DI 5 "register_operand" ""))]
960 "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
961 [(set (match_dup 5) (match_dup 6))
963 (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
964 (ashift:DI (plus:DI (match_dup 5)
970 operands[6] = plus_constant (operands[3],
971 INTVAL (operands[2]) / BITS_PER_UNIT);
972 operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
976 [(set (match_operand:DI 0 "register_operand" "=r")
977 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
978 (match_operand:DI 2 "mul8_operand" "I")))]
983 [(set (match_operand:DI 0 "register_operand" "=r")
984 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
985 (match_operand:DI 2 "mul8_operand" "I")))]
990 [(set (match_operand:DI 0 "register_operand" "=r")
991 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
992 (match_operand:DI 2 "mul8_operand" "I")))]
997 [(set (match_operand:DI 0 "register_operand" "=r")
998 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
999 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1005 [(set (match_operand:DI 0 "register_operand" "=r")
1006 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1007 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1013 [(set (match_operand:DI 0 "register_operand" "=r")
1014 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1015 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1020 ;; We do not include the insXh insns because they are complex to express
1021 ;; and it does not appear that we would ever want to generate them.
1024 [(set (match_operand:DI 0 "register_operand" "=r")
1025 (and:DI (not:DI (ashift:DI
1026 (match_operand:DI 2 "mode_mask_operand" "n")
1028 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1030 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1032 "msk%U2l %r1,%3,%0")
1034 ;; We do not include the mskXh insns because it does not appear we would ever
1037 ;; Floating-point operations. All the double-precision insns can extend
1038 ;; from single, so indicate that. The exception are the ones that simply
1039 ;; play with the sign bits; it's not clear what to do there.
1041 (define_insn "abssf2"
1042 [(set (match_operand:SF 0 "register_operand" "=f")
1043 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1046 [(set_attr "type" "fpop")])
1048 (define_insn "absdf2"
1049 [(set (match_operand:DF 0 "register_operand" "=f")
1050 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1053 [(set_attr "type" "fpop")])
1055 (define_insn "negsf2"
1056 [(set (match_operand:SF 0 "register_operand" "=f")
1057 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1060 [(set_attr "type" "fpop")])
1062 (define_insn "negdf2"
1063 [(set (match_operand:DF 0 "register_operand" "=f")
1064 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1067 [(set_attr "type" "fpop")])
1069 (define_insn "addsf3"
1070 [(set (match_operand:SF 0 "register_operand" "=f")
1071 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1072 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1075 [(set_attr "type" "fpop")])
1077 (define_insn "adddf3"
1078 [(set (match_operand:DF 0 "register_operand" "=f")
1079 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1080 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1083 [(set_attr "type" "fpop")])
1086 [(set (match_operand:DF 0 "register_operand" "=f")
1087 (plus:DF (float_extend:DF
1088 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1089 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1092 [(set_attr "type" "fpop")])
1095 [(set (match_operand:DF 0 "register_operand" "=f")
1096 (plus:DF (float_extend:DF
1097 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1099 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1102 [(set_attr "type" "fpop")])
1104 (define_insn "fix_truncdfdi2"
1105 [(set (match_operand:DI 0 "register_operand" "=f")
1106 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1109 [(set_attr "type" "fpop")])
1111 (define_insn "fix_truncsfdi2"
1112 [(set (match_operand:DI 0 "register_operand" "=f")
1113 (fix:DI (float_extend:DF
1114 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1117 [(set_attr "type" "fpop")])
1119 (define_insn "floatdisf2"
1120 [(set (match_operand:SF 0 "register_operand" "=f")
1121 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1124 [(set_attr "type" "fpop")])
1126 (define_insn "floatdidf2"
1127 [(set (match_operand:DF 0 "register_operand" "=f")
1128 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1131 [(set_attr "type" "fpop")])
1133 (define_insn "extendsfdf2"
1134 [(set (match_operand:DF 0 "register_operand" "=f,f")
1135 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
1140 [(set_attr "type" "fpop,ld")])
1142 (define_insn "truncdfsf2"
1143 [(set (match_operand:SF 0 "register_operand" "=f")
1144 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1147 [(set_attr "type" "fpop")])
1149 (define_insn "divsf3"
1150 [(set (match_operand:SF 0 "register_operand" "=f")
1151 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1152 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1155 [(set_attr "type" "fdivs")])
1157 (define_insn "divdf3"
1158 [(set (match_operand:DF 0 "register_operand" "=f")
1159 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1160 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1163 [(set_attr "type" "fdivt")])
1166 [(set (match_operand:DF 0 "register_operand" "=f")
1167 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1168 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1171 [(set_attr "type" "fdivt")])
1174 [(set (match_operand:DF 0 "register_operand" "=f")
1175 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1177 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1180 [(set_attr "type" "fdivt")])
1183 [(set (match_operand:DF 0 "register_operand" "=f")
1184 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1185 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1188 [(set_attr "type" "fdivt")])
1190 (define_insn "mulsf3"
1191 [(set (match_operand:SF 0 "register_operand" "=f")
1192 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1193 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1196 [(set_attr "type" "fpop")])
1198 (define_insn "muldf3"
1199 [(set (match_operand:DF 0 "register_operand" "=f")
1200 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1201 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1204 [(set_attr "type" "fpop")])
1207 [(set (match_operand:DF 0 "register_operand" "=f")
1208 (mult:DF (float_extend:DF
1209 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1210 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1213 [(set_attr "type" "fpop")])
1216 [(set (match_operand:DF 0 "register_operand" "=f")
1217 (mult:DF (float_extend:DF
1218 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1220 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1223 [(set_attr "type" "fpop")])
1225 (define_insn "subsf3"
1226 [(set (match_operand:SF 0 "register_operand" "=f")
1227 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1228 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1231 [(set_attr "type" "fpop")])
1233 (define_insn "subdf3"
1234 [(set (match_operand:DF 0 "register_operand" "=f")
1235 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1236 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1239 [(set_attr "type" "fpop")])
1242 [(set (match_operand:DF 0 "register_operand" "=f")
1243 (minus:DF (float_extend:DF
1244 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1245 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1248 [(set_attr "type" "fpop")])
1251 [(set (match_operand:DF 0 "register_operand" "=f")
1252 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1254 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1257 [(set_attr "type" "fpop")])
1260 [(set (match_operand:DF 0 "register_operand" "=f")
1261 (minus:DF (float_extend:DF
1262 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1264 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1267 [(set_attr "type" "fpop")])
1269 ;; Next are all the integer comparisons, and conditional moves and branches
1270 ;; and some of the related define_expand's and define_split's.
1273 [(set (match_operand:DI 0 "register_operand" "=r")
1274 (match_operator:DI 1 "alpha_comparison_operator"
1275 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1276 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
1279 [(set_attr "type" "icmp")])
1281 ;; There are three important special-case that don't fit the above pattern
1282 ;; but which we want to handle here.
1285 [(set (match_operand:DI 0 "register_operand" "=r")
1286 (ne:DI (match_operand:DI 1 "register_operand" "r")
1290 [(set_attr "type" "icmp")])
1293 [(set (match_operand:DI 0 "register_operand" "=r")
1294 (gt:DI (match_operand:DI 1 "register_operand" "r")
1298 [(set_attr "type" "icmp")])
1301 [(set (match_operand:DI 0 "register_operand" "=r")
1302 (ge:DI (match_operand:DI 1 "register_operand" "r")
1306 [(set_attr "type" "icmp")])
1308 ;; This pattern exists so conditional moves of SImode values are handled.
1309 ;; Comparisons are still done in DImode though.
1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1314 (match_operator 2 "signed_comparison_operator"
1315 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1316 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1317 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1318 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1319 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1327 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1329 (match_operator 2 "signed_comparison_operator"
1330 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1331 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1332 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1333 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1334 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1342 [(set (match_operand:DI 0 "register_operand" "=r,r")
1344 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1348 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1349 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1356 [(set (match_operand:DI 0 "register_operand" "=r,r")
1358 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1362 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1363 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1369 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
1370 ;; arms constant is a single insn, so it won't try to form it if combine
1371 ;; knows they are really two insns. This occurs in divides by powers
1375 [(set (match_operand:DI 0 "register_operand" "=r")
1377 (match_operator 2 "signed_comparison_operator"
1378 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
1380 (plus:DI (match_dup 0)
1381 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1383 (clobber (match_scratch:DI 4 "=&r"))]
1385 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0")
1388 [(set (match_operand:DI 0 "register_operand" "")
1390 (match_operator 2 "signed_comparison_operator"
1391 [(match_operand:DI 3 "reg_or_0_operand" "")
1393 (plus:DI (match_dup 0)
1394 (match_operand:DI 1 "reg_or_8bit_operand" ""))
1396 (clobber (match_operand:DI 4 "register_operand" ""))]
1398 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
1399 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
1402 (match_dup 4) (match_dup 0)))]
1407 [(set (match_operand:DI 0 "register_operand" "")
1409 (match_operator 1 "comparison_operator"
1410 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1412 (match_operand:DI 3 "const_int_operand" ""))
1414 (match_operand:DI 4 "reg_or_8bit_operand" "")
1415 (match_operand:DI 5 "reg_or_8bit_operand" "")))
1416 (clobber (match_operand:DI 6 "register_operand" ""))])]
1417 "INTVAL (operands[3]) != 0"
1419 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1421 (if_then_else:DI (match_op_dup 1
1422 [(zero_extract:DI (match_dup 6)
1430 ;; For ABS, we have two choices, depending on whether the input and output
1431 ;; registers are the same or not.
1432 (define_expand "absdi2"
1433 [(set (match_operand:DI 0 "register_operand" "")
1434 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1437 { if (rtx_equal_p (operands[0], operands[1]))
1438 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
1440 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
1445 (define_expand "absdi2_same"
1446 [(set (match_operand:DI 1 "register_operand" "")
1447 (neg:DI (match_operand:DI 0 "register_operand" "")))
1449 (if_then_else:DI (ge (match_dup 0) (const_int 0))
1455 (define_expand "absdi2_diff"
1456 [(set (match_operand:DI 0 "register_operand" "")
1457 (neg:DI (match_operand:DI 1 "register_operand" "")))
1459 (if_then_else:DI (lt (match_dup 1) (const_int 0))
1466 [(set (match_operand:DI 0 "register_operand" "")
1467 (abs:DI (match_dup 0)))
1468 (clobber (match_operand:DI 2 "register_operand" ""))]
1470 [(set (match_dup 1) (neg:DI (match_dup 0)))
1471 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
1472 (match_dup 0) (match_dup 1)))]
1476 [(set (match_operand:DI 0 "register_operand" "")
1477 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1478 "! rtx_equal_p (operands[0], operands[1])"
1479 [(set (match_dup 0) (neg:DI (match_dup 1)))
1480 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
1481 (match_dup 0) (match_dup 1)))]
1485 [(set (match_operand:DI 0 "register_operand" "")
1486 (neg:DI (abs:DI (match_dup 0))))
1487 (clobber (match_operand:DI 2 "register_operand" ""))]
1489 [(set (match_dup 1) (neg:DI (match_dup 0)))
1490 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
1491 (match_dup 0) (match_dup 1)))]
1495 [(set (match_operand:DI 0 "register_operand" "")
1496 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
1497 "! rtx_equal_p (operands[0], operands[1])"
1498 [(set (match_dup 0) (neg:DI (match_dup 1)))
1499 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
1500 (match_dup 0) (match_dup 1)))]
1503 (define_expand "smaxdi3"
1505 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
1506 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1507 (set (match_operand:DI 0 "register_operand" "")
1508 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1509 (match_dup 1) (match_dup 2)))]
1512 { operands[3] = gen_reg_rtx (DImode);
1516 [(set (match_operand:DI 0 "register_operand" "")
1517 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1518 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1519 (clobber (match_operand:DI 3 "register_operand" ""))]
1520 "operands[2] != const0_rtx"
1521 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
1522 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1523 (match_dup 1) (match_dup 2)))]
1527 [(set (match_operand:DI 0 "register_operand" "=r")
1528 (smax:DI (match_operand:DI 1 "register_operand" "0")
1533 (define_expand "smindi3"
1535 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
1536 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1537 (set (match_operand:DI 0 "register_operand" "")
1538 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1539 (match_dup 1) (match_dup 2)))]
1542 { operands[3] = gen_reg_rtx (DImode);
1546 [(set (match_operand:DI 0 "register_operand" "")
1547 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1548 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1549 (clobber (match_operand:DI 3 "register_operand" ""))]
1550 "operands[2] != const0_rtx"
1551 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
1552 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1553 (match_dup 1) (match_dup 2)))]
1557 [(set (match_operand:DI 0 "register_operand" "=r")
1558 (smin:DI (match_operand:DI 1 "register_operand" "0")
1563 (define_expand "umaxdi3"
1565 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1566 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1567 (set (match_operand:DI 0 "register_operand" "")
1568 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1569 (match_dup 1) (match_dup 2)))]
1572 { operands[3] = gen_reg_rtx (DImode);
1576 [(set (match_operand:DI 0 "register_operand" "")
1577 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1578 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1579 (clobber (match_operand:DI 3 "register_operand" ""))]
1580 "operands[2] != const0_rtx"
1581 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
1582 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1583 (match_dup 1) (match_dup 2)))]
1586 (define_expand "umindi3"
1588 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1589 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1590 (set (match_operand:DI 0 "register_operand" "")
1591 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1592 (match_dup 1) (match_dup 2)))]
1595 { operands[3] = gen_reg_rtx (DImode);
1599 [(set (match_operand:DI 0 "register_operand" "")
1600 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1601 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1602 (clobber (match_operand:DI 3 "register_operand" ""))]
1603 "operands[2] != const0_rtx"
1604 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
1605 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1606 (match_dup 1) (match_dup 2)))]
1612 (match_operator 1 "signed_comparison_operator"
1613 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1615 (label_ref (match_operand 0 "" ""))
1619 [(set_attr "type" "ibr")])
1624 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1628 (label_ref (match_operand 0 "" ""))
1632 [(set_attr "type" "ibr")])
1637 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1641 (label_ref (match_operand 0 "" ""))
1645 [(set_attr "type" "ibr")])
1651 (match_operator 1 "comparison_operator"
1652 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1654 (match_operand:DI 3 "const_int_operand" ""))
1656 (label_ref (match_operand 0 "" ""))
1658 (clobber (match_operand:DI 4 "register_operand" ""))])]
1659 "INTVAL (operands[3]) != 0"
1661 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1663 (if_then_else (match_op_dup 1
1664 [(zero_extract:DI (match_dup 4)
1668 (label_ref (match_dup 0))
1672 ;; The following are the corresponding floating-point insns. Recall
1673 ;; we need to have variants that expand the arguments from SF mode
1677 [(set (match_operand:DF 0 "register_operand" "=f")
1678 (match_operator:DF 1 "alpha_comparison_operator"
1679 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1680 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1682 "cmpt%C1 %R2,%R3,%0"
1683 [(set_attr "type" "fpop")])
1686 [(set (match_operand:DF 0 "register_operand" "=f")
1687 (match_operator:DF 1 "alpha_comparison_operator"
1689 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1690 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1692 "cmpt%C1 %R2,%R3,%0"
1693 [(set_attr "type" "fpop")])
1696 [(set (match_operand:DF 0 "register_operand" "=f")
1697 (match_operator:DF 1 "alpha_comparison_operator"
1698 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1700 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1702 "cmpt%C1 %R2,%R3,%0"
1703 [(set_attr "type" "fpop")])
1706 [(set (match_operand:DF 0 "register_operand" "=f")
1707 (match_operator:DF 1 "alpha_comparison_operator"
1709 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1711 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1713 "cmpt%C1 %R2,%R3,%0"
1714 [(set_attr "type" "fpop")])
1717 [(set (match_operand:DF 0 "register_operand" "=f,f")
1719 (match_operator 3 "signed_comparison_operator"
1720 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1721 (match_operand:DF 2 "fp0_operand" "G,G")])
1722 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1723 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1727 fcmov%D3 %R4,%R5,%0"
1728 [(set_attr "type" "fpop")])
1731 [(set (match_operand:SF 0 "register_operand" "=f,f")
1733 (match_operator 3 "signed_comparison_operator"
1734 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1735 (match_operand:DF 2 "fp0_operand" "G,G")])
1736 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1737 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1741 fcmov%D3 %R4,%R5,%0"
1742 [(set_attr "type" "fpop")])
1745 [(set (match_operand:DF 0 "register_operand" "=f,f")
1747 (match_operator 3 "signed_comparison_operator"
1748 [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG")
1749 (match_operand:DF 2 "fp0_operand" "G,G")])
1750 (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0"))
1751 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1755 fcmov%D3 %R4,%R5,%0"
1756 [(set_attr "type" "fpop")])
1759 [(set (match_operand:DF 0 "register_operand" "=f,f")
1761 (match_operator 3 "signed_comparison_operator"
1763 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1764 (match_operand:DF 2 "fp0_operand" "G,G")])
1765 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1766 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1770 fcmov%D3 %R4,%R5,%0"
1771 [(set_attr "type" "fpop")])
1774 [(set (match_operand:SF 0 "register_operand" "=f,f")
1776 (match_operator 3 "signed_comparison_operator"
1778 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1779 (match_operand:DF 2 "fp0_operand" "G,G")])
1780 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1781 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1785 fcmov%D3 %R4,%R5,%0"
1786 [(set_attr "type" "fpop")])
1789 [(set (match_operand:DF 0 "register_operand" "=f,f")
1791 (match_operator 3 "signed_comparison_operator"
1793 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1794 (match_operand:DF 2 "fp0_operand" "G,G")])
1795 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
1796 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1800 fcmov%D3 %R4,%R5,%0"
1801 [(set_attr "type" "fpop")])
1803 (define_expand "maxdf3"
1805 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1806 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1807 (set (match_operand:DF 0 "register_operand" "")
1808 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
1809 (match_dup 1) (match_dup 2)))]
1812 { operands[3] = gen_reg_rtx (DFmode);
1813 operands[4] = CONST0_RTX (DFmode);
1816 (define_expand "mindf3"
1818 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1819 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1820 (set (match_operand:DF 0 "register_operand" "")
1821 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
1822 (match_dup 1) (match_dup 2)))]
1825 { operands[3] = gen_reg_rtx (DFmode);
1826 operands[4] = CONST0_RTX (DFmode);
1829 (define_expand "maxsf3"
1831 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1832 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1833 (set (match_operand:SF 0 "register_operand" "")
1834 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
1835 (match_dup 1) (match_dup 2)))]
1838 { operands[3] = gen_reg_rtx (DFmode);
1839 operands[4] = CONST0_RTX (DFmode);
1842 (define_expand "minsf3"
1844 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1845 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1846 (set (match_operand:SF 0 "register_operand" "")
1847 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
1848 (match_dup 1) (match_dup 2)))]
1851 { operands[3] = gen_reg_rtx (DFmode);
1852 operands[4] = CONST0_RTX (DFmode);
1858 (match_operator 1 "signed_comparison_operator"
1859 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1860 (match_operand:DF 3 "fp0_operand" "G")])
1861 (label_ref (match_operand 0 "" ""))
1865 [(set_attr "type" "fbr")])
1870 (match_operator 1 "signed_comparison_operator"
1872 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1873 (match_operand:DF 3 "fp0_operand" "G")])
1874 (label_ref (match_operand 0 "" ""))
1878 [(set_attr "type" "fbr")])
1880 ;; These are the main define_expand's used to make conditional branches
1883 (define_expand "cmpdf"
1884 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
1885 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
1889 alpha_compare_op0 = operands[0];
1890 alpha_compare_op1 = operands[1];
1891 alpha_compare_fp_p = 1;
1895 (define_expand "cmpdi"
1896 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
1897 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
1901 alpha_compare_op0 = operands[0];
1902 alpha_compare_op1 = operands[1];
1903 alpha_compare_fp_p = 0;
1907 (define_expand "beq"
1908 [(set (match_dup 1) (match_dup 2))
1910 (if_then_else (match_dup 3)
1911 (label_ref (match_operand 0 "" ""))
1916 enum machine_mode mode;
1917 enum rtx_code compare_code, branch_code;
1919 if (alpha_compare_fp_p)
1920 mode = DFmode, compare_code = EQ, branch_code = NE;
1923 mode = DImode, compare_code = MINUS, branch_code = EQ;
1924 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1926 compare_code = PLUS;
1927 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1931 operands[1] = gen_reg_rtx (mode);
1932 operands[2] = gen_rtx (compare_code, mode,
1933 alpha_compare_op0, alpha_compare_op1);
1934 operands[3] = gen_rtx (branch_code, VOIDmode,
1935 operands[1], CONST0_RTX (mode));
1938 (define_expand "bne"
1939 [(set (match_dup 1) (match_dup 2))
1941 (if_then_else (match_dup 3)
1942 (label_ref (match_operand 0 "" ""))
1947 enum machine_mode mode;
1948 enum rtx_code compare_code, branch_code;
1950 if (alpha_compare_fp_p)
1951 mode = DFmode, compare_code = EQ, branch_code = EQ;
1954 mode = DImode, compare_code = MINUS, branch_code = NE;
1955 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1957 compare_code = PLUS;
1958 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1962 operands[1] = gen_reg_rtx (mode);
1963 operands[2] = gen_rtx (compare_code, mode,
1964 alpha_compare_op0, alpha_compare_op1);
1965 operands[3] = gen_rtx (branch_code, VOIDmode,
1966 operands[1], CONST0_RTX (mode));
1969 (define_expand "blt"
1970 [(set (match_dup 1) (match_dup 2))
1972 (if_then_else (match_dup 3)
1973 (label_ref (match_operand 0 "" ""))
1978 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1979 operands[1] = gen_reg_rtx (mode);
1980 operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
1981 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1984 (define_expand "ble"
1985 [(set (match_dup 1) (match_dup 2))
1987 (if_then_else (match_dup 3)
1988 (label_ref (match_operand 0 "" ""))
1993 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1994 operands[1] = gen_reg_rtx (mode);
1995 operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
1996 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1999 (define_expand "bgt"
2000 [(set (match_dup 1) (match_dup 2))
2002 (if_then_else (match_dup 3)
2003 (label_ref (match_operand 0 "" ""))
2008 if (alpha_compare_fp_p)
2010 operands[1] = gen_reg_rtx (DFmode);
2011 operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
2012 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2016 operands[1] = gen_reg_rtx (DImode);
2017 operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2018 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2022 (define_expand "bge"
2023 [(set (match_dup 1) (match_dup 2))
2025 (if_then_else (match_dup 3)
2026 (label_ref (match_operand 0 "" ""))
2031 if (alpha_compare_fp_p)
2033 operands[1] = gen_reg_rtx (DFmode);
2034 operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
2035 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2039 operands[1] = gen_reg_rtx (DImode);
2040 operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2041 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2045 (define_expand "bltu"
2046 [(set (match_dup 1) (match_dup 2))
2048 (if_then_else (match_dup 3)
2049 (label_ref (match_operand 0 "" ""))
2054 operands[1] = gen_reg_rtx (DImode);
2055 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2056 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2059 (define_expand "bleu"
2060 [(set (match_dup 1) (match_dup 2))
2062 (if_then_else (match_dup 3)
2063 (label_ref (match_operand 0 "" ""))
2068 operands[1] = gen_reg_rtx (DImode);
2069 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2070 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2073 (define_expand "bgtu"
2074 [(set (match_dup 1) (match_dup 2))
2076 (if_then_else (match_dup 3)
2077 (label_ref (match_operand 0 "" ""))
2082 operands[1] = gen_reg_rtx (DImode);
2083 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2084 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2087 (define_expand "bgeu"
2088 [(set (match_dup 1) (match_dup 2))
2090 (if_then_else (match_dup 3)
2091 (label_ref (match_operand 0 "" ""))
2096 operands[1] = gen_reg_rtx (DImode);
2097 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2098 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2101 (define_expand "seq"
2102 [(set (match_operand:DI 0 "register_operand" "")
2107 if (alpha_compare_fp_p)
2110 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2113 (define_expand "sne"
2114 [(set (match_operand:DI 0 "register_operand" "")
2116 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
2120 if (alpha_compare_fp_p)
2123 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2126 (define_expand "slt"
2127 [(set (match_operand:DI 0 "register_operand" "")
2132 if (alpha_compare_fp_p)
2135 operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2138 (define_expand "sle"
2139 [(set (match_operand:DI 0 "register_operand" "")
2144 if (alpha_compare_fp_p)
2147 operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2150 (define_expand "sgt"
2151 [(set (match_operand:DI 0 "register_operand" "")
2156 if (alpha_compare_fp_p)
2159 operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
2163 (define_expand "sge"
2164 [(set (match_operand:DI 0 "register_operand" "")
2169 if (alpha_compare_fp_p)
2172 operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
2176 (define_expand "sltu"
2177 [(set (match_operand:DI 0 "register_operand" "")
2182 if (alpha_compare_fp_p)
2185 operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2188 (define_expand "sleu"
2189 [(set (match_operand:DI 0 "register_operand" "")
2194 if (alpha_compare_fp_p)
2197 operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2200 (define_expand "sgtu"
2201 [(set (match_operand:DI 0 "register_operand" "")
2206 if (alpha_compare_fp_p)
2209 operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
2213 (define_expand "sgeu"
2214 [(set (match_operand:DI 0 "register_operand" "")
2219 if (alpha_compare_fp_p)
2222 operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
2226 ;; These are the main define_expand's used to make conditional moves.
2228 (define_expand "movsicc"
2229 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2230 (set (match_operand:SI 0 "register_operand" "")
2231 (if_then_else:DI (match_dup 5)
2232 (match_operand:SI 2 "reg_or_8bit_operand" "")
2233 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
2238 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2240 if (alpha_compare_fp_p)
2244 case EQ: case LE: case LT:
2245 op0 = alpha_compare_op0;
2246 op1 = alpha_compare_op1;
2250 op0 = alpha_compare_op0;
2251 op1 = alpha_compare_op1;
2255 op0 = force_reg (DImode, alpha_compare_op1);
2256 op1 = alpha_compare_op0;
2260 op0 = force_reg (DImode, alpha_compare_op1);
2261 op1 = alpha_compare_op0;
2266 operands[1] = gen_rtx (code, DImode, op0, op1);
2267 operands[4] = gen_reg_rtx (DImode);
2268 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
2271 (define_expand "movdicc"
2272 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2273 (set (match_operand:DI 0 "register_operand" "")
2274 (if_then_else:DI (match_dup 5)
2275 (match_operand:DI 2 "reg_or_8bit_operand" "")
2276 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
2281 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2283 if (alpha_compare_fp_p)
2287 case EQ: case LE: case LT:
2288 op0 = alpha_compare_op0;
2289 op1 = alpha_compare_op1;
2293 op0 = alpha_compare_op0;
2294 op1 = alpha_compare_op1;
2298 op0 = force_reg (DImode, alpha_compare_op1);
2299 op1 = alpha_compare_op0;
2303 op0 = force_reg (DImode, alpha_compare_op1);
2304 op1 = alpha_compare_op0;
2309 operands[1] = gen_rtx (code, DImode, op0, op1);
2310 operands[4] = gen_reg_rtx (DImode);
2311 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
2314 (define_expand "movsfcc"
2315 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2316 (set (match_operand:SF 0 "register_operand" "")
2317 (if_then_else:SF (match_dup 5)
2318 (match_operand:SF 2 "reg_or_fp0_operand" "")
2319 (match_operand:SF 3 "reg_or_fp0_operand" "")))]
2324 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2326 if (!alpha_compare_fp_p)
2330 case EQ: case LE: case LT:
2331 op0 = alpha_compare_op0;
2332 op1 = alpha_compare_op1;
2335 /* There isn't a cmptne insn. */
2337 op0 = alpha_compare_op0;
2338 op1 = alpha_compare_op1;
2342 op0 = force_reg (DFmode, alpha_compare_op1);
2343 op1 = alpha_compare_op0;
2347 op0 = force_reg (DFmode, alpha_compare_op1);
2348 op1 = alpha_compare_op0;
2353 operands[1] = gen_rtx (code, DFmode, op0, op1);
2354 operands[4] = gen_reg_rtx (DFmode);
2355 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
2358 (define_expand "movdfcc"
2359 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2360 (set (match_operand:DF 0 "register_operand" "")
2361 (if_then_else:DF (match_dup 5)
2362 (match_operand:DF 2 "reg_or_fp0_operand" "")
2363 (match_operand:DF 3 "reg_or_fp0_operand" "")))]
2368 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2370 if (!alpha_compare_fp_p)
2374 case EQ: case LE: case LT:
2375 op0 = alpha_compare_op0;
2376 op1 = alpha_compare_op1;
2379 /* There isn't a cmptne insn. */
2381 op0 = alpha_compare_op0;
2382 op1 = alpha_compare_op1;
2386 op0 = force_reg (DFmode, alpha_compare_op1);
2387 op1 = alpha_compare_op0;
2391 op0 = force_reg (DFmode, alpha_compare_op1);
2392 op1 = alpha_compare_op0;
2397 operands[1] = gen_rtx (code, DFmode, op0, op1);
2398 operands[4] = gen_reg_rtx (DFmode);
2399 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
2402 ;; These define_split definitions are used in cases when comparisons have
2403 ;; not be stated in the correct way and we need to reverse the second
2404 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
2405 ;; comparison that tests the result being reversed. We have one define_split
2406 ;; for each use of a comparison. They do not match valid insns and need
2407 ;; not generate valid insns.
2409 ;; We can also handle equality comparisons (and inequality comparisons in
2410 ;; cases where the resulting add cannot overflow) by doing an add followed by
2411 ;; a comparison with zero. This is faster since the addition takes one
2412 ;; less cycle than a compare when feeding into a conditional move.
2413 ;; For this case, we also have an SImode pattern since we can merge the add
2414 ;; and sign extend and the order doesn't matter.
2416 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2417 ;; operation could have been generated.
2420 [(set (match_operand:DI 0 "register_operand" "")
2422 (match_operator 1 "comparison_operator"
2423 [(match_operand:DI 2 "reg_or_0_operand" "")
2424 (match_operand:DI 3 "reg_or_cint_operand" "")])
2425 (match_operand:DI 4 "reg_or_cint_operand" "")
2426 (match_operand:DI 5 "reg_or_cint_operand" "")))
2427 (clobber (match_operand:DI 6 "register_operand" ""))]
2428 "operands[3] != const0_rtx"
2429 [(set (match_dup 6) (match_dup 7))
2431 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2433 { enum rtx_code code = GET_CODE (operands[1]);
2434 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2436 /* If we are comparing for equality with a constant and that constant
2437 appears in the arm when the register equals the constant, use the
2438 register since that is more likely to match (and to produce better code
2441 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
2442 && rtx_equal_p (operands[4], operands[3]))
2443 operands[4] = operands[2];
2445 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
2446 && rtx_equal_p (operands[5], operands[3]))
2447 operands[5] = operands[2];
2449 if (code == NE || code == EQ
2450 || (extended_count (operands[2], DImode, unsignedp) >= 1
2451 && extended_count (operands[3], DImode, unsignedp) >= 1))
2453 if (GET_CODE (operands[3]) == CONST_INT)
2454 operands[7] = gen_rtx (PLUS, DImode, operands[2],
2455 GEN_INT (- INTVAL (operands[3])));
2457 operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2459 operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
2462 else if (code == EQ || code == LE || code == LT
2463 || code == LEU || code == LTU)
2465 operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
2466 operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
2470 operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
2472 operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
2477 [(set (match_operand:DI 0 "register_operand" "")
2479 (match_operator 1 "comparison_operator"
2480 [(match_operand:SI 2 "reg_or_0_operand" "")
2481 (match_operand:SI 3 "reg_or_cint_operand" "")])
2482 (match_operand:DI 4 "reg_or_8bit_operand" "")
2483 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2484 (clobber (match_operand:DI 6 "register_operand" ""))]
2485 "operands[3] != const0_rtx
2486 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2487 [(set (match_dup 6) (match_dup 7))
2489 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2491 { enum rtx_code code = GET_CODE (operands[1]);
2492 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2495 if ((code != NE && code != EQ
2496 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
2497 && extended_count (operands[3], DImode, unsignedp) >= 1)))
2500 if (GET_CODE (operands[3]) == CONST_INT)
2501 tem = gen_rtx (PLUS, SImode, operands[2],
2502 GEN_INT (- INTVAL (operands[3])));
2504 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2506 operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem);
2507 operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
2514 (match_operator 1 "comparison_operator"
2515 [(match_operand:DI 2 "reg_or_0_operand" "")
2516 (match_operand:DI 3 "reg_or_cint_operand" "")])
2517 (label_ref (match_operand 0 "" ""))
2519 (clobber (match_operand:DI 4 "register_operand" ""))]
2520 "operands[3] != const0_rtx"
2521 [(set (match_dup 4) (match_dup 5))
2522 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2524 { enum rtx_code code = GET_CODE (operands[1]);
2525 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2527 if (code == NE || code == EQ
2528 || (extended_count (operands[2], DImode, unsignedp) >= 1
2529 && extended_count (operands[3], DImode, unsignedp) >= 1))
2531 if (GET_CODE (operands[3]) == CONST_INT)
2532 operands[5] = gen_rtx (PLUS, DImode, operands[2],
2533 GEN_INT (- INTVAL (operands[3])));
2535 operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2537 operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
2540 else if (code == EQ || code == LE || code == LT
2541 || code == LEU || code == LTU)
2543 operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
2544 operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
2548 operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
2550 operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
2557 (match_operator 1 "comparison_operator"
2558 [(match_operand:SI 2 "reg_or_0_operand" "")
2559 (match_operand:SI 3 "const_int_operand" "")])
2560 (label_ref (match_operand 0 "" ""))
2562 (clobber (match_operand:DI 4 "register_operand" ""))]
2563 "operands[3] != const0_rtx
2564 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2565 [(set (match_dup 4) (match_dup 5))
2566 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2570 if (GET_CODE (operands[3]) == CONST_INT)
2571 tem = gen_rtx (PLUS, SImode, operands[2],
2572 GEN_INT (- INTVAL (operands[3])));
2574 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2576 operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem);
2577 operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
2578 operands[4], const0_rtx);
2581 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
2582 ;; This eliminates one, and sometimes two, insns when the AND can be done
2585 [(set (match_operand:DI 0 "register_operand" "")
2586 (match_operator 1 "comparison_operator"
2587 [(match_operand:DI 2 "register_operand" "")
2588 (match_operand:DI 3 "const_int_operand" "")]))
2589 (clobber (match_operand:DI 4 "register_operand" ""))]
2590 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
2591 && (GET_CODE (operands[1]) == GTU
2592 || GET_CODE (operands[1]) == LEU
2593 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
2594 && extended_count (operands[2], DImode, 1) > 0))"
2595 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
2596 (set (match_dup 0) (match_dup 6))]
2599 operands[5] = GEN_INT (~ INTVAL (operands[3]));
2600 operands[6] = gen_rtx (((GET_CODE (operands[1]) == GTU
2601 || GET_CODE (operands[1]) == GT)
2603 DImode, operands[4], const0_rtx);
2606 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
2607 ;; work differently, so we have different patterns for each.
2609 (define_expand "call"
2610 [(use (match_operand:DI 0 "" ""))
2611 (use (match_operand 1 "" ""))]
2615 emit_call_insn (gen_call_nt (operands[0], operands[1]));
2617 emit_call_insn (gen_call_osf (operands[0], operands[1]));
2622 (define_expand "call_osf"
2623 [(parallel [(call (mem:DI (match_operand 0 "" ""))
2624 (match_operand 1 "" ""))
2625 (clobber (reg:DI 27))
2626 (clobber (reg:DI 26))])]
2629 { if (GET_CODE (operands[0]) != MEM)
2632 operands[0] = XEXP (operands[0], 0);
2634 if (GET_CODE (operands[0]) != SYMBOL_REF
2635 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
2637 rtx tem = gen_rtx (REG, DImode, 27);
2638 emit_move_insn (tem, operands[0]);
2643 (define_expand "call_nt"
2644 [(parallel [(call (mem:DI (match_operand:DI 0 "" ""))
2645 (match_operand 1 "" ""))
2646 (clobber (reg:DI 26))])]
2649 { if (GET_CODE (operands[0]) != MEM)
2651 operands[0] = XEXP (operands[0], 0);
2653 if (GET_CODE (operands[0]) != SYMBOL_REF)
2654 operands[0] = force_reg (Pmode, operands[0]);
2657 (define_expand "call_value"
2658 [(use (match_operand 0 "" ""))
2659 (use (match_operand:DI 1 "" ""))
2660 (use (match_operand 2 "" ""))]
2664 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
2666 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
2671 (define_expand "call_value_osf"
2672 [(parallel [(set (match_operand 0 "" "")
2673 (call (mem:DI (match_operand 1 "" ""))
2674 (match_operand 2 "" "")))
2675 (clobber (reg:DI 27))
2676 (clobber (reg:DI 26))])]
2679 { if (GET_CODE (operands[1]) != MEM)
2682 operands[1] = XEXP (operands[1], 0);
2684 if (GET_CODE (operands[1]) != SYMBOL_REF
2685 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
2687 rtx tem = gen_rtx (REG, DImode, 27);
2688 emit_move_insn (tem, operands[1]);
2693 (define_expand "call_value_nt"
2694 [(parallel [(set (match_operand 0 "" "")
2695 (call (mem:DI (match_operand:DI 1 "" ""))
2696 (match_operand 2 "" "")))
2697 (clobber (reg:DI 26))])]
2700 { if (GET_CODE (operands[1]) != MEM)
2703 operands[1] = XEXP (operands[1], 0);
2704 if (GET_CODE (operands[1]) != SYMBOL_REF)
2705 operands[1] = force_reg (Pmode, operands[1]);
2709 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
2710 (match_operand 1 "" ""))
2711 (clobber (reg:DI 27))
2712 (clobber (reg:DI 26))]
2715 jsr $26,($27),0\;ldgp $29,0($26)
2717 jsr $26,%0\;ldgp $29,0($26)"
2718 [(set_attr "type" "jsr,jsr,ibr")])
2721 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
2722 (match_operand 1 "" ""))
2723 (clobber (reg:DI 26))]
2728 [(set_attr "type" "jsr")])
2731 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
2732 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
2733 (match_operand 2 "" "")))
2734 (clobber (reg:DI 27))
2735 (clobber (reg:DI 26))]
2738 jsr $26,($27),0\;ldgp $29,0($26)
2740 jsr $26,%1\;ldgp $29,0($26)"
2741 [(set_attr "type" "jsr,jsr,ibr")])
2744 [(set (match_operand 0 "register_operand" "=rf,rf")
2745 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
2746 (match_operand 2 "" "")))
2747 (clobber (reg:DI 26))]
2752 [(set_attr "type" "jsr")])
2754 ;; Call subroutine returning any type.
2756 (define_expand "untyped_call"
2757 [(parallel [(call (match_operand 0 "" "")
2759 (match_operand 1 "" "")
2760 (match_operand 2 "" "")])]
2766 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2768 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2770 rtx set = XVECEXP (operands[2], 0, i);
2771 emit_move_insn (SET_DEST (set), SET_SRC (set));
2774 /* The optimizer does not know that the call sets the function value
2775 registers we stored in the result block. We avoid problems by
2776 claiming that all hard registers are used and clobbered at this
2778 emit_insn (gen_blockage ());
2783 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2784 ;; all of memory. This blocks insns from being moved across this point.
2786 (define_insn "blockage"
2787 [(unspec_volatile [(const_int 0)] 1)]
2793 (label_ref (match_operand 0 "" "")))]
2796 [(set_attr "type" "ibr")])
2798 (define_insn "return"
2802 [(set_attr "type" "ibr")])
2804 (define_insn "indirect_jump"
2805 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
2808 [(set_attr "type" "ibr")])
2814 [(set_attr "type" "iaddlog")])
2816 (define_expand "tablejump"
2817 [(use (match_operand:SI 0 "register_operand" ""))
2818 (use (match_operand:SI 1 "" ""))]
2823 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
2825 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
2830 (define_expand "tablejump_osf"
2832 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2833 (parallel [(set (pc)
2834 (plus:DI (match_dup 3)
2835 (label_ref:DI (match_operand 1 "" ""))))
2836 (clobber (match_scratch:DI 2 "=r"))])]
2839 { operands[3] = gen_reg_rtx (DImode); }")
2841 (define_expand "tablejump_nt"
2843 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2844 (parallel [(set (pc)
2846 (use (label_ref (match_operand 1 "" "")))])]
2849 { operands[3] = gen_reg_rtx (DImode); }")
2853 (plus:DI (match_operand:DI 0 "register_operand" "r")
2854 (label_ref:DI (match_operand 1 "" ""))))
2855 (clobber (match_scratch:DI 2 "=r"))]
2856 "! WINDOWS_NT && next_active_insn (insn) != 0
2857 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
2858 && PREV_INSN (next_active_insn (insn)) == operands[1]"
2860 { rtx best_label = 0;
2861 rtx jump_table_insn = next_active_insn (operands[1]);
2863 if (GET_CODE (jump_table_insn) == JUMP_INSN
2864 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
2866 rtx jump_table = PATTERN (jump_table_insn);
2867 int n_labels = XVECLEN (jump_table, 1);
2868 int best_count = -1;
2871 for (i = 0; i < n_labels; i++)
2875 for (j = i + 1; j < n_labels; j++)
2876 if (XEXP (XVECEXP (jump_table, 1, i), 0)
2877 == XEXP (XVECEXP (jump_table, 1, j), 0))
2880 if (count > best_count)
2881 best_count = count, best_label = XVECEXP (jump_table, 1, i);
2887 operands[3] = best_label;
2888 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
2891 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
2893 [(set_attr "type" "ibr")])
2897 (match_operand:DI 0 "register_operand" "r"))
2898 (use (label_ref (match_operand 1 "" "")))]
2899 "WINDOWS_NT && next_active_insn (insn) != 0
2900 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
2901 && PREV_INSN (next_active_insn (insn)) == operands[1]"
2903 { rtx best_label = 0;
2904 rtx jump_table_insn = next_active_insn (operands[1]);
2906 if (GET_CODE (jump_table_insn) == JUMP_INSN
2907 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
2909 rtx jump_table = PATTERN (jump_table_insn);
2910 int n_labels = XVECLEN (jump_table, 1);
2911 int best_count = -1;
2914 for (i = 0; i < n_labels; i++)
2918 for (j = i + 1; j < n_labels; j++)
2919 if (XEXP (XVECEXP (jump_table, 1, i), 0)
2920 == XEXP (XVECEXP (jump_table, 1, j), 0))
2923 if (count > best_count)
2924 best_count = count, best_label = XVECEXP (jump_table, 1, i);
2930 operands[2] = best_label;
2931 return \"jmp $31,(%0),%2\";
2934 return \"jmp $31,(%0),0\";
2936 [(set_attr "type" "ibr")])
2938 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
2939 ;; want to have to include pal.h in our .s file.
2941 [(unspec_volatile [(const_int 0)] 0)]
2945 ;; Finally, we have the basic data motion insns. The byte and word insns
2946 ;; are done via define_expand. Start with the floating-point insns, since
2947 ;; they are simpler.
2950 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2951 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2952 "register_operand (operands[0], SFmode)
2953 || reg_or_fp0_operand (operands[1], SFmode)"
2962 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2965 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2966 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2967 "register_operand (operands[0], DFmode)
2968 || reg_or_fp0_operand (operands[1], DFmode)"
2977 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2979 (define_expand "movsf"
2980 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2981 (match_operand:SF 1 "general_operand" ""))]
2985 if (GET_CODE (operands[0]) == MEM
2986 && ! reg_or_fp0_operand (operands[1], SFmode))
2987 operands[1] = force_reg (SFmode, operands[1]);
2990 (define_expand "movdf"
2991 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2992 (match_operand:DF 1 "general_operand" ""))]
2996 if (GET_CODE (operands[0]) == MEM
2997 && ! reg_or_fp0_operand (operands[1], DFmode))
2998 operands[1] = force_reg (DFmode, operands[1]);
3002 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
3003 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
3004 "! WINDOWS_NT && (register_operand (operands[0], SImode)
3005 || reg_or_0_operand (operands[1], SImode))"
3018 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld,st")])
3021 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
3022 (match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
3023 "WINDOWS_NT && (register_operand (operands[0], SImode)
3024 || reg_or_0_operand (operands[1], SImode))"
3038 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
3041 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3042 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
3043 "register_operand (operands[0], HImode)
3044 || register_operand (operands[1], HImode)"
3052 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
3055 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3056 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
3057 "register_operand (operands[0], QImode)
3058 || register_operand (operands[1], QImode)"
3066 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
3068 ;; We do two major things here: handle mem->mem and construct long
3071 (define_expand "movsi"
3072 [(set (match_operand:SI 0 "general_operand" "")
3073 (match_operand:SI 1 "general_operand" ""))]
3077 if (GET_CODE (operands[0]) == MEM
3078 && ! reg_or_0_operand (operands[1], SImode))
3079 operands[1] = force_reg (SImode, operands[1]);
3081 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
3083 else if (GET_CODE (operands[1]) == CONST_INT)
3086 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
3087 if (rtx_equal_p (operands[0], operands[1]))
3092 ;; Split a load of a large constant into the appropriate two-insn
3096 [(set (match_operand:SI 0 "register_operand" "")
3097 (match_operand:SI 1 "const_int_operand" ""))]
3098 "! add_operand (operands[1], SImode)"
3099 [(set (match_dup 0) (match_dup 2))
3100 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
3103 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
3105 if (tem == operands[0])
3112 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
3113 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
3114 "register_operand (operands[0], DImode)
3115 || reg_or_0_operand (operands[1], DImode)"
3129 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
3131 ;; We do three major things here: handle mem->mem, put 64-bit constants in
3132 ;; memory, and construct long 32-bit constants.
3134 (define_expand "movdi"
3135 [(set (match_operand:DI 0 "general_operand" "")
3136 (match_operand:DI 1 "general_operand" ""))]
3142 if (GET_CODE (operands[0]) == MEM
3143 && ! reg_or_0_operand (operands[1], DImode))
3144 operands[1] = force_reg (DImode, operands[1]);
3146 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
3148 else if (GET_CODE (operands[1]) == CONST_INT
3149 && (tem = alpha_emit_set_const (operands[0], DImode,
3150 INTVAL (operands[1]), 3)) != 0)
3152 if (rtx_equal_p (tem, operands[0]))
3157 else if (CONSTANT_P (operands[1]))
3159 operands[1] = force_const_mem (DImode, operands[1]);
3160 if (reload_in_progress)
3162 emit_move_insn (operands[0], XEXP (operands[1], 0));
3163 operands[1] = copy_rtx (operands[1]);
3164 XEXP (operands[1], 0) = operands[0];
3167 operands[1] = validize_mem (operands[1]);
3173 ;; Split a load of a large constant into the appropriate two-insn
3177 [(set (match_operand:DI 0 "register_operand" "")
3178 (match_operand:DI 1 "const_int_operand" ""))]
3179 "! add_operand (operands[1], DImode)"
3180 [(set (match_dup 0) (match_dup 2))
3181 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
3184 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
3186 if (tem == operands[0])
3192 ;; These are the partial-word cases.
3194 ;; First we have the code to load an aligned word. Operand 0 is the register
3195 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
3196 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
3197 ;; number of bits within the word that the value is. Operand 3 is an SImode
3198 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
3199 ;; same register. It is allowed to conflict with operand 1 as well.
3201 (define_expand "aligned_loadqi"
3202 [(set (match_operand:SI 3 "register_operand" "")
3203 (match_operand:SI 1 "memory_operand" ""))
3204 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3205 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3207 (match_operand:DI 2 "const_int_operand" "")))]
3212 (define_expand "aligned_loadhi"
3213 [(set (match_operand:SI 3 "register_operand" "")
3214 (match_operand:SI 1 "memory_operand" ""))
3215 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
3216 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3218 (match_operand:DI 2 "const_int_operand" "")))]
3223 ;; Similar for unaligned loads. For QImode, we use the sequence from the
3224 ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers
3225 ;; are normally aligned to the byte boundary, so an HImode object cannot
3226 ;; cross a longword boundary. We could use a sequence similar to that for
3227 ;; QImode, but that would fail if the pointer, was, in fact, not aligned.
3228 ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order
3229 ;; bit was not aligned, this will trap and the trap handler will do what is
3232 ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where
3233 ;; operand 3 can overlap the input and output registers.
3235 (define_expand "unaligned_loadqi"
3236 [(set (match_operand:DI 2 "register_operand" "")
3237 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
3239 (set (match_operand:DI 3 "register_operand" "")
3241 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3242 (zero_extract:DI (match_dup 2)
3244 (ashift:DI (match_dup 3) (const_int 3))))]
3248 ;; For this, the address must already be in a register. We also need two
3249 ;; DImode temporaries, neither of which may overlap the input (and hence the
3250 ;; output, since they might be the same register), but both of which may
3253 (define_expand "unaligned_loadhi"
3254 [(set (match_operand:DI 2 "register_operand" "")
3255 (and:DI (match_operand:DI 1 "register_operand" "")
3257 (set (match_operand:DI 3 "register_operand" "")
3258 (mem:DI (match_dup 2)))
3259 (set (match_operand:DI 4 "register_operand" "")
3260 (and:DI (match_dup 1) (const_int -2)))
3261 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
3262 (zero_extract:DI (match_dup 3)
3264 (ashift:DI (match_dup 4) (const_int 3))))]
3268 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
3269 ;; aligned SImode MEM. Operand 1 is the register containing the
3270 ;; byte or word to store. Operand 2 is the number of bits within the word that
3271 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
3273 (define_expand "aligned_store"
3274 [(set (match_operand:SI 3 "register_operand" "")
3275 (match_operand:SI 0 "memory_operand" ""))
3276 (set (subreg:DI (match_dup 3) 0)
3277 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
3278 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
3279 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
3280 (match_operand:DI 2 "const_int_operand" "")))
3281 (set (subreg:DI (match_dup 4) 0)
3282 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
3283 (set (match_dup 0) (match_dup 4))]
3286 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
3287 << INTVAL (operands[2])));
3290 ;; For the unaligned byte case, we use code similar to that in the
3291 ;; Architecture book, but reordered to lower the number of registers
3292 ;; required. Operand 0 is the address. Operand 1 is the data to store.
3293 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
3294 ;; be the same temporary, if desired. If the address is in a register,
3295 ;; operand 2 can be that register.
3297 (define_expand "unaligned_storeqi"
3298 [(set (match_operand:DI 3 "register_operand" "")
3299 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
3301 (set (match_operand:DI 2 "register_operand" "")
3304 (and:DI (not:DI (ashift:DI (const_int 255)
3305 (ashift:DI (match_dup 2) (const_int 3))))
3307 (set (match_operand:DI 4 "register_operand" "")
3308 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
3309 (ashift:DI (match_dup 2) (const_int 3))))
3310 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
3311 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
3316 ;; This is the code for storing into an unaligned short. It uses the same
3317 ;; trick as loading from an unaligned short. It needs lots of temporaries.
3318 ;; However, during reload, we only have two registers available. So we
3319 ;; repeat code so that only two temporaries are available. During RTL
3320 ;; generation, we can use different pseudos for each temporary and CSE
3321 ;; will remove the redundancies. During reload, we have to settle with
3322 ;; what we get. Luckily, unaligned accesses of this kind produced during
3323 ;; reload are quite rare.
3325 ;; Operand 0 is the address of the memory location. Operand 1 contains the
3326 ;; data to store. The rest of the operands are all temporaries, with
3327 ;; various overlap possibilities during reload. See reload_outhi for
3328 ;; details of this use.
3330 (define_expand "unaligned_storehi"
3331 [(set (match_operand:DI 2 "register_operand" "")
3332 (match_operand:DI 0 "address_operand" ""))
3333 (set (match_operand:DI 3 "register_operand" "")
3334 (and:DI (match_dup 2) (const_int -7)))
3335 (set (match_operand:DI 4 "register_operand" "")
3336 (mem:DI (match_dup 3)))
3337 (set (match_operand:DI 10 "register_operand" "")
3338 (and:DI (match_dup 2) (const_int -2)))
3339 (set (match_operand:DI 5 "register_operand" "")
3340 (and:DI (not:DI (ashift:DI (const_int 65535)
3341 (ashift:DI (match_dup 10) (const_int 3))))
3343 (set (match_operand:DI 6 "register_operand" "")
3344 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
3345 (ashift:DI (match_dup 10) (const_int 3))))
3346 (set (match_operand:DI 7 "register_operand" "")
3347 (ior:DI (match_dup 5) (match_dup 6)))
3348 (set (match_operand:DI 8 "register_operand" "") (match_dup 0))
3349 (set (match_operand:DI 9 "register_operand" "")
3350 (and:DI (match_dup 8) (const_int -7)))
3351 (set (mem:DI (match_dup 9)) (match_dup 7))]
3355 ;; Here are the define_expand's for QI and HI moves that use the above
3356 ;; patterns. We have the normal sets, plus the ones that need scratch
3357 ;; registers for reload.
3359 (define_expand "movqi"
3360 [(set (match_operand:QI 0 "general_operand" "")
3361 (match_operand:QI 1 "general_operand" ""))]
3364 { extern rtx get_unaligned_address ();
3366 /* If the output is not a register, the input must be. */
3367 if (GET_CODE (operands[0]) == MEM)
3368 operands[1] = force_reg (QImode, operands[1]);
3370 /* Handle four memory cases, unaligned and aligned for either the input
3371 or the output. The only case where we can be called during reload is
3372 for aligned loads; all other cases require temporaries. */
3374 if (GET_CODE (operands[1]) == MEM
3375 || (GET_CODE (operands[1]) == SUBREG
3376 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3377 || (reload_in_progress && GET_CODE (operands[1]) == REG
3378 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3379 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3380 && GET_CODE (SUBREG_REG (operands[1])) == REG
3381 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3383 if (aligned_memory_operand (operands[1], QImode))
3385 rtx aligned_mem, bitnum;
3386 rtx scratch = (reload_in_progress
3387 ? gen_rtx (REG, SImode, REGNO (operands[0]))
3388 : gen_reg_rtx (SImode));
3390 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3392 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
3397 /* Don't pass these as parameters since that makes the generated
3398 code depend on parameter evaluation order which will cause
3399 bootstrap failures. */
3401 rtx temp1 = gen_reg_rtx (DImode);
3402 rtx temp2 = gen_reg_rtx (DImode);
3403 rtx seq = gen_unaligned_loadqi (operands[0],
3404 get_unaligned_address (operands[1]),
3407 alpha_set_memflags (seq, operands[1]);
3414 else if (GET_CODE (operands[0]) == MEM
3415 || (GET_CODE (operands[0]) == SUBREG
3416 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3417 || (reload_in_progress && GET_CODE (operands[0]) == REG
3418 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3419 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3420 && GET_CODE (SUBREG_REG (operands[0])) == REG
3421 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3423 if (aligned_memory_operand (operands[0], QImode))
3425 rtx aligned_mem, bitnum;
3426 rtx temp1 = gen_reg_rtx (SImode);
3427 rtx temp2 = gen_reg_rtx (SImode);
3429 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3431 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3436 rtx temp1 = gen_reg_rtx (DImode);
3437 rtx temp2 = gen_reg_rtx (DImode);
3438 rtx temp3 = gen_reg_rtx (DImode);
3439 rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]),
3440 operands[1], temp1, temp2, temp3);
3442 alpha_set_memflags (seq, operands[0]);
3449 (define_expand "movhi"
3450 [(set (match_operand:HI 0 "general_operand" "")
3451 (match_operand:HI 1 "general_operand" ""))]
3454 { extern rtx get_unaligned_address ();
3456 /* If the output is not a register, the input must be. */
3457 if (GET_CODE (operands[0]) == MEM)
3458 operands[1] = force_reg (HImode, operands[1]);
3460 /* Handle four memory cases, unaligned and aligned for either the input
3461 or the output. The only case where we can be called during reload is
3462 for aligned loads; all other cases require temporaries. */
3464 if (GET_CODE (operands[1]) == MEM
3465 || (GET_CODE (operands[1]) == SUBREG
3466 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3467 || (reload_in_progress && GET_CODE (operands[1]) == REG
3468 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3469 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3470 && GET_CODE (SUBREG_REG (operands[1])) == REG
3471 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3473 if (aligned_memory_operand (operands[1], HImode))
3475 rtx aligned_mem, bitnum;
3476 rtx scratch = (reload_in_progress
3477 ? gen_rtx (REG, SImode, REGNO (operands[0]))
3478 : gen_reg_rtx (SImode));
3480 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3482 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
3488 = force_reg (DImode,
3489 force_operand (get_unaligned_address (operands[1]),
3491 rtx scratch1 = gen_reg_rtx (DImode);
3492 rtx scratch2 = gen_reg_rtx (DImode);
3493 rtx scratch3 = gen_reg_rtx (DImode);
3495 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1,
3496 scratch2, scratch3);
3498 alpha_set_memflags (seq, operands[1]);
3505 else if (GET_CODE (operands[0]) == MEM
3506 || (GET_CODE (operands[0]) == SUBREG
3507 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3508 || (reload_in_progress && GET_CODE (operands[0]) == REG
3509 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3510 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3511 && GET_CODE (SUBREG_REG (operands[0])) == REG
3512 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3514 if (aligned_memory_operand (operands[0], HImode))
3516 rtx aligned_mem, bitnum;
3517 rtx temp1 = gen_reg_rtx (SImode);
3518 rtx temp2 = gen_reg_rtx (SImode);
3520 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3522 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3527 rtx temp1 = gen_reg_rtx (DImode);
3528 rtx temp2 = gen_reg_rtx (DImode);
3529 rtx temp3 = gen_reg_rtx (DImode);
3530 rtx temp4 = gen_reg_rtx (DImode);
3531 rtx temp5 = gen_reg_rtx (DImode);
3532 rtx temp6 = gen_reg_rtx (DImode);
3533 rtx temp7 = gen_reg_rtx (DImode);
3534 rtx temp8 = gen_reg_rtx (DImode);
3535 rtx temp9 = gen_reg_rtx (DImode);
3537 rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]),
3538 operands[1], temp1, temp2,temp3,
3539 temp4, temp5, temp6,temp7,
3542 alpha_set_memflags (seq, operands[0]);
3550 ;; Here are the versions for reload. Note that in the unaligned cases
3551 ;; we know that the operand must not be a pseudo-register because stack
3552 ;; slots are always aligned references.
3554 (define_expand "reload_inqi"
3555 [(parallel [(match_operand:QI 0 "register_operand" "=r")
3556 (match_operand:QI 1 "unaligned_memory_operand" "m")
3557 (match_operand:TI 2 "register_operand" "=&r")])]
3560 { extern rtx get_unaligned_address ();
3561 rtx addr = get_unaligned_address (operands[1]);
3562 /* It is possible that one of the registers we got for operands[2]
3563 might coincide with that of operands[0] (which is why we made
3564 it TImode). Pick the other one to use as our scratch. */
3565 rtx scratch = gen_rtx (REG, DImode,
3566 REGNO (operands[0]) == REGNO (operands[2])
3567 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
3568 rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
3569 gen_rtx (REG, DImode, REGNO (operands[0])));
3571 alpha_set_memflags (seq, operands[1]);
3576 (define_expand "reload_inhi"
3577 [(parallel [(match_operand:HI 0 "register_operand" "=r")
3578 (match_operand:HI 1 "unaligned_memory_operand" "m")
3579 (match_operand:TI 2 "register_operand" "=&r")])]
3582 { extern rtx get_unaligned_address ();
3583 rtx addr = get_unaligned_address (operands[1]);
3584 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3585 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3588 if (GET_CODE (addr) != REG)
3590 emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr));
3594 seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1, scratch2);
3595 alpha_set_memflags (seq, operands[1]);
3600 (define_expand "reload_outqi"
3601 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
3602 (match_operand:QI 1 "register_operand" "r")
3603 (match_operand:TI 2 "register_operand" "=&r")])]
3606 { extern rtx get_unaligned_address ();
3608 if (aligned_memory_operand (operands[0], QImode))
3610 rtx aligned_mem, bitnum;
3612 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3614 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3615 gen_rtx (REG, SImode, REGNO (operands[2])),
3616 gen_rtx (REG, SImode,
3617 REGNO (operands[2]) + 1)));
3621 rtx addr = get_unaligned_address (operands[0]);
3622 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3623 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3624 rtx scratch3 = scratch1;
3627 if (GET_CODE (addr) == REG)
3630 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
3631 scratch2, scratch3);
3632 alpha_set_memflags (seq, operands[0]);
3639 (define_expand "reload_outhi"
3640 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
3641 (match_operand:HI 1 "register_operand" "r")
3642 (match_operand:TI 2 "register_operand" "=&r")])]
3645 { extern rtx get_unaligned_address ();
3647 if (aligned_memory_operand (operands[0], HImode))
3649 rtx aligned_mem, bitnum;
3651 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3653 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3654 gen_rtx (REG, SImode, REGNO (operands[2])),
3655 gen_rtx (REG, SImode,
3656 REGNO (operands[2]) + 1)));
3660 rtx addr = get_unaligned_address (operands[0]);
3661 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3662 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3663 rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1;
3666 seq = gen_unaligned_storehi (addr, operands[1], scratch_a,
3667 scratch2, scratch2, scratch2,
3668 scratch1, scratch2, scratch_a,
3669 scratch1, scratch_a);
3670 alpha_set_memflags (seq, operands[0]);
3677 ;; Subroutine of stack space allocation. Perform a stack probe.
3678 (define_expand "probe_stack"
3679 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
3683 operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx,
3684 INTVAL (operands[0])));
3685 MEM_VOLATILE_P (operands[1]) = 1;
3687 operands[0] = const0_rtx;
3690 ;; This is how we allocate stack space. If we are allocating a
3691 ;; constant amount of space and we know it is less than 4096
3692 ;; bytes, we need do nothing.
3694 ;; If it is more than 4096 bytes, we need to probe the stack
3696 (define_expand "allocate_stack"
3698 (plus:DI (reg:DI 30)
3699 (match_operand:DI 0 "reg_or_cint_operand" "")))]
3703 if (GET_CODE (operands[0]) == CONST_INT
3704 && INTVAL (operands[0]) < 32768)
3706 if (INTVAL (operands[0]) >= 4096)
3708 /* We do this the same way as in the prologue and generate explicit
3709 probes. Then we update the stack by the constant. */
3713 emit_insn (gen_probe_stack (GEN_INT (- probed)));
3714 while (probed + 8192 < INTVAL (operands[0]))
3715 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
3717 if (probed + 4096 < INTVAL (operands[0]))
3718 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[0]))));
3721 operands[0] = GEN_INT (- INTVAL (operands[0]));
3726 rtx loop_label = gen_label_rtx ();
3727 rtx want = gen_reg_rtx (Pmode);
3728 rtx tmp = gen_reg_rtx (Pmode);
3731 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
3732 force_reg (Pmode, operands[0])));
3733 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
3735 if (GET_CODE (operands[0]) != CONST_INT)
3737 out_label = gen_label_rtx ();
3738 emit_insn (gen_cmpdi (want, tmp));
3739 emit_jump_insn (gen_bgeu (out_label));
3742 emit_label (loop_label);
3743 memref = gen_rtx (MEM, DImode, tmp);
3744 MEM_VOLATILE_P (memref) = 1;
3745 emit_move_insn (memref, const0_rtx);
3746 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
3747 emit_insn (gen_cmpdi (tmp, want));
3748 emit_jump_insn (gen_bgtu (loop_label));
3749 memref = gen_rtx (MEM, DImode, want);
3750 MEM_VOLATILE_P (memref) = 1;
3751 emit_move_insn (memref, const0_rtx);
3754 emit_label (out_label);
3756 emit_move_insn (stack_pointer_rtx, want);