1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Processor type -- this attribute must exactly match the processor_type
25 ;; enumeration in alpha.h.
27 (define_attr "cpu" "ev4,ev5"
28 (const (symbol_ref "alpha_cpu")))
30 ;; Define an insn type attribute. This is used in function unit delay
31 ;; computations, among other purposes. For the most part, we use the names
32 ;; defined in the EV4 documentation, but add a few that we have to know about
36 "ld,st,ibr,fbr,jsr,iadd,ilog,shift,cmov,icmp,imull,imulq,fadd,fmul,fcpys,fdivs,fdivt,ldsym,isubr"
37 (const_string "iadd"))
39 ;; The TRAP_TYPE attribute marks instructions that may generate traps
40 ;; (which are imprecise and may need a trapb if software complention
42 (define_attr "trap" "yes,no" (const_string "no"))
44 ;; For the EV4 we include four function units: ABOX, which computes the address,
45 ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
46 ;; used for FP operations.
48 ;; We assume that we have been successful in getting double issues and
49 ;; hence multiply all costs by two insns per cycle. The minimum time in
50 ;; a function unit is 2 cycle, which will tend to produce the double
53 ;; Memory delivers its result in three cycles.
54 (define_function_unit "ev4_abox" 1 0
55 (and (eq_attr "cpu" "ev4")
56 (eq_attr "type" "ld,st"))
59 ;; Branches have no delay cost, but do tie up the unit for two cycles.
60 (define_function_unit "ev4_bbox" 1 1
61 (and (eq_attr "cpu" "ev4")
62 (eq_attr "type" "ibr,fbr,jsr"))
65 ;; Arithmetic insns are normally have their results available after two
66 ;; cycles. There are a number of exceptions. They are encoded in
67 ;; ADJUST_COST. Some of the other insns have similar exceptions.
69 (define_function_unit "ev4_ebox" 1 0
70 (and (eq_attr "cpu" "ev4")
71 (eq_attr "type" "iadd,ilog,ldsym,shift,cmov,icmp"))
74 ;; These really don't take up the integer pipeline, but they do occupy
75 ;; IBOX1; we approximate here.
77 (define_function_unit "ev4_ebox" 1 0
78 (and (eq_attr "cpu" "ev4")
79 (eq_attr "type" "imull"))
82 (define_function_unit "ev4_ebox" 1 0
83 (and (eq_attr "cpu" "ev4")
84 (eq_attr "type" "imulq"))
87 (define_function_unit "ev4_imult" 1 0
88 (and (eq_attr "cpu" "ev4")
89 (eq_attr "type" "imull"))
92 (define_function_unit "ev4_imult" 1 0
93 (and (eq_attr "cpu" "ev4")
94 (eq_attr "type" "imulq"))
97 (define_function_unit "ev4_fbox" 1 0
98 (and (eq_attr "cpu" "ev4")
99 (eq_attr "type" "fadd,fmul,fcpys"))
102 (define_function_unit "ev4_fbox" 1 0
103 (and (eq_attr "cpu" "ev4")
104 (eq_attr "type" "fdivs"))
107 (define_function_unit "ev4_fbox" 1 0
108 (and (eq_attr "cpu" "ev4")
109 (eq_attr "type" "fdivt"))
112 (define_function_unit "ev4_divider" 1 0
113 (and (eq_attr "cpu" "ev4")
114 (eq_attr "type" "fdivs"))
117 (define_function_unit "ev4_divider" 1 0
118 (and (eq_attr "cpu" "ev4")
119 (eq_attr "type" "fdivt"))
122 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
123 ;; Multiply all costs by 4.
125 ;; EV5 has two integer units.
126 (define_function_unit "ev5_ebox" 2 0
127 (and (eq_attr "cpu" "ev5")
128 (eq_attr "type" "iadd,ilog,icmp,ldsym"))
131 ;; Memory takes at least 2 clocks.
132 ;; Conditional moves always take 2 ticks.
133 (define_function_unit "ev5_ebox" 2 0
134 (and (eq_attr "cpu" "ev5")
135 (eq_attr "type" "ld,cmov"))
138 ;; Loads can dual issue. Store cannot; nor can loads + stores.
139 ;; Model this with a mythical load/store unit.
140 (define_function_unit "ev5_ldst" 1 0
141 (and (eq_attr "cpu" "ev5")
142 (eq_attr "type" "ld"))
143 8 4 [(eq_attr "type" "st")])
145 (define_function_unit "ev5_ldst" 1 0
146 (and (eq_attr "cpu" "ev5")
147 (eq_attr "type" "st"))
150 (define_function_unit "ev5_ebox" 2 0
151 (and (eq_attr "cpu" "ev5")
152 (eq_attr "type" "imull"))
155 (define_function_unit "ev5_ebox" 2 0
156 (and (eq_attr "cpu" "ev5")
157 (eq_attr "type" "imulq"))
160 ;; Multiplies also use the integer multiplier.
161 (define_function_unit "ev5_imult" 1 0
162 (and (eq_attr "cpu" "ev5")
163 (eq_attr "type" "imull"))
166 (define_function_unit "ev5_imult" 1 0
167 (and (eq_attr "cpu" "ev5")
168 (eq_attr "type" "imulq"))
171 ;; There is only 1 shifter/zapper.
172 (define_function_unit "ev5_shift" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "shift"))
177 ;; We pretend EV5 has symmetrical 2 fpus,
178 ;; even though cpys is the only insn that can issue on either unit.
179 (define_function_unit "ev5_fpu" 2 0
180 (and (eq_attr "cpu" "ev5")
181 (eq_attr "type" "fadd,fmul,fcpys"))
184 ;; Multiplies (resp. adds) also use the fmul (resp. fadd) units.
185 (define_function_unit "ev5_fpmul" 1 0
186 (and (eq_attr "cpu" "ev5")
187 (eq_attr "type" "fmul"))
190 (define_function_unit "ev5_fpadd" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "fadd"))
195 (define_function_unit "ev5_fpadd" 1 0
196 (and (eq_attr "cpu" "ev5")
197 (eq_attr "type" "fbr"))
200 (define_function_unit "ev5_fpadd" 1 0
201 (and (eq_attr "cpu" "ev5")
202 (eq_attr "type" "fdivs"))
205 (define_function_unit "ev5_fpadd" 1 0
206 (and (eq_attr "cpu" "ev5")
207 (eq_attr "type" "fdivt"))
210 ;; First define the arithmetic insns. Note that the 32-bit forms also
213 ;; Note that we can do sign extensions in both FP and integer registers.
214 ;; However, the result must be in the same type of register as the input.
215 ;; The register preferencing code can't handle this case very well, so, for
216 ;; now, don't let the FP case show up here for preferencing. Also,
217 ;; sign-extends in FP registers take two instructions.
218 (define_insn "extendsidi2"
219 [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
220 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
225 cvtql %1,%0\;cvtlq %0,%0"
226 [(set_attr "type" "iadd,ld,fadd")])
228 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
229 ;; generates better code. We have the anonymous addsi3 pattern below in
230 ;; case combine wants to make it.
231 (define_expand "addsi3"
232 [(set (match_operand:SI 0 "register_operand" "")
233 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
234 (match_operand:SI 2 "add_operand" "")))]
237 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
238 gen_rtx (PLUS, DImode,
239 gen_lowpart (DImode, operands[1]),
240 gen_lowpart (DImode, operands[2]))));
245 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
246 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
247 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
256 [(set (match_operand:SI 0 "register_operand" "")
257 (plus:SI (match_operand:SI 1 "register_operand" "")
258 (match_operand:SI 2 "const_int_operand" "")))]
259 "! add_operand (operands[2], SImode)"
260 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
261 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
264 HOST_WIDE_INT val = INTVAL (operands[2]);
265 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
266 HOST_WIDE_INT rest = val - low;
268 operands[3] = GEN_INT (rest);
269 operands[4] = GEN_INT (low);
273 [(set (match_operand:DI 0 "register_operand" "=r,r")
275 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
276 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
283 [(set (match_operand:DI 0 "register_operand" "")
285 (plus:SI (match_operand:SI 1 "register_operand" "")
286 (match_operand:SI 2 "const_int_operand" ""))))
287 (clobber (match_operand:SI 3 "register_operand" ""))]
288 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
289 && INTVAL (operands[2]) % 4 == 0"
290 [(set (match_dup 3) (match_dup 4))
291 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
296 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
302 operands[4] = GEN_INT (val);
303 operands[5] = GEN_INT (mult);
307 [(set (match_operand:DI 0 "register_operand" "")
309 (plus:SI (match_operator:SI 1 "comparison_operator"
310 [(match_operand 2 "" "")
311 (match_operand 3 "" "")])
312 (match_operand:SI 4 "add_operand" ""))))
313 (clobber (match_operand:DI 5 "register_operand" ""))]
315 [(set (match_dup 5) (match_dup 6))
316 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
319 operands[6] = gen_rtx (GET_CODE (operands[1]), DImode,
320 operands[2], operands[3]);
321 operands[7] = gen_lowpart (SImode, operands[5]);
324 (define_insn "adddi3"
325 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
326 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
327 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
335 ;; Don't do this if we are adjusting SP since we don't want to do
338 [(set (match_operand:DI 0 "register_operand" "")
339 (plus:DI (match_operand:DI 1 "register_operand" "")
340 (match_operand:DI 2 "const_int_operand" "")))]
341 "! add_operand (operands[2], DImode)
342 && REGNO (operands[0]) != STACK_POINTER_REGNUM"
343 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
344 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
347 HOST_WIDE_INT val = INTVAL (operands[2]);
348 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
349 HOST_WIDE_INT rest = val - low;
351 operands[3] = GEN_INT (rest);
352 operands[4] = GEN_INT (low);
356 [(set (match_operand:SI 0 "register_operand" "=r,r")
357 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
358 (match_operand:SI 2 "const48_operand" "I,I"))
359 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
366 [(set (match_operand:DI 0 "register_operand" "=r,r")
368 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
369 (match_operand:SI 2 "const48_operand" "I,I"))
370 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
377 [(set (match_operand:DI 0 "register_operand" "")
379 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
380 [(match_operand 2 "" "")
381 (match_operand 3 "" "")])
382 (match_operand:SI 4 "const48_operand" ""))
383 (match_operand:SI 5 "add_operand" ""))))
384 (clobber (match_operand:DI 6 "register_operand" ""))]
386 [(set (match_dup 6) (match_dup 7))
388 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
392 operands[7] = gen_rtx (GET_CODE (operands[1]), DImode,
393 operands[2], operands[3]);
394 operands[8] = gen_lowpart (SImode, operands[6]);
398 [(set (match_operand:DI 0 "register_operand" "=r,r")
399 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
400 (match_operand:DI 2 "const48_operand" "I,I"))
401 (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))]
407 ;; These variants of the above insns can occur if the third operand
408 ;; is the frame pointer. This is a kludge, but there doesn't
409 ;; seem to be a way around it. Only recognize them while reloading.
412 [(set (match_operand:DI 0 "some_operand" "=&r")
413 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
414 (match_operand:DI 2 "some_operand" "r"))
415 (match_operand:DI 3 "some_operand" "rIOKL")))]
420 [(set (match_operand:DI 0 "register_operand" "")
421 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
422 (match_operand:DI 2 "register_operand" ""))
423 (match_operand:DI 3 "add_operand" "")))]
425 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
426 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
430 [(set (match_operand:SI 0 "some_operand" "=&r")
431 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
432 (match_operand:SI 2 "const48_operand" "I"))
433 (match_operand:SI 3 "some_operand" "r"))
434 (match_operand:SI 4 "some_operand" "rIOKL")))]
439 [(set (match_operand:SI 0 "register_operand" "r")
440 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
441 (match_operand:SI 2 "const48_operand" ""))
442 (match_operand:SI 3 "register_operand" ""))
443 (match_operand:SI 4 "add_operand" "rIOKL")))]
446 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
447 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
451 [(set (match_operand:DI 0 "some_operand" "=&r")
454 (mult:SI (match_operand:SI 1 "some_operand" "rJ")
455 (match_operand:SI 2 "const48_operand" "I"))
456 (match_operand:SI 3 "some_operand" "r"))
457 (match_operand:SI 4 "some_operand" "rIOKL"))))]
462 [(set (match_operand:DI 0 "register_operand" "")
465 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
466 (match_operand:SI 2 "const48_operand" ""))
467 (match_operand:SI 3 "register_operand" ""))
468 (match_operand:SI 4 "add_operand" ""))))]
471 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
472 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
474 { operands[5] = gen_lowpart (SImode, operands[0]);
478 [(set (match_operand:DI 0 "some_operand" "=&r")
479 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
480 (match_operand:DI 2 "const48_operand" "I"))
481 (match_operand:DI 3 "some_operand" "r"))
482 (match_operand:DI 4 "some_operand" "rIOKL")))]
487 [(set (match_operand:DI 0 "register_operand" "=")
488 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
489 (match_operand:DI 2 "const48_operand" ""))
490 (match_operand:DI 3 "register_operand" ""))
491 (match_operand:DI 4 "add_operand" "")))]
494 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
495 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
498 (define_insn "negsi2"
499 [(set (match_operand:SI 0 "register_operand" "=r")
500 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
505 [(set (match_operand:DI 0 "register_operand" "=r")
506 (sign_extend:DI (neg:SI
507 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
511 (define_insn "negdi2"
512 [(set (match_operand:DI 0 "register_operand" "=r")
513 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
517 (define_expand "subsi3"
518 [(set (match_operand:SI 0 "register_operand" "")
519 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
520 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
523 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
524 gen_rtx (MINUS, DImode,
525 gen_lowpart (DImode, operands[1]),
526 gen_lowpart (DImode, operands[2]))));
532 [(set (match_operand:SI 0 "register_operand" "=r")
533 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
534 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
539 [(set (match_operand:DI 0 "register_operand" "=r")
540 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
541 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
545 (define_insn "subdi3"
546 [(set (match_operand:DI 0 "register_operand" "=r")
547 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
548 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
553 [(set (match_operand:SI 0 "register_operand" "=r")
554 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
555 (match_operand:SI 2 "const48_operand" "I"))
556 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
561 [(set (match_operand:DI 0 "register_operand" "=r")
563 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
564 (match_operand:SI 2 "const48_operand" "I"))
565 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
570 [(set (match_operand:DI 0 "register_operand" "=r")
571 (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
572 (match_operand:DI 2 "const48_operand" "I"))
573 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
577 (define_insn "mulsi3"
578 [(set (match_operand:SI 0 "register_operand" "=r")
579 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
580 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
583 [(set_attr "type" "imull")])
586 [(set (match_operand:DI 0 "register_operand" "=r")
587 (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
588 (match_operand:SI 2 "reg_or_0_operand" "rJ"))))]
591 [(set_attr "type" "imull")])
593 (define_insn "muldi3"
594 [(set (match_operand:DI 0 "register_operand" "=r")
595 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
596 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
599 [(set_attr "type" "imulq")])
601 (define_insn "umuldi3_highpart"
602 [(set (match_operand:DI 0 "register_operand" "=r")
605 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
606 (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
610 [(set_attr "type" "imulq")])
613 [(set (match_operand:DI 0 "register_operand" "=r")
616 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
617 (match_operand:TI 2 "cint8_operand" "I"))
621 [(set_attr "type" "imulq")])
623 ;; The divide and remainder operations always take their inputs from
624 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
626 ;; ??? comment out the divsi routines since the library functions
627 ;; don't seem to do the right thing with the high 32-bits of a
630 ;(define_expand "divsi3"
631 ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
632 ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
633 ; (parallel [(set (reg:SI 27)
634 ; (div:SI (reg:SI 24)
636 ; (clobber (reg:DI 23))
637 ; (clobber (reg:DI 28))])
638 ; (set (match_operand:SI 0 "general_operand" "")
643 ;(define_expand "udivsi3"
644 ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
645 ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
646 ; (parallel [(set (reg:SI 27)
647 ; (udiv:SI (reg:SI 24)
649 ; (clobber (reg:DI 23))
650 ; (clobber (reg:DI 28))])
651 ; (set (match_operand:SI 0 "general_operand" "")
656 ;(define_expand "modsi3"
657 ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
658 ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
659 ; (parallel [(set (reg:SI 27)
660 ; (mod:SI (reg:SI 24)
662 ; (clobber (reg:DI 23))
663 ; (clobber (reg:DI 28))])
664 ; (set (match_operand:SI 0 "general_operand" "")
669 ;(define_expand "umodsi3"
670 ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
671 ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
672 ; (parallel [(set (reg:SI 27)
673 ; (umod:SI (reg:SI 24)
675 ; (clobber (reg:DI 23))
676 ; (clobber (reg:DI 28))])
677 ; (set (match_operand:SI 0 "general_operand" "")
682 (define_expand "divdi3"
683 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
684 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
685 (parallel [(set (reg:DI 27)
688 (clobber (reg:DI 23))
689 (clobber (reg:DI 28))])
690 (set (match_operand:DI 0 "general_operand" "")
695 (define_expand "udivdi3"
696 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
697 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
698 (parallel [(set (reg:DI 27)
701 (clobber (reg:DI 23))
702 (clobber (reg:DI 28))])
703 (set (match_operand:DI 0 "general_operand" "")
708 (define_expand "moddi3"
709 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
710 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
711 (parallel [(set (reg:DI 27)
714 (clobber (reg:DI 23))
715 (clobber (reg:DI 28))])
716 (set (match_operand:DI 0 "general_operand" "")
721 (define_expand "umoddi3"
722 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
723 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
724 (parallel [(set (reg:DI 27)
727 (clobber (reg:DI 23))
728 (clobber (reg:DI 28))])
729 (set (match_operand:DI 0 "general_operand" "")
736 ; (match_operator:SI 1 "divmod_operator"
737 ; [(reg:SI 24) (reg:SI 25)]))
738 ; (clobber (reg:DI 23))
739 ; (clobber (reg:DI 28))]
742 ; [(set_attr "type" "isubr")])
746 (match_operator:DI 1 "divmod_operator"
747 [(reg:DI 24) (reg:DI 25)]))
748 (clobber (reg:DI 23))
749 (clobber (reg:DI 28))]
752 [(set_attr "type" "isubr")])
754 ;; Next are the basic logical operations. These only exist in DImode.
756 (define_insn "anddi3"
757 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
758 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
759 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
765 [(set_attr "type" "ilog,ilog,shift")])
767 ;; There are times when we can split an AND into two AND insns. This occurs
768 ;; when we can first clear any bytes and then clear anything else. For
769 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
770 ;; Only do this when running on 64-bit host since the computations are
771 ;; too messy otherwise.
774 [(set (match_operand:DI 0 "register_operand" "")
775 (and:DI (match_operand:DI 1 "register_operand" "")
776 (match_operand:DI 2 "const_int_operand" "")))]
777 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
778 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
779 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
782 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
783 unsigned HOST_WIDE_INT mask2 = mask1;
786 /* For each byte that isn't all zeros, make it all ones. */
787 for (i = 0; i < 64; i += 8)
788 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
789 mask1 |= (HOST_WIDE_INT) 0xff << i;
791 /* Now turn on any bits we've just turned off. */
794 operands[3] = GEN_INT (mask1);
795 operands[4] = GEN_INT (mask2);
798 (define_insn "zero_extendqihi2"
799 [(set (match_operand:HI 0 "register_operand" "=r")
800 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
803 [(set_attr "type" "shift")])
806 [(set (match_operand:SI 0 "register_operand" "=r,r")
807 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
812 [(set_attr "type" "shift,ld")])
814 (define_insn "zero_extendqisi2"
815 [(set (match_operand:SI 0 "register_operand" "=r")
816 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
819 [(set_attr "type" "shift")])
822 [(set (match_operand:DI 0 "register_operand" "=r,r")
823 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
828 [(set_attr "type" "shift,ld")])
830 (define_insn "zero_extendqidi2"
831 [(set (match_operand:DI 0 "register_operand" "=r")
832 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
835 [(set_attr "type" "shift")])
838 [(set (match_operand:SI 0 "register_operand" "=r,r")
839 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
844 [(set_attr "type" "shift,ld")])
846 (define_insn "zero_extendhisi2"
847 [(set (match_operand:SI 0 "register_operand" "=r")
848 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
851 [(set_attr "type" "shift")])
854 [(set (match_operand:DI 0 "register_operand" "=r,r")
855 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
860 [(set_attr "type" "shift,ld")])
862 (define_insn "zero_extendhidi2"
863 [(set (match_operand:DI 0 "register_operand" "=r")
864 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
867 [(set_attr "type" "shift")])
869 (define_insn "zero_extendsidi2"
870 [(set (match_operand:DI 0 "register_operand" "=r")
871 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
874 [(set_attr "type" "shift")])
877 [(set (match_operand:DI 0 "register_operand" "=r")
878 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
879 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
882 [(set_attr "type" "ilog")])
884 (define_insn "iordi3"
885 [(set (match_operand:DI 0 "register_operand" "=r,r")
886 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
887 (match_operand:DI 2 "or_operand" "rI,N")))]
892 [(set_attr "type" "ilog")])
894 (define_insn "one_cmpldi2"
895 [(set (match_operand:DI 0 "register_operand" "=r")
896 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
899 [(set_attr "type" "ilog")])
902 [(set (match_operand:DI 0 "register_operand" "=r")
903 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
904 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
907 [(set_attr "type" "ilog")])
909 (define_insn "xordi3"
910 [(set (match_operand:DI 0 "register_operand" "=r,r")
911 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
912 (match_operand:DI 2 "or_operand" "rI,N")))]
917 [(set_attr "type" "ilog")])
920 [(set (match_operand:DI 0 "register_operand" "=r")
921 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
922 (match_operand:DI 2 "register_operand" "rI"))))]
925 [(set_attr "type" "ilog")])
927 ;; Next come the shifts and the various extract and insert operations.
929 (define_insn "ashldi3"
930 [(set (match_operand:DI 0 "register_operand" "=r,r")
931 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
932 (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
936 switch (which_alternative)
939 if (operands[2] == const1_rtx)
940 return \"addq %r1,%r1,%0\";
942 return \"s%P2addq %r1,0,%0\";
944 return \"sll %r1,%2,%0\";
947 [(set_attr "type" "iadd,shift")])
949 ;; ??? The following pattern is made by combine, but earlier phases
950 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
951 ;; with this in a better way at some point.
953 ;; [(set (match_operand:DI 0 "register_operand" "=r")
955 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
956 ;; (match_operand:DI 2 "const_int_operand" "P"))
958 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
961 ;; if (operands[2] == const1_rtx)
962 ;; return \"addl %r1,%r1,%0\";
964 ;; return \"s%P2addl %r1,0,%0\";
966 ;; [(set_attr "type" "iadd")])
968 (define_insn "lshrdi3"
969 [(set (match_operand:DI 0 "register_operand" "=r")
970 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
971 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
974 [(set_attr "type" "shift")])
976 (define_insn "ashrdi3"
977 [(set (match_operand:DI 0 "register_operand" "=r")
978 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
979 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
982 [(set_attr "type" "shift")])
984 (define_expand "extendqihi2"
986 (ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
988 (set (match_operand:HI 0 "register_operand" "")
989 (ashiftrt:DI (match_dup 2)
994 /* If we have a MEM (must be unaligned), extend to DImode (which we do
995 specially) and then copy to the result. */
996 if (GET_CODE (operands[1]) == MEM)
998 rtx temp = gen_reg_rtx (DImode);
1000 emit_insn (gen_extendqidi2 (temp, operands[1]));
1001 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1005 operands[0] = gen_lowpart (DImode, operands[0]);
1006 operands[1] = gen_lowpart (DImode, operands[1]);
1007 operands[2] = gen_reg_rtx (DImode);
1010 (define_insn "extendqidi2x"
1011 [(set (match_operand:DI 0 "register_operand" "r")
1012 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1015 [(set_attr "type" "shift")]) ;; not sure what class this belongs to
1017 (define_insn "extendhidi2x"
1018 [(set (match_operand:DI 0 "register_operand" "r")
1019 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1022 [(set_attr "type" "shift")])
1024 (define_expand "extendqisi2"
1026 (ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
1028 (set (match_operand:SI 0 "register_operand" "")
1029 (ashiftrt:DI (match_dup 2)
1034 /* If we have a MEM (must be unaligned), extend to a DImode form of
1035 the result (which we do specially). */
1036 if (GET_CODE (operands[1]) == MEM)
1038 rtx temp = gen_reg_rtx (DImode);
1040 emit_insn (gen_extendqidi2 (temp, operands[1]));
1041 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1045 operands[0] = gen_lowpart (DImode, operands[0]);
1046 operands[1] = gen_lowpart (DImode, operands[1]);
1047 operands[2] = gen_reg_rtx (DImode);
1050 (define_expand "extendqidi2"
1052 (ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
1054 (set (match_operand:DI 0 "register_operand" "")
1055 (ashiftrt:DI (match_dup 2)
1059 { extern rtx get_unaligned_address ();
1061 if (TARGET_BYTE_OPS)
1063 rtx temp = operands[1];
1065 if (GET_CODE (operands[1]) == MEM)
1067 temp = gen_reg_rtx (QImode);
1068 emit_insn (gen_movqi (temp, operands[1]));
1071 emit_insn (gen_extendqidi2x (operands[0], temp));
1075 if (GET_CODE (operands[1]) == MEM)
1078 = gen_unaligned_extendqidi (operands[0],
1079 get_unaligned_address (operands[1], 1));
1081 alpha_set_memflags (seq, operands[1]);
1086 operands[1] = gen_lowpart (DImode, operands[1]);
1087 operands[2] = gen_reg_rtx (DImode);
1090 (define_expand "extendhisi2"
1092 (ashift:DI (match_operand:HI 1 "reg_or_unaligned_mem_operand" "")
1094 (set (match_operand:SI 0 "register_operand" "")
1095 (ashiftrt:DI (match_dup 2)
1100 /* If we have a MEM (must be unaligned), extend to a DImode form of
1101 the result (which we do specially). */
1102 if (GET_CODE (operands[1]) == MEM)
1104 rtx temp = gen_reg_rtx (DImode);
1106 emit_insn (gen_extendhidi2 (temp, operands[1]));
1107 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1111 operands[0] = gen_lowpart (DImode, operands[0]);
1112 operands[1] = gen_lowpart (DImode, operands[1]);
1113 operands[2] = gen_reg_rtx (DImode);
1116 (define_expand "extendhidi2"
1118 (ashift:DI (match_operand:HI 1 "reg_or_unaligned_mem_operand" "")
1120 (set (match_operand:DI 0 "register_operand" "")
1121 (ashiftrt:DI (match_dup 2)
1125 { extern rtx get_unaligned_address ();
1127 if (TARGET_BYTE_OPS)
1129 rtx temp = operands[1];
1131 if (GET_CODE (operands[1]) == MEM)
1133 temp = gen_reg_rtx (HImode);
1134 emit_insn (gen_movhi (temp, operands[1]));
1137 emit_insn (gen_extendhidi2x (operands[0], temp));
1141 if (GET_CODE (operands[1]) == MEM)
1144 = gen_unaligned_extendhidi (operands[0],
1145 get_unaligned_address (operands[1], 2));
1147 alpha_set_memflags (seq, operands[1]);
1152 operands[1] = gen_lowpart (DImode, operands[1]);
1153 operands[2] = gen_reg_rtx (DImode);
1156 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1157 ;; as a pattern saves one instruction. The code is similar to that for
1158 ;; the unaligned loads (see below).
1160 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1161 (define_expand "unaligned_extendqidi"
1162 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1164 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1167 (ashift:DI (match_dup 3)
1168 (minus:DI (const_int 56)
1170 (and:DI (plus:DI (match_dup 2) (const_int -1))
1173 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1174 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1177 { operands[2] = gen_reg_rtx (DImode);
1178 operands[3] = gen_reg_rtx (DImode);
1179 operands[4] = gen_reg_rtx (DImode);
1182 (define_expand "unaligned_extendhidi"
1183 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1185 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1188 (ashift:DI (match_dup 3)
1189 (minus:DI (const_int 56)
1191 (and:DI (plus:DI (match_dup 2) (const_int -1))
1194 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1195 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1198 { operands[2] = gen_reg_rtx (DImode);
1199 operands[3] = gen_reg_rtx (DImode);
1200 operands[4] = gen_reg_rtx (DImode);
1204 [(set (match_operand:DI 0 "register_operand" "=r")
1205 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1206 (match_operand:DI 2 "mode_width_operand" "n")
1207 (match_operand:DI 3 "mul8_operand" "I")))]
1209 "ext%M2l %r1,%s3,%0"
1210 [(set_attr "type" "shift")])
1213 [(set (match_operand:DI 0 "register_operand" "=r")
1214 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1215 (match_operand:DI 2 "mode_width_operand" "n")
1216 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1220 [(set_attr "type" "shift")])
1223 [(set (match_operand:DI 0 "register_operand" "=r")
1225 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1226 (minus:DI (const_int 56)
1229 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1235 [(set_attr "type" "shift")])
1238 [(set (match_operand:DI 0 "register_operand" "=r")
1240 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1241 (const_int 2147483647))
1242 (minus:DI (const_int 56)
1245 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1251 [(set_attr "type" "shift")])
1254 [(set (match_operand:DI 0 "register_operand" "=r")
1256 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1258 (minus:DI (const_int 56)
1261 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1267 [(set_attr "type" "shift")])
1269 ;; This converts an extXl into an extXh with an appropriate adjustment
1270 ;; to the address calculation.
1273 ;; [(set (match_operand:DI 0 "register_operand" "")
1274 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1275 ;; (match_operand:DI 2 "mode_width_operand" "")
1276 ;; (ashift:DI (match_operand:DI 3 "" "")
1278 ;; (match_operand:DI 4 "const_int_operand" "")))
1279 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1280 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1281 ;; [(set (match_dup 5) (match_dup 6))
1282 ;; (set (match_dup 0)
1283 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1284 ;; (ashift:DI (plus:DI (match_dup 5)
1290 ;; operands[6] = plus_constant (operands[3],
1291 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1292 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1296 [(set (match_operand:DI 0 "register_operand" "=r")
1297 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1298 (match_operand:DI 2 "mul8_operand" "I")))]
1301 [(set_attr "type" "shift")])
1304 [(set (match_operand:DI 0 "register_operand" "=r")
1305 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1306 (match_operand:DI 2 "mul8_operand" "I")))]
1309 [(set_attr "type" "shift")])
1312 [(set (match_operand:DI 0 "register_operand" "=r")
1313 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1314 (match_operand:DI 2 "mul8_operand" "I")))]
1317 [(set_attr "type" "shift")])
1320 [(set (match_operand:DI 0 "register_operand" "=r")
1321 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1322 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1326 [(set_attr "type" "shift")])
1329 [(set (match_operand:DI 0 "register_operand" "=r")
1330 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1331 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1335 [(set_attr "type" "shift")])
1338 [(set (match_operand:DI 0 "register_operand" "=r")
1339 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1340 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1344 [(set_attr "type" "shift")])
1346 ;; We do not include the insXh insns because they are complex to express
1347 ;; and it does not appear that we would ever want to generate them.
1350 [(set (match_operand:DI 0 "register_operand" "=r")
1351 (and:DI (not:DI (ashift:DI
1352 (match_operand:DI 2 "mode_mask_operand" "n")
1354 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1356 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1359 [(set_attr "type" "shift")])
1361 ;; We do not include the mskXh insns because it does not appear we would ever
1364 ;; Floating-point operations. All the double-precision insns can extend
1365 ;; from single, so indicate that. The exception are the ones that simply
1366 ;; play with the sign bits; it's not clear what to do there.
1368 (define_insn "abssf2"
1369 [(set (match_operand:SF 0 "register_operand" "=f")
1370 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1373 [(set_attr "type" "fcpys")])
1375 (define_insn "absdf2"
1376 [(set (match_operand:DF 0 "register_operand" "=f")
1377 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1380 [(set_attr "type" "fcpys")])
1382 (define_insn "negsf2"
1383 [(set (match_operand:SF 0 "register_operand" "=f")
1384 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1387 [(set_attr "type" "fadd")])
1389 (define_insn "negdf2"
1390 [(set (match_operand:DF 0 "register_operand" "=f")
1391 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1394 [(set_attr "type" "fadd")])
1397 [(set (match_operand:SF 0 "register_operand" "=&f")
1398 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1399 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1400 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1401 "add%,%)%& %R1,%R2,%0"
1402 [(set_attr "type" "fadd")
1403 (set_attr "trap" "yes")])
1405 (define_insn "addsf3"
1406 [(set (match_operand:SF 0 "register_operand" "=f")
1407 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1408 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1410 "add%,%)%& %R1,%R2,%0"
1411 [(set_attr "type" "fadd")
1412 (set_attr "trap" "yes")])
1415 [(set (match_operand:DF 0 "register_operand" "=&f")
1416 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1417 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1418 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1419 "add%-%)%& %R1,%R2,%0"
1420 [(set_attr "type" "fadd")
1421 (set_attr "trap" "yes")])
1423 (define_insn "adddf3"
1424 [(set (match_operand:DF 0 "register_operand" "=f")
1425 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1426 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1428 "add%-%)%& %R1,%R2,%0"
1429 [(set_attr "type" "fadd")
1430 (set_attr "trap" "yes")])
1433 [(set (match_operand:DF 0 "register_operand" "=f")
1434 (plus:DF (float_extend:DF
1435 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1436 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1437 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1438 "add%-%)%& %R1,%R2,%0"
1439 [(set_attr "type" "fadd")
1440 (set_attr "trap" "yes")])
1443 [(set (match_operand:DF 0 "register_operand" "=f")
1444 (plus:DF (float_extend:DF
1445 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1447 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1448 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1449 "add%-%)%& %R1,%R2,%0"
1450 [(set_attr "type" "fadd")
1451 (set_attr "trap" "yes")])
1453 (define_insn "fix_truncdfdi2"
1454 [(set (match_operand:DI 0 "register_operand" "=f")
1455 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1458 [(set_attr "type" "fadd")])
1460 (define_insn "fix_truncsfdi2"
1461 [(set (match_operand:DI 0 "register_operand" "=f")
1462 (fix:DI (float_extend:DF
1463 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1466 [(set_attr "type" "fadd")])
1468 (define_insn "floatdisf2"
1469 [(set (match_operand:SF 0 "register_operand" "=f")
1470 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1473 [(set_attr "type" "fadd")
1474 (set_attr "trap" "yes")])
1477 [(set (match_operand:DF 0 "register_operand" "=&f")
1478 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1479 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1481 [(set_attr "type" "fadd")
1482 (set_attr "trap" "yes")])
1484 (define_insn "floatdidf2"
1485 [(set (match_operand:DF 0 "register_operand" "=f")
1486 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1489 [(set_attr "type" "fadd")
1490 (set_attr "trap" "yes")])
1492 (define_expand "extendsfdf2"
1493 [(use (match_operand:DF 0 "register_operand" ""))
1494 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
1498 if (alpha_tp == ALPHA_TP_INSN)
1499 emit_insn (gen_extendsfdf2_tp (operands[0],
1500 force_reg (SFmode, operands[1])));
1502 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
1507 (define_insn "extendsfdf2_tp"
1508 [(set (match_operand:DF 0 "register_operand" "=&f")
1509 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
1510 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1512 [(set_attr "type" "fadd")
1513 (set_attr "trap" "yes")])
1515 (define_insn "extendsfdf2_no_tp"
1516 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
1517 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
1518 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1523 [(set_attr "type" "fcpys,ld,st")
1524 (set_attr "trap" "yes")])
1527 [(set (match_operand:SF 0 "register_operand" "=&f")
1528 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1529 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1530 "cvt%-%,%)%& %R1,%0"
1531 [(set_attr "type" "fadd")
1532 (set_attr "trap" "yes")])
1534 (define_insn "truncdfsf2"
1535 [(set (match_operand:SF 0 "register_operand" "=f")
1536 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1538 "cvt%-%,%)%& %R1,%0"
1539 [(set_attr "type" "fadd")
1540 (set_attr "trap" "yes")])
1543 [(set (match_operand:SF 0 "register_operand" "=&f")
1544 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1545 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1546 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1547 "div%,%)%& %R1,%R2,%0"
1548 [(set_attr "type" "fdivs")
1549 (set_attr "trap" "yes")])
1551 (define_insn "divsf3"
1552 [(set (match_operand:SF 0 "register_operand" "=f")
1553 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1554 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1556 "div%,%)%& %R1,%R2,%0"
1557 [(set_attr "type" "fdivs")
1558 (set_attr "trap" "yes")])
1561 [(set (match_operand:DF 0 "register_operand" "=&f")
1562 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1563 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1564 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1565 "div%-%)%& %R1,%R2,%0"
1566 [(set_attr "type" "fdivt")
1567 (set_attr "trap" "yes")])
1569 (define_insn "divdf3"
1570 [(set (match_operand:DF 0 "register_operand" "=f")
1571 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1572 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1574 "div%-%)%& %R1,%R2,%0"
1575 [(set_attr "type" "fdivt")
1576 (set_attr "trap" "yes")])
1579 [(set (match_operand:DF 0 "register_operand" "=f")
1580 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1581 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1582 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1583 "div%-%)%& %R1,%R2,%0"
1584 [(set_attr "type" "fdivt")
1585 (set_attr "trap" "yes")])
1588 [(set (match_operand:DF 0 "register_operand" "=f")
1589 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1591 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1592 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1593 "div%-%)%& %R1,%R2,%0"
1594 [(set_attr "type" "fdivt")
1595 (set_attr "trap" "yes")])
1598 [(set (match_operand:DF 0 "register_operand" "=f")
1599 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1600 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1601 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1602 "div%-%)%& %R1,%R2,%0"
1603 [(set_attr "type" "fdivt")
1604 (set_attr "trap" "yes")])
1607 [(set (match_operand:SF 0 "register_operand" "=&f")
1608 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1609 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1610 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1611 "mul%,%)%& %R1,%R2,%0"
1612 [(set_attr "type" "fmul")
1613 (set_attr "trap" "yes")])
1615 (define_insn "mulsf3"
1616 [(set (match_operand:SF 0 "register_operand" "=f")
1617 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1618 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1620 "mul%,%)%& %R1,%R2,%0"
1621 [(set_attr "type" "fmul")
1622 (set_attr "trap" "yes")])
1625 [(set (match_operand:DF 0 "register_operand" "=&f")
1626 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1627 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1628 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1629 "mul%-%)%& %R1,%R2,%0"
1630 [(set_attr "type" "fmul")
1631 (set_attr "trap" "yes")])
1633 (define_insn "muldf3"
1634 [(set (match_operand:DF 0 "register_operand" "=f")
1635 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1636 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1638 "mul%-%)%& %R1,%R2,%0"
1639 [(set_attr "type" "fmul")
1640 (set_attr "trap" "yes")])
1643 [(set (match_operand:DF 0 "register_operand" "=f")
1644 (mult:DF (float_extend:DF
1645 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1646 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1647 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1648 "mul%-%)%& %R1,%R2,%0"
1649 [(set_attr "type" "fmul")
1650 (set_attr "trap" "yes")])
1653 [(set (match_operand:DF 0 "register_operand" "=f")
1654 (mult:DF (float_extend:DF
1655 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1657 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1658 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1659 "mul%-%)%& %R1,%R2,%0"
1660 [(set_attr "type" "fmul")
1661 (set_attr "trap" "yes")])
1664 [(set (match_operand:SF 0 "register_operand" "=&f")
1665 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1666 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1667 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1668 "sub%,%)%& %R1,%R2,%0"
1669 [(set_attr "type" "fadd")
1670 (set_attr "trap" "yes")])
1672 (define_insn "subsf3"
1673 [(set (match_operand:SF 0 "register_operand" "=f")
1674 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1675 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1677 "sub%,%)%& %R1,%R2,%0"
1678 [(set_attr "type" "fadd")
1679 (set_attr "trap" "yes")])
1682 [(set (match_operand:DF 0 "register_operand" "=&f")
1683 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1684 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1685 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1686 "sub%-%)%& %R1,%R2,%0"
1687 [(set_attr "type" "fadd")
1688 (set_attr "trap" "yes")])
1690 (define_insn "subdf3"
1691 [(set (match_operand:DF 0 "register_operand" "=f")
1692 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1693 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1695 "sub%-%)%& %R1,%R2,%0"
1696 [(set_attr "type" "fadd")
1697 (set_attr "trap" "yes")])
1700 [(set (match_operand:DF 0 "register_operand" "=f")
1701 (minus:DF (float_extend:DF
1702 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1703 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1704 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1705 "sub%-%)%& %R1,%R2,%0"
1706 [(set_attr "type" "fadd")
1707 (set_attr "trap" "yes")])
1710 [(set (match_operand:DF 0 "register_operand" "=f")
1711 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1713 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1714 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1715 "sub%-%)%& %R1,%R2,%0"
1716 [(set_attr "type" "fadd")
1717 (set_attr "trap" "yes")])
1720 [(set (match_operand:DF 0 "register_operand" "=f")
1721 (minus:DF (float_extend:DF
1722 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1724 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1725 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1726 "sub%-%)%& %R1,%R2,%0"
1727 [(set_attr "type" "fadd")
1728 (set_attr "trap" "yes")])
1730 ;; Next are all the integer comparisons, and conditional moves and branches
1731 ;; and some of the related define_expand's and define_split's.
1734 [(set (match_operand:DI 0 "register_operand" "=r")
1735 (match_operator:DI 1 "alpha_comparison_operator"
1736 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1737 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
1740 [(set_attr "type" "icmp")])
1743 [(set (match_operand:DI 0 "register_operand" "=r")
1744 (match_operator:DI 1 "alpha_swapped_comparison_operator"
1745 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
1746 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
1749 [(set_attr "type" "icmp")])
1751 ;; This pattern exists so conditional moves of SImode values are handled.
1752 ;; Comparisons are still done in DImode though.
1755 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1757 (match_operator 2 "signed_comparison_operator"
1758 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1759 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1760 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1761 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1762 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1768 [(set_attr "type" "cmov")])
1771 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1773 (match_operator 2 "signed_comparison_operator"
1774 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1775 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1776 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1777 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1778 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1784 [(set_attr "type" "cmov")])
1787 [(set (match_operand:DI 0 "register_operand" "=r,r")
1789 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1793 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1794 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1799 [(set_attr "type" "cmov")])
1802 [(set (match_operand:DI 0 "register_operand" "=r,r")
1804 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1808 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1809 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1814 [(set_attr "type" "cmov")])
1816 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
1817 ;; arms constant is a single insn, so it won't try to form it if combine
1818 ;; knows they are really two insns. This occurs in divides by powers
1822 [(set (match_operand:DI 0 "register_operand" "=r")
1824 (match_operator 2 "signed_comparison_operator"
1825 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
1827 (plus:DI (match_dup 0)
1828 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1830 (clobber (match_scratch:DI 4 "=&r"))]
1832 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0"
1833 [(set_attr "type" "cmov")])
1836 [(set (match_operand:DI 0 "register_operand" "")
1838 (match_operator 2 "signed_comparison_operator"
1839 [(match_operand:DI 3 "reg_or_0_operand" "")
1841 (plus:DI (match_dup 0)
1842 (match_operand:DI 1 "reg_or_8bit_operand" ""))
1844 (clobber (match_operand:DI 4 "register_operand" ""))]
1846 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
1847 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
1850 (match_dup 4) (match_dup 0)))]
1855 [(set (match_operand:DI 0 "register_operand" "")
1857 (match_operator 1 "comparison_operator"
1858 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1860 (match_operand:DI 3 "const_int_operand" ""))
1862 (match_operand:DI 4 "reg_or_8bit_operand" "")
1863 (match_operand:DI 5 "reg_or_8bit_operand" "")))
1864 (clobber (match_operand:DI 6 "register_operand" ""))])]
1865 "INTVAL (operands[3]) != 0"
1867 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1869 (if_then_else:DI (match_op_dup 1
1870 [(zero_extract:DI (match_dup 6)
1878 ;; For ABS, we have two choices, depending on whether the input and output
1879 ;; registers are the same or not.
1880 (define_expand "absdi2"
1881 [(set (match_operand:DI 0 "register_operand" "")
1882 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1885 { if (rtx_equal_p (operands[0], operands[1]))
1886 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
1888 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
1893 (define_expand "absdi2_same"
1894 [(set (match_operand:DI 1 "register_operand" "")
1895 (neg:DI (match_operand:DI 0 "register_operand" "")))
1897 (if_then_else:DI (ge (match_dup 0) (const_int 0))
1903 (define_expand "absdi2_diff"
1904 [(set (match_operand:DI 0 "register_operand" "")
1905 (neg:DI (match_operand:DI 1 "register_operand" "")))
1907 (if_then_else:DI (lt (match_dup 1) (const_int 0))
1914 [(set (match_operand:DI 0 "register_operand" "")
1915 (abs:DI (match_dup 0)))
1916 (clobber (match_operand:DI 2 "register_operand" ""))]
1918 [(set (match_dup 1) (neg:DI (match_dup 0)))
1919 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
1920 (match_dup 0) (match_dup 1)))]
1924 [(set (match_operand:DI 0 "register_operand" "")
1925 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1926 "! rtx_equal_p (operands[0], operands[1])"
1927 [(set (match_dup 0) (neg:DI (match_dup 1)))
1928 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
1929 (match_dup 0) (match_dup 1)))]
1933 [(set (match_operand:DI 0 "register_operand" "")
1934 (neg:DI (abs:DI (match_dup 0))))
1935 (clobber (match_operand:DI 2 "register_operand" ""))]
1937 [(set (match_dup 1) (neg:DI (match_dup 0)))
1938 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
1939 (match_dup 0) (match_dup 1)))]
1943 [(set (match_operand:DI 0 "register_operand" "")
1944 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
1945 "! rtx_equal_p (operands[0], operands[1])"
1946 [(set (match_dup 0) (neg:DI (match_dup 1)))
1947 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
1948 (match_dup 0) (match_dup 1)))]
1951 (define_expand "smaxdi3"
1953 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
1954 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1955 (set (match_operand:DI 0 "register_operand" "")
1956 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1957 (match_dup 1) (match_dup 2)))]
1960 { operands[3] = gen_reg_rtx (DImode);
1964 [(set (match_operand:DI 0 "register_operand" "")
1965 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1966 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1967 (clobber (match_operand:DI 3 "register_operand" ""))]
1968 "operands[2] != const0_rtx"
1969 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
1970 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1971 (match_dup 1) (match_dup 2)))]
1975 [(set (match_operand:DI 0 "register_operand" "=r")
1976 (smax:DI (match_operand:DI 1 "register_operand" "0")
1980 [(set_attr "type" "cmov")])
1982 (define_expand "smindi3"
1984 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
1985 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1986 (set (match_operand:DI 0 "register_operand" "")
1987 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1988 (match_dup 1) (match_dup 2)))]
1991 { operands[3] = gen_reg_rtx (DImode);
1995 [(set (match_operand:DI 0 "register_operand" "")
1996 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1997 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1998 (clobber (match_operand:DI 3 "register_operand" ""))]
1999 "operands[2] != const0_rtx"
2000 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2001 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2002 (match_dup 1) (match_dup 2)))]
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2007 (smin:DI (match_operand:DI 1 "register_operand" "0")
2011 [(set_attr "type" "cmov")])
2013 (define_expand "umaxdi3"
2015 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2016 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2017 (set (match_operand:DI 0 "register_operand" "")
2018 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2019 (match_dup 1) (match_dup 2)))]
2022 { operands[3] = gen_reg_rtx (DImode);
2026 [(set (match_operand:DI 0 "register_operand" "")
2027 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2028 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2029 (clobber (match_operand:DI 3 "register_operand" ""))]
2030 "operands[2] != const0_rtx"
2031 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2032 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2033 (match_dup 1) (match_dup 2)))]
2036 (define_expand "umindi3"
2038 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2039 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2040 (set (match_operand:DI 0 "register_operand" "")
2041 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2042 (match_dup 1) (match_dup 2)))]
2045 { operands[3] = gen_reg_rtx (DImode);
2049 [(set (match_operand:DI 0 "register_operand" "")
2050 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2051 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2052 (clobber (match_operand:DI 3 "register_operand" ""))]
2053 "operands[2] != const0_rtx"
2054 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2055 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2056 (match_dup 1) (match_dup 2)))]
2062 (match_operator 1 "signed_comparison_operator"
2063 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2065 (label_ref (match_operand 0 "" ""))
2069 [(set_attr "type" "ibr")])
2074 (match_operator 1 "signed_comparison_operator"
2076 (match_operand:DI 2 "register_operand" "r")])
2077 (label_ref (match_operand 0 "" ""))
2081 [(set_attr "type" "ibr")])
2086 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2090 (label_ref (match_operand 0 "" ""))
2094 [(set_attr "type" "ibr")])
2099 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2103 (label_ref (match_operand 0 "" ""))
2107 [(set_attr "type" "ibr")])
2113 (match_operator 1 "comparison_operator"
2114 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2116 (match_operand:DI 3 "const_int_operand" ""))
2118 (label_ref (match_operand 0 "" ""))
2120 (clobber (match_operand:DI 4 "register_operand" ""))])]
2121 "INTVAL (operands[3]) != 0"
2123 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2125 (if_then_else (match_op_dup 1
2126 [(zero_extract:DI (match_dup 4)
2130 (label_ref (match_dup 0))
2134 ;; The following are the corresponding floating-point insns. Recall
2135 ;; we need to have variants that expand the arguments from SF mode
2139 [(set (match_operand:DF 0 "register_operand" "=&f")
2140 (match_operator:DF 1 "alpha_comparison_operator"
2141 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2142 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2143 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2144 "cmp%-%C1%' %R2,%R3,%0"
2145 [(set_attr "type" "fadd")
2146 (set_attr "trap" "yes")])
2149 [(set (match_operand:DF 0 "register_operand" "=f")
2150 (match_operator:DF 1 "alpha_comparison_operator"
2151 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2152 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2153 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2154 "cmp%-%C1%' %R2,%R3,%0"
2155 [(set_attr "type" "fadd")
2156 (set_attr "trap" "yes")])
2159 [(set (match_operand:DF 0 "register_operand" "=f")
2160 (match_operator:DF 1 "alpha_comparison_operator"
2162 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2163 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2164 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2165 "cmp%-%C1%' %R2,%R3,%0"
2166 [(set_attr "type" "fadd")
2167 (set_attr "trap" "yes")])
2170 [(set (match_operand:DF 0 "register_operand" "=f")
2171 (match_operator:DF 1 "alpha_comparison_operator"
2172 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2174 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2175 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2176 "cmp%-%C1%' %R2,%R3,%0"
2177 [(set_attr "type" "fadd")
2178 (set_attr "trap" "yes")])
2181 [(set (match_operand:DF 0 "register_operand" "=f")
2182 (match_operator:DF 1 "alpha_comparison_operator"
2184 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2186 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2187 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2188 "cmp%-%C1%' %R2,%R3,%0"
2189 [(set_attr "type" "fadd")
2190 (set_attr "trap" "yes")])
2193 [(set (match_operand:DF 0 "register_operand" "=&f,f")
2195 (match_operator 3 "signed_comparison_operator"
2196 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2197 (match_operand:DF 2 "fp0_operand" "G,G")])
2198 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2199 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2200 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2203 fcmov%D3 %R4,%R5,%0"
2204 [(set_attr "type" "fadd")])
2207 [(set (match_operand:DF 0 "register_operand" "=f,f")
2209 (match_operator 3 "signed_comparison_operator"
2210 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2211 (match_operand:DF 2 "fp0_operand" "G,G")])
2212 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2213 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2214 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2217 fcmov%D3 %R4,%R5,%0"
2218 [(set_attr "type" "fadd")])
2221 [(set (match_operand:SF 0 "register_operand" "=&f,f")
2223 (match_operator 3 "signed_comparison_operator"
2224 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2225 (match_operand:DF 2 "fp0_operand" "G,G")])
2226 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2227 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2228 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2231 fcmov%D3 %R4,%R5,%0"
2232 [(set_attr "type" "fadd")])
2235 [(set (match_operand:SF 0 "register_operand" "=f,f")
2237 (match_operator 3 "signed_comparison_operator"
2238 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2239 (match_operand:DF 2 "fp0_operand" "G,G")])
2240 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2241 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2242 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2245 fcmov%D3 %R4,%R5,%0"
2246 [(set_attr "type" "fadd")])
2249 [(set (match_operand:DF 0 "register_operand" "=f,f")
2251 (match_operator 3 "signed_comparison_operator"
2252 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2253 (match_operand:DF 2 "fp0_operand" "G,G")])
2254 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2255 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2256 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2259 fcmov%D3 %R4,%R5,%0"
2260 [(set_attr "type" "fadd")])
2263 [(set (match_operand:DF 0 "register_operand" "=f,f")
2265 (match_operator 3 "signed_comparison_operator"
2267 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2268 (match_operand:DF 2 "fp0_operand" "G,G")])
2269 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2270 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2271 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2274 fcmov%D3 %R4,%R5,%0"
2275 [(set_attr "type" "fadd")])
2278 [(set (match_operand:SF 0 "register_operand" "=f,f")
2280 (match_operator 3 "signed_comparison_operator"
2282 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2283 (match_operand:DF 2 "fp0_operand" "G,G")])
2284 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2285 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2286 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2289 fcmov%D3 %R4,%R5,%0"
2290 [(set_attr "type" "fadd")])
2293 [(set (match_operand:DF 0 "register_operand" "=f,f")
2295 (match_operator 3 "signed_comparison_operator"
2297 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2298 (match_operand:DF 2 "fp0_operand" "G,G")])
2299 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2300 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2301 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2304 fcmov%D3 %R4,%R5,%0"
2305 [(set_attr "type" "fadd")])
2307 (define_expand "maxdf3"
2309 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2310 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2311 (set (match_operand:DF 0 "register_operand" "")
2312 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2313 (match_dup 1) (match_dup 2)))]
2316 { operands[3] = gen_reg_rtx (DFmode);
2317 operands[4] = CONST0_RTX (DFmode);
2320 (define_expand "mindf3"
2322 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2323 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2324 (set (match_operand:DF 0 "register_operand" "")
2325 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2326 (match_dup 1) (match_dup 2)))]
2329 { operands[3] = gen_reg_rtx (DFmode);
2330 operands[4] = CONST0_RTX (DFmode);
2333 (define_expand "maxsf3"
2335 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2336 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2337 (set (match_operand:SF 0 "register_operand" "")
2338 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2339 (match_dup 1) (match_dup 2)))]
2342 { operands[3] = gen_reg_rtx (DFmode);
2343 operands[4] = CONST0_RTX (DFmode);
2346 (define_expand "minsf3"
2348 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2349 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2350 (set (match_operand:SF 0 "register_operand" "")
2351 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2352 (match_dup 1) (match_dup 2)))]
2355 { operands[3] = gen_reg_rtx (DFmode);
2356 operands[4] = CONST0_RTX (DFmode);
2362 (match_operator 1 "signed_comparison_operator"
2363 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2364 (match_operand:DF 3 "fp0_operand" "G")])
2365 (label_ref (match_operand 0 "" ""))
2369 [(set_attr "type" "fbr")])
2374 (match_operator 1 "signed_comparison_operator"
2376 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2377 (match_operand:DF 3 "fp0_operand" "G")])
2378 (label_ref (match_operand 0 "" ""))
2382 [(set_attr "type" "fbr")])
2384 ;; These are the main define_expand's used to make conditional branches
2387 (define_expand "cmpdf"
2388 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
2389 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
2393 alpha_compare_op0 = operands[0];
2394 alpha_compare_op1 = operands[1];
2395 alpha_compare_fp_p = 1;
2399 (define_expand "cmpdi"
2400 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
2401 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
2405 alpha_compare_op0 = operands[0];
2406 alpha_compare_op1 = operands[1];
2407 alpha_compare_fp_p = 0;
2411 (define_expand "beq"
2412 [(set (match_dup 1) (match_dup 2))
2414 (if_then_else (match_dup 3)
2415 (label_ref (match_operand 0 "" ""))
2420 enum machine_mode mode;
2421 enum rtx_code compare_code, branch_code;
2423 if (alpha_compare_fp_p)
2424 mode = DFmode, compare_code = EQ, branch_code = NE;
2427 mode = DImode, compare_code = MINUS, branch_code = EQ;
2428 if (GET_CODE (alpha_compare_op1) == CONST_INT)
2430 compare_code = PLUS;
2431 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
2435 operands[1] = gen_reg_rtx (mode);
2436 operands[2] = gen_rtx (compare_code, mode,
2437 alpha_compare_op0, alpha_compare_op1);
2438 operands[3] = gen_rtx (branch_code, VOIDmode,
2439 operands[1], CONST0_RTX (mode));
2442 (define_expand "bne"
2443 [(set (match_dup 1) (match_dup 2))
2445 (if_then_else (match_dup 3)
2446 (label_ref (match_operand 0 "" ""))
2451 enum machine_mode mode;
2452 enum rtx_code compare_code, branch_code;
2454 if (alpha_compare_fp_p)
2455 mode = DFmode, compare_code = EQ, branch_code = EQ;
2458 mode = DImode, compare_code = MINUS, branch_code = NE;
2459 if (GET_CODE (alpha_compare_op1) == CONST_INT)
2461 compare_code = PLUS;
2462 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
2466 operands[1] = gen_reg_rtx (mode);
2467 operands[2] = gen_rtx (compare_code, mode,
2468 alpha_compare_op0, alpha_compare_op1);
2469 operands[3] = gen_rtx (branch_code, VOIDmode,
2470 operands[1], CONST0_RTX (mode));
2473 (define_expand "blt"
2474 [(set (match_dup 1) (match_dup 2))
2476 (if_then_else (match_dup 3)
2477 (label_ref (match_operand 0 "" ""))
2482 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
2483 operands[1] = gen_reg_rtx (mode);
2484 operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
2485 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
2488 (define_expand "ble"
2489 [(set (match_dup 1) (match_dup 2))
2491 (if_then_else (match_dup 3)
2492 (label_ref (match_operand 0 "" ""))
2497 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
2498 operands[1] = gen_reg_rtx (mode);
2499 operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
2500 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
2503 (define_expand "bgt"
2504 [(set (match_dup 1) (match_dup 2))
2506 (if_then_else (match_dup 3)
2507 (label_ref (match_operand 0 "" ""))
2512 if (alpha_compare_fp_p)
2514 operands[1] = gen_reg_rtx (DFmode);
2515 operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
2516 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2520 operands[1] = gen_reg_rtx (DImode);
2521 operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2522 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2526 (define_expand "bge"
2527 [(set (match_dup 1) (match_dup 2))
2529 (if_then_else (match_dup 3)
2530 (label_ref (match_operand 0 "" ""))
2535 if (alpha_compare_fp_p)
2537 operands[1] = gen_reg_rtx (DFmode);
2538 operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
2539 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2543 operands[1] = gen_reg_rtx (DImode);
2544 operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2545 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2549 (define_expand "bltu"
2550 [(set (match_dup 1) (match_dup 2))
2552 (if_then_else (match_dup 3)
2553 (label_ref (match_operand 0 "" ""))
2558 operands[1] = gen_reg_rtx (DImode);
2559 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2560 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2563 (define_expand "bleu"
2564 [(set (match_dup 1) (match_dup 2))
2566 (if_then_else (match_dup 3)
2567 (label_ref (match_operand 0 "" ""))
2572 operands[1] = gen_reg_rtx (DImode);
2573 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2574 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2577 (define_expand "bgtu"
2578 [(set (match_dup 1) (match_dup 2))
2580 (if_then_else (match_dup 3)
2581 (label_ref (match_operand 0 "" ""))
2586 operands[1] = gen_reg_rtx (DImode);
2587 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2588 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2591 (define_expand "bgeu"
2592 [(set (match_dup 1) (match_dup 2))
2594 (if_then_else (match_dup 3)
2595 (label_ref (match_operand 0 "" ""))
2600 operands[1] = gen_reg_rtx (DImode);
2601 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2602 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2605 (define_expand "seq"
2606 [(set (match_operand:DI 0 "register_operand" "")
2611 if (alpha_compare_fp_p)
2614 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2617 (define_expand "sne"
2618 [(set (match_operand:DI 0 "register_operand" "")
2620 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
2624 if (alpha_compare_fp_p)
2627 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2630 (define_expand "slt"
2631 [(set (match_operand:DI 0 "register_operand" "")
2636 if (alpha_compare_fp_p)
2639 operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2642 (define_expand "sle"
2643 [(set (match_operand:DI 0 "register_operand" "")
2648 if (alpha_compare_fp_p)
2651 operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2654 (define_expand "sgt"
2655 [(set (match_operand:DI 0 "register_operand" "")
2660 if (alpha_compare_fp_p)
2663 operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
2667 (define_expand "sge"
2668 [(set (match_operand:DI 0 "register_operand" "")
2673 if (alpha_compare_fp_p)
2676 operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
2680 (define_expand "sltu"
2681 [(set (match_operand:DI 0 "register_operand" "")
2686 if (alpha_compare_fp_p)
2689 operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2692 (define_expand "sleu"
2693 [(set (match_operand:DI 0 "register_operand" "")
2698 if (alpha_compare_fp_p)
2701 operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2704 (define_expand "sgtu"
2705 [(set (match_operand:DI 0 "register_operand" "")
2710 if (alpha_compare_fp_p)
2713 operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
2717 (define_expand "sgeu"
2718 [(set (match_operand:DI 0 "register_operand" "")
2723 if (alpha_compare_fp_p)
2726 operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
2730 ;; These are the main define_expand's used to make conditional moves.
2732 (define_expand "movsicc"
2733 [(set (match_operand:SI 0 "register_operand" "")
2734 (if_then_else:DI (match_operand 1 "comparison_operator" "")
2735 (match_operand:SI 2 "reg_or_8bit_operand" "")
2736 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
2740 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
2744 (define_expand "movdicc"
2745 [(set (match_operand:DI 0 "register_operand" "")
2746 (if_then_else:DI (match_operand 1 "comparison_operator" "")
2747 (match_operand:DI 2 "reg_or_8bit_operand" "")
2748 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
2752 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
2756 (define_expand "movsfcc"
2757 [(set (match_operand:SF 0 "register_operand" "")
2758 (if_then_else:SF (match_operand 1 "comparison_operator" "")
2759 (match_operand:SF 2 "reg_or_8bit_operand" "")
2760 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
2764 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
2768 (define_expand "movdfcc"
2769 [(set (match_operand:DF 0 "register_operand" "")
2770 (if_then_else:DF (match_operand 1 "comparison_operator" "")
2771 (match_operand:DF 2 "reg_or_8bit_operand" "")
2772 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
2776 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
2780 ;; These define_split definitions are used in cases when comparisons have
2781 ;; not be stated in the correct way and we need to reverse the second
2782 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
2783 ;; comparison that tests the result being reversed. We have one define_split
2784 ;; for each use of a comparison. They do not match valid insns and need
2785 ;; not generate valid insns.
2787 ;; We can also handle equality comparisons (and inequality comparisons in
2788 ;; cases where the resulting add cannot overflow) by doing an add followed by
2789 ;; a comparison with zero. This is faster since the addition takes one
2790 ;; less cycle than a compare when feeding into a conditional move.
2791 ;; For this case, we also have an SImode pattern since we can merge the add
2792 ;; and sign extend and the order doesn't matter.
2794 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2795 ;; operation could have been generated.
2798 [(set (match_operand:DI 0 "register_operand" "")
2800 (match_operator 1 "comparison_operator"
2801 [(match_operand:DI 2 "reg_or_0_operand" "")
2802 (match_operand:DI 3 "reg_or_cint_operand" "")])
2803 (match_operand:DI 4 "reg_or_cint_operand" "")
2804 (match_operand:DI 5 "reg_or_cint_operand" "")))
2805 (clobber (match_operand:DI 6 "register_operand" ""))]
2806 "operands[3] != const0_rtx"
2807 [(set (match_dup 6) (match_dup 7))
2809 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2811 { enum rtx_code code = GET_CODE (operands[1]);
2812 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2814 /* If we are comparing for equality with a constant and that constant
2815 appears in the arm when the register equals the constant, use the
2816 register since that is more likely to match (and to produce better code
2819 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
2820 && rtx_equal_p (operands[4], operands[3]))
2821 operands[4] = operands[2];
2823 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
2824 && rtx_equal_p (operands[5], operands[3]))
2825 operands[5] = operands[2];
2827 if (code == NE || code == EQ
2828 || (extended_count (operands[2], DImode, unsignedp) >= 1
2829 && extended_count (operands[3], DImode, unsignedp) >= 1))
2831 if (GET_CODE (operands[3]) == CONST_INT)
2832 operands[7] = gen_rtx (PLUS, DImode, operands[2],
2833 GEN_INT (- INTVAL (operands[3])));
2835 operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2837 operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
2840 else if (code == EQ || code == LE || code == LT
2841 || code == LEU || code == LTU)
2843 operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
2844 operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
2848 operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
2850 operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
2855 [(set (match_operand:DI 0 "register_operand" "")
2857 (match_operator 1 "comparison_operator"
2858 [(match_operand:SI 2 "reg_or_0_operand" "")
2859 (match_operand:SI 3 "reg_or_cint_operand" "")])
2860 (match_operand:DI 4 "reg_or_8bit_operand" "")
2861 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2862 (clobber (match_operand:DI 6 "register_operand" ""))]
2863 "operands[3] != const0_rtx
2864 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2865 [(set (match_dup 6) (match_dup 7))
2867 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2869 { enum rtx_code code = GET_CODE (operands[1]);
2870 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2873 if ((code != NE && code != EQ
2874 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
2875 && extended_count (operands[3], DImode, unsignedp) >= 1)))
2878 if (GET_CODE (operands[3]) == CONST_INT)
2879 tem = gen_rtx (PLUS, SImode, operands[2],
2880 GEN_INT (- INTVAL (operands[3])));
2882 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2884 operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem);
2885 operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
2892 (match_operator 1 "comparison_operator"
2893 [(match_operand:DI 2 "reg_or_0_operand" "")
2894 (match_operand:DI 3 "reg_or_cint_operand" "")])
2895 (label_ref (match_operand 0 "" ""))
2897 (clobber (match_operand:DI 4 "register_operand" ""))]
2898 "operands[3] != const0_rtx"
2899 [(set (match_dup 4) (match_dup 5))
2900 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2902 { enum rtx_code code = GET_CODE (operands[1]);
2903 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2905 if (code == NE || code == EQ
2906 || (extended_count (operands[2], DImode, unsignedp) >= 1
2907 && extended_count (operands[3], DImode, unsignedp) >= 1))
2909 if (GET_CODE (operands[3]) == CONST_INT)
2910 operands[5] = gen_rtx (PLUS, DImode, operands[2],
2911 GEN_INT (- INTVAL (operands[3])));
2913 operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2915 operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
2918 else if (code == EQ || code == LE || code == LT
2919 || code == LEU || code == LTU)
2921 operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
2922 operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
2926 operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
2928 operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
2935 (match_operator 1 "comparison_operator"
2936 [(match_operand:SI 2 "reg_or_0_operand" "")
2937 (match_operand:SI 3 "const_int_operand" "")])
2938 (label_ref (match_operand 0 "" ""))
2940 (clobber (match_operand:DI 4 "register_operand" ""))]
2941 "operands[3] != const0_rtx
2942 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2943 [(set (match_dup 4) (match_dup 5))
2944 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2948 if (GET_CODE (operands[3]) == CONST_INT)
2949 tem = gen_rtx (PLUS, SImode, operands[2],
2950 GEN_INT (- INTVAL (operands[3])));
2952 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2954 operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem);
2955 operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
2956 operands[4], const0_rtx);
2959 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
2960 ;; This eliminates one, and sometimes two, insns when the AND can be done
2963 [(set (match_operand:DI 0 "register_operand" "")
2964 (match_operator 1 "comparison_operator"
2965 [(match_operand:DI 2 "register_operand" "")
2966 (match_operand:DI 3 "const_int_operand" "")]))
2967 (clobber (match_operand:DI 4 "register_operand" ""))]
2968 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
2969 && (GET_CODE (operands[1]) == GTU
2970 || GET_CODE (operands[1]) == LEU
2971 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
2972 && extended_count (operands[2], DImode, 1) > 0))"
2973 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
2974 (set (match_dup 0) (match_dup 6))]
2977 operands[5] = GEN_INT (~ INTVAL (operands[3]));
2978 operands[6] = gen_rtx (((GET_CODE (operands[1]) == GTU
2979 || GET_CODE (operands[1]) == GT)
2981 DImode, operands[4], const0_rtx);
2984 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
2985 ;; work differently, so we have different patterns for each.
2987 (define_expand "call"
2988 [(use (match_operand:DI 0 "" ""))
2989 (use (match_operand 1 "" ""))
2990 (use (match_operand 2 "" ""))
2991 (use (match_operand 3 "" ""))]
2994 { if (TARGET_WINDOWS_NT)
2995 emit_call_insn (gen_call_nt (operands[0], operands[1]));
2996 else if (TARGET_OPEN_VMS)
2997 emit_call_insn (gen_call_vms (operands[0], operands[2]));
2999 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3004 (define_expand "call_osf"
3005 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3006 (match_operand 1 "" ""))
3007 (clobber (reg:DI 27))
3008 (clobber (reg:DI 26))])]
3011 { if (GET_CODE (operands[0]) != MEM)
3014 operands[0] = XEXP (operands[0], 0);
3016 if (GET_CODE (operands[0]) != SYMBOL_REF
3017 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3019 rtx tem = gen_rtx (REG, DImode, 27);
3020 emit_move_insn (tem, operands[0]);
3025 (define_expand "call_nt"
3026 [(parallel [(call (mem:DI (match_operand:DI 0 "" ""))
3027 (match_operand 1 "" ""))
3028 (clobber (reg:DI 26))])]
3031 { if (GET_CODE (operands[0]) != MEM)
3033 operands[0] = XEXP (operands[0], 0);
3035 if (GET_CODE (operands[1]) != SYMBOL_REF
3036 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3038 rtx tem = gen_rtx (REG, DImode, 27);
3039 emit_move_insn (tem, operands[1]);
3045 ;; call openvms/alpha
3046 ;; op 0: symbol ref for called function
3047 ;; op 1: next_arg_reg (argument information value for R25)
3049 (define_expand "call_vms"
3050 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3051 (match_operand 1 "" ""))
3055 (clobber (reg:DI 27))])]
3058 { if (GET_CODE (operands[0]) != MEM)
3061 operands[0] = XEXP (operands[0], 0);
3063 /* Always load AI with argument information, then handle symbolic and
3064 indirect call differently. Load RA and set operands[2] to PV in
3067 emit_move_insn (gen_rtx (REG, DImode, 25), operands[1]);
3068 if (GET_CODE (operands[0]) == SYMBOL_REF)
3070 extern char *savealloc ();
3071 char *symbol = XSTR (operands[0], 0);
3072 char *linksym = savealloc (strlen (symbol) + 5);
3075 alpha_need_linkage (symbol, 0);
3077 strcpy (linksym, symbol);
3078 strcat (linksym, \"..lk\");
3079 linkage = gen_rtx (SYMBOL_REF, Pmode, linksym);
3081 emit_move_insn (gen_rtx (REG, Pmode, 26), gen_rtx (MEM, Pmode, linkage));
3084 = validize_mem (gen_rtx (MEM, Pmode, plus_constant (linkage, 8)));
3088 emit_move_insn (gen_rtx (REG, Pmode, 26),
3089 gen_rtx (MEM, Pmode, plus_constant (operands[0], 8)));
3091 operands[2] = operands[0];
3096 (define_expand "call_value"
3097 [(use (match_operand 0 "" ""))
3098 (use (match_operand:DI 1 "" ""))
3099 (use (match_operand 2 "" ""))
3100 (use (match_operand 3 "" ""))
3101 (use (match_operand 4 "" ""))]
3104 { if (TARGET_WINDOWS_NT)
3105 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3106 else if (TARGET_OPEN_VMS)
3107 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3110 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3115 (define_expand "call_value_osf"
3116 [(parallel [(set (match_operand 0 "" "")
3117 (call (mem:DI (match_operand 1 "" ""))
3118 (match_operand 2 "" "")))
3119 (clobber (reg:DI 27))
3120 (clobber (reg:DI 26))])]
3123 { if (GET_CODE (operands[1]) != MEM)
3126 operands[1] = XEXP (operands[1], 0);
3128 if (GET_CODE (operands[1]) != SYMBOL_REF
3129 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3131 rtx tem = gen_rtx (REG, DImode, 27);
3132 emit_move_insn (tem, operands[1]);
3137 (define_expand "call_value_nt"
3138 [(parallel [(set (match_operand 0 "" "")
3139 (call (mem:DI (match_operand:DI 1 "" ""))
3140 (match_operand 2 "" "")))
3141 (clobber (reg:DI 26))])]
3144 { if (GET_CODE (operands[1]) != MEM)
3147 operands[1] = XEXP (operands[1], 0);
3148 if (GET_CODE (operands[1]) != SYMBOL_REF
3149 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3151 rtx tem = gen_rtx (REG, DImode, 27);
3152 emit_move_insn (tem, operands[1]);
3157 (define_expand "call_value_vms"
3158 [(parallel [(set (match_operand 0 "" "")
3159 (call (mem:DI (match_operand:DI 1 "" ""))
3160 (match_operand 2 "" "")))
3164 (clobber (reg:DI 27))])]
3167 { if (GET_CODE (operands[1]) != MEM)
3170 operands[1] = XEXP (operands[1], 0);
3172 /* Always load AI with argument information, then handle symbolic and
3173 indirect call differently. Load RA and set operands[3] to PV in
3176 emit_move_insn (gen_rtx (REG, DImode, 25), operands[2]);
3177 if (GET_CODE (operands[1]) == SYMBOL_REF)
3179 extern char *savealloc ();
3180 char *symbol = XSTR (operands[1], 0);
3181 char *linksym = savealloc (strlen (symbol) + 5);
3184 alpha_need_linkage (symbol, 0);
3185 strcpy (linksym, symbol);
3186 strcat (linksym, \"..lk\");
3187 linkage = gen_rtx (SYMBOL_REF, Pmode, linksym);
3189 emit_move_insn (gen_rtx (REG, Pmode, 26), gen_rtx (MEM, Pmode, linkage));
3192 = validize_mem (gen_rtx (MEM, Pmode, plus_constant (linkage, 8)));
3196 emit_move_insn (gen_rtx (REG, Pmode, 26),
3197 gen_rtx (MEM, Pmode, plus_constant (operands[1], 8)));
3199 operands[3] = operands[1];
3204 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3205 (match_operand 1 "" ""))
3206 (clobber (reg:DI 27))
3207 (clobber (reg:DI 26))]
3208 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && alpha_tp == ALPHA_TP_INSN"
3210 jsr $26,($27),0\;trapb\;ldgp $29,4($26)
3211 bsr $26,%0..ng\;trapb
3212 jsr $26,%0\;trapb\;ldgp $29,4($26)"
3213 [(set_attr "type" "jsr,jsr,ibr")])
3216 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3217 (match_operand 1 "" ""))
3218 (clobber (reg:DI 27))
3219 (clobber (reg:DI 26))]
3220 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3222 jsr $26,($27),0\;ldgp $29,0($26)
3224 jsr $26,%0\;ldgp $29,0($26)"
3225 [(set_attr "type" "jsr,jsr,ibr")])
3228 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3229 (match_operand 1 "" ""))
3230 (clobber (reg:DI 26))]
3235 [(set_attr "type" "jsr")])
3238 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3239 (match_operand 1 "" ""))
3240 (use (match_operand:DI 2 "general_operand" "r,m"))
3243 (clobber (reg:DI 27))]
3246 bis %2,%2,$27\;jsr $26,0\;ldq $27,0($29)
3247 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3248 [(set_attr "type" "jsr")])
3251 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3252 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3253 (match_operand 2 "" "")))
3254 (clobber (reg:DI 27))
3255 (clobber (reg:DI 26))]
3256 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && alpha_tp == ALPHA_TP_INSN"
3258 jsr $26,($27),0\;trapb\;ldgp $29,4($26)
3259 bsr $26,%1..ng\;trapb
3260 jsr $26,%1\;trapb\;ldgp $29,4($26)"
3261 [(set_attr "type" "jsr,jsr,ibr")])
3264 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3265 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3266 (match_operand 2 "" "")))
3267 (clobber (reg:DI 27))
3268 (clobber (reg:DI 26))]
3269 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3271 jsr $26,($27),0\;ldgp $29,0($26)
3273 jsr $26,%1\;ldgp $29,0($26)"
3274 [(set_attr "type" "jsr,jsr,ibr")])
3277 [(set (match_operand 0 "register_operand" "=rf,rf")
3278 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
3279 (match_operand 2 "" "")))
3280 (clobber (reg:DI 26))]
3285 [(set_attr "type" "jsr")])
3288 [(set (match_operand 0 "register_operand" "")
3289 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
3290 (match_operand 2 "" "")))
3291 (use (match_operand:DI 3 "general_operand" "r,m"))
3294 (clobber (reg:DI 27))]
3297 bis %3,%3,$27\;jsr $26,0\;ldq $27,0($29)
3298 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
3299 [(set_attr "type" "jsr")])
3301 ;; Call subroutine returning any type.
3303 (define_expand "untyped_call"
3304 [(parallel [(call (match_operand 0 "" "")
3306 (match_operand 1 "" "")
3307 (match_operand 2 "" "")])]
3313 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3315 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3317 rtx set = XVECEXP (operands[2], 0, i);
3318 emit_move_insn (SET_DEST (set), SET_SRC (set));
3321 /* The optimizer does not know that the call sets the function value
3322 registers we stored in the result block. We avoid problems by
3323 claiming that all hard registers are used and clobbered at this
3325 emit_insn (gen_blockage ());
3330 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3331 ;; all of memory. This blocks insns from being moved across this point.
3333 (define_insn "blockage"
3334 [(unspec_volatile [(const_int 0)] 1)]
3340 (label_ref (match_operand 0 "" "")))]
3343 [(set_attr "type" "ibr")])
3345 (define_insn "return"
3349 [(set_attr "type" "ibr")])
3351 (define_insn "indirect_jump"
3352 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3355 [(set_attr "type" "ibr")])
3361 [(set_attr "type" "ilog")])
3363 (define_expand "tablejump"
3364 [(use (match_operand:SI 0 "register_operand" ""))
3365 (use (match_operand:SI 1 "" ""))]
3369 if (TARGET_WINDOWS_NT)
3370 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3371 else if (TARGET_OPEN_VMS)
3372 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3374 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3379 (define_expand "tablejump_osf"
3381 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3382 (parallel [(set (pc)
3383 (plus:DI (match_dup 3)
3384 (label_ref:DI (match_operand 1 "" ""))))
3385 (clobber (match_scratch:DI 2 "=r"))])]
3388 { operands[3] = gen_reg_rtx (DImode); }")
3390 (define_expand "tablejump_nt"
3392 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3393 (parallel [(set (pc)
3395 (use (label_ref (match_operand 1 "" "")))])]
3398 { operands[3] = gen_reg_rtx (DImode); }")
3401 ;; tablejump, openVMS way
3403 ;; op 1: label preceding jump-table
3405 (define_expand "tablejump_vms"
3407 (match_operand:DI 0 "register_operand" ""))
3409 (plus:DI (match_dup 2)
3410 (label_ref:DI (match_operand 1 "" ""))))]
3413 { operands[2] = gen_reg_rtx (DImode); }")
3417 (plus:DI (match_operand:DI 0 "register_operand" "r")
3418 (label_ref:DI (match_operand 1 "" ""))))
3419 (clobber (match_scratch:DI 2 "=r"))]
3420 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3421 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3422 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3424 { rtx best_label = 0;
3425 rtx jump_table_insn = next_active_insn (operands[1]);
3427 if (GET_CODE (jump_table_insn) == JUMP_INSN
3428 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3430 rtx jump_table = PATTERN (jump_table_insn);
3431 int n_labels = XVECLEN (jump_table, 1);
3432 int best_count = -1;
3435 for (i = 0; i < n_labels; i++)
3439 for (j = i + 1; j < n_labels; j++)
3440 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3441 == XEXP (XVECEXP (jump_table, 1, j), 0))
3444 if (count > best_count)
3445 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3451 operands[3] = best_label;
3452 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3455 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3457 [(set_attr "type" "ibr")])
3461 (match_operand:DI 0 "register_operand" "r"))
3462 (use (label_ref (match_operand 1 "" "")))]
3463 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3464 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3465 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3467 { rtx best_label = 0;
3468 rtx jump_table_insn = next_active_insn (operands[1]);
3470 if (GET_CODE (jump_table_insn) == JUMP_INSN
3471 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3473 rtx jump_table = PATTERN (jump_table_insn);
3474 int n_labels = XVECLEN (jump_table, 1);
3475 int best_count = -1;
3478 for (i = 0; i < n_labels; i++)
3482 for (j = i + 1; j < n_labels; j++)
3483 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3484 == XEXP (XVECEXP (jump_table, 1, j), 0))
3487 if (count > best_count)
3488 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3494 operands[2] = best_label;
3495 return \"jmp $31,(%0),%2\";
3498 return \"jmp $31,(%0),0\";
3500 [(set_attr "type" "ibr")])
3503 ;; op 0 is table offset
3504 ;; op 1 is table label
3509 (plus:DI (match_operand 0 "register_operand" "r")
3510 (label_ref (match_operand 1 "" ""))))]
3513 [(set_attr "type" "ibr")])
3515 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
3516 ;; want to have to include pal.h in our .s file.
3518 [(unspec_volatile [(const_int 0)] 0)]
3521 [(set_attr "type" "isubr")])
3523 ;; Finally, we have the basic data motion insns. The byte and word insns
3524 ;; are done via define_expand. Start with the floating-point insns, since
3525 ;; they are simpler.
3528 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
3529 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
3530 "register_operand (operands[0], SFmode)
3531 || reg_or_fp0_operand (operands[1], SFmode)"
3540 [(set_attr "type" "ilog,ld,st,fcpys,fcpys,ld,st")])
3543 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
3544 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
3545 "register_operand (operands[0], DFmode)
3546 || reg_or_fp0_operand (operands[1], DFmode)"
3555 [(set_attr "type" "ilog,ld,st,fcpys,fcpys,ld,st")])
3557 (define_expand "movsf"
3558 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3559 (match_operand:SF 1 "general_operand" ""))]
3563 if (GET_CODE (operands[0]) == MEM
3564 && ! reg_or_fp0_operand (operands[1], SFmode))
3565 operands[1] = force_reg (SFmode, operands[1]);
3568 (define_expand "movdf"
3569 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3570 (match_operand:DF 1 "general_operand" ""))]
3574 if (GET_CODE (operands[0]) == MEM
3575 && ! reg_or_fp0_operand (operands[1], DFmode))
3576 operands[1] = force_reg (DFmode, operands[1]);
3580 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
3581 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
3582 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS
3583 && (register_operand (operands[0], SImode)
3584 || reg_or_0_operand (operands[1], SImode))"
3597 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,st,fcpys,fcpys,ld,st")])
3600 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
3601 (match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
3602 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
3603 && (register_operand (operands[0], SImode)
3604 || reg_or_0_operand (operands[1], SImode))"
3618 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ld,st,fcpys,fcpys,ld,st")])
3621 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3622 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
3624 && (register_operand (operands[0], HImode)
3625 || register_operand (operands[1], HImode))"
3633 [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
3636 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
3637 (match_operand:HI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
3639 && (register_operand (operands[0], HImode)
3640 || reg_or_0_operand (operands[1], HImode))"
3650 [(set_attr "type" "ilog,ilog,ilog,iadd,ld,st,fcpys,fcpys")])
3653 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3654 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
3656 && (register_operand (operands[0], QImode)
3657 || register_operand (operands[1], QImode))"
3665 [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
3668 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
3669 (match_operand:QI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
3671 && (register_operand (operands[0], QImode)
3672 || reg_or_0_operand (operands[1], QImode))"
3682 [(set_attr "type" "ilog,ilog,ilog,iadd,ld,st,fcpys,fcpys")])
3684 ;; We do two major things here: handle mem->mem and construct long
3687 (define_expand "movsi"
3688 [(set (match_operand:SI 0 "general_operand" "")
3689 (match_operand:SI 1 "general_operand" ""))]
3693 if (GET_CODE (operands[0]) == MEM
3694 && ! reg_or_0_operand (operands[1], SImode))
3695 operands[1] = force_reg (SImode, operands[1]);
3697 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
3699 else if (GET_CODE (operands[1]) == CONST_INT)
3702 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
3703 if (rtx_equal_p (operands[0], operands[1]))
3708 ;; Split a load of a large constant into the appropriate two-insn
3712 [(set (match_operand:SI 0 "register_operand" "")
3713 (match_operand:SI 1 "const_int_operand" ""))]
3714 "! add_operand (operands[1], SImode)"
3715 [(set (match_dup 0) (match_dup 2))
3716 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
3719 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
3721 if (tem == operands[0])
3728 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
3729 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
3730 "register_operand (operands[0], DImode)
3731 || reg_or_0_operand (operands[1], DImode)"
3745 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ld,st,fcpys,fcpys,ld,st")])
3747 ;; We do three major things here: handle mem->mem, put 64-bit constants in
3748 ;; memory, and construct long 32-bit constants.
3750 (define_expand "movdi"
3751 [(set (match_operand:DI 0 "general_operand" "")
3752 (match_operand:DI 1 "general_operand" ""))]
3758 if (GET_CODE (operands[0]) == MEM
3759 && ! reg_or_0_operand (operands[1], DImode))
3760 operands[1] = force_reg (DImode, operands[1]);
3762 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
3764 else if (GET_CODE (operands[1]) == CONST_INT
3765 && (tem = alpha_emit_set_const (operands[0], DImode,
3766 INTVAL (operands[1]), 3)) != 0)
3768 if (rtx_equal_p (tem, operands[0]))
3773 else if (TARGET_BUILD_CONSTANTS
3774 && GET_CODE (operands[1]) == CONST_INT)
3776 #if HOST_BITS_PER_WIDE_INT == 64
3777 tem = alpha_emit_set_long_const (operands[0], INTVAL (operands[1]));
3778 if (rtx_equal_p (tem, operands[0]))
3786 else if (CONSTANT_P (operands[1]))
3788 operands[1] = force_const_mem (DImode, operands[1]);
3789 if (reload_in_progress)
3791 emit_move_insn (operands[0], XEXP (operands[1], 0));
3792 operands[1] = copy_rtx (operands[1]);
3793 XEXP (operands[1], 0) = operands[0];
3796 operands[1] = validize_mem (operands[1]);
3802 ;; Split a load of a large constant into the appropriate two-insn
3806 [(set (match_operand:DI 0 "register_operand" "")
3807 (match_operand:DI 1 "const_int_operand" ""))]
3808 "! add_operand (operands[1], DImode)"
3809 [(set (match_dup 0) (match_dup 2))
3810 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
3813 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
3815 if (tem == operands[0])
3821 ;; These are the partial-word cases.
3823 ;; First we have the code to load an aligned word. Operand 0 is the register
3824 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
3825 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
3826 ;; number of bits within the word that the value is. Operand 3 is an SImode
3827 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
3828 ;; same register. It is allowed to conflict with operand 1 as well.
3830 (define_expand "aligned_loadqi"
3831 [(set (match_operand:SI 3 "register_operand" "")
3832 (match_operand:SI 1 "memory_operand" ""))
3833 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3834 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3836 (match_operand:DI 2 "const_int_operand" "")))]
3841 (define_expand "aligned_loadhi"
3842 [(set (match_operand:SI 3 "register_operand" "")
3843 (match_operand:SI 1 "memory_operand" ""))
3844 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
3845 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3847 (match_operand:DI 2 "const_int_operand" "")))]
3852 ;; Similar for unaligned loads, where we use the sequence from the
3853 ;; Alpha Architecture manual.
3855 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
3856 ;; operand 3 can overlap the input and output registers.
3858 (define_expand "unaligned_loadqi"
3859 [(set (match_operand:DI 2 "register_operand" "")
3860 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
3862 (set (match_operand:DI 3 "register_operand" "")
3864 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3865 (zero_extract:DI (match_dup 2)
3867 (ashift:DI (match_dup 3) (const_int 3))))]
3871 (define_expand "unaligned_loadhi"
3872 [(set (match_operand:DI 2 "register_operand" "")
3873 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
3875 (set (match_operand:DI 3 "register_operand" "")
3877 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3878 (zero_extract:DI (match_dup 2)
3880 (ashift:DI (match_dup 3) (const_int 3))))]
3884 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
3885 ;; aligned SImode MEM. Operand 1 is the register containing the
3886 ;; byte or word to store. Operand 2 is the number of bits within the word that
3887 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
3889 (define_expand "aligned_store"
3890 [(set (match_operand:SI 3 "register_operand" "")
3891 (match_operand:SI 0 "memory_operand" ""))
3892 (set (subreg:DI (match_dup 3) 0)
3893 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
3894 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
3895 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
3896 (match_operand:DI 2 "const_int_operand" "")))
3897 (set (subreg:DI (match_dup 4) 0)
3898 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
3899 (set (match_dup 0) (match_dup 4))]
3902 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
3903 << INTVAL (operands[2])));
3906 ;; For the unaligned byte and halfword cases, we use code similar to that
3907 ;; in the ;; Architecture book, but reordered to lower the number of registers
3908 ;; required. Operand 0 is the address. Operand 1 is the data to store.
3909 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
3910 ;; be the same temporary, if desired. If the address is in a register,
3911 ;; operand 2 can be that register.
3913 (define_expand "unaligned_storeqi"
3914 [(set (match_operand:DI 3 "register_operand" "")
3915 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
3917 (set (match_operand:DI 2 "register_operand" "")
3920 (and:DI (not:DI (ashift:DI (const_int 255)
3921 (ashift:DI (match_dup 2) (const_int 3))))
3923 (set (match_operand:DI 4 "register_operand" "")
3924 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
3925 (ashift:DI (match_dup 2) (const_int 3))))
3926 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
3927 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
3932 (define_expand "unaligned_storehi"
3933 [(set (match_operand:DI 3 "register_operand" "")
3934 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
3936 (set (match_operand:DI 2 "register_operand" "")
3939 (and:DI (not:DI (ashift:DI (const_int 65535)
3940 (ashift:DI (match_dup 2) (const_int 3))))
3942 (set (match_operand:DI 4 "register_operand" "")
3943 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
3944 (ashift:DI (match_dup 2) (const_int 3))))
3945 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
3946 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
3951 ;; Here are the define_expand's for QI and HI moves that use the above
3952 ;; patterns. We have the normal sets, plus the ones that need scratch
3953 ;; registers for reload.
3955 (define_expand "movqi"
3956 [(set (match_operand:QI 0 "general_operand" "")
3957 (match_operand:QI 1 "general_operand" ""))]
3960 { extern rtx get_unaligned_address ();
3962 if (TARGET_BYTE_OPS)
3964 if (GET_CODE (operands[0]) == MEM
3965 && ! reg_or_0_operand (operands[1], QImode))
3966 operands[1] = force_reg (QImode, operands[1]);
3968 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], QImode))
3970 else if (GET_CODE (operands[1]) == CONST_INT)
3973 = alpha_emit_set_const (operands[0], QImode, INTVAL (operands[1]), 3);
3974 if (rtx_equal_p (operands[0], operands[1]))
3980 /* If the output is not a register, the input must be. */
3981 if (GET_CODE (operands[0]) == MEM)
3982 operands[1] = force_reg (QImode, operands[1]);
3984 /* Handle four memory cases, unaligned and aligned for either the input
3985 or the output. The only case where we can be called during reload is
3986 for aligned loads; all other cases require temporaries. */
3988 if (GET_CODE (operands[1]) == MEM
3989 || (GET_CODE (operands[1]) == SUBREG
3990 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3991 || (reload_in_progress && GET_CODE (operands[1]) == REG
3992 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3993 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3994 && GET_CODE (SUBREG_REG (operands[1])) == REG
3995 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3997 if (aligned_memory_operand (operands[1], QImode))
3999 rtx aligned_mem, bitnum;
4000 rtx scratch = (reload_in_progress
4001 ? gen_rtx (REG, SImode, REGNO (operands[0]))
4002 : gen_reg_rtx (SImode));
4004 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4006 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4011 /* Don't pass these as parameters since that makes the generated
4012 code depend on parameter evaluation order which will cause
4013 bootstrap failures. */
4015 rtx temp1 = gen_reg_rtx (DImode);
4016 rtx temp2 = gen_reg_rtx (DImode);
4018 = gen_unaligned_loadqi (operands[0],
4019 get_unaligned_address (operands[1], 0),
4022 alpha_set_memflags (seq, operands[1]);
4029 else if (GET_CODE (operands[0]) == MEM
4030 || (GET_CODE (operands[0]) == SUBREG
4031 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4032 || (reload_in_progress && GET_CODE (operands[0]) == REG
4033 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4034 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4035 && GET_CODE (SUBREG_REG (operands[0])) == REG
4036 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4038 if (aligned_memory_operand (operands[0], QImode))
4040 rtx aligned_mem, bitnum;
4041 rtx temp1 = gen_reg_rtx (SImode);
4042 rtx temp2 = gen_reg_rtx (SImode);
4044 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4046 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4051 rtx temp1 = gen_reg_rtx (DImode);
4052 rtx temp2 = gen_reg_rtx (DImode);
4053 rtx temp3 = gen_reg_rtx (DImode);
4055 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4056 operands[1], temp1, temp2, temp3);
4058 alpha_set_memflags (seq, operands[0]);
4066 (define_expand "movhi"
4067 [(set (match_operand:HI 0 "general_operand" "")
4068 (match_operand:HI 1 "general_operand" ""))]
4071 { extern rtx get_unaligned_address ();
4073 if (TARGET_BYTE_OPS)
4075 if (GET_CODE (operands[0]) == MEM
4076 && ! reg_or_0_operand (operands[1], HImode))
4077 operands[1] = force_reg (HImode, operands[1]);
4079 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
4081 else if (GET_CODE (operands[1]) == CONST_INT)
4084 = alpha_emit_set_const (operands[0], HImode, INTVAL (operands[1]), 3);
4085 if (rtx_equal_p (operands[0], operands[1]))
4092 /* If the output is not a register, the input must be. */
4093 if (GET_CODE (operands[0]) == MEM)
4094 operands[1] = force_reg (HImode, operands[1]);
4096 /* Handle four memory cases, unaligned and aligned for either the input
4097 or the output. The only case where we can be called during reload is
4098 for aligned loads; all other cases require temporaries. */
4100 if (GET_CODE (operands[1]) == MEM
4101 || (GET_CODE (operands[1]) == SUBREG
4102 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4103 || (reload_in_progress && GET_CODE (operands[1]) == REG
4104 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4105 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4106 && GET_CODE (SUBREG_REG (operands[1])) == REG
4107 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4109 if (aligned_memory_operand (operands[1], HImode))
4111 rtx aligned_mem, bitnum;
4112 rtx scratch = (reload_in_progress
4113 ? gen_rtx (REG, SImode, REGNO (operands[0]))
4114 : gen_reg_rtx (SImode));
4116 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4118 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4123 /* Don't pass these as parameters since that makes the generated
4124 code depend on parameter evaluation order which will cause
4125 bootstrap failures. */
4127 rtx temp1 = gen_reg_rtx (DImode);
4128 rtx temp2 = gen_reg_rtx (DImode);
4130 = gen_unaligned_loadhi (operands[0],
4131 get_unaligned_address (operands[1], 0),
4134 alpha_set_memflags (seq, operands[1]);
4141 else if (GET_CODE (operands[0]) == MEM
4142 || (GET_CODE (operands[0]) == SUBREG
4143 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4144 || (reload_in_progress && GET_CODE (operands[0]) == REG
4145 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4146 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4147 && GET_CODE (SUBREG_REG (operands[0])) == REG
4148 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4150 if (aligned_memory_operand (operands[0], HImode))
4152 rtx aligned_mem, bitnum;
4153 rtx temp1 = gen_reg_rtx (SImode);
4154 rtx temp2 = gen_reg_rtx (SImode);
4156 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4158 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4163 rtx temp1 = gen_reg_rtx (DImode);
4164 rtx temp2 = gen_reg_rtx (DImode);
4165 rtx temp3 = gen_reg_rtx (DImode);
4167 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4168 operands[1], temp1, temp2, temp3);
4170 alpha_set_memflags (seq, operands[0]);
4179 ;; Here are the versions for reload. Note that in the unaligned cases
4180 ;; we know that the operand must not be a pseudo-register because stack
4181 ;; slots are always aligned references.
4183 (define_expand "reload_inqi"
4184 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4185 (match_operand:QI 1 "unaligned_memory_operand" "m")
4186 (match_operand:TI 2 "register_operand" "=&r")])]
4189 { extern rtx get_unaligned_address ();
4190 rtx addr = get_unaligned_address (operands[1], 0);
4191 /* It is possible that one of the registers we got for operands[2]
4192 might coincide with that of operands[0] (which is why we made
4193 it TImode). Pick the other one to use as our scratch. */
4194 rtx scratch = gen_rtx (REG, DImode,
4195 REGNO (operands[0]) == REGNO (operands[2])
4196 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4197 rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4198 gen_rtx (REG, DImode, REGNO (operands[0])));
4200 alpha_set_memflags (seq, operands[1]);
4205 (define_expand "reload_inhi"
4206 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4207 (match_operand:HI 1 "unaligned_memory_operand" "m")
4208 (match_operand:TI 2 "register_operand" "=&r")])]
4211 { extern rtx get_unaligned_address ();
4212 rtx addr = get_unaligned_address (operands[1], 0);
4213 /* It is possible that one of the registers we got for operands[2]
4214 might coincide with that of operands[0] (which is why we made
4215 it TImode). Pick the other one to use as our scratch. */
4216 rtx scratch = gen_rtx (REG, DImode,
4217 REGNO (operands[0]) == REGNO (operands[2])
4218 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4219 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4220 gen_rtx (REG, DImode, REGNO (operands[0])));
4222 alpha_set_memflags (seq, operands[1]);
4227 (define_expand "reload_outqi"
4228 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4229 (match_operand:QI 1 "register_operand" "r")
4230 (match_operand:TI 2 "register_operand" "=&r")])]
4233 { extern rtx get_unaligned_address ();
4235 if (aligned_memory_operand (operands[0], QImode))
4237 rtx aligned_mem, bitnum;
4239 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4241 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4242 gen_rtx (REG, SImode, REGNO (operands[2])),
4243 gen_rtx (REG, SImode,
4244 REGNO (operands[2]) + 1)));
4248 rtx addr = get_unaligned_address (operands[0], 0);
4249 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
4250 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
4251 rtx scratch3 = scratch1;
4254 if (GET_CODE (addr) == REG)
4257 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4258 scratch2, scratch3);
4259 alpha_set_memflags (seq, operands[0]);
4266 (define_expand "reload_outhi"
4267 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4268 (match_operand:HI 1 "register_operand" "r")
4269 (match_operand:TI 2 "register_operand" "=&r")])]
4272 { extern rtx get_unaligned_address ();
4274 if (aligned_memory_operand (operands[0], HImode))
4276 rtx aligned_mem, bitnum;
4278 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4280 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4281 gen_rtx (REG, SImode, REGNO (operands[2])),
4282 gen_rtx (REG, SImode,
4283 REGNO (operands[2]) + 1)));
4287 rtx addr = get_unaligned_address (operands[0], 0);
4288 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
4289 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
4290 rtx scratch3 = scratch1;
4293 if (GET_CODE (addr) == REG)
4296 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4297 scratch2, scratch3);
4298 alpha_set_memflags (seq, operands[0]);
4305 ;; Subroutine of stack space allocation. Perform a stack probe.
4306 (define_expand "probe_stack"
4307 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
4311 operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx,
4312 INTVAL (operands[0])));
4313 MEM_VOLATILE_P (operands[1]) = 1;
4315 operands[0] = const0_rtx;
4318 ;; This is how we allocate stack space. If we are allocating a
4319 ;; constant amount of space and we know it is less than 4096
4320 ;; bytes, we need do nothing.
4322 ;; If it is more than 4096 bytes, we need to probe the stack
4324 (define_expand "allocate_stack"
4326 (plus:DI (reg:DI 30)
4327 (match_operand:DI 0 "reg_or_cint_operand" "")))]
4331 if (GET_CODE (operands[0]) == CONST_INT
4332 && INTVAL (operands[0]) < 32768)
4334 if (INTVAL (operands[0]) >= 4096)
4336 /* We do this the same way as in the prologue and generate explicit
4337 probes. Then we update the stack by the constant. */
4341 emit_insn (gen_probe_stack (GEN_INT (- probed)));
4342 while (probed + 8192 < INTVAL (operands[0]))
4343 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
4345 if (probed + 4096 < INTVAL (operands[0]))
4346 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[0]))));
4349 operands[0] = GEN_INT (- INTVAL (operands[0]));
4354 rtx loop_label = gen_label_rtx ();
4355 rtx want = gen_reg_rtx (Pmode);
4356 rtx tmp = gen_reg_rtx (Pmode);
4359 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
4360 force_reg (Pmode, operands[0])));
4361 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
4363 if (GET_CODE (operands[0]) != CONST_INT)
4365 out_label = gen_label_rtx ();
4366 emit_insn (gen_cmpdi (want, tmp));
4367 emit_jump_insn (gen_bgeu (out_label));
4370 emit_label (loop_label);
4371 memref = gen_rtx (MEM, DImode, tmp);
4372 MEM_VOLATILE_P (memref) = 1;
4373 emit_move_insn (memref, const0_rtx);
4374 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
4375 emit_insn (gen_cmpdi (tmp, want));
4376 emit_jump_insn (gen_bgtu (loop_label));
4377 memref = gen_rtx (MEM, DImode, want);
4378 MEM_VOLATILE_P (memref) = 1;
4379 emit_move_insn (memref, const0_rtx);
4382 emit_label (out_label);
4384 emit_move_insn (stack_pointer_rtx, want);
4390 (define_insn "exception_receiver"
4391 [(unspec_volatile [(const_int 0)] 2)]
4392 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
4393 ".long 0xc3a00000\;ldgp $29,0($29)")
4395 (define_expand "nonlocal_goto_receiver"
4396 [(unspec_volatile [(const_int 0)] 1)
4397 (set (reg:DI 27) (mem:DI (reg:DI 29)))
4398 (unspec_volatile [(const_int 0)] 1)
4403 (define_insn "arg_home"
4404 [(unspec [(const_int 0)] 0)
4419 (clobber (mem:BLK (const_int 0)))
4420 (clobber (reg:DI 24))
4421 (clobber (reg:DI 25))
4422 (clobber (reg:DI 0))]
4424 "lda $0,ots$home_args\;ldq $0,8($0)\;jsr $0,ots$home_args")