1 ;;- Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; Define an insn type attribute. This is used in function unit delay
24 ;; computations, among other purposes. For the most part, we use the names
25 ;; defined in the EV4 documentation, but add a few that we have to know about
29 "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr"
30 (const_string "shiftcm"))
32 ;; We include four function units: ABOX, which computes the address,
33 ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
34 ;; used for FP operations.
36 ;; We assume that we have been successful in getting double issues and
37 ;; hence multiply all costs by two insns per cycle. The minimum time in
38 ;; a function unit is 2 cycle, which will tend to produce the double
41 ;; Memory delivers its result in three cycles.
42 (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2)
44 ;; Branches have no delay cost, but do tie up the unit for two cycles.
45 (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4)
47 ;; Arithmetic insns are normally have their results available after two
48 ;; cycles. There are a number of exceptions. They are encoded in
49 ;; ADJUST_COST. Some of the other insns have similar exceptions.
51 (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2)
53 ;; These really don't take up the integer pipeline, but they do occupy
54 ;; IBOX1; we approximate here.
56 (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2)
57 (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2)
59 (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38)
60 (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42)
62 (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2)
64 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0)
65 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0)
67 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60)
68 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118)
70 ;; First define the arithmetic insns. Note that the 32-bit forms also
73 ;; Note that we can do sign extensions in both FP and integer registers.
74 ;; However, the result must be in the same type of register as the input.
75 ;; The register preferencing code can't handle this case very well, so, for
76 ;; now, don't let the FP case show up here for preferencing. Also,
77 ;; sign-extends in FP registers take two instructions.
78 (define_insn "extendsidi2"
79 [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
80 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
85 cvtql %1,%0\;cvtlq %0,%0"
86 [(set_attr "type" "iaddlog,ld,fpop")])
89 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
90 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
91 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
98 [(set_attr "type" "iaddlog")])
101 [(set (match_operand:SI 0 "register_operand" "")
102 (plus:SI (match_operand:SI 1 "register_operand" "")
103 (match_operand:SI 2 "const_int_operand" "")))]
104 "! add_operand (operands[2], SImode)"
105 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
106 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
109 HOST_WIDE_INT val = INTVAL (operands[2]);
110 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
111 HOST_WIDE_INT rest = val - low;
113 operands[3] = GEN_INT (rest);
114 operands[4] = GEN_INT (low);
118 [(set (match_operand:DI 0 "register_operand" "=r,r")
120 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
121 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
126 [(set_attr "type" "iaddlog")])
129 [(set (match_operand:DI 0 "register_operand" "")
131 (plus:SI (match_operand:SI 1 "register_operand" "")
132 (match_operand:SI 2 "const_int_operand" ""))))
133 (clobber (match_operand:SI 3 "register_operand" ""))]
134 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
135 && INTVAL (operands[2]) % 4 == 0"
136 [(set (match_dup 3) (match_dup 4))
137 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
142 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
148 operands[4] = GEN_INT (val);
149 operands[5] = GEN_INT (mult);
152 (define_insn "adddi3"
153 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
154 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
155 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
162 [(set_attr "type" "iaddlog")])
164 ;; Don't do this if we are adjusting SP since we don't want to do
167 [(set (match_operand:DI 0 "register_operand" "")
168 (plus:DI (match_operand:DI 1 "register_operand" "")
169 (match_operand:DI 2 "const_int_operand" "")))]
170 "! add_operand (operands[2], DImode)
171 && REGNO (operands[0]) != STACK_POINTER_REGNUM"
172 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
173 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
176 HOST_WIDE_INT val = INTVAL (operands[2]);
177 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
178 HOST_WIDE_INT rest = val - low;
180 operands[3] = GEN_INT (rest);
181 operands[4] = GEN_INT (low);
185 [(set (match_operand:SI 0 "register_operand" "=r,r")
186 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
187 (match_operand:SI 2 "const48_operand" "I,I"))
188 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
193 [(set_attr "type" "iaddlog")])
196 [(set (match_operand:DI 0 "register_operand" "=r,r")
198 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
199 (match_operand:SI 2 "const48_operand" "I,I"))
200 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
205 [(set_attr "type" "iaddlog")])
208 [(set (match_operand:DI 0 "register_operand" "=r,r")
209 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
210 (match_operand:DI 2 "const48_operand" "I,I"))
211 (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))]
216 [(set_attr "type" "iaddlog")])
218 ;; These variants of the above insns can occur if the third operand
219 ;; is the frame pointer. This is a kludge, but there doesn't
220 ;; seem to be a way around it. Only recognize them while reloading.
223 [(set (match_operand:SI 0 "register_operand" "=&r")
224 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
225 (match_operand:SI 2 "const48_operand" "I"))
226 (match_operand:SI 3 "register_operand" "r"))
227 (match_operand:SI 4 "const_int_operand" "rI")))]
229 "s%2addl %r1,%3,%0\;addl %0,%4,%0"
230 [(set_attr "type" "iaddlog")])
233 [(set (match_operand:DI 0 "register_operand" "=&r")
236 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
237 (match_operand:SI 2 "const48_operand" "I"))
238 (match_operand:SI 3 "register_operand" "r"))
239 (match_operand:SI 4 "const_int_operand" "rI"))))]
241 "s%2addl %r1,%3,%0\;addl %0,%4,%0"
242 [(set_attr "type" "iaddlog")])
245 [(set (match_operand:DI 0 "register_operand" "=&r")
246 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
247 (match_operand:DI 2 "const48_operand" "I"))
248 (match_operand:DI 3 "register_operand" "r"))
249 (match_operand:DI 4 "const_int_operand" "rI")))]
251 "s%2addq %r1,%3,%0\;addq %0,%4,%0"
252 [(set_attr "type" "iaddlog")])
254 (define_insn "negsi2"
255 [(set (match_operand:SI 0 "register_operand" "=r")
256 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
259 [(set_attr "type" "iaddlog")])
262 [(set (match_operand:DI 0 "register_operand" "=r")
263 (sign_extend:DI (neg:SI
264 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
267 [(set_attr "type" "iaddlog")])
269 (define_insn "negdi2"
270 [(set (match_operand:DI 0 "register_operand" "=r")
271 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
274 [(set_attr "type" "iaddlog")])
276 (define_insn "subsi3"
277 [(set (match_operand:SI 0 "register_operand" "=r")
278 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
279 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
282 [(set_attr "type" "iaddlog")])
285 [(set (match_operand:DI 0 "register_operand" "=r")
286 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
287 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
290 [(set_attr "type" "iaddlog")])
292 (define_insn "subdi3"
293 [(set (match_operand:DI 0 "register_operand" "=r")
294 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
295 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
298 [(set_attr "type" "iaddlog")])
301 [(set (match_operand:SI 0 "register_operand" "=r")
302 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
303 (match_operand:SI 2 "const48_operand" "I"))
304 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
307 [(set_attr "type" "iaddlog")])
310 [(set (match_operand:DI 0 "register_operand" "=r")
312 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
313 (match_operand:SI 2 "const48_operand" "I"))
314 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
317 [(set_attr "type" "iaddlog")])
320 [(set (match_operand:DI 0 "register_operand" "=r")
321 (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
322 (match_operand:DI 2 "const48_operand" "I"))
323 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
326 [(set_attr "type" "iaddlog")])
328 (define_insn "mulsi3"
329 [(set (match_operand:SI 0 "register_operand" "=r")
330 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
331 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
334 [(set_attr "type" "imull")])
337 [(set (match_operand:DI 0 "register_operand" "=r")
338 (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
339 (match_operand:SI 2 "reg_or_0_operand" "rJ"))))]
342 [(set_attr "type" "imull")])
344 (define_insn "muldi3"
345 [(set (match_operand:DI 0 "register_operand" "=r")
346 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
347 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
350 [(set_attr "type" "imulq")])
352 ;; The divide and remainder operations always take their inputs from
353 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
355 (define_expand "divsi3"
356 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
357 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
358 (parallel [(set (reg:SI 27)
361 (clobber (reg:DI 23))
362 (clobber (reg:DI 28))])
363 (set (match_operand:SI 0 "general_operand" "")
368 (define_expand "udivsi3"
369 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
370 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
371 (parallel [(set (reg:SI 27)
374 (clobber (reg:DI 23))
375 (clobber (reg:DI 28))])
376 (set (match_operand:SI 0 "general_operand" "")
381 (define_expand "modsi3"
382 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
383 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
384 (parallel [(set (reg:SI 27)
387 (clobber (reg:DI 23))
388 (clobber (reg:DI 28))])
389 (set (match_operand:SI 0 "general_operand" "")
394 (define_expand "umodsi3"
395 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
396 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
397 (parallel [(set (reg:SI 27)
400 (clobber (reg:DI 23))
401 (clobber (reg:DI 28))])
402 (set (match_operand:SI 0 "general_operand" "")
407 (define_expand "divdi3"
408 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
409 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
410 (parallel [(set (reg:DI 27)
413 (clobber (reg:DI 23))
414 (clobber (reg:DI 28))])
415 (set (match_operand:DI 0 "general_operand" "")
420 (define_expand "udivdi3"
421 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
422 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
423 (parallel [(set (reg:DI 27)
426 (clobber (reg:DI 23))
427 (clobber (reg:DI 28))])
428 (set (match_operand:DI 0 "general_operand" "")
433 (define_expand "moddi3"
434 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
435 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
436 (parallel [(set (reg:DI 27)
439 (clobber (reg:DI 23))
440 (clobber (reg:DI 28))])
441 (set (match_operand:DI 0 "general_operand" "")
446 (define_expand "umoddi3"
447 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
448 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
449 (parallel [(set (reg:DI 27)
452 (clobber (reg:DI 23))
453 (clobber (reg:DI 28))])
454 (set (match_operand:DI 0 "general_operand" "")
461 (match_operator:SI 1 "divmod_operator"
462 [(reg:SI 24) (reg:SI 25)]))
463 (clobber (reg:DI 23))
464 (clobber (reg:DI 28))]
467 [(set_attr "type" "isubr")])
471 (match_operator:DI 1 "divmod_operator"
472 [(reg:DI 24) (reg:DI 25)]))
473 (clobber (reg:DI 23))
474 (clobber (reg:DI 28))]
477 [(set_attr "type" "isubr")])
479 ;; Next are the basic logical operations. These only exist in DImode.
481 (define_insn "anddi3"
482 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
483 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
484 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
490 [(set_attr "type" "iaddlog,iaddlog,shiftcm")])
492 ;; There are times when we can split and AND into two AND insns. This occurs
493 ;; when we can first clear any bytes and then clear anything else. For
494 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
495 ;; Only to this when running on 64-bit host since the computations are
496 ;; too messy otherwise.
499 [(set (match_operand:DI 0 "register_operand" "")
500 (and:DI (match_operand:DI 1 "register_operand" "")
501 (match_operand:DI 2 "const_int_operand" "")))]
502 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
503 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
504 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
507 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
508 unsigned HOST_WIDE_INT mask2 = mask1;
511 /* For each byte that isn't all zeros, make it all ones. */
512 for (i = 0; i < 64; i += 8)
513 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
514 mask1 |= (HOST_WIDE_INT) 0xff << i;
516 /* Now turn on any bits we've just turned off. */
519 operands[3] = GEN_INT (mask1);
520 operands[4] = GEN_INT (mask2);
523 (define_insn "zero_extendqihi2"
524 [(set (match_operand:HI 0 "register_operand" "=r")
525 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
528 [(set_attr "type" "iaddlog")])
530 (define_insn "zero_extendqisi2"
531 [(set (match_operand:SI 0 "register_operand" "=r")
532 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
535 [(set_attr "type" "iaddlog")])
537 (define_insn "zero_extendqidi2"
538 [(set (match_operand:DI 0 "register_operand" "=r")
539 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
542 [(set_attr "type" "iaddlog")])
544 (define_insn "zero_extendhisi2"
545 [(set (match_operand:SI 0 "register_operand" "=r")
546 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
549 [(set_attr "type" "iaddlog")])
551 (define_insn "zero_extendhidi2"
552 [(set (match_operand:DI 0 "register_operand" "=r")
553 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
556 [(set_attr "type" "iaddlog")])
558 (define_insn "zero_extendsidi2"
559 [(set (match_operand:DI 0 "register_operand" "=r")
560 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
563 [(set_attr "type" "iaddlog")])
566 [(set (match_operand:DI 0 "register_operand" "=r")
567 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
568 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
571 [(set_attr "type" "iaddlog")])
573 (define_insn "iordi3"
574 [(set (match_operand:DI 0 "register_operand" "=r,r")
575 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
576 (match_operand:DI 2 "ior_operand" "rI,N")))]
581 [(set_attr "type" "iaddlog")])
583 (define_insn "one_cmpldi2"
584 [(set (match_operand:DI 0 "register_operand" "=r")
585 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
588 [(set_attr "type" "iaddlog")])
591 [(set (match_operand:DI 0 "register_operand" "=r")
592 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
593 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
596 [(set_attr "type" "iaddlog")])
598 (define_insn "xordi3"
599 [(set (match_operand:DI 0 "register_operand" "=r")
600 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
601 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
604 [(set_attr "type" "iaddlog")])
607 [(set (match_operand:DI 0 "register_operand" "=r")
608 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
609 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))))]
612 [(set_attr "type" "iaddlog")])
614 ;; Next come the shifts and the various extract and insert operations.
616 (define_insn "ashldi3"
617 [(set (match_operand:DI 0 "register_operand" "=r,r")
618 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
619 (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
623 switch (which_alternative)
626 if (operands[2] == const1_rtx)
627 return \"addq %r1,%r1,%0\";
629 return \"s%P2addq %r1,0,%0\";
631 return \"sll %r1,%2,%0\";
634 [(set_attr "type" "iaddlog,shiftcm")])
636 ;; This is the same as (sign_extend (shift X [123])).
638 [(set (match_operand:DI 0 "register_operand" "=r")
639 (ashiftrt:DI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
640 (match_operand:DI 2 "const_int_operand" "i"))
642 "INTVAL (operands[2]) >= 33 && INTVAL (operands[2]) <= 35"
645 switch (INTVAL (operands[2]))
648 return \"addl %r1,%r1,%0\";
650 return \"s4addl %r1,0,%0\";
652 return \"s8addl %r1,0,%0\";
657 [(set_attr "type" "iaddlog")])
659 (define_insn "lshrdi3"
660 [(set (match_operand:DI 0 "register_operand" "=r")
661 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
662 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
666 (define_insn "ashrdi3"
667 [(set (match_operand:DI 0 "register_operand" "=r")
668 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
669 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
673 (define_expand "extendqihi2"
675 (ashift:DI (match_operand:QI 1 "register_operand" "")
677 (set (match_operand:HI 0 "register_operand" "")
678 (ashiftrt:DI (match_dup 2)
682 { operands[0] = gen_lowpart (DImode, operands[0]);
683 operands[1] = gen_lowpart (DImode, operands[1]);
684 operands[2] = gen_reg_rtx (DImode);
687 (define_expand "extendqisi2"
689 (ashift:DI (match_operand:QI 1 "register_operand" "")
691 (set (match_operand:SI 0 "register_operand" "")
692 (ashiftrt:DI (match_dup 2)
696 { operands[0] = gen_lowpart (DImode, operands[0]);
697 operands[1] = gen_lowpart (DImode, operands[1]);
698 operands[2] = gen_reg_rtx (DImode);
701 (define_expand "extendqidi2"
703 (ashift:DI (match_operand:QI 1 "register_operand" "")
705 (set (match_operand:DI 0 "register_operand" "")
706 (ashiftrt:DI (match_dup 2)
710 { operands[1] = gen_lowpart (DImode, operands[1]);
711 operands[2] = gen_reg_rtx (DImode);
714 (define_expand "extendhisi2"
716 (ashift:DI (match_operand:HI 1 "register_operand" "")
718 (set (match_operand:SI 0 "register_operand" "")
719 (ashiftrt:DI (match_dup 2)
723 { operands[0] = gen_lowpart (DImode, operands[0]);
724 operands[1] = gen_lowpart (DImode, operands[1]);
725 operands[2] = gen_reg_rtx (DImode);
728 (define_expand "extendhidi2"
730 (ashift:DI (match_operand:HI 1 "register_operand" "")
732 (set (match_operand:DI 0 "register_operand" "")
733 (ashiftrt:DI (match_dup 2)
737 { operands[1] = gen_lowpart (DImode, operands[1]);
738 operands[2] = gen_reg_rtx (DImode);
742 [(set (match_operand:DI 0 "register_operand" "=r")
743 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
744 (match_operand:DI 2 "mode_width_operand" "n")
745 (match_operand:DI 3 "mul8_operand" "I")))]
747 "ext%M2l %r1,%s3,%0")
750 [(set (match_operand:DI 0 "register_operand" "=r")
751 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
752 (match_operand:DI 2 "mode_width_operand" "n")
753 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
759 [(set (match_operand:DI 0 "register_operand" "=r")
761 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
765 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
773 [(set (match_operand:DI 0 "register_operand" "=r")
775 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
779 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
787 [(set (match_operand:DI 0 "register_operand" "=r")
789 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
793 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
800 ;; This converts an extXl into an extXh with an appropriate adjustment
801 ;; to the address calculation.
804 [(set (match_operand:DI 0 "register_operand" "")
805 (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
806 (match_operand:DI 2 "mode_width_operand" "")
807 (ashift:DI (match_operand:DI 3 "" "")
809 (match_operand:DI 4 "const_int_operand" "")))
810 (clobber (match_operand:DI 5 "register_operand" ""))]
811 "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
812 [(set (match_dup 5) (match_dup 6))
814 (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
815 (ashift:DI (plus:DI (match_dup 5)
821 operands[6] = plus_constant (operands[3],
822 INTVAL (operands[2]) / BITS_PER_UNIT);
823 operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
827 [(set (match_operand:DI 0 "register_operand" "=r")
828 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
829 (match_operand:DI 2 "mul8_operand" "I")))]
834 [(set (match_operand:DI 0 "register_operand" "=r")
835 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
836 (match_operand:DI 2 "mul8_operand" "I")))]
841 [(set (match_operand:DI 0 "register_operand" "=r")
842 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
843 (match_operand:DI 2 "mul8_operand" "I")))]
848 [(set (match_operand:DI 0 "register_operand" "=r")
849 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
850 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
856 [(set (match_operand:DI 0 "register_operand" "=r")
857 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
858 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
866 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
871 ;; We do not include the insXh insns because they are complex to express
872 ;; and it does not appear that we would ever want to generate them.
875 [(set (match_operand:DI 0 "register_operand" "=r")
876 (and:DI (not:DI (ashift:DI
877 (match_operand:DI 2 "mode_mask_operand" "n")
879 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
881 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
885 ;; We do not include the mskXh insns because it does not appear we would ever
888 ;; Floating-point operations. All the double-precision insns can extend
889 ;; from single, so indicate that. The exception are the ones that simply
890 ;; play with the sign bits; it's not clear what to do there.
892 (define_insn "abssf2"
893 [(set (match_operand:SF 0 "register_operand" "=f")
894 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
897 [(set_attr "type" "fpop")])
899 (define_insn "absdf2"
900 [(set (match_operand:DF 0 "register_operand" "=f")
901 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
904 [(set_attr "type" "fpop")])
906 (define_insn "negsf2"
907 [(set (match_operand:SF 0 "register_operand" "=f")
908 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
911 [(set_attr "type" "fpop")])
913 (define_insn "negdf2"
914 [(set (match_operand:DF 0 "register_operand" "=f")
915 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
918 [(set_attr "type" "fpop")])
920 (define_insn "addsf3"
921 [(set (match_operand:SF 0 "register_operand" "=f")
922 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
923 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
926 [(set_attr "type" "fpop")])
928 (define_insn "adddf3"
929 [(set (match_operand:DF 0 "register_operand" "=f")
930 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
931 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
934 [(set_attr "type" "fpop")])
937 [(set (match_operand:DF 0 "register_operand" "=f")
938 (plus:DF (float_extend:DF
939 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
940 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
943 [(set_attr "type" "fpop")])
946 [(set (match_operand:DF 0 "register_operand" "=f")
947 (plus:DF (float_extend:DF
948 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
950 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
953 [(set_attr "type" "fpop")])
955 (define_insn "fix_truncdfdi2"
956 [(set (match_operand:DI 0 "register_operand" "=f")
957 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
960 [(set_attr "type" "fpop")])
962 (define_insn "fix_truncsfdi2"
963 [(set (match_operand:DI 0 "register_operand" "=f")
964 (fix:DI (float_extend:DF
965 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
968 [(set_attr "type" "fpop")])
970 (define_insn "floatdisf2"
971 [(set (match_operand:SF 0 "register_operand" "=f")
972 (float:SF (match_operand:DI 1 "register_operand" "f")))]
975 [(set_attr "type" "fpop")])
977 (define_insn "floatdidf2"
978 [(set (match_operand:DF 0 "register_operand" "=f")
979 (float:DF (match_operand:DI 1 "register_operand" "f")))]
982 [(set_attr "type" "fpop")])
984 (define_insn "extendsfdf2"
985 [(set (match_operand:DF 0 "register_operand" "=f,f")
986 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
991 [(set_attr "type" "fpop,ld")])
993 (define_insn "truncdfsf2"
994 [(set (match_operand:SF 0 "register_operand" "=f")
995 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
998 [(set_attr "type" "fpop")])
1000 (define_insn "divsf3"
1001 [(set (match_operand:SF 0 "register_operand" "=f")
1002 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1003 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1006 [(set_attr "type" "fdivs")])
1008 (define_insn "divdf3"
1009 [(set (match_operand:DF 0 "register_operand" "=f")
1010 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1011 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1014 [(set_attr "type" "fdivt")])
1017 [(set (match_operand:DF 0 "register_operand" "=f")
1018 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1019 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1022 [(set_attr "type" "fdivt")])
1025 [(set (match_operand:DF 0 "register_operand" "=f")
1026 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1028 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1031 [(set_attr "type" "fdivt")])
1034 [(set (match_operand:DF 0 "register_operand" "=f")
1035 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1036 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1039 [(set_attr "type" "fdivt")])
1041 (define_insn "mulsf3"
1042 [(set (match_operand:SF 0 "register_operand" "=f")
1043 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1044 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1047 [(set_attr "type" "fpop")])
1049 (define_insn "muldf3"
1050 [(set (match_operand:DF 0 "register_operand" "=f")
1051 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1052 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1055 [(set_attr "type" "fpop")])
1058 [(set (match_operand:DF 0 "register_operand" "=f")
1059 (mult:DF (float_extend:DF
1060 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1061 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1064 [(set_attr "type" "fpop")])
1067 [(set (match_operand:DF 0 "register_operand" "=f")
1068 (mult:DF (float_extend:DF
1069 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1071 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1074 [(set_attr "type" "fpop")])
1076 (define_insn "subsf3"
1077 [(set (match_operand:SF 0 "register_operand" "=f")
1078 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1079 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1082 [(set_attr "type" "fpop")])
1084 (define_insn "subdf3"
1085 [(set (match_operand:DF 0 "register_operand" "=f")
1086 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1087 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1090 [(set_attr "type" "fpop")])
1093 [(set (match_operand:DF 0 "register_operand" "=f")
1094 (minus:DF (float_extend:DF
1095 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1096 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1099 [(set_attr "type" "fpop")])
1102 [(set (match_operand:DF 0 "register_operand" "=f")
1103 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1105 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1108 [(set_attr "type" "fpop")])
1111 [(set (match_operand:DF 0 "register_operand" "=f")
1112 (minus:DF (float_extend:DF
1113 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1115 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1118 [(set_attr "type" "fpop")])
1120 ;; Next are all the integer comparisons, and conditional moves and branches
1121 ;; and some of the related define_expand's and define_split's.
1124 [(set (match_operand:DI 0 "register_operand" "=r")
1125 (match_operator:DI 1 "alpha_comparison_operator"
1126 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1127 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
1130 [(set_attr "type" "icmp")])
1132 ;; There are three important special-case that don't fit the above pattern
1133 ;; but which we want to handle here.
1136 [(set (match_operand:DI 0 "register_operand" "=r")
1137 (ne:DI (match_operand:DI 1 "register_operand" "r")
1141 [(set_attr "type" "icmp")])
1144 [(set (match_operand:DI 0 "register_operand" "=r")
1145 (gt:DI (match_operand:DI 1 "register_operand" "r")
1149 [(set_attr "type" "icmp")])
1152 [(set (match_operand:DI 0 "register_operand" "=r")
1153 (ge:DI (match_operand:DI 1 "register_operand" "r")
1157 [(set_attr "type" "icmp")])
1160 [(set (match_operand:DI 0 "register_operand" "=r,r")
1162 (match_operator 2 "signed_comparison_operator"
1163 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ")
1165 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1166 (match_operand:DI 4 "reg_or_8bit_operand" "0,rI")))]
1173 [(set (match_operand:DI 0 "register_operand" "=r,r")
1175 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1179 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1180 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1187 [(set (match_operand:DI 0 "register_operand" "=r,r")
1189 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1193 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1194 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1200 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
1201 ;; arms constant is a single insn, so it won't try to form it if combine
1202 ;; knows they are really two insns. This occurs in divides by powers
1206 [(set (match_operand:DI 0 "register_operand" "=r")
1208 (match_operator 2 "signed_comparison_operator"
1209 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
1211 (plus:DI (match_dup 0)
1212 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1214 (clobber (match_scratch:DI 4 "=&r"))]
1216 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0")
1219 [(set (match_operand:DI 0 "register_operand" "")
1221 (match_operator 2 "signed_comparison_operator"
1222 [(match_operand:DI 3 "reg_or_0_operand" "")
1224 (plus:DI (match_dup 0)
1225 (match_operand:DI 1 "reg_or_8bit_operand" ""))
1227 (clobber (match_operand:DI 4 "register_operand" ""))]
1229 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
1230 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
1233 (match_dup 4) (match_dup 0)))]
1238 [(set (match_operand:DI 0 "register_operand" "")
1240 (match_operator 1 "comparison_operator"
1241 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1243 (match_operand:DI 3 "const_int_operand" ""))
1245 (match_operand:DI 4 "reg_or_8bit_operand" "")
1246 (match_operand:DI 5 "reg_or_8bit_operand" "")))
1247 (clobber (match_operand:DI 6 "register_operand" ""))])]
1248 "INTVAL (operands[3]) != 0"
1250 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1252 (if_then_else:DI (match_op_dup 1
1253 [(zero_extract:DI (match_dup 6)
1261 ;; For ABS, we have two choices, depending on whether the input and output
1262 ;; registers are the same or not.
1263 (define_expand "absdi2"
1264 [(set (match_operand:DI 0 "register_operand" "")
1265 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1268 { if (rtx_equal_p (operands[0], operands[1]))
1269 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
1271 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
1276 (define_expand "absdi2_same"
1277 [(set (match_operand:DI 1 "register_operand" "")
1278 (neg:DI (match_operand:DI 0 "register_operand" "")))
1280 (if_then_else:DI (ge (match_dup 0) (const_int 0))
1286 (define_expand "absdi2_diff"
1287 [(set (match_operand:DI 0 "register_operand" "")
1288 (neg:DI (match_operand:DI 1 "register_operand" "")))
1290 (if_then_else:DI (lt (match_dup 1) (const_int 0))
1297 [(set (match_operand:DI 0 "register_operand" "")
1298 (abs:DI (match_dup 0)))
1299 (clobber (match_operand:DI 2 "register_operand" ""))]
1301 [(set (match_dup 1) (neg:DI (match_dup 0)))
1302 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
1303 (match_dup 0) (match_dup 1)))]
1307 [(set (match_operand:DI 0 "register_operand" "")
1308 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1309 "! rtx_equal_p (operands[0], operands[1])"
1310 [(set (match_dup 0) (neg:DI (match_dup 1)))
1311 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
1312 (match_dup 0) (match_dup 1)))]
1316 [(set (match_operand:DI 0 "register_operand" "")
1317 (neg:DI (abs:DI (match_dup 0))))
1318 (clobber (match_operand:DI 2 "register_operand" ""))]
1320 [(set (match_dup 1) (neg:DI (match_dup 0)))
1321 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
1322 (match_dup 0) (match_dup 1)))]
1326 [(set (match_operand:DI 0 "register_operand" "")
1327 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
1328 "! rtx_equal_p (operands[0], operands[1])"
1329 [(set (match_dup 0) (neg:DI (match_dup 1)))
1330 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
1331 (match_dup 0) (match_dup 1)))]
1334 (define_expand "smaxdi3"
1336 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
1337 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1338 (set (match_operand:DI 0 "register_operand" "")
1339 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1340 (match_dup 1) (match_dup 2)))]
1343 { operands[3] = gen_reg_rtx (DImode);
1347 [(set (match_operand:DI 0 "register_operand" "")
1348 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1349 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1350 (clobber (match_operand:DI 3 "register_operand" ""))]
1351 "operands[2] != const0_rtx"
1352 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
1353 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1354 (match_dup 1) (match_dup 2)))]
1358 [(set (match_operand:DI 0 "register_operand" "=r")
1359 (smax:DI (match_operand:DI 1 "register_operand" "0")
1364 (define_expand "smindi3"
1366 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
1367 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1368 (set (match_operand:DI 0 "register_operand" "")
1369 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1370 (match_dup 1) (match_dup 2)))]
1373 { operands[3] = gen_reg_rtx (DImode);
1377 [(set (match_operand:DI 0 "register_operand" "")
1378 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1379 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1380 (clobber (match_operand:DI 3 "register_operand" ""))]
1381 "operands[2] != const0_rtx"
1382 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
1383 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1384 (match_dup 1) (match_dup 2)))]
1388 [(set (match_operand:DI 0 "register_operand" "=r")
1389 (smin:DI (match_operand:DI 1 "register_operand" "0")
1394 (define_expand "umaxdi3"
1396 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1397 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1398 (set (match_operand:DI 0 "register_operand" "")
1399 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1400 (match_dup 1) (match_dup 2)))]
1403 { operands[3] = gen_reg_rtx (DImode);
1407 [(set (match_operand:DI 0 "register_operand" "")
1408 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1409 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1410 (clobber (match_operand:DI 3 "register_operand" ""))]
1411 "operands[2] != const0_rtx"
1412 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
1413 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1414 (match_dup 1) (match_dup 2)))]
1417 (define_expand "umindi3"
1419 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1420 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1421 (set (match_operand:DI 0 "register_operand" "")
1422 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1423 (match_dup 1) (match_dup 2)))]
1426 { operands[3] = gen_reg_rtx (DImode);
1430 [(set (match_operand:DI 0 "register_operand" "")
1431 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1432 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1433 (clobber (match_operand:DI 3 "register_operand" ""))]
1434 "operands[2] != const0_rtx"
1435 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
1436 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1437 (match_dup 1) (match_dup 2)))]
1443 (match_operator 1 "signed_comparison_operator"
1444 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1446 (label_ref (match_operand 0 "" ""))
1450 [(set_attr "type" "ibr")])
1455 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1459 (label_ref (match_operand 0 "" ""))
1463 [(set_attr "type" "ibr")])
1468 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1472 (label_ref (match_operand 0 "" ""))
1476 [(set_attr "type" "ibr")])
1482 (match_operator 1 "comparison_operator"
1483 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1485 (match_operand:DI 3 "const_int_operand" ""))
1487 (label_ref (match_operand 0 "" ""))
1489 (clobber (match_operand:DI 4 "register_operand" ""))])]
1490 "INTVAL (operands[3]) != 0"
1492 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1494 (if_then_else (match_op_dup 1
1495 [(zero_extract:DI (match_dup 4)
1499 (label_ref (match_dup 0))
1503 ;; The following are the corresponding floating-point insns. Recall
1504 ;; we need to have variants that expand the arguments from SF mode
1508 [(set (match_operand:DF 0 "register_operand" "=f")
1509 (match_operator:DF 1 "alpha_comparison_operator"
1510 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1511 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1513 "cmpt%C1 %R2,%R3,%0"
1514 [(set_attr "type" "fpop")])
1517 [(set (match_operand:DF 0 "register_operand" "=f")
1518 (match_operator:DF 1 "alpha_comparison_operator"
1520 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1521 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1523 "cmpt%C1 %R2,%R3,%0"
1524 [(set_attr "type" "fpop")])
1527 [(set (match_operand:DF 0 "register_operand" "=f")
1528 (match_operator:DF 1 "alpha_comparison_operator"
1529 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1531 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1533 "cmpt%C1 %R2,%R3,%0"
1534 [(set_attr "type" "fpop")])
1537 [(set (match_operand:DF 0 "register_operand" "=f")
1538 (match_operator:DF 1 "alpha_comparison_operator"
1540 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1542 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1544 "cmpt%C1 %R2,%R3,%0"
1545 [(set_attr "type" "fpop")])
1548 [(set (match_operand:DF 0 "register_operand" "=f,f")
1550 (match_operator 3 "signed_comparison_operator"
1551 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1552 (match_operand:DF 2 "fp0_operand" "G,G")])
1553 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1554 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1558 fcmov%D3 %R4,%R5,%0"
1559 [(set_attr "type" "fpop")])
1562 [(set (match_operand:SF 0 "register_operand" "=f,f")
1564 (match_operator 3 "signed_comparison_operator"
1565 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1566 (match_operand:DF 2 "fp0_operand" "G,G")])
1567 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1568 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1572 fcmov%D3 %R4,%R5,%0"
1573 [(set_attr "type" "fpop")])
1576 [(set (match_operand:DF 0 "register_operand" "=f,f")
1578 (match_operator 3 "signed_comparison_operator"
1579 [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG")
1580 (match_operand:DF 2 "fp0_operand" "G,G")])
1581 (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0"))
1582 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1586 fcmov%D3 %R4,%R5,%0"
1587 [(set_attr "type" "fpop")])
1590 [(set (match_operand:DF 0 "register_operand" "=f,f")
1592 (match_operator 3 "signed_comparison_operator"
1594 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1595 (match_operand:DF 2 "fp0_operand" "G,G")])
1596 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1597 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1601 fcmov%D3 %R4,%R5,%0"
1602 [(set_attr "type" "fpop")])
1605 [(set (match_operand:SF 0 "register_operand" "=f,f")
1607 (match_operator 3 "signed_comparison_operator"
1609 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1610 (match_operand:DF 2 "fp0_operand" "G,G")])
1611 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1612 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1616 fcmov%D3 %R4,%R5,%0"
1617 [(set_attr "type" "fpop")])
1620 [(set (match_operand:DF 0 "register_operand" "=f,f")
1622 (match_operator 3 "signed_comparison_operator"
1624 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1625 (match_operand:DF 2 "fp0_operand" "G,G")])
1626 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
1627 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1631 fcmov%D3 %R4,%R5,%0"
1632 [(set_attr "type" "fpop")])
1634 (define_expand "maxdf3"
1636 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1637 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1638 (set (match_operand:DF 0 "register_operand" "")
1639 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
1640 (match_dup 1) (match_dup 2)))]
1643 { operands[3] = gen_reg_rtx (DFmode);
1644 operands[4] = CONST0_RTX (DFmode);
1647 (define_expand "mindf3"
1649 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1650 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1651 (set (match_operand:DF 0 "register_operand" "")
1652 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
1653 (match_dup 1) (match_dup 2)))]
1656 { operands[3] = gen_reg_rtx (DFmode);
1657 operands[4] = CONST0_RTX (DFmode);
1660 (define_expand "maxsf3"
1662 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1663 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1664 (set (match_operand:SF 0 "register_operand" "")
1665 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
1666 (match_dup 1) (match_dup 2)))]
1669 { operands[3] = gen_reg_rtx (DFmode);
1670 operands[4] = CONST0_RTX (DFmode);
1673 (define_expand "minsf3"
1675 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1676 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1677 (set (match_operand:SF 0 "register_operand" "")
1678 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
1679 (match_dup 1) (match_dup 2)))]
1682 { operands[3] = gen_reg_rtx (DFmode);
1683 operands[4] = CONST0_RTX (DFmode);
1689 (match_operator 1 "signed_comparison_operator"
1690 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1691 (match_operand:DF 3 "fp0_operand" "G")])
1692 (label_ref (match_operand 0 "" ""))
1696 [(set_attr "type" "fbr")])
1701 (match_operator 1 "signed_comparison_operator"
1703 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1704 (match_operand:DF 3 "fp0_operand" "G")])
1705 (label_ref (match_operand 0 "" ""))
1709 [(set_attr "type" "fbr")])
1711 ;; These are the main define_expand's used to make conditional branches
1714 (define_expand "cmpdf"
1715 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
1716 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
1720 alpha_compare_op0 = operands[0];
1721 alpha_compare_op1 = operands[1];
1722 alpha_compare_fp_p = 1;
1726 (define_expand "cmpdi"
1727 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
1728 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
1732 alpha_compare_op0 = operands[0];
1733 alpha_compare_op1 = operands[1];
1734 alpha_compare_fp_p = 0;
1738 (define_expand "beq"
1739 [(set (match_dup 1) (match_dup 2))
1741 (if_then_else (match_dup 3)
1742 (label_ref (match_operand 0 "" ""))
1747 enum machine_mode mode;
1748 enum rtx_code compare_code, branch_code;
1750 if (alpha_compare_fp_p)
1751 mode = DFmode, compare_code = EQ, branch_code = NE;
1754 mode = DImode, compare_code = MINUS, branch_code = EQ;
1755 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1757 compare_code = PLUS;
1758 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1762 operands[1] = gen_reg_rtx (mode);
1763 operands[2] = gen_rtx (compare_code, mode,
1764 alpha_compare_op0, alpha_compare_op1);
1765 operands[3] = gen_rtx (branch_code, VOIDmode,
1766 operands[1], CONST0_RTX (mode));
1769 (define_expand "bne"
1770 [(set (match_dup 1) (match_dup 2))
1772 (if_then_else (match_dup 3)
1773 (label_ref (match_operand 0 "" ""))
1778 enum machine_mode mode;
1779 enum rtx_code compare_code, branch_code;
1781 if (alpha_compare_fp_p)
1782 mode = DFmode, compare_code = EQ, branch_code = EQ;
1785 mode = DImode, compare_code = MINUS, branch_code = NE;
1786 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1788 compare_code = PLUS;
1789 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1793 operands[1] = gen_reg_rtx (mode);
1794 operands[2] = gen_rtx (compare_code, mode,
1795 alpha_compare_op0, alpha_compare_op1);
1796 operands[3] = gen_rtx (branch_code, VOIDmode,
1797 operands[1], CONST0_RTX (mode));
1800 (define_expand "blt"
1801 [(set (match_dup 1) (match_dup 2))
1803 (if_then_else (match_dup 3)
1804 (label_ref (match_operand 0 "" ""))
1809 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1810 operands[1] = gen_reg_rtx (mode);
1811 operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
1812 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1815 (define_expand "ble"
1816 [(set (match_dup 1) (match_dup 2))
1818 (if_then_else (match_dup 3)
1819 (label_ref (match_operand 0 "" ""))
1824 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1825 operands[1] = gen_reg_rtx (mode);
1826 operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
1827 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1830 (define_expand "bgt"
1831 [(set (match_dup 1) (match_dup 2))
1833 (if_then_else (match_dup 3)
1834 (label_ref (match_operand 0 "" ""))
1839 if (alpha_compare_fp_p)
1841 operands[1] = gen_reg_rtx (DFmode);
1842 operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
1843 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
1847 operands[1] = gen_reg_rtx (DImode);
1848 operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
1849 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1853 (define_expand "bge"
1854 [(set (match_dup 1) (match_dup 2))
1856 (if_then_else (match_dup 3)
1857 (label_ref (match_operand 0 "" ""))
1862 if (alpha_compare_fp_p)
1864 operands[1] = gen_reg_rtx (DFmode);
1865 operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
1866 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
1870 operands[1] = gen_reg_rtx (DImode);
1871 operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
1872 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1876 (define_expand "bltu"
1877 [(set (match_dup 1) (match_dup 2))
1879 (if_then_else (match_dup 3)
1880 (label_ref (match_operand 0 "" ""))
1885 operands[1] = gen_reg_rtx (DImode);
1886 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
1887 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
1890 (define_expand "bleu"
1891 [(set (match_dup 1) (match_dup 2))
1893 (if_then_else (match_dup 3)
1894 (label_ref (match_operand 0 "" ""))
1899 operands[1] = gen_reg_rtx (DImode);
1900 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
1901 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
1904 (define_expand "bgtu"
1905 [(set (match_dup 1) (match_dup 2))
1907 (if_then_else (match_dup 3)
1908 (label_ref (match_operand 0 "" ""))
1913 operands[1] = gen_reg_rtx (DImode);
1914 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
1915 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1918 (define_expand "bgeu"
1919 [(set (match_dup 1) (match_dup 2))
1921 (if_then_else (match_dup 3)
1922 (label_ref (match_operand 0 "" ""))
1927 operands[1] = gen_reg_rtx (DImode);
1928 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
1929 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1932 (define_expand "seq"
1933 [(set (match_operand:DI 0 "register_operand" "")
1938 if (alpha_compare_fp_p)
1941 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
1944 (define_expand "sne"
1945 [(set (match_operand:DI 0 "register_operand" "")
1947 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
1951 if (alpha_compare_fp_p)
1954 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
1957 (define_expand "slt"
1958 [(set (match_operand:DI 0 "register_operand" "")
1963 if (alpha_compare_fp_p)
1966 operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
1969 (define_expand "sle"
1970 [(set (match_operand:DI 0 "register_operand" "")
1975 if (alpha_compare_fp_p)
1978 operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
1981 (define_expand "sgt"
1982 [(set (match_operand:DI 0 "register_operand" "")
1987 if (alpha_compare_fp_p)
1990 operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
1994 (define_expand "sge"
1995 [(set (match_operand:DI 0 "register_operand" "")
2000 if (alpha_compare_fp_p)
2003 operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
2007 (define_expand "sltu"
2008 [(set (match_operand:DI 0 "register_operand" "")
2013 if (alpha_compare_fp_p)
2016 operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2019 (define_expand "sleu"
2020 [(set (match_operand:DI 0 "register_operand" "")
2025 if (alpha_compare_fp_p)
2028 operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2031 (define_expand "sgtu"
2032 [(set (match_operand:DI 0 "register_operand" "")
2037 if (alpha_compare_fp_p)
2040 operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
2044 (define_expand "sgeu"
2045 [(set (match_operand:DI 0 "register_operand" "")
2050 if (alpha_compare_fp_p)
2053 operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
2057 ;; These define_split definitions are used in cases when comparisons have
2058 ;; not be stated in the correct way and we need to reverse the second
2059 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
2060 ;; comparison that tests the result being reversed. We have one define_split
2061 ;; for each use of a comparison. They do not match valid insns and need
2062 ;; not generate valid insns.
2064 ;; We can also handle equality comparisons (and inequality comparisons in
2065 ;; cases where the resulting add cannot overflow) by doing an add followed by
2066 ;; a comparison with zero. This is faster since the addition takes one
2067 ;; less cycle than a compare when feeding into a conditional move.
2068 ;; For this case, we also have an SImode pattern since we can merge the add
2069 ;; and sign extend and the order doesn't matter.
2071 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2072 ;; operation could have been generated.
2075 [(set (match_operand:DI 0 "register_operand" "")
2077 (match_operator 1 "comparison_operator"
2078 [(match_operand:DI 2 "reg_or_0_operand" "")
2079 (match_operand:DI 3 "reg_or_cint_operand" "")])
2080 (match_operand:DI 4 "reg_or_cint_operand" "")
2081 (match_operand:DI 5 "reg_or_cint_operand" "")))
2082 (clobber (match_operand:DI 6 "register_operand" ""))]
2083 "operands[3] != const0_rtx"
2084 [(set (match_dup 6) (match_dup 7))
2086 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2088 { enum rtx_code code = GET_CODE (operands[1]);
2089 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2091 /* If we are comparing for equality with a constant and that constant
2092 appears in the arm when the register equals the constant, use the
2093 register since that is more likely to match (and to produce better code
2096 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
2097 && rtx_equal_p (operands[4], operands[3]))
2098 operands[4] = operands[2];
2100 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
2101 && rtx_equal_p (operands[5], operands[3]))
2102 operands[5] = operands[2];
2104 if (code == NE || code == EQ
2105 || (extended_count (operands[2], DImode, unsignedp) >= 1
2106 && extended_count (operands[3], DImode, unsignedp) >= 1))
2108 if (GET_CODE (operands[3]) == CONST_INT)
2109 operands[7] = gen_rtx (PLUS, DImode, operands[2],
2110 GEN_INT (- INTVAL (operands[3])));
2112 operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2114 operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
2117 else if (code == EQ || code == LE || code == LT
2118 || code == LEU || code == LTU)
2120 operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
2121 operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
2125 operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
2127 operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
2132 [(set (match_operand:DI 0 "register_operand" "")
2134 (match_operator 1 "comparison_operator"
2135 [(match_operand:SI 2 "reg_or_0_operand" "")
2136 (match_operand:SI 3 "reg_or_cint_operand" "")])
2137 (match_operand:DI 4 "reg_or_8bit_operand" "")
2138 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2139 (clobber (match_operand:DI 6 "register_operand" ""))]
2140 "operands[3] != const0_rtx
2141 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2142 [(set (match_dup 6) (match_dup 7))
2144 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2146 { enum rtx_code code = GET_CODE (operands[1]);
2147 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2150 if ((code != NE && code != EQ
2151 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
2152 && extended_count (operands[3], DImode, unsignedp) >= 1)))
2155 if (GET_CODE (operands[3]) == CONST_INT)
2156 tem = gen_rtx (PLUS, SImode, operands[2],
2157 GEN_INT (- INTVAL (operands[3])));
2159 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2161 operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem);
2162 operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
2169 (match_operator 1 "comparison_operator"
2170 [(match_operand:DI 2 "reg_or_0_operand" "")
2171 (match_operand:DI 3 "reg_or_cint_operand" "")])
2172 (label_ref (match_operand 0 "" ""))
2174 (clobber (match_operand:DI 4 "register_operand" ""))]
2175 "operands[3] != const0_rtx"
2176 [(set (match_dup 4) (match_dup 5))
2177 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2179 { enum rtx_code code = GET_CODE (operands[1]);
2180 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2182 if (code == NE || code == EQ
2183 || (extended_count (operands[2], DImode, unsignedp) >= 1
2184 && extended_count (operands[3], DImode, unsignedp) >= 1))
2186 if (GET_CODE (operands[3]) == CONST_INT)
2187 operands[5] = gen_rtx (PLUS, DImode, operands[2],
2188 GEN_INT (- INTVAL (operands[3])));
2190 operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2192 operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
2195 else if (code == EQ || code == LE || code == LT
2196 || code == LEU || code == LTU)
2198 operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
2199 operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
2203 operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
2205 operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
2212 (match_operator 1 "comparison_operator"
2213 [(match_operand:SI 2 "reg_or_0_operand" "")
2214 (match_operand:SI 3 "const_int_operand" "")])
2215 (label_ref (match_operand 0 "" ""))
2217 (clobber (match_operand:DI 4 "register_operand" ""))]
2218 "operands[3] != const0_rtx
2219 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2220 [(set (match_dup 4) (match_dup 5))
2221 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2225 if (GET_CODE (operands[3]) == CONST_INT)
2226 tem = gen_rtx (PLUS, SImode, operands[2],
2227 GEN_INT (- INTVAL (operands[3])));
2229 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2231 operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem);
2232 operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
2233 operands[4], const0_rtx);
2236 ;; Here are the CALL and unconditional branch insns.
2238 (define_expand "call"
2239 [(parallel [(call (mem:DI (match_dup 2))
2240 (match_operand 1 "" ""))
2241 (use (match_operand:DI 0 "" ""))
2242 (clobber (reg:DI 26))])]
2245 { if (GET_CODE (operands[0]) != MEM)
2247 operands[0] = XEXP (operands[0], 0);
2249 operands[2] = gen_rtx (REG, DImode, 27);
2250 emit_move_insn (operands[2], operands[0]);
2252 if (GET_CODE (operands[0]) != SYMBOL_REF)
2253 operands[0] = const0_rtx;
2256 (define_expand "call_value"
2257 [(parallel [(set (match_operand 0 "" "")
2258 (call (mem:DI (match_dup 3))
2259 (match_operand 2 "" "")))
2260 (use (match_operand:DI 1 "" ""))
2261 (clobber (reg:DI 26))])]
2264 { if (GET_CODE (operands[1]) != MEM)
2267 operands[1] = XEXP (operands[1], 0);
2269 operands[3] = gen_rtx (REG, DImode, 27);
2270 emit_move_insn (operands[3], operands[1]);
2272 if (GET_CODE (operands[1]) != SYMBOL_REF)
2273 operands[1] = const0_rtx;
2277 [(call (mem:DI (reg:DI 27))
2278 (match_operand 0 "" ""))
2279 (use (match_operand:DI 1 "" ""))
2280 (clobber (reg:DI 26))]
2282 "jsr $26,($27),%1\;ldgp $29,0($26)"
2283 [(set_attr "type" "jsr")])
2286 [(set (match_operand 0 "register_operand" "=rf")
2287 (call (mem:DI (reg:DI 27))
2288 (match_operand 1 "" "")))
2289 (use (match_operand:DI 2 "" ""))
2290 (clobber (reg:DI 26))]
2292 "jsr $26,($27),%2\;ldgp $29,0($26)"
2293 [(set_attr "type" "jsr")])
2296 [(call (mem:DI (match_operand 1 "current_file_function_operand" "i"))
2297 (match_operand 0 "" ""))
2299 (clobber (reg:DI 26))]
2302 [(set_attr "type" "ibr")])
2305 [(set (match_operand 0 "register_operand" "=rf")
2306 (call (mem:DI (match_operand 1 "current_file_function_operand" "i"))
2307 (match_operand 2 "" "")))
2309 (clobber (reg:DI 26))]
2312 [(set_attr "type" "ibr")])
2314 ;; Call subroutine returning any type.
2316 (define_expand "untyped_call"
2317 [(parallel [(call (match_operand 0 "" "")
2319 (match_operand 1 "" "")
2320 (match_operand 2 "" "")])]
2326 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2328 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2330 rtx set = XVECEXP (operands[2], 0, i);
2331 emit_move_insn (SET_DEST (set), SET_SRC (set));
2334 /* The optimizer does not know that the call sets the function value
2335 registers we stored in the result block. We avoid problems by
2336 claiming that all hard registers are used and clobbered at this
2338 emit_insn (gen_blockage ());
2343 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2344 ;; all of memory. This blocks insns from being moved across this point.
2346 (define_insn "blockage"
2347 [(unspec_volatile [(const_int 0)] 1)]
2353 (label_ref (match_operand 0 "" "")))]
2356 [(set_attr "type" "ibr")])
2358 (define_insn "return"
2362 [(set_attr "type" "ibr")])
2364 (define_insn "indirect_jump"
2365 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
2368 [(set_attr "type" "ibr")])
2374 [(set_attr "type" "iaddlog")])
2376 (define_expand "tablejump"
2378 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2379 (parallel [(set (pc) (plus:DI (match_dup 3) (reg:DI 29)))
2380 (use (label_ref (match_operand 1 "" "")))
2381 (clobber (match_scratch:DI 2 "=r"))])]
2384 { operands[3] = gen_reg_rtx (DImode); }")
2388 (plus:DI (match_operand:DI 0 "register_operand" "r")
2390 (use (label_ref (match_operand 1 "" "")))
2391 (clobber (match_scratch:DI 2 "=r"))]
2394 { rtx best_label = 0;
2395 rtx jump_table_insn = next_active_insn (operands[1]);
2397 if (GET_CODE (jump_table_insn) == JUMP_INSN
2398 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_VEC)
2400 rtx jump_table = PATTERN (jump_table_insn);
2401 int n_labels = XVECLEN (jump_table, 0);
2402 int best_count = -1;
2405 for (i = 0; i < n_labels; i++)
2409 for (j = i + 1; j < n_labels; j++)
2410 if (XEXP (XVECEXP (jump_table, 0, i), 0)
2411 == XEXP (XVECEXP (jump_table, 0, j), 0))
2414 if (count > best_count)
2415 best_count = count, best_label = XVECEXP (jump_table, 0, i);
2421 operands[3] = best_label;
2422 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
2425 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
2427 [(set_attr "type" "ibr")])
2429 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
2430 ;; want to have to include pal.h in our .s file.
2432 [(unspec_volatile [(const_int 0)] 0)]
2436 ;; Finally, we have the basic data motion insns. The byte and word insns
2437 ;; are done via define_expand. Start with the floating-point insns, since
2438 ;; they are simpler.
2441 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2442 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2443 "register_operand (operands[0], SFmode)
2444 || reg_or_fp0_operand (operands[1], SFmode)"
2453 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2456 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2457 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2458 "register_operand (operands[0], DFmode)
2459 || reg_or_fp0_operand (operands[1], DFmode)"
2468 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2470 (define_expand "movsf"
2471 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2472 (match_operand:SF 1 "general_operand" ""))]
2476 if (GET_CODE (operands[0]) == MEM
2477 && ! reg_or_fp0_operand (operands[1], SFmode))
2478 operands[1] = force_reg (SFmode, operands[1]);
2481 (define_expand "movdf"
2482 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2483 (match_operand:DF 1 "general_operand" ""))]
2487 if (GET_CODE (operands[0]) == MEM
2488 && ! reg_or_fp0_operand (operands[1], DFmode))
2489 operands[1] = force_reg (DFmode, operands[1]);
2492 ;; There is a problem with 32-bit values in FP registers. We keep such
2493 ;; values in the register as a quadword. This is done on loads by using
2494 ;; the cvtlq instruction. On stores, we can't do anything directly from
2495 ;; floating-point registers. Disallow such an operation and let reload
2496 ;; use an integer register instead. Don't encourage 32-bit values to
2497 ;; be placed in FP registers at all.
2500 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,*f")
2501 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,*f,J,m"))]
2502 "register_operand (operands[0], SImode)
2503 || reg_or_0_operand (operands[1], SImode)"
2514 lds %0,%1\;cvtlq %0,%0"
2515 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld")])
2518 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
2519 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
2520 "register_operand (operands[0], HImode)
2521 || register_operand (operands[1], HImode)"
2529 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
2532 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
2533 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
2534 "register_operand (operands[0], QImode)
2535 || register_operand (operands[1], QImode)"
2543 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
2545 ;; We do two major things here: handle mem->mem and construct long
2548 (define_expand "movsi"
2549 [(set (match_operand:SI 0 "general_operand" "")
2550 (match_operand:SI 1 "general_operand" ""))]
2554 if (GET_CODE (operands[0]) == MEM
2555 && ! reg_or_0_operand (operands[1], SImode))
2556 operands[1] = force_reg (SImode, operands[1]);
2558 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
2560 else if (GET_CODE (operands[1]) == CONST_INT)
2562 if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3))
2569 ;; Split a load of a large constant into the appropriate two-insn
2573 [(set (match_operand:SI 0 "register_operand" "")
2574 (match_operand:SI 1 "const_int_operand" ""))]
2575 "! add_operand (operands[1], SImode)"
2576 [(set (match_dup 0) (match_dup 2))
2577 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
2579 { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2))
2586 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
2587 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
2588 "register_operand (operands[0], DImode)
2589 || reg_or_0_operand (operands[1], DImode)"
2603 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
2605 ;; We do three major things here: handle mem->mem, put 64-bit constants in
2606 ;; memory, and construct long 32-bit constants.
2608 (define_expand "movdi"
2609 [(set (match_operand:DI 0 "general_operand" "")
2610 (match_operand:DI 1 "general_operand" ""))]
2614 if (GET_CODE (operands[0]) == MEM
2615 && ! reg_or_0_operand (operands[1], DImode))
2616 operands[1] = force_reg (DImode, operands[1]);
2618 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
2620 else if (GET_CODE (operands[1]) == CONST_INT
2621 && alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3))
2623 else if (CONSTANT_P (operands[1]))
2625 operands[1] = force_const_mem (DImode, operands[1]);
2626 if (reload_in_progress)
2628 emit_move_insn (operands[0], XEXP (operands[1], 0));
2629 XEXP (operands[1], 0) = operands[0];
2632 operands[1] = validize_mem (operands[1]);
2638 ;; Split a load of a large constant into the appropriate two-insn
2642 [(set (match_operand:DI 0 "register_operand" "")
2643 (match_operand:DI 1 "const_int_operand" ""))]
2644 "! add_operand (operands[1], DImode)"
2645 [(set (match_dup 0) (match_dup 2))
2646 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
2648 { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2))
2654 ;; These are the partial-word cases.
2656 ;; First we have the code to load an aligned word. Operand 0 is the register
2657 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
2658 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
2659 ;; number of bits within the word that the value is. Operand 3 is an SImode
2660 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
2661 ;; same register. It is allowed to conflict with operand 1 as well.
2663 (define_expand "aligned_loadqi"
2664 [(set (match_operand:SI 3 "register_operand" "")
2665 (match_operand:SI 1 "memory_operand" ""))
2666 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
2667 (zero_extract:DI (subreg:DI (match_dup 3) 0)
2669 (match_operand:DI 2 "const_int_operand" "")))]
2674 (define_expand "aligned_loadhi"
2675 [(set (match_operand:SI 3 "register_operand" "")
2676 (match_operand:SI 1 "memory_operand" ""))
2677 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
2678 (zero_extract:DI (subreg:DI (match_dup 3) 0)
2680 (match_operand:DI 2 "const_int_operand" "")))]
2685 ;; Similar for unaligned loads. For QImode, we use the sequence from the
2686 ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers
2687 ;; are normally aligned to the byte boundary, so an HImode object cannot
2688 ;; cross a longword boundary. We could use a sequence similar to that for
2689 ;; QImode, but that would fail if the pointer, was, in fact, not aligned.
2690 ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order
2691 ;; bit was not aligned, this will trap and the trap handler will do what is
2694 ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where
2695 ;; operand 3 can overlap the input and output registers.
2697 (define_expand "unaligned_loadqi"
2698 [(set (match_operand:DI 2 "register_operand" "")
2699 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
2701 (set (match_operand:DI 3 "register_operand" "")
2703 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
2704 (zero_extract:DI (match_dup 2)
2706 (ashift:DI (match_dup 3) (const_int 3))))]
2710 ;; For this, the address must already be in a register. We also need two
2711 ;; DImode temporaries, neither of which may overlap the input (and hence the
2712 ;; output, since they might be the same register), but both of which may
2715 (define_expand "unaligned_loadhi"
2716 [(set (match_operand:DI 2 "register_operand" "")
2717 (and:DI (match_operand:DI 1 "register_operand" "")
2719 (set (match_operand:DI 3 "register_operand" "")
2720 (mem:DI (match_dup 2)))
2721 (set (match_operand:DI 4 "register_operand" "")
2722 (and:DI (match_dup 1) (const_int -2)))
2723 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
2724 (zero_extract:DI (match_dup 3)
2726 (ashift:DI (match_dup 4) (const_int 3))))]
2730 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
2731 ;; aligned SImode MEM. Operand 1 is the register containing the
2732 ;; byte or word to store. Operand 2 is the number of bits within the word that
2733 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
2735 (define_expand "aligned_store"
2736 [(set (match_operand:SI 3 "register_operand" "")
2737 (match_operand:SI 0 "memory_operand" ""))
2738 (set (subreg:DI (match_dup 3) 0)
2739 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
2740 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
2741 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
2742 (match_operand:DI 2 "const_int_operand" "")))
2743 (set (subreg:DI (match_dup 4) 0)
2744 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
2745 (set (match_dup 0) (match_dup 4))]
2748 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
2749 << INTVAL (operands[2])));
2752 ;; For the unaligned byte case, we use code similar to that in the
2753 ;; Architecture book, but reordered to lower the number of registers
2754 ;; required. Operand 0 is the address. Operand 1 is the data to store.
2755 ;; Operands 2, 3, and 4 are DImode temporaries, where the last two may
2756 ;; be the same temporary, if desired. If the address is in a register,
2757 ;; operand 2 can be that register.
2759 (define_expand "unaligned_storeqi"
2760 [(set (match_operand:DI 3 "register_operand" "")
2761 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
2763 (set (match_operand:DI 2 "register_operand" "")
2766 (and:DI (not:DI (ashift:DI (const_int 255)
2767 (ashift:DI (match_dup 2) (const_int 3))))
2769 (set (match_operand:DI 4 "register_operand" "")
2770 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
2771 (ashift:DI (match_dup 2) (const_int 3))))
2772 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
2773 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
2778 ;; This is the code for storing into an unaligned short. It uses the same
2779 ;; trick as loading from an unaligned short. It needs lots of temporaries.
2780 ;; However, during reload, we only have two registers available. So we
2781 ;; repeat code so that only two temporaries are available. During RTL
2782 ;; generation, we can use different pseudos for each temporary and CSE
2783 ;; will remove the redundancies. During reload, we have to settle with
2784 ;; what we get. Luckily, unaligned accesses of this kind produced during
2785 ;; reload are quite rare.
2787 ;; Operand 0 is the address of the memory location. Operand 1 contains the
2788 ;; data to store. The rest of the operands are all temporaries, with
2789 ;; various overlap possibilities during reload. See reload_outhi for
2790 ;; details of this use.
2792 (define_expand "unaligned_storehi"
2793 [(set (match_operand:DI 2 "register_operand" "")
2794 (match_operand:DI 0 "address_operand" ""))
2795 (set (match_operand:DI 3 "register_operand" "")
2796 (and:DI (match_dup 2) (const_int -7)))
2797 (set (match_operand:DI 4 "register_operand" "")
2798 (mem:DI (match_dup 3)))
2799 (set (match_operand:DI 10 "register_operand" "")
2800 (and:DI (match_dup 2) (const_int -2)))
2801 (set (match_operand:DI 5 "register_operand" "")
2802 (and:DI (not:DI (ashift:DI (const_int 65535)
2803 (ashift:DI (match_dup 10) (const_int 3))))
2805 (set (match_operand:DI 6 "register_operand" "")
2806 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
2807 (ashift:DI (match_dup 10) (const_int 3))))
2808 (set (match_operand:DI 7 "register_operand" "")
2809 (ior:DI (match_dup 5) (match_dup 6)))
2810 (set (match_operand:DI 8 "register_operand" "") (match_dup 0))
2811 (set (match_operand:DI 9 "register_operand" "")
2812 (and:DI (match_dup 8) (const_int -7)))
2813 (set (mem:DI (match_dup 9)) (match_dup 7))]
2817 ;; Here are the define_expand's for QI and HI moves that use the above
2818 ;; patterns. We have the normal sets, plus the ones that need scratch
2819 ;; registers for reload.
2821 (define_expand "movqi"
2822 [(set (match_operand:QI 0 "general_operand" "")
2823 (match_operand:QI 1 "general_operand" ""))]
2826 { extern rtx get_unaligned_address ();
2828 /* If the output is not a register, the input must be. */
2829 if (GET_CODE (operands[0]) == MEM)
2830 operands[1] = force_reg (QImode, operands[1]);
2832 /* Handle four memory cases, unaligned and aligned for either the input
2833 or the output. The only case where we can be called during reload is
2834 for aligned loads; all other cases require temporaries. */
2836 if (GET_CODE (operands[1]) == MEM
2837 || (GET_CODE (operands[1]) == SUBREG
2838 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2839 || (reload_in_progress && GET_CODE (operands[1]) == REG
2840 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2841 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2842 && GET_CODE (SUBREG_REG (operands[1])) == REG
2843 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2845 if (aligned_memory_operand (operands[1], QImode))
2847 rtx aligned_mem, bitnum;
2848 rtx scratch = (reload_in_progress
2849 ? gen_rtx (REG, SImode, REGNO (operands[0]))
2850 : gen_reg_rtx (SImode));
2852 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2854 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
2859 /* Don't pass these as parameters since that makes the generated
2860 code depend on parameter evaluation order which will cause
2861 bootstrap failures. */
2863 rtx temp1 = gen_reg_rtx (DImode);
2864 rtx temp2 = gen_reg_rtx (DImode);
2865 rtx seq = gen_unaligned_loadqi (operands[0],
2866 get_unaligned_address (operands[1]),
2869 alpha_set_memflags (seq, operands[1]);
2876 else if (GET_CODE (operands[0]) == MEM
2877 || (GET_CODE (operands[0]) == SUBREG
2878 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2879 || (reload_in_progress && GET_CODE (operands[0]) == REG
2880 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2881 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2882 && GET_CODE (SUBREG_REG (operands[0])) == REG
2883 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2885 if (aligned_memory_operand (operands[0], QImode))
2887 rtx aligned_mem, bitnum;
2888 rtx temp1 = gen_reg_rtx (SImode);
2889 rtx temp2 = gen_reg_rtx (SImode);
2891 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2893 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2898 rtx temp1 = gen_reg_rtx (DImode);
2899 rtx temp2 = gen_reg_rtx (DImode);
2900 rtx temp3 = gen_reg_rtx (DImode);
2901 rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]),
2902 operands[1], temp1, temp2, temp3);
2904 alpha_set_memflags (seq, operands[0]);
2911 (define_expand "movhi"
2912 [(set (match_operand:HI 0 "general_operand" "")
2913 (match_operand:HI 1 "general_operand" ""))]
2916 { extern rtx get_unaligned_address ();
2918 /* If the output is not a register, the input must be. */
2919 if (GET_CODE (operands[0]) == MEM)
2920 operands[1] = force_reg (HImode, operands[1]);
2922 /* Handle four memory cases, unaligned and aligned for either the input
2923 or the output. The only case where we can be called during reload is
2924 for aligned loads; all other cases require temporaries. */
2926 if (GET_CODE (operands[1]) == MEM
2927 || (GET_CODE (operands[1]) == SUBREG
2928 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2929 || (reload_in_progress && GET_CODE (operands[1]) == REG
2930 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2931 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2932 && GET_CODE (SUBREG_REG (operands[1])) == REG
2933 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2935 if (aligned_memory_operand (operands[1], HImode))
2937 rtx aligned_mem, bitnum;
2938 rtx scratch = (reload_in_progress
2939 ? gen_rtx (REG, SImode, REGNO (operands[0]))
2940 : gen_reg_rtx (SImode));
2942 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2944 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
2950 = force_reg (DImode,
2951 force_operand (get_unaligned_address (operands[1]),
2953 rtx scratch1 = gen_reg_rtx (DImode);
2954 rtx scratch2 = gen_reg_rtx (DImode);
2955 rtx scratch3 = gen_reg_rtx (DImode);
2957 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1,
2958 scratch2, scratch3);
2960 alpha_set_memflags (seq, operands[1]);
2967 else if (GET_CODE (operands[0]) == MEM
2968 || (GET_CODE (operands[0]) == SUBREG
2969 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2970 || (reload_in_progress && GET_CODE (operands[0]) == REG
2971 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2972 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2973 && GET_CODE (SUBREG_REG (operands[0])) == REG
2974 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2976 if (aligned_memory_operand (operands[0], HImode))
2978 rtx aligned_mem, bitnum;
2979 rtx temp1 = gen_reg_rtx (SImode);
2980 rtx temp2 = gen_reg_rtx (SImode);
2982 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2984 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2989 rtx temp1 = gen_reg_rtx (DImode);
2990 rtx temp2 = gen_reg_rtx (DImode);
2991 rtx temp3 = gen_reg_rtx (DImode);
2992 rtx temp4 = gen_reg_rtx (DImode);
2993 rtx temp5 = gen_reg_rtx (DImode);
2994 rtx temp6 = gen_reg_rtx (DImode);
2995 rtx temp7 = gen_reg_rtx (DImode);
2996 rtx temp8 = gen_reg_rtx (DImode);
2997 rtx temp9 = gen_reg_rtx (DImode);
2999 rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]),
3000 operands[1], temp1, temp2,temp3,
3001 temp4, temp5, temp6,temp7,
3004 alpha_set_memflags (seq, operands[0]);
3012 ;; Here are the versions for reload. Note that in the unaligned cases
3013 ;; we know that the operand must not be a pseudo-register because stack
3014 ;; slots are always aligned references.
3016 (define_expand "reload_inqi"
3017 [(parallel [(match_operand:QI 0 "register_operand" "=r")
3018 (match_operand:QI 1 "unaligned_memory_operand" "m")
3019 (match_operand:DI 2 "register_operand" "=&r")])]
3022 { extern rtx get_unaligned_address ();
3023 rtx addr = get_unaligned_address (operands[1]);
3024 rtx seq = gen_unaligned_loadqi (operands[0], addr, operands[2],
3025 gen_rtx (REG, DImode, REGNO (operands[0])));
3027 alpha_set_memflags (seq, operands[1]);
3032 (define_expand "reload_inhi"
3033 [(parallel [(match_operand:HI 0 "register_operand" "=r")
3034 (match_operand:HI 1 "unaligned_memory_operand" "m")
3035 (match_operand:TI 2 "register_operand" "=&r")])]
3038 { extern rtx get_unaligned_address ();
3039 rtx addr = get_unaligned_address (operands[1]);
3040 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3041 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3044 if (GET_CODE (addr) != REG)
3046 emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr));
3050 seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1, scratch2);
3051 alpha_set_memflags (seq, operands[1]);
3056 (define_expand "reload_outqi"
3057 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
3058 (match_operand:QI 1 "register_operand" "r")
3059 (match_operand:TI 2 "register_operand" "=&r")])]
3062 { extern rtx get_unaligned_address ();
3064 if (aligned_memory_operand (operands[0], QImode))
3066 rtx aligned_mem, bitnum;
3068 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3070 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3071 gen_rtx (REG, SImode, REGNO (operands[2])),
3072 gen_rtx (REG, SImode,
3073 REGNO (operands[2]) + 1)));
3077 rtx addr = get_unaligned_address (operands[0]);
3078 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3079 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3082 if (GET_CODE (addr) == REG)
3085 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
3086 scratch2, scratch2);
3087 alpha_set_memflags (seq, operands[0]);
3094 (define_expand "reload_outhi"
3095 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
3096 (match_operand:HI 1 "register_operand" "r")
3097 (match_operand:TI 2 "register_operand" "=&r")])]
3100 { extern rtx get_unaligned_address ();
3102 if (aligned_memory_operand (operands[0], HImode))
3104 rtx aligned_mem, bitnum;
3106 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3108 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3109 gen_rtx (REG, SImode, REGNO (operands[2])),
3110 gen_rtx (REG, SImode,
3111 REGNO (operands[2]) + 1)));
3115 rtx addr = get_unaligned_address (operands[0]);
3116 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3117 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3118 rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1;
3121 seq = gen_unaligned_storehi (addr, operands[1], scratch_a,
3122 scratch2, scratch2, scratch2,
3123 scratch1, scratch2, scratch_a,
3124 scratch1, scratch_a);
3125 alpha_set_memflags (seq, operands[0]);
3132 ;; Subroutine of stack space allocation. Perform a stack probe.
3133 (define_expand "probe_stack"
3134 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
3138 operands[0] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx,
3139 INTVAL (operands[0])));
3140 MEM_VOLATILE_P (operands[0]) = 1;
3142 operands[1] = gen_reg_rtx (DImode);
3145 ;; This is how we allocate stack space. If we are allocating a
3146 ;; constant amount of space and we know it is less than 4096
3147 ;; bytes, we need do nothing.
3149 ;; If it is more than 4096 bytes, we need to probe the stack
3151 (define_expand "allocate_stack"
3153 (plus:DI (reg:DI 30)
3154 (match_operand:DI 0 "reg_or_cint_operand" "")))]
3158 if (GET_CODE (operands[0]) == CONST_INT
3159 && INTVAL (operands[0]) < 32768)
3161 if (INTVAL (operands[0]) >= 4096)
3163 /* We do this the same way as in the prologue and generate explicit
3164 probes. Then we update the stack by the constant. */
3168 emit_insn (gen_probe_stack (GEN_INT (- probed)));
3169 while (probed + 8192 < INTVAL (operands[0]))
3170 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
3172 if (probed + 4096 < INTVAL (operands[0]))
3173 emit_insn (gen_probe_stack (GEN_INT (- (probed += 4096))));
3176 operands[0] = GEN_INT (- INTVAL (operands[0]));
3181 rtx loop_label = gen_label_rtx ();
3182 rtx count = gen_reg_rtx (DImode);
3183 rtx access = gen_reg_rtx (Pmode);
3184 rtx memref = gen_rtx (MEM, DImode, access);
3186 MEM_VOLATILE_P (memref) = 1;
3188 /* If the amount to be allocated is not a constant, we only need to
3189 do something special if it is >= 4096. */
3191 if (GET_CODE (operands[0]) != CONST_INT)
3193 operands[0] = force_reg (DImode, operands[0]);
3194 out_label = gen_label_rtx ();
3195 emit_insn (gen_cmpdi (operands[0],
3196 force_reg (DImode, GEN_INT (4096))));
3197 emit_jump_insn (gen_ble (out_label));
3199 /* Compute COUNT = (N + 4096) / 8192. N is known positive. */
3200 emit_insn (gen_adddi3 (count, operands[0], GEN_INT (4096)));
3201 emit_insn (gen_lshrdi3 (count, count, GEN_INT (13)));
3204 emit_move_insn (count, GEN_INT ((INTVAL (operands[0]) + 4096) >> 13));
3206 /* ACCESS = SP + 4096. */
3207 emit_insn (gen_adddi3 (access, stack_pointer_rtx, GEN_INT (4096)));
3208 emit_label (loop_label);
3210 /* Each iteration subtracts 8192 from ACCESS and references it. */
3211 emit_insn (gen_adddi3 (count, count, constm1_rtx));
3212 emit_insn (gen_adddi3 (access, access, GEN_INT (-8192)));
3213 emit_move_insn (gen_reg_rtx (DImode), memref);
3214 emit_insn (gen_cmpdi (count, const0_rtx));
3215 emit_jump_insn (gen_bgt (loop_label));
3218 emit_label (out_label);
3220 /* We need to subtract operands[0] from SP. We know it isn't a
3221 constant less than 32768, so we know we have to load it into
3224 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
3225 force_reg (Pmode, operands[0])));
3227 /* Now, unless we have a constant and we know that we are within
3228 4096 from the end, we need to access sp + 4096. */
3229 if (! (GET_CODE (operands[0]) == CONST_INT
3230 && (INTVAL (operands[0]) % 8192) < 4096))
3231 emit_insn (gen_probe_stack (GEN_INT (4096)));