1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
38 ;; 2 builtin_setjmp_receiver
41 ;; 5 prologue_stack_probe_loop
43 ;; 7 exception_receiver
45 ;; Processor type -- this attribute must exactly match the processor_type
46 ;; enumeration in alpha.h.
48 (define_attr "cpu" "ev4,ev5,ev6"
49 (const (symbol_ref "alpha_cpu")))
51 ;; Define an insn type attribute. This is used in function unit delay
52 ;; computations, among other purposes. For the most part, we use the names
53 ;; defined in the EV4 documentation, but add a few that we have to know about
57 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
58 (const_string "iadd"))
60 ;; Describe a user's asm statement.
61 (define_asm_attributes
62 [(set_attr "type" "multi")])
64 ;; Define the operand size an insn operates on. Used primarily by mul
65 ;; and div operations that have size dependant timings.
67 (define_attr "opsize" "si,di,udi" (const_string "di"))
69 ;; The TRAP_TYPE attribute marks instructions that may generate traps
70 ;; (which are imprecise and may need a trapb if software completion
73 (define_attr "trap" "no,yes" (const_string "no"))
75 ;; The length of an instruction sequence in bytes.
77 (define_attr "length" "" (const_int 4))
79 ;; On EV4 there are two classes of resources to consider: resources needed
80 ;; to issue, and resources needed to execute. IBUS[01] are in the first
81 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
82 ;; (There are a few other register-like resources, but ...)
84 ; First, describe all of the issue constraints with single cycle delays.
85 ; All insns need a bus, but all except loads require one or the other.
86 (define_function_unit "ev4_ibus0" 1 0
87 (and (eq_attr "cpu" "ev4")
88 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
91 (define_function_unit "ev4_ibus1" 1 0
92 (and (eq_attr "cpu" "ev4")
93 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
96 ; Memory delivers its result in three cycles. Actually return one and
97 ; take care of this in adjust_cost, since we want to handle user-defined
99 (define_function_unit "ev4_abox" 1 0
100 (and (eq_attr "cpu" "ev4")
101 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
104 ; Branches have no delay cost, but do tie up the unit for two cycles.
105 (define_function_unit "ev4_bbox" 1 1
106 (and (eq_attr "cpu" "ev4")
107 (eq_attr "type" "ibr,fbr,jsr"))
110 ; Arithmetic insns are normally have their results available after
111 ; two cycles. There are a number of exceptions. They are encoded in
112 ; ADJUST_COST. Some of the other insns have similar exceptions.
113 (define_function_unit "ev4_ebox" 1 0
114 (and (eq_attr "cpu" "ev4")
115 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
118 (define_function_unit "imul" 1 0
119 (and (eq_attr "cpu" "ev4")
120 (and (eq_attr "type" "imul")
121 (eq_attr "opsize" "si")))
124 (define_function_unit "imul" 1 0
125 (and (eq_attr "cpu" "ev4")
126 (and (eq_attr "type" "imul")
127 (eq_attr "opsize" "!si")))
130 (define_function_unit "ev4_fbox" 1 0
131 (and (eq_attr "cpu" "ev4")
132 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
135 (define_function_unit "fdiv" 1 0
136 (and (eq_attr "cpu" "ev4")
137 (and (eq_attr "type" "fdiv")
138 (eq_attr "opsize" "si")))
141 (define_function_unit "fdiv" 1 0
142 (and (eq_attr "cpu" "ev4")
143 (and (eq_attr "type" "fdiv")
144 (eq_attr "opsize" "di")))
147 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
149 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
150 ;; with the combined resource EBOX.
152 (define_function_unit "ev5_ebox" 2 0
153 (and (eq_attr "cpu" "ev5")
154 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
157 ; Memory takes at least 2 clocks. Return one from here and fix up with
158 ; user-defined latencies in adjust_cost.
159 (define_function_unit "ev5_ebox" 2 0
160 (and (eq_attr "cpu" "ev5")
161 (eq_attr "type" "ild,fld,ldsym"))
164 ; Loads can dual issue with one another, but loads and stores do not mix.
165 (define_function_unit "ev5_e0" 1 0
166 (and (eq_attr "cpu" "ev5")
167 (eq_attr "type" "ild,fld,ldsym"))
169 [(eq_attr "type" "ist,fst")])
171 ; Stores, shifts, multiplies can only issue to E0
172 (define_function_unit "ev5_e0" 1 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "ist,fst,shift,imul"))
177 ; Motion video insns also issue only to E0, and take two ticks.
178 (define_function_unit "ev5_e0" 1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "mvi"))
183 ; Conditional moves always take 2 ticks.
184 (define_function_unit "ev5_ebox" 2 0
185 (and (eq_attr "cpu" "ev5")
186 (eq_attr "type" "icmov"))
189 ; Branches can only issue to E1
190 (define_function_unit "ev5_e1" 1 0
191 (and (eq_attr "cpu" "ev5")
192 (eq_attr "type" "ibr,jsr"))
195 ; Multiplies also use the integer multiplier.
196 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
197 ; cycles before an integer multiplication completes."
198 (define_function_unit "imul" 1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "si")))
204 (define_function_unit "imul" 1 0
205 (and (eq_attr "cpu" "ev5")
206 (and (eq_attr "type" "imul")
207 (eq_attr "opsize" "di")))
210 (define_function_unit "imul" 1 0
211 (and (eq_attr "cpu" "ev5")
212 (and (eq_attr "type" "imul")
213 (eq_attr "opsize" "udi")))
216 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
217 ;; on either so we have to play the game again.
219 (define_function_unit "ev5_fbox" 2 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
224 (define_function_unit "ev5_fm" 1 0
225 (and (eq_attr "cpu" "ev5")
226 (eq_attr "type" "fmul"))
229 ; Add and cmov as you would expect; fbr never produces a result;
230 ; fdiv issues through fa to the divider,
231 (define_function_unit "ev5_fa" 1 0
232 (and (eq_attr "cpu" "ev5")
233 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
236 ; ??? How to: "No instruction can be issued to pipe FA exactly five
237 ; cycles before a floating point divide completes."
238 (define_function_unit "fdiv" 1 0
239 (and (eq_attr "cpu" "ev5")
240 (and (eq_attr "type" "fdiv")
241 (eq_attr "opsize" "si")))
242 15 15) ; 15 to 31 data dependant
244 (define_function_unit "fdiv" 1 0
245 (and (eq_attr "cpu" "ev5")
246 (and (eq_attr "type" "fdiv")
247 (eq_attr "opsize" "di")))
248 22 22) ; 22 to 60 data dependant
250 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
252 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
253 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
255 ;; Conditional moves decompose into two independant primitives, each
256 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
258 (define_function_unit "ev6_ebox" 4 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "icmov"))
263 (define_function_unit "ev6_ebox" 4 0
264 (and (eq_attr "cpu" "ev6")
265 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
268 ;; Integer loads take at least 3 clocks, and only issue to lower units.
269 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
270 (define_function_unit "ev6_l" 2 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "ild,ldsym,ist,fst"))
275 ;; FP loads take at least 4 clocks. Return two from here...
276 (define_function_unit "ev6_l" 2 0
277 (and (eq_attr "cpu" "ev6")
278 (eq_attr "type" "fld"))
281 ;; Motion video insns also issue only to U0, and take three ticks.
282 (define_function_unit "ev6_u0" 1 0
283 (and (eq_attr "cpu" "ev6")
284 (eq_attr "type" "mvi"))
287 (define_function_unit "ev6_u" 2 0
288 (and (eq_attr "cpu" "ev6")
289 (eq_attr "type" "mvi"))
292 ;; Shifts issue to either upper pipe.
293 (define_function_unit "ev6_u" 2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "shift"))
298 ;; Multiplies issue only to U1, and all take 7 ticks.
299 ;; Rather than create a new function unit just for U1, reuse IMUL
300 (define_function_unit "imul" 1 0
301 (and (eq_attr "cpu" "ev6")
302 (eq_attr "type" "imul"))
305 (define_function_unit "ev6_u" 2 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "imul"))
310 ;; Branches issue to either upper pipe
311 (define_function_unit "ev6_u" 2 0
312 (and (eq_attr "cpu" "ev6")
313 (eq_attr "type" "ibr"))
316 ;; Calls only issue to L0.
317 (define_function_unit "ev6_l0" 1 0
318 (and (eq_attr "cpu" "ev6")
319 (eq_attr "type" "jsr"))
322 (define_function_unit "ev6_l" 2 0
323 (and (eq_attr "cpu" "ev6")
324 (eq_attr "type" "jsr"))
327 ;; Ftoi/itof only issue to lower pipes
328 (define_function_unit "ev6_l" 2 0
329 (and (eq_attr "cpu" "ev6")
330 (eq_attr "type" "ftoi"))
333 (define_function_unit "ev6_l" 2 0
334 (and (eq_attr "cpu" "ev6")
335 (eq_attr "type" "itof"))
338 ;; For the FPU we are very similar to EV5, except there's no insn that
339 ;; can issue to fm & fa, so we get to leave that out.
341 (define_function_unit "ev6_fm" 1 0
342 (and (eq_attr "cpu" "ev6")
343 (eq_attr "type" "fmul"))
346 (define_function_unit "ev6_fa" 1 0
347 (and (eq_attr "cpu" "ev6")
348 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
351 (define_function_unit "ev6_fa" 1 0
352 (and (eq_attr "cpu" "ev6")
353 (eq_attr "type" "fcmov"))
356 (define_function_unit "fdiv" 1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fdiv")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fdiv" 1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fdiv")
365 (eq_attr "opsize" "di")))
368 (define_function_unit "fsqrt" 1 0
369 (and (eq_attr "cpu" "ev6")
370 (and (eq_attr "type" "fsqrt")
371 (eq_attr "opsize" "si")))
374 (define_function_unit "fsqrt" 1 0
375 (and (eq_attr "cpu" "ev6")
376 (and (eq_attr "type" "fsqrt")
377 (eq_attr "opsize" "di")))
380 ; ??? The FPU communicates with memory and the integer register file
381 ; via two fp store units. We need a slot in the fst immediately, and
382 ; a slot in LOW after the operand data is ready. At which point the
383 ; data may be moved either to the store queue or the integer register
384 ; file and the insn retired.
387 ;; First define the arithmetic insns. Note that the 32-bit forms also
390 ;; Handle 32-64 bit extension from memory to a floating point register
391 ;; specially, since this ocurrs frequently in int->double conversions.
392 ;; This is done with a define_split after reload converting the plain
393 ;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
395 ;; Note that while we must retain the =f case in the insn for reload's
396 ;; benefit, it should be eliminated after reload, so we should never emit
397 ;; code for that case. But we don't reject the possibility.
399 (define_insn "extendsidi2"
400 [(set (match_operand:DI 0 "register_operand" "=r,r,?f")
401 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
406 lds %0,%1\;cvtlq %0,%0"
407 [(set_attr "type" "iadd,ild,fld")
408 (set_attr "length" "*,*,8")])
410 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
412 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
413 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
415 [(set (match_dup 2) (match_dup 1))
416 (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))]
417 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
420 [(set (match_operand:DI 0 "register_operand" "=f")
421 (unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))]
424 [(set_attr "type" "fadd")])
426 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
427 ;; generates better code. We have the anonymous addsi3 pattern below in
428 ;; case combine wants to make it.
429 (define_expand "addsi3"
430 [(set (match_operand:SI 0 "register_operand" "")
431 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
432 (match_operand:SI 2 "add_operand" "")))]
438 rtx op1 = gen_lowpart (DImode, operands[1]);
439 rtx op2 = gen_lowpart (DImode, operands[2]);
441 if (! cse_not_expected)
443 rtx tmp = gen_reg_rtx (DImode);
444 emit_insn (gen_adddi3 (tmp, op1, op2));
445 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
448 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
454 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
455 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
456 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
465 [(set (match_operand:SI 0 "register_operand" "")
466 (plus:SI (match_operand:SI 1 "register_operand" "")
467 (match_operand:SI 2 "const_int_operand" "")))]
468 "! add_operand (operands[2], SImode)"
469 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
470 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
473 HOST_WIDE_INT val = INTVAL (operands[2]);
474 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
475 HOST_WIDE_INT rest = val - low;
477 operands[3] = GEN_INT (rest);
478 operands[4] = GEN_INT (low);
482 [(set (match_operand:DI 0 "register_operand" "=r,r")
484 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
485 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
492 [(set (match_operand:DI 0 "register_operand" "")
494 (plus:SI (match_operand:SI 1 "register_operand" "")
495 (match_operand:SI 2 "const_int_operand" ""))))
496 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
497 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
498 && INTVAL (operands[2]) % 4 == 0"
499 [(set (match_dup 3) (match_dup 4))
500 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
505 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
511 operands[4] = GEN_INT (val);
512 operands[5] = GEN_INT (mult);
516 [(set (match_operand:DI 0 "register_operand" "")
518 (plus:SI (match_operator:SI 1 "comparison_operator"
519 [(match_operand 2 "" "")
520 (match_operand 3 "" "")])
521 (match_operand:SI 4 "add_operand" ""))))
522 (clobber (match_operand:DI 5 "register_operand" ""))]
524 [(set (match_dup 5) (match_dup 6))
525 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
528 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
529 operands[2], operands[3]);
530 operands[7] = gen_lowpart (SImode, operands[5]);
533 (define_insn "adddi3"
534 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
535 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
536 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
540 const char * const pattern[4] = {
547 /* The NT stack unwind code can't handle a subq to adjust the stack
548 (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
549 the exception handling code will loop if a subq is used and an
552 The 19980616 change to emit prologues as RTL also confused some
553 versions of GDB, which also interprets prologues. This has been
554 fixed as of GDB 4.18, but it does not harm to unconditionally
557 int which = which_alternative;
559 if (operands[0] == stack_pointer_rtx
560 && GET_CODE (operands[2]) == CONST_INT
561 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
564 return pattern[which];
567 ;; ??? Allow large constants when basing off the frame pointer or some
568 ;; virtual register that may eliminate to the frame pointer. This is
569 ;; done because register elimination offsets will change the hi/lo split,
570 ;; and if we split before reload, we will require additional instructions.
573 [(set (match_operand:DI 0 "register_operand" "=r")
574 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
575 (match_operand:DI 2 "const_int_operand" "n")))]
576 "REG_OK_FP_BASE_P (operands[1])"
579 ;; Don't do this if we are adjusting SP since we don't want to do it
580 ;; in two steps. Don't split FP sources for the reason listed above.
582 [(set (match_operand:DI 0 "register_operand" "")
583 (plus:DI (match_operand:DI 1 "register_operand" "")
584 (match_operand:DI 2 "const_int_operand" "")))]
585 "! add_operand (operands[2], DImode)
586 && operands[0] != stack_pointer_rtx
587 && operands[1] != frame_pointer_rtx
588 && operands[1] != arg_pointer_rtx"
589 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
590 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
593 HOST_WIDE_INT val = INTVAL (operands[2]);
594 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
595 HOST_WIDE_INT rest = val - low;
597 operands[3] = GEN_INT (rest);
598 operands[4] = GEN_INT (low);
602 [(set (match_operand:SI 0 "register_operand" "=r,r")
603 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
604 (match_operand:SI 2 "const48_operand" "I,I"))
605 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
612 [(set (match_operand:DI 0 "register_operand" "=r,r")
614 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
615 (match_operand:SI 2 "const48_operand" "I,I"))
616 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
623 [(set (match_operand:DI 0 "register_operand" "")
625 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
626 [(match_operand 2 "" "")
627 (match_operand 3 "" "")])
628 (match_operand:SI 4 "const48_operand" ""))
629 (match_operand:SI 5 "add_operand" ""))))
630 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
632 [(set (match_dup 6) (match_dup 7))
634 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
638 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
639 operands[2], operands[3]);
640 operands[8] = gen_lowpart (SImode, operands[6]);
644 [(set (match_operand:DI 0 "register_operand" "=r,r")
645 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
646 (match_operand:DI 2 "const48_operand" "I,I"))
647 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
653 ;; These variants of the above insns can occur if the third operand
654 ;; is the frame pointer. This is a kludge, but there doesn't
655 ;; seem to be a way around it. Only recognize them while reloading.
658 [(set (match_operand:DI 0 "some_operand" "=&r")
659 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
660 (match_operand:DI 2 "some_operand" "r"))
661 (match_operand:DI 3 "some_operand" "rIOKL")))]
666 [(set (match_operand:DI 0 "register_operand" "")
667 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
668 (match_operand:DI 2 "register_operand" ""))
669 (match_operand:DI 3 "add_operand" "")))]
671 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
672 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
676 [(set (match_operand:SI 0 "some_operand" "=&r")
677 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
678 (match_operand:SI 2 "const48_operand" "I"))
679 (match_operand:SI 3 "some_operand" "r"))
680 (match_operand:SI 4 "some_operand" "rIOKL")))]
685 [(set (match_operand:SI 0 "register_operand" "r")
686 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
687 (match_operand:SI 2 "const48_operand" ""))
688 (match_operand:SI 3 "register_operand" ""))
689 (match_operand:SI 4 "add_operand" "rIOKL")))]
692 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
693 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
697 [(set (match_operand:DI 0 "some_operand" "=&r")
700 (mult:SI (match_operand:SI 1 "some_operand" "rJ")
701 (match_operand:SI 2 "const48_operand" "I"))
702 (match_operand:SI 3 "some_operand" "r"))
703 (match_operand:SI 4 "some_operand" "rIOKL"))))]
708 [(set (match_operand:DI 0 "register_operand" "")
711 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
712 (match_operand:SI 2 "const48_operand" ""))
713 (match_operand:SI 3 "register_operand" ""))
714 (match_operand:SI 4 "add_operand" ""))))]
717 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
718 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
719 "operands[5] = gen_lowpart (SImode, operands[0]);")
722 [(set (match_operand:DI 0 "some_operand" "=&r")
723 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
724 (match_operand:DI 2 "const48_operand" "I"))
725 (match_operand:DI 3 "some_operand" "r"))
726 (match_operand:DI 4 "some_operand" "rIOKL")))]
731 [(set (match_operand:DI 0 "register_operand" "=")
732 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
733 (match_operand:DI 2 "const48_operand" ""))
734 (match_operand:DI 3 "register_operand" ""))
735 (match_operand:DI 4 "add_operand" "")))]
738 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
739 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
742 (define_insn "negsi2"
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
749 [(set (match_operand:DI 0 "register_operand" "=r")
750 (sign_extend:DI (neg:SI
751 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
755 (define_insn "negdi2"
756 [(set (match_operand:DI 0 "register_operand" "=r")
757 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
761 (define_expand "subsi3"
762 [(set (match_operand:SI 0 "register_operand" "")
763 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
764 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
770 rtx op1 = gen_lowpart (DImode, operands[1]);
771 rtx op2 = gen_lowpart (DImode, operands[2]);
773 if (! cse_not_expected)
775 rtx tmp = gen_reg_rtx (DImode);
776 emit_insn (gen_subdi3 (tmp, op1, op2));
777 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
780 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
788 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
793 [(set (match_operand:DI 0 "register_operand" "=r")
794 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
795 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
799 (define_insn "subdi3"
800 [(set (match_operand:DI 0 "register_operand" "=r")
801 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
802 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
807 [(set (match_operand:SI 0 "register_operand" "=r")
808 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
809 (match_operand:SI 2 "const48_operand" "I"))
810 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
815 [(set (match_operand:DI 0 "register_operand" "=r")
817 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
818 (match_operand:SI 2 "const48_operand" "I"))
819 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
824 [(set (match_operand:DI 0 "register_operand" "=r")
825 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
826 (match_operand:DI 2 "const48_operand" "I"))
827 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
831 (define_insn "mulsi3"
832 [(set (match_operand:SI 0 "register_operand" "=r")
833 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
834 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
837 [(set_attr "type" "imul")
838 (set_attr "opsize" "si")])
841 [(set (match_operand:DI 0 "register_operand" "=r")
843 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
844 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
847 [(set_attr "type" "imul")
848 (set_attr "opsize" "si")])
850 (define_insn "muldi3"
851 [(set (match_operand:DI 0 "register_operand" "=r")
852 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
853 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
856 [(set_attr "type" "imul")])
858 (define_insn "umuldi3_highpart"
859 [(set (match_operand:DI 0 "register_operand" "=r")
862 (mult:TI (zero_extend:TI
863 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
865 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
869 [(set_attr "type" "imul")
870 (set_attr "opsize" "udi")])
873 [(set (match_operand:DI 0 "register_operand" "=r")
876 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
877 (match_operand:TI 2 "cint8_operand" "I"))
881 [(set_attr "type" "imul")
882 (set_attr "opsize" "udi")])
884 ;; The divide and remainder operations always take their inputs from
885 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
887 ;; ??? Force sign-extension here because some versions of OSF/1 don't
888 ;; do the right thing if the inputs are not properly sign-extended.
889 ;; But Linux, for instance, does not have this problem. Is it worth
890 ;; the complication here to eliminate the sign extension?
891 ;; Interix/NT has the same sign-extension problem.
893 (define_expand "divsi3"
895 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
897 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
898 (parallel [(set (reg:DI 27)
899 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
900 (clobber (reg:DI 23))
901 (clobber (reg:DI 28))])
902 (set (match_operand:SI 0 "general_operand" "")
903 (subreg:SI (reg:DI 27) 0))]
907 (define_expand "udivsi3"
909 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
911 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
912 (parallel [(set (reg:DI 27)
913 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
914 (clobber (reg:DI 23))
915 (clobber (reg:DI 28))])
916 (set (match_operand:SI 0 "general_operand" "")
917 (subreg:SI (reg:DI 27) 0))]
921 (define_expand "modsi3"
923 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
925 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
926 (parallel [(set (reg:DI 27)
927 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
928 (clobber (reg:DI 23))
929 (clobber (reg:DI 28))])
930 (set (match_operand:SI 0 "general_operand" "")
931 (subreg:SI (reg:DI 27) 0))]
935 (define_expand "umodsi3"
937 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
939 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
940 (parallel [(set (reg:DI 27)
941 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
942 (clobber (reg:DI 23))
943 (clobber (reg:DI 28))])
944 (set (match_operand:SI 0 "general_operand" "")
945 (subreg:SI (reg:DI 27) 0))]
949 (define_expand "divdi3"
950 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
951 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
952 (parallel [(set (reg:DI 27)
955 (clobber (reg:DI 23))
956 (clobber (reg:DI 28))])
957 (set (match_operand:DI 0 "general_operand" "")
962 (define_expand "udivdi3"
963 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
964 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
965 (parallel [(set (reg:DI 27)
968 (clobber (reg:DI 23))
969 (clobber (reg:DI 28))])
970 (set (match_operand:DI 0 "general_operand" "")
975 (define_expand "moddi3"
976 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
977 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
978 (parallel [(set (reg:DI 27)
981 (clobber (reg:DI 23))
982 (clobber (reg:DI 28))])
983 (set (match_operand:DI 0 "general_operand" "")
988 (define_expand "umoddi3"
989 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
990 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
991 (parallel [(set (reg:DI 27)
994 (clobber (reg:DI 23))
995 (clobber (reg:DI 28))])
996 (set (match_operand:DI 0 "general_operand" "")
1001 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1002 ;; expanded by the assembler.
1005 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
1006 [(reg:DI 24) (reg:DI 25)])))
1007 (clobber (reg:DI 23))
1008 (clobber (reg:DI 28))]
1011 [(set_attr "type" "jsr")
1012 (set_attr "length" "8")])
1016 (match_operator:DI 1 "divmod_operator"
1017 [(reg:DI 24) (reg:DI 25)]))
1018 (clobber (reg:DI 23))
1019 (clobber (reg:DI 28))]
1022 [(set_attr "type" "jsr")
1023 (set_attr "length" "8")])
1025 ;; Next are the basic logical operations. These only exist in DImode.
1027 (define_insn "anddi3"
1028 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1029 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1030 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1036 [(set_attr "type" "ilog,ilog,shift")])
1038 ;; There are times when we can split an AND into two AND insns. This occurs
1039 ;; when we can first clear any bytes and then clear anything else. For
1040 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1041 ;; Only do this when running on 64-bit host since the computations are
1042 ;; too messy otherwise.
1045 [(set (match_operand:DI 0 "register_operand" "")
1046 (and:DI (match_operand:DI 1 "register_operand" "")
1047 (match_operand:DI 2 "const_int_operand" "")))]
1048 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1049 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1050 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1053 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1054 unsigned HOST_WIDE_INT mask2 = mask1;
1057 /* For each byte that isn't all zeros, make it all ones. */
1058 for (i = 0; i < 64; i += 8)
1059 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1060 mask1 |= (HOST_WIDE_INT) 0xff << i;
1062 /* Now turn on any bits we've just turned off. */
1065 operands[3] = GEN_INT (mask1);
1066 operands[4] = GEN_INT (mask2);
1069 (define_insn "zero_extendqihi2"
1070 [(set (match_operand:HI 0 "register_operand" "=r")
1071 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1074 [(set_attr "type" "ilog")])
1077 [(set (match_operand:SI 0 "register_operand" "=r,r")
1078 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1083 [(set_attr "type" "ilog,ild")])
1086 [(set (match_operand:SI 0 "register_operand" "=r")
1087 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1090 [(set_attr "type" "ilog")])
1092 (define_expand "zero_extendqisi2"
1093 [(set (match_operand:SI 0 "register_operand" "")
1094 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1099 [(set (match_operand:DI 0 "register_operand" "=r,r")
1100 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1105 [(set_attr "type" "ilog,ild")])
1108 [(set (match_operand:DI 0 "register_operand" "=r")
1109 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1112 [(set_attr "type" "ilog")])
1114 (define_expand "zero_extendqidi2"
1115 [(set (match_operand:DI 0 "register_operand" "")
1116 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1121 [(set (match_operand:SI 0 "register_operand" "=r,r")
1122 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1127 [(set_attr "type" "shift,ild")])
1130 [(set (match_operand:SI 0 "register_operand" "=r")
1131 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1134 [(set_attr "type" "shift")])
1136 (define_expand "zero_extendhisi2"
1137 [(set (match_operand:SI 0 "register_operand" "")
1138 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1143 [(set (match_operand:DI 0 "register_operand" "=r,r")
1144 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1149 [(set_attr "type" "shift,ild")])
1152 [(set (match_operand:DI 0 "register_operand" "=r")
1153 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1156 [(set_attr "type" "shift")])
1158 (define_expand "zero_extendhidi2"
1159 [(set (match_operand:DI 0 "register_operand" "")
1160 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1164 (define_insn "zero_extendsidi2"
1165 [(set (match_operand:DI 0 "register_operand" "=r")
1166 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1169 [(set_attr "type" "shift")])
1172 [(set (match_operand:DI 0 "register_operand" "=r")
1173 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1174 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1177 [(set_attr "type" "ilog")])
1179 (define_insn "iordi3"
1180 [(set (match_operand:DI 0 "register_operand" "=r,r")
1181 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1182 (match_operand:DI 2 "or_operand" "rI,N")))]
1187 [(set_attr "type" "ilog")])
1189 (define_insn "one_cmpldi2"
1190 [(set (match_operand:DI 0 "register_operand" "=r")
1191 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1194 [(set_attr "type" "ilog")])
1197 [(set (match_operand:DI 0 "register_operand" "=r")
1198 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1199 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1202 [(set_attr "type" "ilog")])
1204 (define_insn "xordi3"
1205 [(set (match_operand:DI 0 "register_operand" "=r,r")
1206 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1207 (match_operand:DI 2 "or_operand" "rI,N")))]
1212 [(set_attr "type" "ilog")])
1215 [(set (match_operand:DI 0 "register_operand" "=r")
1216 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1217 (match_operand:DI 2 "register_operand" "rI"))))]
1220 [(set_attr "type" "ilog")])
1222 ;; Handle the FFS insn if we support CIX.
1224 (define_expand "ffsdi2"
1226 (unspec [(match_operand:DI 1 "register_operand" "")] 1))
1228 (plus:DI (match_dup 2) (const_int 1)))
1229 (set (match_operand:DI 0 "register_operand" "")
1230 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1231 (const_int 0) (match_dup 3)))]
1235 operands[2] = gen_reg_rtx (DImode);
1236 operands[3] = gen_reg_rtx (DImode);
1240 [(set (match_operand:DI 0 "register_operand" "=r")
1241 (unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
1244 ; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just
1245 ; reuse the existing type name.
1246 [(set_attr "type" "mvi")])
1248 ;; Next come the shifts and the various extract and insert operations.
1250 (define_insn "ashldi3"
1251 [(set (match_operand:DI 0 "register_operand" "=r,r")
1252 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1253 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1257 switch (which_alternative)
1260 if (operands[2] == const1_rtx)
1261 return \"addq %r1,%r1,%0\";
1263 return \"s%P2addq %r1,0,%0\";
1265 return \"sll %r1,%2,%0\";
1270 [(set_attr "type" "iadd,shift")])
1272 ;; ??? The following pattern is made by combine, but earlier phases
1273 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1274 ;; with this in a better way at some point.
1276 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1278 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1279 ;; (match_operand:DI 2 "const_int_operand" "P"))
1281 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1284 ;; if (operands[2] == const1_rtx)
1285 ;; return \"addl %r1,%r1,%0\";
1287 ;; return \"s%P2addl %r1,0,%0\";
1289 ;; [(set_attr "type" "iadd")])
1291 (define_insn "lshrdi3"
1292 [(set (match_operand:DI 0 "register_operand" "=r")
1293 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1294 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1297 [(set_attr "type" "shift")])
1299 (define_insn "ashrdi3"
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1301 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1302 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1305 [(set_attr "type" "shift")])
1307 (define_expand "extendqihi2"
1309 (ashift:DI (match_operand:QI 1 "some_operand" "")
1311 (set (match_operand:HI 0 "register_operand" "")
1312 (ashiftrt:DI (match_dup 2)
1319 emit_insn (gen_extendqihi2x (operands[0],
1320 force_reg (QImode, operands[1])));
1324 /* If we have an unaligned MEM, extend to DImode (which we do
1325 specially) and then copy to the result. */
1326 if (unaligned_memory_operand (operands[1], HImode))
1328 rtx temp = gen_reg_rtx (DImode);
1330 emit_insn (gen_extendqidi2 (temp, operands[1]));
1331 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1335 operands[0] = gen_lowpart (DImode, operands[0]);
1336 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1337 operands[2] = gen_reg_rtx (DImode);
1340 (define_insn "extendqidi2x"
1341 [(set (match_operand:DI 0 "register_operand" "=r")
1342 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1345 [(set_attr "type" "shift")])
1347 (define_insn "extendhidi2x"
1348 [(set (match_operand:DI 0 "register_operand" "=r")
1349 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1352 [(set_attr "type" "shift")])
1354 (define_insn "extendqisi2x"
1355 [(set (match_operand:SI 0 "register_operand" "=r")
1356 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1359 [(set_attr "type" "shift")])
1361 (define_insn "extendhisi2x"
1362 [(set (match_operand:SI 0 "register_operand" "=r")
1363 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1366 [(set_attr "type" "shift")])
1368 (define_insn "extendqihi2x"
1369 [(set (match_operand:HI 0 "register_operand" "=r")
1370 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1373 [(set_attr "type" "shift")])
1375 (define_expand "extendqisi2"
1377 (ashift:DI (match_operand:QI 1 "some_operand" "")
1379 (set (match_operand:SI 0 "register_operand" "")
1380 (ashiftrt:DI (match_dup 2)
1387 emit_insn (gen_extendqisi2x (operands[0],
1388 force_reg (QImode, operands[1])));
1392 /* If we have an unaligned MEM, extend to a DImode form of
1393 the result (which we do specially). */
1394 if (unaligned_memory_operand (operands[1], QImode))
1396 rtx temp = gen_reg_rtx (DImode);
1398 emit_insn (gen_extendqidi2 (temp, operands[1]));
1399 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1403 operands[0] = gen_lowpart (DImode, operands[0]);
1404 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1405 operands[2] = gen_reg_rtx (DImode);
1408 (define_expand "extendqidi2"
1410 (ashift:DI (match_operand:QI 1 "some_operand" "")
1412 (set (match_operand:DI 0 "register_operand" "")
1413 (ashiftrt:DI (match_dup 2)
1420 emit_insn (gen_extendqidi2x (operands[0],
1421 force_reg (QImode, operands[1])));
1425 if (unaligned_memory_operand (operands[1], QImode))
1428 = gen_unaligned_extendqidi (operands[0],
1429 get_unaligned_address (operands[1], 1));
1431 alpha_set_memflags (seq, operands[1]);
1436 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1437 operands[2] = gen_reg_rtx (DImode);
1440 (define_expand "extendhisi2"
1442 (ashift:DI (match_operand:HI 1 "some_operand" "")
1444 (set (match_operand:SI 0 "register_operand" "")
1445 (ashiftrt:DI (match_dup 2)
1452 emit_insn (gen_extendhisi2x (operands[0],
1453 force_reg (HImode, operands[1])));
1457 /* If we have an unaligned MEM, extend to a DImode form of
1458 the result (which we do specially). */
1459 if (unaligned_memory_operand (operands[1], HImode))
1461 rtx temp = gen_reg_rtx (DImode);
1463 emit_insn (gen_extendhidi2 (temp, operands[1]));
1464 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1468 operands[0] = gen_lowpart (DImode, operands[0]);
1469 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1470 operands[2] = gen_reg_rtx (DImode);
1473 (define_expand "extendhidi2"
1475 (ashift:DI (match_operand:HI 1 "some_operand" "")
1477 (set (match_operand:DI 0 "register_operand" "")
1478 (ashiftrt:DI (match_dup 2)
1485 emit_insn (gen_extendhidi2x (operands[0],
1486 force_reg (HImode, operands[1])));
1490 if (unaligned_memory_operand (operands[1], HImode))
1493 = gen_unaligned_extendhidi (operands[0],
1494 get_unaligned_address (operands[1], 2));
1496 alpha_set_memflags (seq, operands[1]);
1501 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1502 operands[2] = gen_reg_rtx (DImode);
1505 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1506 ;; as a pattern saves one instruction. The code is similar to that for
1507 ;; the unaligned loads (see below).
1509 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1510 (define_expand "unaligned_extendqidi"
1511 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1513 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1516 (ashift:DI (match_dup 3)
1517 (minus:DI (const_int 56)
1519 (and:DI (plus:DI (match_dup 2) (const_int -1))
1522 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1523 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1526 { operands[2] = gen_reg_rtx (DImode);
1527 operands[3] = gen_reg_rtx (DImode);
1528 operands[4] = gen_reg_rtx (DImode);
1531 (define_expand "unaligned_extendhidi"
1532 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1534 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1537 (ashift:DI (match_dup 3)
1538 (minus:DI (const_int 56)
1540 (and:DI (plus:DI (match_dup 2) (const_int -1))
1543 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1544 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1547 { operands[2] = gen_reg_rtx (DImode);
1548 operands[3] = gen_reg_rtx (DImode);
1549 operands[4] = gen_reg_rtx (DImode);
1553 [(set (match_operand:DI 0 "register_operand" "=r")
1554 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1555 (match_operand:DI 2 "mode_width_operand" "n")
1556 (match_operand:DI 3 "mul8_operand" "I")))]
1558 "ext%M2l %r1,%s3,%0"
1559 [(set_attr "type" "shift")])
1561 (define_insn "extxl"
1562 [(set (match_operand:DI 0 "register_operand" "=r")
1563 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1564 (match_operand:DI 2 "mode_width_operand" "n")
1565 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1569 [(set_attr "type" "shift")])
1571 ;; Combine has some strange notion of preserving existing undefined behaviour
1572 ;; in shifts larger than a word size. So capture these patterns that it
1573 ;; should have turned into zero_extracts.
1576 [(set (match_operand:DI 0 "register_operand" "=r")
1577 (and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1578 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1580 (match_operand:DI 3 "mode_mask_operand" "n")))]
1583 [(set_attr "type" "shift")])
1586 [(set (match_operand:DI 0 "register_operand" "=r")
1587 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1588 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1592 [(set_attr "type" "shift")])
1594 (define_insn "extqh"
1595 [(set (match_operand:DI 0 "register_operand" "=r")
1597 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1598 (minus:DI (const_int 56)
1601 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1607 [(set_attr "type" "shift")])
1609 (define_insn "extlh"
1610 [(set (match_operand:DI 0 "register_operand" "=r")
1612 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1613 (const_int 2147483647))
1614 (minus:DI (const_int 56)
1617 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1623 [(set_attr "type" "shift")])
1625 (define_insn "extwh"
1626 [(set (match_operand:DI 0 "register_operand" "=r")
1628 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1630 (minus:DI (const_int 56)
1633 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1639 [(set_attr "type" "shift")])
1641 ;; This converts an extXl into an extXh with an appropriate adjustment
1642 ;; to the address calculation.
1645 ;; [(set (match_operand:DI 0 "register_operand" "")
1646 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1647 ;; (match_operand:DI 2 "mode_width_operand" "")
1648 ;; (ashift:DI (match_operand:DI 3 "" "")
1650 ;; (match_operand:DI 4 "const_int_operand" "")))
1651 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1652 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1653 ;; [(set (match_dup 5) (match_dup 6))
1654 ;; (set (match_dup 0)
1655 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1656 ;; (ashift:DI (plus:DI (match_dup 5)
1662 ;; operands[6] = plus_constant (operands[3],
1663 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1664 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1668 [(set (match_operand:DI 0 "register_operand" "=r")
1669 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1670 (match_operand:DI 2 "mul8_operand" "I")))]
1673 [(set_attr "type" "shift")])
1676 [(set (match_operand:DI 0 "register_operand" "=r")
1677 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1678 (match_operand:DI 2 "mul8_operand" "I")))]
1681 [(set_attr "type" "shift")])
1684 [(set (match_operand:DI 0 "register_operand" "=r")
1685 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1686 (match_operand:DI 2 "mul8_operand" "I")))]
1689 [(set_attr "type" "shift")])
1691 (define_insn "insbl"
1692 [(set (match_operand:DI 0 "register_operand" "=r")
1693 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1694 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1698 [(set_attr "type" "shift")])
1700 (define_insn "inswl"
1701 [(set (match_operand:DI 0 "register_operand" "=r")
1702 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1703 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1707 [(set_attr "type" "shift")])
1709 (define_insn "insll"
1710 [(set (match_operand:DI 0 "register_operand" "=r")
1711 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1712 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1716 [(set_attr "type" "shift")])
1718 (define_insn "insql"
1719 [(set (match_operand:DI 0 "register_operand" "=r")
1720 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1721 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1725 [(set_attr "type" "shift")])
1727 ;; Combine has this sometimes habit of moving the and outside of the
1728 ;; shift, making life more interesting.
1731 [(set (match_operand:DI 0 "register_operand" "=r")
1732 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1733 (match_operand:DI 2 "mul8_operand" "I"))
1734 (match_operand:DI 3 "immediate_operand" "i")))]
1735 "HOST_BITS_PER_WIDE_INT == 64
1736 && GET_CODE (operands[3]) == CONST_INT
1737 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1738 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1739 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1740 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1741 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1742 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1745 #if HOST_BITS_PER_WIDE_INT == 64
1746 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1747 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1748 return \"insbl %1,%s2,%0\";
1749 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1750 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1751 return \"inswl %1,%s2,%0\";
1752 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1753 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1754 return \"insll %1,%s2,%0\";
1758 [(set_attr "type" "shift")])
1760 ;; We do not include the insXh insns because they are complex to express
1761 ;; and it does not appear that we would ever want to generate them.
1763 ;; Since we need them for block moves, though, cop out and use unspec.
1765 (define_insn "insxh"
1766 [(set (match_operand:DI 0 "register_operand" "=r")
1767 (unspec [(match_operand:DI 1 "register_operand" "r")
1768 (match_operand:DI 2 "mode_width_operand" "n")
1769 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1772 [(set_attr "type" "shift")])
1774 (define_insn "mskxl"
1775 [(set (match_operand:DI 0 "register_operand" "=r")
1776 (and:DI (not:DI (ashift:DI
1777 (match_operand:DI 2 "mode_mask_operand" "n")
1779 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1781 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1784 [(set_attr "type" "shift")])
1786 ;; We do not include the mskXh insns because it does not appear we would
1787 ;; ever generate one.
1789 ;; Again, we do for block moves and we use unspec again.
1791 (define_insn "mskxh"
1792 [(set (match_operand:DI 0 "register_operand" "=r")
1793 (unspec [(match_operand:DI 1 "register_operand" "r")
1794 (match_operand:DI 2 "mode_width_operand" "n")
1795 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1798 [(set_attr "type" "shift")])
1800 ;; Floating-point operations. All the double-precision insns can extend
1801 ;; from single, so indicate that. The exception are the ones that simply
1802 ;; play with the sign bits; it's not clear what to do there.
1804 (define_insn "abssf2"
1805 [(set (match_operand:SF 0 "register_operand" "=f")
1806 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1809 [(set_attr "type" "fcpys")])
1811 (define_insn "absdf2"
1812 [(set (match_operand:DF 0 "register_operand" "=f")
1813 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1816 [(set_attr "type" "fcpys")])
1818 (define_insn "negsf2"
1819 [(set (match_operand:SF 0 "register_operand" "=f")
1820 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1823 [(set_attr "type" "fadd")])
1825 (define_insn "negdf2"
1826 [(set (match_operand:DF 0 "register_operand" "=f")
1827 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1830 [(set_attr "type" "fadd")])
1833 [(set (match_operand:SF 0 "register_operand" "=&f")
1834 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1835 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1836 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1837 "add%,%)%& %R1,%R2,%0"
1838 [(set_attr "type" "fadd")
1839 (set_attr "trap" "yes")])
1841 (define_insn "addsf3"
1842 [(set (match_operand:SF 0 "register_operand" "=f")
1843 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1844 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1846 "add%,%)%& %R1,%R2,%0"
1847 [(set_attr "type" "fadd")
1848 (set_attr "trap" "yes")])
1851 [(set (match_operand:DF 0 "register_operand" "=&f")
1852 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1853 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1854 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1855 "add%-%)%& %R1,%R2,%0"
1856 [(set_attr "type" "fadd")
1857 (set_attr "trap" "yes")])
1859 (define_insn "adddf3"
1860 [(set (match_operand:DF 0 "register_operand" "=f")
1861 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1862 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1864 "add%-%)%& %R1,%R2,%0"
1865 [(set_attr "type" "fadd")
1866 (set_attr "trap" "yes")])
1869 [(set (match_operand:DF 0 "register_operand" "=f")
1870 (plus:DF (float_extend:DF
1871 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1872 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1873 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1874 "add%-%)%& %R1,%R2,%0"
1875 [(set_attr "type" "fadd")
1876 (set_attr "trap" "yes")])
1879 [(set (match_operand:DF 0 "register_operand" "=f")
1880 (plus:DF (float_extend:DF
1881 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1883 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1884 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1885 "add%-%)%& %R1,%R2,%0"
1886 [(set_attr "type" "fadd")
1887 (set_attr "trap" "yes")])
1889 ;; Define conversion operators between DFmode and SImode, using the cvtql
1890 ;; instruction. To allow combine et al to do useful things, we keep the
1891 ;; operation as a unit until after reload, at which point we split the
1894 ;; Note that we (attempt to) only consider this optimization when the
1895 ;; ultimate destination is memory. If we will be doing further integer
1896 ;; processing, it is cheaper to do the truncation in the int regs.
1898 (define_insn "*cvtql"
1899 [(set (match_operand:SI 0 "register_operand" "=f")
1900 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1903 [(set_attr "type" "fadd")
1904 (set_attr "trap" "yes")])
1907 [(set (match_operand:SI 0 "memory_operand" "")
1908 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1909 (clobber (match_scratch:DI 2 ""))
1910 (clobber (match_scratch:SI 3 ""))]
1911 "TARGET_FP && reload_completed"
1912 [(set (match_dup 2) (fix:DI (match_dup 1)))
1913 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1914 (set (match_dup 0) (match_dup 3))]
1918 [(set (match_operand:SI 0 "memory_operand" "")
1919 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1920 (clobber (match_scratch:DI 2 ""))]
1921 "TARGET_FP && reload_completed"
1922 [(set (match_dup 2) (fix:DI (match_dup 1)))
1923 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1924 (set (match_dup 0) (match_dup 3))]
1925 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1926 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1929 [(set (match_operand:SI 0 "memory_operand" "=m")
1930 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1931 (clobber (match_scratch:DI 2 "=&f"))
1932 (clobber (match_scratch:SI 3 "=&f"))]
1933 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1935 [(set_attr "type" "fadd")
1936 (set_attr "trap" "yes")])
1939 [(set (match_operand:SI 0 "memory_operand" "=m")
1940 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1941 (clobber (match_scratch:DI 2 "=f"))]
1942 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1944 [(set_attr "type" "fadd")
1945 (set_attr "trap" "yes")])
1948 [(set (match_operand:DI 0 "register_operand" "=&f")
1949 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1950 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1952 [(set_attr "type" "fadd")
1953 (set_attr "trap" "yes")])
1955 (define_insn "fix_truncdfdi2"
1956 [(set (match_operand:DI 0 "register_operand" "=f")
1957 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1960 [(set_attr "type" "fadd")
1961 (set_attr "trap" "yes")])
1963 ;; Likewise between SFmode and SImode.
1966 [(set (match_operand:SI 0 "memory_operand" "")
1967 (subreg:SI (fix:DI (float_extend:DF
1968 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1969 (clobber (match_scratch:DI 2 ""))
1970 (clobber (match_scratch:SI 3 ""))]
1971 "TARGET_FP && reload_completed"
1972 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1973 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1974 (set (match_dup 0) (match_dup 3))]
1978 [(set (match_operand:SI 0 "memory_operand" "")
1979 (subreg:SI (fix:DI (float_extend:DF
1980 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1981 (clobber (match_scratch:DI 2 ""))]
1982 "TARGET_FP && reload_completed"
1983 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1984 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1985 (set (match_dup 0) (match_dup 3))]
1986 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1987 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1990 [(set (match_operand:SI 0 "memory_operand" "=m")
1991 (subreg:SI (fix:DI (float_extend:DF
1992 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1993 (clobber (match_scratch:DI 2 "=&f"))
1994 (clobber (match_scratch:SI 3 "=&f"))]
1995 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1997 [(set_attr "type" "fadd")
1998 (set_attr "trap" "yes")])
2001 [(set (match_operand:SI 0 "memory_operand" "=m")
2002 (subreg:SI (fix:DI (float_extend:DF
2003 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2004 (clobber (match_scratch:DI 2 "=f"))]
2005 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2007 [(set_attr "type" "fadd")
2008 (set_attr "trap" "yes")])
2011 [(set (match_operand:DI 0 "register_operand" "=&f")
2012 (fix:DI (float_extend:DF
2013 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2014 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2016 [(set_attr "type" "fadd")
2017 (set_attr "trap" "yes")])
2019 (define_insn "fix_truncsfdi2"
2020 [(set (match_operand:DI 0 "register_operand" "=f")
2021 (fix:DI (float_extend:DF
2022 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2025 [(set_attr "type" "fadd")
2026 (set_attr "trap" "yes")])
2029 [(set (match_operand:SF 0 "register_operand" "=&f")
2030 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2031 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2033 [(set_attr "type" "fadd")
2034 (set_attr "trap" "yes")])
2036 (define_insn "floatdisf2"
2037 [(set (match_operand:SF 0 "register_operand" "=f")
2038 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2041 [(set_attr "type" "fadd")
2042 (set_attr "trap" "yes")])
2045 [(set (match_operand:DF 0 "register_operand" "=&f")
2046 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2047 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2049 [(set_attr "type" "fadd")
2050 (set_attr "trap" "yes")])
2052 (define_insn "floatdidf2"
2053 [(set (match_operand:DF 0 "register_operand" "=f")
2054 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2057 [(set_attr "type" "fadd")
2058 (set_attr "trap" "yes")])
2060 (define_expand "extendsfdf2"
2061 [(use (match_operand:DF 0 "register_operand" ""))
2062 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
2066 if (alpha_tp == ALPHA_TP_INSN)
2067 emit_insn (gen_extendsfdf2_tp (operands[0],
2068 force_reg (SFmode, operands[1])));
2070 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
2075 (define_insn "extendsfdf2_tp"
2076 [(set (match_operand:DF 0 "register_operand" "=&f")
2077 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2078 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2080 [(set_attr "type" "fadd")
2081 (set_attr "trap" "yes")])
2083 (define_insn "extendsfdf2_no_tp"
2084 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2085 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2086 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2091 [(set_attr "type" "fcpys,fld,fst")
2092 (set_attr "trap" "yes")])
2095 [(set (match_operand:SF 0 "register_operand" "=&f")
2096 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2097 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2098 "cvt%-%,%)%& %R1,%0"
2099 [(set_attr "type" "fadd")
2100 (set_attr "trap" "yes")])
2102 (define_insn "truncdfsf2"
2103 [(set (match_operand:SF 0 "register_operand" "=f")
2104 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2106 "cvt%-%,%)%& %R1,%0"
2107 [(set_attr "type" "fadd")
2108 (set_attr "trap" "yes")])
2111 [(set (match_operand:SF 0 "register_operand" "=&f")
2112 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2113 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2114 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2115 "div%,%)%& %R1,%R2,%0"
2116 [(set_attr "type" "fdiv")
2117 (set_attr "opsize" "si")
2118 (set_attr "trap" "yes")])
2120 (define_insn "divsf3"
2121 [(set (match_operand:SF 0 "register_operand" "=f")
2122 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2123 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2125 "div%,%)%& %R1,%R2,%0"
2126 [(set_attr "type" "fdiv")
2127 (set_attr "opsize" "si")
2128 (set_attr "trap" "yes")])
2131 [(set (match_operand:DF 0 "register_operand" "=&f")
2132 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2133 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2134 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2135 "div%-%)%& %R1,%R2,%0"
2136 [(set_attr "type" "fdiv")
2137 (set_attr "trap" "yes")])
2139 (define_insn "divdf3"
2140 [(set (match_operand:DF 0 "register_operand" "=f")
2141 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2142 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2144 "div%-%)%& %R1,%R2,%0"
2145 [(set_attr "type" "fdiv")
2146 (set_attr "trap" "yes")])
2149 [(set (match_operand:DF 0 "register_operand" "=f")
2150 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2151 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2152 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2153 "div%-%)%& %R1,%R2,%0"
2154 [(set_attr "type" "fdiv")
2155 (set_attr "trap" "yes")])
2158 [(set (match_operand:DF 0 "register_operand" "=f")
2159 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2161 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2162 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2163 "div%-%)%& %R1,%R2,%0"
2164 [(set_attr "type" "fdiv")
2165 (set_attr "trap" "yes")])
2168 [(set (match_operand:DF 0 "register_operand" "=f")
2169 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2170 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2171 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2172 "div%-%)%& %R1,%R2,%0"
2173 [(set_attr "type" "fdiv")
2174 (set_attr "trap" "yes")])
2177 [(set (match_operand:SF 0 "register_operand" "=&f")
2178 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2179 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2180 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2181 "mul%,%)%& %R1,%R2,%0"
2182 [(set_attr "type" "fmul")
2183 (set_attr "trap" "yes")])
2185 (define_insn "mulsf3"
2186 [(set (match_operand:SF 0 "register_operand" "=f")
2187 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2188 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2190 "mul%,%)%& %R1,%R2,%0"
2191 [(set_attr "type" "fmul")
2192 (set_attr "trap" "yes")])
2195 [(set (match_operand:DF 0 "register_operand" "=&f")
2196 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2197 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2198 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2199 "mul%-%)%& %R1,%R2,%0"
2200 [(set_attr "type" "fmul")
2201 (set_attr "trap" "yes")])
2203 (define_insn "muldf3"
2204 [(set (match_operand:DF 0 "register_operand" "=f")
2205 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2206 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2208 "mul%-%)%& %R1,%R2,%0"
2209 [(set_attr "type" "fmul")
2210 (set_attr "trap" "yes")])
2213 [(set (match_operand:DF 0 "register_operand" "=f")
2214 (mult:DF (float_extend:DF
2215 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2216 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2217 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2218 "mul%-%)%& %R1,%R2,%0"
2219 [(set_attr "type" "fmul")
2220 (set_attr "trap" "yes")])
2223 [(set (match_operand:DF 0 "register_operand" "=f")
2224 (mult:DF (float_extend:DF
2225 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2227 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2228 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2229 "mul%-%)%& %R1,%R2,%0"
2230 [(set_attr "type" "fmul")
2231 (set_attr "trap" "yes")])
2234 [(set (match_operand:SF 0 "register_operand" "=&f")
2235 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2236 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2237 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2238 "sub%,%)%& %R1,%R2,%0"
2239 [(set_attr "type" "fadd")
2240 (set_attr "trap" "yes")])
2242 (define_insn "subsf3"
2243 [(set (match_operand:SF 0 "register_operand" "=f")
2244 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2245 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2247 "sub%,%)%& %R1,%R2,%0"
2248 [(set_attr "type" "fadd")
2249 (set_attr "trap" "yes")])
2252 [(set (match_operand:DF 0 "register_operand" "=&f")
2253 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2254 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2255 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2256 "sub%-%)%& %R1,%R2,%0"
2257 [(set_attr "type" "fadd")
2258 (set_attr "trap" "yes")])
2260 (define_insn "subdf3"
2261 [(set (match_operand:DF 0 "register_operand" "=f")
2262 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2263 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2265 "sub%-%)%& %R1,%R2,%0"
2266 [(set_attr "type" "fadd")
2267 (set_attr "trap" "yes")])
2270 [(set (match_operand:DF 0 "register_operand" "=f")
2271 (minus:DF (float_extend:DF
2272 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2273 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2274 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2275 "sub%-%)%& %R1,%R2,%0"
2276 [(set_attr "type" "fadd")
2277 (set_attr "trap" "yes")])
2280 [(set (match_operand:DF 0 "register_operand" "=f")
2281 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2283 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2284 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2285 "sub%-%)%& %R1,%R2,%0"
2286 [(set_attr "type" "fadd")
2287 (set_attr "trap" "yes")])
2290 [(set (match_operand:DF 0 "register_operand" "=f")
2291 (minus:DF (float_extend:DF
2292 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2294 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2295 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2296 "sub%-%)%& %R1,%R2,%0"
2297 [(set_attr "type" "fadd")
2298 (set_attr "trap" "yes")])
2301 [(set (match_operand:SF 0 "register_operand" "=&f")
2302 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2303 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2305 [(set_attr "type" "fsqrt")
2306 (set_attr "opsize" "si")
2307 (set_attr "trap" "yes")])
2309 (define_insn "sqrtsf2"
2310 [(set (match_operand:SF 0 "register_operand" "=f")
2311 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2312 "TARGET_FP && TARGET_CIX"
2314 [(set_attr "type" "fsqrt")
2315 (set_attr "opsize" "si")
2316 (set_attr "trap" "yes")])
2319 [(set (match_operand:DF 0 "register_operand" "=&f")
2320 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2321 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2323 [(set_attr "type" "fsqrt")
2324 (set_attr "trap" "yes")])
2326 (define_insn "sqrtdf2"
2327 [(set (match_operand:DF 0 "register_operand" "=f")
2328 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2329 "TARGET_FP && TARGET_CIX"
2331 [(set_attr "type" "fsqrt")
2332 (set_attr "trap" "yes")])
2334 ;; Next are all the integer comparisons, and conditional moves and branches
2335 ;; and some of the related define_expand's and define_split's.
2338 [(set (match_operand:DI 0 "register_operand" "=r")
2339 (match_operator:DI 1 "alpha_comparison_operator"
2340 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2341 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2344 [(set_attr "type" "icmp")])
2347 [(set (match_operand:DI 0 "register_operand" "=r")
2348 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2349 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2350 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2353 [(set_attr "type" "icmp")])
2355 ;; This pattern exists so conditional moves of SImode values are handled.
2356 ;; Comparisons are still done in DImode though.
2359 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2361 (match_operator 2 "signed_comparison_operator"
2362 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2363 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2364 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2365 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2366 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2372 [(set_attr "type" "icmov")])
2375 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2377 (match_operator 2 "signed_comparison_operator"
2378 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2379 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2380 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2381 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2382 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2388 [(set_attr "type" "icmov")])
2391 [(set (match_operand:DI 0 "register_operand" "=r,r")
2393 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2397 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2398 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2403 [(set_attr "type" "icmov")])
2406 [(set (match_operand:DI 0 "register_operand" "=r,r")
2408 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2412 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2413 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2418 [(set_attr "type" "icmov")])
2420 ;; For ABS, we have two choices, depending on whether the input and output
2421 ;; registers are the same or not.
2422 (define_expand "absdi2"
2423 [(set (match_operand:DI 0 "register_operand" "")
2424 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2427 { if (rtx_equal_p (operands[0], operands[1]))
2428 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2430 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2435 (define_expand "absdi2_same"
2436 [(set (match_operand:DI 1 "register_operand" "")
2437 (neg:DI (match_operand:DI 0 "register_operand" "")))
2439 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2445 (define_expand "absdi2_diff"
2446 [(set (match_operand:DI 0 "register_operand" "")
2447 (neg:DI (match_operand:DI 1 "register_operand" "")))
2449 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2456 [(set (match_operand:DI 0 "register_operand" "")
2457 (abs:DI (match_dup 0)))
2458 (clobber (match_operand:DI 2 "register_operand" ""))]
2460 [(set (match_dup 1) (neg:DI (match_dup 0)))
2461 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2462 (match_dup 0) (match_dup 1)))]
2466 [(set (match_operand:DI 0 "register_operand" "")
2467 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2468 "! rtx_equal_p (operands[0], operands[1])"
2469 [(set (match_dup 0) (neg:DI (match_dup 1)))
2470 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2471 (match_dup 0) (match_dup 1)))]
2475 [(set (match_operand:DI 0 "register_operand" "")
2476 (neg:DI (abs:DI (match_dup 0))))
2477 (clobber (match_operand:DI 2 "register_operand" ""))]
2479 [(set (match_dup 1) (neg:DI (match_dup 0)))
2480 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2481 (match_dup 0) (match_dup 1)))]
2485 [(set (match_operand:DI 0 "register_operand" "")
2486 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2487 "! rtx_equal_p (operands[0], operands[1])"
2488 [(set (match_dup 0) (neg:DI (match_dup 1)))
2489 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2490 (match_dup 0) (match_dup 1)))]
2493 (define_insn "sminqi3"
2494 [(set (match_operand:QI 0 "register_operand" "=r")
2495 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2496 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2499 [(set_attr "type" "mvi")])
2501 (define_insn "uminqi3"
2502 [(set (match_operand:QI 0 "register_operand" "=r")
2503 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2504 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2507 [(set_attr "type" "mvi")])
2509 (define_insn "smaxqi3"
2510 [(set (match_operand:QI 0 "register_operand" "=r")
2511 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2512 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2515 [(set_attr "type" "mvi")])
2517 (define_insn "umaxqi3"
2518 [(set (match_operand:QI 0 "register_operand" "=r")
2519 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2520 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2523 [(set_attr "type" "mvi")])
2525 (define_insn "sminhi3"
2526 [(set (match_operand:HI 0 "register_operand" "=r")
2527 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2528 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2531 [(set_attr "type" "mvi")])
2533 (define_insn "uminhi3"
2534 [(set (match_operand:HI 0 "register_operand" "=r")
2535 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2536 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2539 [(set_attr "type" "mvi")])
2541 (define_insn "smaxhi3"
2542 [(set (match_operand:HI 0 "register_operand" "=r")
2543 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2544 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2547 [(set_attr "type" "mvi")])
2549 (define_insn "umaxhi3"
2550 [(set (match_operand:HI 0 "register_operand" "=r")
2551 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2552 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2555 [(set_attr "type" "shift")])
2557 (define_expand "smaxdi3"
2559 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2560 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2561 (set (match_operand:DI 0 "register_operand" "")
2562 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2563 (match_dup 1) (match_dup 2)))]
2566 { operands[3] = gen_reg_rtx (DImode);
2570 [(set (match_operand:DI 0 "register_operand" "")
2571 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2572 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2573 (clobber (match_operand:DI 3 "register_operand" ""))]
2574 "operands[2] != const0_rtx"
2575 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2576 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2577 (match_dup 1) (match_dup 2)))]
2581 [(set (match_operand:DI 0 "register_operand" "=r")
2582 (smax:DI (match_operand:DI 1 "register_operand" "0")
2586 [(set_attr "type" "icmov")])
2588 (define_expand "smindi3"
2590 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2591 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2592 (set (match_operand:DI 0 "register_operand" "")
2593 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2594 (match_dup 1) (match_dup 2)))]
2597 { operands[3] = gen_reg_rtx (DImode);
2601 [(set (match_operand:DI 0 "register_operand" "")
2602 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2603 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2604 (clobber (match_operand:DI 3 "register_operand" ""))]
2605 "operands[2] != const0_rtx"
2606 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2607 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2608 (match_dup 1) (match_dup 2)))]
2612 [(set (match_operand:DI 0 "register_operand" "=r")
2613 (smin:DI (match_operand:DI 1 "register_operand" "0")
2617 [(set_attr "type" "icmov")])
2619 (define_expand "umaxdi3"
2621 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2622 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2623 (set (match_operand:DI 0 "register_operand" "")
2624 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2625 (match_dup 1) (match_dup 2)))]
2628 { operands[3] = gen_reg_rtx (DImode);
2632 [(set (match_operand:DI 0 "register_operand" "")
2633 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2634 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2635 (clobber (match_operand:DI 3 "register_operand" ""))]
2636 "operands[2] != const0_rtx"
2637 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2638 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2639 (match_dup 1) (match_dup 2)))]
2642 (define_expand "umindi3"
2644 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2645 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2646 (set (match_operand:DI 0 "register_operand" "")
2647 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2648 (match_dup 1) (match_dup 2)))]
2651 { operands[3] = gen_reg_rtx (DImode);
2655 [(set (match_operand:DI 0 "register_operand" "")
2656 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2657 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2658 (clobber (match_operand:DI 3 "register_operand" ""))]
2659 "operands[2] != const0_rtx"
2660 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2661 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2662 (match_dup 1) (match_dup 2)))]
2668 (match_operator 1 "signed_comparison_operator"
2669 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2671 (label_ref (match_operand 0 "" ""))
2675 [(set_attr "type" "ibr")])
2680 (match_operator 1 "signed_comparison_operator"
2682 (match_operand:DI 2 "register_operand" "r")])
2683 (label_ref (match_operand 0 "" ""))
2687 [(set_attr "type" "ibr")])
2692 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2696 (label_ref (match_operand 0 "" ""))
2700 [(set_attr "type" "ibr")])
2705 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2709 (label_ref (match_operand 0 "" ""))
2713 [(set_attr "type" "ibr")])
2719 (match_operator 1 "comparison_operator"
2720 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2722 (match_operand:DI 3 "const_int_operand" ""))
2724 (label_ref (match_operand 0 "" ""))
2726 (clobber (match_operand:DI 4 "register_operand" ""))])]
2727 "INTVAL (operands[3]) != 0"
2729 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2731 (if_then_else (match_op_dup 1
2732 [(zero_extract:DI (match_dup 4)
2736 (label_ref (match_dup 0))
2740 ;; The following are the corresponding floating-point insns. Recall
2741 ;; we need to have variants that expand the arguments from SF mode
2745 [(set (match_operand:DF 0 "register_operand" "=&f")
2746 (match_operator:DF 1 "alpha_comparison_operator"
2747 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2748 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2749 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2750 "cmp%-%C1%' %R2,%R3,%0"
2751 [(set_attr "type" "fadd")
2752 (set_attr "trap" "yes")])
2755 [(set (match_operand:DF 0 "register_operand" "=f")
2756 (match_operator:DF 1 "alpha_comparison_operator"
2757 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2758 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2759 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2760 "cmp%-%C1%' %R2,%R3,%0"
2761 [(set_attr "type" "fadd")
2762 (set_attr "trap" "yes")])
2765 [(set (match_operand:DF 0 "register_operand" "=&f")
2766 (match_operator:DF 1 "alpha_comparison_operator"
2768 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2769 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2770 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2771 "cmp%-%C1%' %R2,%R3,%0"
2772 [(set_attr "type" "fadd")
2773 (set_attr "trap" "yes")])
2776 [(set (match_operand:DF 0 "register_operand" "=f")
2777 (match_operator:DF 1 "alpha_comparison_operator"
2779 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2780 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2781 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2782 "cmp%-%C1%' %R2,%R3,%0"
2783 [(set_attr "type" "fadd")
2784 (set_attr "trap" "yes")])
2787 [(set (match_operand:DF 0 "register_operand" "=&f")
2788 (match_operator:DF 1 "alpha_comparison_operator"
2789 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2791 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2792 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2793 "cmp%-%C1%' %R2,%R3,%0"
2794 [(set_attr "type" "fadd")
2795 (set_attr "trap" "yes")])
2798 [(set (match_operand:DF 0 "register_operand" "=f")
2799 (match_operator:DF 1 "alpha_comparison_operator"
2800 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2802 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2803 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2804 "cmp%-%C1%' %R2,%R3,%0"
2805 [(set_attr "type" "fadd")
2806 (set_attr "trap" "yes")])
2809 [(set (match_operand:DF 0 "register_operand" "=&f")
2810 (match_operator:DF 1 "alpha_comparison_operator"
2812 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2814 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2815 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2816 "cmp%-%C1%' %R2,%R3,%0"
2817 [(set_attr "type" "fadd")
2818 (set_attr "trap" "yes")])
2821 [(set (match_operand:DF 0 "register_operand" "=f")
2822 (match_operator:DF 1 "alpha_comparison_operator"
2824 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2826 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2827 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2828 "cmp%-%C1%' %R2,%R3,%0"
2829 [(set_attr "type" "fadd")
2830 (set_attr "trap" "yes")])
2833 [(set (match_operand:DF 0 "register_operand" "=f,f")
2835 (match_operator 3 "signed_comparison_operator"
2836 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2837 (match_operand:DF 2 "fp0_operand" "G,G")])
2838 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2839 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2843 fcmov%D3 %R4,%R5,%0"
2844 [(set_attr "type" "fcmov")])
2847 [(set (match_operand:SF 0 "register_operand" "=f,f")
2849 (match_operator 3 "signed_comparison_operator"
2850 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2851 (match_operand:DF 2 "fp0_operand" "G,G")])
2852 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2853 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2857 fcmov%D3 %R4,%R5,%0"
2858 [(set_attr "type" "fcmov")])
2861 [(set (match_operand:DF 0 "register_operand" "=f,f")
2863 (match_operator 3 "signed_comparison_operator"
2864 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2865 (match_operand:DF 2 "fp0_operand" "G,G")])
2866 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2867 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2871 fcmov%D3 %R4,%R5,%0"
2872 [(set_attr "type" "fcmov")])
2875 [(set (match_operand:DF 0 "register_operand" "=f,f")
2877 (match_operator 3 "signed_comparison_operator"
2879 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2880 (match_operand:DF 2 "fp0_operand" "G,G")])
2881 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2882 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2886 fcmov%D3 %R4,%R5,%0"
2887 [(set_attr "type" "fcmov")])
2890 [(set (match_operand:SF 0 "register_operand" "=f,f")
2892 (match_operator 3 "signed_comparison_operator"
2894 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2895 (match_operand:DF 2 "fp0_operand" "G,G")])
2896 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2897 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2901 fcmov%D3 %R4,%R5,%0"
2902 [(set_attr "type" "fcmov")])
2905 [(set (match_operand:DF 0 "register_operand" "=f,f")
2907 (match_operator 3 "signed_comparison_operator"
2909 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2910 (match_operand:DF 2 "fp0_operand" "G,G")])
2911 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2912 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2916 fcmov%D3 %R4,%R5,%0"
2917 [(set_attr "type" "fcmov")])
2919 (define_expand "maxdf3"
2921 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2922 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2923 (set (match_operand:DF 0 "register_operand" "")
2924 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2925 (match_dup 1) (match_dup 2)))]
2928 { operands[3] = gen_reg_rtx (DFmode);
2929 operands[4] = CONST0_RTX (DFmode);
2932 (define_expand "mindf3"
2934 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2935 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2936 (set (match_operand:DF 0 "register_operand" "")
2937 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2938 (match_dup 1) (match_dup 2)))]
2941 { operands[3] = gen_reg_rtx (DFmode);
2942 operands[4] = CONST0_RTX (DFmode);
2945 (define_expand "maxsf3"
2947 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2948 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2949 (set (match_operand:SF 0 "register_operand" "")
2950 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2951 (match_dup 1) (match_dup 2)))]
2954 { operands[3] = gen_reg_rtx (DFmode);
2955 operands[4] = CONST0_RTX (DFmode);
2958 (define_expand "minsf3"
2960 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2961 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2962 (set (match_operand:SF 0 "register_operand" "")
2963 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2964 (match_dup 1) (match_dup 2)))]
2967 { operands[3] = gen_reg_rtx (DFmode);
2968 operands[4] = CONST0_RTX (DFmode);
2974 (match_operator 1 "signed_comparison_operator"
2975 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2976 (match_operand:DF 3 "fp0_operand" "G")])
2977 (label_ref (match_operand 0 "" ""))
2981 [(set_attr "type" "fbr")])
2986 (match_operator 1 "signed_comparison_operator"
2988 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2989 (match_operand:DF 3 "fp0_operand" "G")])
2990 (label_ref (match_operand 0 "" ""))
2994 [(set_attr "type" "fbr")])
2996 ;; These are the main define_expand's used to make conditional branches
2999 (define_expand "cmpdf"
3000 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3001 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3005 alpha_compare_op0 = operands[0];
3006 alpha_compare_op1 = operands[1];
3007 alpha_compare_fp_p = 1;
3011 (define_expand "cmpdi"
3012 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3013 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3017 alpha_compare_op0 = operands[0];
3018 alpha_compare_op1 = operands[1];
3019 alpha_compare_fp_p = 0;
3023 (define_expand "beq"
3025 (if_then_else (match_dup 1)
3026 (label_ref (match_operand 0 "" ""))
3029 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3031 (define_expand "bne"
3033 (if_then_else (match_dup 1)
3034 (label_ref (match_operand 0 "" ""))
3037 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3039 (define_expand "blt"
3041 (if_then_else (match_dup 1)
3042 (label_ref (match_operand 0 "" ""))
3045 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3047 (define_expand "ble"
3049 (if_then_else (match_dup 1)
3050 (label_ref (match_operand 0 "" ""))
3053 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3055 (define_expand "bgt"
3057 (if_then_else (match_dup 1)
3058 (label_ref (match_operand 0 "" ""))
3061 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3063 (define_expand "bge"
3065 (if_then_else (match_dup 1)
3066 (label_ref (match_operand 0 "" ""))
3069 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3071 (define_expand "bltu"
3073 (if_then_else (match_dup 1)
3074 (label_ref (match_operand 0 "" ""))
3077 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3079 (define_expand "bleu"
3081 (if_then_else (match_dup 1)
3082 (label_ref (match_operand 0 "" ""))
3085 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3087 (define_expand "bgtu"
3089 (if_then_else (match_dup 1)
3090 (label_ref (match_operand 0 "" ""))
3093 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3095 (define_expand "bgeu"
3097 (if_then_else (match_dup 1)
3098 (label_ref (match_operand 0 "" ""))
3101 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3103 (define_expand "seq"
3104 [(set (match_operand:DI 0 "register_operand" "")
3109 if (alpha_compare_fp_p)
3112 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3115 (define_expand "sne"
3116 [(set (match_operand:DI 0 "register_operand" "")
3118 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3122 if (alpha_compare_fp_p)
3125 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3128 (define_expand "slt"
3129 [(set (match_operand:DI 0 "register_operand" "")
3134 if (alpha_compare_fp_p)
3137 operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1);
3140 (define_expand "sle"
3141 [(set (match_operand:DI 0 "register_operand" "")
3146 if (alpha_compare_fp_p)
3149 operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1);
3152 (define_expand "sgt"
3153 [(set (match_operand:DI 0 "register_operand" "")
3158 if (alpha_compare_fp_p)
3161 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1),
3165 (define_expand "sge"
3166 [(set (match_operand:DI 0 "register_operand" "")
3171 if (alpha_compare_fp_p)
3174 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1),
3178 (define_expand "sltu"
3179 [(set (match_operand:DI 0 "register_operand" "")
3184 if (alpha_compare_fp_p)
3187 operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1);
3190 (define_expand "sleu"
3191 [(set (match_operand:DI 0 "register_operand" "")
3196 if (alpha_compare_fp_p)
3199 operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1);
3202 (define_expand "sgtu"
3203 [(set (match_operand:DI 0 "register_operand" "")
3208 if (alpha_compare_fp_p)
3211 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1),
3215 (define_expand "sgeu"
3216 [(set (match_operand:DI 0 "register_operand" "")
3221 if (alpha_compare_fp_p)
3224 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1),
3228 ;; These are the main define_expand's used to make conditional moves.
3230 (define_expand "movsicc"
3231 [(set (match_operand:SI 0 "register_operand" "")
3232 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3233 (match_operand:SI 2 "reg_or_8bit_operand" "")
3234 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3238 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3242 (define_expand "movdicc"
3243 [(set (match_operand:DI 0 "register_operand" "")
3244 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3245 (match_operand:DI 2 "reg_or_8bit_operand" "")
3246 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3250 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3254 (define_expand "movsfcc"
3255 [(set (match_operand:SF 0 "register_operand" "")
3256 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3257 (match_operand:SF 2 "reg_or_8bit_operand" "")
3258 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3262 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3266 (define_expand "movdfcc"
3267 [(set (match_operand:DF 0 "register_operand" "")
3268 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3269 (match_operand:DF 2 "reg_or_8bit_operand" "")
3270 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3274 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3278 ;; These define_split definitions are used in cases when comparisons have
3279 ;; not be stated in the correct way and we need to reverse the second
3280 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3281 ;; comparison that tests the result being reversed. We have one define_split
3282 ;; for each use of a comparison. They do not match valid insns and need
3283 ;; not generate valid insns.
3285 ;; We can also handle equality comparisons (and inequality comparisons in
3286 ;; cases where the resulting add cannot overflow) by doing an add followed by
3287 ;; a comparison with zero. This is faster since the addition takes one
3288 ;; less cycle than a compare when feeding into a conditional move.
3289 ;; For this case, we also have an SImode pattern since we can merge the add
3290 ;; and sign extend and the order doesn't matter.
3292 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3293 ;; operation could have been generated.
3296 [(set (match_operand:DI 0 "register_operand" "")
3298 (match_operator 1 "comparison_operator"
3299 [(match_operand:DI 2 "reg_or_0_operand" "")
3300 (match_operand:DI 3 "reg_or_cint_operand" "")])
3301 (match_operand:DI 4 "reg_or_cint_operand" "")
3302 (match_operand:DI 5 "reg_or_cint_operand" "")))
3303 (clobber (match_operand:DI 6 "register_operand" ""))]
3304 "operands[3] != const0_rtx"
3305 [(set (match_dup 6) (match_dup 7))
3307 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3309 { enum rtx_code code = GET_CODE (operands[1]);
3310 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3312 /* If we are comparing for equality with a constant and that constant
3313 appears in the arm when the register equals the constant, use the
3314 register since that is more likely to match (and to produce better code
3317 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3318 && rtx_equal_p (operands[4], operands[3]))
3319 operands[4] = operands[2];
3321 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3322 && rtx_equal_p (operands[5], operands[3]))
3323 operands[5] = operands[2];
3325 if (code == NE || code == EQ
3326 || (extended_count (operands[2], DImode, unsignedp) >= 1
3327 && extended_count (operands[3], DImode, unsignedp) >= 1))
3329 if (GET_CODE (operands[3]) == CONST_INT)
3330 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3331 GEN_INT (- INTVAL (operands[3])));
3333 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3335 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3338 else if (code == EQ || code == LE || code == LT
3339 || code == LEU || code == LTU)
3341 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3342 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3346 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3347 operands[2], operands[3]);
3348 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3353 [(set (match_operand:DI 0 "register_operand" "")
3355 (match_operator 1 "comparison_operator"
3356 [(match_operand:SI 2 "reg_or_0_operand" "")
3357 (match_operand:SI 3 "reg_or_cint_operand" "")])
3358 (match_operand:DI 4 "reg_or_8bit_operand" "")
3359 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3360 (clobber (match_operand:DI 6 "register_operand" ""))]
3361 "operands[3] != const0_rtx
3362 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3363 [(set (match_dup 6) (match_dup 7))
3365 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3367 { enum rtx_code code = GET_CODE (operands[1]);
3368 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3371 if ((code != NE && code != EQ
3372 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3373 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3376 if (GET_CODE (operands[3]) == CONST_INT)
3377 tem = gen_rtx_PLUS (SImode, operands[2],
3378 GEN_INT (- INTVAL (operands[3])));
3380 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3382 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3383 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3384 operands[6], const0_rtx);
3390 (match_operator 1 "comparison_operator"
3391 [(match_operand:DI 2 "reg_or_0_operand" "")
3392 (match_operand:DI 3 "reg_or_cint_operand" "")])
3393 (label_ref (match_operand 0 "" ""))
3395 (clobber (match_operand:DI 4 "register_operand" ""))]
3396 "operands[3] != const0_rtx"
3397 [(set (match_dup 4) (match_dup 5))
3398 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3400 { enum rtx_code code = GET_CODE (operands[1]);
3401 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3403 if (code == NE || code == EQ
3404 || (extended_count (operands[2], DImode, unsignedp) >= 1
3405 && extended_count (operands[3], DImode, unsignedp) >= 1))
3407 if (GET_CODE (operands[3]) == CONST_INT)
3408 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3409 GEN_INT (- INTVAL (operands[3])));
3411 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3413 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3416 else if (code == EQ || code == LE || code == LT
3417 || code == LEU || code == LTU)
3419 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3420 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3424 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3425 operands[2], operands[3]);
3426 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3433 (match_operator 1 "comparison_operator"
3434 [(match_operand:SI 2 "reg_or_0_operand" "")
3435 (match_operand:SI 3 "const_int_operand" "")])
3436 (label_ref (match_operand 0 "" ""))
3438 (clobber (match_operand:DI 4 "register_operand" ""))]
3439 "operands[3] != const0_rtx
3440 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3441 [(set (match_dup 4) (match_dup 5))
3442 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3446 if (GET_CODE (operands[3]) == CONST_INT)
3447 tem = gen_rtx_PLUS (SImode, operands[2],
3448 GEN_INT (- INTVAL (operands[3])));
3450 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3452 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3453 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3454 operands[4], const0_rtx);
3457 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3458 ;; This eliminates one, and sometimes two, insns when the AND can be done
3461 [(set (match_operand:DI 0 "register_operand" "")
3462 (match_operator 1 "comparison_operator"
3463 [(match_operand:DI 2 "register_operand" "")
3464 (match_operand:DI 3 "const_int_operand" "")]))
3465 (clobber (match_operand:DI 4 "register_operand" ""))]
3466 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3467 && (GET_CODE (operands[1]) == GTU
3468 || GET_CODE (operands[1]) == LEU
3469 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3470 && extended_count (operands[2], DImode, 1) > 0))"
3471 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3472 (set (match_dup 0) (match_dup 6))]
3475 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3476 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3477 || GET_CODE (operands[1]) == GT)
3479 DImode, operands[4], const0_rtx);
3482 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3483 ;; work differently, so we have different patterns for each.
3485 (define_expand "call"
3486 [(use (match_operand:DI 0 "" ""))
3487 (use (match_operand 1 "" ""))
3488 (use (match_operand 2 "" ""))
3489 (use (match_operand 3 "" ""))]
3492 { if (TARGET_WINDOWS_NT)
3493 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3494 else if (TARGET_OPEN_VMS)
3495 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3497 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3502 (define_expand "call_osf"
3503 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3504 (match_operand 1 "" ""))
3505 (clobber (reg:DI 27))
3506 (clobber (reg:DI 26))])]
3509 { if (GET_CODE (operands[0]) != MEM)
3512 operands[0] = XEXP (operands[0], 0);
3514 if (GET_CODE (operands[0]) != SYMBOL_REF
3515 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3517 rtx tem = gen_rtx_REG (DImode, 27);
3518 emit_move_insn (tem, operands[0]);
3523 (define_expand "call_nt"
3524 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3525 (match_operand 1 "" ""))
3526 (clobber (reg:DI 26))])]
3529 { if (GET_CODE (operands[0]) != MEM)
3532 operands[0] = XEXP (operands[0], 0);
3533 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3534 operands[0] = force_reg (DImode, operands[0]);
3538 ;; call openvms/alpha
3539 ;; op 0: symbol ref for called function
3540 ;; op 1: next_arg_reg (argument information value for R25)
3542 (define_expand "call_vms"
3543 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3544 (match_operand 1 "" ""))
3548 (clobber (reg:DI 27))])]
3551 { if (GET_CODE (operands[0]) != MEM)
3554 operands[0] = XEXP (operands[0], 0);
3556 /* Always load AI with argument information, then handle symbolic and
3557 indirect call differently. Load RA and set operands[2] to PV in
3560 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3561 if (GET_CODE (operands[0]) == SYMBOL_REF)
3563 extern char *savealloc ();
3564 char *linksym, *symbol = XSTR (operands[0], 0);
3569 linksym = savealloc (strlen (symbol) + 6);
3571 alpha_need_linkage (symbol, 0);
3574 strcpy (linksym+1, symbol);
3575 strcat (linksym, \"..lk\");
3576 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3578 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3581 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3585 emit_move_insn (gen_rtx_REG (Pmode, 26),
3586 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3588 operands[2] = operands[0];
3593 (define_expand "call_value"
3594 [(use (match_operand 0 "" ""))
3595 (use (match_operand:DI 1 "" ""))
3596 (use (match_operand 2 "" ""))
3597 (use (match_operand 3 "" ""))
3598 (use (match_operand 4 "" ""))]
3601 { if (TARGET_WINDOWS_NT)
3602 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3603 else if (TARGET_OPEN_VMS)
3604 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3607 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3612 (define_expand "call_value_osf"
3613 [(parallel [(set (match_operand 0 "" "")
3614 (call (mem:DI (match_operand 1 "" ""))
3615 (match_operand 2 "" "")))
3616 (clobber (reg:DI 27))
3617 (clobber (reg:DI 26))])]
3620 { if (GET_CODE (operands[1]) != MEM)
3623 operands[1] = XEXP (operands[1], 0);
3625 if (GET_CODE (operands[1]) != SYMBOL_REF
3626 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3628 rtx tem = gen_rtx_REG (DImode, 27);
3629 emit_move_insn (tem, operands[1]);
3634 (define_expand "call_value_nt"
3635 [(parallel [(set (match_operand 0 "" "")
3636 (call (mem:DI (match_operand 1 "" ""))
3637 (match_operand 2 "" "")))
3638 (clobber (reg:DI 26))])]
3641 { if (GET_CODE (operands[1]) != MEM)
3644 operands[1] = XEXP (operands[1], 0);
3645 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3646 operands[1] = force_reg (DImode, operands[1]);
3649 (define_expand "call_value_vms"
3650 [(parallel [(set (match_operand 0 "" "")
3651 (call (mem:DI (match_operand:DI 1 "" ""))
3652 (match_operand 2 "" "")))
3656 (clobber (reg:DI 27))])]
3659 { if (GET_CODE (operands[1]) != MEM)
3662 operands[1] = XEXP (operands[1], 0);
3664 /* Always load AI with argument information, then handle symbolic and
3665 indirect call differently. Load RA and set operands[3] to PV in
3668 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3669 if (GET_CODE (operands[1]) == SYMBOL_REF)
3671 extern char *savealloc ();
3672 char *linksym, *symbol = XSTR (operands[1], 0);
3677 linksym = savealloc (strlen (symbol) + 6);
3679 alpha_need_linkage (symbol, 0);
3681 strcpy (linksym+1, symbol);
3682 strcat (linksym, \"..lk\");
3683 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3685 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3688 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3692 emit_move_insn (gen_rtx_REG (Pmode, 26),
3693 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3695 operands[3] = operands[1];
3700 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3701 (match_operand 1 "" ""))
3702 (clobber (reg:DI 27))
3703 (clobber (reg:DI 26))]
3704 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3706 jsr $26,($27),0\;ldgp $29,0($26)
3708 jsr $26,%0\;ldgp $29,0($26)"
3709 [(set_attr "type" "jsr")
3710 (set_attr "length" "12,*,16")])
3713 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3714 (match_operand 1 "" ""))
3715 (clobber (reg:DI 26))]
3721 [(set_attr "type" "jsr")
3722 (set_attr "length" "*,*,12")])
3725 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3726 (match_operand 1 "" ""))
3727 (use (match_operand:DI 2 "general_operand" "r,m"))
3730 (clobber (reg:DI 27))]
3733 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3734 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3735 [(set_attr "type" "jsr")
3736 (set_attr "length" "12,16")])
3739 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3740 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3741 (match_operand 2 "" "")))
3742 (clobber (reg:DI 27))
3743 (clobber (reg:DI 26))]
3744 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3746 jsr $26,($27),0\;ldgp $29,0($26)
3748 jsr $26,%1\;ldgp $29,0($26)"
3749 [(set_attr "type" "jsr")
3750 (set_attr "length" "12,*,16")])
3753 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3754 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3755 (match_operand 2 "" "")))
3756 (clobber (reg:DI 26))]
3762 [(set_attr "type" "jsr")
3763 (set_attr "length" "*,*,12")])
3766 [(set (match_operand 0 "register_operand" "")
3767 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
3768 (match_operand 2 "" "")))
3769 (use (match_operand:DI 3 "general_operand" "r,m"))
3772 (clobber (reg:DI 27))]
3775 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
3776 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
3777 [(set_attr "type" "jsr")
3778 (set_attr "length" "12,16")])
3780 ;; Call subroutine returning any type.
3782 (define_expand "untyped_call"
3783 [(parallel [(call (match_operand 0 "" "")
3785 (match_operand 1 "" "")
3786 (match_operand 2 "" "")])]
3792 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3794 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3796 rtx set = XVECEXP (operands[2], 0, i);
3797 emit_move_insn (SET_DEST (set), SET_SRC (set));
3800 /* The optimizer does not know that the call sets the function value
3801 registers we stored in the result block. We avoid problems by
3802 claiming that all hard registers are used and clobbered at this
3804 emit_insn (gen_blockage ());
3809 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3810 ;; all of memory. This blocks insns from being moved across this point.
3812 (define_insn "blockage"
3813 [(unspec_volatile [(const_int 0)] 1)]
3816 [(set_attr "length" "0")])
3820 (label_ref (match_operand 0 "" "")))]
3823 [(set_attr "type" "ibr")])
3825 (define_insn "return"
3829 [(set_attr "type" "ibr")])
3831 ;; Use a different pattern for functions which have non-trivial
3832 ;; epilogues so as not to confuse jump and reorg.
3833 (define_insn "return_internal"
3838 [(set_attr "type" "ibr")])
3840 (define_insn "indirect_jump"
3841 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3844 [(set_attr "type" "ibr")])
3846 (define_expand "tablejump"
3847 [(use (match_operand:SI 0 "register_operand" ""))
3848 (use (match_operand:SI 1 "" ""))]
3852 if (TARGET_WINDOWS_NT)
3853 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3854 else if (TARGET_OPEN_VMS)
3855 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3857 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3862 (define_expand "tablejump_osf"
3864 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3865 (parallel [(set (pc)
3866 (plus:DI (match_dup 3)
3867 (label_ref:DI (match_operand 1 "" ""))))
3868 (clobber (match_scratch:DI 2 "=r"))])]
3871 { operands[3] = gen_reg_rtx (DImode); }")
3873 (define_expand "tablejump_nt"
3875 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3876 (parallel [(set (pc)
3878 (use (label_ref (match_operand 1 "" "")))])]
3881 { operands[3] = gen_reg_rtx (DImode); }")
3884 ;; tablejump, openVMS way
3886 ;; op 1: label preceding jump-table
3888 (define_expand "tablejump_vms"
3890 (match_operand:DI 0 "register_operand" ""))
3892 (plus:DI (match_dup 2)
3893 (label_ref:DI (match_operand 1 "" ""))))]
3896 { operands[2] = gen_reg_rtx (DImode); }")
3900 (plus:DI (match_operand:DI 0 "register_operand" "r")
3901 (label_ref:DI (match_operand 1 "" ""))))
3902 (clobber (match_scratch:DI 2 "=r"))]
3903 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3904 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3905 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3907 { rtx best_label = 0;
3908 rtx jump_table_insn = next_active_insn (operands[1]);
3910 if (GET_CODE (jump_table_insn) == JUMP_INSN
3911 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3913 rtx jump_table = PATTERN (jump_table_insn);
3914 int n_labels = XVECLEN (jump_table, 1);
3915 int best_count = -1;
3918 for (i = 0; i < n_labels; i++)
3922 for (j = i + 1; j < n_labels; j++)
3923 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3924 == XEXP (XVECEXP (jump_table, 1, j), 0))
3927 if (count > best_count)
3928 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3934 operands[3] = best_label;
3935 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3938 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3940 [(set_attr "type" "ibr")
3941 (set_attr "length" "8")])
3945 (match_operand:DI 0 "register_operand" "r"))
3946 (use (label_ref (match_operand 1 "" "")))]
3947 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3948 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3949 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3951 { rtx best_label = 0;
3952 rtx jump_table_insn = next_active_insn (operands[1]);
3954 if (GET_CODE (jump_table_insn) == JUMP_INSN
3955 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3957 rtx jump_table = PATTERN (jump_table_insn);
3958 int n_labels = XVECLEN (jump_table, 1);
3959 int best_count = -1;
3962 for (i = 0; i < n_labels; i++)
3966 for (j = i + 1; j < n_labels; j++)
3967 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3968 == XEXP (XVECEXP (jump_table, 1, j), 0))
3971 if (count > best_count)
3972 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3978 operands[2] = best_label;
3979 return \"jmp $31,(%0),%2\";
3982 return \"jmp $31,(%0),0\";
3984 [(set_attr "type" "ibr")])
3987 ;; op 0 is table offset
3988 ;; op 1 is table label
3993 (plus:DI (match_operand 0 "register_operand" "r")
3994 (label_ref (match_operand 1 "" ""))))]
3997 [(set_attr "type" "ibr")])
3999 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4000 ;; want to have to include pal.h in our .s file.
4002 ;; Technically the type for call_pal is jsr, but we use that for determining
4003 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4006 [(unspec_volatile [(const_int 0)] 0)]
4009 [(set_attr "type" "ibr")])
4011 ;; Finally, we have the basic data motion insns. The byte and word insns
4012 ;; are done via define_expand. Start with the floating-point insns, since
4013 ;; they are simpler.
4016 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,m")
4017 (match_operand:SF 1 "input_operand" "rG,m,r,fG,m,fG"))]
4019 && (register_operand (operands[0], SFmode)
4020 || reg_or_fp0_operand (operands[1], SFmode))"
4028 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
4031 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,m,f,*r")
4032 (match_operand:SF 1 "input_operand" "rG,m,r,fG,m,fG,r,*f"))]
4034 && (register_operand (operands[0], SFmode)
4035 || reg_or_fp0_operand (operands[1], SFmode))"
4045 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,itof,ftoi")])
4048 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,m")
4049 (match_operand:DF 1 "input_operand" "rG,m,r,fG,m,fG"))]
4051 && (register_operand (operands[0], DFmode)
4052 || reg_or_fp0_operand (operands[1], DFmode))"
4060 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
4063 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,m,f,*r")
4064 (match_operand:DF 1 "input_operand" "rG,m,r,fG,m,fG,r,*f"))]
4066 && (register_operand (operands[0], DFmode)
4067 || reg_or_fp0_operand (operands[1], DFmode))"
4077 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,itof,ftoi")])
4079 (define_expand "movsf"
4080 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4081 (match_operand:SF 1 "general_operand" ""))]
4085 if (GET_CODE (operands[0]) == MEM
4086 && ! reg_or_fp0_operand (operands[1], SFmode))
4087 operands[1] = force_reg (SFmode, operands[1]);
4090 (define_expand "movdf"
4091 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4092 (match_operand:DF 1 "general_operand" ""))]
4096 if (GET_CODE (operands[0]) == MEM
4097 && ! reg_or_fp0_operand (operands[1], DFmode))
4098 operands[1] = force_reg (DFmode, operands[1]);
4102 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
4103 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
4104 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
4105 && (register_operand (operands[0], SImode)
4106 || reg_or_0_operand (operands[1], SImode))"
4116 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4119 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
4120 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
4121 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
4122 && (register_operand (operands[0], SImode)
4123 || reg_or_0_operand (operands[1], SImode))"
4135 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4138 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,m")
4139 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,m,f"))]
4140 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4141 && (register_operand (operands[0], SImode)
4142 || reg_or_0_operand (operands[1], SImode))"
4153 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4156 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,f")
4157 (match_operand:HI 1 "input_operand" "rJ,n,fJ"))]
4159 && (register_operand (operands[0], HImode)
4160 || register_operand (operands[1], HImode))"
4165 [(set_attr "type" "ilog,iadd,fcpys")])
4168 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,f")
4169 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
4171 && (register_operand (operands[0], HImode)
4172 || reg_or_0_operand (operands[1], HImode))"
4179 [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
4182 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,f")
4183 (match_operand:QI 1 "input_operand" "rJ,n,fJ"))]
4185 && (register_operand (operands[0], QImode)
4186 || register_operand (operands[1], QImode))"
4191 [(set_attr "type" "ilog,iadd,fcpys")])
4194 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,f")
4195 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
4197 && (register_operand (operands[0], QImode)
4198 || reg_or_0_operand (operands[1], QImode))"
4205 [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
4207 ;; We do two major things here: handle mem->mem and construct long
4210 (define_expand "movsi"
4211 [(set (match_operand:SI 0 "general_operand" "")
4212 (match_operand:SI 1 "general_operand" ""))]
4216 if (GET_CODE (operands[0]) == MEM
4217 && ! reg_or_0_operand (operands[1], SImode))
4218 operands[1] = force_reg (SImode, operands[1]);
4220 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4222 else if (GET_CODE (operands[1]) == CONST_INT)
4225 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4226 if (rtx_equal_p (operands[0], operands[1]))
4231 ;; Split a load of a large constant into the appropriate two-insn
4235 [(set (match_operand:SI 0 "register_operand" "")
4236 (match_operand:SI 1 "const_int_operand" ""))]
4237 "! add_operand (operands[1], SImode)"
4238 [(set (match_dup 0) (match_dup 2))
4239 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4242 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4244 if (tem == operands[0])
4251 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q")
4252 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
4254 && (register_operand (operands[0], DImode)
4255 || reg_or_0_operand (operands[1], DImode))"
4266 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4269 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
4270 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
4272 && (register_operand (operands[0], DImode)
4273 || reg_or_0_operand (operands[1], DImode))"
4286 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4288 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4289 ;; memory, and construct long 32-bit constants.
4291 (define_expand "movdi"
4292 [(set (match_operand:DI 0 "general_operand" "")
4293 (match_operand:DI 1 "general_operand" ""))]
4299 if (GET_CODE (operands[0]) == MEM
4300 && ! reg_or_0_operand (operands[1], DImode))
4301 operands[1] = force_reg (DImode, operands[1]);
4303 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4305 else if (GET_CODE (operands[1]) == CONST_INT
4306 && (tem = alpha_emit_set_const (operands[0], DImode,
4307 INTVAL (operands[1]), 3)) != 0)
4309 if (rtx_equal_p (tem, operands[0]))
4314 else if (CONSTANT_P (operands[1]))
4316 if (TARGET_BUILD_CONSTANTS)
4318 HOST_WIDE_INT i0, i1;
4320 if (GET_CODE (operands[1]) == CONST_INT)
4322 i0 = INTVAL (operands[1]);
4325 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4327 #if HOST_BITS_PER_WIDE_INT >= 64
4328 i0 = CONST_DOUBLE_LOW (operands[1]);
4331 i0 = CONST_DOUBLE_LOW (operands[1]);
4332 i1 = CONST_DOUBLE_HIGH (operands[1]);
4338 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4339 if (rtx_equal_p (tem, operands[0]))
4346 operands[1] = force_const_mem (DImode, operands[1]);
4347 if (reload_in_progress)
4349 emit_move_insn (operands[0], XEXP (operands[1], 0));
4350 operands[1] = copy_rtx (operands[1]);
4351 XEXP (operands[1], 0) = operands[0];
4354 operands[1] = validize_mem (operands[1]);
4361 ;; Split a load of a large constant into the appropriate two-insn
4365 [(set (match_operand:DI 0 "register_operand" "")
4366 (match_operand:DI 1 "const_int_operand" ""))]
4367 "! add_operand (operands[1], DImode)"
4368 [(set (match_dup 0) (match_dup 2))
4369 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4372 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4374 if (tem == operands[0])
4380 ;; These are the partial-word cases.
4382 ;; First we have the code to load an aligned word. Operand 0 is the register
4383 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4384 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4385 ;; number of bits within the word that the value is. Operand 3 is an SImode
4386 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4387 ;; same register. It is allowed to conflict with operand 1 as well.
4389 (define_expand "aligned_loadqi"
4390 [(set (match_operand:SI 3 "register_operand" "")
4391 (match_operand:SI 1 "memory_operand" ""))
4392 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4393 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4395 (match_operand:DI 2 "const_int_operand" "")))]
4400 (define_expand "aligned_loadhi"
4401 [(set (match_operand:SI 3 "register_operand" "")
4402 (match_operand:SI 1 "memory_operand" ""))
4403 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4404 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4406 (match_operand:DI 2 "const_int_operand" "")))]
4411 ;; Similar for unaligned loads, where we use the sequence from the
4412 ;; Alpha Architecture manual.
4414 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4415 ;; operand 3 can overlap the input and output registers.
4417 (define_expand "unaligned_loadqi"
4418 [(set (match_operand:DI 2 "register_operand" "")
4419 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4421 (set (match_operand:DI 3 "register_operand" "")
4423 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4424 (zero_extract:DI (match_dup 2)
4426 (ashift:DI (match_dup 3) (const_int 3))))]
4430 (define_expand "unaligned_loadhi"
4431 [(set (match_operand:DI 2 "register_operand" "")
4432 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4434 (set (match_operand:DI 3 "register_operand" "")
4436 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4437 (zero_extract:DI (match_dup 2)
4439 (ashift:DI (match_dup 3) (const_int 3))))]
4443 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4444 ;; aligned SImode MEM. Operand 1 is the register containing the
4445 ;; byte or word to store. Operand 2 is the number of bits within the word that
4446 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4448 (define_expand "aligned_store"
4449 [(set (match_operand:SI 3 "register_operand" "")
4450 (match_operand:SI 0 "memory_operand" ""))
4451 (set (subreg:DI (match_dup 3) 0)
4452 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4453 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4454 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4455 (match_operand:DI 2 "const_int_operand" "")))
4456 (set (subreg:DI (match_dup 4) 0)
4457 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4458 (set (match_dup 0) (match_dup 4))]
4461 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4462 << INTVAL (operands[2])));
4465 ;; For the unaligned byte and halfword cases, we use code similar to that
4466 ;; in the ;; Architecture book, but reordered to lower the number of registers
4467 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4468 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4469 ;; be the same temporary, if desired. If the address is in a register,
4470 ;; operand 2 can be that register.
4472 (define_expand "unaligned_storeqi"
4473 [(set (match_operand:DI 3 "register_operand" "")
4474 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4476 (set (match_operand:DI 2 "register_operand" "")
4479 (and:DI (not:DI (ashift:DI (const_int 255)
4480 (ashift:DI (match_dup 2) (const_int 3))))
4482 (set (match_operand:DI 4 "register_operand" "")
4483 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4484 (ashift:DI (match_dup 2) (const_int 3))))
4485 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4486 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4491 (define_expand "unaligned_storehi"
4492 [(set (match_operand:DI 3 "register_operand" "")
4493 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4495 (set (match_operand:DI 2 "register_operand" "")
4498 (and:DI (not:DI (ashift:DI (const_int 65535)
4499 (ashift:DI (match_dup 2) (const_int 3))))
4501 (set (match_operand:DI 4 "register_operand" "")
4502 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4503 (ashift:DI (match_dup 2) (const_int 3))))
4504 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4505 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4510 ;; Here are the define_expand's for QI and HI moves that use the above
4511 ;; patterns. We have the normal sets, plus the ones that need scratch
4512 ;; registers for reload.
4514 (define_expand "movqi"
4515 [(set (match_operand:QI 0 "general_operand" "")
4516 (match_operand:QI 1 "general_operand" ""))]
4522 if (GET_CODE (operands[0]) == MEM
4523 && ! reg_or_0_operand (operands[1], QImode))
4524 operands[1] = force_reg (QImode, operands[1]);
4526 if (GET_CODE (operands[1]) == CONST_INT
4527 && ! input_operand (operands[1], QImode))
4529 operands[1] = alpha_emit_set_const (operands[0], QImode,
4530 INTVAL (operands[1]), 3);
4532 if (rtx_equal_p (operands[0], operands[1]))
4539 /* If the output is not a register, the input must be. */
4540 if (GET_CODE (operands[0]) == MEM)
4541 operands[1] = force_reg (QImode, operands[1]);
4543 /* Handle four memory cases, unaligned and aligned for either the input
4544 or the output. The only case where we can be called during reload is
4545 for aligned loads; all other cases require temporaries. */
4547 if (GET_CODE (operands[1]) == MEM
4548 || (GET_CODE (operands[1]) == SUBREG
4549 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4550 || (reload_in_progress && GET_CODE (operands[1]) == REG
4551 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4552 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4553 && GET_CODE (SUBREG_REG (operands[1])) == REG
4554 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4556 if (aligned_memory_operand (operands[1], QImode))
4558 rtx aligned_mem, bitnum;
4559 rtx scratch = (reload_in_progress
4560 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4561 : gen_reg_rtx (SImode));
4563 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4565 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4570 /* Don't pass these as parameters since that makes the generated
4571 code depend on parameter evaluation order which will cause
4572 bootstrap failures. */
4574 rtx temp1 = gen_reg_rtx (DImode);
4575 rtx temp2 = gen_reg_rtx (DImode);
4577 = gen_unaligned_loadqi (operands[0],
4578 get_unaligned_address (operands[1], 0),
4581 alpha_set_memflags (seq, operands[1]);
4588 else if (GET_CODE (operands[0]) == MEM
4589 || (GET_CODE (operands[0]) == SUBREG
4590 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4591 || (reload_in_progress && GET_CODE (operands[0]) == REG
4592 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4593 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4594 && GET_CODE (SUBREG_REG (operands[0])) == REG
4595 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4597 if (aligned_memory_operand (operands[0], QImode))
4599 rtx aligned_mem, bitnum;
4600 rtx temp1 = gen_reg_rtx (SImode);
4601 rtx temp2 = gen_reg_rtx (SImode);
4603 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4605 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4610 rtx temp1 = gen_reg_rtx (DImode);
4611 rtx temp2 = gen_reg_rtx (DImode);
4612 rtx temp3 = gen_reg_rtx (DImode);
4614 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4615 operands[1], temp1, temp2, temp3);
4617 alpha_set_memflags (seq, operands[0]);
4625 (define_expand "movhi"
4626 [(set (match_operand:HI 0 "general_operand" "")
4627 (match_operand:HI 1 "general_operand" ""))]
4633 if (GET_CODE (operands[0]) == MEM
4634 && ! reg_or_0_operand (operands[1], HImode))
4635 operands[1] = force_reg (HImode, operands[1]);
4637 if (GET_CODE (operands[1]) == CONST_INT
4638 && ! input_operand (operands[1], HImode))
4640 operands[1] = alpha_emit_set_const (operands[0], HImode,
4641 INTVAL (operands[1]), 3);
4643 if (rtx_equal_p (operands[0], operands[1]))
4650 /* If the output is not a register, the input must be. */
4651 if (GET_CODE (operands[0]) == MEM)
4652 operands[1] = force_reg (HImode, operands[1]);
4654 /* Handle four memory cases, unaligned and aligned for either the input
4655 or the output. The only case where we can be called during reload is
4656 for aligned loads; all other cases require temporaries. */
4658 if (GET_CODE (operands[1]) == MEM
4659 || (GET_CODE (operands[1]) == SUBREG
4660 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4661 || (reload_in_progress && GET_CODE (operands[1]) == REG
4662 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4663 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4664 && GET_CODE (SUBREG_REG (operands[1])) == REG
4665 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4667 if (aligned_memory_operand (operands[1], HImode))
4669 rtx aligned_mem, bitnum;
4670 rtx scratch = (reload_in_progress
4671 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4672 : gen_reg_rtx (SImode));
4674 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4676 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4681 /* Don't pass these as parameters since that makes the generated
4682 code depend on parameter evaluation order which will cause
4683 bootstrap failures. */
4685 rtx temp1 = gen_reg_rtx (DImode);
4686 rtx temp2 = gen_reg_rtx (DImode);
4688 = gen_unaligned_loadhi (operands[0],
4689 get_unaligned_address (operands[1], 0),
4692 alpha_set_memflags (seq, operands[1]);
4699 else if (GET_CODE (operands[0]) == MEM
4700 || (GET_CODE (operands[0]) == SUBREG
4701 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4702 || (reload_in_progress && GET_CODE (operands[0]) == REG
4703 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4704 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4705 && GET_CODE (SUBREG_REG (operands[0])) == REG
4706 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4708 if (aligned_memory_operand (operands[0], HImode))
4710 rtx aligned_mem, bitnum;
4711 rtx temp1 = gen_reg_rtx (SImode);
4712 rtx temp2 = gen_reg_rtx (SImode);
4714 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4716 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4721 rtx temp1 = gen_reg_rtx (DImode);
4722 rtx temp2 = gen_reg_rtx (DImode);
4723 rtx temp3 = gen_reg_rtx (DImode);
4725 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4726 operands[1], temp1, temp2, temp3);
4728 alpha_set_memflags (seq, operands[0]);
4737 ;; Here are the versions for reload. Note that in the unaligned cases
4738 ;; we know that the operand must not be a pseudo-register because stack
4739 ;; slots are always aligned references.
4741 (define_expand "reload_inqi"
4742 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4743 (match_operand:QI 1 "any_memory_operand" "m")
4744 (match_operand:TI 2 "register_operand" "=&r")])]
4750 if (GET_CODE (operands[1]) != MEM)
4753 if (aligned_memory_operand (operands[1], QImode))
4755 rtx aligned_mem, bitnum;
4757 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4758 seq = gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4759 gen_rtx_REG (SImode, REGNO (operands[2])));
4765 /* It is possible that one of the registers we got for operands[2]
4766 might coincide with that of operands[0] (which is why we made
4767 it TImode). Pick the other one to use as our scratch. */
4768 if (REGNO (operands[0]) == REGNO (operands[2]))
4769 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4771 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4773 addr = get_unaligned_address (operands[1], 0);
4774 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4775 gen_rtx_REG (DImode, REGNO (operands[0])));
4776 alpha_set_memflags (seq, operands[1]);
4782 (define_expand "reload_inhi"
4783 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4784 (match_operand:HI 1 "any_memory_operand" "m")
4785 (match_operand:TI 2 "register_operand" "=&r")])]
4791 if (GET_CODE (operands[1]) != MEM)
4794 if (aligned_memory_operand (operands[1], HImode))
4796 rtx aligned_mem, bitnum;
4798 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4799 seq = gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4800 gen_rtx_REG (SImode, REGNO (operands[2])));
4806 /* It is possible that one of the registers we got for operands[2]
4807 might coincide with that of operands[0] (which is why we made
4808 it TImode). Pick the other one to use as our scratch. */
4809 if (REGNO (operands[0]) == REGNO (operands[2]))
4810 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4812 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4814 addr = get_unaligned_address (operands[1], 0);
4815 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4816 gen_rtx_REG (DImode, REGNO (operands[0])));
4817 alpha_set_memflags (seq, operands[1]);
4823 (define_expand "reload_outqi"
4824 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4825 (match_operand:QI 1 "register_operand" "r")
4826 (match_operand:TI 2 "register_operand" "=&r")])]
4830 if (GET_CODE (operands[0]) != MEM)
4833 if (aligned_memory_operand (operands[0], QImode))
4835 rtx aligned_mem, bitnum;
4837 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4839 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4840 gen_rtx_REG (SImode, REGNO (operands[2])),
4841 gen_rtx_REG (SImode,
4842 REGNO (operands[2]) + 1)));
4846 rtx addr = get_unaligned_address (operands[0], 0);
4847 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4848 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4849 rtx scratch3 = scratch1;
4852 if (GET_CODE (addr) == REG)
4855 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4856 scratch2, scratch3);
4857 alpha_set_memflags (seq, operands[0]);
4863 (define_expand "reload_outhi"
4864 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4865 (match_operand:HI 1 "register_operand" "r")
4866 (match_operand:TI 2 "register_operand" "=&r")])]
4870 if (GET_CODE (operands[0]) != MEM)
4873 if (aligned_memory_operand (operands[0], HImode))
4875 rtx aligned_mem, bitnum;
4877 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4879 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4880 gen_rtx_REG (SImode, REGNO (operands[2])),
4881 gen_rtx_REG (SImode,
4882 REGNO (operands[2]) + 1)));
4886 rtx addr = get_unaligned_address (operands[0], 0);
4887 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4888 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4889 rtx scratch3 = scratch1;
4892 if (GET_CODE (addr) == REG)
4895 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4896 scratch2, scratch3);
4897 alpha_set_memflags (seq, operands[0]);
4903 ;; Bit field extract patterns which use ext[wlq][lh]
4905 (define_expand "extv"
4906 [(set (match_operand:DI 0 "register_operand" "")
4907 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
4908 (match_operand:DI 2 "immediate_operand" "")
4909 (match_operand:DI 3 "immediate_operand" "")))]
4913 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4914 if (INTVAL (operands[3]) % 8 != 0
4915 || (INTVAL (operands[2]) != 16
4916 && INTVAL (operands[2]) != 32
4917 && INTVAL (operands[2]) != 64))
4920 /* From mips.md: extract_bit_field doesn't verify that our source
4921 matches the predicate, so we force it to be a MEM here. */
4922 if (GET_CODE (operands[1]) != MEM)
4925 alpha_expand_unaligned_load (operands[0], operands[1],
4926 INTVAL (operands[2]) / 8,
4927 INTVAL (operands[3]) / 8, 1);
4931 (define_expand "extzv"
4932 [(set (match_operand:DI 0 "register_operand" "")
4933 (zero_extract:DI (match_operand:DI 1 "general_operand" "")
4934 (match_operand:DI 2 "immediate_operand" "")
4935 (match_operand:DI 3 "immediate_operand" "")))]
4939 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4940 if (INTVAL (operands[3]) % 8 != 0
4941 || (INTVAL (operands[2]) != 8
4942 && INTVAL (operands[2]) != 16
4943 && INTVAL (operands[2]) != 32
4944 && INTVAL (operands[2]) != 64))
4947 if (GET_CODE (operands[1]) == MEM)
4949 /* Fail 8 bit fields, falling back on a simple byte load. */
4950 if (INTVAL (operands[2]) == 8)
4953 alpha_expand_unaligned_load (operands[0], operands[1],
4954 INTVAL (operands[2]) / 8,
4955 INTVAL (operands[3]) / 8, 0);
4960 (define_expand "insv"
4961 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
4962 (match_operand:DI 1 "immediate_operand" "")
4963 (match_operand:DI 2 "immediate_operand" ""))
4964 (match_operand:DI 3 "register_operand" ""))]
4968 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4969 if (INTVAL (operands[2]) % 8 != 0
4970 || (INTVAL (operands[1]) != 16
4971 && INTVAL (operands[1]) != 32
4972 && INTVAL (operands[1]) != 64))
4975 /* From mips.md: store_bit_field doesn't verify that our source
4976 matches the predicate, so we force it to be a MEM here. */
4977 if (GET_CODE (operands[0]) != MEM)
4980 alpha_expand_unaligned_store (operands[0], operands[3],
4981 INTVAL (operands[1]) / 8,
4982 INTVAL (operands[2]) / 8);
4988 ;; Block move/clear, see alpha.c for more details.
4989 ;; Argument 0 is the destination
4990 ;; Argument 1 is the source
4991 ;; Argument 2 is the length
4992 ;; Argument 3 is the alignment
4994 (define_expand "movstrqi"
4995 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4996 (match_operand:BLK 1 "general_operand" ""))
4997 (use (match_operand:DI 2 "immediate_operand" ""))
4998 (use (match_operand:DI 3 "immediate_operand" ""))])]
5002 if (alpha_expand_block_move (operands))
5008 (define_expand "clrstrqi"
5009 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
5011 (use (match_operand:DI 1 "immediate_operand" ""))
5012 (use (match_operand:DI 2 "immediate_operand" ""))])]
5016 if (alpha_expand_block_clear (operands))
5022 ;; Subroutine of stack space allocation. Perform a stack probe.
5023 (define_expand "probe_stack"
5024 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5028 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5029 INTVAL (operands[0])));
5030 MEM_VOLATILE_P (operands[1]) = 1;
5032 operands[0] = const0_rtx;
5035 ;; This is how we allocate stack space. If we are allocating a
5036 ;; constant amount of space and we know it is less than 4096
5037 ;; bytes, we need do nothing.
5039 ;; If it is more than 4096 bytes, we need to probe the stack
5041 (define_expand "allocate_stack"
5043 (plus:DI (reg:DI 30)
5044 (match_operand:DI 1 "reg_or_cint_operand" "")))
5045 (set (match_operand:DI 0 "register_operand" "=r")
5050 if (GET_CODE (operands[1]) == CONST_INT
5051 && INTVAL (operands[1]) < 32768)
5053 if (INTVAL (operands[1]) >= 4096)
5055 /* We do this the same way as in the prologue and generate explicit
5056 probes. Then we update the stack by the constant. */
5060 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5061 while (probed + 8192 < INTVAL (operands[1]))
5062 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5064 if (probed + 4096 < INTVAL (operands[1]))
5065 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5068 operands[1] = GEN_INT (- INTVAL (operands[1]));
5069 operands[2] = virtual_stack_dynamic_rtx;
5074 rtx loop_label = gen_label_rtx ();
5075 rtx want = gen_reg_rtx (Pmode);
5076 rtx tmp = gen_reg_rtx (Pmode);
5079 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5080 force_reg (Pmode, operands[1])));
5081 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5083 if (GET_CODE (operands[1]) != CONST_INT)
5085 out_label = gen_label_rtx ();
5086 emit_insn (gen_cmpdi (want, tmp));
5087 emit_jump_insn (gen_bgeu (out_label));
5090 emit_label (loop_label);
5091 memref = gen_rtx_MEM (DImode, tmp);
5092 MEM_VOLATILE_P (memref) = 1;
5093 emit_move_insn (memref, const0_rtx);
5094 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5095 emit_insn (gen_cmpdi (tmp, want));
5096 emit_jump_insn (gen_bgtu (loop_label));
5098 gen_rtx_USE (VOIDmode, tmp);
5100 memref = gen_rtx_MEM (DImode, want);
5101 MEM_VOLATILE_P (memref) = 1;
5102 emit_move_insn (memref, const0_rtx);
5105 emit_label (out_label);
5107 emit_move_insn (stack_pointer_rtx, want);
5108 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5113 ;; This is used by alpha_expand_prolog to do the same thing as above,
5114 ;; except we cannot at that time generate new basic blocks, so we hide
5115 ;; the loop in this one insn.
5117 (define_insn "prologue_stack_probe_loop"
5118 [(unspec_volatile [(match_operand 0 "register_operand" "r")
5119 (match_operand 1 "register_operand" "r")] 5)]
5123 operands[2] = gen_label_rtx ();
5124 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5125 CODE_LABEL_NUMBER (operands[2]));
5127 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5129 [(set_attr "length" "16")
5130 (set_attr "type" "multi")])
5132 (define_expand "prologue"
5133 [(clobber (const_int 0))]
5135 "alpha_expand_prologue (); DONE;")
5137 (define_insn "init_fp"
5138 [(set (match_operand:DI 0 "register_operand" "r")
5139 (match_operand:DI 1 "register_operand" "r"))
5140 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
5144 (define_expand "epilogue"
5145 [(clobber (const_int 0))]
5147 "alpha_expand_epilogue (); DONE;")
5149 (define_expand "eh_epilogue"
5150 [(use (match_operand:DI 0 "register_operand" "r"))
5151 (use (match_operand:DI 1 "register_operand" "r"))
5152 (use (match_operand:DI 2 "register_operand" "r"))]
5156 alpha_eh_epilogue_sp_ofs = operands[1];
5157 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5159 rtx ra = gen_rtx_REG (Pmode, 26);
5160 emit_move_insn (ra, operands[2]);
5165 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5166 ;; the frame size into a register. We use this pattern to ensure
5167 ;; we get lda instead of addq.
5168 (define_insn "nt_lda"
5169 [(set (match_operand:DI 0 "register_operand" "r")
5170 (unspec:DI [(match_dup 0)
5171 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5175 (define_expand "builtin_longjmp"
5176 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5177 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5180 /* The elements of the buffer are, in order: */
5181 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5182 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5183 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5184 rtx pv = gen_rtx_REG (Pmode, 27);
5186 /* This bit is the same as expand_builtin_longjmp. */
5187 emit_move_insn (hard_frame_pointer_rtx, fp);
5188 emit_move_insn (pv, lab);
5189 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5190 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5191 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5193 /* Load the label we are jumping through into $27 so that we know
5194 where to look for it when we get back to setjmp's function for
5195 restoring the gp. */
5196 emit_indirect_jump (pv);
5200 (define_insn "builtin_setjmp_receiver"
5201 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5202 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5203 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5204 [(set_attr "length" "8")
5205 (set_attr "type" "multi")])
5208 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5209 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5210 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5211 [(set_attr "length" "12")
5212 (set_attr "type" "multi")])
5214 (define_insn "exception_receiver"
5215 [(unspec_volatile [(const_int 0)] 7)]
5216 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5217 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5218 [(set_attr "length" "12")
5219 (set_attr "type" "multi")])
5221 (define_expand "nonlocal_goto_receiver"
5222 [(unspec_volatile [(const_int 0)] 1)
5223 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5224 (unspec_volatile [(const_int 0)] 1)
5229 (define_insn "arg_home"
5230 [(unspec [(const_int 0)] 0)
5245 (clobber (mem:BLK (const_int 0)))
5246 (clobber (reg:DI 24))
5247 (clobber (reg:DI 25))
5248 (clobber (reg:DI 0))]
5250 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5251 [(set_attr "length" "16")
5252 (set_attr "type" "multi")])
5254 ;; Close the trap shadow of preceeding instructions. This is generated
5257 (define_insn "trapb"
5258 [(unspec_volatile [(const_int 0)] 4)]
5261 [(set_attr "type" "misc")])
5263 ;; No-op instructions used by machine-dependant reorg to preserve
5264 ;; alignment for instruction issue.
5270 [(set_attr "type" "ilog")])
5276 [(set_attr "type" "fcpys")])
5283 (define_insn "realign"
5284 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5286 ".align %0 #realign")
5288 ;; Peepholes go at the end.
5290 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5291 ;; reload when converting fp->int.
5293 ;; ??? What to do now that we actually care about the packing and
5294 ;; alignment of instructions? Perhaps reload can be enlightened, or
5295 ;; the peephole pass moved up after reload but before sched2?
5298 ; [(set (match_operand:SI 0 "register_operand" "=r")
5299 ; (match_operand:SI 1 "memory_operand" "m"))
5300 ; (set (match_operand:DI 2 "register_operand" "=r")
5301 ; (sign_extend:DI (match_dup 0)))]
5302 ; "dead_or_set_p (insn, operands[0])"
5306 ; [(set (match_operand:SI 0 "register_operand" "=r")
5307 ; (match_operand:SI 1 "hard_fp_register_operand" "f"))
5308 ; (set (match_operand:DI 2 "register_operand" "=r")
5309 ; (sign_extend:DI (match_dup 0)))]
5310 ; "TARGET_CIX && dead_or_set_p (insn, operands[0])"