1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
26 %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \
27 %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
28 %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
29 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
30 %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
31 %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \
33 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT}"
35 /* Set the spec to use for signed char. The default tests the above macro
36 but DEC's compiler can't handle the conditional in a "constant"
39 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
41 #define WORD_SWITCH_TAKES_ARG(STR) \
42 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
43 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
44 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
45 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
46 || !strcmp (STR, "isystem"))
48 /* Print subsidiary information on the compiler version in use. */
49 #define TARGET_VERSION
51 /* Run-time compilation parameters selecting different hardware subsets. */
53 /* Which processor to schedule for. The cpu attribute defines a list that
54 mirrors this list, so changes to alpha.md must be made at the same time. */
57 {PROCESSOR_EV4, /* 2106[46]{a,} */
58 PROCESSOR_EV5, /* 21164{a,pc,} */
59 PROCESSOR_EV6}; /* 21264 */
61 extern enum processor_type alpha_cpu;
63 enum alpha_trap_precision
65 ALPHA_TP_PROG, /* No precision (default). */
66 ALPHA_TP_FUNC, /* Trap contained within originating function. */
67 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
70 enum alpha_fp_rounding_mode
72 ALPHA_FPRM_NORM, /* Normal rounding mode. */
73 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
74 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
75 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
78 enum alpha_fp_trap_mode
80 ALPHA_FPTM_N, /* Normal trap mode. */
81 ALPHA_FPTM_U, /* Underflow traps enabled. */
82 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
83 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
86 extern int target_flags;
88 extern enum alpha_trap_precision alpha_tp;
89 extern enum alpha_fp_rounding_mode alpha_fprm;
90 extern enum alpha_fp_trap_mode alpha_fptm;
92 /* This means that floating-point support exists in the target implementation
93 of the Alpha architecture. This is usually the default. */
96 #define TARGET_FP (target_flags & MASK_FP)
98 /* This means that floating-point registers are allowed to be used. Note
99 that Alpha implementations without FP operations are required to
100 provide the FP registers. */
102 #define MASK_FPREGS 2
103 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
105 /* This means that gas is used to process the assembler file. */
108 #define TARGET_GAS (target_flags & MASK_GAS)
110 /* This means that we should mark procedures as IEEE conformant. */
112 #define MASK_IEEE_CONFORMANT 8
113 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
115 /* This means we should be IEEE-compliant except for inexact. */
118 #define TARGET_IEEE (target_flags & MASK_IEEE)
120 /* This means we should be fully IEEE-compliant. */
122 #define MASK_IEEE_WITH_INEXACT 32
123 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
125 /* This means we must construct all constants rather than emitting
126 them as literal data. */
128 #define MASK_BUILD_CONSTANTS 128
129 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
131 /* This means we handle floating points in VAX F- (float)
132 or G- (double) Format. */
134 #define MASK_FLOAT_VAX 512
135 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
137 /* This means that the processor has byte and half word loads and stores
138 (the BWX extension). */
140 #define MASK_BWX 1024
141 #define TARGET_BWX (target_flags & MASK_BWX)
143 /* This means that the processor has the CIX extension. */
144 #define MASK_CIX 2048
145 #define TARGET_CIX (target_flags & MASK_CIX)
147 /* This means that the processor has the MAX extension. */
148 #define MASK_MAX 4096
149 #define TARGET_MAX (target_flags & MASK_MAX)
151 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
152 only in TARGET_CPU_DEFAULT. */
153 #define MASK_CPU_EV5 8192
155 /* Likewise for EV6. */
156 #define MASK_CPU_EV6 16384
158 /* This means we support the .arch directive in the assembler. Only
159 defined in TARGET_CPU_DEFAULT. */
160 #define MASK_SUPPORT_ARCH 32768
161 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
163 /* These are for target os support and cannot be changed at runtime. */
164 #ifndef TARGET_WINDOWS_NT
165 #define TARGET_WINDOWS_NT 0
167 #ifndef TARGET_OPEN_VMS
168 #define TARGET_OPEN_VMS 0
171 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
172 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
174 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
175 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
178 /* Macro to define tables used to set the flags.
179 This is a list in braces of pairs in braces,
180 each pair being { "NAME", VALUE }
181 where VALUE is the bits to set or minus the bits to clear.
182 An empty string NAME is used to identify the default VALUE. */
184 #define TARGET_SWITCHES \
185 { {"no-soft-float", MASK_FP}, \
186 {"soft-float", - MASK_FP}, \
187 {"fp-regs", MASK_FPREGS}, \
188 {"no-fp-regs", - (MASK_FP|MASK_FPREGS)}, \
189 {"alpha-as", -MASK_GAS}, \
191 {"ieee-conformant", MASK_IEEE_CONFORMANT}, \
192 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT}, \
193 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
194 {"build-constants", MASK_BUILD_CONSTANTS}, \
195 {"float-vax", MASK_FLOAT_VAX}, \
196 {"float-ieee", -MASK_FLOAT_VAX}, \
198 {"no-bwx", -MASK_BWX}, \
200 {"no-cix", -MASK_CIX}, \
202 {"no-max", -MASK_MAX}, \
203 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
205 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
207 #ifndef TARGET_CPU_DEFAULT
208 #define TARGET_CPU_DEFAULT 0
211 /* This macro is similar to `TARGET_SWITCHES' but defines names of
212 command options that have values. Its definition is an initializer
213 with a subgrouping for each command option.
215 Each subgrouping contains a string constant, that defines the fixed
216 part of the option name, and the address of a variable. The
217 variable, type `char *', is set to the variable part of the given
218 option if the fixed part matches. The actual option name is made
219 by appending `-m' to the specified name.
221 Here is an example which defines `-mshort-data-NUMBER'. If the
222 given option is `-mshort-data-512', the variable `m88k_short_data'
223 will be set to the string `"512"'.
225 extern char *m88k_short_data;
226 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
228 extern char *alpha_cpu_string; /* For -mcpu= */
229 extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
230 extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
231 extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
232 extern char *alpha_mlat_string; /* For -mmemory-latency= */
234 #define TARGET_OPTIONS \
236 {"cpu=", &alpha_cpu_string}, \
237 {"fp-rounding-mode=", &alpha_fprm_string}, \
238 {"fp-trap-mode=", &alpha_fptm_string}, \
239 {"trap-precision=", &alpha_tp_string}, \
240 {"memory-latency=", &alpha_mlat_string}, \
243 /* Sometimes certain combinations of command options do not make sense
244 on a particular target machine. You can define a macro
245 `OVERRIDE_OPTIONS' to take account of this. This macro, if
246 defined, is executed once just after all the command options have
249 On the Alpha, it is used to translate target-option strings into
252 extern void override_options ();
253 #define OVERRIDE_OPTIONS override_options ()
256 /* Define this macro to change register usage conditional on target flags.
258 On the Alpha, we use this to disable the floating-point registers when
261 #define CONDITIONAL_REGISTER_USAGE \
262 if (! TARGET_FPREGS) \
263 for (i = 32; i < 63; i++) \
264 fixed_regs[i] = call_used_regs[i] = 1;
266 /* Show we can debug even without a frame pointer. */
267 #define CAN_DEBUG_WITHOUT_FP
269 /* target machine storage layout */
271 /* Define to enable software floating point emulation. */
272 #define REAL_ARITHMETIC
274 /* The following #defines are used when compiling the routines in
275 libgcc1.c. Since the Alpha calling conventions require single
276 precision floats to be passed in the floating-point registers
277 (rather than in the general registers) we have to build the
278 libgcc1.c routines in such a way that they know the actual types
279 of their formal arguments and the actual types of their return
280 values. Otherwise, gcc will generate calls to the libgcc1.c
281 routines, passing arguments in the floating-point registers,
282 but the libgcc1.c routines will expect their arguments on the
283 stack (where the Alpha calling conventions require structs &
284 unions to be passed). */
286 #define FLOAT_VALUE_TYPE double
287 #define INTIFY(FLOATVAL) (FLOATVAL)
288 #define FLOATIFY(INTVAL) (INTVAL)
289 #define FLOAT_ARG_TYPE double
291 /* Define the size of `int'. The default is the same as the word size. */
292 #define INT_TYPE_SIZE 32
294 /* Define the size of `long long'. The default is the twice the word size. */
295 #define LONG_LONG_TYPE_SIZE 64
297 /* The two floating-point formats we support are S-floating, which is
298 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
299 and `long double' are T. */
301 #define FLOAT_TYPE_SIZE 32
302 #define DOUBLE_TYPE_SIZE 64
303 #define LONG_DOUBLE_TYPE_SIZE 64
305 #define WCHAR_TYPE "unsigned int"
306 #define WCHAR_TYPE_SIZE 32
308 /* Define this macro if it is advisable to hold scalars in registers
309 in a wider mode than that declared by the program. In such cases,
310 the value is constrained to be within the bounds of the declared
311 type, but kept valid in the wider mode. The signedness of the
312 extension may differ from that of the type.
314 For Alpha, we always store objects in a full register. 32-bit objects
315 are always sign-extended, but smaller objects retain their signedness. */
317 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
318 if (GET_MODE_CLASS (MODE) == MODE_INT \
319 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
321 if ((MODE) == SImode) \
326 /* Define this if function arguments should also be promoted using the above
329 #define PROMOTE_FUNCTION_ARGS
331 /* Likewise, if the function return value is promoted. */
333 #define PROMOTE_FUNCTION_RETURN
335 /* Define this if most significant bit is lowest numbered
336 in instructions that operate on numbered bit-fields.
338 There are no such instructions on the Alpha, but the documentation
340 #define BITS_BIG_ENDIAN 0
342 /* Define this if most significant byte of a word is the lowest numbered.
343 This is false on the Alpha. */
344 #define BYTES_BIG_ENDIAN 0
346 /* Define this if most significant word of a multiword number is lowest
349 For Alpha we can decide arbitrarily since there are no machine instructions
350 for them. Might as well be consistent with bytes. */
351 #define WORDS_BIG_ENDIAN 0
353 /* number of bits in an addressable storage unit */
354 #define BITS_PER_UNIT 8
356 /* Width in bits of a "word", which is the contents of a machine register.
357 Note that this is not necessarily the width of data type `int';
358 if using 16-bit ints on a 68000, this would still be 32.
359 But on a machine with 16-bit registers, this would be 16. */
360 #define BITS_PER_WORD 64
362 /* Width of a word, in units (bytes). */
363 #define UNITS_PER_WORD 8
365 /* Width in bits of a pointer.
366 See also the macro `Pmode' defined below. */
367 #define POINTER_SIZE 64
369 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
370 #define PARM_BOUNDARY 64
372 /* Boundary (in *bits*) on which stack pointer should be aligned. */
373 #define STACK_BOUNDARY 64
375 /* Allocation boundary (in *bits*) for the code of a function. */
376 #define FUNCTION_BOUNDARY 256
378 /* Alignment of field after `int : 0' in a structure. */
379 #define EMPTY_FIELD_BOUNDARY 64
381 /* Every structure's size must be a multiple of this. */
382 #define STRUCTURE_SIZE_BOUNDARY 8
384 /* A bitfield declared as `int' forces `int' alignment for the struct. */
385 #define PCC_BITFIELD_TYPE_MATTERS 1
387 /* Align loop starts for optimal branching.
389 ??? Kludge this and the next macro for the moment by not doing anything if
390 we don't optimize and also if we are writing ECOFF symbols to work around
391 a bug in DEC's assembler. */
393 #define LOOP_ALIGN(LABEL) \
394 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
396 /* This is how to align an instruction for optimal branching. On
397 Alpha we'll get better performance by aligning on an octaword
400 #define ALIGN_LABEL_AFTER_BARRIER(FILE) \
401 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
403 /* No data type wants to be aligned rounder than this. */
404 #define BIGGEST_ALIGNMENT 64
406 /* For atomic access to objects, must have at least 32-bit alignment
407 unless the machine has byte operations. */
408 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
410 /* Align all constants and variables to at least a word boundary so
411 we can pick up pieces of them faster. */
412 /* ??? Only if block-move stuff knows about different source/destination
415 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
416 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
419 /* Set this non-zero if move instructions will actually fail to work
420 when given unaligned data.
422 Since we get an error message when we do one, call them invalid. */
424 #define STRICT_ALIGNMENT 1
426 /* Set this non-zero if unaligned move instructions are extremely slow.
428 On the Alpha, they trap. */
430 #define SLOW_UNALIGNED_ACCESS 1
432 /* Standard register usage. */
434 /* Number of actual hardware registers.
435 The hardware registers are assigned numbers for the compiler
436 from 0 to just below FIRST_PSEUDO_REGISTER.
437 All registers that the compiler knows about must be given numbers,
438 even those that are not normally considered general registers.
440 We define all 32 integer registers, even though $31 is always zero,
441 and all 32 floating-point registers, even though $f31 is also
442 always zero. We do not bother defining the FP status register and
443 there are no other registers.
445 Since $31 is always zero, we will use register number 31 as the
446 argument pointer. It will never appear in the generated code
447 because we will always be eliminating it in favor of the stack
448 pointer or hardware frame pointer.
450 Likewise, we use $f31 for the frame pointer, which will always
451 be eliminated in favor of the hardware frame pointer or the
454 #define FIRST_PSEUDO_REGISTER 64
456 /* 1 for registers that have pervasive standard uses
457 and are not available for the register allocator. */
459 #define FIXED_REGISTERS \
460 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
465 /* 1 for registers not available across function calls.
466 These must include the FIXED_REGISTERS and also any
467 registers that can be used without being saved.
468 The latter must include the registers where values are returned
469 and the register where structure-value addresses are passed.
470 Aside from that, you can include as many other registers as you like. */
471 #define CALL_USED_REGISTERS \
472 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
474 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
475 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
477 /* List the order in which to allocate registers. Each register must be
478 listed once, even those in FIXED_REGISTERS.
480 We allocate in the following order:
481 $f10-$f15 (nonsaved floating-point register)
483 $f21-$f16 (likewise, but input args)
484 $f0 (nonsaved, but return value)
485 $f1 (nonsaved, but immediate before saved)
486 $f2-$f9 (saved floating-point registers)
487 $1-$8 (nonsaved integer registers)
490 $0 (likewise, but return value)
491 $21-$16 (likewise, but input args)
492 $27 (procedure value in OSF, nonsaved in NT)
493 $9-$14 (saved integer registers)
497 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
499 #define REG_ALLOC_ORDER \
500 {42, 43, 44, 45, 46, 47, \
501 54, 55, 56, 57, 58, 59, 60, 61, 62, \
502 53, 52, 51, 50, 49, 48, \
504 34, 35, 36, 37, 38, 39, 40, 41, \
505 1, 2, 3, 4, 5, 6, 7, 8, \
509 21, 20, 19, 18, 17, 16, \
511 9, 10, 11, 12, 13, 14, \
517 /* Return number of consecutive hard regs needed starting at reg REGNO
518 to hold something of mode MODE.
519 This is ordinarily the length in words of a value of mode MODE
520 but can be less for certain modes in special long registers. */
522 #define HARD_REGNO_NREGS(REGNO, MODE) \
523 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
525 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
526 On Alpha, the integer registers can hold any mode. The floating-point
527 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
528 or 8-bit values. If we only allowed the larger integers into FP registers,
529 we'd have to say that QImode and SImode aren't tiable, which is a
530 pain. So say all registers can hold everything and see how that works. */
532 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
534 /* Value is 1 if it is a good idea to tie two pseudo registers
535 when one has mode MODE1 and one has mode MODE2.
536 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
537 for any hard reg, then this must be 0 for correct output. */
539 #define MODES_TIEABLE_P(MODE1, MODE2) 1
541 /* Specify the registers used for certain standard purposes.
542 The values of these macros are register numbers. */
544 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
545 /* #define PC_REGNUM */
547 /* Register to use for pushing function arguments. */
548 #define STACK_POINTER_REGNUM 30
550 /* Base register for access to local variables of the function. */
551 #define HARD_FRAME_POINTER_REGNUM 15
553 /* Value should be nonzero if functions must have frame pointers.
554 Zero means the frame pointer need not be set up (and parms
555 may be accessed via the stack pointer) in functions that seem suitable.
556 This is computed in `reload', in reload1.c. */
557 #define FRAME_POINTER_REQUIRED 0
559 /* Base register for access to arguments of the function. */
560 #define ARG_POINTER_REGNUM 31
562 /* Base register for access to local variables of function. */
563 #define FRAME_POINTER_REGNUM 63
565 /* Register in which static-chain is passed to a function.
567 For the Alpha, this is based on an example; the calling sequence
568 doesn't seem to specify this. */
569 #define STATIC_CHAIN_REGNUM 1
571 /* Register in which address to store a structure value
572 arrives in the function. On the Alpha, the address is passed
573 as a hidden argument. */
574 #define STRUCT_VALUE 0
576 /* Define the classes of registers for register constraints in the
577 machine description. Also define ranges of constants.
579 One of the classes must always be named ALL_REGS and include all hard regs.
580 If there is more than one class, another class must be named NO_REGS
581 and contain no registers.
583 The name GENERAL_REGS must be the name of a class (or an alias for
584 another name such as ALL_REGS). This is the class of registers
585 that is allowed by "g" or "r" in a register constraint.
586 Also, registers outside this class are allocated only when
587 instructions express preferences for them.
589 The classes must be numbered in nondecreasing order; that is,
590 a larger-numbered class must never be contained completely
591 in a smaller-numbered class.
593 For any two classes, it is very desirable that there be another
594 class that represents their union. */
596 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
599 #define N_REG_CLASSES (int) LIM_REG_CLASSES
601 /* Give names of register classes as strings for dump file. */
603 #define REG_CLASS_NAMES \
604 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
606 /* Define which registers fit in which classes.
607 This is an initializer for a vector of HARD_REG_SET
608 of length N_REG_CLASSES. */
610 #define REG_CLASS_CONTENTS \
611 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
613 /* The same information, inverted:
614 Return the class number of the smallest class containing
615 reg number REGNO. This could be a conditional expression
616 or could index an array. */
618 #define REGNO_REG_CLASS(REGNO) \
619 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
621 /* The class value for index registers, and the one for base regs. */
622 #define INDEX_REG_CLASS NO_REGS
623 #define BASE_REG_CLASS GENERAL_REGS
625 /* Get reg_class from a letter such as appears in the machine description. */
627 #define REG_CLASS_FROM_LETTER(C) \
628 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
630 /* Define this macro to change register usage conditional on target flags. */
631 /* #define CONDITIONAL_REGISTER_USAGE */
633 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
634 can be used to stand for particular ranges of immediate operands.
635 This macro defines what the ranges are.
636 C is the letter, and VALUE is a constant value.
637 Return 1 if VALUE is in the range specified by C.
640 `I' is used for the range of constants most insns can contain.
641 `J' is the constant zero.
642 `K' is used for the constant in an LDA insn.
643 `L' is used for the constant in a LDAH insn.
644 `M' is used for the constants that can be AND'ed with using a ZAP insn.
645 `N' is used for complemented 8-bit constants.
646 `O' is used for negated 8-bit constants.
647 `P' is used for the constants 1, 2 and 3. */
649 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
650 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
651 : (C) == 'J' ? (VALUE) == 0 \
652 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
653 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
654 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
655 : (C) == 'M' ? zap_mask (VALUE) \
656 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
657 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
658 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
661 /* Similar, but for floating or large integer constants, and defining letters
662 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
664 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
665 that is the operand of a ZAP insn. */
667 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
668 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
669 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
670 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
671 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
672 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
675 /* Optional extra constraints for this machine.
677 For the Alpha, `Q' means that this is a memory operand but not a
678 reference to an unaligned location.
679 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
682 #define EXTRA_CONSTRAINT(OP, C) \
683 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
684 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
687 /* Given an rtx X being reloaded into a reg required to be
688 in class CLASS, return the class of reg to actually use.
689 In general this is just CLASS; but on some machines
690 in some cases it is preferable to use a more restrictive class.
692 On the Alpha, all constants except zero go into a floating-point
693 register via memory. */
695 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
696 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
697 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
700 /* Loading and storing HImode or QImode values to and from memory
701 usually requires a scratch register. The exceptions are loading
702 QImode and HImode from an aligned address to a general register
703 unless byte instructions are permitted.
704 We also cannot load an unaligned address or a paradoxical SUBREG into an
707 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
708 (((GET_CODE (IN) == MEM \
709 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
710 || (GET_CODE (IN) == SUBREG \
711 && (GET_CODE (SUBREG_REG (IN)) == MEM \
712 || (GET_CODE (SUBREG_REG (IN)) == REG \
713 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
714 && (((CLASS) == FLOAT_REGS \
715 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
716 || (((MODE) == QImode || (MODE) == HImode) \
717 && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
719 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
720 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
721 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
722 && (GET_MODE_SIZE (GET_MODE (IN)) \
723 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
726 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
727 (((GET_CODE (OUT) == MEM \
728 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
729 || (GET_CODE (OUT) == SUBREG \
730 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
731 || (GET_CODE (SUBREG_REG (OUT)) == REG \
732 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
733 && ((((MODE) == HImode || (MODE) == QImode) \
734 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
735 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
737 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
738 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
739 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
740 && (GET_MODE_SIZE (GET_MODE (OUT)) \
741 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
744 /* If we are copying between general and FP registers, we need a memory
745 location unless the CIX extension is available. */
747 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
748 (! TARGET_CIX && (CLASS1) != (CLASS2))
750 /* Specify the mode to be used for memory when a secondary memory
751 location is needed. If MODE is floating-point, use it. Otherwise,
752 widen to a word like the default. This is needed because we always
753 store integers in FP registers in quadword format. This whole
754 area is very tricky! */
755 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
756 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
757 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
758 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
760 /* Return the maximum number of consecutive registers
761 needed to represent mode MODE in a register of class CLASS. */
763 #define CLASS_MAX_NREGS(CLASS, MODE) \
764 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
766 /* If defined, gives a class of registers that cannot be used as the
767 operand of a SUBREG that changes the size of the object. */
769 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
771 /* Define the cost of moving between registers of various classes. Moving
772 between FLOAT_REGS and anything else except float regs is expensive.
773 In fact, we make it quite expensive because we really don't want to
774 do these moves unless it is clearly worth it. Optimizations may
775 reduce the impact of not being able to allocate a pseudo to a
778 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
779 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
781 : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
783 /* A C expressions returning the cost of moving data of MODE from a register to
786 On the Alpha, bump this up a bit. */
788 extern int alpha_memory_latency;
789 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
791 /* Provide the cost of a branch. Exact meaning under development. */
792 #define BRANCH_COST 5
794 /* Adjust the cost of dependencies. */
796 #define ADJUST_COST(INSN,LINK,DEP,COST) \
797 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
799 /* Stack layout; function entry, exit and calling. */
801 /* Define this if pushing a word on the stack
802 makes the stack pointer a smaller address. */
803 #define STACK_GROWS_DOWNWARD
805 /* Define this if the nominal address of the stack frame
806 is at the high-address end of the local variables;
807 that is, each additional local variable allocated
808 goes at a more negative offset in the frame. */
809 /* #define FRAME_GROWS_DOWNWARD */
811 /* Offset within stack frame to start allocating local variables at.
812 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
813 first local allocated. Otherwise, it is the offset to the BEGINNING
814 of the first local allocated. */
816 #define STARTING_FRAME_OFFSET 0
818 /* If we generate an insn to push BYTES bytes,
819 this says how many the stack pointer really advances by.
820 On Alpha, don't define this because there are no push insns. */
821 /* #define PUSH_ROUNDING(BYTES) */
823 /* Define this to be nonzero if stack checking is built into the ABI. */
824 #define STACK_CHECK_BUILTIN 1
826 /* Define this if the maximum size of all the outgoing args is to be
827 accumulated and pushed during the prologue. The amount can be
828 found in the variable current_function_outgoing_args_size. */
829 #define ACCUMULATE_OUTGOING_ARGS
831 /* Offset of first parameter from the argument pointer register value. */
833 #define FIRST_PARM_OFFSET(FNDECL) 0
835 /* Definitions for register eliminations.
837 We have two registers that can be eliminated on the Alpha. First, the
838 frame pointer register can often be eliminated in favor of the stack
839 pointer register. Secondly, the argument pointer register can always be
840 eliminated; it is replaced with either the stack or frame pointer. */
842 /* This is an array of structures. Each structure initializes one pair
843 of eliminable registers. The "from" register number is given first,
844 followed by "to". Eliminations of the same "from" register are listed
845 in order of preference. */
847 #define ELIMINABLE_REGS \
848 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
849 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
850 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
851 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
853 /* Given FROM and TO register numbers, say whether this elimination is allowed.
854 Frame pointer elimination is automatically handled.
856 All eliminations are valid since the cases where FP can't be
857 eliminated are already handled. */
859 #define CAN_ELIMINATE(FROM, TO) 1
861 /* Round up to a multiple of 16 bytes. */
862 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
864 /* Define the offset between two registers, one to be eliminated, and the other
865 its replacement, at the start of a routine. */
866 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
867 { if ((FROM) == FRAME_POINTER_REGNUM) \
868 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
869 + alpha_sa_size ()); \
870 else if ((FROM) == ARG_POINTER_REGNUM) \
871 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
873 + (ALPHA_ROUND (get_frame_size () \
874 + current_function_pretend_args_size) \
875 - current_function_pretend_args_size)); \
878 /* Define this if stack space is still allocated for a parameter passed
880 /* #define REG_PARM_STACK_SPACE */
882 /* Value is the number of bytes of arguments automatically
883 popped when returning from a subroutine call.
884 FUNDECL is the declaration node of the function (as a tree),
885 FUNTYPE is the data type of the function (as a tree),
886 or for a library call it is an identifier node for the subroutine name.
887 SIZE is the number of bytes of arguments passed on the stack. */
889 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
891 /* Define how to find the value returned by a function.
892 VALTYPE is the data type of the value (as a tree).
893 If the precise function being called is known, FUNC is its FUNCTION_DECL;
894 otherwise, FUNC is 0.
896 On Alpha the value is found in $0 for integer functions and
897 $f0 for floating-point functions. */
899 #define FUNCTION_VALUE(VALTYPE, FUNC) \
901 ((INTEGRAL_TYPE_P (VALTYPE) \
902 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
903 || POINTER_TYPE_P (VALTYPE)) \
904 ? word_mode : TYPE_MODE (VALTYPE), \
906 && (TREE_CODE (VALTYPE) == REAL_TYPE \
907 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
910 /* Define how to find the value returned by a library function
911 assuming the value has mode MODE. */
913 #define LIBCALL_VALUE(MODE) \
914 gen_rtx (REG, MODE, \
916 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
917 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
920 /* The definition of this macro implies that there are cases where
921 a scalar value cannot be returned in registers.
923 For the Alpha, any structure or union type is returned in memory, as
924 are integers whose size is larger than 64 bits. */
926 #define RETURN_IN_MEMORY(TYPE) \
927 (TYPE_MODE (TYPE) == BLKmode \
928 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
930 /* 1 if N is a possible register number for a function value
931 as seen by the caller. */
933 #define FUNCTION_VALUE_REGNO_P(N) \
934 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
936 /* 1 if N is a possible register number for function argument passing.
937 On Alpha, these are $16-$21 and $f16-$f21. */
939 #define FUNCTION_ARG_REGNO_P(N) \
940 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
942 /* Define a data type for recording info about an argument list
943 during the scan of that argument list. This data type should
944 hold all necessary information about the function itself
945 and about the args processed so far, enough to enable macros
946 such as FUNCTION_ARG to determine where the next arg should go.
948 On Alpha, this is a single integer, which is a number of words
949 of arguments scanned so far.
950 Thus 6 or more means all following args should go on the stack. */
952 #define CUMULATIVE_ARGS int
954 /* Initialize a variable CUM of type CUMULATIVE_ARGS
955 for a call to a function whose data type is FNTYPE.
956 For a library call, FNTYPE is 0. */
958 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
960 /* Define intermediate macro to compute the size (in registers) of an argument
963 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
965 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
966 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
968 /* Update the data in CUM to advance over an argument
969 of mode MODE and data type TYPE.
970 (TYPE is null for libcalls where that information may not be available.) */
972 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
973 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
976 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
978 /* Determine where to put an argument to a function.
979 Value is zero to push the argument on the stack,
980 or a hard register in which to store the argument.
982 MODE is the argument's machine mode.
983 TYPE is the data type of the argument (as a tree).
984 This is null for libcalls where that information may
986 CUM is a variable of type CUMULATIVE_ARGS which gives info about
987 the preceding args and about the function being called.
988 NAMED is nonzero if this argument is a named parameter
989 (otherwise it is an extra parameter matching an ellipsis).
991 On Alpha the first 6 words of args are normally in registers
992 and the rest are pushed. */
994 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
995 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
996 ? gen_rtx(REG, (MODE), \
997 (CUM) + 16 + ((TARGET_FPREGS \
998 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
999 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1003 /* Specify the padding direction of arguments.
1005 On the Alpha, we must pad upwards in order to be able to pass args in
1008 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1010 /* For an arg passed partly in registers and partly in memory,
1011 this is the number of registers used.
1012 For args passed entirely in registers or entirely in memory, zero. */
1014 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1015 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1018 /* Perform any needed actions needed for a function that is receiving a
1019 variable number of arguments.
1023 MODE and TYPE are the mode and type of the current parameter.
1025 PRETEND_SIZE is a variable that should be set to the amount of stack
1026 that must be pushed by the prolog to pretend that our caller pushed
1029 Normally, this macro will push all remaining incoming registers on the
1030 stack and set PRETEND_SIZE to the length of the registers pushed.
1032 On the Alpha, we allocate space for all 12 arg registers, but only
1033 push those that are remaining.
1035 However, if NO registers need to be saved, don't allocate any space.
1036 This is not only because we won't need the space, but because AP includes
1037 the current_pretend_args_size and we don't want to mess up any
1038 ap-relative addresses already made.
1040 If we are not to use the floating-point registers, save the integer
1041 registers where we would put the floating-point registers. This is
1042 not the most efficient way to implement varargs with just one register
1043 class, but it isn't worth doing anything more efficient in this rare
1047 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1052 move_block_from_reg \
1054 gen_rtx (MEM, BLKmode, \
1055 plus_constant (virtual_incoming_args_rtx, \
1056 ((CUM) + 6)* UNITS_PER_WORD)), \
1057 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1058 move_block_from_reg \
1059 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \
1060 gen_rtx (MEM, BLKmode, \
1061 plus_constant (virtual_incoming_args_rtx, \
1062 (CUM) * UNITS_PER_WORD)), \
1063 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1064 emit_insn (gen_blockage ()); \
1066 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1070 /* Try to output insns to set TARGET equal to the constant C if it can be
1071 done in less than N insns. Do all computations in MODE. Returns the place
1072 where the output has been placed if it can be done and the insns have been
1073 emitted. If it would take more than N insns, zero is returned and no
1074 insns and emitted. */
1075 extern struct rtx_def *alpha_emit_set_const ();
1076 extern struct rtx_def *alpha_emit_set_long_const ();
1077 extern struct rtx_def *alpha_emit_conditional_branch ();
1078 extern struct rtx_def *alpha_emit_conditional_move ();
1080 /* Generate necessary RTL for __builtin_saveregs().
1081 ARGLIST is the argument list; see expr.c. */
1082 extern struct rtx_def *alpha_builtin_saveregs ();
1083 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
1085 /* Define the information needed to generate branch and scc insns. This is
1086 stored from the compare operation. Note that we can't use "rtx" here
1087 since it hasn't been defined! */
1089 extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
1090 extern int alpha_compare_fp_p;
1092 /* Make (or fake) .linkage entry for function call.
1094 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1095 extern void alpha_need_linkage ();
1097 /* This macro defines the start of an assembly comment. */
1099 #define ASM_COMMENT_START " #"
1101 /* This macro produces the initial definition of a function name. On the
1102 Alpha, we need to save the function name for the prologue and epilogue. */
1104 extern char *alpha_function_name;
1106 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1108 alpha_function_name = NAME; \
1111 /* This macro generates the assembly code for function entry.
1112 FILE is a stdio stream to output the code to.
1113 SIZE is an int: how many units of temporary storage to allocate.
1114 Refer to the array `regs_ever_live' to determine which registers
1115 to save; `regs_ever_live[I]' is nonzero if register number I
1116 is ever used in the function. This macro is responsible for
1117 knowing which registers should not be saved even if used. */
1119 #define FUNCTION_PROLOGUE(FILE, SIZE) output_prologue (FILE, SIZE)
1121 /* This macro notes the end of the prologue. */
1123 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1125 /* Output assembler code to FILE to increment profiler label # LABELNO
1126 for profiling a function entry. Under OSF/1, profiling is enabled
1127 by simply passing -pg to the assembler and linker. */
1129 #define FUNCTION_PROFILER(FILE, LABELNO)
1131 /* Output assembler code to FILE to initialize this source file's
1132 basic block profiling info, if that has not already been done.
1133 This assumes that __bb_init_func doesn't garble a1-a5. */
1135 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1137 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1138 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1139 fputs ("\tldq $26,0($16)\n", (FILE)); \
1140 fputs ("\tbne $26,1f\n", (FILE)); \
1141 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1142 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1143 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1144 fputs ("1:\n", (FILE)); \
1145 ASM_OUTPUT_REG_POP (FILE, 16); \
1148 /* Output assembler code to FILE to increment the entry-count for
1149 the BLOCKNO'th basic block in this source file. */
1151 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1153 int blockn = (BLOCKNO); \
1154 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1155 fputs ("\tstq $26,0($30)\n", (FILE)); \
1156 fputs ("\tstq $27,8($30)\n", (FILE)); \
1157 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1158 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1159 fputs ("\taddq $27,1,$27\n", (FILE)); \
1160 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1161 fputs ("\tldq $26,0($30)\n", (FILE)); \
1162 fputs ("\tldq $27,8($30)\n", (FILE)); \
1163 fputs ("\taddq $30,16,$30\n", (FILE)); \
1167 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1168 the stack pointer does not matter. The value is tested only in
1169 functions that have frame pointers.
1170 No definition is equivalent to always zero. */
1172 #define EXIT_IGNORE_STACK 1
1174 /* This macro generates the assembly code for function exit,
1175 on machines that need it. If FUNCTION_EPILOGUE is not defined
1176 then individual return instructions are generated for each
1177 return statement. Args are same as for FUNCTION_PROLOGUE.
1179 The function epilogue should not depend on the current stack pointer!
1180 It should use the frame pointer only. This is mandatory because
1181 of alloca; we also take advantage of it to omit stack adjustments
1182 before returning. */
1184 #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilogue (FILE, SIZE)
1187 /* Output assembler code for a block containing the constant parts
1188 of a trampoline, leaving space for the variable parts.
1190 The trampoline should set the static chain pointer to value placed
1191 into the trampoline and should branch to the specified routine.
1192 Note that $27 has been set to the address of the trampoline, so we can
1193 use it for addressability of the two data items. Trampolines are always
1194 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1196 #define TRAMPOLINE_TEMPLATE(FILE) \
1198 fprintf (FILE, "\tldq $1,24($27)\n"); \
1199 fprintf (FILE, "\tldq $27,16($27)\n"); \
1200 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1201 fprintf (FILE, "\tnop\n"); \
1202 fprintf (FILE, "\t.quad 0,0\n"); \
1205 /* Section in which to place the trampoline. On Alpha, instructions
1206 may only be placed in a text segment. */
1208 #define TRAMPOLINE_SECTION text_section
1210 /* Length in units of the trampoline for entering a nested function. */
1212 #define TRAMPOLINE_SIZE 32
1214 /* Emit RTL insns to initialize the variable parts of a trampoline.
1215 FNADDR is an RTX for the address of the function's pure code.
1216 CXT is an RTX for the static chain value for the function. We assume
1217 here that a function will be called many more times than its address
1218 is taken (e.g., it might be passed to qsort), so we take the trouble
1219 to initialize the "hint" field in the JMP insn. Note that the hint
1220 field is PC (new) + 4 * bits 13:0. */
1222 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1224 rtx _temp, _temp1, _addr; \
1226 _addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1227 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR)); \
1228 _addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1229 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT)); \
1231 _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX); \
1232 _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1, \
1234 _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp, \
1235 build_int_2 (2, 0), NULL_RTX, 1); \
1236 _temp = expand_and (gen_lowpart (SImode, _temp), \
1237 GEN_INT (0x3fff), 0); \
1239 _addr = memory_address (SImode, plus_constant ((TRAMP), 8)); \
1240 _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr)); \
1241 _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX); \
1242 _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1, \
1245 emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1); \
1247 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \
1248 "__enable_execute_stack"), \
1249 0, VOIDmode, 1,_addr, Pmode); \
1251 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1252 gen_rtvec (1, const0_rtx), 0)); \
1255 /* Attempt to turn on access permissions for the stack. */
1257 #define TRANSFER_FROM_TRAMPOLINE \
1259 __enable_execute_stack (addr) \
1262 long size = getpagesize (); \
1263 long mask = ~(size-1); \
1264 char *page = (char *) (((long) addr) & mask); \
1265 char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
1267 /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \
1268 if (mprotect (page, end - page, 7) < 0) \
1269 perror ("mprotect of trampoline code"); \
1272 /* A C expression whose value is RTL representing the value of the return
1273 address for the frame COUNT steps up from the current frame.
1274 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1275 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME} is defined. */
1277 #define RETURN_ADDR_RTX alpha_return_addr
1278 extern struct rtx_def *alpha_return_addr ();
1280 /* Initialize data used by insn expanders. This is called from insn_emit,
1281 once for every function before code is generated. */
1283 #define INIT_EXPANDERS alpha_init_expanders ()
1284 extern void alpha_init_expanders ();
1287 /* Addressing modes, and classification of registers for them. */
1289 /* #define HAVE_POST_INCREMENT */
1290 /* #define HAVE_POST_DECREMENT */
1292 /* #define HAVE_PRE_DECREMENT */
1293 /* #define HAVE_PRE_INCREMENT */
1295 /* Macros to check register numbers against specific register classes. */
1297 /* These assume that REGNO is a hard or pseudo reg number.
1298 They give nonzero only if REGNO is a hard reg of the suitable class
1299 or a pseudo reg currently allocated to a suitable hard reg.
1300 Since they use reg_renumber, they are safe only once reg_renumber
1301 has been allocated, which happens in local-alloc.c. */
1303 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1304 #define REGNO_OK_FOR_BASE_P(REGNO) \
1305 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1306 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1308 /* Maximum number of registers that can appear in a valid memory address. */
1309 #define MAX_REGS_PER_ADDRESS 1
1311 /* Recognize any constant value that is a valid address. For the Alpha,
1312 there are only constants none since we want to use LDA to load any
1313 symbolic addresses into registers. */
1315 #define CONSTANT_ADDRESS_P(X) \
1316 (GET_CODE (X) == CONST_INT \
1317 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1319 /* Include all constant integers and constant doubles, but not
1320 floating-point, except for floating-point zero. */
1322 #define LEGITIMATE_CONSTANT_P(X) \
1323 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1324 || (X) == CONST0_RTX (GET_MODE (X)))
1326 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1327 and check its validity for a certain class.
1328 We have two alternate definitions for each of them.
1329 The usual definition accepts all pseudo regs; the other rejects
1330 them unless they have been allocated suitable hard regs.
1331 The symbol REG_OK_STRICT causes the latter definition to be used.
1333 Most source files want to accept pseudo regs in the hope that
1334 they will get allocated to the class that the insn wants them to be in.
1335 Source files for reload pass need to be strict.
1336 After reload, it makes no difference, since pseudo regs have
1337 been eliminated by then. */
1339 #ifndef REG_OK_STRICT
1341 /* Nonzero if X is a hard reg that can be used as an index
1342 or if it is a pseudo reg. */
1343 #define REG_OK_FOR_INDEX_P(X) 0
1344 /* Nonzero if X is a hard reg that can be used as a base reg
1345 or if it is a pseudo reg. */
1346 #define REG_OK_FOR_BASE_P(X) \
1347 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1351 /* Nonzero if X is a hard reg that can be used as an index. */
1352 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1353 /* Nonzero if X is a hard reg that can be used as a base reg. */
1354 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1358 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1359 that is a valid memory address for an instruction.
1360 The MODE argument is the machine mode for the MEM expression
1361 that wants to use this address.
1363 For Alpha, we have either a constant address or the sum of a register
1364 and a constant address, or just a register. For DImode, any of those
1365 forms can be surrounded with an AND that clear the low-order three bits;
1366 this is an "unaligned" access.
1368 First define the basic valid address. */
1370 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1371 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1373 if (CONSTANT_ADDRESS_P (X)) \
1375 if (GET_CODE (X) == PLUS \
1376 && REG_P (XEXP (X, 0)) \
1377 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1378 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1382 /* Now accept the simple address, or, for DImode only, an AND of a simple
1383 address that turns off the low three bits. */
1385 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1386 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1387 if ((MODE) == DImode \
1388 && GET_CODE (X) == AND \
1389 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1390 && INTVAL (XEXP (X, 1)) == -8) \
1391 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1394 /* Try machine-dependent ways of modifying an illegitimate address
1395 to be legitimate. If we find one, return the new, valid address.
1396 This macro is used in only one place: `memory_address' in explow.c.
1398 OLDX is the address as it was before break_out_memory_refs was called.
1399 In some cases it is useful to look at this to decide what needs to be done.
1401 MODE and WIN are passed so that this macro can use
1402 GO_IF_LEGITIMATE_ADDRESS.
1404 It is always safe for this macro to do nothing. It exists to recognize
1405 opportunities to optimize the output.
1407 For the Alpha, there are three cases we handle:
1409 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1410 valid offset, compute the high part of the constant and add it to the
1411 register. Then our address is (plus temp low-part-const).
1412 (2) If the address is (const (plus FOO const_int)), find the low-order
1413 part of the CONST_INT. Then load FOO plus any high-order part of the
1414 CONST_INT into a register. Our address is (plus reg low-part-const).
1415 This is done to reduce the number of GOT entries.
1416 (3) If we have a (plus reg const), emit the load as in (2), then add
1417 the two registers, and finally generate (plus reg low-part-const) as
1420 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1421 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1422 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1423 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1425 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1426 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1427 HOST_WIDE_INT highpart = val - lowpart; \
1428 rtx high = GEN_INT (highpart); \
1429 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1430 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1432 (X) = plus_constant (temp, lowpart); \
1435 else if (GET_CODE (X) == CONST \
1436 && GET_CODE (XEXP (X, 0)) == PLUS \
1437 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1439 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1440 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1441 HOST_WIDE_INT highpart = val - lowpart; \
1442 rtx high = XEXP (XEXP (X, 0), 0); \
1445 high = plus_constant (high, highpart); \
1447 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1450 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1451 && GET_CODE (XEXP (X, 1)) == CONST \
1452 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1453 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1455 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1456 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1457 HOST_WIDE_INT highpart = val - lowpart; \
1458 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1461 high = plus_constant (high, highpart); \
1463 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1464 force_reg (Pmode, high), \
1465 high, 1, OPTAB_LIB_WIDEN); \
1466 (X) = plus_constant (high, lowpart); \
1471 /* Try a machine-dependent way of reloading an illegitimate address
1472 operand. If we find one, push the reload and jump to WIN. This
1473 macro is used in only one place: `find_reloads_address' in reload.c.
1475 For the Alpha, we wish to handle large displacements off a base
1476 register by splitting the addend across an ldah and the mem insn.
1477 This cuts number of extra insns needed from 3 to 1. */
1479 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1481 if (GET_CODE (X) == PLUS \
1482 && GET_CODE (XEXP (X, 0)) == REG \
1483 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1484 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1485 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1487 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1488 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1489 HOST_WIDE_INT high \
1490 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1492 /* Check for 32-bit overflow. */ \
1493 if (high + low != val) \
1496 /* Reload the high part into a base reg; leave the low part \
1497 in the mem directly. */ \
1499 X = gen_rtx_PLUS (GET_MODE (X), \
1500 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1504 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1505 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1511 /* Go to LABEL if ADDR (a legitimate address expression)
1512 has an effect that depends on the machine mode it is used for.
1513 On the Alpha this is true only for the unaligned modes. We can
1514 simplify this test since we know that the address must be valid. */
1516 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1517 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1519 /* Compute the cost of an address. For the Alpha, all valid addresses are
1522 #define ADDRESS_COST(X) 0
1524 /* Machine-dependent reorg pass. */
1525 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1527 /* Specify the machine mode that this machine uses
1528 for the index in the tablejump instruction. */
1529 #define CASE_VECTOR_MODE SImode
1531 /* Define as C expression which evaluates to nonzero if the tablejump
1532 instruction expects the table to contain offsets from the address of the
1535 Do not define this if the table should contain absolute addresses.
1536 On the Alpha, the table is really GP-relative, not relative to the PC
1537 of the table, but we pretend that it is PC-relative; this should be OK,
1538 but we should try to find some better way sometime. */
1539 #define CASE_VECTOR_PC_RELATIVE 1
1541 /* Specify the tree operation to be used to convert reals to integers. */
1542 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1544 /* This is the kind of divide that is easiest to do in the general case. */
1545 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1547 /* Define this as 1 if `char' should by default be signed; else as 0. */
1548 #define DEFAULT_SIGNED_CHAR 1
1550 /* This flag, if defined, says the same insns that convert to a signed fixnum
1551 also convert validly to an unsigned one.
1553 We actually lie a bit here as overflow conditions are different. But
1554 they aren't being checked anyway. */
1556 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1558 /* Max number of bytes we can move to or from memory
1559 in one reasonably fast instruction. */
1563 /* Controls how many units are moved by expr.c before resorting to movstr.
1564 Without byte/word accesses, we want no more than one; with, several single
1565 byte accesses are better. */
1567 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1569 /* Largest number of bytes of an object that can be placed in a register.
1570 On the Alpha we have plenty of registers, so use TImode. */
1571 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1573 /* Nonzero if access to memory by bytes is no faster than for words.
1574 Also non-zero if doing byte operations (specifically shifts) in registers
1577 On the Alpha, we want to not use the byte operation and instead use
1578 masking operations to access fields; these will save instructions. */
1580 #define SLOW_BYTE_ACCESS 1
1582 /* Define if operations between registers always perform the operation
1583 on the full register even if a narrower mode is specified. */
1584 #define WORD_REGISTER_OPERATIONS
1586 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1587 will either zero-extend or sign-extend. The value of this macro should
1588 be the code that says which one of the two operations is implicitly
1589 done, NIL if none. */
1590 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1592 /* Define if loading short immediate values into registers sign extends. */
1593 #define SHORT_IMMEDIATES_SIGN_EXTEND
1595 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1596 is done just by pretending it is already truncated. */
1597 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1599 /* We assume that the store-condition-codes instructions store 0 for false
1600 and some other value for true. This is the value stored for true. */
1602 #define STORE_FLAG_VALUE 1
1604 /* Define the value returned by a floating-point comparison instruction. */
1606 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1608 /* Canonicalize a comparison from one we don't have to one we do have. */
1610 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1612 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1613 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1618 (CODE) = swap_condition (CODE); \
1620 if (((CODE) == LT || (CODE) == LTU) \
1621 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1623 (CODE) = (CODE) == LT ? LE : LEU; \
1624 (OP1) = GEN_INT (255); \
1628 /* Specify the machine mode that pointers have.
1629 After generation of rtl, the compiler makes no further distinction
1630 between pointers and any other objects of this machine mode. */
1631 #define Pmode DImode
1633 /* Mode of a function address in a call instruction (for indexing purposes). */
1635 #define FUNCTION_MODE Pmode
1637 /* Define this if addresses of constant functions
1638 shouldn't be put through pseudo regs where they can be cse'd.
1639 Desirable on machines where ordinary constants are expensive
1640 but a CALL with constant address is cheap.
1642 We define this on the Alpha so that gen_call and gen_call_value
1643 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1644 then copy it into a register, thus actually letting the address be
1647 #define NO_FUNCTION_CSE
1649 /* Define this to be nonzero if shift instructions ignore all but the low-order
1651 #define SHIFT_COUNT_TRUNCATED 1
1653 /* Use atexit for static constructors/destructors, instead of defining
1654 our own exit function. */
1657 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1658 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1660 /* Compute the cost of computing a constant rtl expression RTX
1661 whose rtx-code is CODE. The body of this macro is a portion
1662 of a switch statement. If the code is computed here,
1663 return it with a return statement. Otherwise, break from the switch.
1665 If this is an 8-bit constant, return zero since it can be used
1666 nearly anywhere with no cost. If it is a valid operand for an
1667 ADD or AND, likewise return 0 if we know it will be used in that
1668 context. Otherwise, return 2 since it might be used there later.
1669 All other constants take at least two insns. */
1671 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1673 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1675 case CONST_DOUBLE: \
1676 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1678 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1679 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1681 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1684 return COSTS_N_INSNS (2); \
1688 switch (alpha_cpu) \
1690 case PROCESSOR_EV4: \
1691 return COSTS_N_INSNS (3); \
1692 case PROCESSOR_EV5: \
1693 case PROCESSOR_EV6: \
1694 return COSTS_N_INSNS (2); \
1698 /* Provide the costs of a rtl expression. This is in the body of a
1701 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1702 case PLUS: case MINUS: \
1703 if (FLOAT_MODE_P (GET_MODE (X))) \
1704 switch (alpha_cpu) \
1706 case PROCESSOR_EV4: \
1707 return COSTS_N_INSNS (6); \
1708 case PROCESSOR_EV5: \
1709 case PROCESSOR_EV6: \
1710 return COSTS_N_INSNS (4); \
1713 else if (GET_CODE (XEXP (X, 0)) == MULT \
1714 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1715 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1716 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1719 switch (alpha_cpu) \
1721 case PROCESSOR_EV4: \
1722 if (FLOAT_MODE_P (GET_MODE (X))) \
1723 return COSTS_N_INSNS (6); \
1724 return COSTS_N_INSNS (23); \
1725 case PROCESSOR_EV5: \
1726 if (FLOAT_MODE_P (GET_MODE (X))) \
1727 return COSTS_N_INSNS (4); \
1728 else if (GET_MODE (X) == DImode) \
1729 return COSTS_N_INSNS (12); \
1731 return COSTS_N_INSNS (8); \
1732 case PROCESSOR_EV6: \
1733 if (FLOAT_MODE_P (GET_MODE (X))) \
1734 return COSTS_N_INSNS (4); \
1736 return COSTS_N_INSNS (7); \
1740 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1741 && INTVAL (XEXP (X, 1)) <= 3) \
1743 /* ... fall through ... */ \
1744 case ASHIFTRT: case LSHIFTRT: \
1745 switch (alpha_cpu) \
1747 case PROCESSOR_EV4: \
1748 return COSTS_N_INSNS (2); \
1749 case PROCESSOR_EV5: \
1750 case PROCESSOR_EV6: \
1751 return COSTS_N_INSNS (1); \
1754 case IF_THEN_ELSE: \
1755 switch (alpha_cpu) \
1757 case PROCESSOR_EV4: \
1758 case PROCESSOR_EV6: \
1759 return COSTS_N_INSNS (2); \
1760 case PROCESSOR_EV5: \
1761 return COSTS_N_INSNS (1); \
1764 case DIV: case UDIV: case MOD: case UMOD: \
1765 switch (alpha_cpu) \
1767 case PROCESSOR_EV4: \
1768 if (GET_MODE (X) == SFmode) \
1769 return COSTS_N_INSNS (34); \
1770 else if (GET_MODE (X) == DFmode) \
1771 return COSTS_N_INSNS (63); \
1773 return COSTS_N_INSNS (70); \
1774 case PROCESSOR_EV5: \
1775 if (GET_MODE (X) == SFmode) \
1776 return COSTS_N_INSNS (15); \
1777 else if (GET_MODE (X) == DFmode) \
1778 return COSTS_N_INSNS (22); \
1780 return COSTS_N_INSNS (70); /* ??? */ \
1781 case PROCESSOR_EV6: \
1782 if (GET_MODE (X) == SFmode) \
1783 return COSTS_N_INSNS (12); \
1784 else if (GET_MODE (X) == DFmode) \
1785 return COSTS_N_INSNS (15); \
1787 return COSTS_N_INSNS (70); /* ??? */ \
1791 switch (alpha_cpu) \
1793 case PROCESSOR_EV4: \
1794 case PROCESSOR_EV6: \
1795 return COSTS_N_INSNS (3); \
1796 case PROCESSOR_EV5: \
1797 return COSTS_N_INSNS (2); \
1800 case NEG: case ABS: \
1801 if (! FLOAT_MODE_P (GET_MODE (X))) \
1803 /* ... fall through ... */ \
1804 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1805 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1806 switch (alpha_cpu) \
1808 case PROCESSOR_EV4: \
1809 return COSTS_N_INSNS (6); \
1810 case PROCESSOR_EV5: \
1811 case PROCESSOR_EV6: \
1812 return COSTS_N_INSNS (4); \
1816 /* Control the assembler format that we output. */
1818 /* We don't emit these labels, so as to avoid getting linker errors about
1819 missing exception handling info. If we emit a gcc_compiled. label into
1820 text, and the file has no code, then the DEC assembler gives us a zero
1821 sized text section with no associated exception handling info. The
1822 DEC linker sees this text section, and gives a warning saying that
1823 the exception handling info is missing. */
1824 #define ASM_IDENTIFY_GCC
1825 #define ASM_IDENTIFY_LANGUAGE
1827 /* Output to assembler file text saying following lines
1828 may contain character constants, extra white space, comments, etc. */
1830 #define ASM_APP_ON ""
1832 /* Output to assembler file text saying following lines
1833 no longer contain unusual constructs. */
1835 #define ASM_APP_OFF ""
1837 #define TEXT_SECTION_ASM_OP ".text"
1839 /* Output before read-only data. */
1841 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1843 /* Output before writable data. */
1845 #define DATA_SECTION_ASM_OP ".data"
1847 /* Define an extra section for read-only data, a routine to enter it, and
1848 indicate that it is for read-only data.
1850 The first time we enter the readonly data section for a file, we write
1851 eight bytes of zero. This works around a bug in DEC's assembler in
1852 some versions of OSF/1 V3.x. */
1854 #define EXTRA_SECTIONS readonly_data
1856 #define EXTRA_SECTION_FUNCTIONS \
1858 literal_section () \
1860 if (in_section != readonly_data) \
1862 static int firsttime = 1; \
1864 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1868 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1871 in_section = readonly_data; \
1875 #define READONLY_DATA_SECTION literal_section
1877 /* If we are referencing a function that is static, make the SYMBOL_REF
1878 special. We use this to see indicate we can branch to this function
1879 without setting PV or restoring GP. */
1881 #define ENCODE_SECTION_INFO(DECL) \
1882 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1883 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1885 /* How to refer to registers in assembler output.
1886 This sequence is indexed by compiler's hard-register-number (see above). */
1888 #define REGISTER_NAMES \
1889 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1890 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1891 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1892 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1893 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1894 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1895 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1896 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1898 /* How to renumber registers for dbx and gdb. */
1900 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1902 /* This is how to output the definition of a user-level label named NAME,
1903 such as the label on a static function or variable NAME. */
1905 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1906 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1908 /* This is how to output a command to make the user-level label named NAME
1909 defined for reference from other files. */
1911 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1912 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1914 /* The prefix to add to user-visible assembler symbols. */
1916 #define USER_LABEL_PREFIX ""
1918 /* This is how to output an internal numbered label where
1919 PREFIX is the class of label and NUM is the number within the class. */
1921 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1922 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1924 /* This is how to output a label for a jump table. Arguments are the same as
1925 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1928 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1929 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1931 /* This is how to store into the string LABEL
1932 the symbol_ref name of an internal numbered label where
1933 PREFIX is the class of label and NUM is the number within the class.
1934 This is suitable for output with `assemble_name'. */
1936 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1937 sprintf (LABEL, "*$%s%d", PREFIX, NUM)
1939 /* Check a floating-point value for validity for a particular machine mode. */
1941 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1942 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1944 /* This is how to output an assembler line defining a `double' constant. */
1946 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1948 if (REAL_VALUE_ISINF (VALUE) \
1949 || REAL_VALUE_ISNAN (VALUE) \
1950 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1953 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1954 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
1955 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1960 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
1961 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
1965 /* This is how to output an assembler line defining a `float' constant. */
1967 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1970 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1971 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
1974 /* This is how to output an assembler line defining an `int' constant. */
1976 #define ASM_OUTPUT_INT(FILE,VALUE) \
1977 ( fprintf (FILE, "\t.long "), \
1978 output_addr_const (FILE, (VALUE)), \
1979 fprintf (FILE, "\n"))
1981 /* This is how to output an assembler line defining a `long' constant. */
1983 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1984 ( fprintf (FILE, "\t.quad "), \
1985 output_addr_const (FILE, (VALUE)), \
1986 fprintf (FILE, "\n"))
1988 /* Likewise for `char' and `short' constants. */
1990 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1991 fprintf (FILE, "\t.word %d\n", \
1992 (GET_CODE (VALUE) == CONST_INT \
1993 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
1995 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1996 fprintf (FILE, "\t.byte %d\n", \
1997 (GET_CODE (VALUE) == CONST_INT \
1998 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2000 /* We use the default ASCII-output routine, except that we don't write more
2001 than 50 characters since the assembler doesn't support very long lines. */
2003 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2005 FILE *_hide_asm_out_file = (MYFILE); \
2006 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
2007 int _hide_thissize = (MYLENGTH); \
2008 int _size_so_far = 0; \
2010 FILE *asm_out_file = _hide_asm_out_file; \
2011 unsigned char *p = _hide_p; \
2012 int thissize = _hide_thissize; \
2014 fprintf (asm_out_file, "\t.ascii \""); \
2016 for (i = 0; i < thissize; i++) \
2018 register int c = p[i]; \
2020 if (_size_so_far ++ > 50 && i < thissize - 4) \
2021 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2023 if (c == '\"' || c == '\\') \
2024 putc ('\\', asm_out_file); \
2025 if (c >= ' ' && c < 0177) \
2026 putc (c, asm_out_file); \
2029 fprintf (asm_out_file, "\\%o", c); \
2030 /* After an octal-escape, if a digit follows, \
2031 terminate one string constant and start another. \
2032 The Vax assembler fails to stop reading the escape \
2033 after three digits, so this is the only way we \
2034 can get it to parse the data properly. */ \
2035 if (i < thissize - 1 \
2036 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2037 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2040 fprintf (asm_out_file, "\"\n"); \
2045 /* This is how to output an insn to push a register on the stack.
2046 It need not be very fast code. */
2048 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2049 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2050 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2053 /* This is how to output an insn to pop a register from the stack.
2054 It need not be very fast code. */
2056 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2057 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2058 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2061 /* This is how to output an assembler line for a numeric constant byte. */
2063 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2064 fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff)
2066 /* This is how to output an element of a case-vector that is absolute.
2067 (Alpha does not use such vectors, but we must define this macro anyway.) */
2069 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2071 /* This is how to output an element of a case-vector that is relative. */
2073 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2074 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2077 /* This is how to output an assembler line
2078 that says to advance the location counter
2079 to a multiple of 2**LOG bytes. */
2081 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2083 fprintf (FILE, "\t.align %d\n", LOG);
2085 /* This is how to advance the location counter by SIZE bytes. */
2087 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2088 fprintf (FILE, "\t.space %d\n", (SIZE))
2090 /* This says how to output an assembler line
2091 to define a global common symbol. */
2093 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2094 ( fputs ("\t.comm ", (FILE)), \
2095 assemble_name ((FILE), (NAME)), \
2096 fprintf ((FILE), ",%d\n", (SIZE)))
2098 /* This says how to output an assembler line
2099 to define a local common symbol. */
2101 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2102 ( fputs ("\t.lcomm ", (FILE)), \
2103 assemble_name ((FILE), (NAME)), \
2104 fprintf ((FILE), ",%d\n", (SIZE)))
2106 /* Store in OUTPUT a string (made with alloca) containing
2107 an assembler-name for a local static variable named NAME.
2108 LABELNO is an integer which is different for each call. */
2110 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2111 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2112 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2114 /* Define the parentheses used to group arithmetic operations
2115 in assembler code. */
2117 #define ASM_OPEN_PAREN "("
2118 #define ASM_CLOSE_PAREN ")"
2120 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2121 Used for C++ multiple inheritance. */
2123 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2125 char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2127 fprintf (FILE, "\t.ent "); \
2128 assemble_name (FILE, alpha_function_name); \
2129 fputc ('\n', FILE); \
2130 ASM_OUTPUT_LABEL (FILE, alpha_function_name); \
2131 fprintf (FILE, "\tldgp $29,0($27)\n"); \
2132 fputc ('$', FILE); \
2133 assemble_name (FILE, alpha_function_name); \
2134 fprintf (FILE, "..ng:\n"); \
2135 fprintf (FILE, "\t.frame $30,0,$26,0\n"); \
2136 fprintf (FILE, "\t.prologue 1\n"); \
2138 /* Rely on the assembler to macro expand a large delta. */ \
2139 fprintf (FILE, "\tlda $16,%ld($16)\n", (long)(DELTA)); \
2141 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \
2143 fprintf (FILE, "\tbr $31,$"); \
2144 assemble_name (FILE, fn_name); \
2145 fprintf (FILE, "..ng\n"); \
2149 fprintf (FILE, "\tlda $27,"); \
2150 assemble_name (FILE, fn_name); \
2151 fprintf (FILE, "\n\tjmp $31,($27),"); \
2152 assemble_name (FILE, fn_name); \
2153 fputc ('\n', FILE); \
2156 fprintf (FILE, "\t.end "); \
2157 assemble_name (FILE, alpha_function_name); \
2158 fputc ('\n', FILE); \
2162 /* Define results of standard character escape sequences. */
2163 #define TARGET_BELL 007
2164 #define TARGET_BS 010
2165 #define TARGET_TAB 011
2166 #define TARGET_NEWLINE 012
2167 #define TARGET_VT 013
2168 #define TARGET_FF 014
2169 #define TARGET_CR 015
2171 /* Print operand X (an rtx) in assembler syntax to file FILE.
2172 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2173 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2175 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2177 /* Determine which codes are valid without a following integer. These must
2178 not be alphabetic (the characters are chosen so that
2179 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2182 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2183 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2184 mode. alpha_fprm controls which suffix is generated.
2186 ' Generates trap-mode suffix for instructions that accept the
2187 su suffix only (cmpt et al).
2189 ` Generates trap-mode suffix for instructions that accept the
2190 v and sv suffix. The only instruction that needs this is cvtql.
2192 ( Generates trap-mode suffix for instructions that accept the
2193 v, sv, and svi suffix. The only instruction that needs this
2196 ) Generates trap-mode suffix for instructions that accept the
2197 u, su, and sui suffix. This is the bulk of the IEEE floating
2198 point instructions (addt et al).
2200 + Generates trap-mode suffix for instructions that accept the
2201 sui suffix (cvtqt and cvtqs).
2203 , Generates single precision suffix for floating point
2204 instructions (s for IEEE, f for VAX)
2206 - Generates double precision suffix for floating point
2207 instructions (t for IEEE, g for VAX)
2210 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2211 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2212 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2214 /* Print a memory address as an operand to reference that memory location. */
2216 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2217 { rtx addr = (ADDR); \
2219 HOST_WIDE_INT offset = 0; \
2221 if (GET_CODE (addr) == AND) \
2222 addr = XEXP (addr, 0); \
2224 if (GET_CODE (addr) == REG) \
2225 basereg = REGNO (addr); \
2226 else if (GET_CODE (addr) == CONST_INT) \
2227 offset = INTVAL (addr); \
2228 else if (GET_CODE (addr) == PLUS \
2229 && GET_CODE (XEXP (addr, 0)) == REG \
2230 && GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2231 basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
2235 fprintf (FILE, "%d($%d)", offset, basereg); \
2237 /* Define the codes that are matched by predicates in alpha.c. */
2239 #define PREDICATE_CODES \
2240 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2241 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2242 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2243 {"cint8_operand", {CONST_INT}}, \
2244 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2245 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2246 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2247 {"const48_operand", {CONST_INT}}, \
2248 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2249 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2250 {"mode_mask_operand", {CONST_INT}}, \
2251 {"mul8_operand", {CONST_INT}}, \
2252 {"mode_width_operand", {CONST_INT}}, \
2253 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2254 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2255 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2256 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2257 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2258 {"fp0_operand", {CONST_DOUBLE}}, \
2259 {"current_file_function_operand", {SYMBOL_REF}}, \
2260 {"call_operand", {REG, SYMBOL_REF}}, \
2261 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2262 SYMBOL_REF, CONST, LABEL_REF}}, \
2263 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2264 SYMBOL_REF, CONST, LABEL_REF}}, \
2265 {"aligned_memory_operand", {MEM}}, \
2266 {"unaligned_memory_operand", {MEM}}, \
2267 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2268 {"any_memory_operand", {MEM}}, \
2269 {"hard_fp_register_operand", {SUBREG, REG}},
2271 /* Tell collect that the object format is ECOFF. */
2272 #define OBJECT_FORMAT_COFF
2273 #define EXTENDED_COFF
2275 /* If we use NM, pass -g to it so it only lists globals. */
2276 #define NM_FLAGS "-pg"
2278 /* Definitions for debugging. */
2280 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2281 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2282 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2284 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2285 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2289 /* Correct the offset of automatic variables and arguments. Note that
2290 the Alpha debug format wants all automatic variables and arguments
2291 to be in terms of two different offsets from the virtual frame pointer,
2292 which is the stack pointer before any adjustment in the function.
2293 The offset for the argument pointer is fixed for the native compiler,
2294 it is either zero (for the no arguments case) or large enough to hold
2295 all argument registers.
2296 The offset for the auto pointer is the fourth argument to the .frame
2297 directive (local_offset).
2298 To stay compatible with the native tools we use the same offsets
2299 from the virtual frame pointer and adjust the debugger arg/auto offsets
2300 accordingly. These debugger offsets are set up in output_prolog. */
2302 extern long alpha_arg_offset;
2303 extern long alpha_auto_offset;
2304 #define DEBUGGER_AUTO_OFFSET(X) \
2305 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2306 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2309 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2310 alpha_output_lineno (STREAM, LINE)
2311 extern void alpha_output_lineno ();
2313 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2314 alpha_output_filename (STREAM, NAME)
2315 extern void alpha_output_filename ();
2317 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2318 number, because the real length runs past this up to the next
2319 continuation point. This is really a dbxout.c bug. */
2320 #define DBX_CONTIN_LENGTH 3000
2322 /* By default, turn on GDB extensions. */
2323 #define DEFAULT_GDB_EXTENSIONS 1
2325 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2326 #define NO_DBX_FUNCTION_END 1
2328 /* If we are smuggling stabs through the ALPHA ECOFF object
2329 format, put a comment in front of the .stab<x> operation so
2330 that the ALPHA assembler does not choke. The mips-tfile program
2331 will correctly put the stab into the object file. */
2333 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2334 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2335 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2337 /* Forward references to tags are allowed. */
2338 #define SDB_ALLOW_FORWARD_REFERENCES
2340 /* Unknown tags are also allowed. */
2341 #define SDB_ALLOW_UNKNOWN_REFERENCES
2343 #define PUT_SDB_DEF(a) \
2345 fprintf (asm_out_file, "\t%s.def\t", \
2346 (TARGET_GAS) ? "" : "#"); \
2347 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2348 fputc (';', asm_out_file); \
2351 #define PUT_SDB_PLAIN_DEF(a) \
2353 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2354 (TARGET_GAS) ? "" : "#", (a)); \
2357 #define PUT_SDB_TYPE(a) \
2359 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2362 /* For block start and end, we create labels, so that
2363 later we can figure out where the correct offset is.
2364 The normal .ent/.end serve well enough for functions,
2365 so those are just commented out. */
2367 extern int sdb_label_count; /* block start/end next label # */
2369 #define PUT_SDB_BLOCK_START(LINE) \
2371 fprintf (asm_out_file, \
2372 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2374 (TARGET_GAS) ? "" : "#", \
2377 sdb_label_count++; \
2380 #define PUT_SDB_BLOCK_END(LINE) \
2382 fprintf (asm_out_file, \
2383 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2385 (TARGET_GAS) ? "" : "#", \
2388 sdb_label_count++; \
2391 #define PUT_SDB_FUNCTION_START(LINE)
2393 #define PUT_SDB_FUNCTION_END(LINE)
2395 #define PUT_SDB_EPILOGUE_END(NAME)
2397 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2398 mips-tdump.c to print them out.
2400 These must match the corresponding definitions in gdb/mipsread.c.
2401 Unfortunately, gcc and gdb do not currently share any directories. */
2403 #define CODE_MASK 0x8F300
2404 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2405 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2406 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2408 /* Override some mips-tfile definitions. */
2410 #define SHASH_SIZE 511
2411 #define THASH_SIZE 55
2413 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2415 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2417 /* The linker will stick __main into the .init section. */
2418 #define HAS_INIT_SECTION
2419 #define LD_INIT_SWITCH "-init"
2420 #define LD_FINI_SWITCH "-fini"
2422 /* The system headers under Alpha systems are generally C++-aware. */
2423 #define NO_IMPLICIT_EXTERN_C
2425 /* Prototypes for alpha.c functions used in the md file. */
2426 extern struct rtx_def *get_unaligned_address ();
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