1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
27 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
28 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
29 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
30 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
32 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
33 %(cpp_cpu) %(cpp_subtarget)"
35 #ifndef CPP_SUBTARGET_SPEC
36 #define CPP_SUBTARGET_SPEC ""
39 /* Set the spec to use for signed char. The default tests the above macro
40 but DEC's compiler can't handle the conditional in a "constant"
43 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
45 #define WORD_SWITCH_TAKES_ARG(STR) \
46 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
47 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
48 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
49 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
50 || !strcmp (STR, "isystem"))
52 /* Print subsidiary information on the compiler version in use. */
53 #define TARGET_VERSION
55 /* Run-time compilation parameters selecting different hardware subsets. */
57 /* Which processor to schedule for. The cpu attribute defines a list that
58 mirrors this list, so changes to alpha.md must be made at the same time. */
61 {PROCESSOR_EV4, /* 2106[46]{a,} */
62 PROCESSOR_EV5, /* 21164{a,pc,} */
63 PROCESSOR_EV6}; /* 21264 */
65 extern enum processor_type alpha_cpu;
67 enum alpha_trap_precision
69 ALPHA_TP_PROG, /* No precision (default). */
70 ALPHA_TP_FUNC, /* Trap contained within originating function. */
71 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
74 enum alpha_fp_rounding_mode
76 ALPHA_FPRM_NORM, /* Normal rounding mode. */
77 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
78 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
79 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
82 enum alpha_fp_trap_mode
84 ALPHA_FPTM_N, /* Normal trap mode. */
85 ALPHA_FPTM_U, /* Underflow traps enabled. */
86 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
87 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
90 extern int target_flags;
92 extern enum alpha_trap_precision alpha_tp;
93 extern enum alpha_fp_rounding_mode alpha_fprm;
94 extern enum alpha_fp_trap_mode alpha_fptm;
96 /* This means that floating-point support exists in the target implementation
97 of the Alpha architecture. This is usually the default. */
98 #define MASK_FP (1 << 0)
99 #define TARGET_FP (target_flags & MASK_FP)
101 /* This means that floating-point registers are allowed to be used. Note
102 that Alpha implementations without FP operations are required to
103 provide the FP registers. */
105 #define MASK_FPREGS (1 << 1)
106 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
108 /* This means that gas is used to process the assembler file. */
110 #define MASK_GAS (1 << 2)
111 #define TARGET_GAS (target_flags & MASK_GAS)
113 /* This means that we should mark procedures as IEEE conformant. */
115 #define MASK_IEEE_CONFORMANT (1 << 3)
116 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
118 /* This means we should be IEEE-compliant except for inexact. */
120 #define MASK_IEEE (1 << 4)
121 #define TARGET_IEEE (target_flags & MASK_IEEE)
123 /* This means we should be fully IEEE-compliant. */
125 #define MASK_IEEE_WITH_INEXACT (1 << 5)
126 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
128 /* This means we must construct all constants rather than emitting
129 them as literal data. */
131 #define MASK_BUILD_CONSTANTS (1 << 6)
132 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
134 /* This means we handle floating points in VAX F- (float)
135 or G- (double) Format. */
137 #define MASK_FLOAT_VAX (1 << 7)
138 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
140 /* This means that the processor has byte and half word loads and stores
141 (the BWX extension). */
143 #define MASK_BWX (1 << 8)
144 #define TARGET_BWX (target_flags & MASK_BWX)
146 /* This means that the processor has the MAX extension. */
147 #define MASK_MAX (1 << 9)
148 #define TARGET_MAX (target_flags & MASK_MAX)
150 /* This means that the processor has the FIX extension. */
151 #define MASK_FIX (1 << 10)
152 #define TARGET_FIX (target_flags & MASK_FIX)
154 /* This means that the processor has the CIX extension. */
155 #define MASK_CIX (1 << 11)
156 #define TARGET_CIX (target_flags & MASK_CIX)
158 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
159 only in TARGET_CPU_DEFAULT. */
160 #define MASK_CPU_EV5 (1 << 28)
162 /* Likewise for EV6. */
163 #define MASK_CPU_EV6 (1 << 29)
165 /* This means we support the .arch directive in the assembler. Only
166 defined in TARGET_CPU_DEFAULT. */
167 #define MASK_SUPPORT_ARCH (1 << 30)
168 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
170 /* These are for target os support and cannot be changed at runtime. */
171 #ifndef TARGET_WINDOWS_NT
172 #define TARGET_WINDOWS_NT 0
174 #ifndef TARGET_OPEN_VMS
175 #define TARGET_OPEN_VMS 0
178 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
179 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
181 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
182 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
185 /* Macro to define tables used to set the flags.
186 This is a list in braces of pairs in braces,
187 each pair being { "NAME", VALUE }
188 where VALUE is the bits to set or minus the bits to clear.
189 An empty string NAME is used to identify the default VALUE. */
191 #define TARGET_SWITCHES \
192 { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
193 {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
194 {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
195 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
196 {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
197 {"gas", MASK_GAS, "Assume GAS"}, \
198 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
199 "Request IEEE-conformant math library routines (OSF/1)"}, \
200 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
201 "Emit IEEE-conformant code, without inexact exceptions"}, \
202 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
203 "Emit IEEE-conformant code, with inexact exceptions"}, \
204 {"build-constants", MASK_BUILD_CONSTANTS, \
205 "Do not emit complex integer constants to read-only memory"}, \
206 {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
207 {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
208 {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
209 {"no-bwx", -MASK_BWX, ""}, \
210 {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
211 {"no-max", -MASK_MAX, ""}, \
212 {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
213 {"no-fix", -MASK_FIX, ""}, \
214 {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
215 {"no-cix", -MASK_CIX, ""}, \
216 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
218 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
220 #ifndef TARGET_CPU_DEFAULT
221 #define TARGET_CPU_DEFAULT 0
224 /* This macro is similar to `TARGET_SWITCHES' but defines names of
225 command options that have values. Its definition is an initializer
226 with a subgrouping for each command option.
228 Each subgrouping contains a string constant, that defines the fixed
229 part of the option name, and the address of a variable. The
230 variable, type `char *', is set to the variable part of the given
231 option if the fixed part matches. The actual option name is made
232 by appending `-m' to the specified name.
234 Here is an example which defines `-mshort-data-NUMBER'. If the
235 given option is `-mshort-data-512', the variable `m88k_short_data'
236 will be set to the string `"512"'.
238 extern char *m88k_short_data;
239 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
241 extern const char *alpha_cpu_string; /* For -mcpu= */
242 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
243 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
244 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
245 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
247 #define TARGET_OPTIONS \
249 {"cpu=", &alpha_cpu_string, \
250 "Generate code for a given CPU"}, \
251 {"fp-rounding-mode=", &alpha_fprm_string, \
252 "Control the generated fp rounding mode"}, \
253 {"fp-trap-mode=", &alpha_fptm_string, \
254 "Control the IEEE trap mode"}, \
255 {"trap-precision=", &alpha_tp_string, \
256 "Control the precision given to fp exceptions"}, \
257 {"memory-latency=", &alpha_mlat_string, \
258 "Tune expected memory latency"}, \
261 /* Attempt to describe CPU characteristics to the preprocessor. */
263 /* Corresponding to amask... */
264 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
265 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
266 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
267 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
269 /* Corresponding to implver... */
270 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
271 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
272 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
274 /* Common combinations. */
275 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
276 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
277 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
278 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
279 #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
281 #ifndef CPP_CPU_DEFAULT_SPEC
282 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
283 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
285 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
286 # if TARGET_CPU_DEFAULT & MASK_MAX
287 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
289 # if TARGET_CPU_DEFAULT & MASK_BWX
290 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
292 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
296 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
299 #endif /* CPP_CPU_DEFAULT_SPEC */
302 #define CPP_CPU_SPEC "\
303 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
304 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
305 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
306 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
307 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
308 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
309 %{!mcpu*:%(cpp_cpu_default) }}"
312 /* This macro defines names of additional specifications to put in the
313 specs that can be used in various specifications like CC1_SPEC. Its
314 definition is an initializer with a subgrouping for each command option.
316 Each subgrouping contains a string constant, that defines the
317 specification name, and a string constant that used by the GNU CC driver
320 Do not define this macro if it does not need to do anything. */
322 #ifndef SUBTARGET_EXTRA_SPECS
323 #define SUBTARGET_EXTRA_SPECS
326 #define EXTRA_SPECS \
327 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
328 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
329 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
330 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
331 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
332 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
333 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
334 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
335 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
336 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
337 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
338 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
339 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
340 { "cpp_cpu", CPP_CPU_SPEC }, \
341 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
342 SUBTARGET_EXTRA_SPECS
345 /* Sometimes certain combinations of command options do not make sense
346 on a particular target machine. You can define a macro
347 `OVERRIDE_OPTIONS' to take account of this. This macro, if
348 defined, is executed once just after all the command options have
351 On the Alpha, it is used to translate target-option strings into
354 extern void override_options ();
355 #define OVERRIDE_OPTIONS override_options ()
358 /* Define this macro to change register usage conditional on target flags.
360 On the Alpha, we use this to disable the floating-point registers when
363 #define CONDITIONAL_REGISTER_USAGE \
364 if (! TARGET_FPREGS) \
365 for (i = 32; i < 63; i++) \
366 fixed_regs[i] = call_used_regs[i] = 1;
368 /* Show we can debug even without a frame pointer. */
369 #define CAN_DEBUG_WITHOUT_FP
371 /* target machine storage layout */
373 /* Define to enable software floating point emulation. */
374 #define REAL_ARITHMETIC
376 /* The following #defines are used when compiling the routines in
377 libgcc1.c. Since the Alpha calling conventions require single
378 precision floats to be passed in the floating-point registers
379 (rather than in the general registers) we have to build the
380 libgcc1.c routines in such a way that they know the actual types
381 of their formal arguments and the actual types of their return
382 values. Otherwise, gcc will generate calls to the libgcc1.c
383 routines, passing arguments in the floating-point registers,
384 but the libgcc1.c routines will expect their arguments on the
385 stack (where the Alpha calling conventions require structs &
386 unions to be passed). */
388 #define FLOAT_VALUE_TYPE double
389 #define INTIFY(FLOATVAL) (FLOATVAL)
390 #define FLOATIFY(INTVAL) (INTVAL)
391 #define FLOAT_ARG_TYPE double
393 /* Define the size of `int'. The default is the same as the word size. */
394 #define INT_TYPE_SIZE 32
396 /* Define the size of `long long'. The default is the twice the word size. */
397 #define LONG_LONG_TYPE_SIZE 64
399 /* The two floating-point formats we support are S-floating, which is
400 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
401 and `long double' are T. */
403 #define FLOAT_TYPE_SIZE 32
404 #define DOUBLE_TYPE_SIZE 64
405 #define LONG_DOUBLE_TYPE_SIZE 64
407 #define WCHAR_TYPE "unsigned int"
408 #define WCHAR_TYPE_SIZE 32
410 /* Define this macro if it is advisable to hold scalars in registers
411 in a wider mode than that declared by the program. In such cases,
412 the value is constrained to be within the bounds of the declared
413 type, but kept valid in the wider mode. The signedness of the
414 extension may differ from that of the type.
416 For Alpha, we always store objects in a full register. 32-bit objects
417 are always sign-extended, but smaller objects retain their signedness. */
419 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
420 if (GET_MODE_CLASS (MODE) == MODE_INT \
421 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
423 if ((MODE) == SImode) \
428 /* Define this if function arguments should also be promoted using the above
431 #define PROMOTE_FUNCTION_ARGS
433 /* Likewise, if the function return value is promoted. */
435 #define PROMOTE_FUNCTION_RETURN
437 /* Define this if most significant bit is lowest numbered
438 in instructions that operate on numbered bit-fields.
440 There are no such instructions on the Alpha, but the documentation
442 #define BITS_BIG_ENDIAN 0
444 /* Define this if most significant byte of a word is the lowest numbered.
445 This is false on the Alpha. */
446 #define BYTES_BIG_ENDIAN 0
448 /* Define this if most significant word of a multiword number is lowest
451 For Alpha we can decide arbitrarily since there are no machine instructions
452 for them. Might as well be consistent with bytes. */
453 #define WORDS_BIG_ENDIAN 0
455 /* number of bits in an addressable storage unit */
456 #define BITS_PER_UNIT 8
458 /* Width in bits of a "word", which is the contents of a machine register.
459 Note that this is not necessarily the width of data type `int';
460 if using 16-bit ints on a 68000, this would still be 32.
461 But on a machine with 16-bit registers, this would be 16. */
462 #define BITS_PER_WORD 64
464 /* Width of a word, in units (bytes). */
465 #define UNITS_PER_WORD 8
467 /* Width in bits of a pointer.
468 See also the macro `Pmode' defined below. */
469 #define POINTER_SIZE 64
471 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
472 #define PARM_BOUNDARY 64
474 /* Boundary (in *bits*) on which stack pointer should be aligned. */
475 #define STACK_BOUNDARY 64
477 /* Allocation boundary (in *bits*) for the code of a function. */
478 #define FUNCTION_BOUNDARY 256
480 /* Alignment of field after `int : 0' in a structure. */
481 #define EMPTY_FIELD_BOUNDARY 64
483 /* Every structure's size must be a multiple of this. */
484 #define STRUCTURE_SIZE_BOUNDARY 8
486 /* A bitfield declared as `int' forces `int' alignment for the struct. */
487 #define PCC_BITFIELD_TYPE_MATTERS 1
489 /* Align loop starts for optimal branching.
491 ??? Kludge this and the next macro for the moment by not doing anything if
492 we don't optimize and also if we are writing ECOFF symbols to work around
493 a bug in DEC's assembler. */
495 #define LOOP_ALIGN(LABEL) \
496 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
498 /* This is how to align an instruction for optimal branching. On
499 Alpha we'll get better performance by aligning on an octaword
502 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
503 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
505 /* No data type wants to be aligned rounder than this. */
506 #define BIGGEST_ALIGNMENT 64
508 /* For atomic access to objects, must have at least 32-bit alignment
509 unless the machine has byte operations. */
510 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
512 /* Align all constants and variables to at least a word boundary so
513 we can pick up pieces of them faster. */
514 /* ??? Only if block-move stuff knows about different source/destination
517 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
518 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
521 /* Set this non-zero if move instructions will actually fail to work
522 when given unaligned data.
524 Since we get an error message when we do one, call them invalid. */
526 #define STRICT_ALIGNMENT 1
528 /* Set this non-zero if unaligned move instructions are extremely slow.
530 On the Alpha, they trap. */
532 #define SLOW_UNALIGNED_ACCESS 1
534 /* Standard register usage. */
536 /* Number of actual hardware registers.
537 The hardware registers are assigned numbers for the compiler
538 from 0 to just below FIRST_PSEUDO_REGISTER.
539 All registers that the compiler knows about must be given numbers,
540 even those that are not normally considered general registers.
542 We define all 32 integer registers, even though $31 is always zero,
543 and all 32 floating-point registers, even though $f31 is also
544 always zero. We do not bother defining the FP status register and
545 there are no other registers.
547 Since $31 is always zero, we will use register number 31 as the
548 argument pointer. It will never appear in the generated code
549 because we will always be eliminating it in favor of the stack
550 pointer or hardware frame pointer.
552 Likewise, we use $f31 for the frame pointer, which will always
553 be eliminated in favor of the hardware frame pointer or the
556 #define FIRST_PSEUDO_REGISTER 64
558 /* 1 for registers that have pervasive standard uses
559 and are not available for the register allocator. */
561 #define FIXED_REGISTERS \
562 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
567 /* 1 for registers not available across function calls.
568 These must include the FIXED_REGISTERS and also any
569 registers that can be used without being saved.
570 The latter must include the registers where values are returned
571 and the register where structure-value addresses are passed.
572 Aside from that, you can include as many other registers as you like. */
573 #define CALL_USED_REGISTERS \
574 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
576 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
579 /* List the order in which to allocate registers. Each register must be
580 listed once, even those in FIXED_REGISTERS.
582 We allocate in the following order:
583 $f10-$f15 (nonsaved floating-point register)
585 $f21-$f16 (likewise, but input args)
586 $f0 (nonsaved, but return value)
587 $f1 (nonsaved, but immediate before saved)
588 $f2-$f9 (saved floating-point registers)
589 $1-$8 (nonsaved integer registers)
592 $0 (likewise, but return value)
593 $21-$16 (likewise, but input args)
594 $27 (procedure value in OSF, nonsaved in NT)
595 $9-$14 (saved integer registers)
599 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
601 #define REG_ALLOC_ORDER \
602 {42, 43, 44, 45, 46, 47, \
603 54, 55, 56, 57, 58, 59, 60, 61, 62, \
604 53, 52, 51, 50, 49, 48, \
606 34, 35, 36, 37, 38, 39, 40, 41, \
607 1, 2, 3, 4, 5, 6, 7, 8, \
611 21, 20, 19, 18, 17, 16, \
613 9, 10, 11, 12, 13, 14, \
619 /* Return number of consecutive hard regs needed starting at reg REGNO
620 to hold something of mode MODE.
621 This is ordinarily the length in words of a value of mode MODE
622 but can be less for certain modes in special long registers. */
624 #define HARD_REGNO_NREGS(REGNO, MODE) \
625 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
627 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
628 On Alpha, the integer registers can hold any mode. The floating-point
629 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
632 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
633 ((REGNO) >= 32 && (REGNO) <= 62 \
634 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
637 /* A C expression that is nonzero if a value of mode
638 MODE1 is accessible in mode MODE2 without copying.
640 This asymmetric test is true when MODE1 could be put
641 in an FP register but MODE2 could not. */
643 #define MODES_TIEABLE_P(MODE1, MODE2) \
644 (HARD_REGNO_MODE_OK (32, (MODE1)) \
645 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
648 /* Specify the registers used for certain standard purposes.
649 The values of these macros are register numbers. */
651 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
652 /* #define PC_REGNUM */
654 /* Register to use for pushing function arguments. */
655 #define STACK_POINTER_REGNUM 30
657 /* Base register for access to local variables of the function. */
658 #define HARD_FRAME_POINTER_REGNUM 15
660 /* Value should be nonzero if functions must have frame pointers.
661 Zero means the frame pointer need not be set up (and parms
662 may be accessed via the stack pointer) in functions that seem suitable.
663 This is computed in `reload', in reload1.c. */
664 #define FRAME_POINTER_REQUIRED 0
666 /* Base register for access to arguments of the function. */
667 #define ARG_POINTER_REGNUM 31
669 /* Base register for access to local variables of function. */
670 #define FRAME_POINTER_REGNUM 63
672 /* Register in which static-chain is passed to a function.
674 For the Alpha, this is based on an example; the calling sequence
675 doesn't seem to specify this. */
676 #define STATIC_CHAIN_REGNUM 1
678 /* Register in which address to store a structure value
679 arrives in the function. On the Alpha, the address is passed
680 as a hidden argument. */
681 #define STRUCT_VALUE 0
683 /* Define the classes of registers for register constraints in the
684 machine description. Also define ranges of constants.
686 One of the classes must always be named ALL_REGS and include all hard regs.
687 If there is more than one class, another class must be named NO_REGS
688 and contain no registers.
690 The name GENERAL_REGS must be the name of a class (or an alias for
691 another name such as ALL_REGS). This is the class of registers
692 that is allowed by "g" or "r" in a register constraint.
693 Also, registers outside this class are allocated only when
694 instructions express preferences for them.
696 The classes must be numbered in nondecreasing order; that is,
697 a larger-numbered class must never be contained completely
698 in a smaller-numbered class.
700 For any two classes, it is very desirable that there be another
701 class that represents their union. */
703 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
706 #define N_REG_CLASSES (int) LIM_REG_CLASSES
708 /* Give names of register classes as strings for dump file. */
710 #define REG_CLASS_NAMES \
711 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
713 /* Define which registers fit in which classes.
714 This is an initializer for a vector of HARD_REG_SET
715 of length N_REG_CLASSES. */
717 #define REG_CLASS_CONTENTS \
718 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
720 /* The same information, inverted:
721 Return the class number of the smallest class containing
722 reg number REGNO. This could be a conditional expression
723 or could index an array. */
725 #define REGNO_REG_CLASS(REGNO) \
726 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
728 /* The class value for index registers, and the one for base regs. */
729 #define INDEX_REG_CLASS NO_REGS
730 #define BASE_REG_CLASS GENERAL_REGS
732 /* Get reg_class from a letter such as appears in the machine description. */
734 #define REG_CLASS_FROM_LETTER(C) \
735 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
737 /* Define this macro to change register usage conditional on target flags. */
738 /* #define CONDITIONAL_REGISTER_USAGE */
740 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
741 can be used to stand for particular ranges of immediate operands.
742 This macro defines what the ranges are.
743 C is the letter, and VALUE is a constant value.
744 Return 1 if VALUE is in the range specified by C.
747 `I' is used for the range of constants most insns can contain.
748 `J' is the constant zero.
749 `K' is used for the constant in an LDA insn.
750 `L' is used for the constant in a LDAH insn.
751 `M' is used for the constants that can be AND'ed with using a ZAP insn.
752 `N' is used for complemented 8-bit constants.
753 `O' is used for negated 8-bit constants.
754 `P' is used for the constants 1, 2 and 3. */
756 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
757 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
758 : (C) == 'J' ? (VALUE) == 0 \
759 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
760 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
761 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
762 : (C) == 'M' ? zap_mask (VALUE) \
763 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
764 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
765 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
768 /* Similar, but for floating or large integer constants, and defining letters
769 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
771 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
772 that is the operand of a ZAP insn. */
774 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
775 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
776 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
777 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
778 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
779 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
782 /* Optional extra constraints for this machine.
784 For the Alpha, `Q' means that this is a memory operand but not a
785 reference to an unaligned location.
787 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
790 'S' is a 6-bit constant (valid for a shift insn). */
792 #define EXTRA_CONSTRAINT(OP, C) \
793 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
794 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
795 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
796 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
798 extern int normal_memory_operand ();
800 /* Given an rtx X being reloaded into a reg required to be
801 in class CLASS, return the class of reg to actually use.
802 In general this is just CLASS; but on some machines
803 in some cases it is preferable to use a more restrictive class.
805 On the Alpha, all constants except zero go into a floating-point
806 register via memory. */
808 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
809 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
810 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
813 /* Loading and storing HImode or QImode values to and from memory
814 usually requires a scratch register. The exceptions are loading
815 QImode and HImode from an aligned address to a general register
816 unless byte instructions are permitted.
817 We also cannot load an unaligned address or a paradoxical SUBREG into an
820 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
821 (((GET_CODE (IN) == MEM \
822 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
823 || (GET_CODE (IN) == SUBREG \
824 && (GET_CODE (SUBREG_REG (IN)) == MEM \
825 || (GET_CODE (SUBREG_REG (IN)) == REG \
826 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
827 && (((CLASS) == FLOAT_REGS \
828 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
829 || (((MODE) == QImode || (MODE) == HImode) \
830 && ! TARGET_BWX && ! aligned_memory_operand (IN, MODE)))) \
832 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
833 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
834 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
835 && (GET_MODE_SIZE (GET_MODE (IN)) \
836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
839 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
840 (((GET_CODE (OUT) == MEM \
841 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
842 || (GET_CODE (OUT) == SUBREG \
843 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
844 || (GET_CODE (SUBREG_REG (OUT)) == REG \
845 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
846 && ((((MODE) == HImode || (MODE) == QImode) \
847 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
848 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
850 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
851 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
852 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
853 && (GET_MODE_SIZE (GET_MODE (OUT)) \
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
857 /* If we are copying between general and FP registers, we need a memory
858 location unless the FIX extension is available. */
860 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
861 (! TARGET_FIX && (CLASS1) != (CLASS2))
863 /* Specify the mode to be used for memory when a secondary memory
864 location is needed. If MODE is floating-point, use it. Otherwise,
865 widen to a word like the default. This is needed because we always
866 store integers in FP registers in quadword format. This whole
867 area is very tricky! */
868 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
869 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
870 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
871 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
873 /* Return the maximum number of consecutive registers
874 needed to represent mode MODE in a register of class CLASS. */
876 #define CLASS_MAX_NREGS(CLASS, MODE) \
877 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
879 /* If defined, gives a class of registers that cannot be used as the
880 operand of a SUBREG that changes the size of the object. */
882 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
884 /* Define the cost of moving between registers of various classes. Moving
885 between FLOAT_REGS and anything else except float regs is expensive.
886 In fact, we make it quite expensive because we really don't want to
887 do these moves unless it is clearly worth it. Optimizations may
888 reduce the impact of not being able to allocate a pseudo to a
891 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
892 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
894 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
896 /* A C expressions returning the cost of moving data of MODE from a register to
899 On the Alpha, bump this up a bit. */
901 extern int alpha_memory_latency;
902 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
904 /* Provide the cost of a branch. Exact meaning under development. */
905 #define BRANCH_COST 5
907 /* Adjust the cost of dependencies. */
909 #define ADJUST_COST(INSN,LINK,DEP,COST) \
910 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
912 /* Stack layout; function entry, exit and calling. */
914 /* Define this if pushing a word on the stack
915 makes the stack pointer a smaller address. */
916 #define STACK_GROWS_DOWNWARD
918 /* Define this if the nominal address of the stack frame
919 is at the high-address end of the local variables;
920 that is, each additional local variable allocated
921 goes at a more negative offset in the frame. */
922 /* #define FRAME_GROWS_DOWNWARD */
924 /* Offset within stack frame to start allocating local variables at.
925 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
926 first local allocated. Otherwise, it is the offset to the BEGINNING
927 of the first local allocated. */
929 #define STARTING_FRAME_OFFSET 0
931 /* If we generate an insn to push BYTES bytes,
932 this says how many the stack pointer really advances by.
933 On Alpha, don't define this because there are no push insns. */
934 /* #define PUSH_ROUNDING(BYTES) */
936 /* Define this to be nonzero if stack checking is built into the ABI. */
937 #define STACK_CHECK_BUILTIN 1
939 /* Define this if the maximum size of all the outgoing args is to be
940 accumulated and pushed during the prologue. The amount can be
941 found in the variable current_function_outgoing_args_size. */
942 #define ACCUMULATE_OUTGOING_ARGS
944 /* Offset of first parameter from the argument pointer register value. */
946 #define FIRST_PARM_OFFSET(FNDECL) 0
948 /* Definitions for register eliminations.
950 We have two registers that can be eliminated on the Alpha. First, the
951 frame pointer register can often be eliminated in favor of the stack
952 pointer register. Secondly, the argument pointer register can always be
953 eliminated; it is replaced with either the stack or frame pointer. */
955 /* This is an array of structures. Each structure initializes one pair
956 of eliminable registers. The "from" register number is given first,
957 followed by "to". Eliminations of the same "from" register are listed
958 in order of preference. */
960 #define ELIMINABLE_REGS \
961 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
962 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
963 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
964 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
966 /* Given FROM and TO register numbers, say whether this elimination is allowed.
967 Frame pointer elimination is automatically handled.
969 All eliminations are valid since the cases where FP can't be
970 eliminated are already handled. */
972 #define CAN_ELIMINATE(FROM, TO) 1
974 /* Round up to a multiple of 16 bytes. */
975 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
977 /* Define the offset between two registers, one to be eliminated, and the other
978 its replacement, at the start of a routine. */
979 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
980 { if ((FROM) == FRAME_POINTER_REGNUM) \
981 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
982 + alpha_sa_size ()); \
983 else if ((FROM) == ARG_POINTER_REGNUM) \
984 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
986 + (ALPHA_ROUND (get_frame_size () \
987 + current_function_pretend_args_size) \
988 - current_function_pretend_args_size)); \
991 /* Define this if stack space is still allocated for a parameter passed
993 /* #define REG_PARM_STACK_SPACE */
995 /* Value is the number of bytes of arguments automatically
996 popped when returning from a subroutine call.
997 FUNDECL is the declaration node of the function (as a tree),
998 FUNTYPE is the data type of the function (as a tree),
999 or for a library call it is an identifier node for the subroutine name.
1000 SIZE is the number of bytes of arguments passed on the stack. */
1002 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1004 /* Define how to find the value returned by a function.
1005 VALTYPE is the data type of the value (as a tree).
1006 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1007 otherwise, FUNC is 0.
1009 On Alpha the value is found in $0 for integer functions and
1010 $f0 for floating-point functions. */
1012 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1013 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
1014 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1015 || POINTER_TYPE_P (VALTYPE)) \
1016 ? word_mode : TYPE_MODE (VALTYPE), \
1018 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1019 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1022 /* Define how to find the value returned by a library function
1023 assuming the value has mode MODE. */
1025 #define LIBCALL_VALUE(MODE) \
1026 gen_rtx_REG (MODE, \
1028 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1029 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1032 /* The definition of this macro implies that there are cases where
1033 a scalar value cannot be returned in registers.
1035 For the Alpha, any structure or union type is returned in memory, as
1036 are integers whose size is larger than 64 bits. */
1038 #define RETURN_IN_MEMORY(TYPE) \
1039 (TYPE_MODE (TYPE) == BLKmode \
1040 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1042 /* 1 if N is a possible register number for a function value
1043 as seen by the caller. */
1045 #define FUNCTION_VALUE_REGNO_P(N) \
1046 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1048 /* 1 if N is a possible register number for function argument passing.
1049 On Alpha, these are $16-$21 and $f16-$f21. */
1051 #define FUNCTION_ARG_REGNO_P(N) \
1052 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1054 /* Define a data type for recording info about an argument list
1055 during the scan of that argument list. This data type should
1056 hold all necessary information about the function itself
1057 and about the args processed so far, enough to enable macros
1058 such as FUNCTION_ARG to determine where the next arg should go.
1060 On Alpha, this is a single integer, which is a number of words
1061 of arguments scanned so far.
1062 Thus 6 or more means all following args should go on the stack. */
1064 #define CUMULATIVE_ARGS int
1066 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1067 for a call to a function whose data type is FNTYPE.
1068 For a library call, FNTYPE is 0. */
1070 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1072 /* Define intermediate macro to compute the size (in registers) of an argument
1075 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1076 ((MODE) != BLKmode \
1077 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1078 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1080 /* Update the data in CUM to advance over an argument
1081 of mode MODE and data type TYPE.
1082 (TYPE is null for libcalls where that information may not be available.) */
1084 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1085 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1088 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1090 /* Determine where to put an argument to a function.
1091 Value is zero to push the argument on the stack,
1092 or a hard register in which to store the argument.
1094 MODE is the argument's machine mode.
1095 TYPE is the data type of the argument (as a tree).
1096 This is null for libcalls where that information may
1098 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1099 the preceding args and about the function being called.
1100 NAMED is nonzero if this argument is a named parameter
1101 (otherwise it is an extra parameter matching an ellipsis).
1103 On Alpha the first 6 words of args are normally in registers
1104 and the rest are pushed. */
1106 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1107 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
1108 ? gen_rtx_REG ((MODE), \
1111 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1112 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1116 /* Specify the padding direction of arguments.
1118 On the Alpha, we must pad upwards in order to be able to pass args in
1121 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1123 /* For an arg passed partly in registers and partly in memory,
1124 this is the number of registers used.
1125 For args passed entirely in registers or entirely in memory, zero. */
1127 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1128 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1131 /* Perform any needed actions needed for a function that is receiving a
1132 variable number of arguments.
1136 MODE and TYPE are the mode and type of the current parameter.
1138 PRETEND_SIZE is a variable that should be set to the amount of stack
1139 that must be pushed by the prolog to pretend that our caller pushed
1142 Normally, this macro will push all remaining incoming registers on the
1143 stack and set PRETEND_SIZE to the length of the registers pushed.
1145 On the Alpha, we allocate space for all 12 arg registers, but only
1146 push those that are remaining.
1148 However, if NO registers need to be saved, don't allocate any space.
1149 This is not only because we won't need the space, but because AP includes
1150 the current_pretend_args_size and we don't want to mess up any
1151 ap-relative addresses already made.
1153 If we are not to use the floating-point registers, save the integer
1154 registers where we would put the floating-point registers. This is
1155 not the most efficient way to implement varargs with just one register
1156 class, but it isn't worth doing anything more efficient in this rare
1160 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1165 rtx tmp; int set = get_varargs_alias_set (); \
1166 tmp = gen_rtx_MEM (BLKmode, \
1167 plus_constant (virtual_incoming_args_rtx, \
1168 ((CUM) + 6)* UNITS_PER_WORD)); \
1169 MEM_ALIAS_SET (tmp) = set; \
1170 move_block_from_reg \
1172 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1174 tmp = gen_rtx_MEM (BLKmode, \
1175 plus_constant (virtual_incoming_args_rtx, \
1176 (CUM) * UNITS_PER_WORD)); \
1177 MEM_ALIAS_SET (tmp) = set; \
1178 move_block_from_reg \
1179 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1180 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1182 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1186 /* Try to output insns to set TARGET equal to the constant C if it can be
1187 done in less than N insns. Do all computations in MODE. Returns the place
1188 where the output has been placed if it can be done and the insns have been
1189 emitted. If it would take more than N insns, zero is returned and no
1190 insns and emitted. */
1191 extern struct rtx_def *alpha_emit_set_const ();
1192 extern struct rtx_def *alpha_emit_set_long_const ();
1193 extern struct rtx_def *alpha_emit_conditional_branch ();
1194 extern struct rtx_def *alpha_emit_conditional_move ();
1196 /* Define the information needed to generate branch and scc insns. This is
1197 stored from the compare operation. Note that we can't use "rtx" here
1198 since it hasn't been defined! */
1200 struct alpha_compare
1202 struct rtx_def *op0, *op1;
1206 extern struct alpha_compare alpha_compare;
1208 /* Machine specific function data. */
1210 struct machine_function
1212 /* An offset to apply to the stack pointer when unwinding from EH. */
1213 struct rtx_def *eh_epilogue_sp_ofs;
1215 /* If non-null, this rtx holds the return address for the function. */
1216 struct rtx_def *ra_rtx;
1219 /* Make (or fake) .linkage entry for function call.
1220 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1221 extern void alpha_need_linkage ();
1223 /* This macro defines the start of an assembly comment. */
1225 #define ASM_COMMENT_START " #"
1227 /* This macro produces the initial definition of a function. */
1229 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1230 alpha_start_function(FILE,NAME,DECL);
1231 extern void alpha_start_function ();
1233 /* This macro closes up a function definition for the assembler. */
1235 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1236 alpha_end_function(FILE,NAME,DECL)
1237 extern void alpha_end_function ();
1239 /* This macro notes the end of the prologue. */
1241 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1242 extern void output_end_prologue ();
1244 /* Output any profiling code before the prologue. */
1246 #define PROFILE_BEFORE_PROLOGUE 1
1248 /* Output assembler code to FILE to increment profiler label # LABELNO
1249 for profiling a function entry. Under OSF/1, profiling is enabled
1250 by simply passing -pg to the assembler and linker. */
1252 #define FUNCTION_PROFILER(FILE, LABELNO)
1254 /* Output assembler code to FILE to initialize this source file's
1255 basic block profiling info, if that has not already been done.
1256 This assumes that __bb_init_func doesn't garble a1-a5. */
1258 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1260 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1261 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1262 fputs ("\tldq $26,0($16)\n", (FILE)); \
1263 fputs ("\tbne $26,1f\n", (FILE)); \
1264 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1265 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1266 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1267 fputs ("1:\n", (FILE)); \
1268 ASM_OUTPUT_REG_POP (FILE, 16); \
1271 /* Output assembler code to FILE to increment the entry-count for
1272 the BLOCKNO'th basic block in this source file. */
1274 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1276 int blockn = (BLOCKNO); \
1277 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1278 fputs ("\tstq $26,0($30)\n", (FILE)); \
1279 fputs ("\tstq $27,8($30)\n", (FILE)); \
1280 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1281 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1282 fputs ("\taddq $27,1,$27\n", (FILE)); \
1283 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1284 fputs ("\tldq $26,0($30)\n", (FILE)); \
1285 fputs ("\tldq $27,8($30)\n", (FILE)); \
1286 fputs ("\taddq $30,16,$30\n", (FILE)); \
1290 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1291 the stack pointer does not matter. The value is tested only in
1292 functions that have frame pointers.
1293 No definition is equivalent to always zero. */
1295 #define EXIT_IGNORE_STACK 1
1297 /* Output assembler code for a block containing the constant parts
1298 of a trampoline, leaving space for the variable parts.
1300 The trampoline should set the static chain pointer to value placed
1301 into the trampoline and should branch to the specified routine.
1302 Note that $27 has been set to the address of the trampoline, so we can
1303 use it for addressability of the two data items. Trampolines are always
1304 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1306 #define TRAMPOLINE_TEMPLATE(FILE) \
1308 fprintf (FILE, "\tldq $1,24($27)\n"); \
1309 fprintf (FILE, "\tldq $27,16($27)\n"); \
1310 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1311 fprintf (FILE, "\tnop\n"); \
1312 fprintf (FILE, "\t.quad 0,0\n"); \
1315 /* Section in which to place the trampoline. On Alpha, instructions
1316 may only be placed in a text segment. */
1318 #define TRAMPOLINE_SECTION text_section
1320 /* Length in units of the trampoline for entering a nested function. */
1322 #define TRAMPOLINE_SIZE 32
1324 /* Emit RTL insns to initialize the variable parts of a trampoline.
1325 FNADDR is an RTX for the address of the function's pure code.
1326 CXT is an RTX for the static chain value for the function. */
1328 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1329 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1330 extern void alpha_initialize_trampoline ();
1332 /* A C expression whose value is RTL representing the value of the return
1333 address for the frame COUNT steps up from the current frame.
1334 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1335 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1337 #define RETURN_ADDR_RTX alpha_return_addr
1338 extern struct rtx_def *alpha_return_addr ();
1340 /* Before the prologue, RA lives in $26. */
1341 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1343 /* Addressing modes, and classification of registers for them. */
1345 /* #define HAVE_POST_INCREMENT 0 */
1346 /* #define HAVE_POST_DECREMENT 0 */
1348 /* #define HAVE_PRE_DECREMENT 0 */
1349 /* #define HAVE_PRE_INCREMENT 0 */
1351 /* Macros to check register numbers against specific register classes. */
1353 /* These assume that REGNO is a hard or pseudo reg number.
1354 They give nonzero only if REGNO is a hard reg of the suitable class
1355 or a pseudo reg currently allocated to a suitable hard reg.
1356 Since they use reg_renumber, they are safe only once reg_renumber
1357 has been allocated, which happens in local-alloc.c. */
1359 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1360 #define REGNO_OK_FOR_BASE_P(REGNO) \
1361 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1362 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1364 /* Maximum number of registers that can appear in a valid memory address. */
1365 #define MAX_REGS_PER_ADDRESS 1
1367 /* Recognize any constant value that is a valid address. For the Alpha,
1368 there are only constants none since we want to use LDA to load any
1369 symbolic addresses into registers. */
1371 #define CONSTANT_ADDRESS_P(X) \
1372 (GET_CODE (X) == CONST_INT \
1373 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1375 /* Include all constant integers and constant doubles, but not
1376 floating-point, except for floating-point zero. */
1378 #define LEGITIMATE_CONSTANT_P(X) \
1379 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1380 || (X) == CONST0_RTX (GET_MODE (X)))
1382 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1383 and check its validity for a certain class.
1384 We have two alternate definitions for each of them.
1385 The usual definition accepts all pseudo regs; the other rejects
1386 them unless they have been allocated suitable hard regs.
1387 The symbol REG_OK_STRICT causes the latter definition to be used.
1389 Most source files want to accept pseudo regs in the hope that
1390 they will get allocated to the class that the insn wants them to be in.
1391 Source files for reload pass need to be strict.
1392 After reload, it makes no difference, since pseudo regs have
1393 been eliminated by then. */
1395 #ifndef REG_OK_STRICT
1397 /* Nonzero if X is a hard reg that can be used as an index
1398 or if it is a pseudo reg. */
1399 #define REG_OK_FOR_INDEX_P(X) 0
1401 /* Nonzero if X is a hard reg that can be used as a base reg
1402 or if it is a pseudo reg. */
1403 #define REG_OK_FOR_BASE_P(X) \
1404 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1406 /* ??? Nonzero if X is the frame pointer, or some virtual register
1407 that may eliminate to the frame pointer. These will be allowed to
1408 have offsets greater than 32K. This is done because register
1409 elimination offsets will change the hi/lo split, and if we split
1410 before reload, we will require additional instructions. */
1411 #define REG_OK_FP_BASE_P(X) \
1412 (REGNO (X) == 31 || REGNO (X) == 63 \
1413 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1414 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1418 /* Nonzero if X is a hard reg that can be used as an index. */
1419 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1421 /* Nonzero if X is a hard reg that can be used as a base reg. */
1422 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1424 #define REG_OK_FP_BASE_P(X) 0
1428 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1429 that is a valid memory address for an instruction.
1430 The MODE argument is the machine mode for the MEM expression
1431 that wants to use this address.
1433 For Alpha, we have either a constant address or the sum of a register
1434 and a constant address, or just a register. For DImode, any of those
1435 forms can be surrounded with an AND that clear the low-order three bits;
1436 this is an "unaligned" access.
1438 First define the basic valid address. */
1440 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1443 if (GET_CODE (tmp) == SUBREG \
1444 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1445 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1446 tmp = SUBREG_REG (tmp); \
1447 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1449 if (CONSTANT_ADDRESS_P (X)) \
1451 if (GET_CODE (X) == PLUS) \
1453 tmp = XEXP (X, 0); \
1454 if (GET_CODE (tmp) == SUBREG \
1455 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1456 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1457 tmp = SUBREG_REG (tmp); \
1460 if (REG_OK_FP_BASE_P (tmp) \
1461 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1463 if (REG_OK_FOR_BASE_P (tmp) \
1464 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1470 /* Now accept the simple address, or, for DImode only, an AND of a simple
1471 address that turns off the low three bits. */
1473 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1474 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1475 if ((MODE) == DImode \
1476 && GET_CODE (X) == AND \
1477 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1478 && INTVAL (XEXP (X, 1)) == -8) \
1479 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1482 /* Try machine-dependent ways of modifying an illegitimate address
1483 to be legitimate. If we find one, return the new, valid address.
1484 This macro is used in only one place: `memory_address' in explow.c.
1486 OLDX is the address as it was before break_out_memory_refs was called.
1487 In some cases it is useful to look at this to decide what needs to be done.
1489 MODE and WIN are passed so that this macro can use
1490 GO_IF_LEGITIMATE_ADDRESS.
1492 It is always safe for this macro to do nothing. It exists to recognize
1493 opportunities to optimize the output.
1495 For the Alpha, there are three cases we handle:
1497 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1498 valid offset, compute the high part of the constant and add it to the
1499 register. Then our address is (plus temp low-part-const).
1500 (2) If the address is (const (plus FOO const_int)), find the low-order
1501 part of the CONST_INT. Then load FOO plus any high-order part of the
1502 CONST_INT into a register. Our address is (plus reg low-part-const).
1503 This is done to reduce the number of GOT entries.
1504 (3) If we have a (plus reg const), emit the load as in (2), then add
1505 the two registers, and finally generate (plus reg low-part-const) as
1508 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1509 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1510 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1511 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1513 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1514 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1515 HOST_WIDE_INT highpart = val - lowpart; \
1516 rtx high = GEN_INT (highpart); \
1517 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1518 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1520 (X) = plus_constant (temp, lowpart); \
1523 else if (GET_CODE (X) == CONST \
1524 && GET_CODE (XEXP (X, 0)) == PLUS \
1525 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1527 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1528 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1529 HOST_WIDE_INT highpart = val - lowpart; \
1530 rtx high = XEXP (XEXP (X, 0), 0); \
1533 high = plus_constant (high, highpart); \
1535 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1538 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1539 && GET_CODE (XEXP (X, 1)) == CONST \
1540 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1541 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1543 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1544 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1545 HOST_WIDE_INT highpart = val - lowpart; \
1546 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1549 high = plus_constant (high, highpart); \
1551 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1552 force_reg (Pmode, high), \
1553 high, 1, OPTAB_LIB_WIDEN); \
1554 (X) = plus_constant (high, lowpart); \
1559 /* Try a machine-dependent way of reloading an illegitimate address
1560 operand. If we find one, push the reload and jump to WIN. This
1561 macro is used in only one place: `find_reloads_address' in reload.c.
1563 For the Alpha, we wish to handle large displacements off a base
1564 register by splitting the addend across an ldah and the mem insn.
1565 This cuts number of extra insns needed from 3 to 1. */
1567 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1569 /* We must recognize output that we have already generated ourselves. */ \
1570 if (GET_CODE (X) == PLUS \
1571 && GET_CODE (XEXP (X, 0)) == PLUS \
1572 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1573 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1574 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1576 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1577 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1581 if (GET_CODE (X) == PLUS \
1582 && GET_CODE (XEXP (X, 0)) == REG \
1583 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1584 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1585 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1587 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1588 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1589 HOST_WIDE_INT high \
1590 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1592 /* Check for 32-bit overflow. */ \
1593 if (high + low != val) \
1596 /* Reload the high part into a base reg; leave the low part \
1597 in the mem directly. */ \
1599 X = gen_rtx_PLUS (GET_MODE (X), \
1600 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1604 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1605 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1611 /* Go to LABEL if ADDR (a legitimate address expression)
1612 has an effect that depends on the machine mode it is used for.
1613 On the Alpha this is true only for the unaligned modes. We can
1614 simplify this test since we know that the address must be valid. */
1616 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1617 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1619 /* Compute the cost of an address. For the Alpha, all valid addresses are
1622 #define ADDRESS_COST(X) 0
1624 /* Machine-dependent reorg pass. */
1625 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1627 /* Specify the machine mode that this machine uses
1628 for the index in the tablejump instruction. */
1629 #define CASE_VECTOR_MODE SImode
1631 /* Define as C expression which evaluates to nonzero if the tablejump
1632 instruction expects the table to contain offsets from the address of the
1635 Do not define this if the table should contain absolute addresses.
1636 On the Alpha, the table is really GP-relative, not relative to the PC
1637 of the table, but we pretend that it is PC-relative; this should be OK,
1638 but we should try to find some better way sometime. */
1639 #define CASE_VECTOR_PC_RELATIVE 1
1641 /* Specify the tree operation to be used to convert reals to integers. */
1642 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1644 /* This is the kind of divide that is easiest to do in the general case. */
1645 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1647 /* Define this as 1 if `char' should by default be signed; else as 0. */
1648 #define DEFAULT_SIGNED_CHAR 1
1650 /* This flag, if defined, says the same insns that convert to a signed fixnum
1651 also convert validly to an unsigned one.
1653 We actually lie a bit here as overflow conditions are different. But
1654 they aren't being checked anyway. */
1656 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1658 /* Max number of bytes we can move to or from memory
1659 in one reasonably fast instruction. */
1663 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1664 move-instruction pairs, we will do a movstr or libcall instead.
1666 Without byte/word accesses, we want no more than four instructions;
1667 with, several single byte accesses are better. */
1669 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1671 /* Largest number of bytes of an object that can be placed in a register.
1672 On the Alpha we have plenty of registers, so use TImode. */
1673 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1675 /* Nonzero if access to memory by bytes is no faster than for words.
1676 Also non-zero if doing byte operations (specifically shifts) in registers
1679 On the Alpha, we want to not use the byte operation and instead use
1680 masking operations to access fields; these will save instructions. */
1682 #define SLOW_BYTE_ACCESS 1
1684 /* Define if operations between registers always perform the operation
1685 on the full register even if a narrower mode is specified. */
1686 #define WORD_REGISTER_OPERATIONS
1688 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1689 will either zero-extend or sign-extend. The value of this macro should
1690 be the code that says which one of the two operations is implicitly
1691 done, NIL if none. */
1692 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1694 /* Define if loading short immediate values into registers sign extends. */
1695 #define SHORT_IMMEDIATES_SIGN_EXTEND
1697 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1698 is done just by pretending it is already truncated. */
1699 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1701 /* We assume that the store-condition-codes instructions store 0 for false
1702 and some other value for true. This is the value stored for true. */
1704 #define STORE_FLAG_VALUE 1
1706 /* Define the value returned by a floating-point comparison instruction. */
1708 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1710 /* Canonicalize a comparison from one we don't have to one we do have. */
1712 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1714 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1715 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1720 (CODE) = swap_condition (CODE); \
1722 if (((CODE) == LT || (CODE) == LTU) \
1723 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1725 (CODE) = (CODE) == LT ? LE : LEU; \
1726 (OP1) = GEN_INT (255); \
1730 /* Specify the machine mode that pointers have.
1731 After generation of rtl, the compiler makes no further distinction
1732 between pointers and any other objects of this machine mode. */
1733 #define Pmode DImode
1735 /* Mode of a function address in a call instruction (for indexing purposes). */
1737 #define FUNCTION_MODE Pmode
1739 /* Define this if addresses of constant functions
1740 shouldn't be put through pseudo regs where they can be cse'd.
1741 Desirable on machines where ordinary constants are expensive
1742 but a CALL with constant address is cheap.
1744 We define this on the Alpha so that gen_call and gen_call_value
1745 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1746 then copy it into a register, thus actually letting the address be
1749 #define NO_FUNCTION_CSE
1751 /* Define this to be nonzero if shift instructions ignore all but the low-order
1753 #define SHIFT_COUNT_TRUNCATED 1
1755 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1756 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1758 /* Describe the fact that MULTI instructions are multiple instructions
1759 and so to assume they don't pair with anything. */
1760 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1761 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1762 (CAN_ISSUE_MORE) = 0
1764 /* Compute the cost of computing a constant rtl expression RTX
1765 whose rtx-code is CODE. The body of this macro is a portion
1766 of a switch statement. If the code is computed here,
1767 return it with a return statement. Otherwise, break from the switch.
1769 If this is an 8-bit constant, return zero since it can be used
1770 nearly anywhere with no cost. If it is a valid operand for an
1771 ADD or AND, likewise return 0 if we know it will be used in that
1772 context. Otherwise, return 2 since it might be used there later.
1773 All other constants take at least two insns. */
1775 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1777 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1779 case CONST_DOUBLE: \
1780 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1782 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1783 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1785 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1788 return COSTS_N_INSNS (2); \
1792 switch (alpha_cpu) \
1794 case PROCESSOR_EV4: \
1795 return COSTS_N_INSNS (3); \
1796 case PROCESSOR_EV5: \
1797 case PROCESSOR_EV6: \
1798 return COSTS_N_INSNS (2); \
1802 /* Provide the costs of a rtl expression. This is in the body of a
1805 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1806 case PLUS: case MINUS: \
1807 if (FLOAT_MODE_P (GET_MODE (X))) \
1808 switch (alpha_cpu) \
1810 case PROCESSOR_EV4: \
1811 return COSTS_N_INSNS (6); \
1812 case PROCESSOR_EV5: \
1813 case PROCESSOR_EV6: \
1814 return COSTS_N_INSNS (4); \
1817 else if (GET_CODE (XEXP (X, 0)) == MULT \
1818 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1819 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1820 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1823 switch (alpha_cpu) \
1825 case PROCESSOR_EV4: \
1826 if (FLOAT_MODE_P (GET_MODE (X))) \
1827 return COSTS_N_INSNS (6); \
1828 return COSTS_N_INSNS (23); \
1829 case PROCESSOR_EV5: \
1830 if (FLOAT_MODE_P (GET_MODE (X))) \
1831 return COSTS_N_INSNS (4); \
1832 else if (GET_MODE (X) == DImode) \
1833 return COSTS_N_INSNS (12); \
1835 return COSTS_N_INSNS (8); \
1836 case PROCESSOR_EV6: \
1837 if (FLOAT_MODE_P (GET_MODE (X))) \
1838 return COSTS_N_INSNS (4); \
1840 return COSTS_N_INSNS (7); \
1844 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1845 && INTVAL (XEXP (X, 1)) <= 3) \
1847 /* ... fall through ... */ \
1848 case ASHIFTRT: case LSHIFTRT: \
1849 switch (alpha_cpu) \
1851 case PROCESSOR_EV4: \
1852 return COSTS_N_INSNS (2); \
1853 case PROCESSOR_EV5: \
1854 case PROCESSOR_EV6: \
1855 return COSTS_N_INSNS (1); \
1858 case IF_THEN_ELSE: \
1859 switch (alpha_cpu) \
1861 case PROCESSOR_EV4: \
1862 case PROCESSOR_EV6: \
1863 return COSTS_N_INSNS (2); \
1864 case PROCESSOR_EV5: \
1865 return COSTS_N_INSNS (1); \
1868 case DIV: case UDIV: case MOD: case UMOD: \
1869 switch (alpha_cpu) \
1871 case PROCESSOR_EV4: \
1872 if (GET_MODE (X) == SFmode) \
1873 return COSTS_N_INSNS (34); \
1874 else if (GET_MODE (X) == DFmode) \
1875 return COSTS_N_INSNS (63); \
1877 return COSTS_N_INSNS (70); \
1878 case PROCESSOR_EV5: \
1879 if (GET_MODE (X) == SFmode) \
1880 return COSTS_N_INSNS (15); \
1881 else if (GET_MODE (X) == DFmode) \
1882 return COSTS_N_INSNS (22); \
1884 return COSTS_N_INSNS (70); /* ??? */ \
1885 case PROCESSOR_EV6: \
1886 if (GET_MODE (X) == SFmode) \
1887 return COSTS_N_INSNS (12); \
1888 else if (GET_MODE (X) == DFmode) \
1889 return COSTS_N_INSNS (15); \
1891 return COSTS_N_INSNS (70); /* ??? */ \
1895 switch (alpha_cpu) \
1897 case PROCESSOR_EV4: \
1898 case PROCESSOR_EV6: \
1899 return COSTS_N_INSNS (3); \
1900 case PROCESSOR_EV5: \
1901 return COSTS_N_INSNS (2); \
1904 case NEG: case ABS: \
1905 if (! FLOAT_MODE_P (GET_MODE (X))) \
1907 /* ... fall through ... */ \
1908 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1909 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1910 switch (alpha_cpu) \
1912 case PROCESSOR_EV4: \
1913 return COSTS_N_INSNS (6); \
1914 case PROCESSOR_EV5: \
1915 case PROCESSOR_EV6: \
1916 return COSTS_N_INSNS (4); \
1920 /* Control the assembler format that we output. */
1922 /* We don't emit these labels, so as to avoid getting linker errors about
1923 missing exception handling info. If we emit a gcc_compiled. label into
1924 text, and the file has no code, then the DEC assembler gives us a zero
1925 sized text section with no associated exception handling info. The
1926 DEC linker sees this text section, and gives a warning saying that
1927 the exception handling info is missing. */
1928 #define ASM_IDENTIFY_GCC(x)
1929 #define ASM_IDENTIFY_LANGUAGE(x)
1931 /* Output to assembler file text saying following lines
1932 may contain character constants, extra white space, comments, etc. */
1934 #define ASM_APP_ON ""
1936 /* Output to assembler file text saying following lines
1937 no longer contain unusual constructs. */
1939 #define ASM_APP_OFF ""
1941 #define TEXT_SECTION_ASM_OP ".text"
1943 /* Output before read-only data. */
1945 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1947 /* Output before writable data. */
1949 #define DATA_SECTION_ASM_OP ".data"
1951 /* Define an extra section for read-only data, a routine to enter it, and
1952 indicate that it is for read-only data.
1954 The first time we enter the readonly data section for a file, we write
1955 eight bytes of zero. This works around a bug in DEC's assembler in
1956 some versions of OSF/1 V3.x. */
1958 #define EXTRA_SECTIONS readonly_data
1960 #define EXTRA_SECTION_FUNCTIONS \
1962 literal_section () \
1964 if (in_section != readonly_data) \
1966 static int firsttime = 1; \
1968 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1972 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1975 in_section = readonly_data; \
1979 #define READONLY_DATA_SECTION literal_section
1981 /* If we are referencing a function that is static, make the SYMBOL_REF
1982 special. We use this to see indicate we can branch to this function
1983 without setting PV or restoring GP. */
1985 #define ENCODE_SECTION_INFO(DECL) \
1986 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1987 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1989 /* How to refer to registers in assembler output.
1990 This sequence is indexed by compiler's hard-register-number (see above). */
1992 #define REGISTER_NAMES \
1993 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1994 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1995 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1996 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1997 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1998 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1999 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
2000 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
2002 /* How to renumber registers for dbx and gdb. */
2004 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2006 /* This is how to output the definition of a user-level label named NAME,
2007 such as the label on a static function or variable NAME. */
2009 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2010 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2012 /* This is how to output a command to make the user-level label named NAME
2013 defined for reference from other files. */
2015 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2016 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2018 /* The prefix to add to user-visible assembler symbols. */
2020 #define USER_LABEL_PREFIX ""
2022 /* This is how to output an internal numbered label where
2023 PREFIX is the class of label and NUM is the number within the class. */
2025 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2026 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2028 /* This is how to output a label for a jump table. Arguments are the same as
2029 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2032 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2033 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2035 /* This is how to store into the string LABEL
2036 the symbol_ref name of an internal numbered label where
2037 PREFIX is the class of label and NUM is the number within the class.
2038 This is suitable for output with `assemble_name'. */
2040 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2041 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2043 /* Check a floating-point value for validity for a particular machine mode. */
2045 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2046 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2048 /* This is how to output an assembler line defining a `double' constant. */
2050 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2052 if (REAL_VALUE_ISINF (VALUE) \
2053 || REAL_VALUE_ISNAN (VALUE) \
2054 || REAL_VALUE_MINUS_ZERO (VALUE)) \
2057 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2058 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2059 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2064 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
2065 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
2069 /* This is how to output an assembler line defining a `float' constant. */
2071 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2074 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2075 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2078 /* This is how to output an assembler line defining an `int' constant. */
2080 #define ASM_OUTPUT_INT(FILE,VALUE) \
2081 ( fprintf (FILE, "\t.long "), \
2082 output_addr_const (FILE, (VALUE)), \
2083 fprintf (FILE, "\n"))
2085 /* This is how to output an assembler line defining a `long' constant. */
2087 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2088 ( fprintf (FILE, "\t.quad "), \
2089 output_addr_const (FILE, (VALUE)), \
2090 fprintf (FILE, "\n"))
2092 /* Likewise for `char' and `short' constants. */
2094 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2095 fprintf (FILE, "\t.word %d\n", \
2096 (int)(GET_CODE (VALUE) == CONST_INT \
2097 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2099 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2100 fprintf (FILE, "\t.byte %d\n", \
2101 (int)(GET_CODE (VALUE) == CONST_INT \
2102 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2104 /* We use the default ASCII-output routine, except that we don't write more
2105 than 50 characters since the assembler doesn't support very long lines. */
2107 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2109 FILE *_hide_asm_out_file = (MYFILE); \
2110 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
2111 int _hide_thissize = (MYLENGTH); \
2112 int _size_so_far = 0; \
2114 FILE *asm_out_file = _hide_asm_out_file; \
2115 unsigned char *p = _hide_p; \
2116 int thissize = _hide_thissize; \
2118 fprintf (asm_out_file, "\t.ascii \""); \
2120 for (i = 0; i < thissize; i++) \
2122 register int c = p[i]; \
2124 if (_size_so_far ++ > 50 && i < thissize - 4) \
2125 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2127 if (c == '\"' || c == '\\') \
2128 putc ('\\', asm_out_file); \
2129 if (c >= ' ' && c < 0177) \
2130 putc (c, asm_out_file); \
2133 fprintf (asm_out_file, "\\%o", c); \
2134 /* After an octal-escape, if a digit follows, \
2135 terminate one string constant and start another. \
2136 The Vax assembler fails to stop reading the escape \
2137 after three digits, so this is the only way we \
2138 can get it to parse the data properly. */ \
2139 if (i < thissize - 1 \
2140 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2141 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2144 fprintf (asm_out_file, "\"\n"); \
2149 /* To get unaligned data, we have to turn off auto alignment. */
2150 #define UNALIGNED_SHORT_ASM_OP ".align 0\n\t.word"
2151 #define UNALIGNED_INT_ASM_OP ".align 0\n\t.long"
2152 #define UNALIGNED_DOUBLE_INT_ASM_OP ".align 0\n\t.quad"
2154 /* This is how to output an insn to push a register on the stack.
2155 It need not be very fast code. */
2157 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2158 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2159 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2162 /* This is how to output an insn to pop a register from the stack.
2163 It need not be very fast code. */
2165 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2166 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2167 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2170 /* This is how to output an assembler line for a numeric constant byte. */
2172 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2173 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2175 /* This is how to output an element of a case-vector that is absolute.
2176 (Alpha does not use such vectors, but we must define this macro anyway.) */
2178 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2180 /* This is how to output an element of a case-vector that is relative. */
2182 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2183 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2186 /* This is how to output an assembler line
2187 that says to advance the location counter
2188 to a multiple of 2**LOG bytes. */
2190 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2192 fprintf (FILE, "\t.align %d\n", LOG);
2194 /* This is how to advance the location counter by SIZE bytes. */
2196 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2197 fprintf (FILE, "\t.space %d\n", (SIZE))
2199 /* This says how to output an assembler line
2200 to define a global common symbol. */
2202 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2203 ( fputs ("\t.comm ", (FILE)), \
2204 assemble_name ((FILE), (NAME)), \
2205 fprintf ((FILE), ",%d\n", (SIZE)))
2207 /* This says how to output an assembler line
2208 to define a local common symbol. */
2210 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2211 ( fputs ("\t.lcomm ", (FILE)), \
2212 assemble_name ((FILE), (NAME)), \
2213 fprintf ((FILE), ",%d\n", (SIZE)))
2215 /* Store in OUTPUT a string (made with alloca) containing
2216 an assembler-name for a local static variable named NAME.
2217 LABELNO is an integer which is different for each call. */
2219 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2220 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2221 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2223 /* Define the parentheses used to group arithmetic operations
2224 in assembler code. */
2226 #define ASM_OPEN_PAREN "("
2227 #define ASM_CLOSE_PAREN ")"
2229 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2230 Used for C++ multiple inheritance. */
2232 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2234 char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2237 /* Mark end of prologue. */ \
2238 output_end_prologue (FILE); \
2240 /* Rely on the assembler to macro expand a large delta. */ \
2241 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2242 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2244 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \
2246 fprintf (FILE, "\tbr $31,$"); \
2247 assemble_name (FILE, fn_name); \
2248 fprintf (FILE, "..ng\n"); \
2252 fprintf (FILE, "\tjmp $31,"); \
2253 assemble_name (FILE, fn_name); \
2254 fputc ('\n', FILE); \
2259 /* Define results of standard character escape sequences. */
2260 #define TARGET_BELL 007
2261 #define TARGET_BS 010
2262 #define TARGET_TAB 011
2263 #define TARGET_NEWLINE 012
2264 #define TARGET_VT 013
2265 #define TARGET_FF 014
2266 #define TARGET_CR 015
2268 /* Print operand X (an rtx) in assembler syntax to file FILE.
2269 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2270 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2272 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2274 /* Determine which codes are valid without a following integer. These must
2275 not be alphabetic (the characters are chosen so that
2276 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2279 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2280 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2281 mode. alpha_fprm controls which suffix is generated.
2283 ' Generates trap-mode suffix for instructions that accept the
2284 su suffix only (cmpt et al).
2286 ` Generates trap-mode suffix for instructions that accept the
2287 v and sv suffix. The only instruction that needs this is cvtql.
2289 ( Generates trap-mode suffix for instructions that accept the
2290 v, sv, and svi suffix. The only instruction that needs this
2293 ) Generates trap-mode suffix for instructions that accept the
2294 u, su, and sui suffix. This is the bulk of the IEEE floating
2295 point instructions (addt et al).
2297 + Generates trap-mode suffix for instructions that accept the
2298 sui suffix (cvtqt and cvtqs).
2300 , Generates single precision suffix for floating point
2301 instructions (s for IEEE, f for VAX)
2303 - Generates double precision suffix for floating point
2304 instructions (t for IEEE, g for VAX)
2307 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2308 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2309 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2311 /* Print a memory address as an operand to reference that memory location. */
2313 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2314 print_operand_address((FILE), (ADDR))
2316 /* Define the codes that are matched by predicates in alpha.c. */
2318 #define PREDICATE_CODES \
2319 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2320 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2321 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2322 {"cint8_operand", {CONST_INT}}, \
2323 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2324 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2325 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2326 {"const48_operand", {CONST_INT}}, \
2327 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2328 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2329 {"mode_mask_operand", {CONST_INT}}, \
2330 {"mul8_operand", {CONST_INT}}, \
2331 {"mode_width_operand", {CONST_INT}}, \
2332 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2333 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2334 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2335 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2336 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2337 {"fp0_operand", {CONST_DOUBLE}}, \
2338 {"current_file_function_operand", {SYMBOL_REF}}, \
2339 {"call_operand", {REG, SYMBOL_REF}}, \
2340 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2341 SYMBOL_REF, CONST, LABEL_REF}}, \
2342 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2343 SYMBOL_REF, CONST, LABEL_REF}}, \
2344 {"aligned_memory_operand", {MEM}}, \
2345 {"unaligned_memory_operand", {MEM}}, \
2346 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2347 {"any_memory_operand", {MEM}}, \
2348 {"hard_fp_register_operand", {SUBREG, REG}}, \
2349 {"reg_not_elim_operand", {SUBREG, REG}}, \
2350 {"reg_no_subreg_operand", {REG}},
2352 /* Define the `__builtin_va_list' type for the ABI. */
2353 #define BUILD_VA_LIST_TYPE(VALIST) \
2354 (VALIST) = alpha_build_va_list ()
2356 /* Implement `va_start' for varargs and stdarg. */
2357 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2358 alpha_va_start (stdarg, valist, nextarg)
2360 /* Implement `va_arg'. */
2361 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2362 alpha_va_arg (valist, type)
2364 /* Tell collect that the object format is ECOFF. */
2365 #define OBJECT_FORMAT_COFF
2366 #define EXTENDED_COFF
2368 /* If we use NM, pass -g to it so it only lists globals. */
2369 #define NM_FLAGS "-pg"
2371 /* Definitions for debugging. */
2373 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2374 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2375 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2377 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2378 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2382 /* Correct the offset of automatic variables and arguments. Note that
2383 the Alpha debug format wants all automatic variables and arguments
2384 to be in terms of two different offsets from the virtual frame pointer,
2385 which is the stack pointer before any adjustment in the function.
2386 The offset for the argument pointer is fixed for the native compiler,
2387 it is either zero (for the no arguments case) or large enough to hold
2388 all argument registers.
2389 The offset for the auto pointer is the fourth argument to the .frame
2390 directive (local_offset).
2391 To stay compatible with the native tools we use the same offsets
2392 from the virtual frame pointer and adjust the debugger arg/auto offsets
2393 accordingly. These debugger offsets are set up in output_prolog. */
2395 extern long alpha_arg_offset;
2396 extern long alpha_auto_offset;
2397 #define DEBUGGER_AUTO_OFFSET(X) \
2398 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2399 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2402 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2403 alpha_output_lineno (STREAM, LINE)
2404 extern void alpha_output_lineno ();
2406 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2407 alpha_output_filename (STREAM, NAME)
2408 extern void alpha_output_filename ();
2410 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2411 number, because the real length runs past this up to the next
2412 continuation point. This is really a dbxout.c bug. */
2413 #define DBX_CONTIN_LENGTH 3000
2415 /* By default, turn on GDB extensions. */
2416 #define DEFAULT_GDB_EXTENSIONS 1
2418 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2419 #define NO_DBX_FUNCTION_END 1
2421 /* If we are smuggling stabs through the ALPHA ECOFF object
2422 format, put a comment in front of the .stab<x> operation so
2423 that the ALPHA assembler does not choke. The mips-tfile program
2424 will correctly put the stab into the object file. */
2426 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2427 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2428 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2430 /* Forward references to tags are allowed. */
2431 #define SDB_ALLOW_FORWARD_REFERENCES
2433 /* Unknown tags are also allowed. */
2434 #define SDB_ALLOW_UNKNOWN_REFERENCES
2436 #define PUT_SDB_DEF(a) \
2438 fprintf (asm_out_file, "\t%s.def\t", \
2439 (TARGET_GAS) ? "" : "#"); \
2440 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2441 fputc (';', asm_out_file); \
2444 #define PUT_SDB_PLAIN_DEF(a) \
2446 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2447 (TARGET_GAS) ? "" : "#", (a)); \
2450 #define PUT_SDB_TYPE(a) \
2452 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2455 /* For block start and end, we create labels, so that
2456 later we can figure out where the correct offset is.
2457 The normal .ent/.end serve well enough for functions,
2458 so those are just commented out. */
2460 extern int sdb_label_count; /* block start/end next label # */
2462 #define PUT_SDB_BLOCK_START(LINE) \
2464 fprintf (asm_out_file, \
2465 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2467 (TARGET_GAS) ? "" : "#", \
2470 sdb_label_count++; \
2473 #define PUT_SDB_BLOCK_END(LINE) \
2475 fprintf (asm_out_file, \
2476 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2478 (TARGET_GAS) ? "" : "#", \
2481 sdb_label_count++; \
2484 #define PUT_SDB_FUNCTION_START(LINE)
2486 #define PUT_SDB_FUNCTION_END(LINE)
2488 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2490 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2491 mips-tdump.c to print them out.
2493 These must match the corresponding definitions in gdb/mipsread.c.
2494 Unfortunately, gcc and gdb do not currently share any directories. */
2496 #define CODE_MASK 0x8F300
2497 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2498 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2499 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2501 /* Override some mips-tfile definitions. */
2503 #define SHASH_SIZE 511
2504 #define THASH_SIZE 55
2506 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2508 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2510 /* The linker will stick __main into the .init section. */
2511 #define HAS_INIT_SECTION
2512 #define LD_INIT_SWITCH "-init"
2513 #define LD_FINI_SWITCH "-fini"
2515 /* The system headers under Alpha systems are generally C++-aware. */
2516 #define NO_IMPLICIT_EXTERN_C
2518 /* Prototypes for alpha.c functions used in the md file & elsewhere. */
2519 extern struct rtx_def *get_unaligned_address ();
2520 extern void alpha_write_verstamp ();
2521 extern void alpha_reorg ();
2522 extern int check_float_value ();
2523 extern int direct_return ();
2524 extern int const48_operand ();
2525 extern int add_operand ();
2526 extern int and_operand ();
2527 extern int unaligned_memory_operand ();
2528 extern int zap_mask ();
2529 extern int current_file_function_operand ();
2530 extern int alpha_sa_size ();
2531 extern int alpha_adjust_cost ();
2532 extern void print_operand ();
2533 extern void print_operand_address ();
2534 extern int reg_or_0_operand ();
2535 extern int reg_or_8bit_operand ();
2536 extern int mul8_operand ();
2537 extern int reg_or_6bit_operand ();
2538 extern int alpha_comparison_operator ();
2539 extern int alpha_swapped_comparison_operator ();
2540 extern int sext_add_operand ();
2541 extern int cint8_operand ();
2542 extern int mode_mask_operand ();
2543 extern int or_operand ();
2544 extern int mode_width_operand ();
2545 extern int reg_or_fp0_operand ();
2546 extern int signed_comparison_operator ();
2547 extern int fp0_operand ();
2548 extern int some_operand ();
2549 extern int input_operand ();
2550 extern int divmod_operator ();
2551 extern int call_operand ();
2552 extern int reg_or_cint_operand ();
2553 extern int hard_fp_register_operand ();
2554 extern int reg_not_elim_operand ();
2555 extern int normal_memory_operand ();
2556 extern int reg_no_subreg_operand ();
2557 extern void alpha_set_memflags ();
2558 extern int aligned_memory_operand ();
2559 extern void get_aligned_mem ();
2560 extern void alpha_expand_unaligned_load ();
2561 extern void alpha_expand_unaligned_store ();
2562 extern int alpha_expand_block_move ();
2563 extern int alpha_expand_block_clear ();
2564 extern void alpha_expand_prologue ();
2565 extern void alpha_expand_epilogue ();
2566 extern union tree_node *alpha_build_va_list ();
2567 extern void alpha_va_start ();
2568 extern struct rtx_def *alpha_va_arg ();
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