1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Write out the correct language type definition for the header files.
25 Unless we have assembler language, write out the symbols for C. */
28 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
29 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
30 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
31 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
33 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
34 %(cpp_cpu) %(cpp_subtarget)"
36 #ifndef CPP_SUBTARGET_SPEC
37 #define CPP_SUBTARGET_SPEC ""
40 /* Set the spec to use for signed char. The default tests the above macro
41 but DEC's compiler can't handle the conditional in a "constant"
44 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
46 #define WORD_SWITCH_TAKES_ARG(STR) \
47 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
48 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
49 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
50 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
51 || !strcmp (STR, "isystem"))
53 /* Print subsidiary information on the compiler version in use. */
54 #define TARGET_VERSION
56 /* Run-time compilation parameters selecting different hardware subsets. */
58 /* Which processor to schedule for. The cpu attribute defines a list that
59 mirrors this list, so changes to alpha.md must be made at the same time. */
62 {PROCESSOR_EV4, /* 2106[46]{a,} */
63 PROCESSOR_EV5, /* 21164{a,pc,} */
64 PROCESSOR_EV6}; /* 21264 */
66 extern enum processor_type alpha_cpu;
68 enum alpha_trap_precision
70 ALPHA_TP_PROG, /* No precision (default). */
71 ALPHA_TP_FUNC, /* Trap contained within originating function. */
72 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
75 enum alpha_fp_rounding_mode
77 ALPHA_FPRM_NORM, /* Normal rounding mode. */
78 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
79 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
80 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
83 enum alpha_fp_trap_mode
85 ALPHA_FPTM_N, /* Normal trap mode. */
86 ALPHA_FPTM_U, /* Underflow traps enabled. */
87 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
88 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
91 extern int target_flags;
93 extern enum alpha_trap_precision alpha_tp;
94 extern enum alpha_fp_rounding_mode alpha_fprm;
95 extern enum alpha_fp_trap_mode alpha_fptm;
97 /* This means that floating-point support exists in the target implementation
98 of the Alpha architecture. This is usually the default. */
99 #define MASK_FP (1 << 0)
100 #define TARGET_FP (target_flags & MASK_FP)
102 /* This means that floating-point registers are allowed to be used. Note
103 that Alpha implementations without FP operations are required to
104 provide the FP registers. */
106 #define MASK_FPREGS (1 << 1)
107 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
109 /* This means that gas is used to process the assembler file. */
111 #define MASK_GAS (1 << 2)
112 #define TARGET_GAS (target_flags & MASK_GAS)
114 /* This means that we should mark procedures as IEEE conformant. */
116 #define MASK_IEEE_CONFORMANT (1 << 3)
117 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
119 /* This means we should be IEEE-compliant except for inexact. */
121 #define MASK_IEEE (1 << 4)
122 #define TARGET_IEEE (target_flags & MASK_IEEE)
124 /* This means we should be fully IEEE-compliant. */
126 #define MASK_IEEE_WITH_INEXACT (1 << 5)
127 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
129 /* This means we must construct all constants rather than emitting
130 them as literal data. */
132 #define MASK_BUILD_CONSTANTS (1 << 6)
133 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
135 /* This means we handle floating points in VAX F- (float)
136 or G- (double) Format. */
138 #define MASK_FLOAT_VAX (1 << 7)
139 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
141 /* This means that the processor has byte and half word loads and stores
142 (the BWX extension). */
144 #define MASK_BWX (1 << 8)
145 #define TARGET_BWX (target_flags & MASK_BWX)
147 /* This means that the processor has the MAX extension. */
148 #define MASK_MAX (1 << 9)
149 #define TARGET_MAX (target_flags & MASK_MAX)
151 /* This means that the processor has the FIX extension. */
152 #define MASK_FIX (1 << 10)
153 #define TARGET_FIX (target_flags & MASK_FIX)
155 /* This means that the processor has the CIX extension. */
156 #define MASK_CIX (1 << 11)
157 #define TARGET_CIX (target_flags & MASK_CIX)
159 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
160 only in TARGET_CPU_DEFAULT. */
161 #define MASK_CPU_EV5 (1 << 28)
163 /* Likewise for EV6. */
164 #define MASK_CPU_EV6 (1 << 29)
166 /* This means we support the .arch directive in the assembler. Only
167 defined in TARGET_CPU_DEFAULT. */
168 #define MASK_SUPPORT_ARCH (1 << 30)
169 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
171 /* These are for target os support and cannot be changed at runtime. */
172 #ifndef TARGET_WINDOWS_NT
173 #define TARGET_WINDOWS_NT 0
175 #ifndef TARGET_OPEN_VMS
176 #define TARGET_OPEN_VMS 0
179 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
180 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
182 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
183 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
185 #ifndef TARGET_HAS_XFLOATING_LIBS
186 #define TARGET_HAS_XFLOATING_LIBS 0
189 /* Macro to define tables used to set the flags.
190 This is a list in braces of pairs in braces,
191 each pair being { "NAME", VALUE }
192 where VALUE is the bits to set or minus the bits to clear.
193 An empty string NAME is used to identify the default VALUE. */
195 #define TARGET_SWITCHES \
196 { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
197 {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
198 {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
199 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
200 {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
201 {"gas", MASK_GAS, "Assume GAS"}, \
202 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
203 "Request IEEE-conformant math library routines (OSF/1)"}, \
204 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
205 "Emit IEEE-conformant code, without inexact exceptions"}, \
206 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
207 "Emit IEEE-conformant code, with inexact exceptions"}, \
208 {"build-constants", MASK_BUILD_CONSTANTS, \
209 "Do not emit complex integer constants to read-only memory"}, \
210 {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
211 {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
212 {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
213 {"no-bwx", -MASK_BWX, ""}, \
214 {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
215 {"no-max", -MASK_MAX, ""}, \
216 {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
217 {"no-fix", -MASK_FIX, ""}, \
218 {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
219 {"no-cix", -MASK_CIX, ""}, \
220 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
222 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
224 #ifndef TARGET_CPU_DEFAULT
225 #define TARGET_CPU_DEFAULT 0
228 /* This macro is similar to `TARGET_SWITCHES' but defines names of
229 command options that have values. Its definition is an initializer
230 with a subgrouping for each command option.
232 Each subgrouping contains a string constant, that defines the fixed
233 part of the option name, and the address of a variable. The
234 variable, type `char *', is set to the variable part of the given
235 option if the fixed part matches. The actual option name is made
236 by appending `-m' to the specified name.
238 Here is an example which defines `-mshort-data-NUMBER'. If the
239 given option is `-mshort-data-512', the variable `m88k_short_data'
240 will be set to the string `"512"'.
242 extern char *m88k_short_data;
243 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
245 extern const char *alpha_cpu_string; /* For -mcpu= */
246 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
247 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
248 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
249 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
251 #define TARGET_OPTIONS \
253 {"cpu=", &alpha_cpu_string, \
254 "Generate code for a given CPU"}, \
255 {"fp-rounding-mode=", &alpha_fprm_string, \
256 "Control the generated fp rounding mode"}, \
257 {"fp-trap-mode=", &alpha_fptm_string, \
258 "Control the IEEE trap mode"}, \
259 {"trap-precision=", &alpha_tp_string, \
260 "Control the precision given to fp exceptions"}, \
261 {"memory-latency=", &alpha_mlat_string, \
262 "Tune expected memory latency"}, \
265 /* Attempt to describe CPU characteristics to the preprocessor. */
267 /* Corresponding to amask... */
268 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
269 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
270 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
271 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
273 /* Corresponding to implver... */
274 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
275 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
276 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
278 /* Common combinations. */
279 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
280 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
281 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
282 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
283 #define CPP_CPU_EV6_SPEC \
284 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
285 #define CPP_CPU_EV67_SPEC \
286 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
288 #ifndef CPP_CPU_DEFAULT_SPEC
289 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
290 # if TARGET_CPU_DEFAULT & MAX_CIX
291 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
293 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
296 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
297 # if TARGET_CPU_DEFAULT & MASK_MAX
298 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
300 # if TARGET_CPU_DEFAULT & MASK_BWX
301 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
303 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
307 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
310 #endif /* CPP_CPU_DEFAULT_SPEC */
313 #define CPP_CPU_SPEC "\
314 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
315 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
316 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
317 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
318 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
319 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
320 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
321 %{!mcpu*:%(cpp_cpu_default) }}"
324 /* This macro defines names of additional specifications to put in the
325 specs that can be used in various specifications like CC1_SPEC. Its
326 definition is an initializer with a subgrouping for each command option.
328 Each subgrouping contains a string constant, that defines the
329 specification name, and a string constant that used by the GNU CC driver
332 Do not define this macro if it does not need to do anything. */
334 #ifndef SUBTARGET_EXTRA_SPECS
335 #define SUBTARGET_EXTRA_SPECS
338 #define EXTRA_SPECS \
339 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
340 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
341 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
342 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
343 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
344 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
345 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
346 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
347 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
348 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
349 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
350 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
351 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
352 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
353 { "cpp_cpu", CPP_CPU_SPEC }, \
354 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
355 SUBTARGET_EXTRA_SPECS
358 /* Sometimes certain combinations of command options do not make sense
359 on a particular target machine. You can define a macro
360 `OVERRIDE_OPTIONS' to take account of this. This macro, if
361 defined, is executed once just after all the command options have
364 On the Alpha, it is used to translate target-option strings into
367 #define OVERRIDE_OPTIONS override_options ()
370 /* Define this macro to change register usage conditional on target flags.
372 On the Alpha, we use this to disable the floating-point registers when
375 #define CONDITIONAL_REGISTER_USAGE \
376 if (! TARGET_FPREGS) \
377 for (i = 32; i < 63; i++) \
378 fixed_regs[i] = call_used_regs[i] = 1;
380 /* Show we can debug even without a frame pointer. */
381 #define CAN_DEBUG_WITHOUT_FP
383 /* target machine storage layout */
385 /* Define to enable software floating point emulation. */
386 #define REAL_ARITHMETIC
388 /* The following #defines are used when compiling the routines in
389 libgcc1.c. Since the Alpha calling conventions require single
390 precision floats to be passed in the floating-point registers
391 (rather than in the general registers) we have to build the
392 libgcc1.c routines in such a way that they know the actual types
393 of their formal arguments and the actual types of their return
394 values. Otherwise, gcc will generate calls to the libgcc1.c
395 routines, passing arguments in the floating-point registers,
396 but the libgcc1.c routines will expect their arguments on the
397 stack (where the Alpha calling conventions require structs &
398 unions to be passed). */
400 #define FLOAT_VALUE_TYPE double
401 #define INTIFY(FLOATVAL) (FLOATVAL)
402 #define FLOATIFY(INTVAL) (INTVAL)
403 #define FLOAT_ARG_TYPE double
405 /* Define the size of `int'. The default is the same as the word size. */
406 #define INT_TYPE_SIZE 32
408 /* Define the size of `long long'. The default is the twice the word size. */
409 #define LONG_LONG_TYPE_SIZE 64
411 /* The two floating-point formats we support are S-floating, which is
412 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
413 and `long double' are T. */
415 #define FLOAT_TYPE_SIZE 32
416 #define DOUBLE_TYPE_SIZE 64
417 #define LONG_DOUBLE_TYPE_SIZE 64
419 #define WCHAR_TYPE "unsigned int"
420 #define WCHAR_TYPE_SIZE 32
422 /* Define this macro if it is advisable to hold scalars in registers
423 in a wider mode than that declared by the program. In such cases,
424 the value is constrained to be within the bounds of the declared
425 type, but kept valid in the wider mode. The signedness of the
426 extension may differ from that of the type.
428 For Alpha, we always store objects in a full register. 32-bit objects
429 are always sign-extended, but smaller objects retain their signedness. */
431 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
432 if (GET_MODE_CLASS (MODE) == MODE_INT \
433 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
435 if ((MODE) == SImode) \
440 /* Define this if function arguments should also be promoted using the above
443 #define PROMOTE_FUNCTION_ARGS
445 /* Likewise, if the function return value is promoted. */
447 #define PROMOTE_FUNCTION_RETURN
449 /* Define this if most significant bit is lowest numbered
450 in instructions that operate on numbered bit-fields.
452 There are no such instructions on the Alpha, but the documentation
454 #define BITS_BIG_ENDIAN 0
456 /* Define this if most significant byte of a word is the lowest numbered.
457 This is false on the Alpha. */
458 #define BYTES_BIG_ENDIAN 0
460 /* Define this if most significant word of a multiword number is lowest
463 For Alpha we can decide arbitrarily since there are no machine instructions
464 for them. Might as well be consistent with bytes. */
465 #define WORDS_BIG_ENDIAN 0
467 /* number of bits in an addressable storage unit */
468 #define BITS_PER_UNIT 8
470 /* Width in bits of a "word", which is the contents of a machine register.
471 Note that this is not necessarily the width of data type `int';
472 if using 16-bit ints on a 68000, this would still be 32.
473 But on a machine with 16-bit registers, this would be 16. */
474 #define BITS_PER_WORD 64
476 /* Width of a word, in units (bytes). */
477 #define UNITS_PER_WORD 8
479 /* Width in bits of a pointer.
480 See also the macro `Pmode' defined below. */
481 #define POINTER_SIZE 64
483 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
484 #define PARM_BOUNDARY 64
486 /* Boundary (in *bits*) on which stack pointer should be aligned. */
487 #define STACK_BOUNDARY 64
489 /* Allocation boundary (in *bits*) for the code of a function. */
490 #define FUNCTION_BOUNDARY 256
492 /* Alignment of field after `int : 0' in a structure. */
493 #define EMPTY_FIELD_BOUNDARY 64
495 /* Every structure's size must be a multiple of this. */
496 #define STRUCTURE_SIZE_BOUNDARY 8
498 /* A bitfield declared as `int' forces `int' alignment for the struct. */
499 #define PCC_BITFIELD_TYPE_MATTERS 1
501 /* Align loop starts for optimal branching.
503 ??? Kludge this and the next macro for the moment by not doing anything if
504 we don't optimize and also if we are writing ECOFF symbols to work around
505 a bug in DEC's assembler. */
507 #define LOOP_ALIGN(LABEL) \
508 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
510 /* This is how to align an instruction for optimal branching. On
511 Alpha we'll get better performance by aligning on an octaword
514 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
515 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
517 /* No data type wants to be aligned rounder than this. */
518 #define BIGGEST_ALIGNMENT 128
520 /* For atomic access to objects, must have at least 32-bit alignment
521 unless the machine has byte operations. */
522 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
524 /* Align all constants and variables to at least a word boundary so
525 we can pick up pieces of them faster. */
526 /* ??? Only if block-move stuff knows about different source/destination
529 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
530 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
533 /* Set this non-zero if move instructions will actually fail to work
534 when given unaligned data.
536 Since we get an error message when we do one, call them invalid. */
538 #define STRICT_ALIGNMENT 1
540 /* Set this non-zero if unaligned move instructions are extremely slow.
542 On the Alpha, they trap. */
544 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
546 /* Standard register usage. */
548 /* Number of actual hardware registers.
549 The hardware registers are assigned numbers for the compiler
550 from 0 to just below FIRST_PSEUDO_REGISTER.
551 All registers that the compiler knows about must be given numbers,
552 even those that are not normally considered general registers.
554 We define all 32 integer registers, even though $31 is always zero,
555 and all 32 floating-point registers, even though $f31 is also
556 always zero. We do not bother defining the FP status register and
557 there are no other registers.
559 Since $31 is always zero, we will use register number 31 as the
560 argument pointer. It will never appear in the generated code
561 because we will always be eliminating it in favor of the stack
562 pointer or hardware frame pointer.
564 Likewise, we use $f31 for the frame pointer, which will always
565 be eliminated in favor of the hardware frame pointer or the
568 #define FIRST_PSEUDO_REGISTER 64
570 /* 1 for registers that have pervasive standard uses
571 and are not available for the register allocator. */
573 #define FIXED_REGISTERS \
574 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
579 /* 1 for registers not available across function calls.
580 These must include the FIXED_REGISTERS and also any
581 registers that can be used without being saved.
582 The latter must include the registers where values are returned
583 and the register where structure-value addresses are passed.
584 Aside from that, you can include as many other registers as you like. */
585 #define CALL_USED_REGISTERS \
586 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
588 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
589 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
591 /* List the order in which to allocate registers. Each register must be
592 listed once, even those in FIXED_REGISTERS.
594 We allocate in the following order:
595 $f10-$f15 (nonsaved floating-point register)
597 $f21-$f16 (likewise, but input args)
598 $f0 (nonsaved, but return value)
599 $f1 (nonsaved, but immediate before saved)
600 $f2-$f9 (saved floating-point registers)
601 $1-$8 (nonsaved integer registers)
604 $0 (likewise, but return value)
605 $21-$16 (likewise, but input args)
606 $27 (procedure value in OSF, nonsaved in NT)
607 $9-$14 (saved integer registers)
611 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
613 #define REG_ALLOC_ORDER \
614 {42, 43, 44, 45, 46, 47, \
615 54, 55, 56, 57, 58, 59, 60, 61, 62, \
616 53, 52, 51, 50, 49, 48, \
618 34, 35, 36, 37, 38, 39, 40, 41, \
619 1, 2, 3, 4, 5, 6, 7, 8, \
623 21, 20, 19, 18, 17, 16, \
625 9, 10, 11, 12, 13, 14, \
631 /* Return number of consecutive hard regs needed starting at reg REGNO
632 to hold something of mode MODE.
633 This is ordinarily the length in words of a value of mode MODE
634 but can be less for certain modes in special long registers. */
636 #define HARD_REGNO_NREGS(REGNO, MODE) \
637 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
639 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
640 On Alpha, the integer registers can hold any mode. The floating-point
641 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
644 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
645 ((REGNO) >= 32 && (REGNO) <= 62 \
646 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
649 /* A C expression that is nonzero if a value of mode
650 MODE1 is accessible in mode MODE2 without copying.
652 This asymmetric test is true when MODE1 could be put
653 in an FP register but MODE2 could not. */
655 #define MODES_TIEABLE_P(MODE1, MODE2) \
656 (HARD_REGNO_MODE_OK (32, (MODE1)) \
657 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
660 /* Specify the registers used for certain standard purposes.
661 The values of these macros are register numbers. */
663 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
664 /* #define PC_REGNUM */
666 /* Register to use for pushing function arguments. */
667 #define STACK_POINTER_REGNUM 30
669 /* Base register for access to local variables of the function. */
670 #define HARD_FRAME_POINTER_REGNUM 15
672 /* Value should be nonzero if functions must have frame pointers.
673 Zero means the frame pointer need not be set up (and parms
674 may be accessed via the stack pointer) in functions that seem suitable.
675 This is computed in `reload', in reload1.c. */
676 #define FRAME_POINTER_REQUIRED 0
678 /* Base register for access to arguments of the function. */
679 #define ARG_POINTER_REGNUM 31
681 /* Base register for access to local variables of function. */
682 #define FRAME_POINTER_REGNUM 63
684 /* Register in which static-chain is passed to a function.
686 For the Alpha, this is based on an example; the calling sequence
687 doesn't seem to specify this. */
688 #define STATIC_CHAIN_REGNUM 1
690 /* Register in which address to store a structure value
691 arrives in the function. On the Alpha, the address is passed
692 as a hidden argument. */
693 #define STRUCT_VALUE 0
695 /* Define the classes of registers for register constraints in the
696 machine description. Also define ranges of constants.
698 One of the classes must always be named ALL_REGS and include all hard regs.
699 If there is more than one class, another class must be named NO_REGS
700 and contain no registers.
702 The name GENERAL_REGS must be the name of a class (or an alias for
703 another name such as ALL_REGS). This is the class of registers
704 that is allowed by "g" or "r" in a register constraint.
705 Also, registers outside this class are allocated only when
706 instructions express preferences for them.
708 The classes must be numbered in nondecreasing order; that is,
709 a larger-numbered class must never be contained completely
710 in a smaller-numbered class.
712 For any two classes, it is very desirable that there be another
713 class that represents their union. */
715 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
718 #define N_REG_CLASSES (int) LIM_REG_CLASSES
720 /* Give names of register classes as strings for dump file. */
722 #define REG_CLASS_NAMES \
723 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
725 /* Define which registers fit in which classes.
726 This is an initializer for a vector of HARD_REG_SET
727 of length N_REG_CLASSES. */
729 #define REG_CLASS_CONTENTS \
730 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
732 /* The same information, inverted:
733 Return the class number of the smallest class containing
734 reg number REGNO. This could be a conditional expression
735 or could index an array. */
737 #define REGNO_REG_CLASS(REGNO) \
738 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
740 /* The class value for index registers, and the one for base regs. */
741 #define INDEX_REG_CLASS NO_REGS
742 #define BASE_REG_CLASS GENERAL_REGS
744 /* Get reg_class from a letter such as appears in the machine description. */
746 #define REG_CLASS_FROM_LETTER(C) \
747 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
749 /* Define this macro to change register usage conditional on target flags. */
750 /* #define CONDITIONAL_REGISTER_USAGE */
752 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
753 can be used to stand for particular ranges of immediate operands.
754 This macro defines what the ranges are.
755 C is the letter, and VALUE is a constant value.
756 Return 1 if VALUE is in the range specified by C.
759 `I' is used for the range of constants most insns can contain.
760 `J' is the constant zero.
761 `K' is used for the constant in an LDA insn.
762 `L' is used for the constant in a LDAH insn.
763 `M' is used for the constants that can be AND'ed with using a ZAP insn.
764 `N' is used for complemented 8-bit constants.
765 `O' is used for negated 8-bit constants.
766 `P' is used for the constants 1, 2 and 3. */
768 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
769 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
770 : (C) == 'J' ? (VALUE) == 0 \
771 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
772 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
773 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
774 : (C) == 'M' ? zap_mask (VALUE) \
775 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
776 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
777 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
780 /* Similar, but for floating or large integer constants, and defining letters
781 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
783 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
784 that is the operand of a ZAP insn. */
786 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
787 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
788 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
789 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
790 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
791 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
794 /* Optional extra constraints for this machine.
796 For the Alpha, `Q' means that this is a memory operand but not a
797 reference to an unaligned location.
799 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
802 'S' is a 6-bit constant (valid for a shift insn). */
804 #define EXTRA_CONSTRAINT(OP, C) \
805 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
806 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
807 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
808 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
811 /* Given an rtx X being reloaded into a reg required to be
812 in class CLASS, return the class of reg to actually use.
813 In general this is just CLASS; but on some machines
814 in some cases it is preferable to use a more restrictive class.
816 On the Alpha, all constants except zero go into a floating-point
817 register via memory. */
819 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
820 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
821 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
824 /* Loading and storing HImode or QImode values to and from memory
825 usually requires a scratch register. The exceptions are loading
826 QImode and HImode from an aligned address to a general register
827 unless byte instructions are permitted.
828 We also cannot load an unaligned address or a paradoxical SUBREG into an
831 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
832 secondary_reload_class((CLASS), (MODE), (IN), 1)
834 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
835 secondary_reload_class((CLASS), (MODE), (OUT), 0)
837 /* If we are copying between general and FP registers, we need a memory
838 location unless the FIX extension is available. */
840 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
841 (! TARGET_FIX && (CLASS1) != (CLASS2))
843 /* Specify the mode to be used for memory when a secondary memory
844 location is needed. If MODE is floating-point, use it. Otherwise,
845 widen to a word like the default. This is needed because we always
846 store integers in FP registers in quadword format. This whole
847 area is very tricky! */
848 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
849 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
850 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
851 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
853 /* Return the maximum number of consecutive registers
854 needed to represent mode MODE in a register of class CLASS. */
856 #define CLASS_MAX_NREGS(CLASS, MODE) \
857 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
859 /* If defined, gives a class of registers that cannot be used as the
860 operand of a SUBREG that changes the size of the object. */
862 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
864 /* Define the cost of moving between registers of various classes. Moving
865 between FLOAT_REGS and anything else except float regs is expensive.
866 In fact, we make it quite expensive because we really don't want to
867 do these moves unless it is clearly worth it. Optimizations may
868 reduce the impact of not being able to allocate a pseudo to a
871 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
872 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
874 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
876 /* A C expressions returning the cost of moving data of MODE from a register to
879 On the Alpha, bump this up a bit. */
881 extern int alpha_memory_latency;
882 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
884 /* Provide the cost of a branch. Exact meaning under development. */
885 #define BRANCH_COST 5
887 /* Adjust the cost of dependencies. */
889 #define ADJUST_COST(INSN,LINK,DEP,COST) \
890 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
892 /* Stack layout; function entry, exit and calling. */
894 /* Define this if pushing a word on the stack
895 makes the stack pointer a smaller address. */
896 #define STACK_GROWS_DOWNWARD
898 /* Define this if the nominal address of the stack frame
899 is at the high-address end of the local variables;
900 that is, each additional local variable allocated
901 goes at a more negative offset in the frame. */
902 /* #define FRAME_GROWS_DOWNWARD */
904 /* Offset within stack frame to start allocating local variables at.
905 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
906 first local allocated. Otherwise, it is the offset to the BEGINNING
907 of the first local allocated. */
909 #define STARTING_FRAME_OFFSET 0
911 /* If we generate an insn to push BYTES bytes,
912 this says how many the stack pointer really advances by.
913 On Alpha, don't define this because there are no push insns. */
914 /* #define PUSH_ROUNDING(BYTES) */
916 /* Define this to be nonzero if stack checking is built into the ABI. */
917 #define STACK_CHECK_BUILTIN 1
919 /* Define this if the maximum size of all the outgoing args is to be
920 accumulated and pushed during the prologue. The amount can be
921 found in the variable current_function_outgoing_args_size. */
922 #define ACCUMULATE_OUTGOING_ARGS
924 /* Offset of first parameter from the argument pointer register value. */
926 #define FIRST_PARM_OFFSET(FNDECL) 0
928 /* Definitions for register eliminations.
930 We have two registers that can be eliminated on the Alpha. First, the
931 frame pointer register can often be eliminated in favor of the stack
932 pointer register. Secondly, the argument pointer register can always be
933 eliminated; it is replaced with either the stack or frame pointer. */
935 /* This is an array of structures. Each structure initializes one pair
936 of eliminable registers. The "from" register number is given first,
937 followed by "to". Eliminations of the same "from" register are listed
938 in order of preference. */
940 #define ELIMINABLE_REGS \
941 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
942 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
943 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
944 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
946 /* Given FROM and TO register numbers, say whether this elimination is allowed.
947 Frame pointer elimination is automatically handled.
949 All eliminations are valid since the cases where FP can't be
950 eliminated are already handled. */
952 #define CAN_ELIMINATE(FROM, TO) 1
954 /* Round up to a multiple of 16 bytes. */
955 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
957 /* Define the offset between two registers, one to be eliminated, and the other
958 its replacement, at the start of a routine. */
959 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
960 { if ((FROM) == FRAME_POINTER_REGNUM) \
961 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
962 + alpha_sa_size ()); \
963 else if ((FROM) == ARG_POINTER_REGNUM) \
964 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
966 + (ALPHA_ROUND (get_frame_size () \
967 + current_function_pretend_args_size) \
968 - current_function_pretend_args_size)); \
973 /* Define this if stack space is still allocated for a parameter passed
975 /* #define REG_PARM_STACK_SPACE */
977 /* Value is the number of bytes of arguments automatically
978 popped when returning from a subroutine call.
979 FUNDECL is the declaration node of the function (as a tree),
980 FUNTYPE is the data type of the function (as a tree),
981 or for a library call it is an identifier node for the subroutine name.
982 SIZE is the number of bytes of arguments passed on the stack. */
984 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
986 /* Define how to find the value returned by a function.
987 VALTYPE is the data type of the value (as a tree).
988 If the precise function being called is known, FUNC is its FUNCTION_DECL;
989 otherwise, FUNC is 0.
991 On Alpha the value is found in $0 for integer functions and
992 $f0 for floating-point functions. */
994 #define FUNCTION_VALUE(VALTYPE, FUNC) \
995 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
996 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
997 || POINTER_TYPE_P (VALTYPE)) \
998 ? word_mode : TYPE_MODE (VALTYPE), \
1000 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1001 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1004 /* Define how to find the value returned by a library function
1005 assuming the value has mode MODE. */
1007 #define LIBCALL_VALUE(MODE) \
1008 gen_rtx_REG (MODE, \
1010 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1011 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1014 /* The definition of this macro implies that there are cases where
1015 a scalar value cannot be returned in registers.
1017 For the Alpha, any structure or union type is returned in memory, as
1018 are integers whose size is larger than 64 bits. */
1020 #define RETURN_IN_MEMORY(TYPE) \
1021 (TYPE_MODE (TYPE) == BLKmode \
1022 || TYPE_MODE (TYPE) == TFmode \
1023 || TYPE_MODE (TYPE) == TCmode \
1024 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1026 /* 1 if N is a possible register number for a function value
1027 as seen by the caller. */
1029 #define FUNCTION_VALUE_REGNO_P(N) \
1030 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1032 /* 1 if N is a possible register number for function argument passing.
1033 On Alpha, these are $16-$21 and $f16-$f21. */
1035 #define FUNCTION_ARG_REGNO_P(N) \
1036 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1038 /* Define a data type for recording info about an argument list
1039 during the scan of that argument list. This data type should
1040 hold all necessary information about the function itself
1041 and about the args processed so far, enough to enable macros
1042 such as FUNCTION_ARG to determine where the next arg should go.
1044 On Alpha, this is a single integer, which is a number of words
1045 of arguments scanned so far.
1046 Thus 6 or more means all following args should go on the stack. */
1048 #define CUMULATIVE_ARGS int
1050 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1051 for a call to a function whose data type is FNTYPE.
1052 For a library call, FNTYPE is 0. */
1054 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1056 /* Define intermediate macro to compute the size (in registers) of an argument
1059 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1060 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1061 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1062 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1064 /* Update the data in CUM to advance over an argument
1065 of mode MODE and data type TYPE.
1066 (TYPE is null for libcalls where that information may not be available.) */
1068 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1069 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1072 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1074 /* Determine where to put an argument to a function.
1075 Value is zero to push the argument on the stack,
1076 or a hard register in which to store the argument.
1078 MODE is the argument's machine mode.
1079 TYPE is the data type of the argument (as a tree).
1080 This is null for libcalls where that information may
1082 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1083 the preceding args and about the function being called.
1084 NAMED is nonzero if this argument is a named parameter
1085 (otherwise it is an extra parameter matching an ellipsis).
1087 On Alpha the first 6 words of args are normally in registers
1088 and the rest are pushed. */
1090 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1091 function_arg((CUM), (MODE), (TYPE), (NAMED))
1093 /* A C expression that indicates when an argument must be passed by
1094 reference. If nonzero for an argument, a copy of that argument is
1095 made in memory and a pointer to the argument is passed instead of
1096 the argument itself. The pointer is passed in whatever way is
1097 appropriate for passing a pointer to that type. */
1099 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1100 ((MODE) == TFmode || (MODE) == TCmode)
1102 /* Specify the padding direction of arguments.
1104 On the Alpha, we must pad upwards in order to be able to pass args in
1107 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1109 /* For an arg passed partly in registers and partly in memory,
1110 this is the number of registers used.
1111 For args passed entirely in registers or entirely in memory, zero. */
1113 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1114 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1117 /* Perform any needed actions needed for a function that is receiving a
1118 variable number of arguments.
1122 MODE and TYPE are the mode and type of the current parameter.
1124 PRETEND_SIZE is a variable that should be set to the amount of stack
1125 that must be pushed by the prolog to pretend that our caller pushed
1128 Normally, this macro will push all remaining incoming registers on the
1129 stack and set PRETEND_SIZE to the length of the registers pushed.
1131 On the Alpha, we allocate space for all 12 arg registers, but only
1132 push those that are remaining.
1134 However, if NO registers need to be saved, don't allocate any space.
1135 This is not only because we won't need the space, but because AP includes
1136 the current_pretend_args_size and we don't want to mess up any
1137 ap-relative addresses already made.
1139 If we are not to use the floating-point registers, save the integer
1140 registers where we would put the floating-point registers. This is
1141 not the most efficient way to implement varargs with just one register
1142 class, but it isn't worth doing anything more efficient in this rare
1145 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1150 rtx tmp; int set = get_varargs_alias_set (); \
1151 tmp = gen_rtx_MEM (BLKmode, \
1152 plus_constant (virtual_incoming_args_rtx, \
1153 ((CUM) + 6)* UNITS_PER_WORD)); \
1154 MEM_ALIAS_SET (tmp) = set; \
1155 move_block_from_reg \
1157 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1159 tmp = gen_rtx_MEM (BLKmode, \
1160 plus_constant (virtual_incoming_args_rtx, \
1161 (CUM) * UNITS_PER_WORD)); \
1162 MEM_ALIAS_SET (tmp) = set; \
1163 move_block_from_reg \
1164 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1165 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1167 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1171 /* We do not allow indirect calls to be optimized into sibling calls, nor
1172 can we allow a call to a function in a different compilation unit to
1173 be optimized into a sibcall. Except if the function is known not to
1174 return, in which case our caller doesn't care what the gp is. */
1175 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1177 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1178 || ! TREE_PUBLIC (DECL) \
1179 || (0 && TREE_THIS_VOLATILE (DECL))))
1181 /* Try to output insns to set TARGET equal to the constant C if it can be
1182 done in less than N insns. Do all computations in MODE. Returns the place
1183 where the output has been placed if it can be done and the insns have been
1184 emitted. If it would take more than N insns, zero is returned and no
1185 insns and emitted. */
1187 /* Define the information needed to generate branch and scc insns. This is
1188 stored from the compare operation. Note that we can't use "rtx" here
1189 since it hasn't been defined! */
1191 struct alpha_compare
1193 struct rtx_def *op0, *op1;
1197 extern struct alpha_compare alpha_compare;
1199 /* Machine specific function data. */
1201 struct machine_function
1203 /* An offset to apply to the stack pointer when unwinding from EH. */
1204 struct rtx_def *eh_epilogue_sp_ofs;
1206 /* If non-null, this rtx holds the return address for the function. */
1207 struct rtx_def *ra_rtx;
1210 /* Make (or fake) .linkage entry for function call.
1211 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1213 /* This macro defines the start of an assembly comment. */
1215 #define ASM_COMMENT_START " #"
1217 /* This macro produces the initial definition of a function. */
1219 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1220 alpha_start_function(FILE,NAME,DECL);
1222 /* This macro closes up a function definition for the assembler. */
1224 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1225 alpha_end_function(FILE,NAME,DECL)
1227 /* This macro notes the end of the prologue. */
1229 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1231 /* Output any profiling code before the prologue. */
1233 #define PROFILE_BEFORE_PROLOGUE 1
1235 /* Output assembler code to FILE to increment profiler label # LABELNO
1236 for profiling a function entry. Under OSF/1, profiling is enabled
1237 by simply passing -pg to the assembler and linker. */
1239 #define FUNCTION_PROFILER(FILE, LABELNO)
1241 /* Output assembler code to FILE to initialize this source file's
1242 basic block profiling info, if that has not already been done.
1243 This assumes that __bb_init_func doesn't garble a1-a5. */
1245 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1247 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1248 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1249 fputs ("\tldq $26,0($16)\n", (FILE)); \
1250 fputs ("\tbne $26,1f\n", (FILE)); \
1251 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1252 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1253 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1254 fputs ("1:\n", (FILE)); \
1255 ASM_OUTPUT_REG_POP (FILE, 16); \
1258 /* Output assembler code to FILE to increment the entry-count for
1259 the BLOCKNO'th basic block in this source file. */
1261 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1263 int blockn = (BLOCKNO); \
1264 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1265 fputs ("\tstq $26,0($30)\n", (FILE)); \
1266 fputs ("\tstq $27,8($30)\n", (FILE)); \
1267 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1268 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1269 fputs ("\taddq $27,1,$27\n", (FILE)); \
1270 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1271 fputs ("\tldq $26,0($30)\n", (FILE)); \
1272 fputs ("\tldq $27,8($30)\n", (FILE)); \
1273 fputs ("\taddq $30,16,$30\n", (FILE)); \
1277 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1278 the stack pointer does not matter. The value is tested only in
1279 functions that have frame pointers.
1280 No definition is equivalent to always zero. */
1282 #define EXIT_IGNORE_STACK 1
1284 /* Define registers used by the epilogue and return instruction. */
1286 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1288 /* Output assembler code for a block containing the constant parts
1289 of a trampoline, leaving space for the variable parts.
1291 The trampoline should set the static chain pointer to value placed
1292 into the trampoline and should branch to the specified routine.
1293 Note that $27 has been set to the address of the trampoline, so we can
1294 use it for addressability of the two data items. Trampolines are always
1295 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1297 #define TRAMPOLINE_TEMPLATE(FILE) \
1299 fprintf (FILE, "\tldq $1,24($27)\n"); \
1300 fprintf (FILE, "\tldq $27,16($27)\n"); \
1301 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1302 fprintf (FILE, "\tnop\n"); \
1303 fprintf (FILE, "\t.quad 0,0\n"); \
1306 /* Section in which to place the trampoline. On Alpha, instructions
1307 may only be placed in a text segment. */
1309 #define TRAMPOLINE_SECTION text_section
1311 /* Length in units of the trampoline for entering a nested function. */
1313 #define TRAMPOLINE_SIZE 32
1315 /* Emit RTL insns to initialize the variable parts of a trampoline.
1316 FNADDR is an RTX for the address of the function's pure code.
1317 CXT is an RTX for the static chain value for the function. */
1319 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1320 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1322 /* A C expression whose value is RTL representing the value of the return
1323 address for the frame COUNT steps up from the current frame.
1324 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1325 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1327 #define RETURN_ADDR_RTX alpha_return_addr
1329 /* Before the prologue, RA lives in $26. */
1330 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1331 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1333 /* Addressing modes, and classification of registers for them. */
1335 /* #define HAVE_POST_INCREMENT 0 */
1336 /* #define HAVE_POST_DECREMENT 0 */
1338 /* #define HAVE_PRE_DECREMENT 0 */
1339 /* #define HAVE_PRE_INCREMENT 0 */
1341 /* Macros to check register numbers against specific register classes. */
1343 /* These assume that REGNO is a hard or pseudo reg number.
1344 They give nonzero only if REGNO is a hard reg of the suitable class
1345 or a pseudo reg currently allocated to a suitable hard reg.
1346 Since they use reg_renumber, they are safe only once reg_renumber
1347 has been allocated, which happens in local-alloc.c. */
1349 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1350 #define REGNO_OK_FOR_BASE_P(REGNO) \
1351 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1352 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1354 /* Maximum number of registers that can appear in a valid memory address. */
1355 #define MAX_REGS_PER_ADDRESS 1
1357 /* Recognize any constant value that is a valid address. For the Alpha,
1358 there are only constants none since we want to use LDA to load any
1359 symbolic addresses into registers. */
1361 #define CONSTANT_ADDRESS_P(X) \
1362 (GET_CODE (X) == CONST_INT \
1363 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1365 /* Include all constant integers and constant doubles, but not
1366 floating-point, except for floating-point zero. */
1368 #define LEGITIMATE_CONSTANT_P(X) \
1369 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1370 || (X) == CONST0_RTX (GET_MODE (X)))
1372 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1373 and check its validity for a certain class.
1374 We have two alternate definitions for each of them.
1375 The usual definition accepts all pseudo regs; the other rejects
1376 them unless they have been allocated suitable hard regs.
1377 The symbol REG_OK_STRICT causes the latter definition to be used.
1379 Most source files want to accept pseudo regs in the hope that
1380 they will get allocated to the class that the insn wants them to be in.
1381 Source files for reload pass need to be strict.
1382 After reload, it makes no difference, since pseudo regs have
1383 been eliminated by then. */
1385 #ifndef REG_OK_STRICT
1387 /* Nonzero if X is a hard reg that can be used as an index
1388 or if it is a pseudo reg. */
1389 #define REG_OK_FOR_INDEX_P(X) 0
1391 /* Nonzero if X is a hard reg that can be used as a base reg
1392 or if it is a pseudo reg. */
1393 #define REG_OK_FOR_BASE_P(X) \
1394 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1396 /* ??? Nonzero if X is the frame pointer, or some virtual register
1397 that may eliminate to the frame pointer. These will be allowed to
1398 have offsets greater than 32K. This is done because register
1399 elimination offsets will change the hi/lo split, and if we split
1400 before reload, we will require additional instructions. */
1401 #define REG_OK_FP_BASE_P(X) \
1402 (REGNO (X) == 31 || REGNO (X) == 63 \
1403 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1404 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1408 /* Nonzero if X is a hard reg that can be used as an index. */
1409 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1411 /* Nonzero if X is a hard reg that can be used as a base reg. */
1412 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1414 #define REG_OK_FP_BASE_P(X) 0
1418 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1419 that is a valid memory address for an instruction.
1420 The MODE argument is the machine mode for the MEM expression
1421 that wants to use this address.
1423 For Alpha, we have either a constant address or the sum of a register
1424 and a constant address, or just a register. For DImode, any of those
1425 forms can be surrounded with an AND that clear the low-order three bits;
1426 this is an "unaligned" access.
1428 First define the basic valid address. */
1430 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1433 if (GET_CODE (tmp) == SUBREG \
1434 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1435 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1436 tmp = SUBREG_REG (tmp); \
1437 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1439 if (CONSTANT_ADDRESS_P (X)) \
1441 if (GET_CODE (X) == PLUS) \
1443 tmp = XEXP (X, 0); \
1444 if (GET_CODE (tmp) == SUBREG \
1445 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1446 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1447 tmp = SUBREG_REG (tmp); \
1450 if (REG_OK_FP_BASE_P (tmp) \
1451 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1453 if (REG_OK_FOR_BASE_P (tmp) \
1454 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1457 else if (GET_CODE (tmp) == ADDRESSOF \
1458 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1463 /* Now accept the simple address, or, for DImode only, an AND of a simple
1464 address that turns off the low three bits. */
1466 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1467 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1468 if ((MODE) == DImode \
1469 && GET_CODE (X) == AND \
1470 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1471 && INTVAL (XEXP (X, 1)) == -8) \
1472 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1475 /* Try machine-dependent ways of modifying an illegitimate address
1476 to be legitimate. If we find one, return the new, valid address.
1477 This macro is used in only one place: `memory_address' in explow.c.
1479 OLDX is the address as it was before break_out_memory_refs was called.
1480 In some cases it is useful to look at this to decide what needs to be done.
1482 MODE and WIN are passed so that this macro can use
1483 GO_IF_LEGITIMATE_ADDRESS.
1485 It is always safe for this macro to do nothing. It exists to recognize
1486 opportunities to optimize the output.
1488 For the Alpha, there are three cases we handle:
1490 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1491 valid offset, compute the high part of the constant and add it to the
1492 register. Then our address is (plus temp low-part-const).
1493 (2) If the address is (const (plus FOO const_int)), find the low-order
1494 part of the CONST_INT. Then load FOO plus any high-order part of the
1495 CONST_INT into a register. Our address is (plus reg low-part-const).
1496 This is done to reduce the number of GOT entries.
1497 (3) If we have a (plus reg const), emit the load as in (2), then add
1498 the two registers, and finally generate (plus reg low-part-const) as
1501 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1502 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1503 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1504 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1506 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1507 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1508 HOST_WIDE_INT highpart = val - lowpart; \
1509 rtx high = GEN_INT (highpart); \
1510 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1511 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1513 (X) = plus_constant (temp, lowpart); \
1516 else if (GET_CODE (X) == CONST \
1517 && GET_CODE (XEXP (X, 0)) == PLUS \
1518 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1520 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1521 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1522 HOST_WIDE_INT highpart = val - lowpart; \
1523 rtx high = XEXP (XEXP (X, 0), 0); \
1526 high = plus_constant (high, highpart); \
1528 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1531 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1532 && GET_CODE (XEXP (X, 1)) == CONST \
1533 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1534 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1536 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1537 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1538 HOST_WIDE_INT highpart = val - lowpart; \
1539 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1542 high = plus_constant (high, highpart); \
1544 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1545 force_reg (Pmode, high), \
1546 high, 1, OPTAB_LIB_WIDEN); \
1547 (X) = plus_constant (high, lowpart); \
1552 /* Try a machine-dependent way of reloading an illegitimate address
1553 operand. If we find one, push the reload and jump to WIN. This
1554 macro is used in only one place: `find_reloads_address' in reload.c.
1556 For the Alpha, we wish to handle large displacements off a base
1557 register by splitting the addend across an ldah and the mem insn.
1558 This cuts number of extra insns needed from 3 to 1. */
1560 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1562 /* We must recognize output that we have already generated ourselves. */ \
1563 if (GET_CODE (X) == PLUS \
1564 && GET_CODE (XEXP (X, 0)) == PLUS \
1565 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1566 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1567 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1569 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1570 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1574 if (GET_CODE (X) == PLUS \
1575 && GET_CODE (XEXP (X, 0)) == REG \
1576 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1577 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1578 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1580 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1581 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1582 HOST_WIDE_INT high \
1583 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1585 /* Check for 32-bit overflow. */ \
1586 if (high + low != val) \
1589 /* Reload the high part into a base reg; leave the low part \
1590 in the mem directly. */ \
1592 X = gen_rtx_PLUS (GET_MODE (X), \
1593 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1597 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1598 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1604 /* Go to LABEL if ADDR (a legitimate address expression)
1605 has an effect that depends on the machine mode it is used for.
1606 On the Alpha this is true only for the unaligned modes. We can
1607 simplify this test since we know that the address must be valid. */
1609 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1610 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1612 /* Compute the cost of an address. For the Alpha, all valid addresses are
1615 #define ADDRESS_COST(X) 0
1617 /* Machine-dependent reorg pass. */
1618 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1620 /* Specify the machine mode that this machine uses
1621 for the index in the tablejump instruction. */
1622 #define CASE_VECTOR_MODE SImode
1624 /* Define as C expression which evaluates to nonzero if the tablejump
1625 instruction expects the table to contain offsets from the address of the
1628 Do not define this if the table should contain absolute addresses.
1629 On the Alpha, the table is really GP-relative, not relative to the PC
1630 of the table, but we pretend that it is PC-relative; this should be OK,
1631 but we should try to find some better way sometime. */
1632 #define CASE_VECTOR_PC_RELATIVE 1
1634 /* Specify the tree operation to be used to convert reals to integers. */
1635 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1637 /* This is the kind of divide that is easiest to do in the general case. */
1638 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1640 /* Define this as 1 if `char' should by default be signed; else as 0. */
1641 #define DEFAULT_SIGNED_CHAR 1
1643 /* This flag, if defined, says the same insns that convert to a signed fixnum
1644 also convert validly to an unsigned one.
1646 We actually lie a bit here as overflow conditions are different. But
1647 they aren't being checked anyway. */
1649 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1651 /* Max number of bytes we can move to or from memory
1652 in one reasonably fast instruction. */
1656 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1657 move-instruction pairs, we will do a movstr or libcall instead.
1659 Without byte/word accesses, we want no more than four instructions;
1660 with, several single byte accesses are better. */
1662 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1664 /* Largest number of bytes of an object that can be placed in a register.
1665 On the Alpha we have plenty of registers, so use TImode. */
1666 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1668 /* Nonzero if access to memory by bytes is no faster than for words.
1669 Also non-zero if doing byte operations (specifically shifts) in registers
1672 On the Alpha, we want to not use the byte operation and instead use
1673 masking operations to access fields; these will save instructions. */
1675 #define SLOW_BYTE_ACCESS 1
1677 /* Define if operations between registers always perform the operation
1678 on the full register even if a narrower mode is specified. */
1679 #define WORD_REGISTER_OPERATIONS
1681 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1682 will either zero-extend or sign-extend. The value of this macro should
1683 be the code that says which one of the two operations is implicitly
1684 done, NIL if none. */
1685 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1687 /* Define if loading short immediate values into registers sign extends. */
1688 #define SHORT_IMMEDIATES_SIGN_EXTEND
1690 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1691 is done just by pretending it is already truncated. */
1692 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1694 /* We assume that the store-condition-codes instructions store 0 for false
1695 and some other value for true. This is the value stored for true. */
1697 #define STORE_FLAG_VALUE 1
1699 /* Define the value returned by a floating-point comparison instruction. */
1701 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1702 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1704 /* Canonicalize a comparison from one we don't have to one we do have. */
1706 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1708 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1709 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1714 (CODE) = swap_condition (CODE); \
1716 if (((CODE) == LT || (CODE) == LTU) \
1717 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1719 (CODE) = (CODE) == LT ? LE : LEU; \
1720 (OP1) = GEN_INT (255); \
1724 /* Specify the machine mode that pointers have.
1725 After generation of rtl, the compiler makes no further distinction
1726 between pointers and any other objects of this machine mode. */
1727 #define Pmode DImode
1729 /* Mode of a function address in a call instruction (for indexing purposes). */
1731 #define FUNCTION_MODE Pmode
1733 /* Define this if addresses of constant functions
1734 shouldn't be put through pseudo regs where they can be cse'd.
1735 Desirable on machines where ordinary constants are expensive
1736 but a CALL with constant address is cheap.
1738 We define this on the Alpha so that gen_call and gen_call_value
1739 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1740 then copy it into a register, thus actually letting the address be
1743 #define NO_FUNCTION_CSE
1745 /* Define this to be nonzero if shift instructions ignore all but the low-order
1747 #define SHIFT_COUNT_TRUNCATED 1
1749 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1750 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1752 /* Describe the fact that MULTI instructions are multiple instructions
1753 and so to assume they don't pair with anything. */
1754 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1755 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1756 (CAN_ISSUE_MORE) = 0
1758 /* Compute the cost of computing a constant rtl expression RTX
1759 whose rtx-code is CODE. The body of this macro is a portion
1760 of a switch statement. If the code is computed here,
1761 return it with a return statement. Otherwise, break from the switch.
1763 If this is an 8-bit constant, return zero since it can be used
1764 nearly anywhere with no cost. If it is a valid operand for an
1765 ADD or AND, likewise return 0 if we know it will be used in that
1766 context. Otherwise, return 2 since it might be used there later.
1767 All other constants take at least two insns. */
1769 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1771 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1773 case CONST_DOUBLE: \
1774 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1776 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1777 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1779 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1782 return COSTS_N_INSNS (2); \
1786 switch (alpha_cpu) \
1788 case PROCESSOR_EV4: \
1789 return COSTS_N_INSNS (3); \
1790 case PROCESSOR_EV5: \
1791 case PROCESSOR_EV6: \
1792 return COSTS_N_INSNS (2); \
1796 /* Provide the costs of a rtl expression. This is in the body of a
1799 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1800 case PLUS: case MINUS: \
1801 if (FLOAT_MODE_P (GET_MODE (X))) \
1802 switch (alpha_cpu) \
1804 case PROCESSOR_EV4: \
1805 return COSTS_N_INSNS (6); \
1806 case PROCESSOR_EV5: \
1807 case PROCESSOR_EV6: \
1808 return COSTS_N_INSNS (4); \
1811 else if (GET_CODE (XEXP (X, 0)) == MULT \
1812 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1813 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1814 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1817 switch (alpha_cpu) \
1819 case PROCESSOR_EV4: \
1820 if (FLOAT_MODE_P (GET_MODE (X))) \
1821 return COSTS_N_INSNS (6); \
1822 return COSTS_N_INSNS (23); \
1823 case PROCESSOR_EV5: \
1824 if (FLOAT_MODE_P (GET_MODE (X))) \
1825 return COSTS_N_INSNS (4); \
1826 else if (GET_MODE (X) == DImode) \
1827 return COSTS_N_INSNS (12); \
1829 return COSTS_N_INSNS (8); \
1830 case PROCESSOR_EV6: \
1831 if (FLOAT_MODE_P (GET_MODE (X))) \
1832 return COSTS_N_INSNS (4); \
1834 return COSTS_N_INSNS (7); \
1838 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1839 && INTVAL (XEXP (X, 1)) <= 3) \
1841 /* ... fall through ... */ \
1842 case ASHIFTRT: case LSHIFTRT: \
1843 switch (alpha_cpu) \
1845 case PROCESSOR_EV4: \
1846 return COSTS_N_INSNS (2); \
1847 case PROCESSOR_EV5: \
1848 case PROCESSOR_EV6: \
1849 return COSTS_N_INSNS (1); \
1852 case IF_THEN_ELSE: \
1853 switch (alpha_cpu) \
1855 case PROCESSOR_EV4: \
1856 case PROCESSOR_EV6: \
1857 return COSTS_N_INSNS (2); \
1858 case PROCESSOR_EV5: \
1859 return COSTS_N_INSNS (1); \
1862 case DIV: case UDIV: case MOD: case UMOD: \
1863 switch (alpha_cpu) \
1865 case PROCESSOR_EV4: \
1866 if (GET_MODE (X) == SFmode) \
1867 return COSTS_N_INSNS (34); \
1868 else if (GET_MODE (X) == DFmode) \
1869 return COSTS_N_INSNS (63); \
1871 return COSTS_N_INSNS (70); \
1872 case PROCESSOR_EV5: \
1873 if (GET_MODE (X) == SFmode) \
1874 return COSTS_N_INSNS (15); \
1875 else if (GET_MODE (X) == DFmode) \
1876 return COSTS_N_INSNS (22); \
1878 return COSTS_N_INSNS (70); /* ??? */ \
1879 case PROCESSOR_EV6: \
1880 if (GET_MODE (X) == SFmode) \
1881 return COSTS_N_INSNS (12); \
1882 else if (GET_MODE (X) == DFmode) \
1883 return COSTS_N_INSNS (15); \
1885 return COSTS_N_INSNS (70); /* ??? */ \
1889 switch (alpha_cpu) \
1891 case PROCESSOR_EV4: \
1892 case PROCESSOR_EV6: \
1893 return COSTS_N_INSNS (3); \
1894 case PROCESSOR_EV5: \
1895 return COSTS_N_INSNS (2); \
1898 case NEG: case ABS: \
1899 if (! FLOAT_MODE_P (GET_MODE (X))) \
1901 /* ... fall through ... */ \
1902 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1903 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1904 switch (alpha_cpu) \
1906 case PROCESSOR_EV4: \
1907 return COSTS_N_INSNS (6); \
1908 case PROCESSOR_EV5: \
1909 case PROCESSOR_EV6: \
1910 return COSTS_N_INSNS (4); \
1914 /* Control the assembler format that we output. */
1916 /* We don't emit these labels, so as to avoid getting linker errors about
1917 missing exception handling info. If we emit a gcc_compiled. label into
1918 text, and the file has no code, then the DEC assembler gives us a zero
1919 sized text section with no associated exception handling info. The
1920 DEC linker sees this text section, and gives a warning saying that
1921 the exception handling info is missing. */
1922 #define ASM_IDENTIFY_GCC(x)
1923 #define ASM_IDENTIFY_LANGUAGE(x)
1925 /* Output to assembler file text saying following lines
1926 may contain character constants, extra white space, comments, etc. */
1928 #define ASM_APP_ON ""
1930 /* Output to assembler file text saying following lines
1931 no longer contain unusual constructs. */
1933 #define ASM_APP_OFF ""
1935 #define TEXT_SECTION_ASM_OP ".text"
1937 /* Output before read-only data. */
1939 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1941 /* Output before writable data. */
1943 #define DATA_SECTION_ASM_OP ".data"
1945 /* Define an extra section for read-only data, a routine to enter it, and
1946 indicate that it is for read-only data.
1948 The first time we enter the readonly data section for a file, we write
1949 eight bytes of zero. This works around a bug in DEC's assembler in
1950 some versions of OSF/1 V3.x. */
1952 #define EXTRA_SECTIONS readonly_data
1954 #define EXTRA_SECTION_FUNCTIONS \
1956 literal_section () \
1958 if (in_section != readonly_data) \
1960 static int firsttime = 1; \
1962 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1966 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1969 in_section = readonly_data; \
1973 #define READONLY_DATA_SECTION literal_section
1975 /* If we are referencing a function that is static, make the SYMBOL_REF
1976 special. We use this to see indicate we can branch to this function
1977 without setting PV or restoring GP. */
1979 #define ENCODE_SECTION_INFO(DECL) \
1980 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1981 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1983 /* How to refer to registers in assembler output.
1984 This sequence is indexed by compiler's hard-register-number (see above). */
1986 #define REGISTER_NAMES \
1987 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1988 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1989 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1990 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1991 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1992 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1993 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1994 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1996 /* How to renumber registers for dbx and gdb. */
1998 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2000 /* This is how to output the definition of a user-level label named NAME,
2001 such as the label on a static function or variable NAME. */
2003 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2004 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2006 /* This is how to output a command to make the user-level label named NAME
2007 defined for reference from other files. */
2009 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2010 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2012 /* The prefix to add to user-visible assembler symbols. */
2014 #define USER_LABEL_PREFIX ""
2016 /* This is how to output an internal numbered label where
2017 PREFIX is the class of label and NUM is the number within the class. */
2019 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2020 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2022 /* This is how to output a label for a jump table. Arguments are the same as
2023 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2026 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2027 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2029 /* This is how to store into the string LABEL
2030 the symbol_ref name of an internal numbered label where
2031 PREFIX is the class of label and NUM is the number within the class.
2032 This is suitable for output with `assemble_name'. */
2034 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2035 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2037 /* Check a floating-point value for validity for a particular machine mode. */
2039 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2040 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2042 /* This is how to output an assembler line defining a `long double'
2045 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2048 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2049 fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \
2050 t[1] & 0xffffffff, t[0] & 0xffffffff, \
2051 t[3] & 0xffffffff, t[2] & 0xffffffff); \
2054 /* This is how to output an assembler line defining a `double' constant. */
2056 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2059 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2060 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2061 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2064 /* This is how to output an assembler line defining a `float' constant. */
2066 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2069 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2070 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2073 /* This is how to output an assembler line defining an `int' constant. */
2075 #define ASM_OUTPUT_INT(FILE,VALUE) \
2076 ( fprintf (FILE, "\t.long "), \
2077 output_addr_const (FILE, (VALUE)), \
2078 fprintf (FILE, "\n"))
2080 /* This is how to output an assembler line defining a `long' constant. */
2082 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2083 ( fprintf (FILE, "\t.quad "), \
2084 output_addr_const (FILE, (VALUE)), \
2085 fprintf (FILE, "\n"))
2087 /* Likewise for `char' and `short' constants. */
2089 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2090 fprintf (FILE, "\t.word %d\n", \
2091 (int)(GET_CODE (VALUE) == CONST_INT \
2092 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2094 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2095 fprintf (FILE, "\t.byte %d\n", \
2096 (int)(GET_CODE (VALUE) == CONST_INT \
2097 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2099 /* We use the default ASCII-output routine, except that we don't write more
2100 than 50 characters since the assembler doesn't support very long lines. */
2102 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2104 FILE *_hide_asm_out_file = (MYFILE); \
2105 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
2106 int _hide_thissize = (MYLENGTH); \
2107 int _size_so_far = 0; \
2109 FILE *asm_out_file = _hide_asm_out_file; \
2110 const unsigned char *p = _hide_p; \
2111 int thissize = _hide_thissize; \
2113 fprintf (asm_out_file, "\t.ascii \""); \
2115 for (i = 0; i < thissize; i++) \
2117 register int c = p[i]; \
2119 if (_size_so_far ++ > 50 && i < thissize - 4) \
2120 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2122 if (c == '\"' || c == '\\') \
2123 putc ('\\', asm_out_file); \
2124 if (c >= ' ' && c < 0177) \
2125 putc (c, asm_out_file); \
2128 fprintf (asm_out_file, "\\%o", c); \
2129 /* After an octal-escape, if a digit follows, \
2130 terminate one string constant and start another. \
2131 The Vax assembler fails to stop reading the escape \
2132 after three digits, so this is the only way we \
2133 can get it to parse the data properly. */ \
2134 if (i < thissize - 1 \
2135 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2136 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2139 fprintf (asm_out_file, "\"\n"); \
2144 /* To get unaligned data, we have to turn off auto alignment. */
2145 #define UNALIGNED_SHORT_ASM_OP ".align 0\n\t.word"
2146 #define UNALIGNED_INT_ASM_OP ".align 0\n\t.long"
2147 #define UNALIGNED_DOUBLE_INT_ASM_OP ".align 0\n\t.quad"
2149 /* This is how to output an insn to push a register on the stack.
2150 It need not be very fast code. */
2152 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2153 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2154 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2157 /* This is how to output an insn to pop a register from the stack.
2158 It need not be very fast code. */
2160 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2161 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2162 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2165 /* This is how to output an assembler line for a numeric constant byte. */
2167 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2168 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2170 /* This is how to output an element of a case-vector that is absolute.
2171 (Alpha does not use such vectors, but we must define this macro anyway.) */
2173 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2175 /* This is how to output an element of a case-vector that is relative. */
2177 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2178 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2181 /* This is how to output an assembler line
2182 that says to advance the location counter
2183 to a multiple of 2**LOG bytes. */
2185 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2187 fprintf (FILE, "\t.align %d\n", LOG);
2189 /* This is how to advance the location counter by SIZE bytes. */
2191 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2192 fprintf (FILE, "\t.space %d\n", (SIZE))
2194 /* This says how to output an assembler line
2195 to define a global common symbol. */
2197 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2198 ( fputs ("\t.comm ", (FILE)), \
2199 assemble_name ((FILE), (NAME)), \
2200 fprintf ((FILE), ",%d\n", (SIZE)))
2202 /* This says how to output an assembler line
2203 to define a local common symbol. */
2205 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2206 ( fputs ("\t.lcomm ", (FILE)), \
2207 assemble_name ((FILE), (NAME)), \
2208 fprintf ((FILE), ",%d\n", (SIZE)))
2210 /* Store in OUTPUT a string (made with alloca) containing
2211 an assembler-name for a local static variable named NAME.
2212 LABELNO is an integer which is different for each call. */
2214 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2215 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2216 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2218 /* Define the parentheses used to group arithmetic operations
2219 in assembler code. */
2221 #define ASM_OPEN_PAREN "("
2222 #define ASM_CLOSE_PAREN ")"
2224 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2225 Used for C++ multiple inheritance. */
2227 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2229 const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2232 /* Mark end of prologue. */ \
2233 output_end_prologue (FILE); \
2235 /* Rely on the assembler to macro expand a large delta. */ \
2236 fprintf (FILE, "\t.set at\n"); \
2237 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2238 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2240 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \
2243 fprintf (FILE, "\tbr $31,$"); \
2244 assemble_name (FILE, fn_name); \
2245 fprintf (FILE, "..ng\n"); \
2249 fprintf (FILE, "\tjmp $31,"); \
2250 assemble_name (FILE, fn_name); \
2251 fputc ('\n', FILE); \
2253 fprintf (FILE, "\t.set noat\n"); \
2257 /* Define results of standard character escape sequences. */
2258 #define TARGET_BELL 007
2259 #define TARGET_BS 010
2260 #define TARGET_TAB 011
2261 #define TARGET_NEWLINE 012
2262 #define TARGET_VT 013
2263 #define TARGET_FF 014
2264 #define TARGET_CR 015
2266 /* Print operand X (an rtx) in assembler syntax to file FILE.
2267 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2268 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2270 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2272 /* Determine which codes are valid without a following integer. These must
2273 not be alphabetic (the characters are chosen so that
2274 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2277 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2278 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2279 mode. alpha_fprm controls which suffix is generated.
2281 ' Generates trap-mode suffix for instructions that accept the
2282 su suffix only (cmpt et al).
2284 ` Generates trap-mode suffix for instructions that accept the
2285 v and sv suffix. The only instruction that needs this is cvtql.
2287 ( Generates trap-mode suffix for instructions that accept the
2288 v, sv, and svi suffix. The only instruction that needs this
2291 ) Generates trap-mode suffix for instructions that accept the
2292 u, su, and sui suffix. This is the bulk of the IEEE floating
2293 point instructions (addt et al).
2295 + Generates trap-mode suffix for instructions that accept the
2296 sui suffix (cvtqt and cvtqs).
2298 , Generates single precision suffix for floating point
2299 instructions (s for IEEE, f for VAX)
2301 - Generates double precision suffix for floating point
2302 instructions (t for IEEE, g for VAX)
2305 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2306 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2307 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2309 /* Print a memory address as an operand to reference that memory location. */
2311 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2312 print_operand_address((FILE), (ADDR))
2314 /* Define the codes that are matched by predicates in alpha.c. */
2316 #define PREDICATE_CODES \
2317 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2318 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2319 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2320 {"cint8_operand", {CONST_INT}}, \
2321 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2322 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2323 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2324 {"const48_operand", {CONST_INT}}, \
2325 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2326 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2327 {"mode_mask_operand", {CONST_INT}}, \
2328 {"mul8_operand", {CONST_INT}}, \
2329 {"mode_width_operand", {CONST_INT}}, \
2330 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2331 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2332 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2333 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2334 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2335 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2336 {"fp0_operand", {CONST_DOUBLE}}, \
2337 {"current_file_function_operand", {SYMBOL_REF}}, \
2338 {"call_operand", {REG, SYMBOL_REF}}, \
2339 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2340 SYMBOL_REF, CONST, LABEL_REF}}, \
2341 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2342 SYMBOL_REF, CONST, LABEL_REF}}, \
2343 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2344 {"aligned_memory_operand", {MEM}}, \
2345 {"unaligned_memory_operand", {MEM}}, \
2346 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2347 {"any_memory_operand", {MEM}}, \
2348 {"hard_fp_register_operand", {SUBREG, REG}}, \
2349 {"reg_not_elim_operand", {SUBREG, REG}}, \
2350 {"reg_no_subreg_operand", {REG}}, \
2351 {"addition_operation", {PLUS}},
2353 /* Define the `__builtin_va_list' type for the ABI. */
2354 #define BUILD_VA_LIST_TYPE(VALIST) \
2355 (VALIST) = alpha_build_va_list ()
2357 /* Implement `va_start' for varargs and stdarg. */
2358 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2359 alpha_va_start (stdarg, valist, nextarg)
2361 /* Implement `va_arg'. */
2362 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2363 alpha_va_arg (valist, type)
2365 /* Tell collect that the object format is ECOFF. */
2366 #define OBJECT_FORMAT_COFF
2367 #define EXTENDED_COFF
2369 /* If we use NM, pass -g to it so it only lists globals. */
2370 #define NM_FLAGS "-pg"
2372 /* Definitions for debugging. */
2374 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2375 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2376 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2378 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2379 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2383 /* Correct the offset of automatic variables and arguments. Note that
2384 the Alpha debug format wants all automatic variables and arguments
2385 to be in terms of two different offsets from the virtual frame pointer,
2386 which is the stack pointer before any adjustment in the function.
2387 The offset for the argument pointer is fixed for the native compiler,
2388 it is either zero (for the no arguments case) or large enough to hold
2389 all argument registers.
2390 The offset for the auto pointer is the fourth argument to the .frame
2391 directive (local_offset).
2392 To stay compatible with the native tools we use the same offsets
2393 from the virtual frame pointer and adjust the debugger arg/auto offsets
2394 accordingly. These debugger offsets are set up in output_prolog. */
2396 extern long alpha_arg_offset;
2397 extern long alpha_auto_offset;
2398 #define DEBUGGER_AUTO_OFFSET(X) \
2399 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2400 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2403 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2404 alpha_output_lineno (STREAM, LINE)
2406 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2407 alpha_output_filename (STREAM, NAME)
2409 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2410 number, because the real length runs past this up to the next
2411 continuation point. This is really a dbxout.c bug. */
2412 #define DBX_CONTIN_LENGTH 3000
2414 /* By default, turn on GDB extensions. */
2415 #define DEFAULT_GDB_EXTENSIONS 1
2417 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2418 #define NO_DBX_FUNCTION_END 1
2420 /* If we are smuggling stabs through the ALPHA ECOFF object
2421 format, put a comment in front of the .stab<x> operation so
2422 that the ALPHA assembler does not choke. The mips-tfile program
2423 will correctly put the stab into the object file. */
2425 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2426 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2427 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2429 /* Forward references to tags are allowed. */
2430 #define SDB_ALLOW_FORWARD_REFERENCES
2432 /* Unknown tags are also allowed. */
2433 #define SDB_ALLOW_UNKNOWN_REFERENCES
2435 #define PUT_SDB_DEF(a) \
2437 fprintf (asm_out_file, "\t%s.def\t", \
2438 (TARGET_GAS) ? "" : "#"); \
2439 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2440 fputc (';', asm_out_file); \
2443 #define PUT_SDB_PLAIN_DEF(a) \
2445 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2446 (TARGET_GAS) ? "" : "#", (a)); \
2449 #define PUT_SDB_TYPE(a) \
2451 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2454 /* For block start and end, we create labels, so that
2455 later we can figure out where the correct offset is.
2456 The normal .ent/.end serve well enough for functions,
2457 so those are just commented out. */
2459 extern int sdb_label_count; /* block start/end next label # */
2461 #define PUT_SDB_BLOCK_START(LINE) \
2463 fprintf (asm_out_file, \
2464 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2466 (TARGET_GAS) ? "" : "#", \
2469 sdb_label_count++; \
2472 #define PUT_SDB_BLOCK_END(LINE) \
2474 fprintf (asm_out_file, \
2475 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2477 (TARGET_GAS) ? "" : "#", \
2480 sdb_label_count++; \
2483 #define PUT_SDB_FUNCTION_START(LINE)
2485 #define PUT_SDB_FUNCTION_END(LINE)
2487 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2489 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2490 mips-tdump.c to print them out.
2492 These must match the corresponding definitions in gdb/mipsread.c.
2493 Unfortunately, gcc and gdb do not currently share any directories. */
2495 #define CODE_MASK 0x8F300
2496 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2497 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2498 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2500 /* Override some mips-tfile definitions. */
2502 #define SHASH_SIZE 511
2503 #define THASH_SIZE 55
2505 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2507 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2509 /* The linker will stick __main into the .init section. */
2510 #define HAS_INIT_SECTION
2511 #define LD_INIT_SWITCH "-init"
2512 #define LD_FINI_SWITCH "-fini"
2514 /* The system headers under Alpha systems are generally C++-aware. */
2515 #define NO_IMPLICIT_EXTERN_C
2517 /* Generate calls to memcpy, etc., not bcopy, etc. */
2518 #define TARGET_MEM_FUNCTIONS 1