1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Write out the correct language type definition for the header files.
25 Unless we have assembler language, write out the symbols for C. */
28 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
29 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
30 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
31 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
33 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
34 %(cpp_cpu) %(cpp_subtarget)"
36 #ifndef CPP_SUBTARGET_SPEC
37 #define CPP_SUBTARGET_SPEC ""
40 /* Set the spec to use for signed char. The default tests the above macro
41 but DEC's compiler can't handle the conditional in a "constant"
44 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
46 #define WORD_SWITCH_TAKES_ARG(STR) \
47 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
49 /* Print subsidiary information on the compiler version in use. */
50 #define TARGET_VERSION
52 /* Run-time compilation parameters selecting different hardware subsets. */
54 /* Which processor to schedule for. The cpu attribute defines a list that
55 mirrors this list, so changes to alpha.md must be made at the same time. */
58 {PROCESSOR_EV4, /* 2106[46]{a,} */
59 PROCESSOR_EV5, /* 21164{a,pc,} */
60 PROCESSOR_EV6}; /* 21264 */
62 extern enum processor_type alpha_cpu;
64 enum alpha_trap_precision
66 ALPHA_TP_PROG, /* No precision (default). */
67 ALPHA_TP_FUNC, /* Trap contained within originating function. */
68 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
71 enum alpha_fp_rounding_mode
73 ALPHA_FPRM_NORM, /* Normal rounding mode. */
74 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
75 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
76 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
79 enum alpha_fp_trap_mode
81 ALPHA_FPTM_N, /* Normal trap mode. */
82 ALPHA_FPTM_U, /* Underflow traps enabled. */
83 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
84 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
87 extern int target_flags;
89 extern enum alpha_trap_precision alpha_tp;
90 extern enum alpha_fp_rounding_mode alpha_fprm;
91 extern enum alpha_fp_trap_mode alpha_fptm;
93 /* This means that floating-point support exists in the target implementation
94 of the Alpha architecture. This is usually the default. */
95 #define MASK_FP (1 << 0)
96 #define TARGET_FP (target_flags & MASK_FP)
98 /* This means that floating-point registers are allowed to be used. Note
99 that Alpha implementations without FP operations are required to
100 provide the FP registers. */
102 #define MASK_FPREGS (1 << 1)
103 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
105 /* This means that gas is used to process the assembler file. */
107 #define MASK_GAS (1 << 2)
108 #define TARGET_GAS (target_flags & MASK_GAS)
110 /* This means that we should mark procedures as IEEE conformant. */
112 #define MASK_IEEE_CONFORMANT (1 << 3)
113 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
115 /* This means we should be IEEE-compliant except for inexact. */
117 #define MASK_IEEE (1 << 4)
118 #define TARGET_IEEE (target_flags & MASK_IEEE)
120 /* This means we should be fully IEEE-compliant. */
122 #define MASK_IEEE_WITH_INEXACT (1 << 5)
123 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
125 /* This means we must construct all constants rather than emitting
126 them as literal data. */
128 #define MASK_BUILD_CONSTANTS (1 << 6)
129 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
131 /* This means we handle floating points in VAX F- (float)
132 or G- (double) Format. */
134 #define MASK_FLOAT_VAX (1 << 7)
135 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
137 /* This means that the processor has byte and half word loads and stores
138 (the BWX extension). */
140 #define MASK_BWX (1 << 8)
141 #define TARGET_BWX (target_flags & MASK_BWX)
143 /* This means that the processor has the MAX extension. */
144 #define MASK_MAX (1 << 9)
145 #define TARGET_MAX (target_flags & MASK_MAX)
147 /* This means that the processor has the FIX extension. */
148 #define MASK_FIX (1 << 10)
149 #define TARGET_FIX (target_flags & MASK_FIX)
151 /* This means that the processor has the CIX extension. */
152 #define MASK_CIX (1 << 11)
153 #define TARGET_CIX (target_flags & MASK_CIX)
155 /* This means that the processor is an EV5, EV56, or PCA56.
156 Unlike alpha_cpu this is not affected by -mtune= setting. */
157 #define MASK_CPU_EV5 (1 << 28)
158 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
160 /* Likewise for EV6. */
161 #define MASK_CPU_EV6 (1 << 29)
162 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
164 /* This means we support the .arch directive in the assembler. Only
165 defined in TARGET_CPU_DEFAULT. */
166 #define MASK_SUPPORT_ARCH (1 << 30)
167 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
169 /* These are for target os support and cannot be changed at runtime. */
170 #ifndef TARGET_WINDOWS_NT
171 #define TARGET_WINDOWS_NT 0
173 #ifndef TARGET_OPEN_VMS
174 #define TARGET_OPEN_VMS 0
177 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
178 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
180 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
181 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
183 #ifndef TARGET_HAS_XFLOATING_LIBS
184 #define TARGET_HAS_XFLOATING_LIBS 0
186 #ifndef TARGET_PROFILING_NEEDS_GP
187 #define TARGET_PROFILING_NEEDS_GP 0
190 /* Macro to define tables used to set the flags.
191 This is a list in braces of pairs in braces,
192 each pair being { "NAME", VALUE }
193 where VALUE is the bits to set or minus the bits to clear.
194 An empty string NAME is used to identify the default VALUE. */
196 #define TARGET_SWITCHES \
197 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
198 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
199 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
200 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
201 N_("Do not use fp registers")}, \
202 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
203 {"gas", MASK_GAS, N_("Assume GAS")}, \
204 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
205 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
206 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
207 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
208 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
209 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
210 {"build-constants", MASK_BUILD_CONSTANTS, \
211 N_("Do not emit complex integer constants to read-only memory")}, \
212 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
213 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
214 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
215 {"no-bwx", -MASK_BWX, ""}, \
217 N_("Emit code for the motion video ISA extension")}, \
218 {"no-max", -MASK_MAX, ""}, \
220 N_("Emit code for the fp move and sqrt ISA extension")}, \
221 {"no-fix", -MASK_FIX, ""}, \
222 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
223 {"no-cix", -MASK_CIX, ""}, \
224 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
226 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
228 #ifndef TARGET_CPU_DEFAULT
229 #define TARGET_CPU_DEFAULT 0
232 /* This macro is similar to `TARGET_SWITCHES' but defines names of
233 command options that have values. Its definition is an initializer
234 with a subgrouping for each command option.
236 Each subgrouping contains a string constant, that defines the fixed
237 part of the option name, and the address of a variable. The
238 variable, type `char *', is set to the variable part of the given
239 option if the fixed part matches. The actual option name is made
240 by appending `-m' to the specified name.
242 Here is an example which defines `-mshort-data-NUMBER'. If the
243 given option is `-mshort-data-512', the variable `m88k_short_data'
244 will be set to the string `"512"'.
246 extern char *m88k_short_data;
247 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
249 extern const char *alpha_cpu_string; /* For -mcpu= */
250 extern const char *alpha_tune_string; /* For -mtune= */
251 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
252 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
253 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
254 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
256 #define TARGET_OPTIONS \
258 {"cpu=", &alpha_cpu_string, \
259 N_("Use features of and schedule given CPU")}, \
260 {"tune=", &alpha_tune_string, \
261 N_("Schedule given CPU")}, \
262 {"fp-rounding-mode=", &alpha_fprm_string, \
263 N_("Control the generated fp rounding mode")}, \
264 {"fp-trap-mode=", &alpha_fptm_string, \
265 N_("Control the IEEE trap mode")}, \
266 {"trap-precision=", &alpha_tp_string, \
267 N_("Control the precision given to fp exceptions")}, \
268 {"memory-latency=", &alpha_mlat_string, \
269 N_("Tune expected memory latency")}, \
272 /* Attempt to describe CPU characteristics to the preprocessor. */
274 /* Corresponding to amask... */
275 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
276 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
277 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
278 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
280 /* Corresponding to implver... */
281 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
282 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
283 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
285 /* Common combinations. */
286 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
287 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
288 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
289 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
290 #define CPP_CPU_EV6_SPEC \
291 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
292 #define CPP_CPU_EV67_SPEC \
293 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
295 #ifndef CPP_CPU_DEFAULT_SPEC
296 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
297 # if TARGET_CPU_DEFAULT & MASK_CIX
298 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
300 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
303 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
304 # if TARGET_CPU_DEFAULT & MASK_MAX
305 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
307 # if TARGET_CPU_DEFAULT & MASK_BWX
308 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
310 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
314 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
317 #endif /* CPP_CPU_DEFAULT_SPEC */
320 #define CPP_CPU_SPEC "\
321 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
322 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
323 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
324 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
325 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
326 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
327 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
328 %{!mcpu*:%(cpp_cpu_default) }}"
331 /* This macro defines names of additional specifications to put in the
332 specs that can be used in various specifications like CC1_SPEC. Its
333 definition is an initializer with a subgrouping for each command option.
335 Each subgrouping contains a string constant, that defines the
336 specification name, and a string constant that used by the GNU CC driver
339 Do not define this macro if it does not need to do anything. */
341 #ifndef SUBTARGET_EXTRA_SPECS
342 #define SUBTARGET_EXTRA_SPECS
345 #define EXTRA_SPECS \
346 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
347 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
348 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
349 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
350 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
351 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
352 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
353 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
354 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
355 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
356 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
357 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
358 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
359 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
360 { "cpp_cpu", CPP_CPU_SPEC }, \
361 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
362 SUBTARGET_EXTRA_SPECS
365 /* Sometimes certain combinations of command options do not make sense
366 on a particular target machine. You can define a macro
367 `OVERRIDE_OPTIONS' to take account of this. This macro, if
368 defined, is executed once just after all the command options have
371 On the Alpha, it is used to translate target-option strings into
374 #define OVERRIDE_OPTIONS override_options ()
377 /* Define this macro to change register usage conditional on target flags.
379 On the Alpha, we use this to disable the floating-point registers when
382 #define CONDITIONAL_REGISTER_USAGE \
383 if (! TARGET_FPREGS) \
384 for (i = 32; i < 63; i++) \
385 fixed_regs[i] = call_used_regs[i] = 1;
387 /* Show we can debug even without a frame pointer. */
388 #define CAN_DEBUG_WITHOUT_FP
390 /* target machine storage layout */
392 /* Define to enable software floating point emulation. */
393 #define REAL_ARITHMETIC
395 /* The following #defines are used when compiling the routines in
396 libgcc1.c. Since the Alpha calling conventions require single
397 precision floats to be passed in the floating-point registers
398 (rather than in the general registers) we have to build the
399 libgcc1.c routines in such a way that they know the actual types
400 of their formal arguments and the actual types of their return
401 values. Otherwise, gcc will generate calls to the libgcc1.c
402 routines, passing arguments in the floating-point registers,
403 but the libgcc1.c routines will expect their arguments on the
404 stack (where the Alpha calling conventions require structs &
405 unions to be passed). */
407 #define FLOAT_VALUE_TYPE double
408 #define INTIFY(FLOATVAL) (FLOATVAL)
409 #define FLOATIFY(INTVAL) (INTVAL)
410 #define FLOAT_ARG_TYPE double
412 /* Define the size of `int'. The default is the same as the word size. */
413 #define INT_TYPE_SIZE 32
415 /* Define the size of `long long'. The default is the twice the word size. */
416 #define LONG_LONG_TYPE_SIZE 64
418 /* The two floating-point formats we support are S-floating, which is
419 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
420 and `long double' are T. */
422 #define FLOAT_TYPE_SIZE 32
423 #define DOUBLE_TYPE_SIZE 64
424 #define LONG_DOUBLE_TYPE_SIZE 64
426 #define WCHAR_TYPE "unsigned int"
427 #define WCHAR_TYPE_SIZE 32
429 /* Define this macro if it is advisable to hold scalars in registers
430 in a wider mode than that declared by the program. In such cases,
431 the value is constrained to be within the bounds of the declared
432 type, but kept valid in the wider mode. The signedness of the
433 extension may differ from that of the type.
435 For Alpha, we always store objects in a full register. 32-bit objects
436 are always sign-extended, but smaller objects retain their signedness. */
438 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
439 if (GET_MODE_CLASS (MODE) == MODE_INT \
440 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
442 if ((MODE) == SImode) \
447 /* Define this if function arguments should also be promoted using the above
450 #define PROMOTE_FUNCTION_ARGS
452 /* Likewise, if the function return value is promoted. */
454 #define PROMOTE_FUNCTION_RETURN
456 /* Define this if most significant bit is lowest numbered
457 in instructions that operate on numbered bit-fields.
459 There are no such instructions on the Alpha, but the documentation
461 #define BITS_BIG_ENDIAN 0
463 /* Define this if most significant byte of a word is the lowest numbered.
464 This is false on the Alpha. */
465 #define BYTES_BIG_ENDIAN 0
467 /* Define this if most significant word of a multiword number is lowest
470 For Alpha we can decide arbitrarily since there are no machine instructions
471 for them. Might as well be consistent with bytes. */
472 #define WORDS_BIG_ENDIAN 0
474 /* number of bits in an addressable storage unit */
475 #define BITS_PER_UNIT 8
477 /* Width in bits of a "word", which is the contents of a machine register.
478 Note that this is not necessarily the width of data type `int';
479 if using 16-bit ints on a 68000, this would still be 32.
480 But on a machine with 16-bit registers, this would be 16. */
481 #define BITS_PER_WORD 64
483 /* Width of a word, in units (bytes). */
484 #define UNITS_PER_WORD 8
486 /* Width in bits of a pointer.
487 See also the macro `Pmode' defined below. */
488 #define POINTER_SIZE 64
490 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
491 #define PARM_BOUNDARY 64
493 /* Boundary (in *bits*) on which stack pointer should be aligned. */
494 #define STACK_BOUNDARY 64
496 /* Allocation boundary (in *bits*) for the code of a function. */
497 #define FUNCTION_BOUNDARY 128
499 /* Alignment of field after `int : 0' in a structure. */
500 #define EMPTY_FIELD_BOUNDARY 64
502 /* Every structure's size must be a multiple of this. */
503 #define STRUCTURE_SIZE_BOUNDARY 8
505 /* A bitfield declared as `int' forces `int' alignment for the struct. */
506 #define PCC_BITFIELD_TYPE_MATTERS 1
508 /* Align loop starts for optimal branching.
510 ??? Kludge this and the next macro for the moment by not doing anything if
511 we don't optimize and also if we are writing ECOFF symbols to work around
512 a bug in DEC's assembler. */
514 #define LOOP_ALIGN(LABEL) \
515 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
517 /* This is how to align an instruction for optimal branching. On
518 Alpha we'll get better performance by aligning on an octaword
521 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
522 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
524 /* No data type wants to be aligned rounder than this. */
525 #define BIGGEST_ALIGNMENT 128
527 /* For atomic access to objects, must have at least 32-bit alignment
528 unless the machine has byte operations. */
529 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
531 /* Align all constants and variables to at least a word boundary so
532 we can pick up pieces of them faster. */
533 /* ??? Only if block-move stuff knows about different source/destination
536 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
537 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
540 /* Set this non-zero if move instructions will actually fail to work
541 when given unaligned data.
543 Since we get an error message when we do one, call them invalid. */
545 #define STRICT_ALIGNMENT 1
547 /* Set this non-zero if unaligned move instructions are extremely slow.
549 On the Alpha, they trap. */
551 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
553 /* Standard register usage. */
555 /* Number of actual hardware registers.
556 The hardware registers are assigned numbers for the compiler
557 from 0 to just below FIRST_PSEUDO_REGISTER.
558 All registers that the compiler knows about must be given numbers,
559 even those that are not normally considered general registers.
561 We define all 32 integer registers, even though $31 is always zero,
562 and all 32 floating-point registers, even though $f31 is also
563 always zero. We do not bother defining the FP status register and
564 there are no other registers.
566 Since $31 is always zero, we will use register number 31 as the
567 argument pointer. It will never appear in the generated code
568 because we will always be eliminating it in favor of the stack
569 pointer or hardware frame pointer.
571 Likewise, we use $f31 for the frame pointer, which will always
572 be eliminated in favor of the hardware frame pointer or the
575 #define FIRST_PSEUDO_REGISTER 64
577 /* 1 for registers that have pervasive standard uses
578 and are not available for the register allocator. */
580 #define FIXED_REGISTERS \
581 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
586 /* 1 for registers not available across function calls.
587 These must include the FIXED_REGISTERS and also any
588 registers that can be used without being saved.
589 The latter must include the registers where values are returned
590 and the register where structure-value addresses are passed.
591 Aside from that, you can include as many other registers as you like. */
592 #define CALL_USED_REGISTERS \
593 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
595 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
598 /* List the order in which to allocate registers. Each register must be
599 listed once, even those in FIXED_REGISTERS.
601 We allocate in the following order:
602 $f10-$f15 (nonsaved floating-point register)
604 $f21-$f16 (likewise, but input args)
605 $f0 (nonsaved, but return value)
606 $f1 (nonsaved, but immediate before saved)
607 $f2-$f9 (saved floating-point registers)
608 $1-$8 (nonsaved integer registers)
611 $0 (likewise, but return value)
612 $21-$16 (likewise, but input args)
613 $27 (procedure value in OSF, nonsaved in NT)
614 $9-$14 (saved integer registers)
618 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
620 #define REG_ALLOC_ORDER \
621 {42, 43, 44, 45, 46, 47, \
622 54, 55, 56, 57, 58, 59, 60, 61, 62, \
623 53, 52, 51, 50, 49, 48, \
625 34, 35, 36, 37, 38, 39, 40, 41, \
626 1, 2, 3, 4, 5, 6, 7, 8, \
630 21, 20, 19, 18, 17, 16, \
632 9, 10, 11, 12, 13, 14, \
638 /* Return number of consecutive hard regs needed starting at reg REGNO
639 to hold something of mode MODE.
640 This is ordinarily the length in words of a value of mode MODE
641 but can be less for certain modes in special long registers. */
643 #define HARD_REGNO_NREGS(REGNO, MODE) \
644 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
646 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
647 On Alpha, the integer registers can hold any mode. The floating-point
648 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
651 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
652 ((REGNO) >= 32 && (REGNO) <= 62 \
653 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
656 /* A C expression that is nonzero if a value of mode
657 MODE1 is accessible in mode MODE2 without copying.
659 This asymmetric test is true when MODE1 could be put
660 in an FP register but MODE2 could not. */
662 #define MODES_TIEABLE_P(MODE1, MODE2) \
663 (HARD_REGNO_MODE_OK (32, (MODE1)) \
664 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
667 /* Specify the registers used for certain standard purposes.
668 The values of these macros are register numbers. */
670 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
671 /* #define PC_REGNUM */
673 /* Register to use for pushing function arguments. */
674 #define STACK_POINTER_REGNUM 30
676 /* Base register for access to local variables of the function. */
677 #define HARD_FRAME_POINTER_REGNUM 15
679 /* Value should be nonzero if functions must have frame pointers.
680 Zero means the frame pointer need not be set up (and parms
681 may be accessed via the stack pointer) in functions that seem suitable.
682 This is computed in `reload', in reload1.c. */
683 #define FRAME_POINTER_REQUIRED 0
685 /* Base register for access to arguments of the function. */
686 #define ARG_POINTER_REGNUM 31
688 /* Base register for access to local variables of function. */
689 #define FRAME_POINTER_REGNUM 63
691 /* Register in which static-chain is passed to a function.
693 For the Alpha, this is based on an example; the calling sequence
694 doesn't seem to specify this. */
695 #define STATIC_CHAIN_REGNUM 1
697 /* Register in which address to store a structure value
698 arrives in the function. On the Alpha, the address is passed
699 as a hidden argument. */
700 #define STRUCT_VALUE 0
702 /* Define the classes of registers for register constraints in the
703 machine description. Also define ranges of constants.
705 One of the classes must always be named ALL_REGS and include all hard regs.
706 If there is more than one class, another class must be named NO_REGS
707 and contain no registers.
709 The name GENERAL_REGS must be the name of a class (or an alias for
710 another name such as ALL_REGS). This is the class of registers
711 that is allowed by "g" or "r" in a register constraint.
712 Also, registers outside this class are allocated only when
713 instructions express preferences for them.
715 The classes must be numbered in nondecreasing order; that is,
716 a larger-numbered class must never be contained completely
717 in a smaller-numbered class.
719 For any two classes, it is very desirable that there be another
720 class that represents their union. */
722 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
725 #define N_REG_CLASSES (int) LIM_REG_CLASSES
727 /* Give names of register classes as strings for dump file. */
729 #define REG_CLASS_NAMES \
730 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
732 /* Define which registers fit in which classes.
733 This is an initializer for a vector of HARD_REG_SET
734 of length N_REG_CLASSES. */
736 #define REG_CLASS_CONTENTS \
737 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
739 /* The same information, inverted:
740 Return the class number of the smallest class containing
741 reg number REGNO. This could be a conditional expression
742 or could index an array. */
744 #define REGNO_REG_CLASS(REGNO) \
745 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
747 /* The class value for index registers, and the one for base regs. */
748 #define INDEX_REG_CLASS NO_REGS
749 #define BASE_REG_CLASS GENERAL_REGS
751 /* Get reg_class from a letter such as appears in the machine description. */
753 #define REG_CLASS_FROM_LETTER(C) \
754 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
756 /* Define this macro to change register usage conditional on target flags. */
757 /* #define CONDITIONAL_REGISTER_USAGE */
759 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
760 can be used to stand for particular ranges of immediate operands.
761 This macro defines what the ranges are.
762 C is the letter, and VALUE is a constant value.
763 Return 1 if VALUE is in the range specified by C.
766 `I' is used for the range of constants most insns can contain.
767 `J' is the constant zero.
768 `K' is used for the constant in an LDA insn.
769 `L' is used for the constant in a LDAH insn.
770 `M' is used for the constants that can be AND'ed with using a ZAP insn.
771 `N' is used for complemented 8-bit constants.
772 `O' is used for negated 8-bit constants.
773 `P' is used for the constants 1, 2 and 3. */
775 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
776 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
777 : (C) == 'J' ? (VALUE) == 0 \
778 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
779 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
780 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
781 : (C) == 'M' ? zap_mask (VALUE) \
782 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
783 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
784 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
787 /* Similar, but for floating or large integer constants, and defining letters
788 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
790 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
791 that is the operand of a ZAP insn. */
793 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
794 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
795 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
796 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
797 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
798 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
801 /* Optional extra constraints for this machine.
803 For the Alpha, `Q' means that this is a memory operand but not a
804 reference to an unaligned location.
806 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
809 'S' is a 6-bit constant (valid for a shift insn). */
811 #define EXTRA_CONSTRAINT(OP, C) \
812 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
813 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
814 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
815 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
818 /* Given an rtx X being reloaded into a reg required to be
819 in class CLASS, return the class of reg to actually use.
820 In general this is just CLASS; but on some machines
821 in some cases it is preferable to use a more restrictive class.
823 On the Alpha, all constants except zero go into a floating-point
824 register via memory. */
826 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
827 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
828 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
831 /* Loading and storing HImode or QImode values to and from memory
832 usually requires a scratch register. The exceptions are loading
833 QImode and HImode from an aligned address to a general register
834 unless byte instructions are permitted.
835 We also cannot load an unaligned address or a paradoxical SUBREG into an
838 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
839 secondary_reload_class((CLASS), (MODE), (IN), 1)
841 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
842 secondary_reload_class((CLASS), (MODE), (OUT), 0)
844 /* If we are copying between general and FP registers, we need a memory
845 location unless the FIX extension is available. */
847 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
848 (! TARGET_FIX && (CLASS1) != (CLASS2))
850 /* Specify the mode to be used for memory when a secondary memory
851 location is needed. If MODE is floating-point, use it. Otherwise,
852 widen to a word like the default. This is needed because we always
853 store integers in FP registers in quadword format. This whole
854 area is very tricky! */
855 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
856 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
857 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
858 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
860 /* Return the maximum number of consecutive registers
861 needed to represent mode MODE in a register of class CLASS. */
863 #define CLASS_MAX_NREGS(CLASS, MODE) \
864 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
866 /* If defined, gives a class of registers that cannot be used as the
867 operand of a SUBREG that changes the mode of the object illegally. */
869 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
871 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
873 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
874 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
876 /* Define the cost of moving between registers of various classes. Moving
877 between FLOAT_REGS and anything else except float regs is expensive.
878 In fact, we make it quite expensive because we really don't want to
879 do these moves unless it is clearly worth it. Optimizations may
880 reduce the impact of not being able to allocate a pseudo to a
883 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
884 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
886 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
888 /* A C expressions returning the cost of moving data of MODE from a register to
891 On the Alpha, bump this up a bit. */
893 extern int alpha_memory_latency;
894 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
896 /* Provide the cost of a branch. Exact meaning under development. */
897 #define BRANCH_COST 5
899 /* Adjust the cost of dependencies. */
901 #define ADJUST_COST(INSN,LINK,DEP,COST) \
902 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
904 /* Stack layout; function entry, exit and calling. */
906 /* Define this if pushing a word on the stack
907 makes the stack pointer a smaller address. */
908 #define STACK_GROWS_DOWNWARD
910 /* Define this if the nominal address of the stack frame
911 is at the high-address end of the local variables;
912 that is, each additional local variable allocated
913 goes at a more negative offset in the frame. */
914 /* #define FRAME_GROWS_DOWNWARD */
916 /* Offset within stack frame to start allocating local variables at.
917 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
918 first local allocated. Otherwise, it is the offset to the BEGINNING
919 of the first local allocated. */
921 #define STARTING_FRAME_OFFSET 0
923 /* If we generate an insn to push BYTES bytes,
924 this says how many the stack pointer really advances by.
925 On Alpha, don't define this because there are no push insns. */
926 /* #define PUSH_ROUNDING(BYTES) */
928 /* Define this to be nonzero if stack checking is built into the ABI. */
929 #define STACK_CHECK_BUILTIN 1
931 /* Define this if the maximum size of all the outgoing args is to be
932 accumulated and pushed during the prologue. The amount can be
933 found in the variable current_function_outgoing_args_size. */
934 #define ACCUMULATE_OUTGOING_ARGS 1
936 /* Offset of first parameter from the argument pointer register value. */
938 #define FIRST_PARM_OFFSET(FNDECL) 0
940 /* Definitions for register eliminations.
942 We have two registers that can be eliminated on the Alpha. First, the
943 frame pointer register can often be eliminated in favor of the stack
944 pointer register. Secondly, the argument pointer register can always be
945 eliminated; it is replaced with either the stack or frame pointer. */
947 /* This is an array of structures. Each structure initializes one pair
948 of eliminable registers. The "from" register number is given first,
949 followed by "to". Eliminations of the same "from" register are listed
950 in order of preference. */
952 #define ELIMINABLE_REGS \
953 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
954 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
955 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
956 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
958 /* Given FROM and TO register numbers, say whether this elimination is allowed.
959 Frame pointer elimination is automatically handled.
961 All eliminations are valid since the cases where FP can't be
962 eliminated are already handled. */
964 #define CAN_ELIMINATE(FROM, TO) 1
966 /* Round up to a multiple of 16 bytes. */
967 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
969 /* Define the offset between two registers, one to be eliminated, and the other
970 its replacement, at the start of a routine. */
971 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
972 { if ((FROM) == FRAME_POINTER_REGNUM) \
973 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
974 + alpha_sa_size ()); \
975 else if ((FROM) == ARG_POINTER_REGNUM) \
976 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
978 + (ALPHA_ROUND (get_frame_size () \
979 + current_function_pretend_args_size) \
980 - current_function_pretend_args_size)); \
985 /* Define this if stack space is still allocated for a parameter passed
987 /* #define REG_PARM_STACK_SPACE */
989 /* Value is the number of bytes of arguments automatically
990 popped when returning from a subroutine call.
991 FUNDECL is the declaration node of the function (as a tree),
992 FUNTYPE is the data type of the function (as a tree),
993 or for a library call it is an identifier node for the subroutine name.
994 SIZE is the number of bytes of arguments passed on the stack. */
996 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
998 /* Define how to find the value returned by a function.
999 VALTYPE is the data type of the value (as a tree).
1000 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1001 otherwise, FUNC is 0.
1003 On Alpha the value is found in $0 for integer functions and
1004 $f0 for floating-point functions. */
1006 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1007 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
1008 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1009 || POINTER_TYPE_P (VALTYPE)) \
1010 ? word_mode : TYPE_MODE (VALTYPE), \
1012 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1013 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1016 /* Define how to find the value returned by a library function
1017 assuming the value has mode MODE. */
1019 #define LIBCALL_VALUE(MODE) \
1020 gen_rtx_REG (MODE, \
1022 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1023 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1026 /* The definition of this macro implies that there are cases where
1027 a scalar value cannot be returned in registers.
1029 For the Alpha, any structure or union type is returned in memory, as
1030 are integers whose size is larger than 64 bits. */
1032 #define RETURN_IN_MEMORY(TYPE) \
1033 (TYPE_MODE (TYPE) == BLKmode \
1034 || TYPE_MODE (TYPE) == TFmode \
1035 || TYPE_MODE (TYPE) == TCmode \
1036 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1038 /* 1 if N is a possible register number for a function value
1039 as seen by the caller. */
1041 #define FUNCTION_VALUE_REGNO_P(N) \
1042 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1044 /* 1 if N is a possible register number for function argument passing.
1045 On Alpha, these are $16-$21 and $f16-$f21. */
1047 #define FUNCTION_ARG_REGNO_P(N) \
1048 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1050 /* Define a data type for recording info about an argument list
1051 during the scan of that argument list. This data type should
1052 hold all necessary information about the function itself
1053 and about the args processed so far, enough to enable macros
1054 such as FUNCTION_ARG to determine where the next arg should go.
1056 On Alpha, this is a single integer, which is a number of words
1057 of arguments scanned so far.
1058 Thus 6 or more means all following args should go on the stack. */
1060 #define CUMULATIVE_ARGS int
1062 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1063 for a call to a function whose data type is FNTYPE.
1064 For a library call, FNTYPE is 0. */
1066 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1068 /* Define intermediate macro to compute the size (in registers) of an argument
1071 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1072 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1073 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1074 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1076 /* Update the data in CUM to advance over an argument
1077 of mode MODE and data type TYPE.
1078 (TYPE is null for libcalls where that information may not be available.) */
1080 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1081 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1084 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1086 /* Determine where to put an argument to a function.
1087 Value is zero to push the argument on the stack,
1088 or a hard register in which to store the argument.
1090 MODE is the argument's machine mode.
1091 TYPE is the data type of the argument (as a tree).
1092 This is null for libcalls where that information may
1094 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1095 the preceding args and about the function being called.
1096 NAMED is nonzero if this argument is a named parameter
1097 (otherwise it is an extra parameter matching an ellipsis).
1099 On Alpha the first 6 words of args are normally in registers
1100 and the rest are pushed. */
1102 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1103 function_arg((CUM), (MODE), (TYPE), (NAMED))
1105 /* A C expression that indicates when an argument must be passed by
1106 reference. If nonzero for an argument, a copy of that argument is
1107 made in memory and a pointer to the argument is passed instead of
1108 the argument itself. The pointer is passed in whatever way is
1109 appropriate for passing a pointer to that type. */
1111 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1112 ((MODE) == TFmode || (MODE) == TCmode)
1114 /* Specify the padding direction of arguments.
1116 On the Alpha, we must pad upwards in order to be able to pass args in
1119 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1121 /* For an arg passed partly in registers and partly in memory,
1122 this is the number of registers used.
1123 For args passed entirely in registers or entirely in memory, zero. */
1125 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1126 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1129 /* Perform any needed actions needed for a function that is receiving a
1130 variable number of arguments.
1134 MODE and TYPE are the mode and type of the current parameter.
1136 PRETEND_SIZE is a variable that should be set to the amount of stack
1137 that must be pushed by the prolog to pretend that our caller pushed
1140 Normally, this macro will push all remaining incoming registers on the
1141 stack and set PRETEND_SIZE to the length of the registers pushed.
1143 On the Alpha, we allocate space for all 12 arg registers, but only
1144 push those that are remaining.
1146 However, if NO registers need to be saved, don't allocate any space.
1147 This is not only because we won't need the space, but because AP includes
1148 the current_pretend_args_size and we don't want to mess up any
1149 ap-relative addresses already made.
1151 If we are not to use the floating-point registers, save the integer
1152 registers where we would put the floating-point registers. This is
1153 not the most efficient way to implement varargs with just one register
1154 class, but it isn't worth doing anything more efficient in this rare
1157 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1162 rtx tmp; int set = get_varargs_alias_set (); \
1163 tmp = gen_rtx_MEM (BLKmode, \
1164 plus_constant (virtual_incoming_args_rtx, \
1165 ((CUM) + 6)* UNITS_PER_WORD)); \
1166 MEM_ALIAS_SET (tmp) = set; \
1167 move_block_from_reg \
1169 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1171 tmp = gen_rtx_MEM (BLKmode, \
1172 plus_constant (virtual_incoming_args_rtx, \
1173 (CUM) * UNITS_PER_WORD)); \
1174 MEM_ALIAS_SET (tmp) = set; \
1175 move_block_from_reg \
1176 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1177 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1179 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1183 /* We do not allow indirect calls to be optimized into sibling calls, nor
1184 can we allow a call to a function in a different compilation unit to
1185 be optimized into a sibcall. Except if the function is known not to
1186 return, in which case our caller doesn't care what the gp is. */
1187 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1189 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1190 || ! TREE_PUBLIC (DECL) \
1191 || (0 && TREE_THIS_VOLATILE (DECL))))
1193 /* Try to output insns to set TARGET equal to the constant C if it can be
1194 done in less than N insns. Do all computations in MODE. Returns the place
1195 where the output has been placed if it can be done and the insns have been
1196 emitted. If it would take more than N insns, zero is returned and no
1197 insns and emitted. */
1199 /* Define the information needed to generate branch and scc insns. This is
1200 stored from the compare operation. Note that we can't use "rtx" here
1201 since it hasn't been defined! */
1203 struct alpha_compare
1205 struct rtx_def *op0, *op1;
1209 extern struct alpha_compare alpha_compare;
1211 /* Machine specific function data. */
1213 struct machine_function
1215 /* An offset to apply to the stack pointer when unwinding from EH. */
1216 struct rtx_def *eh_epilogue_sp_ofs;
1218 /* If non-null, this rtx holds the return address for the function. */
1219 struct rtx_def *ra_rtx;
1222 /* Make (or fake) .linkage entry for function call.
1223 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1225 /* This macro defines the start of an assembly comment. */
1227 #define ASM_COMMENT_START " #"
1229 /* This macro produces the initial definition of a function. */
1231 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1232 alpha_start_function(FILE,NAME,DECL);
1234 /* This macro closes up a function definition for the assembler. */
1236 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1237 alpha_end_function(FILE,NAME,DECL)
1239 /* This macro notes the end of the prologue. */
1241 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1243 /* Output any profiling code before the prologue. */
1245 #define PROFILE_BEFORE_PROLOGUE 1
1247 /* Output assembler code to FILE to increment profiler label # LABELNO
1248 for profiling a function entry. Under OSF/1, profiling is enabled
1249 by simply passing -pg to the assembler and linker. */
1251 #define FUNCTION_PROFILER(FILE, LABELNO)
1253 /* Output assembler code to FILE to initialize this source file's
1254 basic block profiling info, if that has not already been done.
1255 This assumes that __bb_init_func doesn't garble a1-a5. */
1257 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1259 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1260 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1261 fputs ("\tldq $26,0($16)\n", (FILE)); \
1262 fputs ("\tbne $26,1f\n", (FILE)); \
1263 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1264 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1265 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1266 fputs ("1:\n", (FILE)); \
1267 ASM_OUTPUT_REG_POP (FILE, 16); \
1270 /* Output assembler code to FILE to increment the entry-count for
1271 the BLOCKNO'th basic block in this source file. */
1273 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1275 int blockn = (BLOCKNO); \
1276 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1277 fputs ("\tstq $26,0($30)\n", (FILE)); \
1278 fputs ("\tstq $27,8($30)\n", (FILE)); \
1279 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1280 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1281 fputs ("\taddq $27,1,$27\n", (FILE)); \
1282 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1283 fputs ("\tldq $26,0($30)\n", (FILE)); \
1284 fputs ("\tldq $27,8($30)\n", (FILE)); \
1285 fputs ("\taddq $30,16,$30\n", (FILE)); \
1289 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1290 the stack pointer does not matter. The value is tested only in
1291 functions that have frame pointers.
1292 No definition is equivalent to always zero. */
1294 #define EXIT_IGNORE_STACK 1
1296 /* Define registers used by the epilogue and return instruction. */
1298 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1300 /* Output assembler code for a block containing the constant parts
1301 of a trampoline, leaving space for the variable parts.
1303 The trampoline should set the static chain pointer to value placed
1304 into the trampoline and should branch to the specified routine.
1305 Note that $27 has been set to the address of the trampoline, so we can
1306 use it for addressability of the two data items. Trampolines are always
1307 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1309 #define TRAMPOLINE_TEMPLATE(FILE) \
1311 fprintf (FILE, "\tldq $1,24($27)\n"); \
1312 fprintf (FILE, "\tldq $27,16($27)\n"); \
1313 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1314 fprintf (FILE, "\tnop\n"); \
1315 fprintf (FILE, "\t.quad 0,0\n"); \
1318 /* Section in which to place the trampoline. On Alpha, instructions
1319 may only be placed in a text segment. */
1321 #define TRAMPOLINE_SECTION text_section
1323 /* Length in units of the trampoline for entering a nested function. */
1325 #define TRAMPOLINE_SIZE 32
1327 /* Emit RTL insns to initialize the variable parts of a trampoline.
1328 FNADDR is an RTX for the address of the function's pure code.
1329 CXT is an RTX for the static chain value for the function. */
1331 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1332 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1334 /* A C expression whose value is RTL representing the value of the return
1335 address for the frame COUNT steps up from the current frame.
1336 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1337 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1339 #define RETURN_ADDR_RTX alpha_return_addr
1341 /* Before the prologue, RA lives in $26. */
1342 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1343 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1345 /* Addressing modes, and classification of registers for them. */
1347 /* #define HAVE_POST_INCREMENT 0 */
1348 /* #define HAVE_POST_DECREMENT 0 */
1350 /* #define HAVE_PRE_DECREMENT 0 */
1351 /* #define HAVE_PRE_INCREMENT 0 */
1353 /* Macros to check register numbers against specific register classes. */
1355 /* These assume that REGNO is a hard or pseudo reg number.
1356 They give nonzero only if REGNO is a hard reg of the suitable class
1357 or a pseudo reg currently allocated to a suitable hard reg.
1358 Since they use reg_renumber, they are safe only once reg_renumber
1359 has been allocated, which happens in local-alloc.c. */
1361 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1362 #define REGNO_OK_FOR_BASE_P(REGNO) \
1363 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1364 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1366 /* Maximum number of registers that can appear in a valid memory address. */
1367 #define MAX_REGS_PER_ADDRESS 1
1369 /* Recognize any constant value that is a valid address. For the Alpha,
1370 there are only constants none since we want to use LDA to load any
1371 symbolic addresses into registers. */
1373 #define CONSTANT_ADDRESS_P(X) \
1374 (GET_CODE (X) == CONST_INT \
1375 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1377 /* Include all constant integers and constant doubles, but not
1378 floating-point, except for floating-point zero. */
1380 #define LEGITIMATE_CONSTANT_P(X) \
1381 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1382 || (X) == CONST0_RTX (GET_MODE (X)))
1384 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1385 and check its validity for a certain class.
1386 We have two alternate definitions for each of them.
1387 The usual definition accepts all pseudo regs; the other rejects
1388 them unless they have been allocated suitable hard regs.
1389 The symbol REG_OK_STRICT causes the latter definition to be used.
1391 Most source files want to accept pseudo regs in the hope that
1392 they will get allocated to the class that the insn wants them to be in.
1393 Source files for reload pass need to be strict.
1394 After reload, it makes no difference, since pseudo regs have
1395 been eliminated by then. */
1397 #ifndef REG_OK_STRICT
1399 /* Nonzero if X is a hard reg that can be used as an index
1400 or if it is a pseudo reg. */
1401 #define REG_OK_FOR_INDEX_P(X) 0
1403 /* Nonzero if X is a hard reg that can be used as a base reg
1404 or if it is a pseudo reg. */
1405 #define REG_OK_FOR_BASE_P(X) \
1406 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1408 /* ??? Nonzero if X is the frame pointer, or some virtual register
1409 that may eliminate to the frame pointer. These will be allowed to
1410 have offsets greater than 32K. This is done because register
1411 elimination offsets will change the hi/lo split, and if we split
1412 before reload, we will require additional instructions. */
1413 #define REG_OK_FP_BASE_P(X) \
1414 (REGNO (X) == 31 || REGNO (X) == 63 \
1415 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1416 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1420 /* Nonzero if X is a hard reg that can be used as an index. */
1421 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1423 /* Nonzero if X is a hard reg that can be used as a base reg. */
1424 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1426 #define REG_OK_FP_BASE_P(X) 0
1430 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1431 that is a valid memory address for an instruction.
1432 The MODE argument is the machine mode for the MEM expression
1433 that wants to use this address.
1435 For Alpha, we have either a constant address or the sum of a register
1436 and a constant address, or just a register. For DImode, any of those
1437 forms can be surrounded with an AND that clear the low-order three bits;
1438 this is an "unaligned" access.
1440 First define the basic valid address. */
1442 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1445 if (GET_CODE (tmp) == SUBREG \
1446 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1447 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1448 tmp = SUBREG_REG (tmp); \
1449 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1451 if (CONSTANT_ADDRESS_P (X)) \
1453 if (GET_CODE (X) == PLUS) \
1455 tmp = XEXP (X, 0); \
1456 if (GET_CODE (tmp) == SUBREG \
1457 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1458 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1459 tmp = SUBREG_REG (tmp); \
1462 if (REG_OK_FP_BASE_P (tmp) \
1463 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1465 if (REG_OK_FOR_BASE_P (tmp) \
1466 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1469 else if (GET_CODE (tmp) == ADDRESSOF \
1470 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1475 /* Now accept the simple address, or, for DImode only, an AND of a simple
1476 address that turns off the low three bits. */
1478 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1479 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1480 if ((MODE) == DImode \
1481 && GET_CODE (X) == AND \
1482 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1483 && INTVAL (XEXP (X, 1)) == -8) \
1484 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1487 /* Try machine-dependent ways of modifying an illegitimate address
1488 to be legitimate. If we find one, return the new, valid address.
1489 This macro is used in only one place: `memory_address' in explow.c.
1491 OLDX is the address as it was before break_out_memory_refs was called.
1492 In some cases it is useful to look at this to decide what needs to be done.
1494 MODE and WIN are passed so that this macro can use
1495 GO_IF_LEGITIMATE_ADDRESS.
1497 It is always safe for this macro to do nothing. It exists to recognize
1498 opportunities to optimize the output.
1500 For the Alpha, there are three cases we handle:
1502 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1503 valid offset, compute the high part of the constant and add it to the
1504 register. Then our address is (plus temp low-part-const).
1505 (2) If the address is (const (plus FOO const_int)), find the low-order
1506 part of the CONST_INT. Then load FOO plus any high-order part of the
1507 CONST_INT into a register. Our address is (plus reg low-part-const).
1508 This is done to reduce the number of GOT entries.
1509 (3) If we have a (plus reg const), emit the load as in (2), then add
1510 the two registers, and finally generate (plus reg low-part-const) as
1513 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1514 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1515 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1516 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1518 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1519 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1520 HOST_WIDE_INT highpart = val - lowpart; \
1521 rtx high = GEN_INT (highpart); \
1522 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1523 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1525 (X) = plus_constant (temp, lowpart); \
1528 else if (GET_CODE (X) == CONST \
1529 && GET_CODE (XEXP (X, 0)) == PLUS \
1530 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1532 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1533 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1534 HOST_WIDE_INT highpart = val - lowpart; \
1535 rtx high = XEXP (XEXP (X, 0), 0); \
1538 high = plus_constant (high, highpart); \
1540 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1543 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1544 && GET_CODE (XEXP (X, 1)) == CONST \
1545 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1546 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1548 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1549 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1550 HOST_WIDE_INT highpart = val - lowpart; \
1551 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1554 high = plus_constant (high, highpart); \
1556 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1557 force_reg (Pmode, high), \
1558 high, 1, OPTAB_LIB_WIDEN); \
1559 (X) = plus_constant (high, lowpart); \
1564 /* Try a machine-dependent way of reloading an illegitimate address
1565 operand. If we find one, push the reload and jump to WIN. This
1566 macro is used in only one place: `find_reloads_address' in reload.c.
1568 For the Alpha, we wish to handle large displacements off a base
1569 register by splitting the addend across an ldah and the mem insn.
1570 This cuts number of extra insns needed from 3 to 1. */
1572 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1574 /* We must recognize output that we have already generated ourselves. */ \
1575 if (GET_CODE (X) == PLUS \
1576 && GET_CODE (XEXP (X, 0)) == PLUS \
1577 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1578 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1579 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1581 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1582 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1586 if (GET_CODE (X) == PLUS \
1587 && GET_CODE (XEXP (X, 0)) == REG \
1588 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1589 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1590 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1592 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1593 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1594 HOST_WIDE_INT high \
1595 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1597 /* Check for 32-bit overflow. */ \
1598 if (high + low != val) \
1601 /* Reload the high part into a base reg; leave the low part \
1602 in the mem directly. */ \
1604 X = gen_rtx_PLUS (GET_MODE (X), \
1605 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1609 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1610 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1616 /* Go to LABEL if ADDR (a legitimate address expression)
1617 has an effect that depends on the machine mode it is used for.
1618 On the Alpha this is true only for the unaligned modes. We can
1619 simplify this test since we know that the address must be valid. */
1621 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1622 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1624 /* Compute the cost of an address. For the Alpha, all valid addresses are
1627 #define ADDRESS_COST(X) 0
1629 /* Machine-dependent reorg pass. */
1630 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1632 /* Specify the machine mode that this machine uses
1633 for the index in the tablejump instruction. */
1634 #define CASE_VECTOR_MODE SImode
1636 /* Define as C expression which evaluates to nonzero if the tablejump
1637 instruction expects the table to contain offsets from the address of the
1640 Do not define this if the table should contain absolute addresses.
1641 On the Alpha, the table is really GP-relative, not relative to the PC
1642 of the table, but we pretend that it is PC-relative; this should be OK,
1643 but we should try to find some better way sometime. */
1644 #define CASE_VECTOR_PC_RELATIVE 1
1646 /* Specify the tree operation to be used to convert reals to integers. */
1647 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1649 /* This is the kind of divide that is easiest to do in the general case. */
1650 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1652 /* Define this as 1 if `char' should by default be signed; else as 0. */
1653 #define DEFAULT_SIGNED_CHAR 1
1655 /* This flag, if defined, says the same insns that convert to a signed fixnum
1656 also convert validly to an unsigned one.
1658 We actually lie a bit here as overflow conditions are different. But
1659 they aren't being checked anyway. */
1661 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1663 /* Max number of bytes we can move to or from memory
1664 in one reasonably fast instruction. */
1668 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1669 move-instruction pairs, we will do a movstr or libcall instead.
1671 Without byte/word accesses, we want no more than four instructions;
1672 with, several single byte accesses are better. */
1674 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1676 /* Largest number of bytes of an object that can be placed in a register.
1677 On the Alpha we have plenty of registers, so use TImode. */
1678 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1680 /* Nonzero if access to memory by bytes is no faster than for words.
1681 Also non-zero if doing byte operations (specifically shifts) in registers
1684 On the Alpha, we want to not use the byte operation and instead use
1685 masking operations to access fields; these will save instructions. */
1687 #define SLOW_BYTE_ACCESS 1
1689 /* Define if operations between registers always perform the operation
1690 on the full register even if a narrower mode is specified. */
1691 #define WORD_REGISTER_OPERATIONS
1693 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1694 will either zero-extend or sign-extend. The value of this macro should
1695 be the code that says which one of the two operations is implicitly
1696 done, NIL if none. */
1697 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1699 /* Define if loading short immediate values into registers sign extends. */
1700 #define SHORT_IMMEDIATES_SIGN_EXTEND
1702 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1703 is done just by pretending it is already truncated. */
1704 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1706 /* We assume that the store-condition-codes instructions store 0 for false
1707 and some other value for true. This is the value stored for true. */
1709 #define STORE_FLAG_VALUE 1
1711 /* Define the value returned by a floating-point comparison instruction. */
1713 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1714 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1716 /* Canonicalize a comparison from one we don't have to one we do have. */
1718 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1720 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1721 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1726 (CODE) = swap_condition (CODE); \
1728 if (((CODE) == LT || (CODE) == LTU) \
1729 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1731 (CODE) = (CODE) == LT ? LE : LEU; \
1732 (OP1) = GEN_INT (255); \
1736 /* Specify the machine mode that pointers have.
1737 After generation of rtl, the compiler makes no further distinction
1738 between pointers and any other objects of this machine mode. */
1739 #define Pmode DImode
1741 /* Mode of a function address in a call instruction (for indexing purposes). */
1743 #define FUNCTION_MODE Pmode
1745 /* Define this if addresses of constant functions
1746 shouldn't be put through pseudo regs where they can be cse'd.
1747 Desirable on machines where ordinary constants are expensive
1748 but a CALL with constant address is cheap.
1750 We define this on the Alpha so that gen_call and gen_call_value
1751 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1752 then copy it into a register, thus actually letting the address be
1755 #define NO_FUNCTION_CSE
1757 /* Define this to be nonzero if shift instructions ignore all but the low-order
1759 #define SHIFT_COUNT_TRUNCATED 1
1761 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1762 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1764 /* Describe the fact that MULTI instructions are multiple instructions
1765 and so to assume they don't pair with anything. */
1766 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1767 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1768 (CAN_ISSUE_MORE) = 0
1770 /* Compute the cost of computing a constant rtl expression RTX
1771 whose rtx-code is CODE. The body of this macro is a portion
1772 of a switch statement. If the code is computed here,
1773 return it with a return statement. Otherwise, break from the switch.
1775 If this is an 8-bit constant, return zero since it can be used
1776 nearly anywhere with no cost. If it is a valid operand for an
1777 ADD or AND, likewise return 0 if we know it will be used in that
1778 context. Otherwise, return 2 since it might be used there later.
1779 All other constants take at least two insns. */
1781 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1783 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1785 case CONST_DOUBLE: \
1786 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1788 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1789 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1791 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1794 return COSTS_N_INSNS (2); \
1798 switch (alpha_cpu) \
1800 case PROCESSOR_EV4: \
1801 return COSTS_N_INSNS (3); \
1802 case PROCESSOR_EV5: \
1803 case PROCESSOR_EV6: \
1804 return COSTS_N_INSNS (2); \
1808 /* Provide the costs of a rtl expression. This is in the body of a
1811 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1812 case PLUS: case MINUS: \
1813 if (FLOAT_MODE_P (GET_MODE (X))) \
1814 switch (alpha_cpu) \
1816 case PROCESSOR_EV4: \
1817 return COSTS_N_INSNS (6); \
1818 case PROCESSOR_EV5: \
1819 case PROCESSOR_EV6: \
1820 return COSTS_N_INSNS (4); \
1823 else if (GET_CODE (XEXP (X, 0)) == MULT \
1824 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1825 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1826 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1829 switch (alpha_cpu) \
1831 case PROCESSOR_EV4: \
1832 if (FLOAT_MODE_P (GET_MODE (X))) \
1833 return COSTS_N_INSNS (6); \
1834 return COSTS_N_INSNS (23); \
1835 case PROCESSOR_EV5: \
1836 if (FLOAT_MODE_P (GET_MODE (X))) \
1837 return COSTS_N_INSNS (4); \
1838 else if (GET_MODE (X) == DImode) \
1839 return COSTS_N_INSNS (12); \
1841 return COSTS_N_INSNS (8); \
1842 case PROCESSOR_EV6: \
1843 if (FLOAT_MODE_P (GET_MODE (X))) \
1844 return COSTS_N_INSNS (4); \
1846 return COSTS_N_INSNS (7); \
1850 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1851 && INTVAL (XEXP (X, 1)) <= 3) \
1853 /* ... fall through ... */ \
1854 case ASHIFTRT: case LSHIFTRT: \
1855 switch (alpha_cpu) \
1857 case PROCESSOR_EV4: \
1858 return COSTS_N_INSNS (2); \
1859 case PROCESSOR_EV5: \
1860 case PROCESSOR_EV6: \
1861 return COSTS_N_INSNS (1); \
1864 case IF_THEN_ELSE: \
1865 switch (alpha_cpu) \
1867 case PROCESSOR_EV4: \
1868 case PROCESSOR_EV6: \
1869 return COSTS_N_INSNS (2); \
1870 case PROCESSOR_EV5: \
1871 return COSTS_N_INSNS (1); \
1874 case DIV: case UDIV: case MOD: case UMOD: \
1875 switch (alpha_cpu) \
1877 case PROCESSOR_EV4: \
1878 if (GET_MODE (X) == SFmode) \
1879 return COSTS_N_INSNS (34); \
1880 else if (GET_MODE (X) == DFmode) \
1881 return COSTS_N_INSNS (63); \
1883 return COSTS_N_INSNS (70); \
1884 case PROCESSOR_EV5: \
1885 if (GET_MODE (X) == SFmode) \
1886 return COSTS_N_INSNS (15); \
1887 else if (GET_MODE (X) == DFmode) \
1888 return COSTS_N_INSNS (22); \
1890 return COSTS_N_INSNS (70); /* ??? */ \
1891 case PROCESSOR_EV6: \
1892 if (GET_MODE (X) == SFmode) \
1893 return COSTS_N_INSNS (12); \
1894 else if (GET_MODE (X) == DFmode) \
1895 return COSTS_N_INSNS (15); \
1897 return COSTS_N_INSNS (70); /* ??? */ \
1901 switch (alpha_cpu) \
1903 case PROCESSOR_EV4: \
1904 case PROCESSOR_EV6: \
1905 return COSTS_N_INSNS (3); \
1906 case PROCESSOR_EV5: \
1907 return COSTS_N_INSNS (2); \
1910 case NEG: case ABS: \
1911 if (! FLOAT_MODE_P (GET_MODE (X))) \
1913 /* ... fall through ... */ \
1914 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1915 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1916 switch (alpha_cpu) \
1918 case PROCESSOR_EV4: \
1919 return COSTS_N_INSNS (6); \
1920 case PROCESSOR_EV5: \
1921 case PROCESSOR_EV6: \
1922 return COSTS_N_INSNS (4); \
1926 /* Control the assembler format that we output. */
1928 /* We don't emit these labels, so as to avoid getting linker errors about
1929 missing exception handling info. If we emit a gcc_compiled. label into
1930 text, and the file has no code, then the DEC assembler gives us a zero
1931 sized text section with no associated exception handling info. The
1932 DEC linker sees this text section, and gives a warning saying that
1933 the exception handling info is missing. */
1934 #define ASM_IDENTIFY_GCC(x)
1935 #define ASM_IDENTIFY_LANGUAGE(x)
1937 /* Output to assembler file text saying following lines
1938 may contain character constants, extra white space, comments, etc. */
1940 #define ASM_APP_ON ""
1942 /* Output to assembler file text saying following lines
1943 no longer contain unusual constructs. */
1945 #define ASM_APP_OFF ""
1947 #define TEXT_SECTION_ASM_OP "\t.text"
1949 /* Output before read-only data. */
1951 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1953 /* Output before writable data. */
1955 #define DATA_SECTION_ASM_OP "\t.data"
1957 /* Define an extra section for read-only data, a routine to enter it, and
1958 indicate that it is for read-only data.
1960 The first time we enter the readonly data section for a file, we write
1961 eight bytes of zero. This works around a bug in DEC's assembler in
1962 some versions of OSF/1 V3.x. */
1964 #define EXTRA_SECTIONS readonly_data
1966 #define EXTRA_SECTION_FUNCTIONS \
1968 literal_section () \
1970 if (in_section != readonly_data) \
1972 static int firsttime = 1; \
1974 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1978 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1981 in_section = readonly_data; \
1985 #define READONLY_DATA_SECTION literal_section
1987 /* If we are referencing a function that is static, make the SYMBOL_REF
1988 special. We use this to see indicate we can branch to this function
1989 without setting PV or restoring GP. */
1991 #define ENCODE_SECTION_INFO(DECL) \
1992 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1993 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1995 /* How to refer to registers in assembler output.
1996 This sequence is indexed by compiler's hard-register-number (see above). */
1998 #define REGISTER_NAMES \
1999 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
2000 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2001 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2002 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
2003 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
2004 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2005 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
2006 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
2008 /* How to renumber registers for dbx and gdb. */
2010 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2012 /* This is how to output the definition of a user-level label named NAME,
2013 such as the label on a static function or variable NAME. */
2015 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2016 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2018 /* This is how to output a command to make the user-level label named NAME
2019 defined for reference from other files. */
2021 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2022 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2024 /* The prefix to add to user-visible assembler symbols. */
2026 #define USER_LABEL_PREFIX ""
2028 /* This is how to output an internal numbered label where
2029 PREFIX is the class of label and NUM is the number within the class. */
2031 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2032 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2034 /* This is how to output a label for a jump table. Arguments are the same as
2035 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2038 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2039 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2041 /* This is how to store into the string LABEL
2042 the symbol_ref name of an internal numbered label where
2043 PREFIX is the class of label and NUM is the number within the class.
2044 This is suitable for output with `assemble_name'. */
2046 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2047 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2049 /* Check a floating-point value for validity for a particular machine mode. */
2051 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2052 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2054 /* This is how to output an assembler line defining a `long double'
2057 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2060 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2061 fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \
2062 t[1] & 0xffffffff, t[0] & 0xffffffff, \
2063 t[3] & 0xffffffff, t[2] & 0xffffffff); \
2066 /* This is how to output an assembler line defining a `double' constant. */
2068 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2071 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2072 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2073 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2076 /* This is how to output an assembler line defining a `float' constant. */
2078 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2081 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2082 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2085 /* This is how to output an assembler line defining an `int' constant. */
2087 #define ASM_OUTPUT_INT(FILE,VALUE) \
2088 ( fprintf (FILE, "\t.long "), \
2089 output_addr_const (FILE, (VALUE)), \
2090 fprintf (FILE, "\n"))
2092 /* This is how to output an assembler line defining a `long' constant. */
2094 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2095 ( fprintf (FILE, "\t.quad "), \
2096 output_addr_const (FILE, (VALUE)), \
2097 fprintf (FILE, "\n"))
2099 /* Likewise for `char' and `short' constants. */
2101 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2102 fprintf (FILE, "\t.word %d\n", \
2103 (int)(GET_CODE (VALUE) == CONST_INT \
2104 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2106 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2107 fprintf (FILE, "\t.byte %d\n", \
2108 (int)(GET_CODE (VALUE) == CONST_INT \
2109 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2111 /* We use the default ASCII-output routine, except that we don't write more
2112 than 50 characters since the assembler doesn't support very long lines. */
2114 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2116 FILE *_hide_asm_out_file = (MYFILE); \
2117 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
2118 int _hide_thissize = (MYLENGTH); \
2119 int _size_so_far = 0; \
2121 FILE *asm_out_file = _hide_asm_out_file; \
2122 const unsigned char *p = _hide_p; \
2123 int thissize = _hide_thissize; \
2125 fprintf (asm_out_file, "\t.ascii \""); \
2127 for (i = 0; i < thissize; i++) \
2129 register int c = p[i]; \
2131 if (_size_so_far ++ > 50 && i < thissize - 4) \
2132 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2134 if (c == '\"' || c == '\\') \
2135 putc ('\\', asm_out_file); \
2136 if (c >= ' ' && c < 0177) \
2137 putc (c, asm_out_file); \
2140 fprintf (asm_out_file, "\\%o", c); \
2141 /* After an octal-escape, if a digit follows, \
2142 terminate one string constant and start another. \
2143 The Vax assembler fails to stop reading the escape \
2144 after three digits, so this is the only way we \
2145 can get it to parse the data properly. */ \
2146 if (i < thissize - 1 \
2147 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2148 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2151 fprintf (asm_out_file, "\"\n"); \
2156 /* To get unaligned data, we have to turn off auto alignment. */
2157 #define UNALIGNED_SHORT_ASM_OP "\t.align 0\n\t.word\t"
2158 #define UNALIGNED_INT_ASM_OP "\t.align 0\n\t.long\t"
2159 #define UNALIGNED_DOUBLE_INT_ASM_OP "\t.align 0\n\t.quad\t"
2161 /* This is how to output an insn to push a register on the stack.
2162 It need not be very fast code. */
2164 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2165 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2166 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2169 /* This is how to output an insn to pop a register from the stack.
2170 It need not be very fast code. */
2172 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2173 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2174 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2177 /* This is how to output an assembler line for a numeric constant byte. */
2179 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2180 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2182 /* This is how to output an element of a case-vector that is absolute.
2183 (Alpha does not use such vectors, but we must define this macro anyway.) */
2185 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2187 /* This is how to output an element of a case-vector that is relative. */
2189 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2190 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2193 /* This is how to output an assembler line
2194 that says to advance the location counter
2195 to a multiple of 2**LOG bytes. */
2197 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2199 fprintf (FILE, "\t.align %d\n", LOG);
2201 /* This is how to advance the location counter by SIZE bytes. */
2203 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2204 fprintf (FILE, "\t.space %d\n", (SIZE))
2206 /* This says how to output an assembler line
2207 to define a global common symbol. */
2209 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2210 ( fputs ("\t.comm ", (FILE)), \
2211 assemble_name ((FILE), (NAME)), \
2212 fprintf ((FILE), ",%d\n", (SIZE)))
2214 /* This says how to output an assembler line
2215 to define a local common symbol. */
2217 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2218 ( fputs ("\t.lcomm ", (FILE)), \
2219 assemble_name ((FILE), (NAME)), \
2220 fprintf ((FILE), ",%d\n", (SIZE)))
2222 /* Store in OUTPUT a string (made with alloca) containing
2223 an assembler-name for a local static variable named NAME.
2224 LABELNO is an integer which is different for each call. */
2226 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2227 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2228 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2230 /* Define the parentheses used to group arithmetic operations
2231 in assembler code. */
2233 #define ASM_OPEN_PAREN "("
2234 #define ASM_CLOSE_PAREN ")"
2236 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2237 Used for C++ multiple inheritance. */
2239 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2241 const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2244 /* Mark end of prologue. */ \
2245 output_end_prologue (FILE); \
2247 /* Rely on the assembler to macro expand a large delta. */ \
2248 fprintf (FILE, "\t.set at\n"); \
2249 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2250 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2252 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \
2255 fprintf (FILE, "\tbr $31,$"); \
2256 assemble_name (FILE, fn_name); \
2257 fprintf (FILE, "..ng\n"); \
2261 fprintf (FILE, "\tjmp $31,"); \
2262 assemble_name (FILE, fn_name); \
2263 fputc ('\n', FILE); \
2265 fprintf (FILE, "\t.set noat\n"); \
2269 /* Define results of standard character escape sequences. */
2270 #define TARGET_BELL 007
2271 #define TARGET_BS 010
2272 #define TARGET_TAB 011
2273 #define TARGET_NEWLINE 012
2274 #define TARGET_VT 013
2275 #define TARGET_FF 014
2276 #define TARGET_CR 015
2278 /* Print operand X (an rtx) in assembler syntax to file FILE.
2279 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2280 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2282 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2284 /* Determine which codes are valid without a following integer. These must
2287 ~ Generates the name of the current function.
2289 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2290 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2291 mode. alpha_fprm controls which suffix is generated.
2293 ' Generates trap-mode suffix for instructions that accept the
2294 su suffix only (cmpt et al).
2296 ` Generates trap-mode suffix for instructions that accept the
2297 v and sv suffix. The only instruction that needs this is cvtql.
2299 ( Generates trap-mode suffix for instructions that accept the
2300 v, sv, and svi suffix. The only instruction that needs this
2303 ) Generates trap-mode suffix for instructions that accept the
2304 u, su, and sui suffix. This is the bulk of the IEEE floating
2305 point instructions (addt et al).
2307 + Generates trap-mode suffix for instructions that accept the
2308 sui suffix (cvtqt and cvtqs).
2310 , Generates single precision suffix for floating point
2311 instructions (s for IEEE, f for VAX)
2313 - Generates double precision suffix for floating point
2314 instructions (t for IEEE, g for VAX)
2317 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2318 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2319 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-' \
2322 /* Print a memory address as an operand to reference that memory location. */
2324 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2325 print_operand_address((FILE), (ADDR))
2327 /* Define the codes that are matched by predicates in alpha.c. */
2329 #define PREDICATE_CODES \
2330 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2331 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2332 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2333 {"cint8_operand", {CONST_INT}}, \
2334 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2335 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2336 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2337 {"const48_operand", {CONST_INT}}, \
2338 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2339 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2340 {"mode_mask_operand", {CONST_INT}}, \
2341 {"mul8_operand", {CONST_INT}}, \
2342 {"mode_width_operand", {CONST_INT}}, \
2343 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2344 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2345 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
2346 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2347 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2348 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2349 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2350 {"fp0_operand", {CONST_DOUBLE}}, \
2351 {"current_file_function_operand", {SYMBOL_REF}}, \
2352 {"call_operand", {REG, SYMBOL_REF}}, \
2353 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2354 SYMBOL_REF, CONST, LABEL_REF}}, \
2355 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2356 SYMBOL_REF, CONST, LABEL_REF}}, \
2357 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2358 {"aligned_memory_operand", {MEM}}, \
2359 {"unaligned_memory_operand", {MEM}}, \
2360 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2361 {"any_memory_operand", {MEM}}, \
2362 {"hard_fp_register_operand", {SUBREG, REG}}, \
2363 {"hard_int_register_operand", {SUBREG, REG}}, \
2364 {"reg_not_elim_operand", {SUBREG, REG}}, \
2365 {"reg_no_subreg_operand", {REG}}, \
2366 {"addition_operation", {PLUS}},
2368 /* Define the `__builtin_va_list' type for the ABI. */
2369 #define BUILD_VA_LIST_TYPE(VALIST) \
2370 (VALIST) = alpha_build_va_list ()
2372 /* Implement `va_start' for varargs and stdarg. */
2373 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2374 alpha_va_start (stdarg, valist, nextarg)
2376 /* Implement `va_arg'. */
2377 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2378 alpha_va_arg (valist, type)
2380 /* Tell collect that the object format is ECOFF. */
2381 #define OBJECT_FORMAT_COFF
2382 #define EXTENDED_COFF
2384 /* If we use NM, pass -g to it so it only lists globals. */
2385 #define NM_FLAGS "-pg"
2387 /* Definitions for debugging. */
2389 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2390 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2391 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2393 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2394 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2398 /* Correct the offset of automatic variables and arguments. Note that
2399 the Alpha debug format wants all automatic variables and arguments
2400 to be in terms of two different offsets from the virtual frame pointer,
2401 which is the stack pointer before any adjustment in the function.
2402 The offset for the argument pointer is fixed for the native compiler,
2403 it is either zero (for the no arguments case) or large enough to hold
2404 all argument registers.
2405 The offset for the auto pointer is the fourth argument to the .frame
2406 directive (local_offset).
2407 To stay compatible with the native tools we use the same offsets
2408 from the virtual frame pointer and adjust the debugger arg/auto offsets
2409 accordingly. These debugger offsets are set up in output_prolog. */
2411 extern long alpha_arg_offset;
2412 extern long alpha_auto_offset;
2413 #define DEBUGGER_AUTO_OFFSET(X) \
2414 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2415 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2418 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2419 alpha_output_lineno (STREAM, LINE)
2421 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2422 alpha_output_filename (STREAM, NAME)
2424 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2425 number, because the real length runs past this up to the next
2426 continuation point. This is really a dbxout.c bug. */
2427 #define DBX_CONTIN_LENGTH 3000
2429 /* By default, turn on GDB extensions. */
2430 #define DEFAULT_GDB_EXTENSIONS 1
2432 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2433 #define NO_DBX_FUNCTION_END 1
2435 /* If we are smuggling stabs through the ALPHA ECOFF object
2436 format, put a comment in front of the .stab<x> operation so
2437 that the ALPHA assembler does not choke. The mips-tfile program
2438 will correctly put the stab into the object file. */
2440 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2441 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2442 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2444 /* Forward references to tags are allowed. */
2445 #define SDB_ALLOW_FORWARD_REFERENCES
2447 /* Unknown tags are also allowed. */
2448 #define SDB_ALLOW_UNKNOWN_REFERENCES
2450 #define PUT_SDB_DEF(a) \
2452 fprintf (asm_out_file, "\t%s.def\t", \
2453 (TARGET_GAS) ? "" : "#"); \
2454 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2455 fputc (';', asm_out_file); \
2458 #define PUT_SDB_PLAIN_DEF(a) \
2460 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2461 (TARGET_GAS) ? "" : "#", (a)); \
2464 #define PUT_SDB_TYPE(a) \
2466 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2469 /* For block start and end, we create labels, so that
2470 later we can figure out where the correct offset is.
2471 The normal .ent/.end serve well enough for functions,
2472 so those are just commented out. */
2474 extern int sdb_label_count; /* block start/end next label # */
2476 #define PUT_SDB_BLOCK_START(LINE) \
2478 fprintf (asm_out_file, \
2479 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2481 (TARGET_GAS) ? "" : "#", \
2484 sdb_label_count++; \
2487 #define PUT_SDB_BLOCK_END(LINE) \
2489 fprintf (asm_out_file, \
2490 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2492 (TARGET_GAS) ? "" : "#", \
2495 sdb_label_count++; \
2498 #define PUT_SDB_FUNCTION_START(LINE)
2500 #define PUT_SDB_FUNCTION_END(LINE)
2502 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2504 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2505 mips-tdump.c to print them out.
2507 These must match the corresponding definitions in gdb/mipsread.c.
2508 Unfortunately, gcc and gdb do not currently share any directories. */
2510 #define CODE_MASK 0x8F300
2511 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2512 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2513 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2515 /* Override some mips-tfile definitions. */
2517 #define SHASH_SIZE 511
2518 #define THASH_SIZE 55
2520 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2522 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2524 /* The linker will stick __main into the .init section. */
2525 #define HAS_INIT_SECTION
2526 #define LD_INIT_SWITCH "-init"
2527 #define LD_FINI_SWITCH "-fini"
2529 /* The system headers under Alpha systems are generally C++-aware. */
2530 #define NO_IMPLICIT_EXTERN_C
2532 /* Generate calls to memcpy, etc., not bcopy, etc. */
2533 #define TARGET_MEM_FUNCTIONS 1
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