1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* For C++ we need to ensure that __LANGUAGE_C_PLUS_PLUS is defined independent
25 of the source file extension. */
26 #define CPLUSPLUS_CPP_SPEC "\
27 -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus \
31 /* Write out the correct language type definition for the header files.
32 Unless we have assembler language, write out the symbols for C. */
35 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
36 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
37 %{!.S:%{!.cc:%{!.cxx:%{!.cpp:%{!.cp:%{!.c++:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}}}}\
39 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
40 %(cpp_cpu) %(cpp_subtarget)"
42 #ifndef CPP_SUBTARGET_SPEC
43 #define CPP_SUBTARGET_SPEC ""
46 /* Set the spec to use for signed char. The default tests the above macro
47 but DEC's compiler can't handle the conditional in a "constant"
50 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
52 #define WORD_SWITCH_TAKES_ARG(STR) \
53 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
55 /* Print subsidiary information on the compiler version in use. */
56 #define TARGET_VERSION
58 /* Run-time compilation parameters selecting different hardware subsets. */
60 /* Which processor to schedule for. The cpu attribute defines a list that
61 mirrors this list, so changes to alpha.md must be made at the same time. */
64 {PROCESSOR_EV4, /* 2106[46]{a,} */
65 PROCESSOR_EV5, /* 21164{a,pc,} */
66 PROCESSOR_EV6}; /* 21264 */
68 extern enum processor_type alpha_cpu;
70 enum alpha_trap_precision
72 ALPHA_TP_PROG, /* No precision (default). */
73 ALPHA_TP_FUNC, /* Trap contained within originating function. */
74 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
77 enum alpha_fp_rounding_mode
79 ALPHA_FPRM_NORM, /* Normal rounding mode. */
80 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
81 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
82 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
85 enum alpha_fp_trap_mode
87 ALPHA_FPTM_N, /* Normal trap mode. */
88 ALPHA_FPTM_U, /* Underflow traps enabled. */
89 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
90 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
93 extern int target_flags;
95 extern enum alpha_trap_precision alpha_tp;
96 extern enum alpha_fp_rounding_mode alpha_fprm;
97 extern enum alpha_fp_trap_mode alpha_fptm;
99 /* This means that floating-point support exists in the target implementation
100 of the Alpha architecture. This is usually the default. */
101 #define MASK_FP (1 << 0)
102 #define TARGET_FP (target_flags & MASK_FP)
104 /* This means that floating-point registers are allowed to be used. Note
105 that Alpha implementations without FP operations are required to
106 provide the FP registers. */
108 #define MASK_FPREGS (1 << 1)
109 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
111 /* This means that gas is used to process the assembler file. */
113 #define MASK_GAS (1 << 2)
114 #define TARGET_GAS (target_flags & MASK_GAS)
116 /* This means that we should mark procedures as IEEE conformant. */
118 #define MASK_IEEE_CONFORMANT (1 << 3)
119 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
121 /* This means we should be IEEE-compliant except for inexact. */
123 #define MASK_IEEE (1 << 4)
124 #define TARGET_IEEE (target_flags & MASK_IEEE)
126 /* This means we should be fully IEEE-compliant. */
128 #define MASK_IEEE_WITH_INEXACT (1 << 5)
129 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
131 /* This means we must construct all constants rather than emitting
132 them as literal data. */
134 #define MASK_BUILD_CONSTANTS (1 << 6)
135 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
137 /* This means we handle floating points in VAX F- (float)
138 or G- (double) Format. */
140 #define MASK_FLOAT_VAX (1 << 7)
141 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
143 /* This means that the processor has byte and half word loads and stores
144 (the BWX extension). */
146 #define MASK_BWX (1 << 8)
147 #define TARGET_BWX (target_flags & MASK_BWX)
149 /* This means that the processor has the MAX extension. */
150 #define MASK_MAX (1 << 9)
151 #define TARGET_MAX (target_flags & MASK_MAX)
153 /* This means that the processor has the FIX extension. */
154 #define MASK_FIX (1 << 10)
155 #define TARGET_FIX (target_flags & MASK_FIX)
157 /* This means that the processor has the CIX extension. */
158 #define MASK_CIX (1 << 11)
159 #define TARGET_CIX (target_flags & MASK_CIX)
161 /* This means use !literal style explicit relocations. */
162 #define MASK_EXPLICIT_RELOCS (1 << 12)
163 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
165 /* This means use 16-bit relocations to .sdata/.sbss. */
166 #define MASK_SMALL_DATA (1 << 13)
167 #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
169 /* This means that the processor is an EV5, EV56, or PCA56.
170 Unlike alpha_cpu this is not affected by -mtune= setting. */
171 #define MASK_CPU_EV5 (1 << 28)
172 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
174 /* Likewise for EV6. */
175 #define MASK_CPU_EV6 (1 << 29)
176 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
178 /* This means we support the .arch directive in the assembler. Only
179 defined in TARGET_CPU_DEFAULT. */
180 #define MASK_SUPPORT_ARCH (1 << 30)
181 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
183 /* These are for target os support and cannot be changed at runtime. */
184 #define TARGET_ABI_WINDOWS_NT 0
185 #define TARGET_ABI_OPEN_VMS 0
186 #define TARGET_ABI_UNICOSMK 0
187 #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \
188 && !TARGET_ABI_OPEN_VMS \
189 && !TARGET_ABI_UNICOSMK)
191 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
192 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
194 #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX
195 #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS
197 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
198 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
200 #ifndef TARGET_HAS_XFLOATING_LIBS
201 #define TARGET_HAS_XFLOATING_LIBS 0
203 #ifndef TARGET_PROFILING_NEEDS_GP
204 #define TARGET_PROFILING_NEEDS_GP 0
206 #ifndef TARGET_LD_BUGGY_LDGP
207 #define TARGET_LD_BUGGY_LDGP 0
210 /* Macro to define tables used to set the flags.
211 This is a list in braces of pairs in braces,
212 each pair being { "NAME", VALUE }
213 where VALUE is the bits to set or minus the bits to clear.
214 An empty string NAME is used to identify the default VALUE. */
216 #define TARGET_SWITCHES \
217 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
218 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
219 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
220 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
221 N_("Do not use fp registers")}, \
222 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
223 {"gas", MASK_GAS, N_("Assume GAS")}, \
224 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
225 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
226 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
227 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
228 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
229 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
230 {"build-constants", MASK_BUILD_CONSTANTS, \
231 N_("Do not emit complex integer constants to read-only memory")}, \
232 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
233 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
234 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
235 {"no-bwx", -MASK_BWX, ""}, \
237 N_("Emit code for the motion video ISA extension")}, \
238 {"no-max", -MASK_MAX, ""}, \
240 N_("Emit code for the fp move and sqrt ISA extension")}, \
241 {"no-fix", -MASK_FIX, ""}, \
242 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
243 {"no-cix", -MASK_CIX, ""}, \
244 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
245 N_("Emit code using explicit relocation directives")}, \
246 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
247 {"small-data", MASK_SMALL_DATA, \
248 N_("Emit 16-bit relocations to the small data areas")}, \
249 {"large-data", -MASK_SMALL_DATA, \
250 N_("Emit 32-bit relocations to the small data areas")}, \
251 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
253 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
255 #ifndef TARGET_CPU_DEFAULT
256 #define TARGET_CPU_DEFAULT 0
259 /* This macro is similar to `TARGET_SWITCHES' but defines names of
260 command options that have values. Its definition is an initializer
261 with a subgrouping for each command option.
263 Each subgrouping contains a string constant, that defines the fixed
264 part of the option name, and the address of a variable. The
265 variable, type `char *', is set to the variable part of the given
266 option if the fixed part matches. The actual option name is made
267 by appending `-m' to the specified name.
269 Here is an example which defines `-mshort-data-NUMBER'. If the
270 given option is `-mshort-data-512', the variable `m88k_short_data'
271 will be set to the string `"512"'.
273 extern char *m88k_short_data;
274 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
276 extern const char *alpha_cpu_string; /* For -mcpu= */
277 extern const char *alpha_tune_string; /* For -mtune= */
278 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
279 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
280 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
281 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
283 #define TARGET_OPTIONS \
285 {"cpu=", &alpha_cpu_string, \
286 N_("Use features of and schedule given CPU")}, \
287 {"tune=", &alpha_tune_string, \
288 N_("Schedule given CPU")}, \
289 {"fp-rounding-mode=", &alpha_fprm_string, \
290 N_("Control the generated fp rounding mode")}, \
291 {"fp-trap-mode=", &alpha_fptm_string, \
292 N_("Control the IEEE trap mode")}, \
293 {"trap-precision=", &alpha_tp_string, \
294 N_("Control the precision given to fp exceptions")}, \
295 {"memory-latency=", &alpha_mlat_string, \
296 N_("Tune expected memory latency")}, \
299 /* Attempt to describe CPU characteristics to the preprocessor. */
301 /* Corresponding to amask... */
302 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx"
303 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max"
304 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix"
305 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix"
307 /* Corresponding to implver... */
308 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4"
309 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5"
310 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6"
312 /* Common combinations. */
313 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
314 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
315 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
316 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
317 #define CPP_CPU_EV6_SPEC \
318 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
319 #define CPP_CPU_EV67_SPEC \
320 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
322 #ifndef CPP_CPU_DEFAULT_SPEC
323 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
324 # if TARGET_CPU_DEFAULT & MASK_CIX
325 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
327 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
330 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
331 # if TARGET_CPU_DEFAULT & MASK_MAX
332 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
334 # if TARGET_CPU_DEFAULT & MASK_BWX
335 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
337 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
341 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
344 #endif /* CPP_CPU_DEFAULT_SPEC */
347 #define CPP_CPU_SPEC "\
348 %{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \
349 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
350 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
351 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
352 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
353 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
354 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
355 %{!mcpu*:%(cpp_cpu_default) }}"
358 /* This macro defines names of additional specifications to put in the
359 specs that can be used in various specifications like CC1_SPEC. Its
360 definition is an initializer with a subgrouping for each command option.
362 Each subgrouping contains a string constant, that defines the
363 specification name, and a string constant that used by the GNU CC driver
366 Do not define this macro if it does not need to do anything. */
368 #ifndef SUBTARGET_EXTRA_SPECS
369 #define SUBTARGET_EXTRA_SPECS
372 #define EXTRA_SPECS \
373 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
374 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
375 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
376 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
377 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
378 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
379 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
380 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
381 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
382 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
383 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
384 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
385 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
386 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
387 { "cpp_cpu", CPP_CPU_SPEC }, \
388 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
389 SUBTARGET_EXTRA_SPECS
392 /* Sometimes certain combinations of command options do not make sense
393 on a particular target machine. You can define a macro
394 `OVERRIDE_OPTIONS' to take account of this. This macro, if
395 defined, is executed once just after all the command options have
398 On the Alpha, it is used to translate target-option strings into
401 #define OVERRIDE_OPTIONS override_options ()
404 /* Define this macro to change register usage conditional on target flags.
406 On the Alpha, we use this to disable the floating-point registers when
409 #define CONDITIONAL_REGISTER_USAGE \
412 if (! TARGET_FPREGS) \
413 for (i = 32; i < 63; i++) \
414 fixed_regs[i] = call_used_regs[i] = 1; \
418 /* Show we can debug even without a frame pointer. */
419 #define CAN_DEBUG_WITHOUT_FP
421 /* target machine storage layout */
423 /* Define to enable software floating point emulation. */
424 #define REAL_ARITHMETIC
426 /* Define the size of `int'. The default is the same as the word size. */
427 #define INT_TYPE_SIZE 32
429 /* Define the size of `long long'. The default is the twice the word size. */
430 #define LONG_LONG_TYPE_SIZE 64
432 /* The two floating-point formats we support are S-floating, which is
433 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
434 and `long double' are T. */
436 #define FLOAT_TYPE_SIZE 32
437 #define DOUBLE_TYPE_SIZE 64
438 #define LONG_DOUBLE_TYPE_SIZE 64
440 #define WCHAR_TYPE "unsigned int"
441 #define WCHAR_TYPE_SIZE 32
443 /* Define this macro if it is advisable to hold scalars in registers
444 in a wider mode than that declared by the program. In such cases,
445 the value is constrained to be within the bounds of the declared
446 type, but kept valid in the wider mode. The signedness of the
447 extension may differ from that of the type.
449 For Alpha, we always store objects in a full register. 32-bit objects
450 are always sign-extended, but smaller objects retain their signedness. */
452 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
453 if (GET_MODE_CLASS (MODE) == MODE_INT \
454 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
456 if ((MODE) == SImode) \
461 /* Define this if function arguments should also be promoted using the above
464 #define PROMOTE_FUNCTION_ARGS
466 /* Likewise, if the function return value is promoted. */
468 #define PROMOTE_FUNCTION_RETURN
470 /* Define this if most significant bit is lowest numbered
471 in instructions that operate on numbered bit-fields.
473 There are no such instructions on the Alpha, but the documentation
475 #define BITS_BIG_ENDIAN 0
477 /* Define this if most significant byte of a word is the lowest numbered.
478 This is false on the Alpha. */
479 #define BYTES_BIG_ENDIAN 0
481 /* Define this if most significant word of a multiword number is lowest
484 For Alpha we can decide arbitrarily since there are no machine instructions
485 for them. Might as well be consistent with bytes. */
486 #define WORDS_BIG_ENDIAN 0
488 /* number of bits in an addressable storage unit */
489 #define BITS_PER_UNIT 8
491 /* Width in bits of a "word", which is the contents of a machine register.
492 Note that this is not necessarily the width of data type `int';
493 if using 16-bit ints on a 68000, this would still be 32.
494 But on a machine with 16-bit registers, this would be 16. */
495 #define BITS_PER_WORD 64
497 /* Width of a word, in units (bytes). */
498 #define UNITS_PER_WORD 8
500 /* Width in bits of a pointer.
501 See also the macro `Pmode' defined below. */
502 #define POINTER_SIZE 64
504 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
505 #define PARM_BOUNDARY 64
507 /* Boundary (in *bits*) on which stack pointer should be aligned. */
508 #define STACK_BOUNDARY 64
510 /* Allocation boundary (in *bits*) for the code of a function. */
511 #define FUNCTION_BOUNDARY 32
513 /* Alignment of field after `int : 0' in a structure. */
514 #define EMPTY_FIELD_BOUNDARY 64
516 /* Every structure's size must be a multiple of this. */
517 #define STRUCTURE_SIZE_BOUNDARY 8
519 /* A bitfield declared as `int' forces `int' alignment for the struct. */
520 #define PCC_BITFIELD_TYPE_MATTERS 1
522 /* No data type wants to be aligned rounder than this. */
523 #define BIGGEST_ALIGNMENT 128
525 /* For atomic access to objects, must have at least 32-bit alignment
526 unless the machine has byte operations. */
527 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
529 /* Align all constants and variables to at least a word boundary so
530 we can pick up pieces of them faster. */
531 /* ??? Only if block-move stuff knows about different source/destination
534 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
535 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
538 /* Set this non-zero if move instructions will actually fail to work
539 when given unaligned data.
541 Since we get an error message when we do one, call them invalid. */
543 #define STRICT_ALIGNMENT 1
545 /* Set this non-zero if unaligned move instructions are extremely slow.
547 On the Alpha, they trap. */
549 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
551 /* Standard register usage. */
553 /* Number of actual hardware registers.
554 The hardware registers are assigned numbers for the compiler
555 from 0 to just below FIRST_PSEUDO_REGISTER.
556 All registers that the compiler knows about must be given numbers,
557 even those that are not normally considered general registers.
559 We define all 32 integer registers, even though $31 is always zero,
560 and all 32 floating-point registers, even though $f31 is also
561 always zero. We do not bother defining the FP status register and
562 there are no other registers.
564 Since $31 is always zero, we will use register number 31 as the
565 argument pointer. It will never appear in the generated code
566 because we will always be eliminating it in favor of the stack
567 pointer or hardware frame pointer.
569 Likewise, we use $f31 for the frame pointer, which will always
570 be eliminated in favor of the hardware frame pointer or the
573 #define FIRST_PSEUDO_REGISTER 64
575 /* 1 for registers that have pervasive standard uses
576 and are not available for the register allocator. */
578 #define FIXED_REGISTERS \
579 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
584 /* 1 for registers not available across function calls.
585 These must include the FIXED_REGISTERS and also any
586 registers that can be used without being saved.
587 The latter must include the registers where values are returned
588 and the register where structure-value addresses are passed.
589 Aside from that, you can include as many other registers as you like. */
590 #define CALL_USED_REGISTERS \
591 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
593 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
596 /* List the order in which to allocate registers. Each register must be
597 listed once, even those in FIXED_REGISTERS.
599 We allocate in the following order:
600 $f10-$f15 (nonsaved floating-point register)
602 $f21-$f16 (likewise, but input args)
603 $f0 (nonsaved, but return value)
604 $f1 (nonsaved, but immediate before saved)
605 $f2-$f9 (saved floating-point registers)
606 $1-$8 (nonsaved integer registers)
609 $0 (likewise, but return value)
610 $21-$16 (likewise, but input args)
611 $27 (procedure value in OSF, nonsaved in NT)
612 $9-$14 (saved integer registers)
616 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
618 #define REG_ALLOC_ORDER \
619 {42, 43, 44, 45, 46, 47, \
620 54, 55, 56, 57, 58, 59, 60, 61, 62, \
621 53, 52, 51, 50, 49, 48, \
623 34, 35, 36, 37, 38, 39, 40, 41, \
624 1, 2, 3, 4, 5, 6, 7, 8, \
628 21, 20, 19, 18, 17, 16, \
630 9, 10, 11, 12, 13, 14, \
636 /* Return number of consecutive hard regs needed starting at reg REGNO
637 to hold something of mode MODE.
638 This is ordinarily the length in words of a value of mode MODE
639 but can be less for certain modes in special long registers. */
641 #define HARD_REGNO_NREGS(REGNO, MODE) \
642 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
644 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
645 On Alpha, the integer registers can hold any mode. The floating-point
646 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
649 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
650 ((REGNO) >= 32 && (REGNO) <= 62 \
651 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
654 /* A C expression that is nonzero if a value of mode
655 MODE1 is accessible in mode MODE2 without copying.
657 This asymmetric test is true when MODE1 could be put
658 in an FP register but MODE2 could not. */
660 #define MODES_TIEABLE_P(MODE1, MODE2) \
661 (HARD_REGNO_MODE_OK (32, (MODE1)) \
662 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
665 /* Specify the registers used for certain standard purposes.
666 The values of these macros are register numbers. */
668 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
669 /* #define PC_REGNUM */
671 /* Register to use for pushing function arguments. */
672 #define STACK_POINTER_REGNUM 30
674 /* Base register for access to local variables of the function. */
675 #define HARD_FRAME_POINTER_REGNUM 15
677 /* Value should be nonzero if functions must have frame pointers.
678 Zero means the frame pointer need not be set up (and parms
679 may be accessed via the stack pointer) in functions that seem suitable.
680 This is computed in `reload', in reload1.c. */
681 #define FRAME_POINTER_REQUIRED 0
683 /* Base register for access to arguments of the function. */
684 #define ARG_POINTER_REGNUM 31
686 /* Base register for access to local variables of function. */
687 #define FRAME_POINTER_REGNUM 63
689 /* Register in which static-chain is passed to a function.
691 For the Alpha, this is based on an example; the calling sequence
692 doesn't seem to specify this. */
693 #define STATIC_CHAIN_REGNUM 1
695 /* The register number of the register used to address a table of
696 static data addresses in memory. */
697 #define PIC_OFFSET_TABLE_REGNUM 29
699 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM'
700 is clobbered by calls. */
701 /* ??? It is and it isn't. It's required to be valid for a given
702 function when the function returns. It isn't clobbered by
703 current_file functions. Moreover, we do not expose the ldgp
704 until after reload, so we're probably safe. */
705 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
707 /* Register in which address to store a structure value
708 arrives in the function. On the Alpha, the address is passed
709 as a hidden argument. */
710 #define STRUCT_VALUE 0
712 /* Define the classes of registers for register constraints in the
713 machine description. Also define ranges of constants.
715 One of the classes must always be named ALL_REGS and include all hard regs.
716 If there is more than one class, another class must be named NO_REGS
717 and contain no registers.
719 The name GENERAL_REGS must be the name of a class (or an alias for
720 another name such as ALL_REGS). This is the class of registers
721 that is allowed by "g" or "r" in a register constraint.
722 Also, registers outside this class are allocated only when
723 instructions express preferences for them.
725 The classes must be numbered in nondecreasing order; that is,
726 a larger-numbered class must never be contained completely
727 in a smaller-numbered class.
729 For any two classes, it is very desirable that there be another
730 class that represents their union. */
733 NO_REGS, R24_REG, R25_REG, R27_REG,
734 GENERAL_REGS, FLOAT_REGS, ALL_REGS,
738 #define N_REG_CLASSES (int) LIM_REG_CLASSES
740 /* Give names of register classes as strings for dump file. */
742 #define REG_CLASS_NAMES \
743 {"NO_REGS", "R24_REG", "R25_REG", "R27_REG", \
744 "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
746 /* Define which registers fit in which classes.
747 This is an initializer for a vector of HARD_REG_SET
748 of length N_REG_CLASSES. */
750 #define REG_CLASS_CONTENTS \
751 { {0x00000000, 0x00000000}, /* NO_REGS */ \
752 {0x01000000, 0x00000000}, /* R24_REG */ \
753 {0x02000000, 0x00000000}, /* R25_REG */ \
754 {0x08000000, 0x00000000}, /* R27_REG */ \
755 {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \
756 {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \
757 {0xffffffff, 0xffffffff} }
759 /* The same information, inverted:
760 Return the class number of the smallest class containing
761 reg number REGNO. This could be a conditional expression
762 or could index an array. */
764 #define REGNO_REG_CLASS(REGNO) \
765 ((REGNO) == 24 ? R24_REG \
766 : (REGNO) == 25 ? R25_REG \
767 : (REGNO) == 27 ? R27_REG \
768 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
771 /* The class value for index registers, and the one for base regs. */
772 #define INDEX_REG_CLASS NO_REGS
773 #define BASE_REG_CLASS GENERAL_REGS
775 /* Get reg_class from a letter such as appears in the machine description. */
777 #define REG_CLASS_FROM_LETTER(C) \
778 ((C) == 'a' ? R24_REG \
779 : (C) == 'b' ? R25_REG \
780 : (C) == 'c' ? R27_REG \
781 : (C) == 'f' ? FLOAT_REGS \
784 /* Define this macro to change register usage conditional on target flags. */
785 /* #define CONDITIONAL_REGISTER_USAGE */
787 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
788 can be used to stand for particular ranges of immediate operands.
789 This macro defines what the ranges are.
790 C is the letter, and VALUE is a constant value.
791 Return 1 if VALUE is in the range specified by C.
794 `I' is used for the range of constants most insns can contain.
795 `J' is the constant zero.
796 `K' is used for the constant in an LDA insn.
797 `L' is used for the constant in a LDAH insn.
798 `M' is used for the constants that can be AND'ed with using a ZAP insn.
799 `N' is used for complemented 8-bit constants.
800 `O' is used for negated 8-bit constants.
801 `P' is used for the constants 1, 2 and 3. */
803 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
804 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
805 : (C) == 'J' ? (VALUE) == 0 \
806 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
807 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
808 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
809 : (C) == 'M' ? zap_mask (VALUE) \
810 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
811 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
812 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
815 /* Similar, but for floating or large integer constants, and defining letters
816 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
818 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
819 that is the operand of a ZAP insn. */
821 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
822 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
823 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
824 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
825 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
826 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
829 /* Optional extra constraints for this machine.
831 For the Alpha, `Q' means that this is a memory operand but not a
832 reference to an unaligned location.
834 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
837 'S' is a 6-bit constant (valid for a shift insn).
839 'U' is a symbolic operand. */
841 #define EXTRA_CONSTRAINT(OP, C) \
842 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
843 : (C) == 'R' ? direct_call_operand (OP, Pmode) \
844 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
845 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
846 : (C) == 'T' ? GET_CODE (OP) == HIGH \
847 : (TARGET_ABI_UNICOSMK && (C) == 'U') \
848 ? symbolic_operand (OP, VOIDmode) \
851 /* Given an rtx X being reloaded into a reg required to be
852 in class CLASS, return the class of reg to actually use.
853 In general this is just CLASS; but on some machines
854 in some cases it is preferable to use a more restrictive class.
856 On the Alpha, all constants except zero go into a floating-point
857 register via memory. */
859 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
860 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
861 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS \
862 : (CLASS) == ALL_REGS ? GENERAL_REGS : (CLASS)) \
865 /* Loading and storing HImode or QImode values to and from memory
866 usually requires a scratch register. The exceptions are loading
867 QImode and HImode from an aligned address to a general register
868 unless byte instructions are permitted.
869 We also cannot load an unaligned address or a paradoxical SUBREG into an
872 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
873 secondary_reload_class((CLASS), (MODE), (IN), 1)
875 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
876 secondary_reload_class((CLASS), (MODE), (OUT), 0)
878 /* If we are copying between general and FP registers, we need a memory
879 location unless the FIX extension is available. */
881 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
882 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
883 || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))
885 /* Specify the mode to be used for memory when a secondary memory
886 location is needed. If MODE is floating-point, use it. Otherwise,
887 widen to a word like the default. This is needed because we always
888 store integers in FP registers in quadword format. This whole
889 area is very tricky! */
890 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
891 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
892 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
893 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
895 /* Return the maximum number of consecutive registers
896 needed to represent mode MODE in a register of class CLASS. */
898 #define CLASS_MAX_NREGS(CLASS, MODE) \
899 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
901 /* If defined, gives a class of registers that cannot be used as the
902 operand of a SUBREG that changes the mode of the object illegally. */
904 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
906 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
908 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
909 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
911 /* Define the cost of moving between registers of various classes. Moving
912 between FLOAT_REGS and anything else except float regs is expensive.
913 In fact, we make it quite expensive because we really don't want to
914 do these moves unless it is clearly worth it. Optimizations may
915 reduce the impact of not being able to allocate a pseudo to a
918 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
919 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
921 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
923 /* A C expressions returning the cost of moving data of MODE from a register to
926 On the Alpha, bump this up a bit. */
928 extern int alpha_memory_latency;
929 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
931 /* Provide the cost of a branch. Exact meaning under development. */
932 #define BRANCH_COST 5
934 /* Stack layout; function entry, exit and calling. */
936 /* Define this if pushing a word on the stack
937 makes the stack pointer a smaller address. */
938 #define STACK_GROWS_DOWNWARD
940 /* Define this if the nominal address of the stack frame
941 is at the high-address end of the local variables;
942 that is, each additional local variable allocated
943 goes at a more negative offset in the frame. */
944 /* #define FRAME_GROWS_DOWNWARD */
946 /* Offset within stack frame to start allocating local variables at.
947 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
948 first local allocated. Otherwise, it is the offset to the BEGINNING
949 of the first local allocated. */
951 #define STARTING_FRAME_OFFSET 0
953 /* If we generate an insn to push BYTES bytes,
954 this says how many the stack pointer really advances by.
955 On Alpha, don't define this because there are no push insns. */
956 /* #define PUSH_ROUNDING(BYTES) */
958 /* Define this to be nonzero if stack checking is built into the ABI. */
959 #define STACK_CHECK_BUILTIN 1
961 /* Define this if the maximum size of all the outgoing args is to be
962 accumulated and pushed during the prologue. The amount can be
963 found in the variable current_function_outgoing_args_size. */
964 #define ACCUMULATE_OUTGOING_ARGS 1
966 /* Offset of first parameter from the argument pointer register value. */
968 #define FIRST_PARM_OFFSET(FNDECL) 0
970 /* Definitions for register eliminations.
972 We have two registers that can be eliminated on the Alpha. First, the
973 frame pointer register can often be eliminated in favor of the stack
974 pointer register. Secondly, the argument pointer register can always be
975 eliminated; it is replaced with either the stack or frame pointer. */
977 /* This is an array of structures. Each structure initializes one pair
978 of eliminable registers. The "from" register number is given first,
979 followed by "to". Eliminations of the same "from" register are listed
980 in order of preference. */
982 #define ELIMINABLE_REGS \
983 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
984 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
985 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
986 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
988 /* Given FROM and TO register numbers, say whether this elimination is allowed.
989 Frame pointer elimination is automatically handled.
991 All eliminations are valid since the cases where FP can't be
992 eliminated are already handled. */
994 #define CAN_ELIMINATE(FROM, TO) 1
996 /* Round up to a multiple of 16 bytes. */
997 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
999 /* Define the offset between two registers, one to be eliminated, and the other
1000 its replacement, at the start of a routine. */
1001 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1002 { if ((FROM) == FRAME_POINTER_REGNUM) \
1003 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
1004 + alpha_sa_size ()); \
1005 else if ((FROM) == ARG_POINTER_REGNUM) \
1006 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
1007 + alpha_sa_size () \
1008 + (ALPHA_ROUND (get_frame_size () \
1009 + current_function_pretend_args_size) \
1010 - current_function_pretend_args_size)); \
1015 /* Define this if stack space is still allocated for a parameter passed
1017 /* #define REG_PARM_STACK_SPACE */
1019 /* Value is the number of bytes of arguments automatically
1020 popped when returning from a subroutine call.
1021 FUNDECL is the declaration node of the function (as a tree),
1022 FUNTYPE is the data type of the function (as a tree),
1023 or for a library call it is an identifier node for the subroutine name.
1024 SIZE is the number of bytes of arguments passed on the stack. */
1026 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1028 /* Define how to find the value returned by a function.
1029 VALTYPE is the data type of the value (as a tree).
1030 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1031 otherwise, FUNC is 0.
1033 On Alpha the value is found in $0 for integer functions and
1034 $f0 for floating-point functions. */
1036 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1037 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
1038 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1039 || POINTER_TYPE_P (VALTYPE)) \
1040 ? word_mode : TYPE_MODE (VALTYPE), \
1042 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1043 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1046 /* Define how to find the value returned by a library function
1047 assuming the value has mode MODE. */
1049 #define LIBCALL_VALUE(MODE) \
1050 gen_rtx_REG (MODE, \
1052 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1053 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1056 /* The definition of this macro implies that there are cases where
1057 a scalar value cannot be returned in registers.
1059 For the Alpha, any structure or union type is returned in memory, as
1060 are integers whose size is larger than 64 bits. */
1062 #define RETURN_IN_MEMORY(TYPE) \
1063 (TYPE_MODE (TYPE) == BLKmode \
1064 || TYPE_MODE (TYPE) == TFmode \
1065 || TYPE_MODE (TYPE) == TCmode \
1066 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1068 /* 1 if N is a possible register number for a function value
1069 as seen by the caller. */
1071 #define FUNCTION_VALUE_REGNO_P(N) \
1072 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1074 /* 1 if N is a possible register number for function argument passing.
1075 On Alpha, these are $16-$21 and $f16-$f21. */
1077 #define FUNCTION_ARG_REGNO_P(N) \
1078 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1080 /* Define a data type for recording info about an argument list
1081 during the scan of that argument list. This data type should
1082 hold all necessary information about the function itself
1083 and about the args processed so far, enough to enable macros
1084 such as FUNCTION_ARG to determine where the next arg should go.
1086 On Alpha, this is a single integer, which is a number of words
1087 of arguments scanned so far.
1088 Thus 6 or more means all following args should go on the stack. */
1090 #define CUMULATIVE_ARGS int
1092 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1093 for a call to a function whose data type is FNTYPE.
1094 For a library call, FNTYPE is 0. */
1096 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1098 /* Define intermediate macro to compute the size (in registers) of an argument
1101 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1102 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1103 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1104 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1106 /* Update the data in CUM to advance over an argument
1107 of mode MODE and data type TYPE.
1108 (TYPE is null for libcalls where that information may not be available.) */
1110 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1111 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1114 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1116 /* Determine where to put an argument to a function.
1117 Value is zero to push the argument on the stack,
1118 or a hard register in which to store the argument.
1120 MODE is the argument's machine mode.
1121 TYPE is the data type of the argument (as a tree).
1122 This is null for libcalls where that information may
1124 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1125 the preceding args and about the function being called.
1126 NAMED is nonzero if this argument is a named parameter
1127 (otherwise it is an extra parameter matching an ellipsis).
1129 On Alpha the first 6 words of args are normally in registers
1130 and the rest are pushed. */
1132 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1133 function_arg((CUM), (MODE), (TYPE), (NAMED))
1135 /* A C expression that indicates when an argument must be passed by
1136 reference. If nonzero for an argument, a copy of that argument is
1137 made in memory and a pointer to the argument is passed instead of
1138 the argument itself. The pointer is passed in whatever way is
1139 appropriate for passing a pointer to that type. */
1141 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1142 ((MODE) == TFmode || (MODE) == TCmode)
1144 /* Specify the padding direction of arguments.
1146 On the Alpha, we must pad upwards in order to be able to pass args in
1149 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1151 /* For an arg passed partly in registers and partly in memory,
1152 this is the number of registers used.
1153 For args passed entirely in registers or entirely in memory, zero. */
1155 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1156 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1159 /* Perform any needed actions needed for a function that is receiving a
1160 variable number of arguments.
1164 MODE and TYPE are the mode and type of the current parameter.
1166 PRETEND_SIZE is a variable that should be set to the amount of stack
1167 that must be pushed by the prolog to pretend that our caller pushed
1170 Normally, this macro will push all remaining incoming registers on the
1171 stack and set PRETEND_SIZE to the length of the registers pushed.
1173 On the Alpha, we allocate space for all 12 arg registers, but only
1174 push those that are remaining.
1176 However, if NO registers need to be saved, don't allocate any space.
1177 This is not only because we won't need the space, but because AP includes
1178 the current_pretend_args_size and we don't want to mess up any
1179 ap-relative addresses already made.
1181 If we are not to use the floating-point registers, save the integer
1182 registers where we would put the floating-point registers. This is
1183 not the most efficient way to implement varargs with just one register
1184 class, but it isn't worth doing anything more efficient in this rare
1187 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1192 rtx tmp; int set = get_varargs_alias_set (); \
1193 tmp = gen_rtx_MEM (BLKmode, \
1194 plus_constant (virtual_incoming_args_rtx, \
1195 ((CUM) + 6)* UNITS_PER_WORD)); \
1196 set_mem_alias_set (tmp, set); \
1197 move_block_from_reg \
1199 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1201 tmp = gen_rtx_MEM (BLKmode, \
1202 plus_constant (virtual_incoming_args_rtx, \
1203 (CUM) * UNITS_PER_WORD)); \
1204 set_mem_alias_set (tmp, set); \
1205 move_block_from_reg \
1206 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1207 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1209 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1213 /* We do not allow indirect calls to be optimized into sibling calls, nor
1214 can we allow a call to a function in a different compilation unit to
1215 be optimized into a sibcall. Except if the function is known not to
1216 return, in which case our caller doesn't care what the gp is. */
1217 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1219 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1220 || ! TREE_PUBLIC (DECL)))
1222 /* Try to output insns to set TARGET equal to the constant C if it can be
1223 done in less than N insns. Do all computations in MODE. Returns the place
1224 where the output has been placed if it can be done and the insns have been
1225 emitted. If it would take more than N insns, zero is returned and no
1226 insns and emitted. */
1228 /* Define the information needed to generate branch and scc insns. This is
1229 stored from the compare operation. Note that we can't use "rtx" here
1230 since it hasn't been defined! */
1232 struct alpha_compare
1234 struct rtx_def *op0, *op1;
1238 extern struct alpha_compare alpha_compare;
1240 /* Make (or fake) .linkage entry for function call.
1241 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1243 /* This macro defines the start of an assembly comment. */
1245 #define ASM_COMMENT_START " #"
1247 /* This macro produces the initial definition of a function. */
1249 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1250 alpha_start_function(FILE,NAME,DECL);
1252 /* This macro closes up a function definition for the assembler. */
1254 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1255 alpha_end_function(FILE,NAME,DECL)
1257 /* Output any profiling code before the prologue. */
1259 #define PROFILE_BEFORE_PROLOGUE 1
1261 /* Output assembler code to FILE to increment profiler label # LABELNO
1262 for profiling a function entry. Under OSF/1, profiling is enabled
1263 by simply passing -pg to the assembler and linker. */
1265 #define FUNCTION_PROFILER(FILE, LABELNO)
1267 /* Output assembler code to FILE to initialize this source file's
1268 basic block profiling info, if that has not already been done.
1269 This assumes that __bb_init_func doesn't garble a1-a5. */
1271 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1273 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1274 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1275 fputs ("\tldq $26,0($16)\n", (FILE)); \
1276 fputs ("\tbne $26,1f\n", (FILE)); \
1277 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1278 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1279 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1280 fputs ("1:\n", (FILE)); \
1281 ASM_OUTPUT_REG_POP (FILE, 16); \
1284 /* Output assembler code to FILE to increment the entry-count for
1285 the BLOCKNO'th basic block in this source file. */
1287 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1289 int blockn = (BLOCKNO); \
1290 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1291 fputs ("\tstq $26,0($30)\n", (FILE)); \
1292 fputs ("\tstq $27,8($30)\n", (FILE)); \
1293 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1294 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1295 fputs ("\taddq $27,1,$27\n", (FILE)); \
1296 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1297 fputs ("\tldq $26,0($30)\n", (FILE)); \
1298 fputs ("\tldq $27,8($30)\n", (FILE)); \
1299 fputs ("\taddq $30,16,$30\n", (FILE)); \
1303 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1304 the stack pointer does not matter. The value is tested only in
1305 functions that have frame pointers.
1306 No definition is equivalent to always zero. */
1308 #define EXIT_IGNORE_STACK 1
1310 /* Define registers used by the epilogue and return instruction. */
1312 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1314 /* Output assembler code for a block containing the constant parts
1315 of a trampoline, leaving space for the variable parts.
1317 The trampoline should set the static chain pointer to value placed
1318 into the trampoline and should branch to the specified routine.
1319 Note that $27 has been set to the address of the trampoline, so we can
1320 use it for addressability of the two data items. Trampolines are always
1321 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1323 #define TRAMPOLINE_TEMPLATE(FILE) \
1325 fprintf (FILE, "\tldq $1,24($27)\n"); \
1326 fprintf (FILE, "\tldq $27,16($27)\n"); \
1327 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1328 fprintf (FILE, "\tnop\n"); \
1329 fprintf (FILE, "\t.quad 0,0\n"); \
1332 /* Section in which to place the trampoline. On Alpha, instructions
1333 may only be placed in a text segment. */
1335 #define TRAMPOLINE_SECTION text_section
1337 /* Length in units of the trampoline for entering a nested function. */
1339 #define TRAMPOLINE_SIZE 32
1341 /* Emit RTL insns to initialize the variable parts of a trampoline.
1342 FNADDR is an RTX for the address of the function's pure code.
1343 CXT is an RTX for the static chain value for the function. */
1345 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1346 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1348 /* A C expression whose value is RTL representing the value of the return
1349 address for the frame COUNT steps up from the current frame.
1350 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1351 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1353 #define RETURN_ADDR_RTX alpha_return_addr
1355 /* Before the prologue, RA lives in $26. */
1356 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1357 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1359 /* Describe how we implement __builtin_eh_return. */
1360 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
1361 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
1362 #define EH_RETURN_HANDLER_RTX \
1363 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1364 current_function_outgoing_args_size))
1366 /* Addressing modes, and classification of registers for them. */
1368 /* #define HAVE_POST_INCREMENT 0 */
1369 /* #define HAVE_POST_DECREMENT 0 */
1371 /* #define HAVE_PRE_DECREMENT 0 */
1372 /* #define HAVE_PRE_INCREMENT 0 */
1374 /* Macros to check register numbers against specific register classes. */
1376 /* These assume that REGNO is a hard or pseudo reg number.
1377 They give nonzero only if REGNO is a hard reg of the suitable class
1378 or a pseudo reg currently allocated to a suitable hard reg.
1379 Since they use reg_renumber, they are safe only once reg_renumber
1380 has been allocated, which happens in local-alloc.c. */
1382 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1383 #define REGNO_OK_FOR_BASE_P(REGNO) \
1384 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1385 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1387 /* Maximum number of registers that can appear in a valid memory address. */
1388 #define MAX_REGS_PER_ADDRESS 1
1390 /* Recognize any constant value that is a valid address. For the Alpha,
1391 there are only constants none since we want to use LDA to load any
1392 symbolic addresses into registers. */
1394 #define CONSTANT_ADDRESS_P(X) \
1395 (GET_CODE (X) == CONST_INT \
1396 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1398 /* Include all constant integers and constant doubles, but not
1399 floating-point, except for floating-point zero. */
1401 #define LEGITIMATE_CONSTANT_P(X) \
1402 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1403 || (X) == CONST0_RTX (GET_MODE (X)))
1405 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1406 and check its validity for a certain class.
1407 We have two alternate definitions for each of them.
1408 The usual definition accepts all pseudo regs; the other rejects
1409 them unless they have been allocated suitable hard regs.
1410 The symbol REG_OK_STRICT causes the latter definition to be used.
1412 Most source files want to accept pseudo regs in the hope that
1413 they will get allocated to the class that the insn wants them to be in.
1414 Source files for reload pass need to be strict.
1415 After reload, it makes no difference, since pseudo regs have
1416 been eliminated by then. */
1418 /* Nonzero if X is a hard reg that can be used as an index
1419 or if it is a pseudo reg. */
1420 #define REG_OK_FOR_INDEX_P(X) 0
1422 /* Nonzero if X is a hard reg that can be used as a base reg
1423 or if it is a pseudo reg. */
1424 #define NONSTRICT_REG_OK_FOR_BASE_P(X) \
1425 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1427 /* ??? Nonzero if X is the frame pointer, or some virtual register
1428 that may eliminate to the frame pointer. These will be allowed to
1429 have offsets greater than 32K. This is done because register
1430 elimination offsets will change the hi/lo split, and if we split
1431 before reload, we will require additional instructions. */
1432 #define NONSTRICT_REG_OK_FP_BASE_P(X) \
1433 (REGNO (X) == 31 || REGNO (X) == 63 \
1434 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1435 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1437 /* Nonzero if X is a hard reg that can be used as a base reg. */
1438 #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1440 #ifdef REG_OK_STRICT
1441 #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X)
1443 #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X)
1446 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1447 valid memory address for an instruction. */
1449 #ifdef REG_OK_STRICT
1450 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1452 if (alpha_legitimate_address_p (MODE, X, 1)) \
1456 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1458 if (alpha_legitimate_address_p (MODE, X, 0)) \
1463 /* Try machine-dependent ways of modifying an illegitimate address
1464 to be legitimate. If we find one, return the new, valid address.
1465 This macro is used in only one place: `memory_address' in explow.c. */
1467 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1469 rtx new_x = alpha_legitimize_address (X, OLDX, MODE); \
1477 /* Try a machine-dependent way of reloading an illegitimate address
1478 operand. If we find one, push the reload and jump to WIN. This
1479 macro is used in only one place: `find_reloads_address' in reload.c. */
1481 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
1483 rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
1491 /* Go to LABEL if ADDR (a legitimate address expression)
1492 has an effect that depends on the machine mode it is used for.
1493 On the Alpha this is true only for the unaligned modes. We can
1494 simplify this test since we know that the address must be valid. */
1496 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1497 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1499 /* Compute the cost of an address. For the Alpha, all valid addresses are
1502 #define ADDRESS_COST(X) 0
1504 /* Machine-dependent reorg pass. */
1505 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1507 /* Specify the machine mode that this machine uses
1508 for the index in the tablejump instruction. */
1509 #define CASE_VECTOR_MODE SImode
1511 /* Define as C expression which evaluates to nonzero if the tablejump
1512 instruction expects the table to contain offsets from the address of the
1515 Do not define this if the table should contain absolute addresses.
1516 On the Alpha, the table is really GP-relative, not relative to the PC
1517 of the table, but we pretend that it is PC-relative; this should be OK,
1518 but we should try to find some better way sometime. */
1519 #define CASE_VECTOR_PC_RELATIVE 1
1521 /* Specify the tree operation to be used to convert reals to integers. */
1522 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1524 /* This is the kind of divide that is easiest to do in the general case. */
1525 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1527 /* Define this as 1 if `char' should by default be signed; else as 0. */
1528 #define DEFAULT_SIGNED_CHAR 1
1530 /* This flag, if defined, says the same insns that convert to a signed fixnum
1531 also convert validly to an unsigned one.
1533 We actually lie a bit here as overflow conditions are different. But
1534 they aren't being checked anyway. */
1536 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1538 /* Max number of bytes we can move to or from memory
1539 in one reasonably fast instruction. */
1543 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1544 move-instruction pairs, we will do a movstr or libcall instead.
1546 Without byte/word accesses, we want no more than four instructions;
1547 with, several single byte accesses are better. */
1549 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1551 /* Largest number of bytes of an object that can be placed in a register.
1552 On the Alpha we have plenty of registers, so use TImode. */
1553 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1555 /* Nonzero if access to memory by bytes is no faster than for words.
1556 Also non-zero if doing byte operations (specifically shifts) in registers
1559 On the Alpha, we want to not use the byte operation and instead use
1560 masking operations to access fields; these will save instructions. */
1562 #define SLOW_BYTE_ACCESS 1
1564 /* Define if operations between registers always perform the operation
1565 on the full register even if a narrower mode is specified. */
1566 #define WORD_REGISTER_OPERATIONS
1568 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1569 will either zero-extend or sign-extend. The value of this macro should
1570 be the code that says which one of the two operations is implicitly
1571 done, NIL if none. */
1572 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1574 /* Define if loading short immediate values into registers sign extends. */
1575 #define SHORT_IMMEDIATES_SIGN_EXTEND
1577 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1578 is done just by pretending it is already truncated. */
1579 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1581 /* We assume that the store-condition-codes instructions store 0 for false
1582 and some other value for true. This is the value stored for true. */
1584 #define STORE_FLAG_VALUE 1
1586 /* Define the value returned by a floating-point comparison instruction. */
1588 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1589 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1591 /* Canonicalize a comparison from one we don't have to one we do have. */
1593 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1595 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1596 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1601 (CODE) = swap_condition (CODE); \
1603 if (((CODE) == LT || (CODE) == LTU) \
1604 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1606 (CODE) = (CODE) == LT ? LE : LEU; \
1607 (OP1) = GEN_INT (255); \
1611 /* Specify the machine mode that pointers have.
1612 After generation of rtl, the compiler makes no further distinction
1613 between pointers and any other objects of this machine mode. */
1614 #define Pmode DImode
1616 /* Mode of a function address in a call instruction (for indexing purposes). */
1618 #define FUNCTION_MODE Pmode
1620 /* Define this if addresses of constant functions
1621 shouldn't be put through pseudo regs where they can be cse'd.
1622 Desirable on machines where ordinary constants are expensive
1623 but a CALL with constant address is cheap.
1625 We define this on the Alpha so that gen_call and gen_call_value
1626 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1627 then copy it into a register, thus actually letting the address be
1630 #define NO_FUNCTION_CSE
1632 /* Define this to be nonzero if shift instructions ignore all but the low-order
1634 #define SHIFT_COUNT_TRUNCATED 1
1636 /* Compute the cost of computing a constant rtl expression RTX
1637 whose rtx-code is CODE. The body of this macro is a portion
1638 of a switch statement. If the code is computed here,
1639 return it with a return statement. Otherwise, break from the switch.
1641 If this is an 8-bit constant, return zero since it can be used
1642 nearly anywhere with no cost. If it is a valid operand for an
1643 ADD or AND, likewise return 0 if we know it will be used in that
1644 context. Otherwise, return 2 since it might be used there later.
1645 All other constants take at least two insns. */
1647 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1649 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1651 case CONST_DOUBLE: \
1652 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1654 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1655 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1657 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1660 return COSTS_N_INSNS (2); \
1664 switch (alpha_cpu) \
1666 case PROCESSOR_EV4: \
1667 return COSTS_N_INSNS (3); \
1668 case PROCESSOR_EV5: \
1669 case PROCESSOR_EV6: \
1670 return COSTS_N_INSNS (2); \
1674 /* Provide the costs of a rtl expression. This is in the body of a
1677 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1678 case PLUS: case MINUS: \
1679 if (FLOAT_MODE_P (GET_MODE (X))) \
1680 switch (alpha_cpu) \
1682 case PROCESSOR_EV4: \
1683 return COSTS_N_INSNS (6); \
1684 case PROCESSOR_EV5: \
1685 case PROCESSOR_EV6: \
1686 return COSTS_N_INSNS (4); \
1689 else if (GET_CODE (XEXP (X, 0)) == MULT \
1690 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1691 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1692 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1695 switch (alpha_cpu) \
1697 case PROCESSOR_EV4: \
1698 if (FLOAT_MODE_P (GET_MODE (X))) \
1699 return COSTS_N_INSNS (6); \
1700 return COSTS_N_INSNS (23); \
1701 case PROCESSOR_EV5: \
1702 if (FLOAT_MODE_P (GET_MODE (X))) \
1703 return COSTS_N_INSNS (4); \
1704 else if (GET_MODE (X) == DImode) \
1705 return COSTS_N_INSNS (12); \
1707 return COSTS_N_INSNS (8); \
1708 case PROCESSOR_EV6: \
1709 if (FLOAT_MODE_P (GET_MODE (X))) \
1710 return COSTS_N_INSNS (4); \
1712 return COSTS_N_INSNS (7); \
1716 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1717 && INTVAL (XEXP (X, 1)) <= 3) \
1719 /* ... fall through ... */ \
1720 case ASHIFTRT: case LSHIFTRT: \
1721 switch (alpha_cpu) \
1723 case PROCESSOR_EV4: \
1724 return COSTS_N_INSNS (2); \
1725 case PROCESSOR_EV5: \
1726 case PROCESSOR_EV6: \
1727 return COSTS_N_INSNS (1); \
1730 case IF_THEN_ELSE: \
1731 switch (alpha_cpu) \
1733 case PROCESSOR_EV4: \
1734 case PROCESSOR_EV6: \
1735 return COSTS_N_INSNS (2); \
1736 case PROCESSOR_EV5: \
1737 return COSTS_N_INSNS (1); \
1740 case DIV: case UDIV: case MOD: case UMOD: \
1741 switch (alpha_cpu) \
1743 case PROCESSOR_EV4: \
1744 if (GET_MODE (X) == SFmode) \
1745 return COSTS_N_INSNS (34); \
1746 else if (GET_MODE (X) == DFmode) \
1747 return COSTS_N_INSNS (63); \
1749 return COSTS_N_INSNS (70); \
1750 case PROCESSOR_EV5: \
1751 if (GET_MODE (X) == SFmode) \
1752 return COSTS_N_INSNS (15); \
1753 else if (GET_MODE (X) == DFmode) \
1754 return COSTS_N_INSNS (22); \
1756 return COSTS_N_INSNS (70); /* ??? */ \
1757 case PROCESSOR_EV6: \
1758 if (GET_MODE (X) == SFmode) \
1759 return COSTS_N_INSNS (12); \
1760 else if (GET_MODE (X) == DFmode) \
1761 return COSTS_N_INSNS (15); \
1763 return COSTS_N_INSNS (70); /* ??? */ \
1767 switch (alpha_cpu) \
1769 case PROCESSOR_EV4: \
1770 case PROCESSOR_EV6: \
1771 return COSTS_N_INSNS (3); \
1772 case PROCESSOR_EV5: \
1773 return COSTS_N_INSNS (2); \
1776 case NEG: case ABS: \
1777 if (! FLOAT_MODE_P (GET_MODE (X))) \
1779 /* ... fall through ... */ \
1780 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1781 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1782 switch (alpha_cpu) \
1784 case PROCESSOR_EV4: \
1785 return COSTS_N_INSNS (6); \
1786 case PROCESSOR_EV5: \
1787 case PROCESSOR_EV6: \
1788 return COSTS_N_INSNS (4); \
1792 /* Control the assembler format that we output. */
1794 /* Output to assembler file text saying following lines
1795 may contain character constants, extra white space, comments, etc. */
1796 #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "")
1798 /* Output to assembler file text saying following lines
1799 no longer contain unusual constructs. */
1800 #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "")
1802 #define TEXT_SECTION_ASM_OP "\t.text"
1804 /* Output before read-only data. */
1806 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1808 /* Output before writable data. */
1810 #define DATA_SECTION_ASM_OP "\t.data"
1812 /* Define an extra section for read-only data, a routine to enter it, and
1813 indicate that it is for read-only data.
1815 The first time we enter the readonly data section for a file, we write
1816 eight bytes of zero. This works around a bug in DEC's assembler in
1817 some versions of OSF/1 V3.x. */
1819 #define EXTRA_SECTIONS readonly_data
1821 #define EXTRA_SECTION_FUNCTIONS \
1823 literal_section () \
1825 if (in_section != readonly_data) \
1827 static int firsttime = 1; \
1829 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1833 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1836 in_section = readonly_data; \
1840 #define READONLY_DATA_SECTION literal_section
1842 /* Define this macro if references to a symbol must be treated differently
1843 depending on something about the variable or function named by the symbol
1844 (such as what section it is in). */
1846 #define ENCODE_SECTION_INFO(DECL) alpha_encode_section_info (DECL)
1848 /* If a variable is weakened, made one only or moved into a different
1849 section, it may be necessary to redo the section info to move the
1850 variable out of sdata. */
1852 #define REDO_SECTION_INFO_P(DECL) \
1853 ((TREE_CODE (DECL) == VAR_DECL) \
1854 && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \
1855 || DECL_SECTION_NAME (DECL) != 0))
1857 #define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
1859 (VAR) = (SYMBOL_NAME); \
1860 if ((VAR)[0] == '@') \
1862 if ((VAR)[0] == '*') \
1866 /* How to refer to registers in assembler output.
1867 This sequence is indexed by compiler's hard-register-number (see above). */
1869 #define REGISTER_NAMES \
1870 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1871 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1872 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1873 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1874 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1875 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1876 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1877 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1879 /* Strip name encoding when emitting labels. */
1881 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1883 const char *name_ = NAME; \
1884 if (*name_ == '@') \
1886 if (*name_ == '*') \
1889 fputs (user_label_prefix, STREAM); \
1890 fputs (name_, STREAM); \
1893 /* This is how to output the definition of a user-level label named NAME,
1894 such as the label on a static function or variable NAME. */
1896 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1897 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1899 /* This is how to output a command to make the user-level label named NAME
1900 defined for reference from other files. */
1902 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1903 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1905 /* The prefix to add to user-visible assembler symbols. */
1907 #define USER_LABEL_PREFIX ""
1909 /* This is how to output an internal numbered label where
1910 PREFIX is the class of label and NUM is the number within the class. */
1912 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1913 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1915 /* This is how to output a label for a jump table. Arguments are the same as
1916 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1919 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1920 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1922 /* This is how to store into the string LABEL
1923 the symbol_ref name of an internal numbered label where
1924 PREFIX is the class of label and NUM is the number within the class.
1925 This is suitable for output with `assemble_name'. */
1927 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1928 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
1930 /* Check a floating-point value for validity for a particular machine mode. */
1932 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1933 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1935 /* This is how to output an assembler line defining a `long double'
1938 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1941 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1942 fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \
1943 t[1] & 0xffffffff, t[0] & 0xffffffff, \
1944 t[3] & 0xffffffff, t[2] & 0xffffffff); \
1947 /* This is how to output an assembler line defining a `double' constant. */
1949 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1952 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1953 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
1954 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1957 /* This is how to output an assembler line defining a `float' constant. */
1959 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1962 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1963 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
1966 /* This is how to output an assembler line defining an `int' constant. */
1968 #define ASM_OUTPUT_INT(FILE,VALUE) \
1969 ( fprintf (FILE, "\t.long "), \
1970 output_addr_const (FILE, (VALUE)), \
1971 fprintf (FILE, "\n"))
1973 /* This is how to output an assembler line defining a `long' constant. */
1975 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1976 ( fprintf (FILE, "\t.quad "), \
1977 output_addr_const (FILE, (VALUE)), \
1978 fprintf (FILE, "\n"))
1980 /* Likewise for `char' and `short' constants. */
1982 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1983 fprintf (FILE, "\t.word %d\n", \
1984 (int)(GET_CODE (VALUE) == CONST_INT \
1985 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
1987 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1988 fprintf (FILE, "\t.byte %d\n", \
1989 (int)(GET_CODE (VALUE) == CONST_INT \
1990 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
1992 /* We use the default ASCII-output routine, except that we don't write more
1993 than 50 characters since the assembler doesn't support very long lines. */
1995 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
1997 FILE *_hide_asm_out_file = (MYFILE); \
1998 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
1999 int _hide_thissize = (MYLENGTH); \
2000 int _size_so_far = 0; \
2002 FILE *asm_out_file = _hide_asm_out_file; \
2003 const unsigned char *p = _hide_p; \
2004 int thissize = _hide_thissize; \
2006 fprintf (asm_out_file, "\t.ascii \""); \
2008 for (i = 0; i < thissize; i++) \
2010 register int c = p[i]; \
2012 if (_size_so_far ++ > 50 && i < thissize - 4) \
2013 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2015 if (c == '\"' || c == '\\') \
2016 putc ('\\', asm_out_file); \
2017 if (c >= ' ' && c < 0177) \
2018 putc (c, asm_out_file); \
2021 fprintf (asm_out_file, "\\%o", c); \
2022 /* After an octal-escape, if a digit follows, \
2023 terminate one string constant and start another. \
2024 The VAX assembler fails to stop reading the escape \
2025 after three digits, so this is the only way we \
2026 can get it to parse the data properly. */ \
2027 if (i < thissize - 1 && ISDIGIT (p[i + 1])) \
2028 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2031 fprintf (asm_out_file, "\"\n"); \
2036 /* To get unaligned data, we have to turn off auto alignment. */
2037 #define UNALIGNED_SHORT_ASM_OP "\t.align 0\n\t.word\t"
2038 #define UNALIGNED_INT_ASM_OP "\t.align 0\n\t.long\t"
2039 #define UNALIGNED_DOUBLE_INT_ASM_OP "\t.align 0\n\t.quad\t"
2041 /* This is how to output an insn to push a register on the stack.
2042 It need not be very fast code. */
2044 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2045 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2046 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2049 /* This is how to output an insn to pop a register from the stack.
2050 It need not be very fast code. */
2052 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2053 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2054 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2057 /* This is how to output an assembler line for a numeric constant byte. */
2059 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2060 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2062 /* This is how to output an element of a case-vector that is absolute.
2063 (Alpha does not use such vectors, but we must define this macro anyway.) */
2065 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2067 /* This is how to output an element of a case-vector that is relative. */
2069 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2070 fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \
2073 /* This is how to output an assembler line
2074 that says to advance the location counter
2075 to a multiple of 2**LOG bytes. */
2077 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2079 fprintf (FILE, "\t.align %d\n", LOG);
2081 /* This is how to advance the location counter by SIZE bytes. */
2083 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2084 fprintf (FILE, "\t.space %d\n", (SIZE))
2086 /* This says how to output an assembler line
2087 to define a global common symbol. */
2089 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2090 ( fputs ("\t.comm ", (FILE)), \
2091 assemble_name ((FILE), (NAME)), \
2092 fprintf ((FILE), ",%d\n", (SIZE)))
2094 /* This says how to output an assembler line
2095 to define a local common symbol. */
2097 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2098 ( fputs ("\t.lcomm ", (FILE)), \
2099 assemble_name ((FILE), (NAME)), \
2100 fprintf ((FILE), ",%d\n", (SIZE)))
2102 /* Store in OUTPUT a string (made with alloca) containing
2103 an assembler-name for a local static variable named NAME.
2104 LABELNO is an integer which is different for each call. */
2106 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2107 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2108 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2111 /* Print operand X (an rtx) in assembler syntax to file FILE.
2112 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2113 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2115 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2117 /* Determine which codes are valid without a following integer. These must
2120 ~ Generates the name of the current function.
2122 / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX
2123 attributes are examined to determine what is appropriate.
2125 , Generates single precision suffix for floating point
2126 instructions (s for IEEE, f for VAX)
2128 - Generates double precision suffix for floating point
2129 instructions (t for IEEE, g for VAX)
2132 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2133 ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \
2134 || (CODE) == '#' || (CODE) == '*')
2136 /* Print a memory address as an operand to reference that memory location. */
2138 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2139 print_operand_address((FILE), (ADDR))
2141 /* Define the codes that are matched by predicates in alpha.c. */
2143 #define PREDICATE_CODES \
2144 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2145 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2146 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2147 {"cint8_operand", {CONST_INT}}, \
2148 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2149 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2150 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2151 {"const48_operand", {CONST_INT}}, \
2152 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2153 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2154 {"mode_mask_operand", {CONST_INT}}, \
2155 {"mul8_operand", {CONST_INT}}, \
2156 {"mode_width_operand", {CONST_INT}}, \
2157 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2158 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2159 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
2160 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2161 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2162 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2163 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2164 {"fp0_operand", {CONST_DOUBLE}}, \
2165 {"current_file_function_operand", {SYMBOL_REF}}, \
2166 {"direct_call_operand", {SYMBOL_REF}}, \
2167 {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2168 {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \
2169 {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \
2170 {"call_operand", {REG, SYMBOL_REF}}, \
2171 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2172 SYMBOL_REF, CONST, LABEL_REF}}, \
2173 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2174 SYMBOL_REF, CONST, LABEL_REF}}, \
2175 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2176 {"aligned_memory_operand", {MEM}}, \
2177 {"unaligned_memory_operand", {MEM}}, \
2178 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2179 {"any_memory_operand", {MEM}}, \
2180 {"hard_fp_register_operand", {SUBREG, REG}}, \
2181 {"hard_int_register_operand", {SUBREG, REG}}, \
2182 {"reg_not_elim_operand", {SUBREG, REG}}, \
2183 {"reg_no_subreg_operand", {REG}}, \
2184 {"addition_operation", {PLUS}}, \
2185 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},
2187 /* Define the `__builtin_va_list' type for the ABI. */
2188 #define BUILD_VA_LIST_TYPE(VALIST) \
2189 (VALIST) = alpha_build_va_list ()
2191 /* Implement `va_start' for varargs and stdarg. */
2192 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2193 alpha_va_start (stdarg, valist, nextarg)
2195 /* Implement `va_arg'. */
2196 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2197 alpha_va_arg (valist, type)
2199 /* Tell collect that the object format is ECOFF. */
2200 #define OBJECT_FORMAT_COFF
2201 #define EXTENDED_COFF
2203 /* If we use NM, pass -g to it so it only lists globals. */
2204 #define NM_FLAGS "-pg"
2206 /* Definitions for debugging. */
2208 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2209 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2210 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2212 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2213 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2217 /* Correct the offset of automatic variables and arguments. Note that
2218 the Alpha debug format wants all automatic variables and arguments
2219 to be in terms of two different offsets from the virtual frame pointer,
2220 which is the stack pointer before any adjustment in the function.
2221 The offset for the argument pointer is fixed for the native compiler,
2222 it is either zero (for the no arguments case) or large enough to hold
2223 all argument registers.
2224 The offset for the auto pointer is the fourth argument to the .frame
2225 directive (local_offset).
2226 To stay compatible with the native tools we use the same offsets
2227 from the virtual frame pointer and adjust the debugger arg/auto offsets
2228 accordingly. These debugger offsets are set up in output_prolog. */
2230 extern long alpha_arg_offset;
2231 extern long alpha_auto_offset;
2232 #define DEBUGGER_AUTO_OFFSET(X) \
2233 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2234 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2237 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2238 alpha_output_lineno (STREAM, LINE)
2240 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2241 alpha_output_filename (STREAM, NAME)
2243 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2244 number, because the real length runs past this up to the next
2245 continuation point. This is really a dbxout.c bug. */
2246 #define DBX_CONTIN_LENGTH 3000
2248 /* By default, turn on GDB extensions. */
2249 #define DEFAULT_GDB_EXTENSIONS 1
2251 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2252 #define NO_DBX_FUNCTION_END 1
2254 /* If we are smuggling stabs through the ALPHA ECOFF object
2255 format, put a comment in front of the .stab<x> operation so
2256 that the ALPHA assembler does not choke. The mips-tfile program
2257 will correctly put the stab into the object file. */
2259 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2260 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2261 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2263 /* Forward references to tags are allowed. */
2264 #define SDB_ALLOW_FORWARD_REFERENCES
2266 /* Unknown tags are also allowed. */
2267 #define SDB_ALLOW_UNKNOWN_REFERENCES
2269 #define PUT_SDB_DEF(a) \
2271 fprintf (asm_out_file, "\t%s.def\t", \
2272 (TARGET_GAS) ? "" : "#"); \
2273 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2274 fputc (';', asm_out_file); \
2277 #define PUT_SDB_PLAIN_DEF(a) \
2279 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2280 (TARGET_GAS) ? "" : "#", (a)); \
2283 #define PUT_SDB_TYPE(a) \
2285 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2288 /* For block start and end, we create labels, so that
2289 later we can figure out where the correct offset is.
2290 The normal .ent/.end serve well enough for functions,
2291 so those are just commented out. */
2293 extern int sdb_label_count; /* block start/end next label # */
2295 #define PUT_SDB_BLOCK_START(LINE) \
2297 fprintf (asm_out_file, \
2298 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2300 (TARGET_GAS) ? "" : "#", \
2303 sdb_label_count++; \
2306 #define PUT_SDB_BLOCK_END(LINE) \
2308 fprintf (asm_out_file, \
2309 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2311 (TARGET_GAS) ? "" : "#", \
2314 sdb_label_count++; \
2317 #define PUT_SDB_FUNCTION_START(LINE)
2319 #define PUT_SDB_FUNCTION_END(LINE)
2321 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2323 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2324 mips-tdump.c to print them out.
2326 These must match the corresponding definitions in gdb/mipsread.c.
2327 Unfortunately, gcc and gdb do not currently share any directories. */
2329 #define CODE_MASK 0x8F300
2330 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2331 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2332 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2334 /* Override some mips-tfile definitions. */
2336 #define SHASH_SIZE 511
2337 #define THASH_SIZE 55
2339 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2341 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2343 /* The system headers under Alpha systems are generally C++-aware. */
2344 #define NO_IMPLICIT_EXTERN_C
2346 /* Generate calls to memcpy, etc., not bcopy, etc. */
2347 #define TARGET_MEM_FUNCTIONS 1
OSDN Git Service
