1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
45 extern char *version_string;
46 extern int rtx_equal_function_value_matters;
48 /* Specify which cpu to schedule for. */
50 enum processor_type alpha_cpu;
51 static char* const alpha_cpu_name[] =
56 /* Specify how accurate floating-point traps need to be. */
58 enum alpha_trap_precision alpha_tp;
60 /* Specify the floating-point rounding mode. */
62 enum alpha_fp_rounding_mode alpha_fprm;
64 /* Specify which things cause traps. */
66 enum alpha_fp_trap_mode alpha_fptm;
68 /* Strings decoded into the above options. */
70 char *alpha_cpu_string; /* -mcpu= */
71 char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
72 char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
73 char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
74 char *alpha_mlat_string; /* -mmemory-latency= */
76 /* Save information from a "cmpxx" operation until the branch or scc is
79 rtx alpha_compare_op0, alpha_compare_op1;
80 int alpha_compare_fp_p;
82 /* Save the name of the current function as used by the assembler. This
83 is used by the epilogue. */
85 char *alpha_function_name;
87 /* Non-zero if inside of a function, because the Alpha asm can't
88 handle .files inside of functions. */
90 static int inside_function = FALSE;
92 /* Nonzero if the current function needs gp. */
94 int alpha_function_needs_gp;
96 /* If non-null, this rtx holds the return address for the function. */
98 static rtx alpha_return_addr_rtx;
100 /* The number of cycles of latency we should assume on memory reads. */
102 int alpha_memory_latency = 3;
104 /* Declarations of static functions. */
105 static void alpha_set_memflags_1 PROTO((rtx, int, int, int));
106 static rtx alpha_emit_set_const_1 PROTO((rtx, enum machine_mode,
107 HOST_WIDE_INT, int));
108 static void add_long_const PROTO((FILE *, HOST_WIDE_INT, int, int, int));
110 /* Compute the size of the save area in the stack. */
112 static void alpha_sa_mask PROTO((unsigned long *imaskP,
113 unsigned long *fmaskP));
115 /* Get the number of args of a function in one of two ways. */
117 #define NUM_ARGS current_function_args_info.num_args
119 #define NUM_ARGS current_function_args_info
129 /* Parse target option strings. */
134 /* 971208 -- EV6 scheduling parameters are still secret, so don't even
135 pretend and just schedule for an EV5 for now. -- r~ */
137 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
138 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
140 if (alpha_cpu_string)
142 if (! strcmp (alpha_cpu_string, "ev4")
143 || ! strcmp (alpha_cpu_string, "21064"))
145 alpha_cpu = PROCESSOR_EV4;
146 target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
148 else if (! strcmp (alpha_cpu_string, "ev5")
149 || ! strcmp (alpha_cpu_string, "21164"))
151 alpha_cpu = PROCESSOR_EV5;
152 target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
154 else if (! strcmp (alpha_cpu_string, "ev56")
155 || ! strcmp (alpha_cpu_string, "21164a"))
157 alpha_cpu = PROCESSOR_EV5;
158 target_flags |= MASK_BWX;
159 target_flags &= ~ (MASK_CIX | MASK_MAX);
161 else if (! strcmp (alpha_cpu_string, "pca56")
162 || ! strcmp (alpha_cpu_string, "21164PC")
163 || ! strcmp (alpha_cpu_string, "21164pc"))
165 alpha_cpu = PROCESSOR_EV5;
166 target_flags |= MASK_BWX | MASK_MAX;
167 target_flags &= ~ MASK_CIX;
169 else if (! strcmp (alpha_cpu_string, "ev6")
170 || ! strcmp (alpha_cpu_string, "21264"))
172 alpha_cpu = PROCESSOR_EV6;
173 target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
176 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
179 alpha_tp = ALPHA_TP_PROG;
180 alpha_fprm = ALPHA_FPRM_NORM;
181 alpha_fptm = ALPHA_FPTM_N;
185 alpha_tp = ALPHA_TP_INSN;
186 alpha_fptm = ALPHA_FPTM_SU;
189 if (TARGET_IEEE_WITH_INEXACT)
191 alpha_tp = ALPHA_TP_INSN;
192 alpha_fptm = ALPHA_FPTM_SUI;
197 if (! strcmp (alpha_tp_string, "p"))
198 alpha_tp = ALPHA_TP_PROG;
199 else if (! strcmp (alpha_tp_string, "f"))
200 alpha_tp = ALPHA_TP_FUNC;
201 else if (! strcmp (alpha_tp_string, "i"))
202 alpha_tp = ALPHA_TP_INSN;
204 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
207 if (alpha_fprm_string)
209 if (! strcmp (alpha_fprm_string, "n"))
210 alpha_fprm = ALPHA_FPRM_NORM;
211 else if (! strcmp (alpha_fprm_string, "m"))
212 alpha_fprm = ALPHA_FPRM_MINF;
213 else if (! strcmp (alpha_fprm_string, "c"))
214 alpha_fprm = ALPHA_FPRM_CHOP;
215 else if (! strcmp (alpha_fprm_string,"d"))
216 alpha_fprm = ALPHA_FPRM_DYN;
218 error ("bad value `%s' for -mfp-rounding-mode switch",
222 if (alpha_fptm_string)
224 if (strcmp (alpha_fptm_string, "n") == 0)
225 alpha_fptm = ALPHA_FPTM_N;
226 else if (strcmp (alpha_fptm_string, "u") == 0)
227 alpha_fptm = ALPHA_FPTM_U;
228 else if (strcmp (alpha_fptm_string, "su") == 0)
229 alpha_fptm = ALPHA_FPTM_SU;
230 else if (strcmp (alpha_fptm_string, "sui") == 0)
231 alpha_fptm = ALPHA_FPTM_SUI;
233 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
236 /* Do some sanity checks on the above option. */
238 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
239 && alpha_tp != ALPHA_TP_INSN)
241 warning ("fp software completion requires -mtrap-precision=i");
242 alpha_tp = ALPHA_TP_INSN;
245 if (TARGET_FLOAT_VAX)
247 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
249 warning ("rounding mode not supported for VAX floats");
250 alpha_fprm = ALPHA_FPRM_NORM;
252 if (alpha_fptm == ALPHA_FPTM_SUI)
254 warning ("trap mode not supported for VAX floats");
255 alpha_fptm = ALPHA_FPTM_SU;
263 if (!alpha_mlat_string)
264 alpha_mlat_string = "L1";
266 if (isdigit (alpha_mlat_string[0])
267 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
269 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
270 && isdigit (alpha_mlat_string[1])
271 && alpha_mlat_string[2] == '\0')
273 static int const cache_latency[][4] =
275 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
276 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
277 { 3, 13, -1 }, /* ev6 -- Ho hum, doesn't exist yet */
280 lat = alpha_mlat_string[1] - '0';
281 if (lat < 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
283 warning ("L%d cache latency unknown for %s",
284 lat, alpha_cpu_name[alpha_cpu]);
288 lat = cache_latency[alpha_cpu][lat-1];
290 else if (! strcmp (alpha_mlat_string, "main"))
292 /* Most current memories have about 370ns latency. This is
293 a reasonable guess for a fast cpu. */
298 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
302 alpha_memory_latency = lat;
306 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
314 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
316 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
322 /* Returns 1 if OP is either the constant zero or a register. If a
323 register, it must be in the proper mode unless MODE is VOIDmode. */
326 reg_or_0_operand (op, mode)
328 enum machine_mode mode;
330 return op == const0_rtx || register_operand (op, mode);
333 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
337 reg_or_6bit_operand (op, mode)
339 enum machine_mode mode;
341 return ((GET_CODE (op) == CONST_INT
342 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
343 || register_operand (op, mode));
347 /* Return 1 if OP is an 8-bit constant or any register. */
350 reg_or_8bit_operand (op, mode)
352 enum machine_mode mode;
354 return ((GET_CODE (op) == CONST_INT
355 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
356 || register_operand (op, mode));
359 /* Return 1 if OP is an 8-bit constant. */
362 cint8_operand (op, mode)
364 enum machine_mode mode;
366 return (GET_CODE (op) == CONST_INT
367 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100);
370 /* Return 1 if the operand is a valid second operand to an add insn. */
373 add_operand (op, mode)
375 enum machine_mode mode;
377 if (GET_CODE (op) == CONST_INT)
378 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
379 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')
380 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
382 return register_operand (op, mode);
385 /* Return 1 if the operand is a valid second operand to a sign-extending
389 sext_add_operand (op, mode)
391 enum machine_mode mode;
393 if (GET_CODE (op) == CONST_INT)
394 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255
395 || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255);
397 return register_operand (op, mode);
400 /* Return 1 if OP is the constant 4 or 8. */
403 const48_operand (op, mode)
405 enum machine_mode mode;
407 return (GET_CODE (op) == CONST_INT
408 && (INTVAL (op) == 4 || INTVAL (op) == 8));
411 /* Return 1 if OP is a valid first operand to an AND insn. */
414 and_operand (op, mode)
416 enum machine_mode mode;
418 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
419 return (zap_mask (CONST_DOUBLE_LOW (op))
420 && zap_mask (CONST_DOUBLE_HIGH (op)));
422 if (GET_CODE (op) == CONST_INT)
423 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
424 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
425 || zap_mask (INTVAL (op)));
427 return register_operand (op, mode);
430 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
433 or_operand (op, mode)
435 enum machine_mode mode;
437 if (GET_CODE (op) == CONST_INT)
438 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
439 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
441 return register_operand (op, mode);
444 /* Return 1 if OP is a constant that is the width, in bits, of an integral
445 mode smaller than DImode. */
448 mode_width_operand (op, mode)
450 enum machine_mode mode;
452 return (GET_CODE (op) == CONST_INT
453 && (INTVAL (op) == 8 || INTVAL (op) == 16 || INTVAL (op) == 32));
456 /* Return 1 if OP is a constant that is the width of an integral machine mode
457 smaller than an integer. */
460 mode_mask_operand (op, mode)
462 enum machine_mode mode;
464 #if HOST_BITS_PER_WIDE_INT == 32
465 if (GET_CODE (op) == CONST_DOUBLE)
466 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == -1;
469 return (GET_CODE (op) == CONST_INT
470 && (INTVAL (op) == 0xff
471 || INTVAL (op) == 0xffff
472 #if HOST_BITS_PER_WIDE_INT == 64
473 || INTVAL (op) == 0xffffffff
478 /* Return 1 if OP is a multiple of 8 less than 64. */
481 mul8_operand (op, mode)
483 enum machine_mode mode;
485 return (GET_CODE (op) == CONST_INT
486 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
487 && (INTVAL (op) & 7) == 0);
490 /* Return 1 if OP is the constant zero in floating-point. */
493 fp0_operand (op, mode)
495 enum machine_mode mode;
497 return (GET_MODE (op) == mode
498 && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode));
501 /* Return 1 if OP is the floating-point constant zero or a register. */
504 reg_or_fp0_operand (op, mode)
506 enum machine_mode mode;
508 return fp0_operand (op, mode) || register_operand (op, mode);
511 /* Return 1 if OP is a register or a constant integer. */
515 reg_or_cint_operand (op, mode)
517 enum machine_mode mode;
519 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
522 /* Return 1 if OP is something that can be reloaded into a register;
523 if it is a MEM, it need not be valid. */
526 some_operand (op, mode)
528 enum machine_mode mode;
530 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
533 switch (GET_CODE (op))
535 case REG: case MEM: case CONST_DOUBLE:
536 case CONST_INT: case LABEL_REF: case SYMBOL_REF: case CONST:
540 return some_operand (SUBREG_REG (op), VOIDmode);
549 /* Return 1 if OP is a valid operand for the source of a move insn. */
552 input_operand (op, mode)
554 enum machine_mode mode;
556 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
559 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
562 switch (GET_CODE (op))
567 /* This handles both the Windows/NT and OSF cases. */
568 return mode == ptr_mode || mode == DImode;
574 if (register_operand (op, mode))
576 /* ... fall through ... */
578 return ((TARGET_BWX || (mode != HImode && mode != QImode))
579 && general_operand (op, mode));
582 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
585 return mode == QImode || mode == HImode || add_operand (op, mode);
594 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
598 current_file_function_operand (op, mode)
600 enum machine_mode mode;
602 return (GET_CODE (op) == SYMBOL_REF
603 && ! profile_flag && ! profile_block_flag
604 && (SYMBOL_REF_FLAG (op)
605 || op == XEXP (DECL_RTL (current_function_decl), 0)));
608 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
611 call_operand (op, mode)
613 enum machine_mode mode;
618 return (GET_CODE (op) == SYMBOL_REF
619 || (GET_CODE (op) == REG
620 && (TARGET_OPEN_VMS || TARGET_WINDOWS_NT || REGNO (op) == 27)));
623 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
624 comparisons are valid in which insn. */
627 alpha_comparison_operator (op, mode)
629 enum machine_mode mode;
631 enum rtx_code code = GET_CODE (op);
633 if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
636 return (code == EQ || code == LE || code == LT
637 || (mode == DImode && (code == LEU || code == LTU)));
640 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
643 alpha_swapped_comparison_operator (op, mode)
645 enum machine_mode mode;
647 enum rtx_code code = GET_CODE (op);
649 if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
652 code = swap_condition (code);
653 return (code == EQ || code == LE || code == LT
654 || (mode == DImode && (code == LEU || code == LTU)));
657 /* Return 1 if OP is a signed comparison operation. */
660 signed_comparison_operator (op, mode)
662 enum machine_mode mode;
664 switch (GET_CODE (op))
666 case EQ: case NE: case LE: case LT: case GE: case GT:
676 /* Return 1 if this is a divide or modulus operator. */
679 divmod_operator (op, mode)
681 enum machine_mode mode;
683 switch (GET_CODE (op))
685 case DIV: case MOD: case UDIV: case UMOD:
695 /* Return 1 if this memory address is a known aligned register plus
696 a constant. It must be a valid address. This means that we can do
697 this as an aligned reference plus some offset.
699 Take into account what reload will do.
701 We could say that out-of-range stack slots are alignable, but that would
702 complicate get_aligned_mem and it isn't worth the trouble since few
703 functions have large stack space. */
706 aligned_memory_operand (op, mode)
708 enum machine_mode mode;
710 if (GET_CODE (op) == SUBREG)
712 if (GET_MODE (op) != mode)
714 op = SUBREG_REG (op);
715 mode = GET_MODE (op);
718 if (reload_in_progress && GET_CODE (op) == REG
719 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
720 op = reg_equiv_mem[REGNO (op)];
722 if (GET_CODE (op) != MEM || GET_MODE (op) != mode
723 || ! memory_address_p (mode, XEXP (op, 0)))
728 if (GET_CODE (op) == PLUS)
731 return (GET_CODE (op) == REG
732 && REGNO_POINTER_ALIGN (REGNO (op)) >= 4);
735 /* Similar, but return 1 if OP is a MEM which is not alignable. */
738 unaligned_memory_operand (op, mode)
740 enum machine_mode mode;
742 if (GET_CODE (op) == SUBREG)
744 if (GET_MODE (op) != mode)
746 op = SUBREG_REG (op);
747 mode = GET_MODE (op);
750 if (reload_in_progress && GET_CODE (op) == REG
751 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
752 op = reg_equiv_mem[REGNO (op)];
754 if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
759 if (! memory_address_p (mode, op))
762 if (GET_CODE (op) == PLUS)
765 return (GET_CODE (op) != REG
766 || REGNO_POINTER_ALIGN (REGNO (op)) < 4);
769 /* Return 1 if OP is either a register or an unaligned memory location. */
772 reg_or_unaligned_mem_operand (op, mode)
774 enum machine_mode mode;
776 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
779 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
782 any_memory_operand (op, mode)
784 enum machine_mode mode;
786 return (GET_CODE (op) == MEM
787 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
788 || (reload_in_progress && GET_CODE (op) == REG
789 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
790 || (reload_in_progress && GET_CODE (op) == SUBREG
791 && GET_CODE (SUBREG_REG (op)) == REG
792 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
795 /* REF is an alignable memory location. Place an aligned SImode
796 reference into *PALIGNED_MEM and the number of bits to shift into
800 get_aligned_mem (ref, paligned_mem, pbitnum)
802 rtx *paligned_mem, *pbitnum;
805 HOST_WIDE_INT offset = 0;
807 if (GET_CODE (ref) == SUBREG)
809 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
810 if (BYTES_BIG_ENDIAN)
811 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
812 - MIN (UNITS_PER_WORD,
813 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
814 ref = SUBREG_REG (ref);
817 if (GET_CODE (ref) == REG)
818 ref = reg_equiv_mem[REGNO (ref)];
820 if (reload_in_progress)
821 base = find_replacement (&XEXP (ref, 0));
823 base = XEXP (ref, 0);
825 if (GET_CODE (base) == PLUS)
826 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
828 *paligned_mem = gen_rtx (MEM, SImode,
829 plus_constant (base, offset & ~3));
830 MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref);
831 MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref);
832 RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref);
834 *pbitnum = GEN_INT ((offset & 3) * 8);
837 /* Similar, but just get the address. Handle the two reload cases.
838 Add EXTRA_OFFSET to the address we return. */
841 get_unaligned_address (ref, extra_offset)
846 HOST_WIDE_INT offset = 0;
848 if (GET_CODE (ref) == SUBREG)
850 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
851 if (BYTES_BIG_ENDIAN)
852 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
853 - MIN (UNITS_PER_WORD,
854 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
855 ref = SUBREG_REG (ref);
858 if (GET_CODE (ref) == REG)
859 ref = reg_equiv_mem[REGNO (ref)];
861 if (reload_in_progress)
862 base = find_replacement (&XEXP (ref, 0));
864 base = XEXP (ref, 0);
866 if (GET_CODE (base) == PLUS)
867 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
869 return plus_constant (base, offset + extra_offset);
872 /* Subfunction of the following function. Update the flags of any MEM
873 found in part of X. */
876 alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
878 int in_struct_p, volatile_p, unchanging_p;
882 switch (GET_CODE (x))
886 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
887 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
892 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
897 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
899 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
904 MEM_IN_STRUCT_P (x) = in_struct_p;
905 MEM_VOLATILE_P (x) = volatile_p;
906 RTX_UNCHANGING_P (x) = unchanging_p;
914 /* Given INSN, which is either an INSN or a SEQUENCE generated to
915 perform a memory operation, look for any MEMs in either a SET_DEST or
916 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
917 REF into each of the MEMs found. If REF is not a MEM, don't do
921 alpha_set_memflags (insn, ref)
925 /* Note that it is always safe to get these flags, though they won't
926 be what we think if REF is not a MEM. */
927 int in_struct_p = MEM_IN_STRUCT_P (ref);
928 int volatile_p = MEM_VOLATILE_P (ref);
929 int unchanging_p = RTX_UNCHANGING_P (ref);
931 if (GET_CODE (ref) != MEM
932 || (! in_struct_p && ! volatile_p && ! unchanging_p))
935 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
938 /* Try to output insns to set TARGET equal to the constant C if it can be
939 done in less than N insns. Do all computations in MODE. Returns the place
940 where the output has been placed if it can be done and the insns have been
941 emitted. If it would take more than N insns, zero is returned and no
942 insns and emitted. */
945 alpha_emit_set_const (target, mode, c, n)
947 enum machine_mode mode;
954 /* Try 1 insn, then 2, then up to N. */
955 for (i = 1; i <= n; i++)
956 if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
962 /* Internal routine for the above to check for N or below insns. */
965 alpha_emit_set_const_1 (target, mode, c, n)
967 enum machine_mode mode;
971 HOST_WIDE_INT new = c;
973 /* Use a pseudo if highly optimizing and still generating RTL. */
975 = (flag_expensive_optimizations && rtx_equal_function_value_matters
979 #if HOST_BITS_PER_WIDE_INT == 64
980 /* We are only called for SImode and DImode. If this is SImode, ensure that
981 we are sign extended to a full word. This does not make any sense when
982 cross-compiling on a narrow machine. */
985 c = (c & 0xffffffff) - 2 * (c & 0x80000000);
988 /* If this is a sign-extended 32-bit constant, we can do this in at most
989 three insns, so do it if we have enough insns left. We always have
990 a sign-extended 32-bit constant when compiling on a narrow machine. */
992 if (HOST_BITS_PER_WIDE_INT != 64
993 || c >> 31 == -1 || c >> 31 == 0)
995 HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
996 HOST_WIDE_INT tmp1 = c - low;
998 = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
999 HOST_WIDE_INT extra = 0;
1001 /* If HIGH will be interpreted as negative but the constant is
1002 positive, we must adjust it to do two ldha insns. */
1004 if ((high & 0x8000) != 0 && c >= 0)
1008 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1011 if (c == low || (low == 0 && extra == 0))
1013 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1014 but that meant that we can't handle INT_MIN on 32-bit machines
1015 (like NT/Alpha), because we recurse indefinitely through
1016 emit_move_insn to gen_movdi. So instead, since we know exactly
1017 what we want, create it explicitly. */
1020 target = gen_reg_rtx (mode);
1021 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (c)));
1024 else if (n >= 2 + (extra != 0))
1026 temp = copy_to_suggested_reg (GEN_INT (low), subtarget, mode);
1029 temp = expand_binop (mode, add_optab, temp, GEN_INT (extra << 16),
1030 subtarget, 0, OPTAB_WIDEN);
1032 return expand_binop (mode, add_optab, temp, GEN_INT (high << 16),
1033 target, 0, OPTAB_WIDEN);
1037 /* If we couldn't do it that way, try some other methods. But if we have
1038 no instructions left, don't bother. Likewise, if this is SImode and
1039 we can't make pseudos, we can't do anything since the expand_binop
1040 and expand_unop calls will widen and try to make pseudos. */
1043 || (mode == SImode && ! rtx_equal_function_value_matters))
1046 #if HOST_BITS_PER_WIDE_INT == 64
1047 /* First, see if can load a value into the target that is the same as the
1048 constant except that all bytes that are 0 are changed to be 0xff. If we
1049 can, then we can do a ZAPNOT to obtain the desired constant. */
1051 for (i = 0; i < 64; i += 8)
1052 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
1053 new |= (HOST_WIDE_INT) 0xff << i;
1055 /* We are only called for SImode and DImode. If this is SImode, ensure that
1056 we are sign extended to a full word. */
1059 new = (new & 0xffffffff) - 2 * (new & 0x80000000);
1062 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
1063 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
1064 target, 0, OPTAB_WIDEN);
1067 /* Next, see if we can load a related constant and then shift and possibly
1068 negate it to get the constant we want. Try this once each increasing
1069 numbers of insns. */
1071 for (i = 1; i < n; i++)
1073 /* First try complementing. */
1074 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
1075 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1077 /* Next try to form a constant and do a left shift. We can do this
1078 if some low-order bits are zero; the exact_log2 call below tells
1079 us that information. The bits we are shifting out could be any
1080 value, but here we'll just try the 0- and sign-extended forms of
1081 the constant. To try to increase the chance of having the same
1082 constant in more than one insn, start at the highest number of
1083 bits to shift, but try all possibilities in case a ZAPNOT will
1086 if ((bits = exact_log2 (c & - c)) > 0)
1087 for (; bits > 0; bits--)
1088 if ((temp = (alpha_emit_set_const
1090 (unsigned HOST_WIDE_INT) c >> bits, i))) != 0
1091 || ((temp = (alpha_emit_set_const
1093 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
1095 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1096 target, 0, OPTAB_WIDEN);
1098 /* Now try high-order zero bits. Here we try the shifted-in bits as
1099 all zero and all ones. Be careful to avoid shifting outside the
1100 mode and to avoid shifting outside the host wide int size. */
1101 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1102 confuse the recursive call and set all of the high 32 bits. */
1104 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1105 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
1106 for (; bits > 0; bits--)
1107 if ((temp = alpha_emit_set_const (subtarget, mode,
1109 || ((temp = (alpha_emit_set_const
1111 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1114 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1115 target, 1, OPTAB_WIDEN);
1117 /* Now try high-order 1 bits. We get that with a sign-extension.
1118 But one bit isn't enough here. Be careful to avoid shifting outside
1119 the mode and to avoid shifting outside the host wide int size. */
1121 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1122 - floor_log2 (~ c) - 2)) > 0)
1123 for (; bits > 0; bits--)
1124 if ((temp = alpha_emit_set_const (subtarget, mode,
1126 || ((temp = (alpha_emit_set_const
1128 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1131 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1132 target, 0, OPTAB_WIDEN);
1138 #if HOST_BITS_PER_WIDE_INT == 64
1139 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1140 fall back to a straight forward decomposition. We do this to avoid
1141 exponential run times encountered when looking for longer sequences
1142 with alpha_emit_set_const. */
1145 alpha_emit_set_long_const (target, c)
1149 /* Use a pseudo if highly optimizing and still generating RTL. */
1151 = (flag_expensive_optimizations && rtx_equal_function_value_matters
1153 HOST_WIDE_INT d1, d2, d3, d4;
1156 /* Decompose the entire word */
1157 d1 = ((c & 0xffff) ^ 0x8000) - 0x8000;
1159 d2 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
1161 d3 = ((c & 0xffff) ^ 0x8000) - 0x8000;
1163 d4 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
1168 /* Construct the high word */
1170 r1 = copy_to_suggested_reg (GEN_INT (d4), subtarget, DImode);
1172 r1 = copy_to_suggested_reg (GEN_INT (d3), subtarget, DImode);
1174 r1 = expand_binop (DImode, add_optab, GEN_INT (d3), GEN_INT (d4),
1175 subtarget, 0, OPTAB_WIDEN);
1177 /* Shift it into place */
1178 r2 = expand_binop (DImode, ashl_optab, r1, GEN_INT (32),
1179 subtarget, 0, OPTAB_WIDEN);
1181 if (subtarget == 0 && d1 == d3 && d2 == d4)
1182 r1 = expand_binop (DImode, add_optab, r1, r2, subtarget, 0, OPTAB_WIDEN);
1187 /* Add in the low word */
1189 r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d2),
1190 subtarget, 0, OPTAB_WIDEN);
1192 r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d1),
1193 subtarget, 0, OPTAB_WIDEN);
1197 r1 = copy_to_suggested_reg(r1, target, DImode);
1201 #endif /* HOST_BITS_PER_WIDE_INT == 64 */
1203 /* Rewrite a comparison against zero CMP of the form
1204 (CODE (cc0) (const_int 0)) so it can be written validly in
1205 a conditional move (if_then_else CMP ...).
1206 If both of the operands that set cc0 are non-zero we must emit
1207 an insn to perform the compare (it can't be done within
1208 the conditional move). */
1210 alpha_emit_conditional_move (cmp, mode)
1212 enum machine_mode mode;
1214 enum rtx_code code = GET_CODE (cmp);
1215 enum rtx_code cmov_code = NE;
1216 rtx op0 = alpha_compare_op0;
1217 rtx op1 = alpha_compare_op1;
1218 enum machine_mode cmp_mode
1219 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
1220 enum machine_mode cmp_op_mode = alpha_compare_fp_p ? DFmode : DImode;
1223 if (alpha_compare_fp_p != FLOAT_MODE_P (mode))
1226 /* We may be able to use a conditional move directly.
1227 This avoids emitting spurious compares. */
1228 if (signed_comparison_operator (cmp, cmp_op_mode)
1229 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
1230 return gen_rtx (code, VOIDmode, op0, op1);
1232 /* We can't put the comparison insides a conditional move;
1233 emit a compare instruction and put that inside the
1234 conditional move. Make sure we emit only comparisons we have;
1235 swap or reverse as necessary. */
1239 case EQ: case LE: case LT: case LEU: case LTU:
1240 /* We have these compares: */
1244 /* This must be reversed. */
1245 code = reverse_condition (code);
1249 case GE: case GT: case GEU: case GTU:
1250 /* These must be swapped. Make sure the new first operand is in
1252 code = swap_condition (code);
1253 tem = op0, op0 = op1, op1 = tem;
1254 op0 = force_reg (cmp_mode, op0);
1261 tem = gen_reg_rtx (cmp_op_mode);
1262 emit_move_insn (tem, gen_rtx (code, cmp_op_mode, op0, op1));
1263 return gen_rtx (cmov_code, VOIDmode, tem, CONST0_RTX (cmp_op_mode));
1266 /* Adjust the cost of a scheduling dependency. Return the new cost of
1267 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
1270 alpha_adjust_cost (insn, link, dep_insn, cost)
1277 enum attr_type insn_type, dep_insn_type;
1279 /* If the dependence is an anti-dependence, there is no cost. For an
1280 output dependence, there is sometimes a cost, but it doesn't seem
1281 worth handling those few cases. */
1283 if (REG_NOTE_KIND (link) != 0)
1286 /* If we can't recognize the insns, we can't really do anything. */
1287 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
1290 insn_type = get_attr_type (insn);
1291 dep_insn_type = get_attr_type (dep_insn);
1293 /* Bring in the user-defined memory latency. */
1294 if (dep_insn_type == TYPE_ILD
1295 || dep_insn_type == TYPE_FLD
1296 || dep_insn_type == TYPE_LDSYM)
1297 cost += alpha_memory_latency-1;
1302 /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
1303 being stored, we can sometimes lower the cost. */
1305 if ((insn_type == TYPE_IST || insn_type == TYPE_FST)
1306 && (set = single_set (dep_insn)) != 0
1307 && GET_CODE (PATTERN (insn)) == SET
1308 && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
1310 switch (dep_insn_type)
1314 /* No savings here. */
1318 /* In these cases, we save one cycle. */
1322 /* In all other cases, we save two cycles. */
1323 return MAX (0, cost - 2);
1327 /* Another case that needs adjustment is an arithmetic or logical
1328 operation. It's cost is usually one cycle, but we default it to
1329 two in the MD file. The only case that it is actually two is
1330 for the address in loads, stores, and jumps. */
1332 if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
1347 /* The final case is when a compare feeds into an integer branch;
1348 the cost is only one cycle in that case. */
1350 if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
1355 /* And the lord DEC saith: "A special bypass provides an effective
1356 latency of 0 cycles for an ICMP or ILOG insn producing the test
1357 operand of an IBR or ICMOV insn." */
1359 if ((dep_insn_type == TYPE_ICMP || dep_insn_type == TYPE_ILOG)
1360 && (set = single_set (dep_insn)) != 0)
1362 /* A branch only has one input. This must be it. */
1363 if (insn_type == TYPE_IBR)
1365 /* A conditional move has three, make sure it is the test. */
1366 if (insn_type == TYPE_ICMOV
1367 && GET_CODE (set_src = PATTERN (insn)) == SET
1368 && GET_CODE (set_src = SET_SRC (set_src)) == IF_THEN_ELSE
1369 && rtx_equal_p (SET_DEST (set), XEXP (set_src, 0)))
1373 /* "The multiplier is unable to receive data from IEU bypass paths.
1374 The instruction issues at the expected time, but its latency is
1375 increased by the time it takes for the input data to become
1376 available to the multiplier" -- which happens in pipeline stage
1377 six, when results are comitted to the register file. */
1379 if (insn_type == TYPE_IMUL)
1381 switch (dep_insn_type)
1383 /* These insns produce their results in pipeline stage five. */
1390 /* Other integer insns produce results in pipeline stage four. */
1398 /* There is additional latency to move the result of (most) FP
1399 operations anywhere but the FP register file. */
1401 if ((insn_type == TYPE_FST || insn_type == TYPE_FTOI)
1402 && (dep_insn_type == TYPE_FADD ||
1403 dep_insn_type == TYPE_FMUL ||
1404 dep_insn_type == TYPE_FCMOV))
1410 /* Otherwise, return the default cost. */
1414 /* Functions to save and restore alpha_return_addr_rtx. */
1416 struct machine_function
1422 alpha_save_machine_status (p)
1425 struct machine_function *machine =
1426 (struct machine_function *) xmalloc (sizeof (struct machine_function));
1428 p->machine = machine;
1429 machine->ra_rtx = alpha_return_addr_rtx;
1433 alpha_restore_machine_status (p)
1436 struct machine_function *machine = p->machine;
1438 alpha_return_addr_rtx = machine->ra_rtx;
1441 p->machine = (struct machine_function *)0;
1444 /* Do anything needed before RTL is emitted for each function. */
1447 alpha_init_expanders ()
1449 alpha_return_addr_rtx = NULL_RTX;
1451 /* Arrange to save and restore machine status around nested functions. */
1452 save_machine_status = alpha_save_machine_status;
1453 restore_machine_status = alpha_restore_machine_status;
1456 /* Start the ball rolling with RETURN_ADDR_RTX. */
1459 alpha_return_addr (count, frame)
1468 if (alpha_return_addr_rtx)
1469 return alpha_return_addr_rtx;
1471 /* No rtx yet. Invent one, and initialize it from $26 in the prologue. */
1472 alpha_return_addr_rtx = gen_reg_rtx (Pmode);
1473 init = gen_rtx (SET, Pmode, alpha_return_addr_rtx, gen_rtx (REG, Pmode, 26));
1475 /* Emit the insn to the prologue with the other argument copies. */
1476 push_topmost_sequence ();
1477 emit_insn_after (init, get_insns ());
1478 pop_topmost_sequence ();
1480 return alpha_return_addr_rtx;
1484 alpha_ra_ever_killed ()
1488 if (!alpha_return_addr_rtx)
1489 return regs_ever_live[REG_RA];
1491 return reg_set_between_p (gen_rtx (REG, REG_RA), get_insns(), NULL_RTX);
1495 /* Print an operand. Recognize special options, documented below. */
1498 print_operand (file, x, code)
1508 /* Generates fp-rounding mode suffix: nothing for normal, 'c' for
1509 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
1510 mode. alpha_fprm controls which suffix is generated. */
1513 case ALPHA_FPRM_NORM:
1515 case ALPHA_FPRM_MINF:
1518 case ALPHA_FPRM_CHOP:
1521 case ALPHA_FPRM_DYN:
1528 /* Generates trap-mode suffix for instructions that accept the su
1529 suffix only (cmpt et al). */
1530 if (alpha_tp == ALPHA_TP_INSN)
1535 /* Generates trap-mode suffix for instructions that accept the u, su,
1536 and sui suffix. This is the bulk of the IEEE floating point
1537 instructions (addt et al). */
1548 case ALPHA_FPTM_SUI:
1549 fputs ("sui", file);
1555 /* Generates trap-mode suffix for instructions that accept the sui
1556 suffix (cvtqt and cvtqs). */
1559 case ALPHA_FPTM_N: case ALPHA_FPTM_U:
1560 case ALPHA_FPTM_SU: /* cvtqt/cvtqs can't cause underflow */
1562 case ALPHA_FPTM_SUI:
1563 fputs ("sui", file);
1569 /* Generates single precision instruction suffix. */
1570 fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'f' : 's'));
1574 /* Generates double precision instruction suffix. */
1575 fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'g' : 't'));
1579 /* If this operand is the constant zero, write it as "$31". */
1580 if (GET_CODE (x) == REG)
1581 fprintf (file, "%s", reg_names[REGNO (x)]);
1582 else if (x == CONST0_RTX (GET_MODE (x)))
1583 fprintf (file, "$31");
1585 output_operand_lossage ("invalid %%r value");
1590 /* Similar, but for floating-point. */
1591 if (GET_CODE (x) == REG)
1592 fprintf (file, "%s", reg_names[REGNO (x)]);
1593 else if (x == CONST0_RTX (GET_MODE (x)))
1594 fprintf (file, "$f31");
1596 output_operand_lossage ("invalid %%R value");
1601 /* Write the 1's complement of a constant. */
1602 if (GET_CODE (x) != CONST_INT)
1603 output_operand_lossage ("invalid %%N value");
1605 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
1609 /* Write 1 << C, for a constant C. */
1610 if (GET_CODE (x) != CONST_INT)
1611 output_operand_lossage ("invalid %%P value");
1613 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
1617 /* Write the high-order 16 bits of a constant, sign-extended. */
1618 if (GET_CODE (x) != CONST_INT)
1619 output_operand_lossage ("invalid %%h value");
1621 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
1625 /* Write the low-order 16 bits of a constant, sign-extended. */
1626 if (GET_CODE (x) != CONST_INT)
1627 output_operand_lossage ("invalid %%L value");
1629 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
1630 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
1634 /* Write mask for ZAP insn. */
1635 if (GET_CODE (x) == CONST_DOUBLE)
1637 HOST_WIDE_INT mask = 0;
1638 HOST_WIDE_INT value;
1640 value = CONST_DOUBLE_LOW (x);
1641 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
1646 value = CONST_DOUBLE_HIGH (x);
1647 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
1650 mask |= (1 << (i + sizeof (int)));
1652 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
1655 else if (GET_CODE (x) == CONST_INT)
1657 HOST_WIDE_INT mask = 0, value = INTVAL (x);
1659 for (i = 0; i < 8; i++, value >>= 8)
1663 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
1666 output_operand_lossage ("invalid %%m value");
1670 /* 'b', 'w', or 'l' as the value of the constant. */
1671 if (GET_CODE (x) != CONST_INT
1672 || (INTVAL (x) != 8 && INTVAL (x) != 16 && INTVAL (x) != 32))
1673 output_operand_lossage ("invalid %%M value");
1675 fprintf (file, "%s",
1676 INTVAL (x) == 8 ? "b" : INTVAL (x) == 16 ? "w" : "l");
1680 /* Similar, except do it from the mask. */
1681 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff)
1682 fprintf (file, "b");
1683 else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
1684 fprintf (file, "w");
1685 #if HOST_BITS_PER_WIDE_INT == 32
1686 else if (GET_CODE (x) == CONST_DOUBLE
1687 && CONST_DOUBLE_HIGH (x) == 0
1688 && CONST_DOUBLE_LOW (x) == -1)
1689 fprintf (file, "l");
1691 else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
1692 fprintf (file, "l");
1695 output_operand_lossage ("invalid %%U value");
1699 /* Write the constant value divided by 8. */
1700 if (GET_CODE (x) != CONST_INT
1701 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
1702 && (INTVAL (x) & 7) != 8)
1703 output_operand_lossage ("invalid %%s value");
1705 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
1709 /* Same, except compute (64 - c) / 8 */
1711 if (GET_CODE (x) != CONST_INT
1712 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
1713 && (INTVAL (x) & 7) != 8)
1714 output_operand_lossage ("invalid %%s value");
1716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
1719 case 'C': case 'D': case 'c': case 'd':
1720 /* Write out comparison name. */
1722 enum rtx_code c = GET_CODE (x);
1724 if (GET_RTX_CLASS (c) != '<')
1725 output_operand_lossage ("invalid %%C value");
1728 c = reverse_condition (c);
1729 else if (code == 'c')
1730 c = swap_condition (c);
1731 else if (code == 'd')
1732 c = swap_condition (reverse_condition (c));
1735 fprintf (file, "ule");
1737 fprintf (file, "ult");
1739 fprintf (file, "%s", GET_RTX_NAME (c));
1744 /* Write the divide or modulus operator. */
1745 switch (GET_CODE (x))
1748 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
1751 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
1754 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
1757 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
1760 output_operand_lossage ("invalid %%E value");
1766 /* Write "_u" for unaligned access. */
1767 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
1768 fprintf (file, "_u");
1772 if (GET_CODE (x) == REG)
1773 fprintf (file, "%s", reg_names[REGNO (x)]);
1774 else if (GET_CODE (x) == MEM)
1775 output_address (XEXP (x, 0));
1777 output_addr_const (file, x);
1781 output_operand_lossage ("invalid %%xn code");
1785 /* Do what is necessary for `va_start'. The argument is ignored;
1786 We look at the current function to determine if stdarg or varargs
1787 is used and fill in an initial va_list. A pointer to this constructor
1791 alpha_builtin_saveregs (arglist)
1794 rtx block, addr, dest, argsize;
1795 tree fntype = TREE_TYPE (current_function_decl);
1796 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
1797 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1798 != void_type_node));
1800 /* Compute the current position into the args, taking into account
1801 both registers and memory. Both of these are already included in
1804 argsize = GEN_INT (NUM_ARGS * UNITS_PER_WORD);
1806 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base up by 48,
1807 storing fp arg registers in the first 48 bytes, and the integer arg
1808 registers in the next 48 bytes. This is only done, however, if any
1809 integer registers need to be stored.
1811 If no integer registers need be stored, then we must subtract 48 in
1812 order to account for the integer arg registers which are counted in
1813 argsize above, but which are not actually stored on the stack. */
1815 if (TARGET_OPEN_VMS)
1816 addr = plus_constant (virtual_incoming_args_rtx,
1817 NUM_ARGS <= 5 + stdarg
1818 ? UNITS_PER_WORD : - 6 * UNITS_PER_WORD);
1820 addr = (NUM_ARGS <= 5 + stdarg
1821 ? plus_constant (virtual_incoming_args_rtx,
1823 : plus_constant (virtual_incoming_args_rtx,
1824 - (6 * UNITS_PER_WORD)));
1826 /* For VMS, we include the argsize, while on Unix, it's handled as
1827 a separate field. */
1828 if (TARGET_OPEN_VMS)
1829 addr = plus_constant (addr, INTVAL (argsize));
1831 addr = force_operand (addr, NULL_RTX);
1833 #ifdef POINTERS_EXTEND_UNSIGNED
1834 addr = convert_memory_address (ptr_mode, addr);
1837 if (TARGET_OPEN_VMS)
1841 /* Allocate the va_list constructor */
1842 block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
1843 RTX_UNCHANGING_P (block) = 1;
1844 RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
1846 /* Store the address of the first integer register in the __base
1849 dest = change_address (block, ptr_mode, XEXP (block, 0));
1850 emit_move_insn (dest, addr);
1852 if (flag_check_memory_usage)
1853 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
1855 GEN_INT (GET_MODE_SIZE (ptr_mode)),
1856 TYPE_MODE (sizetype),
1857 GEN_INT (MEMORY_USE_RW),
1858 TYPE_MODE (integer_type_node));
1860 /* Store the argsize as the __va_offset member. */
1861 dest = change_address (block, TYPE_MODE (integer_type_node),
1862 plus_constant (XEXP (block, 0),
1863 POINTER_SIZE/BITS_PER_UNIT));
1864 emit_move_insn (dest, argsize);
1866 if (flag_check_memory_usage)
1867 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
1869 GEN_INT (GET_MODE_SIZE
1870 (TYPE_MODE (integer_type_node))),
1871 TYPE_MODE (sizetype),
1872 GEN_INT (MEMORY_USE_RW),
1873 TYPE_MODE (integer_type_node));
1875 /* Return the address of the va_list constructor, but don't put it in a
1876 register. Doing so would fail when not optimizing and produce worse
1877 code when optimizing. */
1878 return XEXP (block, 0);
1882 /* This page contains routines that are used to determine what the function
1883 prologue and epilogue code will do and write them out. */
1885 /* Compute the size of the save area in the stack. */
1889 /* These variables are used for communication between the following functions.
1890 They indicate various things about the current function being compiled
1891 that are used to tell what kind of prologue, epilogue and procedure
1892 descriptior to generate. */
1894 /* Nonzero if we need a stack procedure. */
1895 static int is_stack_procedure;
1897 /* Register number (either FP or SP) that is used to unwind the frame. */
1898 static int unwind_regno;
1900 /* Register number used to save FP. We need not have one for RA since
1901 we don't modify it for register procedures. This is only defined
1902 for register frame procedures. */
1903 static int save_fp_regno;
1905 /* Register number used to reference objects off our PV. */
1906 static int base_regno;
1908 /* Compute register masks for saved registers. */
1911 alpha_sa_mask (imaskP, fmaskP)
1912 unsigned long *imaskP;
1913 unsigned long *fmaskP;
1915 unsigned long imask = 0;
1916 unsigned long fmask = 0;
1919 if (is_stack_procedure)
1920 imask |= (1L << HARD_FRAME_POINTER_REGNUM);
1922 /* One for every register we have to save. */
1924 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1925 if (! fixed_regs[i] && ! call_used_regs[i]
1926 && regs_ever_live[i] && i != REG_RA)
1931 fmask |= (1L << (i - 32));
1944 HOST_WIDE_INT stack_needed;
1947 /* One for every register we have to save. */
1949 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1950 if (! fixed_regs[i] && ! call_used_regs[i]
1951 && regs_ever_live[i] && i != REG_RA)
1954 /* Start by assuming we can use a register procedure if we don't make any
1955 calls (REG_RA not used) or need to save any registers and a stack
1956 procedure if we do. */
1957 is_stack_procedure = sa_size != 0 || alpha_ra_ever_killed ();
1959 /* Decide whether to refer to objects off our PV via FP or PV.
1960 If we need need FP for something else or if we receive a nonlocal
1961 goto (which expects PV to contain the value), we must use PV.
1962 Otherwise, start by assuming we can use FP. */
1963 base_regno = (frame_pointer_needed || current_function_has_nonlocal_label
1964 || is_stack_procedure
1965 || current_function_outgoing_args_size
1966 ? REG_PV : HARD_FRAME_POINTER_REGNUM);
1968 /* If we want to copy PV into FP, we need to find some register in which to
1973 if (base_regno == HARD_FRAME_POINTER_REGNUM)
1974 for (i = 0; i < 32; i++)
1975 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
1978 if (save_fp_regno == -1)
1979 base_regno = REG_PV, is_stack_procedure = 1;
1981 /* Stack unwinding should be done via FP unless we use it for PV. */
1983 = base_regno == REG_PV ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
1985 /* If this is a stack procedure, allow space for saving FP and RA. */
1986 if (is_stack_procedure)
1993 alpha_pv_save_size ()
1996 return is_stack_procedure ? 8 : 0;
2003 return unwind_regno == HARD_FRAME_POINTER_REGNUM;
2006 #else /* ! OPEN_VMS */
2014 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2015 if (! fixed_regs[i] && ! call_used_regs[i]
2016 && regs_ever_live[i] && i != REG_RA)
2019 /* If some registers were saved but not reg 26, reg 26 must also
2020 be saved, so leave space for it. */
2021 if (size != 0 || alpha_ra_ever_killed ())
2024 /* Our size must be even (multiple of 16 bytes). */
2031 #endif /* ! OPEN_VMS */
2033 /* Return 1 if this function can directly return via $26. */
2038 return (! TARGET_OPEN_VMS && reload_completed && alpha_sa_size () == 0
2039 && get_frame_size () == 0
2040 && current_function_outgoing_args_size == 0
2041 && current_function_pretend_args_size == 0);
2044 /* Write a version stamp. Don't write anything if we are running as a
2045 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
2047 #if !defined(CROSS_COMPILE) && !defined(_WIN32) && !defined(__linux__) && !defined(VMS)
2052 alpha_write_verstamp (file)
2056 fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
2060 /* Write code to add constant C to register number IN_REG (possibly 31)
2061 and put the result into OUT_REG. Use TEMP_REG as a scratch register;
2062 usually this will be OUT_REG, but should not be if OUT_REG is
2063 STACK_POINTER_REGNUM, since it must be updated in a single instruction.
2064 Write the code to FILE. */
2067 add_long_const (file, c, in_reg, out_reg, temp_reg)
2070 int in_reg, out_reg, temp_reg;
2072 HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
2073 HOST_WIDE_INT tmp1 = c - low;
2074 HOST_WIDE_INT high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2075 HOST_WIDE_INT extra = 0;
2077 /* We don't have code to write out constants larger than 32 bits. */
2078 #if HOST_BITS_PER_LONG_INT == 64
2079 if ((unsigned HOST_WIDE_INT) c >> 32 != 0)
2083 /* If HIGH will be interpreted as negative, we must adjust it to do two
2084 ldha insns. Note that we will never be building a negative constant
2091 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2096 int result_reg = (extra == 0 && high == 0) ? out_reg : temp_reg;
2098 if (low >= 0 && low < 255)
2099 fprintf (file, "\taddq $%d,%d,$%d\n", in_reg, low, result_reg);
2101 fprintf (file, "\tlda $%d,%d($%d)\n", result_reg, low, in_reg);
2103 in_reg = result_reg;
2108 int result_reg = (high == 0) ? out_reg : temp_reg;
2110 fprintf (file, "\tldah $%d,%d($%d)\n", result_reg, extra, in_reg);
2111 in_reg = result_reg;
2115 fprintf (file, "\tldah $%d,%d($%d)\n", out_reg, high, in_reg);
2118 /* Write function prologue. */
2122 /* On vms we have two kinds of functions:
2124 - stack frame (PROC_STACK)
2125 these are 'normal' functions with local vars and which are
2126 calling other functions
2127 - register frame (PROC_REGISTER)
2128 keeps all data in registers, needs no stack
2130 We must pass this to the assembler so it can generate the
2131 proper pdsc (procedure descriptor)
2132 This is done with the '.pdesc' command.
2134 size is the stack size needed for local variables. */
2137 output_prolog (file, size)
2141 unsigned long imask = 0;
2142 unsigned long fmask = 0;
2143 /* Stack space needed for pushing registers clobbered by us. */
2144 HOST_WIDE_INT sa_size;
2145 /* Complete stack size needed. */
2146 HOST_WIDE_INT frame_size;
2147 /* Offset from base reg to register save area. */
2149 /* Offset during register save. */
2151 /* Label for the procedure entry. */
2152 char *entry_label = (char *) alloca (strlen (alpha_function_name) + 6);
2155 sa_size = alpha_sa_size ();
2157 = ALPHA_ROUND (sa_size
2158 + (is_stack_procedure ? 8 : 0)
2159 + size + current_function_pretend_args_size);
2161 /* Issue function start and label. */
2162 fprintf (file, "\t.ent ");
2163 assemble_name (file, alpha_function_name);
2164 fprintf (file, "\n");
2165 sprintf (entry_label, "$%s..en", alpha_function_name);
2166 ASM_OUTPUT_LABEL (file, entry_label);
2167 inside_function = TRUE;
2169 fprintf (file, "\t.base $%d\n", base_regno);
2171 /* Calculate register masks for clobbered registers. */
2173 if (is_stack_procedure)
2174 alpha_sa_mask (&imask, &fmask);
2176 /* Adjust the stack by the frame size. If the frame size is > 4096
2177 bytes, we need to be sure we probe somewhere in the first and last
2178 4096 bytes (we can probably get away without the latter test) and
2179 every 8192 bytes in between. If the frame size is > 32768, we
2180 do this in a loop. Otherwise, we generate the explicit probe
2183 Note that we are only allowed to adjust sp once in the prologue. */
2185 if (frame_size < 32768)
2187 if (frame_size > 4096)
2191 fprintf (file, "\tstq $31,-%d($30)\n", probed);
2193 while (probed + 8192 < frame_size)
2194 fprintf (file, "\tstq $31,-%d($30)\n", probed += 8192);
2196 /* We only have to do this probe if we aren't saving registers. */
2197 if (sa_size == 0 && probed + 4096 < frame_size)
2198 fprintf (file, "\tstq $31,-%d($30)\n", frame_size);
2201 if (frame_size != 0)
2202 fprintf (file, "\tlda $30,-%d($30)\n", frame_size);
2206 /* Here we generate code to set R4 to SP + 4096 and set R23 to the
2207 number of 8192 byte blocks to probe. We then probe each block
2208 in the loop and then set SP to the proper location. If the
2209 amount remaining is > 4096, we have to do one more probe if we
2210 are not saving any registers. */
2212 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
2213 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
2215 add_long_const (file, blocks, 31, 23, 23);
2217 fprintf (file, "\tlda $22,4096($30)\n");
2220 assemble_name (file, alpha_function_name);
2221 fprintf (file, "..sc:\n");
2223 fprintf (file, "\tstq $31,-8192($22)\n");
2224 fprintf (file, "\tsubq $23,1,$23\n");
2225 fprintf (file, "\tlda $22,-8192($22)\n");
2227 fprintf (file, "\tbne $23,$");
2228 assemble_name (file, alpha_function_name);
2229 fprintf (file, "..sc\n");
2231 if (leftover > 4096 && sa_size == 0)
2232 fprintf (file, "\tstq $31,-%d($22)\n", leftover);
2234 fprintf (file, "\tlda $30,-%d($22)\n", leftover);
2237 if (is_stack_procedure)
2239 int reg_offset = rsa_offset;
2241 /* Store R26 (RA) first. */
2242 fprintf (file, "\tstq $26,%d($30)\n", reg_offset);
2245 /* Store integer regs. according to mask. */
2246 for (i = 0; i < 32; i++)
2247 if (imask & (1L<<i))
2249 fprintf (file, "\tstq $%d,%d($30)\n", i, reg_offset);
2253 /* Print the register mask and do floating-point saves. */
2256 fprintf (file, "\t.mask 0x%x,0\n", imask);
2258 for (i = 0; i < 32; i++)
2260 if (fmask & (1L << i))
2262 fprintf (file, "\tstt $f%d,%d($30)\n", i, reg_offset);
2267 /* Print the floating-point mask, if we've saved any fp register. */
2269 fprintf (file, "\t.fmask 0x%x,0\n", fmask);
2271 fprintf (file, "\tstq $27,0($30)\n");
2275 fprintf (file, "\t.fp_save $%d\n", save_fp_regno);
2276 fprintf (file, "\tbis $%d,$%d,$%d\n", HARD_FRAME_POINTER_REGNUM,
2277 HARD_FRAME_POINTER_REGNUM, save_fp_regno);
2280 if (base_regno != REG_PV)
2281 fprintf (file, "\tbis $%d,$%d,$%d\n", REG_PV, REG_PV, base_regno);
2283 if (unwind_regno == HARD_FRAME_POINTER_REGNUM)
2284 fprintf (file, "\tbis $%d,$%d,$%d\n", STACK_POINTER_REGNUM,
2285 STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM);
2287 /* Describe our frame. */
2288 fprintf (file, "\t.frame $%d,%d,$26,%d\n",
2289 unwind_regno, frame_size, rsa_offset);
2291 /* If we have to allocate space for outgoing args, do it now. */
2292 if (current_function_outgoing_args_size != 0)
2293 fprintf (file, "\tlda $%d,%d($%d)\n", STACK_POINTER_REGNUM,
2294 - ALPHA_ROUND (current_function_outgoing_args_size),
2295 HARD_FRAME_POINTER_REGNUM);
2297 fprintf (file, "\t.prologue\n");
2300 fprintf (file, "\t.align 3\n");
2301 ASM_OUTPUT_LABEL (file, alpha_function_name);
2302 fprintf (file, "\t.pdesc $");
2303 assemble_name (file, alpha_function_name);
2304 fprintf (file, "..en,%s\n", is_stack_procedure ? "stack" : "reg");
2305 alpha_need_linkage (alpha_function_name, 1);
2311 /* Write function epilogue. */
2314 output_epilog (file, size)
2318 unsigned long imask = 0;
2319 unsigned long fmask = 0;
2320 /* Stack space needed for pushing registers clobbered by us. */
2321 HOST_WIDE_INT sa_size = alpha_sa_size ();
2322 /* Complete stack size needed. */
2323 HOST_WIDE_INT frame_size
2324 = ALPHA_ROUND (sa_size
2325 + (is_stack_procedure ? 8 : 0)
2326 + size + current_function_pretend_args_size);
2328 rtx insn = get_last_insn ();
2330 /* If the last insn was a BARRIER, we don't have to write anything except
2331 the .end pseudo-op. */
2333 if (GET_CODE (insn) == NOTE)
2334 insn = prev_nonnote_insn (insn);
2336 if (insn == 0 || GET_CODE (insn) != BARRIER)
2338 /* Restore clobbered registers, load FP last. */
2340 if (is_stack_procedure)
2346 if (unwind_regno == HARD_FRAME_POINTER_REGNUM)
2347 fprintf (file, "\tbis $%d,$%d,$%d\n", HARD_FRAME_POINTER_REGNUM,
2348 HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM);
2350 alpha_sa_mask (&imask, &fmask);
2352 /* Start reloading registers after RA. */
2353 reg_offset = rsa_offset + 8;
2355 for (i = 0; i < 32; i++)
2356 if (imask & (1L<<i))
2358 if (i == HARD_FRAME_POINTER_REGNUM)
2359 fp_offset = reg_offset;
2361 fprintf (file, "\tldq $%d,%d($30)\n",
2366 for (i = 0; i < 32; i++)
2367 if (fmask & (1L << i))
2369 fprintf (file, "\tldt $f%d,%d($30)\n", i, reg_offset);
2373 /* Restore R26 (RA). */
2374 fprintf (file, "\tldq $26,%d($30)\n", rsa_offset);
2376 /* Restore R29 (FP). */
2377 fprintf (file, "\tldq $29,%d($30)\n", fp_offset);
2380 fprintf (file, "\tbis $%d,$%d,$%d\n", save_fp_regno, save_fp_regno,
2381 HARD_FRAME_POINTER_REGNUM);
2383 if (frame_size != 0)
2385 if (frame_size < 32768)
2386 fprintf (file, "\tlda $30,%d($30)\n", frame_size);
2389 long high = frame_size >> 16;
2390 long low = frame_size & 0xffff;
2394 low = -32768 + (low & 0x7fff);
2396 fprintf (file, "\tldah $2,%ld($31)\n", high);
2397 fprintf (file, "\tlda $2,%ld($2)\n", low);
2398 fprintf (file, "\taddq $30,$2,$30\n");
2402 /* Finally return to the caller. */
2403 fprintf (file, "\tret $31,($26),1\n");
2406 /* End the function. */
2407 fprintf (file, "\t.end ");
2408 assemble_name (file, alpha_function_name);
2409 fprintf (file, "\n");
2410 inside_function = FALSE;
2412 /* Show that we know this function if it is called again. */
2413 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
2416 #else /* !OPEN_VMS */
2419 alpha_does_function_need_gp ()
2423 /* We never need a GP for Windows/NT. */
2424 if (TARGET_WINDOWS_NT)
2427 #ifdef TARGET_PROFILING_NEEDS_GP
2432 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
2433 Even if we are a static function, we still need to do this in case
2434 our address is taken and passed to something like qsort. */
2436 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2437 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2438 && GET_CODE (PATTERN (insn)) != USE
2439 && GET_CODE (PATTERN (insn)) != CLOBBER)
2441 enum attr_type type = get_attr_type (insn);
2442 if (type == TYPE_LDSYM || type == TYPE_JSR)
2450 vms_valid_decl_attribute_p (decl, attributes, identifier, args)
2456 if (is_attribute_p ("overlaid", identifier))
2457 return (args == NULL_TREE);
2462 output_prolog (file, size)
2466 HOST_WIDE_INT out_args_size
2467 = ALPHA_ROUND (current_function_outgoing_args_size);
2468 HOST_WIDE_INT sa_size = alpha_sa_size ();
2469 HOST_WIDE_INT frame_size
2470 = (out_args_size + sa_size
2471 + ALPHA_ROUND (size + current_function_pretend_args_size));
2472 HOST_WIDE_INT reg_offset = out_args_size;
2473 HOST_WIDE_INT start_reg_offset = reg_offset;
2474 HOST_WIDE_INT actual_start_reg_offset = start_reg_offset;
2475 int int_reg_save_area_size = 0;
2476 unsigned reg_mask = 0;
2479 /* Ecoff can handle multiple .file directives, so put out file and lineno.
2480 We have to do that before the .ent directive as we cannot switch
2481 files within procedures with native ecoff because line numbers are
2482 linked to procedure descriptors.
2483 Outputting the lineno helps debugging of one line functions as they
2484 would otherwise get no line number at all. Please note that we would
2485 like to put out last_linenum from final.c, but it is not accessible. */
2487 if (write_symbols == SDB_DEBUG)
2489 ASM_OUTPUT_SOURCE_FILENAME (file,
2490 DECL_SOURCE_FILE (current_function_decl));
2491 if (debug_info_level != DINFO_LEVEL_TERSE)
2492 ASM_OUTPUT_SOURCE_LINE (file,
2493 DECL_SOURCE_LINE (current_function_decl));
2496 /* The assembly language programmer's guide states that the second argument
2497 to the .ent directive, the lex_level, is ignored by the assembler,
2498 so we might as well omit it. */
2500 if (!flag_inhibit_size_directive)
2502 fprintf (file, "\t.ent ");
2503 assemble_name (file, alpha_function_name);
2504 fprintf (file, "\n");
2506 ASM_OUTPUT_LABEL (file, alpha_function_name);
2507 inside_function = TRUE;
2509 if (TARGET_IEEE_CONFORMANT && !flag_inhibit_size_directive)
2510 /* Set flags in procedure descriptor to request IEEE-conformant
2511 math-library routines. The value we set it to is PDSC_EXC_IEEE
2512 (/usr/include/pdsc.h). */
2513 fprintf (file, "\t.eflag 48\n");
2515 /* Set up offsets to alpha virtual arg/local debugging pointer. */
2517 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
2518 alpha_arg_offset = -frame_size + 48;
2520 alpha_function_needs_gp = alpha_does_function_need_gp ();
2522 if (TARGET_WINDOWS_NT == 0)
2524 if (alpha_function_needs_gp)
2525 fprintf (file, "\tldgp $29,0($27)\n");
2527 /* Put a label after the GP load so we can enter the function at it. */
2529 assemble_name (file, alpha_function_name);
2530 fprintf (file, "..ng:\n");
2533 /* Adjust the stack by the frame size. If the frame size is > 4096
2534 bytes, we need to be sure we probe somewhere in the first and last
2535 4096 bytes (we can probably get away without the latter test) and
2536 every 8192 bytes in between. If the frame size is > 32768, we
2537 do this in a loop. Otherwise, we generate the explicit probe
2540 Note that we are only allowed to adjust sp once in the prologue. */
2542 if (frame_size < 32768)
2544 if (frame_size > 4096)
2548 fprintf (file, "\tstq $31,-%d($30)\n", probed);
2550 while (probed + 8192 < frame_size)
2551 fprintf (file, "\tstq $31,-%d($30)\n", probed += 8192);
2553 /* We only have to do this probe if we aren't saving registers. */
2554 if (sa_size == 0 && probed + 4096 < frame_size)
2555 fprintf (file, "\tstq $31,-%d($30)\n", frame_size);
2558 if (frame_size != 0)
2559 fprintf (file, "\tlda $30,-%d($30)\n", frame_size);
2563 /* Here we generate code to set R4 to SP + 4096 and set R5 to the
2564 number of 8192 byte blocks to probe. We then probe each block
2565 in the loop and then set SP to the proper location. If the
2566 amount remaining is > 4096, we have to do one more probe if we
2567 are not saving any registers. */
2569 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
2570 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
2572 add_long_const (file, blocks, 31, 5, 5);
2574 fprintf (file, "\tlda $4,4096($30)\n");
2577 assemble_name (file, alpha_function_name);
2578 fprintf (file, "..sc:\n");
2580 fprintf (file, "\tstq $31,-8192($4)\n");
2581 fprintf (file, "\tsubq $5,1,$5\n");
2582 fprintf (file, "\tlda $4,-8192($4)\n");
2584 fprintf (file, "\tbne $5,$");
2585 assemble_name (file, alpha_function_name);
2586 fprintf (file, "..sc\n");
2588 if (leftover > 4096 && sa_size == 0)
2589 fprintf (file, "\tstq $31,-%d($4)\n", leftover);
2591 fprintf (file, "\tlda $30,-%d($4)\n", leftover);
2594 /* Describe our frame. */
2595 if (!flag_inhibit_size_directive)
2597 fprintf (file, "\t.frame $%d,%d,$26,%d\n",
2598 (frame_pointer_needed
2599 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
2600 frame_size, current_function_pretend_args_size);
2603 /* Cope with very large offsets to the register save area. */
2605 if (reg_offset + sa_size > 0x8000)
2607 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
2608 if (low + sa_size <= 0x8000)
2610 add_long_const (file, reg_offset - low, 30, 24, 24);
2615 add_long_const (file, reg_offset, 30, 24, 24);
2621 /* Save register RA if any other register needs to be saved. */
2624 reg_mask |= 1 << REG_RA;
2625 fprintf (file, "\tstq $26,%d($%d)\n", reg_offset, sa_reg);
2627 int_reg_save_area_size += 8;
2630 /* Now save any other used integer registers required to be saved. */
2631 for (i = 0; i < 32; i++)
2632 if (! fixed_regs[i] && ! call_used_regs[i]
2633 && regs_ever_live[i] && i != REG_RA)
2636 fprintf (file, "\tstq $%d,%d($%d)\n", i, reg_offset, sa_reg);
2638 int_reg_save_area_size += 8;
2641 /* Print the register mask and do floating-point saves. */
2642 if (reg_mask && !flag_inhibit_size_directive)
2643 fprintf (file, "\t.mask 0x%x,%d\n", reg_mask,
2644 actual_start_reg_offset - frame_size);
2646 start_reg_offset = reg_offset;
2649 for (i = 0; i < 32; i++)
2650 if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
2651 && regs_ever_live[i + 32])
2654 fprintf (file, "\tstt $f%d,%d($%d)\n", i, reg_offset, sa_reg);
2658 /* Print the floating-point mask, if we've saved any fp register. */
2659 if (reg_mask && !flag_inhibit_size_directive)
2660 fprintf (file, "\t.fmask 0x%x,%d\n", reg_mask,
2661 actual_start_reg_offset - frame_size + int_reg_save_area_size);
2663 /* If we need a frame pointer, set it from the stack pointer. Note that
2664 this must always be the last instruction in the prologue. */
2665 if (frame_pointer_needed)
2666 fprintf (file, "\tbis $30,$30,$15\n");
2668 /* End the prologue and say if we used gp. */
2669 if (!flag_inhibit_size_directive)
2670 fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp);
2673 /* Write function epilogue. */
2676 output_epilog (file, size)
2680 rtx insn = get_last_insn ();
2681 HOST_WIDE_INT out_args_size
2682 = ALPHA_ROUND (current_function_outgoing_args_size);
2683 HOST_WIDE_INT sa_size = alpha_sa_size ();
2684 HOST_WIDE_INT frame_size
2685 = (out_args_size + sa_size
2686 + ALPHA_ROUND (size + current_function_pretend_args_size));
2687 HOST_WIDE_INT reg_offset = out_args_size;
2688 HOST_WIDE_INT frame_size_from_reg_save = frame_size - reg_offset;
2690 = frame_pointer_needed && regs_ever_live[HARD_FRAME_POINTER_REGNUM];
2693 /* If the last insn was a BARRIER, we don't have to write anything except
2694 the .end pseudo-op. */
2695 if (GET_CODE (insn) == NOTE)
2696 insn = prev_nonnote_insn (insn);
2697 if (insn == 0 || GET_CODE (insn) != BARRIER)
2702 /* If we have a frame pointer, restore SP from it. */
2703 if (frame_pointer_needed)
2704 fprintf (file, "\tbis $15,$15,$30\n");
2706 /* Cope with large offsets to the register save area. */
2708 if (reg_offset + sa_size > 0x8000)
2710 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
2711 if (low + sa_size <= 0x8000)
2713 add_long_const (file, reg_offset - low, 30, 24, 24);
2718 add_long_const (file, reg_offset, 30, 24, 24);
2724 /* Restore all the registers, starting with the return address
2728 fprintf (file, "\tldq $26,%d($%d)\n", reg_offset, sa_reg);
2732 /* Now restore any other used integer registers that that we saved,
2733 except for FP if it is being used as FP, since it must be
2736 for (i = 0; i < 32; i++)
2737 if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i]
2740 if (i == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
2741 fp_offset = reg_offset;
2743 fprintf (file, "\tldq $%d,%d($%d)\n", i, reg_offset, sa_reg);
2747 for (i = 0; i < 32; i++)
2748 if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
2749 && regs_ever_live[i + 32])
2751 fprintf (file, "\tldt $f%d,%d($%d)\n", i, reg_offset, sa_reg);
2755 /* If the stack size is large and we have a frame pointer, compute the
2756 size of the stack into a register because the old FP restore, stack
2757 pointer adjust, and return are required to be consecutive
2759 if (frame_size > 32767 && restore_fp)
2760 add_long_const (file, frame_size, 31, 1, 1);
2762 /* If we needed a frame pointer and we have to restore it, do it
2763 now. This must be done in one instruction immediately
2764 before the SP update. */
2765 if (restore_fp && fp_offset)
2766 fprintf (file, "\tldq $15,%d($%d)\n", fp_offset, sa_reg);
2768 /* Now update the stack pointer, if needed. Only one instruction must
2769 modify the stack pointer. It must be the last instruction in the
2770 sequence and must be an ADDQ or LDA instruction. If the frame
2771 pointer was loaded above, we may only put one instruction here. */
2773 if (frame_size > 32768 && restore_fp)
2774 fprintf (file, "\taddq $1,$30,$30\n");
2776 add_long_const (file, frame_size, 30, 30, 1);
2778 /* Finally return to the caller. */
2779 fprintf (file, "\tret $31,($26),1\n");
2782 /* End the function. */
2783 if (!flag_inhibit_size_directive)
2785 fprintf (file, "\t.end ");
2786 assemble_name (file, alpha_function_name);
2787 fprintf (file, "\n");
2789 inside_function = FALSE;
2791 /* Show that we know this function if it is called again. */
2792 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
2794 #endif /* !OPEN_VMS */
2796 /* Debugging support. */
2800 /* Count the number of sdb related labels are generated (to find block
2801 start and end boundaries). */
2803 int sdb_label_count = 0;
2805 /* Next label # for each statement. */
2807 static int sym_lineno = 0;
2809 /* Count the number of .file directives, so that .loc is up to date. */
2811 static int num_source_filenames = 0;
2813 /* Name of the file containing the current function. */
2815 static char *current_function_file = "";
2817 /* Offsets to alpha virtual arg/local debugging pointers. */
2819 long alpha_arg_offset;
2820 long alpha_auto_offset;
2822 /* Emit a new filename to a stream. */
2825 alpha_output_filename (stream, name)
2829 static int first_time = TRUE;
2830 char ltext_label_name[100];
2835 ++num_source_filenames;
2836 current_function_file = name;
2837 fprintf (stream, "\t.file\t%d ", num_source_filenames);
2838 output_quoted_string (stream, name);
2839 fprintf (stream, "\n");
2840 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
2841 fprintf (stream, "\t#@stabs\n");
2844 else if (write_symbols == DBX_DEBUG)
2846 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
2847 fprintf (stream, "%s ", ASM_STABS_OP);
2848 output_quoted_string (stream, name);
2849 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
2852 else if (name != current_function_file
2853 && strcmp (name, current_function_file) != 0)
2855 if (inside_function && ! TARGET_GAS)
2856 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
2859 ++num_source_filenames;
2860 current_function_file = name;
2861 fprintf (stream, "\t.file\t%d ", num_source_filenames);
2864 output_quoted_string (stream, name);
2865 fprintf (stream, "\n");
2869 /* Emit a linenumber to a stream. */
2872 alpha_output_lineno (stream, line)
2876 if (write_symbols == DBX_DEBUG)
2878 /* mips-tfile doesn't understand .stabd directives. */
2880 fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n",
2881 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
2884 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
2887 /* Structure to show the current status of registers and memory. */
2889 struct shadow_summary
2892 unsigned long i : 31; /* Mask of int regs */
2893 unsigned long fp : 31; /* Mask of fp regs */
2894 unsigned long mem : 1; /* mem == imem | fpmem */
2898 /* Summary the effects of expression X on the machine. Update SUM, a pointer
2899 to the summary structure. SET is nonzero if the insn is setting the
2900 object, otherwise zero. */
2903 summarize_insn (x, sum, set)
2905 struct shadow_summary *sum;
2914 switch (GET_CODE (x))
2916 /* ??? Note that this case would be incorrect if the Alpha had a
2917 ZERO_EXTRACT in SET_DEST. */
2919 summarize_insn (SET_SRC (x), sum, 0);
2920 summarize_insn (SET_DEST (x), sum, 1);
2924 summarize_insn (XEXP (x, 0), sum, 1);
2928 summarize_insn (XEXP (x, 0), sum, 0);
2932 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
2933 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
2937 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2938 summarize_insn (XVECEXP (x, 0, i), sum, 0);
2947 int regno = REGNO (x);
2948 unsigned long mask = 1UL << (regno % 32);
2950 if (regno == 31 || regno == 63)
2956 sum->defd.i |= mask;
2958 sum->defd.fp |= mask;
2963 sum->used.i |= mask;
2965 sum->used.fp |= mask;
2976 /* Find the regs used in memory address computation: */
2977 summarize_insn (XEXP (x, 0), sum, 0);
2980 case CONST_INT: case CONST_DOUBLE:
2981 case SYMBOL_REF: case LABEL_REF: case CONST:
2984 /* Handle common unary and binary ops for efficiency. */
2985 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
2986 case MOD: case UDIV: case UMOD: case AND: case IOR:
2987 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
2988 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
2989 case NE: case EQ: case GE: case GT: case LE:
2990 case LT: case GEU: case GTU: case LEU: case LTU:
2991 summarize_insn (XEXP (x, 0), sum, 0);
2992 summarize_insn (XEXP (x, 1), sum, 0);
2995 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
2996 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
2997 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
2998 case SQRT: case FFS:
2999 summarize_insn (XEXP (x, 0), sum, 0);
3003 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
3004 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3005 switch (format_ptr[i])
3008 summarize_insn (XEXP (x, i), sum, 0);
3012 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3013 summarize_insn (XVECEXP (x, i, j), sum, 0);
3022 /* Ensure a sufficient number of `trapb' insns are in the code when the user
3023 requests code with a trap precision of functions or instructions.
3025 In naive mode, when the user requests a trap-precision of "instruction", a
3026 trapb is needed after every instruction that may generate a trap (and after
3027 jsr/bsr instructions, because called functions may import a trap from the
3028 caller). This ensures that the code is resumption safe but it is also slow.
3030 When optimizations are turned on, we delay issuing a trapb as long as
3031 possible. In this context, a trap shadow is the sequence of instructions
3032 that starts with a (potentially) trap generating instruction and extends to
3033 the next trapb or call_pal instruction (but GCC never generates call_pal by
3034 itself). We can delay (and therefore sometimes omit) a trapb subject to the
3035 following conditions:
3037 (a) On entry to the trap shadow, if any Alpha register or memory location
3038 contains a value that is used as an operand value by some instruction in
3039 the trap shadow (live on entry), then no instruction in the trap shadow
3040 may modify the register or memory location.
3042 (b) Within the trap shadow, the computation of the base register for a
3043 memory load or store instruction may not involve using the result
3044 of an instruction that might generate an UNPREDICTABLE result.
3046 (c) Within the trap shadow, no register may be used more than once as a
3047 destination register. (This is to make life easier for the trap-handler.)
3049 (d) The trap shadow may not include any branch instructions. */
3052 alpha_handle_trap_shadows (insns)
3055 struct shadow_summary shadow;
3056 int trap_pending, exception_nesting;
3059 if (alpha_tp == ALPHA_TP_PROG && !flag_exceptions)
3063 exception_nesting = 0;
3066 shadow.used.mem = 0;
3067 shadow.defd = shadow.used;
3069 for (i = insns; i ; i = NEXT_INSN (i))
3071 if (GET_CODE (i) == NOTE)
3073 switch (NOTE_LINE_NUMBER (i))
3075 case NOTE_INSN_EH_REGION_BEG:
3076 exception_nesting++;
3081 case NOTE_INSN_EH_REGION_END:
3082 exception_nesting--;
3087 case NOTE_INSN_EPILOGUE_BEG:
3088 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
3093 else if (trap_pending)
3095 if (alpha_tp == ALPHA_TP_FUNC)
3097 if (GET_CODE (i) == JUMP_INSN
3098 && GET_CODE (PATTERN (i)) == RETURN)
3101 else if (alpha_tp == ALPHA_TP_INSN)
3105 struct shadow_summary sum;
3110 sum.defd = sum.used;
3112 switch (GET_CODE (i))
3115 /* Annoyingly, get_attr_trap will abort on USE. */
3116 if (GET_CODE (PATTERN (i)) == USE)
3119 summarize_insn (PATTERN (i), &sum, 0);
3121 if ((sum.defd.i & shadow.defd.i)
3122 || (sum.defd.fp & shadow.defd.fp))
3124 /* (c) would be violated */
3128 /* Combine shadow with summary of current insn: */
3129 shadow.used.i |= sum.used.i;
3130 shadow.used.fp |= sum.used.fp;
3131 shadow.used.mem |= sum.used.mem;
3132 shadow.defd.i |= sum.defd.i;
3133 shadow.defd.fp |= sum.defd.fp;
3134 shadow.defd.mem |= sum.defd.mem;
3136 if ((sum.defd.i & shadow.used.i)
3137 || (sum.defd.fp & shadow.used.fp)
3138 || (sum.defd.mem & shadow.used.mem))
3140 /* (a) would be violated (also takes care of (b)) */
3141 if (get_attr_trap (i) == TRAP_YES
3142 && ((sum.defd.i & sum.used.i)
3143 || (sum.defd.fp & sum.used.fp)))
3162 emit_insn_before (gen_trapb (), i);
3166 shadow.used.mem = 0;
3167 shadow.defd = shadow.used;
3172 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
3173 && GET_CODE (i) == INSN
3174 && GET_CODE (PATTERN (i)) != USE
3175 && GET_CODE (PATTERN (i)) != CLOBBER
3176 && get_attr_trap (i) == TRAP_YES)
3178 if (optimize && !trap_pending)
3179 summarize_insn (PATTERN (i), &shadow, 0);
3185 /* Machine dependant reorg pass. */
3191 alpha_handle_trap_shadows (insns);
3195 /* Check a floating-point value for validity for a particular machine mode. */
3197 static char *float_strings[] =
3199 /* These are for FLOAT_VAX. */
3200 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
3201 "-1.70141173319264430e+38",
3202 "2.93873587705571877e-39", /* 2^-128 */
3203 "-2.93873587705571877e-39",
3204 /* These are for the default broken IEEE mode, which traps
3205 on infinity or denormal numbers. */
3206 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
3207 "-3.402823466385288598117e+38",
3208 "1.1754943508222875079687e-38", /* 2^-126 */
3209 "-1.1754943508222875079687e-38",
3212 static REAL_VALUE_TYPE float_values[8];
3213 static int inited_float_values = 0;
3216 check_float_value (mode, d, overflow)
3217 enum machine_mode mode;
3222 if (TARGET_IEEE || TARGET_IEEE_CONFORMANT || TARGET_IEEE_WITH_INEXACT)
3225 if (inited_float_values == 0)
3228 for (i = 0; i < 8; i++)
3229 float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
3231 inited_float_values = 1;
3237 REAL_VALUE_TYPE *fvptr;
3239 if (TARGET_FLOAT_VAX)
3240 fvptr = &float_values[0];
3242 fvptr = &float_values[4];
3244 bcopy ((char *) d, (char *) &r, sizeof (REAL_VALUE_TYPE));
3245 if (REAL_VALUES_LESS (fvptr[0], r))
3247 bcopy ((char *) &fvptr[0], (char *) d,
3248 sizeof (REAL_VALUE_TYPE));
3251 else if (REAL_VALUES_LESS (r, fvptr[1]))
3253 bcopy ((char *) &fvptr[1], (char *) d,
3254 sizeof (REAL_VALUE_TYPE));
3257 else if (REAL_VALUES_LESS (dconst0, r)
3258 && REAL_VALUES_LESS (r, fvptr[2]))
3260 bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
3263 else if (REAL_VALUES_LESS (r, dconst0)
3264 && REAL_VALUES_LESS (fvptr[3], r))
3266 bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
3276 /* Return the VMS argument type corresponding to MODE. */
3279 alpha_arg_type (mode)
3280 enum machine_mode mode;
3285 return TARGET_FLOAT_VAX ? FF : FS;
3287 return TARGET_FLOAT_VAX ? FD : FT;
3293 /* Return an rtx for an integer representing the VMS Argument Information
3297 alpha_arg_info_reg_val (cum)
3298 CUMULATIVE_ARGS cum;
3300 unsigned HOST_WIDE_INT regval = cum.num_args;
3303 for (i = 0; i < 6; i++)
3304 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
3306 return GEN_INT (regval);
3309 /* Structure to collect function names for final output
3312 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
3315 struct alpha_links {
3316 struct alpha_links *next;
3318 enum links_kind kind;
3321 static struct alpha_links *alpha_links_base = 0;
3323 /* Make (or fake) .linkage entry for function call.
3325 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
3328 alpha_need_linkage (name, is_local)
3333 struct alpha_links *lptr, *nptr;
3338 /* Is this name already defined ? */
3340 for (lptr = alpha_links_base; lptr; lptr = lptr->next)
3341 if (strcmp (lptr->name, name) == 0)
3345 /* Defined here but external assumed. */
3346 if (lptr->kind == KIND_EXTERN)
3347 lptr->kind = KIND_LOCAL;
3351 /* Used here but unused assumed. */
3352 if (lptr->kind == KIND_UNUSED)
3353 lptr->kind = KIND_LOCAL;
3358 nptr = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
3359 nptr->next = alpha_links_base;
3360 nptr->name = xstrdup (name);
3362 /* Assume external if no definition. */
3363 nptr->kind = (is_local ? KIND_UNUSED : KIND_EXTERN);
3365 /* Ensure we have an IDENTIFIER so assemble_name can mark is used. */
3366 get_identifier (name);
3368 alpha_links_base = nptr;
3375 alpha_write_linkage (stream)
3378 struct alpha_links *lptr, *nptr;
3380 readonly_section ();
3382 fprintf (stream, "\t.align 3\n");
3384 for (lptr = alpha_links_base; lptr; lptr = nptr)
3388 if (lptr->kind == KIND_UNUSED
3389 || ! TREE_SYMBOL_REFERENCED (get_identifier (lptr->name)))
3392 fprintf (stream, "$%s..lk:\n", lptr->name);
3393 if (lptr->kind == KIND_LOCAL)
3395 /* Local and used, build linkage pair. */
3396 fprintf (stream, "\t.quad $%s..en\n", lptr->name);
3397 fprintf (stream, "\t.quad %s\n", lptr->name);
3400 /* External and used, request linkage pair. */
3401 fprintf (stream, "\t.linkage %s\n", lptr->name);
3408 alpha_need_linkage (name, is_local)
3414 #endif /* OPEN_VMS */