1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
44 extern char *version_string;
45 extern int rtx_equal_function_value_matters;
47 /* Specify which cpu to schedule for. */
49 enum processor_type alpha_cpu;
51 /* Specify how accurate floating-point traps need to be. */
53 enum alpha_trap_precision alpha_tp;
55 /* Specify the floating-point rounding mode. */
57 enum alpha_fp_rounding_mode alpha_fprm;
59 /* Specify which things cause traps. */
61 enum alpha_fp_trap_mode alpha_fptm;
63 /* Strings decoded into the above options. */
65 char *alpha_cpu_string; /* -mcpu=ev[4|5] */
66 char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
67 char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
68 char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
70 /* Save information from a "cmpxx" operation until the branch or scc is
73 rtx alpha_compare_op0, alpha_compare_op1;
74 int alpha_compare_fp_p;
76 /* Save the name of the current function as used by the assembler. This
77 is used by the epilogue. */
79 char *alpha_function_name;
81 /* Non-zero if inside of a function, because the Alpha asm can't
82 handle .files inside of functions. */
84 static int inside_function = FALSE;
86 /* Nonzero if the current function needs gp. */
88 int alpha_function_needs_gp;
90 /* If non-null, this rtx holds the return address for the function. */
92 static rtx alpha_return_addr_rtx;
94 /* Declarations of static functions. */
95 static void alpha_set_memflags_1 PROTO((rtx, int, int, int));
96 static rtx alpha_emit_set_const_1 PROTO((rtx, enum machine_mode,
98 static void add_long_const PROTO((FILE *, HOST_WIDE_INT, int, int, int));
100 /* Compute the size of the save area in the stack. */
101 static void alpha_sa_mask PROTO((unsigned long *imaskP,
102 unsigned long *fmaskP));
103 /* Get the number of args of a function in one of two ways. */
105 #define NUM_ARGS current_function_args_info.num_args
107 #define NUM_ARGS current_function_args_info
117 /* Parse target option strings. */
122 /* 971208 -- EV6 scheduling parameters are still secret, so don't even
123 pretend and just schedule for an EV5 for now. -- r~ */
125 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV5
126 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
128 if (alpha_cpu_string)
130 if (! strcmp (alpha_cpu_string, "ev4")
131 || ! strcmp (alpha_cpu_string, "21064"))
133 alpha_cpu = PROCESSOR_EV4;
134 target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
136 else if (! strcmp (alpha_cpu_string, "ev5")
137 || ! strcmp (alpha_cpu_string, "21164"))
139 alpha_cpu = PROCESSOR_EV5;
140 target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
142 else if (! strcmp (alpha_cpu_string, "ev56")
143 || ! strcmp (alpha_cpu_string, "21164a"))
145 alpha_cpu = PROCESSOR_EV5;
146 target_flags |= MASK_BWX;
147 target_flags &= ~ (MASK_CIX | MASK_MAX);
149 else if (! strcmp (alpha_cpu_string, "pca56")
150 || ! strcmp (alpha_cpu_string, "21164PC")
151 || ! strcmp (alpha_cpu_string, "21164pc"))
153 alpha_cpu = PROCESSOR_EV5;
154 target_flags |= MASK_BWX | MASK_MAX;
155 target_flags &= ~ MASK_CIX;
157 else if (! strcmp (alpha_cpu_string, "ev6")
158 || ! strcmp (alpha_cpu_string, "21264"))
160 alpha_cpu = PROCESSOR_EV5;
161 target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
164 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
167 alpha_tp = ALPHA_TP_PROG;
168 alpha_fprm = ALPHA_FPRM_NORM;
169 alpha_fptm = ALPHA_FPTM_N;
173 alpha_tp = ALPHA_TP_INSN;
174 alpha_fptm = ALPHA_FPTM_SU;
177 if (TARGET_IEEE_WITH_INEXACT)
179 alpha_tp = ALPHA_TP_INSN;
180 alpha_fptm = ALPHA_FPTM_SUI;
185 if (! strcmp (alpha_tp_string, "p"))
186 alpha_tp = ALPHA_TP_PROG;
187 else if (! strcmp (alpha_tp_string, "f"))
188 alpha_tp = ALPHA_TP_FUNC;
189 else if (! strcmp (alpha_tp_string, "i"))
190 alpha_tp = ALPHA_TP_INSN;
192 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
195 if (alpha_fprm_string)
197 if (! strcmp (alpha_fprm_string, "n"))
198 alpha_fprm = ALPHA_FPRM_NORM;
199 else if (! strcmp (alpha_fprm_string, "m"))
200 alpha_fprm = ALPHA_FPRM_MINF;
201 else if (! strcmp (alpha_fprm_string, "c"))
202 alpha_fprm = ALPHA_FPRM_CHOP;
203 else if (! strcmp (alpha_fprm_string,"d"))
204 alpha_fprm = ALPHA_FPRM_DYN;
206 error ("bad value `%s' for -mfp-rounding-mode switch",
210 if (alpha_fptm_string)
212 if (strcmp (alpha_fptm_string, "n") == 0)
213 alpha_fptm = ALPHA_FPTM_N;
214 else if (strcmp (alpha_fptm_string, "u") == 0)
215 alpha_fptm = ALPHA_FPTM_U;
216 else if (strcmp (alpha_fptm_string, "su") == 0)
217 alpha_fptm = ALPHA_FPTM_SU;
218 else if (strcmp (alpha_fptm_string, "sui") == 0)
219 alpha_fptm = ALPHA_FPTM_SUI;
221 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
224 /* Do some sanity checks on the above option. */
226 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
227 && alpha_tp != ALPHA_TP_INSN)
229 warning ("fp software completion requires -mtrap-precision=i");
230 alpha_tp = ALPHA_TP_INSN;
233 if (TARGET_FLOAT_VAX)
235 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
237 warning ("rounding mode not supported for VAX floats");
238 alpha_fprm = ALPHA_FPRM_NORM;
240 if (alpha_fptm == ALPHA_FPTM_SUI)
242 warning ("trap mode not supported for VAX floats");
243 alpha_fptm = ALPHA_FPTM_SU;
248 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
256 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
258 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
264 /* Returns 1 if OP is either the constant zero or a register. If a
265 register, it must be in the proper mode unless MODE is VOIDmode. */
268 reg_or_0_operand (op, mode)
270 enum machine_mode mode;
272 return op == const0_rtx || register_operand (op, mode);
275 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
279 reg_or_6bit_operand (op, mode)
281 enum machine_mode mode;
283 return ((GET_CODE (op) == CONST_INT
284 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
285 || register_operand (op, mode));
289 /* Return 1 if OP is an 8-bit constant or any register. */
292 reg_or_8bit_operand (op, mode)
294 enum machine_mode mode;
296 return ((GET_CODE (op) == CONST_INT
297 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
298 || register_operand (op, mode));
301 /* Return 1 if OP is an 8-bit constant. */
304 cint8_operand (op, mode)
306 enum machine_mode mode;
308 return (GET_CODE (op) == CONST_INT
309 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100);
312 /* Return 1 if the operand is a valid second operand to an add insn. */
315 add_operand (op, mode)
317 enum machine_mode mode;
319 if (GET_CODE (op) == CONST_INT)
320 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
321 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')
322 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
324 return register_operand (op, mode);
327 /* Return 1 if the operand is a valid second operand to a sign-extending
331 sext_add_operand (op, mode)
333 enum machine_mode mode;
335 if (GET_CODE (op) == CONST_INT)
336 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255
337 || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255);
339 return register_operand (op, mode);
342 /* Return 1 if OP is the constant 4 or 8. */
345 const48_operand (op, mode)
347 enum machine_mode mode;
349 return (GET_CODE (op) == CONST_INT
350 && (INTVAL (op) == 4 || INTVAL (op) == 8));
353 /* Return 1 if OP is a valid first operand to an AND insn. */
356 and_operand (op, mode)
358 enum machine_mode mode;
360 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
361 return (zap_mask (CONST_DOUBLE_LOW (op))
362 && zap_mask (CONST_DOUBLE_HIGH (op)));
364 if (GET_CODE (op) == CONST_INT)
365 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
366 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
367 || zap_mask (INTVAL (op)));
369 return register_operand (op, mode);
372 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
375 or_operand (op, mode)
377 enum machine_mode mode;
379 if (GET_CODE (op) == CONST_INT)
380 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
381 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
383 return register_operand (op, mode);
386 /* Return 1 if OP is a constant that is the width, in bits, of an integral
387 mode smaller than DImode. */
390 mode_width_operand (op, mode)
392 enum machine_mode mode;
394 return (GET_CODE (op) == CONST_INT
395 && (INTVAL (op) == 8 || INTVAL (op) == 16 || INTVAL (op) == 32));
398 /* Return 1 if OP is a constant that is the width of an integral machine mode
399 smaller than an integer. */
402 mode_mask_operand (op, mode)
404 enum machine_mode mode;
406 #if HOST_BITS_PER_WIDE_INT == 32
407 if (GET_CODE (op) == CONST_DOUBLE)
408 return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == -1;
411 return (GET_CODE (op) == CONST_INT
412 && (INTVAL (op) == 0xff
413 || INTVAL (op) == 0xffff
414 #if HOST_BITS_PER_WIDE_INT == 64
415 || INTVAL (op) == 0xffffffff
420 /* Return 1 if OP is a multiple of 8 less than 64. */
423 mul8_operand (op, mode)
425 enum machine_mode mode;
427 return (GET_CODE (op) == CONST_INT
428 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
429 && (INTVAL (op) & 7) == 0);
432 /* Return 1 if OP is the constant zero in floating-point. */
435 fp0_operand (op, mode)
437 enum machine_mode mode;
439 return (GET_MODE (op) == mode
440 && GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode));
443 /* Return 1 if OP is the floating-point constant zero or a register. */
446 reg_or_fp0_operand (op, mode)
448 enum machine_mode mode;
450 return fp0_operand (op, mode) || register_operand (op, mode);
453 /* Return 1 if OP is a register or a constant integer. */
457 reg_or_cint_operand (op, mode)
459 enum machine_mode mode;
461 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
464 /* Return 1 if OP is something that can be reloaded into a register;
465 if it is a MEM, it need not be valid. */
468 some_operand (op, mode)
470 enum machine_mode mode;
472 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
475 switch (GET_CODE (op))
477 case REG: case MEM: case CONST_DOUBLE:
478 case CONST_INT: case LABEL_REF: case SYMBOL_REF: case CONST:
482 return some_operand (SUBREG_REG (op), VOIDmode);
488 /* Return 1 if OP is a valid operand for the source of a move insn. */
491 input_operand (op, mode)
493 enum machine_mode mode;
495 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
498 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
501 switch (GET_CODE (op))
506 /* This handles both the Windows/NT and OSF cases. */
507 return mode == ptr_mode || mode == DImode;
513 if (register_operand (op, mode))
515 /* ... fall through ... */
517 return ((TARGET_BWX || (mode != HImode && mode != QImode))
518 && general_operand (op, mode));
521 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
524 return mode == QImode || mode == HImode || add_operand (op, mode);
530 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
534 current_file_function_operand (op, mode)
536 enum machine_mode mode;
538 return (GET_CODE (op) == SYMBOL_REF
539 && ! profile_flag && ! profile_block_flag
540 && (SYMBOL_REF_FLAG (op)
541 || op == XEXP (DECL_RTL (current_function_decl), 0)));
544 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
547 call_operand (op, mode)
549 enum machine_mode mode;
554 return (GET_CODE (op) == SYMBOL_REF
555 || (GET_CODE (op) == REG
556 && (TARGET_OPEN_VMS || TARGET_WINDOWS_NT || REGNO (op) == 27)));
559 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
560 comparisons are valid in which insn. */
563 alpha_comparison_operator (op, mode)
565 enum machine_mode mode;
567 enum rtx_code code = GET_CODE (op);
569 if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
572 return (code == EQ || code == LE || code == LT
573 || (mode == DImode && (code == LEU || code == LTU)));
576 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
579 alpha_swapped_comparison_operator (op, mode)
581 enum machine_mode mode;
583 enum rtx_code code = GET_CODE (op);
585 if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
588 code = swap_condition (code);
589 return (code == EQ || code == LE || code == LT
590 || (mode == DImode && (code == LEU || code == LTU)));
593 /* Return 1 if OP is a signed comparison operation. */
596 signed_comparison_operator (op, mode)
598 enum machine_mode mode;
600 switch (GET_CODE (op))
602 case EQ: case NE: case LE: case LT: case GE: case GT:
609 /* Return 1 if this is a divide or modulus operator. */
612 divmod_operator (op, mode)
614 enum machine_mode mode;
616 switch (GET_CODE (op))
618 case DIV: case MOD: case UDIV: case UMOD:
625 /* Return 1 if this memory address is a known aligned register plus
626 a constant. It must be a valid address. This means that we can do
627 this as an aligned reference plus some offset.
629 Take into account what reload will do.
631 We could say that out-of-range stack slots are alignable, but that would
632 complicate get_aligned_mem and it isn't worth the trouble since few
633 functions have large stack space. */
636 aligned_memory_operand (op, mode)
638 enum machine_mode mode;
640 if (GET_CODE (op) == SUBREG)
642 if (GET_MODE (op) != mode)
644 op = SUBREG_REG (op);
645 mode = GET_MODE (op);
648 if (reload_in_progress && GET_CODE (op) == REG
649 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
650 op = reg_equiv_mem[REGNO (op)];
652 if (GET_CODE (op) != MEM || GET_MODE (op) != mode
653 || ! memory_address_p (mode, XEXP (op, 0)))
658 if (GET_CODE (op) == PLUS)
661 return (GET_CODE (op) == REG
662 && REGNO_POINTER_ALIGN (REGNO (op)) >= 4);
665 /* Similar, but return 1 if OP is a MEM which is not alignable. */
668 unaligned_memory_operand (op, mode)
670 enum machine_mode mode;
672 if (GET_CODE (op) == SUBREG)
674 if (GET_MODE (op) != mode)
676 op = SUBREG_REG (op);
677 mode = GET_MODE (op);
680 if (reload_in_progress && GET_CODE (op) == REG
681 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
682 op = reg_equiv_mem[REGNO (op)];
684 if (GET_CODE (op) != MEM || GET_MODE (op) != mode)
689 if (! memory_address_p (mode, op))
692 if (GET_CODE (op) == PLUS)
695 return (GET_CODE (op) != REG
696 || REGNO_POINTER_ALIGN (REGNO (op)) < 4);
699 /* Return 1 if OP is either a register or an unaligned memory location. */
702 reg_or_unaligned_mem_operand (op, mode)
704 enum machine_mode mode;
706 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
709 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
712 any_memory_operand (op, mode)
714 enum machine_mode mode;
716 return (GET_CODE (op) == MEM
717 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
718 || (reload_in_progress && GET_CODE (op) == REG
719 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
720 || (reload_in_progress && GET_CODE (op) == SUBREG
721 && GET_CODE (SUBREG_REG (op)) == REG
722 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
725 /* REF is an alignable memory location. Place an aligned SImode
726 reference into *PALIGNED_MEM and the number of bits to shift into
730 get_aligned_mem (ref, paligned_mem, pbitnum)
732 rtx *paligned_mem, *pbitnum;
735 HOST_WIDE_INT offset = 0;
737 if (GET_CODE (ref) == SUBREG)
739 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
740 if (BYTES_BIG_ENDIAN)
741 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
742 - MIN (UNITS_PER_WORD,
743 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
744 ref = SUBREG_REG (ref);
747 if (GET_CODE (ref) == REG)
748 ref = reg_equiv_mem[REGNO (ref)];
750 if (reload_in_progress)
751 base = find_replacement (&XEXP (ref, 0));
753 base = XEXP (ref, 0);
755 if (GET_CODE (base) == PLUS)
756 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
758 *paligned_mem = gen_rtx (MEM, SImode,
759 plus_constant (base, offset & ~3));
760 MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref);
761 MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref);
762 RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref);
764 *pbitnum = GEN_INT ((offset & 3) * 8);
767 /* Similar, but just get the address. Handle the two reload cases.
768 Add EXTRA_OFFSET to the address we return. */
771 get_unaligned_address (ref, extra_offset)
776 HOST_WIDE_INT offset = 0;
778 if (GET_CODE (ref) == SUBREG)
780 offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
781 if (BYTES_BIG_ENDIAN)
782 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
783 - MIN (UNITS_PER_WORD,
784 GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
785 ref = SUBREG_REG (ref);
788 if (GET_CODE (ref) == REG)
789 ref = reg_equiv_mem[REGNO (ref)];
791 if (reload_in_progress)
792 base = find_replacement (&XEXP (ref, 0));
794 base = XEXP (ref, 0);
796 if (GET_CODE (base) == PLUS)
797 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
799 return plus_constant (base, offset + extra_offset);
802 /* Subfunction of the following function. Update the flags of any MEM
803 found in part of X. */
806 alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
808 int in_struct_p, volatile_p, unchanging_p;
812 switch (GET_CODE (x))
816 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
817 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
822 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
827 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
829 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
834 MEM_IN_STRUCT_P (x) = in_struct_p;
835 MEM_VOLATILE_P (x) = volatile_p;
836 RTX_UNCHANGING_P (x) = unchanging_p;
841 /* Given INSN, which is either an INSN or a SEQUENCE generated to
842 perform a memory operation, look for any MEMs in either a SET_DEST or
843 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
844 REF into each of the MEMs found. If REF is not a MEM, don't do
848 alpha_set_memflags (insn, ref)
852 /* Note that it is always safe to get these flags, though they won't
853 be what we think if REF is not a MEM. */
854 int in_struct_p = MEM_IN_STRUCT_P (ref);
855 int volatile_p = MEM_VOLATILE_P (ref);
856 int unchanging_p = RTX_UNCHANGING_P (ref);
858 if (GET_CODE (ref) != MEM
859 || (! in_struct_p && ! volatile_p && ! unchanging_p))
862 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
865 /* Try to output insns to set TARGET equal to the constant C if it can be
866 done in less than N insns. Do all computations in MODE. Returns the place
867 where the output has been placed if it can be done and the insns have been
868 emitted. If it would take more than N insns, zero is returned and no
869 insns and emitted. */
872 alpha_emit_set_const (target, mode, c, n)
874 enum machine_mode mode;
881 /* Try 1 insn, then 2, then up to N. */
882 for (i = 1; i <= n; i++)
883 if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
889 /* Internal routine for the above to check for N or below insns. */
892 alpha_emit_set_const_1 (target, mode, c, n)
894 enum machine_mode mode;
898 HOST_WIDE_INT new = c;
900 /* Use a pseudo if highly optimizing and still generating RTL. */
902 = (flag_expensive_optimizations && rtx_equal_function_value_matters
906 #if HOST_BITS_PER_WIDE_INT == 64
907 /* We are only called for SImode and DImode. If this is SImode, ensure that
908 we are sign extended to a full word. This does not make any sense when
909 cross-compiling on a narrow machine. */
912 c = (c & 0xffffffff) - 2 * (c & 0x80000000);
915 /* If this is a sign-extended 32-bit constant, we can do this in at most
916 three insns, so do it if we have enough insns left. We always have
917 a sign-extended 32-bit constant when compiling on a narrow machine. */
919 if (HOST_BITS_PER_WIDE_INT != 64
920 || c >> 31 == -1 || c >> 31 == 0)
922 HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
923 HOST_WIDE_INT tmp1 = c - low;
925 = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
926 HOST_WIDE_INT extra = 0;
928 /* If HIGH will be interpreted as negative but the constant is
929 positive, we must adjust it to do two ldha insns. */
931 if ((high & 0x8000) != 0 && c >= 0)
935 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
938 if (c == low || (low == 0 && extra == 0))
940 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
941 but that meant that we can't handle INT_MIN on 32-bit machines
942 (like NT/Alpha), because we recurse indefinitely through
943 emit_move_insn to gen_movdi. So instead, since we know exactly
944 what we want, create it explicitly. */
947 target = gen_reg_rtx (mode);
948 emit_insn (gen_rtx (SET, VOIDmode, target, GEN_INT (c)));
951 else if (n >= 2 + (extra != 0))
953 temp = copy_to_suggested_reg (GEN_INT (low), subtarget, mode);
956 temp = expand_binop (mode, add_optab, temp, GEN_INT (extra << 16),
957 subtarget, 0, OPTAB_WIDEN);
959 return expand_binop (mode, add_optab, temp, GEN_INT (high << 16),
960 target, 0, OPTAB_WIDEN);
964 /* If we couldn't do it that way, try some other methods. But if we have
965 no instructions left, don't bother. Likewise, if this is SImode and
966 we can't make pseudos, we can't do anything since the expand_binop
967 and expand_unop calls will widen and try to make pseudos. */
970 || (mode == SImode && ! rtx_equal_function_value_matters))
973 #if HOST_BITS_PER_WIDE_INT == 64
974 /* First, see if can load a value into the target that is the same as the
975 constant except that all bytes that are 0 are changed to be 0xff. If we
976 can, then we can do a ZAPNOT to obtain the desired constant. */
978 for (i = 0; i < 64; i += 8)
979 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
980 new |= (HOST_WIDE_INT) 0xff << i;
982 /* We are only called for SImode and DImode. If this is SImode, ensure that
983 we are sign extended to a full word. */
986 new = (new & 0xffffffff) - 2 * (new & 0x80000000);
989 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
990 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
991 target, 0, OPTAB_WIDEN);
994 /* Next, see if we can load a related constant and then shift and possibly
995 negate it to get the constant we want. Try this once each increasing
998 for (i = 1; i < n; i++)
1000 /* First try complementing. */
1001 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
1002 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1004 /* Next try to form a constant and do a left shift. We can do this
1005 if some low-order bits are zero; the exact_log2 call below tells
1006 us that information. The bits we are shifting out could be any
1007 value, but here we'll just try the 0- and sign-extended forms of
1008 the constant. To try to increase the chance of having the same
1009 constant in more than one insn, start at the highest number of
1010 bits to shift, but try all possibilities in case a ZAPNOT will
1013 if ((bits = exact_log2 (c & - c)) > 0)
1014 for (; bits > 0; bits--)
1015 if ((temp = (alpha_emit_set_const
1017 (unsigned HOST_WIDE_INT) c >> bits, i))) != 0
1018 || ((temp = (alpha_emit_set_const
1020 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
1022 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1023 target, 0, OPTAB_WIDEN);
1025 /* Now try high-order zero bits. Here we try the shifted-in bits as
1026 all zero and all ones. Be careful to avoid shifting outside the
1027 mode and to avoid shifting outside the host wide int size. */
1028 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1029 confuse the recursive call and set all of the high 32 bits. */
1031 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1032 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
1033 for (; bits > 0; bits--)
1034 if ((temp = alpha_emit_set_const (subtarget, mode,
1036 || ((temp = (alpha_emit_set_const
1038 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1041 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1042 target, 1, OPTAB_WIDEN);
1044 /* Now try high-order 1 bits. We get that with a sign-extension.
1045 But one bit isn't enough here. Be careful to avoid shifting outside
1046 the mode and to avoid shifting outside the host wide int size. */
1048 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1049 - floor_log2 (~ c) - 2)) > 0)
1050 for (; bits > 0; bits--)
1051 if ((temp = alpha_emit_set_const (subtarget, mode,
1053 || ((temp = (alpha_emit_set_const
1055 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1058 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1059 target, 0, OPTAB_WIDEN);
1065 #if HOST_BITS_PER_WIDE_INT == 64
1066 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1067 fall back to a straight forward decomposition. We do this to avoid
1068 exponential run times encountered when looking for longer sequences
1069 with alpha_emit_set_const. */
1072 alpha_emit_set_long_const (target, c)
1076 /* Use a pseudo if highly optimizing and still generating RTL. */
1078 = (flag_expensive_optimizations && rtx_equal_function_value_matters
1080 HOST_WIDE_INT d1, d2, d3, d4;
1083 /* Decompose the entire word */
1084 d1 = ((c & 0xffff) ^ 0x8000) - 0x8000;
1086 d2 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
1088 d3 = ((c & 0xffff) ^ 0x8000) - 0x8000;
1090 d4 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
1095 /* Construct the high word */
1097 r1 = copy_to_suggested_reg (GEN_INT (d4), subtarget, DImode);
1099 r1 = copy_to_suggested_reg (GEN_INT (d3), subtarget, DImode);
1101 r1 = expand_binop (DImode, add_optab, GEN_INT (d3), GEN_INT (d4),
1102 subtarget, 0, OPTAB_WIDEN);
1104 /* Shift it into place */
1105 r2 = expand_binop (DImode, ashl_optab, r1, GEN_INT (32),
1106 subtarget, 0, OPTAB_WIDEN);
1108 if (subtarget == 0 && d1 == d3 && d2 == d4)
1109 r1 = expand_binop (DImode, add_optab, r1, r2, subtarget, 0, OPTAB_WIDEN);
1114 /* Add in the low word */
1116 r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d2),
1117 subtarget, 0, OPTAB_WIDEN);
1119 r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d1),
1120 subtarget, 0, OPTAB_WIDEN);
1124 r1 = copy_to_suggested_reg(r1, target, DImode);
1128 #endif /* HOST_BITS_PER_WIDE_INT == 64 */
1130 /* Rewrite a comparison against zero CMP of the form
1131 (CODE (cc0) (const_int 0)) so it can be written validly in
1132 a conditional move (if_then_else CMP ...).
1133 If both of the operands that set cc0 are non-zero we must emit
1134 an insn to perform the compare (it can't be done within
1135 the conditional move). */
1137 alpha_emit_conditional_move (cmp, mode)
1139 enum machine_mode mode;
1141 enum rtx_code code = GET_CODE (cmp);
1142 enum rtx_code cmov_code = NE;
1143 rtx op0 = alpha_compare_op0;
1144 rtx op1 = alpha_compare_op1;
1145 enum machine_mode cmp_mode
1146 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
1147 enum machine_mode cmp_op_mode = alpha_compare_fp_p ? DFmode : DImode;
1150 if (alpha_compare_fp_p != FLOAT_MODE_P (mode))
1153 /* We may be able to use a conditional move directly.
1154 This avoids emitting spurious compares. */
1155 if (signed_comparison_operator (cmp, cmp_op_mode)
1156 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
1157 return gen_rtx (code, VOIDmode, op0, op1);
1159 /* We can't put the comparison insides a conditional move;
1160 emit a compare instruction and put that inside the
1161 conditional move. Make sure we emit only comparisons we have;
1162 swap or reverse as necessary. */
1166 case EQ: case LE: case LT: case LEU: case LTU:
1167 /* We have these compares: */
1171 /* This must be reversed. */
1172 code = reverse_condition (code);
1176 case GE: case GT: case GEU: case GTU:
1177 /* These must be swapped. Make sure the new first operand is in
1179 code = swap_condition (code);
1180 tem = op0, op0 = op1, op1 = tem;
1181 op0 = force_reg (cmp_mode, op0);
1188 tem = gen_reg_rtx (cmp_op_mode);
1189 emit_move_insn (tem, gen_rtx (code, cmp_op_mode, op0, op1));
1190 return gen_rtx (cmov_code, VOIDmode, tem, CONST0_RTX (cmp_op_mode));
1193 /* Adjust the cost of a scheduling dependency. Return the new cost of
1194 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
1197 alpha_adjust_cost (insn, link, dep_insn, cost)
1204 enum attr_type insn_type, dep_insn_type;
1206 /* If the dependence is an anti-dependence, there is no cost. For an
1207 output dependence, there is sometimes a cost, but it doesn't seem
1208 worth handling those few cases. */
1210 if (REG_NOTE_KIND (link) != 0)
1213 /* If we can't recognize the insns, we can't really do anything. */
1214 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
1217 insn_type = get_attr_type (insn);
1218 dep_insn_type = get_attr_type (dep_insn);
1220 if (alpha_cpu == PROCESSOR_EV5)
1222 /* And the lord DEC saith: "A special bypass provides an effective
1223 latency of 0 cycles for an ICMP or ILOG insn producing the test
1224 operand of an IBR or CMOV insn." */
1225 if ((dep_insn_type == TYPE_ICMP
1226 || dep_insn_type == TYPE_ILOG)
1227 && (insn_type == TYPE_IBR
1228 || (insn_type == TYPE_CMOV
1229 && !((set = single_set (dep_insn)) != 0
1230 && GET_CODE (PATTERN (insn)) == SET
1231 && (set_src = SET_SRC (PATTERN (insn)),
1232 GET_CODE (set_src) == IF_THEN_ELSE)
1233 && (set = SET_DEST (set),
1234 rtx_equal_p (set, XEXP (set_src, 1))
1235 || rtx_equal_p (set, XEXP (set_src, 2)))))))
1238 /* "The multiplier is unable to receive data from IEU bypass paths.
1239 The instruction issues at the expected time, but its latency is
1240 increased by the time it takes for the input data to become
1241 available to the multiplier" -- which happens in pipeline stage
1242 six, when results are comitted to the register file. */
1244 if ((insn_type == TYPE_IMULL
1245 || insn_type == TYPE_IMULQ
1246 || insn_type == TYPE_IMULH)
1247 && (set = single_set (dep_insn)) != 0
1248 && GET_CODE (PATTERN (insn)) == SET
1249 && (set_src = SET_SRC (PATTERN (insn)),
1250 GET_CODE (set_src) == MULT)
1251 && (set = SET_DEST (set),
1252 rtx_equal_p (set, XEXP (set_src, 0))
1253 || rtx_equal_p (set, XEXP (set_src, 1))))
1255 switch (dep_insn_type)
1257 /* These insns produce their results in pipeline stage five. */
1266 /* Other integer insns produce results in pipeline stage four. */
1274 /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
1275 being stored, we can sometimes lower the cost. */
1277 if (insn_type == TYPE_ST
1278 && (set = single_set (dep_insn)) != 0
1279 && GET_CODE (PATTERN (insn)) == SET
1280 && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
1282 switch (dep_insn_type)
1285 /* No savings here. */
1291 /* In these cases, we save one cycle. */
1295 /* In all other cases, we save two cycles. */
1296 return MAX (0, cost - 2);
1300 /* Another case that needs adjustment is an arithmetic or logical
1301 operation. It's cost is usually one cycle, but we default it to
1302 two in the MD file. The only case that it is actually two is
1303 for the address in loads and stores. */
1305 if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
1317 /* The final case is when a compare feeds into an integer branch;
1318 the cost is only one cycle in that case. */
1320 if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
1324 /* Otherwise, return the default cost. */
1328 /* Functions to save and restore alpha_return_addr_rtx. */
1330 struct machine_function
1336 alpha_save_machine_status (p)
1339 struct machine_function *machine =
1340 (struct machine_function *) xmalloc (sizeof (struct machine_function));
1342 p->machine = machine;
1343 machine->ra_rtx = alpha_return_addr_rtx;
1347 alpha_restore_machine_status (p)
1350 struct machine_function *machine = p->machine;
1352 alpha_return_addr_rtx = machine->ra_rtx;
1355 p->machine = (struct machine_function *)0;
1358 /* Do anything needed before RTL is emitted for each function. */
1361 alpha_init_expanders ()
1363 alpha_return_addr_rtx = NULL_RTX;
1365 /* Arrange to save and restore machine status around nested functions. */
1366 save_machine_status = alpha_save_machine_status;
1367 restore_machine_status = alpha_restore_machine_status;
1370 /* Start the ball rolling with RETURN_ADDR_RTX. */
1373 alpha_return_addr (count, frame)
1382 if (alpha_return_addr_rtx)
1383 return alpha_return_addr_rtx;
1385 /* No rtx yet. Invent one, and initialize it from $26 in the prologue. */
1386 alpha_return_addr_rtx = gen_reg_rtx (Pmode);
1387 init = gen_rtx (SET, Pmode, alpha_return_addr_rtx, gen_rtx (REG, Pmode, 26));
1389 /* Emit the insn to the prologue with the other argument copies. */
1390 push_topmost_sequence ();
1391 emit_insn_after (init, get_insns ());
1392 pop_topmost_sequence ();
1394 return alpha_return_addr_rtx;
1398 alpha_ra_ever_killed ()
1402 if (!alpha_return_addr_rtx)
1403 return regs_ever_live[REG_RA];
1405 return reg_set_between_p (gen_rtx (REG, REG_RA), get_insns(), NULL_RTX);
1409 /* Print an operand. Recognize special options, documented below. */
1412 print_operand (file, x, code)
1422 /* Generates fp-rounding mode suffix: nothing for normal, 'c' for
1423 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
1424 mode. alpha_fprm controls which suffix is generated. */
1427 case ALPHA_FPRM_NORM:
1429 case ALPHA_FPRM_MINF:
1432 case ALPHA_FPRM_CHOP:
1435 case ALPHA_FPRM_DYN:
1442 /* Generates trap-mode suffix for instructions that accept the su
1443 suffix only (cmpt et al). */
1444 if (alpha_tp == ALPHA_TP_INSN)
1449 /* Generates trap-mode suffix for instructions that accept the u, su,
1450 and sui suffix. This is the bulk of the IEEE floating point
1451 instructions (addt et al). */
1462 case ALPHA_FPTM_SUI:
1463 fputs ("sui", file);
1469 /* Generates trap-mode suffix for instructions that accept the sui
1470 suffix (cvtqt and cvtqs). */
1473 case ALPHA_FPTM_N: case ALPHA_FPTM_U:
1474 case ALPHA_FPTM_SU: /* cvtqt/cvtqs can't cause underflow */
1476 case ALPHA_FPTM_SUI:
1477 fputs ("sui", file);
1483 /* Generates single precision instruction suffix. */
1484 fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'f' : 's'));
1488 /* Generates double precision instruction suffix. */
1489 fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'g' : 't'));
1493 /* If this operand is the constant zero, write it as "$31". */
1494 if (GET_CODE (x) == REG)
1495 fprintf (file, "%s", reg_names[REGNO (x)]);
1496 else if (x == CONST0_RTX (GET_MODE (x)))
1497 fprintf (file, "$31");
1499 output_operand_lossage ("invalid %%r value");
1504 /* Similar, but for floating-point. */
1505 if (GET_CODE (x) == REG)
1506 fprintf (file, "%s", reg_names[REGNO (x)]);
1507 else if (x == CONST0_RTX (GET_MODE (x)))
1508 fprintf (file, "$f31");
1510 output_operand_lossage ("invalid %%R value");
1515 /* Write the 1's complement of a constant. */
1516 if (GET_CODE (x) != CONST_INT)
1517 output_operand_lossage ("invalid %%N value");
1519 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
1523 /* Write 1 << C, for a constant C. */
1524 if (GET_CODE (x) != CONST_INT)
1525 output_operand_lossage ("invalid %%P value");
1527 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
1531 /* Write the high-order 16 bits of a constant, sign-extended. */
1532 if (GET_CODE (x) != CONST_INT)
1533 output_operand_lossage ("invalid %%h value");
1535 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
1539 /* Write the low-order 16 bits of a constant, sign-extended. */
1540 if (GET_CODE (x) != CONST_INT)
1541 output_operand_lossage ("invalid %%L value");
1543 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
1544 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
1548 /* Write mask for ZAP insn. */
1549 if (GET_CODE (x) == CONST_DOUBLE)
1551 HOST_WIDE_INT mask = 0;
1552 HOST_WIDE_INT value;
1554 value = CONST_DOUBLE_LOW (x);
1555 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
1560 value = CONST_DOUBLE_HIGH (x);
1561 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
1564 mask |= (1 << (i + sizeof (int)));
1566 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
1569 else if (GET_CODE (x) == CONST_INT)
1571 HOST_WIDE_INT mask = 0, value = INTVAL (x);
1573 for (i = 0; i < 8; i++, value >>= 8)
1577 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
1580 output_operand_lossage ("invalid %%m value");
1584 /* 'b', 'w', or 'l' as the value of the constant. */
1585 if (GET_CODE (x) != CONST_INT
1586 || (INTVAL (x) != 8 && INTVAL (x) != 16 && INTVAL (x) != 32))
1587 output_operand_lossage ("invalid %%M value");
1589 fprintf (file, "%s",
1590 INTVAL (x) == 8 ? "b" : INTVAL (x) == 16 ? "w" : "l");
1594 /* Similar, except do it from the mask. */
1595 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xff)
1596 fprintf (file, "b");
1597 else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
1598 fprintf (file, "w");
1599 #if HOST_BITS_PER_WIDE_INT == 32
1600 else if (GET_CODE (x) == CONST_DOUBLE
1601 && CONST_DOUBLE_HIGH (x) == 0
1602 && CONST_DOUBLE_LOW (x) == -1)
1603 fprintf (file, "l");
1605 else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
1606 fprintf (file, "l");
1609 output_operand_lossage ("invalid %%U value");
1613 /* Write the constant value divided by 8. */
1614 if (GET_CODE (x) != CONST_INT
1615 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
1616 && (INTVAL (x) & 7) != 8)
1617 output_operand_lossage ("invalid %%s value");
1619 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
1623 /* Same, except compute (64 - c) / 8 */
1625 if (GET_CODE (x) != CONST_INT
1626 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
1627 && (INTVAL (x) & 7) != 8)
1628 output_operand_lossage ("invalid %%s value");
1630 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
1633 case 'C': case 'D': case 'c': case 'd':
1634 /* Write out comparison name. */
1636 enum rtx_code c = GET_CODE (x);
1638 if (GET_RTX_CLASS (c) != '<')
1639 output_operand_lossage ("invalid %%C value");
1642 c = reverse_condition (c);
1643 else if (code == 'c')
1644 c = swap_condition (c);
1645 else if (code == 'd')
1646 c = swap_condition (reverse_condition (c));
1649 fprintf (file, "ule");
1651 fprintf (file, "ult");
1653 fprintf (file, "%s", GET_RTX_NAME (c));
1658 /* Write the divide or modulus operator. */
1659 switch (GET_CODE (x))
1662 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
1665 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
1668 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
1671 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
1674 output_operand_lossage ("invalid %%E value");
1680 /* Write "_u" for unaligned access. */
1681 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
1682 fprintf (file, "_u");
1686 if (GET_CODE (x) == REG)
1687 fprintf (file, "%s", reg_names[REGNO (x)]);
1688 else if (GET_CODE (x) == MEM)
1689 output_address (XEXP (x, 0));
1691 output_addr_const (file, x);
1695 output_operand_lossage ("invalid %%xn code");
1699 /* Do what is necessary for `va_start'. The argument is ignored;
1700 We look at the current function to determine if stdarg or varargs
1701 is used and fill in an initial va_list. A pointer to this constructor
1705 alpha_builtin_saveregs (arglist)
1708 rtx block, addr, dest, argsize;
1709 tree fntype = TREE_TYPE (current_function_decl);
1710 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
1711 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1712 != void_type_node));
1714 /* Compute the current position into the args, taking into account
1715 both registers and memory. Both of these are already included in
1718 argsize = GEN_INT (NUM_ARGS * UNITS_PER_WORD);
1720 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base up by 48,
1721 storing fp arg registers in the first 48 bytes, and the integer arg
1722 registers in the next 48 bytes. This is only done, however, if any
1723 integer registers need to be stored.
1725 If no integer registers need be stored, then we must subtract 48 in
1726 order to account for the integer arg registers which are counted in
1727 argsize above, but which are not actually stored on the stack. */
1729 if (TARGET_OPEN_VMS)
1730 addr = plus_constant (virtual_incoming_args_rtx,
1731 NUM_ARGS <= 5 + stdarg
1732 ? UNITS_PER_WORD : - 6 * UNITS_PER_WORD);
1734 addr = (NUM_ARGS <= 5 + stdarg
1735 ? plus_constant (virtual_incoming_args_rtx,
1737 : plus_constant (virtual_incoming_args_rtx,
1738 - (6 * UNITS_PER_WORD)));
1740 /* For VMS, we include the argsize, while on Unix, it's handled as
1741 a separate field. */
1742 if (TARGET_OPEN_VMS)
1743 addr = plus_constant (addr, INTVAL (argsize));
1745 addr = force_operand (addr, NULL_RTX);
1747 #ifdef POINTERS_EXTEND_UNSIGNED
1748 addr = convert_memory_address (ptr_mode, addr);
1751 if (TARGET_OPEN_VMS)
1755 /* Allocate the va_list constructor */
1756 block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
1757 RTX_UNCHANGING_P (block) = 1;
1758 RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
1760 /* Store the address of the first integer register in the __base
1763 dest = change_address (block, ptr_mode, XEXP (block, 0));
1764 emit_move_insn (dest, addr);
1766 if (flag_check_memory_usage)
1767 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
1769 GEN_INT (GET_MODE_SIZE (ptr_mode)),
1770 TYPE_MODE (sizetype),
1771 GEN_INT (MEMORY_USE_RW),
1772 TYPE_MODE (integer_type_node));
1774 /* Store the argsize as the __va_offset member. */
1775 dest = change_address (block, TYPE_MODE (integer_type_node),
1776 plus_constant (XEXP (block, 0),
1777 POINTER_SIZE/BITS_PER_UNIT));
1778 emit_move_insn (dest, argsize);
1780 if (flag_check_memory_usage)
1781 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
1783 GEN_INT (GET_MODE_SIZE
1784 (TYPE_MODE (integer_type_node))),
1785 TYPE_MODE (sizetype),
1786 GEN_INT (MEMORY_USE_RW),
1787 TYPE_MODE (integer_type_node));
1789 /* Return the address of the va_list constructor, but don't put it in a
1790 register. Doing so would fail when not optimizing and produce worse
1791 code when optimizing. */
1792 return XEXP (block, 0);
1796 /* This page contains routines that are used to determine what the function
1797 prologue and epilogue code will do and write them out. */
1799 /* Compute the size of the save area in the stack. */
1803 /* These variables are used for communication between the following functions.
1804 They indicate various things about the current function being compiled
1805 that are used to tell what kind of prologue, epilogue and procedure
1806 descriptior to generate. */
1808 /* Nonzero if we need a stack procedure. */
1809 static int is_stack_procedure;
1811 /* Register number (either FP or SP) that is used to unwind the frame. */
1812 static int unwind_regno;
1814 /* Register number used to save FP. We need not have one for RA since
1815 we don't modify it for register procedures. This is only defined
1816 for register frame procedures. */
1817 static int save_fp_regno;
1819 /* Register number used to reference objects off our PV. */
1820 static int base_regno;
1822 /* Compute register masks for saved registers. */
1825 alpha_sa_mask (imaskP, fmaskP)
1826 unsigned long *imaskP;
1827 unsigned long *fmaskP;
1829 unsigned long imask = 0;
1830 unsigned long fmask = 0;
1833 if (is_stack_procedure)
1834 imask |= (1L << HARD_FRAME_POINTER_REGNUM);
1836 /* One for every register we have to save. */
1838 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1839 if (! fixed_regs[i] && ! call_used_regs[i]
1840 && regs_ever_live[i] && i != REG_RA)
1845 fmask |= (1L << (i - 32));
1858 HOST_WIDE_INT stack_needed;
1861 /* One for every register we have to save. */
1863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1864 if (! fixed_regs[i] && ! call_used_regs[i]
1865 && regs_ever_live[i] && i != REG_RA)
1868 /* Start by assuming we can use a register procedure if we don't make any
1869 calls (REG_RA not used) or need to save any registers and a stack
1870 procedure if we do. */
1871 is_stack_procedure = sa_size != 0 || alpha_ra_ever_killed ();
1873 /* Decide whether to refer to objects off our PV via FP or PV.
1874 If we need need FP for something else or if we receive a nonlocal
1875 goto (which expects PV to contain the value), we must use PV.
1876 Otherwise, start by assuming we can use FP. */
1877 base_regno = (frame_pointer_needed || current_function_has_nonlocal_label
1878 || is_stack_procedure
1879 || current_function_outgoing_args_size
1880 ? REG_PV : HARD_FRAME_POINTER_REGNUM);
1882 /* If we want to copy PV into FP, we need to find some register in which to
1887 if (base_regno == HARD_FRAME_POINTER_REGNUM)
1888 for (i = 0; i < 32; i++)
1889 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
1892 if (save_fp_regno == -1)
1893 base_regno = REG_PV, is_stack_procedure = 1;
1895 /* Stack unwinding should be done via FP unless we use it for PV. */
1897 = base_regno == REG_PV ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
1899 /* If this is a stack procedure, allow space for saving FP and RA. */
1900 if (is_stack_procedure)
1907 alpha_pv_save_size ()
1910 return is_stack_procedure ? 8 : 0;
1917 return unwind_regno == HARD_FRAME_POINTER_REGNUM;
1920 #else /* ! OPEN_VMS */
1928 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1929 if (! fixed_regs[i] && ! call_used_regs[i]
1930 && regs_ever_live[i] && i != REG_RA)
1933 /* If some registers were saved but not reg 26, reg 26 must also
1934 be saved, so leave space for it. */
1935 if (size != 0 || alpha_ra_ever_killed ())
1938 /* Our size must be even (multiple of 16 bytes). */
1945 #endif /* ! OPEN_VMS */
1947 /* Return 1 if this function can directly return via $26. */
1952 return (! TARGET_OPEN_VMS && reload_completed && alpha_sa_size () == 0
1953 && get_frame_size () == 0
1954 && current_function_outgoing_args_size == 0
1955 && current_function_pretend_args_size == 0);
1958 /* Write a version stamp. Don't write anything if we are running as a
1959 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
1961 #if !defined(CROSS_COMPILE) && !defined(_WIN32) && !defined(__linux__) && !defined(VMS)
1966 alpha_write_verstamp (file)
1970 fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
1974 /* Write code to add constant C to register number IN_REG (possibly 31)
1975 and put the result into OUT_REG. Use TEMP_REG as a scratch register;
1976 usually this will be OUT_REG, but should not be if OUT_REG is
1977 STACK_POINTER_REGNUM, since it must be updated in a single instruction.
1978 Write the code to FILE. */
1981 add_long_const (file, c, in_reg, out_reg, temp_reg)
1984 int in_reg, out_reg, temp_reg;
1986 HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
1987 HOST_WIDE_INT tmp1 = c - low;
1988 HOST_WIDE_INT high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1989 HOST_WIDE_INT extra = 0;
1991 /* We don't have code to write out constants larger than 32 bits. */
1992 #if HOST_BITS_PER_LONG_INT == 64
1993 if ((unsigned HOST_WIDE_INT) c >> 32 != 0)
1997 /* If HIGH will be interpreted as negative, we must adjust it to do two
1998 ldha insns. Note that we will never be building a negative constant
2005 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2010 int result_reg = (extra == 0 && high == 0) ? out_reg : temp_reg;
2012 if (low >= 0 && low < 255)
2013 fprintf (file, "\taddq $%d,%d,$%d\n", in_reg, low, result_reg);
2015 fprintf (file, "\tlda $%d,%d($%d)\n", result_reg, low, in_reg);
2017 in_reg = result_reg;
2022 int result_reg = (high == 0) ? out_reg : temp_reg;
2024 fprintf (file, "\tldah $%d,%d($%d)\n", result_reg, extra, in_reg);
2025 in_reg = result_reg;
2029 fprintf (file, "\tldah $%d,%d($%d)\n", out_reg, high, in_reg);
2032 /* Write function prologue. */
2036 /* On vms we have two kinds of functions:
2038 - stack frame (PROC_STACK)
2039 these are 'normal' functions with local vars and which are
2040 calling other functions
2041 - register frame (PROC_REGISTER)
2042 keeps all data in registers, needs no stack
2044 We must pass this to the assembler so it can generate the
2045 proper pdsc (procedure descriptor)
2046 This is done with the '.pdesc' command.
2048 size is the stack size needed for local variables. */
2051 output_prolog (file, size)
2055 unsigned long imask = 0;
2056 unsigned long fmask = 0;
2057 /* Stack space needed for pushing registers clobbered by us. */
2058 HOST_WIDE_INT sa_size;
2059 /* Complete stack size needed. */
2060 HOST_WIDE_INT frame_size;
2061 /* Offset from base reg to register save area. */
2063 /* Offset during register save. */
2065 /* Label for the procedure entry. */
2066 char *entry_label = (char *) alloca (strlen (alpha_function_name) + 6);
2069 sa_size = alpha_sa_size ();
2071 = ALPHA_ROUND (sa_size
2072 + (is_stack_procedure ? 8 : 0)
2073 + size + current_function_pretend_args_size);
2075 /* Issue function start and label. */
2076 fprintf (file, "\t.ent ");
2077 assemble_name (file, alpha_function_name);
2078 fprintf (file, "\n");
2079 sprintf (entry_label, "$%s..en", alpha_function_name);
2080 ASM_OUTPUT_LABEL (file, entry_label);
2081 inside_function = TRUE;
2083 fprintf (file, "\t.base $%d\n", base_regno);
2085 /* Calculate register masks for clobbered registers. */
2087 if (is_stack_procedure)
2088 alpha_sa_mask (&imask, &fmask);
2090 /* Adjust the stack by the frame size. If the frame size is > 4096
2091 bytes, we need to be sure we probe somewhere in the first and last
2092 4096 bytes (we can probably get away without the latter test) and
2093 every 8192 bytes in between. If the frame size is > 32768, we
2094 do this in a loop. Otherwise, we generate the explicit probe
2097 Note that we are only allowed to adjust sp once in the prologue. */
2099 if (frame_size < 32768)
2101 if (frame_size > 4096)
2105 fprintf (file, "\tstq $31,-%d($30)\n", probed);
2107 while (probed + 8192 < frame_size)
2108 fprintf (file, "\tstq $31,-%d($30)\n", probed += 8192);
2110 /* We only have to do this probe if we aren't saving registers. */
2111 if (sa_size == 0 && probed + 4096 < frame_size)
2112 fprintf (file, "\tstq $31,-%d($30)\n", frame_size);
2115 if (frame_size != 0)
2116 fprintf (file, "\tlda $30,-%d($30)\n", frame_size);
2120 /* Here we generate code to set R4 to SP + 4096 and set R23 to the
2121 number of 8192 byte blocks to probe. We then probe each block
2122 in the loop and then set SP to the proper location. If the
2123 amount remaining is > 4096, we have to do one more probe if we
2124 are not saving any registers. */
2126 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
2127 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
2129 add_long_const (file, blocks, 31, 23, 23);
2131 fprintf (file, "\tlda $22,4096($30)\n");
2134 assemble_name (file, alpha_function_name);
2135 fprintf (file, "..sc:\n");
2137 fprintf (file, "\tstq $31,-8192($22)\n");
2138 fprintf (file, "\tsubq $23,1,$23\n");
2139 fprintf (file, "\tlda $22,-8192($22)\n");
2141 fprintf (file, "\tbne $23,$");
2142 assemble_name (file, alpha_function_name);
2143 fprintf (file, "..sc\n");
2145 if (leftover > 4096 && sa_size == 0)
2146 fprintf (file, "\tstq $31,-%d($22)\n", leftover);
2148 fprintf (file, "\tlda $30,-%d($22)\n", leftover);
2151 if (is_stack_procedure)
2153 int reg_offset = rsa_offset;
2155 /* Store R26 (RA) first. */
2156 fprintf (file, "\tstq $26,%d($30)\n", reg_offset);
2159 /* Store integer regs. according to mask. */
2160 for (i = 0; i < 32; i++)
2161 if (imask & (1L<<i))
2163 fprintf (file, "\tstq $%d,%d($30)\n", i, reg_offset);
2167 /* Print the register mask and do floating-point saves. */
2170 fprintf (file, "\t.mask 0x%x,0\n", imask);
2172 for (i = 0; i < 32; i++)
2174 if (fmask & (1L << i))
2176 fprintf (file, "\tstt $f%d,%d($30)\n", i, reg_offset);
2181 /* Print the floating-point mask, if we've saved any fp register. */
2183 fprintf (file, "\t.fmask 0x%x,0\n", fmask);
2185 fprintf (file, "\tstq $27,0($30)\n");
2189 fprintf (file, "\t.fp_save $%d\n", save_fp_regno);
2190 fprintf (file, "\tbis $%d,$%d,$%d\n", HARD_FRAME_POINTER_REGNUM,
2191 HARD_FRAME_POINTER_REGNUM, save_fp_regno);
2194 if (base_regno != REG_PV)
2195 fprintf (file, "\tbis $%d,$%d,$%d\n", REG_PV, REG_PV, base_regno);
2197 if (unwind_regno == HARD_FRAME_POINTER_REGNUM)
2198 fprintf (file, "\tbis $%d,$%d,$%d\n", STACK_POINTER_REGNUM,
2199 STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM);
2201 /* Describe our frame. */
2202 fprintf (file, "\t.frame $%d,%d,$26,%d\n",
2203 unwind_regno, frame_size, rsa_offset);
2205 /* If we have to allocate space for outgoing args, do it now. */
2206 if (current_function_outgoing_args_size != 0)
2207 fprintf (file, "\tlda $%d,%d($%d)\n", STACK_POINTER_REGNUM,
2208 - ALPHA_ROUND (current_function_outgoing_args_size),
2209 HARD_FRAME_POINTER_REGNUM);
2211 fprintf (file, "\t.prologue\n");
2214 fprintf (file, "\t.align 3\n");
2215 ASM_OUTPUT_LABEL (file, alpha_function_name);
2216 fprintf (file, "\t.pdesc $");
2217 assemble_name (file, alpha_function_name);
2218 fprintf (file, "..en,%s\n", is_stack_procedure ? "stack" : "reg");
2219 alpha_need_linkage (alpha_function_name, 1);
2225 /* Write function epilogue. */
2228 output_epilog (file, size)
2232 unsigned long imask = 0;
2233 unsigned long fmask = 0;
2234 /* Stack space needed for pushing registers clobbered by us. */
2235 HOST_WIDE_INT sa_size = alpha_sa_size ();
2236 /* Complete stack size needed. */
2237 HOST_WIDE_INT frame_size
2238 = ALPHA_ROUND (sa_size
2239 + (is_stack_procedure ? 8 : 0)
2240 + size + current_function_pretend_args_size);
2242 rtx insn = get_last_insn ();
2244 /* If the last insn was a BARRIER, we don't have to write anything except
2245 the .end pseudo-op. */
2247 if (GET_CODE (insn) == NOTE)
2248 insn = prev_nonnote_insn (insn);
2250 if (insn == 0 || GET_CODE (insn) != BARRIER)
2252 /* Restore clobbered registers, load FP last. */
2254 if (is_stack_procedure)
2260 if (unwind_regno == HARD_FRAME_POINTER_REGNUM)
2261 fprintf (file, "\tbis $%d,$%d,$%d\n", HARD_FRAME_POINTER_REGNUM,
2262 HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM);
2264 alpha_sa_mask (&imask, &fmask);
2266 /* Start reloading registers after RA. */
2267 reg_offset = rsa_offset + 8;
2269 for (i = 0; i < 32; i++)
2270 if (imask & (1L<<i))
2272 if (i == HARD_FRAME_POINTER_REGNUM)
2273 fp_offset = reg_offset;
2275 fprintf (file, "\tldq $%d,%d($30)\n",
2280 for (i = 0; i < 32; i++)
2281 if (fmask & (1L << i))
2283 fprintf (file, "\tldt $f%d,%d($30)\n", i, reg_offset);
2287 /* Restore R26 (RA). */
2288 fprintf (file, "\tldq $26,%d($30)\n", rsa_offset);
2290 /* Restore R29 (FP). */
2291 fprintf (file, "\tldq $29,%d($30)\n", fp_offset);
2294 fprintf (file, "\tbis $%d,$%d,$%d\n", save_fp_regno, save_fp_regno,
2295 HARD_FRAME_POINTER_REGNUM);
2297 if (frame_size != 0)
2299 if (frame_size < 32768)
2300 fprintf (file, "\tlda $30,%d($30)\n", frame_size);
2303 long high = frame_size >> 16;
2304 long low = frame_size & 0xffff;
2308 low = -32768 + (low & 0x7fff);
2310 fprintf (file, "\tldah $2,%ld($31)\n", high);
2311 fprintf (file, "\tlda $2,%ld($2)\n", low);
2312 fprintf (file, "\taddq $30,$2,$30\n");
2316 /* Finally return to the caller. */
2317 fprintf (file, "\tret $31,($26),1\n");
2320 /* End the function. */
2321 fprintf (file, "\t.end ");
2322 assemble_name (file, alpha_function_name);
2323 fprintf (file, "\n");
2324 inside_function = FALSE;
2326 /* Show that we know this function if it is called again. */
2327 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
2330 #else /* !OPEN_VMS */
2333 alpha_does_function_need_gp ()
2337 /* We never need a GP for Windows/NT. */
2338 if (TARGET_WINDOWS_NT)
2341 #ifdef TARGET_PROFILING_NEEDS_GP
2346 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
2347 Even if we are a static function, we still need to do this in case
2348 our address is taken and passed to something like qsort. */
2350 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2351 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2352 && GET_CODE (PATTERN (insn)) != USE
2353 && GET_CODE (PATTERN (insn)) != CLOBBER)
2355 enum attr_type type = get_attr_type (insn);
2356 if (type == TYPE_LDSYM || type == TYPE_JSR)
2364 vms_valid_decl_attribute_p (decl, attributes, identifier, args)
2370 if (is_attribute_p ("overlaid", identifier))
2371 return (args == NULL_TREE);
2376 output_prolog (file, size)
2380 HOST_WIDE_INT out_args_size
2381 = ALPHA_ROUND (current_function_outgoing_args_size);
2382 HOST_WIDE_INT sa_size = alpha_sa_size ();
2383 HOST_WIDE_INT frame_size
2384 = (out_args_size + sa_size
2385 + ALPHA_ROUND (size + current_function_pretend_args_size));
2386 HOST_WIDE_INT reg_offset = out_args_size;
2387 HOST_WIDE_INT start_reg_offset = reg_offset;
2388 HOST_WIDE_INT actual_start_reg_offset = start_reg_offset;
2389 int int_reg_save_area_size = 0;
2390 unsigned reg_mask = 0;
2393 /* Ecoff can handle multiple .file directives, so put out file and lineno.
2394 We have to do that before the .ent directive as we cannot switch
2395 files within procedures with native ecoff because line numbers are
2396 linked to procedure descriptors.
2397 Outputting the lineno helps debugging of one line functions as they
2398 would otherwise get no line number at all. Please note that we would
2399 like to put out last_linenum from final.c, but it is not accessible. */
2401 if (write_symbols == SDB_DEBUG)
2403 ASM_OUTPUT_SOURCE_FILENAME (file,
2404 DECL_SOURCE_FILE (current_function_decl));
2405 if (debug_info_level != DINFO_LEVEL_TERSE)
2406 ASM_OUTPUT_SOURCE_LINE (file,
2407 DECL_SOURCE_LINE (current_function_decl));
2410 /* The assembly language programmer's guide states that the second argument
2411 to the .ent directive, the lex_level, is ignored by the assembler,
2412 so we might as well omit it. */
2414 if (!flag_inhibit_size_directive)
2416 fprintf (file, "\t.ent ");
2417 assemble_name (file, alpha_function_name);
2418 fprintf (file, "\n");
2420 ASM_OUTPUT_LABEL (file, alpha_function_name);
2421 inside_function = TRUE;
2423 if (TARGET_IEEE_CONFORMANT && !flag_inhibit_size_directive)
2424 /* Set flags in procedure descriptor to request IEEE-conformant
2425 math-library routines. The value we set it to is PDSC_EXC_IEEE
2426 (/usr/include/pdsc.h). */
2427 fprintf (file, "\t.eflag 48\n");
2429 /* Set up offsets to alpha virtual arg/local debugging pointer. */
2431 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
2432 alpha_arg_offset = -frame_size + 48;
2434 alpha_function_needs_gp = alpha_does_function_need_gp ();
2436 if (TARGET_WINDOWS_NT == 0)
2438 if (alpha_function_needs_gp)
2439 fprintf (file, "\tldgp $29,0($27)\n");
2441 /* Put a label after the GP load so we can enter the function at it. */
2443 assemble_name (file, alpha_function_name);
2444 fprintf (file, "..ng:\n");
2447 /* Adjust the stack by the frame size. If the frame size is > 4096
2448 bytes, we need to be sure we probe somewhere in the first and last
2449 4096 bytes (we can probably get away without the latter test) and
2450 every 8192 bytes in between. If the frame size is > 32768, we
2451 do this in a loop. Otherwise, we generate the explicit probe
2454 Note that we are only allowed to adjust sp once in the prologue. */
2456 if (frame_size < 32768)
2458 if (frame_size > 4096)
2462 fprintf (file, "\tstq $31,-%d($30)\n", probed);
2464 while (probed + 8192 < frame_size)
2465 fprintf (file, "\tstq $31,-%d($30)\n", probed += 8192);
2467 /* We only have to do this probe if we aren't saving registers. */
2468 if (sa_size == 0 && probed + 4096 < frame_size)
2469 fprintf (file, "\tstq $31,-%d($30)\n", frame_size);
2472 if (frame_size != 0)
2473 fprintf (file, "\tlda $30,-%d($30)\n", frame_size);
2477 /* Here we generate code to set R4 to SP + 4096 and set R5 to the
2478 number of 8192 byte blocks to probe. We then probe each block
2479 in the loop and then set SP to the proper location. If the
2480 amount remaining is > 4096, we have to do one more probe if we
2481 are not saving any registers. */
2483 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
2484 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
2486 add_long_const (file, blocks, 31, 5, 5);
2488 fprintf (file, "\tlda $4,4096($30)\n");
2491 assemble_name (file, alpha_function_name);
2492 fprintf (file, "..sc:\n");
2494 fprintf (file, "\tstq $31,-8192($4)\n");
2495 fprintf (file, "\tsubq $5,1,$5\n");
2496 fprintf (file, "\tlda $4,-8192($4)\n");
2498 fprintf (file, "\tbne $5,$");
2499 assemble_name (file, alpha_function_name);
2500 fprintf (file, "..sc\n");
2502 if (leftover > 4096 && sa_size == 0)
2503 fprintf (file, "\tstq $31,-%d($4)\n", leftover);
2505 fprintf (file, "\tlda $30,-%d($4)\n", leftover);
2508 /* Describe our frame. */
2509 if (!flag_inhibit_size_directive)
2511 fprintf (file, "\t.frame $%d,%d,$26,%d\n",
2512 (frame_pointer_needed
2513 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
2514 frame_size, current_function_pretend_args_size);
2517 /* Cope with very large offsets to the register save area. */
2519 if (reg_offset + sa_size > 0x8000)
2521 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
2522 if (low + sa_size <= 0x8000)
2524 add_long_const (file, reg_offset - low, 30, 24, 24);
2529 add_long_const (file, reg_offset, 30, 24, 24);
2535 /* Save register RA if any other register needs to be saved. */
2538 reg_mask |= 1 << REG_RA;
2539 fprintf (file, "\tstq $26,%d($%d)\n", reg_offset, sa_reg);
2541 int_reg_save_area_size += 8;
2544 /* Now save any other used integer registers required to be saved. */
2545 for (i = 0; i < 32; i++)
2546 if (! fixed_regs[i] && ! call_used_regs[i]
2547 && regs_ever_live[i] && i != REG_RA)
2550 fprintf (file, "\tstq $%d,%d($%d)\n", i, reg_offset, sa_reg);
2552 int_reg_save_area_size += 8;
2555 /* Print the register mask and do floating-point saves. */
2556 if (reg_mask && !flag_inhibit_size_directive)
2557 fprintf (file, "\t.mask 0x%x,%d\n", reg_mask,
2558 actual_start_reg_offset - frame_size);
2560 start_reg_offset = reg_offset;
2563 for (i = 0; i < 32; i++)
2564 if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
2565 && regs_ever_live[i + 32])
2568 fprintf (file, "\tstt $f%d,%d($%d)\n", i, reg_offset, sa_reg);
2572 /* Print the floating-point mask, if we've saved any fp register. */
2573 if (reg_mask && !flag_inhibit_size_directive)
2574 fprintf (file, "\t.fmask 0x%x,%d\n", reg_mask,
2575 actual_start_reg_offset - frame_size + int_reg_save_area_size);
2577 /* If we need a frame pointer, set it from the stack pointer. Note that
2578 this must always be the last instruction in the prologue. */
2579 if (frame_pointer_needed)
2580 fprintf (file, "\tbis $30,$30,$15\n");
2582 /* End the prologue and say if we used gp. */
2583 if (!flag_inhibit_size_directive)
2584 fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp);
2587 /* Write function epilogue. */
2590 output_epilog (file, size)
2594 rtx insn = get_last_insn ();
2595 HOST_WIDE_INT out_args_size
2596 = ALPHA_ROUND (current_function_outgoing_args_size);
2597 HOST_WIDE_INT sa_size = alpha_sa_size ();
2598 HOST_WIDE_INT frame_size
2599 = (out_args_size + sa_size
2600 + ALPHA_ROUND (size + current_function_pretend_args_size));
2601 HOST_WIDE_INT reg_offset = out_args_size;
2602 HOST_WIDE_INT frame_size_from_reg_save = frame_size - reg_offset;
2604 = frame_pointer_needed && regs_ever_live[HARD_FRAME_POINTER_REGNUM];
2607 /* If the last insn was a BARRIER, we don't have to write anything except
2608 the .end pseudo-op. */
2609 if (GET_CODE (insn) == NOTE)
2610 insn = prev_nonnote_insn (insn);
2611 if (insn == 0 || GET_CODE (insn) != BARRIER)
2616 /* If we have a frame pointer, restore SP from it. */
2617 if (frame_pointer_needed)
2618 fprintf (file, "\tbis $15,$15,$30\n");
2620 /* Cope with large offsets to the register save area. */
2622 if (reg_offset + sa_size > 0x8000)
2624 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
2625 if (low + sa_size <= 0x8000)
2627 add_long_const (file, reg_offset - low, 30, 24, 24);
2632 add_long_const (file, reg_offset, 30, 24, 24);
2638 /* Restore all the registers, starting with the return address
2642 fprintf (file, "\tldq $26,%d($%d)\n", reg_offset, sa_reg);
2646 /* Now restore any other used integer registers that that we saved,
2647 except for FP if it is being used as FP, since it must be
2650 for (i = 0; i < 32; i++)
2651 if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i]
2654 if (i == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
2655 fp_offset = reg_offset;
2657 fprintf (file, "\tldq $%d,%d($%d)\n", i, reg_offset, sa_reg);
2661 for (i = 0; i < 32; i++)
2662 if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
2663 && regs_ever_live[i + 32])
2665 fprintf (file, "\tldt $f%d,%d($%d)\n", i, reg_offset, sa_reg);
2669 /* If the stack size is large and we have a frame pointer, compute the
2670 size of the stack into a register because the old FP restore, stack
2671 pointer adjust, and return are required to be consecutive
2673 if (frame_size > 32767 && restore_fp)
2674 add_long_const (file, frame_size, 31, 1, 1);
2676 /* If we needed a frame pointer and we have to restore it, do it
2677 now. This must be done in one instruction immediately
2678 before the SP update. */
2679 if (restore_fp && fp_offset)
2680 fprintf (file, "\tldq $15,%d($%d)\n", fp_offset, sa_reg);
2682 /* Now update the stack pointer, if needed. Only one instruction must
2683 modify the stack pointer. It must be the last instruction in the
2684 sequence and must be an ADDQ or LDA instruction. If the frame
2685 pointer was loaded above, we may only put one instruction here. */
2687 if (frame_size > 32768 && restore_fp)
2688 fprintf (file, "\taddq $1,$30,$30\n");
2690 add_long_const (file, frame_size, 30, 30, 1);
2692 /* Finally return to the caller. */
2693 fprintf (file, "\tret $31,($26),1\n");
2696 /* End the function. */
2697 if (!flag_inhibit_size_directive)
2699 fprintf (file, "\t.end ");
2700 assemble_name (file, alpha_function_name);
2701 fprintf (file, "\n");
2703 inside_function = FALSE;
2705 /* Show that we know this function if it is called again. */
2706 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
2708 #endif /* !OPEN_VMS */
2710 /* Debugging support. */
2714 /* Count the number of sdb related labels are generated (to find block
2715 start and end boundaries). */
2717 int sdb_label_count = 0;
2719 /* Next label # for each statement. */
2721 static int sym_lineno = 0;
2723 /* Count the number of .file directives, so that .loc is up to date. */
2725 static int num_source_filenames = 0;
2727 /* Name of the file containing the current function. */
2729 static char *current_function_file = "";
2731 /* Offsets to alpha virtual arg/local debugging pointers. */
2733 long alpha_arg_offset;
2734 long alpha_auto_offset;
2736 /* Emit a new filename to a stream. */
2739 alpha_output_filename (stream, name)
2743 static int first_time = TRUE;
2744 char ltext_label_name[100];
2749 ++num_source_filenames;
2750 current_function_file = name;
2751 fprintf (stream, "\t.file\t%d ", num_source_filenames);
2752 output_quoted_string (stream, name);
2753 fprintf (stream, "\n");
2754 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
2755 fprintf (stream, "\t#@stabs\n");
2758 else if (write_symbols == DBX_DEBUG)
2760 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
2761 fprintf (stream, "%s ", ASM_STABS_OP);
2762 output_quoted_string (stream, name);
2763 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
2766 else if (name != current_function_file
2767 && strcmp (name, current_function_file) != 0)
2769 if (inside_function && ! TARGET_GAS)
2770 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
2773 ++num_source_filenames;
2774 current_function_file = name;
2775 fprintf (stream, "\t.file\t%d ", num_source_filenames);
2778 output_quoted_string (stream, name);
2779 fprintf (stream, "\n");
2783 /* Emit a linenumber to a stream. */
2786 alpha_output_lineno (stream, line)
2790 if (write_symbols == DBX_DEBUG)
2792 /* mips-tfile doesn't understand .stabd directives. */
2794 fprintf (stream, "$LM%d:\n\t%s %d,0,%d,$LM%d\n",
2795 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
2798 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
2801 /* Structure to show the current status of registers and memory. */
2803 struct shadow_summary
2806 unsigned long i : 31; /* Mask of int regs */
2807 unsigned long fp : 31; /* Mask of fp regs */
2808 unsigned long mem : 1; /* mem == imem | fpmem */
2812 /* Summary the effects of expression X on the machine. Update SUM, a pointer
2813 to the summary structure. SET is nonzero if the insn is setting the
2814 object, otherwise zero. */
2817 summarize_insn (x, sum, set)
2819 struct shadow_summary *sum;
2828 switch (GET_CODE (x))
2830 /* ??? Note that this case would be incorrect if the Alpha had a
2831 ZERO_EXTRACT in SET_DEST. */
2833 summarize_insn (SET_SRC (x), sum, 0);
2834 summarize_insn (SET_DEST (x), sum, 1);
2838 summarize_insn (XEXP (x, 0), sum, 1);
2842 summarize_insn (XEXP (x, 0), sum, 0);
2846 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
2847 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
2851 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2852 summarize_insn (XVECEXP (x, 0, i), sum, 0);
2861 int regno = REGNO (x);
2862 unsigned long mask = 1UL << (regno % 32);
2864 if (regno == 31 || regno == 63)
2870 sum->defd.i |= mask;
2872 sum->defd.fp |= mask;
2877 sum->used.i |= mask;
2879 sum->used.fp |= mask;
2890 /* Find the regs used in memory address computation: */
2891 summarize_insn (XEXP (x, 0), sum, 0);
2894 case CONST_INT: case CONST_DOUBLE:
2895 case SYMBOL_REF: case LABEL_REF: case CONST:
2898 /* Handle common unary and binary ops for efficiency. */
2899 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
2900 case MOD: case UDIV: case UMOD: case AND: case IOR:
2901 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
2902 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
2903 case NE: case EQ: case GE: case GT: case LE:
2904 case LT: case GEU: case GTU: case LEU: case LTU:
2905 summarize_insn (XEXP (x, 0), sum, 0);
2906 summarize_insn (XEXP (x, 1), sum, 0);
2909 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
2910 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
2911 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
2912 case SQRT: case FFS:
2913 summarize_insn (XEXP (x, 0), sum, 0);
2917 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
2918 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
2919 switch (format_ptr[i])
2922 summarize_insn (XEXP (x, i), sum, 0);
2926 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2927 summarize_insn (XVECEXP (x, i, j), sum, 0);
2936 /* Ensure a sufficient number of `trapb' insns are in the code when the user
2937 requests code with a trap precision of functions or instructions.
2939 In naive mode, when the user requests a trap-precision of "instruction", a
2940 trapb is needed after every instruction that may generate a trap (and after
2941 jsr/bsr instructions, because called functions may import a trap from the
2942 caller). This ensures that the code is resumption safe but it is also slow.
2944 When optimizations are turned on, we delay issuing a trapb as long as
2945 possible. In this context, a trap shadow is the sequence of instructions
2946 that starts with a (potentially) trap generating instruction and extends to
2947 the next trapb or call_pal instruction (but GCC never generates call_pal by
2948 itself). We can delay (and therefore sometimes omit) a trapb subject to the
2949 following conditions:
2951 (a) On entry to the trap shadow, if any Alpha register or memory location
2952 contains a value that is used as an operand value by some instruction in
2953 the trap shadow (live on entry), then no instruction in the trap shadow
2954 may modify the register or memory location.
2956 (b) Within the trap shadow, the computation of the base register for a
2957 memory load or store instruction may not involve using the result
2958 of an instruction that might generate an UNPREDICTABLE result.
2960 (c) Within the trap shadow, no register may be used more than once as a
2961 destination register. (This is to make life easier for the trap-handler.)
2963 (d) The trap shadow may not include any branch instructions. */
2966 alpha_handle_trap_shadows (insns)
2969 struct shadow_summary shadow;
2970 int trap_pending, exception_nesting;
2973 if (alpha_tp == ALPHA_TP_PROG && !flag_exceptions)
2977 exception_nesting = 0;
2980 shadow.used.mem = 0;
2981 shadow.defd = shadow.used;
2983 for (i = insns; i ; i = NEXT_INSN (i))
2985 if (GET_CODE (i) == NOTE)
2987 switch (NOTE_LINE_NUMBER (i))
2989 case NOTE_INSN_EH_REGION_BEG:
2990 exception_nesting++;
2995 case NOTE_INSN_EH_REGION_END:
2996 exception_nesting--;
3001 case NOTE_INSN_EPILOGUE_BEG:
3002 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
3007 else if (trap_pending)
3009 if (alpha_tp == ALPHA_TP_FUNC)
3011 if (GET_CODE (i) == JUMP_INSN
3012 && GET_CODE (PATTERN (i)) == RETURN)
3015 else if (alpha_tp == ALPHA_TP_INSN)
3019 struct shadow_summary sum;
3024 sum.defd = sum.used;
3026 switch (GET_CODE (i))
3029 /* Annoyingly, get_attr_trap will abort on USE. */
3030 if (GET_CODE (PATTERN (i)) == USE)
3033 summarize_insn (PATTERN (i), &sum, 0);
3035 if ((sum.defd.i & shadow.defd.i)
3036 || (sum.defd.fp & shadow.defd.fp))
3038 /* (c) would be violated */
3042 /* Combine shadow with summary of current insn: */
3043 shadow.used.i |= sum.used.i;
3044 shadow.used.fp |= sum.used.fp;
3045 shadow.used.mem |= sum.used.mem;
3046 shadow.defd.i |= sum.defd.i;
3047 shadow.defd.fp |= sum.defd.fp;
3048 shadow.defd.mem |= sum.defd.mem;
3050 if ((sum.defd.i & shadow.used.i)
3051 || (sum.defd.fp & shadow.used.fp)
3052 || (sum.defd.mem & shadow.used.mem))
3054 /* (a) would be violated (also takes care of (b)) */
3055 if (get_attr_trap (i) == TRAP_YES
3056 && ((sum.defd.i & sum.used.i)
3057 || (sum.defd.fp & sum.used.fp)))
3076 emit_insn_before (gen_trapb (), i);
3080 shadow.used.mem = 0;
3081 shadow.defd = shadow.used;
3086 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
3087 && GET_CODE (i) == INSN
3088 && GET_CODE (PATTERN (i)) != USE
3089 && GET_CODE (PATTERN (i)) != CLOBBER
3090 && get_attr_trap (i) == TRAP_YES)
3092 if (optimize && !trap_pending)
3093 summarize_insn (PATTERN (i), &shadow, 0);
3099 /* Machine dependant reorg pass. */
3105 alpha_handle_trap_shadows (insns);
3109 /* Check a floating-point value for validity for a particular machine mode. */
3111 static char *float_strings[] =
3113 /* These are for FLOAT_VAX. */
3114 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
3115 "-1.70141173319264430e+38",
3116 "2.93873587705571877e-39", /* 2^-128 */
3117 "-2.93873587705571877e-39",
3118 /* These are for the default broken IEEE mode, which traps
3119 on infinity or denormal numbers. */
3120 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
3121 "-3.402823466385288598117e+38",
3122 "1.1754943508222875079687e-38", /* 2^-126 */
3123 "-1.1754943508222875079687e-38",
3126 static REAL_VALUE_TYPE float_values[8];
3127 static int inited_float_values = 0;
3130 check_float_value (mode, d, overflow)
3131 enum machine_mode mode;
3136 if (TARGET_IEEE || TARGET_IEEE_CONFORMANT || TARGET_IEEE_WITH_INEXACT)
3139 if (inited_float_values == 0)
3142 for (i = 0; i < 8; i++)
3143 float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
3145 inited_float_values = 1;
3151 REAL_VALUE_TYPE *fvptr;
3153 if (TARGET_FLOAT_VAX)
3154 fvptr = &float_values[0];
3156 fvptr = &float_values[4];
3158 bcopy ((char *) d, (char *) &r, sizeof (REAL_VALUE_TYPE));
3159 if (REAL_VALUES_LESS (fvptr[0], r))
3161 bcopy ((char *) &fvptr[0], (char *) d,
3162 sizeof (REAL_VALUE_TYPE));
3165 else if (REAL_VALUES_LESS (r, fvptr[1]))
3167 bcopy ((char *) &fvptr[1], (char *) d,
3168 sizeof (REAL_VALUE_TYPE));
3171 else if (REAL_VALUES_LESS (dconst0, r)
3172 && REAL_VALUES_LESS (r, fvptr[2]))
3174 bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
3177 else if (REAL_VALUES_LESS (r, dconst0)
3178 && REAL_VALUES_LESS (fvptr[3], r))
3180 bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
3190 /* Return the VMS argument type corresponding to MODE. */
3193 alpha_arg_type (mode)
3194 enum machine_mode mode;
3199 return TARGET_FLOAT_VAX ? FF : FS;
3201 return TARGET_FLOAT_VAX ? FD : FT;
3207 /* Return an rtx for an integer representing the VMS Argument Information
3211 alpha_arg_info_reg_val (cum)
3212 CUMULATIVE_ARGS cum;
3214 unsigned HOST_WIDE_INT regval = cum.num_args;
3217 for (i = 0; i < 6; i++)
3218 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
3220 return GEN_INT (regval);
3223 /* Structure to collect function names for final output
3226 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
3229 struct alpha_links {
3230 struct alpha_links *next;
3232 enum links_kind kind;
3235 static struct alpha_links *alpha_links_base = 0;
3237 /* Make (or fake) .linkage entry for function call.
3239 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
3242 alpha_need_linkage (name, is_local)
3247 struct alpha_links *lptr, *nptr;
3252 /* Is this name already defined ? */
3254 for (lptr = alpha_links_base; lptr; lptr = lptr->next)
3255 if (strcmp (lptr->name, name) == 0)
3259 /* Defined here but external assumed. */
3260 if (lptr->kind == KIND_EXTERN)
3261 lptr->kind = KIND_LOCAL;
3265 /* Used here but unused assumed. */
3266 if (lptr->kind == KIND_UNUSED)
3267 lptr->kind = KIND_LOCAL;
3272 nptr = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
3273 nptr->next = alpha_links_base;
3274 nptr->name = xstrdup (name);
3276 /* Assume external if no definition. */
3277 nptr->kind = (is_local ? KIND_UNUSED : KIND_EXTERN);
3279 /* Ensure we have an IDENTIFIER so assemble_name can mark is used. */
3280 get_identifier (name);
3282 alpha_links_base = nptr;
3289 alpha_write_linkage (stream)
3292 struct alpha_links *lptr, *nptr;
3294 readonly_section ();
3296 fprintf (stream, "\t.align 3\n");
3298 for (lptr = alpha_links_base; lptr; lptr = nptr)
3302 if (lptr->kind == KIND_UNUSED
3303 || ! TREE_SYMBOL_REFERENCED (get_identifier (lptr->name)))
3306 fprintf (stream, "$%s..lk:\n", lptr->name);
3307 if (lptr->kind == KIND_LOCAL)
3309 /* Local and used, build linkage pair. */
3310 fprintf (stream, "\t.quad $%s..en\n", lptr->name);
3311 fprintf (stream, "\t.quad %s\n", lptr->name);
3314 /* External and used, request linkage pair. */
3315 fprintf (stream, "\t.linkage %s\n", lptr->name);
3322 alpha_need_linkage (name, is_local)
3328 #endif /* OPEN_VMS */