1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
57 /* Specify which cpu to schedule for. */
59 enum processor_type alpha_cpu;
60 static const char * const alpha_cpu_name[] =
65 /* Specify how accurate floating-point traps need to be. */
67 enum alpha_trap_precision alpha_tp;
69 /* Specify the floating-point rounding mode. */
71 enum alpha_fp_rounding_mode alpha_fprm;
73 /* Specify which things cause traps. */
75 enum alpha_fp_trap_mode alpha_fptm;
77 /* Specify bit size of immediate TLS offsets. */
79 int alpha_tls_size = 32;
81 /* Strings decoded into the above options. */
83 const char *alpha_cpu_string; /* -mcpu= */
84 const char *alpha_tune_string; /* -mtune= */
85 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
86 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
87 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
88 const char *alpha_mlat_string; /* -mmemory-latency= */
89 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
91 /* Save information from a "cmpxx" operation until the branch or scc is
94 struct alpha_compare alpha_compare;
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
99 static int inside_function = FALSE;
101 /* The number of cycles of latency we should assume on memory reads. */
103 int alpha_memory_latency = 3;
105 /* Whether the function needs the GP. */
107 static int alpha_function_needs_gp;
109 /* The alias set for prologue/epilogue register save/restore. */
111 static GTY(()) int alpha_sr_alias_set;
113 /* The assembler name of the current function. */
115 static const char *alpha_fnname;
117 /* The next explicit relocation sequence number. */
118 extern GTY(()) int alpha_next_sequence_number;
119 int alpha_next_sequence_number = 1;
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
123 extern GTY(()) int alpha_this_literal_sequence_number;
124 extern GTY(()) int alpha_this_gpdisp_sequence_number;
125 int alpha_this_literal_sequence_number;
126 int alpha_this_gpdisp_sequence_number;
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
132 unsigned char fp_add;
133 unsigned char fp_mult;
134 unsigned char fp_div_sf;
135 unsigned char fp_div_df;
136 unsigned char int_mult_si;
137 unsigned char int_mult_di;
138 unsigned char int_shift;
139 unsigned char int_cmov;
142 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
145 COSTS_N_INSNS (6), /* fp_add */
146 COSTS_N_INSNS (6), /* fp_mult */
147 COSTS_N_INSNS (34), /* fp_div_sf */
148 COSTS_N_INSNS (63), /* fp_div_df */
149 COSTS_N_INSNS (23), /* int_mult_si */
150 COSTS_N_INSNS (23), /* int_mult_di */
151 COSTS_N_INSNS (2), /* int_shift */
152 COSTS_N_INSNS (2), /* int_cmov */
155 COSTS_N_INSNS (4), /* fp_add */
156 COSTS_N_INSNS (4), /* fp_mult */
157 COSTS_N_INSNS (15), /* fp_div_sf */
158 COSTS_N_INSNS (22), /* fp_div_df */
159 COSTS_N_INSNS (8), /* int_mult_si */
160 COSTS_N_INSNS (12), /* int_mult_di */
161 COSTS_N_INSNS (1) + 1, /* int_shift */
162 COSTS_N_INSNS (1), /* int_cmov */
165 COSTS_N_INSNS (4), /* fp_add */
166 COSTS_N_INSNS (4), /* fp_mult */
167 COSTS_N_INSNS (12), /* fp_div_sf */
168 COSTS_N_INSNS (15), /* fp_div_df */
169 COSTS_N_INSNS (7), /* int_mult_si */
170 COSTS_N_INSNS (7), /* int_mult_di */
171 COSTS_N_INSNS (1), /* int_shift */
172 COSTS_N_INSNS (2), /* int_cmov */
176 /* Get the number of args of a function in one of two ways. */
177 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
178 #define NUM_ARGS current_function_args_info.num_args
180 #define NUM_ARGS current_function_args_info
186 /* Declarations of static functions. */
187 static struct machine_function *alpha_init_machine_status (void);
188 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
190 #if TARGET_ABI_OPEN_VMS
191 static void alpha_write_linkage (FILE *, const char *, tree);
194 static void unicosmk_output_deferred_case_vectors (FILE *);
195 static void unicosmk_gen_dsib (unsigned long *);
196 static void unicosmk_output_ssib (FILE *, const char *);
197 static int unicosmk_need_dex (rtx);
199 /* Parse target option strings. */
202 override_options (void)
205 static const struct cpu_table {
206 const char *const name;
207 const enum processor_type processor;
210 #define EV5_MASK (MASK_CPU_EV5)
211 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
212 { "ev4", PROCESSOR_EV4, 0 },
213 { "ev45", PROCESSOR_EV4, 0 },
214 { "21064", PROCESSOR_EV4, 0 },
215 { "ev5", PROCESSOR_EV5, EV5_MASK },
216 { "21164", PROCESSOR_EV5, EV5_MASK },
217 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
218 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
219 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
220 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
221 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
222 { "ev6", PROCESSOR_EV6, EV6_MASK },
223 { "21264", PROCESSOR_EV6, EV6_MASK },
224 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
225 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
229 /* Unicos/Mk doesn't have shared libraries. */
230 if (TARGET_ABI_UNICOSMK && flag_pic)
232 warning ("-f%s ignored for Unicos/Mk (not supported)",
233 (flag_pic > 1) ? "PIC" : "pic");
237 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
238 floating-point instructions. Make that the default for this target. */
239 if (TARGET_ABI_UNICOSMK)
240 alpha_fprm = ALPHA_FPRM_DYN;
242 alpha_fprm = ALPHA_FPRM_NORM;
244 alpha_tp = ALPHA_TP_PROG;
245 alpha_fptm = ALPHA_FPTM_N;
247 /* We cannot use su and sui qualifiers for conversion instructions on
248 Unicos/Mk. I'm not sure if this is due to assembler or hardware
249 limitations. Right now, we issue a warning if -mieee is specified
250 and then ignore it; eventually, we should either get it right or
251 disable the option altogether. */
255 if (TARGET_ABI_UNICOSMK)
256 warning ("-mieee not supported on Unicos/Mk");
259 alpha_tp = ALPHA_TP_INSN;
260 alpha_fptm = ALPHA_FPTM_SU;
264 if (TARGET_IEEE_WITH_INEXACT)
266 if (TARGET_ABI_UNICOSMK)
267 warning ("-mieee-with-inexact not supported on Unicos/Mk");
270 alpha_tp = ALPHA_TP_INSN;
271 alpha_fptm = ALPHA_FPTM_SUI;
277 if (! strcmp (alpha_tp_string, "p"))
278 alpha_tp = ALPHA_TP_PROG;
279 else if (! strcmp (alpha_tp_string, "f"))
280 alpha_tp = ALPHA_TP_FUNC;
281 else if (! strcmp (alpha_tp_string, "i"))
282 alpha_tp = ALPHA_TP_INSN;
284 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
287 if (alpha_fprm_string)
289 if (! strcmp (alpha_fprm_string, "n"))
290 alpha_fprm = ALPHA_FPRM_NORM;
291 else if (! strcmp (alpha_fprm_string, "m"))
292 alpha_fprm = ALPHA_FPRM_MINF;
293 else if (! strcmp (alpha_fprm_string, "c"))
294 alpha_fprm = ALPHA_FPRM_CHOP;
295 else if (! strcmp (alpha_fprm_string,"d"))
296 alpha_fprm = ALPHA_FPRM_DYN;
298 error ("bad value `%s' for -mfp-rounding-mode switch",
302 if (alpha_fptm_string)
304 if (strcmp (alpha_fptm_string, "n") == 0)
305 alpha_fptm = ALPHA_FPTM_N;
306 else if (strcmp (alpha_fptm_string, "u") == 0)
307 alpha_fptm = ALPHA_FPTM_U;
308 else if (strcmp (alpha_fptm_string, "su") == 0)
309 alpha_fptm = ALPHA_FPTM_SU;
310 else if (strcmp (alpha_fptm_string, "sui") == 0)
311 alpha_fptm = ALPHA_FPTM_SUI;
313 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
316 if (alpha_tls_size_string)
318 if (strcmp (alpha_tls_size_string, "16") == 0)
320 else if (strcmp (alpha_tls_size_string, "32") == 0)
322 else if (strcmp (alpha_tls_size_string, "64") == 0)
325 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
329 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
330 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
332 if (alpha_cpu_string)
334 for (i = 0; cpu_table [i].name; i++)
335 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
337 alpha_cpu = cpu_table [i].processor;
338 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
339 | MASK_CPU_EV5 | MASK_CPU_EV6);
340 target_flags |= cpu_table [i].flags;
343 if (! cpu_table [i].name)
344 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
347 if (alpha_tune_string)
349 for (i = 0; cpu_table [i].name; i++)
350 if (! strcmp (alpha_tune_string, cpu_table [i].name))
352 alpha_cpu = cpu_table [i].processor;
355 if (! cpu_table [i].name)
356 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
359 /* Do some sanity checks on the above options. */
361 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
363 warning ("trap mode not supported on Unicos/Mk");
364 alpha_fptm = ALPHA_FPTM_N;
367 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
368 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
370 warning ("fp software completion requires -mtrap-precision=i");
371 alpha_tp = ALPHA_TP_INSN;
376 /* Except for EV6 pass 1 (not released), we always have precise
377 arithmetic traps. Which means we can do software completion
378 without minding trap shadows. */
379 alpha_tp = ALPHA_TP_PROG;
382 if (TARGET_FLOAT_VAX)
384 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
386 warning ("rounding mode not supported for VAX floats");
387 alpha_fprm = ALPHA_FPRM_NORM;
389 if (alpha_fptm == ALPHA_FPTM_SUI)
391 warning ("trap mode not supported for VAX floats");
392 alpha_fptm = ALPHA_FPTM_SU;
394 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
395 warning ("128-bit long double not supported for VAX floats");
396 target_flags &= ~MASK_LONG_DOUBLE_128;
403 if (!alpha_mlat_string)
404 alpha_mlat_string = "L1";
406 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
407 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
409 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
410 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
411 && alpha_mlat_string[2] == '\0')
413 static int const cache_latency[][4] =
415 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
416 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
417 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
420 lat = alpha_mlat_string[1] - '0';
421 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
423 warning ("L%d cache latency unknown for %s",
424 lat, alpha_cpu_name[alpha_cpu]);
428 lat = cache_latency[alpha_cpu][lat-1];
430 else if (! strcmp (alpha_mlat_string, "main"))
432 /* Most current memories have about 370ns latency. This is
433 a reasonable guess for a fast cpu. */
438 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
442 alpha_memory_latency = lat;
445 /* Default the definition of "small data" to 8 bytes. */
449 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
451 target_flags |= MASK_SMALL_DATA;
452 else if (flag_pic == 2)
453 target_flags &= ~MASK_SMALL_DATA;
455 /* Align labels and loops for optimal branching. */
456 /* ??? Kludge these by not doing anything if we don't optimize and also if
457 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
458 if (optimize > 0 && write_symbols != SDB_DEBUG)
460 if (align_loops <= 0)
462 if (align_jumps <= 0)
465 if (align_functions <= 0)
466 align_functions = 16;
468 /* Acquire a unique set number for our register saves and restores. */
469 alpha_sr_alias_set = new_alias_set ();
471 /* Register variables and functions with the garbage collector. */
473 /* Set up function hooks. */
474 init_machine_status = alpha_init_machine_status;
476 /* Tell the compiler when we're using VAX floating point. */
477 if (TARGET_FLOAT_VAX)
479 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
480 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
481 REAL_MODE_FORMAT (TFmode) = NULL;
485 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
488 zap_mask (HOST_WIDE_INT value)
492 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
494 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
500 /* Returns 1 if OP is either the constant zero or a register. If a
501 register, it must be in the proper mode unless MODE is VOIDmode. */
504 reg_or_0_operand (rtx op, enum machine_mode mode)
506 return op == CONST0_RTX (mode) || register_operand (op, mode);
509 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
513 reg_or_6bit_operand (rtx op, enum machine_mode mode)
515 return ((GET_CODE (op) == CONST_INT
516 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
517 || register_operand (op, mode));
521 /* Return 1 if OP is an 8-bit constant or any register. */
524 reg_or_8bit_operand (rtx op, enum machine_mode mode)
526 return ((GET_CODE (op) == CONST_INT
527 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
528 || register_operand (op, mode));
531 /* Return 1 if OP is a constant or any register. */
534 reg_or_const_int_operand (rtx op, enum machine_mode mode)
536 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
539 /* Return 1 if OP is an 8-bit constant. */
542 cint8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
544 return ((GET_CODE (op) == CONST_INT
545 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
548 /* Return 1 if the operand is a valid second operand to an add insn. */
551 add_operand (rtx op, enum machine_mode mode)
553 if (GET_CODE (op) == CONST_INT)
554 /* Constraints I, J, O and P are covered by K. */
555 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
556 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
558 return register_operand (op, mode);
561 /* Return 1 if the operand is a valid second operand to a sign-extending
565 sext_add_operand (rtx op, enum machine_mode mode)
567 if (GET_CODE (op) == CONST_INT)
568 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
569 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
571 return reg_not_elim_operand (op, mode);
574 /* Return 1 if OP is the constant 4 or 8. */
577 const48_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
579 return (GET_CODE (op) == CONST_INT
580 && (INTVAL (op) == 4 || INTVAL (op) == 8));
583 /* Return 1 if OP is a valid first operand to an AND insn. */
586 and_operand (rtx op, enum machine_mode mode)
588 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
589 return (zap_mask (CONST_DOUBLE_LOW (op))
590 && zap_mask (CONST_DOUBLE_HIGH (op)));
592 if (GET_CODE (op) == CONST_INT)
593 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
594 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
595 || zap_mask (INTVAL (op)));
597 return register_operand (op, mode);
600 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
603 or_operand (rtx op, enum machine_mode mode)
605 if (GET_CODE (op) == CONST_INT)
606 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
607 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
609 return register_operand (op, mode);
612 /* Return 1 if OP is a constant that is the width, in bits, of an integral
613 mode smaller than DImode. */
616 mode_width_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
618 return (GET_CODE (op) == CONST_INT
619 && (INTVAL (op) == 8 || INTVAL (op) == 16
620 || INTVAL (op) == 32 || INTVAL (op) == 64));
623 /* Return 1 if OP is a constant that is the width of an integral machine mode
624 smaller than an integer. */
627 mode_mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
629 if (GET_CODE (op) == CONST_INT)
631 HOST_WIDE_INT value = INTVAL (op);
637 if (value == 0xffffffff)
642 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
644 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
651 /* Return 1 if OP is a multiple of 8 less than 64. */
654 mul8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
656 return (GET_CODE (op) == CONST_INT
657 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
658 && (INTVAL (op) & 7) == 0);
661 /* Return 1 if OP is the zero constant for MODE. */
664 const0_operand (rtx op, enum machine_mode mode)
666 return op == CONST0_RTX (mode);
669 /* Return 1 if OP is a hard floating-point register. */
672 hard_fp_register_operand (rtx op, enum machine_mode mode)
674 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
677 if (GET_CODE (op) == SUBREG)
678 op = SUBREG_REG (op);
679 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
682 /* Return 1 if OP is a hard general register. */
685 hard_int_register_operand (rtx op, enum machine_mode mode)
687 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
690 if (GET_CODE (op) == SUBREG)
691 op = SUBREG_REG (op);
692 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
695 /* Return 1 if OP is a register or a constant integer. */
699 reg_or_cint_operand (rtx op, enum machine_mode mode)
701 return (GET_CODE (op) == CONST_INT
702 || register_operand (op, mode));
705 /* Return 1 if OP is something that can be reloaded into a register;
706 if it is a MEM, it need not be valid. */
709 some_operand (rtx op, enum machine_mode mode)
711 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
714 switch (GET_CODE (op))
728 return some_operand (SUBREG_REG (op), VOIDmode);
737 /* Likewise, but don't accept constants. */
740 some_ni_operand (rtx op, enum machine_mode mode)
742 if (GET_MODE (op) != mode && mode != VOIDmode)
745 if (GET_CODE (op) == SUBREG)
746 op = SUBREG_REG (op);
748 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
751 /* Return 1 if OP is a valid operand for the source of a move insn. */
754 input_operand (rtx op, enum machine_mode mode)
756 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
759 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
762 switch (GET_CODE (op))
767 if (TARGET_EXPLICIT_RELOCS)
769 /* We don't split symbolic operands into something unintelligable
770 until after reload, but we do not wish non-small, non-global
771 symbolic operands to be reconstructed from their high/lo_sum
773 return (small_symbolic_operand (op, mode)
774 || global_symbolic_operand (op, mode)
775 || gotdtp_symbolic_operand (op, mode)
776 || gottp_symbolic_operand (op, mode));
779 /* This handles both the Windows/NT and OSF cases. */
780 return mode == ptr_mode || mode == DImode;
783 return (TARGET_EXPLICIT_RELOCS
784 && local_symbolic_operand (XEXP (op, 0), mode));
791 if (register_operand (op, mode))
793 /* ... fall through ... */
795 return ((TARGET_BWX || (mode != HImode && mode != QImode))
796 && general_operand (op, mode));
800 return op == CONST0_RTX (mode);
803 return mode == QImode || mode == HImode || add_operand (op, mode);
812 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
813 file, and in the same section as the current function. */
816 samegp_function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
818 if (GET_CODE (op) != SYMBOL_REF)
821 /* Easy test for recursion. */
822 if (op == XEXP (DECL_RTL (current_function_decl), 0))
825 /* Functions that are not local can be overridden, and thus may
826 not share the same gp. */
827 if (! SYMBOL_REF_LOCAL_P (op))
830 /* If -msmall-data is in effect, assume that there is only one GP
831 for the module, and so any local symbol has this property. We
832 need explicit relocations to be able to enforce this for symbols
833 not defined in this unit of translation, however. */
834 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
837 /* Functions that are not external are defined in this UoT,
838 and thus must share the same gp. */
839 return ! SYMBOL_REF_EXTERNAL_P (op);
842 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
845 direct_call_operand (rtx op, enum machine_mode mode)
847 tree op_decl, cfun_sec, op_sec;
849 /* Must share the same GP. */
850 if (!samegp_function_operand (op, mode))
853 /* If profiling is implemented via linker tricks, we can't jump
854 to the nogp alternate entry point. Note that current_function_profile
855 would not be correct, since that doesn't indicate if the target
856 function uses profiling. */
857 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
858 but is approximately correct for the OSF ABIs. Don't know
859 what to do for VMS, NT, or UMK. */
860 if (!TARGET_PROFILING_NEEDS_GP && profile_flag)
863 /* Must be a function. In some cases folks create thunks in static
864 data structures and then make calls to them. If we allow the
865 direct call, we'll get an error from the linker about !samegp reloc
866 against a symbol without a .prologue directive. */
867 if (!SYMBOL_REF_FUNCTION_P (op))
870 /* Must be "near" so that the branch is assumed to reach. With
871 -msmall-text, this is assumed true of all local symbols. Since
872 we've already checked samegp, locality is already assured. */
873 if (TARGET_SMALL_TEXT)
876 /* Otherwise, a decl is "near" if it is defined in the same section. */
877 if (flag_function_sections)
880 op_decl = SYMBOL_REF_DECL (op);
881 if (DECL_ONE_ONLY (current_function_decl)
882 || (op_decl && DECL_ONE_ONLY (op_decl)))
885 cfun_sec = DECL_SECTION_NAME (current_function_decl);
886 op_sec = op_decl ? DECL_SECTION_NAME (op_decl) : NULL;
887 return ((!cfun_sec && !op_sec)
888 || (cfun_sec && op_sec
889 && strcmp (TREE_STRING_POINTER (cfun_sec),
890 TREE_STRING_POINTER (op_sec)) == 0));
893 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
894 a (non-tls) variable known to be defined in this file. */
897 local_symbolic_operand (rtx op, enum machine_mode mode)
899 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
902 if (GET_CODE (op) == LABEL_REF)
905 if (GET_CODE (op) == CONST
906 && GET_CODE (XEXP (op, 0)) == PLUS
907 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
908 op = XEXP (XEXP (op, 0), 0);
910 if (GET_CODE (op) != SYMBOL_REF)
913 return SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
916 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
917 known to be defined in this file in the small data area. */
920 small_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
922 if (! TARGET_SMALL_DATA)
925 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
928 if (GET_CODE (op) == CONST
929 && GET_CODE (XEXP (op, 0)) == PLUS
930 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
931 op = XEXP (XEXP (op, 0), 0);
933 if (GET_CODE (op) != SYMBOL_REF)
936 /* ??? There's no encode_section_info equivalent for the rtl
937 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
938 if (CONSTANT_POOL_ADDRESS_P (op))
939 return GET_MODE_SIZE (get_pool_mode (op)) <= g_switch_value;
941 return (SYMBOL_REF_LOCAL_P (op)
942 && SYMBOL_REF_SMALL_P (op)
943 && SYMBOL_REF_TLS_MODEL (op) == 0);
946 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
947 not known (or known not) to be defined in this file. */
950 global_symbolic_operand (rtx op, enum machine_mode mode)
952 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
955 if (GET_CODE (op) == CONST
956 && GET_CODE (XEXP (op, 0)) == PLUS
957 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
958 op = XEXP (XEXP (op, 0), 0);
960 if (GET_CODE (op) != SYMBOL_REF)
963 return !SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
966 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
969 call_operand (rtx op, enum machine_mode mode)
974 if (GET_CODE (op) == REG)
978 /* Disallow virtual registers to cope with pathological test cases
979 such as compile/930117-1.c in which the virtual reg decomposes
980 to the frame pointer. Which is a hard reg that is not $27. */
981 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
986 if (TARGET_ABI_UNICOSMK)
988 if (GET_CODE (op) == SYMBOL_REF)
994 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
995 possibly with an offset. */
998 symbolic_operand (rtx op, enum machine_mode mode)
1000 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1002 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1004 if (GET_CODE (op) == CONST
1005 && GET_CODE (XEXP (op,0)) == PLUS
1006 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1007 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1012 /* Return true if OP is valid for a particular TLS relocation. */
1015 tls_symbolic_operand_1 (rtx op, enum machine_mode mode, int size, int unspec)
1017 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1020 if (GET_CODE (op) != CONST)
1024 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1026 op = XVECEXP (op, 0, 0);
1028 if (GET_CODE (op) != SYMBOL_REF)
1031 if (SYMBOL_REF_LOCAL_P (op))
1033 if (alpha_tls_size > size)
1042 switch (SYMBOL_REF_TLS_MODEL (op))
1044 case TLS_MODEL_LOCAL_DYNAMIC:
1045 return unspec == UNSPEC_DTPREL;
1046 case TLS_MODEL_INITIAL_EXEC:
1047 return unspec == UNSPEC_TPREL && size == 64;
1048 case TLS_MODEL_LOCAL_EXEC:
1049 return unspec == UNSPEC_TPREL;
1055 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1058 dtp16_symbolic_operand (rtx op, enum machine_mode mode)
1060 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1063 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1066 dtp32_symbolic_operand (rtx op, enum machine_mode mode)
1068 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1071 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1074 gotdtp_symbolic_operand (rtx op, enum machine_mode mode)
1076 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1079 /* Return true if OP is valid for 16-bit TP relative relocations. */
1082 tp16_symbolic_operand (rtx op, enum machine_mode mode)
1084 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1087 /* Return true if OP is valid for 32-bit TP relative relocations. */
1090 tp32_symbolic_operand (rtx op, enum machine_mode mode)
1092 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1095 /* Return true if OP is valid for 64-bit TP relative relocations. */
1098 gottp_symbolic_operand (rtx op, enum machine_mode mode)
1100 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1103 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1104 comparisons are valid in which insn. */
1107 alpha_comparison_operator (rtx op, enum machine_mode mode)
1109 enum rtx_code code = GET_CODE (op);
1111 if (mode != GET_MODE (op) && mode != VOIDmode)
1114 return (code == EQ || code == LE || code == LT
1115 || code == LEU || code == LTU);
1118 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1119 Here we know which comparisons are valid in which insn. */
1122 alpha_zero_comparison_operator (rtx op, enum machine_mode mode)
1124 enum rtx_code code = GET_CODE (op);
1126 if (mode != GET_MODE (op) && mode != VOIDmode)
1129 return (code == EQ || code == NE || code == LE || code == LT
1130 || code == LEU || code == LTU);
1133 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1136 alpha_swapped_comparison_operator (rtx op, enum machine_mode mode)
1140 if ((mode != GET_MODE (op) && mode != VOIDmode)
1141 || !COMPARISON_P (op))
1144 code = swap_condition (GET_CODE (op));
1145 return (code == EQ || code == LE || code == LT
1146 || code == LEU || code == LTU);
1149 /* Return 1 if OP is a signed comparison operation. */
1152 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1154 enum rtx_code code = GET_CODE (op);
1156 if (mode != GET_MODE (op) && mode != VOIDmode)
1159 return (code == EQ || code == NE
1160 || code == LE || code == LT
1161 || code == GE || code == GT);
1164 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1165 Here we know which comparisons are valid in which insn. */
1168 alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
1170 enum rtx_code code = GET_CODE (op);
1172 if (mode != GET_MODE (op) && mode != VOIDmode)
1175 return (code == EQ || code == LE || code == LT || code == UNORDERED);
1178 /* Return 1 if this is a divide or modulus operator. */
1181 divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1183 enum rtx_code code = GET_CODE (op);
1185 return (code == DIV || code == MOD || code == UDIV || code == UMOD);
1188 /* Return 1 if this is a float->int conversion operator. */
1191 fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1193 enum rtx_code code = GET_CODE (op);
1195 return (code == FIX || code == UNSIGNED_FIX);
1198 /* Return 1 if this memory address is a known aligned register plus
1199 a constant. It must be a valid address. This means that we can do
1200 this as an aligned reference plus some offset.
1202 Take into account what reload will do. */
1205 aligned_memory_operand (rtx op, enum machine_mode mode)
1209 if (reload_in_progress)
1212 if (GET_CODE (tmp) == SUBREG)
1213 tmp = SUBREG_REG (tmp);
1214 if (GET_CODE (tmp) == REG
1215 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1217 op = reg_equiv_memory_loc[REGNO (tmp)];
1223 if (GET_CODE (op) != MEM)
1225 if (MEM_ALIGN (op) >= 32)
1229 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1230 sorts of constructs. Dig for the real base register. */
1231 if (reload_in_progress
1232 && GET_CODE (op) == PLUS
1233 && GET_CODE (XEXP (op, 0)) == PLUS)
1234 base = XEXP (XEXP (op, 0), 0);
1237 if (! memory_address_p (mode, op))
1239 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1242 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
1245 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1248 unaligned_memory_operand (rtx op, enum machine_mode mode)
1252 if (reload_in_progress)
1255 if (GET_CODE (tmp) == SUBREG)
1256 tmp = SUBREG_REG (tmp);
1257 if (GET_CODE (tmp) == REG
1258 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1260 op = reg_equiv_memory_loc[REGNO (tmp)];
1266 if (GET_CODE (op) != MEM)
1268 if (MEM_ALIGN (op) >= 32)
1272 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1273 sorts of constructs. Dig for the real base register. */
1274 if (reload_in_progress
1275 && GET_CODE (op) == PLUS
1276 && GET_CODE (XEXP (op, 0)) == PLUS)
1277 base = XEXP (XEXP (op, 0), 0);
1280 if (! memory_address_p (mode, op))
1282 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1285 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
1288 /* Return 1 if OP is either a register or an unaligned memory location. */
1291 reg_or_unaligned_mem_operand (rtx op, enum machine_mode mode)
1293 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
1296 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1299 any_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1301 return (GET_CODE (op) == MEM
1302 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1303 || (reload_in_progress && GET_CODE (op) == REG
1304 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1305 || (reload_in_progress && GET_CODE (op) == SUBREG
1306 && GET_CODE (SUBREG_REG (op)) == REG
1307 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1310 /* Returns 1 if OP is not an eliminable register.
1312 This exists to cure a pathological abort in the s8addq (et al) patterns,
1314 long foo () { long t; bar(); return (long) &t * 26107; }
1316 which run afoul of a hack in reload to cure a (presumably) similar
1317 problem with lea-type instructions on other targets. But there is
1318 one of us and many of them, so work around the problem by selectively
1319 preventing combine from making the optimization. */
1322 reg_not_elim_operand (rtx op, enum machine_mode mode)
1325 if (GET_CODE (op) == SUBREG)
1326 inner = SUBREG_REG (op);
1327 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1330 return register_operand (op, mode);
1333 /* Return 1 is OP is a memory location that is not a reference (using
1334 an AND) to an unaligned location. Take into account what reload
1338 normal_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1340 if (reload_in_progress)
1343 if (GET_CODE (tmp) == SUBREG)
1344 tmp = SUBREG_REG (tmp);
1345 if (GET_CODE (tmp) == REG
1346 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1348 op = reg_equiv_memory_loc[REGNO (tmp)];
1350 /* This may not have been assigned an equivalent address if it will
1351 be eliminated. In that case, it doesn't matter what we do. */
1357 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1360 /* Accept a register, but not a subreg of any kind. This allows us to
1361 avoid pathological cases in reload wrt data movement common in
1362 int->fp conversion. */
1365 reg_no_subreg_operand (rtx op, enum machine_mode mode)
1367 if (GET_CODE (op) != REG)
1369 return register_operand (op, mode);
1372 /* Recognize an addition operation that includes a constant. Used to
1373 convince reload to canonize (plus (plus reg c1) c2) during register
1377 addition_operation (rtx op, enum machine_mode mode)
1379 if (GET_MODE (op) != mode && mode != VOIDmode)
1381 if (GET_CODE (op) == PLUS
1382 && register_operand (XEXP (op, 0), mode)
1383 && GET_CODE (XEXP (op, 1)) == CONST_INT
1384 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1389 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1390 the range defined for C in [I-P]. */
1393 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
1398 /* An unsigned 8 bit constant. */
1399 return (unsigned HOST_WIDE_INT) value < 0x100;
1401 /* The constant zero. */
1404 /* A signed 16 bit constant. */
1405 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1407 /* A shifted signed 16 bit constant appropriate for LDAH. */
1408 return ((value & 0xffff) == 0
1409 && ((value) >> 31 == -1 || value >> 31 == 0));
1411 /* A constant that can be AND'ed with using a ZAP insn. */
1412 return zap_mask (value);
1414 /* A complemented unsigned 8 bit constant. */
1415 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1417 /* A negated unsigned 8 bit constant. */
1418 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1420 /* The constant 1, 2 or 3. */
1421 return value == 1 || value == 2 || value == 3;
1428 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1429 matches for C in [GH]. */
1432 alpha_const_double_ok_for_letter_p (rtx value, int c)
1437 /* The floating point zero constant. */
1438 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1439 && value == CONST0_RTX (GET_MODE (value)));
1442 /* A valid operand of a ZAP insn. */
1443 return (GET_MODE (value) == VOIDmode
1444 && zap_mask (CONST_DOUBLE_LOW (value))
1445 && zap_mask (CONST_DOUBLE_HIGH (value)));
1452 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1456 alpha_extra_constraint (rtx value, int c)
1461 return normal_memory_operand (value, VOIDmode);
1463 return direct_call_operand (value, Pmode);
1465 return (GET_CODE (value) == CONST_INT
1466 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1468 return GET_CODE (value) == HIGH;
1470 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
1472 return (GET_CODE (value) == CONST_VECTOR
1473 && value == CONST0_RTX (GET_MODE (value)));
1479 /* Return 1 if this function can directly return via $26. */
1482 direct_return (void)
1484 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
1486 && alpha_sa_size () == 0
1487 && get_frame_size () == 0
1488 && current_function_outgoing_args_size == 0
1489 && current_function_pretend_args_size == 0);
1492 /* Return the ADDR_VEC associated with a tablejump insn. */
1495 alpha_tablejump_addr_vec (rtx insn)
1499 tmp = JUMP_LABEL (insn);
1502 tmp = NEXT_INSN (tmp);
1505 if (GET_CODE (tmp) == JUMP_INSN
1506 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1507 return PATTERN (tmp);
1511 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1514 alpha_tablejump_best_label (rtx insn)
1516 rtx jump_table = alpha_tablejump_addr_vec (insn);
1517 rtx best_label = NULL_RTX;
1519 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1520 there for edge frequency counts from profile data. */
1524 int n_labels = XVECLEN (jump_table, 1);
1525 int best_count = -1;
1528 for (i = 0; i < n_labels; i++)
1532 for (j = i + 1; j < n_labels; j++)
1533 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1534 == XEXP (XVECEXP (jump_table, 1, j), 0))
1537 if (count > best_count)
1538 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1542 return best_label ? best_label : const0_rtx;
1545 /* Return the TLS model to use for SYMBOL. */
1547 static enum tls_model
1548 tls_symbolic_operand_type (rtx symbol)
1550 enum tls_model model;
1552 if (GET_CODE (symbol) != SYMBOL_REF)
1554 model = SYMBOL_REF_TLS_MODEL (symbol);
1556 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1557 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
1558 model = TLS_MODEL_INITIAL_EXEC;
1563 /* Return true if the function DECL will share the same GP as any
1564 function in the current unit of translation. */
1567 decl_has_samegp (tree decl)
1569 /* Functions that are not local can be overridden, and thus may
1570 not share the same gp. */
1571 if (!(*targetm.binds_local_p) (decl))
1574 /* If -msmall-data is in effect, assume that there is only one GP
1575 for the module, and so any local symbol has this property. We
1576 need explicit relocations to be able to enforce this for symbols
1577 not defined in this unit of translation, however. */
1578 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
1581 /* Functions that are not external are defined in this UoT. */
1582 /* ??? Irritatingly, static functions not yet emitted are still
1583 marked "external". Apply this to non-static functions only. */
1584 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
1587 /* Return true if EXP should be placed in the small data section. */
1590 alpha_in_small_data_p (tree exp)
1592 /* We want to merge strings, so we never consider them small data. */
1593 if (TREE_CODE (exp) == STRING_CST)
1596 /* Functions are never in the small data area. Duh. */
1597 if (TREE_CODE (exp) == FUNCTION_DECL)
1600 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1602 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1603 if (strcmp (section, ".sdata") == 0
1604 || strcmp (section, ".sbss") == 0)
1609 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1611 /* If this is an incomplete type with size 0, then we can't put it
1612 in sdata because it might be too big when completed. */
1613 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
1620 #if TARGET_ABI_OPEN_VMS
1622 alpha_linkage_symbol_p (const char *symname)
1624 int symlen = strlen (symname);
1627 return strcmp (&symname [symlen - 4], "..lk") == 0;
1632 #define LINKAGE_SYMBOL_REF_P(X) \
1633 ((GET_CODE (X) == SYMBOL_REF \
1634 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1635 || (GET_CODE (X) == CONST \
1636 && GET_CODE (XEXP (X, 0)) == PLUS \
1637 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1638 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1641 /* legitimate_address_p recognizes an RTL expression that is a valid
1642 memory address for an instruction. The MODE argument is the
1643 machine mode for the MEM expression that wants to use this address.
1645 For Alpha, we have either a constant address or the sum of a
1646 register and a constant address, or just a register. For DImode,
1647 any of those forms can be surrounded with an AND that clear the
1648 low-order three bits; this is an "unaligned" access. */
1651 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1653 /* If this is an ldq_u type address, discard the outer AND. */
1655 && GET_CODE (x) == AND
1656 && GET_CODE (XEXP (x, 1)) == CONST_INT
1657 && INTVAL (XEXP (x, 1)) == -8)
1660 /* Discard non-paradoxical subregs. */
1661 if (GET_CODE (x) == SUBREG
1662 && (GET_MODE_SIZE (GET_MODE (x))
1663 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1666 /* Unadorned general registers are valid. */
1669 ? STRICT_REG_OK_FOR_BASE_P (x)
1670 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
1673 /* Constant addresses (i.e. +/- 32k) are valid. */
1674 if (CONSTANT_ADDRESS_P (x))
1677 #if TARGET_ABI_OPEN_VMS
1678 if (LINKAGE_SYMBOL_REF_P (x))
1682 /* Register plus a small constant offset is valid. */
1683 if (GET_CODE (x) == PLUS)
1685 rtx ofs = XEXP (x, 1);
1688 /* Discard non-paradoxical subregs. */
1689 if (GET_CODE (x) == SUBREG
1690 && (GET_MODE_SIZE (GET_MODE (x))
1691 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1697 && NONSTRICT_REG_OK_FP_BASE_P (x)
1698 && GET_CODE (ofs) == CONST_INT)
1701 ? STRICT_REG_OK_FOR_BASE_P (x)
1702 : NONSTRICT_REG_OK_FOR_BASE_P (x))
1703 && CONSTANT_ADDRESS_P (ofs))
1706 else if (GET_CODE (x) == ADDRESSOF
1707 && GET_CODE (ofs) == CONST_INT)
1711 /* If we're managing explicit relocations, LO_SUM is valid, as
1712 are small data symbols. */
1713 else if (TARGET_EXPLICIT_RELOCS)
1715 if (small_symbolic_operand (x, Pmode))
1718 if (GET_CODE (x) == LO_SUM)
1720 rtx ofs = XEXP (x, 1);
1723 /* Discard non-paradoxical subregs. */
1724 if (GET_CODE (x) == SUBREG
1725 && (GET_MODE_SIZE (GET_MODE (x))
1726 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1729 /* Must have a valid base register. */
1732 ? STRICT_REG_OK_FOR_BASE_P (x)
1733 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
1736 /* The symbol must be local. */
1737 if (local_symbolic_operand (ofs, Pmode)
1738 || dtp32_symbolic_operand (ofs, Pmode)
1739 || tp32_symbolic_operand (ofs, Pmode))
1747 /* Build the SYMBOL_REF for __tls_get_addr. */
1749 static GTY(()) rtx tls_get_addr_libfunc;
1752 get_tls_get_addr (void)
1754 if (!tls_get_addr_libfunc)
1755 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
1756 return tls_get_addr_libfunc;
1759 /* Try machine-dependent ways of modifying an illegitimate address
1760 to be legitimate. If we find one, return the new, valid address. */
1763 alpha_legitimize_address (rtx x, rtx scratch,
1764 enum machine_mode mode ATTRIBUTE_UNUSED)
1766 HOST_WIDE_INT addend;
1768 /* If the address is (plus reg const_int) and the CONST_INT is not a
1769 valid offset, compute the high part of the constant and add it to
1770 the register. Then our address is (plus temp low-part-const). */
1771 if (GET_CODE (x) == PLUS
1772 && GET_CODE (XEXP (x, 0)) == REG
1773 && GET_CODE (XEXP (x, 1)) == CONST_INT
1774 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1776 addend = INTVAL (XEXP (x, 1));
1781 /* If the address is (const (plus FOO const_int)), find the low-order
1782 part of the CONST_INT. Then load FOO plus any high-order part of the
1783 CONST_INT into a register. Our address is (plus reg low-part-const).
1784 This is done to reduce the number of GOT entries. */
1786 && GET_CODE (x) == CONST
1787 && GET_CODE (XEXP (x, 0)) == PLUS
1788 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1790 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1791 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1795 /* If we have a (plus reg const), emit the load as in (2), then add
1796 the two registers, and finally generate (plus reg low-part-const) as
1799 && GET_CODE (x) == PLUS
1800 && GET_CODE (XEXP (x, 0)) == REG
1801 && GET_CODE (XEXP (x, 1)) == CONST
1802 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1803 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1805 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1806 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1807 XEXP (XEXP (XEXP (x, 1), 0), 0),
1808 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1812 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1813 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1815 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1817 switch (tls_symbolic_operand_type (x))
1819 case TLS_MODEL_GLOBAL_DYNAMIC:
1822 r0 = gen_rtx_REG (Pmode, 0);
1823 r16 = gen_rtx_REG (Pmode, 16);
1824 tga = get_tls_get_addr ();
1825 dest = gen_reg_rtx (Pmode);
1826 seq = GEN_INT (alpha_next_sequence_number++);
1828 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1829 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1830 insn = emit_call_insn (insn);
1831 CONST_OR_PURE_CALL_P (insn) = 1;
1832 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1834 insn = get_insns ();
1837 emit_libcall_block (insn, dest, r0, x);
1840 case TLS_MODEL_LOCAL_DYNAMIC:
1843 r0 = gen_rtx_REG (Pmode, 0);
1844 r16 = gen_rtx_REG (Pmode, 16);
1845 tga = get_tls_get_addr ();
1846 scratch = gen_reg_rtx (Pmode);
1847 seq = GEN_INT (alpha_next_sequence_number++);
1849 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1850 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1851 insn = emit_call_insn (insn);
1852 CONST_OR_PURE_CALL_P (insn) = 1;
1853 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1855 insn = get_insns ();
1858 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1859 UNSPEC_TLSLDM_CALL);
1860 emit_libcall_block (insn, scratch, r0, eqv);
1862 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1863 eqv = gen_rtx_CONST (Pmode, eqv);
1865 if (alpha_tls_size == 64)
1867 dest = gen_reg_rtx (Pmode);
1868 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1869 emit_insn (gen_adddi3 (dest, dest, scratch));
1872 if (alpha_tls_size == 32)
1874 insn = gen_rtx_HIGH (Pmode, eqv);
1875 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1876 scratch = gen_reg_rtx (Pmode);
1877 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1879 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1881 case TLS_MODEL_INITIAL_EXEC:
1882 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1883 eqv = gen_rtx_CONST (Pmode, eqv);
1884 tp = gen_reg_rtx (Pmode);
1885 scratch = gen_reg_rtx (Pmode);
1886 dest = gen_reg_rtx (Pmode);
1888 emit_insn (gen_load_tp (tp));
1889 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1890 emit_insn (gen_adddi3 (dest, tp, scratch));
1893 case TLS_MODEL_LOCAL_EXEC:
1894 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1895 eqv = gen_rtx_CONST (Pmode, eqv);
1896 tp = gen_reg_rtx (Pmode);
1898 emit_insn (gen_load_tp (tp));
1899 if (alpha_tls_size == 32)
1901 insn = gen_rtx_HIGH (Pmode, eqv);
1902 insn = gen_rtx_PLUS (Pmode, tp, insn);
1903 tp = gen_reg_rtx (Pmode);
1904 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1906 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1909 if (local_symbolic_operand (x, Pmode))
1911 if (small_symbolic_operand (x, Pmode))
1915 if (!no_new_pseudos)
1916 scratch = gen_reg_rtx (Pmode);
1917 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1918 gen_rtx_HIGH (Pmode, x)));
1919 return gen_rtx_LO_SUM (Pmode, scratch, x);
1928 HOST_WIDE_INT low, high;
1930 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1932 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1936 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1937 (no_new_pseudos ? scratch : NULL_RTX),
1938 1, OPTAB_LIB_WIDEN);
1940 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1941 (no_new_pseudos ? scratch : NULL_RTX),
1942 1, OPTAB_LIB_WIDEN);
1944 return plus_constant (x, low);
1948 /* We do not allow indirect calls to be optimized into sibling calls, nor
1949 can we allow a call to a function with a different GP to be optimized
1953 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1955 /* Can't do indirect tail calls, since we don't know if the target
1956 uses the same GP. */
1960 /* Otherwise, we can make a tail call if the target function shares
1962 return decl_has_samegp (decl);
1965 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1966 small symbolic operand until after reload. At which point we need
1967 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1968 so that sched2 has the proper dependency information. */
1971 some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1975 /* Don't re-split. */
1976 if (GET_CODE (x) == LO_SUM)
1979 return small_symbolic_operand (x, Pmode) != 0;
1983 some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1985 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
1989 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1993 /* Don't re-split. */
1994 if (GET_CODE (x) == LO_SUM)
1997 if (small_symbolic_operand (x, Pmode))
1999 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2008 split_small_symbolic_operand (rtx x)
2011 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
2015 /* Indicate that INSN cannot be duplicated. This is true for any insn
2016 that we've marked with gpdisp relocs, since those have to stay in
2017 1-1 correspondence with one another.
2019 Technically we could copy them if we could set up a mapping from one
2020 sequence number to another, across the set of insns to be duplicated.
2021 This seems overly complicated and error-prone since interblock motion
2022 from sched-ebb could move one of the pair of insns to a different block.
2024 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2025 then they'll be in a different block from their ldgp. Which could lead
2026 the bb reorder code to think that it would be ok to copy just the block
2027 containing the call and branch to the block containing the ldgp. */
2030 alpha_cannot_copy_insn_p (rtx insn)
2032 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
2034 if (recog_memoized (insn) >= 0)
2035 return get_attr_cannot_copy (insn);
2041 /* Try a machine-dependent way of reloading an illegitimate address
2042 operand. If we find one, push the reload and return the new rtx. */
2045 alpha_legitimize_reload_address (rtx x,
2046 enum machine_mode mode ATTRIBUTE_UNUSED,
2047 int opnum, int type,
2048 int ind_levels ATTRIBUTE_UNUSED)
2050 /* We must recognize output that we have already generated ourselves. */
2051 if (GET_CODE (x) == PLUS
2052 && GET_CODE (XEXP (x, 0)) == PLUS
2053 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2054 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2055 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2057 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2058 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2063 /* We wish to handle large displacements off a base register by
2064 splitting the addend across an ldah and the mem insn. This
2065 cuts number of extra insns needed from 3 to 1. */
2066 if (GET_CODE (x) == PLUS
2067 && GET_CODE (XEXP (x, 0)) == REG
2068 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2069 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2070 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2072 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2073 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2075 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2077 /* Check for 32-bit overflow. */
2078 if (high + low != val)
2081 /* Reload the high part into a base reg; leave the low part
2082 in the mem directly. */
2083 x = gen_rtx_PLUS (GET_MODE (x),
2084 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2088 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2089 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2097 /* Compute a (partial) cost for rtx X. Return true if the complete
2098 cost has been computed, and false if subexpressions should be
2099 scanned. In either case, *TOTAL contains the cost result. */
2102 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
2104 enum machine_mode mode = GET_MODE (x);
2105 bool float_mode_p = FLOAT_MODE_P (mode);
2109 /* If this is an 8-bit constant, return zero since it can be used
2110 nearly anywhere with no cost. If it is a valid operand for an
2111 ADD or AND, likewise return 0 if we know it will be used in that
2112 context. Otherwise, return 2 since it might be used there later.
2113 All other constants take at least two insns. */
2115 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
2123 if (x == CONST0_RTX (mode))
2125 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
2126 || (outer_code == AND && and_operand (x, VOIDmode)))
2128 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
2131 *total = COSTS_N_INSNS (2);
2137 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
2138 *total = COSTS_N_INSNS (outer_code != MEM);
2139 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
2140 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
2141 else if (tls_symbolic_operand_type (x))
2142 /* Estimate of cost for call_pal rduniq. */
2143 *total = COSTS_N_INSNS (15);
2145 /* Otherwise we do a load from the GOT. */
2146 *total = COSTS_N_INSNS (alpha_memory_latency);
2152 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2153 else if (GET_CODE (XEXP (x, 0)) == MULT
2154 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
2156 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
2157 + rtx_cost (XEXP (x, 1), outer_code) + COSTS_N_INSNS (1));
2164 *total = alpha_rtx_cost_data[alpha_cpu].fp_mult;
2165 else if (mode == DImode)
2166 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_di;
2168 *total = alpha_rtx_cost_data[alpha_cpu].int_mult_si;
2172 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2173 && INTVAL (XEXP (x, 1)) <= 3)
2175 *total = COSTS_N_INSNS (1);
2182 *total = alpha_rtx_cost_data[alpha_cpu].int_shift;
2187 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2189 *total = alpha_rtx_cost_data[alpha_cpu].int_cmov;
2197 *total = COSTS_N_INSNS (70); /* ??? */
2198 else if (mode == SFmode)
2199 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_sf;
2201 *total = alpha_rtx_cost_data[alpha_cpu].fp_div_df;
2205 *total = COSTS_N_INSNS (alpha_memory_latency);
2211 *total = COSTS_N_INSNS (1);
2219 *total = COSTS_N_INSNS (1) + alpha_rtx_cost_data[alpha_cpu].int_cmov;
2225 case UNSIGNED_FLOAT:
2229 case FLOAT_TRUNCATE:
2230 *total = alpha_rtx_cost_data[alpha_cpu].fp_add;
2238 /* REF is an alignable memory location. Place an aligned SImode
2239 reference into *PALIGNED_MEM and the number of bits to shift into
2240 *PBITNUM. SCRATCH is a free register for use in reloading out
2241 of range stack slots. */
2244 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
2247 HOST_WIDE_INT offset = 0;
2249 if (GET_CODE (ref) != MEM)
2252 if (reload_in_progress
2253 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2255 base = find_replacement (&XEXP (ref, 0));
2257 if (! memory_address_p (GET_MODE (ref), base))
2262 base = XEXP (ref, 0);
2265 if (GET_CODE (base) == PLUS)
2266 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2269 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
2271 if (WORDS_BIG_ENDIAN)
2272 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2273 + (offset & 3) * 8));
2275 *pbitnum = GEN_INT ((offset & 3) * 8);
2278 /* Similar, but just get the address. Handle the two reload cases.
2279 Add EXTRA_OFFSET to the address we return. */
2282 get_unaligned_address (rtx ref, int extra_offset)
2285 HOST_WIDE_INT offset = 0;
2287 if (GET_CODE (ref) != MEM)
2290 if (reload_in_progress
2291 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2293 base = find_replacement (&XEXP (ref, 0));
2295 if (! memory_address_p (GET_MODE (ref), base))
2300 base = XEXP (ref, 0);
2303 if (GET_CODE (base) == PLUS)
2304 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2306 return plus_constant (base, offset + extra_offset);
2309 /* On the Alpha, all (non-symbolic) constants except zero go into
2310 a floating-point register via memory. Note that we cannot
2311 return anything that is not a subset of CLASS, and that some
2312 symbolic constants cannot be dropped to memory. */
2315 alpha_preferred_reload_class(rtx x, enum reg_class class)
2317 /* Zero is present in any register class. */
2318 if (x == CONST0_RTX (GET_MODE (x)))
2321 /* These sorts of constants we can easily drop to memory. */
2322 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2324 if (class == FLOAT_REGS)
2326 if (class == ALL_REGS)
2327 return GENERAL_REGS;
2331 /* All other kinds of constants should not (and in the case of HIGH
2332 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2333 secondary reload. */
2335 return (class == ALL_REGS ? GENERAL_REGS : class);
2340 /* Loading and storing HImode or QImode values to and from memory
2341 usually requires a scratch register. The exceptions are loading
2342 QImode and HImode from an aligned address to a general register
2343 unless byte instructions are permitted.
2345 We also cannot load an unaligned address or a paradoxical SUBREG
2346 into an FP register.
2348 We also cannot do integral arithmetic into FP regs, as might result
2349 from register elimination into a DImode fp register. */
2352 secondary_reload_class (enum reg_class class, enum machine_mode mode,
2355 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
2357 if (GET_CODE (x) == MEM
2358 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2359 || (GET_CODE (x) == SUBREG
2360 && (GET_CODE (SUBREG_REG (x)) == MEM
2361 || (GET_CODE (SUBREG_REG (x)) == REG
2362 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
2364 if (!in || !aligned_memory_operand(x, mode))
2365 return GENERAL_REGS;
2369 if (class == FLOAT_REGS)
2371 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2372 return GENERAL_REGS;
2374 if (GET_CODE (x) == SUBREG
2375 && (GET_MODE_SIZE (GET_MODE (x))
2376 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2377 return GENERAL_REGS;
2379 if (in && INTEGRAL_MODE_P (mode)
2380 && ! (memory_operand (x, mode) || x == const0_rtx))
2381 return GENERAL_REGS;
2387 /* Subfunction of the following function. Update the flags of any MEM
2388 found in part of X. */
2391 alpha_set_memflags_1 (rtx x, int in_struct_p, int volatile_p, int unchanging_p)
2395 switch (GET_CODE (x))
2401 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2402 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
2407 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
2412 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
2414 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
2419 MEM_IN_STRUCT_P (x) = in_struct_p;
2420 MEM_VOLATILE_P (x) = volatile_p;
2421 RTX_UNCHANGING_P (x) = unchanging_p;
2422 /* Sadly, we cannot use alias sets because the extra aliasing
2423 produced by the AND interferes. Given that two-byte quantities
2424 are the only thing we would be able to differentiate anyway,
2425 there does not seem to be any point in convoluting the early
2426 out of the alias check. */
2434 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2435 generated to perform a memory operation, look for any MEMs in either
2436 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2437 volatile flags from REF into each of the MEMs found. If REF is not
2438 a MEM, don't do anything. */
2441 alpha_set_memflags (rtx insn, rtx ref)
2443 int in_struct_p, volatile_p, unchanging_p;
2445 if (GET_CODE (ref) != MEM)
2448 in_struct_p = MEM_IN_STRUCT_P (ref);
2449 volatile_p = MEM_VOLATILE_P (ref);
2450 unchanging_p = RTX_UNCHANGING_P (ref);
2452 /* This is only called from alpha.md, after having had something
2453 generated from one of the insn patterns. So if everything is
2454 zero, the pattern is already up-to-date. */
2455 if (! in_struct_p && ! volatile_p && ! unchanging_p)
2458 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
2461 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2464 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
2465 HOST_WIDE_INT c, int n)
2469 /* Use a pseudo if highly optimizing and still generating RTL. */
2471 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
2474 /* If this is a sign-extended 32-bit constant, we can do this in at most
2475 three insns, so do it if we have enough insns left. We always have
2476 a sign-extended 32-bit constant when compiling on a narrow machine. */
2478 if (HOST_BITS_PER_WIDE_INT != 64
2479 || c >> 31 == -1 || c >> 31 == 0)
2481 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
2482 HOST_WIDE_INT tmp1 = c - low;
2483 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
2484 HOST_WIDE_INT extra = 0;
2486 /* If HIGH will be interpreted as negative but the constant is
2487 positive, we must adjust it to do two ldha insns. */
2489 if ((high & 0x8000) != 0 && c >= 0)
2493 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2496 if (c == low || (low == 0 && extra == 0))
2498 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2499 but that meant that we can't handle INT_MIN on 32-bit machines
2500 (like NT/Alpha), because we recurse indefinitely through
2501 emit_move_insn to gen_movdi. So instead, since we know exactly
2502 what we want, create it explicitly. */
2505 target = gen_reg_rtx (mode);
2506 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
2509 else if (n >= 2 + (extra != 0))
2513 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
2517 temp = copy_to_suggested_reg (GEN_INT (high << 16),
2520 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2521 This means that if we go through expand_binop, we'll try to
2522 generate extensions, etc, which will require new pseudos, which
2523 will fail during some split phases. The SImode add patterns
2524 still exist, but are not named. So build the insns by hand. */
2529 subtarget = gen_reg_rtx (mode);
2530 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2531 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2537 target = gen_reg_rtx (mode);
2538 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2539 insn = gen_rtx_SET (VOIDmode, target, insn);
2545 /* If we couldn't do it that way, try some other methods. But if we have
2546 no instructions left, don't bother. Likewise, if this is SImode and
2547 we can't make pseudos, we can't do anything since the expand_binop
2548 and expand_unop calls will widen and try to make pseudos. */
2550 if (n == 1 || (mode == SImode && no_new_pseudos))
2553 /* Next, see if we can load a related constant and then shift and possibly
2554 negate it to get the constant we want. Try this once each increasing
2555 numbers of insns. */
2557 for (i = 1; i < n; i++)
2559 /* First, see if minus some low bits, we've an easy load of
2562 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2564 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2565 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2566 target, 0, OPTAB_WIDEN);
2568 /* Next try complementing. */
2569 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2570 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
2572 /* Next try to form a constant and do a left shift. We can do this
2573 if some low-order bits are zero; the exact_log2 call below tells
2574 us that information. The bits we are shifting out could be any
2575 value, but here we'll just try the 0- and sign-extended forms of
2576 the constant. To try to increase the chance of having the same
2577 constant in more than one insn, start at the highest number of
2578 bits to shift, but try all possibilities in case a ZAPNOT will
2581 if ((bits = exact_log2 (c & - c)) > 0)
2582 for (; bits > 0; bits--)
2583 if ((temp = (alpha_emit_set_const
2584 (subtarget, mode, c >> bits, i))) != 0
2585 || ((temp = (alpha_emit_set_const
2587 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2589 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2590 target, 0, OPTAB_WIDEN);
2592 /* Now try high-order zero bits. Here we try the shifted-in bits as
2593 all zero and all ones. Be careful to avoid shifting outside the
2594 mode and to avoid shifting outside the host wide int size. */
2595 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2596 confuse the recursive call and set all of the high 32 bits. */
2598 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2599 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
2600 for (; bits > 0; bits--)
2601 if ((temp = alpha_emit_set_const (subtarget, mode,
2603 || ((temp = (alpha_emit_set_const
2605 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2608 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
2609 target, 1, OPTAB_WIDEN);
2611 /* Now try high-order 1 bits. We get that with a sign-extension.
2612 But one bit isn't enough here. Be careful to avoid shifting outside
2613 the mode and to avoid shifting outside the host wide int size. */
2615 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2616 - floor_log2 (~ c) - 2)) > 0)
2617 for (; bits > 0; bits--)
2618 if ((temp = alpha_emit_set_const (subtarget, mode,
2620 || ((temp = (alpha_emit_set_const
2622 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2625 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2626 target, 0, OPTAB_WIDEN);
2629 #if HOST_BITS_PER_WIDE_INT == 64
2630 /* Finally, see if can load a value into the target that is the same as the
2631 constant except that all bytes that are 0 are changed to be 0xff. If we
2632 can, then we can do a ZAPNOT to obtain the desired constant. */
2635 for (i = 0; i < 64; i += 8)
2636 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2637 new |= (HOST_WIDE_INT) 0xff << i;
2639 /* We are only called for SImode and DImode. If this is SImode, ensure that
2640 we are sign extended to a full word. */
2643 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2645 if (new != c && new != -1
2646 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2647 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
2648 target, 0, OPTAB_WIDEN);
2654 /* Try to output insns to set TARGET equal to the constant C if it can be
2655 done in less than N insns. Do all computations in MODE. Returns the place
2656 where the output has been placed if it can be done and the insns have been
2657 emitted. If it would take more than N insns, zero is returned and no
2658 insns and emitted. */
2661 alpha_emit_set_const (rtx target, enum machine_mode mode,
2662 HOST_WIDE_INT c, int n)
2665 rtx orig_target = target;
2668 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2669 can't load this constant in one insn, do this in DImode. */
2670 if (no_new_pseudos && mode == SImode
2671 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2672 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2674 target = gen_lowpart (DImode, target);
2678 /* Try 1 insn, then 2, then up to N. */
2679 for (i = 1; i <= n; i++)
2681 result = alpha_emit_set_const_1 (target, mode, c, i);
2684 rtx insn = get_last_insn ();
2685 rtx set = single_set (insn);
2686 if (! CONSTANT_P (SET_SRC (set)))
2687 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2692 /* Allow for the case where we changed the mode of TARGET. */
2693 if (result == target)
2694 result = orig_target;
2699 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2700 fall back to a straight forward decomposition. We do this to avoid
2701 exponential run times encountered when looking for longer sequences
2702 with alpha_emit_set_const. */
2705 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2707 HOST_WIDE_INT d1, d2, d3, d4;
2709 /* Decompose the entire word */
2710 #if HOST_BITS_PER_WIDE_INT >= 64
2711 if (c2 != -(c1 < 0))
2713 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2715 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2716 c1 = (c1 - d2) >> 32;
2717 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2719 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2723 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2725 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2729 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2731 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2736 /* Construct the high word */
2739 emit_move_insn (target, GEN_INT (d4));
2741 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2744 emit_move_insn (target, GEN_INT (d3));
2746 /* Shift it into place */
2747 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2749 /* Add in the low bits. */
2751 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2753 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2758 /* Expand a move instruction; return true if all work is done.
2759 We don't handle non-bwx subword loads here. */
2762 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2764 /* If the output is not a register, the input must be. */
2765 if (GET_CODE (operands[0]) == MEM
2766 && ! reg_or_0_operand (operands[1], mode))
2767 operands[1] = force_reg (mode, operands[1]);
2769 /* Allow legitimize_address to perform some simplifications. */
2770 if (mode == Pmode && symbolic_operand (operands[1], mode))
2774 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2775 compiled at the end of compilation. In the meantime, someone can
2776 re-encode-section-info on some symbol changing it e.g. from global
2777 to local-not-small. If this happens, we'd have emitted a plain
2778 load rather than a high+losum load and not recognize the insn.
2780 So if rtl inlining is in effect, we delay the global/not-global
2781 decision until rest_of_compilation by wrapping it in an
2783 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2784 && rtx_equal_function_value_matters
2785 && global_symbolic_operand (operands[1], mode))
2787 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2791 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2794 if (tmp == operands[0])
2801 /* Early out for non-constants and valid constants. */
2802 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2805 /* Split large integers. */
2806 if (GET_CODE (operands[1]) == CONST_INT
2807 || GET_CODE (operands[1]) == CONST_DOUBLE)
2809 HOST_WIDE_INT i0, i1;
2810 rtx temp = NULL_RTX;
2812 if (GET_CODE (operands[1]) == CONST_INT)
2814 i0 = INTVAL (operands[1]);
2817 else if (HOST_BITS_PER_WIDE_INT >= 64)
2819 i0 = CONST_DOUBLE_LOW (operands[1]);
2824 i0 = CONST_DOUBLE_LOW (operands[1]);
2825 i1 = CONST_DOUBLE_HIGH (operands[1]);
2828 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2829 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2831 if (!temp && TARGET_BUILD_CONSTANTS)
2832 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2836 if (rtx_equal_p (operands[0], temp))
2843 /* Otherwise we've nothing left but to drop the thing to memory. */
2844 operands[1] = force_const_mem (mode, operands[1]);
2845 if (reload_in_progress)
2847 emit_move_insn (operands[0], XEXP (operands[1], 0));
2848 operands[1] = copy_rtx (operands[1]);
2849 XEXP (operands[1], 0) = operands[0];
2852 operands[1] = validize_mem (operands[1]);
2856 /* Expand a non-bwx QImode or HImode move instruction;
2857 return true if all work is done. */
2860 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2862 /* If the output is not a register, the input must be. */
2863 if (GET_CODE (operands[0]) == MEM)
2864 operands[1] = force_reg (mode, operands[1]);
2866 /* Handle four memory cases, unaligned and aligned for either the input
2867 or the output. The only case where we can be called during reload is
2868 for aligned loads; all other cases require temporaries. */
2870 if (GET_CODE (operands[1]) == MEM
2871 || (GET_CODE (operands[1]) == SUBREG
2872 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2873 || (reload_in_progress && GET_CODE (operands[1]) == REG
2874 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2875 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2876 && GET_CODE (SUBREG_REG (operands[1])) == REG
2877 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2879 if (aligned_memory_operand (operands[1], mode))
2881 if (reload_in_progress)
2883 emit_insn ((mode == QImode
2884 ? gen_reload_inqi_help
2885 : gen_reload_inhi_help)
2886 (operands[0], operands[1],
2887 gen_rtx_REG (SImode, REGNO (operands[0]))));
2891 rtx aligned_mem, bitnum;
2892 rtx scratch = gen_reg_rtx (SImode);
2896 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2898 subtarget = operands[0];
2899 if (GET_CODE (subtarget) == REG)
2900 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2902 subtarget = gen_reg_rtx (DImode), copyout = true;
2904 emit_insn ((mode == QImode
2905 ? gen_aligned_loadqi
2906 : gen_aligned_loadhi)
2907 (subtarget, aligned_mem, bitnum, scratch));
2910 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2915 /* Don't pass these as parameters since that makes the generated
2916 code depend on parameter evaluation order which will cause
2917 bootstrap failures. */
2919 rtx temp1, temp2, seq, subtarget;
2922 temp1 = gen_reg_rtx (DImode);
2923 temp2 = gen_reg_rtx (DImode);
2925 subtarget = operands[0];
2926 if (GET_CODE (subtarget) == REG)
2927 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2929 subtarget = gen_reg_rtx (DImode), copyout = true;
2931 seq = ((mode == QImode
2932 ? gen_unaligned_loadqi
2933 : gen_unaligned_loadhi)
2934 (subtarget, get_unaligned_address (operands[1], 0),
2936 alpha_set_memflags (seq, operands[1]);
2940 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2945 if (GET_CODE (operands[0]) == MEM
2946 || (GET_CODE (operands[0]) == SUBREG
2947 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2948 || (reload_in_progress && GET_CODE (operands[0]) == REG
2949 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2950 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2951 && GET_CODE (SUBREG_REG (operands[0])) == REG
2952 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2954 if (aligned_memory_operand (operands[0], mode))
2956 rtx aligned_mem, bitnum;
2957 rtx temp1 = gen_reg_rtx (SImode);
2958 rtx temp2 = gen_reg_rtx (SImode);
2960 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2962 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2967 rtx temp1 = gen_reg_rtx (DImode);
2968 rtx temp2 = gen_reg_rtx (DImode);
2969 rtx temp3 = gen_reg_rtx (DImode);
2970 rtx seq = ((mode == QImode
2971 ? gen_unaligned_storeqi
2972 : gen_unaligned_storehi)
2973 (get_unaligned_address (operands[0], 0),
2974 operands[1], temp1, temp2, temp3));
2976 alpha_set_memflags (seq, operands[0]);
2985 /* Generate an unsigned DImode to FP conversion. This is the same code
2986 optabs would emit if we didn't have TFmode patterns.
2988 For SFmode, this is the only construction I've found that can pass
2989 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2990 intermediates will work, because you'll get intermediate rounding
2991 that ruins the end result. Some of this could be fixed by turning
2992 on round-to-positive-infinity, but that requires diddling the fpsr,
2993 which kills performance. I tried turning this around and converting
2994 to a negative number, so that I could turn on /m, but either I did
2995 it wrong or there's something else cause I wound up with the exact
2996 same single-bit error. There is a branch-less form of this same code:
3007 fcmoveq $f10,$f11,$f0
3009 I'm not using it because it's the same number of instructions as
3010 this branch-full form, and it has more serialized long latency
3011 instructions on the critical path.
3013 For DFmode, we can avoid rounding errors by breaking up the word
3014 into two pieces, converting them separately, and adding them back:
3016 LC0: .long 0,0x5f800000
3021 cpyse $f11,$f31,$f10
3022 cpyse $f31,$f11,$f11
3030 This doesn't seem to be a clear-cut win over the optabs form.
3031 It probably all depends on the distribution of numbers being
3032 converted -- in the optabs form, all but high-bit-set has a
3033 much lower minimum execution time. */
3036 alpha_emit_floatuns (rtx operands[2])
3038 rtx neglab, donelab, i0, i1, f0, in, out;
3039 enum machine_mode mode;
3042 in = force_reg (DImode, operands[1]);
3043 mode = GET_MODE (out);
3044 neglab = gen_label_rtx ();
3045 donelab = gen_label_rtx ();
3046 i0 = gen_reg_rtx (DImode);
3047 i1 = gen_reg_rtx (DImode);
3048 f0 = gen_reg_rtx (mode);
3050 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
3052 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3053 emit_jump_insn (gen_jump (donelab));
3056 emit_label (neglab);
3058 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3059 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3060 emit_insn (gen_iordi3 (i0, i0, i1));
3061 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3062 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3064 emit_label (donelab);
3067 /* Generate the comparison for a conditional branch. */
3070 alpha_emit_conditional_branch (enum rtx_code code)
3072 enum rtx_code cmp_code, branch_code;
3073 enum machine_mode cmp_mode, branch_mode = VOIDmode;
3074 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3077 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3079 if (! TARGET_HAS_XFLOATING_LIBS)
3082 /* X_floating library comparison functions return
3086 Convert the compare against the raw return value. */
3108 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3110 alpha_compare.fp_p = 0;
3113 /* The general case: fold the comparison code to the types of compares
3114 that we have, choosing the branch as necessary. */
3117 case EQ: case LE: case LT: case LEU: case LTU:
3119 /* We have these compares: */
3120 cmp_code = code, branch_code = NE;
3125 /* These must be reversed. */
3126 cmp_code = reverse_condition (code), branch_code = EQ;
3129 case GE: case GT: case GEU: case GTU:
3130 /* For FP, we swap them, for INT, we reverse them. */
3131 if (alpha_compare.fp_p)
3133 cmp_code = swap_condition (code);
3135 tem = op0, op0 = op1, op1 = tem;
3139 cmp_code = reverse_condition (code);
3148 if (alpha_compare.fp_p)
3151 if (flag_unsafe_math_optimizations)
3153 /* When we are not as concerned about non-finite values, and we
3154 are comparing against zero, we can branch directly. */
3155 if (op1 == CONST0_RTX (DFmode))
3156 cmp_code = NIL, branch_code = code;
3157 else if (op0 == CONST0_RTX (DFmode))
3159 /* Undo the swap we probably did just above. */
3160 tem = op0, op0 = op1, op1 = tem;
3161 branch_code = swap_condition (cmp_code);
3167 /* ??? We mark the branch mode to be CCmode to prevent the
3168 compare and branch from being combined, since the compare
3169 insn follows IEEE rules that the branch does not. */
3170 branch_mode = CCmode;
3177 /* The following optimizations are only for signed compares. */
3178 if (code != LEU && code != LTU && code != GEU && code != GTU)
3180 /* Whee. Compare and branch against 0 directly. */
3181 if (op1 == const0_rtx)
3182 cmp_code = NIL, branch_code = code;
3184 /* If the constants doesn't fit into an immediate, but can
3185 be generated by lda/ldah, we adjust the argument and
3186 compare against zero, so we can use beq/bne directly. */
3187 /* ??? Don't do this when comparing against symbols, otherwise
3188 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3189 be declared false out of hand (at least for non-weak). */
3190 else if (GET_CODE (op1) == CONST_INT
3191 && (code == EQ || code == NE)
3192 && !(symbolic_operand (op0, VOIDmode)
3193 || (GET_CODE (op0) == REG && REG_POINTER (op0))))
3195 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3197 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3198 && (CONST_OK_FOR_LETTER_P (n, 'K')
3199 || CONST_OK_FOR_LETTER_P (n, 'L')))
3201 cmp_code = PLUS, branch_code = code;
3207 if (!reg_or_0_operand (op0, DImode))
3208 op0 = force_reg (DImode, op0);
3209 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3210 op1 = force_reg (DImode, op1);
3213 /* Emit an initial compare instruction, if necessary. */
3215 if (cmp_code != NIL)
3217 tem = gen_reg_rtx (cmp_mode);
3218 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3221 /* Zero the operands. */
3222 memset (&alpha_compare, 0, sizeof (alpha_compare));
3224 /* Return the branch comparison. */
3225 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3228 /* Certain simplifications can be done to make invalid setcc operations
3229 valid. Return the final comparison, or NULL if we can't work. */
3232 alpha_emit_setcc (enum rtx_code code)
3234 enum rtx_code cmp_code;
3235 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3236 int fp_p = alpha_compare.fp_p;
3239 /* Zero the operands. */
3240 memset (&alpha_compare, 0, sizeof (alpha_compare));
3242 if (fp_p && GET_MODE (op0) == TFmode)
3244 if (! TARGET_HAS_XFLOATING_LIBS)
3247 /* X_floating library comparison functions return
3251 Convert the compare against the raw return value. */
3253 if (code == UNORDERED || code == ORDERED)
3258 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3262 if (code == UNORDERED)
3264 else if (code == ORDERED)
3270 if (fp_p && !TARGET_FIX)
3273 /* The general case: fold the comparison code to the types of compares
3274 that we have, choosing the branch as necessary. */
3279 case EQ: case LE: case LT: case LEU: case LTU:
3281 /* We have these compares. */
3283 cmp_code = code, code = NE;
3287 if (!fp_p && op1 == const0_rtx)
3292 cmp_code = reverse_condition (code);
3296 case GE: case GT: case GEU: case GTU:
3297 /* These normally need swapping, but for integer zero we have
3298 special patterns that recognize swapped operands. */
3299 if (!fp_p && op1 == const0_rtx)
3301 code = swap_condition (code);
3303 cmp_code = code, code = NE;
3304 tmp = op0, op0 = op1, op1 = tmp;
3313 if (!register_operand (op0, DImode))
3314 op0 = force_reg (DImode, op0);
3315 if (!reg_or_8bit_operand (op1, DImode))
3316 op1 = force_reg (DImode, op1);
3319 /* Emit an initial compare instruction, if necessary. */
3320 if (cmp_code != NIL)
3322 enum machine_mode mode = fp_p ? DFmode : DImode;
3324 tmp = gen_reg_rtx (mode);
3325 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3326 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3328 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3332 /* Return the setcc comparison. */
3333 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3337 /* Rewrite a comparison against zero CMP of the form
3338 (CODE (cc0) (const_int 0)) so it can be written validly in
3339 a conditional move (if_then_else CMP ...).
3340 If both of the operands that set cc0 are nonzero we must emit
3341 an insn to perform the compare (it can't be done within
3342 the conditional move). */
3345 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
3347 enum rtx_code code = GET_CODE (cmp);
3348 enum rtx_code cmov_code = NE;
3349 rtx op0 = alpha_compare.op0;
3350 rtx op1 = alpha_compare.op1;
3351 int fp_p = alpha_compare.fp_p;
3352 enum machine_mode cmp_mode
3353 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
3354 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
3355 enum machine_mode cmov_mode = VOIDmode;
3356 int local_fast_math = flag_unsafe_math_optimizations;
3359 /* Zero the operands. */
3360 memset (&alpha_compare, 0, sizeof (alpha_compare));
3362 if (fp_p != FLOAT_MODE_P (mode))
3364 enum rtx_code cmp_code;
3369 /* If we have fp<->int register move instructions, do a cmov by
3370 performing the comparison in fp registers, and move the
3371 zero/nonzero value to integer registers, where we can then
3372 use a normal cmov, or vice-versa. */
3376 case EQ: case LE: case LT: case LEU: case LTU:
3377 /* We have these compares. */
3378 cmp_code = code, code = NE;
3382 /* This must be reversed. */
3383 cmp_code = EQ, code = EQ;
3386 case GE: case GT: case GEU: case GTU:
3387 /* These normally need swapping, but for integer zero we have
3388 special patterns that recognize swapped operands. */
3389 if (!fp_p && op1 == const0_rtx)
3390 cmp_code = code, code = NE;
3393 cmp_code = swap_condition (code);
3395 tem = op0, op0 = op1, op1 = tem;
3403 tem = gen_reg_rtx (cmp_op_mode);
3404 emit_insn (gen_rtx_SET (VOIDmode, tem,
3405 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3408 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3409 op0 = gen_lowpart (cmp_op_mode, tem);
3410 op1 = CONST0_RTX (cmp_op_mode);
3412 local_fast_math = 1;
3415 /* We may be able to use a conditional move directly.
3416 This avoids emitting spurious compares. */
3417 if (signed_comparison_operator (cmp, VOIDmode)
3418 && (!fp_p || local_fast_math)
3419 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
3420 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3422 /* We can't put the comparison inside the conditional move;
3423 emit a compare instruction and put that inside the
3424 conditional move. Make sure we emit only comparisons we have;
3425 swap or reverse as necessary. */
3432 case EQ: case LE: case LT: case LEU: case LTU:
3433 /* We have these compares: */
3437 /* This must be reversed. */
3438 code = reverse_condition (code);
3442 case GE: case GT: case GEU: case GTU:
3443 /* These must be swapped. */
3444 if (op1 != CONST0_RTX (cmp_mode))
3446 code = swap_condition (code);
3447 tem = op0, op0 = op1, op1 = tem;
3457 if (!reg_or_0_operand (op0, DImode))
3458 op0 = force_reg (DImode, op0);
3459 if (!reg_or_8bit_operand (op1, DImode))
3460 op1 = force_reg (DImode, op1);
3463 /* ??? We mark the branch mode to be CCmode to prevent the compare
3464 and cmov from being combined, since the compare insn follows IEEE
3465 rules that the cmov does not. */
3466 if (fp_p && !local_fast_math)
3469 tem = gen_reg_rtx (cmp_op_mode);
3470 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
3471 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
3474 /* Simplify a conditional move of two constants into a setcc with
3475 arithmetic. This is done with a splitter since combine would
3476 just undo the work if done during code generation. It also catches
3477 cases we wouldn't have before cse. */
3480 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
3481 rtx t_rtx, rtx f_rtx)
3483 HOST_WIDE_INT t, f, diff;
3484 enum machine_mode mode;
3485 rtx target, subtarget, tmp;
3487 mode = GET_MODE (dest);
3492 if (((code == NE || code == EQ) && diff < 0)
3493 || (code == GE || code == GT))
3495 code = reverse_condition (code);
3496 diff = t, t = f, f = diff;
3500 subtarget = target = dest;
3503 target = gen_lowpart (DImode, dest);
3504 if (! no_new_pseudos)
3505 subtarget = gen_reg_rtx (DImode);
3509 /* Below, we must be careful to use copy_rtx on target and subtarget
3510 in intermediate insns, as they may be a subreg rtx, which may not
3513 if (f == 0 && exact_log2 (diff) > 0
3514 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3515 viable over a longer latency cmove. On EV5, the E0 slot is a
3516 scarce resource, and on EV4 shift has the same latency as a cmove. */
3517 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3519 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3520 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3522 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3523 GEN_INT (exact_log2 (t)));
3524 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3526 else if (f == 0 && t == -1)
3528 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3529 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3531 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
3533 else if (diff == 1 || diff == 4 || diff == 8)
3537 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3538 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3541 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
3544 add_op = GEN_INT (f);
3545 if (sext_add_operand (add_op, mode))
3547 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3549 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3550 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3562 /* Look up the function X_floating library function name for the
3565 struct xfloating_op GTY(())
3567 const enum rtx_code code;
3568 const char *const GTY((skip)) osf_func;
3569 const char *const GTY((skip)) vms_func;
3573 static GTY(()) struct xfloating_op xfloating_ops[] =
3575 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
3576 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
3577 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
3578 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
3579 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
3580 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
3581 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
3582 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
3583 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
3584 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
3585 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
3586 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
3587 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
3588 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
3589 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
3592 static GTY(()) struct xfloating_op vax_cvt_ops[] =
3594 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
3595 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
3599 alpha_lookup_xfloating_lib_func (enum rtx_code code)
3601 struct xfloating_op *ops = xfloating_ops;
3602 long n = ARRAY_SIZE (xfloating_ops);
3605 /* How irritating. Nothing to key off for the main table. */
3606 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
3609 n = ARRAY_SIZE (vax_cvt_ops);
3612 for (i = 0; i < n; ++i, ++ops)
3613 if (ops->code == code)
3615 rtx func = ops->libcall;
3618 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
3619 ? ops->vms_func : ops->osf_func);
3620 ops->libcall = func;
3628 /* Most X_floating operations take the rounding mode as an argument.
3629 Compute that here. */
3632 alpha_compute_xfloating_mode_arg (enum rtx_code code,
3633 enum alpha_fp_rounding_mode round)
3639 case ALPHA_FPRM_NORM:
3642 case ALPHA_FPRM_MINF:
3645 case ALPHA_FPRM_CHOP:
3648 case ALPHA_FPRM_DYN:
3654 /* XXX For reference, round to +inf is mode = 3. */
3657 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3663 /* Emit an X_floating library function call.
3665 Note that these functions do not follow normal calling conventions:
3666 TFmode arguments are passed in two integer registers (as opposed to
3667 indirect); TFmode return values appear in R16+R17.
3669 FUNC is the function to call.
3670 TARGET is where the output belongs.
3671 OPERANDS are the inputs.
3672 NOPERANDS is the count of inputs.
3673 EQUIV is the expression equivalent for the function.
3677 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
3678 int noperands, rtx equiv)
3680 rtx usage = NULL_RTX, tmp, reg;
3685 for (i = 0; i < noperands; ++i)
3687 switch (GET_MODE (operands[i]))
3690 reg = gen_rtx_REG (TFmode, regno);
3695 reg = gen_rtx_REG (DFmode, regno + 32);
3700 if (GET_CODE (operands[i]) != CONST_INT)
3704 reg = gen_rtx_REG (DImode, regno);
3712 emit_move_insn (reg, operands[i]);
3713 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3716 switch (GET_MODE (target))
3719 reg = gen_rtx_REG (TFmode, 16);
3722 reg = gen_rtx_REG (DFmode, 32);
3725 reg = gen_rtx_REG (DImode, 0);
3731 tmp = gen_rtx_MEM (QImode, func);
3732 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3733 const0_rtx, const0_rtx));
3734 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3735 CONST_OR_PURE_CALL_P (tmp) = 1;
3740 emit_libcall_block (tmp, target, reg, equiv);
3743 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3746 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3750 rtx out_operands[3];
3752 func = alpha_lookup_xfloating_lib_func (code);
3753 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3755 out_operands[0] = operands[1];
3756 out_operands[1] = operands[2];
3757 out_operands[2] = GEN_INT (mode);
3758 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3759 gen_rtx_fmt_ee (code, TFmode, operands[1],
3763 /* Emit an X_floating library function call for a comparison. */
3766 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
3769 rtx out, operands[2];
3771 func = alpha_lookup_xfloating_lib_func (code);
3775 out = gen_reg_rtx (DImode);
3777 /* ??? Strange mode for equiv because what's actually returned
3778 is -1,0,1, not a proper boolean value. */
3779 alpha_emit_xfloating_libcall (func, out, operands, 2,
3780 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3785 /* Emit an X_floating library function call for a conversion. */
3788 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3790 int noperands = 1, mode;
3791 rtx out_operands[2];
3793 enum rtx_code code = orig_code;
3795 if (code == UNSIGNED_FIX)
3798 func = alpha_lookup_xfloating_lib_func (code);
3800 out_operands[0] = operands[1];
3805 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3806 out_operands[1] = GEN_INT (mode);
3809 case FLOAT_TRUNCATE:
3810 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3811 out_operands[1] = GEN_INT (mode);
3818 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3819 gen_rtx_fmt_e (orig_code,
3820 GET_MODE (operands[0]),
3824 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3825 OP[0] into OP[0,1]. Naturally, output operand ordering is
3829 alpha_split_tfmode_pair (rtx operands[4])
3831 if (GET_CODE (operands[1]) == REG)
3833 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3834 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3836 else if (GET_CODE (operands[1]) == MEM)
3838 operands[3] = adjust_address (operands[1], DImode, 8);
3839 operands[2] = adjust_address (operands[1], DImode, 0);
3841 else if (operands[1] == CONST0_RTX (TFmode))
3842 operands[2] = operands[3] = const0_rtx;
3846 if (GET_CODE (operands[0]) == REG)
3848 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3849 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3851 else if (GET_CODE (operands[0]) == MEM)
3853 operands[1] = adjust_address (operands[0], DImode, 8);
3854 operands[0] = adjust_address (operands[0], DImode, 0);
3860 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3861 op2 is a register containing the sign bit, operation is the
3862 logical operation to be performed. */
3865 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3867 rtx high_bit = operands[2];
3871 alpha_split_tfmode_pair (operands);
3873 /* Detect three flavors of operand overlap. */
3875 if (rtx_equal_p (operands[0], operands[2]))
3877 else if (rtx_equal_p (operands[1], operands[2]))
3879 if (rtx_equal_p (operands[0], high_bit))
3886 emit_move_insn (operands[0], operands[2]);
3888 /* ??? If the destination overlaps both source tf and high_bit, then
3889 assume source tf is dead in its entirety and use the other half
3890 for a scratch register. Otherwise "scratch" is just the proper
3891 destination register. */
3892 scratch = operands[move < 2 ? 1 : 3];
3894 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3898 emit_move_insn (operands[0], operands[2]);
3900 emit_move_insn (operands[1], scratch);
3904 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3908 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3909 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3910 lda r3,X(r11) lda r3,X+2(r11)
3911 extwl r1,r3,r1 extql r1,r3,r1
3912 extwh r2,r3,r2 extqh r2,r3,r2
3913 or r1.r2.r1 or r1,r2,r1
3916 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3917 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3918 lda r3,X(r11) lda r3,X(r11)
3919 extll r1,r3,r1 extll r1,r3,r1
3920 extlh r2,r3,r2 extlh r2,r3,r2
3921 or r1.r2.r1 addl r1,r2,r1
3923 quad: ldq_u r1,X(r11)
3932 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3933 HOST_WIDE_INT ofs, int sign)
3935 rtx meml, memh, addr, extl, exth, tmp, mema;
3936 enum machine_mode mode;
3938 meml = gen_reg_rtx (DImode);
3939 memh = gen_reg_rtx (DImode);
3940 addr = gen_reg_rtx (DImode);
3941 extl = gen_reg_rtx (DImode);
3942 exth = gen_reg_rtx (DImode);
3944 mema = XEXP (mem, 0);
3945 if (GET_CODE (mema) == LO_SUM)
3946 mema = force_reg (Pmode, mema);
3948 /* AND addresses cannot be in any alias set, since they may implicitly
3949 alias surrounding code. Ideally we'd have some alias set that
3950 covered all types except those with alignment 8 or higher. */
3952 tmp = change_address (mem, DImode,
3953 gen_rtx_AND (DImode,
3954 plus_constant (mema, ofs),
3956 set_mem_alias_set (tmp, 0);
3957 emit_move_insn (meml, tmp);
3959 tmp = change_address (mem, DImode,
3960 gen_rtx_AND (DImode,
3961 plus_constant (mema, ofs + size - 1),
3963 set_mem_alias_set (tmp, 0);
3964 emit_move_insn (memh, tmp);
3966 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3968 emit_move_insn (addr, plus_constant (mema, -1));
3970 emit_insn (gen_extqh_be (extl, meml, addr));
3971 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3973 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3974 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3975 addr, 1, OPTAB_WIDEN);
3977 else if (sign && size == 2)
3979 emit_move_insn (addr, plus_constant (mema, ofs+2));
3981 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3982 emit_insn (gen_extqh_le (exth, memh, addr));
3984 /* We must use tgt here for the target. Alpha-vms port fails if we use
3985 addr for the target, because addr is marked as a pointer and combine
3986 knows that pointers are always sign-extended 32 bit values. */
3987 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3988 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3989 addr, 1, OPTAB_WIDEN);
3993 if (WORDS_BIG_ENDIAN)
3995 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
3999 emit_insn (gen_extwh_be (extl, meml, addr));
4004 emit_insn (gen_extlh_be (extl, meml, addr));
4009 emit_insn (gen_extqh_be (extl, meml, addr));
4016 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4020 emit_move_insn (addr, plus_constant (mema, ofs));
4021 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4025 emit_insn (gen_extwh_le (exth, memh, addr));
4030 emit_insn (gen_extlh_le (exth, memh, addr));
4035 emit_insn (gen_extqh_le (exth, memh, addr));
4044 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4045 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4050 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
4053 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4056 alpha_expand_unaligned_store (rtx dst, rtx src,
4057 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
4059 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
4061 dstl = gen_reg_rtx (DImode);
4062 dsth = gen_reg_rtx (DImode);
4063 insl = gen_reg_rtx (DImode);
4064 insh = gen_reg_rtx (DImode);
4066 dsta = XEXP (dst, 0);
4067 if (GET_CODE (dsta) == LO_SUM)
4068 dsta = force_reg (Pmode, dsta);
4070 /* AND addresses cannot be in any alias set, since they may implicitly
4071 alias surrounding code. Ideally we'd have some alias set that
4072 covered all types except those with alignment 8 or higher. */
4074 meml = change_address (dst, DImode,
4075 gen_rtx_AND (DImode,
4076 plus_constant (dsta, ofs),
4078 set_mem_alias_set (meml, 0);
4080 memh = change_address (dst, DImode,
4081 gen_rtx_AND (DImode,
4082 plus_constant (dsta, ofs + size - 1),
4084 set_mem_alias_set (memh, 0);
4086 emit_move_insn (dsth, memh);
4087 emit_move_insn (dstl, meml);
4088 if (WORDS_BIG_ENDIAN)
4090 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4092 if (src != const0_rtx)
4097 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4100 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4103 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4106 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4107 GEN_INT (size*8), addr));
4113 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
4117 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4118 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
4122 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
4126 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
4130 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
4132 if (src != const0_rtx)
4134 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4135 GEN_INT (size*8), addr));
4140 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4143 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4146 emit_insn (gen_insql_le (insl, src, addr));
4151 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4156 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4160 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4161 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
4165 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
4170 if (src != const0_rtx)
4172 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4173 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
4176 if (WORDS_BIG_ENDIAN)
4178 emit_move_insn (meml, dstl);
4179 emit_move_insn (memh, dsth);
4183 /* Must store high before low for degenerate case of aligned. */
4184 emit_move_insn (memh, dsth);
4185 emit_move_insn (meml, dstl);
4189 /* The block move code tries to maximize speed by separating loads and
4190 stores at the expense of register pressure: we load all of the data
4191 before we store it back out. There are two secondary effects worth
4192 mentioning, that this speeds copying to/from aligned and unaligned
4193 buffers, and that it makes the code significantly easier to write. */
4195 #define MAX_MOVE_WORDS 8
4197 /* Load an integral number of consecutive unaligned quadwords. */
4200 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
4201 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4203 rtx const im8 = GEN_INT (-8);
4204 rtx const i64 = GEN_INT (64);
4205 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
4206 rtx sreg, areg, tmp, smema;
4209 smema = XEXP (smem, 0);
4210 if (GET_CODE (smema) == LO_SUM)
4211 smema = force_reg (Pmode, smema);
4213 /* Generate all the tmp registers we need. */
4214 for (i = 0; i < words; ++i)
4216 data_regs[i] = out_regs[i];
4217 ext_tmps[i] = gen_reg_rtx (DImode);
4219 data_regs[words] = gen_reg_rtx (DImode);
4222 smem = adjust_address (smem, GET_MODE (smem), ofs);
4224 /* Load up all of the source data. */
4225 for (i = 0; i < words; ++i)
4227 tmp = change_address (smem, DImode,
4228 gen_rtx_AND (DImode,
4229 plus_constant (smema, 8*i),
4231 set_mem_alias_set (tmp, 0);
4232 emit_move_insn (data_regs[i], tmp);
4235 tmp = change_address (smem, DImode,
4236 gen_rtx_AND (DImode,
4237 plus_constant (smema, 8*words - 1),
4239 set_mem_alias_set (tmp, 0);
4240 emit_move_insn (data_regs[words], tmp);
4242 /* Extract the half-word fragments. Unfortunately DEC decided to make
4243 extxh with offset zero a noop instead of zeroing the register, so
4244 we must take care of that edge condition ourselves with cmov. */
4246 sreg = copy_addr_to_reg (smema);
4247 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4249 if (WORDS_BIG_ENDIAN)
4250 emit_move_insn (sreg, plus_constant (sreg, 7));
4251 for (i = 0; i < words; ++i)
4253 if (WORDS_BIG_ENDIAN)
4255 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4256 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4260 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4261 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4263 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4264 gen_rtx_IF_THEN_ELSE (DImode,
4265 gen_rtx_EQ (DImode, areg,
4267 const0_rtx, ext_tmps[i])));
4270 /* Merge the half-words into whole words. */
4271 for (i = 0; i < words; ++i)
4273 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4274 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
4278 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4279 may be NULL to store zeros. */
4282 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
4283 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4285 rtx const im8 = GEN_INT (-8);
4286 rtx const i64 = GEN_INT (64);
4287 rtx ins_tmps[MAX_MOVE_WORDS];
4288 rtx st_tmp_1, st_tmp_2, dreg;
4289 rtx st_addr_1, st_addr_2, dmema;
4292 dmema = XEXP (dmem, 0);
4293 if (GET_CODE (dmema) == LO_SUM)
4294 dmema = force_reg (Pmode, dmema);
4296 /* Generate all the tmp registers we need. */
4297 if (data_regs != NULL)
4298 for (i = 0; i < words; ++i)
4299 ins_tmps[i] = gen_reg_rtx(DImode);
4300 st_tmp_1 = gen_reg_rtx(DImode);
4301 st_tmp_2 = gen_reg_rtx(DImode);
4304 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4306 st_addr_2 = change_address (dmem, DImode,
4307 gen_rtx_AND (DImode,
4308 plus_constant (dmema, words*8 - 1),
4310 set_mem_alias_set (st_addr_2, 0);
4312 st_addr_1 = change_address (dmem, DImode,
4313 gen_rtx_AND (DImode, dmema, im8));
4314 set_mem_alias_set (st_addr_1, 0);
4316 /* Load up the destination end bits. */
4317 emit_move_insn (st_tmp_2, st_addr_2);
4318 emit_move_insn (st_tmp_1, st_addr_1);
4320 /* Shift the input data into place. */
4321 dreg = copy_addr_to_reg (dmema);
4322 if (WORDS_BIG_ENDIAN)
4323 emit_move_insn (dreg, plus_constant (dreg, 7));
4324 if (data_regs != NULL)
4326 for (i = words-1; i >= 0; --i)
4328 if (WORDS_BIG_ENDIAN)
4330 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4331 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4335 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4336 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4339 for (i = words-1; i > 0; --i)
4341 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4342 ins_tmps[i-1], ins_tmps[i-1], 1,
4347 /* Split and merge the ends with the destination data. */
4348 if (WORDS_BIG_ENDIAN)
4350 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
4351 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4355 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
4356 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
4359 if (data_regs != NULL)
4361 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4362 st_tmp_2, 1, OPTAB_WIDEN);
4363 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4364 st_tmp_1, 1, OPTAB_WIDEN);
4368 if (WORDS_BIG_ENDIAN)
4369 emit_move_insn (st_addr_1, st_tmp_1);
4371 emit_move_insn (st_addr_2, st_tmp_2);
4372 for (i = words-1; i > 0; --i)
4374 rtx tmp = change_address (dmem, DImode,
4375 gen_rtx_AND (DImode,
4376 plus_constant(dmema,
4377 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
4379 set_mem_alias_set (tmp, 0);
4380 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
4382 if (WORDS_BIG_ENDIAN)
4383 emit_move_insn (st_addr_2, st_tmp_2);
4385 emit_move_insn (st_addr_1, st_tmp_1);
4389 /* Expand string/block move operations.
4391 operands[0] is the pointer to the destination.
4392 operands[1] is the pointer to the source.
4393 operands[2] is the number of bytes to move.
4394 operands[3] is the alignment. */
4397 alpha_expand_block_move (rtx operands[])
4399 rtx bytes_rtx = operands[2];
4400 rtx align_rtx = operands[3];
4401 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4402 HOST_WIDE_INT bytes = orig_bytes;
4403 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4404 HOST_WIDE_INT dst_align = src_align;
4405 rtx orig_src = operands[1];
4406 rtx orig_dst = operands[0];
4407 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4409 unsigned int i, words, ofs, nregs = 0;
4411 if (orig_bytes <= 0)
4413 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4416 /* Look for additional alignment information from recorded register info. */
4418 tmp = XEXP (orig_src, 0);
4419 if (GET_CODE (tmp) == REG)
4420 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4421 else if (GET_CODE (tmp) == PLUS
4422 && GET_CODE (XEXP (tmp, 0)) == REG
4423 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4425 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4426 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4430 if (a >= 64 && c % 8 == 0)
4432 else if (a >= 32 && c % 4 == 0)
4434 else if (a >= 16 && c % 2 == 0)
4439 tmp = XEXP (orig_dst, 0);
4440 if (GET_CODE (tmp) == REG)
4441 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4442 else if (GET_CODE (tmp) == PLUS
4443 && GET_CODE (XEXP (tmp, 0)) == REG
4444 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4446 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4447 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4451 if (a >= 64 && c % 8 == 0)
4453 else if (a >= 32 && c % 4 == 0)
4455 else if (a >= 16 && c % 2 == 0)
4460 /* Load the entire block into registers. */
4461 if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
4463 enum machine_mode mode;
4465 tmp = XEXP (XEXP (orig_src, 0), 0);
4467 /* Don't use the existing register if we're reading more than
4468 is held in the register. Nor if there is not a mode that
4469 handles the exact size. */
4470 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4471 if (GET_CODE (tmp) == REG
4473 && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
4477 data_regs[nregs] = gen_lowpart (DImode, tmp);
4478 data_regs[nregs + 1] = gen_highpart (DImode, tmp);
4482 data_regs[nregs++] = gen_lowpart (mode, tmp);
4487 /* No appropriate mode; fall back on memory. */
4488 orig_src = replace_equiv_address (orig_src,
4489 copy_addr_to_reg (XEXP (orig_src, 0)));
4490 src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4494 if (src_align >= 64 && bytes >= 8)
4498 for (i = 0; i < words; ++i)
4499 data_regs[nregs + i] = gen_reg_rtx (DImode);
4501 for (i = 0; i < words; ++i)
4502 emit_move_insn (data_regs[nregs + i],
4503 adjust_address (orig_src, DImode, ofs + i * 8));
4510 if (src_align >= 32 && bytes >= 4)
4514 for (i = 0; i < words; ++i)
4515 data_regs[nregs + i] = gen_reg_rtx (SImode);
4517 for (i = 0; i < words; ++i)
4518 emit_move_insn (data_regs[nregs + i],
4519 adjust_address (orig_src, SImode, ofs + i * 4));
4530 for (i = 0; i < words+1; ++i)
4531 data_regs[nregs + i] = gen_reg_rtx (DImode);
4533 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4541 if (! TARGET_BWX && bytes >= 4)
4543 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
4544 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
4551 if (src_align >= 16)
4554 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4555 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
4558 } while (bytes >= 2);
4560 else if (! TARGET_BWX)
4562 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4563 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
4571 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
4572 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
4579 if (nregs > ARRAY_SIZE (data_regs))
4582 /* Now save it back out again. */
4586 if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
4588 enum machine_mode mode;
4589 tmp = XEXP (XEXP (orig_dst, 0), 0);
4591 mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
4592 if (GET_CODE (tmp) == REG && GET_MODE (tmp) == mode)
4596 emit_move_insn (tmp, data_regs[0]);
4601 else if (nregs == 2 && mode == TImode)
4603 /* Undo the subregging done above when copying between
4604 two TImode registers. */
4605 if (GET_CODE (data_regs[0]) == SUBREG
4606 && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
4607 emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
4613 emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
4614 emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
4618 emit_no_conflict_block (seq, tmp, data_regs[0],
4619 data_regs[1], NULL_RTX);
4627 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4628 /* ??? Optimize mode < dst_mode with strict_low_part. */
4630 /* No appropriate mode; fall back on memory. We can speed things
4631 up by recognizing extra alignment information. */
4632 orig_dst = replace_equiv_address (orig_dst,
4633 copy_addr_to_reg (XEXP (orig_dst, 0)));
4634 dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4637 /* Write out the data in whatever chunks reading the source allowed. */
4638 if (dst_align >= 64)
4640 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4642 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4649 if (dst_align >= 32)
4651 /* If the source has remaining DImode regs, write them out in
4653 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4655 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4656 NULL_RTX, 1, OPTAB_WIDEN);
4658 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4659 gen_lowpart (SImode, data_regs[i]));
4660 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4661 gen_lowpart (SImode, tmp));
4666 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4668 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4675 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4677 /* Write out a remaining block of words using unaligned methods. */
4679 for (words = 1; i + words < nregs; words++)
4680 if (GET_MODE (data_regs[i + words]) != DImode)
4684 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4686 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4693 /* Due to the above, this won't be aligned. */
4694 /* ??? If we have more than one of these, consider constructing full
4695 words in registers and using alpha_expand_unaligned_store_words. */
4696 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4698 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4703 if (dst_align >= 16)
4704 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4706 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4711 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4713 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4718 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4720 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4734 alpha_expand_block_clear (rtx operands[])
4736 rtx bytes_rtx = operands[1];
4737 rtx align_rtx = operands[2];
4738 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4739 HOST_WIDE_INT bytes = orig_bytes;
4740 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4741 HOST_WIDE_INT alignofs = 0;
4742 rtx orig_dst = operands[0];
4744 int i, words, ofs = 0;
4746 if (orig_bytes <= 0)
4748 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4751 /* Look for stricter alignment. */
4752 tmp = XEXP (orig_dst, 0);
4753 if (GET_CODE (tmp) == REG)
4754 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4755 else if (GET_CODE (tmp) == PLUS
4756 && GET_CODE (XEXP (tmp, 0)) == REG
4757 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4759 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4760 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4765 align = a, alignofs = 8 - c % 8;
4767 align = a, alignofs = 4 - c % 4;
4769 align = a, alignofs = 2 - c % 2;
4772 else if (GET_CODE (tmp) == ADDRESSOF)
4774 enum machine_mode mode;
4776 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4777 if (GET_MODE (XEXP (tmp, 0)) == mode)
4779 emit_move_insn (XEXP (tmp, 0), const0_rtx);
4783 /* No appropriate mode; fall back on memory. */
4784 orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
4785 align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
4788 /* Handle an unaligned prefix first. */
4792 #if HOST_BITS_PER_WIDE_INT >= 64
4793 /* Given that alignofs is bounded by align, the only time BWX could
4794 generate three stores is for a 7 byte fill. Prefer two individual
4795 stores over a load/mask/store sequence. */
4796 if ((!TARGET_BWX || alignofs == 7)
4798 && !(alignofs == 4 && bytes >= 4))
4800 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4801 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4805 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4806 set_mem_alias_set (mem, 0);
4808 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4809 if (bytes < alignofs)
4811 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4822 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4823 NULL_RTX, 1, OPTAB_WIDEN);
4825 emit_move_insn (mem, tmp);
4829 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4831 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4836 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4838 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4843 if (alignofs == 4 && bytes >= 4)
4845 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4851 /* If we've not used the extra lead alignment information by now,
4852 we won't be able to. Downgrade align to match what's left over. */
4855 alignofs = alignofs & -alignofs;
4856 align = MIN (align, alignofs * BITS_PER_UNIT);
4860 /* Handle a block of contiguous long-words. */
4862 if (align >= 64 && bytes >= 8)
4866 for (i = 0; i < words; ++i)
4867 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4874 /* If the block is large and appropriately aligned, emit a single
4875 store followed by a sequence of stq_u insns. */
4877 if (align >= 32 && bytes > 16)
4881 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4885 orig_dsta = XEXP (orig_dst, 0);
4886 if (GET_CODE (orig_dsta) == LO_SUM)
4887 orig_dsta = force_reg (Pmode, orig_dsta);
4890 for (i = 0; i < words; ++i)
4893 = change_address (orig_dst, DImode,
4894 gen_rtx_AND (DImode,
4895 plus_constant (orig_dsta, ofs + i*8),
4897 set_mem_alias_set (mem, 0);
4898 emit_move_insn (mem, const0_rtx);
4901 /* Depending on the alignment, the first stq_u may have overlapped
4902 with the initial stl, which means that the last stq_u didn't
4903 write as much as it would appear. Leave those questionable bytes
4905 bytes -= words * 8 - 4;
4906 ofs += words * 8 - 4;
4909 /* Handle a smaller block of aligned words. */
4911 if ((align >= 64 && bytes == 4)
4912 || (align == 32 && bytes >= 4))
4916 for (i = 0; i < words; ++i)
4917 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4924 /* An unaligned block uses stq_u stores for as many as possible. */
4930 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4936 /* Next clean up any trailing pieces. */
4938 #if HOST_BITS_PER_WIDE_INT >= 64
4939 /* Count the number of bits in BYTES for which aligned stores could
4942 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4946 /* If we have appropriate alignment (and it wouldn't take too many
4947 instructions otherwise), mask out the bytes we need. */
4948 if (TARGET_BWX ? words > 2 : bytes > 0)
4955 mem = adjust_address (orig_dst, DImode, ofs);
4956 set_mem_alias_set (mem, 0);
4958 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4960 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4961 NULL_RTX, 1, OPTAB_WIDEN);
4963 emit_move_insn (mem, tmp);
4966 else if (align >= 32 && bytes < 4)
4971 mem = adjust_address (orig_dst, SImode, ofs);
4972 set_mem_alias_set (mem, 0);
4974 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4976 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4977 NULL_RTX, 1, OPTAB_WIDEN);
4979 emit_move_insn (mem, tmp);
4985 if (!TARGET_BWX && bytes >= 4)
4987 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4997 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
5001 } while (bytes >= 2);
5003 else if (! TARGET_BWX)
5005 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
5013 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
5021 /* Returns a mask so that zap(x, value) == x & mask. */
5024 alpha_expand_zap_mask (HOST_WIDE_INT value)
5029 if (HOST_BITS_PER_WIDE_INT >= 64)
5031 HOST_WIDE_INT mask = 0;
5033 for (i = 7; i >= 0; --i)
5036 if (!((value >> i) & 1))
5040 result = gen_int_mode (mask, DImode);
5042 else if (HOST_BITS_PER_WIDE_INT == 32)
5044 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
5046 for (i = 7; i >= 4; --i)
5049 if (!((value >> i) & 1))
5053 for (i = 3; i >= 0; --i)
5056 if (!((value >> i) & 1))
5060 result = immed_double_const (mask_lo, mask_hi, DImode);
5069 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
5070 enum machine_mode mode,
5071 rtx op0, rtx op1, rtx op2)
5073 op0 = gen_lowpart (mode, op0);
5075 if (op1 == const0_rtx)
5076 op1 = CONST0_RTX (mode);
5078 op1 = gen_lowpart (mode, op1);
5080 if (op2 == const0_rtx)
5081 op2 = CONST0_RTX (mode);
5083 op2 = gen_lowpart (mode, op2);
5085 emit_insn ((*gen) (op0, op1, op2));
5088 /* Adjust the cost of a scheduling dependency. Return the new cost of
5089 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5092 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
5094 enum attr_type insn_type, dep_insn_type;
5096 /* If the dependence is an anti-dependence, there is no cost. For an
5097 output dependence, there is sometimes a cost, but it doesn't seem
5098 worth handling those few cases. */
5099 if (REG_NOTE_KIND (link) != 0)
5102 /* If we can't recognize the insns, we can't really do anything. */
5103 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5106 insn_type = get_attr_type (insn);
5107 dep_insn_type = get_attr_type (dep_insn);
5109 /* Bring in the user-defined memory latency. */
5110 if (dep_insn_type == TYPE_ILD
5111 || dep_insn_type == TYPE_FLD
5112 || dep_insn_type == TYPE_LDSYM)
5113 cost += alpha_memory_latency-1;
5115 /* Everything else handled in DFA bypasses now. */
5120 /* The number of instructions that can be issued per cycle. */
5123 alpha_issue_rate (void)
5125 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5129 alpha_use_dfa_pipeline_interface (void)
5134 /* How many alternative schedules to try. This should be as wide as the
5135 scheduling freedom in the DFA, but no wider. Making this value too
5136 large results extra work for the scheduler.
5138 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5139 alternative schedules. For EV5, we can choose between E0/E1 and
5140 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5143 alpha_multipass_dfa_lookahead (void)
5145 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5148 /* Machine-specific function data. */
5150 struct machine_function GTY(())
5153 /* List of call information words for calls from this function. */
5154 struct rtx_def *first_ciw;
5155 struct rtx_def *last_ciw;
5158 /* List of deferred case vectors. */
5159 struct rtx_def *addr_list;
5162 const char *some_ld_name;
5165 /* How to allocate a 'struct machine_function'. */
5167 static struct machine_function *
5168 alpha_init_machine_status (void)
5170 return ((struct machine_function *)
5171 ggc_alloc_cleared (sizeof (struct machine_function)));
5174 /* Functions to save and restore alpha_return_addr_rtx. */
5176 /* Start the ball rolling with RETURN_ADDR_RTX. */
5179 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5184 return get_hard_reg_initial_val (Pmode, REG_RA);
5187 /* Return or create a pseudo containing the gp value for the current
5188 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5191 alpha_gp_save_rtx (void)
5193 rtx r = get_hard_reg_initial_val (DImode, 29);
5194 if (GET_CODE (r) != MEM)
5195 r = gen_mem_addressof (r, NULL_TREE, /*rescan=*/true);
5200 alpha_ra_ever_killed (void)
5204 if (!has_hard_reg_initial_val (Pmode, REG_RA))
5205 return regs_ever_live[REG_RA];
5207 push_topmost_sequence ();
5209 pop_topmost_sequence ();
5211 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
5215 /* Return the trap mode suffix applicable to the current
5216 instruction, or NULL. */
5219 get_trap_mode_suffix (void)
5221 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
5225 case TRAP_SUFFIX_NONE:
5228 case TRAP_SUFFIX_SU:
5229 if (alpha_fptm >= ALPHA_FPTM_SU)
5233 case TRAP_SUFFIX_SUI:
5234 if (alpha_fptm >= ALPHA_FPTM_SUI)
5238 case TRAP_SUFFIX_V_SV:
5246 case ALPHA_FPTM_SUI:
5251 case TRAP_SUFFIX_V_SV_SVI:
5260 case ALPHA_FPTM_SUI:
5265 case TRAP_SUFFIX_U_SU_SUI:
5274 case ALPHA_FPTM_SUI:
5282 /* Return the rounding mode suffix applicable to the current
5283 instruction, or NULL. */
5286 get_round_mode_suffix (void)
5288 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5292 case ROUND_SUFFIX_NONE:
5294 case ROUND_SUFFIX_NORMAL:
5297 case ALPHA_FPRM_NORM:
5299 case ALPHA_FPRM_MINF:
5301 case ALPHA_FPRM_CHOP:
5303 case ALPHA_FPRM_DYN:
5308 case ROUND_SUFFIX_C:
5314 /* Locate some local-dynamic symbol still in use by this function
5315 so that we can print its name in some movdi_er_tlsldm pattern. */
5318 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5322 if (GET_CODE (x) == SYMBOL_REF
5323 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5325 cfun->machine->some_ld_name = XSTR (x, 0);
5333 get_some_local_dynamic_name (void)
5337 if (cfun->machine->some_ld_name)
5338 return cfun->machine->some_ld_name;
5340 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5342 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5343 return cfun->machine->some_ld_name;
5348 /* Print an operand. Recognize special options, documented below. */
5351 print_operand (FILE *file, rtx x, int code)
5358 /* Print the assembler name of the current function. */
5359 assemble_name (file, alpha_fnname);
5363 assemble_name (file, get_some_local_dynamic_name ());
5368 const char *trap = get_trap_mode_suffix ();
5369 const char *round = get_round_mode_suffix ();
5372 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5373 (trap ? trap : ""), (round ? round : ""));
5378 /* Generates single precision instruction suffix. */
5379 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5383 /* Generates double precision instruction suffix. */
5384 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5388 /* Generates a nop after a noreturn call at the very end of the
5390 if (next_real_insn (current_output_insn) == 0)
5391 fprintf (file, "\n\tnop");
5395 if (alpha_this_literal_sequence_number == 0)
5396 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5397 fprintf (file, "%d", alpha_this_literal_sequence_number);
5401 if (alpha_this_gpdisp_sequence_number == 0)
5402 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5403 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5407 if (GET_CODE (x) == HIGH)
5408 output_addr_const (file, XEXP (x, 0));
5410 output_operand_lossage ("invalid %%H value");
5417 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5419 x = XVECEXP (x, 0, 0);
5420 lituse = "lituse_tlsgd";
5422 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5424 x = XVECEXP (x, 0, 0);
5425 lituse = "lituse_tlsldm";
5427 else if (GET_CODE (x) == CONST_INT)
5428 lituse = "lituse_jsr";
5431 output_operand_lossage ("invalid %%J value");
5435 if (x != const0_rtx)
5436 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5441 /* If this operand is the constant zero, write it as "$31". */
5442 if (GET_CODE (x) == REG)
5443 fprintf (file, "%s", reg_names[REGNO (x)]);
5444 else if (x == CONST0_RTX (GET_MODE (x)))
5445 fprintf (file, "$31");
5447 output_operand_lossage ("invalid %%r value");
5451 /* Similar, but for floating-point. */
5452 if (GET_CODE (x) == REG)
5453 fprintf (file, "%s", reg_names[REGNO (x)]);
5454 else if (x == CONST0_RTX (GET_MODE (x)))
5455 fprintf (file, "$f31");
5457 output_operand_lossage ("invalid %%R value");
5461 /* Write the 1's complement of a constant. */
5462 if (GET_CODE (x) != CONST_INT)
5463 output_operand_lossage ("invalid %%N value");
5465 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5469 /* Write 1 << C, for a constant C. */
5470 if (GET_CODE (x) != CONST_INT)
5471 output_operand_lossage ("invalid %%P value");
5473 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5477 /* Write the high-order 16 bits of a constant, sign-extended. */
5478 if (GET_CODE (x) != CONST_INT)
5479 output_operand_lossage ("invalid %%h value");
5481 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5485 /* Write the low-order 16 bits of a constant, sign-extended. */
5486 if (GET_CODE (x) != CONST_INT)
5487 output_operand_lossage ("invalid %%L value");
5489 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5490 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5494 /* Write mask for ZAP insn. */
5495 if (GET_CODE (x) == CONST_DOUBLE)
5497 HOST_WIDE_INT mask = 0;
5498 HOST_WIDE_INT value;
5500 value = CONST_DOUBLE_LOW (x);
5501 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5506 value = CONST_DOUBLE_HIGH (x);
5507 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5510 mask |= (1 << (i + sizeof (int)));
5512 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5515 else if (GET_CODE (x) == CONST_INT)
5517 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5519 for (i = 0; i < 8; i++, value >>= 8)
5523 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5526 output_operand_lossage ("invalid %%m value");
5530 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5531 if (GET_CODE (x) != CONST_INT
5532 || (INTVAL (x) != 8 && INTVAL (x) != 16
5533 && INTVAL (x) != 32 && INTVAL (x) != 64))
5534 output_operand_lossage ("invalid %%M value");
5536 fprintf (file, "%s",
5537 (INTVAL (x) == 8 ? "b"
5538 : INTVAL (x) == 16 ? "w"
5539 : INTVAL (x) == 32 ? "l"
5544 /* Similar, except do it from the mask. */
5545 if (GET_CODE (x) == CONST_INT)
5547 HOST_WIDE_INT value = INTVAL (x);
5554 if (value == 0xffff)
5559 if (value == 0xffffffff)
5570 else if (HOST_BITS_PER_WIDE_INT == 32
5571 && GET_CODE (x) == CONST_DOUBLE
5572 && CONST_DOUBLE_LOW (x) == 0xffffffff
5573 && CONST_DOUBLE_HIGH (x) == 0)
5578 output_operand_lossage ("invalid %%U value");
5582 /* Write the constant value divided by 8 for little-endian mode or
5583 (56 - value) / 8 for big-endian mode. */
5585 if (GET_CODE (x) != CONST_INT
5586 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5589 || (INTVAL (x) & 7) != 0)
5590 output_operand_lossage ("invalid %%s value");
5592 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5594 ? (56 - INTVAL (x)) / 8
5599 /* Same, except compute (64 - c) / 8 */
5601 if (GET_CODE (x) != CONST_INT
5602 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5603 && (INTVAL (x) & 7) != 8)
5604 output_operand_lossage ("invalid %%s value");
5606 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5611 /* On Unicos/Mk systems: use a DEX expression if the symbol
5612 clashes with a register name. */
5613 int dex = unicosmk_need_dex (x);
5615 fprintf (file, "DEX(%d)", dex);
5617 output_addr_const (file, x);
5621 case 'C': case 'D': case 'c': case 'd':
5622 /* Write out comparison name. */
5624 enum rtx_code c = GET_CODE (x);
5626 if (!COMPARISON_P (x))
5627 output_operand_lossage ("invalid %%C value");
5629 else if (code == 'D')
5630 c = reverse_condition (c);
5631 else if (code == 'c')
5632 c = swap_condition (c);
5633 else if (code == 'd')
5634 c = swap_condition (reverse_condition (c));
5637 fprintf (file, "ule");
5639 fprintf (file, "ult");
5640 else if (c == UNORDERED)
5641 fprintf (file, "un");
5643 fprintf (file, "%s", GET_RTX_NAME (c));
5648 /* Write the divide or modulus operator. */
5649 switch (GET_CODE (x))
5652 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5655 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5658 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5661 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5664 output_operand_lossage ("invalid %%E value");
5670 /* Write "_u" for unaligned access. */
5671 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5672 fprintf (file, "_u");
5676 if (GET_CODE (x) == REG)
5677 fprintf (file, "%s", reg_names[REGNO (x)]);
5678 else if (GET_CODE (x) == MEM)
5679 output_address (XEXP (x, 0));
5680 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5682 switch (XINT (XEXP (x, 0), 1))
5686 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5689 output_operand_lossage ("unknown relocation unspec");
5694 output_addr_const (file, x);
5698 output_operand_lossage ("invalid %%xn code");
5703 print_operand_address (FILE *file, rtx addr)
5706 HOST_WIDE_INT offset = 0;
5708 if (GET_CODE (addr) == AND)
5709 addr = XEXP (addr, 0);
5711 if (GET_CODE (addr) == PLUS
5712 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
5714 offset = INTVAL (XEXP (addr, 1));
5715 addr = XEXP (addr, 0);
5718 if (GET_CODE (addr) == LO_SUM)
5720 const char *reloc16, *reloclo;
5721 rtx op1 = XEXP (addr, 1);
5723 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5725 op1 = XEXP (op1, 0);
5726 switch (XINT (op1, 1))
5730 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5734 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5737 output_operand_lossage ("unknown relocation unspec");
5741 output_addr_const (file, XVECEXP (op1, 0, 0));
5746 reloclo = "gprellow";
5747 output_addr_const (file, op1);
5751 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5753 addr = XEXP (addr, 0);
5754 if (GET_CODE (addr) == REG)
5755 basereg = REGNO (addr);
5756 else if (GET_CODE (addr) == SUBREG
5757 && GET_CODE (SUBREG_REG (addr)) == REG)
5758 basereg = subreg_regno (addr);
5762 fprintf (file, "($%d)\t\t!%s", basereg,
5763 (basereg == 29 ? reloc16 : reloclo));
5767 if (GET_CODE (addr) == REG)
5768 basereg = REGNO (addr);
5769 else if (GET_CODE (addr) == SUBREG
5770 && GET_CODE (SUBREG_REG (addr)) == REG)
5771 basereg = subreg_regno (addr);
5772 else if (GET_CODE (addr) == CONST_INT)
5773 offset = INTVAL (addr);
5775 #if TARGET_ABI_OPEN_VMS
5776 else if (GET_CODE (addr) == SYMBOL_REF)
5778 fprintf (file, "%s", XSTR (addr, 0));
5781 else if (GET_CODE (addr) == CONST
5782 && GET_CODE (XEXP (addr, 0)) == PLUS
5783 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5785 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5786 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5787 INTVAL (XEXP (XEXP (addr, 0), 1)));
5795 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5798 /* Emit RTL insns to initialize the variable parts of a trampoline at
5799 TRAMP. FNADDR is an RTX for the address of the function's pure
5800 code. CXT is an RTX for the static chain value for the function.
5802 The three offset parameters are for the individual template's
5803 layout. A JMPOFS < 0 indicates that the trampoline does not
5804 contain instructions at all.
5806 We assume here that a function will be called many more times than
5807 its address is taken (e.g., it might be passed to qsort), so we
5808 take the trouble to initialize the "hint" field in the JMP insn.
5809 Note that the hint field is PC (new) + 4 * bits 13:0. */
5812 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
5813 int fnofs, int cxtofs, int jmpofs)
5815 rtx temp, temp1, addr;
5816 /* VMS really uses DImode pointers in memory at this point. */
5817 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
5819 #ifdef POINTERS_EXTEND_UNSIGNED
5820 fnaddr = convert_memory_address (mode, fnaddr);
5821 cxt = convert_memory_address (mode, cxt);
5824 /* Store function address and CXT. */
5825 addr = memory_address (mode, plus_constant (tramp, fnofs));
5826 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
5827 addr = memory_address (mode, plus_constant (tramp, cxtofs));
5828 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
5830 /* This has been disabled since the hint only has a 32k range, and in
5831 no existing OS is the stack within 32k of the text segment. */
5832 if (0 && jmpofs >= 0)
5834 /* Compute hint value. */
5835 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
5836 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
5838 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
5839 build_int_2 (2, 0), NULL_RTX, 1);
5840 temp = expand_and (SImode, gen_lowpart (SImode, temp),
5841 GEN_INT (0x3fff), 0);
5843 /* Merge in the hint. */
5844 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
5845 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
5846 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
5847 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
5849 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
5852 #ifdef TRANSFER_FROM_TRAMPOLINE
5853 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5854 0, VOIDmode, 1, tramp, Pmode);
5858 emit_insn (gen_imb ());
5861 /* Determine where to put an argument to a function.
5862 Value is zero to push the argument on the stack,
5863 or a hard register in which to store the argument.
5865 MODE is the argument's machine mode.
5866 TYPE is the data type of the argument (as a tree).
5867 This is null for libcalls where that information may
5869 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5870 the preceding args and about the function being called.
5871 NAMED is nonzero if this argument is a named parameter
5872 (otherwise it is an extra parameter matching an ellipsis).
5874 On Alpha the first 6 words of args are normally in registers
5875 and the rest are pushed. */
5878 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5879 int named ATTRIBUTE_UNUSED)
5884 /* Don't get confused and pass small structures in FP registers. */
5885 if (type && AGGREGATE_TYPE_P (type))
5889 #ifdef ENABLE_CHECKING
5890 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5892 if (COMPLEX_MODE_P (mode))
5896 /* Set up defaults for FP operands passed in FP registers, and
5897 integral operands passed in integer registers. */
5898 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5904 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5905 the three platforms, so we can't avoid conditional compilation. */
5906 #if TARGET_ABI_OPEN_VMS
5908 if (mode == VOIDmode)
5909 return alpha_arg_info_reg_val (cum);
5911 num_args = cum.num_args;
5912 if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
5915 #elif TARGET_ABI_UNICOSMK
5919 /* If this is the last argument, generate the call info word (CIW). */
5920 /* ??? We don't include the caller's line number in the CIW because
5921 I don't know how to determine it if debug infos are turned off. */
5922 if (mode == VOIDmode)
5931 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5932 if (cum.reg_args_type[i])
5933 lo |= (1 << (7 - i));
5935 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5938 lo |= cum.num_reg_words;
5940 #if HOST_BITS_PER_WIDE_INT == 32
5941 hi = (cum.num_args << 20) | cum.num_arg_words;
5943 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5944 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5947 ciw = immed_double_const (lo, hi, DImode);
5949 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5950 UNSPEC_UMK_LOAD_CIW);
5953 size = ALPHA_ARG_SIZE (mode, type, named);
5954 num_args = cum.num_reg_words;
5955 if (MUST_PASS_IN_STACK (mode, type)
5956 || cum.num_reg_words + size > 6 || cum.force_stack)
5958 else if (type && TYPE_MODE (type) == BLKmode)
5962 reg1 = gen_rtx_REG (DImode, num_args + 16);
5963 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5965 /* The argument fits in two registers. Note that we still need to
5966 reserve a register for empty structures. */
5970 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5973 reg2 = gen_rtx_REG (DImode, num_args + 17);
5974 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5975 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5979 #elif TARGET_ABI_OSF
5985 /* VOID is passed as a special flag for "last argument". */
5986 if (type == void_type_node)
5988 else if (MUST_PASS_IN_STACK (mode, type))
5990 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
5994 #error Unhandled ABI
5997 return gen_rtx_REG (mode, num_args + basereg);
6000 /* Return true if TYPE must be returned in memory, instead of in registers. */
6003 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
6005 enum machine_mode mode = VOIDmode;
6010 mode = TYPE_MODE (type);
6012 /* All aggregates are returned in memory. */
6013 if (AGGREGATE_TYPE_P (type))
6017 size = GET_MODE_SIZE (mode);
6018 switch (GET_MODE_CLASS (mode))
6020 case MODE_VECTOR_FLOAT:
6021 /* Pass all float vectors in memory, like an aggregate. */
6024 case MODE_COMPLEX_FLOAT:
6025 /* We judge complex floats on the size of their element,
6026 not the size of the whole type. */
6027 size = GET_MODE_UNIT_SIZE (mode);
6032 case MODE_COMPLEX_INT:
6033 case MODE_VECTOR_INT:
6037 /* ??? We get called on all sorts of random stuff from
6038 aggregate_value_p. We can't abort, but it's not clear
6039 what's safe to return. Pretend it's a struct I guess. */
6043 /* Otherwise types must fit in one register. */
6044 return size > UNITS_PER_WORD;
6047 /* Define how to find the value returned by a function. VALTYPE is the
6048 data type of the value (as a tree). If the precise function being
6049 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
6050 MODE is set instead of VALTYPE for libcalls.
6052 On Alpha the value is found in $0 for integer functions and
6053 $f0 for floating-point functions. */
6056 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6057 enum machine_mode mode)
6059 unsigned int regnum;
6060 enum mode_class class;
6062 #ifdef ENABLE_CHECKING
6063 if (valtype && alpha_return_in_memory (valtype, func))
6068 mode = TYPE_MODE (valtype);
6070 class = GET_MODE_CLASS (mode);
6074 /* Do the same thing as PROMOTE_MODE. */
6078 case MODE_COMPLEX_INT:
6079 case MODE_VECTOR_INT:
6087 case MODE_COMPLEX_FLOAT:
6089 enum machine_mode cmode = GET_MODE_INNER (mode);
6091 return gen_rtx_PARALLEL
6094 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
6096 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
6097 GEN_INT (GET_MODE_SIZE (cmode)))));
6104 return gen_rtx_REG (mode, regnum);
6107 /* TCmode complex values are passed by invisible reference. We
6108 should not split these values. */
6111 alpha_split_complex_arg (tree type)
6113 return TYPE_MODE (type) != TCmode;
6117 alpha_build_builtin_va_list (void)
6119 tree base, ofs, space, record, type_decl;
6121 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6122 return ptr_type_node;
6124 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6125 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6126 TREE_CHAIN (record) = type_decl;
6127 TYPE_NAME (record) = type_decl;
6129 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6131 /* Dummy field to prevent alignment warnings. */
6132 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
6133 DECL_FIELD_CONTEXT (space) = record;
6134 DECL_ARTIFICIAL (space) = 1;
6135 DECL_IGNORED_P (space) = 1;
6137 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6139 DECL_FIELD_CONTEXT (ofs) = record;
6140 TREE_CHAIN (ofs) = space;
6142 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6144 DECL_FIELD_CONTEXT (base) = record;
6145 TREE_CHAIN (base) = ofs;
6147 TYPE_FIELDS (record) = base;
6148 layout_type (record);
6153 /* Perform any needed actions needed for a function that is receiving a
6154 variable number of arguments. */
6157 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
6158 enum machine_mode mode ATTRIBUTE_UNUSED,
6159 tree type ATTRIBUTE_UNUSED,
6160 int *pretend_size, int no_rtl)
6162 #if TARGET_ABI_UNICOSMK
6163 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6164 arguments on the stack. Unfortunately, it doesn't always store the first
6165 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6166 with stdargs as we always have at least one named argument there. */
6167 int num_reg_words = pcum->num_reg_words;
6168 if (num_reg_words < 6)
6172 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
6173 emit_insn (gen_arg_home_umk ());
6177 #elif TARGET_ABI_OPEN_VMS
6178 /* For VMS, we allocate space for all 6 arg registers plus a count.
6180 However, if NO registers need to be saved, don't allocate any space.
6181 This is not only because we won't need the space, but because AP
6182 includes the current_pretend_args_size and we don't want to mess up
6183 any ap-relative addresses already made. */
6184 if (pcum->num_args < 6)
6188 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6189 emit_insn (gen_arg_home ());
6191 *pretend_size = 7 * UNITS_PER_WORD;
6194 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6195 only push those that are remaining. However, if NO registers need to
6196 be saved, don't allocate any space. This is not only because we won't
6197 need the space, but because AP includes the current_pretend_args_size
6198 and we don't want to mess up any ap-relative addresses already made.
6200 If we are not to use the floating-point registers, save the integer
6201 registers where we would put the floating-point registers. This is
6202 not the most efficient way to implement varargs with just one register
6203 class, but it isn't worth doing anything more efficient in this rare
6205 CUMULATIVE_ARGS cum = *pcum;
6212 int set = get_varargs_alias_set ();
6215 tmp = gen_rtx_MEM (BLKmode,
6216 plus_constant (virtual_incoming_args_rtx,
6217 (cum + 6) * UNITS_PER_WORD));
6218 set_mem_alias_set (tmp, set);
6219 move_block_from_reg (16 + cum, tmp, 6 - cum);
6221 tmp = gen_rtx_MEM (BLKmode,
6222 plus_constant (virtual_incoming_args_rtx,
6223 cum * UNITS_PER_WORD));
6224 set_mem_alias_set (tmp, set);
6225 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
6228 *pretend_size = 12 * UNITS_PER_WORD;
6233 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6235 HOST_WIDE_INT offset;
6236 tree t, offset_field, base_field;
6238 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6241 if (TARGET_ABI_UNICOSMK)
6242 std_expand_builtin_va_start (valist, nextarg);
6244 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6245 up by 48, storing fp arg registers in the first 48 bytes, and the
6246 integer arg registers in the next 48 bytes. This is only done,
6247 however, if any integer registers need to be stored.
6249 If no integer registers need be stored, then we must subtract 48
6250 in order to account for the integer arg registers which are counted
6251 in argsize above, but which are not actually stored on the stack.
6252 Must further be careful here about structures straddling the last
6253 integer argument register; that futzes with pretend_args_size,
6254 which changes the meaning of AP. */
6257 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6259 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
6261 if (TARGET_ABI_OPEN_VMS)
6263 nextarg = plus_constant (nextarg, offset);
6264 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6265 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6266 make_tree (ptr_type_node, nextarg));
6267 TREE_SIDE_EFFECTS (t) = 1;
6269 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6273 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6274 offset_field = TREE_CHAIN (base_field);
6276 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6277 valist, base_field, NULL_TREE);
6278 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6279 valist, offset_field, NULL_TREE);
6281 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6282 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6283 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6284 TREE_SIDE_EFFECTS (t) = 1;
6285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6287 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6288 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6289 TREE_SIDE_EFFECTS (t) = 1;
6290 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6295 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, tree *pre_p)
6297 tree type_size, ptr_type, addend, t, addr, internal_post;
6300 /* If the type could not be passed in registers, skip the block
6301 reserved for the registers. */
6302 if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
6304 t = fold_convert (TREE_TYPE (offset), build_int_2 (6*8, 0));
6305 t = build (MODIFY_EXPR, TREE_TYPE (offset), offset,
6306 build (MAX_EXPR, TREE_TYPE (offset), offset, t));
6307 gimplify_and_add (t, pre_p);
6311 ptr_type = build_pointer_type (type);
6314 if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
6317 ptr_type = build_pointer_type (type);
6320 else if (TREE_CODE (type) == COMPLEX_TYPE)
6322 tree real_part, imag_part, real_temp;
6324 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6327 /* Copy the value into a new temporary, lest the formal temporary
6328 be reused out from under us. */
6329 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
6331 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6334 return build (COMPLEX_EXPR, type, real_temp, imag_part);
6336 else if (TREE_CODE (type) == REAL_TYPE)
6338 tree fpaddend, cond, fourtyeight;
6340 fourtyeight = fold_convert (TREE_TYPE (addend), build_int_2 (6*8, 0));
6341 fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend),
6342 addend, fourtyeight));
6343 cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight));
6344 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6348 /* Build the final address and force that value into a temporary. */
6349 addr = build (PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
6350 fold_convert (ptr_type, addend));
6352 addr = build (INDIRECT_REF, type, addr);
6353 internal_post = NULL;
6354 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
6355 append_to_statement_list (internal_post, pre_p);
6357 /* Update the offset field. */
6358 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
6359 if (type_size == NULL || TREE_OVERFLOW (type_size))
6363 t = size_binop (PLUS_EXPR, type_size, size_int (7));
6364 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
6365 t = size_binop (MULT_EXPR, t, size_int (8));
6367 t = fold_convert (TREE_TYPE (offset), t);
6368 t = build (MODIFY_EXPR, void_type_node, offset,
6369 build (PLUS_EXPR, TREE_TYPE (offset), offset, t));
6370 gimplify_and_add (t, pre_p);
6372 return build_fold_indirect_ref (addr);
6376 alpha_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6378 tree offset_field, base_field, offset, base, t, r;
6380 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6381 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6383 base_field = TYPE_FIELDS (va_list_type_node);
6384 offset_field = TREE_CHAIN (base_field);
6385 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6386 valist, base_field, NULL_TREE);
6387 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6388 valist, offset_field, NULL_TREE);
6390 /* Pull the fields of the structure out into temporaries. Since we never
6391 modify the base field, we can use a formal temporary. Sign-extend the
6392 offset field so that it's the proper width for pointer arithmetic. */
6393 base = get_formal_tmp_var (base_field, pre_p);
6395 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
6396 offset = get_initialized_tmp_var (t, pre_p, NULL);
6398 /* Find the value. Note that this will be a stable indirection, or
6399 a composite of stable indirections in the case of complex. */
6400 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
6402 /* Stuff the offset temporary back into its field. */
6403 t = build (MODIFY_EXPR, void_type_node, offset_field,
6404 fold_convert (TREE_TYPE (offset_field), offset));
6405 gimplify_and_add (t, pre_p);
6414 ALPHA_BUILTIN_CMPBGE,
6415 ALPHA_BUILTIN_EXTBL,
6416 ALPHA_BUILTIN_EXTWL,
6417 ALPHA_BUILTIN_EXTLL,
6418 ALPHA_BUILTIN_EXTQL,
6419 ALPHA_BUILTIN_EXTWH,
6420 ALPHA_BUILTIN_EXTLH,
6421 ALPHA_BUILTIN_EXTQH,
6422 ALPHA_BUILTIN_INSBL,
6423 ALPHA_BUILTIN_INSWL,
6424 ALPHA_BUILTIN_INSLL,
6425 ALPHA_BUILTIN_INSQL,
6426 ALPHA_BUILTIN_INSWH,
6427 ALPHA_BUILTIN_INSLH,
6428 ALPHA_BUILTIN_INSQH,
6429 ALPHA_BUILTIN_MSKBL,
6430 ALPHA_BUILTIN_MSKWL,
6431 ALPHA_BUILTIN_MSKLL,
6432 ALPHA_BUILTIN_MSKQL,
6433 ALPHA_BUILTIN_MSKWH,
6434 ALPHA_BUILTIN_MSKLH,
6435 ALPHA_BUILTIN_MSKQH,
6436 ALPHA_BUILTIN_UMULH,
6438 ALPHA_BUILTIN_ZAPNOT,
6439 ALPHA_BUILTIN_AMASK,
6440 ALPHA_BUILTIN_IMPLVER,
6442 ALPHA_BUILTIN_THREAD_POINTER,
6443 ALPHA_BUILTIN_SET_THREAD_POINTER,
6446 ALPHA_BUILTIN_MINUB8,
6447 ALPHA_BUILTIN_MINSB8,
6448 ALPHA_BUILTIN_MINUW4,
6449 ALPHA_BUILTIN_MINSW4,
6450 ALPHA_BUILTIN_MAXUB8,
6451 ALPHA_BUILTIN_MAXSB8,
6452 ALPHA_BUILTIN_MAXUW4,
6453 ALPHA_BUILTIN_MAXSW4,
6457 ALPHA_BUILTIN_UNPKBL,
6458 ALPHA_BUILTIN_UNPKBW,
6463 ALPHA_BUILTIN_CTPOP,
6468 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6469 CODE_FOR_builtin_cmpbge,
6470 CODE_FOR_builtin_extbl,
6471 CODE_FOR_builtin_extwl,
6472 CODE_FOR_builtin_extll,
6473 CODE_FOR_builtin_extql,
6474 CODE_FOR_builtin_extwh,
6475 CODE_FOR_builtin_extlh,
6476 CODE_FOR_builtin_extqh,
6477 CODE_FOR_builtin_insbl,
6478 CODE_FOR_builtin_inswl,
6479 CODE_FOR_builtin_insll,
6480 CODE_FOR_builtin_insql,
6481 CODE_FOR_builtin_inswh,
6482 CODE_FOR_builtin_inslh,
6483 CODE_FOR_builtin_insqh,
6484 CODE_FOR_builtin_mskbl,
6485 CODE_FOR_builtin_mskwl,
6486 CODE_FOR_builtin_mskll,
6487 CODE_FOR_builtin_mskql,
6488 CODE_FOR_builtin_mskwh,
6489 CODE_FOR_builtin_msklh,
6490 CODE_FOR_builtin_mskqh,
6491 CODE_FOR_umuldi3_highpart,
6492 CODE_FOR_builtin_zap,
6493 CODE_FOR_builtin_zapnot,
6494 CODE_FOR_builtin_amask,
6495 CODE_FOR_builtin_implver,
6496 CODE_FOR_builtin_rpcc,
6501 CODE_FOR_builtin_minub8,
6502 CODE_FOR_builtin_minsb8,
6503 CODE_FOR_builtin_minuw4,
6504 CODE_FOR_builtin_minsw4,
6505 CODE_FOR_builtin_maxub8,
6506 CODE_FOR_builtin_maxsb8,
6507 CODE_FOR_builtin_maxuw4,
6508 CODE_FOR_builtin_maxsw4,
6509 CODE_FOR_builtin_perr,
6510 CODE_FOR_builtin_pklb,
6511 CODE_FOR_builtin_pkwb,
6512 CODE_FOR_builtin_unpkbl,
6513 CODE_FOR_builtin_unpkbw,
6516 CODE_FOR_builtin_cttz,
6517 CODE_FOR_builtin_ctlz,
6518 CODE_FOR_builtin_ctpop
6521 struct alpha_builtin_def
6524 enum alpha_builtin code;
6525 unsigned int target_mask;
6528 static struct alpha_builtin_def const zero_arg_builtins[] = {
6529 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6530 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6533 static struct alpha_builtin_def const one_arg_builtins[] = {
6534 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6535 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6536 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6537 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
6538 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6539 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6540 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6541 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6544 static struct alpha_builtin_def const two_arg_builtins[] = {
6545 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
6546 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6547 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6548 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6549 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
6550 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6551 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6552 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
6553 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6554 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6555 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6556 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6557 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6558 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6559 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6560 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6561 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6562 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6563 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6564 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6565 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6566 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6567 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6568 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6569 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6570 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6571 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6572 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6573 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6574 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6575 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6576 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6577 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6578 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6582 alpha_init_builtins (void)
6584 const struct alpha_builtin_def *p;
6588 ftype = build_function_type (long_integer_type_node, void_list_node);
6590 p = zero_arg_builtins;
6591 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6592 if ((target_flags & p->target_mask) == p->target_mask)
6593 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6596 ftype = build_function_type_list (long_integer_type_node,
6597 long_integer_type_node, NULL_TREE);
6599 p = one_arg_builtins;
6600 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6601 if ((target_flags & p->target_mask) == p->target_mask)
6602 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6605 ftype = build_function_type_list (long_integer_type_node,
6606 long_integer_type_node,
6607 long_integer_type_node, NULL_TREE);
6609 p = two_arg_builtins;
6610 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6611 if ((target_flags & p->target_mask) == p->target_mask)
6612 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6615 ftype = build_function_type (ptr_type_node, void_list_node);
6616 builtin_function ("__builtin_thread_pointer", ftype,
6617 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6620 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6621 builtin_function ("__builtin_set_thread_pointer", ftype,
6622 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6626 /* Expand an expression EXP that calls a built-in function,
6627 with result going to TARGET if that's convenient
6628 (and in mode MODE if that's convenient).
6629 SUBTARGET may be used as the target for computing one of EXP's operands.
6630 IGNORE is nonzero if the value is to be ignored. */
6633 alpha_expand_builtin (tree exp, rtx target,
6634 rtx subtarget ATTRIBUTE_UNUSED,
6635 enum machine_mode mode ATTRIBUTE_UNUSED,
6636 int ignore ATTRIBUTE_UNUSED)
6640 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6641 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6642 tree arglist = TREE_OPERAND (exp, 1);
6643 enum insn_code icode;
6644 rtx op[MAX_ARGS], pat;
6648 if (fcode >= ALPHA_BUILTIN_max)
6649 internal_error ("bad builtin fcode");
6650 icode = code_for_builtin[fcode];
6652 internal_error ("bad builtin fcode");
6654 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6656 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6658 arglist = TREE_CHAIN (arglist), arity++)
6660 const struct insn_operand_data *insn_op;
6662 tree arg = TREE_VALUE (arglist);
6663 if (arg == error_mark_node)
6665 if (arity > MAX_ARGS)
6668 insn_op = &insn_data[icode].operand[arity + nonvoid];
6670 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6672 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6673 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6678 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6680 || GET_MODE (target) != tmode
6681 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6682 target = gen_reg_rtx (tmode);
6688 pat = GEN_FCN (icode) (target);
6692 pat = GEN_FCN (icode) (target, op[0]);
6694 pat = GEN_FCN (icode) (op[0]);
6697 pat = GEN_FCN (icode) (target, op[0], op[1]);
6712 /* This page contains routines that are used to determine what the function
6713 prologue and epilogue code will do and write them out. */
6715 /* Compute the size of the save area in the stack. */
6717 /* These variables are used for communication between the following functions.
6718 They indicate various things about the current function being compiled
6719 that are used to tell what kind of prologue, epilogue and procedure
6720 descriptor to generate. */
6722 /* Nonzero if we need a stack procedure. */
6723 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6724 static enum alpha_procedure_types alpha_procedure_type;
6726 /* Register number (either FP or SP) that is used to unwind the frame. */
6727 static int vms_unwind_regno;
6729 /* Register number used to save FP. We need not have one for RA since
6730 we don't modify it for register procedures. This is only defined
6731 for register frame procedures. */
6732 static int vms_save_fp_regno;
6734 /* Register number used to reference objects off our PV. */
6735 static int vms_base_regno;
6737 /* Compute register masks for saved registers. */
6740 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
6742 unsigned long imask = 0;
6743 unsigned long fmask = 0;
6746 /* When outputting a thunk, we don't have valid register life info,
6747 but assemble_start_function wants to output .frame and .mask
6749 if (current_function_is_thunk)
6756 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6757 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
6759 /* One for every register we have to save. */
6760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6761 if (! fixed_regs[i] && ! call_used_regs[i]
6762 && regs_ever_live[i] && i != REG_RA
6763 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6766 imask |= (1UL << i);
6768 fmask |= (1UL << (i - 32));
6771 /* We need to restore these for the handler. */
6772 if (current_function_calls_eh_return)
6776 unsigned regno = EH_RETURN_DATA_REGNO (i);
6777 if (regno == INVALID_REGNUM)
6779 imask |= 1UL << regno;
6782 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6783 avoid hackery in unwind-dw2.c, we need to actively store a
6784 zero in the prologue of _Unwind_RaiseException et al. */
6788 /* If any register spilled, then spill the return address also. */
6789 /* ??? This is required by the Digital stack unwind specification
6790 and isn't needed if we're doing Dwarf2 unwinding. */
6791 if (imask || fmask || alpha_ra_ever_killed ())
6792 imask |= (1UL << REG_RA);
6799 alpha_sa_size (void)
6801 unsigned long mask[2];
6805 alpha_sa_mask (&mask[0], &mask[1]);
6807 if (TARGET_ABI_UNICOSMK)
6809 if (mask[0] || mask[1])
6814 for (j = 0; j < 2; ++j)
6815 for (i = 0; i < 32; ++i)
6816 if ((mask[j] >> i) & 1)
6820 if (TARGET_ABI_UNICOSMK)
6822 /* We might not need to generate a frame if we don't make any calls
6823 (including calls to __T3E_MISMATCH if this is a vararg function),
6824 don't have any local variables which require stack slots, don't
6825 use alloca and have not determined that we need a frame for other
6828 alpha_procedure_type
6829 = (sa_size || get_frame_size() != 0
6830 || current_function_outgoing_args_size
6831 || current_function_stdarg || current_function_calls_alloca
6832 || frame_pointer_needed)
6833 ? PT_STACK : PT_REGISTER;
6835 /* Always reserve space for saving callee-saved registers if we
6836 need a frame as required by the calling convention. */
6837 if (alpha_procedure_type == PT_STACK)
6840 else if (TARGET_ABI_OPEN_VMS)
6842 /* Start by assuming we can use a register procedure if we don't
6843 make any calls (REG_RA not used) or need to save any
6844 registers and a stack procedure if we do. */
6845 if ((mask[0] >> REG_RA) & 1)
6846 alpha_procedure_type = PT_STACK;
6847 else if (get_frame_size() != 0)
6848 alpha_procedure_type = PT_REGISTER;
6850 alpha_procedure_type = PT_NULL;
6852 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6853 made the final decision on stack procedure vs register procedure. */
6854 if (alpha_procedure_type == PT_STACK)
6857 /* Decide whether to refer to objects off our PV via FP or PV.
6858 If we need FP for something else or if we receive a nonlocal
6859 goto (which expects PV to contain the value), we must use PV.
6860 Otherwise, start by assuming we can use FP. */
6863 = (frame_pointer_needed
6864 || current_function_has_nonlocal_label
6865 || alpha_procedure_type == PT_STACK
6866 || current_function_outgoing_args_size)
6867 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6869 /* If we want to copy PV into FP, we need to find some register
6870 in which to save FP. */
6872 vms_save_fp_regno = -1;
6873 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6874 for (i = 0; i < 32; i++)
6875 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6876 vms_save_fp_regno = i;
6878 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6879 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6880 else if (alpha_procedure_type == PT_NULL)
6881 vms_base_regno = REG_PV;
6883 /* Stack unwinding should be done via FP unless we use it for PV. */
6884 vms_unwind_regno = (vms_base_regno == REG_PV
6885 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6887 /* If this is a stack procedure, allow space for saving FP and RA. */
6888 if (alpha_procedure_type == PT_STACK)
6893 /* Our size must be even (multiple of 16 bytes). */
6901 /* Define the offset between two registers, one to be eliminated,
6902 and the other its replacement, at the start of a routine. */
6905 alpha_initial_elimination_offset (unsigned int from,
6906 unsigned int to ATTRIBUTE_UNUSED)
6910 ret = alpha_sa_size ();
6911 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6913 if (from == FRAME_POINTER_REGNUM)
6915 else if (from == ARG_POINTER_REGNUM)
6916 ret += (ALPHA_ROUND (get_frame_size ()
6917 + current_function_pretend_args_size)
6918 - current_function_pretend_args_size);
6926 alpha_pv_save_size (void)
6929 return alpha_procedure_type == PT_STACK ? 8 : 0;
6933 alpha_using_fp (void)
6936 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6939 #if TARGET_ABI_OPEN_VMS
6941 const struct attribute_spec vms_attribute_table[] =
6943 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6944 { "overlaid", 0, 0, true, false, false, NULL },
6945 { "global", 0, 0, true, false, false, NULL },
6946 { "initialize", 0, 0, true, false, false, NULL },
6947 { NULL, 0, 0, false, false, false, NULL }
6953 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6955 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6959 alpha_find_lo_sum_using_gp (rtx insn)
6961 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
6965 alpha_does_function_need_gp (void)
6969 /* The GP being variable is an OSF abi thing. */
6970 if (! TARGET_ABI_OSF)
6973 /* We need the gp to load the address of __mcount. */
6974 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6977 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6978 if (current_function_is_thunk)
6981 /* The nonlocal receiver pattern assumes that the gp is valid for
6982 the nested function. Reasonable because it's almost always set
6983 correctly already. For the cases where that's wrong, make sure
6984 the nested function loads its gp on entry. */
6985 if (current_function_has_nonlocal_goto)
6988 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6989 Even if we are a static function, we still need to do this in case
6990 our address is taken and passed to something like qsort. */
6992 push_topmost_sequence ();
6993 insn = get_insns ();
6994 pop_topmost_sequence ();
6996 for (; insn; insn = NEXT_INSN (insn))
6998 && GET_CODE (PATTERN (insn)) != USE
6999 && GET_CODE (PATTERN (insn)) != CLOBBER
7000 && get_attr_usegp (insn))
7007 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7011 set_frame_related_p (void)
7013 rtx seq = get_insns ();
7024 while (insn != NULL_RTX)
7026 RTX_FRAME_RELATED_P (insn) = 1;
7027 insn = NEXT_INSN (insn);
7029 seq = emit_insn (seq);
7033 seq = emit_insn (seq);
7034 RTX_FRAME_RELATED_P (seq) = 1;
7039 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7041 /* Write function prologue. */
7043 /* On vms we have two kinds of functions:
7045 - stack frame (PROC_STACK)
7046 these are 'normal' functions with local vars and which are
7047 calling other functions
7048 - register frame (PROC_REGISTER)
7049 keeps all data in registers, needs no stack
7051 We must pass this to the assembler so it can generate the
7052 proper pdsc (procedure descriptor)
7053 This is done with the '.pdesc' command.
7055 On not-vms, we don't really differentiate between the two, as we can
7056 simply allocate stack without saving registers. */
7059 alpha_expand_prologue (void)
7061 /* Registers to save. */
7062 unsigned long imask = 0;
7063 unsigned long fmask = 0;
7064 /* Stack space needed for pushing registers clobbered by us. */
7065 HOST_WIDE_INT sa_size;
7066 /* Complete stack size needed. */
7067 HOST_WIDE_INT frame_size;
7068 /* Offset from base reg to register save area. */
7069 HOST_WIDE_INT reg_offset;
7073 sa_size = alpha_sa_size ();
7075 frame_size = get_frame_size ();
7076 if (TARGET_ABI_OPEN_VMS)
7077 frame_size = ALPHA_ROUND (sa_size
7078 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7080 + current_function_pretend_args_size);
7081 else if (TARGET_ABI_UNICOSMK)
7082 /* We have to allocate space for the DSIB if we generate a frame. */
7083 frame_size = ALPHA_ROUND (sa_size
7084 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7085 + ALPHA_ROUND (frame_size
7086 + current_function_outgoing_args_size);
7088 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7090 + ALPHA_ROUND (frame_size
7091 + current_function_pretend_args_size));
7093 if (TARGET_ABI_OPEN_VMS)
7096 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7098 alpha_sa_mask (&imask, &fmask);
7100 /* Emit an insn to reload GP, if needed. */
7103 alpha_function_needs_gp = alpha_does_function_need_gp ();
7104 if (alpha_function_needs_gp)
7105 emit_insn (gen_prologue_ldgp ());
7108 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7109 the call to mcount ourselves, rather than having the linker do it
7110 magically in response to -pg. Since _mcount has special linkage,
7111 don't represent the call as a call. */
7112 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7113 emit_insn (gen_prologue_mcount ());
7115 if (TARGET_ABI_UNICOSMK)
7116 unicosmk_gen_dsib (&imask);
7118 /* Adjust the stack by the frame size. If the frame size is > 4096
7119 bytes, we need to be sure we probe somewhere in the first and last
7120 4096 bytes (we can probably get away without the latter test) and
7121 every 8192 bytes in between. If the frame size is > 32768, we
7122 do this in a loop. Otherwise, we generate the explicit probe
7125 Note that we are only allowed to adjust sp once in the prologue. */
7127 if (frame_size <= 32768)
7129 if (frame_size > 4096)
7134 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7137 while ((probed += 8192) < frame_size);
7139 /* We only have to do this probe if we aren't saving registers. */
7140 if (sa_size == 0 && probed + 4096 < frame_size)
7141 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7144 if (frame_size != 0)
7145 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7146 GEN_INT (TARGET_ABI_UNICOSMK
7152 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7153 number of 8192 byte blocks to probe. We then probe each block
7154 in the loop and then set SP to the proper location. If the
7155 amount remaining is > 4096, we have to do one more probe if we
7156 are not saving any registers. */
7158 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7159 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7160 rtx ptr = gen_rtx_REG (DImode, 22);
7161 rtx count = gen_rtx_REG (DImode, 23);
7164 emit_move_insn (count, GEN_INT (blocks));
7165 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7166 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7168 /* Because of the difficulty in emitting a new basic block this
7169 late in the compilation, generate the loop as a single insn. */
7170 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7172 if (leftover > 4096 && sa_size == 0)
7174 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7175 MEM_VOLATILE_P (last) = 1;
7176 emit_move_insn (last, const0_rtx);
7179 if (TARGET_ABI_WINDOWS_NT)
7181 /* For NT stack unwind (done by 'reverse execution'), it's
7182 not OK to take the result of a loop, even though the value
7183 is already in ptr, so we reload it via a single operation
7184 and subtract it to sp.
7186 Yes, that's correct -- we have to reload the whole constant
7187 into a temporary via ldah+lda then subtract from sp. */
7189 HOST_WIDE_INT lo, hi;
7190 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7191 hi = frame_size - lo;
7193 emit_move_insn (ptr, GEN_INT (hi));
7194 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7195 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7200 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7201 GEN_INT (-leftover)));
7204 /* This alternative is special, because the DWARF code cannot
7205 possibly intuit through the loop above. So we invent this
7206 note it looks at instead. */
7207 RTX_FRAME_RELATED_P (seq) = 1;
7209 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7210 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7211 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7212 GEN_INT (TARGET_ABI_UNICOSMK
7218 if (!TARGET_ABI_UNICOSMK)
7220 /* Cope with very large offsets to the register save area. */
7221 sa_reg = stack_pointer_rtx;
7222 if (reg_offset + sa_size > 0x8000)
7224 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7227 if (low + sa_size <= 0x8000)
7228 bias = reg_offset - low, reg_offset = low;
7230 bias = reg_offset, reg_offset = 0;
7232 sa_reg = gen_rtx_REG (DImode, 24);
7233 FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
7237 /* Save regs in stack order. Beginning with VMS PV. */
7238 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7240 mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
7241 set_mem_alias_set (mem, alpha_sr_alias_set);
7242 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
7245 /* Save register RA next. */
7246 if (imask & (1UL << REG_RA))
7248 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7249 set_mem_alias_set (mem, alpha_sr_alias_set);
7250 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
7251 imask &= ~(1UL << REG_RA);
7255 /* Now save any other registers required to be saved. */
7256 for (i = 0; i < 31; i++)
7257 if (imask & (1UL << i))
7259 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7260 set_mem_alias_set (mem, alpha_sr_alias_set);
7261 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7265 /* Store a zero if requested for unwinding. */
7266 if (imask & (1UL << 31))
7270 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7271 set_mem_alias_set (mem, alpha_sr_alias_set);
7272 insn = emit_move_insn (mem, const0_rtx);
7274 RTX_FRAME_RELATED_P (insn) = 1;
7275 t = gen_rtx_REG (Pmode, 31);
7276 t = gen_rtx_SET (VOIDmode, mem, t);
7277 t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn));
7278 REG_NOTES (insn) = t;
7283 for (i = 0; i < 31; i++)
7284 if (fmask & (1UL << i))
7286 mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
7287 set_mem_alias_set (mem, alpha_sr_alias_set);
7288 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7292 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7294 /* The standard frame on the T3E includes space for saving registers.
7295 We just have to use it. We don't have to save the return address and
7296 the old frame pointer here - they are saved in the DSIB. */
7299 for (i = 9; i < 15; i++)
7300 if (imask & (1UL << i))
7302 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7304 set_mem_alias_set (mem, alpha_sr_alias_set);
7305 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7308 for (i = 2; i < 10; i++)
7309 if (fmask & (1UL << i))
7311 mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
7313 set_mem_alias_set (mem, alpha_sr_alias_set);
7314 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7319 if (TARGET_ABI_OPEN_VMS)
7321 if (alpha_procedure_type == PT_REGISTER)
7322 /* Register frame procedures save the fp.
7323 ?? Ought to have a dwarf2 save for this. */
7324 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7325 hard_frame_pointer_rtx);
7327 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
7328 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7329 gen_rtx_REG (DImode, REG_PV)));
7331 if (alpha_procedure_type != PT_NULL
7332 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7333 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7335 /* If we have to allocate space for outgoing args, do it now. */
7336 if (current_function_outgoing_args_size != 0)
7339 = emit_move_insn (stack_pointer_rtx,
7341 (hard_frame_pointer_rtx,
7343 (current_function_outgoing_args_size))));
7345 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7346 if ! frame_pointer_needed. Setting the bit will change the CFA
7347 computation rule to use sp again, which would be wrong if we had
7348 frame_pointer_needed, as this means sp might move unpredictably
7352 frame_pointer_needed
7353 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7355 current_function_outgoing_args_size != 0
7356 => alpha_procedure_type != PT_NULL,
7358 so when we are not setting the bit here, we are guaranteed to
7359 have emitted an FRP frame pointer update just before. */
7360 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
7363 else if (!TARGET_ABI_UNICOSMK)
7365 /* If we need a frame pointer, set it from the stack pointer. */
7366 if (frame_pointer_needed)
7368 if (TARGET_CAN_FAULT_IN_PROLOGUE)
7369 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7371 /* This must always be the last instruction in the
7372 prologue, thus we emit a special move + clobber. */
7373 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7374 stack_pointer_rtx, sa_reg)));
7378 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7379 the prologue, for exception handling reasons, we cannot do this for
7380 any insn that might fault. We could prevent this for mems with a
7381 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7382 have to prevent all such scheduling with a blockage.
7384 Linux, on the other hand, never bothered to implement OSF/1's
7385 exception handling, and so doesn't care about such things. Anyone
7386 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7388 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7389 emit_insn (gen_blockage ());
7392 /* Output the textual info surrounding the prologue. */
7395 alpha_start_function (FILE *file, const char *fnname,
7396 tree decl ATTRIBUTE_UNUSED)
7398 unsigned long imask = 0;
7399 unsigned long fmask = 0;
7400 /* Stack space needed for pushing registers clobbered by us. */
7401 HOST_WIDE_INT sa_size;
7402 /* Complete stack size needed. */
7403 unsigned HOST_WIDE_INT frame_size;
7404 /* Offset from base reg to register save area. */
7405 HOST_WIDE_INT reg_offset;
7406 char *entry_label = (char *) alloca (strlen (fnname) + 6);
7409 /* Don't emit an extern directive for functions defined in the same file. */
7410 if (TARGET_ABI_UNICOSMK)
7413 name_tree = get_identifier (fnname);
7414 TREE_ASM_WRITTEN (name_tree) = 1;
7417 alpha_fnname = fnname;
7418 sa_size = alpha_sa_size ();
7420 frame_size = get_frame_size ();
7421 if (TARGET_ABI_OPEN_VMS)
7422 frame_size = ALPHA_ROUND (sa_size
7423 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7425 + current_function_pretend_args_size);
7426 else if (TARGET_ABI_UNICOSMK)
7427 frame_size = ALPHA_ROUND (sa_size
7428 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7429 + ALPHA_ROUND (frame_size
7430 + current_function_outgoing_args_size);
7432 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7434 + ALPHA_ROUND (frame_size
7435 + current_function_pretend_args_size));
7437 if (TARGET_ABI_OPEN_VMS)
7440 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7442 alpha_sa_mask (&imask, &fmask);
7444 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7445 We have to do that before the .ent directive as we cannot switch
7446 files within procedures with native ecoff because line numbers are
7447 linked to procedure descriptors.
7448 Outputting the lineno helps debugging of one line functions as they
7449 would otherwise get no line number at all. Please note that we would
7450 like to put out last_linenum from final.c, but it is not accessible. */
7452 if (write_symbols == SDB_DEBUG)
7454 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7455 ASM_OUTPUT_SOURCE_FILENAME (file,
7456 DECL_SOURCE_FILE (current_function_decl));
7458 #ifdef ASM_OUTPUT_SOURCE_LINE
7459 if (debug_info_level != DINFO_LEVEL_TERSE)
7460 ASM_OUTPUT_SOURCE_LINE (file,
7461 DECL_SOURCE_LINE (current_function_decl), 0);
7465 /* Issue function start and label. */
7466 if (TARGET_ABI_OPEN_VMS
7467 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
7469 fputs ("\t.ent ", file);
7470 assemble_name (file, fnname);
7473 /* If the function needs GP, we'll write the "..ng" label there.
7474 Otherwise, do it here. */
7476 && ! alpha_function_needs_gp
7477 && ! current_function_is_thunk)
7480 assemble_name (file, fnname);
7481 fputs ("..ng:\n", file);
7485 strcpy (entry_label, fnname);
7486 if (TARGET_ABI_OPEN_VMS)
7487 strcat (entry_label, "..en");
7489 /* For public functions, the label must be globalized by appending an
7490 additional colon. */
7491 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7492 strcat (entry_label, ":");
7494 ASM_OUTPUT_LABEL (file, entry_label);
7495 inside_function = TRUE;
7497 if (TARGET_ABI_OPEN_VMS)
7498 fprintf (file, "\t.base $%d\n", vms_base_regno);
7500 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
7501 && !flag_inhibit_size_directive)
7503 /* Set flags in procedure descriptor to request IEEE-conformant
7504 math-library routines. The value we set it to is PDSC_EXC_IEEE
7505 (/usr/include/pdsc.h). */
7506 fputs ("\t.eflag 48\n", file);
7509 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7510 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7511 alpha_arg_offset = -frame_size + 48;
7513 /* Describe our frame. If the frame size is larger than an integer,
7514 print it as zero to avoid an assembler error. We won't be
7515 properly describing such a frame, but that's the best we can do. */
7516 if (TARGET_ABI_UNICOSMK)
7518 else if (TARGET_ABI_OPEN_VMS)
7519 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
7520 HOST_WIDE_INT_PRINT_DEC "\n",
7522 frame_size >= (1UL << 31) ? 0 : frame_size,
7524 else if (!flag_inhibit_size_directive)
7525 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
7526 (frame_pointer_needed
7527 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
7528 frame_size >= (1UL << 31) ? 0 : frame_size,
7529 current_function_pretend_args_size);
7531 /* Describe which registers were spilled. */
7532 if (TARGET_ABI_UNICOSMK)
7534 else if (TARGET_ABI_OPEN_VMS)
7537 /* ??? Does VMS care if mask contains ra? The old code didn't
7538 set it, so I don't here. */
7539 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
7541 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
7542 if (alpha_procedure_type == PT_REGISTER)
7543 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7545 else if (!flag_inhibit_size_directive)
7549 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
7550 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7552 for (i = 0; i < 32; ++i)
7553 if (imask & (1UL << i))
7558 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
7559 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7562 #if TARGET_ABI_OPEN_VMS
7563 /* Ifdef'ed cause link_section are only available then. */
7564 readonly_data_section ();
7565 fprintf (file, "\t.align 3\n");
7566 assemble_name (file, fnname); fputs ("..na:\n", file);
7567 fputs ("\t.ascii \"", file);
7568 assemble_name (file, fnname);
7569 fputs ("\\0\"\n", file);
7570 alpha_need_linkage (fnname, 1);
7575 /* Emit the .prologue note at the scheduled end of the prologue. */
7578 alpha_output_function_end_prologue (FILE *file)
7580 if (TARGET_ABI_UNICOSMK)
7582 else if (TARGET_ABI_OPEN_VMS)
7583 fputs ("\t.prologue\n", file);
7584 else if (TARGET_ABI_WINDOWS_NT)
7585 fputs ("\t.prologue 0\n", file);
7586 else if (!flag_inhibit_size_directive)
7587 fprintf (file, "\t.prologue %d\n",
7588 alpha_function_needs_gp || current_function_is_thunk);
7591 /* Write function epilogue. */
7593 /* ??? At some point we will want to support full unwind, and so will
7594 need to mark the epilogue as well. At the moment, we just confuse
7597 #define FRP(exp) exp
7600 alpha_expand_epilogue (void)
7602 /* Registers to save. */
7603 unsigned long imask = 0;
7604 unsigned long fmask = 0;
7605 /* Stack space needed for pushing registers clobbered by us. */
7606 HOST_WIDE_INT sa_size;
7607 /* Complete stack size needed. */
7608 HOST_WIDE_INT frame_size;
7609 /* Offset from base reg to register save area. */
7610 HOST_WIDE_INT reg_offset;
7611 int fp_is_frame_pointer, fp_offset;
7612 rtx sa_reg, sa_reg_exp = NULL;
7613 rtx sp_adj1, sp_adj2, mem;
7617 sa_size = alpha_sa_size ();
7619 frame_size = get_frame_size ();
7620 if (TARGET_ABI_OPEN_VMS)
7621 frame_size = ALPHA_ROUND (sa_size
7622 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7624 + current_function_pretend_args_size);
7625 else if (TARGET_ABI_UNICOSMK)
7626 frame_size = ALPHA_ROUND (sa_size
7627 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7628 + ALPHA_ROUND (frame_size
7629 + current_function_outgoing_args_size);
7631 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7633 + ALPHA_ROUND (frame_size
7634 + current_function_pretend_args_size));
7636 if (TARGET_ABI_OPEN_VMS)
7638 if (alpha_procedure_type == PT_STACK)
7644 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7646 alpha_sa_mask (&imask, &fmask);
7649 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7650 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
7652 sa_reg = stack_pointer_rtx;
7654 if (current_function_calls_eh_return)
7655 eh_ofs = EH_RETURN_STACKADJ_RTX;
7659 if (!TARGET_ABI_UNICOSMK && sa_size)
7661 /* If we have a frame pointer, restore SP from it. */
7662 if ((TARGET_ABI_OPEN_VMS
7663 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7664 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
7665 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
7667 /* Cope with very large offsets to the register save area. */
7668 if (reg_offset + sa_size > 0x8000)
7670 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7673 if (low + sa_size <= 0x8000)
7674 bias = reg_offset - low, reg_offset = low;
7676 bias = reg_offset, reg_offset = 0;
7678 sa_reg = gen_rtx_REG (DImode, 22);
7679 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7681 FRP (emit_move_insn (sa_reg, sa_reg_exp));
7684 /* Restore registers in order, excepting a true frame pointer. */
7686 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7688 set_mem_alias_set (mem, alpha_sr_alias_set);
7689 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7692 imask &= ~(1UL << REG_RA);
7694 for (i = 0; i < 31; ++i)
7695 if (imask & (1UL << i))
7697 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
7698 fp_offset = reg_offset;
7701 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
7702 set_mem_alias_set (mem, alpha_sr_alias_set);
7703 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7708 if (imask & (1UL << 31))
7711 for (i = 0; i < 31; ++i)
7712 if (fmask & (1UL << i))
7714 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
7715 set_mem_alias_set (mem, alpha_sr_alias_set);
7716 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7720 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7722 /* Restore callee-saved general-purpose registers. */
7726 for (i = 9; i < 15; i++)
7727 if (imask & (1UL << i))
7729 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7731 set_mem_alias_set (mem, alpha_sr_alias_set);
7732 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7736 for (i = 2; i < 10; i++)
7737 if (fmask & (1UL << i))
7739 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7741 set_mem_alias_set (mem, alpha_sr_alias_set);
7742 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7746 /* Restore the return address from the DSIB. */
7748 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7749 set_mem_alias_set (mem, alpha_sr_alias_set);
7750 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7753 if (frame_size || eh_ofs)
7755 sp_adj1 = stack_pointer_rtx;
7759 sp_adj1 = gen_rtx_REG (DImode, 23);
7760 emit_move_insn (sp_adj1,
7761 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
7764 /* If the stack size is large, begin computation into a temporary
7765 register so as not to interfere with a potential fp restore,
7766 which must be consecutive with an SP restore. */
7767 if (frame_size < 32768
7768 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
7769 sp_adj2 = GEN_INT (frame_size);
7770 else if (TARGET_ABI_UNICOSMK)
7772 sp_adj1 = gen_rtx_REG (DImode, 23);
7773 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7774 sp_adj2 = const0_rtx;
7776 else if (frame_size < 0x40007fffL)
7778 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7780 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
7781 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7785 sp_adj1 = gen_rtx_REG (DImode, 23);
7786 FRP (emit_move_insn (sp_adj1, sp_adj2));
7788 sp_adj2 = GEN_INT (low);
7792 rtx tmp = gen_rtx_REG (DImode, 23);
7793 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7796 /* We can't drop new things to memory this late, afaik,
7797 so build it up by pieces. */
7798 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7799 -(frame_size < 0)));
7805 /* From now on, things must be in order. So emit blockages. */
7807 /* Restore the frame pointer. */
7808 if (TARGET_ABI_UNICOSMK)
7810 emit_insn (gen_blockage ());
7811 mem = gen_rtx_MEM (DImode,
7812 plus_constant (hard_frame_pointer_rtx, -16));
7813 set_mem_alias_set (mem, alpha_sr_alias_set);
7814 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7816 else if (fp_is_frame_pointer)
7818 emit_insn (gen_blockage ());
7819 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7820 set_mem_alias_set (mem, alpha_sr_alias_set);
7821 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7823 else if (TARGET_ABI_OPEN_VMS)
7825 emit_insn (gen_blockage ());
7826 FRP (emit_move_insn (hard_frame_pointer_rtx,
7827 gen_rtx_REG (DImode, vms_save_fp_regno)));
7830 /* Restore the stack pointer. */
7831 emit_insn (gen_blockage ());
7832 if (sp_adj2 == const0_rtx)
7833 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7835 FRP (emit_move_insn (stack_pointer_rtx,
7836 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7840 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7842 emit_insn (gen_blockage ());
7843 FRP (emit_move_insn (hard_frame_pointer_rtx,
7844 gen_rtx_REG (DImode, vms_save_fp_regno)));
7846 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7848 /* Decrement the frame pointer if the function does not have a
7851 emit_insn (gen_blockage ());
7852 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7853 hard_frame_pointer_rtx, constm1_rtx)));
7858 /* Output the rest of the textual info surrounding the epilogue. */
7861 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7863 #if TARGET_ABI_OPEN_VMS
7864 alpha_write_linkage (file, fnname, decl);
7867 /* End the function. */
7868 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7870 fputs ("\t.end ", file);
7871 assemble_name (file, fnname);
7874 inside_function = FALSE;
7876 /* Output jump tables and the static subroutine information block. */
7877 if (TARGET_ABI_UNICOSMK)
7879 unicosmk_output_ssib (file, fnname);
7880 unicosmk_output_deferred_case_vectors (file);
7885 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7887 In order to avoid the hordes of differences between generated code
7888 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7889 lots of code loading up large constants, generate rtl and emit it
7890 instead of going straight to text.
7892 Not sure why this idea hasn't been explored before... */
7895 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7896 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7899 HOST_WIDE_INT hi, lo;
7900 rtx this, insn, funexp;
7902 /* We always require a valid GP. */
7903 emit_insn (gen_prologue_ldgp ());
7904 emit_note (NOTE_INSN_PROLOGUE_END);
7906 /* Find the "this" pointer. If the function returns a structure,
7907 the structure return pointer is in $16. */
7908 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7909 this = gen_rtx_REG (Pmode, 17);
7911 this = gen_rtx_REG (Pmode, 16);
7913 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7914 entire constant for the add. */
7915 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7916 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7917 if (hi + lo == delta)
7920 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7922 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7926 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7927 delta, -(delta < 0));
7928 emit_insn (gen_adddi3 (this, this, tmp));
7931 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7936 tmp = gen_rtx_REG (Pmode, 0);
7937 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7939 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7940 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7941 if (hi + lo == vcall_offset)
7944 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7948 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7949 vcall_offset, -(vcall_offset < 0));
7950 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
7954 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
7957 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
7959 emit_insn (gen_adddi3 (this, this, tmp));
7962 /* Generate a tail call to the target function. */
7963 if (! TREE_USED (function))
7965 assemble_external (function);
7966 TREE_USED (function) = 1;
7968 funexp = XEXP (DECL_RTL (function), 0);
7969 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7970 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7971 SIBLING_CALL_P (insn) = 1;
7973 /* Run just enough of rest_of_compilation to get the insns emitted.
7974 There's not really enough bulk here to make other passes such as
7975 instruction scheduling worth while. Note that use_thunk calls
7976 assemble_start_function and assemble_end_function. */
7977 insn = get_insns ();
7978 insn_locators_initialize ();
7979 shorten_branches (insn);
7980 final_start_function (insn, file, 1);
7981 final (insn, file, 1, 0);
7982 final_end_function ();
7984 #endif /* TARGET_ABI_OSF */
7986 /* Debugging support. */
7990 /* Count the number of sdb related labels are generated (to find block
7991 start and end boundaries). */
7993 int sdb_label_count = 0;
7995 /* Next label # for each statement. */
7997 static int sym_lineno = 0;
7999 /* Count the number of .file directives, so that .loc is up to date. */
8001 static int num_source_filenames = 0;
8003 /* Name of the file containing the current function. */
8005 static const char *current_function_file = "";
8007 /* Offsets to alpha virtual arg/local debugging pointers. */
8009 long alpha_arg_offset;
8010 long alpha_auto_offset;
8012 /* Emit a new filename to a stream. */
8015 alpha_output_filename (FILE *stream, const char *name)
8017 static int first_time = TRUE;
8018 char ltext_label_name[100];
8023 ++num_source_filenames;
8024 current_function_file = name;
8025 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8026 output_quoted_string (stream, name);
8027 fprintf (stream, "\n");
8028 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
8029 fprintf (stream, "\t#@stabs\n");
8032 else if (write_symbols == DBX_DEBUG)
8034 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
8035 fprintf (stream, "%s", ASM_STABS_OP);
8036 output_quoted_string (stream, name);
8037 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
8040 else if (name != current_function_file
8041 && strcmp (name, current_function_file) != 0)
8043 if (inside_function && ! TARGET_GAS)
8044 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
8047 ++num_source_filenames;
8048 current_function_file = name;
8049 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8052 output_quoted_string (stream, name);
8053 fprintf (stream, "\n");
8057 /* Emit a linenumber to a stream. */
8060 alpha_output_lineno (FILE *stream, int line)
8062 if (write_symbols == DBX_DEBUG)
8064 /* mips-tfile doesn't understand .stabd directives. */
8066 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8067 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8070 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
8073 /* Structure to show the current status of registers and memory. */
8075 struct shadow_summary
8078 unsigned int i : 31; /* Mask of int regs */
8079 unsigned int fp : 31; /* Mask of fp regs */
8080 unsigned int mem : 1; /* mem == imem | fpmem */
8084 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8085 to the summary structure. SET is nonzero if the insn is setting the
8086 object, otherwise zero. */
8089 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8091 const char *format_ptr;
8097 switch (GET_CODE (x))
8099 /* ??? Note that this case would be incorrect if the Alpha had a
8100 ZERO_EXTRACT in SET_DEST. */
8102 summarize_insn (SET_SRC (x), sum, 0);
8103 summarize_insn (SET_DEST (x), sum, 1);
8107 summarize_insn (XEXP (x, 0), sum, 1);
8111 summarize_insn (XEXP (x, 0), sum, 0);
8115 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8116 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8120 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8121 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8125 summarize_insn (SUBREG_REG (x), sum, 0);
8130 int regno = REGNO (x);
8131 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8133 if (regno == 31 || regno == 63)
8139 sum->defd.i |= mask;
8141 sum->defd.fp |= mask;
8146 sum->used.i |= mask;
8148 sum->used.fp |= mask;
8159 /* Find the regs used in memory address computation: */
8160 summarize_insn (XEXP (x, 0), sum, 0);
8163 case CONST_INT: case CONST_DOUBLE:
8164 case SYMBOL_REF: case LABEL_REF: case CONST:
8165 case SCRATCH: case ASM_INPUT:
8168 /* Handle common unary and binary ops for efficiency. */
8169 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8170 case MOD: case UDIV: case UMOD: case AND: case IOR:
8171 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8172 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8173 case NE: case EQ: case GE: case GT: case LE:
8174 case LT: case GEU: case GTU: case LEU: case LTU:
8175 summarize_insn (XEXP (x, 0), sum, 0);
8176 summarize_insn (XEXP (x, 1), sum, 0);
8179 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8180 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8181 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8182 case SQRT: case FFS:
8183 summarize_insn (XEXP (x, 0), sum, 0);
8187 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8188 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8189 switch (format_ptr[i])
8192 summarize_insn (XEXP (x, i), sum, 0);
8196 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8197 summarize_insn (XVECEXP (x, i, j), sum, 0);
8209 /* Ensure a sufficient number of `trapb' insns are in the code when
8210 the user requests code with a trap precision of functions or
8213 In naive mode, when the user requests a trap-precision of
8214 "instruction", a trapb is needed after every instruction that may
8215 generate a trap. This ensures that the code is resumption safe but
8218 When optimizations are turned on, we delay issuing a trapb as long
8219 as possible. In this context, a trap shadow is the sequence of
8220 instructions that starts with a (potentially) trap generating
8221 instruction and extends to the next trapb or call_pal instruction
8222 (but GCC never generates call_pal by itself). We can delay (and
8223 therefore sometimes omit) a trapb subject to the following
8226 (a) On entry to the trap shadow, if any Alpha register or memory
8227 location contains a value that is used as an operand value by some
8228 instruction in the trap shadow (live on entry), then no instruction
8229 in the trap shadow may modify the register or memory location.
8231 (b) Within the trap shadow, the computation of the base register
8232 for a memory load or store instruction may not involve using the
8233 result of an instruction that might generate an UNPREDICTABLE
8236 (c) Within the trap shadow, no register may be used more than once
8237 as a destination register. (This is to make life easier for the
8240 (d) The trap shadow may not include any branch instructions. */
8243 alpha_handle_trap_shadows (void)
8245 struct shadow_summary shadow;
8246 int trap_pending, exception_nesting;
8250 exception_nesting = 0;
8253 shadow.used.mem = 0;
8254 shadow.defd = shadow.used;
8256 for (i = get_insns (); i ; i = NEXT_INSN (i))
8258 if (GET_CODE (i) == NOTE)
8260 switch (NOTE_LINE_NUMBER (i))
8262 case NOTE_INSN_EH_REGION_BEG:
8263 exception_nesting++;
8268 case NOTE_INSN_EH_REGION_END:
8269 exception_nesting--;
8274 case NOTE_INSN_EPILOGUE_BEG:
8275 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8280 else if (trap_pending)
8282 if (alpha_tp == ALPHA_TP_FUNC)
8284 if (GET_CODE (i) == JUMP_INSN
8285 && GET_CODE (PATTERN (i)) == RETURN)
8288 else if (alpha_tp == ALPHA_TP_INSN)
8292 struct shadow_summary sum;
8297 sum.defd = sum.used;
8299 switch (GET_CODE (i))
8302 /* Annoyingly, get_attr_trap will abort on these. */
8303 if (GET_CODE (PATTERN (i)) == USE
8304 || GET_CODE (PATTERN (i)) == CLOBBER)
8307 summarize_insn (PATTERN (i), &sum, 0);
8309 if ((sum.defd.i & shadow.defd.i)
8310 || (sum.defd.fp & shadow.defd.fp))
8312 /* (c) would be violated */
8316 /* Combine shadow with summary of current insn: */
8317 shadow.used.i |= sum.used.i;
8318 shadow.used.fp |= sum.used.fp;
8319 shadow.used.mem |= sum.used.mem;
8320 shadow.defd.i |= sum.defd.i;
8321 shadow.defd.fp |= sum.defd.fp;
8322 shadow.defd.mem |= sum.defd.mem;
8324 if ((sum.defd.i & shadow.used.i)
8325 || (sum.defd.fp & shadow.used.fp)
8326 || (sum.defd.mem & shadow.used.mem))
8328 /* (a) would be violated (also takes care of (b)) */
8329 if (get_attr_trap (i) == TRAP_YES
8330 && ((sum.defd.i & sum.used.i)
8331 || (sum.defd.fp & sum.used.fp)))
8350 n = emit_insn_before (gen_trapb (), i);
8351 PUT_MODE (n, TImode);
8352 PUT_MODE (i, TImode);
8356 shadow.used.mem = 0;
8357 shadow.defd = shadow.used;
8362 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8363 && GET_CODE (i) == INSN
8364 && GET_CODE (PATTERN (i)) != USE
8365 && GET_CODE (PATTERN (i)) != CLOBBER
8366 && get_attr_trap (i) == TRAP_YES)
8368 if (optimize && !trap_pending)
8369 summarize_insn (PATTERN (i), &shadow, 0);
8375 /* Alpha can only issue instruction groups simultaneously if they are
8376 suitably aligned. This is very processor-specific. */
8378 enum alphaev4_pipe {
8385 enum alphaev5_pipe {
8396 static enum alphaev4_pipe
8397 alphaev4_insn_pipe (rtx insn)
8399 if (recog_memoized (insn) < 0)
8401 if (get_attr_length (insn) != 4)
8404 switch (get_attr_type (insn))
8438 static enum alphaev5_pipe
8439 alphaev5_insn_pipe (rtx insn)
8441 if (recog_memoized (insn) < 0)
8443 if (get_attr_length (insn) != 4)
8446 switch (get_attr_type (insn))
8487 /* IN_USE is a mask of the slots currently filled within the insn group.
8488 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8489 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8491 LEN is, of course, the length of the group in bytes. */
8494 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
8501 || GET_CODE (PATTERN (insn)) == CLOBBER
8502 || GET_CODE (PATTERN (insn)) == USE)
8507 enum alphaev4_pipe pipe;
8509 pipe = alphaev4_insn_pipe (insn);
8513 /* Force complex instructions to start new groups. */
8517 /* If this is a completely unrecognized insn, its an asm.
8518 We don't know how long it is, so record length as -1 to
8519 signal a needed realignment. */
8520 if (recog_memoized (insn) < 0)
8523 len = get_attr_length (insn);
8527 if (in_use & EV4_IB0)
8529 if (in_use & EV4_IB1)
8534 in_use |= EV4_IB0 | EV4_IBX;
8538 if (in_use & EV4_IB0)
8540 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8548 if (in_use & EV4_IB1)
8558 /* Haifa doesn't do well scheduling branches. */
8559 if (GET_CODE (insn) == JUMP_INSN)
8563 insn = next_nonnote_insn (insn);
8565 if (!insn || ! INSN_P (insn))
8568 /* Let Haifa tell us where it thinks insn group boundaries are. */
8569 if (GET_MODE (insn) == TImode)
8572 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8577 insn = next_nonnote_insn (insn);
8585 /* IN_USE is a mask of the slots currently filled within the insn group.
8586 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8587 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8589 LEN is, of course, the length of the group in bytes. */
8592 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
8599 || GET_CODE (PATTERN (insn)) == CLOBBER
8600 || GET_CODE (PATTERN (insn)) == USE)
8605 enum alphaev5_pipe pipe;
8607 pipe = alphaev5_insn_pipe (insn);
8611 /* Force complex instructions to start new groups. */
8615 /* If this is a completely unrecognized insn, its an asm.
8616 We don't know how long it is, so record length as -1 to
8617 signal a needed realignment. */
8618 if (recog_memoized (insn) < 0)
8621 len = get_attr_length (insn);
8624 /* ??? Most of the places below, we would like to abort, as
8625 it would indicate an error either in Haifa, or in the
8626 scheduling description. Unfortunately, Haifa never
8627 schedules the last instruction of the BB, so we don't
8628 have an accurate TI bit to go off. */
8630 if (in_use & EV5_E0)
8632 if (in_use & EV5_E1)
8637 in_use |= EV5_E0 | EV5_E01;
8641 if (in_use & EV5_E0)
8643 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
8651 if (in_use & EV5_E1)
8657 if (in_use & EV5_FA)
8659 if (in_use & EV5_FM)
8664 in_use |= EV5_FA | EV5_FAM;
8668 if (in_use & EV5_FA)
8674 if (in_use & EV5_FM)
8687 /* Haifa doesn't do well scheduling branches. */
8688 /* ??? If this is predicted not-taken, slotting continues, except
8689 that no more IBR, FBR, or JSR insns may be slotted. */
8690 if (GET_CODE (insn) == JUMP_INSN)
8694 insn = next_nonnote_insn (insn);
8696 if (!insn || ! INSN_P (insn))
8699 /* Let Haifa tell us where it thinks insn group boundaries are. */
8700 if (GET_MODE (insn) == TImode)
8703 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8708 insn = next_nonnote_insn (insn);
8717 alphaev4_next_nop (int *pin_use)
8719 int in_use = *pin_use;
8722 if (!(in_use & EV4_IB0))
8727 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8732 else if (TARGET_FP && !(in_use & EV4_IB1))
8745 alphaev5_next_nop (int *pin_use)
8747 int in_use = *pin_use;
8750 if (!(in_use & EV5_E1))
8755 else if (TARGET_FP && !(in_use & EV5_FA))
8760 else if (TARGET_FP && !(in_use & EV5_FM))
8772 /* The instruction group alignment main loop. */
8775 alpha_align_insns (unsigned int max_align,
8776 rtx (*next_group) (rtx, int *, int *),
8777 rtx (*next_nop) (int *))
8779 /* ALIGN is the known alignment for the insn group. */
8781 /* OFS is the offset of the current insn in the insn group. */
8783 int prev_in_use, in_use, len;
8786 /* Let shorten branches care for assigning alignments to code labels. */
8787 shorten_branches (get_insns ());
8789 if (align_functions < 4)
8791 else if ((unsigned int) align_functions < max_align)
8792 align = align_functions;
8796 ofs = prev_in_use = 0;
8798 if (GET_CODE (i) == NOTE)
8799 i = next_nonnote_insn (i);
8803 next = (*next_group) (i, &in_use, &len);
8805 /* When we see a label, resync alignment etc. */
8806 if (GET_CODE (i) == CODE_LABEL)
8808 unsigned int new_align = 1 << label_to_alignment (i);
8810 if (new_align >= align)
8812 align = new_align < max_align ? new_align : max_align;
8816 else if (ofs & (new_align-1))
8817 ofs = (ofs | (new_align-1)) + 1;
8822 /* Handle complex instructions special. */
8823 else if (in_use == 0)
8825 /* Asms will have length < 0. This is a signal that we have
8826 lost alignment knowledge. Assume, however, that the asm
8827 will not mis-align instructions. */
8836 /* If the known alignment is smaller than the recognized insn group,
8837 realign the output. */
8838 else if ((int) align < len)
8840 unsigned int new_log_align = len > 8 ? 4 : 3;
8843 where = prev = prev_nonnote_insn (i);
8844 if (!where || GET_CODE (where) != CODE_LABEL)
8847 /* Can't realign between a call and its gp reload. */
8848 if (! (TARGET_EXPLICIT_RELOCS
8849 && prev && GET_CODE (prev) == CALL_INSN))
8851 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8852 align = 1 << new_log_align;
8857 /* If the group won't fit in the same INT16 as the previous,
8858 we need to add padding to keep the group together. Rather
8859 than simply leaving the insn filling to the assembler, we
8860 can make use of the knowledge of what sorts of instructions
8861 were issued in the previous group to make sure that all of
8862 the added nops are really free. */
8863 else if (ofs + len > (int) align)
8865 int nop_count = (align - ofs) / 4;
8868 /* Insert nops before labels, branches, and calls to truly merge
8869 the execution of the nops with the previous instruction group. */
8870 where = prev_nonnote_insn (i);
8873 if (GET_CODE (where) == CODE_LABEL)
8875 rtx where2 = prev_nonnote_insn (where);
8876 if (where2 && GET_CODE (where2) == JUMP_INSN)
8879 else if (GET_CODE (where) == INSN)
8886 emit_insn_before ((*next_nop)(&prev_in_use), where);
8887 while (--nop_count);
8891 ofs = (ofs + len) & (align - 1);
8892 prev_in_use = in_use;
8897 /* Machine dependent reorg pass. */
8902 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8903 alpha_handle_trap_shadows ();
8905 /* Due to the number of extra trapb insns, don't bother fixing up
8906 alignment when trap precision is instruction. Moreover, we can
8907 only do our job when sched2 is run. */
8908 if (optimize && !optimize_size
8909 && alpha_tp != ALPHA_TP_INSN
8910 && flag_schedule_insns_after_reload)
8912 if (alpha_cpu == PROCESSOR_EV4)
8913 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8914 else if (alpha_cpu == PROCESSOR_EV5)
8915 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8919 #if !TARGET_ABI_UNICOSMK
8926 alpha_file_start (void)
8928 #ifdef OBJECT_FORMAT_ELF
8929 /* If emitting dwarf2 debug information, we cannot generate a .file
8930 directive to start the file, as it will conflict with dwarf2out
8931 file numbers. So it's only useful when emitting mdebug output. */
8932 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8935 default_file_start ();
8937 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8940 fputs ("\t.set noreorder\n", asm_out_file);
8941 fputs ("\t.set volatile\n", asm_out_file);
8942 if (!TARGET_ABI_OPEN_VMS)
8943 fputs ("\t.set noat\n", asm_out_file);
8944 if (TARGET_EXPLICIT_RELOCS)
8945 fputs ("\t.set nomacro\n", asm_out_file);
8946 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
8947 fprintf (asm_out_file,
8949 TARGET_CPU_EV6 ? "ev6"
8951 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
8956 #ifdef OBJECT_FORMAT_ELF
8958 /* Switch to the section to which we should output X. The only thing
8959 special we do here is to honor small data. */
8962 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
8963 unsigned HOST_WIDE_INT align)
8965 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8966 /* ??? Consider using mergeable sdata sections. */
8969 default_elf_select_rtx_section (mode, x, align);
8972 #endif /* OBJECT_FORMAT_ELF */
8974 /* Structure to collect function names for final output in link section. */
8975 /* Note that items marked with GTY can't be ifdef'ed out. */
8977 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
8978 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
8980 struct alpha_links GTY(())
8984 enum links_kind lkind;
8985 enum reloc_kind rkind;
8988 struct alpha_funcs GTY(())
8991 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8995 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8996 splay_tree alpha_links_tree;
8997 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
8998 splay_tree alpha_funcs_tree;
9000 static GTY(()) int alpha_funcs_num;
9002 #if TARGET_ABI_OPEN_VMS
9004 /* Return the VMS argument type corresponding to MODE. */
9007 alpha_arg_type (enum machine_mode mode)
9012 return TARGET_FLOAT_VAX ? FF : FS;
9014 return TARGET_FLOAT_VAX ? FD : FT;
9020 /* Return an rtx for an integer representing the VMS Argument Information
9024 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
9026 unsigned HOST_WIDE_INT regval = cum.num_args;
9029 for (i = 0; i < 6; i++)
9030 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
9032 return GEN_INT (regval);
9035 /* Make (or fake) .linkage entry for function call.
9037 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9039 Return an SYMBOL_REF rtx for the linkage. */
9042 alpha_need_linkage (const char *name, int is_local)
9044 splay_tree_node node;
9045 struct alpha_links *al;
9052 struct alpha_funcs *cfaf;
9054 if (!alpha_funcs_tree)
9055 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
9056 splay_tree_compare_pointers);
9058 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
9061 cfaf->num = ++alpha_funcs_num;
9063 splay_tree_insert (alpha_funcs_tree,
9064 (splay_tree_key) current_function_decl,
9065 (splay_tree_value) cfaf);
9068 if (alpha_links_tree)
9070 /* Is this name already defined? */
9072 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9075 al = (struct alpha_links *) node->value;
9078 /* Defined here but external assumed. */
9079 if (al->lkind == KIND_EXTERN)
9080 al->lkind = KIND_LOCAL;
9084 /* Used here but unused assumed. */
9085 if (al->lkind == KIND_UNUSED)
9086 al->lkind = KIND_LOCAL;
9092 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9094 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9095 name = ggc_strdup (name);
9097 /* Assume external if no definition. */
9098 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9100 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9101 get_identifier (name);
9103 /* Construct a SYMBOL_REF for us to call. */
9105 size_t name_len = strlen (name);
9106 char *linksym = alloca (name_len + 6);
9108 memcpy (linksym + 1, name, name_len);
9109 memcpy (linksym + 1 + name_len, "..lk", 5);
9110 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9111 ggc_alloc_string (linksym, name_len + 5));
9114 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9115 (splay_tree_value) al);
9121 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
9123 splay_tree_node cfunnode;
9124 struct alpha_funcs *cfaf;
9125 struct alpha_links *al;
9126 const char *name = XSTR (linkage, 0);
9128 cfaf = (struct alpha_funcs *) 0;
9129 al = (struct alpha_links *) 0;
9131 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9132 cfaf = (struct alpha_funcs *) cfunnode->value;
9136 splay_tree_node lnode;
9138 /* Is this name already defined? */
9140 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9142 al = (struct alpha_links *) lnode->value;
9145 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9153 splay_tree_node node = 0;
9154 struct alpha_links *anl;
9159 name_len = strlen (name);
9161 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9162 al->num = cfaf->num;
9164 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9167 anl = (struct alpha_links *) node->value;
9168 al->lkind = anl->lkind;
9171 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9172 buflen = strlen (buf);
9173 linksym = alloca (buflen + 1);
9174 memcpy (linksym, buf, buflen + 1);
9176 al->linkage = gen_rtx_SYMBOL_REF
9177 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9179 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9180 (splay_tree_value) al);
9184 al->rkind = KIND_CODEADDR;
9186 al->rkind = KIND_LINKAGE;
9189 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9195 alpha_write_one_linkage (splay_tree_node node, void *data)
9197 const char *const name = (const char *) node->key;
9198 struct alpha_links *link = (struct alpha_links *) node->value;
9199 FILE *stream = (FILE *) data;
9201 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9202 if (link->rkind == KIND_CODEADDR)
9204 if (link->lkind == KIND_LOCAL)
9206 /* Local and used */
9207 fprintf (stream, "\t.quad %s..en\n", name);
9211 /* External and used, request code address. */
9212 fprintf (stream, "\t.code_address %s\n", name);
9217 if (link->lkind == KIND_LOCAL)
9219 /* Local and used, build linkage pair. */
9220 fprintf (stream, "\t.quad %s..en\n", name);
9221 fprintf (stream, "\t.quad %s\n", name);
9225 /* External and used, request linkage pair. */
9226 fprintf (stream, "\t.linkage %s\n", name);
9234 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
9236 splay_tree_node node;
9237 struct alpha_funcs *func;
9240 fprintf (stream, "\t.align 3\n");
9241 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9242 func = (struct alpha_funcs *) node->value;
9244 fputs ("\t.name ", stream);
9245 assemble_name (stream, funname);
9246 fputs ("..na\n", stream);
9247 ASM_OUTPUT_LABEL (stream, funname);
9248 fprintf (stream, "\t.pdesc ");
9249 assemble_name (stream, funname);
9250 fprintf (stream, "..en,%s\n",
9251 alpha_procedure_type == PT_STACK ? "stack"
9252 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9256 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9257 /* splay_tree_delete (func->links); */
9261 /* Given a decl, a section name, and whether the decl initializer
9262 has relocs, choose attributes for the section. */
9264 #define SECTION_VMS_OVERLAY SECTION_FORGET
9265 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9266 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9269 vms_section_type_flags (tree decl, const char *name, int reloc)
9271 unsigned int flags = default_section_type_flags (decl, name, reloc);
9273 if (decl && DECL_ATTRIBUTES (decl)
9274 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
9275 flags |= SECTION_VMS_OVERLAY;
9276 if (decl && DECL_ATTRIBUTES (decl)
9277 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9278 flags |= SECTION_VMS_GLOBAL;
9279 if (decl && DECL_ATTRIBUTES (decl)
9280 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9281 flags |= SECTION_VMS_INITIALIZE;
9286 /* Switch to an arbitrary section NAME with attributes as specified
9287 by FLAGS. ALIGN specifies any known alignment requirements for
9288 the section; 0 if the default should be used. */
9291 vms_asm_named_section (const char *name, unsigned int flags)
9293 fputc ('\n', asm_out_file);
9294 fprintf (asm_out_file, ".section\t%s", name);
9296 if (flags & SECTION_VMS_OVERLAY)
9297 fprintf (asm_out_file, ",OVR");
9298 if (flags & SECTION_VMS_GLOBAL)
9299 fprintf (asm_out_file, ",GBL");
9300 if (flags & SECTION_VMS_INITIALIZE)
9301 fprintf (asm_out_file, ",NOMOD");
9302 if (flags & SECTION_DEBUG)
9303 fprintf (asm_out_file, ",NOWRT");
9305 fputc ('\n', asm_out_file);
9308 /* Record an element in the table of global constructors. SYMBOL is
9309 a SYMBOL_REF of the function to be called; PRIORITY is a number
9310 between 0 and MAX_INIT_PRIORITY.
9312 Differs from default_ctors_section_asm_out_constructor in that the
9313 width of the .ctors entry is always 64 bits, rather than the 32 bits
9314 used by a normal pointer. */
9317 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9320 assemble_align (BITS_PER_WORD);
9321 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9325 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9328 assemble_align (BITS_PER_WORD);
9329 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9334 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
9335 int is_local ATTRIBUTE_UNUSED)
9341 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
9342 tree cfundecl ATTRIBUTE_UNUSED,
9343 int lflag ATTRIBUTE_UNUSED,
9344 int rflag ATTRIBUTE_UNUSED)
9349 #endif /* TARGET_ABI_OPEN_VMS */
9351 #if TARGET_ABI_UNICOSMK
9353 /* Define the offset between two registers, one to be eliminated, and the
9354 other its replacement, at the start of a routine. */
9357 unicosmk_initial_elimination_offset (int from, int to)
9361 fixed_size = alpha_sa_size();
9362 if (fixed_size != 0)
9365 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9367 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9369 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9370 return (ALPHA_ROUND (current_function_outgoing_args_size)
9371 + ALPHA_ROUND (get_frame_size()));
9372 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9373 return (ALPHA_ROUND (fixed_size)
9374 + ALPHA_ROUND (get_frame_size()
9375 + current_function_outgoing_args_size));
9380 /* Output the module name for .ident and .end directives. We have to strip
9381 directories and add make sure that the module name starts with a letter
9385 unicosmk_output_module_name (FILE *file)
9387 const char *name = lbasename (main_input_filename);
9388 unsigned len = strlen (name);
9389 char *clean_name = alloca (len + 2);
9390 char *ptr = clean_name;
9392 /* CAM only accepts module names that start with a letter or '$'. We
9393 prefix the module name with a '$' if necessary. */
9395 if (!ISALPHA (*name))
9397 memcpy (ptr, name, len + 1);
9398 clean_symbol_name (clean_name);
9399 fputs (clean_name, file);
9402 /* Output the definition of a common variable. */
9405 unicosmk_output_common (FILE *file, const char *name, int size, int align)
9408 printf ("T3E__: common %s\n", name);
9411 fputs("\t.endp\n\n\t.psect ", file);
9412 assemble_name(file, name);
9413 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9414 fprintf(file, "\t.byte\t0:%d\n", size);
9416 /* Mark the symbol as defined in this module. */
9417 name_tree = get_identifier (name);
9418 TREE_ASM_WRITTEN (name_tree) = 1;
9421 #define SECTION_PUBLIC SECTION_MACH_DEP
9422 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9423 static int current_section_align;
9426 unicosmk_section_type_flags (tree decl, const char *name,
9427 int reloc ATTRIBUTE_UNUSED)
9429 unsigned int flags = default_section_type_flags (decl, name, reloc);
9434 if (TREE_CODE (decl) == FUNCTION_DECL)
9436 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9437 if (align_functions_log > current_section_align)
9438 current_section_align = align_functions_log;
9440 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9441 flags |= SECTION_MAIN;
9444 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9446 if (TREE_PUBLIC (decl))
9447 flags |= SECTION_PUBLIC;
9452 /* Generate a section name for decl and associate it with the
9456 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
9464 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9465 name = default_strip_name_encoding (name);
9466 len = strlen (name);
9468 if (TREE_CODE (decl) == FUNCTION_DECL)
9472 /* It is essential that we prefix the section name here because
9473 otherwise the section names generated for constructors and
9474 destructors confuse collect2. */
9476 string = alloca (len + 6);
9477 sprintf (string, "code@%s", name);
9478 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9480 else if (TREE_PUBLIC (decl))
9481 DECL_SECTION_NAME (decl) = build_string (len, name);
9486 string = alloca (len + 6);
9487 sprintf (string, "data@%s", name);
9488 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9492 /* Switch to an arbitrary section NAME with attributes as specified
9493 by FLAGS. ALIGN specifies any known alignment requirements for
9494 the section; 0 if the default should be used. */
9497 unicosmk_asm_named_section (const char *name, unsigned int flags)
9501 /* Close the previous section. */
9503 fputs ("\t.endp\n\n", asm_out_file);
9505 /* Find out what kind of section we are opening. */
9507 if (flags & SECTION_MAIN)
9508 fputs ("\t.start\tmain\n", asm_out_file);
9510 if (flags & SECTION_CODE)
9512 else if (flags & SECTION_PUBLIC)
9517 if (current_section_align != 0)
9518 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9519 current_section_align, kind);
9521 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9525 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
9528 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
9529 unicosmk_unique_section (decl, 0);
9532 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9533 in code sections because .align fill unused space with zeroes. */
9536 unicosmk_output_align (FILE *file, int align)
9538 if (inside_function)
9539 fprintf (file, "\tgcc@code@align\t%d\n", align);
9541 fprintf (file, "\t.align\t%d\n", align);
9544 /* Add a case vector to the current function's list of deferred case
9545 vectors. Case vectors have to be put into a separate section because CAM
9546 does not allow data definitions in code sections. */
9549 unicosmk_defer_case_vector (rtx lab, rtx vec)
9551 struct machine_function *machine = cfun->machine;
9553 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9554 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9555 machine->addr_list);
9558 /* Output a case vector. */
9561 unicosmk_output_addr_vec (FILE *file, rtx vec)
9563 rtx lab = XEXP (vec, 0);
9564 rtx body = XEXP (vec, 1);
9565 int vlen = XVECLEN (body, 0);
9568 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
9570 for (idx = 0; idx < vlen; idx++)
9572 ASM_OUTPUT_ADDR_VEC_ELT
9573 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9577 /* Output current function's deferred case vectors. */
9580 unicosmk_output_deferred_case_vectors (FILE *file)
9582 struct machine_function *machine = cfun->machine;
9585 if (machine->addr_list == NULL_RTX)
9589 for (t = machine->addr_list; t; t = XEXP (t, 1))
9590 unicosmk_output_addr_vec (file, XEXP (t, 0));
9593 /* Generate the name of the SSIB section for the current function. */
9595 #define SSIB_PREFIX "__SSIB_"
9596 #define SSIB_PREFIX_LEN 7
9599 unicosmk_ssib_name (void)
9601 /* This is ok since CAM won't be able to deal with names longer than that
9604 static char name[256];
9610 x = DECL_RTL (cfun->decl);
9611 if (GET_CODE (x) != MEM)
9614 if (GET_CODE (x) != SYMBOL_REF)
9616 fnname = XSTR (x, 0);
9618 len = strlen (fnname);
9619 if (len + SSIB_PREFIX_LEN > 255)
9620 len = 255 - SSIB_PREFIX_LEN;
9622 strcpy (name, SSIB_PREFIX);
9623 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9624 name[len + SSIB_PREFIX_LEN] = 0;
9629 /* Set up the dynamic subprogram information block (DSIB) and update the
9630 frame pointer register ($15) for subroutines which have a frame. If the
9631 subroutine doesn't have a frame, simply increment $15. */
9634 unicosmk_gen_dsib (unsigned long *imaskP)
9636 if (alpha_procedure_type == PT_STACK)
9638 const char *ssib_name;
9641 /* Allocate 64 bytes for the DSIB. */
9643 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9645 emit_insn (gen_blockage ());
9647 /* Save the return address. */
9649 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9650 set_mem_alias_set (mem, alpha_sr_alias_set);
9651 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9652 (*imaskP) &= ~(1UL << REG_RA);
9654 /* Save the old frame pointer. */
9656 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9657 set_mem_alias_set (mem, alpha_sr_alias_set);
9658 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9659 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
9661 emit_insn (gen_blockage ());
9663 /* Store the SSIB pointer. */
9665 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9666 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9667 set_mem_alias_set (mem, alpha_sr_alias_set);
9669 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9670 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9671 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9673 /* Save the CIW index. */
9675 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9676 set_mem_alias_set (mem, alpha_sr_alias_set);
9677 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9679 emit_insn (gen_blockage ());
9681 /* Set the new frame pointer. */
9683 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9684 stack_pointer_rtx, GEN_INT (64))));
9689 /* Increment the frame pointer register to indicate that we do not
9692 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9693 hard_frame_pointer_rtx, const1_rtx)));
9697 /* Output the static subroutine information block for the current
9701 unicosmk_output_ssib (FILE *file, const char *fnname)
9707 struct machine_function *machine = cfun->machine;
9710 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9711 unicosmk_ssib_name ());
9713 /* Some required stuff and the function name length. */
9715 len = strlen (fnname);
9716 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9719 ??? We don't do that yet. */
9721 fputs ("\t.quad\t0\n", file);
9723 /* Function address. */
9725 fputs ("\t.quad\t", file);
9726 assemble_name (file, fnname);
9729 fputs ("\t.quad\t0\n", file);
9730 fputs ("\t.quad\t0\n", file);
9733 ??? We do it the same way Cray CC does it but this could be
9736 for( i = 0; i < len; i++ )
9737 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9738 if( (len % 8) == 0 )
9739 fputs ("\t.quad\t0\n", file);
9741 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9743 /* All call information words used in the function. */
9745 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9748 #if HOST_BITS_PER_WIDE_INT == 32
9749 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
9750 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9752 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
9757 /* Add a call information word (CIW) to the list of the current function's
9758 CIWs and return its index.
9760 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9763 unicosmk_add_call_info_word (rtx x)
9766 struct machine_function *machine = cfun->machine;
9768 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9769 if (machine->first_ciw == NULL_RTX)
9770 machine->first_ciw = node;
9772 XEXP (machine->last_ciw, 1) = node;
9774 machine->last_ciw = node;
9775 ++machine->ciw_count;
9777 return GEN_INT (machine->ciw_count
9778 + strlen (current_function_name ())/8 + 5);
9781 static char unicosmk_section_buf[100];
9784 unicosmk_text_section (void)
9786 static int count = 0;
9787 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9789 return unicosmk_section_buf;
9793 unicosmk_data_section (void)
9795 static int count = 1;
9796 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9798 return unicosmk_section_buf;
9801 /* The Cray assembler doesn't accept extern declarations for symbols which
9802 are defined in the same file. We have to keep track of all global
9803 symbols which are referenced and/or defined in a source file and output
9804 extern declarations for those which are referenced but not defined at
9807 /* List of identifiers for which an extern declaration might have to be
9809 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9811 struct unicosmk_extern_list
9813 struct unicosmk_extern_list *next;
9817 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9819 /* Output extern declarations which are required for every asm file. */
9822 unicosmk_output_default_externs (FILE *file)
9824 static const char *const externs[] =
9825 { "__T3E_MISMATCH" };
9830 n = ARRAY_SIZE (externs);
9832 for (i = 0; i < n; i++)
9833 fprintf (file, "\t.extern\t%s\n", externs[i]);
9836 /* Output extern declarations for global symbols which are have been
9837 referenced but not defined. */
9840 unicosmk_output_externs (FILE *file)
9842 struct unicosmk_extern_list *p;
9843 const char *real_name;
9847 len = strlen (user_label_prefix);
9848 for (p = unicosmk_extern_head; p != 0; p = p->next)
9850 /* We have to strip the encoding and possibly remove user_label_prefix
9851 from the identifier in order to handle -fleading-underscore and
9852 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9853 real_name = default_strip_name_encoding (p->name);
9854 if (len && p->name[0] == '*'
9855 && !memcmp (real_name, user_label_prefix, len))
9858 name_tree = get_identifier (real_name);
9859 if (! TREE_ASM_WRITTEN (name_tree))
9861 TREE_ASM_WRITTEN (name_tree) = 1;
9862 fputs ("\t.extern\t", file);
9863 assemble_name (file, p->name);
9869 /* Record an extern. */
9872 unicosmk_add_extern (const char *name)
9874 struct unicosmk_extern_list *p;
9876 p = (struct unicosmk_extern_list *)
9877 xmalloc (sizeof (struct unicosmk_extern_list));
9878 p->next = unicosmk_extern_head;
9880 unicosmk_extern_head = p;
9883 /* The Cray assembler generates incorrect code if identifiers which
9884 conflict with register names are used as instruction operands. We have
9885 to replace such identifiers with DEX expressions. */
9887 /* Structure to collect identifiers which have been replaced by DEX
9889 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9891 struct unicosmk_dex {
9892 struct unicosmk_dex *next;
9896 /* List of identifiers which have been replaced by DEX expressions. The DEX
9897 number is determined by the position in the list. */
9899 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9901 /* The number of elements in the DEX list. */
9903 static int unicosmk_dex_count = 0;
9905 /* Check if NAME must be replaced by a DEX expression. */
9908 unicosmk_special_name (const char *name)
9916 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9922 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9925 return (name[2] == '\0'
9926 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9929 return (ISDIGIT (name[1]) && name[2] == '\0');
9933 /* Return the DEX number if X must be replaced by a DEX expression and 0
9937 unicosmk_need_dex (rtx x)
9939 struct unicosmk_dex *dex;
9943 if (GET_CODE (x) != SYMBOL_REF)
9947 if (! unicosmk_special_name (name))
9950 i = unicosmk_dex_count;
9951 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9953 if (! strcmp (name, dex->name))
9958 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
9960 dex->next = unicosmk_dex_list;
9961 unicosmk_dex_list = dex;
9963 ++unicosmk_dex_count;
9964 return unicosmk_dex_count;
9967 /* Output the DEX definitions for this file. */
9970 unicosmk_output_dex (FILE *file)
9972 struct unicosmk_dex *dex;
9975 if (unicosmk_dex_list == NULL)
9978 fprintf (file, "\t.dexstart\n");
9980 i = unicosmk_dex_count;
9981 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9983 fprintf (file, "\tDEX (%d) = ", i);
9984 assemble_name (file, dex->name);
9989 fprintf (file, "\t.dexend\n");
9992 /* Output text that to appear at the beginning of an assembler file. */
9995 unicosmk_file_start (void)
9999 fputs ("\t.ident\t", asm_out_file);
10000 unicosmk_output_module_name (asm_out_file);
10001 fputs ("\n\n", asm_out_file);
10003 /* The Unicos/Mk assembler uses different register names. Instead of trying
10004 to support them, we simply use micro definitions. */
10006 /* CAM has different register names: rN for the integer register N and fN
10007 for the floating-point register N. Instead of trying to use these in
10008 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10011 for (i = 0; i < 32; ++i)
10012 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
10014 for (i = 0; i < 32; ++i)
10015 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
10017 putc ('\n', asm_out_file);
10019 /* The .align directive fill unused space with zeroes which does not work
10020 in code sections. We define the macro 'gcc@code@align' which uses nops
10021 instead. Note that it assumes that code sections always have the
10022 biggest possible alignment since . refers to the current offset from
10023 the beginning of the section. */
10025 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
10026 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
10027 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
10028 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
10029 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
10030 fputs ("\tbis r31,r31,r31\n", asm_out_file);
10031 fputs ("\t.endr\n", asm_out_file);
10032 fputs ("\t.endif\n", asm_out_file);
10033 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
10035 /* Output extern declarations which should always be visible. */
10036 unicosmk_output_default_externs (asm_out_file);
10038 /* Open a dummy section. We always need to be inside a section for the
10039 section-switching code to work correctly.
10040 ??? This should be a module id or something like that. I still have to
10041 figure out what the rules for those are. */
10042 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10045 /* Output text to appear at the end of an assembler file. This includes all
10046 pending extern declarations and DEX expressions. */
10049 unicosmk_file_end (void)
10051 fputs ("\t.endp\n\n", asm_out_file);
10053 /* Output all pending externs. */
10055 unicosmk_output_externs (asm_out_file);
10057 /* Output dex definitions used for functions whose names conflict with
10060 unicosmk_output_dex (asm_out_file);
10062 fputs ("\t.end\t", asm_out_file);
10063 unicosmk_output_module_name (asm_out_file);
10064 putc ('\n', asm_out_file);
10070 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10074 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10078 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10079 const char * fnname ATTRIBUTE_UNUSED)
10083 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10089 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10094 #endif /* TARGET_ABI_UNICOSMK */
10097 alpha_init_libfuncs (void)
10099 if (TARGET_ABI_UNICOSMK)
10101 /* Prevent gcc from generating calls to __divsi3. */
10102 set_optab_libfunc (sdiv_optab, SImode, 0);
10103 set_optab_libfunc (udiv_optab, SImode, 0);
10105 /* Use the functions provided by the system library
10106 for DImode integer division. */
10107 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10108 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10110 else if (TARGET_ABI_OPEN_VMS)
10112 /* Use the VMS runtime library functions for division and
10114 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10115 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10116 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10117 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10118 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10119 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10120 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10121 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10126 /* Initialize the GCC target structure. */
10127 #if TARGET_ABI_OPEN_VMS
10128 # undef TARGET_ATTRIBUTE_TABLE
10129 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10130 # undef TARGET_SECTION_TYPE_FLAGS
10131 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10134 #undef TARGET_IN_SMALL_DATA_P
10135 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10137 #if TARGET_ABI_UNICOSMK
10138 # undef TARGET_INSERT_ATTRIBUTES
10139 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10140 # undef TARGET_SECTION_TYPE_FLAGS
10141 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10142 # undef TARGET_ASM_UNIQUE_SECTION
10143 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10144 # undef TARGET_ASM_GLOBALIZE_LABEL
10145 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10148 #undef TARGET_ASM_ALIGNED_HI_OP
10149 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10150 #undef TARGET_ASM_ALIGNED_DI_OP
10151 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10153 /* Default unaligned ops are provided for ELF systems. To get unaligned
10154 data for non-ELF systems, we have to turn off auto alignment. */
10155 #ifndef OBJECT_FORMAT_ELF
10156 #undef TARGET_ASM_UNALIGNED_HI_OP
10157 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10158 #undef TARGET_ASM_UNALIGNED_SI_OP
10159 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10160 #undef TARGET_ASM_UNALIGNED_DI_OP
10161 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10164 #ifdef OBJECT_FORMAT_ELF
10165 #undef TARGET_ASM_SELECT_RTX_SECTION
10166 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10169 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10170 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10172 #undef TARGET_INIT_LIBFUNCS
10173 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10175 #if TARGET_ABI_UNICOSMK
10176 #undef TARGET_ASM_FILE_START
10177 #define TARGET_ASM_FILE_START unicosmk_file_start
10178 #undef TARGET_ASM_FILE_END
10179 #define TARGET_ASM_FILE_END unicosmk_file_end
10181 #undef TARGET_ASM_FILE_START
10182 #define TARGET_ASM_FILE_START alpha_file_start
10183 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10184 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10187 #undef TARGET_SCHED_ADJUST_COST
10188 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10189 #undef TARGET_SCHED_ISSUE_RATE
10190 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10191 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
10192 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
10193 alpha_use_dfa_pipeline_interface
10194 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10195 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10196 alpha_multipass_dfa_lookahead
10198 #undef TARGET_HAVE_TLS
10199 #define TARGET_HAVE_TLS HAVE_AS_TLS
10201 #undef TARGET_INIT_BUILTINS
10202 #define TARGET_INIT_BUILTINS alpha_init_builtins
10203 #undef TARGET_EXPAND_BUILTIN
10204 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10206 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10207 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10208 #undef TARGET_CANNOT_COPY_INSN_P
10209 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10212 #undef TARGET_ASM_OUTPUT_MI_THUNK
10213 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10214 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10215 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10218 #undef TARGET_RTX_COSTS
10219 #define TARGET_RTX_COSTS alpha_rtx_costs
10220 #undef TARGET_ADDRESS_COST
10221 #define TARGET_ADDRESS_COST hook_int_rtx_0
10223 #undef TARGET_MACHINE_DEPENDENT_REORG
10224 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10226 #undef TARGET_PROMOTE_FUNCTION_ARGS
10227 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10228 #undef TARGET_PROMOTE_FUNCTION_RETURN
10229 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10230 #undef TARGET_PROMOTE_PROTOTYPES
10231 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10232 #undef TARGET_RETURN_IN_MEMORY
10233 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10234 #undef TARGET_SETUP_INCOMING_VARARGS
10235 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10236 #undef TARGET_STRICT_ARGUMENT_NAMING
10237 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10238 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10239 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10240 #undef TARGET_SPLIT_COMPLEX_ARG
10241 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10242 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10243 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10245 #undef TARGET_BUILD_BUILTIN_VA_LIST
10246 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10248 struct gcc_target targetm = TARGET_INITIALIZER;
10251 #include "gt-alpha.h"