1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
57 /* Specify which cpu to schedule for. */
59 enum processor_type alpha_cpu;
60 static const char * const alpha_cpu_name[] =
65 /* Specify how accurate floating-point traps need to be. */
67 enum alpha_trap_precision alpha_tp;
69 /* Specify the floating-point rounding mode. */
71 enum alpha_fp_rounding_mode alpha_fprm;
73 /* Specify which things cause traps. */
75 enum alpha_fp_trap_mode alpha_fptm;
77 /* Specify bit size of immediate TLS offsets. */
79 int alpha_tls_size = 32;
81 /* Strings decoded into the above options. */
83 const char *alpha_cpu_string; /* -mcpu= */
84 const char *alpha_tune_string; /* -mtune= */
85 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
86 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
87 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
88 const char *alpha_mlat_string; /* -mmemory-latency= */
89 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
91 /* Save information from a "cmpxx" operation until the branch or scc is
94 struct alpha_compare alpha_compare;
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
99 static int inside_function = FALSE;
101 /* The number of cycles of latency we should assume on memory reads. */
103 int alpha_memory_latency = 3;
105 /* Whether the function needs the GP. */
107 static int alpha_function_needs_gp;
109 /* The alias set for prologue/epilogue register save/restore. */
111 static GTY(()) int alpha_sr_alias_set;
113 /* The assembler name of the current function. */
115 static const char *alpha_fnname;
117 /* The next explicit relocation sequence number. */
118 extern GTY(()) int alpha_next_sequence_number;
119 int alpha_next_sequence_number = 1;
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
123 extern GTY(()) int alpha_this_literal_sequence_number;
124 extern GTY(()) int alpha_this_gpdisp_sequence_number;
125 int alpha_this_literal_sequence_number;
126 int alpha_this_gpdisp_sequence_number;
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
132 unsigned char fp_add;
133 unsigned char fp_mult;
134 unsigned char fp_div_sf;
135 unsigned char fp_div_df;
136 unsigned char int_mult_si;
137 unsigned char int_mult_di;
138 unsigned char int_shift;
139 unsigned char int_cmov;
140 unsigned short int_div;
143 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
146 COSTS_N_INSNS (6), /* fp_add */
147 COSTS_N_INSNS (6), /* fp_mult */
148 COSTS_N_INSNS (34), /* fp_div_sf */
149 COSTS_N_INSNS (63), /* fp_div_df */
150 COSTS_N_INSNS (23), /* int_mult_si */
151 COSTS_N_INSNS (23), /* int_mult_di */
152 COSTS_N_INSNS (2), /* int_shift */
153 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (97), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (15), /* fp_div_sf */
160 COSTS_N_INSNS (22), /* fp_div_df */
161 COSTS_N_INSNS (8), /* int_mult_si */
162 COSTS_N_INSNS (12), /* int_mult_di */
163 COSTS_N_INSNS (1) + 1, /* int_shift */
164 COSTS_N_INSNS (1), /* int_cmov */
165 COSTS_N_INSNS (83), /* int_div */
168 COSTS_N_INSNS (4), /* fp_add */
169 COSTS_N_INSNS (4), /* fp_mult */
170 COSTS_N_INSNS (12), /* fp_div_sf */
171 COSTS_N_INSNS (15), /* fp_div_df */
172 COSTS_N_INSNS (7), /* int_mult_si */
173 COSTS_N_INSNS (7), /* int_mult_di */
174 COSTS_N_INSNS (1), /* int_shift */
175 COSTS_N_INSNS (2), /* int_cmov */
176 COSTS_N_INSNS (86), /* int_div */
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
185 static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
187 COSTS_N_INSNS (1), /* fp_add */
188 COSTS_N_INSNS (1), /* fp_mult */
189 COSTS_N_INSNS (1), /* fp_div_sf */
190 COSTS_N_INSNS (1) + 1, /* fp_div_df */
191 COSTS_N_INSNS (1) + 1, /* int_mult_si */
192 COSTS_N_INSNS (1) + 2, /* int_mult_di */
193 COSTS_N_INSNS (1), /* int_shift */
194 COSTS_N_INSNS (1), /* int_cmov */
195 COSTS_N_INSNS (6), /* int_div */
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
202 #define NUM_ARGS current_function_args_info
208 /* Declarations of static functions. */
209 static struct machine_function *alpha_init_machine_status (void);
210 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
212 #if TARGET_ABI_OPEN_VMS
213 static void alpha_write_linkage (FILE *, const char *, tree);
216 static void unicosmk_output_deferred_case_vectors (FILE *);
217 static void unicosmk_gen_dsib (unsigned long *);
218 static void unicosmk_output_ssib (FILE *, const char *);
219 static int unicosmk_need_dex (rtx);
221 /* Parse target option strings. */
224 override_options (void)
227 static const struct cpu_table {
228 const char *const name;
229 const enum processor_type processor;
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
234 { "ev4", PROCESSOR_EV4, 0 },
235 { "ev45", PROCESSOR_EV4, 0 },
236 { "21064", PROCESSOR_EV4, 0 },
237 { "ev5", PROCESSOR_EV5, EV5_MASK },
238 { "21164", PROCESSOR_EV5, EV5_MASK },
239 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
240 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
241 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
242 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
243 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
244 { "ev6", PROCESSOR_EV6, EV6_MASK },
245 { "21264", PROCESSOR_EV6, EV6_MASK },
246 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
247 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
251 /* Unicos/Mk doesn't have shared libraries. */
252 if (TARGET_ABI_UNICOSMK && flag_pic)
254 warning ("-f%s ignored for Unicos/Mk (not supported)",
255 (flag_pic > 1) ? "PIC" : "pic");
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
261 if (TARGET_ABI_UNICOSMK)
262 alpha_fprm = ALPHA_FPRM_DYN;
264 alpha_fprm = ALPHA_FPRM_NORM;
266 alpha_tp = ALPHA_TP_PROG;
267 alpha_fptm = ALPHA_FPTM_N;
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
277 if (TARGET_ABI_UNICOSMK)
278 warning ("-mieee not supported on Unicos/Mk");
281 alpha_tp = ALPHA_TP_INSN;
282 alpha_fptm = ALPHA_FPTM_SU;
286 if (TARGET_IEEE_WITH_INEXACT)
288 if (TARGET_ABI_UNICOSMK)
289 warning ("-mieee-with-inexact not supported on Unicos/Mk");
292 alpha_tp = ALPHA_TP_INSN;
293 alpha_fptm = ALPHA_FPTM_SUI;
299 if (! strcmp (alpha_tp_string, "p"))
300 alpha_tp = ALPHA_TP_PROG;
301 else if (! strcmp (alpha_tp_string, "f"))
302 alpha_tp = ALPHA_TP_FUNC;
303 else if (! strcmp (alpha_tp_string, "i"))
304 alpha_tp = ALPHA_TP_INSN;
306 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
309 if (alpha_fprm_string)
311 if (! strcmp (alpha_fprm_string, "n"))
312 alpha_fprm = ALPHA_FPRM_NORM;
313 else if (! strcmp (alpha_fprm_string, "m"))
314 alpha_fprm = ALPHA_FPRM_MINF;
315 else if (! strcmp (alpha_fprm_string, "c"))
316 alpha_fprm = ALPHA_FPRM_CHOP;
317 else if (! strcmp (alpha_fprm_string,"d"))
318 alpha_fprm = ALPHA_FPRM_DYN;
320 error ("bad value `%s' for -mfp-rounding-mode switch",
324 if (alpha_fptm_string)
326 if (strcmp (alpha_fptm_string, "n") == 0)
327 alpha_fptm = ALPHA_FPTM_N;
328 else if (strcmp (alpha_fptm_string, "u") == 0)
329 alpha_fptm = ALPHA_FPTM_U;
330 else if (strcmp (alpha_fptm_string, "su") == 0)
331 alpha_fptm = ALPHA_FPTM_SU;
332 else if (strcmp (alpha_fptm_string, "sui") == 0)
333 alpha_fptm = ALPHA_FPTM_SUI;
335 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
338 if (alpha_tls_size_string)
340 if (strcmp (alpha_tls_size_string, "16") == 0)
342 else if (strcmp (alpha_tls_size_string, "32") == 0)
344 else if (strcmp (alpha_tls_size_string, "64") == 0)
347 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
351 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
352 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
354 if (alpha_cpu_string)
356 for (i = 0; cpu_table [i].name; i++)
357 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
359 alpha_cpu = cpu_table [i].processor;
360 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
361 | MASK_CPU_EV5 | MASK_CPU_EV6);
362 target_flags |= cpu_table [i].flags;
365 if (! cpu_table [i].name)
366 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
369 if (alpha_tune_string)
371 for (i = 0; cpu_table [i].name; i++)
372 if (! strcmp (alpha_tune_string, cpu_table [i].name))
374 alpha_cpu = cpu_table [i].processor;
377 if (! cpu_table [i].name)
378 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
381 /* Do some sanity checks on the above options. */
383 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
385 warning ("trap mode not supported on Unicos/Mk");
386 alpha_fptm = ALPHA_FPTM_N;
389 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
390 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
392 warning ("fp software completion requires -mtrap-precision=i");
393 alpha_tp = ALPHA_TP_INSN;
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
401 alpha_tp = ALPHA_TP_PROG;
404 if (TARGET_FLOAT_VAX)
406 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
408 warning ("rounding mode not supported for VAX floats");
409 alpha_fprm = ALPHA_FPRM_NORM;
411 if (alpha_fptm == ALPHA_FPTM_SUI)
413 warning ("trap mode not supported for VAX floats");
414 alpha_fptm = ALPHA_FPTM_SU;
416 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
417 warning ("128-bit long double not supported for VAX floats");
418 target_flags &= ~MASK_LONG_DOUBLE_128;
425 if (!alpha_mlat_string)
426 alpha_mlat_string = "L1";
428 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
429 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
431 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
432 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
433 && alpha_mlat_string[2] == '\0')
435 static int const cache_latency[][4] =
437 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
438 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
439 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
442 lat = alpha_mlat_string[1] - '0';
443 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
445 warning ("L%d cache latency unknown for %s",
446 lat, alpha_cpu_name[alpha_cpu]);
450 lat = cache_latency[alpha_cpu][lat-1];
452 else if (! strcmp (alpha_mlat_string, "main"))
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
460 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
464 alpha_memory_latency = lat;
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
473 target_flags |= MASK_SMALL_DATA;
474 else if (flag_pic == 2)
475 target_flags &= ~MASK_SMALL_DATA;
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
480 if (optimize > 0 && write_symbols != SDB_DEBUG)
482 if (align_loops <= 0)
484 if (align_jumps <= 0)
487 if (align_functions <= 0)
488 align_functions = 16;
490 /* Acquire a unique set number for our register saves and restores. */
491 alpha_sr_alias_set = new_alias_set ();
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
496 init_machine_status = alpha_init_machine_status;
498 /* Tell the compiler when we're using VAX floating point. */
499 if (TARGET_FLOAT_VAX)
501 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
502 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
503 REAL_MODE_FORMAT (TFmode) = NULL;
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
510 zap_mask (HOST_WIDE_INT value)
514 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
516 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
522 /* Return true if OP is valid for a particular TLS relocation.
523 We are already guaranteed that OP is a CONST. */
526 tls_symbolic_operand_1 (rtx op, int size, int unspec)
530 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
532 op = XVECEXP (op, 0, 0);
534 if (GET_CODE (op) != SYMBOL_REF)
537 if (SYMBOL_REF_LOCAL_P (op))
539 if (alpha_tls_size > size)
548 switch (SYMBOL_REF_TLS_MODEL (op))
550 case TLS_MODEL_LOCAL_DYNAMIC:
551 return unspec == UNSPEC_DTPREL;
552 case TLS_MODEL_INITIAL_EXEC:
553 return unspec == UNSPEC_TPREL && size == 64;
554 case TLS_MODEL_LOCAL_EXEC:
555 return unspec == UNSPEC_TPREL;
561 /* Used by aligned_memory_operand and unaligned_memory_operand to
562 resolve what reload is going to do with OP if it's a register. */
565 resolve_reload_operand (rtx op)
567 if (reload_in_progress)
570 if (GET_CODE (tmp) == SUBREG)
571 tmp = SUBREG_REG (tmp);
572 if (GET_CODE (tmp) == REG
573 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
575 op = reg_equiv_memory_loc[REGNO (tmp)];
583 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
584 the range defined for C in [I-P]. */
587 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
592 /* An unsigned 8 bit constant. */
593 return (unsigned HOST_WIDE_INT) value < 0x100;
595 /* The constant zero. */
598 /* A signed 16 bit constant. */
599 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
601 /* A shifted signed 16 bit constant appropriate for LDAH. */
602 return ((value & 0xffff) == 0
603 && ((value) >> 31 == -1 || value >> 31 == 0));
605 /* A constant that can be AND'ed with using a ZAP insn. */
606 return zap_mask (value);
608 /* A complemented unsigned 8 bit constant. */
609 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
611 /* A negated unsigned 8 bit constant. */
612 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
614 /* The constant 1, 2 or 3. */
615 return value == 1 || value == 2 || value == 3;
622 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
623 matches for C in [GH]. */
626 alpha_const_double_ok_for_letter_p (rtx value, int c)
631 /* The floating point zero constant. */
632 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
633 && value == CONST0_RTX (GET_MODE (value)));
636 /* A valid operand of a ZAP insn. */
637 return (GET_MODE (value) == VOIDmode
638 && zap_mask (CONST_DOUBLE_LOW (value))
639 && zap_mask (CONST_DOUBLE_HIGH (value)));
646 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
650 alpha_extra_constraint (rtx value, int c)
655 return normal_memory_operand (value, VOIDmode);
657 return direct_call_operand (value, Pmode);
659 return (GET_CODE (value) == CONST_INT
660 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
662 return GET_CODE (value) == HIGH;
664 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
666 return (GET_CODE (value) == CONST_VECTOR
667 && value == CONST0_RTX (GET_MODE (value)));
673 /* The scalar modes supported differs from the default check-what-c-supports
674 version in that sometimes TFmode is available even when long double
675 indicates only DFmode. On unicosmk, we have the situation that HImode
676 doesn't map to any C type, but of course we still support that. */
679 alpha_scalar_mode_supported_p (enum machine_mode mode)
687 case TImode: /* via optabs.c */
695 return TARGET_HAS_XFLOATING_LIBS;
702 /* Alpha implements a couple of integer vector mode operations when
703 TARGET_MAX is enabled. */
706 alpha_vector_mode_supported_p (enum machine_mode mode)
711 || mode == V2SImode))
717 /* Return 1 if this function can directly return via $26. */
722 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
724 && alpha_sa_size () == 0
725 && get_frame_size () == 0
726 && current_function_outgoing_args_size == 0
727 && current_function_pretend_args_size == 0);
730 /* Return the ADDR_VEC associated with a tablejump insn. */
733 alpha_tablejump_addr_vec (rtx insn)
737 tmp = JUMP_LABEL (insn);
740 tmp = NEXT_INSN (tmp);
743 if (GET_CODE (tmp) == JUMP_INSN
744 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
745 return PATTERN (tmp);
749 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
752 alpha_tablejump_best_label (rtx insn)
754 rtx jump_table = alpha_tablejump_addr_vec (insn);
755 rtx best_label = NULL_RTX;
757 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
758 there for edge frequency counts from profile data. */
762 int n_labels = XVECLEN (jump_table, 1);
766 for (i = 0; i < n_labels; i++)
770 for (j = i + 1; j < n_labels; j++)
771 if (XEXP (XVECEXP (jump_table, 1, i), 0)
772 == XEXP (XVECEXP (jump_table, 1, j), 0))
775 if (count > best_count)
776 best_count = count, best_label = XVECEXP (jump_table, 1, i);
780 return best_label ? best_label : const0_rtx;
783 /* Return the TLS model to use for SYMBOL. */
785 static enum tls_model
786 tls_symbolic_operand_type (rtx symbol)
788 enum tls_model model;
790 if (GET_CODE (symbol) != SYMBOL_REF)
792 model = SYMBOL_REF_TLS_MODEL (symbol);
794 /* Local-exec with a 64-bit size is the same code as initial-exec. */
795 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
796 model = TLS_MODEL_INITIAL_EXEC;
801 /* Return true if the function DECL will share the same GP as any
802 function in the current unit of translation. */
805 decl_has_samegp (tree decl)
807 /* Functions that are not local can be overridden, and thus may
808 not share the same gp. */
809 if (!(*targetm.binds_local_p) (decl))
812 /* If -msmall-data is in effect, assume that there is only one GP
813 for the module, and so any local symbol has this property. We
814 need explicit relocations to be able to enforce this for symbols
815 not defined in this unit of translation, however. */
816 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
819 /* Functions that are not external are defined in this UoT. */
820 /* ??? Irritatingly, static functions not yet emitted are still
821 marked "external". Apply this to non-static functions only. */
822 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
825 /* Return true if EXP should be placed in the small data section. */
828 alpha_in_small_data_p (tree exp)
830 /* We want to merge strings, so we never consider them small data. */
831 if (TREE_CODE (exp) == STRING_CST)
834 /* Functions are never in the small data area. Duh. */
835 if (TREE_CODE (exp) == FUNCTION_DECL)
838 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
840 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
841 if (strcmp (section, ".sdata") == 0
842 || strcmp (section, ".sbss") == 0)
847 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
849 /* If this is an incomplete type with size 0, then we can't put it
850 in sdata because it might be too big when completed. */
851 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
858 #if TARGET_ABI_OPEN_VMS
860 alpha_linkage_symbol_p (const char *symname)
862 int symlen = strlen (symname);
865 return strcmp (&symname [symlen - 4], "..lk") == 0;
870 #define LINKAGE_SYMBOL_REF_P(X) \
871 ((GET_CODE (X) == SYMBOL_REF \
872 && alpha_linkage_symbol_p (XSTR (X, 0))) \
873 || (GET_CODE (X) == CONST \
874 && GET_CODE (XEXP (X, 0)) == PLUS \
875 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
876 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
879 /* legitimate_address_p recognizes an RTL expression that is a valid
880 memory address for an instruction. The MODE argument is the
881 machine mode for the MEM expression that wants to use this address.
883 For Alpha, we have either a constant address or the sum of a
884 register and a constant address, or just a register. For DImode,
885 any of those forms can be surrounded with an AND that clear the
886 low-order three bits; this is an "unaligned" access. */
889 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
891 /* If this is an ldq_u type address, discard the outer AND. */
893 && GET_CODE (x) == AND
894 && GET_CODE (XEXP (x, 1)) == CONST_INT
895 && INTVAL (XEXP (x, 1)) == -8)
898 /* Discard non-paradoxical subregs. */
899 if (GET_CODE (x) == SUBREG
900 && (GET_MODE_SIZE (GET_MODE (x))
901 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
904 /* Unadorned general registers are valid. */
907 ? STRICT_REG_OK_FOR_BASE_P (x)
908 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
911 /* Constant addresses (i.e. +/- 32k) are valid. */
912 if (CONSTANT_ADDRESS_P (x))
915 #if TARGET_ABI_OPEN_VMS
916 if (LINKAGE_SYMBOL_REF_P (x))
920 /* Register plus a small constant offset is valid. */
921 if (GET_CODE (x) == PLUS)
923 rtx ofs = XEXP (x, 1);
926 /* Discard non-paradoxical subregs. */
927 if (GET_CODE (x) == SUBREG
928 && (GET_MODE_SIZE (GET_MODE (x))
929 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
935 && NONSTRICT_REG_OK_FP_BASE_P (x)
936 && GET_CODE (ofs) == CONST_INT)
939 ? STRICT_REG_OK_FOR_BASE_P (x)
940 : NONSTRICT_REG_OK_FOR_BASE_P (x))
941 && CONSTANT_ADDRESS_P (ofs))
946 /* If we're managing explicit relocations, LO_SUM is valid, as
947 are small data symbols. */
948 else if (TARGET_EXPLICIT_RELOCS)
950 if (small_symbolic_operand (x, Pmode))
953 if (GET_CODE (x) == LO_SUM)
955 rtx ofs = XEXP (x, 1);
958 /* Discard non-paradoxical subregs. */
959 if (GET_CODE (x) == SUBREG
960 && (GET_MODE_SIZE (GET_MODE (x))
961 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
964 /* Must have a valid base register. */
967 ? STRICT_REG_OK_FOR_BASE_P (x)
968 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
971 /* The symbol must be local. */
972 if (local_symbolic_operand (ofs, Pmode)
973 || dtp32_symbolic_operand (ofs, Pmode)
974 || tp32_symbolic_operand (ofs, Pmode))
982 /* Build the SYMBOL_REF for __tls_get_addr. */
984 static GTY(()) rtx tls_get_addr_libfunc;
987 get_tls_get_addr (void)
989 if (!tls_get_addr_libfunc)
990 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
991 return tls_get_addr_libfunc;
994 /* Try machine-dependent ways of modifying an illegitimate address
995 to be legitimate. If we find one, return the new, valid address. */
998 alpha_legitimize_address (rtx x, rtx scratch,
999 enum machine_mode mode ATTRIBUTE_UNUSED)
1001 HOST_WIDE_INT addend;
1003 /* If the address is (plus reg const_int) and the CONST_INT is not a
1004 valid offset, compute the high part of the constant and add it to
1005 the register. Then our address is (plus temp low-part-const). */
1006 if (GET_CODE (x) == PLUS
1007 && GET_CODE (XEXP (x, 0)) == REG
1008 && GET_CODE (XEXP (x, 1)) == CONST_INT
1009 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1011 addend = INTVAL (XEXP (x, 1));
1016 /* If the address is (const (plus FOO const_int)), find the low-order
1017 part of the CONST_INT. Then load FOO plus any high-order part of the
1018 CONST_INT into a register. Our address is (plus reg low-part-const).
1019 This is done to reduce the number of GOT entries. */
1021 && GET_CODE (x) == CONST
1022 && GET_CODE (XEXP (x, 0)) == PLUS
1023 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1025 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1026 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1030 /* If we have a (plus reg const), emit the load as in (2), then add
1031 the two registers, and finally generate (plus reg low-part-const) as
1034 && GET_CODE (x) == PLUS
1035 && GET_CODE (XEXP (x, 0)) == REG
1036 && GET_CODE (XEXP (x, 1)) == CONST
1037 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1038 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1040 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1041 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1042 XEXP (XEXP (XEXP (x, 1), 0), 0),
1043 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1047 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1048 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1050 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1052 switch (tls_symbolic_operand_type (x))
1054 case TLS_MODEL_GLOBAL_DYNAMIC:
1057 r0 = gen_rtx_REG (Pmode, 0);
1058 r16 = gen_rtx_REG (Pmode, 16);
1059 tga = get_tls_get_addr ();
1060 dest = gen_reg_rtx (Pmode);
1061 seq = GEN_INT (alpha_next_sequence_number++);
1063 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1064 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1065 insn = emit_call_insn (insn);
1066 CONST_OR_PURE_CALL_P (insn) = 1;
1067 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1069 insn = get_insns ();
1072 emit_libcall_block (insn, dest, r0, x);
1075 case TLS_MODEL_LOCAL_DYNAMIC:
1078 r0 = gen_rtx_REG (Pmode, 0);
1079 r16 = gen_rtx_REG (Pmode, 16);
1080 tga = get_tls_get_addr ();
1081 scratch = gen_reg_rtx (Pmode);
1082 seq = GEN_INT (alpha_next_sequence_number++);
1084 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1085 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1086 insn = emit_call_insn (insn);
1087 CONST_OR_PURE_CALL_P (insn) = 1;
1088 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1090 insn = get_insns ();
1093 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1094 UNSPEC_TLSLDM_CALL);
1095 emit_libcall_block (insn, scratch, r0, eqv);
1097 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1098 eqv = gen_rtx_CONST (Pmode, eqv);
1100 if (alpha_tls_size == 64)
1102 dest = gen_reg_rtx (Pmode);
1103 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1104 emit_insn (gen_adddi3 (dest, dest, scratch));
1107 if (alpha_tls_size == 32)
1109 insn = gen_rtx_HIGH (Pmode, eqv);
1110 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1111 scratch = gen_reg_rtx (Pmode);
1112 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1114 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1116 case TLS_MODEL_INITIAL_EXEC:
1117 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1118 eqv = gen_rtx_CONST (Pmode, eqv);
1119 tp = gen_reg_rtx (Pmode);
1120 scratch = gen_reg_rtx (Pmode);
1121 dest = gen_reg_rtx (Pmode);
1123 emit_insn (gen_load_tp (tp));
1124 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1125 emit_insn (gen_adddi3 (dest, tp, scratch));
1128 case TLS_MODEL_LOCAL_EXEC:
1129 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1130 eqv = gen_rtx_CONST (Pmode, eqv);
1131 tp = gen_reg_rtx (Pmode);
1133 emit_insn (gen_load_tp (tp));
1134 if (alpha_tls_size == 32)
1136 insn = gen_rtx_HIGH (Pmode, eqv);
1137 insn = gen_rtx_PLUS (Pmode, tp, insn);
1138 tp = gen_reg_rtx (Pmode);
1139 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1141 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1144 if (local_symbolic_operand (x, Pmode))
1146 if (small_symbolic_operand (x, Pmode))
1150 if (!no_new_pseudos)
1151 scratch = gen_reg_rtx (Pmode);
1152 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1153 gen_rtx_HIGH (Pmode, x)));
1154 return gen_rtx_LO_SUM (Pmode, scratch, x);
1163 HOST_WIDE_INT low, high;
1165 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1167 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1171 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1172 (no_new_pseudos ? scratch : NULL_RTX),
1173 1, OPTAB_LIB_WIDEN);
1175 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1176 (no_new_pseudos ? scratch : NULL_RTX),
1177 1, OPTAB_LIB_WIDEN);
1179 return plus_constant (x, low);
1183 /* Primarily this is required for TLS symbols, but given that our move
1184 patterns *ought* to be able to handle any symbol at any time, we
1185 should never be spilling symbolic operands to the constant pool, ever. */
1188 alpha_cannot_force_const_mem (rtx x)
1190 enum rtx_code code = GET_CODE (x);
1191 return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
1194 /* We do not allow indirect calls to be optimized into sibling calls, nor
1195 can we allow a call to a function with a different GP to be optimized
1199 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1201 /* Can't do indirect tail calls, since we don't know if the target
1202 uses the same GP. */
1206 /* Otherwise, we can make a tail call if the target function shares
1208 return decl_has_samegp (decl);
1211 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1212 small symbolic operand until after reload. At which point we need
1213 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1214 so that sched2 has the proper dependency information. */
1216 {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \
1221 some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1225 /* Don't re-split. */
1226 if (GET_CODE (x) == LO_SUM)
1229 return small_symbolic_operand (x, Pmode) != 0;
1233 some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1235 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
1239 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1243 /* Don't re-split. */
1244 if (GET_CODE (x) == LO_SUM)
1247 if (small_symbolic_operand (x, Pmode))
1249 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
1258 split_small_symbolic_operand (rtx x)
1261 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
1265 /* Indicate that INSN cannot be duplicated. This is true for any insn
1266 that we've marked with gpdisp relocs, since those have to stay in
1267 1-1 correspondence with one another.
1269 Technically we could copy them if we could set up a mapping from one
1270 sequence number to another, across the set of insns to be duplicated.
1271 This seems overly complicated and error-prone since interblock motion
1272 from sched-ebb could move one of the pair of insns to a different block.
1274 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1275 then they'll be in a different block from their ldgp. Which could lead
1276 the bb reorder code to think that it would be ok to copy just the block
1277 containing the call and branch to the block containing the ldgp. */
1280 alpha_cannot_copy_insn_p (rtx insn)
1282 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
1284 if (recog_memoized (insn) >= 0)
1285 return get_attr_cannot_copy (insn);
1291 /* Try a machine-dependent way of reloading an illegitimate address
1292 operand. If we find one, push the reload and return the new rtx. */
1295 alpha_legitimize_reload_address (rtx x,
1296 enum machine_mode mode ATTRIBUTE_UNUSED,
1297 int opnum, int type,
1298 int ind_levels ATTRIBUTE_UNUSED)
1300 /* We must recognize output that we have already generated ourselves. */
1301 if (GET_CODE (x) == PLUS
1302 && GET_CODE (XEXP (x, 0)) == PLUS
1303 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1304 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1305 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1307 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1308 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1313 /* We wish to handle large displacements off a base register by
1314 splitting the addend across an ldah and the mem insn. This
1315 cuts number of extra insns needed from 3 to 1. */
1316 if (GET_CODE (x) == PLUS
1317 && GET_CODE (XEXP (x, 0)) == REG
1318 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
1319 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
1320 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1322 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
1323 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1325 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1327 /* Check for 32-bit overflow. */
1328 if (high + low != val)
1331 /* Reload the high part into a base reg; leave the low part
1332 in the mem directly. */
1333 x = gen_rtx_PLUS (GET_MODE (x),
1334 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
1338 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1339 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1347 /* Compute a (partial) cost for rtx X. Return true if the complete
1348 cost has been computed, and false if subexpressions should be
1349 scanned. In either case, *TOTAL contains the cost result. */
1352 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
1354 enum machine_mode mode = GET_MODE (x);
1355 bool float_mode_p = FLOAT_MODE_P (mode);
1356 const struct alpha_rtx_cost_data *cost_data;
1359 cost_data = &alpha_rtx_cost_size;
1361 cost_data = &alpha_rtx_cost_data[alpha_cpu];
1366 /* If this is an 8-bit constant, return zero since it can be used
1367 nearly anywhere with no cost. If it is a valid operand for an
1368 ADD or AND, likewise return 0 if we know it will be used in that
1369 context. Otherwise, return 2 since it might be used there later.
1370 All other constants take at least two insns. */
1371 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
1379 if (x == CONST0_RTX (mode))
1381 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
1382 || (outer_code == AND && and_operand (x, VOIDmode)))
1384 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
1387 *total = COSTS_N_INSNS (2);
1393 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
1394 *total = COSTS_N_INSNS (outer_code != MEM);
1395 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
1396 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
1397 else if (tls_symbolic_operand_type (x))
1398 /* Estimate of cost for call_pal rduniq. */
1399 /* ??? How many insns do we emit here? More than one... */
1400 *total = COSTS_N_INSNS (15);
1402 /* Otherwise we do a load from the GOT. */
1403 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
1409 *total = cost_data->fp_add;
1410 else if (GET_CODE (XEXP (x, 0)) == MULT
1411 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
1413 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
1414 + rtx_cost (XEXP (x, 1), outer_code) + COSTS_N_INSNS (1));
1421 *total = cost_data->fp_mult;
1422 else if (mode == DImode)
1423 *total = cost_data->int_mult_di;
1425 *total = cost_data->int_mult_si;
1429 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1430 && INTVAL (XEXP (x, 1)) <= 3)
1432 *total = COSTS_N_INSNS (1);
1439 *total = cost_data->int_shift;
1444 *total = cost_data->fp_add;
1446 *total = cost_data->int_cmov;
1454 *total = cost_data->int_div;
1455 else if (mode == SFmode)
1456 *total = cost_data->fp_div_sf;
1458 *total = cost_data->fp_div_df;
1462 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
1468 *total = COSTS_N_INSNS (1);
1476 *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
1482 case UNSIGNED_FLOAT:
1486 case FLOAT_TRUNCATE:
1487 *total = cost_data->fp_add;
1495 /* REF is an alignable memory location. Place an aligned SImode
1496 reference into *PALIGNED_MEM and the number of bits to shift into
1497 *PBITNUM. SCRATCH is a free register for use in reloading out
1498 of range stack slots. */
1501 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
1504 HOST_WIDE_INT offset = 0;
1506 if (GET_CODE (ref) != MEM)
1509 if (reload_in_progress
1510 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1512 base = find_replacement (&XEXP (ref, 0));
1514 if (! memory_address_p (GET_MODE (ref), base))
1519 base = XEXP (ref, 0);
1522 if (GET_CODE (base) == PLUS)
1523 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1526 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
1528 if (WORDS_BIG_ENDIAN)
1529 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
1530 + (offset & 3) * 8));
1532 *pbitnum = GEN_INT ((offset & 3) * 8);
1535 /* Similar, but just get the address. Handle the two reload cases.
1536 Add EXTRA_OFFSET to the address we return. */
1539 get_unaligned_address (rtx ref, int extra_offset)
1542 HOST_WIDE_INT offset = 0;
1544 if (GET_CODE (ref) != MEM)
1547 if (reload_in_progress
1548 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1550 base = find_replacement (&XEXP (ref, 0));
1552 if (! memory_address_p (GET_MODE (ref), base))
1557 base = XEXP (ref, 0);
1560 if (GET_CODE (base) == PLUS)
1561 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1563 return plus_constant (base, offset + extra_offset);
1566 /* On the Alpha, all (non-symbolic) constants except zero go into
1567 a floating-point register via memory. Note that we cannot
1568 return anything that is not a subset of CLASS, and that some
1569 symbolic constants cannot be dropped to memory. */
1572 alpha_preferred_reload_class(rtx x, enum reg_class class)
1574 /* Zero is present in any register class. */
1575 if (x == CONST0_RTX (GET_MODE (x)))
1578 /* These sorts of constants we can easily drop to memory. */
1579 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
1581 if (class == FLOAT_REGS)
1583 if (class == ALL_REGS)
1584 return GENERAL_REGS;
1588 /* All other kinds of constants should not (and in the case of HIGH
1589 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1590 secondary reload. */
1592 return (class == ALL_REGS ? GENERAL_REGS : class);
1597 /* Loading and storing HImode or QImode values to and from memory
1598 usually requires a scratch register. The exceptions are loading
1599 QImode and HImode from an aligned address to a general register
1600 unless byte instructions are permitted.
1602 We also cannot load an unaligned address or a paradoxical SUBREG
1603 into an FP register.
1605 We also cannot do integral arithmetic into FP regs, as might result
1606 from register elimination into a DImode fp register. */
1609 secondary_reload_class (enum reg_class class, enum machine_mode mode,
1612 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
1614 if (GET_CODE (x) == MEM
1615 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
1616 || (GET_CODE (x) == SUBREG
1617 && (GET_CODE (SUBREG_REG (x)) == MEM
1618 || (GET_CODE (SUBREG_REG (x)) == REG
1619 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
1621 if (!in || !aligned_memory_operand(x, mode))
1622 return GENERAL_REGS;
1626 if (class == FLOAT_REGS)
1628 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
1629 return GENERAL_REGS;
1631 if (GET_CODE (x) == SUBREG
1632 && (GET_MODE_SIZE (GET_MODE (x))
1633 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1634 return GENERAL_REGS;
1636 if (in && INTEGRAL_MODE_P (mode)
1637 && ! (memory_operand (x, mode) || x == const0_rtx))
1638 return GENERAL_REGS;
1644 /* Subfunction of the following function. Update the flags of any MEM
1645 found in part of X. */
1648 alpha_set_memflags_1 (rtx *xp, void *data)
1650 rtx x = *xp, orig = (rtx) data;
1652 if (GET_CODE (x) != MEM)
1655 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig);
1656 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig);
1657 MEM_SCALAR_P (x) = MEM_SCALAR_P (orig);
1658 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig);
1659 MEM_READONLY_P (x) = MEM_READONLY_P (orig);
1661 /* Sadly, we cannot use alias sets because the extra aliasing
1662 produced by the AND interferes. Given that two-byte quantities
1663 are the only thing we would be able to differentiate anyway,
1664 there does not seem to be any point in convoluting the early
1665 out of the alias check. */
1670 /* Given INSN, which is an INSN list or the PATTERN of a single insn
1671 generated to perform a memory operation, look for any MEMs in either
1672 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1673 volatile flags from REF into each of the MEMs found. If REF is not
1674 a MEM, don't do anything. */
1677 alpha_set_memflags (rtx insn, rtx ref)
1681 if (GET_CODE (ref) != MEM)
1684 /* This is only called from alpha.md, after having had something
1685 generated from one of the insn patterns. So if everything is
1686 zero, the pattern is already up-to-date. */
1687 if (!MEM_VOLATILE_P (ref)
1688 && !MEM_IN_STRUCT_P (ref)
1689 && !MEM_SCALAR_P (ref)
1690 && !MEM_NOTRAP_P (ref)
1691 && !MEM_READONLY_P (ref))
1695 base_ptr = &PATTERN (insn);
1698 for_each_rtx (base_ptr, alpha_set_memflags_1, (void *) ref);
1701 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
1704 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
1705 HOST_WIDE_INT c, int n)
1709 /* Use a pseudo if highly optimizing and still generating RTL. */
1711 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
1714 /* If this is a sign-extended 32-bit constant, we can do this in at most
1715 three insns, so do it if we have enough insns left. We always have
1716 a sign-extended 32-bit constant when compiling on a narrow machine. */
1718 if (HOST_BITS_PER_WIDE_INT != 64
1719 || c >> 31 == -1 || c >> 31 == 0)
1721 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
1722 HOST_WIDE_INT tmp1 = c - low;
1723 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
1724 HOST_WIDE_INT extra = 0;
1726 /* If HIGH will be interpreted as negative but the constant is
1727 positive, we must adjust it to do two ldha insns. */
1729 if ((high & 0x8000) != 0 && c >= 0)
1733 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1736 if (c == low || (low == 0 && extra == 0))
1738 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1739 but that meant that we can't handle INT_MIN on 32-bit machines
1740 (like NT/Alpha), because we recurse indefinitely through
1741 emit_move_insn to gen_movdi. So instead, since we know exactly
1742 what we want, create it explicitly. */
1745 target = gen_reg_rtx (mode);
1746 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
1749 else if (n >= 2 + (extra != 0))
1753 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
1757 temp = copy_to_suggested_reg (GEN_INT (high << 16),
1760 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1761 This means that if we go through expand_binop, we'll try to
1762 generate extensions, etc, which will require new pseudos, which
1763 will fail during some split phases. The SImode add patterns
1764 still exist, but are not named. So build the insns by hand. */
1769 subtarget = gen_reg_rtx (mode);
1770 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
1771 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
1777 target = gen_reg_rtx (mode);
1778 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1779 insn = gen_rtx_SET (VOIDmode, target, insn);
1785 /* If we couldn't do it that way, try some other methods. But if we have
1786 no instructions left, don't bother. Likewise, if this is SImode and
1787 we can't make pseudos, we can't do anything since the expand_binop
1788 and expand_unop calls will widen and try to make pseudos. */
1790 if (n == 1 || (mode == SImode && no_new_pseudos))
1793 /* Next, see if we can load a related constant and then shift and possibly
1794 negate it to get the constant we want. Try this once each increasing
1795 numbers of insns. */
1797 for (i = 1; i < n; i++)
1799 /* First, see if minus some low bits, we've an easy load of
1802 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
1804 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
1805 return expand_binop (mode, add_optab, temp, GEN_INT (new),
1806 target, 0, OPTAB_WIDEN);
1808 /* Next try complementing. */
1809 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
1810 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1812 /* Next try to form a constant and do a left shift. We can do this
1813 if some low-order bits are zero; the exact_log2 call below tells
1814 us that information. The bits we are shifting out could be any
1815 value, but here we'll just try the 0- and sign-extended forms of
1816 the constant. To try to increase the chance of having the same
1817 constant in more than one insn, start at the highest number of
1818 bits to shift, but try all possibilities in case a ZAPNOT will
1821 if ((bits = exact_log2 (c & - c)) > 0)
1822 for (; bits > 0; bits--)
1823 if ((temp = (alpha_emit_set_const
1824 (subtarget, mode, c >> bits, i))) != 0
1825 || ((temp = (alpha_emit_set_const
1827 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
1829 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1830 target, 0, OPTAB_WIDEN);
1832 /* Now try high-order zero bits. Here we try the shifted-in bits as
1833 all zero and all ones. Be careful to avoid shifting outside the
1834 mode and to avoid shifting outside the host wide int size. */
1835 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1836 confuse the recursive call and set all of the high 32 bits. */
1838 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1839 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
1840 for (; bits > 0; bits--)
1841 if ((temp = alpha_emit_set_const (subtarget, mode,
1843 || ((temp = (alpha_emit_set_const
1845 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1848 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1849 target, 1, OPTAB_WIDEN);
1851 /* Now try high-order 1 bits. We get that with a sign-extension.
1852 But one bit isn't enough here. Be careful to avoid shifting outside
1853 the mode and to avoid shifting outside the host wide int size. */
1855 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1856 - floor_log2 (~ c) - 2)) > 0)
1857 for (; bits > 0; bits--)
1858 if ((temp = alpha_emit_set_const (subtarget, mode,
1860 || ((temp = (alpha_emit_set_const
1862 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
1865 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1866 target, 0, OPTAB_WIDEN);
1869 #if HOST_BITS_PER_WIDE_INT == 64
1870 /* Finally, see if can load a value into the target that is the same as the
1871 constant except that all bytes that are 0 are changed to be 0xff. If we
1872 can, then we can do a ZAPNOT to obtain the desired constant. */
1875 for (i = 0; i < 64; i += 8)
1876 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
1877 new |= (HOST_WIDE_INT) 0xff << i;
1879 /* We are only called for SImode and DImode. If this is SImode, ensure that
1880 we are sign extended to a full word. */
1883 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
1885 if (new != c && new != -1
1886 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
1887 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
1888 target, 0, OPTAB_WIDEN);
1894 /* Try to output insns to set TARGET equal to the constant C if it can be
1895 done in less than N insns. Do all computations in MODE. Returns the place
1896 where the output has been placed if it can be done and the insns have been
1897 emitted. If it would take more than N insns, zero is returned and no
1898 insns and emitted. */
1901 alpha_emit_set_const (rtx target, enum machine_mode mode,
1902 HOST_WIDE_INT c, int n)
1905 rtx orig_target = target;
1908 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1909 can't load this constant in one insn, do this in DImode. */
1910 if (no_new_pseudos && mode == SImode
1911 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
1912 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
1914 target = gen_lowpart (DImode, target);
1918 /* Try 1 insn, then 2, then up to N. */
1919 for (i = 1; i <= n; i++)
1921 result = alpha_emit_set_const_1 (target, mode, c, i);
1924 rtx insn = get_last_insn ();
1925 rtx set = single_set (insn);
1926 if (! CONSTANT_P (SET_SRC (set)))
1927 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
1932 /* Allow for the case where we changed the mode of TARGET. */
1933 if (result == target)
1934 result = orig_target;
1939 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1940 fall back to a straight forward decomposition. We do this to avoid
1941 exponential run times encountered when looking for longer sequences
1942 with alpha_emit_set_const. */
1945 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
1947 HOST_WIDE_INT d1, d2, d3, d4;
1949 /* Decompose the entire word */
1950 #if HOST_BITS_PER_WIDE_INT >= 64
1951 if (c2 != -(c1 < 0))
1953 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1955 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1956 c1 = (c1 - d2) >> 32;
1957 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1959 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1963 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1965 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1969 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
1971 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1976 /* Construct the high word */
1979 emit_move_insn (target, GEN_INT (d4));
1981 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
1984 emit_move_insn (target, GEN_INT (d3));
1986 /* Shift it into place */
1987 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
1989 /* Add in the low bits. */
1991 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
1993 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
1998 /* Expand a move instruction; return true if all work is done.
1999 We don't handle non-bwx subword loads here. */
2002 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2004 /* If the output is not a register, the input must be. */
2005 if (GET_CODE (operands[0]) == MEM
2006 && ! reg_or_0_operand (operands[1], mode))
2007 operands[1] = force_reg (mode, operands[1]);
2009 /* Allow legitimize_address to perform some simplifications. */
2010 if (mode == Pmode && symbolic_operand (operands[1], mode))
2014 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2017 if (tmp == operands[0])
2024 /* Early out for non-constants and valid constants. */
2025 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2028 /* Split large integers. */
2029 if (GET_CODE (operands[1]) == CONST_INT
2030 || GET_CODE (operands[1]) == CONST_DOUBLE)
2032 HOST_WIDE_INT i0, i1;
2033 rtx temp = NULL_RTX;
2035 if (GET_CODE (operands[1]) == CONST_INT)
2037 i0 = INTVAL (operands[1]);
2040 else if (HOST_BITS_PER_WIDE_INT >= 64)
2042 i0 = CONST_DOUBLE_LOW (operands[1]);
2047 i0 = CONST_DOUBLE_LOW (operands[1]);
2048 i1 = CONST_DOUBLE_HIGH (operands[1]);
2051 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2052 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2054 if (!temp && TARGET_BUILD_CONSTANTS)
2055 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2059 if (rtx_equal_p (operands[0], temp))
2066 /* Otherwise we've nothing left but to drop the thing to memory. */
2067 operands[1] = force_const_mem (mode, operands[1]);
2068 if (reload_in_progress)
2070 emit_move_insn (operands[0], XEXP (operands[1], 0));
2071 operands[1] = copy_rtx (operands[1]);
2072 XEXP (operands[1], 0) = operands[0];
2075 operands[1] = validize_mem (operands[1]);
2079 /* Expand a non-bwx QImode or HImode move instruction;
2080 return true if all work is done. */
2083 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2085 /* If the output is not a register, the input must be. */
2086 if (GET_CODE (operands[0]) == MEM)
2087 operands[1] = force_reg (mode, operands[1]);
2089 /* Handle four memory cases, unaligned and aligned for either the input
2090 or the output. The only case where we can be called during reload is
2091 for aligned loads; all other cases require temporaries. */
2093 if (GET_CODE (operands[1]) == MEM
2094 || (GET_CODE (operands[1]) == SUBREG
2095 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2096 || (reload_in_progress && GET_CODE (operands[1]) == REG
2097 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2098 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2099 && GET_CODE (SUBREG_REG (operands[1])) == REG
2100 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2102 if (aligned_memory_operand (operands[1], mode))
2104 if (reload_in_progress)
2106 emit_insn ((mode == QImode
2107 ? gen_reload_inqi_help
2108 : gen_reload_inhi_help)
2109 (operands[0], operands[1],
2110 gen_rtx_REG (SImode, REGNO (operands[0]))));
2114 rtx aligned_mem, bitnum;
2115 rtx scratch = gen_reg_rtx (SImode);
2119 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2121 subtarget = operands[0];
2122 if (GET_CODE (subtarget) == REG)
2123 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2125 subtarget = gen_reg_rtx (DImode), copyout = true;
2127 emit_insn ((mode == QImode
2128 ? gen_aligned_loadqi
2129 : gen_aligned_loadhi)
2130 (subtarget, aligned_mem, bitnum, scratch));
2133 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2138 /* Don't pass these as parameters since that makes the generated
2139 code depend on parameter evaluation order which will cause
2140 bootstrap failures. */
2142 rtx temp1, temp2, seq, subtarget;
2145 temp1 = gen_reg_rtx (DImode);
2146 temp2 = gen_reg_rtx (DImode);
2148 subtarget = operands[0];
2149 if (GET_CODE (subtarget) == REG)
2150 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2152 subtarget = gen_reg_rtx (DImode), copyout = true;
2154 seq = ((mode == QImode
2155 ? gen_unaligned_loadqi
2156 : gen_unaligned_loadhi)
2157 (subtarget, get_unaligned_address (operands[1], 0),
2159 alpha_set_memflags (seq, operands[1]);
2163 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2168 if (GET_CODE (operands[0]) == MEM
2169 || (GET_CODE (operands[0]) == SUBREG
2170 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2171 || (reload_in_progress && GET_CODE (operands[0]) == REG
2172 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2173 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2174 && GET_CODE (SUBREG_REG (operands[0])) == REG
2175 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2177 if (aligned_memory_operand (operands[0], mode))
2179 rtx aligned_mem, bitnum;
2180 rtx temp1 = gen_reg_rtx (SImode);
2181 rtx temp2 = gen_reg_rtx (SImode);
2183 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2185 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2190 rtx temp1 = gen_reg_rtx (DImode);
2191 rtx temp2 = gen_reg_rtx (DImode);
2192 rtx temp3 = gen_reg_rtx (DImode);
2193 rtx seq = ((mode == QImode
2194 ? gen_unaligned_storeqi
2195 : gen_unaligned_storehi)
2196 (get_unaligned_address (operands[0], 0),
2197 operands[1], temp1, temp2, temp3));
2199 alpha_set_memflags (seq, operands[0]);
2208 /* Generate an unsigned DImode to FP conversion. This is the same code
2209 optabs would emit if we didn't have TFmode patterns.
2211 For SFmode, this is the only construction I've found that can pass
2212 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2213 intermediates will work, because you'll get intermediate rounding
2214 that ruins the end result. Some of this could be fixed by turning
2215 on round-to-positive-infinity, but that requires diddling the fpsr,
2216 which kills performance. I tried turning this around and converting
2217 to a negative number, so that I could turn on /m, but either I did
2218 it wrong or there's something else cause I wound up with the exact
2219 same single-bit error. There is a branch-less form of this same code:
2230 fcmoveq $f10,$f11,$f0
2232 I'm not using it because it's the same number of instructions as
2233 this branch-full form, and it has more serialized long latency
2234 instructions on the critical path.
2236 For DFmode, we can avoid rounding errors by breaking up the word
2237 into two pieces, converting them separately, and adding them back:
2239 LC0: .long 0,0x5f800000
2244 cpyse $f11,$f31,$f10
2245 cpyse $f31,$f11,$f11
2253 This doesn't seem to be a clear-cut win over the optabs form.
2254 It probably all depends on the distribution of numbers being
2255 converted -- in the optabs form, all but high-bit-set has a
2256 much lower minimum execution time. */
2259 alpha_emit_floatuns (rtx operands[2])
2261 rtx neglab, donelab, i0, i1, f0, in, out;
2262 enum machine_mode mode;
2265 in = force_reg (DImode, operands[1]);
2266 mode = GET_MODE (out);
2267 neglab = gen_label_rtx ();
2268 donelab = gen_label_rtx ();
2269 i0 = gen_reg_rtx (DImode);
2270 i1 = gen_reg_rtx (DImode);
2271 f0 = gen_reg_rtx (mode);
2273 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
2275 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
2276 emit_jump_insn (gen_jump (donelab));
2279 emit_label (neglab);
2281 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
2282 emit_insn (gen_anddi3 (i1, in, const1_rtx));
2283 emit_insn (gen_iordi3 (i0, i0, i1));
2284 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
2285 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
2287 emit_label (donelab);
2290 /* Generate the comparison for a conditional branch. */
2293 alpha_emit_conditional_branch (enum rtx_code code)
2295 enum rtx_code cmp_code, branch_code;
2296 enum machine_mode cmp_mode, branch_mode = VOIDmode;
2297 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
2300 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
2302 if (! TARGET_HAS_XFLOATING_LIBS)
2305 /* X_floating library comparison functions return
2309 Convert the compare against the raw return value. */
2331 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
2333 alpha_compare.fp_p = 0;
2336 /* The general case: fold the comparison code to the types of compares
2337 that we have, choosing the branch as necessary. */
2340 case EQ: case LE: case LT: case LEU: case LTU:
2342 /* We have these compares: */
2343 cmp_code = code, branch_code = NE;
2348 /* These must be reversed. */
2349 cmp_code = reverse_condition (code), branch_code = EQ;
2352 case GE: case GT: case GEU: case GTU:
2353 /* For FP, we swap them, for INT, we reverse them. */
2354 if (alpha_compare.fp_p)
2356 cmp_code = swap_condition (code);
2358 tem = op0, op0 = op1, op1 = tem;
2362 cmp_code = reverse_condition (code);
2371 if (alpha_compare.fp_p)
2374 if (flag_unsafe_math_optimizations)
2376 /* When we are not as concerned about non-finite values, and we
2377 are comparing against zero, we can branch directly. */
2378 if (op1 == CONST0_RTX (DFmode))
2379 cmp_code = UNKNOWN, branch_code = code;
2380 else if (op0 == CONST0_RTX (DFmode))
2382 /* Undo the swap we probably did just above. */
2383 tem = op0, op0 = op1, op1 = tem;
2384 branch_code = swap_condition (cmp_code);
2390 /* ??? We mark the branch mode to be CCmode to prevent the
2391 compare and branch from being combined, since the compare
2392 insn follows IEEE rules that the branch does not. */
2393 branch_mode = CCmode;
2400 /* The following optimizations are only for signed compares. */
2401 if (code != LEU && code != LTU && code != GEU && code != GTU)
2403 /* Whee. Compare and branch against 0 directly. */
2404 if (op1 == const0_rtx)
2405 cmp_code = UNKNOWN, branch_code = code;
2407 /* If the constants doesn't fit into an immediate, but can
2408 be generated by lda/ldah, we adjust the argument and
2409 compare against zero, so we can use beq/bne directly. */
2410 /* ??? Don't do this when comparing against symbols, otherwise
2411 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2412 be declared false out of hand (at least for non-weak). */
2413 else if (GET_CODE (op1) == CONST_INT
2414 && (code == EQ || code == NE)
2415 && !(symbolic_operand (op0, VOIDmode)
2416 || (GET_CODE (op0) == REG && REG_POINTER (op0))))
2418 HOST_WIDE_INT v = INTVAL (op1), n = -v;
2420 if (! CONST_OK_FOR_LETTER_P (v, 'I')
2421 && (CONST_OK_FOR_LETTER_P (n, 'K')
2422 || CONST_OK_FOR_LETTER_P (n, 'L')))
2424 cmp_code = PLUS, branch_code = code;
2430 if (!reg_or_0_operand (op0, DImode))
2431 op0 = force_reg (DImode, op0);
2432 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
2433 op1 = force_reg (DImode, op1);
2436 /* Emit an initial compare instruction, if necessary. */
2438 if (cmp_code != UNKNOWN)
2440 tem = gen_reg_rtx (cmp_mode);
2441 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
2444 /* Zero the operands. */
2445 memset (&alpha_compare, 0, sizeof (alpha_compare));
2447 /* Return the branch comparison. */
2448 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
2451 /* Certain simplifications can be done to make invalid setcc operations
2452 valid. Return the final comparison, or NULL if we can't work. */
2455 alpha_emit_setcc (enum rtx_code code)
2457 enum rtx_code cmp_code;
2458 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
2459 int fp_p = alpha_compare.fp_p;
2462 /* Zero the operands. */
2463 memset (&alpha_compare, 0, sizeof (alpha_compare));
2465 if (fp_p && GET_MODE (op0) == TFmode)
2467 if (! TARGET_HAS_XFLOATING_LIBS)
2470 /* X_floating library comparison functions return
2474 Convert the compare against the raw return value. */
2476 if (code == UNORDERED || code == ORDERED)
2481 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
2485 if (code == UNORDERED)
2487 else if (code == ORDERED)
2493 if (fp_p && !TARGET_FIX)
2496 /* The general case: fold the comparison code to the types of compares
2497 that we have, choosing the branch as necessary. */
2502 case EQ: case LE: case LT: case LEU: case LTU:
2504 /* We have these compares. */
2506 cmp_code = code, code = NE;
2510 if (!fp_p && op1 == const0_rtx)
2515 cmp_code = reverse_condition (code);
2519 case GE: case GT: case GEU: case GTU:
2520 /* These normally need swapping, but for integer zero we have
2521 special patterns that recognize swapped operands. */
2522 if (!fp_p && op1 == const0_rtx)
2524 code = swap_condition (code);
2526 cmp_code = code, code = NE;
2527 tmp = op0, op0 = op1, op1 = tmp;
2536 if (!register_operand (op0, DImode))
2537 op0 = force_reg (DImode, op0);
2538 if (!reg_or_8bit_operand (op1, DImode))
2539 op1 = force_reg (DImode, op1);
2542 /* Emit an initial compare instruction, if necessary. */
2543 if (cmp_code != UNKNOWN)
2545 enum machine_mode mode = fp_p ? DFmode : DImode;
2547 tmp = gen_reg_rtx (mode);
2548 emit_insn (gen_rtx_SET (VOIDmode, tmp,
2549 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
2551 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
2555 /* Return the setcc comparison. */
2556 return gen_rtx_fmt_ee (code, DImode, op0, op1);
2560 /* Rewrite a comparison against zero CMP of the form
2561 (CODE (cc0) (const_int 0)) so it can be written validly in
2562 a conditional move (if_then_else CMP ...).
2563 If both of the operands that set cc0 are nonzero we must emit
2564 an insn to perform the compare (it can't be done within
2565 the conditional move). */
2568 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
2570 enum rtx_code code = GET_CODE (cmp);
2571 enum rtx_code cmov_code = NE;
2572 rtx op0 = alpha_compare.op0;
2573 rtx op1 = alpha_compare.op1;
2574 int fp_p = alpha_compare.fp_p;
2575 enum machine_mode cmp_mode
2576 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
2577 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
2578 enum machine_mode cmov_mode = VOIDmode;
2579 int local_fast_math = flag_unsafe_math_optimizations;
2582 /* Zero the operands. */
2583 memset (&alpha_compare, 0, sizeof (alpha_compare));
2585 if (fp_p != FLOAT_MODE_P (mode))
2587 enum rtx_code cmp_code;
2592 /* If we have fp<->int register move instructions, do a cmov by
2593 performing the comparison in fp registers, and move the
2594 zero/nonzero value to integer registers, where we can then
2595 use a normal cmov, or vice-versa. */
2599 case EQ: case LE: case LT: case LEU: case LTU:
2600 /* We have these compares. */
2601 cmp_code = code, code = NE;
2605 /* This must be reversed. */
2606 cmp_code = EQ, code = EQ;
2609 case GE: case GT: case GEU: case GTU:
2610 /* These normally need swapping, but for integer zero we have
2611 special patterns that recognize swapped operands. */
2612 if (!fp_p && op1 == const0_rtx)
2613 cmp_code = code, code = NE;
2616 cmp_code = swap_condition (code);
2618 tem = op0, op0 = op1, op1 = tem;
2626 tem = gen_reg_rtx (cmp_op_mode);
2627 emit_insn (gen_rtx_SET (VOIDmode, tem,
2628 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
2631 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
2632 op0 = gen_lowpart (cmp_op_mode, tem);
2633 op1 = CONST0_RTX (cmp_op_mode);
2635 local_fast_math = 1;
2638 /* We may be able to use a conditional move directly.
2639 This avoids emitting spurious compares. */
2640 if (signed_comparison_operator (cmp, VOIDmode)
2641 && (!fp_p || local_fast_math)
2642 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
2643 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
2645 /* We can't put the comparison inside the conditional move;
2646 emit a compare instruction and put that inside the
2647 conditional move. Make sure we emit only comparisons we have;
2648 swap or reverse as necessary. */
2655 case EQ: case LE: case LT: case LEU: case LTU:
2656 /* We have these compares: */
2660 /* This must be reversed. */
2661 code = reverse_condition (code);
2665 case GE: case GT: case GEU: case GTU:
2666 /* These must be swapped. */
2667 if (op1 != CONST0_RTX (cmp_mode))
2669 code = swap_condition (code);
2670 tem = op0, op0 = op1, op1 = tem;
2680 if (!reg_or_0_operand (op0, DImode))
2681 op0 = force_reg (DImode, op0);
2682 if (!reg_or_8bit_operand (op1, DImode))
2683 op1 = force_reg (DImode, op1);
2686 /* ??? We mark the branch mode to be CCmode to prevent the compare
2687 and cmov from being combined, since the compare insn follows IEEE
2688 rules that the cmov does not. */
2689 if (fp_p && !local_fast_math)
2692 tem = gen_reg_rtx (cmp_op_mode);
2693 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
2694 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
2697 /* Simplify a conditional move of two constants into a setcc with
2698 arithmetic. This is done with a splitter since combine would
2699 just undo the work if done during code generation. It also catches
2700 cases we wouldn't have before cse. */
2703 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
2704 rtx t_rtx, rtx f_rtx)
2706 HOST_WIDE_INT t, f, diff;
2707 enum machine_mode mode;
2708 rtx target, subtarget, tmp;
2710 mode = GET_MODE (dest);
2715 if (((code == NE || code == EQ) && diff < 0)
2716 || (code == GE || code == GT))
2718 code = reverse_condition (code);
2719 diff = t, t = f, f = diff;
2723 subtarget = target = dest;
2726 target = gen_lowpart (DImode, dest);
2727 if (! no_new_pseudos)
2728 subtarget = gen_reg_rtx (DImode);
2732 /* Below, we must be careful to use copy_rtx on target and subtarget
2733 in intermediate insns, as they may be a subreg rtx, which may not
2736 if (f == 0 && exact_log2 (diff) > 0
2737 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2738 viable over a longer latency cmove. On EV5, the E0 slot is a
2739 scarce resource, and on EV4 shift has the same latency as a cmove. */
2740 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
2742 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2743 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2745 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
2746 GEN_INT (exact_log2 (t)));
2747 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2749 else if (f == 0 && t == -1)
2751 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2752 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2754 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
2756 else if (diff == 1 || diff == 4 || diff == 8)
2760 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2761 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2764 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
2767 add_op = GEN_INT (f);
2768 if (sext_add_operand (add_op, mode))
2770 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
2772 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
2773 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2785 /* Look up the function X_floating library function name for the
2788 struct xfloating_op GTY(())
2790 const enum rtx_code code;
2791 const char *const GTY((skip)) osf_func;
2792 const char *const GTY((skip)) vms_func;
2796 static GTY(()) struct xfloating_op xfloating_ops[] =
2798 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
2799 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
2800 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
2801 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
2802 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
2803 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
2804 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
2805 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
2806 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
2807 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
2808 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2809 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
2810 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2811 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2812 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2815 static GTY(()) struct xfloating_op vax_cvt_ops[] =
2817 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2818 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2822 alpha_lookup_xfloating_lib_func (enum rtx_code code)
2824 struct xfloating_op *ops = xfloating_ops;
2825 long n = ARRAY_SIZE (xfloating_ops);
2828 /* How irritating. Nothing to key off for the main table. */
2829 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
2832 n = ARRAY_SIZE (vax_cvt_ops);
2835 for (i = 0; i < n; ++i, ++ops)
2836 if (ops->code == code)
2838 rtx func = ops->libcall;
2841 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
2842 ? ops->vms_func : ops->osf_func);
2843 ops->libcall = func;
2851 /* Most X_floating operations take the rounding mode as an argument.
2852 Compute that here. */
2855 alpha_compute_xfloating_mode_arg (enum rtx_code code,
2856 enum alpha_fp_rounding_mode round)
2862 case ALPHA_FPRM_NORM:
2865 case ALPHA_FPRM_MINF:
2868 case ALPHA_FPRM_CHOP:
2871 case ALPHA_FPRM_DYN:
2877 /* XXX For reference, round to +inf is mode = 3. */
2880 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
2886 /* Emit an X_floating library function call.
2888 Note that these functions do not follow normal calling conventions:
2889 TFmode arguments are passed in two integer registers (as opposed to
2890 indirect); TFmode return values appear in R16+R17.
2892 FUNC is the function to call.
2893 TARGET is where the output belongs.
2894 OPERANDS are the inputs.
2895 NOPERANDS is the count of inputs.
2896 EQUIV is the expression equivalent for the function.
2900 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
2901 int noperands, rtx equiv)
2903 rtx usage = NULL_RTX, tmp, reg;
2908 for (i = 0; i < noperands; ++i)
2910 switch (GET_MODE (operands[i]))
2913 reg = gen_rtx_REG (TFmode, regno);
2918 reg = gen_rtx_REG (DFmode, regno + 32);
2923 if (GET_CODE (operands[i]) != CONST_INT)
2927 reg = gen_rtx_REG (DImode, regno);
2935 emit_move_insn (reg, operands[i]);
2936 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
2939 switch (GET_MODE (target))
2942 reg = gen_rtx_REG (TFmode, 16);
2945 reg = gen_rtx_REG (DFmode, 32);
2948 reg = gen_rtx_REG (DImode, 0);
2954 tmp = gen_rtx_MEM (QImode, func);
2955 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
2956 const0_rtx, const0_rtx));
2957 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
2958 CONST_OR_PURE_CALL_P (tmp) = 1;
2963 emit_libcall_block (tmp, target, reg, equiv);
2966 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
2969 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
2973 rtx out_operands[3];
2975 func = alpha_lookup_xfloating_lib_func (code);
2976 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
2978 out_operands[0] = operands[1];
2979 out_operands[1] = operands[2];
2980 out_operands[2] = GEN_INT (mode);
2981 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
2982 gen_rtx_fmt_ee (code, TFmode, operands[1],
2986 /* Emit an X_floating library function call for a comparison. */
2989 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
2992 rtx out, operands[2];
2994 func = alpha_lookup_xfloating_lib_func (code);
2998 out = gen_reg_rtx (DImode);
3000 /* ??? Strange mode for equiv because what's actually returned
3001 is -1,0,1, not a proper boolean value. */
3002 alpha_emit_xfloating_libcall (func, out, operands, 2,
3003 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3008 /* Emit an X_floating library function call for a conversion. */
3011 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3013 int noperands = 1, mode;
3014 rtx out_operands[2];
3016 enum rtx_code code = orig_code;
3018 if (code == UNSIGNED_FIX)
3021 func = alpha_lookup_xfloating_lib_func (code);
3023 out_operands[0] = operands[1];
3028 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3029 out_operands[1] = GEN_INT (mode);
3032 case FLOAT_TRUNCATE:
3033 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3034 out_operands[1] = GEN_INT (mode);
3041 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3042 gen_rtx_fmt_e (orig_code,
3043 GET_MODE (operands[0]),
3047 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3048 OP[0] into OP[0,1]. Naturally, output operand ordering is
3052 alpha_split_tfmode_pair (rtx operands[4])
3054 if (GET_CODE (operands[1]) == REG)
3056 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3057 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3059 else if (GET_CODE (operands[1]) == MEM)
3061 operands[3] = adjust_address (operands[1], DImode, 8);
3062 operands[2] = adjust_address (operands[1], DImode, 0);
3064 else if (operands[1] == CONST0_RTX (TFmode))
3065 operands[2] = operands[3] = const0_rtx;
3069 if (GET_CODE (operands[0]) == REG)
3071 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3072 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3074 else if (GET_CODE (operands[0]) == MEM)
3076 operands[1] = adjust_address (operands[0], DImode, 8);
3077 operands[0] = adjust_address (operands[0], DImode, 0);
3083 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3084 op2 is a register containing the sign bit, operation is the
3085 logical operation to be performed. */
3088 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3090 rtx high_bit = operands[2];
3094 alpha_split_tfmode_pair (operands);
3096 /* Detect three flavors of operand overlap. */
3098 if (rtx_equal_p (operands[0], operands[2]))
3100 else if (rtx_equal_p (operands[1], operands[2]))
3102 if (rtx_equal_p (operands[0], high_bit))
3109 emit_move_insn (operands[0], operands[2]);
3111 /* ??? If the destination overlaps both source tf and high_bit, then
3112 assume source tf is dead in its entirety and use the other half
3113 for a scratch register. Otherwise "scratch" is just the proper
3114 destination register. */
3115 scratch = operands[move < 2 ? 1 : 3];
3117 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3121 emit_move_insn (operands[0], operands[2]);
3123 emit_move_insn (operands[1], scratch);
3127 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3131 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3132 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3133 lda r3,X(r11) lda r3,X+2(r11)
3134 extwl r1,r3,r1 extql r1,r3,r1
3135 extwh r2,r3,r2 extqh r2,r3,r2
3136 or r1.r2.r1 or r1,r2,r1
3139 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3140 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3141 lda r3,X(r11) lda r3,X(r11)
3142 extll r1,r3,r1 extll r1,r3,r1
3143 extlh r2,r3,r2 extlh r2,r3,r2
3144 or r1.r2.r1 addl r1,r2,r1
3146 quad: ldq_u r1,X(r11)
3155 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3156 HOST_WIDE_INT ofs, int sign)
3158 rtx meml, memh, addr, extl, exth, tmp, mema;
3159 enum machine_mode mode;
3161 meml = gen_reg_rtx (DImode);
3162 memh = gen_reg_rtx (DImode);
3163 addr = gen_reg_rtx (DImode);
3164 extl = gen_reg_rtx (DImode);
3165 exth = gen_reg_rtx (DImode);
3167 mema = XEXP (mem, 0);
3168 if (GET_CODE (mema) == LO_SUM)
3169 mema = force_reg (Pmode, mema);
3171 /* AND addresses cannot be in any alias set, since they may implicitly
3172 alias surrounding code. Ideally we'd have some alias set that
3173 covered all types except those with alignment 8 or higher. */
3175 tmp = change_address (mem, DImode,
3176 gen_rtx_AND (DImode,
3177 plus_constant (mema, ofs),
3179 set_mem_alias_set (tmp, 0);
3180 emit_move_insn (meml, tmp);
3182 tmp = change_address (mem, DImode,
3183 gen_rtx_AND (DImode,
3184 plus_constant (mema, ofs + size - 1),
3186 set_mem_alias_set (tmp, 0);
3187 emit_move_insn (memh, tmp);
3189 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3191 emit_move_insn (addr, plus_constant (mema, -1));
3193 emit_insn (gen_extqh_be (extl, meml, addr));
3194 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3196 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3197 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3198 addr, 1, OPTAB_WIDEN);
3200 else if (sign && size == 2)
3202 emit_move_insn (addr, plus_constant (mema, ofs+2));
3204 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3205 emit_insn (gen_extqh_le (exth, memh, addr));
3207 /* We must use tgt here for the target. Alpha-vms port fails if we use
3208 addr for the target, because addr is marked as a pointer and combine
3209 knows that pointers are always sign-extended 32 bit values. */
3210 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3211 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3212 addr, 1, OPTAB_WIDEN);
3216 if (WORDS_BIG_ENDIAN)
3218 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
3222 emit_insn (gen_extwh_be (extl, meml, addr));
3227 emit_insn (gen_extlh_be (extl, meml, addr));
3232 emit_insn (gen_extqh_be (extl, meml, addr));
3239 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
3243 emit_move_insn (addr, plus_constant (mema, ofs));
3244 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
3248 emit_insn (gen_extwh_le (exth, memh, addr));
3253 emit_insn (gen_extlh_le (exth, memh, addr));
3258 emit_insn (gen_extqh_le (exth, memh, addr));
3267 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
3268 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
3273 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
3276 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3279 alpha_expand_unaligned_store (rtx dst, rtx src,
3280 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
3282 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
3284 dstl = gen_reg_rtx (DImode);
3285 dsth = gen_reg_rtx (DImode);
3286 insl = gen_reg_rtx (DImode);
3287 insh = gen_reg_rtx (DImode);
3289 dsta = XEXP (dst, 0);
3290 if (GET_CODE (dsta) == LO_SUM)
3291 dsta = force_reg (Pmode, dsta);
3293 /* AND addresses cannot be in any alias set, since they may implicitly
3294 alias surrounding code. Ideally we'd have some alias set that
3295 covered all types except those with alignment 8 or higher. */
3297 meml = change_address (dst, DImode,
3298 gen_rtx_AND (DImode,
3299 plus_constant (dsta, ofs),
3301 set_mem_alias_set (meml, 0);
3303 memh = change_address (dst, DImode,
3304 gen_rtx_AND (DImode,
3305 plus_constant (dsta, ofs + size - 1),
3307 set_mem_alias_set (memh, 0);
3309 emit_move_insn (dsth, memh);
3310 emit_move_insn (dstl, meml);
3311 if (WORDS_BIG_ENDIAN)
3313 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
3315 if (src != const0_rtx)
3320 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
3323 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
3326 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
3329 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
3330 GEN_INT (size*8), addr));
3336 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
3340 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3341 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
3345 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
3349 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
3353 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
3355 if (src != const0_rtx)
3357 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
3358 GEN_INT (size*8), addr));
3363 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
3366 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
3369 emit_insn (gen_insql_le (insl, src, addr));
3374 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
3379 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
3383 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3384 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
3388 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
3393 if (src != const0_rtx)
3395 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
3396 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
3399 if (WORDS_BIG_ENDIAN)
3401 emit_move_insn (meml, dstl);
3402 emit_move_insn (memh, dsth);
3406 /* Must store high before low for degenerate case of aligned. */
3407 emit_move_insn (memh, dsth);
3408 emit_move_insn (meml, dstl);
3412 /* The block move code tries to maximize speed by separating loads and
3413 stores at the expense of register pressure: we load all of the data
3414 before we store it back out. There are two secondary effects worth
3415 mentioning, that this speeds copying to/from aligned and unaligned
3416 buffers, and that it makes the code significantly easier to write. */
3418 #define MAX_MOVE_WORDS 8
3420 /* Load an integral number of consecutive unaligned quadwords. */
3423 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
3424 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3426 rtx const im8 = GEN_INT (-8);
3427 rtx const i64 = GEN_INT (64);
3428 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
3429 rtx sreg, areg, tmp, smema;
3432 smema = XEXP (smem, 0);
3433 if (GET_CODE (smema) == LO_SUM)
3434 smema = force_reg (Pmode, smema);
3436 /* Generate all the tmp registers we need. */
3437 for (i = 0; i < words; ++i)
3439 data_regs[i] = out_regs[i];
3440 ext_tmps[i] = gen_reg_rtx (DImode);
3442 data_regs[words] = gen_reg_rtx (DImode);
3445 smem = adjust_address (smem, GET_MODE (smem), ofs);
3447 /* Load up all of the source data. */
3448 for (i = 0; i < words; ++i)
3450 tmp = change_address (smem, DImode,
3451 gen_rtx_AND (DImode,
3452 plus_constant (smema, 8*i),
3454 set_mem_alias_set (tmp, 0);
3455 emit_move_insn (data_regs[i], tmp);
3458 tmp = change_address (smem, DImode,
3459 gen_rtx_AND (DImode,
3460 plus_constant (smema, 8*words - 1),
3462 set_mem_alias_set (tmp, 0);
3463 emit_move_insn (data_regs[words], tmp);
3465 /* Extract the half-word fragments. Unfortunately DEC decided to make
3466 extxh with offset zero a noop instead of zeroing the register, so
3467 we must take care of that edge condition ourselves with cmov. */
3469 sreg = copy_addr_to_reg (smema);
3470 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
3472 if (WORDS_BIG_ENDIAN)
3473 emit_move_insn (sreg, plus_constant (sreg, 7));
3474 for (i = 0; i < words; ++i)
3476 if (WORDS_BIG_ENDIAN)
3478 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
3479 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
3483 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
3484 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
3486 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
3487 gen_rtx_IF_THEN_ELSE (DImode,
3488 gen_rtx_EQ (DImode, areg,
3490 const0_rtx, ext_tmps[i])));
3493 /* Merge the half-words into whole words. */
3494 for (i = 0; i < words; ++i)
3496 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
3497 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
3501 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3502 may be NULL to store zeros. */
3505 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
3506 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3508 rtx const im8 = GEN_INT (-8);
3509 rtx const i64 = GEN_INT (64);
3510 rtx ins_tmps[MAX_MOVE_WORDS];
3511 rtx st_tmp_1, st_tmp_2, dreg;
3512 rtx st_addr_1, st_addr_2, dmema;
3515 dmema = XEXP (dmem, 0);
3516 if (GET_CODE (dmema) == LO_SUM)
3517 dmema = force_reg (Pmode, dmema);
3519 /* Generate all the tmp registers we need. */
3520 if (data_regs != NULL)
3521 for (i = 0; i < words; ++i)
3522 ins_tmps[i] = gen_reg_rtx(DImode);
3523 st_tmp_1 = gen_reg_rtx(DImode);
3524 st_tmp_2 = gen_reg_rtx(DImode);
3527 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
3529 st_addr_2 = change_address (dmem, DImode,
3530 gen_rtx_AND (DImode,
3531 plus_constant (dmema, words*8 - 1),
3533 set_mem_alias_set (st_addr_2, 0);
3535 st_addr_1 = change_address (dmem, DImode,
3536 gen_rtx_AND (DImode, dmema, im8));
3537 set_mem_alias_set (st_addr_1, 0);
3539 /* Load up the destination end bits. */
3540 emit_move_insn (st_tmp_2, st_addr_2);
3541 emit_move_insn (st_tmp_1, st_addr_1);
3543 /* Shift the input data into place. */
3544 dreg = copy_addr_to_reg (dmema);
3545 if (WORDS_BIG_ENDIAN)
3546 emit_move_insn (dreg, plus_constant (dreg, 7));
3547 if (data_regs != NULL)
3549 for (i = words-1; i >= 0; --i)
3551 if (WORDS_BIG_ENDIAN)
3553 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
3554 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
3558 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
3559 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
3562 for (i = words-1; i > 0; --i)
3564 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
3565 ins_tmps[i-1], ins_tmps[i-1], 1,
3570 /* Split and merge the ends with the destination data. */
3571 if (WORDS_BIG_ENDIAN)
3573 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
3574 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
3578 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
3579 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
3582 if (data_regs != NULL)
3584 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
3585 st_tmp_2, 1, OPTAB_WIDEN);
3586 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
3587 st_tmp_1, 1, OPTAB_WIDEN);
3591 if (WORDS_BIG_ENDIAN)
3592 emit_move_insn (st_addr_1, st_tmp_1);
3594 emit_move_insn (st_addr_2, st_tmp_2);
3595 for (i = words-1; i > 0; --i)
3597 rtx tmp = change_address (dmem, DImode,
3598 gen_rtx_AND (DImode,
3599 plus_constant(dmema,
3600 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
3602 set_mem_alias_set (tmp, 0);
3603 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
3605 if (WORDS_BIG_ENDIAN)
3606 emit_move_insn (st_addr_2, st_tmp_2);
3608 emit_move_insn (st_addr_1, st_tmp_1);
3612 /* Expand string/block move operations.
3614 operands[0] is the pointer to the destination.
3615 operands[1] is the pointer to the source.
3616 operands[2] is the number of bytes to move.
3617 operands[3] is the alignment. */
3620 alpha_expand_block_move (rtx operands[])
3622 rtx bytes_rtx = operands[2];
3623 rtx align_rtx = operands[3];
3624 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3625 HOST_WIDE_INT bytes = orig_bytes;
3626 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
3627 HOST_WIDE_INT dst_align = src_align;
3628 rtx orig_src = operands[1];
3629 rtx orig_dst = operands[0];
3630 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
3632 unsigned int i, words, ofs, nregs = 0;
3634 if (orig_bytes <= 0)
3636 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3639 /* Look for additional alignment information from recorded register info. */
3641 tmp = XEXP (orig_src, 0);
3642 if (GET_CODE (tmp) == REG)
3643 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3644 else if (GET_CODE (tmp) == PLUS
3645 && GET_CODE (XEXP (tmp, 0)) == REG
3646 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3648 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3649 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3653 if (a >= 64 && c % 8 == 0)
3655 else if (a >= 32 && c % 4 == 0)
3657 else if (a >= 16 && c % 2 == 0)
3662 tmp = XEXP (orig_dst, 0);
3663 if (GET_CODE (tmp) == REG)
3664 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3665 else if (GET_CODE (tmp) == PLUS
3666 && GET_CODE (XEXP (tmp, 0)) == REG
3667 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3669 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3670 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3674 if (a >= 64 && c % 8 == 0)
3676 else if (a >= 32 && c % 4 == 0)
3678 else if (a >= 16 && c % 2 == 0)
3684 if (src_align >= 64 && bytes >= 8)
3688 for (i = 0; i < words; ++i)
3689 data_regs[nregs + i] = gen_reg_rtx (DImode);
3691 for (i = 0; i < words; ++i)
3692 emit_move_insn (data_regs[nregs + i],
3693 adjust_address (orig_src, DImode, ofs + i * 8));
3700 if (src_align >= 32 && bytes >= 4)
3704 for (i = 0; i < words; ++i)
3705 data_regs[nregs + i] = gen_reg_rtx (SImode);
3707 for (i = 0; i < words; ++i)
3708 emit_move_insn (data_regs[nregs + i],
3709 adjust_address (orig_src, SImode, ofs + i * 4));
3720 for (i = 0; i < words+1; ++i)
3721 data_regs[nregs + i] = gen_reg_rtx (DImode);
3723 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
3731 if (! TARGET_BWX && bytes >= 4)
3733 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
3734 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
3741 if (src_align >= 16)
3744 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3745 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
3748 } while (bytes >= 2);
3750 else if (! TARGET_BWX)
3752 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3753 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
3761 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
3762 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
3767 if (nregs > ARRAY_SIZE (data_regs))
3770 /* Now save it back out again. */
3774 /* Write out the data in whatever chunks reading the source allowed. */
3775 if (dst_align >= 64)
3777 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3779 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
3786 if (dst_align >= 32)
3788 /* If the source has remaining DImode regs, write them out in
3790 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3792 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
3793 NULL_RTX, 1, OPTAB_WIDEN);
3795 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
3796 gen_lowpart (SImode, data_regs[i]));
3797 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
3798 gen_lowpart (SImode, tmp));
3803 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
3805 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
3812 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
3814 /* Write out a remaining block of words using unaligned methods. */
3816 for (words = 1; i + words < nregs; words++)
3817 if (GET_MODE (data_regs[i + words]) != DImode)
3821 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
3823 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
3830 /* Due to the above, this won't be aligned. */
3831 /* ??? If we have more than one of these, consider constructing full
3832 words in registers and using alpha_expand_unaligned_store_words. */
3833 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
3835 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
3840 if (dst_align >= 16)
3841 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
3843 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
3848 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
3850 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
3855 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
3857 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
3869 alpha_expand_block_clear (rtx operands[])
3871 rtx bytes_rtx = operands[1];
3872 rtx align_rtx = operands[2];
3873 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3874 HOST_WIDE_INT bytes = orig_bytes;
3875 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
3876 HOST_WIDE_INT alignofs = 0;
3877 rtx orig_dst = operands[0];
3879 int i, words, ofs = 0;
3881 if (orig_bytes <= 0)
3883 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3886 /* Look for stricter alignment. */
3887 tmp = XEXP (orig_dst, 0);
3888 if (GET_CODE (tmp) == REG)
3889 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3890 else if (GET_CODE (tmp) == PLUS
3891 && GET_CODE (XEXP (tmp, 0)) == REG
3892 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
3894 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3895 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3900 align = a, alignofs = 8 - c % 8;
3902 align = a, alignofs = 4 - c % 4;
3904 align = a, alignofs = 2 - c % 2;
3908 /* Handle an unaligned prefix first. */
3912 #if HOST_BITS_PER_WIDE_INT >= 64
3913 /* Given that alignofs is bounded by align, the only time BWX could
3914 generate three stores is for a 7 byte fill. Prefer two individual
3915 stores over a load/mask/store sequence. */
3916 if ((!TARGET_BWX || alignofs == 7)
3918 && !(alignofs == 4 && bytes >= 4))
3920 enum machine_mode mode = (align >= 64 ? DImode : SImode);
3921 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
3925 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
3926 set_mem_alias_set (mem, 0);
3928 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
3929 if (bytes < alignofs)
3931 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
3942 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
3943 NULL_RTX, 1, OPTAB_WIDEN);
3945 emit_move_insn (mem, tmp);
3949 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
3951 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
3956 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
3958 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
3963 if (alignofs == 4 && bytes >= 4)
3965 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
3971 /* If we've not used the extra lead alignment information by now,
3972 we won't be able to. Downgrade align to match what's left over. */
3975 alignofs = alignofs & -alignofs;
3976 align = MIN (align, alignofs * BITS_PER_UNIT);
3980 /* Handle a block of contiguous long-words. */
3982 if (align >= 64 && bytes >= 8)
3986 for (i = 0; i < words; ++i)
3987 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
3994 /* If the block is large and appropriately aligned, emit a single
3995 store followed by a sequence of stq_u insns. */
3997 if (align >= 32 && bytes > 16)
4001 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4005 orig_dsta = XEXP (orig_dst, 0);
4006 if (GET_CODE (orig_dsta) == LO_SUM)
4007 orig_dsta = force_reg (Pmode, orig_dsta);
4010 for (i = 0; i < words; ++i)
4013 = change_address (orig_dst, DImode,
4014 gen_rtx_AND (DImode,
4015 plus_constant (orig_dsta, ofs + i*8),
4017 set_mem_alias_set (mem, 0);
4018 emit_move_insn (mem, const0_rtx);
4021 /* Depending on the alignment, the first stq_u may have overlapped
4022 with the initial stl, which means that the last stq_u didn't
4023 write as much as it would appear. Leave those questionable bytes
4025 bytes -= words * 8 - 4;
4026 ofs += words * 8 - 4;
4029 /* Handle a smaller block of aligned words. */
4031 if ((align >= 64 && bytes == 4)
4032 || (align == 32 && bytes >= 4))
4036 for (i = 0; i < words; ++i)
4037 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4044 /* An unaligned block uses stq_u stores for as many as possible. */
4050 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4056 /* Next clean up any trailing pieces. */
4058 #if HOST_BITS_PER_WIDE_INT >= 64
4059 /* Count the number of bits in BYTES for which aligned stores could
4062 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4066 /* If we have appropriate alignment (and it wouldn't take too many
4067 instructions otherwise), mask out the bytes we need. */
4068 if (TARGET_BWX ? words > 2 : bytes > 0)
4075 mem = adjust_address (orig_dst, DImode, ofs);
4076 set_mem_alias_set (mem, 0);
4078 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4080 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4081 NULL_RTX, 1, OPTAB_WIDEN);
4083 emit_move_insn (mem, tmp);
4086 else if (align >= 32 && bytes < 4)
4091 mem = adjust_address (orig_dst, SImode, ofs);
4092 set_mem_alias_set (mem, 0);
4094 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4096 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4097 NULL_RTX, 1, OPTAB_WIDEN);
4099 emit_move_insn (mem, tmp);
4105 if (!TARGET_BWX && bytes >= 4)
4107 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4117 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
4121 } while (bytes >= 2);
4123 else if (! TARGET_BWX)
4125 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
4133 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4141 /* Returns a mask so that zap(x, value) == x & mask. */
4144 alpha_expand_zap_mask (HOST_WIDE_INT value)
4149 if (HOST_BITS_PER_WIDE_INT >= 64)
4151 HOST_WIDE_INT mask = 0;
4153 for (i = 7; i >= 0; --i)
4156 if (!((value >> i) & 1))
4160 result = gen_int_mode (mask, DImode);
4162 else if (HOST_BITS_PER_WIDE_INT == 32)
4164 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
4166 for (i = 7; i >= 4; --i)
4169 if (!((value >> i) & 1))
4173 for (i = 3; i >= 0; --i)
4176 if (!((value >> i) & 1))
4180 result = immed_double_const (mask_lo, mask_hi, DImode);
4189 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
4190 enum machine_mode mode,
4191 rtx op0, rtx op1, rtx op2)
4193 op0 = gen_lowpart (mode, op0);
4195 if (op1 == const0_rtx)
4196 op1 = CONST0_RTX (mode);
4198 op1 = gen_lowpart (mode, op1);
4200 if (op2 == const0_rtx)
4201 op2 = CONST0_RTX (mode);
4203 op2 = gen_lowpart (mode, op2);
4205 emit_insn ((*gen) (op0, op1, op2));
4208 /* Adjust the cost of a scheduling dependency. Return the new cost of
4209 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4212 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4214 enum attr_type insn_type, dep_insn_type;
4216 /* If the dependence is an anti-dependence, there is no cost. For an
4217 output dependence, there is sometimes a cost, but it doesn't seem
4218 worth handling those few cases. */
4219 if (REG_NOTE_KIND (link) != 0)
4222 /* If we can't recognize the insns, we can't really do anything. */
4223 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
4226 insn_type = get_attr_type (insn);
4227 dep_insn_type = get_attr_type (dep_insn);
4229 /* Bring in the user-defined memory latency. */
4230 if (dep_insn_type == TYPE_ILD
4231 || dep_insn_type == TYPE_FLD
4232 || dep_insn_type == TYPE_LDSYM)
4233 cost += alpha_memory_latency-1;
4235 /* Everything else handled in DFA bypasses now. */
4240 /* The number of instructions that can be issued per cycle. */
4243 alpha_issue_rate (void)
4245 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
4248 /* How many alternative schedules to try. This should be as wide as the
4249 scheduling freedom in the DFA, but no wider. Making this value too
4250 large results extra work for the scheduler.
4252 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4253 alternative schedules. For EV5, we can choose between E0/E1 and
4254 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4257 alpha_multipass_dfa_lookahead (void)
4259 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
4262 /* Machine-specific function data. */
4264 struct machine_function GTY(())
4267 /* List of call information words for calls from this function. */
4268 struct rtx_def *first_ciw;
4269 struct rtx_def *last_ciw;
4272 /* List of deferred case vectors. */
4273 struct rtx_def *addr_list;
4276 const char *some_ld_name;
4278 /* For TARGET_LD_BUGGY_LDGP. */
4279 struct rtx_def *gp_save_rtx;
4282 /* How to allocate a 'struct machine_function'. */
4284 static struct machine_function *
4285 alpha_init_machine_status (void)
4287 return ((struct machine_function *)
4288 ggc_alloc_cleared (sizeof (struct machine_function)));
4291 /* Functions to save and restore alpha_return_addr_rtx. */
4293 /* Start the ball rolling with RETURN_ADDR_RTX. */
4296 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4301 return get_hard_reg_initial_val (Pmode, REG_RA);
4304 /* Return or create a memory slot containing the gp value for the current
4305 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4308 alpha_gp_save_rtx (void)
4310 rtx seq, m = cfun->machine->gp_save_rtx;
4316 m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
4317 m = validize_mem (m);
4318 emit_move_insn (m, pic_offset_table_rtx);
4322 emit_insn_after (seq, entry_of_function ());
4324 cfun->machine->gp_save_rtx = m;
4331 alpha_ra_ever_killed (void)
4335 if (!has_hard_reg_initial_val (Pmode, REG_RA))
4336 return regs_ever_live[REG_RA];
4338 push_topmost_sequence ();
4340 pop_topmost_sequence ();
4342 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
4346 /* Return the trap mode suffix applicable to the current
4347 instruction, or NULL. */
4350 get_trap_mode_suffix (void)
4352 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
4356 case TRAP_SUFFIX_NONE:
4359 case TRAP_SUFFIX_SU:
4360 if (alpha_fptm >= ALPHA_FPTM_SU)
4364 case TRAP_SUFFIX_SUI:
4365 if (alpha_fptm >= ALPHA_FPTM_SUI)
4369 case TRAP_SUFFIX_V_SV:
4377 case ALPHA_FPTM_SUI:
4382 case TRAP_SUFFIX_V_SV_SVI:
4391 case ALPHA_FPTM_SUI:
4396 case TRAP_SUFFIX_U_SU_SUI:
4405 case ALPHA_FPTM_SUI:
4413 /* Return the rounding mode suffix applicable to the current
4414 instruction, or NULL. */
4417 get_round_mode_suffix (void)
4419 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
4423 case ROUND_SUFFIX_NONE:
4425 case ROUND_SUFFIX_NORMAL:
4428 case ALPHA_FPRM_NORM:
4430 case ALPHA_FPRM_MINF:
4432 case ALPHA_FPRM_CHOP:
4434 case ALPHA_FPRM_DYN:
4439 case ROUND_SUFFIX_C:
4445 /* Locate some local-dynamic symbol still in use by this function
4446 so that we can print its name in some movdi_er_tlsldm pattern. */
4449 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4453 if (GET_CODE (x) == SYMBOL_REF
4454 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
4456 cfun->machine->some_ld_name = XSTR (x, 0);
4464 get_some_local_dynamic_name (void)
4468 if (cfun->machine->some_ld_name)
4469 return cfun->machine->some_ld_name;
4471 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4473 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4474 return cfun->machine->some_ld_name;
4479 /* Print an operand. Recognize special options, documented below. */
4482 print_operand (FILE *file, rtx x, int code)
4489 /* Print the assembler name of the current function. */
4490 assemble_name (file, alpha_fnname);
4494 assemble_name (file, get_some_local_dynamic_name ());
4499 const char *trap = get_trap_mode_suffix ();
4500 const char *round = get_round_mode_suffix ();
4503 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
4504 (trap ? trap : ""), (round ? round : ""));
4509 /* Generates single precision instruction suffix. */
4510 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
4514 /* Generates double precision instruction suffix. */
4515 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
4519 /* Generates a nop after a noreturn call at the very end of the
4521 if (next_real_insn (current_output_insn) == 0)
4522 fprintf (file, "\n\tnop");
4526 if (alpha_this_literal_sequence_number == 0)
4527 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
4528 fprintf (file, "%d", alpha_this_literal_sequence_number);
4532 if (alpha_this_gpdisp_sequence_number == 0)
4533 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
4534 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
4538 if (GET_CODE (x) == HIGH)
4539 output_addr_const (file, XEXP (x, 0));
4541 output_operand_lossage ("invalid %%H value");
4548 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
4550 x = XVECEXP (x, 0, 0);
4551 lituse = "lituse_tlsgd";
4553 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
4555 x = XVECEXP (x, 0, 0);
4556 lituse = "lituse_tlsldm";
4558 else if (GET_CODE (x) == CONST_INT)
4559 lituse = "lituse_jsr";
4562 output_operand_lossage ("invalid %%J value");
4566 if (x != const0_rtx)
4567 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
4572 /* If this operand is the constant zero, write it as "$31". */
4573 if (GET_CODE (x) == REG)
4574 fprintf (file, "%s", reg_names[REGNO (x)]);
4575 else if (x == CONST0_RTX (GET_MODE (x)))
4576 fprintf (file, "$31");
4578 output_operand_lossage ("invalid %%r value");
4582 /* Similar, but for floating-point. */
4583 if (GET_CODE (x) == REG)
4584 fprintf (file, "%s", reg_names[REGNO (x)]);
4585 else if (x == CONST0_RTX (GET_MODE (x)))
4586 fprintf (file, "$f31");
4588 output_operand_lossage ("invalid %%R value");
4592 /* Write the 1's complement of a constant. */
4593 if (GET_CODE (x) != CONST_INT)
4594 output_operand_lossage ("invalid %%N value");
4596 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
4600 /* Write 1 << C, for a constant C. */
4601 if (GET_CODE (x) != CONST_INT)
4602 output_operand_lossage ("invalid %%P value");
4604 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
4608 /* Write the high-order 16 bits of a constant, sign-extended. */
4609 if (GET_CODE (x) != CONST_INT)
4610 output_operand_lossage ("invalid %%h value");
4612 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
4616 /* Write the low-order 16 bits of a constant, sign-extended. */
4617 if (GET_CODE (x) != CONST_INT)
4618 output_operand_lossage ("invalid %%L value");
4620 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4621 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
4625 /* Write mask for ZAP insn. */
4626 if (GET_CODE (x) == CONST_DOUBLE)
4628 HOST_WIDE_INT mask = 0;
4629 HOST_WIDE_INT value;
4631 value = CONST_DOUBLE_LOW (x);
4632 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
4637 value = CONST_DOUBLE_HIGH (x);
4638 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
4641 mask |= (1 << (i + sizeof (int)));
4643 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
4646 else if (GET_CODE (x) == CONST_INT)
4648 HOST_WIDE_INT mask = 0, value = INTVAL (x);
4650 for (i = 0; i < 8; i++, value >>= 8)
4654 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
4657 output_operand_lossage ("invalid %%m value");
4661 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
4662 if (GET_CODE (x) != CONST_INT
4663 || (INTVAL (x) != 8 && INTVAL (x) != 16
4664 && INTVAL (x) != 32 && INTVAL (x) != 64))
4665 output_operand_lossage ("invalid %%M value");
4667 fprintf (file, "%s",
4668 (INTVAL (x) == 8 ? "b"
4669 : INTVAL (x) == 16 ? "w"
4670 : INTVAL (x) == 32 ? "l"
4675 /* Similar, except do it from the mask. */
4676 if (GET_CODE (x) == CONST_INT)
4678 HOST_WIDE_INT value = INTVAL (x);
4685 if (value == 0xffff)
4690 if (value == 0xffffffff)
4701 else if (HOST_BITS_PER_WIDE_INT == 32
4702 && GET_CODE (x) == CONST_DOUBLE
4703 && CONST_DOUBLE_LOW (x) == 0xffffffff
4704 && CONST_DOUBLE_HIGH (x) == 0)
4709 output_operand_lossage ("invalid %%U value");
4713 /* Write the constant value divided by 8 for little-endian mode or
4714 (56 - value) / 8 for big-endian mode. */
4716 if (GET_CODE (x) != CONST_INT
4717 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
4720 || (INTVAL (x) & 7) != 0)
4721 output_operand_lossage ("invalid %%s value");
4723 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4725 ? (56 - INTVAL (x)) / 8
4730 /* Same, except compute (64 - c) / 8 */
4732 if (GET_CODE (x) != CONST_INT
4733 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
4734 && (INTVAL (x) & 7) != 8)
4735 output_operand_lossage ("invalid %%s value");
4737 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
4742 /* On Unicos/Mk systems: use a DEX expression if the symbol
4743 clashes with a register name. */
4744 int dex = unicosmk_need_dex (x);
4746 fprintf (file, "DEX(%d)", dex);
4748 output_addr_const (file, x);
4752 case 'C': case 'D': case 'c': case 'd':
4753 /* Write out comparison name. */
4755 enum rtx_code c = GET_CODE (x);
4757 if (!COMPARISON_P (x))
4758 output_operand_lossage ("invalid %%C value");
4760 else if (code == 'D')
4761 c = reverse_condition (c);
4762 else if (code == 'c')
4763 c = swap_condition (c);
4764 else if (code == 'd')
4765 c = swap_condition (reverse_condition (c));
4768 fprintf (file, "ule");
4770 fprintf (file, "ult");
4771 else if (c == UNORDERED)
4772 fprintf (file, "un");
4774 fprintf (file, "%s", GET_RTX_NAME (c));
4779 /* Write the divide or modulus operator. */
4780 switch (GET_CODE (x))
4783 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
4786 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
4789 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
4792 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
4795 output_operand_lossage ("invalid %%E value");
4801 /* Write "_u" for unaligned access. */
4802 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
4803 fprintf (file, "_u");
4807 if (GET_CODE (x) == REG)
4808 fprintf (file, "%s", reg_names[REGNO (x)]);
4809 else if (GET_CODE (x) == MEM)
4810 output_address (XEXP (x, 0));
4811 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
4813 switch (XINT (XEXP (x, 0), 1))
4817 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
4820 output_operand_lossage ("unknown relocation unspec");
4825 output_addr_const (file, x);
4829 output_operand_lossage ("invalid %%xn code");
4834 print_operand_address (FILE *file, rtx addr)
4837 HOST_WIDE_INT offset = 0;
4839 if (GET_CODE (addr) == AND)
4840 addr = XEXP (addr, 0);
4842 if (GET_CODE (addr) == PLUS
4843 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
4845 offset = INTVAL (XEXP (addr, 1));
4846 addr = XEXP (addr, 0);
4849 if (GET_CODE (addr) == LO_SUM)
4851 const char *reloc16, *reloclo;
4852 rtx op1 = XEXP (addr, 1);
4854 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
4856 op1 = XEXP (op1, 0);
4857 switch (XINT (op1, 1))
4861 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
4865 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
4868 output_operand_lossage ("unknown relocation unspec");
4872 output_addr_const (file, XVECEXP (op1, 0, 0));
4877 reloclo = "gprellow";
4878 output_addr_const (file, op1);
4882 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
4884 addr = XEXP (addr, 0);
4885 if (GET_CODE (addr) == REG)
4886 basereg = REGNO (addr);
4887 else if (GET_CODE (addr) == SUBREG
4888 && GET_CODE (SUBREG_REG (addr)) == REG)
4889 basereg = subreg_regno (addr);
4893 fprintf (file, "($%d)\t\t!%s", basereg,
4894 (basereg == 29 ? reloc16 : reloclo));
4898 if (GET_CODE (addr) == REG)
4899 basereg = REGNO (addr);
4900 else if (GET_CODE (addr) == SUBREG
4901 && GET_CODE (SUBREG_REG (addr)) == REG)
4902 basereg = subreg_regno (addr);
4903 else if (GET_CODE (addr) == CONST_INT)
4904 offset = INTVAL (addr);
4906 #if TARGET_ABI_OPEN_VMS
4907 else if (GET_CODE (addr) == SYMBOL_REF)
4909 fprintf (file, "%s", XSTR (addr, 0));
4912 else if (GET_CODE (addr) == CONST
4913 && GET_CODE (XEXP (addr, 0)) == PLUS
4914 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
4916 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
4917 XSTR (XEXP (XEXP (addr, 0), 0), 0),
4918 INTVAL (XEXP (XEXP (addr, 0), 1)));
4926 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
4929 /* Emit RTL insns to initialize the variable parts of a trampoline at
4930 TRAMP. FNADDR is an RTX for the address of the function's pure
4931 code. CXT is an RTX for the static chain value for the function.
4933 The three offset parameters are for the individual template's
4934 layout. A JMPOFS < 0 indicates that the trampoline does not
4935 contain instructions at all.
4937 We assume here that a function will be called many more times than
4938 its address is taken (e.g., it might be passed to qsort), so we
4939 take the trouble to initialize the "hint" field in the JMP insn.
4940 Note that the hint field is PC (new) + 4 * bits 13:0. */
4943 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
4944 int fnofs, int cxtofs, int jmpofs)
4946 rtx temp, temp1, addr;
4947 /* VMS really uses DImode pointers in memory at this point. */
4948 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
4950 #ifdef POINTERS_EXTEND_UNSIGNED
4951 fnaddr = convert_memory_address (mode, fnaddr);
4952 cxt = convert_memory_address (mode, cxt);
4955 /* Store function address and CXT. */
4956 addr = memory_address (mode, plus_constant (tramp, fnofs));
4957 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
4958 addr = memory_address (mode, plus_constant (tramp, cxtofs));
4959 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
4961 /* This has been disabled since the hint only has a 32k range, and in
4962 no existing OS is the stack within 32k of the text segment. */
4963 if (0 && jmpofs >= 0)
4965 /* Compute hint value. */
4966 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
4967 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
4969 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
4970 build_int_cst (NULL_TREE, 2), NULL_RTX, 1);
4971 temp = expand_and (SImode, gen_lowpart (SImode, temp),
4972 GEN_INT (0x3fff), 0);
4974 /* Merge in the hint. */
4975 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
4976 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
4977 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
4978 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
4980 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
4983 #ifdef ENABLE_EXECUTE_STACK
4984 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
4985 0, VOIDmode, 1, tramp, Pmode);
4989 emit_insn (gen_imb ());
4992 /* Determine where to put an argument to a function.
4993 Value is zero to push the argument on the stack,
4994 or a hard register in which to store the argument.
4996 MODE is the argument's machine mode.
4997 TYPE is the data type of the argument (as a tree).
4998 This is null for libcalls where that information may
5000 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5001 the preceding args and about the function being called.
5002 NAMED is nonzero if this argument is a named parameter
5003 (otherwise it is an extra parameter matching an ellipsis).
5005 On Alpha the first 6 words of args are normally in registers
5006 and the rest are pushed. */
5009 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5010 int named ATTRIBUTE_UNUSED)
5015 /* Don't get confused and pass small structures in FP registers. */
5016 if (type && AGGREGATE_TYPE_P (type))
5020 #ifdef ENABLE_CHECKING
5021 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5023 if (COMPLEX_MODE_P (mode))
5027 /* Set up defaults for FP operands passed in FP registers, and
5028 integral operands passed in integer registers. */
5029 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5035 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5036 the three platforms, so we can't avoid conditional compilation. */
5037 #if TARGET_ABI_OPEN_VMS
5039 if (mode == VOIDmode)
5040 return alpha_arg_info_reg_val (cum);
5042 num_args = cum.num_args;
5044 || targetm.calls.must_pass_in_stack (mode, type))
5047 #elif TARGET_ABI_UNICOSMK
5051 /* If this is the last argument, generate the call info word (CIW). */
5052 /* ??? We don't include the caller's line number in the CIW because
5053 I don't know how to determine it if debug infos are turned off. */
5054 if (mode == VOIDmode)
5063 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5064 if (cum.reg_args_type[i])
5065 lo |= (1 << (7 - i));
5067 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5070 lo |= cum.num_reg_words;
5072 #if HOST_BITS_PER_WIDE_INT == 32
5073 hi = (cum.num_args << 20) | cum.num_arg_words;
5075 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5076 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5079 ciw = immed_double_const (lo, hi, DImode);
5081 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5082 UNSPEC_UMK_LOAD_CIW);
5085 size = ALPHA_ARG_SIZE (mode, type, named);
5086 num_args = cum.num_reg_words;
5088 || cum.num_reg_words + size > 6
5089 || targetm.calls.must_pass_in_stack (mode, type))
5091 else if (type && TYPE_MODE (type) == BLKmode)
5095 reg1 = gen_rtx_REG (DImode, num_args + 16);
5096 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5098 /* The argument fits in two registers. Note that we still need to
5099 reserve a register for empty structures. */
5103 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5106 reg2 = gen_rtx_REG (DImode, num_args + 17);
5107 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5108 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5112 #elif TARGET_ABI_OSF
5118 /* VOID is passed as a special flag for "last argument". */
5119 if (type == void_type_node)
5121 else if (targetm.calls.must_pass_in_stack (mode, type))
5125 #error Unhandled ABI
5128 return gen_rtx_REG (mode, num_args + basereg);
5131 /* Return true if TYPE must be returned in memory, instead of in registers. */
5134 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
5136 enum machine_mode mode = VOIDmode;
5141 mode = TYPE_MODE (type);
5143 /* All aggregates are returned in memory. */
5144 if (AGGREGATE_TYPE_P (type))
5148 size = GET_MODE_SIZE (mode);
5149 switch (GET_MODE_CLASS (mode))
5151 case MODE_VECTOR_FLOAT:
5152 /* Pass all float vectors in memory, like an aggregate. */
5155 case MODE_COMPLEX_FLOAT:
5156 /* We judge complex floats on the size of their element,
5157 not the size of the whole type. */
5158 size = GET_MODE_UNIT_SIZE (mode);
5163 case MODE_COMPLEX_INT:
5164 case MODE_VECTOR_INT:
5168 /* ??? We get called on all sorts of random stuff from
5169 aggregate_value_p. We can't abort, but it's not clear
5170 what's safe to return. Pretend it's a struct I guess. */
5174 /* Otherwise types must fit in one register. */
5175 return size > UNITS_PER_WORD;
5178 /* Return true if TYPE should be passed by invisible reference. */
5181 alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5182 enum machine_mode mode,
5183 tree type ATTRIBUTE_UNUSED,
5184 bool named ATTRIBUTE_UNUSED)
5186 return mode == TFmode || mode == TCmode;
5189 /* Define how to find the value returned by a function. VALTYPE is the
5190 data type of the value (as a tree). If the precise function being
5191 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5192 MODE is set instead of VALTYPE for libcalls.
5194 On Alpha the value is found in $0 for integer functions and
5195 $f0 for floating-point functions. */
5198 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
5199 enum machine_mode mode)
5201 unsigned int regnum, dummy;
5202 enum mode_class class;
5204 #ifdef ENABLE_CHECKING
5205 if (valtype && alpha_return_in_memory (valtype, func))
5210 mode = TYPE_MODE (valtype);
5212 class = GET_MODE_CLASS (mode);
5216 PROMOTE_MODE (mode, dummy, valtype);
5219 case MODE_COMPLEX_INT:
5220 case MODE_VECTOR_INT:
5228 case MODE_COMPLEX_FLOAT:
5230 enum machine_mode cmode = GET_MODE_INNER (mode);
5232 return gen_rtx_PARALLEL
5235 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
5237 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
5238 GEN_INT (GET_MODE_SIZE (cmode)))));
5245 return gen_rtx_REG (mode, regnum);
5248 /* TCmode complex values are passed by invisible reference. We
5249 should not split these values. */
5252 alpha_split_complex_arg (tree type)
5254 return TYPE_MODE (type) != TCmode;
5258 alpha_build_builtin_va_list (void)
5260 tree base, ofs, space, record, type_decl;
5262 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5263 return ptr_type_node;
5265 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5266 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5267 TREE_CHAIN (record) = type_decl;
5268 TYPE_NAME (record) = type_decl;
5270 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5272 /* Dummy field to prevent alignment warnings. */
5273 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
5274 DECL_FIELD_CONTEXT (space) = record;
5275 DECL_ARTIFICIAL (space) = 1;
5276 DECL_IGNORED_P (space) = 1;
5278 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
5280 DECL_FIELD_CONTEXT (ofs) = record;
5281 TREE_CHAIN (ofs) = space;
5283 base = build_decl (FIELD_DECL, get_identifier ("__base"),
5285 DECL_FIELD_CONTEXT (base) = record;
5286 TREE_CHAIN (base) = ofs;
5288 TYPE_FIELDS (record) = base;
5289 layout_type (record);
5294 /* Perform any needed actions needed for a function that is receiving a
5295 variable number of arguments. */
5298 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
5299 enum machine_mode mode ATTRIBUTE_UNUSED,
5300 tree type ATTRIBUTE_UNUSED,
5301 int *pretend_size, int no_rtl)
5303 #if TARGET_ABI_UNICOSMK
5304 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
5305 arguments on the stack. Unfortunately, it doesn't always store the first
5306 one (i.e. the one that arrives in $16 or $f16). This is not a problem
5307 with stdargs as we always have at least one named argument there. */
5308 int num_reg_words = pcum->num_reg_words;
5309 if (num_reg_words < 6)
5313 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
5314 emit_insn (gen_arg_home_umk ());
5318 #elif TARGET_ABI_OPEN_VMS
5319 /* For VMS, we allocate space for all 6 arg registers plus a count.
5321 However, if NO registers need to be saved, don't allocate any space.
5322 This is not only because we won't need the space, but because AP
5323 includes the current_pretend_args_size and we don't want to mess up
5324 any ap-relative addresses already made. */
5325 if (pcum->num_args < 6)
5329 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
5330 emit_insn (gen_arg_home ());
5332 *pretend_size = 7 * UNITS_PER_WORD;
5335 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
5336 only push those that are remaining. However, if NO registers need to
5337 be saved, don't allocate any space. This is not only because we won't
5338 need the space, but because AP includes the current_pretend_args_size
5339 and we don't want to mess up any ap-relative addresses already made.
5341 If we are not to use the floating-point registers, save the integer
5342 registers where we would put the floating-point registers. This is
5343 not the most efficient way to implement varargs with just one register
5344 class, but it isn't worth doing anything more efficient in this rare
5346 CUMULATIVE_ARGS cum = *pcum;
5353 int set = get_varargs_alias_set ();
5356 tmp = gen_rtx_MEM (BLKmode,
5357 plus_constant (virtual_incoming_args_rtx,
5358 (cum + 6) * UNITS_PER_WORD));
5359 set_mem_alias_set (tmp, set);
5360 move_block_from_reg (16 + cum, tmp, 6 - cum);
5362 tmp = gen_rtx_MEM (BLKmode,
5363 plus_constant (virtual_incoming_args_rtx,
5364 cum * UNITS_PER_WORD));
5365 set_mem_alias_set (tmp, set);
5366 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
5369 *pretend_size = 12 * UNITS_PER_WORD;
5374 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
5376 HOST_WIDE_INT offset;
5377 tree t, offset_field, base_field;
5379 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
5382 if (TARGET_ABI_UNICOSMK)
5383 std_expand_builtin_va_start (valist, nextarg);
5385 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
5386 up by 48, storing fp arg registers in the first 48 bytes, and the
5387 integer arg registers in the next 48 bytes. This is only done,
5388 however, if any integer registers need to be stored.
5390 If no integer registers need be stored, then we must subtract 48
5391 in order to account for the integer arg registers which are counted
5392 in argsize above, but which are not actually stored on the stack.
5393 Must further be careful here about structures straddling the last
5394 integer argument register; that futzes with pretend_args_size,
5395 which changes the meaning of AP. */
5398 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
5400 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
5402 if (TARGET_ABI_OPEN_VMS)
5404 nextarg = plus_constant (nextarg, offset);
5405 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
5406 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
5407 make_tree (ptr_type_node, nextarg));
5408 TREE_SIDE_EFFECTS (t) = 1;
5410 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5414 base_field = TYPE_FIELDS (TREE_TYPE (valist));
5415 offset_field = TREE_CHAIN (base_field);
5417 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
5418 valist, base_field, NULL_TREE);
5419 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
5420 valist, offset_field, NULL_TREE);
5422 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
5423 t = build (PLUS_EXPR, ptr_type_node, t,
5424 build_int_cst (NULL_TREE, offset));
5425 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
5426 TREE_SIDE_EFFECTS (t) = 1;
5427 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5429 t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
5430 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
5431 TREE_SIDE_EFFECTS (t) = 1;
5432 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5437 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, tree *pre_p)
5439 tree type_size, ptr_type, addend, t, addr, internal_post;
5441 /* If the type could not be passed in registers, skip the block
5442 reserved for the registers. */
5443 if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
5445 t = build_int_cst (TREE_TYPE (offset), 6*8);
5446 t = build (MODIFY_EXPR, TREE_TYPE (offset), offset,
5447 build (MAX_EXPR, TREE_TYPE (offset), offset, t));
5448 gimplify_and_add (t, pre_p);
5452 ptr_type = build_pointer_type (type);
5454 if (TREE_CODE (type) == COMPLEX_TYPE)
5456 tree real_part, imag_part, real_temp;
5458 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
5461 /* Copy the value into a new temporary, lest the formal temporary
5462 be reused out from under us. */
5463 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
5465 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
5468 return build (COMPLEX_EXPR, type, real_temp, imag_part);
5470 else if (TREE_CODE (type) == REAL_TYPE)
5472 tree fpaddend, cond, fourtyeight;
5474 fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
5475 fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend),
5476 addend, fourtyeight));
5477 cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight));
5478 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
5482 /* Build the final address and force that value into a temporary. */
5483 addr = build (PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
5484 fold_convert (ptr_type, addend));
5485 internal_post = NULL;
5486 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
5487 append_to_statement_list (internal_post, pre_p);
5489 /* Update the offset field. */
5490 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
5491 if (type_size == NULL || TREE_OVERFLOW (type_size))
5495 t = size_binop (PLUS_EXPR, type_size, size_int (7));
5496 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
5497 t = size_binop (MULT_EXPR, t, size_int (8));
5499 t = fold_convert (TREE_TYPE (offset), t);
5500 t = build (MODIFY_EXPR, void_type_node, offset,
5501 build (PLUS_EXPR, TREE_TYPE (offset), offset, t));
5502 gimplify_and_add (t, pre_p);
5504 return build_fold_indirect_ref (addr);
5508 alpha_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5510 tree offset_field, base_field, offset, base, t, r;
5513 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5514 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5516 base_field = TYPE_FIELDS (va_list_type_node);
5517 offset_field = TREE_CHAIN (base_field);
5518 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
5519 valist, base_field, NULL_TREE);
5520 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
5521 valist, offset_field, NULL_TREE);
5523 /* Pull the fields of the structure out into temporaries. Since we never
5524 modify the base field, we can use a formal temporary. Sign-extend the
5525 offset field so that it's the proper width for pointer arithmetic. */
5526 base = get_formal_tmp_var (base_field, pre_p);
5528 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
5529 offset = get_initialized_tmp_var (t, pre_p, NULL);
5531 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5533 type = build_pointer_type (type);
5535 /* Find the value. Note that this will be a stable indirection, or
5536 a composite of stable indirections in the case of complex. */
5537 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
5539 /* Stuff the offset temporary back into its field. */
5540 t = build (MODIFY_EXPR, void_type_node, offset_field,
5541 fold_convert (TREE_TYPE (offset_field), offset));
5542 gimplify_and_add (t, pre_p);
5545 r = build_fold_indirect_ref (r);
5554 ALPHA_BUILTIN_CMPBGE,
5555 ALPHA_BUILTIN_EXTBL,
5556 ALPHA_BUILTIN_EXTWL,
5557 ALPHA_BUILTIN_EXTLL,
5558 ALPHA_BUILTIN_EXTQL,
5559 ALPHA_BUILTIN_EXTWH,
5560 ALPHA_BUILTIN_EXTLH,
5561 ALPHA_BUILTIN_EXTQH,
5562 ALPHA_BUILTIN_INSBL,
5563 ALPHA_BUILTIN_INSWL,
5564 ALPHA_BUILTIN_INSLL,
5565 ALPHA_BUILTIN_INSQL,
5566 ALPHA_BUILTIN_INSWH,
5567 ALPHA_BUILTIN_INSLH,
5568 ALPHA_BUILTIN_INSQH,
5569 ALPHA_BUILTIN_MSKBL,
5570 ALPHA_BUILTIN_MSKWL,
5571 ALPHA_BUILTIN_MSKLL,
5572 ALPHA_BUILTIN_MSKQL,
5573 ALPHA_BUILTIN_MSKWH,
5574 ALPHA_BUILTIN_MSKLH,
5575 ALPHA_BUILTIN_MSKQH,
5576 ALPHA_BUILTIN_UMULH,
5578 ALPHA_BUILTIN_ZAPNOT,
5579 ALPHA_BUILTIN_AMASK,
5580 ALPHA_BUILTIN_IMPLVER,
5582 ALPHA_BUILTIN_THREAD_POINTER,
5583 ALPHA_BUILTIN_SET_THREAD_POINTER,
5586 ALPHA_BUILTIN_MINUB8,
5587 ALPHA_BUILTIN_MINSB8,
5588 ALPHA_BUILTIN_MINUW4,
5589 ALPHA_BUILTIN_MINSW4,
5590 ALPHA_BUILTIN_MAXUB8,
5591 ALPHA_BUILTIN_MAXSB8,
5592 ALPHA_BUILTIN_MAXUW4,
5593 ALPHA_BUILTIN_MAXSW4,
5597 ALPHA_BUILTIN_UNPKBL,
5598 ALPHA_BUILTIN_UNPKBW,
5603 ALPHA_BUILTIN_CTPOP,
5608 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
5609 CODE_FOR_builtin_cmpbge,
5610 CODE_FOR_builtin_extbl,
5611 CODE_FOR_builtin_extwl,
5612 CODE_FOR_builtin_extll,
5613 CODE_FOR_builtin_extql,
5614 CODE_FOR_builtin_extwh,
5615 CODE_FOR_builtin_extlh,
5616 CODE_FOR_builtin_extqh,
5617 CODE_FOR_builtin_insbl,
5618 CODE_FOR_builtin_inswl,
5619 CODE_FOR_builtin_insll,
5620 CODE_FOR_builtin_insql,
5621 CODE_FOR_builtin_inswh,
5622 CODE_FOR_builtin_inslh,
5623 CODE_FOR_builtin_insqh,
5624 CODE_FOR_builtin_mskbl,
5625 CODE_FOR_builtin_mskwl,
5626 CODE_FOR_builtin_mskll,
5627 CODE_FOR_builtin_mskql,
5628 CODE_FOR_builtin_mskwh,
5629 CODE_FOR_builtin_msklh,
5630 CODE_FOR_builtin_mskqh,
5631 CODE_FOR_umuldi3_highpart,
5632 CODE_FOR_builtin_zap,
5633 CODE_FOR_builtin_zapnot,
5634 CODE_FOR_builtin_amask,
5635 CODE_FOR_builtin_implver,
5636 CODE_FOR_builtin_rpcc,
5641 CODE_FOR_builtin_minub8,
5642 CODE_FOR_builtin_minsb8,
5643 CODE_FOR_builtin_minuw4,
5644 CODE_FOR_builtin_minsw4,
5645 CODE_FOR_builtin_maxub8,
5646 CODE_FOR_builtin_maxsb8,
5647 CODE_FOR_builtin_maxuw4,
5648 CODE_FOR_builtin_maxsw4,
5649 CODE_FOR_builtin_perr,
5650 CODE_FOR_builtin_pklb,
5651 CODE_FOR_builtin_pkwb,
5652 CODE_FOR_builtin_unpkbl,
5653 CODE_FOR_builtin_unpkbw,
5656 CODE_FOR_builtin_cttz,
5657 CODE_FOR_builtin_ctlz,
5658 CODE_FOR_builtin_ctpop
5661 struct alpha_builtin_def
5664 enum alpha_builtin code;
5665 unsigned int target_mask;
5668 static struct alpha_builtin_def const zero_arg_builtins[] = {
5669 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
5670 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
5673 static struct alpha_builtin_def const one_arg_builtins[] = {
5674 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
5675 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
5676 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
5677 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
5678 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
5679 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
5680 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
5681 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
5684 static struct alpha_builtin_def const two_arg_builtins[] = {
5685 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
5686 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
5687 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
5688 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
5689 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
5690 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
5691 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
5692 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
5693 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
5694 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
5695 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
5696 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
5697 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
5698 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
5699 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
5700 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
5701 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
5702 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
5703 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
5704 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
5705 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
5706 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
5707 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
5708 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
5709 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
5710 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
5711 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
5712 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
5713 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
5714 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
5715 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
5716 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
5717 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
5718 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
5722 alpha_init_builtins (void)
5724 const struct alpha_builtin_def *p;
5728 ftype = build_function_type (long_integer_type_node, void_list_node);
5730 p = zero_arg_builtins;
5731 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
5732 if ((target_flags & p->target_mask) == p->target_mask)
5733 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5736 ftype = build_function_type_list (long_integer_type_node,
5737 long_integer_type_node, NULL_TREE);
5739 p = one_arg_builtins;
5740 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
5741 if ((target_flags & p->target_mask) == p->target_mask)
5742 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5745 ftype = build_function_type_list (long_integer_type_node,
5746 long_integer_type_node,
5747 long_integer_type_node, NULL_TREE);
5749 p = two_arg_builtins;
5750 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
5751 if ((target_flags & p->target_mask) == p->target_mask)
5752 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
5755 ftype = build_function_type (ptr_type_node, void_list_node);
5756 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
5757 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
5760 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
5761 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
5762 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
5766 /* Expand an expression EXP that calls a built-in function,
5767 with result going to TARGET if that's convenient
5768 (and in mode MODE if that's convenient).
5769 SUBTARGET may be used as the target for computing one of EXP's operands.
5770 IGNORE is nonzero if the value is to be ignored. */
5773 alpha_expand_builtin (tree exp, rtx target,
5774 rtx subtarget ATTRIBUTE_UNUSED,
5775 enum machine_mode mode ATTRIBUTE_UNUSED,
5776 int ignore ATTRIBUTE_UNUSED)
5780 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5781 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5782 tree arglist = TREE_OPERAND (exp, 1);
5783 enum insn_code icode;
5784 rtx op[MAX_ARGS], pat;
5788 if (fcode >= ALPHA_BUILTIN_max)
5789 internal_error ("bad builtin fcode");
5790 icode = code_for_builtin[fcode];
5792 internal_error ("bad builtin fcode");
5794 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
5796 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
5798 arglist = TREE_CHAIN (arglist), arity++)
5800 const struct insn_operand_data *insn_op;
5802 tree arg = TREE_VALUE (arglist);
5803 if (arg == error_mark_node)
5805 if (arity > MAX_ARGS)
5808 insn_op = &insn_data[icode].operand[arity + nonvoid];
5810 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
5812 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
5813 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
5818 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5820 || GET_MODE (target) != tmode
5821 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
5822 target = gen_reg_rtx (tmode);
5828 pat = GEN_FCN (icode) (target);
5832 pat = GEN_FCN (icode) (target, op[0]);
5834 pat = GEN_FCN (icode) (op[0]);
5837 pat = GEN_FCN (icode) (target, op[0], op[1]);
5852 /* This page contains routines that are used to determine what the function
5853 prologue and epilogue code will do and write them out. */
5855 /* Compute the size of the save area in the stack. */
5857 /* These variables are used for communication between the following functions.
5858 They indicate various things about the current function being compiled
5859 that are used to tell what kind of prologue, epilogue and procedure
5860 descriptor to generate. */
5862 /* Nonzero if we need a stack procedure. */
5863 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
5864 static enum alpha_procedure_types alpha_procedure_type;
5866 /* Register number (either FP or SP) that is used to unwind the frame. */
5867 static int vms_unwind_regno;
5869 /* Register number used to save FP. We need not have one for RA since
5870 we don't modify it for register procedures. This is only defined
5871 for register frame procedures. */
5872 static int vms_save_fp_regno;
5874 /* Register number used to reference objects off our PV. */
5875 static int vms_base_regno;
5877 /* Compute register masks for saved registers. */
5880 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
5882 unsigned long imask = 0;
5883 unsigned long fmask = 0;
5886 /* When outputting a thunk, we don't have valid register life info,
5887 but assemble_start_function wants to output .frame and .mask
5889 if (current_function_is_thunk)
5896 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
5897 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
5899 /* One for every register we have to save. */
5900 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5901 if (! fixed_regs[i] && ! call_used_regs[i]
5902 && regs_ever_live[i] && i != REG_RA
5903 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
5906 imask |= (1UL << i);
5908 fmask |= (1UL << (i - 32));
5911 /* We need to restore these for the handler. */
5912 if (current_function_calls_eh_return)
5916 unsigned regno = EH_RETURN_DATA_REGNO (i);
5917 if (regno == INVALID_REGNUM)
5919 imask |= 1UL << regno;
5922 /* Glibc likes to use $31 as an unwind stopper for crt0. To
5923 avoid hackery in unwind-dw2.c, we need to actively store a
5924 zero in the prologue of _Unwind_RaiseException et al. */
5928 /* If any register spilled, then spill the return address also. */
5929 /* ??? This is required by the Digital stack unwind specification
5930 and isn't needed if we're doing Dwarf2 unwinding. */
5931 if (imask || fmask || alpha_ra_ever_killed ())
5932 imask |= (1UL << REG_RA);
5939 alpha_sa_size (void)
5941 unsigned long mask[2];
5945 alpha_sa_mask (&mask[0], &mask[1]);
5947 if (TARGET_ABI_UNICOSMK)
5949 if (mask[0] || mask[1])
5954 for (j = 0; j < 2; ++j)
5955 for (i = 0; i < 32; ++i)
5956 if ((mask[j] >> i) & 1)
5960 if (TARGET_ABI_UNICOSMK)
5962 /* We might not need to generate a frame if we don't make any calls
5963 (including calls to __T3E_MISMATCH if this is a vararg function),
5964 don't have any local variables which require stack slots, don't
5965 use alloca and have not determined that we need a frame for other
5968 alpha_procedure_type
5969 = (sa_size || get_frame_size() != 0
5970 || current_function_outgoing_args_size
5971 || current_function_stdarg || current_function_calls_alloca
5972 || frame_pointer_needed)
5973 ? PT_STACK : PT_REGISTER;
5975 /* Always reserve space for saving callee-saved registers if we
5976 need a frame as required by the calling convention. */
5977 if (alpha_procedure_type == PT_STACK)
5980 else if (TARGET_ABI_OPEN_VMS)
5982 /* Start by assuming we can use a register procedure if we don't
5983 make any calls (REG_RA not used) or need to save any
5984 registers and a stack procedure if we do. */
5985 if ((mask[0] >> REG_RA) & 1)
5986 alpha_procedure_type = PT_STACK;
5987 else if (get_frame_size() != 0)
5988 alpha_procedure_type = PT_REGISTER;
5990 alpha_procedure_type = PT_NULL;
5992 /* Don't reserve space for saving FP & RA yet. Do that later after we've
5993 made the final decision on stack procedure vs register procedure. */
5994 if (alpha_procedure_type == PT_STACK)
5997 /* Decide whether to refer to objects off our PV via FP or PV.
5998 If we need FP for something else or if we receive a nonlocal
5999 goto (which expects PV to contain the value), we must use PV.
6000 Otherwise, start by assuming we can use FP. */
6003 = (frame_pointer_needed
6004 || current_function_has_nonlocal_label
6005 || alpha_procedure_type == PT_STACK
6006 || current_function_outgoing_args_size)
6007 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6009 /* If we want to copy PV into FP, we need to find some register
6010 in which to save FP. */
6012 vms_save_fp_regno = -1;
6013 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6014 for (i = 0; i < 32; i++)
6015 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6016 vms_save_fp_regno = i;
6018 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6019 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6020 else if (alpha_procedure_type == PT_NULL)
6021 vms_base_regno = REG_PV;
6023 /* Stack unwinding should be done via FP unless we use it for PV. */
6024 vms_unwind_regno = (vms_base_regno == REG_PV
6025 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6027 /* If this is a stack procedure, allow space for saving FP and RA. */
6028 if (alpha_procedure_type == PT_STACK)
6033 /* Our size must be even (multiple of 16 bytes). */
6041 /* Define the offset between two registers, one to be eliminated,
6042 and the other its replacement, at the start of a routine. */
6045 alpha_initial_elimination_offset (unsigned int from,
6046 unsigned int to ATTRIBUTE_UNUSED)
6050 ret = alpha_sa_size ();
6051 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6053 if (from == FRAME_POINTER_REGNUM)
6055 else if (from == ARG_POINTER_REGNUM)
6056 ret += (ALPHA_ROUND (get_frame_size ()
6057 + current_function_pretend_args_size)
6058 - current_function_pretend_args_size);
6066 alpha_pv_save_size (void)
6069 return alpha_procedure_type == PT_STACK ? 8 : 0;
6073 alpha_using_fp (void)
6076 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6079 #if TARGET_ABI_OPEN_VMS
6081 const struct attribute_spec vms_attribute_table[] =
6083 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6084 { "overlaid", 0, 0, true, false, false, NULL },
6085 { "global", 0, 0, true, false, false, NULL },
6086 { "initialize", 0, 0, true, false, false, NULL },
6087 { NULL, 0, 0, false, false, false, NULL }
6093 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6095 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6099 alpha_find_lo_sum_using_gp (rtx insn)
6101 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
6105 alpha_does_function_need_gp (void)
6109 /* The GP being variable is an OSF abi thing. */
6110 if (! TARGET_ABI_OSF)
6113 /* We need the gp to load the address of __mcount. */
6114 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6117 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6118 if (current_function_is_thunk)
6121 /* The nonlocal receiver pattern assumes that the gp is valid for
6122 the nested function. Reasonable because it's almost always set
6123 correctly already. For the cases where that's wrong, make sure
6124 the nested function loads its gp on entry. */
6125 if (current_function_has_nonlocal_goto)
6128 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6129 Even if we are a static function, we still need to do this in case
6130 our address is taken and passed to something like qsort. */
6132 push_topmost_sequence ();
6133 insn = get_insns ();
6134 pop_topmost_sequence ();
6136 for (; insn; insn = NEXT_INSN (insn))
6138 && GET_CODE (PATTERN (insn)) != USE
6139 && GET_CODE (PATTERN (insn)) != CLOBBER
6140 && get_attr_usegp (insn))
6147 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6151 set_frame_related_p (void)
6153 rtx seq = get_insns ();
6164 while (insn != NULL_RTX)
6166 RTX_FRAME_RELATED_P (insn) = 1;
6167 insn = NEXT_INSN (insn);
6169 seq = emit_insn (seq);
6173 seq = emit_insn (seq);
6174 RTX_FRAME_RELATED_P (seq) = 1;
6179 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6181 /* Generates a store with the proper unwind info attached. VALUE is
6182 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
6183 contains SP+FRAME_BIAS, and that is the unwind info that should be
6184 generated. If FRAME_REG != VALUE, then VALUE is being stored on
6185 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
6188 emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
6189 HOST_WIDE_INT base_ofs, rtx frame_reg)
6191 rtx addr, mem, insn;
6193 addr = plus_constant (base_reg, base_ofs);
6194 mem = gen_rtx_MEM (DImode, addr);
6195 set_mem_alias_set (mem, alpha_sr_alias_set);
6197 insn = emit_move_insn (mem, value);
6198 RTX_FRAME_RELATED_P (insn) = 1;
6200 if (frame_bias || value != frame_reg)
6204 addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
6205 mem = gen_rtx_MEM (DImode, addr);
6209 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6210 gen_rtx_SET (VOIDmode, mem, frame_reg),
6216 emit_frame_store (unsigned int regno, rtx base_reg,
6217 HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
6219 rtx reg = gen_rtx_REG (DImode, regno);
6220 emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
6223 /* Write function prologue. */
6225 /* On vms we have two kinds of functions:
6227 - stack frame (PROC_STACK)
6228 these are 'normal' functions with local vars and which are
6229 calling other functions
6230 - register frame (PROC_REGISTER)
6231 keeps all data in registers, needs no stack
6233 We must pass this to the assembler so it can generate the
6234 proper pdsc (procedure descriptor)
6235 This is done with the '.pdesc' command.
6237 On not-vms, we don't really differentiate between the two, as we can
6238 simply allocate stack without saving registers. */
6241 alpha_expand_prologue (void)
6243 /* Registers to save. */
6244 unsigned long imask = 0;
6245 unsigned long fmask = 0;
6246 /* Stack space needed for pushing registers clobbered by us. */
6247 HOST_WIDE_INT sa_size;
6248 /* Complete stack size needed. */
6249 HOST_WIDE_INT frame_size;
6250 /* Offset from base reg to register save area. */
6251 HOST_WIDE_INT reg_offset;
6255 sa_size = alpha_sa_size ();
6257 frame_size = get_frame_size ();
6258 if (TARGET_ABI_OPEN_VMS)
6259 frame_size = ALPHA_ROUND (sa_size
6260 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6262 + current_function_pretend_args_size);
6263 else if (TARGET_ABI_UNICOSMK)
6264 /* We have to allocate space for the DSIB if we generate a frame. */
6265 frame_size = ALPHA_ROUND (sa_size
6266 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6267 + ALPHA_ROUND (frame_size
6268 + current_function_outgoing_args_size);
6270 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6272 + ALPHA_ROUND (frame_size
6273 + current_function_pretend_args_size));
6275 if (TARGET_ABI_OPEN_VMS)
6278 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6280 alpha_sa_mask (&imask, &fmask);
6282 /* Emit an insn to reload GP, if needed. */
6285 alpha_function_needs_gp = alpha_does_function_need_gp ();
6286 if (alpha_function_needs_gp)
6287 emit_insn (gen_prologue_ldgp ());
6290 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6291 the call to mcount ourselves, rather than having the linker do it
6292 magically in response to -pg. Since _mcount has special linkage,
6293 don't represent the call as a call. */
6294 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6295 emit_insn (gen_prologue_mcount ());
6297 if (TARGET_ABI_UNICOSMK)
6298 unicosmk_gen_dsib (&imask);
6300 /* Adjust the stack by the frame size. If the frame size is > 4096
6301 bytes, we need to be sure we probe somewhere in the first and last
6302 4096 bytes (we can probably get away without the latter test) and
6303 every 8192 bytes in between. If the frame size is > 32768, we
6304 do this in a loop. Otherwise, we generate the explicit probe
6307 Note that we are only allowed to adjust sp once in the prologue. */
6309 if (frame_size <= 32768)
6311 if (frame_size > 4096)
6316 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6319 while ((probed += 8192) < frame_size);
6321 /* We only have to do this probe if we aren't saving registers. */
6322 if (sa_size == 0 && probed + 4096 < frame_size)
6323 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
6326 if (frame_size != 0)
6327 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6328 GEN_INT (TARGET_ABI_UNICOSMK
6334 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6335 number of 8192 byte blocks to probe. We then probe each block
6336 in the loop and then set SP to the proper location. If the
6337 amount remaining is > 4096, we have to do one more probe if we
6338 are not saving any registers. */
6340 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
6341 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
6342 rtx ptr = gen_rtx_REG (DImode, 22);
6343 rtx count = gen_rtx_REG (DImode, 23);
6346 emit_move_insn (count, GEN_INT (blocks));
6347 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
6348 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
6350 /* Because of the difficulty in emitting a new basic block this
6351 late in the compilation, generate the loop as a single insn. */
6352 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
6354 if (leftover > 4096 && sa_size == 0)
6356 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
6357 MEM_VOLATILE_P (last) = 1;
6358 emit_move_insn (last, const0_rtx);
6361 if (TARGET_ABI_WINDOWS_NT)
6363 /* For NT stack unwind (done by 'reverse execution'), it's
6364 not OK to take the result of a loop, even though the value
6365 is already in ptr, so we reload it via a single operation
6366 and subtract it to sp.
6368 Yes, that's correct -- we have to reload the whole constant
6369 into a temporary via ldah+lda then subtract from sp. */
6371 HOST_WIDE_INT lo, hi;
6372 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
6373 hi = frame_size - lo;
6375 emit_move_insn (ptr, GEN_INT (hi));
6376 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
6377 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6382 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
6383 GEN_INT (-leftover)));
6386 /* This alternative is special, because the DWARF code cannot
6387 possibly intuit through the loop above. So we invent this
6388 note it looks at instead. */
6389 RTX_FRAME_RELATED_P (seq) = 1;
6391 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6392 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6393 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6394 GEN_INT (TARGET_ABI_UNICOSMK
6400 if (!TARGET_ABI_UNICOSMK)
6402 HOST_WIDE_INT sa_bias = 0;
6404 /* Cope with very large offsets to the register save area. */
6405 sa_reg = stack_pointer_rtx;
6406 if (reg_offset + sa_size > 0x8000)
6408 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
6411 if (low + sa_size <= 0x8000)
6412 sa_bias = reg_offset - low, reg_offset = low;
6414 sa_bias = reg_offset, reg_offset = 0;
6416 sa_reg = gen_rtx_REG (DImode, 24);
6417 sa_bias_rtx = GEN_INT (sa_bias);
6419 if (add_operand (sa_bias_rtx, DImode))
6420 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
6423 emit_move_insn (sa_reg, sa_bias_rtx);
6424 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
6428 /* Save regs in stack order. Beginning with VMS PV. */
6429 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6430 emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
6432 /* Save register RA next. */
6433 if (imask & (1UL << REG_RA))
6435 emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
6436 imask &= ~(1UL << REG_RA);
6440 /* Now save any other registers required to be saved. */
6441 for (i = 0; i < 31; i++)
6442 if (imask & (1UL << i))
6444 emit_frame_store (i, sa_reg, sa_bias, reg_offset);
6448 /* Store a zero if requested for unwinding. */
6449 if (imask & (1UL << 31))
6451 emit_frame_store_1 (const0_rtx, sa_reg, sa_bias, reg_offset,
6452 gen_rtx_REG (Pmode, 31));
6456 for (i = 0; i < 31; i++)
6457 if (fmask & (1UL << i))
6459 emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
6463 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
6465 /* The standard frame on the T3E includes space for saving registers.
6466 We just have to use it. We don't have to save the return address and
6467 the old frame pointer here - they are saved in the DSIB. */
6470 for (i = 9; i < 15; i++)
6471 if (imask & (1UL << i))
6473 emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
6476 for (i = 2; i < 10; i++)
6477 if (fmask & (1UL << i))
6479 emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
6484 if (TARGET_ABI_OPEN_VMS)
6486 if (alpha_procedure_type == PT_REGISTER)
6487 /* Register frame procedures save the fp.
6488 ?? Ought to have a dwarf2 save for this. */
6489 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
6490 hard_frame_pointer_rtx);
6492 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
6493 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
6494 gen_rtx_REG (DImode, REG_PV)));
6496 if (alpha_procedure_type != PT_NULL
6497 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
6498 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
6500 /* If we have to allocate space for outgoing args, do it now. */
6501 if (current_function_outgoing_args_size != 0)
6504 = emit_move_insn (stack_pointer_rtx,
6506 (hard_frame_pointer_rtx,
6508 (current_function_outgoing_args_size))));
6510 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
6511 if ! frame_pointer_needed. Setting the bit will change the CFA
6512 computation rule to use sp again, which would be wrong if we had
6513 frame_pointer_needed, as this means sp might move unpredictably
6517 frame_pointer_needed
6518 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
6520 current_function_outgoing_args_size != 0
6521 => alpha_procedure_type != PT_NULL,
6523 so when we are not setting the bit here, we are guaranteed to
6524 have emitted an FRP frame pointer update just before. */
6525 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
6528 else if (!TARGET_ABI_UNICOSMK)
6530 /* If we need a frame pointer, set it from the stack pointer. */
6531 if (frame_pointer_needed)
6533 if (TARGET_CAN_FAULT_IN_PROLOGUE)
6534 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
6536 /* This must always be the last instruction in the
6537 prologue, thus we emit a special move + clobber. */
6538 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
6539 stack_pointer_rtx, sa_reg)));
6543 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6544 the prologue, for exception handling reasons, we cannot do this for
6545 any insn that might fault. We could prevent this for mems with a
6546 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6547 have to prevent all such scheduling with a blockage.
6549 Linux, on the other hand, never bothered to implement OSF/1's
6550 exception handling, and so doesn't care about such things. Anyone
6551 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6553 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
6554 emit_insn (gen_blockage ());
6557 /* Output the textual info surrounding the prologue. */
6560 alpha_start_function (FILE *file, const char *fnname,
6561 tree decl ATTRIBUTE_UNUSED)
6563 unsigned long imask = 0;
6564 unsigned long fmask = 0;
6565 /* Stack space needed for pushing registers clobbered by us. */
6566 HOST_WIDE_INT sa_size;
6567 /* Complete stack size needed. */
6568 unsigned HOST_WIDE_INT frame_size;
6569 /* Offset from base reg to register save area. */
6570 HOST_WIDE_INT reg_offset;
6571 char *entry_label = (char *) alloca (strlen (fnname) + 6);
6574 /* Don't emit an extern directive for functions defined in the same file. */
6575 if (TARGET_ABI_UNICOSMK)
6578 name_tree = get_identifier (fnname);
6579 TREE_ASM_WRITTEN (name_tree) = 1;
6582 alpha_fnname = fnname;
6583 sa_size = alpha_sa_size ();
6585 frame_size = get_frame_size ();
6586 if (TARGET_ABI_OPEN_VMS)
6587 frame_size = ALPHA_ROUND (sa_size
6588 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6590 + current_function_pretend_args_size);
6591 else if (TARGET_ABI_UNICOSMK)
6592 frame_size = ALPHA_ROUND (sa_size
6593 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6594 + ALPHA_ROUND (frame_size
6595 + current_function_outgoing_args_size);
6597 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6599 + ALPHA_ROUND (frame_size
6600 + current_function_pretend_args_size));
6602 if (TARGET_ABI_OPEN_VMS)
6605 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6607 alpha_sa_mask (&imask, &fmask);
6609 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6610 We have to do that before the .ent directive as we cannot switch
6611 files within procedures with native ecoff because line numbers are
6612 linked to procedure descriptors.
6613 Outputting the lineno helps debugging of one line functions as they
6614 would otherwise get no line number at all. Please note that we would
6615 like to put out last_linenum from final.c, but it is not accessible. */
6617 if (write_symbols == SDB_DEBUG)
6619 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6620 ASM_OUTPUT_SOURCE_FILENAME (file,
6621 DECL_SOURCE_FILE (current_function_decl));
6623 #ifdef ASM_OUTPUT_SOURCE_LINE
6624 if (debug_info_level != DINFO_LEVEL_TERSE)
6625 ASM_OUTPUT_SOURCE_LINE (file,
6626 DECL_SOURCE_LINE (current_function_decl), 0);
6630 /* Issue function start and label. */
6631 if (TARGET_ABI_OPEN_VMS
6632 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
6634 fputs ("\t.ent ", file);
6635 assemble_name (file, fnname);
6638 /* If the function needs GP, we'll write the "..ng" label there.
6639 Otherwise, do it here. */
6641 && ! alpha_function_needs_gp
6642 && ! current_function_is_thunk)
6645 assemble_name (file, fnname);
6646 fputs ("..ng:\n", file);
6650 strcpy (entry_label, fnname);
6651 if (TARGET_ABI_OPEN_VMS)
6652 strcat (entry_label, "..en");
6654 /* For public functions, the label must be globalized by appending an
6655 additional colon. */
6656 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
6657 strcat (entry_label, ":");
6659 ASM_OUTPUT_LABEL (file, entry_label);
6660 inside_function = TRUE;
6662 if (TARGET_ABI_OPEN_VMS)
6663 fprintf (file, "\t.base $%d\n", vms_base_regno);
6665 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
6666 && !flag_inhibit_size_directive)
6668 /* Set flags in procedure descriptor to request IEEE-conformant
6669 math-library routines. The value we set it to is PDSC_EXC_IEEE
6670 (/usr/include/pdsc.h). */
6671 fputs ("\t.eflag 48\n", file);
6674 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6675 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
6676 alpha_arg_offset = -frame_size + 48;
6678 /* Describe our frame. If the frame size is larger than an integer,
6679 print it as zero to avoid an assembler error. We won't be
6680 properly describing such a frame, but that's the best we can do. */
6681 if (TARGET_ABI_UNICOSMK)
6683 else if (TARGET_ABI_OPEN_VMS)
6684 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
6685 HOST_WIDE_INT_PRINT_DEC "\n",
6687 frame_size >= (1UL << 31) ? 0 : frame_size,
6689 else if (!flag_inhibit_size_directive)
6690 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
6691 (frame_pointer_needed
6692 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
6693 frame_size >= (1UL << 31) ? 0 : frame_size,
6694 current_function_pretend_args_size);
6696 /* Describe which registers were spilled. */
6697 if (TARGET_ABI_UNICOSMK)
6699 else if (TARGET_ABI_OPEN_VMS)
6702 /* ??? Does VMS care if mask contains ra? The old code didn't
6703 set it, so I don't here. */
6704 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
6706 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
6707 if (alpha_procedure_type == PT_REGISTER)
6708 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
6710 else if (!flag_inhibit_size_directive)
6714 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
6715 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
6717 for (i = 0; i < 32; ++i)
6718 if (imask & (1UL << i))
6723 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
6724 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
6727 #if TARGET_ABI_OPEN_VMS
6728 /* Ifdef'ed cause link_section are only available then. */
6729 readonly_data_section ();
6730 fprintf (file, "\t.align 3\n");
6731 assemble_name (file, fnname); fputs ("..na:\n", file);
6732 fputs ("\t.ascii \"", file);
6733 assemble_name (file, fnname);
6734 fputs ("\\0\"\n", file);
6735 alpha_need_linkage (fnname, 1);
6740 /* Emit the .prologue note at the scheduled end of the prologue. */
6743 alpha_output_function_end_prologue (FILE *file)
6745 if (TARGET_ABI_UNICOSMK)
6747 else if (TARGET_ABI_OPEN_VMS)
6748 fputs ("\t.prologue\n", file);
6749 else if (TARGET_ABI_WINDOWS_NT)
6750 fputs ("\t.prologue 0\n", file);
6751 else if (!flag_inhibit_size_directive)
6752 fprintf (file, "\t.prologue %d\n",
6753 alpha_function_needs_gp || current_function_is_thunk);
6756 /* Write function epilogue. */
6758 /* ??? At some point we will want to support full unwind, and so will
6759 need to mark the epilogue as well. At the moment, we just confuse
6762 #define FRP(exp) exp
6765 alpha_expand_epilogue (void)
6767 /* Registers to save. */
6768 unsigned long imask = 0;
6769 unsigned long fmask = 0;
6770 /* Stack space needed for pushing registers clobbered by us. */
6771 HOST_WIDE_INT sa_size;
6772 /* Complete stack size needed. */
6773 HOST_WIDE_INT frame_size;
6774 /* Offset from base reg to register save area. */
6775 HOST_WIDE_INT reg_offset;
6776 int fp_is_frame_pointer, fp_offset;
6777 rtx sa_reg, sa_reg_exp = NULL;
6778 rtx sp_adj1, sp_adj2, mem;
6782 sa_size = alpha_sa_size ();
6784 frame_size = get_frame_size ();
6785 if (TARGET_ABI_OPEN_VMS)
6786 frame_size = ALPHA_ROUND (sa_size
6787 + (alpha_procedure_type == PT_STACK ? 8 : 0)
6789 + current_function_pretend_args_size);
6790 else if (TARGET_ABI_UNICOSMK)
6791 frame_size = ALPHA_ROUND (sa_size
6792 + (alpha_procedure_type == PT_STACK ? 48 : 0))
6793 + ALPHA_ROUND (frame_size
6794 + current_function_outgoing_args_size);
6796 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
6798 + ALPHA_ROUND (frame_size
6799 + current_function_pretend_args_size));
6801 if (TARGET_ABI_OPEN_VMS)
6803 if (alpha_procedure_type == PT_STACK)
6809 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
6811 alpha_sa_mask (&imask, &fmask);
6814 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6815 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
6817 sa_reg = stack_pointer_rtx;
6819 if (current_function_calls_eh_return)
6820 eh_ofs = EH_RETURN_STACKADJ_RTX;
6824 if (!TARGET_ABI_UNICOSMK && sa_size)
6826 /* If we have a frame pointer, restore SP from it. */
6827 if ((TARGET_ABI_OPEN_VMS
6828 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
6829 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
6830 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
6832 /* Cope with very large offsets to the register save area. */
6833 if (reg_offset + sa_size > 0x8000)
6835 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
6838 if (low + sa_size <= 0x8000)
6839 bias = reg_offset - low, reg_offset = low;
6841 bias = reg_offset, reg_offset = 0;
6843 sa_reg = gen_rtx_REG (DImode, 22);
6844 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
6846 FRP (emit_move_insn (sa_reg, sa_reg_exp));
6849 /* Restore registers in order, excepting a true frame pointer. */
6851 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
6853 set_mem_alias_set (mem, alpha_sr_alias_set);
6854 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
6857 imask &= ~(1UL << REG_RA);
6859 for (i = 0; i < 31; ++i)
6860 if (imask & (1UL << i))
6862 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
6863 fp_offset = reg_offset;
6866 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
6867 set_mem_alias_set (mem, alpha_sr_alias_set);
6868 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
6873 if (imask & (1UL << 31))
6876 for (i = 0; i < 31; ++i)
6877 if (fmask & (1UL << i))
6879 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
6880 set_mem_alias_set (mem, alpha_sr_alias_set);
6881 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
6885 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
6887 /* Restore callee-saved general-purpose registers. */
6891 for (i = 9; i < 15; i++)
6892 if (imask & (1UL << i))
6894 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
6896 set_mem_alias_set (mem, alpha_sr_alias_set);
6897 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
6901 for (i = 2; i < 10; i++)
6902 if (fmask & (1UL << i))
6904 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
6906 set_mem_alias_set (mem, alpha_sr_alias_set);
6907 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
6911 /* Restore the return address from the DSIB. */
6913 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
6914 set_mem_alias_set (mem, alpha_sr_alias_set);
6915 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
6918 if (frame_size || eh_ofs)
6920 sp_adj1 = stack_pointer_rtx;
6924 sp_adj1 = gen_rtx_REG (DImode, 23);
6925 emit_move_insn (sp_adj1,
6926 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
6929 /* If the stack size is large, begin computation into a temporary
6930 register so as not to interfere with a potential fp restore,
6931 which must be consecutive with an SP restore. */
6932 if (frame_size < 32768
6933 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
6934 sp_adj2 = GEN_INT (frame_size);
6935 else if (TARGET_ABI_UNICOSMK)
6937 sp_adj1 = gen_rtx_REG (DImode, 23);
6938 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
6939 sp_adj2 = const0_rtx;
6941 else if (frame_size < 0x40007fffL)
6943 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
6945 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
6946 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
6950 sp_adj1 = gen_rtx_REG (DImode, 23);
6951 FRP (emit_move_insn (sp_adj1, sp_adj2));
6953 sp_adj2 = GEN_INT (low);
6957 rtx tmp = gen_rtx_REG (DImode, 23);
6958 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
6961 /* We can't drop new things to memory this late, afaik,
6962 so build it up by pieces. */
6963 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
6964 -(frame_size < 0)));
6970 /* From now on, things must be in order. So emit blockages. */
6972 /* Restore the frame pointer. */
6973 if (TARGET_ABI_UNICOSMK)
6975 emit_insn (gen_blockage ());
6976 mem = gen_rtx_MEM (DImode,
6977 plus_constant (hard_frame_pointer_rtx, -16));
6978 set_mem_alias_set (mem, alpha_sr_alias_set);
6979 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
6981 else if (fp_is_frame_pointer)
6983 emit_insn (gen_blockage ());
6984 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
6985 set_mem_alias_set (mem, alpha_sr_alias_set);
6986 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
6988 else if (TARGET_ABI_OPEN_VMS)
6990 emit_insn (gen_blockage ());
6991 FRP (emit_move_insn (hard_frame_pointer_rtx,
6992 gen_rtx_REG (DImode, vms_save_fp_regno)));
6995 /* Restore the stack pointer. */
6996 emit_insn (gen_blockage ());
6997 if (sp_adj2 == const0_rtx)
6998 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7000 FRP (emit_move_insn (stack_pointer_rtx,
7001 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7005 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7007 emit_insn (gen_blockage ());
7008 FRP (emit_move_insn (hard_frame_pointer_rtx,
7009 gen_rtx_REG (DImode, vms_save_fp_regno)));
7011 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7013 /* Decrement the frame pointer if the function does not have a
7016 emit_insn (gen_blockage ());
7017 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7018 hard_frame_pointer_rtx, constm1_rtx)));
7023 /* Output the rest of the textual info surrounding the epilogue. */
7026 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7028 #if TARGET_ABI_OPEN_VMS
7029 alpha_write_linkage (file, fnname, decl);
7032 /* End the function. */
7033 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7035 fputs ("\t.end ", file);
7036 assemble_name (file, fnname);
7039 inside_function = FALSE;
7041 /* Output jump tables and the static subroutine information block. */
7042 if (TARGET_ABI_UNICOSMK)
7044 unicosmk_output_ssib (file, fnname);
7045 unicosmk_output_deferred_case_vectors (file);
7050 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7052 In order to avoid the hordes of differences between generated code
7053 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7054 lots of code loading up large constants, generate rtl and emit it
7055 instead of going straight to text.
7057 Not sure why this idea hasn't been explored before... */
7060 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7061 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7064 HOST_WIDE_INT hi, lo;
7065 rtx this, insn, funexp;
7067 reset_block_changes ();
7069 /* We always require a valid GP. */
7070 emit_insn (gen_prologue_ldgp ());
7071 emit_note (NOTE_INSN_PROLOGUE_END);
7073 /* Find the "this" pointer. If the function returns a structure,
7074 the structure return pointer is in $16. */
7075 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7076 this = gen_rtx_REG (Pmode, 17);
7078 this = gen_rtx_REG (Pmode, 16);
7080 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7081 entire constant for the add. */
7082 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7083 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7084 if (hi + lo == delta)
7087 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7089 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7093 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7094 delta, -(delta < 0));
7095 emit_insn (gen_adddi3 (this, this, tmp));
7098 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7103 tmp = gen_rtx_REG (Pmode, 0);
7104 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7106 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7107 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7108 if (hi + lo == vcall_offset)
7111 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7115 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7116 vcall_offset, -(vcall_offset < 0));
7117 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
7121 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
7124 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
7126 emit_insn (gen_adddi3 (this, this, tmp));
7129 /* Generate a tail call to the target function. */
7130 if (! TREE_USED (function))
7132 assemble_external (function);
7133 TREE_USED (function) = 1;
7135 funexp = XEXP (DECL_RTL (function), 0);
7136 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7137 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7138 SIBLING_CALL_P (insn) = 1;
7140 /* Run just enough of rest_of_compilation to get the insns emitted.
7141 There's not really enough bulk here to make other passes such as
7142 instruction scheduling worth while. Note that use_thunk calls
7143 assemble_start_function and assemble_end_function. */
7144 insn = get_insns ();
7145 insn_locators_initialize ();
7146 shorten_branches (insn);
7147 final_start_function (insn, file, 1);
7148 final (insn, file, 1, 0);
7149 final_end_function ();
7151 #endif /* TARGET_ABI_OSF */
7153 /* Debugging support. */
7157 /* Count the number of sdb related labels are generated (to find block
7158 start and end boundaries). */
7160 int sdb_label_count = 0;
7162 /* Next label # for each statement. */
7164 static int sym_lineno = 0;
7166 /* Count the number of .file directives, so that .loc is up to date. */
7168 static int num_source_filenames = 0;
7170 /* Name of the file containing the current function. */
7172 static const char *current_function_file = "";
7174 /* Offsets to alpha virtual arg/local debugging pointers. */
7176 long alpha_arg_offset;
7177 long alpha_auto_offset;
7179 /* Emit a new filename to a stream. */
7182 alpha_output_filename (FILE *stream, const char *name)
7184 static int first_time = TRUE;
7185 char ltext_label_name[100];
7190 ++num_source_filenames;
7191 current_function_file = name;
7192 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7193 output_quoted_string (stream, name);
7194 fprintf (stream, "\n");
7195 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
7196 fprintf (stream, "\t#@stabs\n");
7199 else if (write_symbols == DBX_DEBUG)
7201 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
7202 fprintf (stream, "%s", ASM_STABS_OP);
7203 output_quoted_string (stream, name);
7204 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
7207 else if (name != current_function_file
7208 && strcmp (name, current_function_file) != 0)
7210 if (inside_function && ! TARGET_GAS)
7211 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
7214 ++num_source_filenames;
7215 current_function_file = name;
7216 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7219 output_quoted_string (stream, name);
7220 fprintf (stream, "\n");
7224 /* Emit a linenumber to a stream. */
7227 alpha_output_lineno (FILE *stream, int line)
7229 if (write_symbols == DBX_DEBUG)
7231 /* mips-tfile doesn't understand .stabd directives. */
7233 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7234 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
7237 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
7240 /* Structure to show the current status of registers and memory. */
7242 struct shadow_summary
7245 unsigned int i : 31; /* Mask of int regs */
7246 unsigned int fp : 31; /* Mask of fp regs */
7247 unsigned int mem : 1; /* mem == imem | fpmem */
7251 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7252 to the summary structure. SET is nonzero if the insn is setting the
7253 object, otherwise zero. */
7256 summarize_insn (rtx x, struct shadow_summary *sum, int set)
7258 const char *format_ptr;
7264 switch (GET_CODE (x))
7266 /* ??? Note that this case would be incorrect if the Alpha had a
7267 ZERO_EXTRACT in SET_DEST. */
7269 summarize_insn (SET_SRC (x), sum, 0);
7270 summarize_insn (SET_DEST (x), sum, 1);
7274 summarize_insn (XEXP (x, 0), sum, 1);
7278 summarize_insn (XEXP (x, 0), sum, 0);
7282 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
7283 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
7287 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
7288 summarize_insn (XVECEXP (x, 0, i), sum, 0);
7292 summarize_insn (SUBREG_REG (x), sum, 0);
7297 int regno = REGNO (x);
7298 unsigned long mask = ((unsigned long) 1) << (regno % 32);
7300 if (regno == 31 || regno == 63)
7306 sum->defd.i |= mask;
7308 sum->defd.fp |= mask;
7313 sum->used.i |= mask;
7315 sum->used.fp |= mask;
7326 /* Find the regs used in memory address computation: */
7327 summarize_insn (XEXP (x, 0), sum, 0);
7330 case CONST_INT: case CONST_DOUBLE:
7331 case SYMBOL_REF: case LABEL_REF: case CONST:
7332 case SCRATCH: case ASM_INPUT:
7335 /* Handle common unary and binary ops for efficiency. */
7336 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
7337 case MOD: case UDIV: case UMOD: case AND: case IOR:
7338 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
7339 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
7340 case NE: case EQ: case GE: case GT: case LE:
7341 case LT: case GEU: case GTU: case LEU: case LTU:
7342 summarize_insn (XEXP (x, 0), sum, 0);
7343 summarize_insn (XEXP (x, 1), sum, 0);
7346 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
7347 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
7348 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
7349 case SQRT: case FFS:
7350 summarize_insn (XEXP (x, 0), sum, 0);
7354 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
7355 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7356 switch (format_ptr[i])
7359 summarize_insn (XEXP (x, i), sum, 0);
7363 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7364 summarize_insn (XVECEXP (x, i, j), sum, 0);
7376 /* Ensure a sufficient number of `trapb' insns are in the code when
7377 the user requests code with a trap precision of functions or
7380 In naive mode, when the user requests a trap-precision of
7381 "instruction", a trapb is needed after every instruction that may
7382 generate a trap. This ensures that the code is resumption safe but
7385 When optimizations are turned on, we delay issuing a trapb as long
7386 as possible. In this context, a trap shadow is the sequence of
7387 instructions that starts with a (potentially) trap generating
7388 instruction and extends to the next trapb or call_pal instruction
7389 (but GCC never generates call_pal by itself). We can delay (and
7390 therefore sometimes omit) a trapb subject to the following
7393 (a) On entry to the trap shadow, if any Alpha register or memory
7394 location contains a value that is used as an operand value by some
7395 instruction in the trap shadow (live on entry), then no instruction
7396 in the trap shadow may modify the register or memory location.
7398 (b) Within the trap shadow, the computation of the base register
7399 for a memory load or store instruction may not involve using the
7400 result of an instruction that might generate an UNPREDICTABLE
7403 (c) Within the trap shadow, no register may be used more than once
7404 as a destination register. (This is to make life easier for the
7407 (d) The trap shadow may not include any branch instructions. */
7410 alpha_handle_trap_shadows (void)
7412 struct shadow_summary shadow;
7413 int trap_pending, exception_nesting;
7417 exception_nesting = 0;
7420 shadow.used.mem = 0;
7421 shadow.defd = shadow.used;
7423 for (i = get_insns (); i ; i = NEXT_INSN (i))
7425 if (GET_CODE (i) == NOTE)
7427 switch (NOTE_LINE_NUMBER (i))
7429 case NOTE_INSN_EH_REGION_BEG:
7430 exception_nesting++;
7435 case NOTE_INSN_EH_REGION_END:
7436 exception_nesting--;
7441 case NOTE_INSN_EPILOGUE_BEG:
7442 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
7447 else if (trap_pending)
7449 if (alpha_tp == ALPHA_TP_FUNC)
7451 if (GET_CODE (i) == JUMP_INSN
7452 && GET_CODE (PATTERN (i)) == RETURN)
7455 else if (alpha_tp == ALPHA_TP_INSN)
7459 struct shadow_summary sum;
7464 sum.defd = sum.used;
7466 switch (GET_CODE (i))
7469 /* Annoyingly, get_attr_trap will abort on these. */
7470 if (GET_CODE (PATTERN (i)) == USE
7471 || GET_CODE (PATTERN (i)) == CLOBBER)
7474 summarize_insn (PATTERN (i), &sum, 0);
7476 if ((sum.defd.i & shadow.defd.i)
7477 || (sum.defd.fp & shadow.defd.fp))
7479 /* (c) would be violated */
7483 /* Combine shadow with summary of current insn: */
7484 shadow.used.i |= sum.used.i;
7485 shadow.used.fp |= sum.used.fp;
7486 shadow.used.mem |= sum.used.mem;
7487 shadow.defd.i |= sum.defd.i;
7488 shadow.defd.fp |= sum.defd.fp;
7489 shadow.defd.mem |= sum.defd.mem;
7491 if ((sum.defd.i & shadow.used.i)
7492 || (sum.defd.fp & shadow.used.fp)
7493 || (sum.defd.mem & shadow.used.mem))
7495 /* (a) would be violated (also takes care of (b)) */
7496 if (get_attr_trap (i) == TRAP_YES
7497 && ((sum.defd.i & sum.used.i)
7498 || (sum.defd.fp & sum.used.fp)))
7517 n = emit_insn_before (gen_trapb (), i);
7518 PUT_MODE (n, TImode);
7519 PUT_MODE (i, TImode);
7523 shadow.used.mem = 0;
7524 shadow.defd = shadow.used;
7529 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
7530 && GET_CODE (i) == INSN
7531 && GET_CODE (PATTERN (i)) != USE
7532 && GET_CODE (PATTERN (i)) != CLOBBER
7533 && get_attr_trap (i) == TRAP_YES)
7535 if (optimize && !trap_pending)
7536 summarize_insn (PATTERN (i), &shadow, 0);
7542 /* Alpha can only issue instruction groups simultaneously if they are
7543 suitably aligned. This is very processor-specific. */
7545 enum alphaev4_pipe {
7552 enum alphaev5_pipe {
7563 static enum alphaev4_pipe
7564 alphaev4_insn_pipe (rtx insn)
7566 if (recog_memoized (insn) < 0)
7568 if (get_attr_length (insn) != 4)
7571 switch (get_attr_type (insn))
7605 static enum alphaev5_pipe
7606 alphaev5_insn_pipe (rtx insn)
7608 if (recog_memoized (insn) < 0)
7610 if (get_attr_length (insn) != 4)
7613 switch (get_attr_type (insn))
7654 /* IN_USE is a mask of the slots currently filled within the insn group.
7655 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7656 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7658 LEN is, of course, the length of the group in bytes. */
7661 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
7668 || GET_CODE (PATTERN (insn)) == CLOBBER
7669 || GET_CODE (PATTERN (insn)) == USE)
7674 enum alphaev4_pipe pipe;
7676 pipe = alphaev4_insn_pipe (insn);
7680 /* Force complex instructions to start new groups. */
7684 /* If this is a completely unrecognized insn, its an asm.
7685 We don't know how long it is, so record length as -1 to
7686 signal a needed realignment. */
7687 if (recog_memoized (insn) < 0)
7690 len = get_attr_length (insn);
7694 if (in_use & EV4_IB0)
7696 if (in_use & EV4_IB1)
7701 in_use |= EV4_IB0 | EV4_IBX;
7705 if (in_use & EV4_IB0)
7707 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
7715 if (in_use & EV4_IB1)
7725 /* Haifa doesn't do well scheduling branches. */
7726 if (GET_CODE (insn) == JUMP_INSN)
7730 insn = next_nonnote_insn (insn);
7732 if (!insn || ! INSN_P (insn))
7735 /* Let Haifa tell us where it thinks insn group boundaries are. */
7736 if (GET_MODE (insn) == TImode)
7739 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
7744 insn = next_nonnote_insn (insn);
7752 /* IN_USE is a mask of the slots currently filled within the insn group.
7753 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7754 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7756 LEN is, of course, the length of the group in bytes. */
7759 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
7766 || GET_CODE (PATTERN (insn)) == CLOBBER
7767 || GET_CODE (PATTERN (insn)) == USE)
7772 enum alphaev5_pipe pipe;
7774 pipe = alphaev5_insn_pipe (insn);
7778 /* Force complex instructions to start new groups. */
7782 /* If this is a completely unrecognized insn, its an asm.
7783 We don't know how long it is, so record length as -1 to
7784 signal a needed realignment. */
7785 if (recog_memoized (insn) < 0)
7788 len = get_attr_length (insn);
7791 /* ??? Most of the places below, we would like to abort, as
7792 it would indicate an error either in Haifa, or in the
7793 scheduling description. Unfortunately, Haifa never
7794 schedules the last instruction of the BB, so we don't
7795 have an accurate TI bit to go off. */
7797 if (in_use & EV5_E0)
7799 if (in_use & EV5_E1)
7804 in_use |= EV5_E0 | EV5_E01;
7808 if (in_use & EV5_E0)
7810 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
7818 if (in_use & EV5_E1)
7824 if (in_use & EV5_FA)
7826 if (in_use & EV5_FM)
7831 in_use |= EV5_FA | EV5_FAM;
7835 if (in_use & EV5_FA)
7841 if (in_use & EV5_FM)
7854 /* Haifa doesn't do well scheduling branches. */
7855 /* ??? If this is predicted not-taken, slotting continues, except
7856 that no more IBR, FBR, or JSR insns may be slotted. */
7857 if (GET_CODE (insn) == JUMP_INSN)
7861 insn = next_nonnote_insn (insn);
7863 if (!insn || ! INSN_P (insn))
7866 /* Let Haifa tell us where it thinks insn group boundaries are. */
7867 if (GET_MODE (insn) == TImode)
7870 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
7875 insn = next_nonnote_insn (insn);
7884 alphaev4_next_nop (int *pin_use)
7886 int in_use = *pin_use;
7889 if (!(in_use & EV4_IB0))
7894 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
7899 else if (TARGET_FP && !(in_use & EV4_IB1))
7912 alphaev5_next_nop (int *pin_use)
7914 int in_use = *pin_use;
7917 if (!(in_use & EV5_E1))
7922 else if (TARGET_FP && !(in_use & EV5_FA))
7927 else if (TARGET_FP && !(in_use & EV5_FM))
7939 /* The instruction group alignment main loop. */
7942 alpha_align_insns (unsigned int max_align,
7943 rtx (*next_group) (rtx, int *, int *),
7944 rtx (*next_nop) (int *))
7946 /* ALIGN is the known alignment for the insn group. */
7948 /* OFS is the offset of the current insn in the insn group. */
7950 int prev_in_use, in_use, len;
7953 /* Let shorten branches care for assigning alignments to code labels. */
7954 shorten_branches (get_insns ());
7956 if (align_functions < 4)
7958 else if ((unsigned int) align_functions < max_align)
7959 align = align_functions;
7963 ofs = prev_in_use = 0;
7965 if (GET_CODE (i) == NOTE)
7966 i = next_nonnote_insn (i);
7970 next = (*next_group) (i, &in_use, &len);
7972 /* When we see a label, resync alignment etc. */
7973 if (GET_CODE (i) == CODE_LABEL)
7975 unsigned int new_align = 1 << label_to_alignment (i);
7977 if (new_align >= align)
7979 align = new_align < max_align ? new_align : max_align;
7983 else if (ofs & (new_align-1))
7984 ofs = (ofs | (new_align-1)) + 1;
7989 /* Handle complex instructions special. */
7990 else if (in_use == 0)
7992 /* Asms will have length < 0. This is a signal that we have
7993 lost alignment knowledge. Assume, however, that the asm
7994 will not mis-align instructions. */
8003 /* If the known alignment is smaller than the recognized insn group,
8004 realign the output. */
8005 else if ((int) align < len)
8007 unsigned int new_log_align = len > 8 ? 4 : 3;
8010 where = prev = prev_nonnote_insn (i);
8011 if (!where || GET_CODE (where) != CODE_LABEL)
8014 /* Can't realign between a call and its gp reload. */
8015 if (! (TARGET_EXPLICIT_RELOCS
8016 && prev && GET_CODE (prev) == CALL_INSN))
8018 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8019 align = 1 << new_log_align;
8024 /* If the group won't fit in the same INT16 as the previous,
8025 we need to add padding to keep the group together. Rather
8026 than simply leaving the insn filling to the assembler, we
8027 can make use of the knowledge of what sorts of instructions
8028 were issued in the previous group to make sure that all of
8029 the added nops are really free. */
8030 else if (ofs + len > (int) align)
8032 int nop_count = (align - ofs) / 4;
8035 /* Insert nops before labels, branches, and calls to truly merge
8036 the execution of the nops with the previous instruction group. */
8037 where = prev_nonnote_insn (i);
8040 if (GET_CODE (where) == CODE_LABEL)
8042 rtx where2 = prev_nonnote_insn (where);
8043 if (where2 && GET_CODE (where2) == JUMP_INSN)
8046 else if (GET_CODE (where) == INSN)
8053 emit_insn_before ((*next_nop)(&prev_in_use), where);
8054 while (--nop_count);
8058 ofs = (ofs + len) & (align - 1);
8059 prev_in_use = in_use;
8064 /* Machine dependent reorg pass. */
8069 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8070 alpha_handle_trap_shadows ();
8072 /* Due to the number of extra trapb insns, don't bother fixing up
8073 alignment when trap precision is instruction. Moreover, we can
8074 only do our job when sched2 is run. */
8075 if (optimize && !optimize_size
8076 && alpha_tp != ALPHA_TP_INSN
8077 && flag_schedule_insns_after_reload)
8079 if (alpha_cpu == PROCESSOR_EV4)
8080 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8081 else if (alpha_cpu == PROCESSOR_EV5)
8082 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8086 #if !TARGET_ABI_UNICOSMK
8093 alpha_file_start (void)
8095 #ifdef OBJECT_FORMAT_ELF
8096 /* If emitting dwarf2 debug information, we cannot generate a .file
8097 directive to start the file, as it will conflict with dwarf2out
8098 file numbers. So it's only useful when emitting mdebug output. */
8099 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8102 default_file_start ();
8104 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8107 fputs ("\t.set noreorder\n", asm_out_file);
8108 fputs ("\t.set volatile\n", asm_out_file);
8109 if (!TARGET_ABI_OPEN_VMS)
8110 fputs ("\t.set noat\n", asm_out_file);
8111 if (TARGET_EXPLICIT_RELOCS)
8112 fputs ("\t.set nomacro\n", asm_out_file);
8113 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
8114 fprintf (asm_out_file,
8116 TARGET_CPU_EV6 ? "ev6"
8118 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
8123 #ifdef OBJECT_FORMAT_ELF
8125 /* Switch to the section to which we should output X. The only thing
8126 special we do here is to honor small data. */
8129 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
8130 unsigned HOST_WIDE_INT align)
8132 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8133 /* ??? Consider using mergeable sdata sections. */
8136 default_elf_select_rtx_section (mode, x, align);
8139 #endif /* OBJECT_FORMAT_ELF */
8141 /* Structure to collect function names for final output in link section. */
8142 /* Note that items marked with GTY can't be ifdef'ed out. */
8144 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
8145 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
8147 struct alpha_links GTY(())
8151 enum links_kind lkind;
8152 enum reloc_kind rkind;
8155 struct alpha_funcs GTY(())
8158 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8162 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8163 splay_tree alpha_links_tree;
8164 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
8165 splay_tree alpha_funcs_tree;
8167 static GTY(()) int alpha_funcs_num;
8169 #if TARGET_ABI_OPEN_VMS
8171 /* Return the VMS argument type corresponding to MODE. */
8174 alpha_arg_type (enum machine_mode mode)
8179 return TARGET_FLOAT_VAX ? FF : FS;
8181 return TARGET_FLOAT_VAX ? FD : FT;
8187 /* Return an rtx for an integer representing the VMS Argument Information
8191 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
8193 unsigned HOST_WIDE_INT regval = cum.num_args;
8196 for (i = 0; i < 6; i++)
8197 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
8199 return GEN_INT (regval);
8202 /* Make (or fake) .linkage entry for function call.
8204 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8206 Return an SYMBOL_REF rtx for the linkage. */
8209 alpha_need_linkage (const char *name, int is_local)
8211 splay_tree_node node;
8212 struct alpha_links *al;
8219 struct alpha_funcs *cfaf;
8221 if (!alpha_funcs_tree)
8222 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
8223 splay_tree_compare_pointers);
8225 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
8228 cfaf->num = ++alpha_funcs_num;
8230 splay_tree_insert (alpha_funcs_tree,
8231 (splay_tree_key) current_function_decl,
8232 (splay_tree_value) cfaf);
8235 if (alpha_links_tree)
8237 /* Is this name already defined? */
8239 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
8242 al = (struct alpha_links *) node->value;
8245 /* Defined here but external assumed. */
8246 if (al->lkind == KIND_EXTERN)
8247 al->lkind = KIND_LOCAL;
8251 /* Used here but unused assumed. */
8252 if (al->lkind == KIND_UNUSED)
8253 al->lkind = KIND_LOCAL;
8259 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
8261 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
8262 name = ggc_strdup (name);
8264 /* Assume external if no definition. */
8265 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
8267 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8268 get_identifier (name);
8270 /* Construct a SYMBOL_REF for us to call. */
8272 size_t name_len = strlen (name);
8273 char *linksym = alloca (name_len + 6);
8275 memcpy (linksym + 1, name, name_len);
8276 memcpy (linksym + 1 + name_len, "..lk", 5);
8277 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
8278 ggc_alloc_string (linksym, name_len + 5));
8281 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
8282 (splay_tree_value) al);
8288 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
8290 splay_tree_node cfunnode;
8291 struct alpha_funcs *cfaf;
8292 struct alpha_links *al;
8293 const char *name = XSTR (linkage, 0);
8295 cfaf = (struct alpha_funcs *) 0;
8296 al = (struct alpha_links *) 0;
8298 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
8299 cfaf = (struct alpha_funcs *) cfunnode->value;
8303 splay_tree_node lnode;
8305 /* Is this name already defined? */
8307 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
8309 al = (struct alpha_links *) lnode->value;
8312 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
8320 splay_tree_node node = 0;
8321 struct alpha_links *anl;
8326 name_len = strlen (name);
8328 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
8329 al->num = cfaf->num;
8331 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
8334 anl = (struct alpha_links *) node->value;
8335 al->lkind = anl->lkind;
8338 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
8339 buflen = strlen (buf);
8340 linksym = alloca (buflen + 1);
8341 memcpy (linksym, buf, buflen + 1);
8343 al->linkage = gen_rtx_SYMBOL_REF
8344 (Pmode, ggc_alloc_string (linksym, buflen + 1));
8346 splay_tree_insert (cfaf->links, (splay_tree_key) name,
8347 (splay_tree_value) al);
8351 al->rkind = KIND_CODEADDR;
8353 al->rkind = KIND_LINKAGE;
8356 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
8362 alpha_write_one_linkage (splay_tree_node node, void *data)
8364 const char *const name = (const char *) node->key;
8365 struct alpha_links *link = (struct alpha_links *) node->value;
8366 FILE *stream = (FILE *) data;
8368 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
8369 if (link->rkind == KIND_CODEADDR)
8371 if (link->lkind == KIND_LOCAL)
8373 /* Local and used */
8374 fprintf (stream, "\t.quad %s..en\n", name);
8378 /* External and used, request code address. */
8379 fprintf (stream, "\t.code_address %s\n", name);
8384 if (link->lkind == KIND_LOCAL)
8386 /* Local and used, build linkage pair. */
8387 fprintf (stream, "\t.quad %s..en\n", name);
8388 fprintf (stream, "\t.quad %s\n", name);
8392 /* External and used, request linkage pair. */
8393 fprintf (stream, "\t.linkage %s\n", name);
8401 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
8403 splay_tree_node node;
8404 struct alpha_funcs *func;
8407 fprintf (stream, "\t.align 3\n");
8408 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
8409 func = (struct alpha_funcs *) node->value;
8411 fputs ("\t.name ", stream);
8412 assemble_name (stream, funname);
8413 fputs ("..na\n", stream);
8414 ASM_OUTPUT_LABEL (stream, funname);
8415 fprintf (stream, "\t.pdesc ");
8416 assemble_name (stream, funname);
8417 fprintf (stream, "..en,%s\n",
8418 alpha_procedure_type == PT_STACK ? "stack"
8419 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
8423 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
8424 /* splay_tree_delete (func->links); */
8428 /* Given a decl, a section name, and whether the decl initializer
8429 has relocs, choose attributes for the section. */
8431 #define SECTION_VMS_OVERLAY SECTION_FORGET
8432 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8433 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8436 vms_section_type_flags (tree decl, const char *name, int reloc)
8438 unsigned int flags = default_section_type_flags (decl, name, reloc);
8440 if (decl && DECL_ATTRIBUTES (decl)
8441 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
8442 flags |= SECTION_VMS_OVERLAY;
8443 if (decl && DECL_ATTRIBUTES (decl)
8444 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
8445 flags |= SECTION_VMS_GLOBAL;
8446 if (decl && DECL_ATTRIBUTES (decl)
8447 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
8448 flags |= SECTION_VMS_INITIALIZE;
8453 /* Switch to an arbitrary section NAME with attributes as specified
8454 by FLAGS. ALIGN specifies any known alignment requirements for
8455 the section; 0 if the default should be used. */
8458 vms_asm_named_section (const char *name, unsigned int flags,
8459 tree decl ATTRIBUTE_UNUSED)
8461 fputc ('\n', asm_out_file);
8462 fprintf (asm_out_file, ".section\t%s", name);
8464 if (flags & SECTION_VMS_OVERLAY)
8465 fprintf (asm_out_file, ",OVR");
8466 if (flags & SECTION_VMS_GLOBAL)
8467 fprintf (asm_out_file, ",GBL");
8468 if (flags & SECTION_VMS_INITIALIZE)
8469 fprintf (asm_out_file, ",NOMOD");
8470 if (flags & SECTION_DEBUG)
8471 fprintf (asm_out_file, ",NOWRT");
8473 fputc ('\n', asm_out_file);
8476 /* Record an element in the table of global constructors. SYMBOL is
8477 a SYMBOL_REF of the function to be called; PRIORITY is a number
8478 between 0 and MAX_INIT_PRIORITY.
8480 Differs from default_ctors_section_asm_out_constructor in that the
8481 width of the .ctors entry is always 64 bits, rather than the 32 bits
8482 used by a normal pointer. */
8485 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
8488 assemble_align (BITS_PER_WORD);
8489 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
8493 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
8496 assemble_align (BITS_PER_WORD);
8497 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
8502 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
8503 int is_local ATTRIBUTE_UNUSED)
8509 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
8510 tree cfundecl ATTRIBUTE_UNUSED,
8511 int lflag ATTRIBUTE_UNUSED,
8512 int rflag ATTRIBUTE_UNUSED)
8517 #endif /* TARGET_ABI_OPEN_VMS */
8519 #if TARGET_ABI_UNICOSMK
8521 /* This evaluates to true if we do not know how to pass TYPE solely in
8522 registers. This is the case for all arguments that do not fit in two
8526 unicosmk_must_pass_in_stack (enum machine_mode mode, tree type)
8531 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
8533 if (TREE_ADDRESSABLE (type))
8536 return ALPHA_ARG_SIZE (mode, type, 0) > 2;
8539 /* Define the offset between two registers, one to be eliminated, and the
8540 other its replacement, at the start of a routine. */
8543 unicosmk_initial_elimination_offset (int from, int to)
8547 fixed_size = alpha_sa_size();
8548 if (fixed_size != 0)
8551 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8553 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8555 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8556 return (ALPHA_ROUND (current_function_outgoing_args_size)
8557 + ALPHA_ROUND (get_frame_size()));
8558 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8559 return (ALPHA_ROUND (fixed_size)
8560 + ALPHA_ROUND (get_frame_size()
8561 + current_function_outgoing_args_size));
8566 /* Output the module name for .ident and .end directives. We have to strip
8567 directories and add make sure that the module name starts with a letter
8571 unicosmk_output_module_name (FILE *file)
8573 const char *name = lbasename (main_input_filename);
8574 unsigned len = strlen (name);
8575 char *clean_name = alloca (len + 2);
8576 char *ptr = clean_name;
8578 /* CAM only accepts module names that start with a letter or '$'. We
8579 prefix the module name with a '$' if necessary. */
8581 if (!ISALPHA (*name))
8583 memcpy (ptr, name, len + 1);
8584 clean_symbol_name (clean_name);
8585 fputs (clean_name, file);
8588 /* Output the definition of a common variable. */
8591 unicosmk_output_common (FILE *file, const char *name, int size, int align)
8594 printf ("T3E__: common %s\n", name);
8597 fputs("\t.endp\n\n\t.psect ", file);
8598 assemble_name(file, name);
8599 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
8600 fprintf(file, "\t.byte\t0:%d\n", size);
8602 /* Mark the symbol as defined in this module. */
8603 name_tree = get_identifier (name);
8604 TREE_ASM_WRITTEN (name_tree) = 1;
8607 #define SECTION_PUBLIC SECTION_MACH_DEP
8608 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8609 static int current_section_align;
8612 unicosmk_section_type_flags (tree decl, const char *name,
8613 int reloc ATTRIBUTE_UNUSED)
8615 unsigned int flags = default_section_type_flags (decl, name, reloc);
8620 if (TREE_CODE (decl) == FUNCTION_DECL)
8622 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8623 if (align_functions_log > current_section_align)
8624 current_section_align = align_functions_log;
8626 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
8627 flags |= SECTION_MAIN;
8630 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
8632 if (TREE_PUBLIC (decl))
8633 flags |= SECTION_PUBLIC;
8638 /* Generate a section name for decl and associate it with the
8642 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
8650 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
8651 name = default_strip_name_encoding (name);
8652 len = strlen (name);
8654 if (TREE_CODE (decl) == FUNCTION_DECL)
8658 /* It is essential that we prefix the section name here because
8659 otherwise the section names generated for constructors and
8660 destructors confuse collect2. */
8662 string = alloca (len + 6);
8663 sprintf (string, "code@%s", name);
8664 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
8666 else if (TREE_PUBLIC (decl))
8667 DECL_SECTION_NAME (decl) = build_string (len, name);
8672 string = alloca (len + 6);
8673 sprintf (string, "data@%s", name);
8674 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
8678 /* Switch to an arbitrary section NAME with attributes as specified
8679 by FLAGS. ALIGN specifies any known alignment requirements for
8680 the section; 0 if the default should be used. */
8683 unicosmk_asm_named_section (const char *name, unsigned int flags,
8684 tree decl ATTRIBUTE_UNUSED)
8688 /* Close the previous section. */
8690 fputs ("\t.endp\n\n", asm_out_file);
8692 /* Find out what kind of section we are opening. */
8694 if (flags & SECTION_MAIN)
8695 fputs ("\t.start\tmain\n", asm_out_file);
8697 if (flags & SECTION_CODE)
8699 else if (flags & SECTION_PUBLIC)
8704 if (current_section_align != 0)
8705 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
8706 current_section_align, kind);
8708 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
8712 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
8715 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
8716 unicosmk_unique_section (decl, 0);
8719 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8720 in code sections because .align fill unused space with zeroes. */
8723 unicosmk_output_align (FILE *file, int align)
8725 if (inside_function)
8726 fprintf (file, "\tgcc@code@align\t%d\n", align);
8728 fprintf (file, "\t.align\t%d\n", align);
8731 /* Add a case vector to the current function's list of deferred case
8732 vectors. Case vectors have to be put into a separate section because CAM
8733 does not allow data definitions in code sections. */
8736 unicosmk_defer_case_vector (rtx lab, rtx vec)
8738 struct machine_function *machine = cfun->machine;
8740 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8741 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
8742 machine->addr_list);
8745 /* Output a case vector. */
8748 unicosmk_output_addr_vec (FILE *file, rtx vec)
8750 rtx lab = XEXP (vec, 0);
8751 rtx body = XEXP (vec, 1);
8752 int vlen = XVECLEN (body, 0);
8755 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
8757 for (idx = 0; idx < vlen; idx++)
8759 ASM_OUTPUT_ADDR_VEC_ELT
8760 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8764 /* Output current function's deferred case vectors. */
8767 unicosmk_output_deferred_case_vectors (FILE *file)
8769 struct machine_function *machine = cfun->machine;
8772 if (machine->addr_list == NULL_RTX)
8776 for (t = machine->addr_list; t; t = XEXP (t, 1))
8777 unicosmk_output_addr_vec (file, XEXP (t, 0));
8780 /* Generate the name of the SSIB section for the current function. */
8782 #define SSIB_PREFIX "__SSIB_"
8783 #define SSIB_PREFIX_LEN 7
8786 unicosmk_ssib_name (void)
8788 /* This is ok since CAM won't be able to deal with names longer than that
8791 static char name[256];
8797 x = DECL_RTL (cfun->decl);
8798 if (GET_CODE (x) != MEM)
8801 if (GET_CODE (x) != SYMBOL_REF)
8803 fnname = XSTR (x, 0);
8805 len = strlen (fnname);
8806 if (len + SSIB_PREFIX_LEN > 255)
8807 len = 255 - SSIB_PREFIX_LEN;
8809 strcpy (name, SSIB_PREFIX);
8810 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
8811 name[len + SSIB_PREFIX_LEN] = 0;
8816 /* Set up the dynamic subprogram information block (DSIB) and update the
8817 frame pointer register ($15) for subroutines which have a frame. If the
8818 subroutine doesn't have a frame, simply increment $15. */
8821 unicosmk_gen_dsib (unsigned long *imaskP)
8823 if (alpha_procedure_type == PT_STACK)
8825 const char *ssib_name;
8828 /* Allocate 64 bytes for the DSIB. */
8830 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
8832 emit_insn (gen_blockage ());
8834 /* Save the return address. */
8836 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
8837 set_mem_alias_set (mem, alpha_sr_alias_set);
8838 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
8839 (*imaskP) &= ~(1UL << REG_RA);
8841 /* Save the old frame pointer. */
8843 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
8844 set_mem_alias_set (mem, alpha_sr_alias_set);
8845 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
8846 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
8848 emit_insn (gen_blockage ());
8850 /* Store the SSIB pointer. */
8852 ssib_name = ggc_strdup (unicosmk_ssib_name ());
8853 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
8854 set_mem_alias_set (mem, alpha_sr_alias_set);
8856 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
8857 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
8858 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
8860 /* Save the CIW index. */
8862 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
8863 set_mem_alias_set (mem, alpha_sr_alias_set);
8864 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
8866 emit_insn (gen_blockage ());
8868 /* Set the new frame pointer. */
8870 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8871 stack_pointer_rtx, GEN_INT (64))));
8876 /* Increment the frame pointer register to indicate that we do not
8879 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8880 hard_frame_pointer_rtx, const1_rtx)));
8884 /* Output the static subroutine information block for the current
8888 unicosmk_output_ssib (FILE *file, const char *fnname)
8894 struct machine_function *machine = cfun->machine;
8897 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
8898 unicosmk_ssib_name ());
8900 /* Some required stuff and the function name length. */
8902 len = strlen (fnname);
8903 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
8906 ??? We don't do that yet. */
8908 fputs ("\t.quad\t0\n", file);
8910 /* Function address. */
8912 fputs ("\t.quad\t", file);
8913 assemble_name (file, fnname);
8916 fputs ("\t.quad\t0\n", file);
8917 fputs ("\t.quad\t0\n", file);
8920 ??? We do it the same way Cray CC does it but this could be
8923 for( i = 0; i < len; i++ )
8924 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
8925 if( (len % 8) == 0 )
8926 fputs ("\t.quad\t0\n", file);
8928 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
8930 /* All call information words used in the function. */
8932 for (x = machine->first_ciw; x; x = XEXP (x, 1))
8935 #if HOST_BITS_PER_WIDE_INT == 32
8936 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
8937 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
8939 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
8944 /* Add a call information word (CIW) to the list of the current function's
8945 CIWs and return its index.
8947 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8950 unicosmk_add_call_info_word (rtx x)
8953 struct machine_function *machine = cfun->machine;
8955 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
8956 if (machine->first_ciw == NULL_RTX)
8957 machine->first_ciw = node;
8959 XEXP (machine->last_ciw, 1) = node;
8961 machine->last_ciw = node;
8962 ++machine->ciw_count;
8964 return GEN_INT (machine->ciw_count
8965 + strlen (current_function_name ())/8 + 5);
8968 static char unicosmk_section_buf[100];
8971 unicosmk_text_section (void)
8973 static int count = 0;
8974 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
8976 return unicosmk_section_buf;
8980 unicosmk_data_section (void)
8982 static int count = 1;
8983 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
8985 return unicosmk_section_buf;
8988 /* The Cray assembler doesn't accept extern declarations for symbols which
8989 are defined in the same file. We have to keep track of all global
8990 symbols which are referenced and/or defined in a source file and output
8991 extern declarations for those which are referenced but not defined at
8994 /* List of identifiers for which an extern declaration might have to be
8996 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
8998 struct unicosmk_extern_list
9000 struct unicosmk_extern_list *next;
9004 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9006 /* Output extern declarations which are required for every asm file. */
9009 unicosmk_output_default_externs (FILE *file)
9011 static const char *const externs[] =
9012 { "__T3E_MISMATCH" };
9017 n = ARRAY_SIZE (externs);
9019 for (i = 0; i < n; i++)
9020 fprintf (file, "\t.extern\t%s\n", externs[i]);
9023 /* Output extern declarations for global symbols which are have been
9024 referenced but not defined. */
9027 unicosmk_output_externs (FILE *file)
9029 struct unicosmk_extern_list *p;
9030 const char *real_name;
9034 len = strlen (user_label_prefix);
9035 for (p = unicosmk_extern_head; p != 0; p = p->next)
9037 /* We have to strip the encoding and possibly remove user_label_prefix
9038 from the identifier in order to handle -fleading-underscore and
9039 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9040 real_name = default_strip_name_encoding (p->name);
9041 if (len && p->name[0] == '*'
9042 && !memcmp (real_name, user_label_prefix, len))
9045 name_tree = get_identifier (real_name);
9046 if (! TREE_ASM_WRITTEN (name_tree))
9048 TREE_ASM_WRITTEN (name_tree) = 1;
9049 fputs ("\t.extern\t", file);
9050 assemble_name (file, p->name);
9056 /* Record an extern. */
9059 unicosmk_add_extern (const char *name)
9061 struct unicosmk_extern_list *p;
9063 p = (struct unicosmk_extern_list *)
9064 xmalloc (sizeof (struct unicosmk_extern_list));
9065 p->next = unicosmk_extern_head;
9067 unicosmk_extern_head = p;
9070 /* The Cray assembler generates incorrect code if identifiers which
9071 conflict with register names are used as instruction operands. We have
9072 to replace such identifiers with DEX expressions. */
9074 /* Structure to collect identifiers which have been replaced by DEX
9076 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9078 struct unicosmk_dex {
9079 struct unicosmk_dex *next;
9083 /* List of identifiers which have been replaced by DEX expressions. The DEX
9084 number is determined by the position in the list. */
9086 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9088 /* The number of elements in the DEX list. */
9090 static int unicosmk_dex_count = 0;
9092 /* Check if NAME must be replaced by a DEX expression. */
9095 unicosmk_special_name (const char *name)
9103 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9109 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9112 return (name[2] == '\0'
9113 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9116 return (ISDIGIT (name[1]) && name[2] == '\0');
9120 /* Return the DEX number if X must be replaced by a DEX expression and 0
9124 unicosmk_need_dex (rtx x)
9126 struct unicosmk_dex *dex;
9130 if (GET_CODE (x) != SYMBOL_REF)
9134 if (! unicosmk_special_name (name))
9137 i = unicosmk_dex_count;
9138 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9140 if (! strcmp (name, dex->name))
9145 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
9147 dex->next = unicosmk_dex_list;
9148 unicosmk_dex_list = dex;
9150 ++unicosmk_dex_count;
9151 return unicosmk_dex_count;
9154 /* Output the DEX definitions for this file. */
9157 unicosmk_output_dex (FILE *file)
9159 struct unicosmk_dex *dex;
9162 if (unicosmk_dex_list == NULL)
9165 fprintf (file, "\t.dexstart\n");
9167 i = unicosmk_dex_count;
9168 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9170 fprintf (file, "\tDEX (%d) = ", i);
9171 assemble_name (file, dex->name);
9176 fprintf (file, "\t.dexend\n");
9179 /* Output text that to appear at the beginning of an assembler file. */
9182 unicosmk_file_start (void)
9186 fputs ("\t.ident\t", asm_out_file);
9187 unicosmk_output_module_name (asm_out_file);
9188 fputs ("\n\n", asm_out_file);
9190 /* The Unicos/Mk assembler uses different register names. Instead of trying
9191 to support them, we simply use micro definitions. */
9193 /* CAM has different register names: rN for the integer register N and fN
9194 for the floating-point register N. Instead of trying to use these in
9195 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9198 for (i = 0; i < 32; ++i)
9199 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
9201 for (i = 0; i < 32; ++i)
9202 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
9204 putc ('\n', asm_out_file);
9206 /* The .align directive fill unused space with zeroes which does not work
9207 in code sections. We define the macro 'gcc@code@align' which uses nops
9208 instead. Note that it assumes that code sections always have the
9209 biggest possible alignment since . refers to the current offset from
9210 the beginning of the section. */
9212 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
9213 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
9214 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
9215 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
9216 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
9217 fputs ("\tbis r31,r31,r31\n", asm_out_file);
9218 fputs ("\t.endr\n", asm_out_file);
9219 fputs ("\t.endif\n", asm_out_file);
9220 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
9222 /* Output extern declarations which should always be visible. */
9223 unicosmk_output_default_externs (asm_out_file);
9225 /* Open a dummy section. We always need to be inside a section for the
9226 section-switching code to work correctly.
9227 ??? This should be a module id or something like that. I still have to
9228 figure out what the rules for those are. */
9229 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
9232 /* Output text to appear at the end of an assembler file. This includes all
9233 pending extern declarations and DEX expressions. */
9236 unicosmk_file_end (void)
9238 fputs ("\t.endp\n\n", asm_out_file);
9240 /* Output all pending externs. */
9242 unicosmk_output_externs (asm_out_file);
9244 /* Output dex definitions used for functions whose names conflict with
9247 unicosmk_output_dex (asm_out_file);
9249 fputs ("\t.end\t", asm_out_file);
9250 unicosmk_output_module_name (asm_out_file);
9251 putc ('\n', asm_out_file);
9257 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
9261 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
9265 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
9266 const char * fnname ATTRIBUTE_UNUSED)
9270 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
9276 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
9281 #endif /* TARGET_ABI_UNICOSMK */
9284 alpha_init_libfuncs (void)
9286 if (TARGET_ABI_UNICOSMK)
9288 /* Prevent gcc from generating calls to __divsi3. */
9289 set_optab_libfunc (sdiv_optab, SImode, 0);
9290 set_optab_libfunc (udiv_optab, SImode, 0);
9292 /* Use the functions provided by the system library
9293 for DImode integer division. */
9294 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
9295 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
9297 else if (TARGET_ABI_OPEN_VMS)
9299 /* Use the VMS runtime library functions for division and
9301 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
9302 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
9303 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
9304 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
9305 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
9306 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
9307 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
9308 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
9313 /* Initialize the GCC target structure. */
9314 #if TARGET_ABI_OPEN_VMS
9315 # undef TARGET_ATTRIBUTE_TABLE
9316 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
9317 # undef TARGET_SECTION_TYPE_FLAGS
9318 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
9321 #undef TARGET_IN_SMALL_DATA_P
9322 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
9324 #if TARGET_ABI_UNICOSMK
9325 # undef TARGET_INSERT_ATTRIBUTES
9326 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
9327 # undef TARGET_SECTION_TYPE_FLAGS
9328 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
9329 # undef TARGET_ASM_UNIQUE_SECTION
9330 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
9331 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
9332 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
9333 # undef TARGET_ASM_GLOBALIZE_LABEL
9334 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
9335 # undef TARGET_MUST_PASS_IN_STACK
9336 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
9339 #undef TARGET_ASM_ALIGNED_HI_OP
9340 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9341 #undef TARGET_ASM_ALIGNED_DI_OP
9342 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9344 /* Default unaligned ops are provided for ELF systems. To get unaligned
9345 data for non-ELF systems, we have to turn off auto alignment. */
9346 #ifndef OBJECT_FORMAT_ELF
9347 #undef TARGET_ASM_UNALIGNED_HI_OP
9348 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
9349 #undef TARGET_ASM_UNALIGNED_SI_OP
9350 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
9351 #undef TARGET_ASM_UNALIGNED_DI_OP
9352 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
9355 #ifdef OBJECT_FORMAT_ELF
9356 #undef TARGET_ASM_SELECT_RTX_SECTION
9357 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
9360 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
9361 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
9363 #undef TARGET_INIT_LIBFUNCS
9364 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
9366 #if TARGET_ABI_UNICOSMK
9367 #undef TARGET_ASM_FILE_START
9368 #define TARGET_ASM_FILE_START unicosmk_file_start
9369 #undef TARGET_ASM_FILE_END
9370 #define TARGET_ASM_FILE_END unicosmk_file_end
9372 #undef TARGET_ASM_FILE_START
9373 #define TARGET_ASM_FILE_START alpha_file_start
9374 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
9375 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
9378 #undef TARGET_SCHED_ADJUST_COST
9379 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
9380 #undef TARGET_SCHED_ISSUE_RATE
9381 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
9382 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9383 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
9384 alpha_multipass_dfa_lookahead
9386 #undef TARGET_HAVE_TLS
9387 #define TARGET_HAVE_TLS HAVE_AS_TLS
9389 #undef TARGET_INIT_BUILTINS
9390 #define TARGET_INIT_BUILTINS alpha_init_builtins
9391 #undef TARGET_EXPAND_BUILTIN
9392 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
9394 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9395 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
9396 #undef TARGET_CANNOT_COPY_INSN_P
9397 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
9398 #undef TARGET_CANNOT_FORCE_CONST_MEM
9399 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
9402 #undef TARGET_ASM_OUTPUT_MI_THUNK
9403 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
9404 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9405 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9408 #undef TARGET_RTX_COSTS
9409 #define TARGET_RTX_COSTS alpha_rtx_costs
9410 #undef TARGET_ADDRESS_COST
9411 #define TARGET_ADDRESS_COST hook_int_rtx_0
9413 #undef TARGET_MACHINE_DEPENDENT_REORG
9414 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
9416 #undef TARGET_PROMOTE_FUNCTION_ARGS
9417 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9418 #undef TARGET_PROMOTE_FUNCTION_RETURN
9419 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9420 #undef TARGET_PROMOTE_PROTOTYPES
9421 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
9422 #undef TARGET_RETURN_IN_MEMORY
9423 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
9424 #undef TARGET_PASS_BY_REFERENCE
9425 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
9426 #undef TARGET_SETUP_INCOMING_VARARGS
9427 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
9428 #undef TARGET_STRICT_ARGUMENT_NAMING
9429 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
9430 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
9431 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
9432 #undef TARGET_SPLIT_COMPLEX_ARG
9433 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
9434 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9435 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
9437 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9438 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
9439 #undef TARGET_VECTOR_MODE_SUPPORTED_P
9440 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
9442 #undef TARGET_BUILD_BUILTIN_VA_LIST
9443 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
9445 struct gcc_target targetm = TARGET_INITIALIZER;
9448 #include "gt-alpha.h"