1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
84 #include "hard-reg-set.h"
85 #include "basic-block.h"
86 #include "insn-config.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-flags.h"
91 #include "insn-codes.h"
92 #include "insn-attr.h"
98 #ifndef ACCUMULATE_OUTGOING_ARGS
99 #define ACCUMULATE_OUTGOING_ARGS 0
102 /* Supply a default definition for PUSH_ARGS. */
105 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
111 /* It is not safe to use ordinary gen_lowpart in combine.
112 Use gen_lowpart_for_combine instead. See comments there. */
113 #define gen_lowpart dont_use_gen_lowpart_you_dummy
115 /* Number of attempts to combine instructions in this function. */
117 static int combine_attempts;
119 /* Number of attempts that got as far as substitution in this function. */
121 static int combine_merges;
123 /* Number of instructions combined with added SETs in this function. */
125 static int combine_extras;
127 /* Number of instructions combined in this function. */
129 static int combine_successes;
131 /* Totals over entire compilation. */
133 static int total_attempts, total_merges, total_extras, total_successes;
135 /* Define a default value for REVERSIBLE_CC_MODE.
136 We can never assume that a condition code mode is safe to reverse unless
137 the md tells us so. */
138 #ifndef REVERSIBLE_CC_MODE
139 #define REVERSIBLE_CC_MODE(MODE) 0
142 /* Vector mapping INSN_UIDs to cuids.
143 The cuids are like uids but increase monotonically always.
144 Combine always uses cuids so that it can compare them.
145 But actually renumbering the uids, which we used to do,
146 proves to be a bad idea because it makes it hard to compare
147 the dumps produced by earlier passes with those from later passes. */
149 static int *uid_cuid;
150 static int max_uid_cuid;
152 /* Get the cuid of an insn. */
154 #define INSN_CUID(INSN) \
155 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
157 /* Maximum register number, which is the size of the tables below. */
159 static unsigned int combine_max_regno;
161 /* Record last point of death of (hard or pseudo) register n. */
163 static rtx *reg_last_death;
165 /* Record last point of modification of (hard or pseudo) register n. */
167 static rtx *reg_last_set;
169 /* Record the cuid of the last insn that invalidated memory
170 (anything that writes memory, and subroutine calls, but not pushes). */
172 static int mem_last_set;
174 /* Record the cuid of the last CALL_INSN
175 so we can tell whether a potential combination crosses any calls. */
177 static int last_call_cuid;
179 /* When `subst' is called, this is the insn that is being modified
180 (by combining in a previous insn). The PATTERN of this insn
181 is still the old pattern partially modified and it should not be
182 looked at, but this may be used to examine the successors of the insn
183 to judge whether a simplification is valid. */
185 static rtx subst_insn;
187 /* This is an insn that belongs before subst_insn, but is not currently
188 on the insn chain. */
190 static rtx subst_prev_insn;
192 /* This is the lowest CUID that `subst' is currently dealing with.
193 get_last_value will not return a value if the register was set at or
194 after this CUID. If not for this mechanism, we could get confused if
195 I2 or I1 in try_combine were an insn that used the old value of a register
196 to obtain a new value. In that case, we might erroneously get the
197 new value of the register when we wanted the old one. */
199 static int subst_low_cuid;
201 /* This contains any hard registers that are used in newpat; reg_dead_at_p
202 must consider all these registers to be always live. */
204 static HARD_REG_SET newpat_used_regs;
206 /* This is an insn to which a LOG_LINKS entry has been added. If this
207 insn is the earlier than I2 or I3, combine should rescan starting at
210 static rtx added_links_insn;
212 /* Basic block number of the block in which we are performing combines. */
213 static int this_basic_block;
215 /* A bitmap indicating which blocks had registers go dead at entry.
216 After combine, we'll need to re-do global life analysis with
217 those blocks as starting points. */
218 static sbitmap refresh_blocks;
219 static int need_refresh;
221 /* The next group of arrays allows the recording of the last value assigned
222 to (hard or pseudo) register n. We use this information to see if a
223 operation being processed is redundant given a prior operation performed
224 on the register. For example, an `and' with a constant is redundant if
225 all the zero bits are already known to be turned off.
227 We use an approach similar to that used by cse, but change it in the
230 (1) We do not want to reinitialize at each label.
231 (2) It is useful, but not critical, to know the actual value assigned
232 to a register. Often just its form is helpful.
234 Therefore, we maintain the following arrays:
236 reg_last_set_value the last value assigned
237 reg_last_set_label records the value of label_tick when the
238 register was assigned
239 reg_last_set_table_tick records the value of label_tick when a
240 value using the register is assigned
241 reg_last_set_invalid set to non-zero when it is not valid
242 to use the value of this register in some
245 To understand the usage of these tables, it is important to understand
246 the distinction between the value in reg_last_set_value being valid
247 and the register being validly contained in some other expression in the
250 Entry I in reg_last_set_value is valid if it is non-zero, and either
251 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
253 Register I may validly appear in any expression returned for the value
254 of another register if reg_n_sets[i] is 1. It may also appear in the
255 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
256 reg_last_set_invalid[j] is zero.
258 If an expression is found in the table containing a register which may
259 not validly appear in an expression, the register is replaced by
260 something that won't match, (clobber (const_int 0)).
262 reg_last_set_invalid[i] is set non-zero when register I is being assigned
263 to and reg_last_set_table_tick[i] == label_tick. */
265 /* Record last value assigned to (hard or pseudo) register n. */
267 static rtx *reg_last_set_value;
269 /* Record the value of label_tick when the value for register n is placed in
270 reg_last_set_value[n]. */
272 static int *reg_last_set_label;
274 /* Record the value of label_tick when an expression involving register n
275 is placed in reg_last_set_value. */
277 static int *reg_last_set_table_tick;
279 /* Set non-zero if references to register n in expressions should not be
282 static char *reg_last_set_invalid;
284 /* Incremented for each label. */
286 static int label_tick;
288 /* Some registers that are set more than once and used in more than one
289 basic block are nevertheless always set in similar ways. For example,
290 a QImode register may be loaded from memory in two places on a machine
291 where byte loads zero extend.
293 We record in the following array what we know about the nonzero
294 bits of a register, specifically which bits are known to be zero.
296 If an entry is zero, it means that we don't know anything special. */
298 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
300 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
301 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero if we know that a register has some leading bits that are always
306 equal to the sign bit. */
308 static unsigned char *reg_sign_bit_copies;
310 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
311 It is zero while computing them and after combine has completed. This
312 former test prevents propagating values based on previously set values,
313 which can be incorrect if a variable is modified in a loop. */
315 static int nonzero_sign_valid;
317 /* These arrays are maintained in parallel with reg_last_set_value
318 and are used to store the mode in which the register was last set,
319 the bits that were known to be zero when it was last set, and the
320 number of sign bits copies it was known to have when it was last set. */
322 static enum machine_mode *reg_last_set_mode;
323 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
324 static char *reg_last_set_sign_bit_copies;
326 /* Record one modification to rtl structure
327 to be undone by storing old_contents into *where.
328 is_int is 1 if the contents are an int. */
334 union {rtx r; int i;} old_contents;
335 union {rtx *r; int *i;} where;
338 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
339 num_undo says how many are currently recorded.
341 storage is nonzero if we must undo the allocation of new storage.
342 The value of storage is what to pass to obfree.
344 other_insn is nonzero if we have modified some other insn in the process
345 of working on subst_insn. It must be verified too.
347 previous_undos is the value of undobuf.undos when we started processing
348 this substitution. This will prevent gen_rtx_combine from re-used a piece
349 from the previous expression. Doing so can produce circular rtl
357 struct undo *previous_undos;
361 static struct undobuf undobuf;
363 /* Number of times the pseudo being substituted for
364 was found and replaced. */
366 static int n_occurrences;
368 static void do_SUBST PARAMS ((rtx *, rtx));
369 static void do_SUBST_INT PARAMS ((int *, int));
370 static void init_reg_last_arrays PARAMS ((void));
371 static void setup_incoming_promotions PARAMS ((void));
372 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
373 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
374 static int sets_function_arg_p PARAMS ((rtx));
375 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
376 static int contains_muldiv PARAMS ((rtx));
377 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
378 static void undo_all PARAMS ((void));
379 static void undo_commit PARAMS ((void));
380 static rtx *find_split_point PARAMS ((rtx *, rtx));
381 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
382 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
383 static rtx simplify_if_then_else PARAMS ((rtx));
384 static rtx simplify_set PARAMS ((rtx));
385 static rtx simplify_logical PARAMS ((rtx, int));
386 static rtx expand_compound_operation PARAMS ((rtx));
387 static rtx expand_field_assignment PARAMS ((rtx));
388 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
389 rtx, unsigned HOST_WIDE_INT, int,
391 static rtx extract_left_shift PARAMS ((rtx, int));
392 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
393 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
394 unsigned HOST_WIDE_INT *));
395 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
396 unsigned HOST_WIDE_INT, rtx, int));
397 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
398 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
399 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
400 static rtx make_field_assignment PARAMS ((rtx));
401 static rtx apply_distributive_law PARAMS ((rtx));
402 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
403 unsigned HOST_WIDE_INT));
404 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
405 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
406 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
407 enum rtx_code, HOST_WIDE_INT,
408 enum machine_mode, int *));
409 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
411 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
412 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
413 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
415 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
417 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
418 enum machine_mode, rtx));
419 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
420 static int reversible_comparison_p PARAMS ((rtx));
421 static void update_table_tick PARAMS ((rtx));
422 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
423 static void check_promoted_subreg PARAMS ((rtx, rtx));
424 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
425 static void record_dead_and_set_regs PARAMS ((rtx));
426 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
427 static rtx get_last_value PARAMS ((rtx));
428 static int use_crosses_set_p PARAMS ((rtx, int));
429 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
430 static int reg_dead_at_p PARAMS ((rtx, rtx));
431 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
432 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
433 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
434 static void distribute_links PARAMS ((rtx));
435 static void mark_used_regs_combine PARAMS ((rtx));
436 static int insn_cuid PARAMS ((rtx));
437 static void record_promoted_value PARAMS ((rtx, rtx));
439 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
440 insn. The substitution can be undone by undo_all. If INTO is already
441 set to NEWVAL, do not record this change. Because computing NEWVAL might
442 also call SUBST, we have to compute it before we put anything into
446 do_SUBST(into, newval)
452 if (oldval == newval)
456 buf = undobuf.frees, undobuf.frees = buf->next;
458 buf = (struct undo *) xmalloc (sizeof (struct undo));
462 buf->old_contents.r = oldval;
465 buf->next = undobuf.undos, undobuf.undos = buf;
468 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
470 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
471 for the value of a HOST_WIDE_INT value (including CONST_INT) is
475 do_SUBST_INT(into, newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return non-zero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (f, nregs)
509 register rtx insn, next;
514 register rtx links, nextlinks;
516 int new_direct_jump_p = 0;
518 combine_attempts = 0;
521 combine_successes = 0;
523 combine_max_regno = nregs;
525 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
526 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
528 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
530 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
533 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
535 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
537 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits
539 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
540 reg_last_set_sign_bit_copies
541 = (char *) xmalloc (nregs * sizeof (char));
543 init_reg_last_arrays ();
545 init_recog_no_volatile ();
547 /* Compute maximum uid value so uid_cuid can be allocated. */
549 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
550 if (INSN_UID (insn) > i)
553 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
556 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
558 /* Don't use reg_nonzero_bits when computing it. This can cause problems
559 when, for example, we have j <<= 1 in a loop. */
561 nonzero_sign_valid = 0;
563 /* Compute the mapping from uids to cuids.
564 Cuids are numbers assigned to insns, like uids,
565 except that cuids increase monotonically through the code.
567 Scan all SETs and see if we can deduce anything about what
568 bits are known to be zero for some registers and how many copies
569 of the sign bit are known to exist for those registers.
571 Also set any known values so that we can use it while searching
572 for what bits are known to be set. */
576 /* We need to initialize it here, because record_dead_and_set_regs may call
578 subst_prev_insn = NULL_RTX;
580 setup_incoming_promotions ();
582 refresh_blocks = sbitmap_alloc (n_basic_blocks);
583 sbitmap_zero (refresh_blocks);
586 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
588 uid_cuid[INSN_UID (insn)] = ++i;
592 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
594 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
596 record_dead_and_set_regs (insn);
599 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
600 if (REG_NOTE_KIND (links) == REG_INC)
601 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
606 if (GET_CODE (insn) == CODE_LABEL)
610 nonzero_sign_valid = 1;
612 /* Now scan all the insns in forward order. */
614 this_basic_block = -1;
618 init_reg_last_arrays ();
619 setup_incoming_promotions ();
621 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
625 /* If INSN starts a new basic block, update our basic block number. */
626 if (this_basic_block + 1 < n_basic_blocks
627 && BLOCK_HEAD (this_basic_block + 1) == insn)
630 if (GET_CODE (insn) == CODE_LABEL)
633 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
635 /* See if we know about function return values before this
636 insn based upon SUBREG flags. */
637 check_promoted_subreg (insn, PATTERN (insn));
639 /* Try this insn with each insn it links back to. */
641 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
642 if ((next = try_combine (insn, XEXP (links, 0),
643 NULL_RTX, &new_direct_jump_p)) != 0)
646 /* Try each sequence of three linked insns ending with this one. */
648 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, XEXP (links, 0),
653 &new_direct_jump_p)) != 0)
657 /* Try to combine a jump insn that uses CC0
658 with a preceding insn that sets CC0, and maybe with its
659 logical predecessor as well.
660 This is how we make decrement-and-branch insns.
661 We need this special code because data flow connections
662 via CC0 do not get entered in LOG_LINKS. */
664 if (GET_CODE (insn) == JUMP_INSN
665 && (prev = prev_nonnote_insn (insn)) != 0
666 && GET_CODE (prev) == INSN
667 && sets_cc0_p (PATTERN (prev)))
669 if ((next = try_combine (insn, prev,
670 NULL_RTX, &new_direct_jump_p)) != 0)
673 for (nextlinks = LOG_LINKS (prev); nextlinks;
674 nextlinks = XEXP (nextlinks, 1))
675 if ((next = try_combine (insn, prev,
677 &new_direct_jump_p)) != 0)
681 /* Do the same for an insn that explicitly references CC0. */
682 if (GET_CODE (insn) == INSN
683 && (prev = prev_nonnote_insn (insn)) != 0
684 && GET_CODE (prev) == INSN
685 && sets_cc0_p (PATTERN (prev))
686 && GET_CODE (PATTERN (insn)) == SET
687 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
689 if ((next = try_combine (insn, prev,
690 NULL_RTX, &new_direct_jump_p)) != 0)
693 for (nextlinks = LOG_LINKS (prev); nextlinks;
694 nextlinks = XEXP (nextlinks, 1))
695 if ((next = try_combine (insn, prev,
697 &new_direct_jump_p)) != 0)
701 /* Finally, see if any of the insns that this insn links to
702 explicitly references CC0. If so, try this insn, that insn,
703 and its predecessor if it sets CC0. */
704 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
705 if (GET_CODE (XEXP (links, 0)) == INSN
706 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
707 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
708 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
709 && GET_CODE (prev) == INSN
710 && sets_cc0_p (PATTERN (prev))
711 && (next = try_combine (insn, XEXP (links, 0),
712 prev, &new_direct_jump_p)) != 0)
716 /* Try combining an insn with two different insns whose results it
718 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
719 for (nextlinks = XEXP (links, 1); nextlinks;
720 nextlinks = XEXP (nextlinks, 1))
721 if ((next = try_combine (insn, XEXP (links, 0),
723 &new_direct_jump_p)) != 0)
726 if (GET_CODE (insn) != NOTE)
727 record_dead_and_set_regs (insn);
736 compute_bb_for_insn (get_max_uid ());
737 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
742 sbitmap_free (refresh_blocks);
743 free (reg_nonzero_bits);
744 free (reg_sign_bit_copies);
745 free (reg_last_death);
747 free (reg_last_set_value);
748 free (reg_last_set_table_tick);
749 free (reg_last_set_label);
750 free (reg_last_set_invalid);
751 free (reg_last_set_mode);
752 free (reg_last_set_nonzero_bits);
753 free (reg_last_set_sign_bit_copies);
757 struct undo *undo, *next;
758 for (undo = undobuf.frees; undo; undo = next)
766 total_attempts += combine_attempts;
767 total_merges += combine_merges;
768 total_extras += combine_extras;
769 total_successes += combine_successes;
771 nonzero_sign_valid = 0;
773 /* Make recognizer allow volatile MEMs again. */
776 return new_direct_jump_p;
779 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
782 init_reg_last_arrays ()
784 unsigned int nregs = combine_max_regno;
786 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
787 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
788 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
789 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
790 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
791 bzero (reg_last_set_invalid, nregs * sizeof (char));
792 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
793 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
794 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
797 /* Set up any promoted values for incoming argument registers. */
800 setup_incoming_promotions ()
802 #ifdef PROMOTE_FUNCTION_ARGS
805 enum machine_mode mode;
807 rtx first = get_insns ();
809 #ifndef OUTGOING_REGNO
810 #define OUTGOING_REGNO(N) N
812 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
817 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
820 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode, const0_rtx)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (x, set, data)
843 void *data ATTRIBUTE_UNUSED;
847 if (GET_CODE (x) == REG
848 && REGNO (x) >= FIRST_PSEUDO_REGISTER
849 /* If this register is undefined at the start of the file, we can't
850 say what its contents were. */
851 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
852 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
854 if (set == 0 || GET_CODE (set) == CLOBBER)
856 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
857 reg_sign_bit_copies[REGNO (x)] = 1;
861 /* If this is a complex assignment, see if we can convert it into a
862 simple assignment. */
863 set = expand_field_assignment (set);
865 /* If this is a simple assignment, or we have a paradoxical SUBREG,
866 set what we know about X. */
868 if (SET_DEST (set) == x
869 || (GET_CODE (SET_DEST (set)) == SUBREG
870 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
872 && SUBREG_REG (SET_DEST (set)) == x))
874 rtx src = SET_SRC (set);
876 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
877 /* If X is narrower than a word and SRC is a non-negative
878 constant that would appear negative in the mode of X,
879 sign-extend it for use in reg_nonzero_bits because some
880 machines (maybe most) will actually do the sign-extension
881 and this is the conservative approach.
883 ??? For 2.5, try to tighten up the MD files in this regard
884 instead of this kludge. */
886 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
887 && GET_CODE (src) == CONST_INT
889 && 0 != (INTVAL (src)
891 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
892 src = GEN_INT (INTVAL (src)
893 | ((HOST_WIDE_INT) (-1)
894 << GET_MODE_BITSIZE (GET_MODE (x))));
897 reg_nonzero_bits[REGNO (x)]
898 |= nonzero_bits (src, nonzero_bits_mode);
899 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
900 if (reg_sign_bit_copies[REGNO (x)] == 0
901 || reg_sign_bit_copies[REGNO (x)] > num)
902 reg_sign_bit_copies[REGNO (x)] = num;
906 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
907 reg_sign_bit_copies[REGNO (x)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (insn, i3, pred, succ, pdest, psrc)
926 rtx pred ATTRIBUTE_UNUSED;
931 rtx set = 0, src, dest;
936 int all_adjacent = (succ ? (next_active_insn (insn) == succ
937 && next_active_insn (succ) == i3)
938 : next_active_insn (insn) == i3);
940 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
941 or a PARALLEL consisting of such a SET and CLOBBERs.
943 If INSN has CLOBBER parallel parts, ignore them for our processing.
944 By definition, these happen during the execution of the insn. When it
945 is merged with another insn, all bets are off. If they are, in fact,
946 needed and aren't also supplied in I3, they may be added by
947 recog_for_combine. Otherwise, it won't match.
949 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
952 Get the source and destination of INSN. If more than one, can't
955 if (GET_CODE (PATTERN (insn)) == SET)
956 set = PATTERN (insn);
957 else if (GET_CODE (PATTERN (insn)) == PARALLEL
958 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
960 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
962 rtx elt = XVECEXP (PATTERN (insn), 0, i);
964 switch (GET_CODE (elt))
966 /* This is important to combine floating point insns
969 /* Combining an isolated USE doesn't make sense.
970 We depend here on combinable_i3_pat to reject them. */
971 /* The code below this loop only verifies that the inputs of
972 the SET in INSN do not change. We call reg_set_between_p
973 to verify that the REG in the USE does not change betweeen
975 If the USE in INSN was for a pseudo register, the matching
976 insn pattern will likely match any register; combining this
977 with any other USE would only be safe if we knew that the
978 used registers have identical values, or if there was
979 something to tell them apart, e.g. different modes. For
980 now, we forgo such compilcated tests and simply disallow
981 combining of USES of pseudo registers with any other USE. */
982 if (GET_CODE (XEXP (elt, 0)) == REG
983 && GET_CODE (PATTERN (i3)) == PARALLEL)
985 rtx i3pat = PATTERN (i3);
986 int i = XVECLEN (i3pat, 0) - 1;
987 unsigned int regno = REGNO (XEXP (elt, 0));
991 rtx i3elt = XVECEXP (i3pat, 0, i);
993 if (GET_CODE (i3elt) == USE
994 && GET_CODE (XEXP (i3elt, 0)) == REG
995 && (REGNO (XEXP (i3elt, 0)) == regno
996 ? reg_set_between_p (XEXP (elt, 0),
997 PREV_INSN (insn), i3)
998 : regno >= FIRST_PSEUDO_REGISTER))
1005 /* We can ignore CLOBBERs. */
1010 /* Ignore SETs whose result isn't used but not those that
1011 have side-effects. */
1012 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1013 && ! side_effects_p (elt))
1016 /* If we have already found a SET, this is a second one and
1017 so we cannot combine with this insn. */
1025 /* Anything else means we can't combine. */
1031 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1032 so don't do anything with it. */
1033 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1042 set = expand_field_assignment (set);
1043 src = SET_SRC (set), dest = SET_DEST (set);
1045 /* Don't eliminate a store in the stack pointer. */
1046 if (dest == stack_pointer_rtx
1047 /* If we couldn't eliminate a field assignment, we can't combine. */
1048 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1049 /* Don't combine with an insn that sets a register to itself if it has
1050 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1051 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1052 /* Can't merge a function call. */
1053 || GET_CODE (src) == CALL
1054 /* Don't eliminate a function call argument. */
1055 || (GET_CODE (i3) == CALL_INSN
1056 && (find_reg_fusage (i3, USE, dest)
1057 || (GET_CODE (dest) == REG
1058 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1059 && global_regs[REGNO (dest)])))
1060 /* Don't substitute into an incremented register. */
1061 || FIND_REG_INC_NOTE (i3, dest)
1062 || (succ && FIND_REG_INC_NOTE (succ, dest))
1064 /* Don't combine the end of a libcall into anything. */
1065 /* ??? This gives worse code, and appears to be unnecessary, since no
1066 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1067 use REG_RETVAL notes for noconflict blocks, but other code here
1068 makes sure that those insns don't disappear. */
1069 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1071 /* Make sure that DEST is not used after SUCC but before I3. */
1072 || (succ && ! all_adjacent
1073 && reg_used_between_p (dest, succ, i3))
1074 /* Make sure that the value that is to be substituted for the register
1075 does not use any registers whose values alter in between. However,
1076 If the insns are adjacent, a use can't cross a set even though we
1077 think it might (this can happen for a sequence of insns each setting
1078 the same destination; reg_last_set of that register might point to
1079 a NOTE). If INSN has a REG_EQUIV note, the register is always
1080 equivalent to the memory so the substitution is valid even if there
1081 are intervening stores. Also, don't move a volatile asm or
1082 UNSPEC_VOLATILE across any other insns. */
1084 && (((GET_CODE (src) != MEM
1085 || ! find_reg_note (insn, REG_EQUIV, src))
1086 && use_crosses_set_p (src, INSN_CUID (insn)))
1087 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1088 || GET_CODE (src) == UNSPEC_VOLATILE))
1089 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1090 better register allocation by not doing the combine. */
1091 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1092 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1093 /* Don't combine across a CALL_INSN, because that would possibly
1094 change whether the life span of some REGs crosses calls or not,
1095 and it is a pain to update that information.
1096 Exception: if source is a constant, moving it later can't hurt.
1097 Accept that special case, because it helps -fforce-addr a lot. */
1098 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1101 /* DEST must either be a REG or CC0. */
1102 if (GET_CODE (dest) == REG)
1104 /* If register alignment is being enforced for multi-word items in all
1105 cases except for parameters, it is possible to have a register copy
1106 insn referencing a hard register that is not allowed to contain the
1107 mode being copied and which would not be valid as an operand of most
1108 insns. Eliminate this problem by not combining with such an insn.
1110 Also, on some machines we don't want to extend the life of a hard
1113 This is the same test done in can_combine except that we don't test
1114 if SRC is a CALL operation to permit a hard register with
1115 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1118 if (GET_CODE (src) == REG
1119 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1121 /* Don't extend the life of a hard register unless it is
1122 user variable (if we have few registers) or it can't
1123 fit into the desired register (meaning something special
1125 Also avoid substituting a return register into I3, because
1126 reload can't handle a conflict with constraints of other
1128 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1129 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1130 || (SMALL_REGISTER_CLASSES
1131 && ((! all_adjacent && ! REG_USERVAR_P (src))
1132 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1133 && ! REG_USERVAR_P (src))))))))
1136 else if (GET_CODE (dest) != CC0)
1139 /* Don't substitute for a register intended as a clobberable operand.
1140 Similarly, don't substitute an expression containing a register that
1141 will be clobbered in I3. */
1142 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1143 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1144 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1145 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1147 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1150 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1151 or not), reject, unless nothing volatile comes between it and I3 */
1153 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1155 /* Make sure succ doesn't contain a volatile reference. */
1156 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1159 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1160 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1161 && p != succ && volatile_refs_p (PATTERN (p)))
1165 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1166 to be an explicit register variable, and was chosen for a reason. */
1168 if (GET_CODE (src) == ASM_OPERANDS
1169 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1172 /* If there are any volatile insns between INSN and I3, reject, because
1173 they might affect machine state. */
1175 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1176 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1177 && p != succ && volatile_insn_p (PATTERN (p)))
1180 /* If INSN or I2 contains an autoincrement or autodecrement,
1181 make sure that register is not used between there and I3,
1182 and not already used in I3 either.
1183 Also insist that I3 not be a jump; if it were one
1184 and the incremented register were spilled, we would lose. */
1187 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1188 if (REG_NOTE_KIND (link) == REG_INC
1189 && (GET_CODE (i3) == JUMP_INSN
1190 || reg_used_between_p (XEXP (link, 0), insn, i3)
1191 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1196 /* Don't combine an insn that follows a CC0-setting insn.
1197 An insn that uses CC0 must not be separated from the one that sets it.
1198 We do, however, allow I2 to follow a CC0-setting insn if that insn
1199 is passed as I1; in that case it will be deleted also.
1200 We also allow combining in this case if all the insns are adjacent
1201 because that would leave the two CC0 insns adjacent as well.
1202 It would be more logical to test whether CC0 occurs inside I1 or I2,
1203 but that would be much slower, and this ought to be equivalent. */
1205 p = prev_nonnote_insn (insn);
1206 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1211 /* If we get here, we have passed all the tests and the combination is
1220 /* Check if PAT is an insn - or a part of it - used to set up an
1221 argument for a function in a hard register. */
1224 sets_function_arg_p (pat)
1230 switch (GET_CODE (pat))
1233 return sets_function_arg_p (PATTERN (pat));
1236 for (i = XVECLEN (pat, 0); --i >= 0;)
1237 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1243 inner_dest = SET_DEST (pat);
1244 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1245 || GET_CODE (inner_dest) == SUBREG
1246 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1247 inner_dest = XEXP (inner_dest, 0);
1249 return (GET_CODE (inner_dest) == REG
1250 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1251 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1260 /* LOC is the location within I3 that contains its pattern or the component
1261 of a PARALLEL of the pattern. We validate that it is valid for combining.
1263 One problem is if I3 modifies its output, as opposed to replacing it
1264 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1265 so would produce an insn that is not equivalent to the original insns.
1269 (set (reg:DI 101) (reg:DI 100))
1270 (set (subreg:SI (reg:DI 101) 0) <foo>)
1272 This is NOT equivalent to:
1274 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1275 (set (reg:DI 101) (reg:DI 100))])
1277 Not only does this modify 100 (in which case it might still be valid
1278 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1280 We can also run into a problem if I2 sets a register that I1
1281 uses and I1 gets directly substituted into I3 (not via I2). In that
1282 case, we would be getting the wrong value of I2DEST into I3, so we
1283 must reject the combination. This case occurs when I2 and I1 both
1284 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1285 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1286 of a SET must prevent combination from occurring.
1288 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1289 if the destination of a SET is a hard register that isn't a user
1292 Before doing the above check, we first try to expand a field assignment
1293 into a set of logical operations.
1295 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1296 we place a register that is both set and used within I3. If more than one
1297 such register is detected, we fail.
1299 Return 1 if the combination is valid, zero otherwise. */
1302 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1308 rtx *pi3dest_killed;
1312 if (GET_CODE (x) == SET)
1314 rtx set = expand_field_assignment (x);
1315 rtx dest = SET_DEST (set);
1316 rtx src = SET_SRC (set);
1317 rtx inner_dest = dest;
1320 rtx inner_src = src;
1325 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1326 || GET_CODE (inner_dest) == SUBREG
1327 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1328 inner_dest = XEXP (inner_dest, 0);
1330 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1333 while (GET_CODE (inner_src) == STRICT_LOW_PART
1334 || GET_CODE (inner_src) == SUBREG
1335 || GET_CODE (inner_src) == ZERO_EXTRACT)
1336 inner_src = XEXP (inner_src, 0);
1338 /* If it is better that two different modes keep two different pseudos,
1339 avoid combining them. This avoids producing the following pattern
1341 (set (subreg:SI (reg/v:QI 21) 0)
1342 (lshiftrt:SI (reg/v:SI 20)
1344 If that were made, reload could not handle the pair of
1345 reg 20/21, since it would try to get any GENERAL_REGS
1346 but some of them don't handle QImode. */
1348 if (rtx_equal_p (inner_src, i2dest)
1349 && GET_CODE (inner_dest) == REG
1350 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1354 /* Check for the case where I3 modifies its output, as
1356 if ((inner_dest != dest
1357 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1358 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1360 /* This is the same test done in can_combine_p except that we
1361 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1362 CALL operation. Moreover, we can't test all_adjacent; we don't
1363 have to, since this instruction will stay in place, thus we are
1364 not considering increasing the lifetime of INNER_DEST.
1366 Also, if this insn sets a function argument, combining it with
1367 something that might need a spill could clobber a previous
1368 function argument; the all_adjacent test in can_combine_p also
1369 checks this; here, we do a more specific test for this case. */
1371 || (GET_CODE (inner_dest) == REG
1372 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1373 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1374 GET_MODE (inner_dest))
1375 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1376 && ! REG_USERVAR_P (inner_dest)
1377 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1378 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1380 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1381 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1384 /* If DEST is used in I3, it is being killed in this insn,
1385 so record that for later.
1386 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1387 STACK_POINTER_REGNUM, since these are always considered to be
1388 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1389 if (pi3dest_killed && GET_CODE (dest) == REG
1390 && reg_referenced_p (dest, PATTERN (i3))
1391 && REGNO (dest) != FRAME_POINTER_REGNUM
1392 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1393 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1395 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1396 && (REGNO (dest) != ARG_POINTER_REGNUM
1397 || ! fixed_regs [REGNO (dest)])
1399 && REGNO (dest) != STACK_POINTER_REGNUM)
1401 if (*pi3dest_killed)
1404 *pi3dest_killed = dest;
1408 else if (GET_CODE (x) == PARALLEL)
1412 for (i = 0; i < XVECLEN (x, 0); i++)
1413 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1414 i1_not_in_src, pi3dest_killed))
1421 /* Return 1 if X is an arithmetic expression that contains a multiplication
1422 and division. We don't count multiplications by powers of two here. */
1428 switch (GET_CODE (x))
1430 case MOD: case DIV: case UMOD: case UDIV:
1434 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1435 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1437 switch (GET_RTX_CLASS (GET_CODE (x)))
1439 case 'c': case '<': case '2':
1440 return contains_muldiv (XEXP (x, 0))
1441 || contains_muldiv (XEXP (x, 1));
1444 return contains_muldiv (XEXP (x, 0));
1452 /* Try to combine the insns I1 and I2 into I3.
1453 Here I1 and I2 appear earlier than I3.
1454 I1 can be zero; then we combine just I2 into I3.
1456 It we are combining three insns and the resulting insn is not recognized,
1457 try splitting it into two insns. If that happens, I2 and I3 are retained
1458 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1461 Return 0 if the combination does not work. Then nothing is changed.
1462 If we did the combination, return the insn at which combine should
1465 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1466 new direct jump instruction. */
1469 try_combine (i3, i2, i1, new_direct_jump_p)
1470 register rtx i3, i2, i1;
1471 register int *new_direct_jump_p;
1473 /* New patterns for I3 and I3, respectively. */
1474 rtx newpat, newi2pat = 0;
1475 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1476 int added_sets_1, added_sets_2;
1477 /* Total number of SETs to put into I3. */
1479 /* Nonzero is I2's body now appears in I3. */
1481 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1482 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1483 /* Contains I3 if the destination of I3 is used in its source, which means
1484 that the old life of I3 is being killed. If that usage is placed into
1485 I2 and not in I3, a REG_DEAD note must be made. */
1486 rtx i3dest_killed = 0;
1487 /* SET_DEST and SET_SRC of I2 and I1. */
1488 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1489 /* PATTERN (I2), or a copy of it in certain cases. */
1491 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1492 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1493 int i1_feeds_i3 = 0;
1494 /* Notes that must be added to REG_NOTES in I3 and I2. */
1495 rtx new_i3_notes, new_i2_notes;
1496 /* Notes that we substituted I3 into I2 instead of the normal case. */
1497 int i3_subst_into_i2 = 0;
1498 /* Notes that I1, I2 or I3 is a MULT operation. */
1506 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1507 This can occur when flow deletes an insn that it has merged into an
1508 auto-increment address. We also can't do anything if I3 has a
1509 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1512 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1513 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1514 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1516 /* ??? This gives worse code, and appears to be unnecessary, since no
1517 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1518 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1524 undobuf.other_insn = 0;
1526 /* Save the current high-water-mark so we can free storage if we didn't
1527 accept this combination. */
1528 undobuf.storage = (char *) oballoc (0);
1530 /* Reset the hard register usage information. */
1531 CLEAR_HARD_REG_SET (newpat_used_regs);
1533 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1534 code below, set I1 to be the earlier of the two insns. */
1535 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1536 temp = i1, i1 = i2, i2 = temp;
1538 added_links_insn = 0;
1540 /* First check for one important special-case that the code below will
1541 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1542 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1543 we may be able to replace that destination with the destination of I3.
1544 This occurs in the common code where we compute both a quotient and
1545 remainder into a structure, in which case we want to do the computation
1546 directly into the structure to avoid register-register copies.
1548 We make very conservative checks below and only try to handle the
1549 most common cases of this. For example, we only handle the case
1550 where I2 and I3 are adjacent to avoid making difficult register
1553 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1554 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1555 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1556 && (! SMALL_REGISTER_CLASSES
1557 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1558 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1559 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1560 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1561 && GET_CODE (PATTERN (i2)) == PARALLEL
1562 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1563 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1564 below would need to check what is inside (and reg_overlap_mentioned_p
1565 doesn't support those codes anyway). Don't allow those destinations;
1566 the resulting insn isn't likely to be recognized anyway. */
1567 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1568 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1569 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1570 SET_DEST (PATTERN (i3)))
1571 && next_real_insn (i2) == i3)
1573 rtx p2 = PATTERN (i2);
1575 /* Make sure that the destination of I3,
1576 which we are going to substitute into one output of I2,
1577 is not used within another output of I2. We must avoid making this:
1578 (parallel [(set (mem (reg 69)) ...)
1579 (set (reg 69) ...)])
1580 which is not well-defined as to order of actions.
1581 (Besides, reload can't handle output reloads for this.)
1583 The problem can also happen if the dest of I3 is a memory ref,
1584 if another dest in I2 is an indirect memory ref. */
1585 for (i = 0; i < XVECLEN (p2, 0); i++)
1586 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1587 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1588 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1589 SET_DEST (XVECEXP (p2, 0, i))))
1592 if (i == XVECLEN (p2, 0))
1593 for (i = 0; i < XVECLEN (p2, 0); i++)
1594 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1595 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1596 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1601 subst_low_cuid = INSN_CUID (i2);
1603 added_sets_2 = added_sets_1 = 0;
1604 i2dest = SET_SRC (PATTERN (i3));
1606 /* Replace the dest in I2 with our dest and make the resulting
1607 insn the new pattern for I3. Then skip to where we
1608 validate the pattern. Everything was set up above. */
1609 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1610 SET_DEST (PATTERN (i3)));
1613 i3_subst_into_i2 = 1;
1614 goto validate_replacement;
1618 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1619 one of those words to another constant, merge them by making a new
1622 && (temp = single_set (i2)) != 0
1623 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1624 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1625 && GET_CODE (SET_DEST (temp)) == REG
1626 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1627 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1628 && GET_CODE (PATTERN (i3)) == SET
1629 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1630 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1633 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1635 HOST_WIDE_INT lo, hi;
1637 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1638 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1641 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1642 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1645 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1646 lo = INTVAL (SET_SRC (PATTERN (i3)));
1648 hi = INTVAL (SET_SRC (PATTERN (i3)));
1652 subst_low_cuid = INSN_CUID (i2);
1653 added_sets_2 = added_sets_1 = 0;
1654 i2dest = SET_DEST (temp);
1656 SUBST (SET_SRC (temp),
1657 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1659 newpat = PATTERN (i2);
1660 i3_subst_into_i2 = 1;
1661 goto validate_replacement;
1665 /* If we have no I1 and I2 looks like:
1666 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1668 make up a dummy I1 that is
1671 (set (reg:CC X) (compare:CC Y (const_int 0)))
1673 (We can ignore any trailing CLOBBERs.)
1675 This undoes a previous combination and allows us to match a branch-and-
1678 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1679 && XVECLEN (PATTERN (i2), 0) >= 2
1680 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1681 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1683 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1684 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1685 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1686 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1687 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1688 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1690 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1691 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1696 /* We make I1 with the same INSN_UID as I2. This gives it
1697 the same INSN_CUID for value tracking. Our fake I1 will
1698 never appear in the insn stream so giving it the same INSN_UID
1699 as I2 will not cause a problem. */
1701 subst_prev_insn = i1
1702 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1703 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1706 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1707 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1708 SET_DEST (PATTERN (i1)));
1713 /* Verify that I2 and I1 are valid for combining. */
1714 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1715 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1721 /* Record whether I2DEST is used in I2SRC and similarly for the other
1722 cases. Knowing this will help in register status updating below. */
1723 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1724 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1725 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1727 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1729 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1731 /* Ensure that I3's pattern can be the destination of combines. */
1732 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1733 i1 && i2dest_in_i1src && i1_feeds_i3,
1740 /* See if any of the insns is a MULT operation. Unless one is, we will
1741 reject a combination that is, since it must be slower. Be conservative
1743 if (GET_CODE (i2src) == MULT
1744 || (i1 != 0 && GET_CODE (i1src) == MULT)
1745 || (GET_CODE (PATTERN (i3)) == SET
1746 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1749 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1750 We used to do this EXCEPT in one case: I3 has a post-inc in an
1751 output operand. However, that exception can give rise to insns like
1753 which is a famous insn on the PDP-11 where the value of r3 used as the
1754 source was model-dependent. Avoid this sort of thing. */
1757 if (!(GET_CODE (PATTERN (i3)) == SET
1758 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1759 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1760 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1761 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1762 /* It's not the exception. */
1765 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1766 if (REG_NOTE_KIND (link) == REG_INC
1767 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1769 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1776 /* See if the SETs in I1 or I2 need to be kept around in the merged
1777 instruction: whenever the value set there is still needed past I3.
1778 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1780 For the SET in I1, we have two cases: If I1 and I2 independently
1781 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1782 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1783 in I1 needs to be kept around unless I1DEST dies or is set in either
1784 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1785 I1DEST. If so, we know I1 feeds into I2. */
1787 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1790 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1791 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1793 /* If the set in I2 needs to be kept around, we must make a copy of
1794 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1795 PATTERN (I2), we are only substituting for the original I1DEST, not into
1796 an already-substituted copy. This also prevents making self-referential
1797 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1800 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1801 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1805 i2pat = copy_rtx (i2pat);
1809 /* Substitute in the latest insn for the regs set by the earlier ones. */
1811 maxreg = max_reg_num ();
1815 /* It is possible that the source of I2 or I1 may be performing an
1816 unneeded operation, such as a ZERO_EXTEND of something that is known
1817 to have the high part zero. Handle that case by letting subst look at
1818 the innermost one of them.
1820 Another way to do this would be to have a function that tries to
1821 simplify a single insn instead of merging two or more insns. We don't
1822 do this because of the potential of infinite loops and because
1823 of the potential extra memory required. However, doing it the way
1824 we are is a bit of a kludge and doesn't catch all cases.
1826 But only do this if -fexpensive-optimizations since it slows things down
1827 and doesn't usually win. */
1829 if (flag_expensive_optimizations)
1831 /* Pass pc_rtx so no substitutions are done, just simplifications.
1832 The cases that we are interested in here do not involve the few
1833 cases were is_replaced is checked. */
1836 subst_low_cuid = INSN_CUID (i1);
1837 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1841 subst_low_cuid = INSN_CUID (i2);
1842 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1845 undobuf.previous_undos = undobuf.undos;
1849 /* Many machines that don't use CC0 have insns that can both perform an
1850 arithmetic operation and set the condition code. These operations will
1851 be represented as a PARALLEL with the first element of the vector
1852 being a COMPARE of an arithmetic operation with the constant zero.
1853 The second element of the vector will set some pseudo to the result
1854 of the same arithmetic operation. If we simplify the COMPARE, we won't
1855 match such a pattern and so will generate an extra insn. Here we test
1856 for this case, where both the comparison and the operation result are
1857 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1858 I2SRC. Later we will make the PARALLEL that contains I2. */
1860 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1861 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1862 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1863 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1865 #ifdef EXTRA_CC_MODES
1867 enum machine_mode compare_mode;
1870 newpat = PATTERN (i3);
1871 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1875 #ifdef EXTRA_CC_MODES
1876 /* See if a COMPARE with the operand we substituted in should be done
1877 with the mode that is currently being used. If not, do the same
1878 processing we do in `subst' for a SET; namely, if the destination
1879 is used only once, try to replace it with a register of the proper
1880 mode and also replace the COMPARE. */
1881 if (undobuf.other_insn == 0
1882 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1883 &undobuf.other_insn))
1884 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1886 != GET_MODE (SET_DEST (newpat))))
1888 unsigned int regno = REGNO (SET_DEST (newpat));
1889 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1891 if (regno < FIRST_PSEUDO_REGISTER
1892 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1893 && ! REG_USERVAR_P (SET_DEST (newpat))))
1895 if (regno >= FIRST_PSEUDO_REGISTER)
1896 SUBST (regno_reg_rtx[regno], new_dest);
1898 SUBST (SET_DEST (newpat), new_dest);
1899 SUBST (XEXP (*cc_use, 0), new_dest);
1900 SUBST (SET_SRC (newpat),
1901 gen_rtx_combine (COMPARE, compare_mode,
1902 i2src, const0_rtx));
1905 undobuf.other_insn = 0;
1912 n_occurrences = 0; /* `subst' counts here */
1914 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1915 need to make a unique copy of I2SRC each time we substitute it
1916 to avoid self-referential rtl. */
1918 subst_low_cuid = INSN_CUID (i2);
1919 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1920 ! i1_feeds_i3 && i1dest_in_i1src);
1921 undobuf.previous_undos = undobuf.undos;
1923 /* Record whether i2's body now appears within i3's body. */
1924 i2_is_used = n_occurrences;
1927 /* If we already got a failure, don't try to do more. Otherwise,
1928 try to substitute in I1 if we have it. */
1930 if (i1 && GET_CODE (newpat) != CLOBBER)
1932 /* Before we can do this substitution, we must redo the test done
1933 above (see detailed comments there) that ensures that I1DEST
1934 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1936 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1944 subst_low_cuid = INSN_CUID (i1);
1945 newpat = subst (newpat, i1dest, i1src, 0, 0);
1946 undobuf.previous_undos = undobuf.undos;
1949 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1950 to count all the ways that I2SRC and I1SRC can be used. */
1951 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1952 && i2_is_used + added_sets_2 > 1)
1953 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1954 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1956 /* Fail if we tried to make a new register (we used to abort, but there's
1957 really no reason to). */
1958 || max_reg_num () != maxreg
1959 /* Fail if we couldn't do something and have a CLOBBER. */
1960 || GET_CODE (newpat) == CLOBBER
1961 /* Fail if this new pattern is a MULT and we didn't have one before
1962 at the outer level. */
1963 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1970 /* If the actions of the earlier insns must be kept
1971 in addition to substituting them into the latest one,
1972 we must make a new PARALLEL for the latest insn
1973 to hold additional the SETs. */
1975 if (added_sets_1 || added_sets_2)
1979 if (GET_CODE (newpat) == PARALLEL)
1981 rtvec old = XVEC (newpat, 0);
1982 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1983 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1984 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1985 sizeof (old->elem[0]) * old->num_elem);
1990 total_sets = 1 + added_sets_1 + added_sets_2;
1991 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1992 XVECEXP (newpat, 0, 0) = old;
1996 XVECEXP (newpat, 0, --total_sets)
1997 = (GET_CODE (PATTERN (i1)) == PARALLEL
1998 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2002 /* If there is no I1, use I2's body as is. We used to also not do
2003 the subst call below if I2 was substituted into I3,
2004 but that could lose a simplification. */
2006 XVECEXP (newpat, 0, --total_sets) = i2pat;
2008 /* See comment where i2pat is assigned. */
2009 XVECEXP (newpat, 0, --total_sets)
2010 = subst (i2pat, i1dest, i1src, 0, 0);
2014 /* We come here when we are replacing a destination in I2 with the
2015 destination of I3. */
2016 validate_replacement:
2018 /* Note which hard regs this insn has as inputs. */
2019 mark_used_regs_combine (newpat);
2021 /* Is the result of combination a valid instruction? */
2022 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2024 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2025 the second SET's destination is a register that is unused. In that case,
2026 we just need the first SET. This can occur when simplifying a divmod
2027 insn. We *must* test for this case here because the code below that
2028 splits two independent SETs doesn't handle this case correctly when it
2029 updates the register status. Also check the case where the first
2030 SET's destination is unused. That would not cause incorrect code, but
2031 does cause an unneeded insn to remain. */
2033 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2034 && XVECLEN (newpat, 0) == 2
2035 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2036 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2037 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2038 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2039 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2040 && asm_noperands (newpat) < 0)
2042 newpat = XVECEXP (newpat, 0, 0);
2043 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2046 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2047 && XVECLEN (newpat, 0) == 2
2048 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2049 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2051 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2052 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2053 && asm_noperands (newpat) < 0)
2055 newpat = XVECEXP (newpat, 0, 1);
2056 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2059 /* If we were combining three insns and the result is a simple SET
2060 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2061 insns. There are two ways to do this. It can be split using a
2062 machine-specific method (like when you have an addition of a large
2063 constant) or by combine in the function find_split_point. */
2065 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2066 && asm_noperands (newpat) < 0)
2068 rtx m_split, *split;
2069 rtx ni2dest = i2dest;
2071 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2072 use I2DEST as a scratch register will help. In the latter case,
2073 convert I2DEST to the mode of the source of NEWPAT if we can. */
2075 m_split = split_insns (newpat, i3);
2077 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2078 inputs of NEWPAT. */
2080 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2081 possible to try that as a scratch reg. This would require adding
2082 more code to make it work though. */
2084 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2086 /* If I2DEST is a hard register or the only use of a pseudo,
2087 we can change its mode. */
2088 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2089 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2090 && GET_CODE (i2dest) == REG
2091 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2092 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2093 && ! REG_USERVAR_P (i2dest))))
2094 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2097 m_split = split_insns (gen_rtx_PARALLEL
2099 gen_rtvec (2, newpat,
2100 gen_rtx_CLOBBER (VOIDmode,
2105 if (m_split && GET_CODE (m_split) == SEQUENCE
2106 && XVECLEN (m_split, 0) == 2
2107 && (next_real_insn (i2) == i3
2108 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2112 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2113 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2115 i3set = single_set (XVECEXP (m_split, 0, 1));
2116 i2set = single_set (XVECEXP (m_split, 0, 0));
2118 /* In case we changed the mode of I2DEST, replace it in the
2119 pseudo-register table here. We can't do it above in case this
2120 code doesn't get executed and we do a split the other way. */
2122 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2123 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2125 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2127 /* If I2 or I3 has multiple SETs, we won't know how to track
2128 register status, so don't use these insns. If I2's destination
2129 is used between I2 and I3, we also can't use these insns. */
2131 if (i2_code_number >= 0 && i2set && i3set
2132 && (next_real_insn (i2) == i3
2133 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2134 insn_code_number = recog_for_combine (&newi3pat, i3,
2136 if (insn_code_number >= 0)
2139 /* It is possible that both insns now set the destination of I3.
2140 If so, we must show an extra use of it. */
2142 if (insn_code_number >= 0)
2144 rtx new_i3_dest = SET_DEST (i3set);
2145 rtx new_i2_dest = SET_DEST (i2set);
2147 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2148 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2149 || GET_CODE (new_i3_dest) == SUBREG)
2150 new_i3_dest = XEXP (new_i3_dest, 0);
2152 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2153 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2154 || GET_CODE (new_i2_dest) == SUBREG)
2155 new_i2_dest = XEXP (new_i2_dest, 0);
2157 if (GET_CODE (new_i3_dest) == REG
2158 && GET_CODE (new_i2_dest) == REG
2159 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2160 REG_N_SETS (REGNO (new_i2_dest))++;
2164 /* If we can split it and use I2DEST, go ahead and see if that
2165 helps things be recognized. Verify that none of the registers
2166 are set between I2 and I3. */
2167 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2169 && GET_CODE (i2dest) == REG
2171 /* We need I2DEST in the proper mode. If it is a hard register
2172 or the only use of a pseudo, we can change its mode. */
2173 && (GET_MODE (*split) == GET_MODE (i2dest)
2174 || GET_MODE (*split) == VOIDmode
2175 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2176 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2177 && ! REG_USERVAR_P (i2dest)))
2178 && (next_real_insn (i2) == i3
2179 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2180 /* We can't overwrite I2DEST if its value is still used by
2182 && ! reg_referenced_p (i2dest, newpat))
2184 rtx newdest = i2dest;
2185 enum rtx_code split_code = GET_CODE (*split);
2186 enum machine_mode split_mode = GET_MODE (*split);
2188 /* Get NEWDEST as a register in the proper mode. We have already
2189 validated that we can do this. */
2190 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2192 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2194 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2195 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2198 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2199 an ASHIFT. This can occur if it was inside a PLUS and hence
2200 appeared to be a memory address. This is a kludge. */
2201 if (split_code == MULT
2202 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2203 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2205 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2206 XEXP (*split, 0), GEN_INT (i)));
2207 /* Update split_code because we may not have a multiply
2209 split_code = GET_CODE (*split);
2212 #ifdef INSN_SCHEDULING
2213 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2214 be written as a ZERO_EXTEND. */
2215 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2216 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2220 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2221 SUBST (*split, newdest);
2222 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2224 /* If the split point was a MULT and we didn't have one before,
2225 don't use one now. */
2226 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2227 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2231 /* Check for a case where we loaded from memory in a narrow mode and
2232 then sign extended it, but we need both registers. In that case,
2233 we have a PARALLEL with both loads from the same memory location.
2234 We can split this into a load from memory followed by a register-register
2235 copy. This saves at least one insn, more if register allocation can
2238 We cannot do this if the destination of the second assignment is
2239 a register that we have already assumed is zero-extended. Similarly
2240 for a SUBREG of such a register. */
2242 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2243 && GET_CODE (newpat) == PARALLEL
2244 && XVECLEN (newpat, 0) == 2
2245 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2246 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2247 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2248 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2249 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2250 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2252 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2253 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2254 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2255 (GET_CODE (temp) == REG
2256 && reg_nonzero_bits[REGNO (temp)] != 0
2257 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2258 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2259 && (reg_nonzero_bits[REGNO (temp)]
2260 != GET_MODE_MASK (word_mode))))
2261 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2262 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2263 (GET_CODE (temp) == REG
2264 && reg_nonzero_bits[REGNO (temp)] != 0
2265 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2266 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2267 && (reg_nonzero_bits[REGNO (temp)]
2268 != GET_MODE_MASK (word_mode)))))
2269 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2270 SET_SRC (XVECEXP (newpat, 0, 1)))
2271 && ! find_reg_note (i3, REG_UNUSED,
2272 SET_DEST (XVECEXP (newpat, 0, 0))))
2276 newi2pat = XVECEXP (newpat, 0, 0);
2277 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2278 newpat = XVECEXP (newpat, 0, 1);
2279 SUBST (SET_SRC (newpat),
2280 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2281 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2283 if (i2_code_number >= 0)
2284 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2286 if (insn_code_number >= 0)
2291 /* If we will be able to accept this, we have made a change to the
2292 destination of I3. This can invalidate a LOG_LINKS pointing
2293 to I3. No other part of combine.c makes such a transformation.
2295 The new I3 will have a destination that was previously the
2296 destination of I1 or I2 and which was used in i2 or I3. Call
2297 distribute_links to make a LOG_LINK from the next use of
2298 that destination. */
2300 PATTERN (i3) = newpat;
2301 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2303 /* I3 now uses what used to be its destination and which is
2304 now I2's destination. That means we need a LOG_LINK from
2305 I3 to I2. But we used to have one, so we still will.
2307 However, some later insn might be using I2's dest and have
2308 a LOG_LINK pointing at I3. We must remove this link.
2309 The simplest way to remove the link is to point it at I1,
2310 which we know will be a NOTE. */
2312 for (insn = NEXT_INSN (i3);
2313 insn && (this_basic_block == n_basic_blocks - 1
2314 || insn != BLOCK_HEAD (this_basic_block + 1));
2315 insn = NEXT_INSN (insn))
2317 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2318 && reg_referenced_p (ni2dest, PATTERN (insn)))
2320 for (link = LOG_LINKS (insn); link;
2321 link = XEXP (link, 1))
2322 if (XEXP (link, 0) == i3)
2323 XEXP (link, 0) = i1;
2331 /* Similarly, check for a case where we have a PARALLEL of two independent
2332 SETs but we started with three insns. In this case, we can do the sets
2333 as two separate insns. This case occurs when some SET allows two
2334 other insns to combine, but the destination of that SET is still live. */
2336 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2337 && GET_CODE (newpat) == PARALLEL
2338 && XVECLEN (newpat, 0) == 2
2339 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2340 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2341 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2342 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2343 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2344 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2345 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2347 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2348 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2349 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2350 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2351 XVECEXP (newpat, 0, 0))
2352 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2353 XVECEXP (newpat, 0, 1))
2354 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2355 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2357 /* Normally, it doesn't matter which of the two is done first,
2358 but it does if one references cc0. In that case, it has to
2361 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2363 newi2pat = XVECEXP (newpat, 0, 0);
2364 newpat = XVECEXP (newpat, 0, 1);
2369 newi2pat = XVECEXP (newpat, 0, 1);
2370 newpat = XVECEXP (newpat, 0, 0);
2373 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2375 if (i2_code_number >= 0)
2376 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2379 /* If it still isn't recognized, fail and change things back the way they
2381 if ((insn_code_number < 0
2382 /* Is the result a reasonable ASM_OPERANDS? */
2383 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2389 /* If we had to change another insn, make sure it is valid also. */
2390 if (undobuf.other_insn)
2392 rtx other_pat = PATTERN (undobuf.other_insn);
2393 rtx new_other_notes;
2396 CLEAR_HARD_REG_SET (newpat_used_regs);
2398 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2401 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2407 PATTERN (undobuf.other_insn) = other_pat;
2409 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2410 are still valid. Then add any non-duplicate notes added by
2411 recog_for_combine. */
2412 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2414 next = XEXP (note, 1);
2416 if (REG_NOTE_KIND (note) == REG_UNUSED
2417 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2419 if (GET_CODE (XEXP (note, 0)) == REG)
2420 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2422 remove_note (undobuf.other_insn, note);
2426 for (note = new_other_notes; note; note = XEXP (note, 1))
2427 if (GET_CODE (XEXP (note, 0)) == REG)
2428 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2430 distribute_notes (new_other_notes, undobuf.other_insn,
2431 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2434 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2435 they are adjacent to each other or not. */
2437 rtx p = prev_nonnote_insn (i3);
2438 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat && sets_cc0_p (newi2pat))
2446 /* We now know that we can do this combination. Merge the insns and
2447 update the status of registers and LOG_LINKS. */
2450 rtx i3notes, i2notes, i1notes = 0;
2451 rtx i3links, i2links, i1links = 0;
2454 /* Compute which registers we expect to eliminate. newi2pat may be setting
2455 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2456 same as i3dest, in which case newi2pat may be setting i1dest. */
2457 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2458 || i2dest_in_i2src || i2dest_in_i1src
2460 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2461 || (newi2pat && reg_set_p (i1dest, newi2pat))
2464 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2466 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2467 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2469 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2471 /* Ensure that we do not have something that should not be shared but
2472 occurs multiple times in the new insns. Check this by first
2473 resetting all the `used' flags and then copying anything is shared. */
2475 reset_used_flags (i3notes);
2476 reset_used_flags (i2notes);
2477 reset_used_flags (i1notes);
2478 reset_used_flags (newpat);
2479 reset_used_flags (newi2pat);
2480 if (undobuf.other_insn)
2481 reset_used_flags (PATTERN (undobuf.other_insn));
2483 i3notes = copy_rtx_if_shared (i3notes);
2484 i2notes = copy_rtx_if_shared (i2notes);
2485 i1notes = copy_rtx_if_shared (i1notes);
2486 newpat = copy_rtx_if_shared (newpat);
2487 newi2pat = copy_rtx_if_shared (newi2pat);
2488 if (undobuf.other_insn)
2489 reset_used_flags (PATTERN (undobuf.other_insn));
2491 INSN_CODE (i3) = insn_code_number;
2492 PATTERN (i3) = newpat;
2493 if (undobuf.other_insn)
2494 INSN_CODE (undobuf.other_insn) = other_code_number;
2496 /* We had one special case above where I2 had more than one set and
2497 we replaced a destination of one of those sets with the destination
2498 of I3. In that case, we have to update LOG_LINKS of insns later
2499 in this basic block. Note that this (expensive) case is rare.
2501 Also, in this case, we must pretend that all REG_NOTEs for I2
2502 actually came from I3, so that REG_UNUSED notes from I2 will be
2503 properly handled. */
2505 if (i3_subst_into_i2)
2507 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2509 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2510 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2511 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2512 && ! find_reg_note (i2, REG_UNUSED,
2513 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2514 for (temp = NEXT_INSN (i2);
2515 temp && (this_basic_block == n_basic_blocks - 1
2516 || BLOCK_HEAD (this_basic_block) != temp);
2517 temp = NEXT_INSN (temp))
2518 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2519 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2520 if (XEXP (link, 0) == i2)
2521 XEXP (link, 0) = i3;
2527 while (XEXP (link, 1))
2528 link = XEXP (link, 1);
2529 XEXP (link, 1) = i2notes;
2543 INSN_CODE (i2) = i2_code_number;
2544 PATTERN (i2) = newi2pat;
2548 PUT_CODE (i2, NOTE);
2549 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2550 NOTE_SOURCE_FILE (i2) = 0;
2557 PUT_CODE (i1, NOTE);
2558 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2559 NOTE_SOURCE_FILE (i1) = 0;
2562 /* Get death notes for everything that is now used in either I3 or
2563 I2 and used to die in a previous insn. If we built two new
2564 patterns, move from I1 to I2 then I2 to I3 so that we get the
2565 proper movement on registers that I2 modifies. */
2569 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2570 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2573 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2576 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2578 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2581 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2584 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2587 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2590 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2591 know these are REG_UNUSED and want them to go to the desired insn,
2592 so we always pass it as i3. We have not counted the notes in
2593 reg_n_deaths yet, so we need to do so now. */
2595 if (newi2pat && new_i2_notes)
2597 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2598 if (GET_CODE (XEXP (temp, 0)) == REG)
2599 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2601 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2606 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2607 if (GET_CODE (XEXP (temp, 0)) == REG)
2608 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2610 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2613 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2614 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2615 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2616 in that case, it might delete I2. Similarly for I2 and I1.
2617 Show an additional death due to the REG_DEAD note we make here. If
2618 we discard it in distribute_notes, we will decrement it again. */
2622 if (GET_CODE (i3dest_killed) == REG)
2623 REG_N_DEATHS (REGNO (i3dest_killed))++;
2625 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2626 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2628 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2630 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2632 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2636 if (i2dest_in_i2src)
2638 if (GET_CODE (i2dest) == REG)
2639 REG_N_DEATHS (REGNO (i2dest))++;
2641 if (newi2pat && reg_set_p (i2dest, newi2pat))
2642 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2643 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2645 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2646 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2647 NULL_RTX, NULL_RTX);
2650 if (i1dest_in_i1src)
2652 if (GET_CODE (i1dest) == REG)
2653 REG_N_DEATHS (REGNO (i1dest))++;
2655 if (newi2pat && reg_set_p (i1dest, newi2pat))
2656 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2657 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2659 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2660 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2661 NULL_RTX, NULL_RTX);
2664 distribute_links (i3links);
2665 distribute_links (i2links);
2666 distribute_links (i1links);
2668 if (GET_CODE (i2dest) == REG)
2671 rtx i2_insn = 0, i2_val = 0, set;
2673 /* The insn that used to set this register doesn't exist, and
2674 this life of the register may not exist either. See if one of
2675 I3's links points to an insn that sets I2DEST. If it does,
2676 that is now the last known value for I2DEST. If we don't update
2677 this and I2 set the register to a value that depended on its old
2678 contents, we will get confused. If this insn is used, thing
2679 will be set correctly in combine_instructions. */
2681 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2682 if ((set = single_set (XEXP (link, 0))) != 0
2683 && rtx_equal_p (i2dest, SET_DEST (set)))
2684 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2686 record_value_for_reg (i2dest, i2_insn, i2_val);
2688 /* If the reg formerly set in I2 died only once and that was in I3,
2689 zero its use count so it won't make `reload' do any work. */
2691 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2692 && ! i2dest_in_i2src)
2694 regno = REGNO (i2dest);
2695 REG_N_SETS (regno)--;
2699 if (i1 && GET_CODE (i1dest) == REG)
2702 rtx i1_insn = 0, i1_val = 0, set;
2704 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2705 if ((set = single_set (XEXP (link, 0))) != 0
2706 && rtx_equal_p (i1dest, SET_DEST (set)))
2707 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2709 record_value_for_reg (i1dest, i1_insn, i1_val);
2711 regno = REGNO (i1dest);
2712 if (! added_sets_1 && ! i1dest_in_i1src)
2713 REG_N_SETS (regno)--;
2716 /* Update reg_nonzero_bits et al for any changes that may have been made
2719 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2721 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2723 /* Set new_direct_jump_p if a new return or simple jump instruction
2726 If I3 is now an unconditional jump, ensure that it has a
2727 BARRIER following it since it may have initially been a
2728 conditional jump. It may also be the last nonnote insn. */
2730 if (GET_CODE (newpat) == RETURN || simplejump_p (i3))
2732 *new_direct_jump_p = 1;
2734 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2735 || GET_CODE (temp) != BARRIER)
2736 emit_barrier_after (i3);
2740 combine_successes++;
2743 /* Clear this here, so that subsequent get_last_value calls are not
2745 subst_prev_insn = NULL_RTX;
2747 if (added_links_insn
2748 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2749 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2750 return added_links_insn;
2752 return newi2pat ? i2 : i3;
2755 /* Undo all the modifications recorded in undobuf. */
2760 struct undo *undo, *next;
2762 for (undo = undobuf.undos; undo; undo = next)
2766 *undo->where.i = undo->old_contents.i;
2768 *undo->where.r = undo->old_contents.r;
2770 undo->next = undobuf.frees;
2771 undobuf.frees = undo;
2774 obfree (undobuf.storage);
2775 undobuf.undos = undobuf.previous_undos = 0;
2777 /* Clear this here, so that subsequent get_last_value calls are not
2779 subst_prev_insn = NULL_RTX;
2782 /* We've committed to accepting the changes we made. Move all
2783 of the undos to the free list. */
2788 struct undo *undo, *next;
2790 for (undo = undobuf.undos; undo; undo = next)
2793 undo->next = undobuf.frees;
2794 undobuf.frees = undo;
2796 undobuf.undos = undobuf.previous_undos = 0;
2800 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2801 where we have an arithmetic expression and return that point. LOC will
2804 try_combine will call this function to see if an insn can be split into
2808 find_split_point (loc, insn)
2813 enum rtx_code code = GET_CODE (x);
2815 unsigned HOST_WIDE_INT len = 0;
2816 HOST_WIDE_INT pos = 0;
2818 rtx inner = NULL_RTX;
2820 /* First special-case some codes. */
2824 #ifdef INSN_SCHEDULING
2825 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2827 if (GET_CODE (SUBREG_REG (x)) == MEM)
2830 return find_split_point (&SUBREG_REG (x), insn);
2834 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2835 using LO_SUM and HIGH. */
2836 if (GET_CODE (XEXP (x, 0)) == CONST
2837 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2840 gen_rtx_combine (LO_SUM, Pmode,
2841 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2843 return &XEXP (XEXP (x, 0), 0);
2847 /* If we have a PLUS whose second operand is a constant and the
2848 address is not valid, perhaps will can split it up using
2849 the machine-specific way to split large constants. We use
2850 the first pseudo-reg (one of the virtual regs) as a placeholder;
2851 it will not remain in the result. */
2852 if (GET_CODE (XEXP (x, 0)) == PLUS
2853 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2854 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2856 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2857 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2860 /* This should have produced two insns, each of which sets our
2861 placeholder. If the source of the second is a valid address,
2862 we can make put both sources together and make a split point
2865 if (seq && XVECLEN (seq, 0) == 2
2866 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2867 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2868 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2869 && ! reg_mentioned_p (reg,
2870 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2871 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2872 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2873 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2874 && memory_address_p (GET_MODE (x),
2875 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2877 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2878 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2880 /* Replace the placeholder in SRC2 with SRC1. If we can
2881 find where in SRC2 it was placed, that can become our
2882 split point and we can replace this address with SRC2.
2883 Just try two obvious places. */
2885 src2 = replace_rtx (src2, reg, src1);
2887 if (XEXP (src2, 0) == src1)
2888 split = &XEXP (src2, 0);
2889 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2890 && XEXP (XEXP (src2, 0), 0) == src1)
2891 split = &XEXP (XEXP (src2, 0), 0);
2895 SUBST (XEXP (x, 0), src2);
2900 /* If that didn't work, perhaps the first operand is complex and
2901 needs to be computed separately, so make a split point there.
2902 This will occur on machines that just support REG + CONST
2903 and have a constant moved through some previous computation. */
2905 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2906 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2907 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2909 return &XEXP (XEXP (x, 0), 0);
2915 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2916 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2917 we need to put the operand into a register. So split at that
2920 if (SET_DEST (x) == cc0_rtx
2921 && GET_CODE (SET_SRC (x)) != COMPARE
2922 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2923 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2924 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2925 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2926 return &SET_SRC (x);
2929 /* See if we can split SET_SRC as it stands. */
2930 split = find_split_point (&SET_SRC (x), insn);
2931 if (split && split != &SET_SRC (x))
2934 /* See if we can split SET_DEST as it stands. */
2935 split = find_split_point (&SET_DEST (x), insn);
2936 if (split && split != &SET_DEST (x))
2939 /* See if this is a bitfield assignment with everything constant. If
2940 so, this is an IOR of an AND, so split it into that. */
2941 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2942 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2943 <= HOST_BITS_PER_WIDE_INT)
2944 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2945 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2946 && GET_CODE (SET_SRC (x)) == CONST_INT
2947 && ((INTVAL (XEXP (SET_DEST (x), 1))
2948 + INTVAL (XEXP (SET_DEST (x), 2)))
2949 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2950 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2952 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2953 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2954 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2955 rtx dest = XEXP (SET_DEST (x), 0);
2956 enum machine_mode mode = GET_MODE (dest);
2957 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2959 if (BITS_BIG_ENDIAN)
2960 pos = GET_MODE_BITSIZE (mode) - len - pos;
2964 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2967 gen_binary (IOR, mode,
2968 gen_binary (AND, mode, dest,
2969 GEN_INT (~ (mask << pos)
2970 & GET_MODE_MASK (mode))),
2971 GEN_INT (src << pos)));
2973 SUBST (SET_DEST (x), dest);
2975 split = find_split_point (&SET_SRC (x), insn);
2976 if (split && split != &SET_SRC (x))
2980 /* Otherwise, see if this is an operation that we can split into two.
2981 If so, try to split that. */
2982 code = GET_CODE (SET_SRC (x));
2987 /* If we are AND'ing with a large constant that is only a single
2988 bit and the result is only being used in a context where we
2989 need to know if it is zero or non-zero, replace it with a bit
2990 extraction. This will avoid the large constant, which might
2991 have taken more than one insn to make. If the constant were
2992 not a valid argument to the AND but took only one insn to make,
2993 this is no worse, but if it took more than one insn, it will
2996 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2997 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2998 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2999 && GET_CODE (SET_DEST (x)) == REG
3000 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3001 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3002 && XEXP (*split, 0) == SET_DEST (x)
3003 && XEXP (*split, 1) == const0_rtx)
3005 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3006 XEXP (SET_SRC (x), 0),
3007 pos, NULL_RTX, 1, 1, 0, 0);
3008 if (extraction != 0)
3010 SUBST (SET_SRC (x), extraction);
3011 return find_split_point (loc, insn);
3017 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3018 is known to be on, this can be converted into a NEG of a shift. */
3019 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3020 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3021 && 1 <= (pos = exact_log2
3022 (nonzero_bits (XEXP (SET_SRC (x), 0),
3023 GET_MODE (XEXP (SET_SRC (x), 0))))))
3025 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3028 gen_rtx_combine (NEG, mode,
3029 gen_rtx_combine (LSHIFTRT, mode,
3030 XEXP (SET_SRC (x), 0),
3033 split = find_split_point (&SET_SRC (x), insn);
3034 if (split && split != &SET_SRC (x))
3040 inner = XEXP (SET_SRC (x), 0);
3042 /* We can't optimize if either mode is a partial integer
3043 mode as we don't know how many bits are significant
3045 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3046 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3050 len = GET_MODE_BITSIZE (GET_MODE (inner));
3056 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3057 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3059 inner = XEXP (SET_SRC (x), 0);
3060 len = INTVAL (XEXP (SET_SRC (x), 1));
3061 pos = INTVAL (XEXP (SET_SRC (x), 2));
3063 if (BITS_BIG_ENDIAN)
3064 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3065 unsignedp = (code == ZERO_EXTRACT);
3073 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3075 enum machine_mode mode = GET_MODE (SET_SRC (x));
3077 /* For unsigned, we have a choice of a shift followed by an
3078 AND or two shifts. Use two shifts for field sizes where the
3079 constant might be too large. We assume here that we can
3080 always at least get 8-bit constants in an AND insn, which is
3081 true for every current RISC. */
3083 if (unsignedp && len <= 8)
3088 gen_rtx_combine (LSHIFTRT, mode,
3089 gen_lowpart_for_combine (mode, inner),
3091 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3093 split = find_split_point (&SET_SRC (x), insn);
3094 if (split && split != &SET_SRC (x))
3101 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3102 gen_rtx_combine (ASHIFT, mode,
3103 gen_lowpart_for_combine (mode, inner),
3104 GEN_INT (GET_MODE_BITSIZE (mode)
3106 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3108 split = find_split_point (&SET_SRC (x), insn);
3109 if (split && split != &SET_SRC (x))
3114 /* See if this is a simple operation with a constant as the second
3115 operand. It might be that this constant is out of range and hence
3116 could be used as a split point. */
3117 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3118 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3119 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3120 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3121 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3122 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3123 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3125 return &XEXP (SET_SRC (x), 1);
3127 /* Finally, see if this is a simple operation with its first operand
3128 not in a register. The operation might require this operand in a
3129 register, so return it as a split point. We can always do this
3130 because if the first operand were another operation, we would have
3131 already found it as a split point. */
3132 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3133 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3134 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3135 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3136 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3137 return &XEXP (SET_SRC (x), 0);
3143 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3144 it is better to write this as (not (ior A B)) so we can split it.
3145 Similarly for IOR. */
3146 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3149 gen_rtx_combine (NOT, GET_MODE (x),
3150 gen_rtx_combine (code == IOR ? AND : IOR,
3152 XEXP (XEXP (x, 0), 0),
3153 XEXP (XEXP (x, 1), 0))));
3154 return find_split_point (loc, insn);
3157 /* Many RISC machines have a large set of logical insns. If the
3158 second operand is a NOT, put it first so we will try to split the
3159 other operand first. */
3160 if (GET_CODE (XEXP (x, 1)) == NOT)
3162 rtx tem = XEXP (x, 0);
3163 SUBST (XEXP (x, 0), XEXP (x, 1));
3164 SUBST (XEXP (x, 1), tem);
3172 /* Otherwise, select our actions depending on our rtx class. */
3173 switch (GET_RTX_CLASS (code))
3175 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3177 split = find_split_point (&XEXP (x, 2), insn);
3180 /* ... fall through ... */
3184 split = find_split_point (&XEXP (x, 1), insn);
3187 /* ... fall through ... */
3189 /* Some machines have (and (shift ...) ...) insns. If X is not
3190 an AND, but XEXP (X, 0) is, use it as our split point. */
3191 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3192 return &XEXP (x, 0);
3194 split = find_split_point (&XEXP (x, 0), insn);
3200 /* Otherwise, we don't have a split point. */
3204 /* Throughout X, replace FROM with TO, and return the result.
3205 The result is TO if X is FROM;
3206 otherwise the result is X, but its contents may have been modified.
3207 If they were modified, a record was made in undobuf so that
3208 undo_all will (among other things) return X to its original state.
3210 If the number of changes necessary is too much to record to undo,
3211 the excess changes are not made, so the result is invalid.
3212 The changes already made can still be undone.
3213 undobuf.num_undo is incremented for such changes, so by testing that
3214 the caller can tell whether the result is valid.
3216 `n_occurrences' is incremented each time FROM is replaced.
3218 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3220 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3221 by copying if `n_occurrences' is non-zero. */
3224 subst (x, from, to, in_dest, unique_copy)
3225 register rtx x, from, to;
3229 register enum rtx_code code = GET_CODE (x);
3230 enum machine_mode op0_mode = VOIDmode;
3231 register const char *fmt;
3232 register int len, i;
3235 /* Two expressions are equal if they are identical copies of a shared
3236 RTX or if they are both registers with the same register number
3239 #define COMBINE_RTX_EQUAL_P(X,Y) \
3241 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3242 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3244 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3247 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3250 /* If X and FROM are the same register but different modes, they will
3251 not have been seen as equal above. However, flow.c will make a
3252 LOG_LINKS entry for that case. If we do nothing, we will try to
3253 rerecognize our original insn and, when it succeeds, we will
3254 delete the feeding insn, which is incorrect.
3256 So force this insn not to match in this (rare) case. */
3257 if (! in_dest && code == REG && GET_CODE (from) == REG
3258 && REGNO (x) == REGNO (from))
3259 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3261 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3262 of which may contain things that can be combined. */
3263 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3266 /* It is possible to have a subexpression appear twice in the insn.
3267 Suppose that FROM is a register that appears within TO.
3268 Then, after that subexpression has been scanned once by `subst',
3269 the second time it is scanned, TO may be found. If we were
3270 to scan TO here, we would find FROM within it and create a
3271 self-referent rtl structure which is completely wrong. */
3272 if (COMBINE_RTX_EQUAL_P (x, to))
3275 /* Parallel asm_operands need special attention because all of the
3276 inputs are shared across the arms. Furthermore, unsharing the
3277 rtl results in recognition failures. Failure to handle this case
3278 specially can result in circular rtl.
3280 Solve this by doing a normal pass across the first entry of the
3281 parallel, and only processing the SET_DESTs of the subsequent
3284 if (code == PARALLEL
3285 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3286 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3288 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3290 /* If this substitution failed, this whole thing fails. */
3291 if (GET_CODE (new) == CLOBBER
3292 && XEXP (new, 0) == const0_rtx)
3295 SUBST (XVECEXP (x, 0, 0), new);
3297 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3299 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3301 if (GET_CODE (dest) != REG
3302 && GET_CODE (dest) != CC0
3303 && GET_CODE (dest) != PC)
3305 new = subst (dest, from, to, 0, unique_copy);
3307 /* If this substitution failed, this whole thing fails. */
3308 if (GET_CODE (new) == CLOBBER
3309 && XEXP (new, 0) == const0_rtx)
3312 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3318 len = GET_RTX_LENGTH (code);
3319 fmt = GET_RTX_FORMAT (code);
3321 /* We don't need to process a SET_DEST that is a register, CC0,
3322 or PC, so set up to skip this common case. All other cases
3323 where we want to suppress replacing something inside a
3324 SET_SRC are handled via the IN_DEST operand. */
3326 && (GET_CODE (SET_DEST (x)) == REG
3327 || GET_CODE (SET_DEST (x)) == CC0
3328 || GET_CODE (SET_DEST (x)) == PC))
3331 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3334 op0_mode = GET_MODE (XEXP (x, 0));
3336 for (i = 0; i < len; i++)
3341 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3343 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3345 new = (unique_copy && n_occurrences
3346 ? copy_rtx (to) : to);
3351 new = subst (XVECEXP (x, i, j), from, to, 0,
3354 /* If this substitution failed, this whole thing
3356 if (GET_CODE (new) == CLOBBER
3357 && XEXP (new, 0) == const0_rtx)
3361 SUBST (XVECEXP (x, i, j), new);
3364 else if (fmt[i] == 'e')
3366 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3368 /* In general, don't install a subreg involving two
3369 modes not tieable. It can worsen register
3370 allocation, and can even make invalid reload
3371 insns, since the reg inside may need to be copied
3372 from in the outside mode, and that may be invalid
3373 if it is an fp reg copied in integer mode.
3375 We allow two exceptions to this: It is valid if
3376 it is inside another SUBREG and the mode of that
3377 SUBREG and the mode of the inside of TO is
3378 tieable and it is valid if X is a SET that copies
3381 if (GET_CODE (to) == SUBREG
3382 && ! MODES_TIEABLE_P (GET_MODE (to),
3383 GET_MODE (SUBREG_REG (to)))
3384 && ! (code == SUBREG
3385 && MODES_TIEABLE_P (GET_MODE (x),
3386 GET_MODE (SUBREG_REG (to))))
3388 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3391 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3393 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3397 /* If we are in a SET_DEST, suppress most cases unless we
3398 have gone inside a MEM, in which case we want to
3399 simplify the address. We assume here that things that
3400 are actually part of the destination have their inner
3401 parts in the first expression. This is true for SUBREG,
3402 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3403 things aside from REG and MEM that should appear in a
3405 new = subst (XEXP (x, i), from, to,
3407 && (code == SUBREG || code == STRICT_LOW_PART
3408 || code == ZERO_EXTRACT))
3410 && i == 0), unique_copy);
3412 /* If we found that we will have to reject this combination,
3413 indicate that by returning the CLOBBER ourselves, rather than
3414 an expression containing it. This will speed things up as
3415 well as prevent accidents where two CLOBBERs are considered
3416 to be equal, thus producing an incorrect simplification. */
3418 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3421 SUBST (XEXP (x, i), new);
3426 /* Try to simplify X. If the simplification changed the code, it is likely
3427 that further simplification will help, so loop, but limit the number
3428 of repetitions that will be performed. */
3430 for (i = 0; i < 4; i++)
3432 /* If X is sufficiently simple, don't bother trying to do anything
3434 if (code != CONST_INT && code != REG && code != CLOBBER)
3435 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3437 if (GET_CODE (x) == code)
3440 code = GET_CODE (x);
3442 /* We no longer know the original mode of operand 0 since we
3443 have changed the form of X) */
3444 op0_mode = VOIDmode;
3450 /* Simplify X, a piece of RTL. We just operate on the expression at the
3451 outer level; call `subst' to simplify recursively. Return the new
3454 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3455 will be the iteration even if an expression with a code different from
3456 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3459 combine_simplify_rtx (x, op0_mode, last, in_dest)
3461 enum machine_mode op0_mode;
3465 enum rtx_code code = GET_CODE (x);
3466 enum machine_mode mode = GET_MODE (x);
3470 /* If this is a commutative operation, put a constant last and a complex
3471 expression first. We don't need to do this for comparisons here. */
3472 if (GET_RTX_CLASS (code) == 'c'
3473 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3474 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3475 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3476 || (GET_CODE (XEXP (x, 0)) == SUBREG
3477 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3478 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3481 SUBST (XEXP (x, 0), XEXP (x, 1));
3482 SUBST (XEXP (x, 1), temp);
3485 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3486 sign extension of a PLUS with a constant, reverse the order of the sign
3487 extension and the addition. Note that this not the same as the original
3488 code, but overflow is undefined for signed values. Also note that the
3489 PLUS will have been partially moved "inside" the sign-extension, so that
3490 the first operand of X will really look like:
3491 (ashiftrt (plus (ashift A C4) C5) C4).
3493 (plus (ashiftrt (ashift A C4) C2) C4)
3494 and replace the first operand of X with that expression. Later parts
3495 of this function may simplify the expression further.
3497 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3498 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3499 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3501 We do this to simplify address expressions. */
3503 if ((code == PLUS || code == MINUS || code == MULT)
3504 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3505 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3506 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3507 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3508 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3509 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3510 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3511 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3512 XEXP (XEXP (XEXP (x, 0), 0), 1),
3513 XEXP (XEXP (x, 0), 1))) != 0)
3516 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3517 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3518 INTVAL (XEXP (XEXP (x, 0), 1)));
3520 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3521 INTVAL (XEXP (XEXP (x, 0), 1)));
3523 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3526 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3527 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3528 things. Check for cases where both arms are testing the same
3531 Don't do anything if all operands are very simple. */
3533 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3534 || GET_RTX_CLASS (code) == '<')
3535 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3536 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3537 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3539 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3540 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3541 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3543 || (GET_RTX_CLASS (code) == '1'
3544 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3545 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3546 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3549 rtx cond, true, false;
3551 cond = if_then_else_cond (x, &true, &false);
3553 /* If everything is a comparison, what we have is highly unlikely
3554 to be simpler, so don't use it. */
3555 && ! (GET_RTX_CLASS (code) == '<'
3556 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3557 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3559 rtx cop1 = const0_rtx;
3560 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3562 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3565 /* Simplify the alternative arms; this may collapse the true and
3566 false arms to store-flag values. */
3567 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3568 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3570 /* Restarting if we generate a store-flag expression will cause
3571 us to loop. Just drop through in this case. */
3573 /* If the result values are STORE_FLAG_VALUE and zero, we can
3574 just make the comparison operation. */
3575 if (true == const_true_rtx && false == const0_rtx)
3576 x = gen_binary (cond_code, mode, cond, cop1);
3577 else if (true == const0_rtx && false == const_true_rtx)
3578 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3580 /* Likewise, we can make the negate of a comparison operation
3581 if the result values are - STORE_FLAG_VALUE and zero. */
3582 else if (GET_CODE (true) == CONST_INT
3583 && INTVAL (true) == - STORE_FLAG_VALUE
3584 && false == const0_rtx)
3585 x = gen_unary (NEG, mode, mode,
3586 gen_binary (cond_code, mode, cond, cop1));
3587 else if (GET_CODE (false) == CONST_INT
3588 && INTVAL (false) == - STORE_FLAG_VALUE
3589 && true == const0_rtx)
3590 x = gen_unary (NEG, mode, mode,
3591 gen_binary (reverse_condition (cond_code),
3594 return gen_rtx_IF_THEN_ELSE (mode,
3595 gen_binary (cond_code, VOIDmode,
3599 code = GET_CODE (x);
3600 op0_mode = VOIDmode;
3604 /* Try to fold this expression in case we have constants that weren't
3607 switch (GET_RTX_CLASS (code))
3610 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3613 temp = simplify_relational_operation (code, op0_mode,
3614 XEXP (x, 0), XEXP (x, 1));
3615 #ifdef FLOAT_STORE_FLAG_VALUE
3616 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3618 if (temp == const0_rtx)
3619 temp = CONST0_RTX (mode);
3621 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3627 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3631 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3632 XEXP (x, 1), XEXP (x, 2));
3637 x = temp, code = GET_CODE (temp);
3639 /* First see if we can apply the inverse distributive law. */
3640 if (code == PLUS || code == MINUS
3641 || code == AND || code == IOR || code == XOR)
3643 x = apply_distributive_law (x);
3644 code = GET_CODE (x);
3647 /* If CODE is an associative operation not otherwise handled, see if we
3648 can associate some operands. This can win if they are constants or
3649 if they are logically related (i.e. (a & b) & a. */
3650 if ((code == PLUS || code == MINUS
3651 || code == MULT || code == AND || code == IOR || code == XOR
3652 || code == DIV || code == UDIV
3653 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3654 && INTEGRAL_MODE_P (mode))
3656 if (GET_CODE (XEXP (x, 0)) == code)
3658 rtx other = XEXP (XEXP (x, 0), 0);
3659 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3660 rtx inner_op1 = XEXP (x, 1);
3663 /* Make sure we pass the constant operand if any as the second
3664 one if this is a commutative operation. */
3665 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3667 rtx tem = inner_op0;
3668 inner_op0 = inner_op1;
3671 inner = simplify_binary_operation (code == MINUS ? PLUS
3672 : code == DIV ? MULT
3673 : code == UDIV ? MULT
3675 mode, inner_op0, inner_op1);
3677 /* For commutative operations, try the other pair if that one
3679 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3681 other = XEXP (XEXP (x, 0), 1);
3682 inner = simplify_binary_operation (code, mode,
3683 XEXP (XEXP (x, 0), 0),
3688 return gen_binary (code, mode, other, inner);
3692 /* A little bit of algebraic simplification here. */
3696 /* Ensure that our address has any ASHIFTs converted to MULT in case
3697 address-recognizing predicates are called later. */
3698 temp = make_compound_operation (XEXP (x, 0), MEM);
3699 SUBST (XEXP (x, 0), temp);
3703 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3704 is paradoxical. If we can't do that safely, then it becomes
3705 something nonsensical so that this combination won't take place. */
3707 if (GET_CODE (SUBREG_REG (x)) == MEM
3708 && (GET_MODE_SIZE (mode)
3709 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3711 rtx inner = SUBREG_REG (x);
3712 int endian_offset = 0;
3713 /* Don't change the mode of the MEM
3714 if that would change the meaning of the address. */
3715 if (MEM_VOLATILE_P (SUBREG_REG (x))
3716 || mode_dependent_address_p (XEXP (inner, 0)))
3717 return gen_rtx_CLOBBER (mode, const0_rtx);
3719 if (BYTES_BIG_ENDIAN)
3721 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3722 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3723 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3724 endian_offset -= (UNITS_PER_WORD
3725 - GET_MODE_SIZE (GET_MODE (inner)));
3727 /* Note if the plus_constant doesn't make a valid address
3728 then this combination won't be accepted. */
3729 x = gen_rtx_MEM (mode,
3730 plus_constant (XEXP (inner, 0),
3731 (SUBREG_WORD (x) * UNITS_PER_WORD
3733 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3734 MEM_COPY_ATTRIBUTES (x, inner);
3738 /* If we are in a SET_DEST, these other cases can't apply. */
3742 /* Changing mode twice with SUBREG => just change it once,
3743 or not at all if changing back to starting mode. */
3744 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3746 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3747 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3748 return SUBREG_REG (SUBREG_REG (x));
3750 SUBST_INT (SUBREG_WORD (x),
3751 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3752 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3755 /* SUBREG of a hard register => just change the register number
3756 and/or mode. If the hard register is not valid in that mode,
3757 suppress this combination. If the hard register is the stack,
3758 frame, or argument pointer, leave this as a SUBREG. */
3760 if (GET_CODE (SUBREG_REG (x)) == REG
3761 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3762 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3763 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3764 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3766 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3767 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3769 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3771 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3773 return gen_rtx_REG (mode,
3774 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3776 return gen_rtx_CLOBBER (mode, const0_rtx);
3779 /* For a constant, try to pick up the part we want. Handle a full
3780 word and low-order part. Only do this if we are narrowing
3781 the constant; if it is being widened, we have no idea what
3782 the extra bits will have been set to. */
3784 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3785 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3786 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3787 && GET_MODE_CLASS (mode) == MODE_INT)
3789 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3795 /* If we want a subreg of a constant, at offset 0,
3796 take the low bits. On a little-endian machine, that's
3797 always valid. On a big-endian machine, it's valid
3798 only if the constant's mode fits in one word. Note that we
3799 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3800 if (CONSTANT_P (SUBREG_REG (x))
3801 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3802 || ! WORDS_BIG_ENDIAN)
3803 ? SUBREG_WORD (x) == 0
3805 == ((GET_MODE_SIZE (op0_mode)
3806 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3808 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3809 && (! WORDS_BIG_ENDIAN
3810 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3811 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3813 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3814 since we are saying that the high bits don't matter. */
3815 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3816 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3818 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3819 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3820 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3821 return SUBREG_REG (x);
3824 /* Note that we cannot do any narrowing for non-constants since
3825 we might have been counting on using the fact that some bits were
3826 zero. We now do this in the SET. */
3831 /* (not (plus X -1)) can become (neg X). */
3832 if (GET_CODE (XEXP (x, 0)) == PLUS
3833 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3834 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3836 /* Similarly, (not (neg X)) is (plus X -1). */
3837 if (GET_CODE (XEXP (x, 0)) == NEG)
3838 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3841 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3842 if (GET_CODE (XEXP (x, 0)) == XOR
3843 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3844 && (temp = simplify_unary_operation (NOT, mode,
3845 XEXP (XEXP (x, 0), 1),
3847 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3849 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3850 other than 1, but that is not valid. We could do a similar
3851 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3852 but this doesn't seem common enough to bother with. */
3853 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3854 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3855 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3856 XEXP (XEXP (x, 0), 1));
3858 if (GET_CODE (XEXP (x, 0)) == SUBREG
3859 && subreg_lowpart_p (XEXP (x, 0))
3860 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3861 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3862 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3863 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3865 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3867 x = gen_rtx_ROTATE (inner_mode,
3868 gen_unary (NOT, inner_mode, inner_mode,
3870 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3871 return gen_lowpart_for_combine (mode, x);
3874 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3875 reversing the comparison code if valid. */
3876 if (STORE_FLAG_VALUE == -1
3877 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3878 && reversible_comparison_p (XEXP (x, 0)))
3879 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3880 mode, XEXP (XEXP (x, 0), 0),
3881 XEXP (XEXP (x, 0), 1));
3883 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3884 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3885 perform the above simplification. */
3887 if (STORE_FLAG_VALUE == -1
3888 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3889 && XEXP (x, 1) == const1_rtx
3890 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3891 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3892 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3894 /* Apply De Morgan's laws to reduce number of patterns for machines
3895 with negating logical insns (and-not, nand, etc.). If result has
3896 only one NOT, put it first, since that is how the patterns are
3899 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3901 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3903 if (GET_CODE (in1) == NOT)
3904 in1 = XEXP (in1, 0);
3906 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3908 if (GET_CODE (in2) == NOT)
3909 in2 = XEXP (in2, 0);
3910 else if (GET_CODE (in2) == CONST_INT
3911 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3912 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3914 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3916 if (GET_CODE (in2) == NOT)
3919 in2 = in1; in1 = tem;
3922 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3928 /* (neg (plus X 1)) can become (not X). */
3929 if (GET_CODE (XEXP (x, 0)) == PLUS
3930 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3931 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3933 /* Similarly, (neg (not X)) is (plus X 1). */
3934 if (GET_CODE (XEXP (x, 0)) == NOT)
3935 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3937 /* (neg (minus X Y)) can become (minus Y X). */
3938 if (GET_CODE (XEXP (x, 0)) == MINUS
3939 && (! FLOAT_MODE_P (mode)
3940 /* x-y != -(y-x) with IEEE floating point. */
3941 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3943 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3944 XEXP (XEXP (x, 0), 0));
3946 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3947 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3948 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3949 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3951 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3952 if we can then eliminate the NEG (e.g.,
3953 if the operand is a constant). */
3955 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3957 temp = simplify_unary_operation (NEG, mode,
3958 XEXP (XEXP (x, 0), 0), mode);
3961 SUBST (XEXP (XEXP (x, 0), 0), temp);
3966 temp = expand_compound_operation (XEXP (x, 0));
3968 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3969 replaced by (lshiftrt X C). This will convert
3970 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3972 if (GET_CODE (temp) == ASHIFTRT
3973 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3974 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3975 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3976 INTVAL (XEXP (temp, 1)));
3978 /* If X has only a single bit that might be nonzero, say, bit I, convert
3979 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3980 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3981 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3982 or a SUBREG of one since we'd be making the expression more
3983 complex if it was just a register. */
3985 if (GET_CODE (temp) != REG
3986 && ! (GET_CODE (temp) == SUBREG
3987 && GET_CODE (SUBREG_REG (temp)) == REG)
3988 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3990 rtx temp1 = simplify_shift_const
3991 (NULL_RTX, ASHIFTRT, mode,
3992 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3993 GET_MODE_BITSIZE (mode) - 1 - i),
3994 GET_MODE_BITSIZE (mode) - 1 - i);
3996 /* If all we did was surround TEMP with the two shifts, we
3997 haven't improved anything, so don't use it. Otherwise,
3998 we are better off with TEMP1. */
3999 if (GET_CODE (temp1) != ASHIFTRT
4000 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4001 || XEXP (XEXP (temp1, 0), 0) != temp)
4007 /* We can't handle truncation to a partial integer mode here
4008 because we don't know the real bitsize of the partial
4010 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4013 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4014 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4015 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4017 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4018 GET_MODE_MASK (mode), NULL_RTX, 0));
4020 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4021 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4022 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4023 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4024 return XEXP (XEXP (x, 0), 0);
4026 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4027 (OP:SI foo:SI) if OP is NEG or ABS. */
4028 if ((GET_CODE (XEXP (x, 0)) == ABS
4029 || GET_CODE (XEXP (x, 0)) == NEG)
4030 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4031 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4032 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4033 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4034 XEXP (XEXP (XEXP (x, 0), 0), 0));
4036 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4038 if (GET_CODE (XEXP (x, 0)) == SUBREG
4039 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4040 && subreg_lowpart_p (XEXP (x, 0)))
4041 return SUBREG_REG (XEXP (x, 0));
4043 /* If we know that the value is already truncated, we can
4044 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4045 is nonzero for the corresponding modes. But don't do this
4046 for an (LSHIFTRT (MULT ...)) since this will cause problems
4047 with the umulXi3_highpart patterns. */
4048 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4049 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4050 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4051 >= GET_MODE_BITSIZE (mode) + 1
4052 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4053 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4054 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4056 /* A truncate of a comparison can be replaced with a subreg if
4057 STORE_FLAG_VALUE permits. This is like the previous test,
4058 but it works even if the comparison is done in a mode larger
4059 than HOST_BITS_PER_WIDE_INT. */
4060 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4061 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4062 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4063 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4065 /* Similarly, a truncate of a register whose value is a
4066 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4068 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4069 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4070 && (temp = get_last_value (XEXP (x, 0)))
4071 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4072 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4076 case FLOAT_TRUNCATE:
4077 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4078 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4079 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4080 return XEXP (XEXP (x, 0), 0);
4082 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4083 (OP:SF foo:SF) if OP is NEG or ABS. */
4084 if ((GET_CODE (XEXP (x, 0)) == ABS
4085 || GET_CODE (XEXP (x, 0)) == NEG)
4086 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4087 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4088 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4089 XEXP (XEXP (XEXP (x, 0), 0), 0));
4091 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4092 is (float_truncate:SF x). */
4093 if (GET_CODE (XEXP (x, 0)) == SUBREG
4094 && subreg_lowpart_p (XEXP (x, 0))
4095 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4096 return SUBREG_REG (XEXP (x, 0));
4101 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4102 using cc0, in which case we want to leave it as a COMPARE
4103 so we can distinguish it from a register-register-copy. */
4104 if (XEXP (x, 1) == const0_rtx)
4107 /* In IEEE floating point, x-0 is not the same as x. */
4108 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4109 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4111 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4117 /* (const (const X)) can become (const X). Do it this way rather than
4118 returning the inner CONST since CONST can be shared with a
4120 if (GET_CODE (XEXP (x, 0)) == CONST)
4121 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4126 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4127 can add in an offset. find_split_point will split this address up
4128 again if it doesn't match. */
4129 if (GET_CODE (XEXP (x, 0)) == HIGH
4130 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4136 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4137 outermost. That's because that's the way indexed addresses are
4138 supposed to appear. This code used to check many more cases, but
4139 they are now checked elsewhere. */
4140 if (GET_CODE (XEXP (x, 0)) == PLUS
4141 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4142 return gen_binary (PLUS, mode,
4143 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4145 XEXP (XEXP (x, 0), 1));
4147 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4148 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4149 bit-field and can be replaced by either a sign_extend or a
4150 sign_extract. The `and' may be a zero_extend and the two
4151 <c>, -<c> constants may be reversed. */
4152 if (GET_CODE (XEXP (x, 0)) == XOR
4153 && GET_CODE (XEXP (x, 1)) == CONST_INT
4154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4155 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4156 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4157 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4158 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4159 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4160 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4161 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4162 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4163 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4164 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4165 == (unsigned int) i + 1))))
4166 return simplify_shift_const
4167 (NULL_RTX, ASHIFTRT, mode,
4168 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4169 XEXP (XEXP (XEXP (x, 0), 0), 0),
4170 GET_MODE_BITSIZE (mode) - (i + 1)),
4171 GET_MODE_BITSIZE (mode) - (i + 1));
4173 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4174 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4175 is 1. This produces better code than the alternative immediately
4177 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4178 && reversible_comparison_p (XEXP (x, 0))
4179 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4180 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4182 gen_unary (NEG, mode, mode,
4183 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4184 mode, XEXP (XEXP (x, 0), 0),
4185 XEXP (XEXP (x, 0), 1)));
4187 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4188 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4189 the bitsize of the mode - 1. This allows simplification of
4190 "a = (b & 8) == 0;" */
4191 if (XEXP (x, 1) == constm1_rtx
4192 && GET_CODE (XEXP (x, 0)) != REG
4193 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4194 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4195 && nonzero_bits (XEXP (x, 0), mode) == 1)
4196 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4197 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4198 gen_rtx_combine (XOR, mode,
4199 XEXP (x, 0), const1_rtx),
4200 GET_MODE_BITSIZE (mode) - 1),
4201 GET_MODE_BITSIZE (mode) - 1);
4203 /* If we are adding two things that have no bits in common, convert
4204 the addition into an IOR. This will often be further simplified,
4205 for example in cases like ((a & 1) + (a & 2)), which can
4208 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4209 && (nonzero_bits (XEXP (x, 0), mode)
4210 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4211 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4215 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4216 by reversing the comparison code if valid. */
4217 if (STORE_FLAG_VALUE == 1
4218 && XEXP (x, 0) == const1_rtx
4219 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4220 && reversible_comparison_p (XEXP (x, 1)))
4221 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4222 mode, XEXP (XEXP (x, 1), 0),
4223 XEXP (XEXP (x, 1), 1));
4225 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4226 (and <foo> (const_int pow2-1)) */
4227 if (GET_CODE (XEXP (x, 1)) == AND
4228 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4229 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4230 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4231 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4232 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4234 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4236 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4237 return gen_binary (MINUS, mode,
4238 gen_binary (MINUS, mode, XEXP (x, 0),
4239 XEXP (XEXP (x, 1), 0)),
4240 XEXP (XEXP (x, 1), 1));
4244 /* If we have (mult (plus A B) C), apply the distributive law and then
4245 the inverse distributive law to see if things simplify. This
4246 occurs mostly in addresses, often when unrolling loops. */
4248 if (GET_CODE (XEXP (x, 0)) == PLUS)
4250 x = apply_distributive_law
4251 (gen_binary (PLUS, mode,
4252 gen_binary (MULT, mode,
4253 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4254 gen_binary (MULT, mode,
4255 XEXP (XEXP (x, 0), 1),
4256 copy_rtx (XEXP (x, 1)))));
4258 if (GET_CODE (x) != MULT)
4264 /* If this is a divide by a power of two, treat it as a shift if
4265 its first operand is a shift. */
4266 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4267 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4268 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4269 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4270 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4271 || GET_CODE (XEXP (x, 0)) == ROTATE
4272 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4273 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4277 case GT: case GTU: case GE: case GEU:
4278 case LT: case LTU: case LE: case LEU:
4279 /* If the first operand is a condition code, we can't do anything
4281 if (GET_CODE (XEXP (x, 0)) == COMPARE
4282 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4284 && XEXP (x, 0) != cc0_rtx
4288 rtx op0 = XEXP (x, 0);
4289 rtx op1 = XEXP (x, 1);
4290 enum rtx_code new_code;
4292 if (GET_CODE (op0) == COMPARE)
4293 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4295 /* Simplify our comparison, if possible. */
4296 new_code = simplify_comparison (code, &op0, &op1);
4298 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4299 if only the low-order bit is possibly nonzero in X (such as when
4300 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4301 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4302 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4305 Remove any ZERO_EXTRACT we made when thinking this was a
4306 comparison. It may now be simpler to use, e.g., an AND. If a
4307 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4308 the call to make_compound_operation in the SET case. */
4310 if (STORE_FLAG_VALUE == 1
4311 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4312 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4313 return gen_lowpart_for_combine (mode,
4314 expand_compound_operation (op0));
4316 else if (STORE_FLAG_VALUE == 1
4317 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4318 && op1 == const0_rtx
4319 && (num_sign_bit_copies (op0, mode)
4320 == GET_MODE_BITSIZE (mode)))
4322 op0 = expand_compound_operation (op0);
4323 return gen_unary (NEG, mode, mode,
4324 gen_lowpart_for_combine (mode, op0));
4327 else if (STORE_FLAG_VALUE == 1
4328 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4329 && op1 == const0_rtx
4330 && nonzero_bits (op0, mode) == 1)
4332 op0 = expand_compound_operation (op0);
4333 return gen_binary (XOR, mode,
4334 gen_lowpart_for_combine (mode, op0),
4338 else if (STORE_FLAG_VALUE == 1
4339 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4340 && op1 == const0_rtx
4341 && (num_sign_bit_copies (op0, mode)
4342 == GET_MODE_BITSIZE (mode)))
4344 op0 = expand_compound_operation (op0);
4345 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4348 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4350 if (STORE_FLAG_VALUE == -1
4351 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4352 && op1 == const0_rtx
4353 && (num_sign_bit_copies (op0, mode)
4354 == GET_MODE_BITSIZE (mode)))
4355 return gen_lowpart_for_combine (mode,
4356 expand_compound_operation (op0));
4358 else if (STORE_FLAG_VALUE == -1
4359 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4360 && op1 == const0_rtx
4361 && nonzero_bits (op0, mode) == 1)
4363 op0 = expand_compound_operation (op0);
4364 return gen_unary (NEG, mode, mode,
4365 gen_lowpart_for_combine (mode, op0));
4368 else if (STORE_FLAG_VALUE == -1
4369 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4370 && op1 == const0_rtx
4371 && (num_sign_bit_copies (op0, mode)
4372 == GET_MODE_BITSIZE (mode)))
4374 op0 = expand_compound_operation (op0);
4375 return gen_unary (NOT, mode, mode,
4376 gen_lowpart_for_combine (mode, op0));
4379 /* If X is 0/1, (eq X 0) is X-1. */
4380 else if (STORE_FLAG_VALUE == -1
4381 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4382 && op1 == const0_rtx
4383 && nonzero_bits (op0, mode) == 1)
4385 op0 = expand_compound_operation (op0);
4386 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4389 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4390 one bit that might be nonzero, we can convert (ne x 0) to
4391 (ashift x c) where C puts the bit in the sign bit. Remove any
4392 AND with STORE_FLAG_VALUE when we are done, since we are only
4393 going to test the sign bit. */
4394 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4395 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4396 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4397 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4398 && op1 == const0_rtx
4399 && mode == GET_MODE (op0)
4400 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4402 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4403 expand_compound_operation (op0),
4404 GET_MODE_BITSIZE (mode) - 1 - i);
4405 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4411 /* If the code changed, return a whole new comparison. */
4412 if (new_code != code)
4413 return gen_rtx_combine (new_code, mode, op0, op1);
4415 /* Otherwise, keep this operation, but maybe change its operands.
4416 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4417 SUBST (XEXP (x, 0), op0);
4418 SUBST (XEXP (x, 1), op1);
4423 return simplify_if_then_else (x);
4429 /* If we are processing SET_DEST, we are done. */
4433 return expand_compound_operation (x);
4436 return simplify_set (x);
4441 return simplify_logical (x, last);
4444 /* (abs (neg <foo>)) -> (abs <foo>) */
4445 if (GET_CODE (XEXP (x, 0)) == NEG)
4446 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4448 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4450 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4453 /* If operand is something known to be positive, ignore the ABS. */
4454 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4455 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4456 <= HOST_BITS_PER_WIDE_INT)
4457 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4458 & ((HOST_WIDE_INT) 1
4459 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4464 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4465 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4466 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4471 /* (ffs (*_extend <X>)) = (ffs <X>) */
4472 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4473 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4474 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4478 /* (float (sign_extend <X>)) = (float <X>). */
4479 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4480 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4488 /* If this is a shift by a constant amount, simplify it. */
4489 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4490 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4491 INTVAL (XEXP (x, 1)));
4493 #ifdef SHIFT_COUNT_TRUNCATED
4494 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4496 force_to_mode (XEXP (x, 1), GET_MODE (x),
4498 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4512 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4515 simplify_if_then_else (x)
4518 enum machine_mode mode = GET_MODE (x);
4519 rtx cond = XEXP (x, 0);
4520 rtx true = XEXP (x, 1);
4521 rtx false = XEXP (x, 2);
4522 enum rtx_code true_code = GET_CODE (cond);
4523 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4527 /* Simplify storing of the truth value. */
4528 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4529 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4531 /* Also when the truth value has to be reversed. */
4532 if (comparison_p && reversible_comparison_p (cond)
4533 && true == const0_rtx && false == const_true_rtx)
4534 return gen_binary (reverse_condition (true_code),
4535 mode, XEXP (cond, 0), XEXP (cond, 1));
4537 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4538 in it is being compared against certain values. Get the true and false
4539 comparisons and see if that says anything about the value of each arm. */
4541 if (comparison_p && reversible_comparison_p (cond)
4542 && GET_CODE (XEXP (cond, 0)) == REG)
4545 rtx from = XEXP (cond, 0);
4546 enum rtx_code false_code = reverse_condition (true_code);
4547 rtx true_val = XEXP (cond, 1);
4548 rtx false_val = true_val;
4551 /* If FALSE_CODE is EQ, swap the codes and arms. */
4553 if (false_code == EQ)
4555 swapped = 1, true_code = EQ, false_code = NE;
4556 temp = true, true = false, false = temp;
4559 /* If we are comparing against zero and the expression being tested has
4560 only a single bit that might be nonzero, that is its value when it is
4561 not equal to zero. Similarly if it is known to be -1 or 0. */
4563 if (true_code == EQ && true_val == const0_rtx
4564 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4565 false_code = EQ, false_val = GEN_INT (nzb);
4566 else if (true_code == EQ && true_val == const0_rtx
4567 && (num_sign_bit_copies (from, GET_MODE (from))
4568 == GET_MODE_BITSIZE (GET_MODE (from))))
4569 false_code = EQ, false_val = constm1_rtx;
4571 /* Now simplify an arm if we know the value of the register in the
4572 branch and it is used in the arm. Be careful due to the potential
4573 of locally-shared RTL. */
4575 if (reg_mentioned_p (from, true))
4576 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4577 pc_rtx, pc_rtx, 0, 0);
4578 if (reg_mentioned_p (from, false))
4579 false = subst (known_cond (copy_rtx (false), false_code,
4581 pc_rtx, pc_rtx, 0, 0);
4583 SUBST (XEXP (x, 1), swapped ? false : true);
4584 SUBST (XEXP (x, 2), swapped ? true : false);
4586 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4589 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4590 reversed, do so to avoid needing two sets of patterns for
4591 subtract-and-branch insns. Similarly if we have a constant in the true
4592 arm, the false arm is the same as the first operand of the comparison, or
4593 the false arm is more complicated than the true arm. */
4595 if (comparison_p && reversible_comparison_p (cond)
4597 || (CONSTANT_P (true)
4598 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4599 || true == const0_rtx
4600 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4601 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4602 || (GET_CODE (true) == SUBREG
4603 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4604 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4605 || reg_mentioned_p (true, false)
4606 || rtx_equal_p (false, XEXP (cond, 0))))
4608 true_code = reverse_condition (true_code);
4610 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4613 SUBST (XEXP (x, 1), false);
4614 SUBST (XEXP (x, 2), true);
4616 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4618 /* It is possible that the conditional has been simplified out. */
4619 true_code = GET_CODE (cond);
4620 comparison_p = GET_RTX_CLASS (true_code) == '<';
4623 /* If the two arms are identical, we don't need the comparison. */
4625 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4628 /* Convert a == b ? b : a to "a". */
4629 if (true_code == EQ && ! side_effects_p (cond)
4630 && rtx_equal_p (XEXP (cond, 0), false)
4631 && rtx_equal_p (XEXP (cond, 1), true))
4633 else if (true_code == NE && ! side_effects_p (cond)
4634 && rtx_equal_p (XEXP (cond, 0), true)
4635 && rtx_equal_p (XEXP (cond, 1), false))
4638 /* Look for cases where we have (abs x) or (neg (abs X)). */
4640 if (GET_MODE_CLASS (mode) == MODE_INT
4641 && GET_CODE (false) == NEG
4642 && rtx_equal_p (true, XEXP (false, 0))
4644 && rtx_equal_p (true, XEXP (cond, 0))
4645 && ! side_effects_p (true))
4650 return gen_unary (ABS, mode, mode, true);
4653 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4658 /* Look for MIN or MAX. */
4660 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4662 && rtx_equal_p (XEXP (cond, 0), true)
4663 && rtx_equal_p (XEXP (cond, 1), false)
4664 && ! side_effects_p (cond))
4669 return gen_binary (SMAX, mode, true, false);
4672 return gen_binary (SMIN, mode, true, false);
4675 return gen_binary (UMAX, mode, true, false);
4678 return gen_binary (UMIN, mode, true, false);
4683 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4684 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4685 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4686 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4687 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4688 neither 1 or -1, but it isn't worth checking for. */
4690 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4691 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4693 rtx t = make_compound_operation (true, SET);
4694 rtx f = make_compound_operation (false, SET);
4695 rtx cond_op0 = XEXP (cond, 0);
4696 rtx cond_op1 = XEXP (cond, 1);
4697 enum rtx_code op = NIL, extend_op = NIL;
4698 enum machine_mode m = mode;
4699 rtx z = 0, c1 = NULL_RTX;
4701 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4702 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4703 || GET_CODE (t) == ASHIFT
4704 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4705 && rtx_equal_p (XEXP (t, 0), f))
4706 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4708 /* If an identity-zero op is commutative, check whether there
4709 would be a match if we swapped the operands. */
4710 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4711 || GET_CODE (t) == XOR)
4712 && rtx_equal_p (XEXP (t, 1), f))
4713 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4714 else if (GET_CODE (t) == SIGN_EXTEND
4715 && (GET_CODE (XEXP (t, 0)) == PLUS
4716 || GET_CODE (XEXP (t, 0)) == MINUS
4717 || GET_CODE (XEXP (t, 0)) == IOR
4718 || GET_CODE (XEXP (t, 0)) == XOR
4719 || GET_CODE (XEXP (t, 0)) == ASHIFT
4720 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4721 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4722 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4723 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4724 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4725 && (num_sign_bit_copies (f, GET_MODE (f))
4726 > (GET_MODE_BITSIZE (mode)
4727 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4729 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4730 extend_op = SIGN_EXTEND;
4731 m = GET_MODE (XEXP (t, 0));
4733 else if (GET_CODE (t) == SIGN_EXTEND
4734 && (GET_CODE (XEXP (t, 0)) == PLUS
4735 || GET_CODE (XEXP (t, 0)) == IOR
4736 || GET_CODE (XEXP (t, 0)) == XOR)
4737 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4738 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4739 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4740 && (num_sign_bit_copies (f, GET_MODE (f))
4741 > (GET_MODE_BITSIZE (mode)
4742 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4744 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4745 extend_op = SIGN_EXTEND;
4746 m = GET_MODE (XEXP (t, 0));
4748 else if (GET_CODE (t) == ZERO_EXTEND
4749 && (GET_CODE (XEXP (t, 0)) == PLUS
4750 || GET_CODE (XEXP (t, 0)) == MINUS
4751 || GET_CODE (XEXP (t, 0)) == IOR
4752 || GET_CODE (XEXP (t, 0)) == XOR
4753 || GET_CODE (XEXP (t, 0)) == ASHIFT
4754 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4755 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4756 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4757 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4758 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4759 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4760 && ((nonzero_bits (f, GET_MODE (f))
4761 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4764 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4765 extend_op = ZERO_EXTEND;
4766 m = GET_MODE (XEXP (t, 0));
4768 else if (GET_CODE (t) == ZERO_EXTEND
4769 && (GET_CODE (XEXP (t, 0)) == PLUS
4770 || GET_CODE (XEXP (t, 0)) == IOR
4771 || GET_CODE (XEXP (t, 0)) == XOR)
4772 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4773 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4774 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4775 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4776 && ((nonzero_bits (f, GET_MODE (f))
4777 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4780 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4781 extend_op = ZERO_EXTEND;
4782 m = GET_MODE (XEXP (t, 0));
4787 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4788 pc_rtx, pc_rtx, 0, 0);
4789 temp = gen_binary (MULT, m, temp,
4790 gen_binary (MULT, m, c1, const_true_rtx));
4791 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4792 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4794 if (extend_op != NIL)
4795 temp = gen_unary (extend_op, mode, m, temp);
4801 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4802 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4803 negation of a single bit, we can convert this operation to a shift. We
4804 can actually do this more generally, but it doesn't seem worth it. */
4806 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4807 && false == const0_rtx && GET_CODE (true) == CONST_INT
4808 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4809 && (i = exact_log2 (INTVAL (true))) >= 0)
4810 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4811 == GET_MODE_BITSIZE (mode))
4812 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4814 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4815 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4820 /* Simplify X, a SET expression. Return the new expression. */
4826 rtx src = SET_SRC (x);
4827 rtx dest = SET_DEST (x);
4828 enum machine_mode mode
4829 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4833 /* (set (pc) (return)) gets written as (return). */
4834 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4837 /* Now that we know for sure which bits of SRC we are using, see if we can
4838 simplify the expression for the object knowing that we only need the
4841 if (GET_MODE_CLASS (mode) == MODE_INT)
4843 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4844 SUBST (SET_SRC (x), src);
4847 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4848 the comparison result and try to simplify it unless we already have used
4849 undobuf.other_insn. */
4850 if ((GET_CODE (src) == COMPARE
4855 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4856 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4857 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4858 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4860 enum rtx_code old_code = GET_CODE (*cc_use);
4861 enum rtx_code new_code;
4863 int other_changed = 0;
4864 enum machine_mode compare_mode = GET_MODE (dest);
4866 if (GET_CODE (src) == COMPARE)
4867 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4869 op0 = src, op1 = const0_rtx;
4871 /* Simplify our comparison, if possible. */
4872 new_code = simplify_comparison (old_code, &op0, &op1);
4874 #ifdef EXTRA_CC_MODES
4875 /* If this machine has CC modes other than CCmode, check to see if we
4876 need to use a different CC mode here. */
4877 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4878 #endif /* EXTRA_CC_MODES */
4880 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4881 /* If the mode changed, we have to change SET_DEST, the mode in the
4882 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4883 a hard register, just build new versions with the proper mode. If it
4884 is a pseudo, we lose unless it is only time we set the pseudo, in
4885 which case we can safely change its mode. */
4886 if (compare_mode != GET_MODE (dest))
4888 unsigned int regno = REGNO (dest);
4889 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4891 if (regno < FIRST_PSEUDO_REGISTER
4892 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4894 if (regno >= FIRST_PSEUDO_REGISTER)
4895 SUBST (regno_reg_rtx[regno], new_dest);
4897 SUBST (SET_DEST (x), new_dest);
4898 SUBST (XEXP (*cc_use, 0), new_dest);
4906 /* If the code changed, we have to build a new comparison in
4907 undobuf.other_insn. */
4908 if (new_code != old_code)
4910 unsigned HOST_WIDE_INT mask;
4912 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4915 /* If the only change we made was to change an EQ into an NE or
4916 vice versa, OP0 has only one bit that might be nonzero, and OP1
4917 is zero, check if changing the user of the condition code will
4918 produce a valid insn. If it won't, we can keep the original code
4919 in that insn by surrounding our operation with an XOR. */
4921 if (((old_code == NE && new_code == EQ)
4922 || (old_code == EQ && new_code == NE))
4923 && ! other_changed && op1 == const0_rtx
4924 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4925 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4927 rtx pat = PATTERN (other_insn), note = 0;
4929 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4930 && ! check_asm_operands (pat)))
4932 PUT_CODE (*cc_use, old_code);
4935 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4943 undobuf.other_insn = other_insn;
4946 /* If we are now comparing against zero, change our source if
4947 needed. If we do not use cc0, we always have a COMPARE. */
4948 if (op1 == const0_rtx && dest == cc0_rtx)
4950 SUBST (SET_SRC (x), op0);
4956 /* Otherwise, if we didn't previously have a COMPARE in the
4957 correct mode, we need one. */
4958 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4961 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4966 /* Otherwise, update the COMPARE if needed. */
4967 SUBST (XEXP (src, 0), op0);
4968 SUBST (XEXP (src, 1), op1);
4973 /* Get SET_SRC in a form where we have placed back any
4974 compound expressions. Then do the checks below. */
4975 src = make_compound_operation (src, SET);
4976 SUBST (SET_SRC (x), src);
4979 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4980 and X being a REG or (subreg (reg)), we may be able to convert this to
4981 (set (subreg:m2 x) (op)).
4983 We can always do this if M1 is narrower than M2 because that means that
4984 we only care about the low bits of the result.
4986 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4987 perform a narrower operation than requested since the high-order bits will
4988 be undefined. On machine where it is defined, this transformation is safe
4989 as long as M1 and M2 have the same number of words. */
4991 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4992 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4993 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4995 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4996 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4997 #ifndef WORD_REGISTER_OPERATIONS
4998 && (GET_MODE_SIZE (GET_MODE (src))
4999 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5001 #ifdef CLASS_CANNOT_CHANGE_SIZE
5002 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5003 && (TEST_HARD_REG_BIT
5004 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
5006 && (GET_MODE_SIZE (GET_MODE (src))
5007 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
5009 && (GET_CODE (dest) == REG
5010 || (GET_CODE (dest) == SUBREG
5011 && GET_CODE (SUBREG_REG (dest)) == REG)))
5013 SUBST (SET_DEST (x),
5014 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5016 SUBST (SET_SRC (x), SUBREG_REG (src));
5018 src = SET_SRC (x), dest = SET_DEST (x);
5021 #ifdef LOAD_EXTEND_OP
5022 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5023 would require a paradoxical subreg. Replace the subreg with a
5024 zero_extend to avoid the reload that would otherwise be required. */
5026 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5027 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5028 && SUBREG_WORD (src) == 0
5029 && (GET_MODE_SIZE (GET_MODE (src))
5030 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5031 && GET_CODE (SUBREG_REG (src)) == MEM)
5034 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5035 GET_MODE (src), XEXP (src, 0)));
5041 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5042 are comparing an item known to be 0 or -1 against 0, use a logical
5043 operation instead. Check for one of the arms being an IOR of the other
5044 arm with some value. We compute three terms to be IOR'ed together. In
5045 practice, at most two will be nonzero. Then we do the IOR's. */
5047 if (GET_CODE (dest) != PC
5048 && GET_CODE (src) == IF_THEN_ELSE
5049 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5050 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5051 && XEXP (XEXP (src, 0), 1) == const0_rtx
5052 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5053 #ifdef HAVE_conditional_move
5054 && ! can_conditionally_move_p (GET_MODE (src))
5056 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5057 GET_MODE (XEXP (XEXP (src, 0), 0)))
5058 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5059 && ! side_effects_p (src))
5061 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5062 ? XEXP (src, 1) : XEXP (src, 2));
5063 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5064 ? XEXP (src, 2) : XEXP (src, 1));
5065 rtx term1 = const0_rtx, term2, term3;
5067 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5068 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5069 else if (GET_CODE (true) == IOR
5070 && rtx_equal_p (XEXP (true, 1), false))
5071 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5072 else if (GET_CODE (false) == IOR
5073 && rtx_equal_p (XEXP (false, 0), true))
5074 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5075 else if (GET_CODE (false) == IOR
5076 && rtx_equal_p (XEXP (false, 1), true))
5077 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5079 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5080 term3 = gen_binary (AND, GET_MODE (src),
5081 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5082 XEXP (XEXP (src, 0), 0)),
5086 gen_binary (IOR, GET_MODE (src),
5087 gen_binary (IOR, GET_MODE (src), term1, term2),
5093 #ifdef HAVE_conditional_arithmetic
5094 /* If we have conditional arithmetic and the operand of a SET is
5095 a conditional expression, replace this with an IF_THEN_ELSE.
5096 We can either have a conditional expression or a MULT of that expression
5098 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5099 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5100 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5101 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5102 || (GET_CODE (XEXP (src, 0)) == MULT
5103 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5104 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5106 rtx cond = XEXP (src, 0);
5107 rtx true_val = const1_rtx;
5108 rtx false_arm, true_arm;
5110 if (GET_CODE (cond) == MULT)
5112 true_val = XEXP (cond, 1);
5113 cond = XEXP (cond, 0);
5116 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5118 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5119 GET_MODE (XEXP (src, 0)), true_val);
5120 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5121 GET_MODE (XEXP (src, 0)), const0_rtx);
5125 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5126 true_val, XEXP (src, 1));
5127 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5128 const0_rtx, XEXP (src, 1));
5131 /* Canonicalize if true_arm is the simpler one. */
5132 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5133 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5134 && reversible_comparison_p (cond))
5136 rtx temp = true_arm;
5138 true_arm = false_arm;
5141 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5142 GET_MODE (cond), XEXP (cond, 0),
5146 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5147 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5150 true_arm, false_arm);
5151 SUBST (SET_SRC (x), src);
5155 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5156 whole thing fail. */
5157 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5159 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5162 /* Convert this into a field assignment operation, if possible. */
5163 return make_field_assignment (x);
5166 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5167 result. LAST is nonzero if this is the last retry. */
5170 simplify_logical (x, last)
5174 enum machine_mode mode = GET_MODE (x);
5175 rtx op0 = XEXP (x, 0);
5176 rtx op1 = XEXP (x, 1);
5178 switch (GET_CODE (x))
5181 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5182 insn (and may simplify more). */
5183 if (GET_CODE (op0) == XOR
5184 && rtx_equal_p (XEXP (op0, 0), op1)
5185 && ! side_effects_p (op1))
5186 x = gen_binary (AND, mode,
5187 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5189 if (GET_CODE (op0) == XOR
5190 && rtx_equal_p (XEXP (op0, 1), op1)
5191 && ! side_effects_p (op1))
5192 x = gen_binary (AND, mode,
5193 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5195 /* Similarly for (~ (A ^ B)) & A. */
5196 if (GET_CODE (op0) == NOT
5197 && GET_CODE (XEXP (op0, 0)) == XOR
5198 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5199 && ! side_effects_p (op1))
5200 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5202 if (GET_CODE (op0) == NOT
5203 && GET_CODE (XEXP (op0, 0)) == XOR
5204 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5205 && ! side_effects_p (op1))
5206 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5208 /* We can call simplify_and_const_int only if we don't lose
5209 any (sign) bits when converting INTVAL (op1) to
5210 "unsigned HOST_WIDE_INT". */
5211 if (GET_CODE (op1) == CONST_INT
5212 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5213 || INTVAL (op1) > 0))
5215 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5217 /* If we have (ior (and (X C1) C2)) and the next restart would be
5218 the last, simplify this by making C1 as small as possible
5221 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5222 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5223 && GET_CODE (op1) == CONST_INT)
5224 return gen_binary (IOR, mode,
5225 gen_binary (AND, mode, XEXP (op0, 0),
5226 GEN_INT (INTVAL (XEXP (op0, 1))
5227 & ~ INTVAL (op1))), op1);
5229 if (GET_CODE (x) != AND)
5232 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5233 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5234 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5237 /* Convert (A | B) & A to A. */
5238 if (GET_CODE (op0) == IOR
5239 && (rtx_equal_p (XEXP (op0, 0), op1)
5240 || rtx_equal_p (XEXP (op0, 1), op1))
5241 && ! side_effects_p (XEXP (op0, 0))
5242 && ! side_effects_p (XEXP (op0, 1)))
5245 /* In the following group of tests (and those in case IOR below),
5246 we start with some combination of logical operations and apply
5247 the distributive law followed by the inverse distributive law.
5248 Most of the time, this results in no change. However, if some of
5249 the operands are the same or inverses of each other, simplifications
5252 For example, (and (ior A B) (not B)) can occur as the result of
5253 expanding a bit field assignment. When we apply the distributive
5254 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5255 which then simplifies to (and (A (not B))).
5257 If we have (and (ior A B) C), apply the distributive law and then
5258 the inverse distributive law to see if things simplify. */
5260 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5262 x = apply_distributive_law
5263 (gen_binary (GET_CODE (op0), mode,
5264 gen_binary (AND, mode, XEXP (op0, 0), op1),
5265 gen_binary (AND, mode, XEXP (op0, 1),
5267 if (GET_CODE (x) != AND)
5271 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5272 return apply_distributive_law
5273 (gen_binary (GET_CODE (op1), mode,
5274 gen_binary (AND, mode, XEXP (op1, 0), op0),
5275 gen_binary (AND, mode, XEXP (op1, 1),
5278 /* Similarly, taking advantage of the fact that
5279 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5281 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5282 return apply_distributive_law
5283 (gen_binary (XOR, mode,
5284 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5285 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5288 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5289 return apply_distributive_law
5290 (gen_binary (XOR, mode,
5291 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5292 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5296 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5297 if (GET_CODE (op1) == CONST_INT
5298 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5299 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5302 /* Convert (A & B) | A to A. */
5303 if (GET_CODE (op0) == AND
5304 && (rtx_equal_p (XEXP (op0, 0), op1)
5305 || rtx_equal_p (XEXP (op0, 1), op1))
5306 && ! side_effects_p (XEXP (op0, 0))
5307 && ! side_effects_p (XEXP (op0, 1)))
5310 /* If we have (ior (and A B) C), apply the distributive law and then
5311 the inverse distributive law to see if things simplify. */
5313 if (GET_CODE (op0) == AND)
5315 x = apply_distributive_law
5316 (gen_binary (AND, mode,
5317 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5318 gen_binary (IOR, mode, XEXP (op0, 1),
5321 if (GET_CODE (x) != IOR)
5325 if (GET_CODE (op1) == AND)
5327 x = apply_distributive_law
5328 (gen_binary (AND, mode,
5329 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5330 gen_binary (IOR, mode, XEXP (op1, 1),
5333 if (GET_CODE (x) != IOR)
5337 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5338 mode size to (rotate A CX). */
5340 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5341 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5342 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5343 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5344 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5345 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5346 == GET_MODE_BITSIZE (mode)))
5347 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5348 (GET_CODE (op0) == ASHIFT
5349 ? XEXP (op0, 1) : XEXP (op1, 1)));
5351 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5352 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5353 does not affect any of the bits in OP1, it can really be done
5354 as a PLUS and we can associate. We do this by seeing if OP1
5355 can be safely shifted left C bits. */
5356 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5357 && GET_CODE (XEXP (op0, 0)) == PLUS
5358 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5359 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5360 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5362 int count = INTVAL (XEXP (op0, 1));
5363 HOST_WIDE_INT mask = INTVAL (op1) << count;
5365 if (mask >> count == INTVAL (op1)
5366 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5368 SUBST (XEXP (XEXP (op0, 0), 1),
5369 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5376 /* If we are XORing two things that have no bits in common,
5377 convert them into an IOR. This helps to detect rotation encoded
5378 using those methods and possibly other simplifications. */
5380 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5381 && (nonzero_bits (op0, mode)
5382 & nonzero_bits (op1, mode)) == 0)
5383 return (gen_binary (IOR, mode, op0, op1));
5385 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5386 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5389 int num_negated = 0;
5391 if (GET_CODE (op0) == NOT)
5392 num_negated++, op0 = XEXP (op0, 0);
5393 if (GET_CODE (op1) == NOT)
5394 num_negated++, op1 = XEXP (op1, 0);
5396 if (num_negated == 2)
5398 SUBST (XEXP (x, 0), op0);
5399 SUBST (XEXP (x, 1), op1);
5401 else if (num_negated == 1)
5402 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5405 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5406 correspond to a machine insn or result in further simplifications
5407 if B is a constant. */
5409 if (GET_CODE (op0) == AND
5410 && rtx_equal_p (XEXP (op0, 1), op1)
5411 && ! side_effects_p (op1))
5412 return gen_binary (AND, mode,
5413 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5416 else if (GET_CODE (op0) == AND
5417 && rtx_equal_p (XEXP (op0, 0), op1)
5418 && ! side_effects_p (op1))
5419 return gen_binary (AND, mode,
5420 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5423 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5424 comparison if STORE_FLAG_VALUE is 1. */
5425 if (STORE_FLAG_VALUE == 1
5426 && op1 == const1_rtx
5427 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5428 && reversible_comparison_p (op0))
5429 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5430 mode, XEXP (op0, 0), XEXP (op0, 1));
5432 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5433 is (lt foo (const_int 0)), so we can perform the above
5434 simplification if STORE_FLAG_VALUE is 1. */
5436 if (STORE_FLAG_VALUE == 1
5437 && op1 == const1_rtx
5438 && GET_CODE (op0) == LSHIFTRT
5439 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5440 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5441 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5443 /* (xor (comparison foo bar) (const_int sign-bit))
5444 when STORE_FLAG_VALUE is the sign bit. */
5445 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5446 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5447 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5448 && op1 == const_true_rtx
5449 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5450 && reversible_comparison_p (op0))
5451 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5452 mode, XEXP (op0, 0), XEXP (op0, 1));
5463 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5464 operations" because they can be replaced with two more basic operations.
5465 ZERO_EXTEND is also considered "compound" because it can be replaced with
5466 an AND operation, which is simpler, though only one operation.
5468 The function expand_compound_operation is called with an rtx expression
5469 and will convert it to the appropriate shifts and AND operations,
5470 simplifying at each stage.
5472 The function make_compound_operation is called to convert an expression
5473 consisting of shifts and ANDs into the equivalent compound expression.
5474 It is the inverse of this function, loosely speaking. */
5477 expand_compound_operation (x)
5480 unsigned HOST_WIDE_INT pos = 0, len;
5482 unsigned int modewidth;
5485 switch (GET_CODE (x))
5490 /* We can't necessarily use a const_int for a multiword mode;
5491 it depends on implicitly extending the value.
5492 Since we don't know the right way to extend it,
5493 we can't tell whether the implicit way is right.
5495 Even for a mode that is no wider than a const_int,
5496 we can't win, because we need to sign extend one of its bits through
5497 the rest of it, and we don't know which bit. */
5498 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5501 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5502 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5503 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5504 reloaded. If not for that, MEM's would very rarely be safe.
5506 Reject MODEs bigger than a word, because we might not be able
5507 to reference a two-register group starting with an arbitrary register
5508 (and currently gen_lowpart might crash for a SUBREG). */
5510 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5513 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5514 /* If the inner object has VOIDmode (the only way this can happen
5515 is if it is a ASM_OPERANDS), we can't do anything since we don't
5516 know how much masking to do. */
5525 /* If the operand is a CLOBBER, just return it. */
5526 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5529 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5530 || GET_CODE (XEXP (x, 2)) != CONST_INT
5531 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5534 len = INTVAL (XEXP (x, 1));
5535 pos = INTVAL (XEXP (x, 2));
5537 /* If this goes outside the object being extracted, replace the object
5538 with a (use (mem ...)) construct that only combine understands
5539 and is used only for this purpose. */
5540 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5541 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5543 if (BITS_BIG_ENDIAN)
5544 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5551 /* Convert sign extension to zero extension, if we know that the high
5552 bit is not set, as this is easier to optimize. It will be converted
5553 back to cheaper alternative in make_extraction. */
5554 if (GET_CODE (x) == SIGN_EXTEND
5555 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5556 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5557 & ~ (((unsigned HOST_WIDE_INT)
5558 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5562 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5563 return expand_compound_operation (temp);
5566 /* We can optimize some special cases of ZERO_EXTEND. */
5567 if (GET_CODE (x) == ZERO_EXTEND)
5569 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5570 know that the last value didn't have any inappropriate bits
5572 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5573 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5574 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5575 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5576 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5577 return XEXP (XEXP (x, 0), 0);
5579 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5580 if (GET_CODE (XEXP (x, 0)) == SUBREG
5581 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5582 && subreg_lowpart_p (XEXP (x, 0))
5583 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5584 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5585 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5586 return SUBREG_REG (XEXP (x, 0));
5588 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5589 is a comparison and STORE_FLAG_VALUE permits. This is like
5590 the first case, but it works even when GET_MODE (x) is larger
5591 than HOST_WIDE_INT. */
5592 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5593 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5594 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5595 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5596 <= HOST_BITS_PER_WIDE_INT)
5597 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5598 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5599 return XEXP (XEXP (x, 0), 0);
5601 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5602 if (GET_CODE (XEXP (x, 0)) == SUBREG
5603 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5604 && subreg_lowpart_p (XEXP (x, 0))
5605 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5606 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5607 <= HOST_BITS_PER_WIDE_INT)
5608 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5609 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5610 return SUBREG_REG (XEXP (x, 0));
5614 /* If we reach here, we want to return a pair of shifts. The inner
5615 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5616 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5617 logical depending on the value of UNSIGNEDP.
5619 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5620 converted into an AND of a shift.
5622 We must check for the case where the left shift would have a negative
5623 count. This can happen in a case like (x >> 31) & 255 on machines
5624 that can't shift by a constant. On those machines, we would first
5625 combine the shift with the AND to produce a variable-position
5626 extraction. Then the constant of 31 would be substituted in to produce
5627 a such a position. */
5629 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5630 if (modewidth + len >= pos)
5631 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5633 simplify_shift_const (NULL_RTX, ASHIFT,
5636 modewidth - pos - len),
5639 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5640 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5641 simplify_shift_const (NULL_RTX, LSHIFTRT,
5644 ((HOST_WIDE_INT) 1 << len) - 1);
5646 /* Any other cases we can't handle. */
5650 /* If we couldn't do this for some reason, return the original
5652 if (GET_CODE (tem) == CLOBBER)
5658 /* X is a SET which contains an assignment of one object into
5659 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5660 or certain SUBREGS). If possible, convert it into a series of
5663 We half-heartedly support variable positions, but do not at all
5664 support variable lengths. */
5667 expand_field_assignment (x)
5671 rtx pos; /* Always counts from low bit. */
5674 enum machine_mode compute_mode;
5676 /* Loop until we find something we can't simplify. */
5679 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5680 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5682 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5683 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5684 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5686 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5687 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5689 inner = XEXP (SET_DEST (x), 0);
5690 len = INTVAL (XEXP (SET_DEST (x), 1));
5691 pos = XEXP (SET_DEST (x), 2);
5693 /* If the position is constant and spans the width of INNER,
5694 surround INNER with a USE to indicate this. */
5695 if (GET_CODE (pos) == CONST_INT
5696 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5697 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5699 if (BITS_BIG_ENDIAN)
5701 if (GET_CODE (pos) == CONST_INT)
5702 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5704 else if (GET_CODE (pos) == MINUS
5705 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5706 && (INTVAL (XEXP (pos, 1))
5707 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5708 /* If position is ADJUST - X, new position is X. */
5709 pos = XEXP (pos, 0);
5711 pos = gen_binary (MINUS, GET_MODE (pos),
5712 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5718 /* A SUBREG between two modes that occupy the same numbers of words
5719 can be done by moving the SUBREG to the source. */
5720 else if (GET_CODE (SET_DEST (x)) == SUBREG
5721 /* We need SUBREGs to compute nonzero_bits properly. */
5722 && nonzero_sign_valid
5723 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5724 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5725 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5726 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5728 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5729 gen_lowpart_for_combine
5730 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5737 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5738 inner = SUBREG_REG (inner);
5740 compute_mode = GET_MODE (inner);
5742 /* Don't attempt bitwise arithmetic on non-integral modes. */
5743 if (! INTEGRAL_MODE_P (compute_mode))
5745 enum machine_mode imode;
5747 /* Something is probably seriously wrong if this matches. */
5748 if (! FLOAT_MODE_P (compute_mode))
5751 /* Try to find an integral mode to pun with. */
5752 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5753 if (imode == BLKmode)
5756 compute_mode = imode;
5757 inner = gen_lowpart_for_combine (imode, inner);
5760 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5761 if (len < HOST_BITS_PER_WIDE_INT)
5762 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5766 /* Now compute the equivalent expression. Make a copy of INNER
5767 for the SET_DEST in case it is a MEM into which we will substitute;
5768 we don't want shared RTL in that case. */
5770 (VOIDmode, copy_rtx (inner),
5771 gen_binary (IOR, compute_mode,
5772 gen_binary (AND, compute_mode,
5773 gen_unary (NOT, compute_mode,
5779 gen_binary (ASHIFT, compute_mode,
5780 gen_binary (AND, compute_mode,
5781 gen_lowpart_for_combine
5782 (compute_mode, SET_SRC (x)),
5790 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5791 it is an RTX that represents a variable starting position; otherwise,
5792 POS is the (constant) starting bit position (counted from the LSB).
5794 INNER may be a USE. This will occur when we started with a bitfield
5795 that went outside the boundary of the object in memory, which is
5796 allowed on most machines. To isolate this case, we produce a USE
5797 whose mode is wide enough and surround the MEM with it. The only
5798 code that understands the USE is this routine. If it is not removed,
5799 it will cause the resulting insn not to match.
5801 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5804 IN_DEST is non-zero if this is a reference in the destination of a
5805 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5806 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5809 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5810 ZERO_EXTRACT should be built even for bits starting at bit 0.
5812 MODE is the desired mode of the result (if IN_DEST == 0).
5814 The result is an RTX for the extraction or NULL_RTX if the target
5818 make_extraction (mode, inner, pos, pos_rtx, len,
5819 unsignedp, in_dest, in_compare)
5820 enum machine_mode mode;
5824 unsigned HOST_WIDE_INT len;
5826 int in_dest, in_compare;
5828 /* This mode describes the size of the storage area
5829 to fetch the overall value from. Within that, we
5830 ignore the POS lowest bits, etc. */
5831 enum machine_mode is_mode = GET_MODE (inner);
5832 enum machine_mode inner_mode;
5833 enum machine_mode wanted_inner_mode = byte_mode;
5834 enum machine_mode wanted_inner_reg_mode = word_mode;
5835 enum machine_mode pos_mode = word_mode;
5836 enum machine_mode extraction_mode = word_mode;
5837 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5840 rtx orig_pos_rtx = pos_rtx;
5841 HOST_WIDE_INT orig_pos;
5843 /* Get some information about INNER and get the innermost object. */
5844 if (GET_CODE (inner) == USE)
5845 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5846 /* We don't need to adjust the position because we set up the USE
5847 to pretend that it was a full-word object. */
5848 spans_byte = 1, inner = XEXP (inner, 0);
5849 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5851 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5852 consider just the QI as the memory to extract from.
5853 The subreg adds or removes high bits; its mode is
5854 irrelevant to the meaning of this extraction,
5855 since POS and LEN count from the lsb. */
5856 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5857 is_mode = GET_MODE (SUBREG_REG (inner));
5858 inner = SUBREG_REG (inner);
5861 inner_mode = GET_MODE (inner);
5863 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5864 pos = INTVAL (pos_rtx), pos_rtx = 0;
5866 /* See if this can be done without an extraction. We never can if the
5867 width of the field is not the same as that of some integer mode. For
5868 registers, we can only avoid the extraction if the position is at the
5869 low-order bit and this is either not in the destination or we have the
5870 appropriate STRICT_LOW_PART operation available.
5872 For MEM, we can avoid an extract if the field starts on an appropriate
5873 boundary and we can change the mode of the memory reference. However,
5874 we cannot directly access the MEM if we have a USE and the underlying
5875 MEM is not TMODE. This combination means that MEM was being used in a
5876 context where bits outside its mode were being referenced; that is only
5877 valid in bit-field insns. */
5879 if (tmode != BLKmode
5880 && ! (spans_byte && inner_mode != tmode)
5881 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5882 && GET_CODE (inner) != MEM
5884 || (GET_CODE (inner) == REG
5885 && (movstrict_optab->handlers[(int) tmode].insn_code
5886 != CODE_FOR_nothing))))
5887 || (GET_CODE (inner) == MEM && pos_rtx == 0
5889 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5890 : BITS_PER_UNIT)) == 0
5891 /* We can't do this if we are widening INNER_MODE (it
5892 may not be aligned, for one thing). */
5893 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5894 && (inner_mode == tmode
5895 || (! mode_dependent_address_p (XEXP (inner, 0))
5896 && ! MEM_VOLATILE_P (inner))))))
5898 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5899 field. If the original and current mode are the same, we need not
5900 adjust the offset. Otherwise, we do if bytes big endian.
5902 If INNER is not a MEM, get a piece consisting of just the field
5903 of interest (in this case POS % BITS_PER_WORD must be 0). */
5905 if (GET_CODE (inner) == MEM)
5908 /* POS counts from lsb, but make OFFSET count in memory order. */
5909 if (BYTES_BIG_ENDIAN)
5910 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5912 offset = pos / BITS_PER_UNIT;
5914 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5915 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5916 MEM_COPY_ATTRIBUTES (new, inner);
5918 else if (GET_CODE (inner) == REG)
5920 /* We can't call gen_lowpart_for_combine here since we always want
5921 a SUBREG and it would sometimes return a new hard register. */
5922 if (tmode != inner_mode)
5923 new = gen_rtx_SUBREG (tmode, inner,
5925 && (GET_MODE_SIZE (inner_mode)
5927 ? (((GET_MODE_SIZE (inner_mode)
5928 - GET_MODE_SIZE (tmode))
5930 - pos / BITS_PER_WORD)
5931 : pos / BITS_PER_WORD));
5936 new = force_to_mode (inner, tmode,
5937 len >= HOST_BITS_PER_WIDE_INT
5938 ? GET_MODE_MASK (tmode)
5939 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5942 /* If this extraction is going into the destination of a SET,
5943 make a STRICT_LOW_PART unless we made a MEM. */
5946 return (GET_CODE (new) == MEM ? new
5947 : (GET_CODE (new) != SUBREG
5948 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5949 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5954 /* If we know that no extraneous bits are set, and that the high
5955 bit is not set, convert the extraction to the cheaper of
5956 sign and zero extension, that are equivalent in these cases. */
5957 if (flag_expensive_optimizations
5958 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5959 && ((nonzero_bits (new, tmode)
5960 & ~ (((unsigned HOST_WIDE_INT)
5961 GET_MODE_MASK (tmode))
5965 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5966 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5968 /* Prefer ZERO_EXTENSION, since it gives more information to
5970 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
5975 /* Otherwise, sign- or zero-extend unless we already are in the
5978 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5982 /* Unless this is a COMPARE or we have a funny memory reference,
5983 don't do anything with zero-extending field extracts starting at
5984 the low-order bit since they are simple AND operations. */
5985 if (pos_rtx == 0 && pos == 0 && ! in_dest
5986 && ! in_compare && ! spans_byte && unsignedp)
5989 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5990 we would be spanning bytes or if the position is not a constant and the
5991 length is not 1. In all other cases, we would only be going outside
5992 our object in cases when an original shift would have been
5994 if (! spans_byte && GET_CODE (inner) == MEM
5995 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5996 || (pos_rtx != 0 && len != 1)))
5999 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6000 and the mode for the result. */
6004 wanted_inner_reg_mode
6005 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6006 if (wanted_inner_reg_mode == VOIDmode)
6007 wanted_inner_reg_mode = word_mode;
6009 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6010 if (pos_mode == VOIDmode)
6011 pos_mode = word_mode;
6013 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6014 if (extraction_mode == VOIDmode)
6015 extraction_mode = word_mode;
6020 if (! in_dest && unsignedp)
6022 wanted_inner_reg_mode
6023 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6024 if (wanted_inner_reg_mode == VOIDmode)
6025 wanted_inner_reg_mode = word_mode;
6027 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6028 if (pos_mode == VOIDmode)
6029 pos_mode = word_mode;
6031 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6032 if (extraction_mode == VOIDmode)
6033 extraction_mode = word_mode;
6038 if (! in_dest && ! unsignedp)
6040 wanted_inner_reg_mode
6041 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6042 if (wanted_inner_reg_mode == VOIDmode)
6043 wanted_inner_reg_mode = word_mode;
6045 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6046 if (pos_mode == VOIDmode)
6047 pos_mode = word_mode;
6049 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6050 if (extraction_mode == VOIDmode)
6051 extraction_mode = word_mode;
6055 /* Never narrow an object, since that might not be safe. */
6057 if (mode != VOIDmode
6058 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6059 extraction_mode = mode;
6061 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6062 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6063 pos_mode = GET_MODE (pos_rtx);
6065 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6066 if we have to change the mode of memory and cannot, the desired mode is
6068 if (GET_CODE (inner) != MEM)
6069 wanted_inner_mode = wanted_inner_reg_mode;
6070 else if (inner_mode != wanted_inner_mode
6071 && (mode_dependent_address_p (XEXP (inner, 0))
6072 || MEM_VOLATILE_P (inner)))
6073 wanted_inner_mode = extraction_mode;
6077 if (BITS_BIG_ENDIAN)
6079 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6080 BITS_BIG_ENDIAN style. If position is constant, compute new
6081 position. Otherwise, build subtraction.
6082 Note that POS is relative to the mode of the original argument.
6083 If it's a MEM we need to recompute POS relative to that.
6084 However, if we're extracting from (or inserting into) a register,
6085 we want to recompute POS relative to wanted_inner_mode. */
6086 int width = (GET_CODE (inner) == MEM
6087 ? GET_MODE_BITSIZE (is_mode)
6088 : GET_MODE_BITSIZE (wanted_inner_mode));
6091 pos = width - len - pos;
6094 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6095 GEN_INT (width - len), pos_rtx);
6096 /* POS may be less than 0 now, but we check for that below.
6097 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6100 /* If INNER has a wider mode, make it smaller. If this is a constant
6101 extract, try to adjust the byte to point to the byte containing
6103 if (wanted_inner_mode != VOIDmode
6104 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6105 && ((GET_CODE (inner) == MEM
6106 && (inner_mode == wanted_inner_mode
6107 || (! mode_dependent_address_p (XEXP (inner, 0))
6108 && ! MEM_VOLATILE_P (inner))))))
6112 /* The computations below will be correct if the machine is big
6113 endian in both bits and bytes or little endian in bits and bytes.
6114 If it is mixed, we must adjust. */
6116 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6117 adjust OFFSET to compensate. */
6118 if (BYTES_BIG_ENDIAN
6120 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6121 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6123 /* If this is a constant position, we can move to the desired byte. */
6126 offset += pos / BITS_PER_UNIT;
6127 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6130 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6132 && is_mode != wanted_inner_mode)
6133 offset = (GET_MODE_SIZE (is_mode)
6134 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6136 if (offset != 0 || inner_mode != wanted_inner_mode)
6138 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6139 plus_constant (XEXP (inner, 0), offset));
6140 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
6141 MEM_COPY_ATTRIBUTES (newmem, inner);
6146 /* If INNER is not memory, we can always get it into the proper mode. If we
6147 are changing its mode, POS must be a constant and smaller than the size
6149 else if (GET_CODE (inner) != MEM)
6151 if (GET_MODE (inner) != wanted_inner_mode
6153 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6156 inner = force_to_mode (inner, wanted_inner_mode,
6158 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6159 ? GET_MODE_MASK (wanted_inner_mode)
6160 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6165 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6166 have to zero extend. Otherwise, we can just use a SUBREG. */
6168 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6170 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6172 /* If we know that no extraneous bits are set, and that the high
6173 bit is not set, convert extraction to cheaper one - eighter
6174 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6176 if (flag_expensive_optimizations
6177 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6178 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6179 & ~ (((unsigned HOST_WIDE_INT)
6180 GET_MODE_MASK (GET_MODE (pos_rtx)))
6184 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6186 /* Preffer ZERO_EXTENSION, since it gives more information to
6188 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6193 else if (pos_rtx != 0
6194 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6195 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6197 /* Make POS_RTX unless we already have it and it is correct. If we don't
6198 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6200 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6201 pos_rtx = orig_pos_rtx;
6203 else if (pos_rtx == 0)
6204 pos_rtx = GEN_INT (pos);
6206 /* Make the required operation. See if we can use existing rtx. */
6207 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6208 extraction_mode, inner, GEN_INT (len), pos_rtx);
6210 new = gen_lowpart_for_combine (mode, new);
6215 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6216 with any other operations in X. Return X without that shift if so. */
6219 extract_left_shift (x, count)
6223 enum rtx_code code = GET_CODE (x);
6224 enum machine_mode mode = GET_MODE (x);
6230 /* This is the shift itself. If it is wide enough, we will return
6231 either the value being shifted if the shift count is equal to
6232 COUNT or a shift for the difference. */
6233 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6234 && INTVAL (XEXP (x, 1)) >= count)
6235 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6236 INTVAL (XEXP (x, 1)) - count);
6240 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6241 return gen_unary (code, mode, mode, tem);
6245 case PLUS: case IOR: case XOR: case AND:
6246 /* If we can safely shift this constant and we find the inner shift,
6247 make a new operation. */
6248 if (GET_CODE (XEXP (x,1)) == CONST_INT
6249 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6250 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6251 return gen_binary (code, mode, tem,
6252 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6263 /* Look at the expression rooted at X. Look for expressions
6264 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6265 Form these expressions.
6267 Return the new rtx, usually just X.
6269 Also, for machines like the Vax that don't have logical shift insns,
6270 try to convert logical to arithmetic shift operations in cases where
6271 they are equivalent. This undoes the canonicalizations to logical
6272 shifts done elsewhere.
6274 We try, as much as possible, to re-use rtl expressions to save memory.
6276 IN_CODE says what kind of expression we are processing. Normally, it is
6277 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6278 being kludges), it is MEM. When processing the arguments of a comparison
6279 or a COMPARE against zero, it is COMPARE. */
6282 make_compound_operation (x, in_code)
6284 enum rtx_code in_code;
6286 enum rtx_code code = GET_CODE (x);
6287 enum machine_mode mode = GET_MODE (x);
6288 int mode_width = GET_MODE_BITSIZE (mode);
6290 enum rtx_code next_code;
6296 /* Select the code to be used in recursive calls. Once we are inside an
6297 address, we stay there. If we have a comparison, set to COMPARE,
6298 but once inside, go back to our default of SET. */
6300 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6301 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6302 && XEXP (x, 1) == const0_rtx) ? COMPARE
6303 : in_code == COMPARE ? SET : in_code);
6305 /* Process depending on the code of this operation. If NEW is set
6306 non-zero, it will be returned. */
6311 /* Convert shifts by constants into multiplications if inside
6313 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6314 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6315 && INTVAL (XEXP (x, 1)) >= 0)
6317 new = make_compound_operation (XEXP (x, 0), next_code);
6318 new = gen_rtx_combine (MULT, mode, new,
6319 GEN_INT ((HOST_WIDE_INT) 1
6320 << INTVAL (XEXP (x, 1))));
6325 /* If the second operand is not a constant, we can't do anything
6327 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6330 /* If the constant is a power of two minus one and the first operand
6331 is a logical right shift, make an extraction. */
6332 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6333 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6335 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6336 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6337 0, in_code == COMPARE);
6340 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6341 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6342 && subreg_lowpart_p (XEXP (x, 0))
6343 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6344 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6346 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6348 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6349 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6350 0, in_code == COMPARE);
6352 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6353 else if ((GET_CODE (XEXP (x, 0)) == XOR
6354 || GET_CODE (XEXP (x, 0)) == IOR)
6355 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6356 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6357 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6359 /* Apply the distributive law, and then try to make extractions. */
6360 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6361 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6363 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6365 new = make_compound_operation (new, in_code);
6368 /* If we are have (and (rotate X C) M) and C is larger than the number
6369 of bits in M, this is an extraction. */
6371 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6372 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6373 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6374 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6376 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6377 new = make_extraction (mode, new,
6378 (GET_MODE_BITSIZE (mode)
6379 - INTVAL (XEXP (XEXP (x, 0), 1))),
6380 NULL_RTX, i, 1, 0, in_code == COMPARE);
6383 /* On machines without logical shifts, if the operand of the AND is
6384 a logical shift and our mask turns off all the propagated sign
6385 bits, we can replace the logical shift with an arithmetic shift. */
6386 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6387 && (lshr_optab->handlers[(int) mode].insn_code
6388 == CODE_FOR_nothing)
6389 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6390 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6391 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6392 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6393 && mode_width <= HOST_BITS_PER_WIDE_INT)
6395 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6397 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6398 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6400 gen_rtx_combine (ASHIFTRT, mode,
6401 make_compound_operation (XEXP (XEXP (x, 0), 0),
6403 XEXP (XEXP (x, 0), 1)));
6406 /* If the constant is one less than a power of two, this might be
6407 representable by an extraction even if no shift is present.
6408 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6409 we are in a COMPARE. */
6410 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6411 new = make_extraction (mode,
6412 make_compound_operation (XEXP (x, 0),
6414 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6416 /* If we are in a comparison and this is an AND with a power of two,
6417 convert this into the appropriate bit extract. */
6418 else if (in_code == COMPARE
6419 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6420 new = make_extraction (mode,
6421 make_compound_operation (XEXP (x, 0),
6423 i, NULL_RTX, 1, 1, 0, 1);
6428 /* If the sign bit is known to be zero, replace this with an
6429 arithmetic shift. */
6430 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6431 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6432 && mode_width <= HOST_BITS_PER_WIDE_INT
6433 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6435 new = gen_rtx_combine (ASHIFTRT, mode,
6436 make_compound_operation (XEXP (x, 0),
6442 /* ... fall through ... */
6448 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6449 this is a SIGN_EXTRACT. */
6450 if (GET_CODE (rhs) == CONST_INT
6451 && GET_CODE (lhs) == ASHIFT
6452 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6453 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6455 new = make_compound_operation (XEXP (lhs, 0), next_code);
6456 new = make_extraction (mode, new,
6457 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6458 NULL_RTX, mode_width - INTVAL (rhs),
6459 code == LSHIFTRT, 0, in_code == COMPARE);
6462 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6463 If so, try to merge the shifts into a SIGN_EXTEND. We could
6464 also do this for some cases of SIGN_EXTRACT, but it doesn't
6465 seem worth the effort; the case checked for occurs on Alpha. */
6467 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6468 && ! (GET_CODE (lhs) == SUBREG
6469 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6470 && GET_CODE (rhs) == CONST_INT
6471 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6472 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6473 new = make_extraction (mode, make_compound_operation (new, next_code),
6474 0, NULL_RTX, mode_width - INTVAL (rhs),
6475 code == LSHIFTRT, 0, in_code == COMPARE);
6480 /* Call ourselves recursively on the inner expression. If we are
6481 narrowing the object and it has a different RTL code from
6482 what it originally did, do this SUBREG as a force_to_mode. */
6484 tem = make_compound_operation (SUBREG_REG (x), in_code);
6485 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6486 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6487 && subreg_lowpart_p (x))
6489 rtx newer = force_to_mode (tem, mode,
6490 GET_MODE_MASK (mode), NULL_RTX, 0);
6492 /* If we have something other than a SUBREG, we might have
6493 done an expansion, so rerun outselves. */
6494 if (GET_CODE (newer) != SUBREG)
6495 newer = make_compound_operation (newer, in_code);
6500 /* If this is a paradoxical subreg, and the new code is a sign or
6501 zero extension, omit the subreg and widen the extension. If it
6502 is a regular subreg, we can still get rid of the subreg by not
6503 widening so much, or in fact removing the extension entirely. */
6504 if ((GET_CODE (tem) == SIGN_EXTEND
6505 || GET_CODE (tem) == ZERO_EXTEND)
6506 && subreg_lowpart_p (x))
6508 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6509 || (GET_MODE_SIZE (mode) >
6510 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6511 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6513 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6524 x = gen_lowpart_for_combine (mode, new);
6525 code = GET_CODE (x);
6528 /* Now recursively process each operand of this operation. */
6529 fmt = GET_RTX_FORMAT (code);
6530 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6533 new = make_compound_operation (XEXP (x, i), next_code);
6534 SUBST (XEXP (x, i), new);
6540 /* Given M see if it is a value that would select a field of bits
6541 within an item, but not the entire word. Return -1 if not.
6542 Otherwise, return the starting position of the field, where 0 is the
6545 *PLEN is set to the length of the field. */
6548 get_pos_from_mask (m, plen)
6549 unsigned HOST_WIDE_INT m;
6550 unsigned HOST_WIDE_INT *plen;
6552 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6553 int pos = exact_log2 (m & - m);
6558 /* Now shift off the low-order zero bits and see if we have a power of
6560 *plen = exact_log2 ((m >> pos) + 1);
6568 /* See if X can be simplified knowing that we will only refer to it in
6569 MODE and will only refer to those bits that are nonzero in MASK.
6570 If other bits are being computed or if masking operations are done
6571 that select a superset of the bits in MASK, they can sometimes be
6574 Return a possibly simplified expression, but always convert X to
6575 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6577 Also, if REG is non-zero and X is a register equal in value to REG,
6580 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6581 are all off in X. This is used when X will be complemented, by either
6582 NOT, NEG, or XOR. */
6585 force_to_mode (x, mode, mask, reg, just_select)
6587 enum machine_mode mode;
6588 unsigned HOST_WIDE_INT mask;
6592 enum rtx_code code = GET_CODE (x);
6593 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6594 enum machine_mode op_mode;
6595 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6598 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6599 code below will do the wrong thing since the mode of such an
6600 expression is VOIDmode.
6602 Also do nothing if X is a CLOBBER; this can happen if X was
6603 the return value from a call to gen_lowpart_for_combine. */
6604 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6607 /* We want to perform the operation is its present mode unless we know
6608 that the operation is valid in MODE, in which case we do the operation
6610 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6611 && code_to_optab[(int) code] != 0
6612 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6613 != CODE_FOR_nothing))
6614 ? mode : GET_MODE (x));
6616 /* It is not valid to do a right-shift in a narrower mode
6617 than the one it came in with. */
6618 if ((code == LSHIFTRT || code == ASHIFTRT)
6619 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6620 op_mode = GET_MODE (x);
6622 /* Truncate MASK to fit OP_MODE. */
6624 mask &= GET_MODE_MASK (op_mode);
6626 /* When we have an arithmetic operation, or a shift whose count we
6627 do not know, we need to assume that all bit the up to the highest-order
6628 bit in MASK will be needed. This is how we form such a mask. */
6630 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6631 ? GET_MODE_MASK (op_mode)
6632 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6635 fuller_mask = ~ (HOST_WIDE_INT) 0;
6637 /* Determine what bits of X are guaranteed to be (non)zero. */
6638 nonzero = nonzero_bits (x, mode);
6640 /* If none of the bits in X are needed, return a zero. */
6641 if (! just_select && (nonzero & mask) == 0)
6644 /* If X is a CONST_INT, return a new one. Do this here since the
6645 test below will fail. */
6646 if (GET_CODE (x) == CONST_INT)
6648 HOST_WIDE_INT cval = INTVAL (x) & mask;
6649 int width = GET_MODE_BITSIZE (mode);
6651 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6652 number, sign extend it. */
6653 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6654 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6655 cval |= (HOST_WIDE_INT) -1 << width;
6657 return GEN_INT (cval);
6660 /* If X is narrower than MODE and we want all the bits in X's mode, just
6661 get X in the proper mode. */
6662 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6663 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6664 return gen_lowpart_for_combine (mode, x);
6666 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6667 MASK are already known to be zero in X, we need not do anything. */
6668 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6674 /* If X is a (clobber (const_int)), return it since we know we are
6675 generating something that won't match. */
6679 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6680 spanned the boundary of the MEM. If we are now masking so it is
6681 within that boundary, we don't need the USE any more. */
6682 if (! BITS_BIG_ENDIAN
6683 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6684 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6691 x = expand_compound_operation (x);
6692 if (GET_CODE (x) != code)
6693 return force_to_mode (x, mode, mask, reg, next_select);
6697 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6698 || rtx_equal_p (reg, get_last_value (x))))
6703 if (subreg_lowpart_p (x)
6704 /* We can ignore the effect of this SUBREG if it narrows the mode or
6705 if the constant masks to zero all the bits the mode doesn't
6707 && ((GET_MODE_SIZE (GET_MODE (x))
6708 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6710 & GET_MODE_MASK (GET_MODE (x))
6711 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6712 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6716 /* If this is an AND with a constant, convert it into an AND
6717 whose constant is the AND of that constant with MASK. If it
6718 remains an AND of MASK, delete it since it is redundant. */
6720 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6722 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6723 mask & INTVAL (XEXP (x, 1)));
6725 /* If X is still an AND, see if it is an AND with a mask that
6726 is just some low-order bits. If so, and it is MASK, we don't
6729 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6730 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6733 /* If it remains an AND, try making another AND with the bits
6734 in the mode mask that aren't in MASK turned on. If the
6735 constant in the AND is wide enough, this might make a
6736 cheaper constant. */
6738 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6739 && GET_MODE_MASK (GET_MODE (x)) != mask
6740 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6742 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6743 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6744 int width = GET_MODE_BITSIZE (GET_MODE (x));
6747 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6748 number, sign extend it. */
6749 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6750 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6751 cval |= (HOST_WIDE_INT) -1 << width;
6753 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6754 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6764 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6765 low-order bits (as in an alignment operation) and FOO is already
6766 aligned to that boundary, mask C1 to that boundary as well.
6767 This may eliminate that PLUS and, later, the AND. */
6770 unsigned int width = GET_MODE_BITSIZE (mode);
6771 unsigned HOST_WIDE_INT smask = mask;
6773 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6774 number, sign extend it. */
6776 if (width < HOST_BITS_PER_WIDE_INT
6777 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6778 smask |= (HOST_WIDE_INT) -1 << width;
6780 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6781 && exact_log2 (- smask) >= 0)
6785 && (XEXP (x, 0) == stack_pointer_rtx
6786 || XEXP (x, 0) == frame_pointer_rtx))
6788 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6789 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6791 sp_mask &= ~ (sp_alignment - 1);
6792 if ((sp_mask & ~ smask) == 0
6793 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6794 return force_to_mode (plus_constant (XEXP (x, 0),
6795 ((INTVAL (XEXP (x, 1)) -
6796 STACK_BIAS) & smask)
6798 mode, smask, reg, next_select);
6801 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6802 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6803 return force_to_mode (plus_constant (XEXP (x, 0),
6804 (INTVAL (XEXP (x, 1))
6806 mode, smask, reg, next_select);
6810 /* ... fall through ... */
6814 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6815 most significant bit in MASK since carries from those bits will
6816 affect the bits we are interested in. */
6822 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6823 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6824 operation which may be a bitfield extraction. Ensure that the
6825 constant we form is not wider than the mode of X. */
6827 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6828 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6829 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6830 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6831 && GET_CODE (XEXP (x, 1)) == CONST_INT
6832 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6833 + floor_log2 (INTVAL (XEXP (x, 1))))
6834 < GET_MODE_BITSIZE (GET_MODE (x)))
6835 && (INTVAL (XEXP (x, 1))
6836 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6838 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6839 << INTVAL (XEXP (XEXP (x, 0), 1)));
6840 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6841 XEXP (XEXP (x, 0), 0), temp);
6842 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6843 XEXP (XEXP (x, 0), 1));
6844 return force_to_mode (x, mode, mask, reg, next_select);
6848 /* For most binary operations, just propagate into the operation and
6849 change the mode if we have an operation of that mode. */
6851 op0 = gen_lowpart_for_combine (op_mode,
6852 force_to_mode (XEXP (x, 0), mode, mask,
6854 op1 = gen_lowpart_for_combine (op_mode,
6855 force_to_mode (XEXP (x, 1), mode, mask,
6858 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6859 MASK since OP1 might have been sign-extended but we never want
6860 to turn on extra bits, since combine might have previously relied
6861 on them being off. */
6862 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6863 && (INTVAL (op1) & mask) != 0)
6864 op1 = GEN_INT (INTVAL (op1) & mask);
6866 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6867 x = gen_binary (code, op_mode, op0, op1);
6871 /* For left shifts, do the same, but just for the first operand.
6872 However, we cannot do anything with shifts where we cannot
6873 guarantee that the counts are smaller than the size of the mode
6874 because such a count will have a different meaning in a
6877 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6878 && INTVAL (XEXP (x, 1)) >= 0
6879 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6880 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6881 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6882 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6885 /* If the shift count is a constant and we can do arithmetic in
6886 the mode of the shift, refine which bits we need. Otherwise, use the
6887 conservative form of the mask. */
6888 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6889 && INTVAL (XEXP (x, 1)) >= 0
6890 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6891 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6892 mask >>= INTVAL (XEXP (x, 1));
6896 op0 = gen_lowpart_for_combine (op_mode,
6897 force_to_mode (XEXP (x, 0), op_mode,
6898 mask, reg, next_select));
6900 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6901 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6905 /* Here we can only do something if the shift count is a constant,
6906 this shift constant is valid for the host, and we can do arithmetic
6909 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6910 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6911 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6913 rtx inner = XEXP (x, 0);
6914 unsigned HOST_WIDE_INT inner_mask;
6916 /* Select the mask of the bits we need for the shift operand. */
6917 inner_mask = mask << INTVAL (XEXP (x, 1));
6919 /* We can only change the mode of the shift if we can do arithmetic
6920 in the mode of the shift and INNER_MASK is no wider than the
6921 width of OP_MODE. */
6922 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6923 || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6924 op_mode = GET_MODE (x);
6926 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6928 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6929 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6932 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6933 shift and AND produces only copies of the sign bit (C2 is one less
6934 than a power of two), we can do this with just a shift. */
6936 if (GET_CODE (x) == LSHIFTRT
6937 && GET_CODE (XEXP (x, 1)) == CONST_INT
6938 /* The shift puts one of the sign bit copies in the least significant
6940 && ((INTVAL (XEXP (x, 1))
6941 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6942 >= GET_MODE_BITSIZE (GET_MODE (x)))
6943 && exact_log2 (mask + 1) >= 0
6944 /* Number of bits left after the shift must be more than the mask
6946 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6947 <= GET_MODE_BITSIZE (GET_MODE (x)))
6948 /* Must be more sign bit copies than the mask needs. */
6949 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6950 >= exact_log2 (mask + 1)))
6951 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6952 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6953 - exact_log2 (mask + 1)));
6958 /* If we are just looking for the sign bit, we don't need this shift at
6959 all, even if it has a variable count. */
6960 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6961 && (mask == ((unsigned HOST_WIDE_INT) 1
6962 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6963 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6965 /* If this is a shift by a constant, get a mask that contains those bits
6966 that are not copies of the sign bit. We then have two cases: If
6967 MASK only includes those bits, this can be a logical shift, which may
6968 allow simplifications. If MASK is a single-bit field not within
6969 those bits, we are requesting a copy of the sign bit and hence can
6970 shift the sign bit to the appropriate location. */
6972 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6973 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6977 /* If the considered data is wider then HOST_WIDE_INT, we can't
6978 represent a mask for all its bits in a single scalar.
6979 But we only care about the lower bits, so calculate these. */
6981 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6983 nonzero = ~ (HOST_WIDE_INT) 0;
6985 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6986 is the number of bits a full-width mask would have set.
6987 We need only shift if these are fewer than nonzero can
6988 hold. If not, we must keep all bits set in nonzero. */
6990 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6991 < HOST_BITS_PER_WIDE_INT)
6992 nonzero >>= INTVAL (XEXP (x, 1))
6993 + HOST_BITS_PER_WIDE_INT
6994 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6998 nonzero = GET_MODE_MASK (GET_MODE (x));
6999 nonzero >>= INTVAL (XEXP (x, 1));
7002 if ((mask & ~ nonzero) == 0
7003 || (i = exact_log2 (mask)) >= 0)
7005 x = simplify_shift_const
7006 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7007 i < 0 ? INTVAL (XEXP (x, 1))
7008 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7010 if (GET_CODE (x) != ASHIFTRT)
7011 return force_to_mode (x, mode, mask, reg, next_select);
7015 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7016 even if the shift count isn't a constant. */
7018 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7022 /* If this is a zero- or sign-extension operation that just affects bits
7023 we don't care about, remove it. Be sure the call above returned
7024 something that is still a shift. */
7026 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7027 && GET_CODE (XEXP (x, 1)) == CONST_INT
7028 && INTVAL (XEXP (x, 1)) >= 0
7029 && (INTVAL (XEXP (x, 1))
7030 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7031 && GET_CODE (XEXP (x, 0)) == ASHIFT
7032 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7033 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7034 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7041 /* If the shift count is constant and we can do computations
7042 in the mode of X, compute where the bits we care about are.
7043 Otherwise, we can't do anything. Don't change the mode of
7044 the shift or propagate MODE into the shift, though. */
7045 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7046 && INTVAL (XEXP (x, 1)) >= 0)
7048 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7049 GET_MODE (x), GEN_INT (mask),
7051 if (temp && GET_CODE(temp) == CONST_INT)
7053 force_to_mode (XEXP (x, 0), GET_MODE (x),
7054 INTVAL (temp), reg, next_select));
7059 /* If we just want the low-order bit, the NEG isn't needed since it
7060 won't change the low-order bit. */
7062 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7064 /* We need any bits less significant than the most significant bit in
7065 MASK since carries from those bits will affect the bits we are
7071 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7072 same as the XOR case above. Ensure that the constant we form is not
7073 wider than the mode of X. */
7075 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7077 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7078 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7079 < GET_MODE_BITSIZE (GET_MODE (x)))
7080 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7082 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7083 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7084 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7086 return force_to_mode (x, mode, mask, reg, next_select);
7089 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7090 use the full mask inside the NOT. */
7094 op0 = gen_lowpart_for_combine (op_mode,
7095 force_to_mode (XEXP (x, 0), mode, mask,
7097 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7098 x = gen_unary (code, op_mode, op_mode, op0);
7102 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7103 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7104 which is equal to STORE_FLAG_VALUE. */
7105 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7106 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7107 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7108 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7113 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7114 written in a narrower mode. We play it safe and do not do so. */
7117 gen_lowpart_for_combine (GET_MODE (x),
7118 force_to_mode (XEXP (x, 1), mode,
7119 mask, reg, next_select)));
7121 gen_lowpart_for_combine (GET_MODE (x),
7122 force_to_mode (XEXP (x, 2), mode,
7123 mask, reg,next_select)));
7130 /* Ensure we return a value of the proper mode. */
7131 return gen_lowpart_for_combine (mode, x);
7134 /* Return nonzero if X is an expression that has one of two values depending on
7135 whether some other value is zero or nonzero. In that case, we return the
7136 value that is being tested, *PTRUE is set to the value if the rtx being
7137 returned has a nonzero value, and *PFALSE is set to the other alternative.
7139 If we return zero, we set *PTRUE and *PFALSE to X. */
7142 if_then_else_cond (x, ptrue, pfalse)
7144 rtx *ptrue, *pfalse;
7146 enum machine_mode mode = GET_MODE (x);
7147 enum rtx_code code = GET_CODE (x);
7148 unsigned int size = GET_MODE_BITSIZE (mode);
7149 rtx cond0, cond1, true0, true1, false0, false1;
7150 unsigned HOST_WIDE_INT nz;
7152 /* If we are comparing a value against zero, we are done. */
7153 if ((code == NE || code == EQ)
7154 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7156 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7157 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7161 /* If this is a unary operation whose operand has one of two values, apply
7162 our opcode to compute those values. */
7163 else if (GET_RTX_CLASS (code) == '1'
7164 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7166 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7167 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7171 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7172 make can't possibly match and would suppress other optimizations. */
7173 else if (code == COMPARE)
7176 /* If this is a binary operation, see if either side has only one of two
7177 values. If either one does or if both do and they are conditional on
7178 the same value, compute the new true and false values. */
7179 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7180 || GET_RTX_CLASS (code) == '<')
7182 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7183 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7185 if ((cond0 != 0 || cond1 != 0)
7186 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7188 /* If if_then_else_cond returned zero, then true/false are the
7189 same rtl. We must copy one of them to prevent invalid rtl
7192 true0 = copy_rtx (true0);
7193 else if (cond1 == 0)
7194 true1 = copy_rtx (true1);
7196 *ptrue = gen_binary (code, mode, true0, true1);
7197 *pfalse = gen_binary (code, mode, false0, false1);
7198 return cond0 ? cond0 : cond1;
7201 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7202 operands is zero when the other is non-zero, and vice-versa,
7203 and STORE_FLAG_VALUE is 1 or -1. */
7205 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7206 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7208 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7210 rtx op0 = XEXP (XEXP (x, 0), 1);
7211 rtx op1 = XEXP (XEXP (x, 1), 1);
7213 cond0 = XEXP (XEXP (x, 0), 0);
7214 cond1 = XEXP (XEXP (x, 1), 0);
7216 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7217 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7218 && reversible_comparison_p (cond1)
7219 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7220 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7221 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7222 || ((swap_condition (GET_CODE (cond0))
7223 == reverse_condition (GET_CODE (cond1)))
7224 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7225 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7226 && ! side_effects_p (x))
7228 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7229 *pfalse = gen_binary (MULT, mode,
7231 ? gen_unary (NEG, mode, mode, op1) : op1),
7237 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7239 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7240 && (code == MULT || code == AND || code == UMIN)
7241 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7243 cond0 = XEXP (XEXP (x, 0), 0);
7244 cond1 = XEXP (XEXP (x, 1), 0);
7246 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7247 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7248 && reversible_comparison_p (cond1)
7249 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7250 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7251 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7252 || ((swap_condition (GET_CODE (cond0))
7253 == reverse_condition (GET_CODE (cond1)))
7254 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7255 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7256 && ! side_effects_p (x))
7258 *ptrue = *pfalse = const0_rtx;
7264 else if (code == IF_THEN_ELSE)
7266 /* If we have IF_THEN_ELSE already, extract the condition and
7267 canonicalize it if it is NE or EQ. */
7268 cond0 = XEXP (x, 0);
7269 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7270 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7271 return XEXP (cond0, 0);
7272 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7274 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7275 return XEXP (cond0, 0);
7281 /* If X is a normal SUBREG with both inner and outer modes integral,
7282 we can narrow both the true and false values of the inner expression,
7283 if there is a condition. */
7284 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7285 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7286 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7287 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7290 if ((GET_CODE (SUBREG_REG (x)) == REG
7291 || GET_CODE (SUBREG_REG (x)) == MEM
7292 || CONSTANT_P (SUBREG_REG (x)))
7293 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7294 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7296 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7297 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7299 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7301 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7306 /* If X is a constant, this isn't special and will cause confusions
7307 if we treat it as such. Likewise if it is equivalent to a constant. */
7308 else if (CONSTANT_P (x)
7309 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7312 /* If X is known to be either 0 or -1, those are the true and
7313 false values when testing X. */
7314 else if (num_sign_bit_copies (x, mode) == size)
7316 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7320 /* Likewise for 0 or a single bit. */
7321 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7323 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7327 /* Otherwise fail; show no condition with true and false values the same. */
7328 *ptrue = *pfalse = x;
7332 /* Return the value of expression X given the fact that condition COND
7333 is known to be true when applied to REG as its first operand and VAL
7334 as its second. X is known to not be shared and so can be modified in
7337 We only handle the simplest cases, and specifically those cases that
7338 arise with IF_THEN_ELSE expressions. */
7341 known_cond (x, cond, reg, val)
7346 enum rtx_code code = GET_CODE (x);
7351 if (side_effects_p (x))
7354 if (cond == EQ && rtx_equal_p (x, reg))
7357 /* If X is (abs REG) and we know something about REG's relationship
7358 with zero, we may be able to simplify this. */
7360 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7363 case GE: case GT: case EQ:
7366 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7372 /* The only other cases we handle are MIN, MAX, and comparisons if the
7373 operands are the same as REG and VAL. */
7375 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7377 if (rtx_equal_p (XEXP (x, 0), val))
7378 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7380 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7382 if (GET_RTX_CLASS (code) == '<')
7384 if (comparison_dominates_p (cond, code))
7385 return const_true_rtx;
7387 code = reverse_condition (code);
7389 && comparison_dominates_p (cond, code))
7394 else if (code == SMAX || code == SMIN
7395 || code == UMIN || code == UMAX)
7397 int unsignedp = (code == UMIN || code == UMAX);
7399 if (code == SMAX || code == UMAX)
7400 cond = reverse_condition (cond);
7405 return unsignedp ? x : XEXP (x, 1);
7407 return unsignedp ? x : XEXP (x, 0);
7409 return unsignedp ? XEXP (x, 1) : x;
7411 return unsignedp ? XEXP (x, 0) : x;
7419 fmt = GET_RTX_FORMAT (code);
7420 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7423 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7424 else if (fmt[i] == 'E')
7425 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7426 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7433 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7434 assignment as a field assignment. */
7437 rtx_equal_for_field_assignment_p (x, y)
7441 if (x == y || rtx_equal_p (x, y))
7444 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7447 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7448 Note that all SUBREGs of MEM are paradoxical; otherwise they
7449 would have been rewritten. */
7450 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7451 && GET_CODE (SUBREG_REG (y)) == MEM
7452 && rtx_equal_p (SUBREG_REG (y),
7453 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7456 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7457 && GET_CODE (SUBREG_REG (x)) == MEM
7458 && rtx_equal_p (SUBREG_REG (x),
7459 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7462 /* We used to see if get_last_value of X and Y were the same but that's
7463 not correct. In one direction, we'll cause the assignment to have
7464 the wrong destination and in the case, we'll import a register into this
7465 insn that might have already have been dead. So fail if none of the
7466 above cases are true. */
7470 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7471 Return that assignment if so.
7473 We only handle the most common cases. */
7476 make_field_assignment (x)
7479 rtx dest = SET_DEST (x);
7480 rtx src = SET_SRC (x);
7485 unsigned HOST_WIDE_INT len;
7487 enum machine_mode mode;
7489 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7490 a clear of a one-bit field. We will have changed it to
7491 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7494 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7495 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7496 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7497 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7499 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7502 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7506 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7507 && subreg_lowpart_p (XEXP (src, 0))
7508 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7509 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7510 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7511 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7512 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7514 assign = make_extraction (VOIDmode, dest, 0,
7515 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7518 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7522 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7524 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7525 && XEXP (XEXP (src, 0), 0) == const1_rtx
7526 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7528 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7531 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7535 /* The other case we handle is assignments into a constant-position
7536 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7537 a mask that has all one bits except for a group of zero bits and
7538 OTHER is known to have zeros where C1 has ones, this is such an
7539 assignment. Compute the position and length from C1. Shift OTHER
7540 to the appropriate position, force it to the required mode, and
7541 make the extraction. Check for the AND in both operands. */
7543 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7546 rhs = expand_compound_operation (XEXP (src, 0));
7547 lhs = expand_compound_operation (XEXP (src, 1));
7549 if (GET_CODE (rhs) == AND
7550 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7551 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7552 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7553 else if (GET_CODE (lhs) == AND
7554 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7555 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7556 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7560 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7561 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7562 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7563 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7566 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7570 /* The mode to use for the source is the mode of the assignment, or of
7571 what is inside a possible STRICT_LOW_PART. */
7572 mode = (GET_CODE (assign) == STRICT_LOW_PART
7573 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7575 /* Shift OTHER right POS places and make it the source, restricting it
7576 to the proper length and mode. */
7578 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7579 GET_MODE (src), other, pos),
7581 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7582 ? GET_MODE_MASK (mode)
7583 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7586 return gen_rtx_combine (SET, VOIDmode, assign, src);
7589 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7593 apply_distributive_law (x)
7596 enum rtx_code code = GET_CODE (x);
7597 rtx lhs, rhs, other;
7599 enum rtx_code inner_code;
7601 /* Distributivity is not true for floating point.
7602 It can change the value. So don't do it.
7603 -- rms and moshier@world.std.com. */
7604 if (FLOAT_MODE_P (GET_MODE (x)))
7607 /* The outer operation can only be one of the following: */
7608 if (code != IOR && code != AND && code != XOR
7609 && code != PLUS && code != MINUS)
7612 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7614 /* If either operand is a primitive we can't do anything, so get out
7616 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7617 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7620 lhs = expand_compound_operation (lhs);
7621 rhs = expand_compound_operation (rhs);
7622 inner_code = GET_CODE (lhs);
7623 if (inner_code != GET_CODE (rhs))
7626 /* See if the inner and outer operations distribute. */
7633 /* These all distribute except over PLUS. */
7634 if (code == PLUS || code == MINUS)
7639 if (code != PLUS && code != MINUS)
7644 /* This is also a multiply, so it distributes over everything. */
7648 /* Non-paradoxical SUBREGs distributes over all operations, provided
7649 the inner modes and word numbers are the same, this is an extraction
7650 of a low-order part, we don't convert an fp operation to int or
7651 vice versa, and we would not be converting a single-word
7652 operation into a multi-word operation. The latter test is not
7653 required, but it prevents generating unneeded multi-word operations.
7654 Some of the previous tests are redundant given the latter test, but
7655 are retained because they are required for correctness.
7657 We produce the result slightly differently in this case. */
7659 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7660 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7661 || ! subreg_lowpart_p (lhs)
7662 || (GET_MODE_CLASS (GET_MODE (lhs))
7663 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7664 || (GET_MODE_SIZE (GET_MODE (lhs))
7665 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7666 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7669 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7670 SUBREG_REG (lhs), SUBREG_REG (rhs));
7671 return gen_lowpart_for_combine (GET_MODE (x), tem);
7677 /* Set LHS and RHS to the inner operands (A and B in the example
7678 above) and set OTHER to the common operand (C in the example).
7679 These is only one way to do this unless the inner operation is
7681 if (GET_RTX_CLASS (inner_code) == 'c'
7682 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7683 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7684 else if (GET_RTX_CLASS (inner_code) == 'c'
7685 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7686 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7687 else if (GET_RTX_CLASS (inner_code) == 'c'
7688 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7689 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7690 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7691 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7695 /* Form the new inner operation, seeing if it simplifies first. */
7696 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7698 /* There is one exception to the general way of distributing:
7699 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7700 if (code == XOR && inner_code == IOR)
7703 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7706 /* We may be able to continuing distributing the result, so call
7707 ourselves recursively on the inner operation before forming the
7708 outer operation, which we return. */
7709 return gen_binary (inner_code, GET_MODE (x),
7710 apply_distributive_law (tem), other);
7713 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7716 Return an equivalent form, if different from X. Otherwise, return X. If
7717 X is zero, we are to always construct the equivalent form. */
7720 simplify_and_const_int (x, mode, varop, constop)
7722 enum machine_mode mode;
7724 unsigned HOST_WIDE_INT constop;
7726 unsigned HOST_WIDE_INT nonzero;
7729 /* Simplify VAROP knowing that we will be only looking at some of the
7731 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7733 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7734 CONST_INT, we are done. */
7735 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7738 /* See what bits may be nonzero in VAROP. Unlike the general case of
7739 a call to nonzero_bits, here we don't care about bits outside
7742 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7743 nonzero = trunc_int_for_mode (nonzero, mode);
7745 /* Turn off all bits in the constant that are known to already be zero.
7746 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7747 which is tested below. */
7751 /* If we don't have any bits left, return zero. */
7755 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7756 a power of two, we can replace this with a ASHIFT. */
7757 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7758 && (i = exact_log2 (constop)) >= 0)
7759 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7761 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7762 or XOR, then try to apply the distributive law. This may eliminate
7763 operations if either branch can be simplified because of the AND.
7764 It may also make some cases more complex, but those cases probably
7765 won't match a pattern either with or without this. */
7767 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7769 gen_lowpart_for_combine
7771 apply_distributive_law
7772 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7773 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7774 XEXP (varop, 0), constop),
7775 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7776 XEXP (varop, 1), constop))));
7778 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7779 if we already had one (just check for the simplest cases). */
7780 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7781 && GET_MODE (XEXP (x, 0)) == mode
7782 && SUBREG_REG (XEXP (x, 0)) == varop)
7783 varop = XEXP (x, 0);
7785 varop = gen_lowpart_for_combine (mode, varop);
7787 /* If we can't make the SUBREG, try to return what we were given. */
7788 if (GET_CODE (varop) == CLOBBER)
7789 return x ? x : varop;
7791 /* If we are only masking insignificant bits, return VAROP. */
7792 if (constop == nonzero)
7795 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7796 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7797 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7801 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7802 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7803 SUBST (XEXP (x, 1), GEN_INT (constop));
7805 SUBST (XEXP (x, 0), varop);
7811 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7812 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7813 is less useful. We can't allow both, because that results in exponential
7814 run time recursion. There is a nullstone testcase that triggered
7815 this. This macro avoids accidental uses of num_sign_bit_copies. */
7816 #define num_sign_bit_copies()
7818 /* Given an expression, X, compute which bits in X can be non-zero.
7819 We don't care about bits outside of those defined in MODE.
7821 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7822 a shift, AND, or zero_extract, we can do better. */
7824 static unsigned HOST_WIDE_INT
7825 nonzero_bits (x, mode)
7827 enum machine_mode mode;
7829 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7830 unsigned HOST_WIDE_INT inner_nz;
7832 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7835 /* For floating-point values, assume all bits are needed. */
7836 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7839 /* If X is wider than MODE, use its mode instead. */
7840 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7842 mode = GET_MODE (x);
7843 nonzero = GET_MODE_MASK (mode);
7844 mode_width = GET_MODE_BITSIZE (mode);
7847 if (mode_width > HOST_BITS_PER_WIDE_INT)
7848 /* Our only callers in this case look for single bit values. So
7849 just return the mode mask. Those tests will then be false. */
7852 #ifndef WORD_REGISTER_OPERATIONS
7853 /* If MODE is wider than X, but both are a single word for both the host
7854 and target machines, we can compute this from which bits of the
7855 object might be nonzero in its own mode, taking into account the fact
7856 that on many CISC machines, accessing an object in a wider mode
7857 causes the high-order bits to become undefined. So they are
7858 not known to be zero. */
7860 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7861 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7863 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7865 nonzero &= nonzero_bits (x, GET_MODE (x));
7866 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7871 code = GET_CODE (x);
7875 #ifdef POINTERS_EXTEND_UNSIGNED
7876 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7877 all the bits above ptr_mode are known to be zero. */
7878 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7879 && REGNO_POINTER_FLAG (REGNO (x)))
7880 nonzero &= GET_MODE_MASK (ptr_mode);
7883 #ifdef STACK_BOUNDARY
7884 /* If this is the stack pointer, we may know something about its
7885 alignment. If PUSH_ROUNDING is defined, it is possible for the
7886 stack to be momentarily aligned only to that amount, so we pick
7887 the least alignment. */
7889 /* We can't check for arg_pointer_rtx here, because it is not
7890 guaranteed to have as much alignment as the stack pointer.
7891 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7892 alignment but the argument pointer has only 64 bit alignment. */
7894 if ((x == frame_pointer_rtx
7895 || x == stack_pointer_rtx
7896 || x == hard_frame_pointer_rtx
7897 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7898 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7904 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7906 #ifdef PUSH_ROUNDING
7907 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7908 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7911 /* We must return here, otherwise we may get a worse result from
7912 one of the choices below. There is nothing useful below as
7913 far as the stack pointer is concerned. */
7914 return nonzero &= ~ (sp_alignment - 1);
7918 /* If X is a register whose nonzero bits value is current, use it.
7919 Otherwise, if X is a register whose value we can find, use that
7920 value. Otherwise, use the previously-computed global nonzero bits
7921 for this register. */
7923 if (reg_last_set_value[REGNO (x)] != 0
7924 && reg_last_set_mode[REGNO (x)] == mode
7925 && (reg_last_set_label[REGNO (x)] == label_tick
7926 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7927 && REG_N_SETS (REGNO (x)) == 1
7928 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7930 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7931 return reg_last_set_nonzero_bits[REGNO (x)];
7933 tem = get_last_value (x);
7937 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7938 /* If X is narrower than MODE and TEM is a non-negative
7939 constant that would appear negative in the mode of X,
7940 sign-extend it for use in reg_nonzero_bits because some
7941 machines (maybe most) will actually do the sign-extension
7942 and this is the conservative approach.
7944 ??? For 2.5, try to tighten up the MD files in this regard
7945 instead of this kludge. */
7947 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7948 && GET_CODE (tem) == CONST_INT
7950 && 0 != (INTVAL (tem)
7951 & ((HOST_WIDE_INT) 1
7952 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7953 tem = GEN_INT (INTVAL (tem)
7954 | ((HOST_WIDE_INT) (-1)
7955 << GET_MODE_BITSIZE (GET_MODE (x))));
7957 return nonzero_bits (tem, mode);
7959 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7960 return reg_nonzero_bits[REGNO (x)] & nonzero;
7965 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7966 /* If X is negative in MODE, sign-extend the value. */
7967 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7968 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7969 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7975 #ifdef LOAD_EXTEND_OP
7976 /* In many, if not most, RISC machines, reading a byte from memory
7977 zeros the rest of the register. Noticing that fact saves a lot
7978 of extra zero-extends. */
7979 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7980 nonzero &= GET_MODE_MASK (GET_MODE (x));
7990 /* If this produces an integer result, we know which bits are set.
7991 Code here used to clear bits outside the mode of X, but that is
7994 if (GET_MODE_CLASS (mode) == MODE_INT
7995 && mode_width <= HOST_BITS_PER_WIDE_INT)
7996 nonzero = STORE_FLAG_VALUE;
8001 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8002 and num_sign_bit_copies. */
8003 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8004 == GET_MODE_BITSIZE (GET_MODE (x)))
8008 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8009 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
8014 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8015 and num_sign_bit_copies. */
8016 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8017 == GET_MODE_BITSIZE (GET_MODE (x)))
8023 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8027 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8028 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8029 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8033 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8034 Otherwise, show all the bits in the outer mode but not the inner
8036 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8037 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8039 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8041 & (((HOST_WIDE_INT) 1
8042 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8043 inner_nz |= (GET_MODE_MASK (mode)
8044 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8047 nonzero &= inner_nz;
8051 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8052 & nonzero_bits (XEXP (x, 1), mode));
8056 case UMIN: case UMAX: case SMIN: case SMAX:
8057 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8058 | nonzero_bits (XEXP (x, 1), mode));
8061 case PLUS: case MINUS:
8063 case DIV: case UDIV:
8064 case MOD: case UMOD:
8065 /* We can apply the rules of arithmetic to compute the number of
8066 high- and low-order zero bits of these operations. We start by
8067 computing the width (position of the highest-order non-zero bit)
8068 and the number of low-order zero bits for each value. */
8070 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8071 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8072 int width0 = floor_log2 (nz0) + 1;
8073 int width1 = floor_log2 (nz1) + 1;
8074 int low0 = floor_log2 (nz0 & -nz0);
8075 int low1 = floor_log2 (nz1 & -nz1);
8076 HOST_WIDE_INT op0_maybe_minusp
8077 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8078 HOST_WIDE_INT op1_maybe_minusp
8079 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8080 unsigned int result_width = mode_width;
8088 && (XEXP (x, 0) == stack_pointer_rtx
8089 || XEXP (x, 0) == frame_pointer_rtx)
8090 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8092 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8094 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8095 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8096 width0 = floor_log2 (nz0) + 1;
8097 width1 = floor_log2 (nz1) + 1;
8098 low0 = floor_log2 (nz0 & -nz0);
8099 low1 = floor_log2 (nz1 & -nz1);
8102 result_width = MAX (width0, width1) + 1;
8103 result_low = MIN (low0, low1);
8106 result_low = MIN (low0, low1);
8109 result_width = width0 + width1;
8110 result_low = low0 + low1;
8113 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8114 result_width = width0;
8117 result_width = width0;
8120 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8121 result_width = MIN (width0, width1);
8122 result_low = MIN (low0, low1);
8125 result_width = MIN (width0, width1);
8126 result_low = MIN (low0, low1);
8132 if (result_width < mode_width)
8133 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8136 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8141 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8142 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8143 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8147 /* If this is a SUBREG formed for a promoted variable that has
8148 been zero-extended, we know that at least the high-order bits
8149 are zero, though others might be too. */
8151 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8152 nonzero = (GET_MODE_MASK (GET_MODE (x))
8153 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8155 /* If the inner mode is a single word for both the host and target
8156 machines, we can compute this from which bits of the inner
8157 object might be nonzero. */
8158 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8159 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8160 <= HOST_BITS_PER_WIDE_INT))
8162 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8164 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8165 /* If this is a typical RISC machine, we only have to worry
8166 about the way loads are extended. */
8167 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8169 & (((unsigned HOST_WIDE_INT) 1
8170 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8172 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8175 /* On many CISC machines, accessing an object in a wider mode
8176 causes the high-order bits to become undefined. So they are
8177 not known to be zero. */
8178 if (GET_MODE_SIZE (GET_MODE (x))
8179 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8180 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8181 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8190 /* The nonzero bits are in two classes: any bits within MODE
8191 that aren't in GET_MODE (x) are always significant. The rest of the
8192 nonzero bits are those that are significant in the operand of
8193 the shift when shifted the appropriate number of bits. This
8194 shows that high-order bits are cleared by the right shift and
8195 low-order bits by left shifts. */
8196 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8197 && INTVAL (XEXP (x, 1)) >= 0
8198 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8200 enum machine_mode inner_mode = GET_MODE (x);
8201 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8202 int count = INTVAL (XEXP (x, 1));
8203 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8204 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8205 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8206 unsigned HOST_WIDE_INT outer = 0;
8208 if (mode_width > width)
8209 outer = (op_nonzero & nonzero & ~ mode_mask);
8211 if (code == LSHIFTRT)
8213 else if (code == ASHIFTRT)
8217 /* If the sign bit may have been nonzero before the shift, we
8218 need to mark all the places it could have been copied to
8219 by the shift as possibly nonzero. */
8220 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8221 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8223 else if (code == ASHIFT)
8226 inner = ((inner << (count % width)
8227 | (inner >> (width - (count % width)))) & mode_mask);
8229 nonzero &= (outer | inner);
8234 /* This is at most the number of bits in the mode. */
8235 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8239 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8240 | nonzero_bits (XEXP (x, 2), mode));
8250 /* See the macro definition above. */
8251 #undef num_sign_bit_copies
8253 /* Return the number of bits at the high-order end of X that are known to
8254 be equal to the sign bit. X will be used in mode MODE; if MODE is
8255 VOIDmode, X will be used in its own mode. The returned value will always
8256 be between 1 and the number of bits in MODE. */
8259 num_sign_bit_copies (x, mode)
8261 enum machine_mode mode;
8263 enum rtx_code code = GET_CODE (x);
8264 unsigned int bitwidth;
8265 int num0, num1, result;
8266 unsigned HOST_WIDE_INT nonzero;
8269 /* If we weren't given a mode, use the mode of X. If the mode is still
8270 VOIDmode, we don't know anything. Likewise if one of the modes is
8273 if (mode == VOIDmode)
8274 mode = GET_MODE (x);
8276 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8279 bitwidth = GET_MODE_BITSIZE (mode);
8281 /* For a smaller object, just ignore the high bits. */
8282 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8284 num0 = num_sign_bit_copies (x, GET_MODE (x));
8286 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8289 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8291 #ifndef WORD_REGISTER_OPERATIONS
8292 /* If this machine does not do all register operations on the entire
8293 register and MODE is wider than the mode of X, we can say nothing
8294 at all about the high-order bits. */
8297 /* Likewise on machines that do, if the mode of the object is smaller
8298 than a word and loads of that size don't sign extend, we can say
8299 nothing about the high order bits. */
8300 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8301 #ifdef LOAD_EXTEND_OP
8302 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8313 #ifdef POINTERS_EXTEND_UNSIGNED
8314 /* If pointers extend signed and this is a pointer in Pmode, say that
8315 all the bits above ptr_mode are known to be sign bit copies. */
8316 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8317 && REGNO_POINTER_FLAG (REGNO (x)))
8318 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8321 if (reg_last_set_value[REGNO (x)] != 0
8322 && reg_last_set_mode[REGNO (x)] == mode
8323 && (reg_last_set_label[REGNO (x)] == label_tick
8324 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8325 && REG_N_SETS (REGNO (x)) == 1
8326 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8328 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8329 return reg_last_set_sign_bit_copies[REGNO (x)];
8331 tem = get_last_value (x);
8333 return num_sign_bit_copies (tem, mode);
8335 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8336 return reg_sign_bit_copies[REGNO (x)];
8340 #ifdef LOAD_EXTEND_OP
8341 /* Some RISC machines sign-extend all loads of smaller than a word. */
8342 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8343 return MAX (1, ((int) bitwidth
8344 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8349 /* If the constant is negative, take its 1's complement and remask.
8350 Then see how many zero bits we have. */
8351 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8352 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8353 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8354 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8356 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8359 /* If this is a SUBREG for a promoted object that is sign-extended
8360 and we are looking at it in a wider mode, we know that at least the
8361 high-order bits are known to be sign bit copies. */
8363 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8365 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8366 return MAX ((int) bitwidth
8367 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8371 /* For a smaller object, just ignore the high bits. */
8372 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8374 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8375 return MAX (1, (num0
8376 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8380 #ifdef WORD_REGISTER_OPERATIONS
8381 #ifdef LOAD_EXTEND_OP
8382 /* For paradoxical SUBREGs on machines where all register operations
8383 affect the entire register, just look inside. Note that we are
8384 passing MODE to the recursive call, so the number of sign bit copies
8385 will remain relative to that mode, not the inner mode. */
8387 /* This works only if loads sign extend. Otherwise, if we get a
8388 reload for the inner part, it may be loaded from the stack, and
8389 then we lose all sign bit copies that existed before the store
8392 if ((GET_MODE_SIZE (GET_MODE (x))
8393 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8394 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8395 return num_sign_bit_copies (SUBREG_REG (x), mode);
8401 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8402 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8406 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8407 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8410 /* For a smaller object, just ignore the high bits. */
8411 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8412 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8416 return num_sign_bit_copies (XEXP (x, 0), mode);
8418 case ROTATE: case ROTATERT:
8419 /* If we are rotating left by a number of bits less than the number
8420 of sign bit copies, we can just subtract that amount from the
8422 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8423 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8425 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8426 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8427 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8432 /* In general, this subtracts one sign bit copy. But if the value
8433 is known to be positive, the number of sign bit copies is the
8434 same as that of the input. Finally, if the input has just one bit
8435 that might be nonzero, all the bits are copies of the sign bit. */
8436 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8437 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8438 return num0 > 1 ? num0 - 1 : 1;
8440 nonzero = nonzero_bits (XEXP (x, 0), mode);
8445 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8450 case IOR: case AND: case XOR:
8451 case SMIN: case SMAX: case UMIN: case UMAX:
8452 /* Logical operations will preserve the number of sign-bit copies.
8453 MIN and MAX operations always return one of the operands. */
8454 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8455 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8456 return MIN (num0, num1);
8458 case PLUS: case MINUS:
8459 /* For addition and subtraction, we can have a 1-bit carry. However,
8460 if we are subtracting 1 from a positive number, there will not
8461 be such a carry. Furthermore, if the positive number is known to
8462 be 0 or 1, we know the result is either -1 or 0. */
8464 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8465 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8467 nonzero = nonzero_bits (XEXP (x, 0), mode);
8468 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8469 return (nonzero == 1 || nonzero == 0 ? bitwidth
8470 : bitwidth - floor_log2 (nonzero) - 1);
8473 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8474 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8475 return MAX (1, MIN (num0, num1) - 1);
8478 /* The number of bits of the product is the sum of the number of
8479 bits of both terms. However, unless one of the terms if known
8480 to be positive, we must allow for an additional bit since negating
8481 a negative number can remove one sign bit copy. */
8483 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8484 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8486 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8488 && (bitwidth > HOST_BITS_PER_WIDE_INT
8489 || (((nonzero_bits (XEXP (x, 0), mode)
8490 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8491 && ((nonzero_bits (XEXP (x, 1), mode)
8492 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8495 return MAX (1, result);
8498 /* The result must be <= the first operand. If the first operand
8499 has the high bit set, we know nothing about the number of sign
8501 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8503 else if ((nonzero_bits (XEXP (x, 0), mode)
8504 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8507 return num_sign_bit_copies (XEXP (x, 0), mode);
8510 /* The result must be <= the scond operand. */
8511 return num_sign_bit_copies (XEXP (x, 1), mode);
8514 /* Similar to unsigned division, except that we have to worry about
8515 the case where the divisor is negative, in which case we have
8517 result = num_sign_bit_copies (XEXP (x, 0), mode);
8519 && (bitwidth > HOST_BITS_PER_WIDE_INT
8520 || (nonzero_bits (XEXP (x, 1), mode)
8521 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8527 result = num_sign_bit_copies (XEXP (x, 1), mode);
8529 && (bitwidth > HOST_BITS_PER_WIDE_INT
8530 || (nonzero_bits (XEXP (x, 1), mode)
8531 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8537 /* Shifts by a constant add to the number of bits equal to the
8539 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8540 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8541 && INTVAL (XEXP (x, 1)) > 0)
8542 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8547 /* Left shifts destroy copies. */
8548 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8549 || INTVAL (XEXP (x, 1)) < 0
8550 || INTVAL (XEXP (x, 1)) >= bitwidth)
8553 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8554 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8557 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8558 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8559 return MIN (num0, num1);
8561 case EQ: case NE: case GE: case GT: case LE: case LT:
8562 case GEU: case GTU: case LEU: case LTU:
8563 if (STORE_FLAG_VALUE == -1)
8571 /* If we haven't been able to figure it out by one of the above rules,
8572 see if some of the high-order bits are known to be zero. If so,
8573 count those bits and return one less than that amount. If we can't
8574 safely compute the mask for this mode, always return BITWIDTH. */
8576 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8579 nonzero = nonzero_bits (x, mode);
8580 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8581 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8584 /* Return the number of "extended" bits there are in X, when interpreted
8585 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8586 unsigned quantities, this is the number of high-order zero bits.
8587 For signed quantities, this is the number of copies of the sign bit
8588 minus 1. In both case, this function returns the number of "spare"
8589 bits. For example, if two quantities for which this function returns
8590 at least 1 are added, the addition is known not to overflow.
8592 This function will always return 0 unless called during combine, which
8593 implies that it must be called from a define_split. */
8596 extended_count (x, mode, unsignedp)
8598 enum machine_mode mode;
8601 if (nonzero_sign_valid == 0)
8605 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8606 ? (GET_MODE_BITSIZE (mode) - 1
8607 - floor_log2 (nonzero_bits (x, mode)))
8609 : num_sign_bit_copies (x, mode) - 1);
8612 /* This function is called from `simplify_shift_const' to merge two
8613 outer operations. Specifically, we have already found that we need
8614 to perform operation *POP0 with constant *PCONST0 at the outermost
8615 position. We would now like to also perform OP1 with constant CONST1
8616 (with *POP0 being done last).
8618 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8619 the resulting operation. *PCOMP_P is set to 1 if we would need to
8620 complement the innermost operand, otherwise it is unchanged.
8622 MODE is the mode in which the operation will be done. No bits outside
8623 the width of this mode matter. It is assumed that the width of this mode
8624 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8626 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8627 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8628 result is simply *PCONST0.
8630 If the resulting operation cannot be expressed as one operation, we
8631 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8634 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8635 enum rtx_code *pop0;
8636 HOST_WIDE_INT *pconst0;
8638 HOST_WIDE_INT const1;
8639 enum machine_mode mode;
8642 enum rtx_code op0 = *pop0;
8643 HOST_WIDE_INT const0 = *pconst0;
8645 const0 &= GET_MODE_MASK (mode);
8646 const1 &= GET_MODE_MASK (mode);
8648 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8652 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8655 if (op1 == NIL || op0 == SET)
8658 else if (op0 == NIL)
8659 op0 = op1, const0 = const1;
8661 else if (op0 == op1)
8685 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8686 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8689 /* If the two constants aren't the same, we can't do anything. The
8690 remaining six cases can all be done. */
8691 else if (const0 != const1)
8699 /* (a & b) | b == b */
8701 else /* op1 == XOR */
8702 /* (a ^ b) | b == a | b */
8708 /* (a & b) ^ b == (~a) & b */
8709 op0 = AND, *pcomp_p = 1;
8710 else /* op1 == IOR */
8711 /* (a | b) ^ b == a & ~b */
8712 op0 = AND, *pconst0 = ~ const0;
8717 /* (a | b) & b == b */
8719 else /* op1 == XOR */
8720 /* (a ^ b) & b) == (~a) & b */
8727 /* Check for NO-OP cases. */
8728 const0 &= GET_MODE_MASK (mode);
8730 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8732 else if (const0 == 0 && op0 == AND)
8734 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8738 /* ??? Slightly redundant with the above mask, but not entirely.
8739 Moving this above means we'd have to sign-extend the mode mask
8740 for the final test. */
8741 const0 = trunc_int_for_mode (const0, mode);
8749 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8750 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8751 that we started with.
8753 The shift is normally computed in the widest mode we find in VAROP, as
8754 long as it isn't a different number of words than RESULT_MODE. Exceptions
8755 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8758 simplify_shift_const (x, code, result_mode, varop, input_count)
8761 enum machine_mode result_mode;
8765 enum rtx_code orig_code = code;
8766 int orig_count = input_count;
8769 enum machine_mode mode = result_mode;
8770 enum machine_mode shift_mode, tmode;
8771 unsigned int mode_words
8772 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8773 /* We form (outer_op (code varop count) (outer_const)). */
8774 enum rtx_code outer_op = NIL;
8775 HOST_WIDE_INT outer_const = 0;
8777 int complement_p = 0;
8780 /* If we were given an invalid count, don't do anything except exactly
8781 what was requested. */
8783 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8788 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8791 count = input_count;
8793 /* Unless one of the branches of the `if' in this loop does a `continue',
8794 we will `break' the loop after the `if'. */
8798 /* If we have an operand of (clobber (const_int 0)), just return that
8800 if (GET_CODE (varop) == CLOBBER)
8803 /* If we discovered we had to complement VAROP, leave. Making a NOT
8804 here would cause an infinite loop. */
8808 /* Convert ROTATERT to ROTATE. */
8809 if (code == ROTATERT)
8810 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8812 /* We need to determine what mode we will do the shift in. If the
8813 shift is a right shift or a ROTATE, we must always do it in the mode
8814 it was originally done in. Otherwise, we can do it in MODE, the
8815 widest mode encountered. */
8817 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8818 ? result_mode : mode);
8820 /* Handle cases where the count is greater than the size of the mode
8821 minus 1. For ASHIFT, use the size minus one as the count (this can
8822 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8823 take the count modulo the size. For other shifts, the result is
8826 Since these shifts are being produced by the compiler by combining
8827 multiple operations, each of which are defined, we know what the
8828 result is supposed to be. */
8830 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8832 if (code == ASHIFTRT)
8833 count = GET_MODE_BITSIZE (shift_mode) - 1;
8834 else if (code == ROTATE || code == ROTATERT)
8835 count %= GET_MODE_BITSIZE (shift_mode);
8838 /* We can't simply return zero because there may be an
8846 /* An arithmetic right shift of a quantity known to be -1 or 0
8848 if (code == ASHIFTRT
8849 && (num_sign_bit_copies (varop, shift_mode)
8850 == GET_MODE_BITSIZE (shift_mode)))
8856 /* If we are doing an arithmetic right shift and discarding all but
8857 the sign bit copies, this is equivalent to doing a shift by the
8858 bitsize minus one. Convert it into that shift because it will often
8859 allow other simplifications. */
8861 if (code == ASHIFTRT
8862 && (count + num_sign_bit_copies (varop, shift_mode)
8863 >= GET_MODE_BITSIZE (shift_mode)))
8864 count = GET_MODE_BITSIZE (shift_mode) - 1;
8866 /* We simplify the tests below and elsewhere by converting
8867 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8868 `make_compound_operation' will convert it to a ASHIFTRT for
8869 those machines (such as Vax) that don't have a LSHIFTRT. */
8870 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8872 && ((nonzero_bits (varop, shift_mode)
8873 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8877 switch (GET_CODE (varop))
8883 new = expand_compound_operation (varop);
8892 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8893 minus the width of a smaller mode, we can do this with a
8894 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8895 if ((code == ASHIFTRT || code == LSHIFTRT)
8896 && ! mode_dependent_address_p (XEXP (varop, 0))
8897 && ! MEM_VOLATILE_P (varop)
8898 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8899 MODE_INT, 1)) != BLKmode)
8901 if (BYTES_BIG_ENDIAN)
8902 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8904 new = gen_rtx_MEM (tmode,
8905 plus_constant (XEXP (varop, 0),
8906 count / BITS_PER_UNIT));
8907 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8908 MEM_COPY_ATTRIBUTES (new, varop);
8909 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8910 : ZERO_EXTEND, mode, new);
8917 /* Similar to the case above, except that we can only do this if
8918 the resulting mode is the same as that of the underlying
8919 MEM and adjust the address depending on the *bits* endianness
8920 because of the way that bit-field extract insns are defined. */
8921 if ((code == ASHIFTRT || code == LSHIFTRT)
8922 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8923 MODE_INT, 1)) != BLKmode
8924 && tmode == GET_MODE (XEXP (varop, 0)))
8926 if (BITS_BIG_ENDIAN)
8927 new = XEXP (varop, 0);
8930 new = copy_rtx (XEXP (varop, 0));
8931 SUBST (XEXP (new, 0),
8932 plus_constant (XEXP (new, 0),
8933 count / BITS_PER_UNIT));
8936 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8937 : ZERO_EXTEND, mode, new);
8944 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8945 the same number of words as what we've seen so far. Then store
8946 the widest mode in MODE. */
8947 if (subreg_lowpart_p (varop)
8948 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8949 > GET_MODE_SIZE (GET_MODE (varop)))
8950 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8951 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8954 varop = SUBREG_REG (varop);
8955 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8956 mode = GET_MODE (varop);
8962 /* Some machines use MULT instead of ASHIFT because MULT
8963 is cheaper. But it is still better on those machines to
8964 merge two shifts into one. */
8965 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8966 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8969 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8970 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8976 /* Similar, for when divides are cheaper. */
8977 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8978 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8981 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8982 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8988 /* If we are extracting just the sign bit of an arithmetic right
8989 shift, that shift is not needed. */
8990 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8992 varop = XEXP (varop, 0);
8996 /* ... fall through ... */
9001 /* Here we have two nested shifts. The result is usually the
9002 AND of a new shift with a mask. We compute the result below. */
9003 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9004 && INTVAL (XEXP (varop, 1)) >= 0
9005 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9006 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9007 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9009 enum rtx_code first_code = GET_CODE (varop);
9010 unsigned int first_count = INTVAL (XEXP (varop, 1));
9011 unsigned HOST_WIDE_INT mask;
9014 /* We have one common special case. We can't do any merging if
9015 the inner code is an ASHIFTRT of a smaller mode. However, if
9016 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9017 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9018 we can convert it to
9019 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9020 This simplifies certain SIGN_EXTEND operations. */
9021 if (code == ASHIFT && first_code == ASHIFTRT
9022 && (GET_MODE_BITSIZE (result_mode)
9023 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9025 /* C3 has the low-order C1 bits zero. */
9027 mask = (GET_MODE_MASK (mode)
9028 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
9030 varop = simplify_and_const_int (NULL_RTX, result_mode,
9031 XEXP (varop, 0), mask);
9032 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9034 count = first_count;
9039 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9040 than C1 high-order bits equal to the sign bit, we can convert
9041 this to either an ASHIFT or a ASHIFTRT depending on the
9044 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9046 if (code == ASHIFTRT && first_code == ASHIFT
9047 && GET_MODE (varop) == shift_mode
9048 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9051 varop = XEXP (varop, 0);
9053 signed_count = count - first_count;
9054 if (signed_count < 0)
9055 count = - signed_count, code = ASHIFT;
9057 count = signed_count;
9062 /* There are some cases we can't do. If CODE is ASHIFTRT,
9063 we can only do this if FIRST_CODE is also ASHIFTRT.
9065 We can't do the case when CODE is ROTATE and FIRST_CODE is
9068 If the mode of this shift is not the mode of the outer shift,
9069 we can't do this if either shift is a right shift or ROTATE.
9071 Finally, we can't do any of these if the mode is too wide
9072 unless the codes are the same.
9074 Handle the case where the shift codes are the same
9077 if (code == first_code)
9079 if (GET_MODE (varop) != result_mode
9080 && (code == ASHIFTRT || code == LSHIFTRT
9084 count += first_count;
9085 varop = XEXP (varop, 0);
9089 if (code == ASHIFTRT
9090 || (code == ROTATE && first_code == ASHIFTRT)
9091 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9092 || (GET_MODE (varop) != result_mode
9093 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9094 || first_code == ROTATE
9095 || code == ROTATE)))
9098 /* To compute the mask to apply after the shift, shift the
9099 nonzero bits of the inner shift the same way the
9100 outer shift will. */
9102 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9105 = simplify_binary_operation (code, result_mode, mask_rtx,
9108 /* Give up if we can't compute an outer operation to use. */
9110 || GET_CODE (mask_rtx) != CONST_INT
9111 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9113 result_mode, &complement_p))
9116 /* If the shifts are in the same direction, we add the
9117 counts. Otherwise, we subtract them. */
9118 signed_count = count;
9119 if ((code == ASHIFTRT || code == LSHIFTRT)
9120 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9121 signed_count += first_count;
9123 signed_count -= first_count;
9125 /* If COUNT is positive, the new shift is usually CODE,
9126 except for the two exceptions below, in which case it is
9127 FIRST_CODE. If the count is negative, FIRST_CODE should
9129 if (signed_count > 0
9130 && ((first_code == ROTATE && code == ASHIFT)
9131 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9132 code = first_code, count = signed_count;
9133 else if (signed_count < 0)
9134 code = first_code, count = - signed_count;
9136 count = signed_count;
9138 varop = XEXP (varop, 0);
9142 /* If we have (A << B << C) for any shift, we can convert this to
9143 (A << C << B). This wins if A is a constant. Only try this if
9144 B is not a constant. */
9146 else if (GET_CODE (varop) == code
9147 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9149 = simplify_binary_operation (code, mode,
9153 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9160 /* Make this fit the case below. */
9161 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9162 GEN_INT (GET_MODE_MASK (mode)));
9168 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9169 with C the size of VAROP - 1 and the shift is logical if
9170 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9171 we have an (le X 0) operation. If we have an arithmetic shift
9172 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9173 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9175 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9176 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9177 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9178 && (code == LSHIFTRT || code == ASHIFTRT)
9179 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9180 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9183 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9186 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9187 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9192 /* If we have (shift (logical)), move the logical to the outside
9193 to allow it to possibly combine with another logical and the
9194 shift to combine with another shift. This also canonicalizes to
9195 what a ZERO_EXTRACT looks like. Also, some machines have
9196 (and (shift)) insns. */
9198 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9199 && (new = simplify_binary_operation (code, result_mode,
9201 GEN_INT (count))) != 0
9202 && GET_CODE(new) == CONST_INT
9203 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9204 INTVAL (new), result_mode, &complement_p))
9206 varop = XEXP (varop, 0);
9210 /* If we can't do that, try to simplify the shift in each arm of the
9211 logical expression, make a new logical expression, and apply
9212 the inverse distributive law. */
9214 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9215 XEXP (varop, 0), count);
9216 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9217 XEXP (varop, 1), count);
9219 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9220 varop = apply_distributive_law (varop);
9227 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9228 says that the sign bit can be tested, FOO has mode MODE, C is
9229 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9230 that may be nonzero. */
9231 if (code == LSHIFTRT
9232 && XEXP (varop, 1) == const0_rtx
9233 && GET_MODE (XEXP (varop, 0)) == result_mode
9234 && count == GET_MODE_BITSIZE (result_mode) - 1
9235 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9236 && ((STORE_FLAG_VALUE
9237 & ((HOST_WIDE_INT) 1
9238 < (GET_MODE_BITSIZE (result_mode) - 1))))
9239 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9240 && merge_outer_ops (&outer_op, &outer_const, XOR,
9241 (HOST_WIDE_INT) 1, result_mode,
9244 varop = XEXP (varop, 0);
9251 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9252 than the number of bits in the mode is equivalent to A. */
9253 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9254 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9256 varop = XEXP (varop, 0);
9261 /* NEG commutes with ASHIFT since it is multiplication. Move the
9262 NEG outside to allow shifts to combine. */
9264 && merge_outer_ops (&outer_op, &outer_const, NEG,
9265 (HOST_WIDE_INT) 0, result_mode,
9268 varop = XEXP (varop, 0);
9274 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9275 is one less than the number of bits in the mode is
9276 equivalent to (xor A 1). */
9277 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9278 && XEXP (varop, 1) == constm1_rtx
9279 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9280 && merge_outer_ops (&outer_op, &outer_const, XOR,
9281 (HOST_WIDE_INT) 1, result_mode,
9285 varop = XEXP (varop, 0);
9289 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9290 that might be nonzero in BAR are those being shifted out and those
9291 bits are known zero in FOO, we can replace the PLUS with FOO.
9292 Similarly in the other operand order. This code occurs when
9293 we are computing the size of a variable-size array. */
9295 if ((code == ASHIFTRT || code == LSHIFTRT)
9296 && count < HOST_BITS_PER_WIDE_INT
9297 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9298 && (nonzero_bits (XEXP (varop, 1), result_mode)
9299 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9301 varop = XEXP (varop, 0);
9304 else if ((code == ASHIFTRT || code == LSHIFTRT)
9305 && count < HOST_BITS_PER_WIDE_INT
9306 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9307 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9309 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9310 & nonzero_bits (XEXP (varop, 1),
9313 varop = XEXP (varop, 1);
9317 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9319 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9320 && (new = simplify_binary_operation (ASHIFT, result_mode,
9322 GEN_INT (count))) != 0
9323 && GET_CODE (new) == CONST_INT
9324 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9325 INTVAL (new), result_mode, &complement_p))
9327 varop = XEXP (varop, 0);
9333 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9334 with C the size of VAROP - 1 and the shift is logical if
9335 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9336 we have a (gt X 0) operation. If the shift is arithmetic with
9337 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9338 we have a (neg (gt X 0)) operation. */
9340 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9341 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9342 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9343 && (code == LSHIFTRT || code == ASHIFTRT)
9344 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9345 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9346 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9349 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9352 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9353 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9360 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9361 if the truncate does not affect the value. */
9362 if (code == LSHIFTRT
9363 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9364 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9365 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9366 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9367 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9369 rtx varop_inner = XEXP (varop, 0);
9372 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9373 XEXP (varop_inner, 0),
9375 + INTVAL (XEXP (varop_inner, 1))));
9376 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9390 /* We need to determine what mode to do the shift in. If the shift is
9391 a right shift or ROTATE, we must always do it in the mode it was
9392 originally done in. Otherwise, we can do it in MODE, the widest mode
9393 encountered. The code we care about is that of the shift that will
9394 actually be done, not the shift that was originally requested. */
9396 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9397 ? result_mode : mode);
9399 /* We have now finished analyzing the shift. The result should be
9400 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9401 OUTER_OP is non-NIL, it is an operation that needs to be applied
9402 to the result of the shift. OUTER_CONST is the relevant constant,
9403 but we must turn off all bits turned off in the shift.
9405 If we were passed a value for X, see if we can use any pieces of
9406 it. If not, make new rtx. */
9408 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9409 && GET_CODE (XEXP (x, 1)) == CONST_INT
9410 && INTVAL (XEXP (x, 1)) == count)
9411 const_rtx = XEXP (x, 1);
9413 const_rtx = GEN_INT (count);
9415 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9416 && GET_MODE (XEXP (x, 0)) == shift_mode
9417 && SUBREG_REG (XEXP (x, 0)) == varop)
9418 varop = XEXP (x, 0);
9419 else if (GET_MODE (varop) != shift_mode)
9420 varop = gen_lowpart_for_combine (shift_mode, varop);
9422 /* If we can't make the SUBREG, try to return what we were given. */
9423 if (GET_CODE (varop) == CLOBBER)
9424 return x ? x : varop;
9426 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9431 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9432 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9434 SUBST (XEXP (x, 0), varop);
9435 SUBST (XEXP (x, 1), const_rtx);
9438 /* If we have an outer operation and we just made a shift, it is
9439 possible that we could have simplified the shift were it not
9440 for the outer operation. So try to do the simplification
9443 if (outer_op != NIL && GET_CODE (x) == code
9444 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9445 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9446 INTVAL (XEXP (x, 1)));
9448 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9449 turn off all the bits that the shift would have turned off. */
9450 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9451 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9452 GET_MODE_MASK (result_mode) >> orig_count);
9454 /* Do the remainder of the processing in RESULT_MODE. */
9455 x = gen_lowpart_for_combine (result_mode, x);
9457 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9460 x = gen_unary (NOT, result_mode, result_mode, x);
9462 if (outer_op != NIL)
9464 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9465 outer_const = trunc_int_for_mode (outer_const, result_mode);
9467 if (outer_op == AND)
9468 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9469 else if (outer_op == SET)
9470 /* This means that we have determined that the result is
9471 equivalent to a constant. This should be rare. */
9472 x = GEN_INT (outer_const);
9473 else if (GET_RTX_CLASS (outer_op) == '1')
9474 x = gen_unary (outer_op, result_mode, result_mode, x);
9476 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9482 /* Like recog, but we receive the address of a pointer to a new pattern.
9483 We try to match the rtx that the pointer points to.
9484 If that fails, we may try to modify or replace the pattern,
9485 storing the replacement into the same pointer object.
9487 Modifications include deletion or addition of CLOBBERs.
9489 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9490 the CLOBBERs are placed.
9492 The value is the final insn code from the pattern ultimately matched,
9496 recog_for_combine (pnewpat, insn, pnotes)
9501 register rtx pat = *pnewpat;
9502 int insn_code_number;
9503 int num_clobbers_to_add = 0;
9507 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9508 we use to indicate that something didn't match. If we find such a
9509 thing, force rejection. */
9510 if (GET_CODE (pat) == PARALLEL)
9511 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9512 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9513 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9516 /* Is the result of combination a valid instruction? */
9517 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9519 /* If it isn't, there is the possibility that we previously had an insn
9520 that clobbered some register as a side effect, but the combined
9521 insn doesn't need to do that. So try once more without the clobbers
9522 unless this represents an ASM insn. */
9524 if (insn_code_number < 0 && ! check_asm_operands (pat)
9525 && GET_CODE (pat) == PARALLEL)
9529 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9530 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9533 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9537 SUBST_INT (XVECLEN (pat, 0), pos);
9540 pat = XVECEXP (pat, 0, 0);
9542 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9545 /* If we had any clobbers to add, make a new pattern than contains
9546 them. Then check to make sure that all of them are dead. */
9547 if (num_clobbers_to_add)
9549 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9550 gen_rtvec (GET_CODE (pat) == PARALLEL
9552 + num_clobbers_to_add)
9553 : num_clobbers_to_add + 1));
9555 if (GET_CODE (pat) == PARALLEL)
9556 for (i = 0; i < XVECLEN (pat, 0); i++)
9557 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9559 XVECEXP (newpat, 0, 0) = pat;
9561 add_clobbers (newpat, insn_code_number);
9563 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9564 i < XVECLEN (newpat, 0); i++)
9566 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9567 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9569 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9570 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9578 return insn_code_number;
9581 /* Like gen_lowpart but for use by combine. In combine it is not possible
9582 to create any new pseudoregs. However, it is safe to create
9583 invalid memory addresses, because combine will try to recognize
9584 them and all they will do is make the combine attempt fail.
9586 If for some reason this cannot do its job, an rtx
9587 (clobber (const_int 0)) is returned.
9588 An insn containing that will not be recognized. */
9593 gen_lowpart_for_combine (mode, x)
9594 enum machine_mode mode;
9599 if (GET_MODE (x) == mode)
9602 /* We can only support MODE being wider than a word if X is a
9603 constant integer or has a mode the same size. */
9605 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9606 && ! ((GET_MODE (x) == VOIDmode
9607 && (GET_CODE (x) == CONST_INT
9608 || GET_CODE (x) == CONST_DOUBLE))
9609 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9610 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9612 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9613 won't know what to do. So we will strip off the SUBREG here and
9614 process normally. */
9615 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9618 if (GET_MODE (x) == mode)
9622 result = gen_lowpart_common (mode, x);
9624 && GET_CODE (result) == SUBREG
9625 && GET_CODE (SUBREG_REG (result)) == REG
9626 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9627 && (GET_MODE_SIZE (GET_MODE (result))
9628 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9629 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9634 if (GET_CODE (x) == MEM)
9636 register int offset = 0;
9639 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9641 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9642 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9644 /* If we want to refer to something bigger than the original memref,
9645 generate a perverse subreg instead. That will force a reload
9646 of the original memref X. */
9647 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9648 return gen_rtx_SUBREG (mode, x, 0);
9650 if (WORDS_BIG_ENDIAN)
9651 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9652 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9654 if (BYTES_BIG_ENDIAN)
9656 /* Adjust the address so that the address-after-the-data is
9658 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9659 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9661 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9662 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9663 MEM_COPY_ATTRIBUTES (new, x);
9667 /* If X is a comparison operator, rewrite it in a new mode. This
9668 probably won't match, but may allow further simplifications. */
9669 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9670 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9672 /* If we couldn't simplify X any other way, just enclose it in a
9673 SUBREG. Normally, this SUBREG won't match, but some patterns may
9674 include an explicit SUBREG or we may simplify it further in combine. */
9679 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9680 word = ((GET_MODE_SIZE (GET_MODE (x))
9681 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9683 return gen_rtx_SUBREG (mode, x, word);
9687 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9688 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9690 If the identical expression was previously in the insn (in the undobuf),
9691 it will be returned. Only if it is not found will a new expression
9696 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9698 #ifndef ANSI_PROTOTYPES
9700 enum machine_mode mode;
9712 #ifndef ANSI_PROTOTYPES
9713 code = va_arg (p, enum rtx_code);
9714 mode = va_arg (p, enum machine_mode);
9717 n_args = GET_RTX_LENGTH (code);
9718 fmt = GET_RTX_FORMAT (code);
9720 if (n_args == 0 || n_args > 3)
9723 /* Get each arg and verify that it is supposed to be an expression. */
9724 for (j = 0; j < n_args; j++)
9729 args[j] = va_arg (p, rtx);
9734 /* See if this is in undobuf. Be sure we don't use objects that came
9735 from another insn; this could produce circular rtl structures. */
9737 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9739 && GET_CODE (undo->old_contents.r) == code
9740 && GET_MODE (undo->old_contents.r) == mode)
9742 for (j = 0; j < n_args; j++)
9743 if (XEXP (undo->old_contents.r, j) != args[j])
9747 return undo->old_contents.r;
9750 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9751 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9752 rt = rtx_alloc (code);
9753 PUT_MODE (rt, mode);
9754 XEXP (rt, 0) = args[0];
9757 XEXP (rt, 1) = args[1];
9759 XEXP (rt, 2) = args[2];
9764 /* These routines make binary and unary operations by first seeing if they
9765 fold; if not, a new expression is allocated. */
9768 gen_binary (code, mode, op0, op1)
9770 enum machine_mode mode;
9776 if (GET_RTX_CLASS (code) == 'c'
9777 && (GET_CODE (op0) == CONST_INT
9778 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9779 tem = op0, op0 = op1, op1 = tem;
9781 if (GET_RTX_CLASS (code) == '<')
9783 enum machine_mode op_mode = GET_MODE (op0);
9785 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9786 just (REL_OP X Y). */
9787 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9789 op1 = XEXP (op0, 1);
9790 op0 = XEXP (op0, 0);
9791 op_mode = GET_MODE (op0);
9794 if (op_mode == VOIDmode)
9795 op_mode = GET_MODE (op1);
9796 result = simplify_relational_operation (code, op_mode, op0, op1);
9799 result = simplify_binary_operation (code, mode, op0, op1);
9804 /* Put complex operands first and constants second. */
9805 if (GET_RTX_CLASS (code) == 'c'
9806 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9807 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9808 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9809 || (GET_CODE (op0) == SUBREG
9810 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9811 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9812 return gen_rtx_combine (code, mode, op1, op0);
9814 /* If we are turning off bits already known off in OP0, we need not do
9816 else if (code == AND && GET_CODE (op1) == CONST_INT
9817 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9818 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9821 return gen_rtx_combine (code, mode, op0, op1);
9825 gen_unary (code, mode, op0_mode, op0)
9827 enum machine_mode mode, op0_mode;
9830 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9835 return gen_rtx_combine (code, mode, op0);
9838 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9839 comparison code that will be tested.
9841 The result is a possibly different comparison code to use. *POP0 and
9842 *POP1 may be updated.
9844 It is possible that we might detect that a comparison is either always
9845 true or always false. However, we do not perform general constant
9846 folding in combine, so this knowledge isn't useful. Such tautologies
9847 should have been detected earlier. Hence we ignore all such cases. */
9849 static enum rtx_code
9850 simplify_comparison (code, pop0, pop1)
9859 enum machine_mode mode, tmode;
9861 /* Try a few ways of applying the same transformation to both operands. */
9864 #ifndef WORD_REGISTER_OPERATIONS
9865 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9866 so check specially. */
9867 if (code != GTU && code != GEU && code != LTU && code != LEU
9868 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9869 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9870 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9871 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9872 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9873 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9874 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9875 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9876 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9877 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9878 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9879 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9880 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9881 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9882 && (INTVAL (XEXP (op0, 1))
9883 == (GET_MODE_BITSIZE (GET_MODE (op0))
9885 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9887 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9888 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9892 /* If both operands are the same constant shift, see if we can ignore the
9893 shift. We can if the shift is a rotate or if the bits shifted out of
9894 this shift are known to be zero for both inputs and if the type of
9895 comparison is compatible with the shift. */
9896 if (GET_CODE (op0) == GET_CODE (op1)
9897 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9898 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9899 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9900 && (code != GT && code != LT && code != GE && code != LE))
9901 || (GET_CODE (op0) == ASHIFTRT
9902 && (code != GTU && code != LTU
9903 && code != GEU && code != GEU)))
9904 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9905 && INTVAL (XEXP (op0, 1)) >= 0
9906 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9907 && XEXP (op0, 1) == XEXP (op1, 1))
9909 enum machine_mode mode = GET_MODE (op0);
9910 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9911 int shift_count = INTVAL (XEXP (op0, 1));
9913 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9914 mask &= (mask >> shift_count) << shift_count;
9915 else if (GET_CODE (op0) == ASHIFT)
9916 mask = (mask & (mask << shift_count)) >> shift_count;
9918 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9919 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9920 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9925 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9926 SUBREGs are of the same mode, and, in both cases, the AND would
9927 be redundant if the comparison was done in the narrower mode,
9928 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9929 and the operand's possibly nonzero bits are 0xffffff01; in that case
9930 if we only care about QImode, we don't need the AND). This case
9931 occurs if the output mode of an scc insn is not SImode and
9932 STORE_FLAG_VALUE == 1 (e.g., the 386).
9934 Similarly, check for a case where the AND's are ZERO_EXTEND
9935 operations from some narrower mode even though a SUBREG is not
9938 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9939 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9940 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9942 rtx inner_op0 = XEXP (op0, 0);
9943 rtx inner_op1 = XEXP (op1, 0);
9944 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9945 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9948 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9949 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9950 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9951 && (GET_MODE (SUBREG_REG (inner_op0))
9952 == GET_MODE (SUBREG_REG (inner_op1)))
9953 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9954 <= HOST_BITS_PER_WIDE_INT)
9955 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9956 GET_MODE (SUBREG_REG (inner_op0)))))
9957 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9958 GET_MODE (SUBREG_REG (inner_op1))))))
9960 op0 = SUBREG_REG (inner_op0);
9961 op1 = SUBREG_REG (inner_op1);
9963 /* The resulting comparison is always unsigned since we masked
9964 off the original sign bit. */
9965 code = unsigned_condition (code);
9971 for (tmode = GET_CLASS_NARROWEST_MODE
9972 (GET_MODE_CLASS (GET_MODE (op0)));
9973 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9974 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9976 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9977 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9978 code = unsigned_condition (code);
9987 /* If both operands are NOT, we can strip off the outer operation
9988 and adjust the comparison code for swapped operands; similarly for
9989 NEG, except that this must be an equality comparison. */
9990 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9991 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9992 && (code == EQ || code == NE)))
9993 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9999 /* If the first operand is a constant, swap the operands and adjust the
10000 comparison code appropriately, but don't do this if the second operand
10001 is already a constant integer. */
10002 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10004 tem = op0, op0 = op1, op1 = tem;
10005 code = swap_condition (code);
10008 /* We now enter a loop during which we will try to simplify the comparison.
10009 For the most part, we only are concerned with comparisons with zero,
10010 but some things may really be comparisons with zero but not start
10011 out looking that way. */
10013 while (GET_CODE (op1) == CONST_INT)
10015 enum machine_mode mode = GET_MODE (op0);
10016 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10017 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10018 int equality_comparison_p;
10019 int sign_bit_comparison_p;
10020 int unsigned_comparison_p;
10021 HOST_WIDE_INT const_op;
10023 /* We only want to handle integral modes. This catches VOIDmode,
10024 CCmode, and the floating-point modes. An exception is that we
10025 can handle VOIDmode if OP0 is a COMPARE or a comparison
10028 if (GET_MODE_CLASS (mode) != MODE_INT
10029 && ! (mode == VOIDmode
10030 && (GET_CODE (op0) == COMPARE
10031 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10034 /* Get the constant we are comparing against and turn off all bits
10035 not on in our mode. */
10036 const_op = INTVAL (op1);
10037 if (mode_width <= HOST_BITS_PER_WIDE_INT)
10040 /* If we are comparing against a constant power of two and the value
10041 being compared can only have that single bit nonzero (e.g., it was
10042 `and'ed with that bit), we can replace this with a comparison
10045 && (code == EQ || code == NE || code == GE || code == GEU
10046 || code == LT || code == LTU)
10047 && mode_width <= HOST_BITS_PER_WIDE_INT
10048 && exact_log2 (const_op) >= 0
10049 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10051 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10052 op1 = const0_rtx, const_op = 0;
10055 /* Similarly, if we are comparing a value known to be either -1 or
10056 0 with -1, change it to the opposite comparison against zero. */
10059 && (code == EQ || code == NE || code == GT || code == LE
10060 || code == GEU || code == LTU)
10061 && num_sign_bit_copies (op0, mode) == mode_width)
10063 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10064 op1 = const0_rtx, const_op = 0;
10067 /* Do some canonicalizations based on the comparison code. We prefer
10068 comparisons against zero and then prefer equality comparisons.
10069 If we can reduce the size of a constant, we will do that too. */
10074 /* < C is equivalent to <= (C - 1) */
10078 op1 = GEN_INT (const_op);
10080 /* ... fall through to LE case below. */
10086 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10090 op1 = GEN_INT (const_op);
10094 /* If we are doing a <= 0 comparison on a value known to have
10095 a zero sign bit, we can replace this with == 0. */
10096 else if (const_op == 0
10097 && mode_width <= HOST_BITS_PER_WIDE_INT
10098 && (nonzero_bits (op0, mode)
10099 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10104 /* >= C is equivalent to > (C - 1). */
10108 op1 = GEN_INT (const_op);
10110 /* ... fall through to GT below. */
10116 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10120 op1 = GEN_INT (const_op);
10124 /* If we are doing a > 0 comparison on a value known to have
10125 a zero sign bit, we can replace this with != 0. */
10126 else if (const_op == 0
10127 && mode_width <= HOST_BITS_PER_WIDE_INT
10128 && (nonzero_bits (op0, mode)
10129 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10134 /* < C is equivalent to <= (C - 1). */
10138 op1 = GEN_INT (const_op);
10140 /* ... fall through ... */
10143 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10144 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10145 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10147 const_op = 0, op1 = const0_rtx;
10155 /* unsigned <= 0 is equivalent to == 0 */
10159 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10160 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10161 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10163 const_op = 0, op1 = const0_rtx;
10169 /* >= C is equivalent to < (C - 1). */
10173 op1 = GEN_INT (const_op);
10175 /* ... fall through ... */
10178 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10179 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10180 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10182 const_op = 0, op1 = const0_rtx;
10190 /* unsigned > 0 is equivalent to != 0 */
10194 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10195 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10196 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10198 const_op = 0, op1 = const0_rtx;
10207 /* Compute some predicates to simplify code below. */
10209 equality_comparison_p = (code == EQ || code == NE);
10210 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10211 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10214 /* If this is a sign bit comparison and we can do arithmetic in
10215 MODE, say that we will only be needing the sign bit of OP0. */
10216 if (sign_bit_comparison_p
10217 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10218 op0 = force_to_mode (op0, mode,
10220 << (GET_MODE_BITSIZE (mode) - 1)),
10223 /* Now try cases based on the opcode of OP0. If none of the cases
10224 does a "continue", we exit this loop immediately after the
10227 switch (GET_CODE (op0))
10230 /* If we are extracting a single bit from a variable position in
10231 a constant that has only a single bit set and are comparing it
10232 with zero, we can convert this into an equality comparison
10233 between the position and the location of the single bit. */
10235 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10236 && XEXP (op0, 1) == const1_rtx
10237 && equality_comparison_p && const_op == 0
10238 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10240 if (BITS_BIG_ENDIAN)
10243 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10244 if (mode == VOIDmode)
10246 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10248 i = BITS_PER_WORD - 1 - i;
10252 op0 = XEXP (op0, 2);
10256 /* Result is nonzero iff shift count is equal to I. */
10257 code = reverse_condition (code);
10261 /* ... fall through ... */
10264 tem = expand_compound_operation (op0);
10273 /* If testing for equality, we can take the NOT of the constant. */
10274 if (equality_comparison_p
10275 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10277 op0 = XEXP (op0, 0);
10282 /* If just looking at the sign bit, reverse the sense of the
10284 if (sign_bit_comparison_p)
10286 op0 = XEXP (op0, 0);
10287 code = (code == GE ? LT : GE);
10293 /* If testing for equality, we can take the NEG of the constant. */
10294 if (equality_comparison_p
10295 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10297 op0 = XEXP (op0, 0);
10302 /* The remaining cases only apply to comparisons with zero. */
10306 /* When X is ABS or is known positive,
10307 (neg X) is < 0 if and only if X != 0. */
10309 if (sign_bit_comparison_p
10310 && (GET_CODE (XEXP (op0, 0)) == ABS
10311 || (mode_width <= HOST_BITS_PER_WIDE_INT
10312 && (nonzero_bits (XEXP (op0, 0), mode)
10313 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10315 op0 = XEXP (op0, 0);
10316 code = (code == LT ? NE : EQ);
10320 /* If we have NEG of something whose two high-order bits are the
10321 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10322 if (num_sign_bit_copies (op0, mode) >= 2)
10324 op0 = XEXP (op0, 0);
10325 code = swap_condition (code);
10331 /* If we are testing equality and our count is a constant, we
10332 can perform the inverse operation on our RHS. */
10333 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10334 && (tem = simplify_binary_operation (ROTATERT, mode,
10335 op1, XEXP (op0, 1))) != 0)
10337 op0 = XEXP (op0, 0);
10342 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10343 a particular bit. Convert it to an AND of a constant of that
10344 bit. This will be converted into a ZERO_EXTRACT. */
10345 if (const_op == 0 && sign_bit_comparison_p
10346 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10347 && mode_width <= HOST_BITS_PER_WIDE_INT)
10349 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10352 - INTVAL (XEXP (op0, 1)))));
10353 code = (code == LT ? NE : EQ);
10357 /* ... fall through ... */
10360 /* ABS is ignorable inside an equality comparison with zero. */
10361 if (const_op == 0 && equality_comparison_p)
10363 op0 = XEXP (op0, 0);
10370 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10371 to (compare FOO CONST) if CONST fits in FOO's mode and we
10372 are either testing inequality or have an unsigned comparison
10373 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10374 if (! unsigned_comparison_p
10375 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10376 <= HOST_BITS_PER_WIDE_INT)
10377 && ((unsigned HOST_WIDE_INT) const_op
10378 < (((unsigned HOST_WIDE_INT) 1
10379 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10381 op0 = XEXP (op0, 0);
10387 /* Check for the case where we are comparing A - C1 with C2,
10388 both constants are smaller than 1/2 the maximum positive
10389 value in MODE, and the comparison is equality or unsigned.
10390 In that case, if A is either zero-extended to MODE or has
10391 sufficient sign bits so that the high-order bit in MODE
10392 is a copy of the sign in the inner mode, we can prove that it is
10393 safe to do the operation in the wider mode. This simplifies
10394 many range checks. */
10396 if (mode_width <= HOST_BITS_PER_WIDE_INT
10397 && subreg_lowpart_p (op0)
10398 && GET_CODE (SUBREG_REG (op0)) == PLUS
10399 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10400 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10401 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10402 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10403 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10404 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10405 GET_MODE (SUBREG_REG (op0)))
10406 & ~ GET_MODE_MASK (mode))
10407 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10408 GET_MODE (SUBREG_REG (op0)))
10409 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10410 - GET_MODE_BITSIZE (mode)))))
10412 op0 = SUBREG_REG (op0);
10416 /* If the inner mode is narrower and we are extracting the low part,
10417 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10418 if (subreg_lowpart_p (op0)
10419 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10420 /* Fall through */ ;
10424 /* ... fall through ... */
10427 if ((unsigned_comparison_p || equality_comparison_p)
10428 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10429 <= HOST_BITS_PER_WIDE_INT)
10430 && ((unsigned HOST_WIDE_INT) const_op
10431 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10433 op0 = XEXP (op0, 0);
10439 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10440 this for equality comparisons due to pathological cases involving
10442 if (equality_comparison_p
10443 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10444 op1, XEXP (op0, 1))))
10446 op0 = XEXP (op0, 0);
10451 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10452 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10453 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10455 op0 = XEXP (XEXP (op0, 0), 0);
10456 code = (code == LT ? EQ : NE);
10462 /* We used to optimize signed comparisons against zero, but that
10463 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10464 arrive here as equality comparisons, or (GEU, LTU) are
10465 optimized away. No need to special-case them. */
10467 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10468 (eq B (minus A C)), whichever simplifies. We can only do
10469 this for equality comparisons due to pathological cases involving
10471 if (equality_comparison_p
10472 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10473 XEXP (op0, 1), op1)))
10475 op0 = XEXP (op0, 0);
10480 if (equality_comparison_p
10481 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10482 XEXP (op0, 0), op1)))
10484 op0 = XEXP (op0, 1);
10489 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10490 of bits in X minus 1, is one iff X > 0. */
10491 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10492 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10493 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10494 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10496 op0 = XEXP (op0, 1);
10497 code = (code == GE ? LE : GT);
10503 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10504 if C is zero or B is a constant. */
10505 if (equality_comparison_p
10506 && 0 != (tem = simplify_binary_operation (XOR, mode,
10507 XEXP (op0, 1), op1)))
10509 op0 = XEXP (op0, 0);
10516 case LT: case LTU: case LE: case LEU:
10517 case GT: case GTU: case GE: case GEU:
10518 /* We can't do anything if OP0 is a condition code value, rather
10519 than an actual data value. */
10522 || XEXP (op0, 0) == cc0_rtx
10524 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10527 /* Get the two operands being compared. */
10528 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10529 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10531 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10533 /* Check for the cases where we simply want the result of the
10534 earlier test or the opposite of that result. */
10536 || (code == EQ && reversible_comparison_p (op0))
10537 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10538 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10539 && (STORE_FLAG_VALUE
10540 & (((HOST_WIDE_INT) 1
10541 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10543 || (code == GE && reversible_comparison_p (op0)))))
10545 code = (code == LT || code == NE
10546 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10547 op0 = tem, op1 = tem1;
10553 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10555 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10556 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10557 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10559 op0 = XEXP (op0, 1);
10560 code = (code == GE ? GT : LE);
10566 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10567 will be converted to a ZERO_EXTRACT later. */
10568 if (const_op == 0 && equality_comparison_p
10569 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10570 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10572 op0 = simplify_and_const_int
10573 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10575 XEXP (XEXP (op0, 0), 1)),
10576 (HOST_WIDE_INT) 1);
10580 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10581 zero and X is a comparison and C1 and C2 describe only bits set
10582 in STORE_FLAG_VALUE, we can compare with X. */
10583 if (const_op == 0 && equality_comparison_p
10584 && mode_width <= HOST_BITS_PER_WIDE_INT
10585 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10586 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10587 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10588 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10589 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10591 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10592 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10593 if ((~ STORE_FLAG_VALUE & mask) == 0
10594 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10595 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10596 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10598 op0 = XEXP (XEXP (op0, 0), 0);
10603 /* If we are doing an equality comparison of an AND of a bit equal
10604 to the sign bit, replace this with a LT or GE comparison of
10605 the underlying value. */
10606 if (equality_comparison_p
10608 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10609 && mode_width <= HOST_BITS_PER_WIDE_INT
10610 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10611 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10613 op0 = XEXP (op0, 0);
10614 code = (code == EQ ? GE : LT);
10618 /* If this AND operation is really a ZERO_EXTEND from a narrower
10619 mode, the constant fits within that mode, and this is either an
10620 equality or unsigned comparison, try to do this comparison in
10621 the narrower mode. */
10622 if ((equality_comparison_p || unsigned_comparison_p)
10623 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10624 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10625 & GET_MODE_MASK (mode))
10627 && const_op >> i == 0
10628 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10630 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10634 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10635 in both M1 and M2 and the SUBREG is either paradoxical or
10636 represents the low part, permute the SUBREG and the AND and
10638 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10640 #ifdef WORD_REGISTER_OPERATIONS
10642 > (GET_MODE_BITSIZE
10643 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10644 && mode_width <= BITS_PER_WORD)
10647 <= (GET_MODE_BITSIZE
10648 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10649 && subreg_lowpart_p (XEXP (op0, 0))))
10650 #ifndef WORD_REGISTER_OPERATIONS
10651 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10652 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10653 As originally written the upper bits have a defined value
10654 due to the AND operation. However, if we commute the AND
10655 inside the SUBREG then they no longer have defined values
10656 and the meaning of the code has been changed. */
10657 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10658 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10660 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10661 && mode_width <= HOST_BITS_PER_WIDE_INT
10662 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10663 <= HOST_BITS_PER_WIDE_INT)
10664 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10665 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10666 & INTVAL (XEXP (op0, 1)))
10667 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10668 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10669 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10673 = gen_lowpart_for_combine
10675 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10676 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10683 /* If we have (compare (ashift FOO N) (const_int C)) and
10684 the high order N bits of FOO (N+1 if an inequality comparison)
10685 are known to be zero, we can do this by comparing FOO with C
10686 shifted right N bits so long as the low-order N bits of C are
10688 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10689 && INTVAL (XEXP (op0, 1)) >= 0
10690 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10691 < HOST_BITS_PER_WIDE_INT)
10693 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10694 && mode_width <= HOST_BITS_PER_WIDE_INT
10695 && (nonzero_bits (XEXP (op0, 0), mode)
10696 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10697 + ! equality_comparison_p))) == 0)
10699 /* We must perform a logical shift, not an arithmetic one,
10700 as we want the top N bits of C to be zero. */
10701 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10703 temp >>= INTVAL (XEXP (op0, 1));
10704 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10705 op0 = XEXP (op0, 0);
10709 /* If we are doing a sign bit comparison, it means we are testing
10710 a particular bit. Convert it to the appropriate AND. */
10711 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10712 && mode_width <= HOST_BITS_PER_WIDE_INT)
10714 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10717 - INTVAL (XEXP (op0, 1)))));
10718 code = (code == LT ? NE : EQ);
10722 /* If this an equality comparison with zero and we are shifting
10723 the low bit to the sign bit, we can convert this to an AND of the
10725 if (const_op == 0 && equality_comparison_p
10726 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10727 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10729 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10730 (HOST_WIDE_INT) 1);
10736 /* If this is an equality comparison with zero, we can do this
10737 as a logical shift, which might be much simpler. */
10738 if (equality_comparison_p && const_op == 0
10739 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10741 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10743 INTVAL (XEXP (op0, 1)));
10747 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10748 do the comparison in a narrower mode. */
10749 if (! unsigned_comparison_p
10750 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10751 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10752 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10753 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10754 MODE_INT, 1)) != BLKmode
10755 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10756 || ((unsigned HOST_WIDE_INT) - const_op
10757 <= GET_MODE_MASK (tmode))))
10759 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10763 /* Likewise if OP0 is a PLUS of a sign extension with a
10764 constant, which is usually represented with the PLUS
10765 between the shifts. */
10766 if (! unsigned_comparison_p
10767 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10768 && GET_CODE (XEXP (op0, 0)) == PLUS
10769 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10770 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10771 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10772 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10773 MODE_INT, 1)) != BLKmode
10774 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10775 || ((unsigned HOST_WIDE_INT) - const_op
10776 <= GET_MODE_MASK (tmode))))
10778 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10779 rtx add_const = XEXP (XEXP (op0, 0), 1);
10780 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10783 op0 = gen_binary (PLUS, tmode,
10784 gen_lowpart_for_combine (tmode, inner),
10789 /* ... fall through ... */
10791 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10792 the low order N bits of FOO are known to be zero, we can do this
10793 by comparing FOO with C shifted left N bits so long as no
10794 overflow occurs. */
10795 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10796 && INTVAL (XEXP (op0, 1)) >= 0
10797 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10798 && mode_width <= HOST_BITS_PER_WIDE_INT
10799 && (nonzero_bits (XEXP (op0, 0), mode)
10800 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10802 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10805 const_op <<= INTVAL (XEXP (op0, 1));
10806 op1 = GEN_INT (const_op);
10807 op0 = XEXP (op0, 0);
10811 /* If we are using this shift to extract just the sign bit, we
10812 can replace this with an LT or GE comparison. */
10814 && (equality_comparison_p || sign_bit_comparison_p)
10815 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10816 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10818 op0 = XEXP (op0, 0);
10819 code = (code == NE || code == GT ? LT : GE);
10831 /* Now make any compound operations involved in this comparison. Then,
10832 check for an outmost SUBREG on OP0 that is not doing anything or is
10833 paradoxical. The latter case can only occur when it is known that the
10834 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10835 We can never remove a SUBREG for a non-equality comparison because the
10836 sign bit is in a different place in the underlying object. */
10838 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10839 op1 = make_compound_operation (op1, SET);
10841 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10842 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10843 && (code == NE || code == EQ)
10844 && ((GET_MODE_SIZE (GET_MODE (op0))
10845 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10847 op0 = SUBREG_REG (op0);
10848 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10851 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10852 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10853 && (code == NE || code == EQ)
10854 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10855 <= HOST_BITS_PER_WIDE_INT)
10856 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10857 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10858 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10860 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10861 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10862 op0 = SUBREG_REG (op0), op1 = tem;
10864 /* We now do the opposite procedure: Some machines don't have compare
10865 insns in all modes. If OP0's mode is an integer mode smaller than a
10866 word and we can't do a compare in that mode, see if there is a larger
10867 mode for which we can do the compare. There are a number of cases in
10868 which we can use the wider mode. */
10870 mode = GET_MODE (op0);
10871 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10872 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10873 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10874 for (tmode = GET_MODE_WIDER_MODE (mode);
10876 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10877 tmode = GET_MODE_WIDER_MODE (tmode))
10878 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10880 /* If the only nonzero bits in OP0 and OP1 are those in the
10881 narrower mode and this is an equality or unsigned comparison,
10882 we can use the wider mode. Similarly for sign-extended
10883 values, in which case it is true for all comparisons. */
10884 if (((code == EQ || code == NE
10885 || code == GEU || code == GTU || code == LEU || code == LTU)
10886 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10887 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10888 || ((num_sign_bit_copies (op0, tmode)
10889 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10890 && (num_sign_bit_copies (op1, tmode)
10891 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10893 /* If OP0 is an AND and we don't have an AND in MODE either,
10894 make a new AND in the proper mode. */
10895 if (GET_CODE (op0) == AND
10896 && (add_optab->handlers[(int) mode].insn_code
10897 == CODE_FOR_nothing))
10898 op0 = gen_binary (AND, tmode,
10899 gen_lowpart_for_combine (tmode,
10901 gen_lowpart_for_combine (tmode,
10904 op0 = gen_lowpart_for_combine (tmode, op0);
10905 op1 = gen_lowpart_for_combine (tmode, op1);
10909 /* If this is a test for negative, we can make an explicit
10910 test of the sign bit. */
10912 if (op1 == const0_rtx && (code == LT || code == GE)
10913 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10915 op0 = gen_binary (AND, tmode,
10916 gen_lowpart_for_combine (tmode, op0),
10917 GEN_INT ((HOST_WIDE_INT) 1
10918 << (GET_MODE_BITSIZE (mode) - 1)));
10919 code = (code == LT) ? NE : EQ;
10924 #ifdef CANONICALIZE_COMPARISON
10925 /* If this machine only supports a subset of valid comparisons, see if we
10926 can convert an unsupported one into a supported one. */
10927 CANONICALIZE_COMPARISON (code, op0, op1);
10936 /* Return 1 if we know that X, a comparison operation, is not operating
10937 on a floating-point value or is EQ or NE, meaning that we can safely
10941 reversible_comparison_p (x)
10944 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10946 || GET_CODE (x) == NE || GET_CODE (x) == EQ
10947 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
10950 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10953 case MODE_PARTIAL_INT:
10954 case MODE_COMPLEX_INT:
10958 /* If the mode of the condition codes tells us that this is safe,
10959 we need look no further. */
10960 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10963 /* Otherwise try and find where the condition codes were last set and
10965 x = get_last_value (XEXP (x, 0));
10966 return (x && GET_CODE (x) == COMPARE
10967 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10974 /* Utility function for following routine. Called when X is part of a value
10975 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10976 for each register mentioned. Similar to mention_regs in cse.c */
10979 update_table_tick (x)
10982 register enum rtx_code code = GET_CODE (x);
10983 register const char *fmt = GET_RTX_FORMAT (code);
10988 unsigned int regno = REGNO (x);
10989 unsigned int endregno
10990 = regno + (regno < FIRST_PSEUDO_REGISTER
10991 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10994 for (r = regno; r < endregno; r++)
10995 reg_last_set_table_tick[r] = label_tick;
11000 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11001 /* Note that we can't have an "E" in values stored; see
11002 get_last_value_validate. */
11004 update_table_tick (XEXP (x, i));
11007 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11008 are saying that the register is clobbered and we no longer know its
11009 value. If INSN is zero, don't update reg_last_set; this is only permitted
11010 with VALUE also zero and is used to invalidate the register. */
11013 record_value_for_reg (reg, insn, value)
11018 unsigned int regno = REGNO (reg);
11019 unsigned int endregno
11020 = regno + (regno < FIRST_PSEUDO_REGISTER
11021 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11024 /* If VALUE contains REG and we have a previous value for REG, substitute
11025 the previous value. */
11026 if (value && insn && reg_overlap_mentioned_p (reg, value))
11030 /* Set things up so get_last_value is allowed to see anything set up to
11032 subst_low_cuid = INSN_CUID (insn);
11033 tem = get_last_value (reg);
11035 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11036 it isn't going to be useful and will take a lot of time to process,
11037 so just use the CLOBBER. */
11041 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11042 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11043 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11044 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11045 tem = XEXP (tem, 0);
11047 value = replace_rtx (copy_rtx (value), reg, tem);
11051 /* For each register modified, show we don't know its value, that
11052 we don't know about its bitwise content, that its value has been
11053 updated, and that we don't know the location of the death of the
11055 for (i = regno; i < endregno; i++)
11058 reg_last_set[i] = insn;
11060 reg_last_set_value[i] = 0;
11061 reg_last_set_mode[i] = 0;
11062 reg_last_set_nonzero_bits[i] = 0;
11063 reg_last_set_sign_bit_copies[i] = 0;
11064 reg_last_death[i] = 0;
11067 /* Mark registers that are being referenced in this value. */
11069 update_table_tick (value);
11071 /* Now update the status of each register being set.
11072 If someone is using this register in this block, set this register
11073 to invalid since we will get confused between the two lives in this
11074 basic block. This makes using this register always invalid. In cse, we
11075 scan the table to invalidate all entries using this register, but this
11076 is too much work for us. */
11078 for (i = regno; i < endregno; i++)
11080 reg_last_set_label[i] = label_tick;
11081 if (value && reg_last_set_table_tick[i] == label_tick)
11082 reg_last_set_invalid[i] = 1;
11084 reg_last_set_invalid[i] = 0;
11087 /* The value being assigned might refer to X (like in "x++;"). In that
11088 case, we must replace it with (clobber (const_int 0)) to prevent
11090 if (value && ! get_last_value_validate (&value, insn,
11091 reg_last_set_label[regno], 0))
11093 value = copy_rtx (value);
11094 if (! get_last_value_validate (&value, insn,
11095 reg_last_set_label[regno], 1))
11099 /* For the main register being modified, update the value, the mode, the
11100 nonzero bits, and the number of sign bit copies. */
11102 reg_last_set_value[regno] = value;
11106 subst_low_cuid = INSN_CUID (insn);
11107 reg_last_set_mode[regno] = GET_MODE (reg);
11108 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11109 reg_last_set_sign_bit_copies[regno]
11110 = num_sign_bit_copies (value, GET_MODE (reg));
11114 /* Called via note_stores from record_dead_and_set_regs to handle one
11115 SET or CLOBBER in an insn. DATA is the instruction in which the
11116 set is occurring. */
11119 record_dead_and_set_regs_1 (dest, setter, data)
11123 rtx record_dead_insn = (rtx) data;
11125 if (GET_CODE (dest) == SUBREG)
11126 dest = SUBREG_REG (dest);
11128 if (GET_CODE (dest) == REG)
11130 /* If we are setting the whole register, we know its value. Otherwise
11131 show that we don't know the value. We can handle SUBREG in
11133 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11134 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11135 else if (GET_CODE (setter) == SET
11136 && GET_CODE (SET_DEST (setter)) == SUBREG
11137 && SUBREG_REG (SET_DEST (setter)) == dest
11138 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11139 && subreg_lowpart_p (SET_DEST (setter)))
11140 record_value_for_reg (dest, record_dead_insn,
11141 gen_lowpart_for_combine (GET_MODE (dest),
11142 SET_SRC (setter)));
11144 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11146 else if (GET_CODE (dest) == MEM
11147 /* Ignore pushes, they clobber nothing. */
11148 && ! push_operand (dest, GET_MODE (dest)))
11149 mem_last_set = INSN_CUID (record_dead_insn);
11152 /* Update the records of when each REG was most recently set or killed
11153 for the things done by INSN. This is the last thing done in processing
11154 INSN in the combiner loop.
11156 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11157 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11158 and also the similar information mem_last_set (which insn most recently
11159 modified memory) and last_call_cuid (which insn was the most recent
11160 subroutine call). */
11163 record_dead_and_set_regs (insn)
11169 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11171 if (REG_NOTE_KIND (link) == REG_DEAD
11172 && GET_CODE (XEXP (link, 0)) == REG)
11174 unsigned int regno = REGNO (XEXP (link, 0));
11175 unsigned int endregno
11176 = regno + (regno < FIRST_PSEUDO_REGISTER
11177 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11180 for (i = regno; i < endregno; i++)
11181 reg_last_death[i] = insn;
11183 else if (REG_NOTE_KIND (link) == REG_INC)
11184 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11187 if (GET_CODE (insn) == CALL_INSN)
11189 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11190 if (call_used_regs[i])
11192 reg_last_set_value[i] = 0;
11193 reg_last_set_mode[i] = 0;
11194 reg_last_set_nonzero_bits[i] = 0;
11195 reg_last_set_sign_bit_copies[i] = 0;
11196 reg_last_death[i] = 0;
11199 last_call_cuid = mem_last_set = INSN_CUID (insn);
11202 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11205 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11206 register present in the SUBREG, so for each such SUBREG go back and
11207 adjust nonzero and sign bit information of the registers that are
11208 known to have some zero/sign bits set.
11210 This is needed because when combine blows the SUBREGs away, the
11211 information on zero/sign bits is lost and further combines can be
11212 missed because of that. */
11215 record_promoted_value (insn, subreg)
11220 unsigned int regno = REGNO (SUBREG_REG (subreg));
11221 enum machine_mode mode = GET_MODE (subreg);
11223 if (GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT)
11226 for (links = LOG_LINKS (insn); links; )
11228 insn = XEXP (links, 0);
11229 set = single_set (insn);
11231 if (! set || GET_CODE (SET_DEST (set)) != REG
11232 || REGNO (SET_DEST (set)) != regno
11233 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11235 links = XEXP (links, 1);
11239 if (reg_last_set [regno] == insn)
11241 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11242 reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11245 if (GET_CODE (SET_SRC (set)) == REG)
11247 regno = REGNO (SET_SRC (set));
11248 links = LOG_LINKS (insn);
11255 /* Scan X for promoted SUBREGs. For each one found,
11256 note what it implies to the registers used in it. */
11259 check_promoted_subreg (insn, x)
11263 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11264 && GET_CODE (SUBREG_REG (x)) == REG)
11265 record_promoted_value (insn, x);
11268 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11271 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11272 switch (format [i])
11275 check_promoted_subreg (insn, XEXP (x, i));
11279 if (XVEC (x, i) != 0)
11280 for (j = 0; j < XVECLEN (x, i); j++)
11281 check_promoted_subreg (insn, XVECEXP (x, i, j));
11287 /* Utility routine for the following function. Verify that all the registers
11288 mentioned in *LOC are valid when *LOC was part of a value set when
11289 label_tick == TICK. Return 0 if some are not.
11291 If REPLACE is non-zero, replace the invalid reference with
11292 (clobber (const_int 0)) and return 1. This replacement is useful because
11293 we often can get useful information about the form of a value (e.g., if
11294 it was produced by a shift that always produces -1 or 0) even though
11295 we don't know exactly what registers it was produced from. */
11298 get_last_value_validate (loc, insn, tick, replace)
11305 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11306 int len = GET_RTX_LENGTH (GET_CODE (x));
11309 if (GET_CODE (x) == REG)
11311 unsigned int regno = REGNO (x);
11312 unsigned int endregno
11313 = regno + (regno < FIRST_PSEUDO_REGISTER
11314 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11317 for (j = regno; j < endregno; j++)
11318 if (reg_last_set_invalid[j]
11319 /* If this is a pseudo-register that was only set once and not
11320 live at the beginning of the function, it is always valid. */
11321 || (! (regno >= FIRST_PSEUDO_REGISTER
11322 && REG_N_SETS (regno) == 1
11323 && (! REGNO_REG_SET_P
11324 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11325 && reg_last_set_label[j] > tick))
11328 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11334 /* If this is a memory reference, make sure that there were
11335 no stores after it that might have clobbered the value. We don't
11336 have alias info, so we assume any store invalidates it. */
11337 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11338 && INSN_CUID (insn) <= mem_last_set)
11341 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11345 for (i = 0; i < len; i++)
11347 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11348 /* Don't bother with these. They shouldn't occur anyway. */
11352 /* If we haven't found a reason for it to be invalid, it is valid. */
11356 /* Get the last value assigned to X, if known. Some registers
11357 in the value may be replaced with (clobber (const_int 0)) if their value
11358 is known longer known reliably. */
11364 unsigned int regno;
11367 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11368 then convert it to the desired mode. If this is a paradoxical SUBREG,
11369 we cannot predict what values the "extra" bits might have. */
11370 if (GET_CODE (x) == SUBREG
11371 && subreg_lowpart_p (x)
11372 && (GET_MODE_SIZE (GET_MODE (x))
11373 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11374 && (value = get_last_value (SUBREG_REG (x))) != 0)
11375 return gen_lowpart_for_combine (GET_MODE (x), value);
11377 if (GET_CODE (x) != REG)
11381 value = reg_last_set_value[regno];
11383 /* If we don't have a value, or if it isn't for this basic block and
11384 it's either a hard register, set more than once, or it's a live
11385 at the beginning of the function, return 0.
11387 Because if it's not live at the beginnning of the function then the reg
11388 is always set before being used (is never used without being set).
11389 And, if it's set only once, and it's always set before use, then all
11390 uses must have the same last value, even if it's not from this basic
11394 || (reg_last_set_label[regno] != label_tick
11395 && (regno < FIRST_PSEUDO_REGISTER
11396 || REG_N_SETS (regno) != 1
11397 || (REGNO_REG_SET_P
11398 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11401 /* If the value was set in a later insn than the ones we are processing,
11402 we can't use it even if the register was only set once. */
11403 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11406 /* If the value has all its registers valid, return it. */
11407 if (get_last_value_validate (&value, reg_last_set[regno],
11408 reg_last_set_label[regno], 0))
11411 /* Otherwise, make a copy and replace any invalid register with
11412 (clobber (const_int 0)). If that fails for some reason, return 0. */
11414 value = copy_rtx (value);
11415 if (get_last_value_validate (&value, reg_last_set[regno],
11416 reg_last_set_label[regno], 1))
11422 /* Return nonzero if expression X refers to a REG or to memory
11423 that is set in an instruction more recent than FROM_CUID. */
11426 use_crosses_set_p (x, from_cuid)
11430 register const char *fmt;
11432 register enum rtx_code code = GET_CODE (x);
11436 unsigned int regno = REGNO (x);
11437 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11438 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11440 #ifdef PUSH_ROUNDING
11441 /* Don't allow uses of the stack pointer to be moved,
11442 because we don't know whether the move crosses a push insn. */
11443 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11446 for (; regno < endreg; regno++)
11447 if (reg_last_set[regno]
11448 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11453 if (code == MEM && mem_last_set > from_cuid)
11456 fmt = GET_RTX_FORMAT (code);
11458 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11463 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11464 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11467 else if (fmt[i] == 'e'
11468 && use_crosses_set_p (XEXP (x, i), from_cuid))
11474 /* Define three variables used for communication between the following
11477 static unsigned int reg_dead_regno, reg_dead_endregno;
11478 static int reg_dead_flag;
11480 /* Function called via note_stores from reg_dead_at_p.
11482 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11483 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11486 reg_dead_at_p_1 (dest, x, data)
11489 void *data ATTRIBUTE_UNUSED;
11491 unsigned int regno, endregno;
11493 if (GET_CODE (dest) != REG)
11496 regno = REGNO (dest);
11497 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11498 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11500 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11501 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11504 /* Return non-zero if REG is known to be dead at INSN.
11506 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11507 referencing REG, it is dead. If we hit a SET referencing REG, it is
11508 live. Otherwise, see if it is live or dead at the start of the basic
11509 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11510 must be assumed to be always live. */
11513 reg_dead_at_p (reg, insn)
11520 /* Set variables for reg_dead_at_p_1. */
11521 reg_dead_regno = REGNO (reg);
11522 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11523 ? HARD_REGNO_NREGS (reg_dead_regno,
11529 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11530 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11532 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11533 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11537 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11538 beginning of function. */
11539 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11540 insn = prev_nonnote_insn (insn))
11542 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11544 return reg_dead_flag == 1 ? 1 : 0;
11546 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11550 /* Get the basic block number that we were in. */
11555 for (block = 0; block < n_basic_blocks; block++)
11556 if (insn == BLOCK_HEAD (block))
11559 if (block == n_basic_blocks)
11563 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11564 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11570 /* Note hard registers in X that are used. This code is similar to
11571 that in flow.c, but much simpler since we don't care about pseudos. */
11574 mark_used_regs_combine (x)
11577 RTX_CODE code = GET_CODE (x);
11578 unsigned int regno;
11590 case ADDR_DIFF_VEC:
11593 /* CC0 must die in the insn after it is set, so we don't need to take
11594 special note of it here. */
11600 /* If we are clobbering a MEM, mark any hard registers inside the
11601 address as used. */
11602 if (GET_CODE (XEXP (x, 0)) == MEM)
11603 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11608 /* A hard reg in a wide mode may really be multiple registers.
11609 If so, mark all of them just like the first. */
11610 if (regno < FIRST_PSEUDO_REGISTER)
11612 unsigned int endregno, r;
11614 /* None of this applies to the stack, frame or arg pointers */
11615 if (regno == STACK_POINTER_REGNUM
11616 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11617 || regno == HARD_FRAME_POINTER_REGNUM
11619 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11620 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11622 || regno == FRAME_POINTER_REGNUM)
11625 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11626 for (r = regno; r < endregno; r++)
11627 SET_HARD_REG_BIT (newpat_used_regs, r);
11633 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11635 register rtx testreg = SET_DEST (x);
11637 while (GET_CODE (testreg) == SUBREG
11638 || GET_CODE (testreg) == ZERO_EXTRACT
11639 || GET_CODE (testreg) == SIGN_EXTRACT
11640 || GET_CODE (testreg) == STRICT_LOW_PART)
11641 testreg = XEXP (testreg, 0);
11643 if (GET_CODE (testreg) == MEM)
11644 mark_used_regs_combine (XEXP (testreg, 0));
11646 mark_used_regs_combine (SET_SRC (x));
11654 /* Recursively scan the operands of this expression. */
11657 register const char *fmt = GET_RTX_FORMAT (code);
11659 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11662 mark_used_regs_combine (XEXP (x, i));
11663 else if (fmt[i] == 'E')
11667 for (j = 0; j < XVECLEN (x, i); j++)
11668 mark_used_regs_combine (XVECEXP (x, i, j));
11675 /* Remove register number REGNO from the dead registers list of INSN.
11677 Return the note used to record the death, if there was one. */
11680 remove_death (regno, insn)
11681 unsigned int regno;
11684 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11688 REG_N_DEATHS (regno)--;
11689 remove_note (insn, note);
11695 /* For each register (hardware or pseudo) used within expression X, if its
11696 death is in an instruction with cuid between FROM_CUID (inclusive) and
11697 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11698 list headed by PNOTES.
11700 That said, don't move registers killed by maybe_kill_insn.
11702 This is done when X is being merged by combination into TO_INSN. These
11703 notes will then be distributed as needed. */
11706 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11708 rtx maybe_kill_insn;
11713 register const char *fmt;
11714 register int len, i;
11715 register enum rtx_code code = GET_CODE (x);
11719 unsigned int regno = REGNO (x);
11720 register rtx where_dead = reg_last_death[regno];
11721 register rtx before_dead, after_dead;
11723 /* Don't move the register if it gets killed in between from and to */
11724 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11725 && ! reg_referenced_p (x, maybe_kill_insn))
11728 /* WHERE_DEAD could be a USE insn made by combine, so first we
11729 make sure that we have insns with valid INSN_CUID values. */
11730 before_dead = where_dead;
11731 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11732 before_dead = PREV_INSN (before_dead);
11734 after_dead = where_dead;
11735 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11736 after_dead = NEXT_INSN (after_dead);
11738 if (before_dead && after_dead
11739 && INSN_CUID (before_dead) >= from_cuid
11740 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11741 || (where_dead != after_dead
11742 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11744 rtx note = remove_death (regno, where_dead);
11746 /* It is possible for the call above to return 0. This can occur
11747 when reg_last_death points to I2 or I1 that we combined with.
11748 In that case make a new note.
11750 We must also check for the case where X is a hard register
11751 and NOTE is a death note for a range of hard registers
11752 including X. In that case, we must put REG_DEAD notes for
11753 the remaining registers in place of NOTE. */
11755 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11756 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11757 > GET_MODE_SIZE (GET_MODE (x))))
11759 unsigned int deadregno = REGNO (XEXP (note, 0));
11760 unsigned int deadend
11761 = (deadregno + HARD_REGNO_NREGS (deadregno,
11762 GET_MODE (XEXP (note, 0))));
11763 unsigned int ourend
11764 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11767 for (i = deadregno; i < deadend; i++)
11768 if (i < regno || i >= ourend)
11769 REG_NOTES (where_dead)
11770 = gen_rtx_EXPR_LIST (REG_DEAD,
11771 gen_rtx_REG (reg_raw_mode[i], i),
11772 REG_NOTES (where_dead));
11775 /* If we didn't find any note, or if we found a REG_DEAD note that
11776 covers only part of the given reg, and we have a multi-reg hard
11777 register, then to be safe we must check for REG_DEAD notes
11778 for each register other than the first. They could have
11779 their own REG_DEAD notes lying around. */
11780 else if ((note == 0
11782 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11783 < GET_MODE_SIZE (GET_MODE (x)))))
11784 && regno < FIRST_PSEUDO_REGISTER
11785 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11787 unsigned int ourend
11788 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11789 unsigned int i, offset;
11793 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11797 for (i = regno + offset; i < ourend; i++)
11798 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11799 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11802 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11804 XEXP (note, 1) = *pnotes;
11808 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11810 REG_N_DEATHS (regno)++;
11816 else if (GET_CODE (x) == SET)
11818 rtx dest = SET_DEST (x);
11820 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11822 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11823 that accesses one word of a multi-word item, some
11824 piece of everything register in the expression is used by
11825 this insn, so remove any old death. */
11827 if (GET_CODE (dest) == ZERO_EXTRACT
11828 || GET_CODE (dest) == STRICT_LOW_PART
11829 || (GET_CODE (dest) == SUBREG
11830 && (((GET_MODE_SIZE (GET_MODE (dest))
11831 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11832 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11833 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11835 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11839 /* If this is some other SUBREG, we know it replaces the entire
11840 value, so use that as the destination. */
11841 if (GET_CODE (dest) == SUBREG)
11842 dest = SUBREG_REG (dest);
11844 /* If this is a MEM, adjust deaths of anything used in the address.
11845 For a REG (the only other possibility), the entire value is
11846 being replaced so the old value is not used in this insn. */
11848 if (GET_CODE (dest) == MEM)
11849 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11854 else if (GET_CODE (x) == CLOBBER)
11857 len = GET_RTX_LENGTH (code);
11858 fmt = GET_RTX_FORMAT (code);
11860 for (i = 0; i < len; i++)
11865 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11866 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11869 else if (fmt[i] == 'e')
11870 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11874 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11875 pattern of an insn. X must be a REG. */
11878 reg_bitfield_target_p (x, body)
11884 if (GET_CODE (body) == SET)
11886 rtx dest = SET_DEST (body);
11888 unsigned int regno, tregno, endregno, endtregno;
11890 if (GET_CODE (dest) == ZERO_EXTRACT)
11891 target = XEXP (dest, 0);
11892 else if (GET_CODE (dest) == STRICT_LOW_PART)
11893 target = SUBREG_REG (XEXP (dest, 0));
11897 if (GET_CODE (target) == SUBREG)
11898 target = SUBREG_REG (target);
11900 if (GET_CODE (target) != REG)
11903 tregno = REGNO (target), regno = REGNO (x);
11904 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11905 return target == x;
11907 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11908 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11910 return endregno > tregno && regno < endtregno;
11913 else if (GET_CODE (body) == PARALLEL)
11914 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11915 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11921 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11922 as appropriate. I3 and I2 are the insns resulting from the combination
11923 insns including FROM (I2 may be zero).
11925 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11926 not need REG_DEAD notes because they are being substituted for. This
11927 saves searching in the most common cases.
11929 Each note in the list is either ignored or placed on some insns, depending
11930 on the type of note. */
11933 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11937 rtx elim_i2, elim_i1;
11939 rtx note, next_note;
11942 for (note = notes; note; note = next_note)
11944 rtx place = 0, place2 = 0;
11946 /* If this NOTE references a pseudo register, ensure it references
11947 the latest copy of that register. */
11948 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11949 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11950 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11952 next_note = XEXP (note, 1);
11953 switch (REG_NOTE_KIND (note))
11956 case REG_EXEC_COUNT:
11957 /* Doesn't matter much where we put this, as long as it's somewhere.
11958 It is preferable to keep these notes on branches, which is most
11959 likely to be i3. */
11963 case REG_EH_REGION:
11964 case REG_EH_RETHROW:
11965 /* These notes must remain with the call. It should not be
11966 possible for both I2 and I3 to be a call. */
11967 if (GET_CODE (i3) == CALL_INSN)
11969 else if (i2 && GET_CODE (i2) == CALL_INSN)
11976 /* Any clobbers for i3 may still exist, and so we must process
11977 REG_UNUSED notes from that insn.
11979 Any clobbers from i2 or i1 can only exist if they were added by
11980 recog_for_combine. In that case, recog_for_combine created the
11981 necessary REG_UNUSED notes. Trying to keep any original
11982 REG_UNUSED notes from these insns can cause incorrect output
11983 if it is for the same register as the original i3 dest.
11984 In that case, we will notice that the register is set in i3,
11985 and then add a REG_UNUSED note for the destination of i3, which
11986 is wrong. However, it is possible to have REG_UNUSED notes from
11987 i2 or i1 for register which were both used and clobbered, so
11988 we keep notes from i2 or i1 if they will turn into REG_DEAD
11991 /* If this register is set or clobbered in I3, put the note there
11992 unless there is one already. */
11993 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11995 if (from_insn != i3)
11998 if (! (GET_CODE (XEXP (note, 0)) == REG
11999 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12000 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12003 /* Otherwise, if this register is used by I3, then this register
12004 now dies here, so we must put a REG_DEAD note here unless there
12006 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12007 && ! (GET_CODE (XEXP (note, 0)) == REG
12008 ? find_regno_note (i3, REG_DEAD,
12009 REGNO (XEXP (note, 0)))
12010 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12012 PUT_REG_NOTE_KIND (note, REG_DEAD);
12021 /* These notes say something about results of an insn. We can
12022 only support them if they used to be on I3 in which case they
12023 remain on I3. Otherwise they are ignored.
12025 If the note refers to an expression that is not a constant, we
12026 must also ignore the note since we cannot tell whether the
12027 equivalence is still true. It might be possible to do
12028 slightly better than this (we only have a problem if I2DEST
12029 or I1DEST is present in the expression), but it doesn't
12030 seem worth the trouble. */
12032 if (from_insn == i3
12033 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12038 case REG_NO_CONFLICT:
12039 /* These notes say something about how a register is used. They must
12040 be present on any use of the register in I2 or I3. */
12041 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12044 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12054 /* This can show up in several ways -- either directly in the
12055 pattern, or hidden off in the constant pool with (or without?)
12056 a REG_EQUAL note. */
12057 /* ??? Ignore the without-reg_equal-note problem for now. */
12058 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12059 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12060 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12061 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12065 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12066 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12067 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12068 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12078 /* It is too much trouble to try to see if this note is still
12079 correct in all situations. It is better to simply delete it. */
12083 /* If the insn previously containing this note still exists,
12084 put it back where it was. Otherwise move it to the previous
12085 insn. Adjust the corresponding REG_LIBCALL note. */
12086 if (GET_CODE (from_insn) != NOTE)
12090 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12091 place = prev_real_insn (from_insn);
12093 XEXP (tem, 0) = place;
12098 /* This is handled similarly to REG_RETVAL. */
12099 if (GET_CODE (from_insn) != NOTE)
12103 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12104 place = next_real_insn (from_insn);
12106 XEXP (tem, 0) = place;
12111 /* If the register is used as an input in I3, it dies there.
12112 Similarly for I2, if it is non-zero and adjacent to I3.
12114 If the register is not used as an input in either I3 or I2
12115 and it is not one of the registers we were supposed to eliminate,
12116 there are two possibilities. We might have a non-adjacent I2
12117 or we might have somehow eliminated an additional register
12118 from a computation. For example, we might have had A & B where
12119 we discover that B will always be zero. In this case we will
12120 eliminate the reference to A.
12122 In both cases, we must search to see if we can find a previous
12123 use of A and put the death note there. */
12126 && GET_CODE (from_insn) == CALL_INSN
12127 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12129 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12131 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12132 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12135 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12140 basic_block bb = BASIC_BLOCK (this_basic_block);
12142 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12144 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12146 if (tem == bb->head)
12151 /* If the register is being set at TEM, see if that is all
12152 TEM is doing. If so, delete TEM. Otherwise, make this
12153 into a REG_UNUSED note instead. */
12154 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12156 rtx set = single_set (tem);
12157 rtx inner_dest = 0;
12159 rtx cc0_setter = NULL_RTX;
12163 for (inner_dest = SET_DEST (set);
12164 GET_CODE (inner_dest) == STRICT_LOW_PART
12165 || GET_CODE (inner_dest) == SUBREG
12166 || GET_CODE (inner_dest) == ZERO_EXTRACT;
12167 inner_dest = XEXP (inner_dest, 0))
12170 /* Verify that it was the set, and not a clobber that
12171 modified the register.
12173 CC0 targets must be careful to maintain setter/user
12174 pairs. If we cannot delete the setter due to side
12175 effects, mark the user with an UNUSED note instead
12178 if (set != 0 && ! side_effects_p (SET_SRC (set))
12179 && rtx_equal_p (XEXP (note, 0), inner_dest)
12181 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12182 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12183 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12187 /* Move the notes and links of TEM elsewhere.
12188 This might delete other dead insns recursively.
12189 First set the pattern to something that won't use
12192 PATTERN (tem) = pc_rtx;
12194 distribute_notes (REG_NOTES (tem), tem, tem,
12195 NULL_RTX, NULL_RTX, NULL_RTX);
12196 distribute_links (LOG_LINKS (tem));
12198 PUT_CODE (tem, NOTE);
12199 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12200 NOTE_SOURCE_FILE (tem) = 0;
12203 /* Delete the setter too. */
12206 PATTERN (cc0_setter) = pc_rtx;
12208 distribute_notes (REG_NOTES (cc0_setter),
12209 cc0_setter, cc0_setter,
12210 NULL_RTX, NULL_RTX, NULL_RTX);
12211 distribute_links (LOG_LINKS (cc0_setter));
12213 PUT_CODE (cc0_setter, NOTE);
12214 NOTE_LINE_NUMBER (cc0_setter)
12215 = NOTE_INSN_DELETED;
12216 NOTE_SOURCE_FILE (cc0_setter) = 0;
12220 /* If the register is both set and used here, put the
12221 REG_DEAD note here, but place a REG_UNUSED note
12222 here too unless there already is one. */
12223 else if (reg_referenced_p (XEXP (note, 0),
12228 if (! find_regno_note (tem, REG_UNUSED,
12229 REGNO (XEXP (note, 0))))
12231 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12236 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12238 /* If there isn't already a REG_UNUSED note, put one
12240 if (! find_regno_note (tem, REG_UNUSED,
12241 REGNO (XEXP (note, 0))))
12246 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12247 || (GET_CODE (tem) == CALL_INSN
12248 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12252 /* If we are doing a 3->2 combination, and we have a
12253 register which formerly died in i3 and was not used
12254 by i2, which now no longer dies in i3 and is used in
12255 i2 but does not die in i2, and place is between i2
12256 and i3, then we may need to move a link from place to
12258 if (i2 && INSN_UID (place) <= max_uid_cuid
12259 && INSN_CUID (place) > INSN_CUID (i2)
12260 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12261 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12263 rtx links = LOG_LINKS (place);
12264 LOG_LINKS (place) = 0;
12265 distribute_links (links);
12270 if (tem == bb->head)
12274 /* We haven't found an insn for the death note and it
12275 is still a REG_DEAD note, but we have hit the beginning
12276 of the block. If the existing life info says the reg
12277 was dead, there's nothing left to do. Otherwise, we'll
12278 need to do a global life update after combine. */
12279 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12280 && REGNO_REG_SET_P (bb->global_live_at_start,
12281 REGNO (XEXP (note, 0))))
12283 SET_BIT (refresh_blocks, this_basic_block);
12288 /* If the register is set or already dead at PLACE, we needn't do
12289 anything with this note if it is still a REG_DEAD note.
12290 We can here if it is set at all, not if is it totally replace,
12291 which is what `dead_or_set_p' checks, so also check for it being
12294 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12296 unsigned int regno = REGNO (XEXP (note, 0));
12298 if (dead_or_set_p (place, XEXP (note, 0))
12299 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12301 /* Unless the register previously died in PLACE, clear
12302 reg_last_death. [I no longer understand why this is
12304 if (reg_last_death[regno] != place)
12305 reg_last_death[regno] = 0;
12309 reg_last_death[regno] = place;
12311 /* If this is a death note for a hard reg that is occupying
12312 multiple registers, ensure that we are still using all
12313 parts of the object. If we find a piece of the object
12314 that is unused, we must add a USE for that piece before
12315 PLACE and put the appropriate REG_DEAD note on it.
12317 An alternative would be to put a REG_UNUSED for the pieces
12318 on the insn that set the register, but that can't be done if
12319 it is not in the same block. It is simpler, though less
12320 efficient, to add the USE insns. */
12322 if (place && regno < FIRST_PSEUDO_REGISTER
12323 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12325 unsigned int endregno
12326 = regno + HARD_REGNO_NREGS (regno,
12327 GET_MODE (XEXP (note, 0)));
12331 for (i = regno; i < endregno; i++)
12332 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12333 && ! find_regno_fusage (place, USE, i))
12335 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12338 /* See if we already placed a USE note for this
12339 register in front of PLACE. */
12341 GET_CODE (PREV_INSN (p)) == INSN
12342 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12344 if (rtx_equal_p (piece,
12345 XEXP (PATTERN (PREV_INSN (p)), 0)))
12354 = emit_insn_before (gen_rtx_USE (VOIDmode,
12357 REG_NOTES (use_insn)
12358 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12359 REG_NOTES (use_insn));
12365 /* Check for the case where the register dying partially
12366 overlaps the register set by this insn. */
12368 for (i = regno; i < endregno; i++)
12369 if (dead_or_set_regno_p (place, i))
12377 /* Put only REG_DEAD notes for pieces that are
12378 still used and that are not already dead or set. */
12380 for (i = regno; i < endregno; i++)
12382 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12384 if ((reg_referenced_p (piece, PATTERN (place))
12385 || (GET_CODE (place) == CALL_INSN
12386 && find_reg_fusage (place, USE, piece)))
12387 && ! dead_or_set_p (place, piece)
12388 && ! reg_bitfield_target_p (piece,
12391 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12392 REG_NOTES (place));
12402 /* Any other notes should not be present at this point in the
12409 XEXP (note, 1) = REG_NOTES (place);
12410 REG_NOTES (place) = note;
12412 else if ((REG_NOTE_KIND (note) == REG_DEAD
12413 || REG_NOTE_KIND (note) == REG_UNUSED)
12414 && GET_CODE (XEXP (note, 0)) == REG)
12415 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12419 if ((REG_NOTE_KIND (note) == REG_DEAD
12420 || REG_NOTE_KIND (note) == REG_UNUSED)
12421 && GET_CODE (XEXP (note, 0)) == REG)
12422 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12424 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12425 REG_NOTE_KIND (note),
12427 REG_NOTES (place2));
12432 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12433 I3, I2, and I1 to new locations. This is also called in one case to
12434 add a link pointing at I3 when I3's destination is changed. */
12437 distribute_links (links)
12440 rtx link, next_link;
12442 for (link = links; link; link = next_link)
12448 next_link = XEXP (link, 1);
12450 /* If the insn that this link points to is a NOTE or isn't a single
12451 set, ignore it. In the latter case, it isn't clear what we
12452 can do other than ignore the link, since we can't tell which
12453 register it was for. Such links wouldn't be used by combine
12456 It is not possible for the destination of the target of the link to
12457 have been changed by combine. The only potential of this is if we
12458 replace I3, I2, and I1 by I3 and I2. But in that case the
12459 destination of I2 also remains unchanged. */
12461 if (GET_CODE (XEXP (link, 0)) == NOTE
12462 || (set = single_set (XEXP (link, 0))) == 0)
12465 reg = SET_DEST (set);
12466 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12467 || GET_CODE (reg) == SIGN_EXTRACT
12468 || GET_CODE (reg) == STRICT_LOW_PART)
12469 reg = XEXP (reg, 0);
12471 /* A LOG_LINK is defined as being placed on the first insn that uses
12472 a register and points to the insn that sets the register. Start
12473 searching at the next insn after the target of the link and stop
12474 when we reach a set of the register or the end of the basic block.
12476 Note that this correctly handles the link that used to point from
12477 I3 to I2. Also note that not much searching is typically done here
12478 since most links don't point very far away. */
12480 for (insn = NEXT_INSN (XEXP (link, 0));
12481 (insn && (this_basic_block == n_basic_blocks - 1
12482 || BLOCK_HEAD (this_basic_block + 1) != insn));
12483 insn = NEXT_INSN (insn))
12484 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12485 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12487 if (reg_referenced_p (reg, PATTERN (insn)))
12491 else if (GET_CODE (insn) == CALL_INSN
12492 && find_reg_fusage (insn, USE, reg))
12498 /* If we found a place to put the link, place it there unless there
12499 is already a link to the same insn as LINK at that point. */
12505 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12506 if (XEXP (link2, 0) == XEXP (link, 0))
12511 XEXP (link, 1) = LOG_LINKS (place);
12512 LOG_LINKS (place) = link;
12514 /* Set added_links_insn to the earliest insn we added a
12516 if (added_links_insn == 0
12517 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12518 added_links_insn = place;
12524 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12530 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12531 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12532 insn = NEXT_INSN (insn);
12534 if (INSN_UID (insn) > max_uid_cuid)
12537 return INSN_CUID (insn);
12541 dump_combine_stats (file)
12546 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12547 combine_attempts, combine_merges, combine_extras, combine_successes);
12551 dump_combine_total_stats (file)
12556 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12557 total_attempts, total_merges, total_extras, total_successes);