1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx, bool);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
778 rtx newi2pat, rtx newotherpat)
780 int i0_cost, i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
793 i0_cost = INSN_COST (i0);
794 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
795 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
799 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
800 ? i1_cost + i2_cost + i3_cost : 0);
806 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
807 i1_cost = i0_cost = 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
814 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
815 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
816 ? new_i2_cost + new_i3_cost : 0;
820 new_cost = new_i3_cost;
824 if (undobuf.other_insn)
826 int old_other_cost, new_other_cost;
828 old_other_cost = INSN_COST (undobuf.other_insn);
829 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
830 if (old_other_cost > 0 && new_other_cost > 0)
832 old_cost += old_other_cost;
833 new_cost += new_other_cost;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost > old_cost)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
852 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
860 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
861 i1_cost, i2_cost, i3_cost, old_cost);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2), INSN_UID (i3));
868 fprintf (dump_file, "original costs %d + %d = %d\n",
869 i2_cost, i3_cost, old_cost);
874 fprintf (dump_file, "replacement costs %d + %d = %d\n",
875 new_i2_cost, new_i3_cost, new_cost);
878 fprintf (dump_file, "replacement cost %d\n", new_cost);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2) = new_i2_cost;
886 INSN_COST (i3) = new_i3_cost;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
906 next = NEXT_INSN (insn);
907 if (INSN_P (insn) && noop_move_p (insn))
910 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
912 delete_insn_and_edges (insn);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref *def_vec, *use_vec;
928 next_use = XCNEWVEC (rtx, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb, insn)
943 if (!NONDEBUG_INSN_P (insn))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn));
949 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
951 df_ref def = *def_vec;
952 int regno = DF_REF_REGNO (def);
955 if (!next_use[regno])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
962 /* Do not make the log link for frame pointer. */
963 if ((regno == FRAME_POINTER_REGNUM
964 && (! reload_completed || frame_pointer_needed))
965 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
966 || (regno == HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed || frame_pointer_needed))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
975 use_insn = next_use[regno];
976 if (BLOCK_FOR_INSN (use_insn) == bb)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno >= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links = LOG_LINKS (use_insn); links;
991 links = XEXP (links, 1))
992 if (insn == XEXP (links, 0))
996 LOG_LINKS (use_insn) =
997 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
1000 next_use[regno] = NULL_RTX;
1003 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1005 df_ref use = *use_vec;
1006 int regno = DF_REF_REGNO (use);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1013 next_use[regno] = insn;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1030 free_INSN_LIST_list (&LOG_LINKS (insn));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a, rtx b)
1042 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1043 if (XEXP (links, 0) == a)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f, unsigned int nregs)
1060 rtx links, nextlinks;
1062 basic_block last_bb;
1064 int new_direct_jump_p = 0;
1066 for (first = f; first && !INSN_P (first); )
1067 first = NEXT_INSN (first);
1071 combine_attempts = 0;
1074 combine_successes = 0;
1076 rtl_hooks = combine_rtl_hooks;
1078 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known = get_max_uid ();
1084 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1085 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1087 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid = 0;
1093 label_tick = label_tick_ebb_start = 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb = ENTRY_BLOCK_PTR;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block)
1110 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1115 if (!single_pred_p (this_basic_block)
1116 || single_pred (this_basic_block) != last_bb)
1117 label_tick_ebb_start = label_tick;
1118 last_bb = this_basic_block;
1120 FOR_BB_INSNS (this_basic_block, insn)
1121 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1123 subst_low_luid = DF_INSN_LUID (insn);
1126 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1128 record_dead_and_set_regs (insn);
1131 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1132 if (REG_NOTE_KIND (links) == REG_INC)
1133 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn))
1139 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1140 optimize_this_for_speed_p);
1142 fprintf(dump_file, "insn_cost %d: %d\n",
1143 INSN_UID (insn), INSN_COST (insn));
1147 nonzero_sign_valid = 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick = label_tick_ebb_start = 1;
1152 setup_incoming_promotions (first);
1153 last_bb = ENTRY_BLOCK_PTR;
1155 FOR_EACH_BB (this_basic_block)
1157 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1162 if (!single_pred_p (this_basic_block)
1163 || single_pred (this_basic_block) != last_bb)
1164 label_tick_ebb_start = label_tick;
1165 last_bb = this_basic_block;
1167 rtl_profile_for_bb (this_basic_block);
1168 for (insn = BB_HEAD (this_basic_block);
1169 insn != NEXT_INSN (BB_END (this_basic_block));
1170 insn = next ? next : NEXT_INSN (insn))
1173 if (NONDEBUG_INSN_P (insn))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn, PATTERN (insn));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1184 /* Try this insn with each insn it links back to. */
1186 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1187 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1188 NULL_RTX, &new_direct_jump_p)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1195 rtx link = XEXP (links, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks = LOG_LINKS (link);
1204 nextlinks = XEXP (nextlinks, 1))
1205 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1207 &new_direct_jump_p)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev = prev_nonnote_insn (insn)) != 0
1221 && NONJUMP_INSN_P (prev)
1222 && sets_cc0_p (PATTERN (prev)))
1224 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1225 &new_direct_jump_p)) != 0)
1228 for (nextlinks = LOG_LINKS (prev); nextlinks;
1229 nextlinks = XEXP (nextlinks, 1))
1230 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1232 &new_direct_jump_p)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn)
1238 && (prev = prev_nonnote_insn (insn)) != 0
1239 && NONJUMP_INSN_P (prev)
1240 && sets_cc0_p (PATTERN (prev))
1241 && GET_CODE (PATTERN (insn)) == SET
1242 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1244 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1245 &new_direct_jump_p)) != 0)
1248 for (nextlinks = LOG_LINKS (prev); nextlinks;
1249 nextlinks = XEXP (nextlinks, 1))
1250 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1252 &new_direct_jump_p)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1260 if (NONJUMP_INSN_P (XEXP (links, 0))
1261 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1263 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1264 && NONJUMP_INSN_P (prev)
1265 && sets_cc0_p (PATTERN (prev))
1266 && (next = try_combine (insn, XEXP (links, 0),
1268 &new_direct_jump_p)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1275 for (nextlinks = XEXP (links, 1); nextlinks;
1276 nextlinks = XEXP (nextlinks, 1))
1277 if ((next = try_combine (insn, XEXP (links, 0),
1278 XEXP (nextlinks, 0), NULL_RTX,
1279 &new_direct_jump_p)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1286 rtx link = XEXP (links, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1295 rtx link1 = XEXP (next1, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks = LOG_LINKS (link1); nextlinks;
1300 nextlinks = XEXP (nextlinks, 1))
1301 if ((next = try_combine (insn, link, link1,
1302 XEXP (nextlinks, 0),
1303 &new_direct_jump_p)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks = XEXP (next1, 1); nextlinks;
1307 nextlinks = XEXP (nextlinks, 1))
1308 if ((next = try_combine (insn, link, link1,
1309 XEXP (nextlinks, 0),
1310 &new_direct_jump_p)) != 0)
1314 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1316 rtx link1 = XEXP (next1, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks = LOG_LINKS (link); nextlinks;
1321 nextlinks = XEXP (nextlinks, 1))
1322 if ((next = try_combine (insn, link, link1,
1323 XEXP (nextlinks, 0),
1324 &new_direct_jump_p)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks = LOG_LINKS (link1); nextlinks;
1328 nextlinks = XEXP (nextlinks, 1))
1329 if ((next = try_combine (insn, link, link1,
1330 XEXP (nextlinks, 0),
1331 &new_direct_jump_p)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1340 rtx temp = XEXP (links, 0);
1341 if ((set = single_set (temp)) != 0
1342 && (note = find_reg_equal_equiv_note (temp)) != 0
1343 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note, SET_SRC (set))
1347 && (GET_MODE (note) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1349 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig = SET_SRC (set);
1355 SET_SRC (set) = note;
1357 i2mod_old_rhs = copy_rtx (orig);
1358 i2mod_new_rhs = copy_rtx (note);
1359 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1360 &new_direct_jump_p);
1364 SET_SRC (set) = orig;
1369 record_dead_and_set_regs (insn);
1377 default_rtl_profile ();
1380 new_direct_jump_p |= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links);
1385 free (uid_insn_cost);
1386 VEC_free (reg_stat_type, heap, reg_stat);
1389 struct undo *undo, *next;
1390 for (undo = undobuf.frees; undo; undo = next)
1398 total_attempts += combine_attempts;
1399 total_merges += combine_merges;
1400 total_extras += combine_extras;
1401 total_successes += combine_successes;
1403 nonzero_sign_valid = 0;
1404 rtl_hooks = general_rtl_hooks;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1421 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first)
1430 bool strictly_local = false;
1432 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1433 arg = DECL_CHAIN (arg))
1435 rtx x, reg = DECL_INCOMING_RTL (arg);
1437 enum machine_mode mode1, mode2, mode3, mode4;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local = cgraph_local_info (current_function_decl)->local;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1 = TYPE_MODE (TREE_TYPE (arg));
1452 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1457 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1462 TREE_TYPE (cfun->decl), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4 = GET_MODE (reg);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1497 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1498 record_value_for_reg (reg, first, x);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1516 rtx insn = (rtx) data;
1520 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1525 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1527 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1529 if (set == 0 || GET_CODE (set) == CLOBBER)
1531 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1532 rsp->sign_bit_copies = 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x, PATTERN (insn))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1556 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1558 if (dead_or_set_p (XEXP (link, 0), x))
1563 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1564 rsp->sign_bit_copies = 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set = expand_field_assignment (set);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set) == x
1577 || (GET_CODE (SET_DEST (set)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1580 && SUBREG_REG (SET_DEST (set)) == x))
1582 rtx src = SET_SRC (set);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1595 && CONST_INT_P (src)
1597 && 0 != (INTVAL (src)
1598 & ((HOST_WIDE_INT) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1600 src = GEN_INT (INTVAL (src)
1601 | ((HOST_WIDE_INT) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1607 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1608 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1609 if (rsp->sign_bit_copies == 0
1610 || rsp->sign_bit_copies > num)
1611 rsp->sign_bit_copies = num;
1615 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1616 rsp->sign_bit_copies = 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1634 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1635 rtx *pdest, rtx *psrc)
1644 bool all_adjacent = true;
1650 if (next_active_insn (succ2) != i3)
1651 all_adjacent = false;
1652 if (next_active_insn (succ) != succ2)
1653 all_adjacent = false;
1655 else if (next_active_insn (succ) != i3)
1656 all_adjacent = false;
1657 if (next_active_insn (insn) != succ)
1658 all_adjacent = false;
1660 else if (next_active_insn (insn) != i3)
1661 all_adjacent = false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn)) == SET)
1679 set = PATTERN (insn);
1680 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1683 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1685 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1687 switch (GET_CODE (elt))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt, 0))
1706 && GET_CODE (PATTERN (i3)) == PARALLEL)
1708 rtx i3pat = PATTERN (i3);
1709 int i = XVECLEN (i3pat, 0) - 1;
1710 unsigned int regno = REGNO (XEXP (elt, 0));
1714 rtx i3elt = XVECEXP (i3pat, 0, i);
1716 if (GET_CODE (i3elt) == USE
1717 && REG_P (XEXP (i3elt, 0))
1718 && (REGNO (XEXP (i3elt, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt, 0),
1720 PREV_INSN (insn), i3)
1721 : regno >= FIRST_PSEUDO_REGISTER))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1736 && insn_nothrow_p (insn)
1737 && !side_effects_p (elt))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1766 set = expand_field_assignment (set);
1767 src = SET_SRC (set), dest = SET_DEST (set);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest == stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3, USE, dest)
1782 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1783 && global_regs[REGNO (dest)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3, dest)
1786 || (succ && FIND_REG_INC_NOTE (succ, dest))
1787 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest, succ2, i3)
1794 || reg_used_between_p (dest, succ, succ2)))
1795 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn, REG_EQUIV, src))
1808 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1809 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1810 || GET_CODE (src) == UNSPEC_VOLATILE))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1845 else if (GET_CODE (dest) != CC0)
1849 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1850 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1856 if (rtx_equal_p (reg, dest))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs[REGNO (reg)])
1869 if (reg_overlap_mentioned_p (reg, src))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1881 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src) == ASM_OPERANDS
1890 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1897 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1908 if (REG_NOTE_KIND (link) == REG_INC
1910 || reg_used_between_p (XEXP (link, 0), insn, i3)
1911 || (pred != NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1913 || (pred2 != NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1915 || (succ != NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1917 || (succ2 != NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1919 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p = prev_nonnote_insn (insn);
1934 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
1988 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
1992 if (GET_CODE (x) == SET)
1995 rtx dest = SET_DEST (set);
1996 rtx src = SET_SRC (set);
1997 rtx inner_dest = dest;
2000 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest) == SUBREG
2002 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2003 inner_dest = XEXP (inner_dest, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest != dest &&
2010 (!MEM_P (inner_dest)
2011 || rtx_equal_p (i2dest, inner_dest)
2012 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2013 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2014 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2015 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2016 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest)
2029 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2031 GET_MODE (inner_dest))))
2032 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2033 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2047 subdest = SUBREG_REG (subdest);
2050 && reg_referenced_p (subdest, PATTERN (i3))
2051 && REGNO (subdest) != FRAME_POINTER_REGNUM
2052 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2053 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest) != ARG_POINTER_REGNUM
2057 || ! fixed_regs [REGNO (subdest)])
2059 && REGNO (subdest) != STACK_POINTER_REGNUM)
2061 if (*pi3dest_killed)
2064 *pi3dest_killed = subdest;
2068 else if (GET_CODE (x) == PARALLEL)
2072 for (i = 0; i < XVECLEN (x, 0); i++)
2073 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2074 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x)
2087 switch (GET_CODE (x))
2089 case MOD: case DIV: case UMOD: case UDIV:
2093 return ! (CONST_INT_P (XEXP (x, 1))
2094 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
2097 return contains_muldiv (XEXP (x, 0))
2098 || contains_muldiv (XEXP (x, 1));
2101 return contains_muldiv (XEXP (x, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set = single_set (insn);
2133 src = SET_SRC (set);
2134 dest = SET_DEST (set);
2135 if (GET_CODE (src) == SUBREG)
2136 src = SUBREG_REG (src);
2137 if (GET_CODE (dest) == SUBREG)
2138 dest = SUBREG_REG (dest);
2139 if (REG_P (src) && REG_P (dest)
2140 && ((HARD_REGISTER_P (src)
2141 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2142 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2143 || (HARD_REGISTER_P (dest)
2144 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2145 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno, nregs;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2162 struct likely_spilled_retval_info *const info =
2163 (struct likely_spilled_retval_info *) data;
2164 unsigned regno, nregs;
2167 if (!REG_P (XEXP (set, 0)))
2170 if (regno >= info->regno + info->nregs)
2172 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2173 if (regno + nregs <= info->regno)
2175 new_mask = (2U << (nregs - 1)) - 1;
2176 if (regno < info->regno)
2177 new_mask >>= info->regno - regno;
2179 new_mask <<= regno - info->regno;
2180 info->mask &= ~new_mask;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn)
2191 rtx use = BB_END (this_basic_block);
2193 unsigned regno, nregs;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info;
2200 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2202 reg = XEXP (PATTERN (use), 0);
2203 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2205 regno = REGNO (reg);
2206 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2209 mask = (2U << (nregs - 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2217 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask & 1 << nregs)
2226 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2248 df_insn_rescan (insn);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno < FIRST_PSEUDO_REGISTER)
2265 return (HARD_REGNO_MODE_OK (regno, mode)
2266 && (hard_regno_nregs[regno][GET_MODE (x)]
2267 >= hard_regno_nregs[regno][mode]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno) == 1 && !added_sets
2271 && !REG_USERVAR_P (x));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x, rtx reg)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2285 if (GET_CODE (x) == STRICT_LOW_PART
2286 || GET_CODE (x) == ZERO_EXTRACT)
2289 return GET_CODE (x) == SUBREG
2290 && SUBREG_REG (x) == reg
2291 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2295 /* Replace auto-increment addressing modes with explicit operations to access
2296 the same addresses without modifying the corresponding registers. */
2299 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2302 const RTX_CODE code = GET_CODE (x);
2318 /* SCRATCH must be shared because they represent distinct values. */
2321 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2326 if (shared_const_p (x))
2331 mem_mode = GET_MODE (x);
2336 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2337 return gen_rtx_PLUS (GET_MODE (x),
2338 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2339 GEN_INT (code == PRE_INC
2340 ? GET_MODE_SIZE (mem_mode)
2341 : -GET_MODE_SIZE (mem_mode)));
2347 return cleanup_auto_inc_dec (code == PRE_MODIFY
2348 ? XEXP (x, 1) : XEXP (x, 0),
2355 /* Copy the various flags, fields, and other information. We assume
2356 that all fields need copying, and then clear the fields that should
2357 not be copied. That is the sensible default behavior, and forces
2358 us to explicitly document why we are *not* copying a flag. */
2359 x = shallow_copy_rtx (x);
2361 /* We do not copy the USED flag, which is used as a mark bit during
2362 walks over the RTL. */
2363 RTX_FLAG (x, used) = 0;
2365 /* We do not copy FRAME_RELATED for INSNs. */
2367 RTX_FLAG (x, frame_related) = 0;
2369 fmt = GET_RTX_FORMAT (code);
2370 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2372 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2373 else if (fmt[i] == 'E' || fmt[i] == 'V')
2376 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2377 for (j = 0; j < XVECLEN (x, i); j++)
2379 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2386 /* Auxiliary data structure for propagate_for_debug_stmt. */
2388 struct rtx_subst_pair
2394 /* DATA points to an rtx_subst_pair. Return the value that should be
2398 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2400 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2402 if (!rtx_equal_p (from, old_rtx))
2404 if (!pair->adjusted)
2406 pair->adjusted = true;
2408 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2410 pair->to = copy_rtx (pair->to);
2412 pair->to = make_compound_operation (pair->to, SET);
2415 return copy_rtx (pair->to);
2418 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2422 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2426 struct rtx_subst_pair p;
2430 next = NEXT_INSN (insn);
2431 while (next != last)
2434 next = NEXT_INSN (insn);
2435 if (DEBUG_INSN_P (insn))
2437 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2438 dest, propagate_for_debug_subst, &p);
2439 if (loc == INSN_VAR_LOCATION_LOC (insn))
2441 INSN_VAR_LOCATION_LOC (insn) = loc;
2442 df_insn_rescan (insn);
2447 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2448 Note that the INSN should be deleted *after* removing dead edges, so
2449 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2450 but not for a (set (pc) (label_ref FOO)). */
2453 update_cfg_for_uncondjump (rtx insn)
2455 basic_block bb = BLOCK_FOR_INSN (insn);
2456 bool at_end = (BB_END (bb) == insn);
2459 purge_dead_edges (bb);
2462 if (at_end && EDGE_COUNT (bb->succs) == 1)
2463 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2466 /* Try to combine the insns I0, I1 and I2 into I3.
2467 Here I0, I1 and I2 appear earlier than I3.
2468 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2471 If we are combining more than two insns and the resulting insn is not
2472 recognized, try splitting it into two insns. If that happens, I2 and I3
2473 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2474 Otherwise, I0, I1 and I2 are pseudo-deleted.
2476 Return 0 if the combination does not work. Then nothing is changed.
2477 If we did the combination, return the insn at which combine should
2480 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2481 new direct jump instruction. */
2484 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p)
2486 /* New patterns for I3 and I2, respectively. */
2487 rtx newpat, newi2pat = 0;
2488 rtvec newpat_vec_with_clobbers = 0;
2489 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2490 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2492 int added_sets_0, added_sets_1, added_sets_2;
2493 /* Total number of SETs to put into I3. */
2495 /* Nonzero if I2's or I1's body now appears in I3. */
2496 int i2_is_used = 0, i1_is_used = 0;
2497 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2498 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2499 /* Contains I3 if the destination of I3 is used in its source, which means
2500 that the old life of I3 is being killed. If that usage is placed into
2501 I2 and not in I3, a REG_DEAD note must be made. */
2502 rtx i3dest_killed = 0;
2503 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2504 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2505 /* Set if I2DEST was reused as a scratch register. */
2506 bool i2scratch = false;
2507 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2508 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2509 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2510 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2511 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2512 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2513 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2514 /* Notes that must be added to REG_NOTES in I3 and I2. */
2515 rtx new_i3_notes, new_i2_notes;
2516 /* Notes that we substituted I3 into I2 instead of the normal case. */
2517 int i3_subst_into_i2 = 0;
2518 /* Notes that I1, I2 or I3 is a MULT operation. */
2521 int changed_i3_dest = 0;
2527 rtx new_other_notes;
2530 /* Only try four-insn combinations when there's high likelihood of
2531 success. Look for simple insns, such as loads of constants or
2532 binary operations involving a constant. */
2539 if (!flag_expensive_optimizations)
2542 for (i = 0; i < 4; i++)
2544 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2545 rtx set = single_set (insn);
2549 src = SET_SRC (set);
2550 if (CONSTANT_P (src))
2555 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2557 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2558 || GET_CODE (src) == LSHIFTRT)
2561 if (ngood < 2 && nshift < 2)
2565 /* Exit early if one of the insns involved can't be used for
2567 if (cant_combine_insn_p (i3)
2568 || cant_combine_insn_p (i2)
2569 || (i1 && cant_combine_insn_p (i1))
2570 || (i0 && cant_combine_insn_p (i0))
2571 || likely_spilled_retval_p (i3))
2575 undobuf.other_insn = 0;
2577 /* Reset the hard register usage information. */
2578 CLEAR_HARD_REG_SET (newpat_used_regs);
2580 if (dump_file && (dump_flags & TDF_DETAILS))
2583 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2584 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2586 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2587 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2589 fprintf (dump_file, "\nTrying %d -> %d:\n",
2590 INSN_UID (i2), INSN_UID (i3));
2593 /* If multiple insns feed into one of I2 or I3, they can be in any
2594 order. To simplify the code below, reorder them in sequence. */
2595 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2596 temp = i2, i2 = i0, i0 = temp;
2597 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2598 temp = i1, i1 = i0, i0 = temp;
2599 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2600 temp = i1, i1 = i2, i2 = temp;
2602 added_links_insn = 0;
2604 /* First check for one important special case that the code below will
2605 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2606 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2607 we may be able to replace that destination with the destination of I3.
2608 This occurs in the common code where we compute both a quotient and
2609 remainder into a structure, in which case we want to do the computation
2610 directly into the structure to avoid register-register copies.
2612 Note that this case handles both multiple sets in I2 and also cases
2613 where I2 has a number of CLOBBERs inside the PARALLEL.
2615 We make very conservative checks below and only try to handle the
2616 most common cases of this. For example, we only handle the case
2617 where I2 and I3 are adjacent to avoid making difficult register
2620 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2621 && REG_P (SET_SRC (PATTERN (i3)))
2622 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2623 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2624 && GET_CODE (PATTERN (i2)) == PARALLEL
2625 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2626 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2627 below would need to check what is inside (and reg_overlap_mentioned_p
2628 doesn't support those codes anyway). Don't allow those destinations;
2629 the resulting insn isn't likely to be recognized anyway. */
2630 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2631 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2632 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2633 SET_DEST (PATTERN (i3)))
2634 && next_active_insn (i2) == i3)
2636 rtx p2 = PATTERN (i2);
2638 /* Make sure that the destination of I3,
2639 which we are going to substitute into one output of I2,
2640 is not used within another output of I2. We must avoid making this:
2641 (parallel [(set (mem (reg 69)) ...)
2642 (set (reg 69) ...)])
2643 which is not well-defined as to order of actions.
2644 (Besides, reload can't handle output reloads for this.)
2646 The problem can also happen if the dest of I3 is a memory ref,
2647 if another dest in I2 is an indirect memory ref. */
2648 for (i = 0; i < XVECLEN (p2, 0); i++)
2649 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2650 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2651 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2652 SET_DEST (XVECEXP (p2, 0, i))))
2655 if (i == XVECLEN (p2, 0))
2656 for (i = 0; i < XVECLEN (p2, 0); i++)
2657 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2658 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2663 subst_low_luid = DF_INSN_LUID (i2);
2665 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2666 i2src = SET_SRC (XVECEXP (p2, 0, i));
2667 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2668 i2dest_killed = dead_or_set_p (i2, i2dest);
2670 /* Replace the dest in I2 with our dest and make the resulting
2671 insn the new pattern for I3. Then skip to where we validate
2672 the pattern. Everything was set up above. */
2673 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2675 i3_subst_into_i2 = 1;
2676 goto validate_replacement;
2680 /* If I2 is setting a pseudo to a constant and I3 is setting some
2681 sub-part of it to another constant, merge them by making a new
2684 && (temp = single_set (i2)) != 0
2685 && (CONST_INT_P (SET_SRC (temp))
2686 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2687 && GET_CODE (PATTERN (i3)) == SET
2688 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2689 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2690 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2692 rtx dest = SET_DEST (PATTERN (i3));
2696 if (GET_CODE (dest) == ZERO_EXTRACT)
2698 if (CONST_INT_P (XEXP (dest, 1))
2699 && CONST_INT_P (XEXP (dest, 2)))
2701 width = INTVAL (XEXP (dest, 1));
2702 offset = INTVAL (XEXP (dest, 2));
2703 dest = XEXP (dest, 0);
2704 if (BITS_BIG_ENDIAN)
2705 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2710 if (GET_CODE (dest) == STRICT_LOW_PART)
2711 dest = XEXP (dest, 0);
2712 width = GET_MODE_BITSIZE (GET_MODE (dest));
2718 /* If this is the low part, we're done. */
2719 if (subreg_lowpart_p (dest))
2721 /* Handle the case where inner is twice the size of outer. */
2722 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2723 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2724 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2725 /* Otherwise give up for now. */
2731 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2732 <= HOST_BITS_PER_DOUBLE_INT))
2735 rtx inner = SET_SRC (PATTERN (i3));
2736 rtx outer = SET_SRC (temp);
2738 o = rtx_to_double_int (outer);
2739 i = rtx_to_double_int (inner);
2741 m = double_int_mask (width);
2742 i = double_int_and (i, m);
2743 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2744 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2745 o = double_int_ior (double_int_and_not (o, m), i);
2749 subst_low_luid = DF_INSN_LUID (i2);
2750 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2751 i2dest = SET_DEST (temp);
2752 i2dest_killed = dead_or_set_p (i2, i2dest);
2754 /* Replace the source in I2 with the new constant and make the
2755 resulting insn the new pattern for I3. Then skip to where we
2756 validate the pattern. Everything was set up above. */
2757 SUBST (SET_SRC (temp),
2758 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2760 newpat = PATTERN (i2);
2762 /* The dest of I3 has been replaced with the dest of I2. */
2763 changed_i3_dest = 1;
2764 goto validate_replacement;
2769 /* If we have no I1 and I2 looks like:
2770 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2772 make up a dummy I1 that is
2775 (set (reg:CC X) (compare:CC Y (const_int 0)))
2777 (We can ignore any trailing CLOBBERs.)
2779 This undoes a previous combination and allows us to match a branch-and-
2782 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2783 && XVECLEN (PATTERN (i2), 0) >= 2
2784 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2785 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2787 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2788 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2789 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2790 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2791 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2792 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2794 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2795 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2800 /* We make I1 with the same INSN_UID as I2. This gives it
2801 the same DF_INSN_LUID for value tracking. Our fake I1 will
2802 never appear in the insn stream so giving it the same INSN_UID
2803 as I2 will not cause a problem. */
2805 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2806 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2807 INSN_LOCATOR (i2), -1, NULL_RTX);
2809 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2810 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2811 SET_DEST (PATTERN (i1)));
2816 /* Verify that I2 and I1 are valid for combining. */
2817 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2818 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2820 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2827 /* Record whether I2DEST is used in I2SRC and similarly for the other
2828 cases. Knowing this will help in register status updating below. */
2829 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2830 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2831 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2832 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2833 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2834 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2835 i2dest_killed = dead_or_set_p (i2, i2dest);
2836 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2837 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2839 /* For the earlier insns, determine which of the subsequent ones they
2841 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2842 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2843 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2844 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2845 && reg_overlap_mentioned_p (i0dest, i2src))));
2847 /* Ensure that I3's pattern can be the destination of combines. */
2848 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2849 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2850 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2851 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2858 /* See if any of the insns is a MULT operation. Unless one is, we will
2859 reject a combination that is, since it must be slower. Be conservative
2861 if (GET_CODE (i2src) == MULT
2862 || (i1 != 0 && GET_CODE (i1src) == MULT)
2863 || (i0 != 0 && GET_CODE (i0src) == MULT)
2864 || (GET_CODE (PATTERN (i3)) == SET
2865 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2868 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2869 We used to do this EXCEPT in one case: I3 has a post-inc in an
2870 output operand. However, that exception can give rise to insns like
2872 which is a famous insn on the PDP-11 where the value of r3 used as the
2873 source was model-dependent. Avoid this sort of thing. */
2876 if (!(GET_CODE (PATTERN (i3)) == SET
2877 && REG_P (SET_SRC (PATTERN (i3)))
2878 && MEM_P (SET_DEST (PATTERN (i3)))
2879 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2880 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2881 /* It's not the exception. */
2884 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2885 if (REG_NOTE_KIND (link) == REG_INC
2886 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2888 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2895 /* See if the SETs in I1 or I2 need to be kept around in the merged
2896 instruction: whenever the value set there is still needed past I3.
2897 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2899 For the SET in I1, we have two cases: If I1 and I2 independently
2900 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2901 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2902 in I1 needs to be kept around unless I1DEST dies or is set in either
2903 I2 or I3. The same consideration applies to I0. */
2905 added_sets_2 = !dead_or_set_p (i3, i2dest);
2908 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2909 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2914 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2915 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2916 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2920 /* We are about to copy insns for the case where they need to be kept
2921 around. Check that they can be copied in the merged instruction. */
2923 if (targetm.cannot_copy_insn_p
2924 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2925 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2926 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2932 /* If the set in I2 needs to be kept around, we must make a copy of
2933 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2934 PATTERN (I2), we are only substituting for the original I1DEST, not into
2935 an already-substituted copy. This also prevents making self-referential
2936 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2941 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2942 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2944 i2pat = copy_rtx (PATTERN (i2));
2949 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2950 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2952 i1pat = copy_rtx (PATTERN (i1));
2957 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2958 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2960 i0pat = copy_rtx (PATTERN (i0));
2965 /* Substitute in the latest insn for the regs set by the earlier ones. */
2967 maxreg = max_reg_num ();
2972 /* Many machines that don't use CC0 have insns that can both perform an
2973 arithmetic operation and set the condition code. These operations will
2974 be represented as a PARALLEL with the first element of the vector
2975 being a COMPARE of an arithmetic operation with the constant zero.
2976 The second element of the vector will set some pseudo to the result
2977 of the same arithmetic operation. If we simplify the COMPARE, we won't
2978 match such a pattern and so will generate an extra insn. Here we test
2979 for this case, where both the comparison and the operation result are
2980 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2981 I2SRC. Later we will make the PARALLEL that contains I2. */
2983 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2984 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2985 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2986 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2988 #ifdef SELECT_CC_MODE
2990 enum machine_mode compare_mode;
2993 newpat = PATTERN (i3);
2994 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2998 #ifdef SELECT_CC_MODE
2999 /* See if a COMPARE with the operand we substituted in should be done
3000 with the mode that is currently being used. If not, do the same
3001 processing we do in `subst' for a SET; namely, if the destination
3002 is used only once, try to replace it with a register of the proper
3003 mode and also replace the COMPARE. */
3004 if (undobuf.other_insn == 0
3005 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3006 &undobuf.other_insn))
3007 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3009 != GET_MODE (SET_DEST (newpat))))
3011 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3014 unsigned int regno = REGNO (SET_DEST (newpat));
3017 if (regno < FIRST_PSEUDO_REGISTER)
3018 new_dest = gen_rtx_REG (compare_mode, regno);
3021 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3022 new_dest = regno_reg_rtx[regno];
3025 SUBST (SET_DEST (newpat), new_dest);
3026 SUBST (XEXP (*cc_use, 0), new_dest);
3027 SUBST (SET_SRC (newpat),
3028 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3031 undobuf.other_insn = 0;
3038 /* It is possible that the source of I2 or I1 may be performing
3039 an unneeded operation, such as a ZERO_EXTEND of something
3040 that is known to have the high part zero. Handle that case
3041 by letting subst look at the innermost one of them.
3043 Another way to do this would be to have a function that tries
3044 to simplify a single insn instead of merging two or more
3045 insns. We don't do this because of the potential of infinite
3046 loops and because of the potential extra memory required.
3047 However, doing it the way we are is a bit of a kludge and
3048 doesn't catch all cases.
3050 But only do this if -fexpensive-optimizations since it slows
3051 things down and doesn't usually win.
3053 This is not done in the COMPARE case above because the
3054 unmodified I2PAT is used in the PARALLEL and so a pattern
3055 with a modified I2SRC would not match. */
3057 if (flag_expensive_optimizations)
3059 /* Pass pc_rtx so no substitutions are done, just
3063 subst_low_luid = DF_INSN_LUID (i1);
3064 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3068 subst_low_luid = DF_INSN_LUID (i2);
3069 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3073 n_occurrences = 0; /* `subst' counts here */
3075 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3076 unique copy of I2SRC each time we substitute it to avoid
3077 self-referential rtl. */
3079 subst_low_luid = DF_INSN_LUID (i2);
3080 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3081 ((i1_feeds_i2_n && i1dest_in_i1src)
3082 || (i0_feeds_i2_n && i0dest_in_i0src)));
3085 /* Record whether i2's body now appears within i3's body. */
3086 i2_is_used = n_occurrences;
3089 /* If we already got a failure, don't try to do more. Otherwise,
3090 try to substitute in I1 if we have it. */
3092 if (i1 && GET_CODE (newpat) != CLOBBER)
3094 /* Check that an autoincrement side-effect on I1 has not been lost.
3095 This happens if I1DEST is mentioned in I2 and dies there, and
3096 has disappeared from the new pattern. */
3097 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3099 && dead_or_set_p (i2, i1dest)
3100 && !reg_overlap_mentioned_p (i1dest, newpat))
3101 /* Before we can do this substitution, we must redo the test done
3102 above (see detailed comments there) that ensures that I1DEST
3103 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3104 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3112 subst_low_luid = DF_INSN_LUID (i1);
3113 newpat = subst (newpat, i1dest, i1src, 0,
3114 i0_feeds_i1_n && i0dest_in_i0src);
3116 i1_is_used = n_occurrences;
3118 if (i0 && GET_CODE (newpat) != CLOBBER)
3120 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3121 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3122 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3123 && !reg_overlap_mentioned_p (i0dest, newpat))
3124 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3132 subst_low_luid = DF_INSN_LUID (i0);
3133 newpat = subst (newpat, i0dest, i0src, 0,
3134 i0_feeds_i1_n && i0dest_in_i0src);
3138 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3139 to count all the ways that I2SRC and I1SRC can be used. */
3140 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3141 && i2_is_used + added_sets_2 > 1)
3142 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3143 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3145 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3146 && (n_occurrences + added_sets_0
3147 + (added_sets_1 && i0_feeds_i1_n)
3148 + (added_sets_2 && i0_feeds_i2_n)
3150 /* Fail if we tried to make a new register. */
3151 || max_reg_num () != maxreg
3152 /* Fail if we couldn't do something and have a CLOBBER. */
3153 || GET_CODE (newpat) == CLOBBER
3154 /* Fail if this new pattern is a MULT and we didn't have one before
3155 at the outer level. */
3156 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3163 /* If the actions of the earlier insns must be kept
3164 in addition to substituting them into the latest one,
3165 we must make a new PARALLEL for the latest insn
3166 to hold additional the SETs. */
3168 if (added_sets_0 || added_sets_1 || added_sets_2)
3170 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3173 if (GET_CODE (newpat) == PARALLEL)
3175 rtvec old = XVEC (newpat, 0);
3176 total_sets = XVECLEN (newpat, 0) + extra_sets;
3177 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3178 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3179 sizeof (old->elem[0]) * old->num_elem);
3184 total_sets = 1 + extra_sets;
3185 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3186 XVECEXP (newpat, 0, 0) = old;
3190 XVECEXP (newpat, 0, --total_sets) = i0pat;
3196 t = subst (t, i0dest, i0src, 0, 0);
3198 XVECEXP (newpat, 0, --total_sets) = t;
3204 t = subst (t, i0dest, i0src, 0, 0);
3206 t = subst (t, i1dest, i1src, 0, 0);
3207 if (i0_feeds_i1_n && i1_feeds_i2_n)
3208 t = subst (t, i0dest, i0src, 0, 0);
3210 XVECEXP (newpat, 0, --total_sets) = t;
3214 validate_replacement:
3216 /* Note which hard regs this insn has as inputs. */
3217 mark_used_regs_combine (newpat);
3219 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3220 consider splitting this pattern, we might need these clobbers. */
3221 if (i1 && GET_CODE (newpat) == PARALLEL
3222 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3224 int len = XVECLEN (newpat, 0);
3226 newpat_vec_with_clobbers = rtvec_alloc (len);
3227 for (i = 0; i < len; i++)
3228 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3231 /* Is the result of combination a valid instruction? */
3232 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3234 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3235 the second SET's destination is a register that is unused and isn't
3236 marked as an instruction that might trap in an EH region. In that case,
3237 we just need the first SET. This can occur when simplifying a divmod
3238 insn. We *must* test for this case here because the code below that
3239 splits two independent SETs doesn't handle this case correctly when it
3240 updates the register status.
3242 It's pointless doing this if we originally had two sets, one from
3243 i3, and one from i2. Combining then splitting the parallel results
3244 in the original i2 again plus an invalid insn (which we delete).
3245 The net effect is only to move instructions around, which makes
3246 debug info less accurate.
3248 Also check the case where the first SET's destination is unused.
3249 That would not cause incorrect code, but does cause an unneeded
3252 if (insn_code_number < 0
3253 && !(added_sets_2 && i1 == 0)
3254 && GET_CODE (newpat) == PARALLEL
3255 && XVECLEN (newpat, 0) == 2
3256 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3257 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3258 && asm_noperands (newpat) < 0)
3260 rtx set0 = XVECEXP (newpat, 0, 0);
3261 rtx set1 = XVECEXP (newpat, 0, 1);
3263 if (((REG_P (SET_DEST (set1))
3264 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3265 || (GET_CODE (SET_DEST (set1)) == SUBREG
3266 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3267 && insn_nothrow_p (i3)
3268 && !side_effects_p (SET_SRC (set1)))
3271 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3274 else if (((REG_P (SET_DEST (set0))
3275 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3276 || (GET_CODE (SET_DEST (set0)) == SUBREG
3277 && find_reg_note (i3, REG_UNUSED,
3278 SUBREG_REG (SET_DEST (set0)))))
3279 && insn_nothrow_p (i3)
3280 && !side_effects_p (SET_SRC (set0)))
3283 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3285 if (insn_code_number >= 0)
3286 changed_i3_dest = 1;
3290 /* If we were combining three insns and the result is a simple SET
3291 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3292 insns. There are two ways to do this. It can be split using a
3293 machine-specific method (like when you have an addition of a large
3294 constant) or by combine in the function find_split_point. */
3296 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3297 && asm_noperands (newpat) < 0)
3299 rtx parallel, m_split, *split;
3301 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3302 use I2DEST as a scratch register will help. In the latter case,
3303 convert I2DEST to the mode of the source of NEWPAT if we can. */
3305 m_split = combine_split_insns (newpat, i3);
3307 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3308 inputs of NEWPAT. */
3310 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3311 possible to try that as a scratch reg. This would require adding
3312 more code to make it work though. */
3314 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3316 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3318 /* First try to split using the original register as a
3319 scratch register. */
3320 parallel = gen_rtx_PARALLEL (VOIDmode,
3321 gen_rtvec (2, newpat,
3322 gen_rtx_CLOBBER (VOIDmode,
3324 m_split = combine_split_insns (parallel, i3);
3326 /* If that didn't work, try changing the mode of I2DEST if
3329 && new_mode != GET_MODE (i2dest)
3330 && new_mode != VOIDmode
3331 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3333 enum machine_mode old_mode = GET_MODE (i2dest);
3336 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3337 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3340 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3341 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3344 parallel = (gen_rtx_PARALLEL
3346 gen_rtvec (2, newpat,
3347 gen_rtx_CLOBBER (VOIDmode,
3349 m_split = combine_split_insns (parallel, i3);
3352 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3356 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3357 buf = undobuf.undos;
3358 undobuf.undos = buf->next;
3359 buf->next = undobuf.frees;
3360 undobuf.frees = buf;
3364 i2scratch = m_split != 0;
3367 /* If recog_for_combine has discarded clobbers, try to use them
3368 again for the split. */
3369 if (m_split == 0 && newpat_vec_with_clobbers)
3371 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3372 m_split = combine_split_insns (parallel, i3);
3375 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3377 m_split = PATTERN (m_split);
3378 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3379 if (insn_code_number >= 0)
3382 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3383 && (next_real_insn (i2) == i3
3384 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3387 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3388 newi2pat = PATTERN (m_split);
3390 i3set = single_set (NEXT_INSN (m_split));
3391 i2set = single_set (m_split);
3393 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3395 /* If I2 or I3 has multiple SETs, we won't know how to track
3396 register status, so don't use these insns. If I2's destination
3397 is used between I2 and I3, we also can't use these insns. */
3399 if (i2_code_number >= 0 && i2set && i3set
3400 && (next_real_insn (i2) == i3
3401 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3402 insn_code_number = recog_for_combine (&newi3pat, i3,
3404 if (insn_code_number >= 0)
3407 /* It is possible that both insns now set the destination of I3.
3408 If so, we must show an extra use of it. */
3410 if (insn_code_number >= 0)
3412 rtx new_i3_dest = SET_DEST (i3set);
3413 rtx new_i2_dest = SET_DEST (i2set);
3415 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3416 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3417 || GET_CODE (new_i3_dest) == SUBREG)
3418 new_i3_dest = XEXP (new_i3_dest, 0);
3420 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3421 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3422 || GET_CODE (new_i2_dest) == SUBREG)
3423 new_i2_dest = XEXP (new_i2_dest, 0);
3425 if (REG_P (new_i3_dest)
3426 && REG_P (new_i2_dest)
3427 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3428 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3432 /* If we can split it and use I2DEST, go ahead and see if that
3433 helps things be recognized. Verify that none of the registers
3434 are set between I2 and I3. */
3435 if (insn_code_number < 0
3436 && (split = find_split_point (&newpat, i3, false)) != 0
3440 /* We need I2DEST in the proper mode. If it is a hard register
3441 or the only use of a pseudo, we can change its mode.
3442 Make sure we don't change a hard register to have a mode that
3443 isn't valid for it, or change the number of registers. */
3444 && (GET_MODE (*split) == GET_MODE (i2dest)
3445 || GET_MODE (*split) == VOIDmode
3446 || can_change_dest_mode (i2dest, added_sets_2,
3448 && (next_real_insn (i2) == i3
3449 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3450 /* We can't overwrite I2DEST if its value is still used by
3452 && ! reg_referenced_p (i2dest, newpat))
3454 rtx newdest = i2dest;
3455 enum rtx_code split_code = GET_CODE (*split);
3456 enum machine_mode split_mode = GET_MODE (*split);
3457 bool subst_done = false;
3458 newi2pat = NULL_RTX;
3462 /* *SPLIT may be part of I2SRC, so make sure we have the
3463 original expression around for later debug processing.
3464 We should not need I2SRC any more in other cases. */
3465 if (MAY_HAVE_DEBUG_INSNS)
3466 i2src = copy_rtx (i2src);
3470 /* Get NEWDEST as a register in the proper mode. We have already
3471 validated that we can do this. */
3472 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3474 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3475 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3478 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3479 newdest = regno_reg_rtx[REGNO (i2dest)];
3483 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3484 an ASHIFT. This can occur if it was inside a PLUS and hence
3485 appeared to be a memory address. This is a kludge. */
3486 if (split_code == MULT
3487 && CONST_INT_P (XEXP (*split, 1))
3488 && INTVAL (XEXP (*split, 1)) > 0
3489 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3491 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3492 XEXP (*split, 0), GEN_INT (i)));
3493 /* Update split_code because we may not have a multiply
3495 split_code = GET_CODE (*split);
3498 #ifdef INSN_SCHEDULING
3499 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3500 be written as a ZERO_EXTEND. */
3501 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3503 #ifdef LOAD_EXTEND_OP
3504 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3505 what it really is. */
3506 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3508 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3509 SUBREG_REG (*split)));
3512 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3513 SUBREG_REG (*split)));
3517 /* Attempt to split binary operators using arithmetic identities. */
3518 if (BINARY_P (SET_SRC (newpat))
3519 && split_mode == GET_MODE (SET_SRC (newpat))
3520 && ! side_effects_p (SET_SRC (newpat)))
3522 rtx setsrc = SET_SRC (newpat);
3523 enum machine_mode mode = GET_MODE (setsrc);
3524 enum rtx_code code = GET_CODE (setsrc);
3525 rtx src_op0 = XEXP (setsrc, 0);
3526 rtx src_op1 = XEXP (setsrc, 1);
3528 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3529 if (rtx_equal_p (src_op0, src_op1))
3531 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3532 SUBST (XEXP (setsrc, 0), newdest);
3533 SUBST (XEXP (setsrc, 1), newdest);
3536 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3537 else if ((code == PLUS || code == MULT)
3538 && GET_CODE (src_op0) == code
3539 && GET_CODE (XEXP (src_op0, 0)) == code
3540 && (INTEGRAL_MODE_P (mode)
3541 || (FLOAT_MODE_P (mode)
3542 && flag_unsafe_math_optimizations)))
3544 rtx p = XEXP (XEXP (src_op0, 0), 0);
3545 rtx q = XEXP (XEXP (src_op0, 0), 1);
3546 rtx r = XEXP (src_op0, 1);
3549 /* Split both "((X op Y) op X) op Y" and
3550 "((X op Y) op Y) op X" as "T op T" where T is
3552 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3553 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3555 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3557 SUBST (XEXP (setsrc, 0), newdest);
3558 SUBST (XEXP (setsrc, 1), newdest);
3561 /* Split "((X op X) op Y) op Y)" as "T op T" where
3563 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3565 rtx tmp = simplify_gen_binary (code, mode, p, r);
3566 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3567 SUBST (XEXP (setsrc, 0), newdest);
3568 SUBST (XEXP (setsrc, 1), newdest);
3576 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3577 SUBST (*split, newdest);
3580 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3582 /* recog_for_combine might have added CLOBBERs to newi2pat.
3583 Make sure NEWPAT does not depend on the clobbered regs. */
3584 if (GET_CODE (newi2pat) == PARALLEL)
3585 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3586 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3588 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3589 if (reg_overlap_mentioned_p (reg, newpat))
3596 /* If the split point was a MULT and we didn't have one before,
3597 don't use one now. */
3598 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3599 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3603 /* Check for a case where we loaded from memory in a narrow mode and
3604 then sign extended it, but we need both registers. In that case,
3605 we have a PARALLEL with both loads from the same memory location.
3606 We can split this into a load from memory followed by a register-register
3607 copy. This saves at least one insn, more if register allocation can
3610 We cannot do this if the destination of the first assignment is a
3611 condition code register or cc0. We eliminate this case by making sure
3612 the SET_DEST and SET_SRC have the same mode.
3614 We cannot do this if the destination of the second assignment is
3615 a register that we have already assumed is zero-extended. Similarly
3616 for a SUBREG of such a register. */
3618 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3619 && GET_CODE (newpat) == PARALLEL
3620 && XVECLEN (newpat, 0) == 2
3621 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3622 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3623 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3624 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3625 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3626 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3627 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3628 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3630 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3631 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3632 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3634 && VEC_index (reg_stat_type, reg_stat,
3635 REGNO (temp))->nonzero_bits != 0
3636 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3637 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3638 && (VEC_index (reg_stat_type, reg_stat,
3639 REGNO (temp))->nonzero_bits
3640 != GET_MODE_MASK (word_mode))))
3641 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3642 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3644 && VEC_index (reg_stat_type, reg_stat,
3645 REGNO (temp))->nonzero_bits != 0
3646 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3647 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3648 && (VEC_index (reg_stat_type, reg_stat,
3649 REGNO (temp))->nonzero_bits
3650 != GET_MODE_MASK (word_mode)))))
3651 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3652 SET_SRC (XVECEXP (newpat, 0, 1)))
3653 && ! find_reg_note (i3, REG_UNUSED,
3654 SET_DEST (XVECEXP (newpat, 0, 0))))
3658 newi2pat = XVECEXP (newpat, 0, 0);
3659 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3660 newpat = XVECEXP (newpat, 0, 1);
3661 SUBST (SET_SRC (newpat),
3662 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3663 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3665 if (i2_code_number >= 0)
3666 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3668 if (insn_code_number >= 0)
3672 /* Similarly, check for a case where we have a PARALLEL of two independent
3673 SETs but we started with three insns. In this case, we can do the sets
3674 as two separate insns. This case occurs when some SET allows two
3675 other insns to combine, but the destination of that SET is still live. */
3677 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3678 && GET_CODE (newpat) == PARALLEL
3679 && XVECLEN (newpat, 0) == 2
3680 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3681 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3682 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3683 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3684 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3685 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3686 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3687 XVECEXP (newpat, 0, 0))
3688 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3689 XVECEXP (newpat, 0, 1))
3690 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3691 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3693 /* Normally, it doesn't matter which of the two is done first,
3694 but the one that references cc0 can't be the second, and
3695 one which uses any regs/memory set in between i2 and i3 can't
3697 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3700 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3704 newi2pat = XVECEXP (newpat, 0, 1);
3705 newpat = XVECEXP (newpat, 0, 0);
3707 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3710 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3714 newi2pat = XVECEXP (newpat, 0, 0);
3715 newpat = XVECEXP (newpat, 0, 1);
3723 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3725 if (i2_code_number >= 0)
3727 /* recog_for_combine might have added CLOBBERs to newi2pat.
3728 Make sure NEWPAT does not depend on the clobbered regs. */
3729 if (GET_CODE (newi2pat) == PARALLEL)
3731 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3732 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3734 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3735 if (reg_overlap_mentioned_p (reg, newpat))
3743 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3747 /* If it still isn't recognized, fail and change things back the way they
3749 if ((insn_code_number < 0
3750 /* Is the result a reasonable ASM_OPERANDS? */
3751 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3757 /* If we had to change another insn, make sure it is valid also. */
3758 if (undobuf.other_insn)
3760 CLEAR_HARD_REG_SET (newpat_used_regs);
3762 other_pat = PATTERN (undobuf.other_insn);
3763 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3766 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3774 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3775 they are adjacent to each other or not. */
3777 rtx p = prev_nonnote_insn (i3);
3778 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3779 && sets_cc0_p (newi2pat))
3787 /* Only allow this combination if insn_rtx_costs reports that the
3788 replacement instructions are cheaper than the originals. */
3789 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3795 if (MAY_HAVE_DEBUG_INSNS)
3799 for (undo = undobuf.undos; undo; undo = undo->next)
3800 if (undo->kind == UNDO_MODE)
3802 rtx reg = *undo->where.r;
3803 enum machine_mode new_mode = GET_MODE (reg);
3804 enum machine_mode old_mode = undo->old_contents.m;
3806 /* Temporarily revert mode back. */
3807 adjust_reg_mode (reg, old_mode);
3809 if (reg == i2dest && i2scratch)
3811 /* If we used i2dest as a scratch register with a
3812 different mode, substitute it for the original
3813 i2src while its original mode is temporarily
3814 restored, and then clear i2scratch so that we don't
3815 do it again later. */
3816 propagate_for_debug (i2, i3, reg, i2src);
3818 /* Put back the new mode. */
3819 adjust_reg_mode (reg, new_mode);
3823 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3834 last = undobuf.other_insn;
3838 /* We're dealing with a reg that changed mode but not
3839 meaning, so we want to turn it into a subreg for
3840 the new mode. However, because of REG sharing and
3841 because its mode had already changed, we have to do
3842 it in two steps. First, replace any debug uses of
3843 reg, with its original mode temporarily restored,
3844 with this copy we have created; then, replace the
3845 copy with the SUBREG of the original shared reg,
3846 once again changed to the new mode. */
3847 propagate_for_debug (first, last, reg, tempreg);
3848 adjust_reg_mode (reg, new_mode);
3849 propagate_for_debug (first, last, tempreg,
3850 lowpart_subreg (old_mode, reg, new_mode));
3855 /* If we will be able to accept this, we have made a
3856 change to the destination of I3. This requires us to
3857 do a few adjustments. */
3859 if (changed_i3_dest)
3861 PATTERN (i3) = newpat;
3862 adjust_for_new_dest (i3);
3865 /* We now know that we can do this combination. Merge the insns and
3866 update the status of registers and LOG_LINKS. */
3868 if (undobuf.other_insn)
3872 PATTERN (undobuf.other_insn) = other_pat;
3874 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3875 are still valid. Then add any non-duplicate notes added by
3876 recog_for_combine. */
3877 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3879 next = XEXP (note, 1);
3881 if (REG_NOTE_KIND (note) == REG_UNUSED
3882 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3883 remove_note (undobuf.other_insn, note);
3886 distribute_notes (new_other_notes, undobuf.other_insn,
3887 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3897 /* I3 now uses what used to be its destination and which is now
3898 I2's destination. This requires us to do a few adjustments. */
3899 PATTERN (i3) = newpat;
3900 adjust_for_new_dest (i3);
3902 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3905 However, some later insn might be using I2's dest and have
3906 a LOG_LINK pointing at I3. We must remove this link.
3907 The simplest way to remove the link is to point it at I1,
3908 which we know will be a NOTE. */
3910 /* newi2pat is usually a SET here; however, recog_for_combine might
3911 have added some clobbers. */
3912 if (GET_CODE (newi2pat) == PARALLEL)
3913 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3915 ni2dest = SET_DEST (newi2pat);
3917 for (insn = NEXT_INSN (i3);
3918 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3919 || insn != BB_HEAD (this_basic_block->next_bb));
3920 insn = NEXT_INSN (insn))
3922 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3924 for (link = LOG_LINKS (insn); link;
3925 link = XEXP (link, 1))
3926 if (XEXP (link, 0) == i3)
3927 XEXP (link, 0) = i1;
3935 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3936 rtx i3links, i2links, i1links = 0, i0links = 0;
3940 /* Compute which registers we expect to eliminate. newi2pat may be setting
3941 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3942 same as i3dest, in which case newi2pat may be setting i1dest. */
3943 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3944 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3947 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3948 || (newi2pat && reg_set_p (i1dest, newi2pat))
3951 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3952 || (newi2pat && reg_set_p (i0dest, newi2pat))
3956 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3958 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3959 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3961 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3963 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3965 /* Ensure that we do not have something that should not be shared but
3966 occurs multiple times in the new insns. Check this by first
3967 resetting all the `used' flags and then copying anything is shared. */
3969 reset_used_flags (i3notes);
3970 reset_used_flags (i2notes);
3971 reset_used_flags (i1notes);
3972 reset_used_flags (i0notes);
3973 reset_used_flags (newpat);
3974 reset_used_flags (newi2pat);
3975 if (undobuf.other_insn)
3976 reset_used_flags (PATTERN (undobuf.other_insn));
3978 i3notes = copy_rtx_if_shared (i3notes);
3979 i2notes = copy_rtx_if_shared (i2notes);
3980 i1notes = copy_rtx_if_shared (i1notes);
3981 i0notes = copy_rtx_if_shared (i0notes);
3982 newpat = copy_rtx_if_shared (newpat);
3983 newi2pat = copy_rtx_if_shared (newi2pat);
3984 if (undobuf.other_insn)
3985 reset_used_flags (PATTERN (undobuf.other_insn));
3987 INSN_CODE (i3) = insn_code_number;
3988 PATTERN (i3) = newpat;
3990 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3992 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3994 reset_used_flags (call_usage);
3995 call_usage = copy_rtx (call_usage);
3999 /* I2SRC must still be meaningful at this point. Some splitting
4000 operations can invalidate I2SRC, but those operations do not
4003 replace_rtx (call_usage, i2dest, i2src);
4007 replace_rtx (call_usage, i1dest, i1src);
4009 replace_rtx (call_usage, i0dest, i0src);
4011 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4014 if (undobuf.other_insn)
4015 INSN_CODE (undobuf.other_insn) = other_code_number;
4017 /* We had one special case above where I2 had more than one set and
4018 we replaced a destination of one of those sets with the destination
4019 of I3. In that case, we have to update LOG_LINKS of insns later
4020 in this basic block. Note that this (expensive) case is rare.
4022 Also, in this case, we must pretend that all REG_NOTEs for I2
4023 actually came from I3, so that REG_UNUSED notes from I2 will be
4024 properly handled. */
4026 if (i3_subst_into_i2)
4028 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4029 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4030 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4031 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4032 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4033 && ! find_reg_note (i2, REG_UNUSED,
4034 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4035 for (temp = NEXT_INSN (i2);
4036 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4037 || BB_HEAD (this_basic_block) != temp);
4038 temp = NEXT_INSN (temp))
4039 if (temp != i3 && INSN_P (temp))
4040 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4041 if (XEXP (link, 0) == i2)
4042 XEXP (link, 0) = i3;
4047 while (XEXP (link, 1))
4048 link = XEXP (link, 1);
4049 XEXP (link, 1) = i2notes;
4063 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4064 propagate_for_debug (i2, i3, i2dest, i2src);
4065 INSN_CODE (i2) = i2_code_number;
4066 PATTERN (i2) = newi2pat;
4070 if (MAY_HAVE_DEBUG_INSNS && i2src)
4071 propagate_for_debug (i2, i3, i2dest, i2src);
4072 SET_INSN_DELETED (i2);
4079 if (MAY_HAVE_DEBUG_INSNS)
4080 propagate_for_debug (i1, i3, i1dest, i1src);
4081 SET_INSN_DELETED (i1);
4088 if (MAY_HAVE_DEBUG_INSNS)
4089 propagate_for_debug (i0, i3, i0dest, i0src);
4090 SET_INSN_DELETED (i0);
4093 /* Get death notes for everything that is now used in either I3 or
4094 I2 and used to die in a previous insn. If we built two new
4095 patterns, move from I1 to I2 then I2 to I3 so that we get the
4096 proper movement on registers that I2 modifies. */
4099 from_luid = DF_INSN_LUID (i0);
4101 from_luid = DF_INSN_LUID (i1);
4103 from_luid = DF_INSN_LUID (i2);
4105 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4106 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4108 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4110 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4111 elim_i2, elim_i1, elim_i0);
4113 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4114 elim_i2, elim_i1, elim_i0);
4116 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4117 elim_i2, elim_i1, elim_i0);
4119 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4120 elim_i2, elim_i1, elim_i0);
4122 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4123 elim_i2, elim_i1, elim_i0);
4125 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4126 know these are REG_UNUSED and want them to go to the desired insn,
4127 so we always pass it as i3. */
4129 if (newi2pat && new_i2_notes)
4130 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4134 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4137 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4138 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4139 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4140 in that case, it might delete I2. Similarly for I2 and I1.
4141 Show an additional death due to the REG_DEAD note we make here. If
4142 we discard it in distribute_notes, we will decrement it again. */
4146 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4147 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4149 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4151 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4153 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4154 elim_i2, elim_i1, elim_i0);
4157 if (i2dest_in_i2src)
4159 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4160 if (newi2pat && reg_set_p (i2dest, newi2pat))
4161 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4162 NULL_RTX, NULL_RTX);
4164 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4165 NULL_RTX, NULL_RTX, NULL_RTX);
4168 if (i1dest_in_i1src)
4170 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4171 if (newi2pat && reg_set_p (i1dest, newi2pat))
4172 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4173 NULL_RTX, NULL_RTX);
4175 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4176 NULL_RTX, NULL_RTX, NULL_RTX);
4179 if (i0dest_in_i0src)
4181 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4182 if (newi2pat && reg_set_p (i0dest, newi2pat))
4183 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4184 NULL_RTX, NULL_RTX);
4186 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4187 NULL_RTX, NULL_RTX, NULL_RTX);
4190 distribute_links (i3links);
4191 distribute_links (i2links);
4192 distribute_links (i1links);
4193 distribute_links (i0links);
4198 rtx i2_insn = 0, i2_val = 0, set;
4200 /* The insn that used to set this register doesn't exist, and
4201 this life of the register may not exist either. See if one of
4202 I3's links points to an insn that sets I2DEST. If it does,
4203 that is now the last known value for I2DEST. If we don't update
4204 this and I2 set the register to a value that depended on its old
4205 contents, we will get confused. If this insn is used, thing
4206 will be set correctly in combine_instructions. */
4208 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4209 if ((set = single_set (XEXP (link, 0))) != 0
4210 && rtx_equal_p (i2dest, SET_DEST (set)))
4211 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4213 record_value_for_reg (i2dest, i2_insn, i2_val);
4215 /* If the reg formerly set in I2 died only once and that was in I3,
4216 zero its use count so it won't make `reload' do any work. */
4218 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4219 && ! i2dest_in_i2src)
4221 regno = REGNO (i2dest);
4222 INC_REG_N_SETS (regno, -1);
4226 if (i1 && REG_P (i1dest))
4229 rtx i1_insn = 0, i1_val = 0, set;
4231 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4232 if ((set = single_set (XEXP (link, 0))) != 0
4233 && rtx_equal_p (i1dest, SET_DEST (set)))
4234 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4236 record_value_for_reg (i1dest, i1_insn, i1_val);
4238 regno = REGNO (i1dest);
4239 if (! added_sets_1 && ! i1dest_in_i1src)
4240 INC_REG_N_SETS (regno, -1);
4243 if (i0 && REG_P (i0dest))
4246 rtx i0_insn = 0, i0_val = 0, set;
4248 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4249 if ((set = single_set (XEXP (link, 0))) != 0
4250 && rtx_equal_p (i0dest, SET_DEST (set)))
4251 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4253 record_value_for_reg (i0dest, i0_insn, i0_val);
4255 regno = REGNO (i0dest);
4256 if (! added_sets_0 && ! i0dest_in_i0src)
4257 INC_REG_N_SETS (regno, -1);
4260 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4261 been made to this insn. The order of
4262 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4263 can affect nonzero_bits of newpat */
4265 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4266 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4269 if (undobuf.other_insn != NULL_RTX)
4273 fprintf (dump_file, "modifying other_insn ");
4274 dump_insn_slim (dump_file, undobuf.other_insn);
4276 df_insn_rescan (undobuf.other_insn);
4279 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4283 fprintf (dump_file, "modifying insn i1 ");
4284 dump_insn_slim (dump_file, i0);
4286 df_insn_rescan (i0);
4289 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4293 fprintf (dump_file, "modifying insn i1 ");
4294 dump_insn_slim (dump_file, i1);
4296 df_insn_rescan (i1);
4299 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4303 fprintf (dump_file, "modifying insn i2 ");
4304 dump_insn_slim (dump_file, i2);
4306 df_insn_rescan (i2);
4309 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4313 fprintf (dump_file, "modifying insn i3 ");
4314 dump_insn_slim (dump_file, i3);
4316 df_insn_rescan (i3);
4319 /* Set new_direct_jump_p if a new return or simple jump instruction
4320 has been created. Adjust the CFG accordingly. */
4322 if (returnjump_p (i3) || any_uncondjump_p (i3))
4324 *new_direct_jump_p = 1;
4325 mark_jump_label (PATTERN (i3), i3, 0);
4326 update_cfg_for_uncondjump (i3);
4329 if (undobuf.other_insn != NULL_RTX
4330 && (returnjump_p (undobuf.other_insn)
4331 || any_uncondjump_p (undobuf.other_insn)))
4333 *new_direct_jump_p = 1;
4334 update_cfg_for_uncondjump (undobuf.other_insn);
4337 /* A noop might also need cleaning up of CFG, if it comes from the
4338 simplification of a jump. */
4339 if (GET_CODE (newpat) == SET
4340 && SET_SRC (newpat) == pc_rtx
4341 && SET_DEST (newpat) == pc_rtx)
4343 *new_direct_jump_p = 1;
4344 update_cfg_for_uncondjump (i3);
4347 combine_successes++;
4350 if (added_links_insn
4351 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4352 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4353 return added_links_insn;
4355 return newi2pat ? i2 : i3;
4358 /* Undo all the modifications recorded in undobuf. */
4363 struct undo *undo, *next;
4365 for (undo = undobuf.undos; undo; undo = next)
4371 *undo->where.r = undo->old_contents.r;
4374 *undo->where.i = undo->old_contents.i;
4377 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4383 undo->next = undobuf.frees;
4384 undobuf.frees = undo;
4390 /* We've committed to accepting the changes we made. Move all
4391 of the undos to the free list. */
4396 struct undo *undo, *next;
4398 for (undo = undobuf.undos; undo; undo = next)
4401 undo->next = undobuf.frees;
4402 undobuf.frees = undo;
4407 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4408 where we have an arithmetic expression and return that point. LOC will
4411 try_combine will call this function to see if an insn can be split into
4415 find_split_point (rtx *loc, rtx insn, bool set_src)
4418 enum rtx_code code = GET_CODE (x);
4420 unsigned HOST_WIDE_INT len = 0;
4421 HOST_WIDE_INT pos = 0;
4423 rtx inner = NULL_RTX;
4425 /* First special-case some codes. */
4429 #ifdef INSN_SCHEDULING
4430 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4432 if (MEM_P (SUBREG_REG (x)))
4435 return find_split_point (&SUBREG_REG (x), insn, false);
4439 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4440 using LO_SUM and HIGH. */
4441 if (GET_CODE (XEXP (x, 0)) == CONST
4442 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4444 enum machine_mode address_mode
4445 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4448 gen_rtx_LO_SUM (address_mode,
4449 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4451 return &XEXP (XEXP (x, 0), 0);
4455 /* If we have a PLUS whose second operand is a constant and the
4456 address is not valid, perhaps will can split it up using
4457 the machine-specific way to split large constants. We use
4458 the first pseudo-reg (one of the virtual regs) as a placeholder;
4459 it will not remain in the result. */
4460 if (GET_CODE (XEXP (x, 0)) == PLUS
4461 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4462 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4463 MEM_ADDR_SPACE (x)))
4465 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4466 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4470 /* This should have produced two insns, each of which sets our
4471 placeholder. If the source of the second is a valid address,
4472 we can make put both sources together and make a split point
4476 && NEXT_INSN (seq) != NULL_RTX
4477 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4478 && NONJUMP_INSN_P (seq)
4479 && GET_CODE (PATTERN (seq)) == SET
4480 && SET_DEST (PATTERN (seq)) == reg
4481 && ! reg_mentioned_p (reg,
4482 SET_SRC (PATTERN (seq)))
4483 && NONJUMP_INSN_P (NEXT_INSN (seq))
4484 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4485 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4486 && memory_address_addr_space_p
4487 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4488 MEM_ADDR_SPACE (x)))
4490 rtx src1 = SET_SRC (PATTERN (seq));
4491 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4493 /* Replace the placeholder in SRC2 with SRC1. If we can
4494 find where in SRC2 it was placed, that can become our
4495 split point and we can replace this address with SRC2.
4496 Just try two obvious places. */
4498 src2 = replace_rtx (src2, reg, src1);
4500 if (XEXP (src2, 0) == src1)
4501 split = &XEXP (src2, 0);
4502 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4503 && XEXP (XEXP (src2, 0), 0) == src1)
4504 split = &XEXP (XEXP (src2, 0), 0);
4508 SUBST (XEXP (x, 0), src2);
4513 /* If that didn't work, perhaps the first operand is complex and
4514 needs to be computed separately, so make a split point there.
4515 This will occur on machines that just support REG + CONST
4516 and have a constant moved through some previous computation. */
4518 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4519 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4520 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4521 return &XEXP (XEXP (x, 0), 0);
4524 /* If we have a PLUS whose first operand is complex, try computing it
4525 separately by making a split there. */
4526 if (GET_CODE (XEXP (x, 0)) == PLUS
4527 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4529 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4530 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4531 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4532 return &XEXP (XEXP (x, 0), 0);
4537 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4538 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4539 we need to put the operand into a register. So split at that
4542 if (SET_DEST (x) == cc0_rtx
4543 && GET_CODE (SET_SRC (x)) != COMPARE
4544 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4545 && !OBJECT_P (SET_SRC (x))
4546 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4547 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4548 return &SET_SRC (x);
4551 /* See if we can split SET_SRC as it stands. */
4552 split = find_split_point (&SET_SRC (x), insn, true);
4553 if (split && split != &SET_SRC (x))
4556 /* See if we can split SET_DEST as it stands. */
4557 split = find_split_point (&SET_DEST (x), insn, false);
4558 if (split && split != &SET_DEST (x))
4561 /* See if this is a bitfield assignment with everything constant. If
4562 so, this is an IOR of an AND, so split it into that. */
4563 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4564 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4565 <= HOST_BITS_PER_WIDE_INT)
4566 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4567 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4568 && CONST_INT_P (SET_SRC (x))
4569 && ((INTVAL (XEXP (SET_DEST (x), 1))
4570 + INTVAL (XEXP (SET_DEST (x), 2)))
4571 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4572 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4574 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4575 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4576 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4577 rtx dest = XEXP (SET_DEST (x), 0);
4578 enum machine_mode mode = GET_MODE (dest);
4579 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4582 if (BITS_BIG_ENDIAN)
4583 pos = GET_MODE_BITSIZE (mode) - len - pos;
4585 or_mask = gen_int_mode (src << pos, mode);
4588 simplify_gen_binary (IOR, mode, dest, or_mask));
4591 rtx negmask = gen_int_mode (~(mask << pos), mode);
4593 simplify_gen_binary (IOR, mode,
4594 simplify_gen_binary (AND, mode,
4599 SUBST (SET_DEST (x), dest);
4601 split = find_split_point (&SET_SRC (x), insn, true);
4602 if (split && split != &SET_SRC (x))
4606 /* Otherwise, see if this is an operation that we can split into two.
4607 If so, try to split that. */
4608 code = GET_CODE (SET_SRC (x));
4613 /* If we are AND'ing with a large constant that is only a single
4614 bit and the result is only being used in a context where we
4615 need to know if it is zero or nonzero, replace it with a bit
4616 extraction. This will avoid the large constant, which might
4617 have taken more than one insn to make. If the constant were
4618 not a valid argument to the AND but took only one insn to make,
4619 this is no worse, but if it took more than one insn, it will
4622 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4623 && REG_P (XEXP (SET_SRC (x), 0))
4624 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4625 && REG_P (SET_DEST (x))
4626 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4627 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4628 && XEXP (*split, 0) == SET_DEST (x)
4629 && XEXP (*split, 1) == const0_rtx)
4631 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4632 XEXP (SET_SRC (x), 0),
4633 pos, NULL_RTX, 1, 1, 0, 0);
4634 if (extraction != 0)
4636 SUBST (SET_SRC (x), extraction);
4637 return find_split_point (loc, insn, false);
4643 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4644 is known to be on, this can be converted into a NEG of a shift. */
4645 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4646 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4647 && 1 <= (pos = exact_log2
4648 (nonzero_bits (XEXP (SET_SRC (x), 0),
4649 GET_MODE (XEXP (SET_SRC (x), 0))))))
4651 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4655 gen_rtx_LSHIFTRT (mode,
4656 XEXP (SET_SRC (x), 0),
4659 split = find_split_point (&SET_SRC (x), insn, true);
4660 if (split && split != &SET_SRC (x))
4666 inner = XEXP (SET_SRC (x), 0);
4668 /* We can't optimize if either mode is a partial integer
4669 mode as we don't know how many bits are significant
4671 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4672 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4676 len = GET_MODE_BITSIZE (GET_MODE (inner));
4682 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4683 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4685 inner = XEXP (SET_SRC (x), 0);
4686 len = INTVAL (XEXP (SET_SRC (x), 1));
4687 pos = INTVAL (XEXP (SET_SRC (x), 2));
4689 if (BITS_BIG_ENDIAN)
4690 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4691 unsignedp = (code == ZERO_EXTRACT);
4699 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4701 enum machine_mode mode = GET_MODE (SET_SRC (x));
4703 /* For unsigned, we have a choice of a shift followed by an
4704 AND or two shifts. Use two shifts for field sizes where the
4705 constant might be too large. We assume here that we can
4706 always at least get 8-bit constants in an AND insn, which is
4707 true for every current RISC. */
4709 if (unsignedp && len <= 8)
4714 (mode, gen_lowpart (mode, inner),
4716 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4718 split = find_split_point (&SET_SRC (x), insn, true);
4719 if (split && split != &SET_SRC (x))
4726 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4727 gen_rtx_ASHIFT (mode,
4728 gen_lowpart (mode, inner),
4729 GEN_INT (GET_MODE_BITSIZE (mode)
4731 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4733 split = find_split_point (&SET_SRC (x), insn, true);
4734 if (split && split != &SET_SRC (x))
4739 /* See if this is a simple operation with a constant as the second
4740 operand. It might be that this constant is out of range and hence
4741 could be used as a split point. */
4742 if (BINARY_P (SET_SRC (x))
4743 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4744 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4745 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4746 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4747 return &XEXP (SET_SRC (x), 1);
4749 /* Finally, see if this is a simple operation with its first operand
4750 not in a register. The operation might require this operand in a
4751 register, so return it as a split point. We can always do this
4752 because if the first operand were another operation, we would have
4753 already found it as a split point. */
4754 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4755 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4756 return &XEXP (SET_SRC (x), 0);
4762 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4763 it is better to write this as (not (ior A B)) so we can split it.
4764 Similarly for IOR. */
4765 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4768 gen_rtx_NOT (GET_MODE (x),
4769 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4771 XEXP (XEXP (x, 0), 0),
4772 XEXP (XEXP (x, 1), 0))));
4773 return find_split_point (loc, insn, set_src);
4776 /* Many RISC machines have a large set of logical insns. If the
4777 second operand is a NOT, put it first so we will try to split the
4778 other operand first. */
4779 if (GET_CODE (XEXP (x, 1)) == NOT)
4781 rtx tem = XEXP (x, 0);
4782 SUBST (XEXP (x, 0), XEXP (x, 1));
4783 SUBST (XEXP (x, 1), tem);
4789 /* Canonicalization can produce (minus A (mult B C)), where C is a
4790 constant. It may be better to try splitting (plus (mult B -C) A)
4791 instead if this isn't a multiply by a power of two. */
4792 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4793 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4794 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4796 enum machine_mode mode = GET_MODE (x);
4797 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4798 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4799 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4800 XEXP (XEXP (x, 1), 0),
4801 GEN_INT (other_int)),
4803 return find_split_point (loc, insn, set_src);
4806 /* Split at a multiply-accumulate instruction. However if this is
4807 the SET_SRC, we likely do not have such an instruction and it's
4808 worthless to try this split. */
4809 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4816 /* Otherwise, select our actions depending on our rtx class. */
4817 switch (GET_RTX_CLASS (code))
4819 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4821 split = find_split_point (&XEXP (x, 2), insn, false);
4824 /* ... fall through ... */
4826 case RTX_COMM_ARITH:
4828 case RTX_COMM_COMPARE:
4829 split = find_split_point (&XEXP (x, 1), insn, false);
4832 /* ... fall through ... */
4834 /* Some machines have (and (shift ...) ...) insns. If X is not
4835 an AND, but XEXP (X, 0) is, use it as our split point. */
4836 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4837 return &XEXP (x, 0);
4839 split = find_split_point (&XEXP (x, 0), insn, false);
4845 /* Otherwise, we don't have a split point. */
4850 /* Throughout X, replace FROM with TO, and return the result.
4851 The result is TO if X is FROM;
4852 otherwise the result is X, but its contents may have been modified.
4853 If they were modified, a record was made in undobuf so that
4854 undo_all will (among other things) return X to its original state.
4856 If the number of changes necessary is too much to record to undo,
4857 the excess changes are not made, so the result is invalid.
4858 The changes already made can still be undone.
4859 undobuf.num_undo is incremented for such changes, so by testing that
4860 the caller can tell whether the result is valid.
4862 `n_occurrences' is incremented each time FROM is replaced.
4864 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4866 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4867 by copying if `n_occurrences' is nonzero. */
4870 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4872 enum rtx_code code = GET_CODE (x);
4873 enum machine_mode op0_mode = VOIDmode;
4878 /* Two expressions are equal if they are identical copies of a shared
4879 RTX or if they are both registers with the same register number
4882 #define COMBINE_RTX_EQUAL_P(X,Y) \
4884 || (REG_P (X) && REG_P (Y) \
4885 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4887 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4890 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4893 /* If X and FROM are the same register but different modes, they
4894 will not have been seen as equal above. However, the log links code
4895 will make a LOG_LINKS entry for that case. If we do nothing, we
4896 will try to rerecognize our original insn and, when it succeeds,
4897 we will delete the feeding insn, which is incorrect.
4899 So force this insn not to match in this (rare) case. */
4900 if (! in_dest && code == REG && REG_P (from)
4901 && reg_overlap_mentioned_p (x, from))
4902 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4904 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4905 of which may contain things that can be combined. */
4906 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4909 /* It is possible to have a subexpression appear twice in the insn.
4910 Suppose that FROM is a register that appears within TO.
4911 Then, after that subexpression has been scanned once by `subst',
4912 the second time it is scanned, TO may be found. If we were
4913 to scan TO here, we would find FROM within it and create a
4914 self-referent rtl structure which is completely wrong. */
4915 if (COMBINE_RTX_EQUAL_P (x, to))
4918 /* Parallel asm_operands need special attention because all of the
4919 inputs are shared across the arms. Furthermore, unsharing the
4920 rtl results in recognition failures. Failure to handle this case
4921 specially can result in circular rtl.
4923 Solve this by doing a normal pass across the first entry of the
4924 parallel, and only processing the SET_DESTs of the subsequent
4927 if (code == PARALLEL
4928 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4929 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4931 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4933 /* If this substitution failed, this whole thing fails. */
4934 if (GET_CODE (new_rtx) == CLOBBER
4935 && XEXP (new_rtx, 0) == const0_rtx)
4938 SUBST (XVECEXP (x, 0, 0), new_rtx);
4940 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4942 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4945 && GET_CODE (dest) != CC0
4946 && GET_CODE (dest) != PC)
4948 new_rtx = subst (dest, from, to, 0, unique_copy);
4950 /* If this substitution failed, this whole thing fails. */
4951 if (GET_CODE (new_rtx) == CLOBBER
4952 && XEXP (new_rtx, 0) == const0_rtx)
4955 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4961 len = GET_RTX_LENGTH (code);
4962 fmt = GET_RTX_FORMAT (code);
4964 /* We don't need to process a SET_DEST that is a register, CC0,
4965 or PC, so set up to skip this common case. All other cases
4966 where we want to suppress replacing something inside a
4967 SET_SRC are handled via the IN_DEST operand. */
4969 && (REG_P (SET_DEST (x))
4970 || GET_CODE (SET_DEST (x)) == CC0
4971 || GET_CODE (SET_DEST (x)) == PC))
4974 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4977 op0_mode = GET_MODE (XEXP (x, 0));
4979 for (i = 0; i < len; i++)
4984 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4986 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4988 new_rtx = (unique_copy && n_occurrences
4989 ? copy_rtx (to) : to);
4994 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4997 /* If this substitution failed, this whole thing
4999 if (GET_CODE (new_rtx) == CLOBBER
5000 && XEXP (new_rtx, 0) == const0_rtx)
5004 SUBST (XVECEXP (x, i, j), new_rtx);
5007 else if (fmt[i] == 'e')
5009 /* If this is a register being set, ignore it. */
5010 new_rtx = XEXP (x, i);
5013 && (((code == SUBREG || code == ZERO_EXTRACT)
5015 || code == STRICT_LOW_PART))
5018 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5020 /* In general, don't install a subreg involving two
5021 modes not tieable. It can worsen register
5022 allocation, and can even make invalid reload
5023 insns, since the reg inside may need to be copied
5024 from in the outside mode, and that may be invalid
5025 if it is an fp reg copied in integer mode.
5027 We allow two exceptions to this: It is valid if
5028 it is inside another SUBREG and the mode of that
5029 SUBREG and the mode of the inside of TO is
5030 tieable and it is valid if X is a SET that copies
5033 if (GET_CODE (to) == SUBREG
5034 && ! MODES_TIEABLE_P (GET_MODE (to),
5035 GET_MODE (SUBREG_REG (to)))
5036 && ! (code == SUBREG
5037 && MODES_TIEABLE_P (GET_MODE (x),
5038 GET_MODE (SUBREG_REG (to))))
5040 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5043 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5045 #ifdef CANNOT_CHANGE_MODE_CLASS
5048 && REGNO (to) < FIRST_PSEUDO_REGISTER
5049 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5052 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5055 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5059 /* If we are in a SET_DEST, suppress most cases unless we
5060 have gone inside a MEM, in which case we want to
5061 simplify the address. We assume here that things that
5062 are actually part of the destination have their inner
5063 parts in the first expression. This is true for SUBREG,
5064 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5065 things aside from REG and MEM that should appear in a
5067 new_rtx = subst (XEXP (x, i), from, to,
5069 && (code == SUBREG || code == STRICT_LOW_PART
5070 || code == ZERO_EXTRACT))
5072 && i == 0), unique_copy);
5074 /* If we found that we will have to reject this combination,
5075 indicate that by returning the CLOBBER ourselves, rather than
5076 an expression containing it. This will speed things up as
5077 well as prevent accidents where two CLOBBERs are considered
5078 to be equal, thus producing an incorrect simplification. */
5080 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5083 if (GET_CODE (x) == SUBREG
5084 && (CONST_INT_P (new_rtx)
5085 || GET_CODE (new_rtx) == CONST_DOUBLE))
5087 enum machine_mode mode = GET_MODE (x);
5089 x = simplify_subreg (GET_MODE (x), new_rtx,
5090 GET_MODE (SUBREG_REG (x)),
5093 x = gen_rtx_CLOBBER (mode, const0_rtx);
5095 else if (CONST_INT_P (new_rtx)
5096 && GET_CODE (x) == ZERO_EXTEND)
5098 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5099 new_rtx, GET_MODE (XEXP (x, 0)));
5103 SUBST (XEXP (x, i), new_rtx);
5108 /* Check if we are loading something from the constant pool via float
5109 extension; in this case we would undo compress_float_constant
5110 optimization and degenerate constant load to an immediate value. */
5111 if (GET_CODE (x) == FLOAT_EXTEND
5112 && MEM_P (XEXP (x, 0))
5113 && MEM_READONLY_P (XEXP (x, 0)))
5115 rtx tmp = avoid_constant_pool_reference (x);
5120 /* Try to simplify X. If the simplification changed the code, it is likely
5121 that further simplification will help, so loop, but limit the number
5122 of repetitions that will be performed. */
5124 for (i = 0; i < 4; i++)
5126 /* If X is sufficiently simple, don't bother trying to do anything
5128 if (code != CONST_INT && code != REG && code != CLOBBER)
5129 x = combine_simplify_rtx (x, op0_mode, in_dest);
5131 if (GET_CODE (x) == code)
5134 code = GET_CODE (x);
5136 /* We no longer know the original mode of operand 0 since we
5137 have changed the form of X) */
5138 op0_mode = VOIDmode;
5144 /* Simplify X, a piece of RTL. We just operate on the expression at the
5145 outer level; call `subst' to simplify recursively. Return the new
5148 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5149 if we are inside a SET_DEST. */
5152 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5154 enum rtx_code code = GET_CODE (x);
5155 enum machine_mode mode = GET_MODE (x);
5159 /* If this is a commutative operation, put a constant last and a complex
5160 expression first. We don't need to do this for comparisons here. */
5161 if (COMMUTATIVE_ARITH_P (x)
5162 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5165 SUBST (XEXP (x, 0), XEXP (x, 1));
5166 SUBST (XEXP (x, 1), temp);
5169 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5170 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5171 things. Check for cases where both arms are testing the same
5174 Don't do anything if all operands are very simple. */
5177 && ((!OBJECT_P (XEXP (x, 0))
5178 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5179 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5180 || (!OBJECT_P (XEXP (x, 1))
5181 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5182 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5184 && (!OBJECT_P (XEXP (x, 0))
5185 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5186 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5188 rtx cond, true_rtx, false_rtx;
5190 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5192 /* If everything is a comparison, what we have is highly unlikely
5193 to be simpler, so don't use it. */
5194 && ! (COMPARISON_P (x)
5195 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5197 rtx cop1 = const0_rtx;
5198 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5200 if (cond_code == NE && COMPARISON_P (cond))
5203 /* Simplify the alternative arms; this may collapse the true and
5204 false arms to store-flag values. Be careful to use copy_rtx
5205 here since true_rtx or false_rtx might share RTL with x as a
5206 result of the if_then_else_cond call above. */
5207 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5208 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5210 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5211 is unlikely to be simpler. */
5212 if (general_operand (true_rtx, VOIDmode)
5213 && general_operand (false_rtx, VOIDmode))
5215 enum rtx_code reversed;
5217 /* Restarting if we generate a store-flag expression will cause
5218 us to loop. Just drop through in this case. */
5220 /* If the result values are STORE_FLAG_VALUE and zero, we can
5221 just make the comparison operation. */
5222 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5223 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5225 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5226 && ((reversed = reversed_comparison_code_parts
5227 (cond_code, cond, cop1, NULL))
5229 x = simplify_gen_relational (reversed, mode, VOIDmode,
5232 /* Likewise, we can make the negate of a comparison operation
5233 if the result values are - STORE_FLAG_VALUE and zero. */
5234 else if (CONST_INT_P (true_rtx)
5235 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5236 && false_rtx == const0_rtx)
5237 x = simplify_gen_unary (NEG, mode,
5238 simplify_gen_relational (cond_code,
5242 else if (CONST_INT_P (false_rtx)
5243 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5244 && true_rtx == const0_rtx
5245 && ((reversed = reversed_comparison_code_parts
5246 (cond_code, cond, cop1, NULL))
5248 x = simplify_gen_unary (NEG, mode,
5249 simplify_gen_relational (reversed,
5254 return gen_rtx_IF_THEN_ELSE (mode,
5255 simplify_gen_relational (cond_code,
5260 true_rtx, false_rtx);
5262 code = GET_CODE (x);
5263 op0_mode = VOIDmode;
5268 /* Try to fold this expression in case we have constants that weren't
5271 switch (GET_RTX_CLASS (code))
5274 if (op0_mode == VOIDmode)
5275 op0_mode = GET_MODE (XEXP (x, 0));
5276 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5279 case RTX_COMM_COMPARE:
5281 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5282 if (cmp_mode == VOIDmode)
5284 cmp_mode = GET_MODE (XEXP (x, 1));
5285 if (cmp_mode == VOIDmode)
5286 cmp_mode = op0_mode;
5288 temp = simplify_relational_operation (code, mode, cmp_mode,
5289 XEXP (x, 0), XEXP (x, 1));
5292 case RTX_COMM_ARITH:
5294 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5296 case RTX_BITFIELD_OPS:
5298 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5299 XEXP (x, 1), XEXP (x, 2));
5308 code = GET_CODE (temp);
5309 op0_mode = VOIDmode;
5310 mode = GET_MODE (temp);
5313 /* First see if we can apply the inverse distributive law. */
5314 if (code == PLUS || code == MINUS
5315 || code == AND || code == IOR || code == XOR)
5317 x = apply_distributive_law (x);
5318 code = GET_CODE (x);
5319 op0_mode = VOIDmode;
5322 /* If CODE is an associative operation not otherwise handled, see if we
5323 can associate some operands. This can win if they are constants or
5324 if they are logically related (i.e. (a & b) & a). */
5325 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5326 || code == AND || code == IOR || code == XOR
5327 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5328 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5329 || (flag_associative_math && FLOAT_MODE_P (mode))))
5331 if (GET_CODE (XEXP (x, 0)) == code)
5333 rtx other = XEXP (XEXP (x, 0), 0);
5334 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5335 rtx inner_op1 = XEXP (x, 1);
5338 /* Make sure we pass the constant operand if any as the second
5339 one if this is a commutative operation. */
5340 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5342 rtx tem = inner_op0;
5343 inner_op0 = inner_op1;
5346 inner = simplify_binary_operation (code == MINUS ? PLUS
5347 : code == DIV ? MULT
5349 mode, inner_op0, inner_op1);
5351 /* For commutative operations, try the other pair if that one
5353 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5355 other = XEXP (XEXP (x, 0), 1);
5356 inner = simplify_binary_operation (code, mode,
5357 XEXP (XEXP (x, 0), 0),
5362 return simplify_gen_binary (code, mode, other, inner);
5366 /* A little bit of algebraic simplification here. */
5370 /* Ensure that our address has any ASHIFTs converted to MULT in case
5371 address-recognizing predicates are called later. */
5372 temp = make_compound_operation (XEXP (x, 0), MEM);
5373 SUBST (XEXP (x, 0), temp);
5377 if (op0_mode == VOIDmode)
5378 op0_mode = GET_MODE (SUBREG_REG (x));
5380 /* See if this can be moved to simplify_subreg. */
5381 if (CONSTANT_P (SUBREG_REG (x))
5382 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5383 /* Don't call gen_lowpart if the inner mode
5384 is VOIDmode and we cannot simplify it, as SUBREG without
5385 inner mode is invalid. */
5386 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5387 || gen_lowpart_common (mode, SUBREG_REG (x))))
5388 return gen_lowpart (mode, SUBREG_REG (x));
5390 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5394 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5400 /* Don't change the mode of the MEM if that would change the meaning
5402 if (MEM_P (SUBREG_REG (x))
5403 && (MEM_VOLATILE_P (SUBREG_REG (x))
5404 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5405 return gen_rtx_CLOBBER (mode, const0_rtx);
5407 /* Note that we cannot do any narrowing for non-constants since
5408 we might have been counting on using the fact that some bits were
5409 zero. We now do this in the SET. */
5414 temp = expand_compound_operation (XEXP (x, 0));
5416 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5417 replaced by (lshiftrt X C). This will convert
5418 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5420 if (GET_CODE (temp) == ASHIFTRT
5421 && CONST_INT_P (XEXP (temp, 1))
5422 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5423 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5424 INTVAL (XEXP (temp, 1)));
5426 /* If X has only a single bit that might be nonzero, say, bit I, convert
5427 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5428 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5429 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5430 or a SUBREG of one since we'd be making the expression more
5431 complex if it was just a register. */
5434 && ! (GET_CODE (temp) == SUBREG
5435 && REG_P (SUBREG_REG (temp)))
5436 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5438 rtx temp1 = simplify_shift_const
5439 (NULL_RTX, ASHIFTRT, mode,
5440 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5441 GET_MODE_BITSIZE (mode) - 1 - i),
5442 GET_MODE_BITSIZE (mode) - 1 - i);
5444 /* If all we did was surround TEMP with the two shifts, we
5445 haven't improved anything, so don't use it. Otherwise,
5446 we are better off with TEMP1. */
5447 if (GET_CODE (temp1) != ASHIFTRT
5448 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5449 || XEXP (XEXP (temp1, 0), 0) != temp)
5455 /* We can't handle truncation to a partial integer mode here
5456 because we don't know the real bitsize of the partial
5458 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5461 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5463 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5464 GET_MODE_MASK (mode), 0));
5466 /* We can truncate a constant value and return it. */
5467 if (CONST_INT_P (XEXP (x, 0)))
5468 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5470 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5471 whose value is a comparison can be replaced with a subreg if
5472 STORE_FLAG_VALUE permits. */
5473 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5474 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5475 && (temp = get_last_value (XEXP (x, 0)))
5476 && COMPARISON_P (temp))
5477 return gen_lowpart (mode, XEXP (x, 0));
5481 /* (const (const X)) can become (const X). Do it this way rather than
5482 returning the inner CONST since CONST can be shared with a
5484 if (GET_CODE (XEXP (x, 0)) == CONST)
5485 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5490 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5491 can add in an offset. find_split_point will split this address up
5492 again if it doesn't match. */
5493 if (GET_CODE (XEXP (x, 0)) == HIGH
5494 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5500 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5501 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5502 bit-field and can be replaced by either a sign_extend or a
5503 sign_extract. The `and' may be a zero_extend and the two
5504 <c>, -<c> constants may be reversed. */
5505 if (GET_CODE (XEXP (x, 0)) == XOR
5506 && CONST_INT_P (XEXP (x, 1))
5507 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5508 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5509 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5510 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5511 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5512 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5513 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5514 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5515 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5516 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5517 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5518 == (unsigned int) i + 1))))
5519 return simplify_shift_const
5520 (NULL_RTX, ASHIFTRT, mode,
5521 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5522 XEXP (XEXP (XEXP (x, 0), 0), 0),
5523 GET_MODE_BITSIZE (mode) - (i + 1)),
5524 GET_MODE_BITSIZE (mode) - (i + 1));
5526 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5527 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5528 the bitsize of the mode - 1. This allows simplification of
5529 "a = (b & 8) == 0;" */
5530 if (XEXP (x, 1) == constm1_rtx
5531 && !REG_P (XEXP (x, 0))
5532 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5533 && REG_P (SUBREG_REG (XEXP (x, 0))))
5534 && nonzero_bits (XEXP (x, 0), mode) == 1)
5535 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5536 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5537 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5538 GET_MODE_BITSIZE (mode) - 1),
5539 GET_MODE_BITSIZE (mode) - 1);
5541 /* If we are adding two things that have no bits in common, convert
5542 the addition into an IOR. This will often be further simplified,
5543 for example in cases like ((a & 1) + (a & 2)), which can
5546 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5547 && (nonzero_bits (XEXP (x, 0), mode)
5548 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5550 /* Try to simplify the expression further. */
5551 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5552 temp = combine_simplify_rtx (tor, mode, in_dest);
5554 /* If we could, great. If not, do not go ahead with the IOR
5555 replacement, since PLUS appears in many special purpose
5556 address arithmetic instructions. */
5557 if (GET_CODE (temp) != CLOBBER && temp != tor)
5563 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5564 (and <foo> (const_int pow2-1)) */
5565 if (GET_CODE (XEXP (x, 1)) == AND
5566 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5567 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5568 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5569 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5570 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5574 /* If we have (mult (plus A B) C), apply the distributive law and then
5575 the inverse distributive law to see if things simplify. This
5576 occurs mostly in addresses, often when unrolling loops. */
5578 if (GET_CODE (XEXP (x, 0)) == PLUS)
5580 rtx result = distribute_and_simplify_rtx (x, 0);
5585 /* Try simplify a*(b/c) as (a*b)/c. */
5586 if (FLOAT_MODE_P (mode) && flag_associative_math
5587 && GET_CODE (XEXP (x, 0)) == DIV)
5589 rtx tem = simplify_binary_operation (MULT, mode,
5590 XEXP (XEXP (x, 0), 0),
5593 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5598 /* If this is a divide by a power of two, treat it as a shift if
5599 its first operand is a shift. */
5600 if (CONST_INT_P (XEXP (x, 1))
5601 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5602 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5603 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5604 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5605 || GET_CODE (XEXP (x, 0)) == ROTATE
5606 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5607 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5611 case GT: case GTU: case GE: case GEU:
5612 case LT: case LTU: case LE: case LEU:
5613 case UNEQ: case LTGT:
5614 case UNGT: case UNGE:
5615 case UNLT: case UNLE:
5616 case UNORDERED: case ORDERED:
5617 /* If the first operand is a condition code, we can't do anything
5619 if (GET_CODE (XEXP (x, 0)) == COMPARE
5620 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5621 && ! CC0_P (XEXP (x, 0))))
5623 rtx op0 = XEXP (x, 0);
5624 rtx op1 = XEXP (x, 1);
5625 enum rtx_code new_code;
5627 if (GET_CODE (op0) == COMPARE)
5628 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5630 /* Simplify our comparison, if possible. */
5631 new_code = simplify_comparison (code, &op0, &op1);
5633 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5634 if only the low-order bit is possibly nonzero in X (such as when
5635 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5636 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5637 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5640 Remove any ZERO_EXTRACT we made when thinking this was a
5641 comparison. It may now be simpler to use, e.g., an AND. If a
5642 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5643 the call to make_compound_operation in the SET case. */
5645 if (STORE_FLAG_VALUE == 1
5646 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5647 && op1 == const0_rtx
5648 && mode == GET_MODE (op0)
5649 && nonzero_bits (op0, mode) == 1)
5650 return gen_lowpart (mode,
5651 expand_compound_operation (op0));
5653 else if (STORE_FLAG_VALUE == 1
5654 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5655 && op1 == const0_rtx
5656 && mode == GET_MODE (op0)
5657 && (num_sign_bit_copies (op0, mode)
5658 == GET_MODE_BITSIZE (mode)))
5660 op0 = expand_compound_operation (op0);
5661 return simplify_gen_unary (NEG, mode,
5662 gen_lowpart (mode, op0),
5666 else if (STORE_FLAG_VALUE == 1
5667 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5668 && op1 == const0_rtx
5669 && mode == GET_MODE (op0)
5670 && nonzero_bits (op0, mode) == 1)
5672 op0 = expand_compound_operation (op0);
5673 return simplify_gen_binary (XOR, mode,
5674 gen_lowpart (mode, op0),
5678 else if (STORE_FLAG_VALUE == 1
5679 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5680 && op1 == const0_rtx
5681 && mode == GET_MODE (op0)
5682 && (num_sign_bit_copies (op0, mode)
5683 == GET_MODE_BITSIZE (mode)))
5685 op0 = expand_compound_operation (op0);
5686 return plus_constant (gen_lowpart (mode, op0), 1);
5689 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5691 if (STORE_FLAG_VALUE == -1
5692 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5693 && op1 == const0_rtx
5694 && (num_sign_bit_copies (op0, mode)
5695 == GET_MODE_BITSIZE (mode)))
5696 return gen_lowpart (mode,
5697 expand_compound_operation (op0));
5699 else if (STORE_FLAG_VALUE == -1
5700 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5701 && op1 == const0_rtx
5702 && mode == GET_MODE (op0)
5703 && nonzero_bits (op0, mode) == 1)
5705 op0 = expand_compound_operation (op0);
5706 return simplify_gen_unary (NEG, mode,
5707 gen_lowpart (mode, op0),
5711 else if (STORE_FLAG_VALUE == -1
5712 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5713 && op1 == const0_rtx
5714 && mode == GET_MODE (op0)
5715 && (num_sign_bit_copies (op0, mode)
5716 == GET_MODE_BITSIZE (mode)))
5718 op0 = expand_compound_operation (op0);
5719 return simplify_gen_unary (NOT, mode,
5720 gen_lowpart (mode, op0),
5724 /* If X is 0/1, (eq X 0) is X-1. */
5725 else if (STORE_FLAG_VALUE == -1
5726 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5727 && op1 == const0_rtx
5728 && mode == GET_MODE (op0)
5729 && nonzero_bits (op0, mode) == 1)
5731 op0 = expand_compound_operation (op0);
5732 return plus_constant (gen_lowpart (mode, op0), -1);
5735 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5736 one bit that might be nonzero, we can convert (ne x 0) to
5737 (ashift x c) where C puts the bit in the sign bit. Remove any
5738 AND with STORE_FLAG_VALUE when we are done, since we are only
5739 going to test the sign bit. */
5740 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5741 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5742 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5743 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5744 && op1 == const0_rtx
5745 && mode == GET_MODE (op0)
5746 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5748 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5749 expand_compound_operation (op0),
5750 GET_MODE_BITSIZE (mode) - 1 - i);
5751 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5757 /* If the code changed, return a whole new comparison. */
5758 if (new_code != code)
5759 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5761 /* Otherwise, keep this operation, but maybe change its operands.
5762 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5763 SUBST (XEXP (x, 0), op0);
5764 SUBST (XEXP (x, 1), op1);
5769 return simplify_if_then_else (x);
5775 /* If we are processing SET_DEST, we are done. */
5779 return expand_compound_operation (x);
5782 return simplify_set (x);
5786 return simplify_logical (x);
5793 /* If this is a shift by a constant amount, simplify it. */
5794 if (CONST_INT_P (XEXP (x, 1)))
5795 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5796 INTVAL (XEXP (x, 1)));
5798 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5800 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5802 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5814 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5817 simplify_if_then_else (rtx x)
5819 enum machine_mode mode = GET_MODE (x);
5820 rtx cond = XEXP (x, 0);
5821 rtx true_rtx = XEXP (x, 1);
5822 rtx false_rtx = XEXP (x, 2);
5823 enum rtx_code true_code = GET_CODE (cond);
5824 int comparison_p = COMPARISON_P (cond);
5827 enum rtx_code false_code;
5830 /* Simplify storing of the truth value. */
5831 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5832 return simplify_gen_relational (true_code, mode, VOIDmode,
5833 XEXP (cond, 0), XEXP (cond, 1));
5835 /* Also when the truth value has to be reversed. */
5837 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5838 && (reversed = reversed_comparison (cond, mode)))
5841 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5842 in it is being compared against certain values. Get the true and false
5843 comparisons and see if that says anything about the value of each arm. */
5846 && ((false_code = reversed_comparison_code (cond, NULL))
5848 && REG_P (XEXP (cond, 0)))
5851 rtx from = XEXP (cond, 0);
5852 rtx true_val = XEXP (cond, 1);
5853 rtx false_val = true_val;
5856 /* If FALSE_CODE is EQ, swap the codes and arms. */
5858 if (false_code == EQ)
5860 swapped = 1, true_code = EQ, false_code = NE;
5861 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5864 /* If we are comparing against zero and the expression being tested has
5865 only a single bit that might be nonzero, that is its value when it is
5866 not equal to zero. Similarly if it is known to be -1 or 0. */
5868 if (true_code == EQ && true_val == const0_rtx
5869 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5872 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5874 else if (true_code == EQ && true_val == const0_rtx
5875 && (num_sign_bit_copies (from, GET_MODE (from))
5876 == GET_MODE_BITSIZE (GET_MODE (from))))
5879 false_val = constm1_rtx;
5882 /* Now simplify an arm if we know the value of the register in the
5883 branch and it is used in the arm. Be careful due to the potential
5884 of locally-shared RTL. */
5886 if (reg_mentioned_p (from, true_rtx))
5887 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5889 pc_rtx, pc_rtx, 0, 0);
5890 if (reg_mentioned_p (from, false_rtx))
5891 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5893 pc_rtx, pc_rtx, 0, 0);
5895 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5896 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5898 true_rtx = XEXP (x, 1);
5899 false_rtx = XEXP (x, 2);
5900 true_code = GET_CODE (cond);
5903 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5904 reversed, do so to avoid needing two sets of patterns for
5905 subtract-and-branch insns. Similarly if we have a constant in the true
5906 arm, the false arm is the same as the first operand of the comparison, or
5907 the false arm is more complicated than the true arm. */
5910 && reversed_comparison_code (cond, NULL) != UNKNOWN
5911 && (true_rtx == pc_rtx
5912 || (CONSTANT_P (true_rtx)
5913 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5914 || true_rtx == const0_rtx
5915 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5916 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5917 && !OBJECT_P (false_rtx))
5918 || reg_mentioned_p (true_rtx, false_rtx)
5919 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5921 true_code = reversed_comparison_code (cond, NULL);
5922 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5923 SUBST (XEXP (x, 1), false_rtx);
5924 SUBST (XEXP (x, 2), true_rtx);
5926 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5929 /* It is possible that the conditional has been simplified out. */
5930 true_code = GET_CODE (cond);
5931 comparison_p = COMPARISON_P (cond);
5934 /* If the two arms are identical, we don't need the comparison. */
5936 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5939 /* Convert a == b ? b : a to "a". */
5940 if (true_code == EQ && ! side_effects_p (cond)
5941 && !HONOR_NANS (mode)
5942 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5943 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5945 else if (true_code == NE && ! side_effects_p (cond)
5946 && !HONOR_NANS (mode)
5947 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5948 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5951 /* Look for cases where we have (abs x) or (neg (abs X)). */
5953 if (GET_MODE_CLASS (mode) == MODE_INT
5955 && XEXP (cond, 1) == const0_rtx
5956 && GET_CODE (false_rtx) == NEG
5957 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5958 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5959 && ! side_effects_p (true_rtx))
5964 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5968 simplify_gen_unary (NEG, mode,
5969 simplify_gen_unary (ABS, mode, true_rtx, mode),
5975 /* Look for MIN or MAX. */
5977 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5979 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5980 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5981 && ! side_effects_p (cond))
5986 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5989 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5992 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5995 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6000 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6001 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6002 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6003 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6004 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6005 neither 1 or -1, but it isn't worth checking for. */
6007 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6009 && GET_MODE_CLASS (mode) == MODE_INT
6010 && ! side_effects_p (x))
6012 rtx t = make_compound_operation (true_rtx, SET);
6013 rtx f = make_compound_operation (false_rtx, SET);
6014 rtx cond_op0 = XEXP (cond, 0);
6015 rtx cond_op1 = XEXP (cond, 1);
6016 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6017 enum machine_mode m = mode;
6018 rtx z = 0, c1 = NULL_RTX;
6020 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6021 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6022 || GET_CODE (t) == ASHIFT
6023 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6024 && rtx_equal_p (XEXP (t, 0), f))
6025 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6027 /* If an identity-zero op is commutative, check whether there
6028 would be a match if we swapped the operands. */
6029 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6030 || GET_CODE (t) == XOR)
6031 && rtx_equal_p (XEXP (t, 1), f))
6032 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6033 else if (GET_CODE (t) == SIGN_EXTEND
6034 && (GET_CODE (XEXP (t, 0)) == PLUS
6035 || GET_CODE (XEXP (t, 0)) == MINUS
6036 || GET_CODE (XEXP (t, 0)) == IOR
6037 || GET_CODE (XEXP (t, 0)) == XOR
6038 || GET_CODE (XEXP (t, 0)) == ASHIFT
6039 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6040 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6041 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6042 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6043 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6044 && (num_sign_bit_copies (f, GET_MODE (f))
6046 (GET_MODE_BITSIZE (mode)
6047 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6049 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6050 extend_op = SIGN_EXTEND;
6051 m = GET_MODE (XEXP (t, 0));
6053 else if (GET_CODE (t) == SIGN_EXTEND
6054 && (GET_CODE (XEXP (t, 0)) == PLUS
6055 || GET_CODE (XEXP (t, 0)) == IOR
6056 || GET_CODE (XEXP (t, 0)) == XOR)
6057 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6058 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6059 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6060 && (num_sign_bit_copies (f, GET_MODE (f))
6062 (GET_MODE_BITSIZE (mode)
6063 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6065 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6066 extend_op = SIGN_EXTEND;
6067 m = GET_MODE (XEXP (t, 0));
6069 else if (GET_CODE (t) == ZERO_EXTEND
6070 && (GET_CODE (XEXP (t, 0)) == PLUS
6071 || GET_CODE (XEXP (t, 0)) == MINUS
6072 || GET_CODE (XEXP (t, 0)) == IOR
6073 || GET_CODE (XEXP (t, 0)) == XOR
6074 || GET_CODE (XEXP (t, 0)) == ASHIFT
6075 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6076 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6077 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6078 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6079 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6080 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6081 && ((nonzero_bits (f, GET_MODE (f))
6082 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6085 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6086 extend_op = ZERO_EXTEND;
6087 m = GET_MODE (XEXP (t, 0));
6089 else if (GET_CODE (t) == ZERO_EXTEND
6090 && (GET_CODE (XEXP (t, 0)) == PLUS
6091 || GET_CODE (XEXP (t, 0)) == IOR
6092 || GET_CODE (XEXP (t, 0)) == XOR)
6093 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6094 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6095 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6096 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6097 && ((nonzero_bits (f, GET_MODE (f))
6098 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6101 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6102 extend_op = ZERO_EXTEND;
6103 m = GET_MODE (XEXP (t, 0));
6108 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6109 cond_op0, cond_op1),
6110 pc_rtx, pc_rtx, 0, 0);
6111 temp = simplify_gen_binary (MULT, m, temp,
6112 simplify_gen_binary (MULT, m, c1,
6114 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6115 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6117 if (extend_op != UNKNOWN)
6118 temp = simplify_gen_unary (extend_op, mode, temp, m);
6124 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6125 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6126 negation of a single bit, we can convert this operation to a shift. We
6127 can actually do this more generally, but it doesn't seem worth it. */
6129 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6130 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6131 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6132 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
6133 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6134 == GET_MODE_BITSIZE (mode))
6135 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
6137 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6138 gen_lowpart (mode, XEXP (cond, 0)), i);
6140 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6141 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6142 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6143 && GET_MODE (XEXP (cond, 0)) == mode
6144 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
6145 == nonzero_bits (XEXP (cond, 0), mode)
6146 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6147 return XEXP (cond, 0);
6152 /* Simplify X, a SET expression. Return the new expression. */
6155 simplify_set (rtx x)
6157 rtx src = SET_SRC (x);
6158 rtx dest = SET_DEST (x);
6159 enum machine_mode mode
6160 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6164 /* (set (pc) (return)) gets written as (return). */
6165 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6168 /* Now that we know for sure which bits of SRC we are using, see if we can
6169 simplify the expression for the object knowing that we only need the
6172 if (GET_MODE_CLASS (mode) == MODE_INT
6173 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6175 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
6176 SUBST (SET_SRC (x), src);
6179 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6180 the comparison result and try to simplify it unless we already have used
6181 undobuf.other_insn. */
6182 if ((GET_MODE_CLASS (mode) == MODE_CC
6183 || GET_CODE (src) == COMPARE
6185 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6186 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6187 && COMPARISON_P (*cc_use)
6188 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6190 enum rtx_code old_code = GET_CODE (*cc_use);
6191 enum rtx_code new_code;
6193 int other_changed = 0;
6194 enum machine_mode compare_mode = GET_MODE (dest);
6196 if (GET_CODE (src) == COMPARE)
6197 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6199 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6201 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6204 new_code = old_code;
6205 else if (!CONSTANT_P (tmp))
6207 new_code = GET_CODE (tmp);
6208 op0 = XEXP (tmp, 0);
6209 op1 = XEXP (tmp, 1);
6213 rtx pat = PATTERN (other_insn);
6214 undobuf.other_insn = other_insn;
6215 SUBST (*cc_use, tmp);
6217 /* Attempt to simplify CC user. */
6218 if (GET_CODE (pat) == SET)
6220 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6221 if (new_rtx != NULL_RTX)
6222 SUBST (SET_SRC (pat), new_rtx);
6225 /* Convert X into a no-op move. */
6226 SUBST (SET_DEST (x), pc_rtx);
6227 SUBST (SET_SRC (x), pc_rtx);
6231 /* Simplify our comparison, if possible. */
6232 new_code = simplify_comparison (new_code, &op0, &op1);
6234 #ifdef SELECT_CC_MODE
6235 /* If this machine has CC modes other than CCmode, check to see if we
6236 need to use a different CC mode here. */
6237 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6238 compare_mode = GET_MODE (op0);
6240 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6243 /* If the mode changed, we have to change SET_DEST, the mode in the
6244 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6245 a hard register, just build new versions with the proper mode. If it
6246 is a pseudo, we lose unless it is only time we set the pseudo, in
6247 which case we can safely change its mode. */
6248 if (compare_mode != GET_MODE (dest))
6250 if (can_change_dest_mode (dest, 0, compare_mode))
6252 unsigned int regno = REGNO (dest);
6255 if (regno < FIRST_PSEUDO_REGISTER)
6256 new_dest = gen_rtx_REG (compare_mode, regno);
6259 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6260 new_dest = regno_reg_rtx[regno];
6263 SUBST (SET_DEST (x), new_dest);
6264 SUBST (XEXP (*cc_use, 0), new_dest);
6271 #endif /* SELECT_CC_MODE */
6273 /* If the code changed, we have to build a new comparison in
6274 undobuf.other_insn. */
6275 if (new_code != old_code)
6277 int other_changed_previously = other_changed;
6278 unsigned HOST_WIDE_INT mask;
6279 rtx old_cc_use = *cc_use;
6281 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6285 /* If the only change we made was to change an EQ into an NE or
6286 vice versa, OP0 has only one bit that might be nonzero, and OP1
6287 is zero, check if changing the user of the condition code will
6288 produce a valid insn. If it won't, we can keep the original code
6289 in that insn by surrounding our operation with an XOR. */
6291 if (((old_code == NE && new_code == EQ)
6292 || (old_code == EQ && new_code == NE))
6293 && ! other_changed_previously && op1 == const0_rtx
6294 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6295 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6297 rtx pat = PATTERN (other_insn), note = 0;
6299 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6300 && ! check_asm_operands (pat)))
6302 *cc_use = old_cc_use;
6305 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6306 op0, GEN_INT (mask));
6312 undobuf.other_insn = other_insn;
6314 /* Otherwise, if we didn't previously have a COMPARE in the
6315 correct mode, we need one. */
6316 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6318 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6321 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6323 SUBST (SET_SRC (x), op0);
6326 /* Otherwise, update the COMPARE if needed. */
6327 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6329 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6335 /* Get SET_SRC in a form where we have placed back any
6336 compound expressions. Then do the checks below. */
6337 src = make_compound_operation (src, SET);
6338 SUBST (SET_SRC (x), src);
6341 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6342 and X being a REG or (subreg (reg)), we may be able to convert this to
6343 (set (subreg:m2 x) (op)).
6345 We can always do this if M1 is narrower than M2 because that means that
6346 we only care about the low bits of the result.
6348 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6349 perform a narrower operation than requested since the high-order bits will
6350 be undefined. On machine where it is defined, this transformation is safe
6351 as long as M1 and M2 have the same number of words. */
6353 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6354 && !OBJECT_P (SUBREG_REG (src))
6355 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6357 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6358 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6359 #ifndef WORD_REGISTER_OPERATIONS
6360 && (GET_MODE_SIZE (GET_MODE (src))
6361 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6363 #ifdef CANNOT_CHANGE_MODE_CLASS
6364 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6365 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6366 GET_MODE (SUBREG_REG (src)),
6370 || (GET_CODE (dest) == SUBREG
6371 && REG_P (SUBREG_REG (dest)))))
6373 SUBST (SET_DEST (x),
6374 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6376 SUBST (SET_SRC (x), SUBREG_REG (src));
6378 src = SET_SRC (x), dest = SET_DEST (x);
6382 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6385 && GET_CODE (src) == SUBREG
6386 && subreg_lowpart_p (src)
6387 && (GET_MODE_BITSIZE (GET_MODE (src))
6388 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6390 rtx inner = SUBREG_REG (src);
6391 enum machine_mode inner_mode = GET_MODE (inner);
6393 /* Here we make sure that we don't have a sign bit on. */
6394 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6395 && (nonzero_bits (inner, inner_mode)
6396 < ((unsigned HOST_WIDE_INT) 1
6397 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6399 SUBST (SET_SRC (x), inner);
6405 #ifdef LOAD_EXTEND_OP
6406 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6407 would require a paradoxical subreg. Replace the subreg with a
6408 zero_extend to avoid the reload that would otherwise be required. */
6410 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6411 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6412 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6413 && SUBREG_BYTE (src) == 0
6414 && (GET_MODE_SIZE (GET_MODE (src))
6415 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6416 && MEM_P (SUBREG_REG (src)))
6419 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6420 GET_MODE (src), SUBREG_REG (src)));
6426 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6427 are comparing an item known to be 0 or -1 against 0, use a logical
6428 operation instead. Check for one of the arms being an IOR of the other
6429 arm with some value. We compute three terms to be IOR'ed together. In
6430 practice, at most two will be nonzero. Then we do the IOR's. */
6432 if (GET_CODE (dest) != PC
6433 && GET_CODE (src) == IF_THEN_ELSE
6434 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6435 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6436 && XEXP (XEXP (src, 0), 1) == const0_rtx
6437 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6438 #ifdef HAVE_conditional_move
6439 && ! can_conditionally_move_p (GET_MODE (src))
6441 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6442 GET_MODE (XEXP (XEXP (src, 0), 0)))
6443 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6444 && ! side_effects_p (src))
6446 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6447 ? XEXP (src, 1) : XEXP (src, 2));
6448 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6449 ? XEXP (src, 2) : XEXP (src, 1));
6450 rtx term1 = const0_rtx, term2, term3;
6452 if (GET_CODE (true_rtx) == IOR
6453 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6454 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6455 else if (GET_CODE (true_rtx) == IOR
6456 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6457 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6458 else if (GET_CODE (false_rtx) == IOR
6459 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6460 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6461 else if (GET_CODE (false_rtx) == IOR
6462 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6463 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6465 term2 = simplify_gen_binary (AND, GET_MODE (src),
6466 XEXP (XEXP (src, 0), 0), true_rtx);
6467 term3 = simplify_gen_binary (AND, GET_MODE (src),
6468 simplify_gen_unary (NOT, GET_MODE (src),
6469 XEXP (XEXP (src, 0), 0),
6474 simplify_gen_binary (IOR, GET_MODE (src),
6475 simplify_gen_binary (IOR, GET_MODE (src),
6482 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6483 whole thing fail. */
6484 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6486 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6489 /* Convert this into a field assignment operation, if possible. */
6490 return make_field_assignment (x);
6493 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6497 simplify_logical (rtx x)
6499 enum machine_mode mode = GET_MODE (x);
6500 rtx op0 = XEXP (x, 0);
6501 rtx op1 = XEXP (x, 1);
6503 switch (GET_CODE (x))
6506 /* We can call simplify_and_const_int only if we don't lose
6507 any (sign) bits when converting INTVAL (op1) to
6508 "unsigned HOST_WIDE_INT". */
6509 if (CONST_INT_P (op1)
6510 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6511 || INTVAL (op1) > 0))
6513 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6514 if (GET_CODE (x) != AND)
6521 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6522 apply the distributive law and then the inverse distributive
6523 law to see if things simplify. */
6524 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6526 rtx result = distribute_and_simplify_rtx (x, 0);
6530 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6532 rtx result = distribute_and_simplify_rtx (x, 1);
6539 /* If we have (ior (and A B) C), apply the distributive law and then
6540 the inverse distributive law to see if things simplify. */
6542 if (GET_CODE (op0) == AND)
6544 rtx result = distribute_and_simplify_rtx (x, 0);
6549 if (GET_CODE (op1) == AND)
6551 rtx result = distribute_and_simplify_rtx (x, 1);
6564 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6565 operations" because they can be replaced with two more basic operations.
6566 ZERO_EXTEND is also considered "compound" because it can be replaced with
6567 an AND operation, which is simpler, though only one operation.
6569 The function expand_compound_operation is called with an rtx expression
6570 and will convert it to the appropriate shifts and AND operations,
6571 simplifying at each stage.
6573 The function make_compound_operation is called to convert an expression
6574 consisting of shifts and ANDs into the equivalent compound expression.
6575 It is the inverse of this function, loosely speaking. */
6578 expand_compound_operation (rtx x)
6580 unsigned HOST_WIDE_INT pos = 0, len;
6582 unsigned int modewidth;
6585 switch (GET_CODE (x))
6590 /* We can't necessarily use a const_int for a multiword mode;
6591 it depends on implicitly extending the value.
6592 Since we don't know the right way to extend it,
6593 we can't tell whether the implicit way is right.
6595 Even for a mode that is no wider than a const_int,
6596 we can't win, because we need to sign extend one of its bits through
6597 the rest of it, and we don't know which bit. */
6598 if (CONST_INT_P (XEXP (x, 0)))
6601 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6602 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6603 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6604 reloaded. If not for that, MEM's would very rarely be safe.
6606 Reject MODEs bigger than a word, because we might not be able
6607 to reference a two-register group starting with an arbitrary register
6608 (and currently gen_lowpart might crash for a SUBREG). */
6610 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6613 /* Reject MODEs that aren't scalar integers because turning vector
6614 or complex modes into shifts causes problems. */
6616 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6619 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6620 /* If the inner object has VOIDmode (the only way this can happen
6621 is if it is an ASM_OPERANDS), we can't do anything since we don't
6622 know how much masking to do. */
6631 /* ... fall through ... */
6634 /* If the operand is a CLOBBER, just return it. */
6635 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6638 if (!CONST_INT_P (XEXP (x, 1))
6639 || !CONST_INT_P (XEXP (x, 2))
6640 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6643 /* Reject MODEs that aren't scalar integers because turning vector
6644 or complex modes into shifts causes problems. */
6646 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6649 len = INTVAL (XEXP (x, 1));
6650 pos = INTVAL (XEXP (x, 2));
6652 /* This should stay within the object being extracted, fail otherwise. */
6653 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6656 if (BITS_BIG_ENDIAN)
6657 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6664 /* Convert sign extension to zero extension, if we know that the high
6665 bit is not set, as this is easier to optimize. It will be converted
6666 back to cheaper alternative in make_extraction. */
6667 if (GET_CODE (x) == SIGN_EXTEND
6668 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6669 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6670 & ~(((unsigned HOST_WIDE_INT)
6671 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6675 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6676 rtx temp2 = expand_compound_operation (temp);
6678 /* Make sure this is a profitable operation. */
6679 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6680 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6682 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6683 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6689 /* We can optimize some special cases of ZERO_EXTEND. */
6690 if (GET_CODE (x) == ZERO_EXTEND)
6692 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6693 know that the last value didn't have any inappropriate bits
6695 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6696 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6697 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6698 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6699 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6700 return XEXP (XEXP (x, 0), 0);
6702 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6703 if (GET_CODE (XEXP (x, 0)) == SUBREG
6704 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6705 && subreg_lowpart_p (XEXP (x, 0))
6706 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6707 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6708 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6709 return SUBREG_REG (XEXP (x, 0));
6711 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6712 is a comparison and STORE_FLAG_VALUE permits. This is like
6713 the first case, but it works even when GET_MODE (x) is larger
6714 than HOST_WIDE_INT. */
6715 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6716 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6717 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6719 <= HOST_BITS_PER_WIDE_INT)
6720 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6721 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6722 return XEXP (XEXP (x, 0), 0);
6724 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6725 if (GET_CODE (XEXP (x, 0)) == SUBREG
6726 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6727 && subreg_lowpart_p (XEXP (x, 0))
6728 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6729 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6730 <= HOST_BITS_PER_WIDE_INT)
6731 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6732 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6733 return SUBREG_REG (XEXP (x, 0));
6737 /* If we reach here, we want to return a pair of shifts. The inner
6738 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6739 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6740 logical depending on the value of UNSIGNEDP.
6742 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6743 converted into an AND of a shift.
6745 We must check for the case where the left shift would have a negative
6746 count. This can happen in a case like (x >> 31) & 255 on machines
6747 that can't shift by a constant. On those machines, we would first
6748 combine the shift with the AND to produce a variable-position
6749 extraction. Then the constant of 31 would be substituted in to produce
6750 a such a position. */
6752 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6753 if (modewidth + len >= pos)
6755 enum machine_mode mode = GET_MODE (x);
6756 tem = gen_lowpart (mode, XEXP (x, 0));
6757 if (!tem || GET_CODE (tem) == CLOBBER)
6759 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6760 tem, modewidth - pos - len);
6761 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6762 mode, tem, modewidth - len);
6764 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6765 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6766 simplify_shift_const (NULL_RTX, LSHIFTRT,
6769 ((HOST_WIDE_INT) 1 << len) - 1);
6771 /* Any other cases we can't handle. */
6774 /* If we couldn't do this for some reason, return the original
6776 if (GET_CODE (tem) == CLOBBER)
6782 /* X is a SET which contains an assignment of one object into
6783 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6784 or certain SUBREGS). If possible, convert it into a series of
6787 We half-heartedly support variable positions, but do not at all
6788 support variable lengths. */
6791 expand_field_assignment (const_rtx x)
6794 rtx pos; /* Always counts from low bit. */
6796 rtx mask, cleared, masked;
6797 enum machine_mode compute_mode;
6799 /* Loop until we find something we can't simplify. */
6802 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6803 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6805 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6806 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6807 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6809 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6810 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6812 inner = XEXP (SET_DEST (x), 0);
6813 len = INTVAL (XEXP (SET_DEST (x), 1));
6814 pos = XEXP (SET_DEST (x), 2);
6816 /* A constant position should stay within the width of INNER. */
6817 if (CONST_INT_P (pos)
6818 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6821 if (BITS_BIG_ENDIAN)
6823 if (CONST_INT_P (pos))
6824 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6826 else if (GET_CODE (pos) == MINUS
6827 && CONST_INT_P (XEXP (pos, 1))
6828 && (INTVAL (XEXP (pos, 1))
6829 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6830 /* If position is ADJUST - X, new position is X. */
6831 pos = XEXP (pos, 0);
6833 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6834 GEN_INT (GET_MODE_BITSIZE (
6841 /* A SUBREG between two modes that occupy the same numbers of words
6842 can be done by moving the SUBREG to the source. */
6843 else if (GET_CODE (SET_DEST (x)) == SUBREG
6844 /* We need SUBREGs to compute nonzero_bits properly. */
6845 && nonzero_sign_valid
6846 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6847 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6848 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6849 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6851 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6853 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6860 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6861 inner = SUBREG_REG (inner);
6863 compute_mode = GET_MODE (inner);
6865 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6866 if (! SCALAR_INT_MODE_P (compute_mode))
6868 enum machine_mode imode;
6870 /* Don't do anything for vector or complex integral types. */
6871 if (! FLOAT_MODE_P (compute_mode))
6874 /* Try to find an integral mode to pun with. */
6875 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6876 if (imode == BLKmode)
6879 compute_mode = imode;
6880 inner = gen_lowpart (imode, inner);
6883 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6884 if (len >= HOST_BITS_PER_WIDE_INT)
6887 /* Now compute the equivalent expression. Make a copy of INNER
6888 for the SET_DEST in case it is a MEM into which we will substitute;
6889 we don't want shared RTL in that case. */
6890 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6891 cleared = simplify_gen_binary (AND, compute_mode,
6892 simplify_gen_unary (NOT, compute_mode,
6893 simplify_gen_binary (ASHIFT,
6898 masked = simplify_gen_binary (ASHIFT, compute_mode,
6899 simplify_gen_binary (
6901 gen_lowpart (compute_mode, SET_SRC (x)),
6905 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6906 simplify_gen_binary (IOR, compute_mode,
6913 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6914 it is an RTX that represents a variable starting position; otherwise,
6915 POS is the (constant) starting bit position (counted from the LSB).
6917 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6920 IN_DEST is nonzero if this is a reference in the destination of a
6921 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6922 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6925 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6926 ZERO_EXTRACT should be built even for bits starting at bit 0.
6928 MODE is the desired mode of the result (if IN_DEST == 0).
6930 The result is an RTX for the extraction or NULL_RTX if the target
6934 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6935 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6936 int in_dest, int in_compare)
6938 /* This mode describes the size of the storage area
6939 to fetch the overall value from. Within that, we
6940 ignore the POS lowest bits, etc. */
6941 enum machine_mode is_mode = GET_MODE (inner);
6942 enum machine_mode inner_mode;
6943 enum machine_mode wanted_inner_mode;
6944 enum machine_mode wanted_inner_reg_mode = word_mode;
6945 enum machine_mode pos_mode = word_mode;
6946 enum machine_mode extraction_mode = word_mode;
6947 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6949 rtx orig_pos_rtx = pos_rtx;
6950 HOST_WIDE_INT orig_pos;
6952 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6954 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6955 consider just the QI as the memory to extract from.
6956 The subreg adds or removes high bits; its mode is
6957 irrelevant to the meaning of this extraction,
6958 since POS and LEN count from the lsb. */
6959 if (MEM_P (SUBREG_REG (inner)))
6960 is_mode = GET_MODE (SUBREG_REG (inner));
6961 inner = SUBREG_REG (inner);
6963 else if (GET_CODE (inner) == ASHIFT
6964 && CONST_INT_P (XEXP (inner, 1))
6965 && pos_rtx == 0 && pos == 0
6966 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6968 /* We're extracting the least significant bits of an rtx
6969 (ashift X (const_int C)), where LEN > C. Extract the
6970 least significant (LEN - C) bits of X, giving an rtx
6971 whose mode is MODE, then shift it left C times. */
6972 new_rtx = make_extraction (mode, XEXP (inner, 0),
6973 0, 0, len - INTVAL (XEXP (inner, 1)),
6974 unsignedp, in_dest, in_compare);
6976 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6979 inner_mode = GET_MODE (inner);
6981 if (pos_rtx && CONST_INT_P (pos_rtx))
6982 pos = INTVAL (pos_rtx), pos_rtx = 0;
6984 /* See if this can be done without an extraction. We never can if the
6985 width of the field is not the same as that of some integer mode. For
6986 registers, we can only avoid the extraction if the position is at the
6987 low-order bit and this is either not in the destination or we have the
6988 appropriate STRICT_LOW_PART operation available.
6990 For MEM, we can avoid an extract if the field starts on an appropriate
6991 boundary and we can change the mode of the memory reference. */
6993 if (tmode != BLKmode
6994 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6996 && (inner_mode == tmode
6998 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6999 GET_MODE_BITSIZE (inner_mode))
7000 || reg_truncated_to_mode (tmode, inner))
7003 && have_insn_for (STRICT_LOW_PART, tmode))))
7004 || (MEM_P (inner) && pos_rtx == 0
7006 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7007 : BITS_PER_UNIT)) == 0
7008 /* We can't do this if we are widening INNER_MODE (it
7009 may not be aligned, for one thing). */
7010 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7011 && (inner_mode == tmode
7012 || (! mode_dependent_address_p (XEXP (inner, 0))
7013 && ! MEM_VOLATILE_P (inner))))))
7015 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7016 field. If the original and current mode are the same, we need not
7017 adjust the offset. Otherwise, we do if bytes big endian.
7019 If INNER is not a MEM, get a piece consisting of just the field
7020 of interest (in this case POS % BITS_PER_WORD must be 0). */
7024 HOST_WIDE_INT offset;
7026 /* POS counts from lsb, but make OFFSET count in memory order. */
7027 if (BYTES_BIG_ENDIAN)
7028 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7030 offset = pos / BITS_PER_UNIT;
7032 new_rtx = adjust_address_nv (inner, tmode, offset);
7034 else if (REG_P (inner))
7036 if (tmode != inner_mode)
7038 /* We can't call gen_lowpart in a DEST since we
7039 always want a SUBREG (see below) and it would sometimes
7040 return a new hard register. */
7043 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7045 if (WORDS_BIG_ENDIAN
7046 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7047 final_word = ((GET_MODE_SIZE (inner_mode)
7048 - GET_MODE_SIZE (tmode))
7049 / UNITS_PER_WORD) - final_word;
7051 final_word *= UNITS_PER_WORD;
7052 if (BYTES_BIG_ENDIAN &&
7053 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7054 final_word += (GET_MODE_SIZE (inner_mode)
7055 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7057 /* Avoid creating invalid subregs, for example when
7058 simplifying (x>>32)&255. */
7059 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7062 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7065 new_rtx = gen_lowpart (tmode, inner);
7071 new_rtx = force_to_mode (inner, tmode,
7072 len >= HOST_BITS_PER_WIDE_INT
7073 ? ~(unsigned HOST_WIDE_INT) 0
7074 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7077 /* If this extraction is going into the destination of a SET,
7078 make a STRICT_LOW_PART unless we made a MEM. */
7081 return (MEM_P (new_rtx) ? new_rtx
7082 : (GET_CODE (new_rtx) != SUBREG
7083 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7084 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7089 if (CONST_INT_P (new_rtx)
7090 || GET_CODE (new_rtx) == CONST_DOUBLE)
7091 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7092 mode, new_rtx, tmode);
7094 /* If we know that no extraneous bits are set, and that the high
7095 bit is not set, convert the extraction to the cheaper of
7096 sign and zero extension, that are equivalent in these cases. */
7097 if (flag_expensive_optimizations
7098 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7099 && ((nonzero_bits (new_rtx, tmode)
7100 & ~(((unsigned HOST_WIDE_INT)
7101 GET_MODE_MASK (tmode))
7105 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7106 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7108 /* Prefer ZERO_EXTENSION, since it gives more information to
7110 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7111 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7116 /* Otherwise, sign- or zero-extend unless we already are in the
7119 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7123 /* Unless this is a COMPARE or we have a funny memory reference,
7124 don't do anything with zero-extending field extracts starting at
7125 the low-order bit since they are simple AND operations. */
7126 if (pos_rtx == 0 && pos == 0 && ! in_dest
7127 && ! in_compare && unsignedp)
7130 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7131 if the position is not a constant and the length is not 1. In all
7132 other cases, we would only be going outside our object in cases when
7133 an original shift would have been undefined. */
7135 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7136 || (pos_rtx != 0 && len != 1)))
7139 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7140 and the mode for the result. */
7141 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7143 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7144 pos_mode = mode_for_extraction (EP_insv, 2);
7145 extraction_mode = mode_for_extraction (EP_insv, 3);
7148 if (! in_dest && unsignedp
7149 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7151 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7152 pos_mode = mode_for_extraction (EP_extzv, 3);
7153 extraction_mode = mode_for_extraction (EP_extzv, 0);
7156 if (! in_dest && ! unsignedp
7157 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7159 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7160 pos_mode = mode_for_extraction (EP_extv, 3);
7161 extraction_mode = mode_for_extraction (EP_extv, 0);
7164 /* Never narrow an object, since that might not be safe. */
7166 if (mode != VOIDmode
7167 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7168 extraction_mode = mode;
7170 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7171 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7172 pos_mode = GET_MODE (pos_rtx);
7174 /* If this is not from memory, the desired mode is the preferred mode
7175 for an extraction pattern's first input operand, or word_mode if there
7178 wanted_inner_mode = wanted_inner_reg_mode;
7181 /* Be careful not to go beyond the extracted object and maintain the
7182 natural alignment of the memory. */
7183 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7184 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7185 > GET_MODE_BITSIZE (wanted_inner_mode))
7187 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7188 gcc_assert (wanted_inner_mode != VOIDmode);
7191 /* If we have to change the mode of memory and cannot, the desired mode
7192 is EXTRACTION_MODE. */
7193 if (inner_mode != wanted_inner_mode
7194 && (mode_dependent_address_p (XEXP (inner, 0))
7195 || MEM_VOLATILE_P (inner)
7197 wanted_inner_mode = extraction_mode;
7202 if (BITS_BIG_ENDIAN)
7204 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7205 BITS_BIG_ENDIAN style. If position is constant, compute new
7206 position. Otherwise, build subtraction.
7207 Note that POS is relative to the mode of the original argument.
7208 If it's a MEM we need to recompute POS relative to that.
7209 However, if we're extracting from (or inserting into) a register,
7210 we want to recompute POS relative to wanted_inner_mode. */
7211 int width = (MEM_P (inner)
7212 ? GET_MODE_BITSIZE (is_mode)
7213 : GET_MODE_BITSIZE (wanted_inner_mode));
7216 pos = width - len - pos;
7219 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7220 /* POS may be less than 0 now, but we check for that below.
7221 Note that it can only be less than 0 if !MEM_P (inner). */
7224 /* If INNER has a wider mode, and this is a constant extraction, try to
7225 make it smaller and adjust the byte to point to the byte containing
7227 if (wanted_inner_mode != VOIDmode
7228 && inner_mode != wanted_inner_mode
7230 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7232 && ! mode_dependent_address_p (XEXP (inner, 0))
7233 && ! MEM_VOLATILE_P (inner))
7237 /* The computations below will be correct if the machine is big
7238 endian in both bits and bytes or little endian in bits and bytes.
7239 If it is mixed, we must adjust. */
7241 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7242 adjust OFFSET to compensate. */
7243 if (BYTES_BIG_ENDIAN
7244 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7245 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7247 /* We can now move to the desired byte. */
7248 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7249 * GET_MODE_SIZE (wanted_inner_mode);
7250 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7252 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7253 && is_mode != wanted_inner_mode)
7254 offset = (GET_MODE_SIZE (is_mode)
7255 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7257 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7260 /* If INNER is not memory, get it into the proper mode. If we are changing
7261 its mode, POS must be a constant and smaller than the size of the new
7263 else if (!MEM_P (inner))
7265 /* On the LHS, don't create paradoxical subregs implicitely truncating
7266 the register unless TRULY_NOOP_TRUNCATION. */
7268 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7269 GET_MODE_BITSIZE (wanted_inner_mode)))
7272 if (GET_MODE (inner) != wanted_inner_mode
7274 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7280 inner = force_to_mode (inner, wanted_inner_mode,
7282 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7283 ? ~(unsigned HOST_WIDE_INT) 0
7284 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7289 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7290 have to zero extend. Otherwise, we can just use a SUBREG. */
7292 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7294 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7296 /* If we know that no extraneous bits are set, and that the high
7297 bit is not set, convert extraction to cheaper one - either
7298 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7300 if (flag_expensive_optimizations
7301 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7302 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7303 & ~(((unsigned HOST_WIDE_INT)
7304 GET_MODE_MASK (GET_MODE (pos_rtx)))
7308 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7310 /* Prefer ZERO_EXTENSION, since it gives more information to
7312 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7313 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7318 else if (pos_rtx != 0
7319 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7320 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7322 /* Make POS_RTX unless we already have it and it is correct. If we don't
7323 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7325 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7326 pos_rtx = orig_pos_rtx;
7328 else if (pos_rtx == 0)
7329 pos_rtx = GEN_INT (pos);
7331 /* Make the required operation. See if we can use existing rtx. */
7332 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7333 extraction_mode, inner, GEN_INT (len), pos_rtx);
7335 new_rtx = gen_lowpart (mode, new_rtx);
7340 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7341 with any other operations in X. Return X without that shift if so. */
7344 extract_left_shift (rtx x, int count)
7346 enum rtx_code code = GET_CODE (x);
7347 enum machine_mode mode = GET_MODE (x);
7353 /* This is the shift itself. If it is wide enough, we will return
7354 either the value being shifted if the shift count is equal to
7355 COUNT or a shift for the difference. */
7356 if (CONST_INT_P (XEXP (x, 1))
7357 && INTVAL (XEXP (x, 1)) >= count)
7358 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7359 INTVAL (XEXP (x, 1)) - count);
7363 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7364 return simplify_gen_unary (code, mode, tem, mode);
7368 case PLUS: case IOR: case XOR: case AND:
7369 /* If we can safely shift this constant and we find the inner shift,
7370 make a new operation. */
7371 if (CONST_INT_P (XEXP (x, 1))
7372 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7373 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7374 return simplify_gen_binary (code, mode, tem,
7375 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7386 /* Look at the expression rooted at X. Look for expressions
7387 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7388 Form these expressions.
7390 Return the new rtx, usually just X.
7392 Also, for machines like the VAX that don't have logical shift insns,
7393 try to convert logical to arithmetic shift operations in cases where
7394 they are equivalent. This undoes the canonicalizations to logical
7395 shifts done elsewhere.
7397 We try, as much as possible, to re-use rtl expressions to save memory.
7399 IN_CODE says what kind of expression we are processing. Normally, it is
7400 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7401 being kludges), it is MEM. When processing the arguments of a comparison
7402 or a COMPARE against zero, it is COMPARE. */
7405 make_compound_operation (rtx x, enum rtx_code in_code)
7407 enum rtx_code code = GET_CODE (x);
7408 enum machine_mode mode = GET_MODE (x);
7409 int mode_width = GET_MODE_BITSIZE (mode);
7411 enum rtx_code next_code;
7417 /* Select the code to be used in recursive calls. Once we are inside an
7418 address, we stay there. If we have a comparison, set to COMPARE,
7419 but once inside, go back to our default of SET. */
7421 next_code = (code == MEM ? MEM
7422 : ((code == PLUS || code == MINUS)
7423 && SCALAR_INT_MODE_P (mode)) ? MEM
7424 : ((code == COMPARE || COMPARISON_P (x))
7425 && XEXP (x, 1) == const0_rtx) ? COMPARE
7426 : in_code == COMPARE ? SET : in_code);
7428 /* Process depending on the code of this operation. If NEW is set
7429 nonzero, it will be returned. */
7434 /* Convert shifts by constants into multiplications if inside
7436 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7437 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7438 && INTVAL (XEXP (x, 1)) >= 0)
7440 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7441 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7443 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7444 if (GET_CODE (new_rtx) == NEG)
7446 new_rtx = XEXP (new_rtx, 0);
7449 multval = trunc_int_for_mode (multval, mode);
7450 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7457 lhs = make_compound_operation (lhs, next_code);
7458 rhs = make_compound_operation (rhs, next_code);
7459 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7460 && SCALAR_INT_MODE_P (mode))
7462 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7464 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7466 else if (GET_CODE (lhs) == MULT
7467 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7469 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7470 simplify_gen_unary (NEG, mode,
7473 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7477 SUBST (XEXP (x, 0), lhs);
7478 SUBST (XEXP (x, 1), rhs);
7481 x = gen_lowpart (mode, new_rtx);
7487 lhs = make_compound_operation (lhs, next_code);
7488 rhs = make_compound_operation (rhs, next_code);
7489 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7490 && SCALAR_INT_MODE_P (mode))
7492 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7494 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7496 else if (GET_CODE (rhs) == MULT
7497 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7499 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7500 simplify_gen_unary (NEG, mode,
7503 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7507 SUBST (XEXP (x, 0), lhs);
7508 SUBST (XEXP (x, 1), rhs);
7511 return gen_lowpart (mode, new_rtx);
7514 /* If the second operand is not a constant, we can't do anything
7516 if (!CONST_INT_P (XEXP (x, 1)))
7519 /* If the constant is a power of two minus one and the first operand
7520 is a logical right shift, make an extraction. */
7521 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7522 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7524 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7525 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7526 0, in_code == COMPARE);
7529 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7530 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7531 && subreg_lowpart_p (XEXP (x, 0))
7532 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7533 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7535 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7537 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7538 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7539 0, in_code == COMPARE);
7541 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7542 else if ((GET_CODE (XEXP (x, 0)) == XOR
7543 || GET_CODE (XEXP (x, 0)) == IOR)
7544 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7545 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7546 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7548 /* Apply the distributive law, and then try to make extractions. */
7549 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7550 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7552 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7554 new_rtx = make_compound_operation (new_rtx, in_code);
7557 /* If we are have (and (rotate X C) M) and C is larger than the number
7558 of bits in M, this is an extraction. */
7560 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7561 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7562 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7563 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7565 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7566 new_rtx = make_extraction (mode, new_rtx,
7567 (GET_MODE_BITSIZE (mode)
7568 - INTVAL (XEXP (XEXP (x, 0), 1))),
7569 NULL_RTX, i, 1, 0, in_code == COMPARE);
7572 /* On machines without logical shifts, if the operand of the AND is
7573 a logical shift and our mask turns off all the propagated sign
7574 bits, we can replace the logical shift with an arithmetic shift. */
7575 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7576 && !have_insn_for (LSHIFTRT, mode)
7577 && have_insn_for (ASHIFTRT, mode)
7578 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7579 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7580 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7581 && mode_width <= HOST_BITS_PER_WIDE_INT)
7583 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7585 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7586 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7588 gen_rtx_ASHIFTRT (mode,
7589 make_compound_operation
7590 (XEXP (XEXP (x, 0), 0), next_code),
7591 XEXP (XEXP (x, 0), 1)));
7594 /* If the constant is one less than a power of two, this might be
7595 representable by an extraction even if no shift is present.
7596 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7597 we are in a COMPARE. */
7598 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7599 new_rtx = make_extraction (mode,
7600 make_compound_operation (XEXP (x, 0),
7602 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7604 /* If we are in a comparison and this is an AND with a power of two,
7605 convert this into the appropriate bit extract. */
7606 else if (in_code == COMPARE
7607 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7608 new_rtx = make_extraction (mode,
7609 make_compound_operation (XEXP (x, 0),
7611 i, NULL_RTX, 1, 1, 0, 1);
7616 /* If the sign bit is known to be zero, replace this with an
7617 arithmetic shift. */
7618 if (have_insn_for (ASHIFTRT, mode)
7619 && ! have_insn_for (LSHIFTRT, mode)
7620 && mode_width <= HOST_BITS_PER_WIDE_INT
7621 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7623 new_rtx = gen_rtx_ASHIFTRT (mode,
7624 make_compound_operation (XEXP (x, 0),
7630 /* ... fall through ... */
7636 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7637 this is a SIGN_EXTRACT. */
7638 if (CONST_INT_P (rhs)
7639 && GET_CODE (lhs) == ASHIFT
7640 && CONST_INT_P (XEXP (lhs, 1))
7641 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7642 && INTVAL (rhs) < mode_width)
7644 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7645 new_rtx = make_extraction (mode, new_rtx,
7646 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7647 NULL_RTX, mode_width - INTVAL (rhs),
7648 code == LSHIFTRT, 0, in_code == COMPARE);
7652 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7653 If so, try to merge the shifts into a SIGN_EXTEND. We could
7654 also do this for some cases of SIGN_EXTRACT, but it doesn't
7655 seem worth the effort; the case checked for occurs on Alpha. */
7658 && ! (GET_CODE (lhs) == SUBREG
7659 && (OBJECT_P (SUBREG_REG (lhs))))
7660 && CONST_INT_P (rhs)
7661 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7662 && INTVAL (rhs) < mode_width
7663 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7664 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7665 0, NULL_RTX, mode_width - INTVAL (rhs),
7666 code == LSHIFTRT, 0, in_code == COMPARE);
7671 /* Call ourselves recursively on the inner expression. If we are
7672 narrowing the object and it has a different RTL code from
7673 what it originally did, do this SUBREG as a force_to_mode. */
7675 rtx inner = SUBREG_REG (x), simplified;
7677 tem = make_compound_operation (inner, in_code);
7680 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7684 if (GET_CODE (tem) != GET_CODE (inner)
7685 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7686 && subreg_lowpart_p (x))
7688 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 0);
7690 /* If we have something other than a SUBREG, we might have
7691 done an expansion, so rerun ourselves. */
7692 if (GET_CODE (newer) != SUBREG)
7693 newer = make_compound_operation (newer, in_code);
7695 /* force_to_mode can expand compounds. If it just re-expanded the
7696 compound, use gen_lowpart to convert to the desired mode. */
7697 if (rtx_equal_p (newer, x)
7698 /* Likewise if it re-expanded the compound only partially.
7699 This happens for SUBREG of ZERO_EXTRACT if they extract
7700 the same number of bits. */
7701 || (GET_CODE (newer) == SUBREG
7702 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7703 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7704 && GET_CODE (inner) == AND
7705 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7706 return gen_lowpart (GET_MODE (x), tem);
7722 x = gen_lowpart (mode, new_rtx);
7723 code = GET_CODE (x);
7726 /* Now recursively process each operand of this operation. */
7727 fmt = GET_RTX_FORMAT (code);
7728 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7731 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7732 SUBST (XEXP (x, i), new_rtx);
7734 else if (fmt[i] == 'E')
7735 for (j = 0; j < XVECLEN (x, i); j++)
7737 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7738 SUBST (XVECEXP (x, i, j), new_rtx);
7742 /* If this is a commutative operation, the changes to the operands
7743 may have made it noncanonical. */
7744 if (COMMUTATIVE_ARITH_P (x)
7745 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7748 SUBST (XEXP (x, 0), XEXP (x, 1));
7749 SUBST (XEXP (x, 1), tem);
7755 /* Given M see if it is a value that would select a field of bits
7756 within an item, but not the entire word. Return -1 if not.
7757 Otherwise, return the starting position of the field, where 0 is the
7760 *PLEN is set to the length of the field. */
7763 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7765 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7766 int pos = m ? ctz_hwi (m) : -1;
7770 /* Now shift off the low-order zero bits and see if we have a
7771 power of two minus 1. */
7772 len = exact_log2 ((m >> pos) + 1);
7781 /* If X refers to a register that equals REG in value, replace these
7782 references with REG. */
7784 canon_reg_for_combine (rtx x, rtx reg)
7791 enum rtx_code code = GET_CODE (x);
7792 switch (GET_RTX_CLASS (code))
7795 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7796 if (op0 != XEXP (x, 0))
7797 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7802 case RTX_COMM_ARITH:
7803 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7804 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7805 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7806 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7810 case RTX_COMM_COMPARE:
7811 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7812 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7813 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7814 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7815 GET_MODE (op0), op0, op1);
7819 case RTX_BITFIELD_OPS:
7820 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7821 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7822 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7823 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7824 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7825 GET_MODE (op0), op0, op1, op2);
7830 if (rtx_equal_p (get_last_value (reg), x)
7831 || rtx_equal_p (reg, get_last_value (x)))
7840 fmt = GET_RTX_FORMAT (code);
7842 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7845 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7846 if (op != XEXP (x, i))
7856 else if (fmt[i] == 'E')
7859 for (j = 0; j < XVECLEN (x, i); j++)
7861 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7862 if (op != XVECEXP (x, i, j))
7869 XVECEXP (x, i, j) = op;
7880 /* Return X converted to MODE. If the value is already truncated to
7881 MODE we can just return a subreg even though in the general case we
7882 would need an explicit truncation. */
7885 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7887 if (!CONST_INT_P (x)
7888 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7889 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7890 GET_MODE_BITSIZE (GET_MODE (x)))
7891 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7893 /* Bit-cast X into an integer mode. */
7894 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7895 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7896 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7900 return gen_lowpart (mode, x);
7903 /* See if X can be simplified knowing that we will only refer to it in
7904 MODE and will only refer to those bits that are nonzero in MASK.
7905 If other bits are being computed or if masking operations are done
7906 that select a superset of the bits in MASK, they can sometimes be
7909 Return a possibly simplified expression, but always convert X to
7910 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7912 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7913 are all off in X. This is used when X will be complemented, by either
7914 NOT, NEG, or XOR. */
7917 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7920 enum rtx_code code = GET_CODE (x);
7921 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7922 enum machine_mode op_mode;
7923 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7926 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7927 code below will do the wrong thing since the mode of such an
7928 expression is VOIDmode.
7930 Also do nothing if X is a CLOBBER; this can happen if X was
7931 the return value from a call to gen_lowpart. */
7932 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7935 /* We want to perform the operation is its present mode unless we know
7936 that the operation is valid in MODE, in which case we do the operation
7938 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7939 && have_insn_for (code, mode))
7940 ? mode : GET_MODE (x));
7942 /* It is not valid to do a right-shift in a narrower mode
7943 than the one it came in with. */
7944 if ((code == LSHIFTRT || code == ASHIFTRT)
7945 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7946 op_mode = GET_MODE (x);
7948 /* Truncate MASK to fit OP_MODE. */
7950 mask &= GET_MODE_MASK (op_mode);
7952 /* When we have an arithmetic operation, or a shift whose count we
7953 do not know, we need to assume that all bits up to the highest-order
7954 bit in MASK will be needed. This is how we form such a mask. */
7955 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7956 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7958 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7961 /* Determine what bits of X are guaranteed to be (non)zero. */
7962 nonzero = nonzero_bits (x, mode);
7964 /* If none of the bits in X are needed, return a zero. */
7965 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7968 /* If X is a CONST_INT, return a new one. Do this here since the
7969 test below will fail. */
7970 if (CONST_INT_P (x))
7972 if (SCALAR_INT_MODE_P (mode))
7973 return gen_int_mode (INTVAL (x) & mask, mode);
7976 x = GEN_INT (INTVAL (x) & mask);
7977 return gen_lowpart_common (mode, x);
7981 /* If X is narrower than MODE and we want all the bits in X's mode, just
7982 get X in the proper mode. */
7983 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7984 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7985 return gen_lowpart (mode, x);
7987 /* We can ignore the effect of a SUBREG if it narrows the mode or
7988 if the constant masks to zero all the bits the mode doesn't have. */
7989 if (GET_CODE (x) == SUBREG
7990 && subreg_lowpart_p (x)
7991 && ((GET_MODE_SIZE (GET_MODE (x))
7992 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7994 & GET_MODE_MASK (GET_MODE (x))
7995 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7996 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7998 /* The arithmetic simplifications here only work for scalar integer modes. */
7999 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8000 return gen_lowpart_or_truncate (mode, x);
8005 /* If X is a (clobber (const_int)), return it since we know we are
8006 generating something that won't match. */
8013 x = expand_compound_operation (x);
8014 if (GET_CODE (x) != code)
8015 return force_to_mode (x, mode, mask, next_select);
8019 /* Similarly for a truncate. */
8020 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8023 /* If this is an AND with a constant, convert it into an AND
8024 whose constant is the AND of that constant with MASK. If it
8025 remains an AND of MASK, delete it since it is redundant. */
8027 if (CONST_INT_P (XEXP (x, 1)))
8029 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8030 mask & INTVAL (XEXP (x, 1)));
8032 /* If X is still an AND, see if it is an AND with a mask that
8033 is just some low-order bits. If so, and it is MASK, we don't
8036 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8037 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8041 /* If it remains an AND, try making another AND with the bits
8042 in the mode mask that aren't in MASK turned on. If the
8043 constant in the AND is wide enough, this might make a
8044 cheaper constant. */
8046 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8047 && GET_MODE_MASK (GET_MODE (x)) != mask
8048 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8050 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
8051 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
8052 int width = GET_MODE_BITSIZE (GET_MODE (x));
8055 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8056 number, sign extend it. */
8057 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8058 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8059 cval |= (HOST_WIDE_INT) -1 << width;
8061 y = simplify_gen_binary (AND, GET_MODE (x),
8062 XEXP (x, 0), GEN_INT (cval));
8063 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8064 < rtx_cost (x, SET, optimize_this_for_speed_p))
8074 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8075 low-order bits (as in an alignment operation) and FOO is already
8076 aligned to that boundary, mask C1 to that boundary as well.
8077 This may eliminate that PLUS and, later, the AND. */
8080 unsigned int width = GET_MODE_BITSIZE (mode);
8081 unsigned HOST_WIDE_INT smask = mask;
8083 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8084 number, sign extend it. */
8086 if (width < HOST_BITS_PER_WIDE_INT
8087 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8088 smask |= (HOST_WIDE_INT) -1 << width;
8090 if (CONST_INT_P (XEXP (x, 1))
8091 && exact_log2 (- smask) >= 0
8092 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8093 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8094 return force_to_mode (plus_constant (XEXP (x, 0),
8095 (INTVAL (XEXP (x, 1)) & smask)),
8096 mode, smask, next_select);
8099 /* ... fall through ... */
8102 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8103 most significant bit in MASK since carries from those bits will
8104 affect the bits we are interested in. */
8109 /* If X is (minus C Y) where C's least set bit is larger than any bit
8110 in the mask, then we may replace with (neg Y). */
8111 if (CONST_INT_P (XEXP (x, 0))
8112 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8113 & -INTVAL (XEXP (x, 0))))
8116 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8118 return force_to_mode (x, mode, mask, next_select);
8121 /* Similarly, if C contains every bit in the fuller_mask, then we may
8122 replace with (not Y). */
8123 if (CONST_INT_P (XEXP (x, 0))
8124 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
8125 == INTVAL (XEXP (x, 0))))
8127 x = simplify_gen_unary (NOT, GET_MODE (x),
8128 XEXP (x, 1), GET_MODE (x));
8129 return force_to_mode (x, mode, mask, next_select);
8137 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8138 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8139 operation which may be a bitfield extraction. Ensure that the
8140 constant we form is not wider than the mode of X. */
8142 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8143 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8144 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8145 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8146 && CONST_INT_P (XEXP (x, 1))
8147 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8148 + floor_log2 (INTVAL (XEXP (x, 1))))
8149 < GET_MODE_BITSIZE (GET_MODE (x)))
8150 && (INTVAL (XEXP (x, 1))
8151 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8153 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8154 << INTVAL (XEXP (XEXP (x, 0), 1)));
8155 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8156 XEXP (XEXP (x, 0), 0), temp);
8157 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8158 XEXP (XEXP (x, 0), 1));
8159 return force_to_mode (x, mode, mask, next_select);
8163 /* For most binary operations, just propagate into the operation and
8164 change the mode if we have an operation of that mode. */
8166 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8167 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8169 /* If we ended up truncating both operands, truncate the result of the
8170 operation instead. */
8171 if (GET_CODE (op0) == TRUNCATE
8172 && GET_CODE (op1) == TRUNCATE)
8174 op0 = XEXP (op0, 0);
8175 op1 = XEXP (op1, 0);
8178 op0 = gen_lowpart_or_truncate (op_mode, op0);
8179 op1 = gen_lowpart_or_truncate (op_mode, op1);
8181 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8182 x = simplify_gen_binary (code, op_mode, op0, op1);
8186 /* For left shifts, do the same, but just for the first operand.
8187 However, we cannot do anything with shifts where we cannot
8188 guarantee that the counts are smaller than the size of the mode
8189 because such a count will have a different meaning in a
8192 if (! (CONST_INT_P (XEXP (x, 1))
8193 && INTVAL (XEXP (x, 1)) >= 0
8194 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8195 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8196 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8197 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8200 /* If the shift count is a constant and we can do arithmetic in
8201 the mode of the shift, refine which bits we need. Otherwise, use the
8202 conservative form of the mask. */
8203 if (CONST_INT_P (XEXP (x, 1))
8204 && INTVAL (XEXP (x, 1)) >= 0
8205 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8206 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8207 mask >>= INTVAL (XEXP (x, 1));
8211 op0 = gen_lowpart_or_truncate (op_mode,
8212 force_to_mode (XEXP (x, 0), op_mode,
8213 mask, next_select));
8215 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8216 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8220 /* Here we can only do something if the shift count is a constant,
8221 this shift constant is valid for the host, and we can do arithmetic
8224 if (CONST_INT_P (XEXP (x, 1))
8225 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8226 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8228 rtx inner = XEXP (x, 0);
8229 unsigned HOST_WIDE_INT inner_mask;
8231 /* Select the mask of the bits we need for the shift operand. */
8232 inner_mask = mask << INTVAL (XEXP (x, 1));
8234 /* We can only change the mode of the shift if we can do arithmetic
8235 in the mode of the shift and INNER_MASK is no wider than the
8236 width of X's mode. */
8237 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8238 op_mode = GET_MODE (x);
8240 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8242 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8243 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8246 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8247 shift and AND produces only copies of the sign bit (C2 is one less
8248 than a power of two), we can do this with just a shift. */
8250 if (GET_CODE (x) == LSHIFTRT
8251 && CONST_INT_P (XEXP (x, 1))
8252 /* The shift puts one of the sign bit copies in the least significant
8254 && ((INTVAL (XEXP (x, 1))
8255 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8256 >= GET_MODE_BITSIZE (GET_MODE (x)))
8257 && exact_log2 (mask + 1) >= 0
8258 /* Number of bits left after the shift must be more than the mask
8260 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8261 <= GET_MODE_BITSIZE (GET_MODE (x)))
8262 /* Must be more sign bit copies than the mask needs. */
8263 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8264 >= exact_log2 (mask + 1)))
8265 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8266 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8267 - exact_log2 (mask + 1)));
8272 /* If we are just looking for the sign bit, we don't need this shift at
8273 all, even if it has a variable count. */
8274 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8275 && (mask == ((unsigned HOST_WIDE_INT) 1
8276 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8277 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8279 /* If this is a shift by a constant, get a mask that contains those bits
8280 that are not copies of the sign bit. We then have two cases: If
8281 MASK only includes those bits, this can be a logical shift, which may
8282 allow simplifications. If MASK is a single-bit field not within
8283 those bits, we are requesting a copy of the sign bit and hence can
8284 shift the sign bit to the appropriate location. */
8286 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8287 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8291 /* If the considered data is wider than HOST_WIDE_INT, we can't
8292 represent a mask for all its bits in a single scalar.
8293 But we only care about the lower bits, so calculate these. */
8295 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8297 nonzero = ~(HOST_WIDE_INT) 0;
8299 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8300 is the number of bits a full-width mask would have set.
8301 We need only shift if these are fewer than nonzero can
8302 hold. If not, we must keep all bits set in nonzero. */
8304 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8305 < HOST_BITS_PER_WIDE_INT)
8306 nonzero >>= INTVAL (XEXP (x, 1))
8307 + HOST_BITS_PER_WIDE_INT
8308 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8312 nonzero = GET_MODE_MASK (GET_MODE (x));
8313 nonzero >>= INTVAL (XEXP (x, 1));
8316 if ((mask & ~nonzero) == 0)
8318 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8319 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8320 if (GET_CODE (x) != ASHIFTRT)
8321 return force_to_mode (x, mode, mask, next_select);
8324 else if ((i = exact_log2 (mask)) >= 0)
8326 x = simplify_shift_const
8327 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8328 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8330 if (GET_CODE (x) != ASHIFTRT)
8331 return force_to_mode (x, mode, mask, next_select);
8335 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8336 even if the shift count isn't a constant. */
8338 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8339 XEXP (x, 0), XEXP (x, 1));
8343 /* If this is a zero- or sign-extension operation that just affects bits
8344 we don't care about, remove it. Be sure the call above returned
8345 something that is still a shift. */
8347 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8348 && CONST_INT_P (XEXP (x, 1))
8349 && INTVAL (XEXP (x, 1)) >= 0
8350 && (INTVAL (XEXP (x, 1))
8351 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8352 && GET_CODE (XEXP (x, 0)) == ASHIFT
8353 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8354 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8361 /* If the shift count is constant and we can do computations
8362 in the mode of X, compute where the bits we care about are.
8363 Otherwise, we can't do anything. Don't change the mode of
8364 the shift or propagate MODE into the shift, though. */
8365 if (CONST_INT_P (XEXP (x, 1))
8366 && INTVAL (XEXP (x, 1)) >= 0)
8368 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8369 GET_MODE (x), GEN_INT (mask),
8371 if (temp && CONST_INT_P (temp))
8373 force_to_mode (XEXP (x, 0), GET_MODE (x),
8374 INTVAL (temp), next_select));
8379 /* If we just want the low-order bit, the NEG isn't needed since it
8380 won't change the low-order bit. */
8382 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8384 /* We need any bits less significant than the most significant bit in
8385 MASK since carries from those bits will affect the bits we are
8391 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8392 same as the XOR case above. Ensure that the constant we form is not
8393 wider than the mode of X. */
8395 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8396 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8397 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8398 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8399 < GET_MODE_BITSIZE (GET_MODE (x)))
8400 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8402 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8404 temp = simplify_gen_binary (XOR, GET_MODE (x),
8405 XEXP (XEXP (x, 0), 0), temp);
8406 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8407 temp, XEXP (XEXP (x, 0), 1));
8409 return force_to_mode (x, mode, mask, next_select);
8412 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8413 use the full mask inside the NOT. */
8417 op0 = gen_lowpart_or_truncate (op_mode,
8418 force_to_mode (XEXP (x, 0), mode, mask,
8420 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8421 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8425 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8426 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8427 which is equal to STORE_FLAG_VALUE. */
8428 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8429 && GET_MODE (XEXP (x, 0)) == mode
8430 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8431 && (nonzero_bits (XEXP (x, 0), mode)
8432 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8433 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8438 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8439 written in a narrower mode. We play it safe and do not do so. */
8442 gen_lowpart_or_truncate (GET_MODE (x),
8443 force_to_mode (XEXP (x, 1), mode,
8444 mask, next_select)));
8446 gen_lowpart_or_truncate (GET_MODE (x),
8447 force_to_mode (XEXP (x, 2), mode,
8448 mask, next_select)));
8455 /* Ensure we return a value of the proper mode. */
8456 return gen_lowpart_or_truncate (mode, x);
8459 /* Return nonzero if X is an expression that has one of two values depending on
8460 whether some other value is zero or nonzero. In that case, we return the
8461 value that is being tested, *PTRUE is set to the value if the rtx being
8462 returned has a nonzero value, and *PFALSE is set to the other alternative.
8464 If we return zero, we set *PTRUE and *PFALSE to X. */
8467 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8469 enum machine_mode mode = GET_MODE (x);
8470 enum rtx_code code = GET_CODE (x);
8471 rtx cond0, cond1, true0, true1, false0, false1;
8472 unsigned HOST_WIDE_INT nz;
8474 /* If we are comparing a value against zero, we are done. */
8475 if ((code == NE || code == EQ)
8476 && XEXP (x, 1) == const0_rtx)
8478 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8479 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8483 /* If this is a unary operation whose operand has one of two values, apply
8484 our opcode to compute those values. */
8485 else if (UNARY_P (x)
8486 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8488 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8489 *pfalse = simplify_gen_unary (code, mode, false0,
8490 GET_MODE (XEXP (x, 0)));
8494 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8495 make can't possibly match and would suppress other optimizations. */
8496 else if (code == COMPARE)
8499 /* If this is a binary operation, see if either side has only one of two
8500 values. If either one does or if both do and they are conditional on
8501 the same value, compute the new true and false values. */
8502 else if (BINARY_P (x))
8504 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8505 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8507 if ((cond0 != 0 || cond1 != 0)
8508 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8510 /* If if_then_else_cond returned zero, then true/false are the
8511 same rtl. We must copy one of them to prevent invalid rtl
8514 true0 = copy_rtx (true0);
8515 else if (cond1 == 0)
8516 true1 = copy_rtx (true1);
8518 if (COMPARISON_P (x))
8520 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8522 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8527 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8528 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8531 return cond0 ? cond0 : cond1;
8534 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8535 operands is zero when the other is nonzero, and vice-versa,
8536 and STORE_FLAG_VALUE is 1 or -1. */
8538 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8539 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8541 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8543 rtx op0 = XEXP (XEXP (x, 0), 1);
8544 rtx op1 = XEXP (XEXP (x, 1), 1);
8546 cond0 = XEXP (XEXP (x, 0), 0);
8547 cond1 = XEXP (XEXP (x, 1), 0);
8549 if (COMPARISON_P (cond0)
8550 && COMPARISON_P (cond1)
8551 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8552 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8553 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8554 || ((swap_condition (GET_CODE (cond0))
8555 == reversed_comparison_code (cond1, NULL))
8556 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8557 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8558 && ! side_effects_p (x))
8560 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8561 *pfalse = simplify_gen_binary (MULT, mode,
8563 ? simplify_gen_unary (NEG, mode,
8571 /* Similarly for MULT, AND and UMIN, except that for these the result
8573 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8574 && (code == MULT || code == AND || code == UMIN)
8575 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8577 cond0 = XEXP (XEXP (x, 0), 0);
8578 cond1 = XEXP (XEXP (x, 1), 0);
8580 if (COMPARISON_P (cond0)
8581 && COMPARISON_P (cond1)
8582 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8583 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8584 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8585 || ((swap_condition (GET_CODE (cond0))
8586 == reversed_comparison_code (cond1, NULL))
8587 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8588 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8589 && ! side_effects_p (x))
8591 *ptrue = *pfalse = const0_rtx;
8597 else if (code == IF_THEN_ELSE)
8599 /* If we have IF_THEN_ELSE already, extract the condition and
8600 canonicalize it if it is NE or EQ. */
8601 cond0 = XEXP (x, 0);
8602 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8603 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8604 return XEXP (cond0, 0);
8605 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8607 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8608 return XEXP (cond0, 0);
8614 /* If X is a SUBREG, we can narrow both the true and false values
8615 if the inner expression, if there is a condition. */
8616 else if (code == SUBREG
8617 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8620 true0 = simplify_gen_subreg (mode, true0,
8621 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8622 false0 = simplify_gen_subreg (mode, false0,
8623 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8624 if (true0 && false0)
8632 /* If X is a constant, this isn't special and will cause confusions
8633 if we treat it as such. Likewise if it is equivalent to a constant. */
8634 else if (CONSTANT_P (x)
8635 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8638 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8639 will be least confusing to the rest of the compiler. */
8640 else if (mode == BImode)
8642 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8646 /* If X is known to be either 0 or -1, those are the true and
8647 false values when testing X. */
8648 else if (x == constm1_rtx || x == const0_rtx
8649 || (mode != VOIDmode
8650 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8652 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8656 /* Likewise for 0 or a single bit. */
8657 else if (SCALAR_INT_MODE_P (mode)
8658 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8659 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8661 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8665 /* Otherwise fail; show no condition with true and false values the same. */
8666 *ptrue = *pfalse = x;
8670 /* Return the value of expression X given the fact that condition COND
8671 is known to be true when applied to REG as its first operand and VAL
8672 as its second. X is known to not be shared and so can be modified in
8675 We only handle the simplest cases, and specifically those cases that
8676 arise with IF_THEN_ELSE expressions. */
8679 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8681 enum rtx_code code = GET_CODE (x);
8686 if (side_effects_p (x))
8689 /* If either operand of the condition is a floating point value,
8690 then we have to avoid collapsing an EQ comparison. */
8692 && rtx_equal_p (x, reg)
8693 && ! FLOAT_MODE_P (GET_MODE (x))
8694 && ! FLOAT_MODE_P (GET_MODE (val)))
8697 if (cond == UNEQ && rtx_equal_p (x, reg))
8700 /* If X is (abs REG) and we know something about REG's relationship
8701 with zero, we may be able to simplify this. */
8703 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8706 case GE: case GT: case EQ:
8709 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8711 GET_MODE (XEXP (x, 0)));
8716 /* The only other cases we handle are MIN, MAX, and comparisons if the
8717 operands are the same as REG and VAL. */
8719 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8721 if (rtx_equal_p (XEXP (x, 0), val))
8722 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8724 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8726 if (COMPARISON_P (x))
8728 if (comparison_dominates_p (cond, code))
8729 return const_true_rtx;
8731 code = reversed_comparison_code (x, NULL);
8733 && comparison_dominates_p (cond, code))
8738 else if (code == SMAX || code == SMIN
8739 || code == UMIN || code == UMAX)
8741 int unsignedp = (code == UMIN || code == UMAX);
8743 /* Do not reverse the condition when it is NE or EQ.
8744 This is because we cannot conclude anything about
8745 the value of 'SMAX (x, y)' when x is not equal to y,
8746 but we can when x equals y. */
8747 if ((code == SMAX || code == UMAX)
8748 && ! (cond == EQ || cond == NE))
8749 cond = reverse_condition (cond);
8754 return unsignedp ? x : XEXP (x, 1);
8756 return unsignedp ? x : XEXP (x, 0);
8758 return unsignedp ? XEXP (x, 1) : x;
8760 return unsignedp ? XEXP (x, 0) : x;
8767 else if (code == SUBREG)
8769 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8770 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8772 if (SUBREG_REG (x) != r)
8774 /* We must simplify subreg here, before we lose track of the
8775 original inner_mode. */
8776 new_rtx = simplify_subreg (GET_MODE (x), r,
8777 inner_mode, SUBREG_BYTE (x));
8781 SUBST (SUBREG_REG (x), r);
8786 /* We don't have to handle SIGN_EXTEND here, because even in the
8787 case of replacing something with a modeless CONST_INT, a
8788 CONST_INT is already (supposed to be) a valid sign extension for
8789 its narrower mode, which implies it's already properly
8790 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8791 story is different. */
8792 else if (code == ZERO_EXTEND)
8794 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8795 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8797 if (XEXP (x, 0) != r)
8799 /* We must simplify the zero_extend here, before we lose
8800 track of the original inner_mode. */
8801 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8806 SUBST (XEXP (x, 0), r);
8812 fmt = GET_RTX_FORMAT (code);
8813 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8816 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8817 else if (fmt[i] == 'E')
8818 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8819 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8826 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8827 assignment as a field assignment. */
8830 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8832 if (x == y || rtx_equal_p (x, y))
8835 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8838 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8839 Note that all SUBREGs of MEM are paradoxical; otherwise they
8840 would have been rewritten. */
8841 if (MEM_P (x) && GET_CODE (y) == SUBREG
8842 && MEM_P (SUBREG_REG (y))
8843 && rtx_equal_p (SUBREG_REG (y),
8844 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8847 if (MEM_P (y) && GET_CODE (x) == SUBREG
8848 && MEM_P (SUBREG_REG (x))
8849 && rtx_equal_p (SUBREG_REG (x),
8850 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8853 /* We used to see if get_last_value of X and Y were the same but that's
8854 not correct. In one direction, we'll cause the assignment to have
8855 the wrong destination and in the case, we'll import a register into this
8856 insn that might have already have been dead. So fail if none of the
8857 above cases are true. */
8861 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8862 Return that assignment if so.
8864 We only handle the most common cases. */
8867 make_field_assignment (rtx x)
8869 rtx dest = SET_DEST (x);
8870 rtx src = SET_SRC (x);
8875 unsigned HOST_WIDE_INT len;
8877 enum machine_mode mode;
8879 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8880 a clear of a one-bit field. We will have changed it to
8881 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8884 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8885 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8886 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8887 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8889 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8892 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8896 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8897 && subreg_lowpart_p (XEXP (src, 0))
8898 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8899 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8900 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8901 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8902 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8903 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8905 assign = make_extraction (VOIDmode, dest, 0,
8906 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8909 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8913 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8915 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8916 && XEXP (XEXP (src, 0), 0) == const1_rtx
8917 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8919 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8922 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8926 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8927 SRC is an AND with all bits of that field set, then we can discard
8929 if (GET_CODE (dest) == ZERO_EXTRACT
8930 && CONST_INT_P (XEXP (dest, 1))
8931 && GET_CODE (src) == AND
8932 && CONST_INT_P (XEXP (src, 1)))
8934 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8935 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8936 unsigned HOST_WIDE_INT ze_mask;
8938 if (width >= HOST_BITS_PER_WIDE_INT)
8941 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8943 /* Complete overlap. We can remove the source AND. */
8944 if ((and_mask & ze_mask) == ze_mask)
8945 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8947 /* Partial overlap. We can reduce the source AND. */
8948 if ((and_mask & ze_mask) != and_mask)
8950 mode = GET_MODE (src);
8951 src = gen_rtx_AND (mode, XEXP (src, 0),
8952 gen_int_mode (and_mask & ze_mask, mode));
8953 return gen_rtx_SET (VOIDmode, dest, src);
8957 /* The other case we handle is assignments into a constant-position
8958 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8959 a mask that has all one bits except for a group of zero bits and
8960 OTHER is known to have zeros where C1 has ones, this is such an
8961 assignment. Compute the position and length from C1. Shift OTHER
8962 to the appropriate position, force it to the required mode, and
8963 make the extraction. Check for the AND in both operands. */
8965 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8968 rhs = expand_compound_operation (XEXP (src, 0));
8969 lhs = expand_compound_operation (XEXP (src, 1));
8971 if (GET_CODE (rhs) == AND
8972 && CONST_INT_P (XEXP (rhs, 1))
8973 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8974 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8975 else if (GET_CODE (lhs) == AND
8976 && CONST_INT_P (XEXP (lhs, 1))
8977 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8978 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8982 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8983 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8984 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8985 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8988 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8992 /* The mode to use for the source is the mode of the assignment, or of
8993 what is inside a possible STRICT_LOW_PART. */
8994 mode = (GET_CODE (assign) == STRICT_LOW_PART
8995 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8997 /* Shift OTHER right POS places and make it the source, restricting it
8998 to the proper length and mode. */
9000 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9004 src = force_to_mode (src, mode,
9005 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9006 ? ~(unsigned HOST_WIDE_INT) 0
9007 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9010 /* If SRC is masked by an AND that does not make a difference in
9011 the value being stored, strip it. */
9012 if (GET_CODE (assign) == ZERO_EXTRACT
9013 && CONST_INT_P (XEXP (assign, 1))
9014 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9015 && GET_CODE (src) == AND
9016 && CONST_INT_P (XEXP (src, 1))
9017 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
9018 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
9019 src = XEXP (src, 0);
9021 return gen_rtx_SET (VOIDmode, assign, src);
9024 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9028 apply_distributive_law (rtx x)
9030 enum rtx_code code = GET_CODE (x);
9031 enum rtx_code inner_code;
9032 rtx lhs, rhs, other;
9035 /* Distributivity is not true for floating point as it can change the
9036 value. So we don't do it unless -funsafe-math-optimizations. */
9037 if (FLOAT_MODE_P (GET_MODE (x))
9038 && ! flag_unsafe_math_optimizations)
9041 /* The outer operation can only be one of the following: */
9042 if (code != IOR && code != AND && code != XOR
9043 && code != PLUS && code != MINUS)
9049 /* If either operand is a primitive we can't do anything, so get out
9051 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9054 lhs = expand_compound_operation (lhs);
9055 rhs = expand_compound_operation (rhs);
9056 inner_code = GET_CODE (lhs);
9057 if (inner_code != GET_CODE (rhs))
9060 /* See if the inner and outer operations distribute. */
9067 /* These all distribute except over PLUS. */
9068 if (code == PLUS || code == MINUS)
9073 if (code != PLUS && code != MINUS)
9078 /* This is also a multiply, so it distributes over everything. */
9082 /* Non-paradoxical SUBREGs distributes over all operations,
9083 provided the inner modes and byte offsets are the same, this
9084 is an extraction of a low-order part, we don't convert an fp
9085 operation to int or vice versa, this is not a vector mode,
9086 and we would not be converting a single-word operation into a
9087 multi-word operation. The latter test is not required, but
9088 it prevents generating unneeded multi-word operations. Some
9089 of the previous tests are redundant given the latter test,
9090 but are retained because they are required for correctness.
9092 We produce the result slightly differently in this case. */
9094 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9095 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9096 || ! subreg_lowpart_p (lhs)
9097 || (GET_MODE_CLASS (GET_MODE (lhs))
9098 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9099 || (GET_MODE_SIZE (GET_MODE (lhs))
9100 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9101 || VECTOR_MODE_P (GET_MODE (lhs))
9102 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9103 /* Result might need to be truncated. Don't change mode if
9104 explicit truncation is needed. */
9105 || !TRULY_NOOP_TRUNCATION
9106 (GET_MODE_BITSIZE (GET_MODE (x)),
9107 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9110 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9111 SUBREG_REG (lhs), SUBREG_REG (rhs));
9112 return gen_lowpart (GET_MODE (x), tem);
9118 /* Set LHS and RHS to the inner operands (A and B in the example
9119 above) and set OTHER to the common operand (C in the example).
9120 There is only one way to do this unless the inner operation is
9122 if (COMMUTATIVE_ARITH_P (lhs)
9123 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9124 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9125 else if (COMMUTATIVE_ARITH_P (lhs)
9126 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9127 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9128 else if (COMMUTATIVE_ARITH_P (lhs)
9129 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9130 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9131 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9132 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9136 /* Form the new inner operation, seeing if it simplifies first. */
9137 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9139 /* There is one exception to the general way of distributing:
9140 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9141 if (code == XOR && inner_code == IOR)
9144 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9147 /* We may be able to continuing distributing the result, so call
9148 ourselves recursively on the inner operation before forming the
9149 outer operation, which we return. */
9150 return simplify_gen_binary (inner_code, GET_MODE (x),
9151 apply_distributive_law (tem), other);
9154 /* See if X is of the form (* (+ A B) C), and if so convert to
9155 (+ (* A C) (* B C)) and try to simplify.
9157 Most of the time, this results in no change. However, if some of
9158 the operands are the same or inverses of each other, simplifications
9161 For example, (and (ior A B) (not B)) can occur as the result of
9162 expanding a bit field assignment. When we apply the distributive
9163 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9164 which then simplifies to (and (A (not B))).
9166 Note that no checks happen on the validity of applying the inverse
9167 distributive law. This is pointless since we can do it in the
9168 few places where this routine is called.
9170 N is the index of the term that is decomposed (the arithmetic operation,
9171 i.e. (+ A B) in the first example above). !N is the index of the term that
9172 is distributed, i.e. of C in the first example above. */
9174 distribute_and_simplify_rtx (rtx x, int n)
9176 enum machine_mode mode;
9177 enum rtx_code outer_code, inner_code;
9178 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9180 /* Distributivity is not true for floating point as it can change the
9181 value. So we don't do it unless -funsafe-math-optimizations. */
9182 if (FLOAT_MODE_P (GET_MODE (x))
9183 && ! flag_unsafe_math_optimizations)
9186 decomposed = XEXP (x, n);
9187 if (!ARITHMETIC_P (decomposed))
9190 mode = GET_MODE (x);
9191 outer_code = GET_CODE (x);
9192 distributed = XEXP (x, !n);
9194 inner_code = GET_CODE (decomposed);
9195 inner_op0 = XEXP (decomposed, 0);
9196 inner_op1 = XEXP (decomposed, 1);
9198 /* Special case (and (xor B C) (not A)), which is equivalent to
9199 (xor (ior A B) (ior A C)) */
9200 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9202 distributed = XEXP (distributed, 0);
9208 /* Distribute the second term. */
9209 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9210 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9214 /* Distribute the first term. */
9215 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9216 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9219 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9221 if (GET_CODE (tmp) != outer_code
9222 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9223 < rtx_cost (x, SET, optimize_this_for_speed_p))
9229 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9230 in MODE. Return an equivalent form, if different from (and VAROP
9231 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9234 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9235 unsigned HOST_WIDE_INT constop)
9237 unsigned HOST_WIDE_INT nonzero;
9238 unsigned HOST_WIDE_INT orig_constop;
9243 orig_constop = constop;
9244 if (GET_CODE (varop) == CLOBBER)
9247 /* Simplify VAROP knowing that we will be only looking at some of the
9250 Note by passing in CONSTOP, we guarantee that the bits not set in
9251 CONSTOP are not significant and will never be examined. We must
9252 ensure that is the case by explicitly masking out those bits
9253 before returning. */
9254 varop = force_to_mode (varop, mode, constop, 0);
9256 /* If VAROP is a CLOBBER, we will fail so return it. */
9257 if (GET_CODE (varop) == CLOBBER)
9260 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9261 to VAROP and return the new constant. */
9262 if (CONST_INT_P (varop))
9263 return gen_int_mode (INTVAL (varop) & constop, mode);
9265 /* See what bits may be nonzero in VAROP. Unlike the general case of
9266 a call to nonzero_bits, here we don't care about bits outside
9269 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9271 /* Turn off all bits in the constant that are known to already be zero.
9272 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9273 which is tested below. */
9277 /* If we don't have any bits left, return zero. */
9281 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9282 a power of two, we can replace this with an ASHIFT. */
9283 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9284 && (i = exact_log2 (constop)) >= 0)
9285 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9287 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9288 or XOR, then try to apply the distributive law. This may eliminate
9289 operations if either branch can be simplified because of the AND.
9290 It may also make some cases more complex, but those cases probably
9291 won't match a pattern either with or without this. */
9293 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9297 apply_distributive_law
9298 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9299 simplify_and_const_int (NULL_RTX,
9303 simplify_and_const_int (NULL_RTX,
9308 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9309 the AND and see if one of the operands simplifies to zero. If so, we
9310 may eliminate it. */
9312 if (GET_CODE (varop) == PLUS
9313 && exact_log2 (constop + 1) >= 0)
9317 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9318 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9319 if (o0 == const0_rtx)
9321 if (o1 == const0_rtx)
9325 /* Make a SUBREG if necessary. If we can't make it, fail. */
9326 varop = gen_lowpart (mode, varop);
9327 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9330 /* If we are only masking insignificant bits, return VAROP. */
9331 if (constop == nonzero)
9334 if (varop == orig_varop && constop == orig_constop)
9337 /* Otherwise, return an AND. */
9338 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9342 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9345 Return an equivalent form, if different from X. Otherwise, return X. If
9346 X is zero, we are to always construct the equivalent form. */
9349 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9350 unsigned HOST_WIDE_INT constop)
9352 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9357 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9358 gen_int_mode (constop, mode));
9359 if (GET_MODE (x) != mode)
9360 x = gen_lowpart (mode, x);
9364 /* Given a REG, X, compute which bits in X can be nonzero.
9365 We don't care about bits outside of those defined in MODE.
9367 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9368 a shift, AND, or zero_extract, we can do better. */
9371 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9372 const_rtx known_x ATTRIBUTE_UNUSED,
9373 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9374 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9375 unsigned HOST_WIDE_INT *nonzero)
9380 /* If X is a register whose nonzero bits value is current, use it.
9381 Otherwise, if X is a register whose value we can find, use that
9382 value. Otherwise, use the previously-computed global nonzero bits
9383 for this register. */
9385 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9386 if (rsp->last_set_value != 0
9387 && (rsp->last_set_mode == mode
9388 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9389 && GET_MODE_CLASS (mode) == MODE_INT))
9390 && ((rsp->last_set_label >= label_tick_ebb_start
9391 && rsp->last_set_label < label_tick)
9392 || (rsp->last_set_label == label_tick
9393 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9394 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9395 && REG_N_SETS (REGNO (x)) == 1
9397 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9399 *nonzero &= rsp->last_set_nonzero_bits;
9403 tem = get_last_value (x);
9407 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9408 /* If X is narrower than MODE and TEM is a non-negative
9409 constant that would appear negative in the mode of X,
9410 sign-extend it for use in reg_nonzero_bits because some
9411 machines (maybe most) will actually do the sign-extension
9412 and this is the conservative approach.
9414 ??? For 2.5, try to tighten up the MD files in this regard
9415 instead of this kludge. */
9417 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9418 && CONST_INT_P (tem)
9420 && 0 != (INTVAL (tem)
9421 & ((HOST_WIDE_INT) 1
9422 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9423 tem = GEN_INT (INTVAL (tem)
9424 | ((HOST_WIDE_INT) (-1)
9425 << GET_MODE_BITSIZE (GET_MODE (x))));
9429 else if (nonzero_sign_valid && rsp->nonzero_bits)
9431 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9433 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9434 /* We don't know anything about the upper bits. */
9435 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9442 /* Return the number of bits at the high-order end of X that are known to
9443 be equal to the sign bit. X will be used in mode MODE; if MODE is
9444 VOIDmode, X will be used in its own mode. The returned value will always
9445 be between 1 and the number of bits in MODE. */
9448 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9449 const_rtx known_x ATTRIBUTE_UNUSED,
9450 enum machine_mode known_mode
9452 unsigned int known_ret ATTRIBUTE_UNUSED,
9453 unsigned int *result)
9458 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9459 if (rsp->last_set_value != 0
9460 && rsp->last_set_mode == mode
9461 && ((rsp->last_set_label >= label_tick_ebb_start
9462 && rsp->last_set_label < label_tick)
9463 || (rsp->last_set_label == label_tick
9464 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9465 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9466 && REG_N_SETS (REGNO (x)) == 1
9468 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9470 *result = rsp->last_set_sign_bit_copies;
9474 tem = get_last_value (x);
9478 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9479 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9480 *result = rsp->sign_bit_copies;
9485 /* Return the number of "extended" bits there are in X, when interpreted
9486 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9487 unsigned quantities, this is the number of high-order zero bits.
9488 For signed quantities, this is the number of copies of the sign bit
9489 minus 1. In both case, this function returns the number of "spare"
9490 bits. For example, if two quantities for which this function returns
9491 at least 1 are added, the addition is known not to overflow.
9493 This function will always return 0 unless called during combine, which
9494 implies that it must be called from a define_split. */
9497 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9499 if (nonzero_sign_valid == 0)
9503 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9504 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9505 - floor_log2 (nonzero_bits (x, mode)))
9507 : num_sign_bit_copies (x, mode) - 1);
9510 /* This function is called from `simplify_shift_const' to merge two
9511 outer operations. Specifically, we have already found that we need
9512 to perform operation *POP0 with constant *PCONST0 at the outermost
9513 position. We would now like to also perform OP1 with constant CONST1
9514 (with *POP0 being done last).
9516 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9517 the resulting operation. *PCOMP_P is set to 1 if we would need to
9518 complement the innermost operand, otherwise it is unchanged.
9520 MODE is the mode in which the operation will be done. No bits outside
9521 the width of this mode matter. It is assumed that the width of this mode
9522 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9524 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9525 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9526 result is simply *PCONST0.
9528 If the resulting operation cannot be expressed as one operation, we
9529 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9532 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9534 enum rtx_code op0 = *pop0;
9535 HOST_WIDE_INT const0 = *pconst0;
9537 const0 &= GET_MODE_MASK (mode);
9538 const1 &= GET_MODE_MASK (mode);
9540 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9544 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9547 if (op1 == UNKNOWN || op0 == SET)
9550 else if (op0 == UNKNOWN)
9551 op0 = op1, const0 = const1;
9553 else if (op0 == op1)
9577 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9578 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9581 /* If the two constants aren't the same, we can't do anything. The
9582 remaining six cases can all be done. */
9583 else if (const0 != const1)
9591 /* (a & b) | b == b */
9593 else /* op1 == XOR */
9594 /* (a ^ b) | b == a | b */
9600 /* (a & b) ^ b == (~a) & b */
9601 op0 = AND, *pcomp_p = 1;
9602 else /* op1 == IOR */
9603 /* (a | b) ^ b == a & ~b */
9604 op0 = AND, const0 = ~const0;
9609 /* (a | b) & b == b */
9611 else /* op1 == XOR */
9612 /* (a ^ b) & b) == (~a) & b */
9619 /* Check for NO-OP cases. */
9620 const0 &= GET_MODE_MASK (mode);
9622 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9624 else if (const0 == 0 && op0 == AND)
9626 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9632 /* ??? Slightly redundant with the above mask, but not entirely.
9633 Moving this above means we'd have to sign-extend the mode mask
9634 for the final test. */
9635 if (op0 != UNKNOWN && op0 != NEG)
9636 *pconst0 = trunc_int_for_mode (const0, mode);
9641 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9642 the shift in. The original shift operation CODE is performed on OP in
9643 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9644 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9645 result of the shift is subject to operation OUTER_CODE with operand
9648 static enum machine_mode
9649 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9650 enum machine_mode orig_mode, enum machine_mode mode,
9651 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9653 if (orig_mode == mode)
9655 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9657 /* In general we can't perform in wider mode for right shift and rotate. */
9661 /* We can still widen if the bits brought in from the left are identical
9662 to the sign bit of ORIG_MODE. */
9663 if (num_sign_bit_copies (op, mode)
9664 > (unsigned) (GET_MODE_BITSIZE (mode)
9665 - GET_MODE_BITSIZE (orig_mode)))
9670 /* Similarly here but with zero bits. */
9671 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9672 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9675 /* We can also widen if the bits brought in will be masked off. This
9676 operation is performed in ORIG_MODE. */
9677 if (outer_code == AND)
9679 int care_bits = low_bitmask_len (orig_mode, outer_const);
9682 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9698 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9699 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9700 simplify it. Otherwise, return a simplified value.
9702 The shift is normally computed in the widest mode we find in VAROP, as
9703 long as it isn't a different number of words than RESULT_MODE. Exceptions
9704 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9707 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9708 rtx varop, int orig_count)
9710 enum rtx_code orig_code = code;
9711 rtx orig_varop = varop;
9713 enum machine_mode mode = result_mode;
9714 enum machine_mode shift_mode, tmode;
9715 unsigned int mode_words
9716 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9717 /* We form (outer_op (code varop count) (outer_const)). */
9718 enum rtx_code outer_op = UNKNOWN;
9719 HOST_WIDE_INT outer_const = 0;
9720 int complement_p = 0;
9723 /* Make sure and truncate the "natural" shift on the way in. We don't
9724 want to do this inside the loop as it makes it more difficult to
9726 if (SHIFT_COUNT_TRUNCATED)
9727 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9729 /* If we were given an invalid count, don't do anything except exactly
9730 what was requested. */
9732 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9737 /* Unless one of the branches of the `if' in this loop does a `continue',
9738 we will `break' the loop after the `if'. */
9742 /* If we have an operand of (clobber (const_int 0)), fail. */
9743 if (GET_CODE (varop) == CLOBBER)
9746 /* Convert ROTATERT to ROTATE. */
9747 if (code == ROTATERT)
9749 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9751 if (VECTOR_MODE_P (result_mode))
9752 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9754 count = bitsize - count;
9757 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9758 mode, outer_op, outer_const);
9760 /* Handle cases where the count is greater than the size of the mode
9761 minus 1. For ASHIFT, use the size minus one as the count (this can
9762 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9763 take the count modulo the size. For other shifts, the result is
9766 Since these shifts are being produced by the compiler by combining
9767 multiple operations, each of which are defined, we know what the
9768 result is supposed to be. */
9770 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9772 if (code == ASHIFTRT)
9773 count = GET_MODE_BITSIZE (shift_mode) - 1;
9774 else if (code == ROTATE || code == ROTATERT)
9775 count %= GET_MODE_BITSIZE (shift_mode);
9778 /* We can't simply return zero because there may be an
9786 /* If we discovered we had to complement VAROP, leave. Making a NOT
9787 here would cause an infinite loop. */
9791 /* An arithmetic right shift of a quantity known to be -1 or 0
9793 if (code == ASHIFTRT
9794 && (num_sign_bit_copies (varop, shift_mode)
9795 == GET_MODE_BITSIZE (shift_mode)))
9801 /* If we are doing an arithmetic right shift and discarding all but
9802 the sign bit copies, this is equivalent to doing a shift by the
9803 bitsize minus one. Convert it into that shift because it will often
9804 allow other simplifications. */
9806 if (code == ASHIFTRT
9807 && (count + num_sign_bit_copies (varop, shift_mode)
9808 >= GET_MODE_BITSIZE (shift_mode)))
9809 count = GET_MODE_BITSIZE (shift_mode) - 1;
9811 /* We simplify the tests below and elsewhere by converting
9812 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9813 `make_compound_operation' will convert it to an ASHIFTRT for
9814 those machines (such as VAX) that don't have an LSHIFTRT. */
9815 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9817 && ((nonzero_bits (varop, shift_mode)
9818 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9822 if (((code == LSHIFTRT
9823 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9824 && !(nonzero_bits (varop, shift_mode) >> count))
9826 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9827 && !((nonzero_bits (varop, shift_mode) << count)
9828 & GET_MODE_MASK (shift_mode))))
9829 && !side_effects_p (varop))
9832 switch (GET_CODE (varop))
9838 new_rtx = expand_compound_operation (varop);
9839 if (new_rtx != varop)
9847 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9848 minus the width of a smaller mode, we can do this with a
9849 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9850 if ((code == ASHIFTRT || code == LSHIFTRT)
9851 && ! mode_dependent_address_p (XEXP (varop, 0))
9852 && ! MEM_VOLATILE_P (varop)
9853 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9854 MODE_INT, 1)) != BLKmode)
9856 new_rtx = adjust_address_nv (varop, tmode,
9857 BYTES_BIG_ENDIAN ? 0
9858 : count / BITS_PER_UNIT);
9860 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9861 : ZERO_EXTEND, mode, new_rtx);
9868 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9869 the same number of words as what we've seen so far. Then store
9870 the widest mode in MODE. */
9871 if (subreg_lowpart_p (varop)
9872 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9873 > GET_MODE_SIZE (GET_MODE (varop)))
9874 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9875 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9877 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9878 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9880 varop = SUBREG_REG (varop);
9881 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9882 mode = GET_MODE (varop);
9888 /* Some machines use MULT instead of ASHIFT because MULT
9889 is cheaper. But it is still better on those machines to
9890 merge two shifts into one. */
9891 if (CONST_INT_P (XEXP (varop, 1))
9892 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9895 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9897 GEN_INT (exact_log2 (
9898 INTVAL (XEXP (varop, 1)))));
9904 /* Similar, for when divides are cheaper. */
9905 if (CONST_INT_P (XEXP (varop, 1))
9906 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9909 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9911 GEN_INT (exact_log2 (
9912 INTVAL (XEXP (varop, 1)))));
9918 /* If we are extracting just the sign bit of an arithmetic
9919 right shift, that shift is not needed. However, the sign
9920 bit of a wider mode may be different from what would be
9921 interpreted as the sign bit in a narrower mode, so, if
9922 the result is narrower, don't discard the shift. */
9923 if (code == LSHIFTRT
9924 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9925 && (GET_MODE_BITSIZE (result_mode)
9926 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9928 varop = XEXP (varop, 0);
9932 /* ... fall through ... */
9937 /* Here we have two nested shifts. The result is usually the
9938 AND of a new shift with a mask. We compute the result below. */
9939 if (CONST_INT_P (XEXP (varop, 1))
9940 && INTVAL (XEXP (varop, 1)) >= 0
9941 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9942 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9943 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9944 && !VECTOR_MODE_P (result_mode))
9946 enum rtx_code first_code = GET_CODE (varop);
9947 unsigned int first_count = INTVAL (XEXP (varop, 1));
9948 unsigned HOST_WIDE_INT mask;
9951 /* We have one common special case. We can't do any merging if
9952 the inner code is an ASHIFTRT of a smaller mode. However, if
9953 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9954 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9955 we can convert it to
9956 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9957 This simplifies certain SIGN_EXTEND operations. */
9958 if (code == ASHIFT && first_code == ASHIFTRT
9959 && count == (GET_MODE_BITSIZE (result_mode)
9960 - GET_MODE_BITSIZE (GET_MODE (varop))))
9962 /* C3 has the low-order C1 bits zero. */
9964 mask = (GET_MODE_MASK (mode)
9965 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9967 varop = simplify_and_const_int (NULL_RTX, result_mode,
9968 XEXP (varop, 0), mask);
9969 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9971 count = first_count;
9976 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9977 than C1 high-order bits equal to the sign bit, we can convert
9978 this to either an ASHIFT or an ASHIFTRT depending on the
9981 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9983 if (code == ASHIFTRT && first_code == ASHIFT
9984 && GET_MODE (varop) == shift_mode
9985 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9988 varop = XEXP (varop, 0);
9989 count -= first_count;
9999 /* There are some cases we can't do. If CODE is ASHIFTRT,
10000 we can only do this if FIRST_CODE is also ASHIFTRT.
10002 We can't do the case when CODE is ROTATE and FIRST_CODE is
10005 If the mode of this shift is not the mode of the outer shift,
10006 we can't do this if either shift is a right shift or ROTATE.
10008 Finally, we can't do any of these if the mode is too wide
10009 unless the codes are the same.
10011 Handle the case where the shift codes are the same
10014 if (code == first_code)
10016 if (GET_MODE (varop) != result_mode
10017 && (code == ASHIFTRT || code == LSHIFTRT
10018 || code == ROTATE))
10021 count += first_count;
10022 varop = XEXP (varop, 0);
10026 if (code == ASHIFTRT
10027 || (code == ROTATE && first_code == ASHIFTRT)
10028 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10029 || (GET_MODE (varop) != result_mode
10030 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10031 || first_code == ROTATE
10032 || code == ROTATE)))
10035 /* To compute the mask to apply after the shift, shift the
10036 nonzero bits of the inner shift the same way the
10037 outer shift will. */
10039 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10042 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10045 /* Give up if we can't compute an outer operation to use. */
10047 || !CONST_INT_P (mask_rtx)
10048 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10050 result_mode, &complement_p))
10053 /* If the shifts are in the same direction, we add the
10054 counts. Otherwise, we subtract them. */
10055 if ((code == ASHIFTRT || code == LSHIFTRT)
10056 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10057 count += first_count;
10059 count -= first_count;
10061 /* If COUNT is positive, the new shift is usually CODE,
10062 except for the two exceptions below, in which case it is
10063 FIRST_CODE. If the count is negative, FIRST_CODE should
10066 && ((first_code == ROTATE && code == ASHIFT)
10067 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10069 else if (count < 0)
10070 code = first_code, count = -count;
10072 varop = XEXP (varop, 0);
10076 /* If we have (A << B << C) for any shift, we can convert this to
10077 (A << C << B). This wins if A is a constant. Only try this if
10078 B is not a constant. */
10080 else if (GET_CODE (varop) == code
10081 && CONST_INT_P (XEXP (varop, 0))
10082 && !CONST_INT_P (XEXP (varop, 1)))
10084 rtx new_rtx = simplify_const_binary_operation (code, mode,
10087 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10094 if (VECTOR_MODE_P (mode))
10097 /* Make this fit the case below. */
10098 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10099 GEN_INT (GET_MODE_MASK (mode)));
10105 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10106 with C the size of VAROP - 1 and the shift is logical if
10107 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10108 we have an (le X 0) operation. If we have an arithmetic shift
10109 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10110 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10112 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10113 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10114 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10115 && (code == LSHIFTRT || code == ASHIFTRT)
10116 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10117 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10120 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10123 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10124 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10129 /* If we have (shift (logical)), move the logical to the outside
10130 to allow it to possibly combine with another logical and the
10131 shift to combine with another shift. This also canonicalizes to
10132 what a ZERO_EXTRACT looks like. Also, some machines have
10133 (and (shift)) insns. */
10135 if (CONST_INT_P (XEXP (varop, 1))
10136 /* We can't do this if we have (ashiftrt (xor)) and the
10137 constant has its sign bit set in shift_mode. */
10138 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10139 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10141 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10143 GEN_INT (count))) != 0
10144 && CONST_INT_P (new_rtx)
10145 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10146 INTVAL (new_rtx), result_mode, &complement_p))
10148 varop = XEXP (varop, 0);
10152 /* If we can't do that, try to simplify the shift in each arm of the
10153 logical expression, make a new logical expression, and apply
10154 the inverse distributive law. This also can't be done
10155 for some (ashiftrt (xor)). */
10156 if (CONST_INT_P (XEXP (varop, 1))
10157 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10158 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10161 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10162 XEXP (varop, 0), count);
10163 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10164 XEXP (varop, 1), count);
10166 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10168 varop = apply_distributive_law (varop);
10176 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10177 says that the sign bit can be tested, FOO has mode MODE, C is
10178 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10179 that may be nonzero. */
10180 if (code == LSHIFTRT
10181 && XEXP (varop, 1) == const0_rtx
10182 && GET_MODE (XEXP (varop, 0)) == result_mode
10183 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10184 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10185 && STORE_FLAG_VALUE == -1
10186 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10187 && merge_outer_ops (&outer_op, &outer_const, XOR,
10188 (HOST_WIDE_INT) 1, result_mode,
10191 varop = XEXP (varop, 0);
10198 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10199 than the number of bits in the mode is equivalent to A. */
10200 if (code == LSHIFTRT
10201 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10202 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10204 varop = XEXP (varop, 0);
10209 /* NEG commutes with ASHIFT since it is multiplication. Move the
10210 NEG outside to allow shifts to combine. */
10212 && merge_outer_ops (&outer_op, &outer_const, NEG,
10213 (HOST_WIDE_INT) 0, result_mode,
10216 varop = XEXP (varop, 0);
10222 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10223 is one less than the number of bits in the mode is
10224 equivalent to (xor A 1). */
10225 if (code == LSHIFTRT
10226 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10227 && XEXP (varop, 1) == constm1_rtx
10228 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10229 && merge_outer_ops (&outer_op, &outer_const, XOR,
10230 (HOST_WIDE_INT) 1, result_mode,
10234 varop = XEXP (varop, 0);
10238 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10239 that might be nonzero in BAR are those being shifted out and those
10240 bits are known zero in FOO, we can replace the PLUS with FOO.
10241 Similarly in the other operand order. This code occurs when
10242 we are computing the size of a variable-size array. */
10244 if ((code == ASHIFTRT || code == LSHIFTRT)
10245 && count < HOST_BITS_PER_WIDE_INT
10246 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10247 && (nonzero_bits (XEXP (varop, 1), result_mode)
10248 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10250 varop = XEXP (varop, 0);
10253 else if ((code == ASHIFTRT || code == LSHIFTRT)
10254 && count < HOST_BITS_PER_WIDE_INT
10255 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10256 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10258 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10259 & nonzero_bits (XEXP (varop, 1),
10262 varop = XEXP (varop, 1);
10266 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10268 && CONST_INT_P (XEXP (varop, 1))
10269 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10271 GEN_INT (count))) != 0
10272 && CONST_INT_P (new_rtx)
10273 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10274 INTVAL (new_rtx), result_mode, &complement_p))
10276 varop = XEXP (varop, 0);
10280 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10281 signbit', and attempt to change the PLUS to an XOR and move it to
10282 the outer operation as is done above in the AND/IOR/XOR case
10283 leg for shift(logical). See details in logical handling above
10284 for reasoning in doing so. */
10285 if (code == LSHIFTRT
10286 && CONST_INT_P (XEXP (varop, 1))
10287 && mode_signbit_p (result_mode, XEXP (varop, 1))
10288 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10290 GEN_INT (count))) != 0
10291 && CONST_INT_P (new_rtx)
10292 && merge_outer_ops (&outer_op, &outer_const, XOR,
10293 INTVAL (new_rtx), result_mode, &complement_p))
10295 varop = XEXP (varop, 0);
10302 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10303 with C the size of VAROP - 1 and the shift is logical if
10304 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10305 we have a (gt X 0) operation. If the shift is arithmetic with
10306 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10307 we have a (neg (gt X 0)) operation. */
10309 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10310 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10311 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10312 && (code == LSHIFTRT || code == ASHIFTRT)
10313 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10314 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10315 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10318 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10321 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10322 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10329 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10330 if the truncate does not affect the value. */
10331 if (code == LSHIFTRT
10332 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10333 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10334 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10335 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10336 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10338 rtx varop_inner = XEXP (varop, 0);
10341 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10342 XEXP (varop_inner, 0),
10344 (count + INTVAL (XEXP (varop_inner, 1))));
10345 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10358 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10359 outer_op, outer_const);
10361 /* We have now finished analyzing the shift. The result should be
10362 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10363 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10364 to the result of the shift. OUTER_CONST is the relevant constant,
10365 but we must turn off all bits turned off in the shift. */
10367 if (outer_op == UNKNOWN
10368 && orig_code == code && orig_count == count
10369 && varop == orig_varop
10370 && shift_mode == GET_MODE (varop))
10373 /* Make a SUBREG if necessary. If we can't make it, fail. */
10374 varop = gen_lowpart (shift_mode, varop);
10375 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10378 /* If we have an outer operation and we just made a shift, it is
10379 possible that we could have simplified the shift were it not
10380 for the outer operation. So try to do the simplification
10383 if (outer_op != UNKNOWN)
10384 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10389 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10391 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10392 turn off all the bits that the shift would have turned off. */
10393 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10394 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10395 GET_MODE_MASK (result_mode) >> orig_count);
10397 /* Do the remainder of the processing in RESULT_MODE. */
10398 x = gen_lowpart_or_truncate (result_mode, x);
10400 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10403 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10405 if (outer_op != UNKNOWN)
10407 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10408 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10409 outer_const = trunc_int_for_mode (outer_const, result_mode);
10411 if (outer_op == AND)
10412 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10413 else if (outer_op == SET)
10415 /* This means that we have determined that the result is
10416 equivalent to a constant. This should be rare. */
10417 if (!side_effects_p (x))
10418 x = GEN_INT (outer_const);
10420 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10421 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10423 x = simplify_gen_binary (outer_op, result_mode, x,
10424 GEN_INT (outer_const));
10430 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10431 The result of the shift is RESULT_MODE. If we cannot simplify it,
10432 return X or, if it is NULL, synthesize the expression with
10433 simplify_gen_binary. Otherwise, return a simplified value.
10435 The shift is normally computed in the widest mode we find in VAROP, as
10436 long as it isn't a different number of words than RESULT_MODE. Exceptions
10437 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10440 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10441 rtx varop, int count)
10443 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10448 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10449 if (GET_MODE (x) != result_mode)
10450 x = gen_lowpart (result_mode, x);
10455 /* Like recog, but we receive the address of a pointer to a new pattern.
10456 We try to match the rtx that the pointer points to.
10457 If that fails, we may try to modify or replace the pattern,
10458 storing the replacement into the same pointer object.
10460 Modifications include deletion or addition of CLOBBERs.
10462 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10463 the CLOBBERs are placed.
10465 The value is the final insn code from the pattern ultimately matched,
10469 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10471 rtx pat = *pnewpat;
10472 int insn_code_number;
10473 int num_clobbers_to_add = 0;
10476 rtx old_notes, old_pat;
10478 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10479 we use to indicate that something didn't match. If we find such a
10480 thing, force rejection. */
10481 if (GET_CODE (pat) == PARALLEL)
10482 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10483 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10484 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10487 old_pat = PATTERN (insn);
10488 old_notes = REG_NOTES (insn);
10489 PATTERN (insn) = pat;
10490 REG_NOTES (insn) = 0;
10492 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10493 if (dump_file && (dump_flags & TDF_DETAILS))
10495 if (insn_code_number < 0)
10496 fputs ("Failed to match this instruction:\n", dump_file);
10498 fputs ("Successfully matched this instruction:\n", dump_file);
10499 print_rtl_single (dump_file, pat);
10502 /* If it isn't, there is the possibility that we previously had an insn
10503 that clobbered some register as a side effect, but the combined
10504 insn doesn't need to do that. So try once more without the clobbers
10505 unless this represents an ASM insn. */
10507 if (insn_code_number < 0 && ! check_asm_operands (pat)
10508 && GET_CODE (pat) == PARALLEL)
10512 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10513 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10516 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10520 SUBST_INT (XVECLEN (pat, 0), pos);
10523 pat = XVECEXP (pat, 0, 0);
10525 PATTERN (insn) = pat;
10526 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10527 if (dump_file && (dump_flags & TDF_DETAILS))
10529 if (insn_code_number < 0)
10530 fputs ("Failed to match this instruction:\n", dump_file);
10532 fputs ("Successfully matched this instruction:\n", dump_file);
10533 print_rtl_single (dump_file, pat);
10536 PATTERN (insn) = old_pat;
10537 REG_NOTES (insn) = old_notes;
10539 /* Recognize all noop sets, these will be killed by followup pass. */
10540 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10541 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10543 /* If we had any clobbers to add, make a new pattern than contains
10544 them. Then check to make sure that all of them are dead. */
10545 if (num_clobbers_to_add)
10547 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10548 rtvec_alloc (GET_CODE (pat) == PARALLEL
10549 ? (XVECLEN (pat, 0)
10550 + num_clobbers_to_add)
10551 : num_clobbers_to_add + 1));
10553 if (GET_CODE (pat) == PARALLEL)
10554 for (i = 0; i < XVECLEN (pat, 0); i++)
10555 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10557 XVECEXP (newpat, 0, 0) = pat;
10559 add_clobbers (newpat, insn_code_number);
10561 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10562 i < XVECLEN (newpat, 0); i++)
10564 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10565 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10567 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10569 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10570 notes = alloc_reg_note (REG_UNUSED,
10571 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10580 return insn_code_number;
10583 /* Like gen_lowpart_general but for use by combine. In combine it
10584 is not possible to create any new pseudoregs. However, it is
10585 safe to create invalid memory addresses, because combine will
10586 try to recognize them and all they will do is make the combine
10589 If for some reason this cannot do its job, an rtx
10590 (clobber (const_int 0)) is returned.
10591 An insn containing that will not be recognized. */
10594 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10596 enum machine_mode imode = GET_MODE (x);
10597 unsigned int osize = GET_MODE_SIZE (omode);
10598 unsigned int isize = GET_MODE_SIZE (imode);
10601 if (omode == imode)
10604 /* Return identity if this is a CONST or symbolic reference. */
10606 && (GET_CODE (x) == CONST
10607 || GET_CODE (x) == SYMBOL_REF
10608 || GET_CODE (x) == LABEL_REF))
10611 /* We can only support MODE being wider than a word if X is a
10612 constant integer or has a mode the same size. */
10613 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10614 && ! ((imode == VOIDmode
10615 && (CONST_INT_P (x)
10616 || GET_CODE (x) == CONST_DOUBLE))
10617 || isize == osize))
10620 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10621 won't know what to do. So we will strip off the SUBREG here and
10622 process normally. */
10623 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10625 x = SUBREG_REG (x);
10627 /* For use in case we fall down into the address adjustments
10628 further below, we need to adjust the known mode and size of
10629 x; imode and isize, since we just adjusted x. */
10630 imode = GET_MODE (x);
10632 if (imode == omode)
10635 isize = GET_MODE_SIZE (imode);
10638 result = gen_lowpart_common (omode, x);
10647 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10649 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10652 /* If we want to refer to something bigger than the original memref,
10653 generate a paradoxical subreg instead. That will force a reload
10654 of the original memref X. */
10656 return gen_rtx_SUBREG (omode, x, 0);
10658 if (WORDS_BIG_ENDIAN)
10659 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10661 /* Adjust the address so that the address-after-the-data is
10663 if (BYTES_BIG_ENDIAN)
10664 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10666 return adjust_address_nv (x, omode, offset);
10669 /* If X is a comparison operator, rewrite it in a new mode. This
10670 probably won't match, but may allow further simplifications. */
10671 else if (COMPARISON_P (x))
10672 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10674 /* If we couldn't simplify X any other way, just enclose it in a
10675 SUBREG. Normally, this SUBREG won't match, but some patterns may
10676 include an explicit SUBREG or we may simplify it further in combine. */
10682 offset = subreg_lowpart_offset (omode, imode);
10683 if (imode == VOIDmode)
10685 imode = int_mode_for_mode (omode);
10686 x = gen_lowpart_common (imode, x);
10690 res = simplify_gen_subreg (omode, x, imode, offset);
10696 return gen_rtx_CLOBBER (omode, const0_rtx);
10699 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10700 comparison code that will be tested.
10702 The result is a possibly different comparison code to use. *POP0 and
10703 *POP1 may be updated.
10705 It is possible that we might detect that a comparison is either always
10706 true or always false. However, we do not perform general constant
10707 folding in combine, so this knowledge isn't useful. Such tautologies
10708 should have been detected earlier. Hence we ignore all such cases. */
10710 static enum rtx_code
10711 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10717 enum machine_mode mode, tmode;
10719 /* Try a few ways of applying the same transformation to both operands. */
10722 #ifndef WORD_REGISTER_OPERATIONS
10723 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10724 so check specially. */
10725 if (code != GTU && code != GEU && code != LTU && code != LEU
10726 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10727 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10728 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10729 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10730 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10731 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10732 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10733 && CONST_INT_P (XEXP (op0, 1))
10734 && XEXP (op0, 1) == XEXP (op1, 1)
10735 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10736 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10737 && (INTVAL (XEXP (op0, 1))
10738 == (GET_MODE_BITSIZE (GET_MODE (op0))
10739 - (GET_MODE_BITSIZE
10740 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10742 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10743 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10747 /* If both operands are the same constant shift, see if we can ignore the
10748 shift. We can if the shift is a rotate or if the bits shifted out of
10749 this shift are known to be zero for both inputs and if the type of
10750 comparison is compatible with the shift. */
10751 if (GET_CODE (op0) == GET_CODE (op1)
10752 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10753 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10754 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10755 && (code != GT && code != LT && code != GE && code != LE))
10756 || (GET_CODE (op0) == ASHIFTRT
10757 && (code != GTU && code != LTU
10758 && code != GEU && code != LEU)))
10759 && CONST_INT_P (XEXP (op0, 1))
10760 && INTVAL (XEXP (op0, 1)) >= 0
10761 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10762 && XEXP (op0, 1) == XEXP (op1, 1))
10764 enum machine_mode mode = GET_MODE (op0);
10765 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10766 int shift_count = INTVAL (XEXP (op0, 1));
10768 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10769 mask &= (mask >> shift_count) << shift_count;
10770 else if (GET_CODE (op0) == ASHIFT)
10771 mask = (mask & (mask << shift_count)) >> shift_count;
10773 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10774 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10775 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10780 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10781 SUBREGs are of the same mode, and, in both cases, the AND would
10782 be redundant if the comparison was done in the narrower mode,
10783 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10784 and the operand's possibly nonzero bits are 0xffffff01; in that case
10785 if we only care about QImode, we don't need the AND). This case
10786 occurs if the output mode of an scc insn is not SImode and
10787 STORE_FLAG_VALUE == 1 (e.g., the 386).
10789 Similarly, check for a case where the AND's are ZERO_EXTEND
10790 operations from some narrower mode even though a SUBREG is not
10793 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10794 && CONST_INT_P (XEXP (op0, 1))
10795 && CONST_INT_P (XEXP (op1, 1)))
10797 rtx inner_op0 = XEXP (op0, 0);
10798 rtx inner_op1 = XEXP (op1, 0);
10799 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10800 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10803 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10804 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10805 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10806 && (GET_MODE (SUBREG_REG (inner_op0))
10807 == GET_MODE (SUBREG_REG (inner_op1)))
10808 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10809 <= HOST_BITS_PER_WIDE_INT)
10810 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10811 GET_MODE (SUBREG_REG (inner_op0)))))
10812 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10813 GET_MODE (SUBREG_REG (inner_op1))))))
10815 op0 = SUBREG_REG (inner_op0);
10816 op1 = SUBREG_REG (inner_op1);
10818 /* The resulting comparison is always unsigned since we masked
10819 off the original sign bit. */
10820 code = unsigned_condition (code);
10826 for (tmode = GET_CLASS_NARROWEST_MODE
10827 (GET_MODE_CLASS (GET_MODE (op0)));
10828 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10829 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10831 op0 = gen_lowpart (tmode, inner_op0);
10832 op1 = gen_lowpart (tmode, inner_op1);
10833 code = unsigned_condition (code);
10842 /* If both operands are NOT, we can strip off the outer operation
10843 and adjust the comparison code for swapped operands; similarly for
10844 NEG, except that this must be an equality comparison. */
10845 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10846 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10847 && (code == EQ || code == NE)))
10848 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10854 /* If the first operand is a constant, swap the operands and adjust the
10855 comparison code appropriately, but don't do this if the second operand
10856 is already a constant integer. */
10857 if (swap_commutative_operands_p (op0, op1))
10859 tem = op0, op0 = op1, op1 = tem;
10860 code = swap_condition (code);
10863 /* We now enter a loop during which we will try to simplify the comparison.
10864 For the most part, we only are concerned with comparisons with zero,
10865 but some things may really be comparisons with zero but not start
10866 out looking that way. */
10868 while (CONST_INT_P (op1))
10870 enum machine_mode mode = GET_MODE (op0);
10871 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10872 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10873 int equality_comparison_p;
10874 int sign_bit_comparison_p;
10875 int unsigned_comparison_p;
10876 HOST_WIDE_INT const_op;
10878 /* We only want to handle integral modes. This catches VOIDmode,
10879 CCmode, and the floating-point modes. An exception is that we
10880 can handle VOIDmode if OP0 is a COMPARE or a comparison
10883 if (GET_MODE_CLASS (mode) != MODE_INT
10884 && ! (mode == VOIDmode
10885 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10888 /* Get the constant we are comparing against and turn off all bits
10889 not on in our mode. */
10890 const_op = INTVAL (op1);
10891 if (mode != VOIDmode)
10892 const_op = trunc_int_for_mode (const_op, mode);
10893 op1 = GEN_INT (const_op);
10895 /* If we are comparing against a constant power of two and the value
10896 being compared can only have that single bit nonzero (e.g., it was
10897 `and'ed with that bit), we can replace this with a comparison
10900 && (code == EQ || code == NE || code == GE || code == GEU
10901 || code == LT || code == LTU)
10902 && mode_width <= HOST_BITS_PER_WIDE_INT
10903 && exact_log2 (const_op) >= 0
10904 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10906 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10907 op1 = const0_rtx, const_op = 0;
10910 /* Similarly, if we are comparing a value known to be either -1 or
10911 0 with -1, change it to the opposite comparison against zero. */
10914 && (code == EQ || code == NE || code == GT || code == LE
10915 || code == GEU || code == LTU)
10916 && num_sign_bit_copies (op0, mode) == mode_width)
10918 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10919 op1 = const0_rtx, const_op = 0;
10922 /* Do some canonicalizations based on the comparison code. We prefer
10923 comparisons against zero and then prefer equality comparisons.
10924 If we can reduce the size of a constant, we will do that too. */
10929 /* < C is equivalent to <= (C - 1) */
10933 op1 = GEN_INT (const_op);
10935 /* ... fall through to LE case below. */
10941 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10945 op1 = GEN_INT (const_op);
10949 /* If we are doing a <= 0 comparison on a value known to have
10950 a zero sign bit, we can replace this with == 0. */
10951 else if (const_op == 0
10952 && mode_width <= HOST_BITS_PER_WIDE_INT
10953 && (nonzero_bits (op0, mode)
10954 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10959 /* >= C is equivalent to > (C - 1). */
10963 op1 = GEN_INT (const_op);
10965 /* ... fall through to GT below. */
10971 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10975 op1 = GEN_INT (const_op);
10979 /* If we are doing a > 0 comparison on a value known to have
10980 a zero sign bit, we can replace this with != 0. */
10981 else if (const_op == 0
10982 && mode_width <= HOST_BITS_PER_WIDE_INT
10983 && (nonzero_bits (op0, mode)
10984 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10989 /* < C is equivalent to <= (C - 1). */
10993 op1 = GEN_INT (const_op);
10995 /* ... fall through ... */
10998 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10999 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11000 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
11002 const_op = 0, op1 = const0_rtx;
11010 /* unsigned <= 0 is equivalent to == 0 */
11014 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11015 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11016 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
11018 const_op = 0, op1 = const0_rtx;
11024 /* >= C is equivalent to > (C - 1). */
11028 op1 = GEN_INT (const_op);
11030 /* ... fall through ... */
11033 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11034 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11035 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
11037 const_op = 0, op1 = const0_rtx;
11045 /* unsigned > 0 is equivalent to != 0 */
11049 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11050 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11051 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
11053 const_op = 0, op1 = const0_rtx;
11062 /* Compute some predicates to simplify code below. */
11064 equality_comparison_p = (code == EQ || code == NE);
11065 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11066 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11069 /* If this is a sign bit comparison and we can do arithmetic in
11070 MODE, say that we will only be needing the sign bit of OP0. */
11071 if (sign_bit_comparison_p
11072 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11073 op0 = force_to_mode (op0, mode,
11075 << (GET_MODE_BITSIZE (mode) - 1)),
11078 /* Now try cases based on the opcode of OP0. If none of the cases
11079 does a "continue", we exit this loop immediately after the
11082 switch (GET_CODE (op0))
11085 /* If we are extracting a single bit from a variable position in
11086 a constant that has only a single bit set and are comparing it
11087 with zero, we can convert this into an equality comparison
11088 between the position and the location of the single bit. */
11089 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11090 have already reduced the shift count modulo the word size. */
11091 if (!SHIFT_COUNT_TRUNCATED
11092 && CONST_INT_P (XEXP (op0, 0))
11093 && XEXP (op0, 1) == const1_rtx
11094 && equality_comparison_p && const_op == 0
11095 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
11097 if (BITS_BIG_ENDIAN)
11099 enum machine_mode new_mode
11100 = mode_for_extraction (EP_extzv, 1);
11101 if (new_mode == MAX_MACHINE_MODE)
11102 i = BITS_PER_WORD - 1 - i;
11106 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11110 op0 = XEXP (op0, 2);
11114 /* Result is nonzero iff shift count is equal to I. */
11115 code = reverse_condition (code);
11119 /* ... fall through ... */
11122 tem = expand_compound_operation (op0);
11131 /* If testing for equality, we can take the NOT of the constant. */
11132 if (equality_comparison_p
11133 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11135 op0 = XEXP (op0, 0);
11140 /* If just looking at the sign bit, reverse the sense of the
11142 if (sign_bit_comparison_p)
11144 op0 = XEXP (op0, 0);
11145 code = (code == GE ? LT : GE);
11151 /* If testing for equality, we can take the NEG of the constant. */
11152 if (equality_comparison_p
11153 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11155 op0 = XEXP (op0, 0);
11160 /* The remaining cases only apply to comparisons with zero. */
11164 /* When X is ABS or is known positive,
11165 (neg X) is < 0 if and only if X != 0. */
11167 if (sign_bit_comparison_p
11168 && (GET_CODE (XEXP (op0, 0)) == ABS
11169 || (mode_width <= HOST_BITS_PER_WIDE_INT
11170 && (nonzero_bits (XEXP (op0, 0), mode)
11171 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
11173 op0 = XEXP (op0, 0);
11174 code = (code == LT ? NE : EQ);
11178 /* If we have NEG of something whose two high-order bits are the
11179 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11180 if (num_sign_bit_copies (op0, mode) >= 2)
11182 op0 = XEXP (op0, 0);
11183 code = swap_condition (code);
11189 /* If we are testing equality and our count is a constant, we
11190 can perform the inverse operation on our RHS. */
11191 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11192 && (tem = simplify_binary_operation (ROTATERT, mode,
11193 op1, XEXP (op0, 1))) != 0)
11195 op0 = XEXP (op0, 0);
11200 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11201 a particular bit. Convert it to an AND of a constant of that
11202 bit. This will be converted into a ZERO_EXTRACT. */
11203 if (const_op == 0 && sign_bit_comparison_p
11204 && CONST_INT_P (XEXP (op0, 1))
11205 && mode_width <= HOST_BITS_PER_WIDE_INT)
11207 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11210 - INTVAL (XEXP (op0, 1)))));
11211 code = (code == LT ? NE : EQ);
11215 /* Fall through. */
11218 /* ABS is ignorable inside an equality comparison with zero. */
11219 if (const_op == 0 && equality_comparison_p)
11221 op0 = XEXP (op0, 0);
11227 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11228 (compare FOO CONST) if CONST fits in FOO's mode and we
11229 are either testing inequality or have an unsigned
11230 comparison with ZERO_EXTEND or a signed comparison with
11231 SIGN_EXTEND. But don't do it if we don't have a compare
11232 insn of the given mode, since we'd have to revert it
11233 later on, and then we wouldn't know whether to sign- or
11235 mode = GET_MODE (XEXP (op0, 0));
11236 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11237 && ! unsigned_comparison_p
11238 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11239 && ((unsigned HOST_WIDE_INT) const_op
11240 < (((unsigned HOST_WIDE_INT) 1
11241 << (GET_MODE_BITSIZE (mode) - 1))))
11242 && have_insn_for (COMPARE, mode))
11244 op0 = XEXP (op0, 0);
11250 /* Check for the case where we are comparing A - C1 with C2, that is
11252 (subreg:MODE (plus (A) (-C1))) op (C2)
11254 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11255 comparison in the wider mode. One of the following two conditions
11256 must be true in order for this to be valid:
11258 1. The mode extension results in the same bit pattern being added
11259 on both sides and the comparison is equality or unsigned. As
11260 C2 has been truncated to fit in MODE, the pattern can only be
11263 2. The mode extension results in the sign bit being copied on
11266 The difficulty here is that we have predicates for A but not for
11267 (A - C1) so we need to check that C1 is within proper bounds so
11268 as to perturbate A as little as possible. */
11270 if (mode_width <= HOST_BITS_PER_WIDE_INT
11271 && subreg_lowpart_p (op0)
11272 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11273 && GET_CODE (SUBREG_REG (op0)) == PLUS
11274 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11276 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11277 rtx a = XEXP (SUBREG_REG (op0), 0);
11278 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11281 && (unsigned HOST_WIDE_INT) c1
11282 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11283 && (equality_comparison_p || unsigned_comparison_p)
11284 /* (A - C1) zero-extends if it is positive and sign-extends
11285 if it is negative, C2 both zero- and sign-extends. */
11286 && ((0 == (nonzero_bits (a, inner_mode)
11287 & ~GET_MODE_MASK (mode))
11289 /* (A - C1) sign-extends if it is positive and 1-extends
11290 if it is negative, C2 both sign- and 1-extends. */
11291 || (num_sign_bit_copies (a, inner_mode)
11292 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11295 || ((unsigned HOST_WIDE_INT) c1
11296 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11297 /* (A - C1) always sign-extends, like C2. */
11298 && num_sign_bit_copies (a, inner_mode)
11299 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11300 - (mode_width - 1))))
11302 op0 = SUBREG_REG (op0);
11307 /* If the inner mode is narrower and we are extracting the low part,
11308 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11309 if (subreg_lowpart_p (op0)
11310 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11311 /* Fall through */ ;
11315 /* ... fall through ... */
11318 mode = GET_MODE (XEXP (op0, 0));
11319 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11320 && (unsigned_comparison_p || equality_comparison_p)
11321 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11322 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11323 && have_insn_for (COMPARE, mode))
11325 op0 = XEXP (op0, 0);
11331 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11332 this for equality comparisons due to pathological cases involving
11334 if (equality_comparison_p
11335 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11336 op1, XEXP (op0, 1))))
11338 op0 = XEXP (op0, 0);
11343 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11344 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11345 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11347 op0 = XEXP (XEXP (op0, 0), 0);
11348 code = (code == LT ? EQ : NE);
11354 /* We used to optimize signed comparisons against zero, but that
11355 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11356 arrive here as equality comparisons, or (GEU, LTU) are
11357 optimized away. No need to special-case them. */
11359 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11360 (eq B (minus A C)), whichever simplifies. We can only do
11361 this for equality comparisons due to pathological cases involving
11363 if (equality_comparison_p
11364 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11365 XEXP (op0, 1), op1)))
11367 op0 = XEXP (op0, 0);
11372 if (equality_comparison_p
11373 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11374 XEXP (op0, 0), op1)))
11376 op0 = XEXP (op0, 1);
11381 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11382 of bits in X minus 1, is one iff X > 0. */
11383 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11384 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11385 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11387 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11389 op0 = XEXP (op0, 1);
11390 code = (code == GE ? LE : GT);
11396 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11397 if C is zero or B is a constant. */
11398 if (equality_comparison_p
11399 && 0 != (tem = simplify_binary_operation (XOR, mode,
11400 XEXP (op0, 1), op1)))
11402 op0 = XEXP (op0, 0);
11409 case UNEQ: case LTGT:
11410 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11411 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11412 case UNORDERED: case ORDERED:
11413 /* We can't do anything if OP0 is a condition code value, rather
11414 than an actual data value. */
11416 || CC0_P (XEXP (op0, 0))
11417 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11420 /* Get the two operands being compared. */
11421 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11422 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11424 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11426 /* Check for the cases where we simply want the result of the
11427 earlier test or the opposite of that result. */
11428 if (code == NE || code == EQ
11429 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11430 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11431 && (STORE_FLAG_VALUE
11432 & (((HOST_WIDE_INT) 1
11433 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11434 && (code == LT || code == GE)))
11436 enum rtx_code new_code;
11437 if (code == LT || code == NE)
11438 new_code = GET_CODE (op0);
11440 new_code = reversed_comparison_code (op0, NULL);
11442 if (new_code != UNKNOWN)
11453 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11455 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11456 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11457 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11459 op0 = XEXP (op0, 1);
11460 code = (code == GE ? GT : LE);
11466 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11467 will be converted to a ZERO_EXTRACT later. */
11468 if (const_op == 0 && equality_comparison_p
11469 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11470 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11472 op0 = simplify_and_const_int
11473 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11475 XEXP (XEXP (op0, 0), 1)),
11476 (HOST_WIDE_INT) 1);
11480 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11481 zero and X is a comparison and C1 and C2 describe only bits set
11482 in STORE_FLAG_VALUE, we can compare with X. */
11483 if (const_op == 0 && equality_comparison_p
11484 && mode_width <= HOST_BITS_PER_WIDE_INT
11485 && CONST_INT_P (XEXP (op0, 1))
11486 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11487 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11488 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11489 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11491 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11492 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11493 if ((~STORE_FLAG_VALUE & mask) == 0
11494 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11495 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11496 && COMPARISON_P (tem))))
11498 op0 = XEXP (XEXP (op0, 0), 0);
11503 /* If we are doing an equality comparison of an AND of a bit equal
11504 to the sign bit, replace this with a LT or GE comparison of
11505 the underlying value. */
11506 if (equality_comparison_p
11508 && CONST_INT_P (XEXP (op0, 1))
11509 && mode_width <= HOST_BITS_PER_WIDE_INT
11510 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11511 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11513 op0 = XEXP (op0, 0);
11514 code = (code == EQ ? GE : LT);
11518 /* If this AND operation is really a ZERO_EXTEND from a narrower
11519 mode, the constant fits within that mode, and this is either an
11520 equality or unsigned comparison, try to do this comparison in
11525 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11526 -> (ne:DI (reg:SI 4) (const_int 0))
11528 unless TRULY_NOOP_TRUNCATION allows it or the register is
11529 known to hold a value of the required mode the
11530 transformation is invalid. */
11531 if ((equality_comparison_p || unsigned_comparison_p)
11532 && CONST_INT_P (XEXP (op0, 1))
11533 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11534 & GET_MODE_MASK (mode))
11536 && const_op >> i == 0
11537 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11538 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11539 GET_MODE_BITSIZE (GET_MODE (op0)))
11540 || (REG_P (XEXP (op0, 0))
11541 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11543 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11547 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11548 fits in both M1 and M2 and the SUBREG is either paradoxical
11549 or represents the low part, permute the SUBREG and the AND
11551 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11553 unsigned HOST_WIDE_INT c1;
11554 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11555 /* Require an integral mode, to avoid creating something like
11557 if (SCALAR_INT_MODE_P (tmode)
11558 /* It is unsafe to commute the AND into the SUBREG if the
11559 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11560 not defined. As originally written the upper bits
11561 have a defined value due to the AND operation.
11562 However, if we commute the AND inside the SUBREG then
11563 they no longer have defined values and the meaning of
11564 the code has been changed. */
11566 #ifdef WORD_REGISTER_OPERATIONS
11567 || (mode_width > GET_MODE_BITSIZE (tmode)
11568 && mode_width <= BITS_PER_WORD)
11570 || (mode_width <= GET_MODE_BITSIZE (tmode)
11571 && subreg_lowpart_p (XEXP (op0, 0))))
11572 && CONST_INT_P (XEXP (op0, 1))
11573 && mode_width <= HOST_BITS_PER_WIDE_INT
11574 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11575 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11576 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11578 && c1 != GET_MODE_MASK (tmode))
11580 op0 = simplify_gen_binary (AND, tmode,
11581 SUBREG_REG (XEXP (op0, 0)),
11582 gen_int_mode (c1, tmode));
11583 op0 = gen_lowpart (mode, op0);
11588 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11589 if (const_op == 0 && equality_comparison_p
11590 && XEXP (op0, 1) == const1_rtx
11591 && GET_CODE (XEXP (op0, 0)) == NOT)
11593 op0 = simplify_and_const_int
11594 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11595 code = (code == NE ? EQ : NE);
11599 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11600 (eq (and (lshiftrt X) 1) 0).
11601 Also handle the case where (not X) is expressed using xor. */
11602 if (const_op == 0 && equality_comparison_p
11603 && XEXP (op0, 1) == const1_rtx
11604 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11606 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11607 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11609 if (GET_CODE (shift_op) == NOT
11610 || (GET_CODE (shift_op) == XOR
11611 && CONST_INT_P (XEXP (shift_op, 1))
11612 && CONST_INT_P (shift_count)
11613 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11614 && (INTVAL (XEXP (shift_op, 1))
11615 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11617 op0 = simplify_and_const_int
11619 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11620 (HOST_WIDE_INT) 1);
11621 code = (code == NE ? EQ : NE);
11628 /* If we have (compare (ashift FOO N) (const_int C)) and
11629 the high order N bits of FOO (N+1 if an inequality comparison)
11630 are known to be zero, we can do this by comparing FOO with C
11631 shifted right N bits so long as the low-order N bits of C are
11633 if (CONST_INT_P (XEXP (op0, 1))
11634 && INTVAL (XEXP (op0, 1)) >= 0
11635 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11636 < HOST_BITS_PER_WIDE_INT)
11638 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11639 && mode_width <= HOST_BITS_PER_WIDE_INT
11640 && (nonzero_bits (XEXP (op0, 0), mode)
11641 & ~(mask >> (INTVAL (XEXP (op0, 1))
11642 + ! equality_comparison_p))) == 0)
11644 /* We must perform a logical shift, not an arithmetic one,
11645 as we want the top N bits of C to be zero. */
11646 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11648 temp >>= INTVAL (XEXP (op0, 1));
11649 op1 = gen_int_mode (temp, mode);
11650 op0 = XEXP (op0, 0);
11654 /* If we are doing a sign bit comparison, it means we are testing
11655 a particular bit. Convert it to the appropriate AND. */
11656 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11657 && mode_width <= HOST_BITS_PER_WIDE_INT)
11659 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11662 - INTVAL (XEXP (op0, 1)))));
11663 code = (code == LT ? NE : EQ);
11667 /* If this an equality comparison with zero and we are shifting
11668 the low bit to the sign bit, we can convert this to an AND of the
11670 if (const_op == 0 && equality_comparison_p
11671 && CONST_INT_P (XEXP (op0, 1))
11672 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11675 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11676 (HOST_WIDE_INT) 1);
11682 /* If this is an equality comparison with zero, we can do this
11683 as a logical shift, which might be much simpler. */
11684 if (equality_comparison_p && const_op == 0
11685 && CONST_INT_P (XEXP (op0, 1)))
11687 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11689 INTVAL (XEXP (op0, 1)));
11693 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11694 do the comparison in a narrower mode. */
11695 if (! unsigned_comparison_p
11696 && CONST_INT_P (XEXP (op0, 1))
11697 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11698 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11699 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11700 MODE_INT, 1)) != BLKmode
11701 && (((unsigned HOST_WIDE_INT) const_op
11702 + (GET_MODE_MASK (tmode) >> 1) + 1)
11703 <= GET_MODE_MASK (tmode)))
11705 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11709 /* Likewise if OP0 is a PLUS of a sign extension with a
11710 constant, which is usually represented with the PLUS
11711 between the shifts. */
11712 if (! unsigned_comparison_p
11713 && CONST_INT_P (XEXP (op0, 1))
11714 && GET_CODE (XEXP (op0, 0)) == PLUS
11715 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11716 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11717 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11718 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11719 MODE_INT, 1)) != BLKmode
11720 && (((unsigned HOST_WIDE_INT) const_op
11721 + (GET_MODE_MASK (tmode) >> 1) + 1)
11722 <= GET_MODE_MASK (tmode)))
11724 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11725 rtx add_const = XEXP (XEXP (op0, 0), 1);
11726 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11727 add_const, XEXP (op0, 1));
11729 op0 = simplify_gen_binary (PLUS, tmode,
11730 gen_lowpart (tmode, inner),
11735 /* ... fall through ... */
11737 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11738 the low order N bits of FOO are known to be zero, we can do this
11739 by comparing FOO with C shifted left N bits so long as no
11740 overflow occurs. Even if the low order N bits of FOO aren't known
11741 to be zero, if the comparison is >= or < we can use the same
11742 optimization and for > or <= by setting all the low
11743 order N bits in the comparison constant. */
11744 if (CONST_INT_P (XEXP (op0, 1))
11745 && INTVAL (XEXP (op0, 1)) > 0
11746 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11747 && mode_width <= HOST_BITS_PER_WIDE_INT
11748 && (((unsigned HOST_WIDE_INT) const_op
11749 + (GET_CODE (op0) != LSHIFTRT
11750 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11753 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11755 unsigned HOST_WIDE_INT low_bits
11756 = (nonzero_bits (XEXP (op0, 0), mode)
11757 & (((unsigned HOST_WIDE_INT) 1
11758 << INTVAL (XEXP (op0, 1))) - 1));
11759 if (low_bits == 0 || !equality_comparison_p)
11761 /* If the shift was logical, then we must make the condition
11763 if (GET_CODE (op0) == LSHIFTRT)
11764 code = unsigned_condition (code);
11766 const_op <<= INTVAL (XEXP (op0, 1));
11768 && (code == GT || code == GTU
11769 || code == LE || code == LEU))
11771 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11772 op1 = GEN_INT (const_op);
11773 op0 = XEXP (op0, 0);
11778 /* If we are using this shift to extract just the sign bit, we
11779 can replace this with an LT or GE comparison. */
11781 && (equality_comparison_p || sign_bit_comparison_p)
11782 && CONST_INT_P (XEXP (op0, 1))
11783 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11786 op0 = XEXP (op0, 0);
11787 code = (code == NE || code == GT ? LT : GE);
11799 /* Now make any compound operations involved in this comparison. Then,
11800 check for an outmost SUBREG on OP0 that is not doing anything or is
11801 paradoxical. The latter transformation must only be performed when
11802 it is known that the "extra" bits will be the same in op0 and op1 or
11803 that they don't matter. There are three cases to consider:
11805 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11806 care bits and we can assume they have any convenient value. So
11807 making the transformation is safe.
11809 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11810 In this case the upper bits of op0 are undefined. We should not make
11811 the simplification in that case as we do not know the contents of
11814 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11815 UNKNOWN. In that case we know those bits are zeros or ones. We must
11816 also be sure that they are the same as the upper bits of op1.
11818 We can never remove a SUBREG for a non-equality comparison because
11819 the sign bit is in a different place in the underlying object. */
11821 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11822 op1 = make_compound_operation (op1, SET);
11824 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11825 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11826 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11827 && (code == NE || code == EQ))
11829 if (GET_MODE_SIZE (GET_MODE (op0))
11830 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11832 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11834 if (REG_P (SUBREG_REG (op0)))
11836 op0 = SUBREG_REG (op0);
11837 op1 = gen_lowpart (GET_MODE (op0), op1);
11840 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11841 <= HOST_BITS_PER_WIDE_INT)
11842 && (nonzero_bits (SUBREG_REG (op0),
11843 GET_MODE (SUBREG_REG (op0)))
11844 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11846 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11848 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11849 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11850 op0 = SUBREG_REG (op0), op1 = tem;
11854 /* We now do the opposite procedure: Some machines don't have compare
11855 insns in all modes. If OP0's mode is an integer mode smaller than a
11856 word and we can't do a compare in that mode, see if there is a larger
11857 mode for which we can do the compare. There are a number of cases in
11858 which we can use the wider mode. */
11860 mode = GET_MODE (op0);
11861 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11862 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11863 && ! have_insn_for (COMPARE, mode))
11864 for (tmode = GET_MODE_WIDER_MODE (mode);
11866 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11867 tmode = GET_MODE_WIDER_MODE (tmode))
11868 if (have_insn_for (COMPARE, tmode))
11872 /* If this is a test for negative, we can make an explicit
11873 test of the sign bit. Test this first so we can use
11874 a paradoxical subreg to extend OP0. */
11876 if (op1 == const0_rtx && (code == LT || code == GE)
11877 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11879 op0 = simplify_gen_binary (AND, tmode,
11880 gen_lowpart (tmode, op0),
11881 GEN_INT ((HOST_WIDE_INT) 1
11882 << (GET_MODE_BITSIZE (mode)
11884 code = (code == LT) ? NE : EQ;
11888 /* If the only nonzero bits in OP0 and OP1 are those in the
11889 narrower mode and this is an equality or unsigned comparison,
11890 we can use the wider mode. Similarly for sign-extended
11891 values, in which case it is true for all comparisons. */
11892 zero_extended = ((code == EQ || code == NE
11893 || code == GEU || code == GTU
11894 || code == LEU || code == LTU)
11895 && (nonzero_bits (op0, tmode)
11896 & ~GET_MODE_MASK (mode)) == 0
11897 && ((CONST_INT_P (op1)
11898 || (nonzero_bits (op1, tmode)
11899 & ~GET_MODE_MASK (mode)) == 0)));
11902 || ((num_sign_bit_copies (op0, tmode)
11903 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11904 - GET_MODE_BITSIZE (mode)))
11905 && (num_sign_bit_copies (op1, tmode)
11906 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11907 - GET_MODE_BITSIZE (mode)))))
11909 /* If OP0 is an AND and we don't have an AND in MODE either,
11910 make a new AND in the proper mode. */
11911 if (GET_CODE (op0) == AND
11912 && !have_insn_for (AND, mode))
11913 op0 = simplify_gen_binary (AND, tmode,
11914 gen_lowpart (tmode,
11916 gen_lowpart (tmode,
11922 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11923 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11927 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11928 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11935 #ifdef CANONICALIZE_COMPARISON
11936 /* If this machine only supports a subset of valid comparisons, see if we
11937 can convert an unsupported one into a supported one. */
11938 CANONICALIZE_COMPARISON (code, op0, op1);
11947 /* Utility function for record_value_for_reg. Count number of
11952 enum rtx_code code = GET_CODE (x);
11956 if (GET_RTX_CLASS (code) == '2'
11957 || GET_RTX_CLASS (code) == 'c')
11959 rtx x0 = XEXP (x, 0);
11960 rtx x1 = XEXP (x, 1);
11963 return 1 + 2 * count_rtxs (x0);
11965 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11966 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11967 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11968 return 2 + 2 * count_rtxs (x0)
11969 + count_rtxs (x == XEXP (x1, 0)
11970 ? XEXP (x1, 1) : XEXP (x1, 0));
11972 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11973 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11974 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11975 return 2 + 2 * count_rtxs (x1)
11976 + count_rtxs (x == XEXP (x0, 0)
11977 ? XEXP (x0, 1) : XEXP (x0, 0));
11980 fmt = GET_RTX_FORMAT (code);
11981 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11983 ret += count_rtxs (XEXP (x, i));
11984 else if (fmt[i] == 'E')
11985 for (j = 0; j < XVECLEN (x, i); j++)
11986 ret += count_rtxs (XVECEXP (x, i, j));
11991 /* Utility function for following routine. Called when X is part of a value
11992 being stored into last_set_value. Sets last_set_table_tick
11993 for each register mentioned. Similar to mention_regs in cse.c */
11996 update_table_tick (rtx x)
11998 enum rtx_code code = GET_CODE (x);
11999 const char *fmt = GET_RTX_FORMAT (code);
12004 unsigned int regno = REGNO (x);
12005 unsigned int endregno = END_REGNO (x);
12008 for (r = regno; r < endregno; r++)
12010 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12011 rsp->last_set_table_tick = label_tick;
12017 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12020 /* Check for identical subexpressions. If x contains
12021 identical subexpression we only have to traverse one of
12023 if (i == 0 && ARITHMETIC_P (x))
12025 /* Note that at this point x1 has already been
12027 rtx x0 = XEXP (x, 0);
12028 rtx x1 = XEXP (x, 1);
12030 /* If x0 and x1 are identical then there is no need to
12035 /* If x0 is identical to a subexpression of x1 then while
12036 processing x1, x0 has already been processed. Thus we
12037 are done with x. */
12038 if (ARITHMETIC_P (x1)
12039 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12042 /* If x1 is identical to a subexpression of x0 then we
12043 still have to process the rest of x0. */
12044 if (ARITHMETIC_P (x0)
12045 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12047 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12052 update_table_tick (XEXP (x, i));
12054 else if (fmt[i] == 'E')
12055 for (j = 0; j < XVECLEN (x, i); j++)
12056 update_table_tick (XVECEXP (x, i, j));
12059 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12060 are saying that the register is clobbered and we no longer know its
12061 value. If INSN is zero, don't update reg_stat[].last_set; this is
12062 only permitted with VALUE also zero and is used to invalidate the
12066 record_value_for_reg (rtx reg, rtx insn, rtx value)
12068 unsigned int regno = REGNO (reg);
12069 unsigned int endregno = END_REGNO (reg);
12071 reg_stat_type *rsp;
12073 /* If VALUE contains REG and we have a previous value for REG, substitute
12074 the previous value. */
12075 if (value && insn && reg_overlap_mentioned_p (reg, value))
12079 /* Set things up so get_last_value is allowed to see anything set up to
12081 subst_low_luid = DF_INSN_LUID (insn);
12082 tem = get_last_value (reg);
12084 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12085 it isn't going to be useful and will take a lot of time to process,
12086 so just use the CLOBBER. */
12090 if (ARITHMETIC_P (tem)
12091 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12092 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12093 tem = XEXP (tem, 0);
12094 else if (count_occurrences (value, reg, 1) >= 2)
12096 /* If there are two or more occurrences of REG in VALUE,
12097 prevent the value from growing too much. */
12098 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12099 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12102 value = replace_rtx (copy_rtx (value), reg, tem);
12106 /* For each register modified, show we don't know its value, that
12107 we don't know about its bitwise content, that its value has been
12108 updated, and that we don't know the location of the death of the
12110 for (i = regno; i < endregno; i++)
12112 rsp = VEC_index (reg_stat_type, reg_stat, i);
12115 rsp->last_set = insn;
12117 rsp->last_set_value = 0;
12118 rsp->last_set_mode = VOIDmode;
12119 rsp->last_set_nonzero_bits = 0;
12120 rsp->last_set_sign_bit_copies = 0;
12121 rsp->last_death = 0;
12122 rsp->truncated_to_mode = VOIDmode;
12125 /* Mark registers that are being referenced in this value. */
12127 update_table_tick (value);
12129 /* Now update the status of each register being set.
12130 If someone is using this register in this block, set this register
12131 to invalid since we will get confused between the two lives in this
12132 basic block. This makes using this register always invalid. In cse, we
12133 scan the table to invalidate all entries using this register, but this
12134 is too much work for us. */
12136 for (i = regno; i < endregno; i++)
12138 rsp = VEC_index (reg_stat_type, reg_stat, i);
12139 rsp->last_set_label = label_tick;
12141 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12142 rsp->last_set_invalid = 1;
12144 rsp->last_set_invalid = 0;
12147 /* The value being assigned might refer to X (like in "x++;"). In that
12148 case, we must replace it with (clobber (const_int 0)) to prevent
12150 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12151 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12153 value = copy_rtx (value);
12154 if (!get_last_value_validate (&value, insn, label_tick, 1))
12158 /* For the main register being modified, update the value, the mode, the
12159 nonzero bits, and the number of sign bit copies. */
12161 rsp->last_set_value = value;
12165 enum machine_mode mode = GET_MODE (reg);
12166 subst_low_luid = DF_INSN_LUID (insn);
12167 rsp->last_set_mode = mode;
12168 if (GET_MODE_CLASS (mode) == MODE_INT
12169 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12170 mode = nonzero_bits_mode;
12171 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12172 rsp->last_set_sign_bit_copies
12173 = num_sign_bit_copies (value, GET_MODE (reg));
12177 /* Called via note_stores from record_dead_and_set_regs to handle one
12178 SET or CLOBBER in an insn. DATA is the instruction in which the
12179 set is occurring. */
12182 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12184 rtx record_dead_insn = (rtx) data;
12186 if (GET_CODE (dest) == SUBREG)
12187 dest = SUBREG_REG (dest);
12189 if (!record_dead_insn)
12192 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12198 /* If we are setting the whole register, we know its value. Otherwise
12199 show that we don't know the value. We can handle SUBREG in
12201 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12202 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12203 else if (GET_CODE (setter) == SET
12204 && GET_CODE (SET_DEST (setter)) == SUBREG
12205 && SUBREG_REG (SET_DEST (setter)) == dest
12206 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12207 && subreg_lowpart_p (SET_DEST (setter)))
12208 record_value_for_reg (dest, record_dead_insn,
12209 gen_lowpart (GET_MODE (dest),
12210 SET_SRC (setter)));
12212 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12214 else if (MEM_P (dest)
12215 /* Ignore pushes, they clobber nothing. */
12216 && ! push_operand (dest, GET_MODE (dest)))
12217 mem_last_set = DF_INSN_LUID (record_dead_insn);
12220 /* Update the records of when each REG was most recently set or killed
12221 for the things done by INSN. This is the last thing done in processing
12222 INSN in the combiner loop.
12224 We update reg_stat[], in particular fields last_set, last_set_value,
12225 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12226 last_death, and also the similar information mem_last_set (which insn
12227 most recently modified memory) and last_call_luid (which insn was the
12228 most recent subroutine call). */
12231 record_dead_and_set_regs (rtx insn)
12236 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12238 if (REG_NOTE_KIND (link) == REG_DEAD
12239 && REG_P (XEXP (link, 0)))
12241 unsigned int regno = REGNO (XEXP (link, 0));
12242 unsigned int endregno = END_REGNO (XEXP (link, 0));
12244 for (i = regno; i < endregno; i++)
12246 reg_stat_type *rsp;
12248 rsp = VEC_index (reg_stat_type, reg_stat, i);
12249 rsp->last_death = insn;
12252 else if (REG_NOTE_KIND (link) == REG_INC)
12253 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12258 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12259 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12261 reg_stat_type *rsp;
12263 rsp = VEC_index (reg_stat_type, reg_stat, i);
12264 rsp->last_set_invalid = 1;
12265 rsp->last_set = insn;
12266 rsp->last_set_value = 0;
12267 rsp->last_set_mode = VOIDmode;
12268 rsp->last_set_nonzero_bits = 0;
12269 rsp->last_set_sign_bit_copies = 0;
12270 rsp->last_death = 0;
12271 rsp->truncated_to_mode = VOIDmode;
12274 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12276 /* We can't combine into a call pattern. Remember, though, that
12277 the return value register is set at this LUID. We could
12278 still replace a register with the return value from the
12279 wrong subroutine call! */
12280 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12283 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12286 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12287 register present in the SUBREG, so for each such SUBREG go back and
12288 adjust nonzero and sign bit information of the registers that are
12289 known to have some zero/sign bits set.
12291 This is needed because when combine blows the SUBREGs away, the
12292 information on zero/sign bits is lost and further combines can be
12293 missed because of that. */
12296 record_promoted_value (rtx insn, rtx subreg)
12299 unsigned int regno = REGNO (SUBREG_REG (subreg));
12300 enum machine_mode mode = GET_MODE (subreg);
12302 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12305 for (links = LOG_LINKS (insn); links;)
12307 reg_stat_type *rsp;
12309 insn = XEXP (links, 0);
12310 set = single_set (insn);
12312 if (! set || !REG_P (SET_DEST (set))
12313 || REGNO (SET_DEST (set)) != regno
12314 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12316 links = XEXP (links, 1);
12320 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12321 if (rsp->last_set == insn)
12323 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12324 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12327 if (REG_P (SET_SRC (set)))
12329 regno = REGNO (SET_SRC (set));
12330 links = LOG_LINKS (insn);
12337 /* Check if X, a register, is known to contain a value already
12338 truncated to MODE. In this case we can use a subreg to refer to
12339 the truncated value even though in the generic case we would need
12340 an explicit truncation. */
12343 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12345 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12346 enum machine_mode truncated = rsp->truncated_to_mode;
12349 || rsp->truncation_label < label_tick_ebb_start)
12351 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12353 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12354 GET_MODE_BITSIZE (truncated)))
12359 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12360 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12361 might be able to turn a truncate into a subreg using this information.
12362 Return -1 if traversing *P is complete or 0 otherwise. */
12365 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12368 enum machine_mode truncated_mode;
12369 reg_stat_type *rsp;
12371 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12373 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12374 truncated_mode = GET_MODE (x);
12376 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12379 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12380 GET_MODE_BITSIZE (original_mode)))
12383 x = SUBREG_REG (x);
12385 /* ??? For hard-regs we now record everything. We might be able to
12386 optimize this using last_set_mode. */
12387 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12388 truncated_mode = GET_MODE (x);
12392 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12393 if (rsp->truncated_to_mode == 0
12394 || rsp->truncation_label < label_tick_ebb_start
12395 || (GET_MODE_SIZE (truncated_mode)
12396 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12398 rsp->truncated_to_mode = truncated_mode;
12399 rsp->truncation_label = label_tick;
12405 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12406 the modes they are used in. This can help truning TRUNCATEs into
12410 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12412 for_each_rtx (x, record_truncated_value, NULL);
12415 /* Scan X for promoted SUBREGs. For each one found,
12416 note what it implies to the registers used in it. */
12419 check_promoted_subreg (rtx insn, rtx x)
12421 if (GET_CODE (x) == SUBREG
12422 && SUBREG_PROMOTED_VAR_P (x)
12423 && REG_P (SUBREG_REG (x)))
12424 record_promoted_value (insn, x);
12427 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12430 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12434 check_promoted_subreg (insn, XEXP (x, i));
12438 if (XVEC (x, i) != 0)
12439 for (j = 0; j < XVECLEN (x, i); j++)
12440 check_promoted_subreg (insn, XVECEXP (x, i, j));
12446 /* Verify that all the registers and memory references mentioned in *LOC are
12447 still valid. *LOC was part of a value set in INSN when label_tick was
12448 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12449 the invalid references with (clobber (const_int 0)) and return 1. This
12450 replacement is useful because we often can get useful information about
12451 the form of a value (e.g., if it was produced by a shift that always
12452 produces -1 or 0) even though we don't know exactly what registers it
12453 was produced from. */
12456 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12459 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12460 int len = GET_RTX_LENGTH (GET_CODE (x));
12465 unsigned int regno = REGNO (x);
12466 unsigned int endregno = END_REGNO (x);
12469 for (j = regno; j < endregno; j++)
12471 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12472 if (rsp->last_set_invalid
12473 /* If this is a pseudo-register that was only set once and not
12474 live at the beginning of the function, it is always valid. */
12475 || (! (regno >= FIRST_PSEUDO_REGISTER
12476 && REG_N_SETS (regno) == 1
12477 && (!REGNO_REG_SET_P
12478 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12479 && rsp->last_set_label > tick))
12482 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12489 /* If this is a memory reference, make sure that there were no stores after
12490 it that might have clobbered the value. We don't have alias info, so we
12491 assume any store invalidates it. Moreover, we only have local UIDs, so
12492 we also assume that there were stores in the intervening basic blocks. */
12493 else if (MEM_P (x) && !MEM_READONLY_P (x)
12494 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12497 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12501 for (i = 0; i < len; i++)
12505 /* Check for identical subexpressions. If x contains
12506 identical subexpression we only have to traverse one of
12508 if (i == 1 && ARITHMETIC_P (x))
12510 /* Note that at this point x0 has already been checked
12511 and found valid. */
12512 rtx x0 = XEXP (x, 0);
12513 rtx x1 = XEXP (x, 1);
12515 /* If x0 and x1 are identical then x is also valid. */
12519 /* If x1 is identical to a subexpression of x0 then
12520 while checking x0, x1 has already been checked. Thus
12521 it is valid and so as x. */
12522 if (ARITHMETIC_P (x0)
12523 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12526 /* If x0 is identical to a subexpression of x1 then x is
12527 valid iff the rest of x1 is valid. */
12528 if (ARITHMETIC_P (x1)
12529 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12531 get_last_value_validate (&XEXP (x1,
12532 x0 == XEXP (x1, 0) ? 1 : 0),
12533 insn, tick, replace);
12536 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12540 else if (fmt[i] == 'E')
12541 for (j = 0; j < XVECLEN (x, i); j++)
12542 if (get_last_value_validate (&XVECEXP (x, i, j),
12543 insn, tick, replace) == 0)
12547 /* If we haven't found a reason for it to be invalid, it is valid. */
12551 /* Get the last value assigned to X, if known. Some registers
12552 in the value may be replaced with (clobber (const_int 0)) if their value
12553 is known longer known reliably. */
12556 get_last_value (const_rtx x)
12558 unsigned int regno;
12560 reg_stat_type *rsp;
12562 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12563 then convert it to the desired mode. If this is a paradoxical SUBREG,
12564 we cannot predict what values the "extra" bits might have. */
12565 if (GET_CODE (x) == SUBREG
12566 && subreg_lowpart_p (x)
12567 && (GET_MODE_SIZE (GET_MODE (x))
12568 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12569 && (value = get_last_value (SUBREG_REG (x))) != 0)
12570 return gen_lowpart (GET_MODE (x), value);
12576 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12577 value = rsp->last_set_value;
12579 /* If we don't have a value, or if it isn't for this basic block and
12580 it's either a hard register, set more than once, or it's a live
12581 at the beginning of the function, return 0.
12583 Because if it's not live at the beginning of the function then the reg
12584 is always set before being used (is never used without being set).
12585 And, if it's set only once, and it's always set before use, then all
12586 uses must have the same last value, even if it's not from this basic
12590 || (rsp->last_set_label < label_tick_ebb_start
12591 && (regno < FIRST_PSEUDO_REGISTER
12592 || REG_N_SETS (regno) != 1
12594 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12597 /* If the value was set in a later insn than the ones we are processing,
12598 we can't use it even if the register was only set once. */
12599 if (rsp->last_set_label == label_tick
12600 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12603 /* If the value has all its registers valid, return it. */
12604 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12607 /* Otherwise, make a copy and replace any invalid register with
12608 (clobber (const_int 0)). If that fails for some reason, return 0. */
12610 value = copy_rtx (value);
12611 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12617 /* Return nonzero if expression X refers to a REG or to memory
12618 that is set in an instruction more recent than FROM_LUID. */
12621 use_crosses_set_p (const_rtx x, int from_luid)
12625 enum rtx_code code = GET_CODE (x);
12629 unsigned int regno = REGNO (x);
12630 unsigned endreg = END_REGNO (x);
12632 #ifdef PUSH_ROUNDING
12633 /* Don't allow uses of the stack pointer to be moved,
12634 because we don't know whether the move crosses a push insn. */
12635 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12638 for (; regno < endreg; regno++)
12640 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12642 && rsp->last_set_label == label_tick
12643 && DF_INSN_LUID (rsp->last_set) > from_luid)
12649 if (code == MEM && mem_last_set > from_luid)
12652 fmt = GET_RTX_FORMAT (code);
12654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12660 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12663 else if (fmt[i] == 'e'
12664 && use_crosses_set_p (XEXP (x, i), from_luid))
12670 /* Define three variables used for communication between the following
12673 static unsigned int reg_dead_regno, reg_dead_endregno;
12674 static int reg_dead_flag;
12676 /* Function called via note_stores from reg_dead_at_p.
12678 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12679 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12682 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12684 unsigned int regno, endregno;
12689 regno = REGNO (dest);
12690 endregno = END_REGNO (dest);
12691 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12692 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12695 /* Return nonzero if REG is known to be dead at INSN.
12697 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12698 referencing REG, it is dead. If we hit a SET referencing REG, it is
12699 live. Otherwise, see if it is live or dead at the start of the basic
12700 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12701 must be assumed to be always live. */
12704 reg_dead_at_p (rtx reg, rtx insn)
12709 /* Set variables for reg_dead_at_p_1. */
12710 reg_dead_regno = REGNO (reg);
12711 reg_dead_endregno = END_REGNO (reg);
12715 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12716 we allow the machine description to decide whether use-and-clobber
12717 patterns are OK. */
12718 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12720 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12721 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12725 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12726 beginning of basic block. */
12727 block = BLOCK_FOR_INSN (insn);
12732 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12734 return reg_dead_flag == 1 ? 1 : 0;
12736 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12740 if (insn == BB_HEAD (block))
12743 insn = PREV_INSN (insn);
12746 /* Look at live-in sets for the basic block that we were in. */
12747 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12748 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12754 /* Note hard registers in X that are used. */
12757 mark_used_regs_combine (rtx x)
12759 RTX_CODE code = GET_CODE (x);
12760 unsigned int regno;
12773 case ADDR_DIFF_VEC:
12776 /* CC0 must die in the insn after it is set, so we don't need to take
12777 special note of it here. */
12783 /* If we are clobbering a MEM, mark any hard registers inside the
12784 address as used. */
12785 if (MEM_P (XEXP (x, 0)))
12786 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12791 /* A hard reg in a wide mode may really be multiple registers.
12792 If so, mark all of them just like the first. */
12793 if (regno < FIRST_PSEUDO_REGISTER)
12795 /* None of this applies to the stack, frame or arg pointers. */
12796 if (regno == STACK_POINTER_REGNUM
12797 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12798 || regno == HARD_FRAME_POINTER_REGNUM
12800 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12801 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12803 || regno == FRAME_POINTER_REGNUM)
12806 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12812 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12814 rtx testreg = SET_DEST (x);
12816 while (GET_CODE (testreg) == SUBREG
12817 || GET_CODE (testreg) == ZERO_EXTRACT
12818 || GET_CODE (testreg) == STRICT_LOW_PART)
12819 testreg = XEXP (testreg, 0);
12821 if (MEM_P (testreg))
12822 mark_used_regs_combine (XEXP (testreg, 0));
12824 mark_used_regs_combine (SET_SRC (x));
12832 /* Recursively scan the operands of this expression. */
12835 const char *fmt = GET_RTX_FORMAT (code);
12837 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12840 mark_used_regs_combine (XEXP (x, i));
12841 else if (fmt[i] == 'E')
12845 for (j = 0; j < XVECLEN (x, i); j++)
12846 mark_used_regs_combine (XVECEXP (x, i, j));
12852 /* Remove register number REGNO from the dead registers list of INSN.
12854 Return the note used to record the death, if there was one. */
12857 remove_death (unsigned int regno, rtx insn)
12859 rtx note = find_regno_note (insn, REG_DEAD, regno);
12862 remove_note (insn, note);
12867 /* For each register (hardware or pseudo) used within expression X, if its
12868 death is in an instruction with luid between FROM_LUID (inclusive) and
12869 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12870 list headed by PNOTES.
12872 That said, don't move registers killed by maybe_kill_insn.
12874 This is done when X is being merged by combination into TO_INSN. These
12875 notes will then be distributed as needed. */
12878 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12883 enum rtx_code code = GET_CODE (x);
12887 unsigned int regno = REGNO (x);
12888 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12890 /* Don't move the register if it gets killed in between from and to. */
12891 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12892 && ! reg_referenced_p (x, maybe_kill_insn))
12896 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12897 && DF_INSN_LUID (where_dead) >= from_luid
12898 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12900 rtx note = remove_death (regno, where_dead);
12902 /* It is possible for the call above to return 0. This can occur
12903 when last_death points to I2 or I1 that we combined with.
12904 In that case make a new note.
12906 We must also check for the case where X is a hard register
12907 and NOTE is a death note for a range of hard registers
12908 including X. In that case, we must put REG_DEAD notes for
12909 the remaining registers in place of NOTE. */
12911 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12912 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12913 > GET_MODE_SIZE (GET_MODE (x))))
12915 unsigned int deadregno = REGNO (XEXP (note, 0));
12916 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12917 unsigned int ourend = END_HARD_REGNO (x);
12920 for (i = deadregno; i < deadend; i++)
12921 if (i < regno || i >= ourend)
12922 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12925 /* If we didn't find any note, or if we found a REG_DEAD note that
12926 covers only part of the given reg, and we have a multi-reg hard
12927 register, then to be safe we must check for REG_DEAD notes
12928 for each register other than the first. They could have
12929 their own REG_DEAD notes lying around. */
12930 else if ((note == 0
12932 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12933 < GET_MODE_SIZE (GET_MODE (x)))))
12934 && regno < FIRST_PSEUDO_REGISTER
12935 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12937 unsigned int ourend = END_HARD_REGNO (x);
12938 unsigned int i, offset;
12942 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12946 for (i = regno + offset; i < ourend; i++)
12947 move_deaths (regno_reg_rtx[i],
12948 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12951 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12953 XEXP (note, 1) = *pnotes;
12957 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12963 else if (GET_CODE (x) == SET)
12965 rtx dest = SET_DEST (x);
12967 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12969 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12970 that accesses one word of a multi-word item, some
12971 piece of everything register in the expression is used by
12972 this insn, so remove any old death. */
12973 /* ??? So why do we test for equality of the sizes? */
12975 if (GET_CODE (dest) == ZERO_EXTRACT
12976 || GET_CODE (dest) == STRICT_LOW_PART
12977 || (GET_CODE (dest) == SUBREG
12978 && (((GET_MODE_SIZE (GET_MODE (dest))
12979 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12980 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12981 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12983 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12987 /* If this is some other SUBREG, we know it replaces the entire
12988 value, so use that as the destination. */
12989 if (GET_CODE (dest) == SUBREG)
12990 dest = SUBREG_REG (dest);
12992 /* If this is a MEM, adjust deaths of anything used in the address.
12993 For a REG (the only other possibility), the entire value is
12994 being replaced so the old value is not used in this insn. */
12997 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13002 else if (GET_CODE (x) == CLOBBER)
13005 len = GET_RTX_LENGTH (code);
13006 fmt = GET_RTX_FORMAT (code);
13008 for (i = 0; i < len; i++)
13013 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13014 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13017 else if (fmt[i] == 'e')
13018 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13022 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13023 pattern of an insn. X must be a REG. */
13026 reg_bitfield_target_p (rtx x, rtx body)
13030 if (GET_CODE (body) == SET)
13032 rtx dest = SET_DEST (body);
13034 unsigned int regno, tregno, endregno, endtregno;
13036 if (GET_CODE (dest) == ZERO_EXTRACT)
13037 target = XEXP (dest, 0);
13038 else if (GET_CODE (dest) == STRICT_LOW_PART)
13039 target = SUBREG_REG (XEXP (dest, 0));
13043 if (GET_CODE (target) == SUBREG)
13044 target = SUBREG_REG (target);
13046 if (!REG_P (target))
13049 tregno = REGNO (target), regno = REGNO (x);
13050 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13051 return target == x;
13053 endtregno = end_hard_regno (GET_MODE (target), tregno);
13054 endregno = end_hard_regno (GET_MODE (x), regno);
13056 return endregno > tregno && regno < endtregno;
13059 else if (GET_CODE (body) == PARALLEL)
13060 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13061 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13067 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13068 as appropriate. I3 and I2 are the insns resulting from the combination
13069 insns including FROM (I2 may be zero).
13071 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13072 not need REG_DEAD notes because they are being substituted for. This
13073 saves searching in the most common cases.
13075 Each note in the list is either ignored or placed on some insns, depending
13076 on the type of note. */
13079 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13080 rtx elim_i1, rtx elim_i0)
13082 rtx note, next_note;
13085 for (note = notes; note; note = next_note)
13087 rtx place = 0, place2 = 0;
13089 next_note = XEXP (note, 1);
13090 switch (REG_NOTE_KIND (note))
13094 /* Doesn't matter much where we put this, as long as it's somewhere.
13095 It is preferable to keep these notes on branches, which is most
13096 likely to be i3. */
13100 case REG_VALUE_PROFILE:
13101 /* Just get rid of this note, as it is unused later anyway. */
13104 case REG_NON_LOCAL_GOTO:
13109 gcc_assert (i2 && JUMP_P (i2));
13114 case REG_EH_REGION:
13115 /* These notes must remain with the call or trapping instruction. */
13118 else if (i2 && CALL_P (i2))
13122 gcc_assert (cfun->can_throw_non_call_exceptions);
13123 if (may_trap_p (i3))
13125 else if (i2 && may_trap_p (i2))
13127 /* ??? Otherwise assume we've combined things such that we
13128 can now prove that the instructions can't trap. Drop the
13129 note in this case. */
13135 /* These notes must remain with the call. It should not be
13136 possible for both I2 and I3 to be a call. */
13141 gcc_assert (i2 && CALL_P (i2));
13147 /* Any clobbers for i3 may still exist, and so we must process
13148 REG_UNUSED notes from that insn.
13150 Any clobbers from i2 or i1 can only exist if they were added by
13151 recog_for_combine. In that case, recog_for_combine created the
13152 necessary REG_UNUSED notes. Trying to keep any original
13153 REG_UNUSED notes from these insns can cause incorrect output
13154 if it is for the same register as the original i3 dest.
13155 In that case, we will notice that the register is set in i3,
13156 and then add a REG_UNUSED note for the destination of i3, which
13157 is wrong. However, it is possible to have REG_UNUSED notes from
13158 i2 or i1 for register which were both used and clobbered, so
13159 we keep notes from i2 or i1 if they will turn into REG_DEAD
13162 /* If this register is set or clobbered in I3, put the note there
13163 unless there is one already. */
13164 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13166 if (from_insn != i3)
13169 if (! (REG_P (XEXP (note, 0))
13170 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13171 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13174 /* Otherwise, if this register is used by I3, then this register
13175 now dies here, so we must put a REG_DEAD note here unless there
13177 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13178 && ! (REG_P (XEXP (note, 0))
13179 ? find_regno_note (i3, REG_DEAD,
13180 REGNO (XEXP (note, 0)))
13181 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13183 PUT_REG_NOTE_KIND (note, REG_DEAD);
13191 /* These notes say something about results of an insn. We can
13192 only support them if they used to be on I3 in which case they
13193 remain on I3. Otherwise they are ignored.
13195 If the note refers to an expression that is not a constant, we
13196 must also ignore the note since we cannot tell whether the
13197 equivalence is still true. It might be possible to do
13198 slightly better than this (we only have a problem if I2DEST
13199 or I1DEST is present in the expression), but it doesn't
13200 seem worth the trouble. */
13202 if (from_insn == i3
13203 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13208 /* These notes say something about how a register is used. They must
13209 be present on any use of the register in I2 or I3. */
13210 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13213 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13222 case REG_LABEL_TARGET:
13223 case REG_LABEL_OPERAND:
13224 /* This can show up in several ways -- either directly in the
13225 pattern, or hidden off in the constant pool with (or without?)
13226 a REG_EQUAL note. */
13227 /* ??? Ignore the without-reg_equal-note problem for now. */
13228 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13229 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13230 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13231 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13235 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13236 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13237 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13238 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13246 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13247 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13249 if (place && JUMP_P (place)
13250 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13251 && (JUMP_LABEL (place) == NULL
13252 || JUMP_LABEL (place) == XEXP (note, 0)))
13254 rtx label = JUMP_LABEL (place);
13257 JUMP_LABEL (place) = XEXP (note, 0);
13258 else if (LABEL_P (label))
13259 LABEL_NUSES (label)--;
13262 if (place2 && JUMP_P (place2)
13263 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13264 && (JUMP_LABEL (place2) == NULL
13265 || JUMP_LABEL (place2) == XEXP (note, 0)))
13267 rtx label = JUMP_LABEL (place2);
13270 JUMP_LABEL (place2) = XEXP (note, 0);
13271 else if (LABEL_P (label))
13272 LABEL_NUSES (label)--;
13278 /* This note says something about the value of a register prior
13279 to the execution of an insn. It is too much trouble to see
13280 if the note is still correct in all situations. It is better
13281 to simply delete it. */
13285 /* If we replaced the right hand side of FROM_INSN with a
13286 REG_EQUAL note, the original use of the dying register
13287 will not have been combined into I3 and I2. In such cases,
13288 FROM_INSN is guaranteed to be the first of the combined
13289 instructions, so we simply need to search back before
13290 FROM_INSN for the previous use or set of this register,
13291 then alter the notes there appropriately.
13293 If the register is used as an input in I3, it dies there.
13294 Similarly for I2, if it is nonzero and adjacent to I3.
13296 If the register is not used as an input in either I3 or I2
13297 and it is not one of the registers we were supposed to eliminate,
13298 there are two possibilities. We might have a non-adjacent I2
13299 or we might have somehow eliminated an additional register
13300 from a computation. For example, we might have had A & B where
13301 we discover that B will always be zero. In this case we will
13302 eliminate the reference to A.
13304 In both cases, we must search to see if we can find a previous
13305 use of A and put the death note there. */
13308 && from_insn == i2mod
13309 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13314 && CALL_P (from_insn)
13315 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13317 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13319 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13320 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13322 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13324 && reg_overlap_mentioned_p (XEXP (note, 0),
13326 || rtx_equal_p (XEXP (note, 0), elim_i1)
13327 || rtx_equal_p (XEXP (note, 0), elim_i0))
13334 basic_block bb = this_basic_block;
13336 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13338 if (!NONDEBUG_INSN_P (tem))
13340 if (tem == BB_HEAD (bb))
13345 /* If the register is being set at TEM, see if that is all
13346 TEM is doing. If so, delete TEM. Otherwise, make this
13347 into a REG_UNUSED note instead. Don't delete sets to
13348 global register vars. */
13349 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13350 || !global_regs[REGNO (XEXP (note, 0))])
13351 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13353 rtx set = single_set (tem);
13354 rtx inner_dest = 0;
13356 rtx cc0_setter = NULL_RTX;
13360 for (inner_dest = SET_DEST (set);
13361 (GET_CODE (inner_dest) == STRICT_LOW_PART
13362 || GET_CODE (inner_dest) == SUBREG
13363 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13364 inner_dest = XEXP (inner_dest, 0))
13367 /* Verify that it was the set, and not a clobber that
13368 modified the register.
13370 CC0 targets must be careful to maintain setter/user
13371 pairs. If we cannot delete the setter due to side
13372 effects, mark the user with an UNUSED note instead
13375 if (set != 0 && ! side_effects_p (SET_SRC (set))
13376 && rtx_equal_p (XEXP (note, 0), inner_dest)
13378 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13379 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13380 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13384 /* Move the notes and links of TEM elsewhere.
13385 This might delete other dead insns recursively.
13386 First set the pattern to something that won't use
13388 rtx old_notes = REG_NOTES (tem);
13390 PATTERN (tem) = pc_rtx;
13391 REG_NOTES (tem) = NULL;
13393 distribute_notes (old_notes, tem, tem, NULL_RTX,
13394 NULL_RTX, NULL_RTX, NULL_RTX);
13395 distribute_links (LOG_LINKS (tem));
13397 SET_INSN_DELETED (tem);
13402 /* Delete the setter too. */
13405 PATTERN (cc0_setter) = pc_rtx;
13406 old_notes = REG_NOTES (cc0_setter);
13407 REG_NOTES (cc0_setter) = NULL;
13409 distribute_notes (old_notes, cc0_setter,
13410 cc0_setter, NULL_RTX,
13411 NULL_RTX, NULL_RTX, NULL_RTX);
13412 distribute_links (LOG_LINKS (cc0_setter));
13414 SET_INSN_DELETED (cc0_setter);
13415 if (cc0_setter == i2)
13422 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13424 /* If there isn't already a REG_UNUSED note, put one
13425 here. Do not place a REG_DEAD note, even if
13426 the register is also used here; that would not
13427 match the algorithm used in lifetime analysis
13428 and can cause the consistency check in the
13429 scheduler to fail. */
13430 if (! find_regno_note (tem, REG_UNUSED,
13431 REGNO (XEXP (note, 0))))
13436 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13438 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13442 /* If we are doing a 3->2 combination, and we have a
13443 register which formerly died in i3 and was not used
13444 by i2, which now no longer dies in i3 and is used in
13445 i2 but does not die in i2, and place is between i2
13446 and i3, then we may need to move a link from place to
13448 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13450 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13451 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13453 rtx links = LOG_LINKS (place);
13454 LOG_LINKS (place) = 0;
13455 distribute_links (links);
13460 if (tem == BB_HEAD (bb))
13466 /* If the register is set or already dead at PLACE, we needn't do
13467 anything with this note if it is still a REG_DEAD note.
13468 We check here if it is set at all, not if is it totally replaced,
13469 which is what `dead_or_set_p' checks, so also check for it being
13472 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13474 unsigned int regno = REGNO (XEXP (note, 0));
13475 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13477 if (dead_or_set_p (place, XEXP (note, 0))
13478 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13480 /* Unless the register previously died in PLACE, clear
13481 last_death. [I no longer understand why this is
13483 if (rsp->last_death != place)
13484 rsp->last_death = 0;
13488 rsp->last_death = place;
13490 /* If this is a death note for a hard reg that is occupying
13491 multiple registers, ensure that we are still using all
13492 parts of the object. If we find a piece of the object
13493 that is unused, we must arrange for an appropriate REG_DEAD
13494 note to be added for it. However, we can't just emit a USE
13495 and tag the note to it, since the register might actually
13496 be dead; so we recourse, and the recursive call then finds
13497 the previous insn that used this register. */
13499 if (place && regno < FIRST_PSEUDO_REGISTER
13500 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13502 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13506 for (i = regno; i < endregno; i++)
13507 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13508 && ! find_regno_fusage (place, USE, i))
13509 || dead_or_set_regno_p (place, i))
13514 /* Put only REG_DEAD notes for pieces that are
13515 not already dead or set. */
13517 for (i = regno; i < endregno;
13518 i += hard_regno_nregs[i][reg_raw_mode[i]])
13520 rtx piece = regno_reg_rtx[i];
13521 basic_block bb = this_basic_block;
13523 if (! dead_or_set_p (place, piece)
13524 && ! reg_bitfield_target_p (piece,
13527 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13530 distribute_notes (new_note, place, place,
13531 NULL_RTX, NULL_RTX, NULL_RTX,
13534 else if (! refers_to_regno_p (i, i + 1,
13535 PATTERN (place), 0)
13536 && ! find_regno_fusage (place, USE, i))
13537 for (tem = PREV_INSN (place); ;
13538 tem = PREV_INSN (tem))
13540 if (!NONDEBUG_INSN_P (tem))
13542 if (tem == BB_HEAD (bb))
13546 if (dead_or_set_p (tem, piece)
13547 || reg_bitfield_target_p (piece,
13550 add_reg_note (tem, REG_UNUSED, piece);
13564 /* Any other notes should not be present at this point in the
13566 gcc_unreachable ();
13571 XEXP (note, 1) = REG_NOTES (place);
13572 REG_NOTES (place) = note;
13576 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13580 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13581 I3, I2, and I1 to new locations. This is also called to add a link
13582 pointing at I3 when I3's destination is changed. */
13585 distribute_links (rtx links)
13587 rtx link, next_link;
13589 for (link = links; link; link = next_link)
13595 next_link = XEXP (link, 1);
13597 /* If the insn that this link points to is a NOTE or isn't a single
13598 set, ignore it. In the latter case, it isn't clear what we
13599 can do other than ignore the link, since we can't tell which
13600 register it was for. Such links wouldn't be used by combine
13603 It is not possible for the destination of the target of the link to
13604 have been changed by combine. The only potential of this is if we
13605 replace I3, I2, and I1 by I3 and I2. But in that case the
13606 destination of I2 also remains unchanged. */
13608 if (NOTE_P (XEXP (link, 0))
13609 || (set = single_set (XEXP (link, 0))) == 0)
13612 reg = SET_DEST (set);
13613 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13614 || GET_CODE (reg) == STRICT_LOW_PART)
13615 reg = XEXP (reg, 0);
13617 /* A LOG_LINK is defined as being placed on the first insn that uses
13618 a register and points to the insn that sets the register. Start
13619 searching at the next insn after the target of the link and stop
13620 when we reach a set of the register or the end of the basic block.
13622 Note that this correctly handles the link that used to point from
13623 I3 to I2. Also note that not much searching is typically done here
13624 since most links don't point very far away. */
13626 for (insn = NEXT_INSN (XEXP (link, 0));
13627 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13628 || BB_HEAD (this_basic_block->next_bb) != insn));
13629 insn = NEXT_INSN (insn))
13630 if (DEBUG_INSN_P (insn))
13632 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13634 if (reg_referenced_p (reg, PATTERN (insn)))
13638 else if (CALL_P (insn)
13639 && find_reg_fusage (insn, USE, reg))
13644 else if (INSN_P (insn) && reg_set_p (reg, insn))
13647 /* If we found a place to put the link, place it there unless there
13648 is already a link to the same insn as LINK at that point. */
13654 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13655 if (XEXP (link2, 0) == XEXP (link, 0))
13660 XEXP (link, 1) = LOG_LINKS (place);
13661 LOG_LINKS (place) = link;
13663 /* Set added_links_insn to the earliest insn we added a
13665 if (added_links_insn == 0
13666 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13667 added_links_insn = place;
13673 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13674 Check whether the expression pointer to by LOC is a register or
13675 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13676 Otherwise return zero. */
13679 unmentioned_reg_p_1 (rtx *loc, void *expr)
13684 && (REG_P (x) || MEM_P (x))
13685 && ! reg_mentioned_p (x, (rtx) expr))
13690 /* Check for any register or memory mentioned in EQUIV that is not
13691 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13692 of EXPR where some registers may have been replaced by constants. */
13695 unmentioned_reg_p (rtx equiv, rtx expr)
13697 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13701 dump_combine_stats (FILE *file)
13705 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13706 combine_attempts, combine_merges, combine_extras, combine_successes);
13710 dump_combine_total_stats (FILE *file)
13714 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13715 total_attempts, total_merges, total_extras, total_successes);
13719 gate_handle_combine (void)
13721 return (optimize > 0);
13724 /* Try combining insns through substitution. */
13725 static unsigned int
13726 rest_of_handle_combine (void)
13728 int rebuild_jump_labels_after_combine;
13730 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13731 df_note_add_problem ();
13734 regstat_init_n_sets_and_refs ();
13736 rebuild_jump_labels_after_combine
13737 = combine_instructions (get_insns (), max_reg_num ());
13739 /* Combining insns may have turned an indirect jump into a
13740 direct jump. Rebuild the JUMP_LABEL fields of jumping
13742 if (rebuild_jump_labels_after_combine)
13744 timevar_push (TV_JUMP);
13745 rebuild_jump_labels (get_insns ());
13747 timevar_pop (TV_JUMP);
13750 regstat_free_n_sets_and_refs ();
13754 struct rtl_opt_pass pass_combine =
13758 "combine", /* name */
13759 gate_handle_combine, /* gate */
13760 rest_of_handle_combine, /* execute */
13763 0, /* static_pass_number */
13764 TV_COMBINE, /* tv_id */
13765 PROP_cfglayout, /* properties_required */
13766 0, /* properties_provided */
13767 0, /* properties_destroyed */
13768 0, /* todo_flags_start */
13770 TODO_df_finish | TODO_verify_rtl_sharing |
13771 TODO_ggc_collect, /* todo_flags_finish */