1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
97 #ifndef ACCUMULATE_OUTGOING_ARGS
98 #define ACCUMULATE_OUTGOING_ARGS 0
101 /* Supply a default definition for PUSH_ARGS. */
104 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
110 /* It is not safe to use ordinary gen_lowpart in combine.
111 Use gen_lowpart_for_combine instead. See comments there. */
112 #define gen_lowpart dont_use_gen_lowpart_you_dummy
114 /* Number of attempts to combine instructions in this function. */
116 static int combine_attempts;
118 /* Number of attempts that got as far as substitution in this function. */
120 static int combine_merges;
122 /* Number of instructions combined with added SETs in this function. */
124 static int combine_extras;
126 /* Number of instructions combined in this function. */
128 static int combine_successes;
130 /* Totals over entire compilation. */
132 static int total_attempts, total_merges, total_extras, total_successes;
135 /* Vector mapping INSN_UIDs to cuids.
136 The cuids are like uids but increase monotonically always.
137 Combine always uses cuids so that it can compare them.
138 But actually renumbering the uids, which we used to do,
139 proves to be a bad idea because it makes it hard to compare
140 the dumps produced by earlier passes with those from later passes. */
142 static int *uid_cuid;
143 static int max_uid_cuid;
145 /* Get the cuid of an insn. */
147 #define INSN_CUID(INSN) \
148 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
150 /* Maximum register number, which is the size of the tables below. */
152 static unsigned int combine_max_regno;
154 /* Record last point of death of (hard or pseudo) register n. */
156 static rtx *reg_last_death;
158 /* Record last point of modification of (hard or pseudo) register n. */
160 static rtx *reg_last_set;
162 /* Record the cuid of the last insn that invalidated memory
163 (anything that writes memory, and subroutine calls, but not pushes). */
165 static int mem_last_set;
167 /* Record the cuid of the last CALL_INSN
168 so we can tell whether a potential combination crosses any calls. */
170 static int last_call_cuid;
172 /* When `subst' is called, this is the insn that is being modified
173 (by combining in a previous insn). The PATTERN of this insn
174 is still the old pattern partially modified and it should not be
175 looked at, but this may be used to examine the successors of the insn
176 to judge whether a simplification is valid. */
178 static rtx subst_insn;
180 /* This is an insn that belongs before subst_insn, but is not currently
181 on the insn chain. */
183 static rtx subst_prev_insn;
185 /* This is the lowest CUID that `subst' is currently dealing with.
186 get_last_value will not return a value if the register was set at or
187 after this CUID. If not for this mechanism, we could get confused if
188 I2 or I1 in try_combine were an insn that used the old value of a register
189 to obtain a new value. In that case, we might erroneously get the
190 new value of the register when we wanted the old one. */
192 static int subst_low_cuid;
194 /* This contains any hard registers that are used in newpat; reg_dead_at_p
195 must consider all these registers to be always live. */
197 static HARD_REG_SET newpat_used_regs;
199 /* This is an insn to which a LOG_LINKS entry has been added. If this
200 insn is the earlier than I2 or I3, combine should rescan starting at
203 static rtx added_links_insn;
205 /* Basic block number of the block in which we are performing combines. */
206 static int this_basic_block;
208 /* A bitmap indicating which blocks had registers go dead at entry.
209 After combine, we'll need to re-do global life analysis with
210 those blocks as starting points. */
211 static sbitmap refresh_blocks;
212 static int need_refresh;
214 /* The next group of arrays allows the recording of the last value assigned
215 to (hard or pseudo) register n. We use this information to see if a
216 operation being processed is redundant given a prior operation performed
217 on the register. For example, an `and' with a constant is redundant if
218 all the zero bits are already known to be turned off.
220 We use an approach similar to that used by cse, but change it in the
223 (1) We do not want to reinitialize at each label.
224 (2) It is useful, but not critical, to know the actual value assigned
225 to a register. Often just its form is helpful.
227 Therefore, we maintain the following arrays:
229 reg_last_set_value the last value assigned
230 reg_last_set_label records the value of label_tick when the
231 register was assigned
232 reg_last_set_table_tick records the value of label_tick when a
233 value using the register is assigned
234 reg_last_set_invalid set to non-zero when it is not valid
235 to use the value of this register in some
238 To understand the usage of these tables, it is important to understand
239 the distinction between the value in reg_last_set_value being valid
240 and the register being validly contained in some other expression in the
243 Entry I in reg_last_set_value is valid if it is non-zero, and either
244 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
246 Register I may validly appear in any expression returned for the value
247 of another register if reg_n_sets[i] is 1. It may also appear in the
248 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
249 reg_last_set_invalid[j] is zero.
251 If an expression is found in the table containing a register which may
252 not validly appear in an expression, the register is replaced by
253 something that won't match, (clobber (const_int 0)).
255 reg_last_set_invalid[i] is set non-zero when register I is being assigned
256 to and reg_last_set_table_tick[i] == label_tick. */
258 /* Record last value assigned to (hard or pseudo) register n. */
260 static rtx *reg_last_set_value;
262 /* Record the value of label_tick when the value for register n is placed in
263 reg_last_set_value[n]. */
265 static int *reg_last_set_label;
267 /* Record the value of label_tick when an expression involving register n
268 is placed in reg_last_set_value. */
270 static int *reg_last_set_table_tick;
272 /* Set non-zero if references to register n in expressions should not be
275 static char *reg_last_set_invalid;
277 /* Incremented for each label. */
279 static int label_tick;
281 /* Some registers that are set more than once and used in more than one
282 basic block are nevertheless always set in similar ways. For example,
283 a QImode register may be loaded from memory in two places on a machine
284 where byte loads zero extend.
286 We record in the following array what we know about the nonzero
287 bits of a register, specifically which bits are known to be zero.
289 If an entry is zero, it means that we don't know anything special. */
291 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
293 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
294 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
296 static enum machine_mode nonzero_bits_mode;
298 /* Nonzero if we know that a register has some leading bits that are always
299 equal to the sign bit. */
301 static unsigned char *reg_sign_bit_copies;
303 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
304 It is zero while computing them and after combine has completed. This
305 former test prevents propagating values based on previously set values,
306 which can be incorrect if a variable is modified in a loop. */
308 static int nonzero_sign_valid;
310 /* These arrays are maintained in parallel with reg_last_set_value
311 and are used to store the mode in which the register was last set,
312 the bits that were known to be zero when it was last set, and the
313 number of sign bits copies it was known to have when it was last set. */
315 static enum machine_mode *reg_last_set_mode;
316 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
317 static char *reg_last_set_sign_bit_copies;
319 /* Record one modification to rtl structure
320 to be undone by storing old_contents into *where.
321 is_int is 1 if the contents are an int. */
327 union {rtx r; unsigned int i;} old_contents;
328 union {rtx *r; unsigned int *i;} where;
331 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
332 num_undo says how many are currently recorded.
334 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too.
337 previous_undos is the value of undobuf.undos when we started processing
338 this substitution. This will prevent gen_rtx_combine from re-used a piece
339 from the previous expression. Doing so can produce circular rtl
346 struct undo *previous_undos;
350 static struct undobuf undobuf;
352 /* Number of times the pseudo being substituted for
353 was found and replaced. */
355 static int n_occurrences;
357 static void do_SUBST PARAMS ((rtx *, rtx));
358 static void do_SUBST_INT PARAMS ((unsigned int *,
360 static void init_reg_last_arrays PARAMS ((void));
361 static void setup_incoming_promotions PARAMS ((void));
362 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
363 static int cant_combine_insn_p PARAMS ((rtx));
364 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
365 static int sets_function_arg_p PARAMS ((rtx));
366 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
367 static int contains_muldiv PARAMS ((rtx));
368 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
369 static void undo_all PARAMS ((void));
370 static void undo_commit PARAMS ((void));
371 static rtx *find_split_point PARAMS ((rtx *, rtx));
372 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
373 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
374 static rtx simplify_if_then_else PARAMS ((rtx));
375 static rtx simplify_set PARAMS ((rtx));
376 static rtx simplify_logical PARAMS ((rtx, int));
377 static rtx expand_compound_operation PARAMS ((rtx));
378 static rtx expand_field_assignment PARAMS ((rtx));
379 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
380 rtx, unsigned HOST_WIDE_INT, int,
382 static rtx extract_left_shift PARAMS ((rtx, int));
383 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
384 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
385 unsigned HOST_WIDE_INT *));
386 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
387 unsigned HOST_WIDE_INT, rtx, int));
388 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
389 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
390 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
391 static rtx make_field_assignment PARAMS ((rtx));
392 static rtx apply_distributive_law PARAMS ((rtx));
393 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
394 unsigned HOST_WIDE_INT));
395 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
396 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
397 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
398 enum rtx_code, HOST_WIDE_INT,
399 enum machine_mode, int *));
400 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
402 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
403 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
404 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
406 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
408 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
409 enum machine_mode, rtx));
410 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
411 static void update_table_tick PARAMS ((rtx));
412 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
413 static void check_promoted_subreg PARAMS ((rtx, rtx));
414 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
415 static void record_dead_and_set_regs PARAMS ((rtx));
416 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
417 static rtx get_last_value PARAMS ((rtx));
418 static int use_crosses_set_p PARAMS ((rtx, int));
419 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
420 static int reg_dead_at_p PARAMS ((rtx, rtx));
421 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
422 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
423 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
424 static void distribute_links PARAMS ((rtx));
425 static void mark_used_regs_combine PARAMS ((rtx));
426 static int insn_cuid PARAMS ((rtx));
427 static void record_promoted_value PARAMS ((rtx, rtx));
428 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
429 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
431 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
432 insn. The substitution can be undone by undo_all. If INTO is already
433 set to NEWVAL, do not record this change. Because computing NEWVAL might
434 also call SUBST, we have to compute it before we put anything into
438 do_SUBST (into, newval)
444 if (oldval == newval)
448 buf = undobuf.frees, undobuf.frees = buf->next;
450 buf = (struct undo *) xmalloc (sizeof (struct undo));
454 buf->old_contents.r = oldval;
457 buf->next = undobuf.undos, undobuf.undos = buf;
460 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
462 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
463 for the value of a HOST_WIDE_INT value (including CONST_INT) is
467 do_SUBST_INT (into, newval)
468 unsigned int *into, newval;
471 unsigned int oldval = *into;
473 if (oldval == newval)
477 buf = undobuf.frees, undobuf.frees = buf->next;
479 buf = (struct undo *) xmalloc (sizeof (struct undo));
483 buf->old_contents.i = oldval;
486 buf->next = undobuf.undos, undobuf.undos = buf;
489 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
491 /* Main entry point for combiner. F is the first insn of the function.
492 NREGS is the first unused pseudo-reg number.
494 Return non-zero if the combiner has turned an indirect jump
495 instruction into a direct jump. */
497 combine_instructions (f, nregs)
501 register rtx insn, next;
506 register rtx links, nextlinks;
508 int new_direct_jump_p = 0;
510 combine_attempts = 0;
513 combine_successes = 0;
515 combine_max_regno = nregs;
517 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
518 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
520 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
522 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
523 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
524 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
525 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
526 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
527 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
529 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
530 reg_last_set_nonzero_bits
531 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
532 reg_last_set_sign_bit_copies
533 = (char *) xmalloc (nregs * sizeof (char));
535 init_reg_last_arrays ();
537 init_recog_no_volatile ();
539 /* Compute maximum uid value so uid_cuid can be allocated. */
541 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
542 if (INSN_UID (insn) > i)
545 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
548 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
550 /* Don't use reg_nonzero_bits when computing it. This can cause problems
551 when, for example, we have j <<= 1 in a loop. */
553 nonzero_sign_valid = 0;
555 /* Compute the mapping from uids to cuids.
556 Cuids are numbers assigned to insns, like uids,
557 except that cuids increase monotonically through the code.
559 Scan all SETs and see if we can deduce anything about what
560 bits are known to be zero for some registers and how many copies
561 of the sign bit are known to exist for those registers.
563 Also set any known values so that we can use it while searching
564 for what bits are known to be set. */
568 /* We need to initialize it here, because record_dead_and_set_regs may call
570 subst_prev_insn = NULL_RTX;
572 setup_incoming_promotions ();
574 refresh_blocks = sbitmap_alloc (n_basic_blocks);
575 sbitmap_zero (refresh_blocks);
578 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
580 uid_cuid[INSN_UID (insn)] = ++i;
586 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
588 record_dead_and_set_regs (insn);
591 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
592 if (REG_NOTE_KIND (links) == REG_INC)
593 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
598 if (GET_CODE (insn) == CODE_LABEL)
602 nonzero_sign_valid = 1;
604 /* Now scan all the insns in forward order. */
606 this_basic_block = -1;
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
617 /* If INSN starts a new basic block, update our basic block number. */
618 if (this_basic_block + 1 < n_basic_blocks
619 && BLOCK_HEAD (this_basic_block + 1) == insn)
622 if (GET_CODE (insn) == CODE_LABEL)
625 else if (INSN_P (insn))
627 /* See if we know about function return values before this
628 insn based upon SUBREG flags. */
629 check_promoted_subreg (insn, PATTERN (insn));
631 /* Try this insn with each insn it links back to. */
633 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
634 if ((next = try_combine (insn, XEXP (links, 0),
635 NULL_RTX, &new_direct_jump_p)) != 0)
638 /* Try each sequence of three linked insns ending with this one. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
642 rtx link = XEXP (links, 0);
644 /* If the linked insn has been replaced by a note, then there
645 is no point in persuing this chain any further. */
646 if (GET_CODE (link) == NOTE)
649 for (nextlinks = LOG_LINKS (link);
651 nextlinks = XEXP (nextlinks, 1))
652 if ((next = try_combine (insn, XEXP (links, 0),
654 &new_direct_jump_p)) != 0)
659 /* Try to combine a jump insn that uses CC0
660 with a preceding insn that sets CC0, and maybe with its
661 logical predecessor as well.
662 This is how we make decrement-and-branch insns.
663 We need this special code because data flow connections
664 via CC0 do not get entered in LOG_LINKS. */
666 if (GET_CODE (insn) == JUMP_INSN
667 && (prev = prev_nonnote_insn (insn)) != 0
668 && GET_CODE (prev) == INSN
669 && sets_cc0_p (PATTERN (prev)))
671 if ((next = try_combine (insn, prev,
672 NULL_RTX, &new_direct_jump_p)) != 0)
675 for (nextlinks = LOG_LINKS (prev); nextlinks;
676 nextlinks = XEXP (nextlinks, 1))
677 if ((next = try_combine (insn, prev,
679 &new_direct_jump_p)) != 0)
683 /* Do the same for an insn that explicitly references CC0. */
684 if (GET_CODE (insn) == INSN
685 && (prev = prev_nonnote_insn (insn)) != 0
686 && GET_CODE (prev) == INSN
687 && sets_cc0_p (PATTERN (prev))
688 && GET_CODE (PATTERN (insn)) == SET
689 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
691 if ((next = try_combine (insn, prev,
692 NULL_RTX, &new_direct_jump_p)) != 0)
695 for (nextlinks = LOG_LINKS (prev); nextlinks;
696 nextlinks = XEXP (nextlinks, 1))
697 if ((next = try_combine (insn, prev,
699 &new_direct_jump_p)) != 0)
703 /* Finally, see if any of the insns that this insn links to
704 explicitly references CC0. If so, try this insn, that insn,
705 and its predecessor if it sets CC0. */
706 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
707 if (GET_CODE (XEXP (links, 0)) == INSN
708 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
709 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
710 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
711 && GET_CODE (prev) == INSN
712 && sets_cc0_p (PATTERN (prev))
713 && (next = try_combine (insn, XEXP (links, 0),
714 prev, &new_direct_jump_p)) != 0)
718 /* Try combining an insn with two different insns whose results it
720 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
721 for (nextlinks = XEXP (links, 1); nextlinks;
722 nextlinks = XEXP (nextlinks, 1))
723 if ((next = try_combine (insn, XEXP (links, 0),
725 &new_direct_jump_p)) != 0)
728 if (GET_CODE (insn) != NOTE)
729 record_dead_and_set_regs (insn);
738 compute_bb_for_insn (get_max_uid ());
739 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
744 sbitmap_free (refresh_blocks);
745 free (reg_nonzero_bits);
746 free (reg_sign_bit_copies);
747 free (reg_last_death);
749 free (reg_last_set_value);
750 free (reg_last_set_table_tick);
751 free (reg_last_set_label);
752 free (reg_last_set_invalid);
753 free (reg_last_set_mode);
754 free (reg_last_set_nonzero_bits);
755 free (reg_last_set_sign_bit_copies);
759 struct undo *undo, *next;
760 for (undo = undobuf.frees; undo; undo = next)
768 total_attempts += combine_attempts;
769 total_merges += combine_merges;
770 total_extras += combine_extras;
771 total_successes += combine_successes;
773 nonzero_sign_valid = 0;
775 /* Make recognizer allow volatile MEMs again. */
778 return new_direct_jump_p;
781 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
784 init_reg_last_arrays ()
786 unsigned int nregs = combine_max_regno;
788 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
789 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
790 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
791 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
792 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
793 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
794 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
795 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
796 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
799 /* Set up any promoted values for incoming argument registers. */
802 setup_incoming_promotions ()
804 #ifdef PROMOTE_FUNCTION_ARGS
807 enum machine_mode mode;
809 rtx first = get_insns ();
811 #ifndef OUTGOING_REGNO
812 #define OUTGOING_REGNO(N) N
814 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
815 /* Check whether this register can hold an incoming pointer
816 argument. FUNCTION_ARG_REGNO_P tests outgoing register
817 numbers, so translate if necessary due to register windows. */
818 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
819 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
822 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
825 gen_rtx_CLOBBER (mode, const0_rtx)));
830 /* Called via note_stores. If X is a pseudo that is narrower than
831 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
833 If we are setting only a portion of X and we can't figure out what
834 portion, assume all bits will be used since we don't know what will
837 Similarly, set how many bits of X are known to be copies of the sign bit
838 at all locations in the function. This is the smallest number implied
842 set_nonzero_bits_and_sign_copies (x, set, data)
845 void *data ATTRIBUTE_UNUSED;
849 if (GET_CODE (x) == REG
850 && REGNO (x) >= FIRST_PSEUDO_REGISTER
851 /* If this register is undefined at the start of the file, we can't
852 say what its contents were. */
853 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
854 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
856 if (set == 0 || GET_CODE (set) == CLOBBER)
858 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
859 reg_sign_bit_copies[REGNO (x)] = 1;
863 /* If this is a complex assignment, see if we can convert it into a
864 simple assignment. */
865 set = expand_field_assignment (set);
867 /* If this is a simple assignment, or we have a paradoxical SUBREG,
868 set what we know about X. */
870 if (SET_DEST (set) == x
871 || (GET_CODE (SET_DEST (set)) == SUBREG
872 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
873 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
874 && SUBREG_REG (SET_DEST (set)) == x))
876 rtx src = SET_SRC (set);
878 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
879 /* If X is narrower than a word and SRC is a non-negative
880 constant that would appear negative in the mode of X,
881 sign-extend it for use in reg_nonzero_bits because some
882 machines (maybe most) will actually do the sign-extension
883 and this is the conservative approach.
885 ??? For 2.5, try to tighten up the MD files in this regard
886 instead of this kludge. */
888 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
889 && GET_CODE (src) == CONST_INT
891 && 0 != (INTVAL (src)
893 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
894 src = GEN_INT (INTVAL (src)
895 | ((HOST_WIDE_INT) (-1)
896 << GET_MODE_BITSIZE (GET_MODE (x))));
899 reg_nonzero_bits[REGNO (x)]
900 |= nonzero_bits (src, nonzero_bits_mode);
901 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
902 if (reg_sign_bit_copies[REGNO (x)] == 0
903 || reg_sign_bit_copies[REGNO (x)] > num)
904 reg_sign_bit_copies[REGNO (x)] = num;
908 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
909 reg_sign_bit_copies[REGNO (x)] = 1;
914 /* See if INSN can be combined into I3. PRED and SUCC are optionally
915 insns that were previously combined into I3 or that will be combined
916 into the merger of INSN and I3.
918 Return 0 if the combination is not allowed for any reason.
920 If the combination is allowed, *PDEST will be set to the single
921 destination of INSN and *PSRC to the single source, and this function
925 can_combine_p (insn, i3, pred, succ, pdest, psrc)
928 rtx pred ATTRIBUTE_UNUSED;
933 rtx set = 0, src, dest;
938 int all_adjacent = (succ ? (next_active_insn (insn) == succ
939 && next_active_insn (succ) == i3)
940 : next_active_insn (insn) == i3);
942 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
943 or a PARALLEL consisting of such a SET and CLOBBERs.
945 If INSN has CLOBBER parallel parts, ignore them for our processing.
946 By definition, these happen during the execution of the insn. When it
947 is merged with another insn, all bets are off. If they are, in fact,
948 needed and aren't also supplied in I3, they may be added by
949 recog_for_combine. Otherwise, it won't match.
951 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
954 Get the source and destination of INSN. If more than one, can't
957 if (GET_CODE (PATTERN (insn)) == SET)
958 set = PATTERN (insn);
959 else if (GET_CODE (PATTERN (insn)) == PARALLEL
960 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
962 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
964 rtx elt = XVECEXP (PATTERN (insn), 0, i);
966 switch (GET_CODE (elt))
968 /* This is important to combine floating point insns
971 /* Combining an isolated USE doesn't make sense.
972 We depend here on combinable_i3_pat to reject them. */
973 /* The code below this loop only verifies that the inputs of
974 the SET in INSN do not change. We call reg_set_between_p
975 to verify that the REG in the USE does not change betweeen
977 If the USE in INSN was for a pseudo register, the matching
978 insn pattern will likely match any register; combining this
979 with any other USE would only be safe if we knew that the
980 used registers have identical values, or if there was
981 something to tell them apart, e.g. different modes. For
982 now, we forgo such compilcated tests and simply disallow
983 combining of USES of pseudo registers with any other USE. */
984 if (GET_CODE (XEXP (elt, 0)) == REG
985 && GET_CODE (PATTERN (i3)) == PARALLEL)
987 rtx i3pat = PATTERN (i3);
988 int i = XVECLEN (i3pat, 0) - 1;
989 unsigned int regno = REGNO (XEXP (elt, 0));
993 rtx i3elt = XVECEXP (i3pat, 0, i);
995 if (GET_CODE (i3elt) == USE
996 && GET_CODE (XEXP (i3elt, 0)) == REG
997 && (REGNO (XEXP (i3elt, 0)) == regno
998 ? reg_set_between_p (XEXP (elt, 0),
999 PREV_INSN (insn), i3)
1000 : regno >= FIRST_PSEUDO_REGISTER))
1007 /* We can ignore CLOBBERs. */
1012 /* Ignore SETs whose result isn't used but not those that
1013 have side-effects. */
1014 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1015 && ! side_effects_p (elt))
1018 /* If we have already found a SET, this is a second one and
1019 so we cannot combine with this insn. */
1027 /* Anything else means we can't combine. */
1033 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1034 so don't do anything with it. */
1035 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1044 set = expand_field_assignment (set);
1045 src = SET_SRC (set), dest = SET_DEST (set);
1047 /* Don't eliminate a store in the stack pointer. */
1048 if (dest == stack_pointer_rtx
1049 /* If we couldn't eliminate a field assignment, we can't combine. */
1050 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1051 /* Don't combine with an insn that sets a register to itself if it has
1052 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1053 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1054 /* Can't merge an ASM_OPERANDS. */
1055 || GET_CODE (src) == ASM_OPERANDS
1056 /* Can't merge a function call. */
1057 || GET_CODE (src) == CALL
1058 /* Don't eliminate a function call argument. */
1059 || (GET_CODE (i3) == CALL_INSN
1060 && (find_reg_fusage (i3, USE, dest)
1061 || (GET_CODE (dest) == REG
1062 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1063 && global_regs[REGNO (dest)])))
1064 /* Don't substitute into an incremented register. */
1065 || FIND_REG_INC_NOTE (i3, dest)
1066 || (succ && FIND_REG_INC_NOTE (succ, dest))
1068 /* Don't combine the end of a libcall into anything. */
1069 /* ??? This gives worse code, and appears to be unnecessary, since no
1070 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1071 use REG_RETVAL notes for noconflict blocks, but other code here
1072 makes sure that those insns don't disappear. */
1073 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1075 /* Make sure that DEST is not used after SUCC but before I3. */
1076 || (succ && ! all_adjacent
1077 && reg_used_between_p (dest, succ, i3))
1078 /* Make sure that the value that is to be substituted for the register
1079 does not use any registers whose values alter in between. However,
1080 If the insns are adjacent, a use can't cross a set even though we
1081 think it might (this can happen for a sequence of insns each setting
1082 the same destination; reg_last_set of that register might point to
1083 a NOTE). If INSN has a REG_EQUIV note, the register is always
1084 equivalent to the memory so the substitution is valid even if there
1085 are intervening stores. Also, don't move a volatile asm or
1086 UNSPEC_VOLATILE across any other insns. */
1088 && (((GET_CODE (src) != MEM
1089 || ! find_reg_note (insn, REG_EQUIV, src))
1090 && use_crosses_set_p (src, INSN_CUID (insn)))
1091 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1092 || GET_CODE (src) == UNSPEC_VOLATILE))
1093 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1094 better register allocation by not doing the combine. */
1095 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1096 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1097 /* Don't combine across a CALL_INSN, because that would possibly
1098 change whether the life span of some REGs crosses calls or not,
1099 and it is a pain to update that information.
1100 Exception: if source is a constant, moving it later can't hurt.
1101 Accept that special case, because it helps -fforce-addr a lot. */
1102 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1105 /* DEST must either be a REG or CC0. */
1106 if (GET_CODE (dest) == REG)
1108 /* If register alignment is being enforced for multi-word items in all
1109 cases except for parameters, it is possible to have a register copy
1110 insn referencing a hard register that is not allowed to contain the
1111 mode being copied and which would not be valid as an operand of most
1112 insns. Eliminate this problem by not combining with such an insn.
1114 Also, on some machines we don't want to extend the life of a hard
1117 if (GET_CODE (src) == REG
1118 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1119 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1120 /* Don't extend the life of a hard register unless it is
1121 user variable (if we have few registers) or it can't
1122 fit into the desired register (meaning something special
1124 Also avoid substituting a return register into I3, because
1125 reload can't handle a conflict with constraints of other
1127 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1128 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1131 else if (GET_CODE (dest) != CC0)
1134 /* Don't substitute for a register intended as a clobberable operand.
1135 Similarly, don't substitute an expression containing a register that
1136 will be clobbered in I3. */
1137 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1138 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1139 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1140 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1142 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1145 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1146 or not), reject, unless nothing volatile comes between it and I3 */
1148 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1150 /* Make sure succ doesn't contain a volatile reference. */
1151 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1154 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1155 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1159 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1160 to be an explicit register variable, and was chosen for a reason. */
1162 if (GET_CODE (src) == ASM_OPERANDS
1163 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1166 /* If there are any volatile insns between INSN and I3, reject, because
1167 they might affect machine state. */
1169 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1170 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1173 /* If INSN or I2 contains an autoincrement or autodecrement,
1174 make sure that register is not used between there and I3,
1175 and not already used in I3 either.
1176 Also insist that I3 not be a jump; if it were one
1177 and the incremented register were spilled, we would lose. */
1180 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1181 if (REG_NOTE_KIND (link) == REG_INC
1182 && (GET_CODE (i3) == JUMP_INSN
1183 || reg_used_between_p (XEXP (link, 0), insn, i3)
1184 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1189 /* Don't combine an insn that follows a CC0-setting insn.
1190 An insn that uses CC0 must not be separated from the one that sets it.
1191 We do, however, allow I2 to follow a CC0-setting insn if that insn
1192 is passed as I1; in that case it will be deleted also.
1193 We also allow combining in this case if all the insns are adjacent
1194 because that would leave the two CC0 insns adjacent as well.
1195 It would be more logical to test whether CC0 occurs inside I1 or I2,
1196 but that would be much slower, and this ought to be equivalent. */
1198 p = prev_nonnote_insn (insn);
1199 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1204 /* If we get here, we have passed all the tests and the combination is
1213 /* Check if PAT is an insn - or a part of it - used to set up an
1214 argument for a function in a hard register. */
1217 sets_function_arg_p (pat)
1223 switch (GET_CODE (pat))
1226 return sets_function_arg_p (PATTERN (pat));
1229 for (i = XVECLEN (pat, 0); --i >= 0;)
1230 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1236 inner_dest = SET_DEST (pat);
1237 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1238 || GET_CODE (inner_dest) == SUBREG
1239 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1240 inner_dest = XEXP (inner_dest, 0);
1242 return (GET_CODE (inner_dest) == REG
1243 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1244 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1253 /* LOC is the location within I3 that contains its pattern or the component
1254 of a PARALLEL of the pattern. We validate that it is valid for combining.
1256 One problem is if I3 modifies its output, as opposed to replacing it
1257 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1258 so would produce an insn that is not equivalent to the original insns.
1262 (set (reg:DI 101) (reg:DI 100))
1263 (set (subreg:SI (reg:DI 101) 0) <foo>)
1265 This is NOT equivalent to:
1267 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1268 (set (reg:DI 101) (reg:DI 100))])
1270 Not only does this modify 100 (in which case it might still be valid
1271 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1273 We can also run into a problem if I2 sets a register that I1
1274 uses and I1 gets directly substituted into I3 (not via I2). In that
1275 case, we would be getting the wrong value of I2DEST into I3, so we
1276 must reject the combination. This case occurs when I2 and I1 both
1277 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1278 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1279 of a SET must prevent combination from occurring.
1281 Before doing the above check, we first try to expand a field assignment
1282 into a set of logical operations.
1284 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1285 we place a register that is both set and used within I3. If more than one
1286 such register is detected, we fail.
1288 Return 1 if the combination is valid, zero otherwise. */
1291 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1297 rtx *pi3dest_killed;
1301 if (GET_CODE (x) == SET)
1303 rtx set = expand_field_assignment (x);
1304 rtx dest = SET_DEST (set);
1305 rtx src = SET_SRC (set);
1306 rtx inner_dest = dest;
1309 rtx inner_src = src;
1314 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1315 || GET_CODE (inner_dest) == SUBREG
1316 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1317 inner_dest = XEXP (inner_dest, 0);
1319 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1322 while (GET_CODE (inner_src) == STRICT_LOW_PART
1323 || GET_CODE (inner_src) == SUBREG
1324 || GET_CODE (inner_src) == ZERO_EXTRACT)
1325 inner_src = XEXP (inner_src, 0);
1327 /* If it is better that two different modes keep two different pseudos,
1328 avoid combining them. This avoids producing the following pattern
1330 (set (subreg:SI (reg/v:QI 21) 0)
1331 (lshiftrt:SI (reg/v:SI 20)
1333 If that were made, reload could not handle the pair of
1334 reg 20/21, since it would try to get any GENERAL_REGS
1335 but some of them don't handle QImode. */
1337 if (rtx_equal_p (inner_src, i2dest)
1338 && GET_CODE (inner_dest) == REG
1339 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1343 /* Check for the case where I3 modifies its output, as
1345 if ((inner_dest != dest
1346 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1347 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1349 /* This is the same test done in can_combine_p except we can't test
1350 all_adjacent; we don't have to, since this instruction will stay
1351 in place, thus we are not considering increasing the lifetime of
1354 Also, if this insn sets a function argument, combining it with
1355 something that might need a spill could clobber a previous
1356 function argument; the all_adjacent test in can_combine_p also
1357 checks this; here, we do a more specific test for this case. */
1359 || (GET_CODE (inner_dest) == REG
1360 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1361 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1362 GET_MODE (inner_dest))))
1363 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1366 /* If DEST is used in I3, it is being killed in this insn,
1367 so record that for later.
1368 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1369 STACK_POINTER_REGNUM, since these are always considered to be
1370 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1371 if (pi3dest_killed && GET_CODE (dest) == REG
1372 && reg_referenced_p (dest, PATTERN (i3))
1373 && REGNO (dest) != FRAME_POINTER_REGNUM
1374 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1375 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1377 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1378 && (REGNO (dest) != ARG_POINTER_REGNUM
1379 || ! fixed_regs [REGNO (dest)])
1381 && REGNO (dest) != STACK_POINTER_REGNUM)
1383 if (*pi3dest_killed)
1386 *pi3dest_killed = dest;
1390 else if (GET_CODE (x) == PARALLEL)
1394 for (i = 0; i < XVECLEN (x, 0); i++)
1395 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1396 i1_not_in_src, pi3dest_killed))
1403 /* Return 1 if X is an arithmetic expression that contains a multiplication
1404 and division. We don't count multiplications by powers of two here. */
1410 switch (GET_CODE (x))
1412 case MOD: case DIV: case UMOD: case UDIV:
1416 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1417 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1419 switch (GET_RTX_CLASS (GET_CODE (x)))
1421 case 'c': case '<': case '2':
1422 return contains_muldiv (XEXP (x, 0))
1423 || contains_muldiv (XEXP (x, 1));
1426 return contains_muldiv (XEXP (x, 0));
1434 /* Determine whether INSN can be used in a combination. Return nonzero if
1435 not. This is used in try_combine to detect early some cases where we
1436 can't perform combinations. */
1439 cant_combine_insn_p (insn)
1445 /* If this isn't really an insn, we can't do anything.
1446 This can occur when flow deletes an insn that it has merged into an
1447 auto-increment address. */
1448 if (! INSN_P (insn))
1451 /* Never combine loads and stores involving hard regs. The register
1452 allocator can usually handle such reg-reg moves by tying. If we allow
1453 the combiner to make substitutions of hard regs, we risk aborting in
1454 reload on machines that have SMALL_REGISTER_CLASSES.
1455 As an exception, we allow combinations involving fixed regs; these are
1456 not available to the register allocator so there's no risk involved. */
1458 set = single_set (insn);
1461 src = SET_SRC (set);
1462 dest = SET_DEST (set);
1463 if (GET_CODE (src) == SUBREG)
1464 src = SUBREG_REG (src);
1465 if (GET_CODE (dest) == SUBREG)
1466 dest = SUBREG_REG (dest);
1467 if (REG_P (src) && REG_P (dest)
1468 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1469 && ! fixed_regs[REGNO (src)])
1470 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1471 && ! fixed_regs[REGNO (dest)])))
1477 /* Try to combine the insns I1 and I2 into I3.
1478 Here I1 and I2 appear earlier than I3.
1479 I1 can be zero; then we combine just I2 into I3.
1481 It we are combining three insns and the resulting insn is not recognized,
1482 try splitting it into two insns. If that happens, I2 and I3 are retained
1483 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1486 Return 0 if the combination does not work. Then nothing is changed.
1487 If we did the combination, return the insn at which combine should
1490 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1491 new direct jump instruction. */
1494 try_combine (i3, i2, i1, new_direct_jump_p)
1495 register rtx i3, i2, i1;
1496 register int *new_direct_jump_p;
1498 /* New patterns for I3 and I2, respectively. */
1499 rtx newpat, newi2pat = 0;
1500 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1501 int added_sets_1, added_sets_2;
1502 /* Total number of SETs to put into I3. */
1504 /* Nonzero is I2's body now appears in I3. */
1506 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1507 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1508 /* Contains I3 if the destination of I3 is used in its source, which means
1509 that the old life of I3 is being killed. If that usage is placed into
1510 I2 and not in I3, a REG_DEAD note must be made. */
1511 rtx i3dest_killed = 0;
1512 /* SET_DEST and SET_SRC of I2 and I1. */
1513 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1514 /* PATTERN (I2), or a copy of it in certain cases. */
1516 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1517 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1518 int i1_feeds_i3 = 0;
1519 /* Notes that must be added to REG_NOTES in I3 and I2. */
1520 rtx new_i3_notes, new_i2_notes;
1521 /* Notes that we substituted I3 into I2 instead of the normal case. */
1522 int i3_subst_into_i2 = 0;
1523 /* Notes that I1, I2 or I3 is a MULT operation. */
1531 /* Exit early if one of the insns involved can't be used for
1533 if (cant_combine_insn_p (i3)
1534 || cant_combine_insn_p (i2)
1535 || (i1 && cant_combine_insn_p (i1))
1536 /* We also can't do anything if I3 has a
1537 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1540 /* ??? This gives worse code, and appears to be unnecessary, since no
1541 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1542 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1548 undobuf.other_insn = 0;
1550 /* Reset the hard register usage information. */
1551 CLEAR_HARD_REG_SET (newpat_used_regs);
1553 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1554 code below, set I1 to be the earlier of the two insns. */
1555 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1556 temp = i1, i1 = i2, i2 = temp;
1558 added_links_insn = 0;
1560 /* First check for one important special-case that the code below will
1561 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1562 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1563 we may be able to replace that destination with the destination of I3.
1564 This occurs in the common code where we compute both a quotient and
1565 remainder into a structure, in which case we want to do the computation
1566 directly into the structure to avoid register-register copies.
1568 Note that this case handles both multiple sets in I2 and also
1569 cases where I2 has a number of CLOBBER or PARALLELs.
1571 We make very conservative checks below and only try to handle the
1572 most common cases of this. For example, we only handle the case
1573 where I2 and I3 are adjacent to avoid making difficult register
1576 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1577 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1578 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1579 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1580 && GET_CODE (PATTERN (i2)) == PARALLEL
1581 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1582 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1583 below would need to check what is inside (and reg_overlap_mentioned_p
1584 doesn't support those codes anyway). Don't allow those destinations;
1585 the resulting insn isn't likely to be recognized anyway. */
1586 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1587 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1588 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1589 SET_DEST (PATTERN (i3)))
1590 && next_real_insn (i2) == i3)
1592 rtx p2 = PATTERN (i2);
1594 /* Make sure that the destination of I3,
1595 which we are going to substitute into one output of I2,
1596 is not used within another output of I2. We must avoid making this:
1597 (parallel [(set (mem (reg 69)) ...)
1598 (set (reg 69) ...)])
1599 which is not well-defined as to order of actions.
1600 (Besides, reload can't handle output reloads for this.)
1602 The problem can also happen if the dest of I3 is a memory ref,
1603 if another dest in I2 is an indirect memory ref. */
1604 for (i = 0; i < XVECLEN (p2, 0); i++)
1605 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1606 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1607 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1608 SET_DEST (XVECEXP (p2, 0, i))))
1611 if (i == XVECLEN (p2, 0))
1612 for (i = 0; i < XVECLEN (p2, 0); i++)
1613 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1614 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1615 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1620 subst_low_cuid = INSN_CUID (i2);
1622 added_sets_2 = added_sets_1 = 0;
1623 i2dest = SET_SRC (PATTERN (i3));
1625 /* Replace the dest in I2 with our dest and make the resulting
1626 insn the new pattern for I3. Then skip to where we
1627 validate the pattern. Everything was set up above. */
1628 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1629 SET_DEST (PATTERN (i3)));
1632 i3_subst_into_i2 = 1;
1633 goto validate_replacement;
1637 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1638 one of those words to another constant, merge them by making a new
1641 && (temp = single_set (i2)) != 0
1642 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1643 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1644 && GET_CODE (SET_DEST (temp)) == REG
1645 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1646 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1647 && GET_CODE (PATTERN (i3)) == SET
1648 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1649 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1650 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1651 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1652 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1654 HOST_WIDE_INT lo, hi;
1656 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1657 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1660 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1661 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1664 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1665 lo = INTVAL (SET_SRC (PATTERN (i3)));
1667 hi = INTVAL (SET_SRC (PATTERN (i3)));
1671 subst_low_cuid = INSN_CUID (i2);
1672 added_sets_2 = added_sets_1 = 0;
1673 i2dest = SET_DEST (temp);
1675 SUBST (SET_SRC (temp),
1676 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1678 newpat = PATTERN (i2);
1679 goto validate_replacement;
1683 /* If we have no I1 and I2 looks like:
1684 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1686 make up a dummy I1 that is
1689 (set (reg:CC X) (compare:CC Y (const_int 0)))
1691 (We can ignore any trailing CLOBBERs.)
1693 This undoes a previous combination and allows us to match a branch-and-
1696 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1697 && XVECLEN (PATTERN (i2), 0) >= 2
1698 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1699 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1701 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1702 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1703 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1704 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1705 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1706 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1708 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1709 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1714 /* We make I1 with the same INSN_UID as I2. This gives it
1715 the same INSN_CUID for value tracking. Our fake I1 will
1716 never appear in the insn stream so giving it the same INSN_UID
1717 as I2 will not cause a problem. */
1719 subst_prev_insn = i1
1720 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1721 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1724 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1725 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1726 SET_DEST (PATTERN (i1)));
1731 /* Verify that I2 and I1 are valid for combining. */
1732 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1733 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1739 /* Record whether I2DEST is used in I2SRC and similarly for the other
1740 cases. Knowing this will help in register status updating below. */
1741 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1742 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1743 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1745 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1747 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1749 /* Ensure that I3's pattern can be the destination of combines. */
1750 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1751 i1 && i2dest_in_i1src && i1_feeds_i3,
1758 /* See if any of the insns is a MULT operation. Unless one is, we will
1759 reject a combination that is, since it must be slower. Be conservative
1761 if (GET_CODE (i2src) == MULT
1762 || (i1 != 0 && GET_CODE (i1src) == MULT)
1763 || (GET_CODE (PATTERN (i3)) == SET
1764 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1767 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1768 We used to do this EXCEPT in one case: I3 has a post-inc in an
1769 output operand. However, that exception can give rise to insns like
1771 which is a famous insn on the PDP-11 where the value of r3 used as the
1772 source was model-dependent. Avoid this sort of thing. */
1775 if (!(GET_CODE (PATTERN (i3)) == SET
1776 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1777 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1778 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1779 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1780 /* It's not the exception. */
1783 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1784 if (REG_NOTE_KIND (link) == REG_INC
1785 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1787 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1794 /* See if the SETs in I1 or I2 need to be kept around in the merged
1795 instruction: whenever the value set there is still needed past I3.
1796 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1798 For the SET in I1, we have two cases: If I1 and I2 independently
1799 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1800 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1801 in I1 needs to be kept around unless I1DEST dies or is set in either
1802 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1803 I1DEST. If so, we know I1 feeds into I2. */
1805 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1808 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1809 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1811 /* If the set in I2 needs to be kept around, we must make a copy of
1812 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1813 PATTERN (I2), we are only substituting for the original I1DEST, not into
1814 an already-substituted copy. This also prevents making self-referential
1815 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1818 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1819 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1823 i2pat = copy_rtx (i2pat);
1827 /* Substitute in the latest insn for the regs set by the earlier ones. */
1829 maxreg = max_reg_num ();
1833 /* It is possible that the source of I2 or I1 may be performing an
1834 unneeded operation, such as a ZERO_EXTEND of something that is known
1835 to have the high part zero. Handle that case by letting subst look at
1836 the innermost one of them.
1838 Another way to do this would be to have a function that tries to
1839 simplify a single insn instead of merging two or more insns. We don't
1840 do this because of the potential of infinite loops and because
1841 of the potential extra memory required. However, doing it the way
1842 we are is a bit of a kludge and doesn't catch all cases.
1844 But only do this if -fexpensive-optimizations since it slows things down
1845 and doesn't usually win. */
1847 if (flag_expensive_optimizations)
1849 /* Pass pc_rtx so no substitutions are done, just simplifications.
1850 The cases that we are interested in here do not involve the few
1851 cases were is_replaced is checked. */
1854 subst_low_cuid = INSN_CUID (i1);
1855 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1859 subst_low_cuid = INSN_CUID (i2);
1860 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1863 undobuf.previous_undos = undobuf.undos;
1867 /* Many machines that don't use CC0 have insns that can both perform an
1868 arithmetic operation and set the condition code. These operations will
1869 be represented as a PARALLEL with the first element of the vector
1870 being a COMPARE of an arithmetic operation with the constant zero.
1871 The second element of the vector will set some pseudo to the result
1872 of the same arithmetic operation. If we simplify the COMPARE, we won't
1873 match such a pattern and so will generate an extra insn. Here we test
1874 for this case, where both the comparison and the operation result are
1875 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1876 I2SRC. Later we will make the PARALLEL that contains I2. */
1878 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1879 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1880 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1881 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1883 #ifdef EXTRA_CC_MODES
1885 enum machine_mode compare_mode;
1888 newpat = PATTERN (i3);
1889 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1893 #ifdef EXTRA_CC_MODES
1894 /* See if a COMPARE with the operand we substituted in should be done
1895 with the mode that is currently being used. If not, do the same
1896 processing we do in `subst' for a SET; namely, if the destination
1897 is used only once, try to replace it with a register of the proper
1898 mode and also replace the COMPARE. */
1899 if (undobuf.other_insn == 0
1900 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1901 &undobuf.other_insn))
1902 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1904 != GET_MODE (SET_DEST (newpat))))
1906 unsigned int regno = REGNO (SET_DEST (newpat));
1907 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1909 if (regno < FIRST_PSEUDO_REGISTER
1910 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1911 && ! REG_USERVAR_P (SET_DEST (newpat))))
1913 if (regno >= FIRST_PSEUDO_REGISTER)
1914 SUBST (regno_reg_rtx[regno], new_dest);
1916 SUBST (SET_DEST (newpat), new_dest);
1917 SUBST (XEXP (*cc_use, 0), new_dest);
1918 SUBST (SET_SRC (newpat),
1919 gen_rtx_combine (COMPARE, compare_mode,
1920 i2src, const0_rtx));
1923 undobuf.other_insn = 0;
1930 n_occurrences = 0; /* `subst' counts here */
1932 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1933 need to make a unique copy of I2SRC each time we substitute it
1934 to avoid self-referential rtl. */
1936 subst_low_cuid = INSN_CUID (i2);
1937 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1938 ! i1_feeds_i3 && i1dest_in_i1src);
1939 undobuf.previous_undos = undobuf.undos;
1941 /* Record whether i2's body now appears within i3's body. */
1942 i2_is_used = n_occurrences;
1945 /* If we already got a failure, don't try to do more. Otherwise,
1946 try to substitute in I1 if we have it. */
1948 if (i1 && GET_CODE (newpat) != CLOBBER)
1950 /* Before we can do this substitution, we must redo the test done
1951 above (see detailed comments there) that ensures that I1DEST
1952 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1954 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1962 subst_low_cuid = INSN_CUID (i1);
1963 newpat = subst (newpat, i1dest, i1src, 0, 0);
1964 undobuf.previous_undos = undobuf.undos;
1967 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1968 to count all the ways that I2SRC and I1SRC can be used. */
1969 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1970 && i2_is_used + added_sets_2 > 1)
1971 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1972 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1974 /* Fail if we tried to make a new register (we used to abort, but there's
1975 really no reason to). */
1976 || max_reg_num () != maxreg
1977 /* Fail if we couldn't do something and have a CLOBBER. */
1978 || GET_CODE (newpat) == CLOBBER
1979 /* Fail if this new pattern is a MULT and we didn't have one before
1980 at the outer level. */
1981 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1988 /* If the actions of the earlier insns must be kept
1989 in addition to substituting them into the latest one,
1990 we must make a new PARALLEL for the latest insn
1991 to hold additional the SETs. */
1993 if (added_sets_1 || added_sets_2)
1997 if (GET_CODE (newpat) == PARALLEL)
1999 rtvec old = XVEC (newpat, 0);
2000 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2001 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2002 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
2003 sizeof (old->elem[0]) * old->num_elem);
2008 total_sets = 1 + added_sets_1 + added_sets_2;
2009 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2010 XVECEXP (newpat, 0, 0) = old;
2014 XVECEXP (newpat, 0, --total_sets)
2015 = (GET_CODE (PATTERN (i1)) == PARALLEL
2016 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2020 /* If there is no I1, use I2's body as is. We used to also not do
2021 the subst call below if I2 was substituted into I3,
2022 but that could lose a simplification. */
2024 XVECEXP (newpat, 0, --total_sets) = i2pat;
2026 /* See comment where i2pat is assigned. */
2027 XVECEXP (newpat, 0, --total_sets)
2028 = subst (i2pat, i1dest, i1src, 0, 0);
2032 /* We come here when we are replacing a destination in I2 with the
2033 destination of I3. */
2034 validate_replacement:
2036 /* Note which hard regs this insn has as inputs. */
2037 mark_used_regs_combine (newpat);
2039 /* Is the result of combination a valid instruction? */
2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2042 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2043 the second SET's destination is a register that is unused. In that case,
2044 we just need the first SET. This can occur when simplifying a divmod
2045 insn. We *must* test for this case here because the code below that
2046 splits two independent SETs doesn't handle this case correctly when it
2047 updates the register status. Also check the case where the first
2048 SET's destination is unused. That would not cause incorrect code, but
2049 does cause an unneeded insn to remain. */
2051 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2056 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2058 && asm_noperands (newpat) < 0)
2060 newpat = XVECEXP (newpat, 0, 0);
2061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2064 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2065 && XVECLEN (newpat, 0) == 2
2066 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2067 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2068 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2069 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2070 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2071 && asm_noperands (newpat) < 0)
2073 newpat = XVECEXP (newpat, 0, 1);
2074 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If we were combining three insns and the result is a simple SET
2078 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2079 insns. There are two ways to do this. It can be split using a
2080 machine-specific method (like when you have an addition of a large
2081 constant) or by combine in the function find_split_point. */
2083 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2084 && asm_noperands (newpat) < 0)
2086 rtx m_split, *split;
2087 rtx ni2dest = i2dest;
2089 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2090 use I2DEST as a scratch register will help. In the latter case,
2091 convert I2DEST to the mode of the source of NEWPAT if we can. */
2093 m_split = split_insns (newpat, i3);
2095 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2096 inputs of NEWPAT. */
2098 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2099 possible to try that as a scratch reg. This would require adding
2100 more code to make it work though. */
2102 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2104 /* If I2DEST is a hard register or the only use of a pseudo,
2105 we can change its mode. */
2106 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2107 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2108 && GET_CODE (i2dest) == REG
2109 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2110 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2111 && ! REG_USERVAR_P (i2dest))))
2112 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2115 m_split = split_insns (gen_rtx_PARALLEL
2117 gen_rtvec (2, newpat,
2118 gen_rtx_CLOBBER (VOIDmode,
2123 if (m_split && GET_CODE (m_split) != SEQUENCE)
2125 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2126 if (insn_code_number >= 0)
2129 else if (m_split && GET_CODE (m_split) == SEQUENCE
2130 && XVECLEN (m_split, 0) == 2
2131 && (next_real_insn (i2) == i3
2132 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2136 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2137 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2139 i3set = single_set (XVECEXP (m_split, 0, 1));
2140 i2set = single_set (XVECEXP (m_split, 0, 0));
2142 /* In case we changed the mode of I2DEST, replace it in the
2143 pseudo-register table here. We can't do it above in case this
2144 code doesn't get executed and we do a split the other way. */
2146 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2147 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2149 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2151 /* If I2 or I3 has multiple SETs, we won't know how to track
2152 register status, so don't use these insns. If I2's destination
2153 is used between I2 and I3, we also can't use these insns. */
2155 if (i2_code_number >= 0 && i2set && i3set
2156 && (next_real_insn (i2) == i3
2157 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2158 insn_code_number = recog_for_combine (&newi3pat, i3,
2160 if (insn_code_number >= 0)
2163 /* It is possible that both insns now set the destination of I3.
2164 If so, we must show an extra use of it. */
2166 if (insn_code_number >= 0)
2168 rtx new_i3_dest = SET_DEST (i3set);
2169 rtx new_i2_dest = SET_DEST (i2set);
2171 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2172 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2173 || GET_CODE (new_i3_dest) == SUBREG)
2174 new_i3_dest = XEXP (new_i3_dest, 0);
2176 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2177 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2178 || GET_CODE (new_i2_dest) == SUBREG)
2179 new_i2_dest = XEXP (new_i2_dest, 0);
2181 if (GET_CODE (new_i3_dest) == REG
2182 && GET_CODE (new_i2_dest) == REG
2183 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2184 REG_N_SETS (REGNO (new_i2_dest))++;
2188 /* If we can split it and use I2DEST, go ahead and see if that
2189 helps things be recognized. Verify that none of the registers
2190 are set between I2 and I3. */
2191 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2193 && GET_CODE (i2dest) == REG
2195 /* We need I2DEST in the proper mode. If it is a hard register
2196 or the only use of a pseudo, we can change its mode. */
2197 && (GET_MODE (*split) == GET_MODE (i2dest)
2198 || GET_MODE (*split) == VOIDmode
2199 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2200 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2201 && ! REG_USERVAR_P (i2dest)))
2202 && (next_real_insn (i2) == i3
2203 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2204 /* We can't overwrite I2DEST if its value is still used by
2206 && ! reg_referenced_p (i2dest, newpat))
2208 rtx newdest = i2dest;
2209 enum rtx_code split_code = GET_CODE (*split);
2210 enum machine_mode split_mode = GET_MODE (*split);
2212 /* Get NEWDEST as a register in the proper mode. We have already
2213 validated that we can do this. */
2214 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2216 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2218 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2219 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2222 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2223 an ASHIFT. This can occur if it was inside a PLUS and hence
2224 appeared to be a memory address. This is a kludge. */
2225 if (split_code == MULT
2226 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2227 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2229 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2230 XEXP (*split, 0), GEN_INT (i)));
2231 /* Update split_code because we may not have a multiply
2233 split_code = GET_CODE (*split);
2236 #ifdef INSN_SCHEDULING
2237 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2238 be written as a ZERO_EXTEND. */
2239 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2240 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2244 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2245 SUBST (*split, newdest);
2246 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2248 /* If the split point was a MULT and we didn't have one before,
2249 don't use one now. */
2250 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2251 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2255 /* Check for a case where we loaded from memory in a narrow mode and
2256 then sign extended it, but we need both registers. In that case,
2257 we have a PARALLEL with both loads from the same memory location.
2258 We can split this into a load from memory followed by a register-register
2259 copy. This saves at least one insn, more if register allocation can
2262 We cannot do this if the destination of the second assignment is
2263 a register that we have already assumed is zero-extended. Similarly
2264 for a SUBREG of such a register. */
2266 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2267 && GET_CODE (newpat) == PARALLEL
2268 && XVECLEN (newpat, 0) == 2
2269 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2270 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2271 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2272 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2273 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2274 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2276 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2277 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2278 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2279 (GET_CODE (temp) == REG
2280 && reg_nonzero_bits[REGNO (temp)] != 0
2281 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2282 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2283 && (reg_nonzero_bits[REGNO (temp)]
2284 != GET_MODE_MASK (word_mode))))
2285 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2286 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2287 (GET_CODE (temp) == REG
2288 && reg_nonzero_bits[REGNO (temp)] != 0
2289 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2290 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2291 && (reg_nonzero_bits[REGNO (temp)]
2292 != GET_MODE_MASK (word_mode)))))
2293 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2294 SET_SRC (XVECEXP (newpat, 0, 1)))
2295 && ! find_reg_note (i3, REG_UNUSED,
2296 SET_DEST (XVECEXP (newpat, 0, 0))))
2300 newi2pat = XVECEXP (newpat, 0, 0);
2301 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2302 newpat = XVECEXP (newpat, 0, 1);
2303 SUBST (SET_SRC (newpat),
2304 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2305 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2307 if (i2_code_number >= 0)
2308 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2310 if (insn_code_number >= 0)
2315 /* If we will be able to accept this, we have made a change to the
2316 destination of I3. This can invalidate a LOG_LINKS pointing
2317 to I3. No other part of combine.c makes such a transformation.
2319 The new I3 will have a destination that was previously the
2320 destination of I1 or I2 and which was used in i2 or I3. Call
2321 distribute_links to make a LOG_LINK from the next use of
2322 that destination. */
2324 PATTERN (i3) = newpat;
2325 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2327 /* I3 now uses what used to be its destination and which is
2328 now I2's destination. That means we need a LOG_LINK from
2329 I3 to I2. But we used to have one, so we still will.
2331 However, some later insn might be using I2's dest and have
2332 a LOG_LINK pointing at I3. We must remove this link.
2333 The simplest way to remove the link is to point it at I1,
2334 which we know will be a NOTE. */
2336 for (insn = NEXT_INSN (i3);
2337 insn && (this_basic_block == n_basic_blocks - 1
2338 || insn != BLOCK_HEAD (this_basic_block + 1));
2339 insn = NEXT_INSN (insn))
2341 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2343 for (link = LOG_LINKS (insn); link;
2344 link = XEXP (link, 1))
2345 if (XEXP (link, 0) == i3)
2346 XEXP (link, 0) = i1;
2354 /* Similarly, check for a case where we have a PARALLEL of two independent
2355 SETs but we started with three insns. In this case, we can do the sets
2356 as two separate insns. This case occurs when some SET allows two
2357 other insns to combine, but the destination of that SET is still live. */
2359 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2360 && GET_CODE (newpat) == PARALLEL
2361 && XVECLEN (newpat, 0) == 2
2362 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2363 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2364 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2365 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2366 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2367 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2368 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2370 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2371 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2372 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2373 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2374 XVECEXP (newpat, 0, 0))
2375 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2376 XVECEXP (newpat, 0, 1))
2377 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2378 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2380 /* Normally, it doesn't matter which of the two is done first,
2381 but it does if one references cc0. In that case, it has to
2384 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2386 newi2pat = XVECEXP (newpat, 0, 0);
2387 newpat = XVECEXP (newpat, 0, 1);
2392 newi2pat = XVECEXP (newpat, 0, 1);
2393 newpat = XVECEXP (newpat, 0, 0);
2396 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2398 if (i2_code_number >= 0)
2399 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2402 /* If it still isn't recognized, fail and change things back the way they
2404 if ((insn_code_number < 0
2405 /* Is the result a reasonable ASM_OPERANDS? */
2406 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2412 /* If we had to change another insn, make sure it is valid also. */
2413 if (undobuf.other_insn)
2415 rtx other_pat = PATTERN (undobuf.other_insn);
2416 rtx new_other_notes;
2419 CLEAR_HARD_REG_SET (newpat_used_regs);
2421 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2424 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2430 PATTERN (undobuf.other_insn) = other_pat;
2432 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2433 are still valid. Then add any non-duplicate notes added by
2434 recog_for_combine. */
2435 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2437 next = XEXP (note, 1);
2439 if (REG_NOTE_KIND (note) == REG_UNUSED
2440 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2442 if (GET_CODE (XEXP (note, 0)) == REG)
2443 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2445 remove_note (undobuf.other_insn, note);
2449 for (note = new_other_notes; note; note = XEXP (note, 1))
2450 if (GET_CODE (XEXP (note, 0)) == REG)
2451 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2453 distribute_notes (new_other_notes, undobuf.other_insn,
2454 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2457 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2458 they are adjacent to each other or not. */
2460 rtx p = prev_nonnote_insn (i3);
2461 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2462 && sets_cc0_p (newi2pat))
2470 /* We now know that we can do this combination. Merge the insns and
2471 update the status of registers and LOG_LINKS. */
2474 rtx i3notes, i2notes, i1notes = 0;
2475 rtx i3links, i2links, i1links = 0;
2478 /* Compute which registers we expect to eliminate. newi2pat may be setting
2479 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2480 same as i3dest, in which case newi2pat may be setting i1dest. */
2481 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2482 || i2dest_in_i2src || i2dest_in_i1src
2484 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2485 || (newi2pat && reg_set_p (i1dest, newi2pat))
2488 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2490 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2491 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2493 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2495 /* Ensure that we do not have something that should not be shared but
2496 occurs multiple times in the new insns. Check this by first
2497 resetting all the `used' flags and then copying anything is shared. */
2499 reset_used_flags (i3notes);
2500 reset_used_flags (i2notes);
2501 reset_used_flags (i1notes);
2502 reset_used_flags (newpat);
2503 reset_used_flags (newi2pat);
2504 if (undobuf.other_insn)
2505 reset_used_flags (PATTERN (undobuf.other_insn));
2507 i3notes = copy_rtx_if_shared (i3notes);
2508 i2notes = copy_rtx_if_shared (i2notes);
2509 i1notes = copy_rtx_if_shared (i1notes);
2510 newpat = copy_rtx_if_shared (newpat);
2511 newi2pat = copy_rtx_if_shared (newi2pat);
2512 if (undobuf.other_insn)
2513 reset_used_flags (PATTERN (undobuf.other_insn));
2515 INSN_CODE (i3) = insn_code_number;
2516 PATTERN (i3) = newpat;
2517 if (undobuf.other_insn)
2518 INSN_CODE (undobuf.other_insn) = other_code_number;
2520 /* We had one special case above where I2 had more than one set and
2521 we replaced a destination of one of those sets with the destination
2522 of I3. In that case, we have to update LOG_LINKS of insns later
2523 in this basic block. Note that this (expensive) case is rare.
2525 Also, in this case, we must pretend that all REG_NOTEs for I2
2526 actually came from I3, so that REG_UNUSED notes from I2 will be
2527 properly handled. */
2529 if (i3_subst_into_i2)
2531 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2532 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2533 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2534 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2535 && ! find_reg_note (i2, REG_UNUSED,
2536 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2537 for (temp = NEXT_INSN (i2);
2538 temp && (this_basic_block == n_basic_blocks - 1
2539 || BLOCK_HEAD (this_basic_block) != temp);
2540 temp = NEXT_INSN (temp))
2541 if (temp != i3 && INSN_P (temp))
2542 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2543 if (XEXP (link, 0) == i2)
2544 XEXP (link, 0) = i3;
2549 while (XEXP (link, 1))
2550 link = XEXP (link, 1);
2551 XEXP (link, 1) = i2notes;
2565 INSN_CODE (i2) = i2_code_number;
2566 PATTERN (i2) = newi2pat;
2570 PUT_CODE (i2, NOTE);
2571 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2572 NOTE_SOURCE_FILE (i2) = 0;
2579 PUT_CODE (i1, NOTE);
2580 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2581 NOTE_SOURCE_FILE (i1) = 0;
2584 /* Get death notes for everything that is now used in either I3 or
2585 I2 and used to die in a previous insn. If we built two new
2586 patterns, move from I1 to I2 then I2 to I3 so that we get the
2587 proper movement on registers that I2 modifies. */
2591 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2592 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2595 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2598 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2600 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2603 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2606 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2609 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2612 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2613 know these are REG_UNUSED and want them to go to the desired insn,
2614 so we always pass it as i3. We have not counted the notes in
2615 reg_n_deaths yet, so we need to do so now. */
2617 if (newi2pat && new_i2_notes)
2619 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2620 if (GET_CODE (XEXP (temp, 0)) == REG)
2621 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2623 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2628 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2629 if (GET_CODE (XEXP (temp, 0)) == REG)
2630 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2632 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2635 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2636 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2637 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2638 in that case, it might delete I2. Similarly for I2 and I1.
2639 Show an additional death due to the REG_DEAD note we make here. If
2640 we discard it in distribute_notes, we will decrement it again. */
2644 if (GET_CODE (i3dest_killed) == REG)
2645 REG_N_DEATHS (REGNO (i3dest_killed))++;
2647 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2648 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2650 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2654 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2658 if (i2dest_in_i2src)
2660 if (GET_CODE (i2dest) == REG)
2661 REG_N_DEATHS (REGNO (i2dest))++;
2663 if (newi2pat && reg_set_p (i2dest, newi2pat))
2664 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2665 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2668 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2669 NULL_RTX, NULL_RTX);
2672 if (i1dest_in_i1src)
2674 if (GET_CODE (i1dest) == REG)
2675 REG_N_DEATHS (REGNO (i1dest))++;
2677 if (newi2pat && reg_set_p (i1dest, newi2pat))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2679 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2682 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2683 NULL_RTX, NULL_RTX);
2686 distribute_links (i3links);
2687 distribute_links (i2links);
2688 distribute_links (i1links);
2690 if (GET_CODE (i2dest) == REG)
2693 rtx i2_insn = 0, i2_val = 0, set;
2695 /* The insn that used to set this register doesn't exist, and
2696 this life of the register may not exist either. See if one of
2697 I3's links points to an insn that sets I2DEST. If it does,
2698 that is now the last known value for I2DEST. If we don't update
2699 this and I2 set the register to a value that depended on its old
2700 contents, we will get confused. If this insn is used, thing
2701 will be set correctly in combine_instructions. */
2703 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2704 if ((set = single_set (XEXP (link, 0))) != 0
2705 && rtx_equal_p (i2dest, SET_DEST (set)))
2706 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2708 record_value_for_reg (i2dest, i2_insn, i2_val);
2710 /* If the reg formerly set in I2 died only once and that was in I3,
2711 zero its use count so it won't make `reload' do any work. */
2713 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2714 && ! i2dest_in_i2src)
2716 regno = REGNO (i2dest);
2717 REG_N_SETS (regno)--;
2721 if (i1 && GET_CODE (i1dest) == REG)
2724 rtx i1_insn = 0, i1_val = 0, set;
2726 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2727 if ((set = single_set (XEXP (link, 0))) != 0
2728 && rtx_equal_p (i1dest, SET_DEST (set)))
2729 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2731 record_value_for_reg (i1dest, i1_insn, i1_val);
2733 regno = REGNO (i1dest);
2734 if (! added_sets_1 && ! i1dest_in_i1src)
2735 REG_N_SETS (regno)--;
2738 /* Update reg_nonzero_bits et al for any changes that may have been made
2739 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2740 important. Because newi2pat can affect nonzero_bits of newpat */
2742 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2743 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2745 /* Set new_direct_jump_p if a new return or simple jump instruction
2748 If I3 is now an unconditional jump, ensure that it has a
2749 BARRIER following it since it may have initially been a
2750 conditional jump. It may also be the last nonnote insn. */
2752 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2754 *new_direct_jump_p = 1;
2756 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2757 || GET_CODE (temp) != BARRIER)
2758 emit_barrier_after (i3);
2762 combine_successes++;
2765 /* Clear this here, so that subsequent get_last_value calls are not
2767 subst_prev_insn = NULL_RTX;
2769 if (added_links_insn
2770 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2771 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2772 return added_links_insn;
2774 return newi2pat ? i2 : i3;
2777 /* Undo all the modifications recorded in undobuf. */
2782 struct undo *undo, *next;
2784 for (undo = undobuf.undos; undo; undo = next)
2788 *undo->where.i = undo->old_contents.i;
2790 *undo->where.r = undo->old_contents.r;
2792 undo->next = undobuf.frees;
2793 undobuf.frees = undo;
2796 undobuf.undos = undobuf.previous_undos = 0;
2798 /* Clear this here, so that subsequent get_last_value calls are not
2800 subst_prev_insn = NULL_RTX;
2803 /* We've committed to accepting the changes we made. Move all
2804 of the undos to the free list. */
2809 struct undo *undo, *next;
2811 for (undo = undobuf.undos; undo; undo = next)
2814 undo->next = undobuf.frees;
2815 undobuf.frees = undo;
2817 undobuf.undos = undobuf.previous_undos = 0;
2821 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2822 where we have an arithmetic expression and return that point. LOC will
2825 try_combine will call this function to see if an insn can be split into
2829 find_split_point (loc, insn)
2834 enum rtx_code code = GET_CODE (x);
2836 unsigned HOST_WIDE_INT len = 0;
2837 HOST_WIDE_INT pos = 0;
2839 rtx inner = NULL_RTX;
2841 /* First special-case some codes. */
2845 #ifdef INSN_SCHEDULING
2846 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2848 if (GET_CODE (SUBREG_REG (x)) == MEM)
2851 return find_split_point (&SUBREG_REG (x), insn);
2855 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2856 using LO_SUM and HIGH. */
2857 if (GET_CODE (XEXP (x, 0)) == CONST
2858 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2861 gen_rtx_combine (LO_SUM, Pmode,
2862 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2864 return &XEXP (XEXP (x, 0), 0);
2868 /* If we have a PLUS whose second operand is a constant and the
2869 address is not valid, perhaps will can split it up using
2870 the machine-specific way to split large constants. We use
2871 the first pseudo-reg (one of the virtual regs) as a placeholder;
2872 it will not remain in the result. */
2873 if (GET_CODE (XEXP (x, 0)) == PLUS
2874 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2875 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2877 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2878 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2881 /* This should have produced two insns, each of which sets our
2882 placeholder. If the source of the second is a valid address,
2883 we can make put both sources together and make a split point
2886 if (seq && XVECLEN (seq, 0) == 2
2887 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2888 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2889 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2890 && ! reg_mentioned_p (reg,
2891 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2892 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2893 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2894 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2895 && memory_address_p (GET_MODE (x),
2896 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2898 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2899 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2901 /* Replace the placeholder in SRC2 with SRC1. If we can
2902 find where in SRC2 it was placed, that can become our
2903 split point and we can replace this address with SRC2.
2904 Just try two obvious places. */
2906 src2 = replace_rtx (src2, reg, src1);
2908 if (XEXP (src2, 0) == src1)
2909 split = &XEXP (src2, 0);
2910 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2911 && XEXP (XEXP (src2, 0), 0) == src1)
2912 split = &XEXP (XEXP (src2, 0), 0);
2916 SUBST (XEXP (x, 0), src2);
2921 /* If that didn't work, perhaps the first operand is complex and
2922 needs to be computed separately, so make a split point there.
2923 This will occur on machines that just support REG + CONST
2924 and have a constant moved through some previous computation. */
2926 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2927 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2928 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2930 return &XEXP (XEXP (x, 0), 0);
2936 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2937 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2938 we need to put the operand into a register. So split at that
2941 if (SET_DEST (x) == cc0_rtx
2942 && GET_CODE (SET_SRC (x)) != COMPARE
2943 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2944 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2945 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2946 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2947 return &SET_SRC (x);
2950 /* See if we can split SET_SRC as it stands. */
2951 split = find_split_point (&SET_SRC (x), insn);
2952 if (split && split != &SET_SRC (x))
2955 /* See if we can split SET_DEST as it stands. */
2956 split = find_split_point (&SET_DEST (x), insn);
2957 if (split && split != &SET_DEST (x))
2960 /* See if this is a bitfield assignment with everything constant. If
2961 so, this is an IOR of an AND, so split it into that. */
2962 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2963 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2964 <= HOST_BITS_PER_WIDE_INT)
2965 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2966 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2967 && GET_CODE (SET_SRC (x)) == CONST_INT
2968 && ((INTVAL (XEXP (SET_DEST (x), 1))
2969 + INTVAL (XEXP (SET_DEST (x), 2)))
2970 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2971 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2973 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2974 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2975 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2976 rtx dest = XEXP (SET_DEST (x), 0);
2977 enum machine_mode mode = GET_MODE (dest);
2978 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2980 if (BITS_BIG_ENDIAN)
2981 pos = GET_MODE_BITSIZE (mode) - len - pos;
2985 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2988 gen_binary (IOR, mode,
2989 gen_binary (AND, mode, dest,
2990 GEN_INT (~(mask << pos)
2991 & GET_MODE_MASK (mode))),
2992 GEN_INT (src << pos)));
2994 SUBST (SET_DEST (x), dest);
2996 split = find_split_point (&SET_SRC (x), insn);
2997 if (split && split != &SET_SRC (x))
3001 /* Otherwise, see if this is an operation that we can split into two.
3002 If so, try to split that. */
3003 code = GET_CODE (SET_SRC (x));
3008 /* If we are AND'ing with a large constant that is only a single
3009 bit and the result is only being used in a context where we
3010 need to know if it is zero or non-zero, replace it with a bit
3011 extraction. This will avoid the large constant, which might
3012 have taken more than one insn to make. If the constant were
3013 not a valid argument to the AND but took only one insn to make,
3014 this is no worse, but if it took more than one insn, it will
3017 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3018 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3019 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3020 && GET_CODE (SET_DEST (x)) == REG
3021 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3022 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3023 && XEXP (*split, 0) == SET_DEST (x)
3024 && XEXP (*split, 1) == const0_rtx)
3026 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3027 XEXP (SET_SRC (x), 0),
3028 pos, NULL_RTX, 1, 1, 0, 0);
3029 if (extraction != 0)
3031 SUBST (SET_SRC (x), extraction);
3032 return find_split_point (loc, insn);
3038 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3039 is known to be on, this can be converted into a NEG of a shift. */
3040 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3041 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3042 && 1 <= (pos = exact_log2
3043 (nonzero_bits (XEXP (SET_SRC (x), 0),
3044 GET_MODE (XEXP (SET_SRC (x), 0))))))
3046 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3049 gen_rtx_combine (NEG, mode,
3050 gen_rtx_combine (LSHIFTRT, mode,
3051 XEXP (SET_SRC (x), 0),
3054 split = find_split_point (&SET_SRC (x), insn);
3055 if (split && split != &SET_SRC (x))
3061 inner = XEXP (SET_SRC (x), 0);
3063 /* We can't optimize if either mode is a partial integer
3064 mode as we don't know how many bits are significant
3066 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3067 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3071 len = GET_MODE_BITSIZE (GET_MODE (inner));
3077 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3078 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3080 inner = XEXP (SET_SRC (x), 0);
3081 len = INTVAL (XEXP (SET_SRC (x), 1));
3082 pos = INTVAL (XEXP (SET_SRC (x), 2));
3084 if (BITS_BIG_ENDIAN)
3085 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3086 unsignedp = (code == ZERO_EXTRACT);
3094 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3096 enum machine_mode mode = GET_MODE (SET_SRC (x));
3098 /* For unsigned, we have a choice of a shift followed by an
3099 AND or two shifts. Use two shifts for field sizes where the
3100 constant might be too large. We assume here that we can
3101 always at least get 8-bit constants in an AND insn, which is
3102 true for every current RISC. */
3104 if (unsignedp && len <= 8)
3109 gen_rtx_combine (LSHIFTRT, mode,
3110 gen_lowpart_for_combine (mode, inner),
3112 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3114 split = find_split_point (&SET_SRC (x), insn);
3115 if (split && split != &SET_SRC (x))
3122 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3123 gen_rtx_combine (ASHIFT, mode,
3124 gen_lowpart_for_combine (mode, inner),
3125 GEN_INT (GET_MODE_BITSIZE (mode)
3127 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3129 split = find_split_point (&SET_SRC (x), insn);
3130 if (split && split != &SET_SRC (x))
3135 /* See if this is a simple operation with a constant as the second
3136 operand. It might be that this constant is out of range and hence
3137 could be used as a split point. */
3138 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3139 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3140 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3141 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3142 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3143 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3144 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3146 return &XEXP (SET_SRC (x), 1);
3148 /* Finally, see if this is a simple operation with its first operand
3149 not in a register. The operation might require this operand in a
3150 register, so return it as a split point. We can always do this
3151 because if the first operand were another operation, we would have
3152 already found it as a split point. */
3153 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3154 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3155 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3156 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3157 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3158 return &XEXP (SET_SRC (x), 0);
3164 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3165 it is better to write this as (not (ior A B)) so we can split it.
3166 Similarly for IOR. */
3167 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3170 gen_rtx_combine (NOT, GET_MODE (x),
3171 gen_rtx_combine (code == IOR ? AND : IOR,
3173 XEXP (XEXP (x, 0), 0),
3174 XEXP (XEXP (x, 1), 0))));
3175 return find_split_point (loc, insn);
3178 /* Many RISC machines have a large set of logical insns. If the
3179 second operand is a NOT, put it first so we will try to split the
3180 other operand first. */
3181 if (GET_CODE (XEXP (x, 1)) == NOT)
3183 rtx tem = XEXP (x, 0);
3184 SUBST (XEXP (x, 0), XEXP (x, 1));
3185 SUBST (XEXP (x, 1), tem);
3193 /* Otherwise, select our actions depending on our rtx class. */
3194 switch (GET_RTX_CLASS (code))
3196 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3198 split = find_split_point (&XEXP (x, 2), insn);
3201 /* ... fall through ... */
3205 split = find_split_point (&XEXP (x, 1), insn);
3208 /* ... fall through ... */
3210 /* Some machines have (and (shift ...) ...) insns. If X is not
3211 an AND, but XEXP (X, 0) is, use it as our split point. */
3212 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3213 return &XEXP (x, 0);
3215 split = find_split_point (&XEXP (x, 0), insn);
3221 /* Otherwise, we don't have a split point. */
3225 /* Throughout X, replace FROM with TO, and return the result.
3226 The result is TO if X is FROM;
3227 otherwise the result is X, but its contents may have been modified.
3228 If they were modified, a record was made in undobuf so that
3229 undo_all will (among other things) return X to its original state.
3231 If the number of changes necessary is too much to record to undo,
3232 the excess changes are not made, so the result is invalid.
3233 The changes already made can still be undone.
3234 undobuf.num_undo is incremented for such changes, so by testing that
3235 the caller can tell whether the result is valid.
3237 `n_occurrences' is incremented each time FROM is replaced.
3239 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3241 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3242 by copying if `n_occurrences' is non-zero. */
3245 subst (x, from, to, in_dest, unique_copy)
3246 register rtx x, from, to;
3250 register enum rtx_code code = GET_CODE (x);
3251 enum machine_mode op0_mode = VOIDmode;
3252 register const char *fmt;
3253 register int len, i;
3256 /* Two expressions are equal if they are identical copies of a shared
3257 RTX or if they are both registers with the same register number
3260 #define COMBINE_RTX_EQUAL_P(X,Y) \
3262 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3263 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3265 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3268 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3271 /* If X and FROM are the same register but different modes, they will
3272 not have been seen as equal above. However, flow.c will make a
3273 LOG_LINKS entry for that case. If we do nothing, we will try to
3274 rerecognize our original insn and, when it succeeds, we will
3275 delete the feeding insn, which is incorrect.
3277 So force this insn not to match in this (rare) case. */
3278 if (! in_dest && code == REG && GET_CODE (from) == REG
3279 && REGNO (x) == REGNO (from))
3280 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3282 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3283 of which may contain things that can be combined. */
3284 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3287 /* It is possible to have a subexpression appear twice in the insn.
3288 Suppose that FROM is a register that appears within TO.
3289 Then, after that subexpression has been scanned once by `subst',
3290 the second time it is scanned, TO may be found. If we were
3291 to scan TO here, we would find FROM within it and create a
3292 self-referent rtl structure which is completely wrong. */
3293 if (COMBINE_RTX_EQUAL_P (x, to))
3296 /* Parallel asm_operands need special attention because all of the
3297 inputs are shared across the arms. Furthermore, unsharing the
3298 rtl results in recognition failures. Failure to handle this case
3299 specially can result in circular rtl.
3301 Solve this by doing a normal pass across the first entry of the
3302 parallel, and only processing the SET_DESTs of the subsequent
3305 if (code == PARALLEL
3306 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3307 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3309 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3311 /* If this substitution failed, this whole thing fails. */
3312 if (GET_CODE (new) == CLOBBER
3313 && XEXP (new, 0) == const0_rtx)
3316 SUBST (XVECEXP (x, 0, 0), new);
3318 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3320 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3322 if (GET_CODE (dest) != REG
3323 && GET_CODE (dest) != CC0
3324 && GET_CODE (dest) != PC)
3326 new = subst (dest, from, to, 0, unique_copy);
3328 /* If this substitution failed, this whole thing fails. */
3329 if (GET_CODE (new) == CLOBBER
3330 && XEXP (new, 0) == const0_rtx)
3333 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3339 len = GET_RTX_LENGTH (code);
3340 fmt = GET_RTX_FORMAT (code);
3342 /* We don't need to process a SET_DEST that is a register, CC0,
3343 or PC, so set up to skip this common case. All other cases
3344 where we want to suppress replacing something inside a
3345 SET_SRC are handled via the IN_DEST operand. */
3347 && (GET_CODE (SET_DEST (x)) == REG
3348 || GET_CODE (SET_DEST (x)) == CC0
3349 || GET_CODE (SET_DEST (x)) == PC))
3352 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3355 op0_mode = GET_MODE (XEXP (x, 0));
3357 for (i = 0; i < len; i++)
3362 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3364 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3366 new = (unique_copy && n_occurrences
3367 ? copy_rtx (to) : to);
3372 new = subst (XVECEXP (x, i, j), from, to, 0,
3375 /* If this substitution failed, this whole thing
3377 if (GET_CODE (new) == CLOBBER
3378 && XEXP (new, 0) == const0_rtx)
3382 SUBST (XVECEXP (x, i, j), new);
3385 else if (fmt[i] == 'e')
3387 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3389 /* In general, don't install a subreg involving two
3390 modes not tieable. It can worsen register
3391 allocation, and can even make invalid reload
3392 insns, since the reg inside may need to be copied
3393 from in the outside mode, and that may be invalid
3394 if it is an fp reg copied in integer mode.
3396 We allow two exceptions to this: It is valid if
3397 it is inside another SUBREG and the mode of that
3398 SUBREG and the mode of the inside of TO is
3399 tieable and it is valid if X is a SET that copies
3402 if (GET_CODE (to) == SUBREG
3403 && ! MODES_TIEABLE_P (GET_MODE (to),
3404 GET_MODE (SUBREG_REG (to)))
3405 && ! (code == SUBREG
3406 && MODES_TIEABLE_P (GET_MODE (x),
3407 GET_MODE (SUBREG_REG (to))))
3409 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3412 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3414 #ifdef CLASS_CANNOT_CHANGE_MODE
3416 && GET_CODE (to) == REG
3417 && REGNO (to) < FIRST_PSEUDO_REGISTER
3418 && (TEST_HARD_REG_BIT
3419 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3421 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3423 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3426 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3430 /* If we are in a SET_DEST, suppress most cases unless we
3431 have gone inside a MEM, in which case we want to
3432 simplify the address. We assume here that things that
3433 are actually part of the destination have their inner
3434 parts in the first expression. This is true for SUBREG,
3435 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3436 things aside from REG and MEM that should appear in a
3438 new = subst (XEXP (x, i), from, to,
3440 && (code == SUBREG || code == STRICT_LOW_PART
3441 || code == ZERO_EXTRACT))
3443 && i == 0), unique_copy);
3445 /* If we found that we will have to reject this combination,
3446 indicate that by returning the CLOBBER ourselves, rather than
3447 an expression containing it. This will speed things up as
3448 well as prevent accidents where two CLOBBERs are considered
3449 to be equal, thus producing an incorrect simplification. */
3451 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3454 SUBST (XEXP (x, i), new);
3459 /* Try to simplify X. If the simplification changed the code, it is likely
3460 that further simplification will help, so loop, but limit the number
3461 of repetitions that will be performed. */
3463 for (i = 0; i < 4; i++)
3465 /* If X is sufficiently simple, don't bother trying to do anything
3467 if (code != CONST_INT && code != REG && code != CLOBBER)
3468 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3470 if (GET_CODE (x) == code)
3473 code = GET_CODE (x);
3475 /* We no longer know the original mode of operand 0 since we
3476 have changed the form of X) */
3477 op0_mode = VOIDmode;
3483 /* Simplify X, a piece of RTL. We just operate on the expression at the
3484 outer level; call `subst' to simplify recursively. Return the new
3487 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3488 will be the iteration even if an expression with a code different from
3489 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3492 combine_simplify_rtx (x, op0_mode, last, in_dest)
3494 enum machine_mode op0_mode;
3498 enum rtx_code code = GET_CODE (x);
3499 enum machine_mode mode = GET_MODE (x);
3504 /* If this is a commutative operation, put a constant last and a complex
3505 expression first. We don't need to do this for comparisons here. */
3506 if (GET_RTX_CLASS (code) == 'c'
3507 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3508 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3509 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3510 || (GET_CODE (XEXP (x, 0)) == SUBREG
3511 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3512 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3515 SUBST (XEXP (x, 0), XEXP (x, 1));
3516 SUBST (XEXP (x, 1), temp);
3519 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3520 sign extension of a PLUS with a constant, reverse the order of the sign
3521 extension and the addition. Note that this not the same as the original
3522 code, but overflow is undefined for signed values. Also note that the
3523 PLUS will have been partially moved "inside" the sign-extension, so that
3524 the first operand of X will really look like:
3525 (ashiftrt (plus (ashift A C4) C5) C4).
3527 (plus (ashiftrt (ashift A C4) C2) C4)
3528 and replace the first operand of X with that expression. Later parts
3529 of this function may simplify the expression further.
3531 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3532 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3533 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3535 We do this to simplify address expressions. */
3537 if ((code == PLUS || code == MINUS || code == MULT)
3538 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3539 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3540 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3541 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3542 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3543 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3544 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3545 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3546 XEXP (XEXP (XEXP (x, 0), 0), 1),
3547 XEXP (XEXP (x, 0), 1))) != 0)
3550 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3551 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3552 INTVAL (XEXP (XEXP (x, 0), 1)));
3554 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3555 INTVAL (XEXP (XEXP (x, 0), 1)));
3557 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3560 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3561 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3562 things. Check for cases where both arms are testing the same
3565 Don't do anything if all operands are very simple. */
3567 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3568 || GET_RTX_CLASS (code) == '<')
3569 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3570 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3571 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3573 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3574 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3575 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3577 || (GET_RTX_CLASS (code) == '1'
3578 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3579 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3580 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3583 rtx cond, true, false;
3585 cond = if_then_else_cond (x, &true, &false);
3587 /* If everything is a comparison, what we have is highly unlikely
3588 to be simpler, so don't use it. */
3589 && ! (GET_RTX_CLASS (code) == '<'
3590 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3591 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3593 rtx cop1 = const0_rtx;
3594 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3596 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3599 /* Simplify the alternative arms; this may collapse the true and
3600 false arms to store-flag values. */
3601 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3602 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3604 /* If true and false are not general_operands, an if_then_else
3605 is unlikely to be simpler. */
3606 if (general_operand (true, VOIDmode)
3607 && general_operand (false, VOIDmode))
3609 /* Restarting if we generate a store-flag expression will cause
3610 us to loop. Just drop through in this case. */
3612 /* If the result values are STORE_FLAG_VALUE and zero, we can
3613 just make the comparison operation. */
3614 if (true == const_true_rtx && false == const0_rtx)
3615 x = gen_binary (cond_code, mode, cond, cop1);
3616 else if (true == const0_rtx && false == const_true_rtx)
3617 x = gen_binary (reverse_condition (cond_code),
3620 /* Likewise, we can make the negate of a comparison operation
3621 if the result values are - STORE_FLAG_VALUE and zero. */
3622 else if (GET_CODE (true) == CONST_INT
3623 && INTVAL (true) == - STORE_FLAG_VALUE
3624 && false == const0_rtx)
3625 x = gen_unary (NEG, mode, mode,
3626 gen_binary (cond_code, mode, cond, cop1));
3627 else if (GET_CODE (false) == CONST_INT
3628 && INTVAL (false) == - STORE_FLAG_VALUE
3629 && true == const0_rtx)
3630 x = gen_unary (NEG, mode, mode,
3631 gen_binary (reverse_condition (cond_code),
3634 return gen_rtx_IF_THEN_ELSE (mode,
3635 gen_binary (cond_code, VOIDmode,
3639 code = GET_CODE (x);
3640 op0_mode = VOIDmode;
3645 /* Try to fold this expression in case we have constants that weren't
3648 switch (GET_RTX_CLASS (code))
3651 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3655 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3656 if (cmp_mode == VOIDmode)
3658 cmp_mode = GET_MODE (XEXP (x, 1));
3659 if (cmp_mode == VOIDmode)
3660 cmp_mode = op0_mode;
3662 temp = simplify_relational_operation (code, cmp_mode,
3663 XEXP (x, 0), XEXP (x, 1));
3665 #ifdef FLOAT_STORE_FLAG_VALUE
3666 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3668 if (temp == const0_rtx)
3669 temp = CONST0_RTX (mode);
3671 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3677 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3681 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3682 XEXP (x, 1), XEXP (x, 2));
3687 x = temp, code = GET_CODE (temp);
3689 /* First see if we can apply the inverse distributive law. */
3690 if (code == PLUS || code == MINUS
3691 || code == AND || code == IOR || code == XOR)
3693 x = apply_distributive_law (x);
3694 code = GET_CODE (x);
3697 /* If CODE is an associative operation not otherwise handled, see if we
3698 can associate some operands. This can win if they are constants or
3699 if they are logically related (i.e. (a & b) & a. */
3700 if ((code == PLUS || code == MINUS
3701 || code == MULT || code == AND || code == IOR || code == XOR
3702 || code == DIV || code == UDIV
3703 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3704 && INTEGRAL_MODE_P (mode))
3706 if (GET_CODE (XEXP (x, 0)) == code)
3708 rtx other = XEXP (XEXP (x, 0), 0);
3709 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3710 rtx inner_op1 = XEXP (x, 1);
3713 /* Make sure we pass the constant operand if any as the second
3714 one if this is a commutative operation. */
3715 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3717 rtx tem = inner_op0;
3718 inner_op0 = inner_op1;
3721 inner = simplify_binary_operation (code == MINUS ? PLUS
3722 : code == DIV ? MULT
3723 : code == UDIV ? MULT
3725 mode, inner_op0, inner_op1);
3727 /* For commutative operations, try the other pair if that one
3729 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3731 other = XEXP (XEXP (x, 0), 1);
3732 inner = simplify_binary_operation (code, mode,
3733 XEXP (XEXP (x, 0), 0),
3738 return gen_binary (code, mode, other, inner);
3742 /* A little bit of algebraic simplification here. */
3746 /* Ensure that our address has any ASHIFTs converted to MULT in case
3747 address-recognizing predicates are called later. */
3748 temp = make_compound_operation (XEXP (x, 0), MEM);
3749 SUBST (XEXP (x, 0), temp);
3753 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3754 is paradoxical. If we can't do that safely, then it becomes
3755 something nonsensical so that this combination won't take place. */
3757 if (GET_CODE (SUBREG_REG (x)) == MEM
3758 && (GET_MODE_SIZE (mode)
3759 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3761 rtx inner = SUBREG_REG (x);
3762 int endian_offset = 0;
3763 /* Don't change the mode of the MEM
3764 if that would change the meaning of the address. */
3765 if (MEM_VOLATILE_P (SUBREG_REG (x))
3766 || mode_dependent_address_p (XEXP (inner, 0)))
3767 return gen_rtx_CLOBBER (mode, const0_rtx);
3769 if (BYTES_BIG_ENDIAN)
3771 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3772 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3773 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3774 endian_offset -= (UNITS_PER_WORD
3775 - GET_MODE_SIZE (GET_MODE (inner)));
3777 /* Note if the plus_constant doesn't make a valid address
3778 then this combination won't be accepted. */
3779 x = gen_rtx_MEM (mode,
3780 plus_constant (XEXP (inner, 0),
3781 (SUBREG_WORD (x) * UNITS_PER_WORD
3783 MEM_COPY_ATTRIBUTES (x, inner);
3787 /* If we are in a SET_DEST, these other cases can't apply. */
3791 /* Changing mode twice with SUBREG => just change it once,
3792 or not at all if changing back to starting mode. */
3793 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3795 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3796 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3797 return SUBREG_REG (SUBREG_REG (x));
3799 SUBST_INT (SUBREG_WORD (x),
3800 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3801 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3804 /* SUBREG of a hard register => just change the register number
3805 and/or mode. If the hard register is not valid in that mode,
3806 suppress this combination. If the hard register is the stack,
3807 frame, or argument pointer, leave this as a SUBREG. */
3809 if (GET_CODE (SUBREG_REG (x)) == REG
3810 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3811 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3812 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3813 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3815 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3816 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3818 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3820 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3822 return gen_rtx_REG (mode,
3823 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3825 return gen_rtx_CLOBBER (mode, const0_rtx);
3828 /* For a constant, try to pick up the part we want. Handle a full
3829 word and low-order part. Only do this if we are narrowing
3830 the constant; if it is being widened, we have no idea what
3831 the extra bits will have been set to. */
3833 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3834 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3835 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3836 && GET_MODE_CLASS (mode) == MODE_INT)
3838 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3844 /* If we want a subreg of a constant, at offset 0,
3845 take the low bits. On a little-endian machine, that's
3846 always valid. On a big-endian machine, it's valid
3847 only if the constant's mode fits in one word. Note that we
3848 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3849 if (CONSTANT_P (SUBREG_REG (x))
3850 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3851 || ! WORDS_BIG_ENDIAN)
3852 ? SUBREG_WORD (x) == 0
3854 == ((GET_MODE_SIZE (op0_mode)
3855 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3857 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3858 && (! WORDS_BIG_ENDIAN
3859 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3860 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3862 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3863 since we are saying that the high bits don't matter. */
3864 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3865 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3867 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3868 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3869 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3870 return SUBREG_REG (x);
3873 /* Note that we cannot do any narrowing for non-constants since
3874 we might have been counting on using the fact that some bits were
3875 zero. We now do this in the SET. */
3880 /* (not (plus X -1)) can become (neg X). */
3881 if (GET_CODE (XEXP (x, 0)) == PLUS
3882 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3883 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3885 /* Similarly, (not (neg X)) is (plus X -1). */
3886 if (GET_CODE (XEXP (x, 0)) == NEG)
3887 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3890 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3891 if (GET_CODE (XEXP (x, 0)) == XOR
3892 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3893 && (temp = simplify_unary_operation (NOT, mode,
3894 XEXP (XEXP (x, 0), 1),
3896 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3898 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3899 other than 1, but that is not valid. We could do a similar
3900 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3901 but this doesn't seem common enough to bother with. */
3902 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3903 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3904 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3905 XEXP (XEXP (x, 0), 1));
3907 if (GET_CODE (XEXP (x, 0)) == SUBREG
3908 && subreg_lowpart_p (XEXP (x, 0))
3909 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3910 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3911 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3912 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3914 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3916 x = gen_rtx_ROTATE (inner_mode,
3917 gen_unary (NOT, inner_mode, inner_mode,
3919 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3920 return gen_lowpart_for_combine (mode, x);
3923 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3924 reversing the comparison code if valid. */
3925 if (STORE_FLAG_VALUE == -1
3926 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3927 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3928 XEXP (XEXP (x, 0), 1))))
3931 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3932 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3933 perform the above simplification. */
3935 if (STORE_FLAG_VALUE == -1
3936 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3937 && XEXP (x, 1) == const1_rtx
3938 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3939 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3940 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3942 /* Apply De Morgan's laws to reduce number of patterns for machines
3943 with negating logical insns (and-not, nand, etc.). If result has
3944 only one NOT, put it first, since that is how the patterns are
3947 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3949 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3950 enum machine_mode op_mode;
3952 op_mode = GET_MODE (in1);
3953 in1 = gen_unary (NOT, op_mode, op_mode, in1);
3955 op_mode = GET_MODE (in2);
3956 if (op_mode == VOIDmode)
3958 in2 = gen_unary (NOT, op_mode, op_mode, in2);
3960 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3963 in2 = in1; in1 = tem;
3966 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3972 /* (neg (plus X 1)) can become (not X). */
3973 if (GET_CODE (XEXP (x, 0)) == PLUS
3974 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3975 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3977 /* Similarly, (neg (not X)) is (plus X 1). */
3978 if (GET_CODE (XEXP (x, 0)) == NOT)
3979 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3981 /* (neg (minus X Y)) can become (minus Y X). */
3982 if (GET_CODE (XEXP (x, 0)) == MINUS
3983 && (! FLOAT_MODE_P (mode)
3984 /* x-y != -(y-x) with IEEE floating point. */
3985 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3987 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3988 XEXP (XEXP (x, 0), 0));
3990 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3991 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3992 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3993 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3995 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3996 if we can then eliminate the NEG (e.g.,
3997 if the operand is a constant). */
3999 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4001 temp = simplify_unary_operation (NEG, mode,
4002 XEXP (XEXP (x, 0), 0), mode);
4005 SUBST (XEXP (XEXP (x, 0), 0), temp);
4010 temp = expand_compound_operation (XEXP (x, 0));
4012 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4013 replaced by (lshiftrt X C). This will convert
4014 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4016 if (GET_CODE (temp) == ASHIFTRT
4017 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4018 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4019 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4020 INTVAL (XEXP (temp, 1)));
4022 /* If X has only a single bit that might be nonzero, say, bit I, convert
4023 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4024 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4025 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4026 or a SUBREG of one since we'd be making the expression more
4027 complex if it was just a register. */
4029 if (GET_CODE (temp) != REG
4030 && ! (GET_CODE (temp) == SUBREG
4031 && GET_CODE (SUBREG_REG (temp)) == REG)
4032 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4034 rtx temp1 = simplify_shift_const
4035 (NULL_RTX, ASHIFTRT, mode,
4036 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4037 GET_MODE_BITSIZE (mode) - 1 - i),
4038 GET_MODE_BITSIZE (mode) - 1 - i);
4040 /* If all we did was surround TEMP with the two shifts, we
4041 haven't improved anything, so don't use it. Otherwise,
4042 we are better off with TEMP1. */
4043 if (GET_CODE (temp1) != ASHIFTRT
4044 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4045 || XEXP (XEXP (temp1, 0), 0) != temp)
4051 /* We can't handle truncation to a partial integer mode here
4052 because we don't know the real bitsize of the partial
4054 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4057 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4058 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4059 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4061 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4062 GET_MODE_MASK (mode), NULL_RTX, 0));
4064 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4065 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4066 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4067 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4068 return XEXP (XEXP (x, 0), 0);
4070 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4071 (OP:SI foo:SI) if OP is NEG or ABS. */
4072 if ((GET_CODE (XEXP (x, 0)) == ABS
4073 || GET_CODE (XEXP (x, 0)) == NEG)
4074 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4075 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4076 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4077 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4078 XEXP (XEXP (XEXP (x, 0), 0), 0));
4080 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4082 if (GET_CODE (XEXP (x, 0)) == SUBREG
4083 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4084 && subreg_lowpart_p (XEXP (x, 0)))
4085 return SUBREG_REG (XEXP (x, 0));
4087 /* If we know that the value is already truncated, we can
4088 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4089 is nonzero for the corresponding modes. But don't do this
4090 for an (LSHIFTRT (MULT ...)) since this will cause problems
4091 with the umulXi3_highpart patterns. */
4092 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4093 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4094 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4095 >= GET_MODE_BITSIZE (mode) + 1
4096 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4097 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4098 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4100 /* A truncate of a comparison can be replaced with a subreg if
4101 STORE_FLAG_VALUE permits. This is like the previous test,
4102 but it works even if the comparison is done in a mode larger
4103 than HOST_BITS_PER_WIDE_INT. */
4104 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4105 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4106 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4107 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4109 /* Similarly, a truncate of a register whose value is a
4110 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4112 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4113 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4114 && (temp = get_last_value (XEXP (x, 0)))
4115 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4116 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4120 case FLOAT_TRUNCATE:
4121 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4122 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4123 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4124 return XEXP (XEXP (x, 0), 0);
4126 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4127 (OP:SF foo:SF) if OP is NEG or ABS. */
4128 if ((GET_CODE (XEXP (x, 0)) == ABS
4129 || GET_CODE (XEXP (x, 0)) == NEG)
4130 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4131 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4132 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4133 XEXP (XEXP (XEXP (x, 0), 0), 0));
4135 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4136 is (float_truncate:SF x). */
4137 if (GET_CODE (XEXP (x, 0)) == SUBREG
4138 && subreg_lowpart_p (XEXP (x, 0))
4139 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4140 return SUBREG_REG (XEXP (x, 0));
4145 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4146 using cc0, in which case we want to leave it as a COMPARE
4147 so we can distinguish it from a register-register-copy. */
4148 if (XEXP (x, 1) == const0_rtx)
4151 /* In IEEE floating point, x-0 is not the same as x. */
4152 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4153 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4155 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4161 /* (const (const X)) can become (const X). Do it this way rather than
4162 returning the inner CONST since CONST can be shared with a
4164 if (GET_CODE (XEXP (x, 0)) == CONST)
4165 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4170 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4171 can add in an offset. find_split_point will split this address up
4172 again if it doesn't match. */
4173 if (GET_CODE (XEXP (x, 0)) == HIGH
4174 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4180 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4181 outermost. That's because that's the way indexed addresses are
4182 supposed to appear. This code used to check many more cases, but
4183 they are now checked elsewhere. */
4184 if (GET_CODE (XEXP (x, 0)) == PLUS
4185 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4186 return gen_binary (PLUS, mode,
4187 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4189 XEXP (XEXP (x, 0), 1));
4191 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4192 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4193 bit-field and can be replaced by either a sign_extend or a
4194 sign_extract. The `and' may be a zero_extend and the two
4195 <c>, -<c> constants may be reversed. */
4196 if (GET_CODE (XEXP (x, 0)) == XOR
4197 && GET_CODE (XEXP (x, 1)) == CONST_INT
4198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4199 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4200 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4201 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4202 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4203 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4204 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4205 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4206 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4207 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4208 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4209 == (unsigned int) i + 1))))
4210 return simplify_shift_const
4211 (NULL_RTX, ASHIFTRT, mode,
4212 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4213 XEXP (XEXP (XEXP (x, 0), 0), 0),
4214 GET_MODE_BITSIZE (mode) - (i + 1)),
4215 GET_MODE_BITSIZE (mode) - (i + 1));
4217 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4218 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4219 is 1. This produces better code than the alternative immediately
4221 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4222 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4223 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4224 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4225 XEXP (XEXP (x, 0), 0),
4226 XEXP (XEXP (x, 0), 1))))
4228 gen_unary (NEG, mode, mode, reversed);
4230 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4231 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4232 the bitsize of the mode - 1. This allows simplification of
4233 "a = (b & 8) == 0;" */
4234 if (XEXP (x, 1) == constm1_rtx
4235 && GET_CODE (XEXP (x, 0)) != REG
4236 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4237 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4238 && nonzero_bits (XEXP (x, 0), mode) == 1)
4239 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4240 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4241 gen_rtx_combine (XOR, mode,
4242 XEXP (x, 0), const1_rtx),
4243 GET_MODE_BITSIZE (mode) - 1),
4244 GET_MODE_BITSIZE (mode) - 1);
4246 /* If we are adding two things that have no bits in common, convert
4247 the addition into an IOR. This will often be further simplified,
4248 for example in cases like ((a & 1) + (a & 2)), which can
4251 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4252 && (nonzero_bits (XEXP (x, 0), mode)
4253 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4255 /* Try to simplify the expression further. */
4256 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4257 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4259 /* If we could, great. If not, do not go ahead with the IOR
4260 replacement, since PLUS appears in many special purpose
4261 address arithmetic instructions. */
4262 if (GET_CODE (temp) != CLOBBER && temp != tor)
4268 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4269 by reversing the comparison code if valid. */
4270 if (STORE_FLAG_VALUE == 1
4271 && XEXP (x, 0) == const1_rtx
4272 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4273 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4274 XEXP (XEXP (x, 1), 0),
4275 XEXP (XEXP (x, 1), 1))))
4278 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4279 (and <foo> (const_int pow2-1)) */
4280 if (GET_CODE (XEXP (x, 1)) == AND
4281 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4282 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4283 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4284 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4285 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4287 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4289 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4290 return gen_binary (MINUS, mode,
4291 gen_binary (MINUS, mode, XEXP (x, 0),
4292 XEXP (XEXP (x, 1), 0)),
4293 XEXP (XEXP (x, 1), 1));
4297 /* If we have (mult (plus A B) C), apply the distributive law and then
4298 the inverse distributive law to see if things simplify. This
4299 occurs mostly in addresses, often when unrolling loops. */
4301 if (GET_CODE (XEXP (x, 0)) == PLUS)
4303 x = apply_distributive_law
4304 (gen_binary (PLUS, mode,
4305 gen_binary (MULT, mode,
4306 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4307 gen_binary (MULT, mode,
4308 XEXP (XEXP (x, 0), 1),
4309 copy_rtx (XEXP (x, 1)))));
4311 if (GET_CODE (x) != MULT)
4317 /* If this is a divide by a power of two, treat it as a shift if
4318 its first operand is a shift. */
4319 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4320 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4321 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4322 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4323 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4324 || GET_CODE (XEXP (x, 0)) == ROTATE
4325 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4326 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4330 case GT: case GTU: case GE: case GEU:
4331 case LT: case LTU: case LE: case LEU:
4332 case UNEQ: case LTGT:
4333 case UNGT: case UNGE:
4334 case UNLT: case UNLE:
4335 case UNORDERED: case ORDERED:
4336 /* If the first operand is a condition code, we can't do anything
4338 if (GET_CODE (XEXP (x, 0)) == COMPARE
4339 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4341 && XEXP (x, 0) != cc0_rtx
4345 rtx op0 = XEXP (x, 0);
4346 rtx op1 = XEXP (x, 1);
4347 enum rtx_code new_code;
4349 if (GET_CODE (op0) == COMPARE)
4350 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4352 /* Simplify our comparison, if possible. */
4353 new_code = simplify_comparison (code, &op0, &op1);
4355 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4356 if only the low-order bit is possibly nonzero in X (such as when
4357 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4358 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4359 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4362 Remove any ZERO_EXTRACT we made when thinking this was a
4363 comparison. It may now be simpler to use, e.g., an AND. If a
4364 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4365 the call to make_compound_operation in the SET case. */
4367 if (STORE_FLAG_VALUE == 1
4368 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4369 && op1 == const0_rtx
4370 && mode == GET_MODE (op0)
4371 && nonzero_bits (op0, mode) == 1)
4372 return gen_lowpart_for_combine (mode,
4373 expand_compound_operation (op0));
4375 else if (STORE_FLAG_VALUE == 1
4376 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4377 && op1 == const0_rtx
4378 && mode == GET_MODE (op0)
4379 && (num_sign_bit_copies (op0, mode)
4380 == GET_MODE_BITSIZE (mode)))
4382 op0 = expand_compound_operation (op0);
4383 return gen_unary (NEG, mode, mode,
4384 gen_lowpart_for_combine (mode, op0));
4387 else if (STORE_FLAG_VALUE == 1
4388 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4389 && op1 == const0_rtx
4390 && mode == GET_MODE (op0)
4391 && nonzero_bits (op0, mode) == 1)
4393 op0 = expand_compound_operation (op0);
4394 return gen_binary (XOR, mode,
4395 gen_lowpart_for_combine (mode, op0),
4399 else if (STORE_FLAG_VALUE == 1
4400 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4401 && op1 == const0_rtx
4402 && mode == GET_MODE (op0)
4403 && (num_sign_bit_copies (op0, mode)
4404 == GET_MODE_BITSIZE (mode)))
4406 op0 = expand_compound_operation (op0);
4407 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4410 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4412 if (STORE_FLAG_VALUE == -1
4413 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4414 && op1 == const0_rtx
4415 && (num_sign_bit_copies (op0, mode)
4416 == GET_MODE_BITSIZE (mode)))
4417 return gen_lowpart_for_combine (mode,
4418 expand_compound_operation (op0));
4420 else if (STORE_FLAG_VALUE == -1
4421 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4422 && op1 == const0_rtx
4423 && mode == GET_MODE (op0)
4424 && nonzero_bits (op0, mode) == 1)
4426 op0 = expand_compound_operation (op0);
4427 return gen_unary (NEG, mode, mode,
4428 gen_lowpart_for_combine (mode, op0));
4431 else if (STORE_FLAG_VALUE == -1
4432 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4433 && op1 == const0_rtx
4434 && mode == GET_MODE (op0)
4435 && (num_sign_bit_copies (op0, mode)
4436 == GET_MODE_BITSIZE (mode)))
4438 op0 = expand_compound_operation (op0);
4439 return gen_unary (NOT, mode, mode,
4440 gen_lowpart_for_combine (mode, op0));
4443 /* If X is 0/1, (eq X 0) is X-1. */
4444 else if (STORE_FLAG_VALUE == -1
4445 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4446 && op1 == const0_rtx
4447 && mode == GET_MODE (op0)
4448 && nonzero_bits (op0, mode) == 1)
4450 op0 = expand_compound_operation (op0);
4451 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4454 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4455 one bit that might be nonzero, we can convert (ne x 0) to
4456 (ashift x c) where C puts the bit in the sign bit. Remove any
4457 AND with STORE_FLAG_VALUE when we are done, since we are only
4458 going to test the sign bit. */
4459 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4460 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4461 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4462 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4463 && op1 == const0_rtx
4464 && mode == GET_MODE (op0)
4465 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4467 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4468 expand_compound_operation (op0),
4469 GET_MODE_BITSIZE (mode) - 1 - i);
4470 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4476 /* If the code changed, return a whole new comparison. */
4477 if (new_code != code)
4478 return gen_rtx_combine (new_code, mode, op0, op1);
4480 /* Otherwise, keep this operation, but maybe change its operands.
4481 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4482 SUBST (XEXP (x, 0), op0);
4483 SUBST (XEXP (x, 1), op1);
4488 return simplify_if_then_else (x);
4494 /* If we are processing SET_DEST, we are done. */
4498 return expand_compound_operation (x);
4501 return simplify_set (x);
4506 return simplify_logical (x, last);
4509 /* (abs (neg <foo>)) -> (abs <foo>) */
4510 if (GET_CODE (XEXP (x, 0)) == NEG)
4511 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4513 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4515 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4518 /* If operand is something known to be positive, ignore the ABS. */
4519 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4520 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4521 <= HOST_BITS_PER_WIDE_INT)
4522 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4523 & ((HOST_WIDE_INT) 1
4524 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4528 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4529 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4530 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4535 /* (ffs (*_extend <X>)) = (ffs <X>) */
4536 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4537 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4538 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4542 /* (float (sign_extend <X>)) = (float <X>). */
4543 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4544 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4552 /* If this is a shift by a constant amount, simplify it. */
4553 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4554 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4555 INTVAL (XEXP (x, 1)));
4557 #ifdef SHIFT_COUNT_TRUNCATED
4558 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4560 force_to_mode (XEXP (x, 1), GET_MODE (x),
4562 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4571 rtx op0 = XEXP (x, 0);
4572 rtx op1 = XEXP (x, 1);
4575 if (GET_CODE (op1) != PARALLEL)
4577 len = XVECLEN (op1, 0);
4579 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4580 && GET_CODE (op0) == VEC_CONCAT)
4582 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4584 /* Try to find the element in the VEC_CONCAT. */
4587 if (GET_MODE (op0) == GET_MODE (x))
4589 if (GET_CODE (op0) == VEC_CONCAT)
4591 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4592 if (op0_size < offset)
4593 op0 = XEXP (op0, 0);
4597 op0 = XEXP (op0, 1);
4615 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4618 simplify_if_then_else (x)
4621 enum machine_mode mode = GET_MODE (x);
4622 rtx cond = XEXP (x, 0);
4623 rtx true = XEXP (x, 1);
4624 rtx false = XEXP (x, 2);
4625 enum rtx_code true_code = GET_CODE (cond);
4626 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4629 enum rtx_code false_code;
4632 /* Simplify storing of the truth value. */
4633 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4634 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4636 /* Also when the truth value has to be reversed. */
4638 && true == const0_rtx && false == const_true_rtx
4639 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4643 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4644 in it is being compared against certain values. Get the true and false
4645 comparisons and see if that says anything about the value of each arm. */
4648 && ((false_code = combine_reversed_comparison_code (cond))
4650 && GET_CODE (XEXP (cond, 0)) == REG)
4653 rtx from = XEXP (cond, 0);
4654 rtx true_val = XEXP (cond, 1);
4655 rtx false_val = true_val;
4658 /* If FALSE_CODE is EQ, swap the codes and arms. */
4660 if (false_code == EQ)
4662 swapped = 1, true_code = EQ, false_code = NE;
4663 temp = true, true = false, false = temp;
4666 /* If we are comparing against zero and the expression being tested has
4667 only a single bit that might be nonzero, that is its value when it is
4668 not equal to zero. Similarly if it is known to be -1 or 0. */
4670 if (true_code == EQ && true_val == const0_rtx
4671 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4672 false_code = EQ, false_val = GEN_INT (nzb);
4673 else if (true_code == EQ && true_val == const0_rtx
4674 && (num_sign_bit_copies (from, GET_MODE (from))
4675 == GET_MODE_BITSIZE (GET_MODE (from))))
4676 false_code = EQ, false_val = constm1_rtx;
4678 /* Now simplify an arm if we know the value of the register in the
4679 branch and it is used in the arm. Be careful due to the potential
4680 of locally-shared RTL. */
4682 if (reg_mentioned_p (from, true))
4683 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4684 pc_rtx, pc_rtx, 0, 0);
4685 if (reg_mentioned_p (from, false))
4686 false = subst (known_cond (copy_rtx (false), false_code,
4688 pc_rtx, pc_rtx, 0, 0);
4690 SUBST (XEXP (x, 1), swapped ? false : true);
4691 SUBST (XEXP (x, 2), swapped ? true : false);
4693 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4696 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4697 reversed, do so to avoid needing two sets of patterns for
4698 subtract-and-branch insns. Similarly if we have a constant in the true
4699 arm, the false arm is the same as the first operand of the comparison, or
4700 the false arm is more complicated than the true arm. */
4703 && combine_reversed_comparison_code (cond) != UNKNOWN
4705 || (CONSTANT_P (true)
4706 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4707 || true == const0_rtx
4708 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4709 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4710 || (GET_CODE (true) == SUBREG
4711 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4712 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4713 || reg_mentioned_p (true, false)
4714 || rtx_equal_p (false, XEXP (cond, 0))))
4716 true_code = reversed_comparison_code (cond, NULL);
4718 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4721 SUBST (XEXP (x, 1), false);
4722 SUBST (XEXP (x, 2), true);
4724 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4726 /* It is possible that the conditional has been simplified out. */
4727 true_code = GET_CODE (cond);
4728 comparison_p = GET_RTX_CLASS (true_code) == '<';
4731 /* If the two arms are identical, we don't need the comparison. */
4733 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4736 /* Convert a == b ? b : a to "a". */
4737 if (true_code == EQ && ! side_effects_p (cond)
4738 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4739 && rtx_equal_p (XEXP (cond, 0), false)
4740 && rtx_equal_p (XEXP (cond, 1), true))
4742 else if (true_code == NE && ! side_effects_p (cond)
4743 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4744 && rtx_equal_p (XEXP (cond, 0), true)
4745 && rtx_equal_p (XEXP (cond, 1), false))
4748 /* Look for cases where we have (abs x) or (neg (abs X)). */
4750 if (GET_MODE_CLASS (mode) == MODE_INT
4751 && GET_CODE (false) == NEG
4752 && rtx_equal_p (true, XEXP (false, 0))
4754 && rtx_equal_p (true, XEXP (cond, 0))
4755 && ! side_effects_p (true))
4760 return gen_unary (ABS, mode, mode, true);
4763 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4768 /* Look for MIN or MAX. */
4770 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4772 && rtx_equal_p (XEXP (cond, 0), true)
4773 && rtx_equal_p (XEXP (cond, 1), false)
4774 && ! side_effects_p (cond))
4779 return gen_binary (SMAX, mode, true, false);
4782 return gen_binary (SMIN, mode, true, false);
4785 return gen_binary (UMAX, mode, true, false);
4788 return gen_binary (UMIN, mode, true, false);
4793 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4794 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4795 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4796 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4797 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4798 neither 1 or -1, but it isn't worth checking for. */
4800 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4801 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4803 rtx t = make_compound_operation (true, SET);
4804 rtx f = make_compound_operation (false, SET);
4805 rtx cond_op0 = XEXP (cond, 0);
4806 rtx cond_op1 = XEXP (cond, 1);
4807 enum rtx_code op = NIL, extend_op = NIL;
4808 enum machine_mode m = mode;
4809 rtx z = 0, c1 = NULL_RTX;
4811 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4812 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4813 || GET_CODE (t) == ASHIFT
4814 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4815 && rtx_equal_p (XEXP (t, 0), f))
4816 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4818 /* If an identity-zero op is commutative, check whether there
4819 would be a match if we swapped the operands. */
4820 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4821 || GET_CODE (t) == XOR)
4822 && rtx_equal_p (XEXP (t, 1), f))
4823 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4824 else if (GET_CODE (t) == SIGN_EXTEND
4825 && (GET_CODE (XEXP (t, 0)) == PLUS
4826 || GET_CODE (XEXP (t, 0)) == MINUS
4827 || GET_CODE (XEXP (t, 0)) == IOR
4828 || GET_CODE (XEXP (t, 0)) == XOR
4829 || GET_CODE (XEXP (t, 0)) == ASHIFT
4830 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4831 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4832 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4833 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4834 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4835 && (num_sign_bit_copies (f, GET_MODE (f))
4836 > (GET_MODE_BITSIZE (mode)
4837 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4839 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4840 extend_op = SIGN_EXTEND;
4841 m = GET_MODE (XEXP (t, 0));
4843 else if (GET_CODE (t) == SIGN_EXTEND
4844 && (GET_CODE (XEXP (t, 0)) == PLUS
4845 || GET_CODE (XEXP (t, 0)) == IOR
4846 || GET_CODE (XEXP (t, 0)) == XOR)
4847 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4848 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4849 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4850 && (num_sign_bit_copies (f, GET_MODE (f))
4851 > (GET_MODE_BITSIZE (mode)
4852 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4854 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4855 extend_op = SIGN_EXTEND;
4856 m = GET_MODE (XEXP (t, 0));
4858 else if (GET_CODE (t) == ZERO_EXTEND
4859 && (GET_CODE (XEXP (t, 0)) == PLUS
4860 || GET_CODE (XEXP (t, 0)) == MINUS
4861 || GET_CODE (XEXP (t, 0)) == IOR
4862 || GET_CODE (XEXP (t, 0)) == XOR
4863 || GET_CODE (XEXP (t, 0)) == ASHIFT
4864 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4865 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4866 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4867 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4868 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4869 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4870 && ((nonzero_bits (f, GET_MODE (f))
4871 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4874 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4875 extend_op = ZERO_EXTEND;
4876 m = GET_MODE (XEXP (t, 0));
4878 else if (GET_CODE (t) == ZERO_EXTEND
4879 && (GET_CODE (XEXP (t, 0)) == PLUS
4880 || GET_CODE (XEXP (t, 0)) == IOR
4881 || GET_CODE (XEXP (t, 0)) == XOR)
4882 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4883 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4884 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4885 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4886 && ((nonzero_bits (f, GET_MODE (f))
4887 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4890 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4891 extend_op = ZERO_EXTEND;
4892 m = GET_MODE (XEXP (t, 0));
4897 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4898 pc_rtx, pc_rtx, 0, 0);
4899 temp = gen_binary (MULT, m, temp,
4900 gen_binary (MULT, m, c1, const_true_rtx));
4901 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4902 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4904 if (extend_op != NIL)
4905 temp = gen_unary (extend_op, mode, m, temp);
4911 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4912 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4913 negation of a single bit, we can convert this operation to a shift. We
4914 can actually do this more generally, but it doesn't seem worth it. */
4916 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4917 && false == const0_rtx && GET_CODE (true) == CONST_INT
4918 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4919 && (i = exact_log2 (INTVAL (true))) >= 0)
4920 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4921 == GET_MODE_BITSIZE (mode))
4922 && (i = exact_log2 (-INTVAL (true))) >= 0)))
4924 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4925 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4930 /* Simplify X, a SET expression. Return the new expression. */
4936 rtx src = SET_SRC (x);
4937 rtx dest = SET_DEST (x);
4938 enum machine_mode mode
4939 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4943 /* (set (pc) (return)) gets written as (return). */
4944 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4947 /* Now that we know for sure which bits of SRC we are using, see if we can
4948 simplify the expression for the object knowing that we only need the
4951 if (GET_MODE_CLASS (mode) == MODE_INT)
4953 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4954 SUBST (SET_SRC (x), src);
4957 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4958 the comparison result and try to simplify it unless we already have used
4959 undobuf.other_insn. */
4960 if ((GET_CODE (src) == COMPARE
4965 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4966 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4967 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4968 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4970 enum rtx_code old_code = GET_CODE (*cc_use);
4971 enum rtx_code new_code;
4973 int other_changed = 0;
4974 enum machine_mode compare_mode = GET_MODE (dest);
4976 if (GET_CODE (src) == COMPARE)
4977 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4979 op0 = src, op1 = const0_rtx;
4981 /* Simplify our comparison, if possible. */
4982 new_code = simplify_comparison (old_code, &op0, &op1);
4984 #ifdef EXTRA_CC_MODES
4985 /* If this machine has CC modes other than CCmode, check to see if we
4986 need to use a different CC mode here. */
4987 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4988 #endif /* EXTRA_CC_MODES */
4990 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4991 /* If the mode changed, we have to change SET_DEST, the mode in the
4992 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4993 a hard register, just build new versions with the proper mode. If it
4994 is a pseudo, we lose unless it is only time we set the pseudo, in
4995 which case we can safely change its mode. */
4996 if (compare_mode != GET_MODE (dest))
4998 unsigned int regno = REGNO (dest);
4999 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5001 if (regno < FIRST_PSEUDO_REGISTER
5002 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5004 if (regno >= FIRST_PSEUDO_REGISTER)
5005 SUBST (regno_reg_rtx[regno], new_dest);
5007 SUBST (SET_DEST (x), new_dest);
5008 SUBST (XEXP (*cc_use, 0), new_dest);
5016 /* If the code changed, we have to build a new comparison in
5017 undobuf.other_insn. */
5018 if (new_code != old_code)
5020 unsigned HOST_WIDE_INT mask;
5022 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
5025 /* If the only change we made was to change an EQ into an NE or
5026 vice versa, OP0 has only one bit that might be nonzero, and OP1
5027 is zero, check if changing the user of the condition code will
5028 produce a valid insn. If it won't, we can keep the original code
5029 in that insn by surrounding our operation with an XOR. */
5031 if (((old_code == NE && new_code == EQ)
5032 || (old_code == EQ && new_code == NE))
5033 && ! other_changed && op1 == const0_rtx
5034 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5035 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5037 rtx pat = PATTERN (other_insn), note = 0;
5039 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5040 && ! check_asm_operands (pat)))
5042 PUT_CODE (*cc_use, old_code);
5045 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5053 undobuf.other_insn = other_insn;
5056 /* If we are now comparing against zero, change our source if
5057 needed. If we do not use cc0, we always have a COMPARE. */
5058 if (op1 == const0_rtx && dest == cc0_rtx)
5060 SUBST (SET_SRC (x), op0);
5066 /* Otherwise, if we didn't previously have a COMPARE in the
5067 correct mode, we need one. */
5068 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5071 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5076 /* Otherwise, update the COMPARE if needed. */
5077 SUBST (XEXP (src, 0), op0);
5078 SUBST (XEXP (src, 1), op1);
5083 /* Get SET_SRC in a form where we have placed back any
5084 compound expressions. Then do the checks below. */
5085 src = make_compound_operation (src, SET);
5086 SUBST (SET_SRC (x), src);
5089 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5090 and X being a REG or (subreg (reg)), we may be able to convert this to
5091 (set (subreg:m2 x) (op)).
5093 We can always do this if M1 is narrower than M2 because that means that
5094 we only care about the low bits of the result.
5096 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5097 perform a narrower operation than requested since the high-order bits will
5098 be undefined. On machine where it is defined, this transformation is safe
5099 as long as M1 and M2 have the same number of words. */
5101 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5102 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5103 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5105 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5106 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5107 #ifndef WORD_REGISTER_OPERATIONS
5108 && (GET_MODE_SIZE (GET_MODE (src))
5109 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5111 #ifdef CLASS_CANNOT_CHANGE_MODE
5112 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5113 && (TEST_HARD_REG_BIT
5114 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5116 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5117 GET_MODE (SUBREG_REG (src))))
5119 && (GET_CODE (dest) == REG
5120 || (GET_CODE (dest) == SUBREG
5121 && GET_CODE (SUBREG_REG (dest)) == REG)))
5123 SUBST (SET_DEST (x),
5124 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5126 SUBST (SET_SRC (x), SUBREG_REG (src));
5128 src = SET_SRC (x), dest = SET_DEST (x);
5131 #ifdef LOAD_EXTEND_OP
5132 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5133 would require a paradoxical subreg. Replace the subreg with a
5134 zero_extend to avoid the reload that would otherwise be required. */
5136 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5137 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5138 && SUBREG_WORD (src) == 0
5139 && (GET_MODE_SIZE (GET_MODE (src))
5140 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5141 && GET_CODE (SUBREG_REG (src)) == MEM)
5144 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5145 GET_MODE (src), XEXP (src, 0)));
5151 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5152 are comparing an item known to be 0 or -1 against 0, use a logical
5153 operation instead. Check for one of the arms being an IOR of the other
5154 arm with some value. We compute three terms to be IOR'ed together. In
5155 practice, at most two will be nonzero. Then we do the IOR's. */
5157 if (GET_CODE (dest) != PC
5158 && GET_CODE (src) == IF_THEN_ELSE
5159 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5160 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5161 && XEXP (XEXP (src, 0), 1) == const0_rtx
5162 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5163 #ifdef HAVE_conditional_move
5164 && ! can_conditionally_move_p (GET_MODE (src))
5166 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5167 GET_MODE (XEXP (XEXP (src, 0), 0)))
5168 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5169 && ! side_effects_p (src))
5171 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5172 ? XEXP (src, 1) : XEXP (src, 2));
5173 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5174 ? XEXP (src, 2) : XEXP (src, 1));
5175 rtx term1 = const0_rtx, term2, term3;
5177 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5178 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5179 else if (GET_CODE (true) == IOR
5180 && rtx_equal_p (XEXP (true, 1), false))
5181 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5182 else if (GET_CODE (false) == IOR
5183 && rtx_equal_p (XEXP (false, 0), true))
5184 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5185 else if (GET_CODE (false) == IOR
5186 && rtx_equal_p (XEXP (false, 1), true))
5187 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5189 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5190 term3 = gen_binary (AND, GET_MODE (src),
5191 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5192 XEXP (XEXP (src, 0), 0)),
5196 gen_binary (IOR, GET_MODE (src),
5197 gen_binary (IOR, GET_MODE (src), term1, term2),
5203 #ifdef HAVE_conditional_arithmetic
5204 /* If we have conditional arithmetic and the operand of a SET is
5205 a conditional expression, replace this with an IF_THEN_ELSE.
5206 We can either have a conditional expression or a MULT of that expression
5208 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5209 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5210 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5211 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5212 || (GET_CODE (XEXP (src, 0)) == MULT
5213 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5214 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5216 rtx cond = XEXP (src, 0);
5217 rtx true_val = const1_rtx;
5218 rtx false_arm, true_arm;
5221 if (GET_CODE (cond) == MULT)
5223 true_val = XEXP (cond, 1);
5224 cond = XEXP (cond, 0);
5227 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5229 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5230 GET_MODE (XEXP (src, 0)), true_val);
5231 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5232 GET_MODE (XEXP (src, 0)), const0_rtx);
5236 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5237 true_val, XEXP (src, 1));
5238 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5239 const0_rtx, XEXP (src, 1));
5242 /* Canonicalize if true_arm is the simpler one. */
5243 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5244 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5245 && (reversed = reversed_comparison_code (cond, GET_MODE (cond),
5249 rtx temp = true_arm;
5251 true_arm = false_arm;
5257 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5258 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5261 true_arm, false_arm);
5262 SUBST (SET_SRC (x), src);
5266 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5267 whole thing fail. */
5268 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5270 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5273 /* Convert this into a field assignment operation, if possible. */
5274 return make_field_assignment (x);
5277 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5278 result. LAST is nonzero if this is the last retry. */
5281 simplify_logical (x, last)
5285 enum machine_mode mode = GET_MODE (x);
5286 rtx op0 = XEXP (x, 0);
5287 rtx op1 = XEXP (x, 1);
5290 switch (GET_CODE (x))
5293 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5294 insn (and may simplify more). */
5295 if (GET_CODE (op0) == XOR
5296 && rtx_equal_p (XEXP (op0, 0), op1)
5297 && ! side_effects_p (op1))
5298 x = gen_binary (AND, mode,
5299 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5301 if (GET_CODE (op0) == XOR
5302 && rtx_equal_p (XEXP (op0, 1), op1)
5303 && ! side_effects_p (op1))
5304 x = gen_binary (AND, mode,
5305 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5307 /* Similarly for (~(A ^ B)) & A. */
5308 if (GET_CODE (op0) == NOT
5309 && GET_CODE (XEXP (op0, 0)) == XOR
5310 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5311 && ! side_effects_p (op1))
5312 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5314 if (GET_CODE (op0) == NOT
5315 && GET_CODE (XEXP (op0, 0)) == XOR
5316 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5317 && ! side_effects_p (op1))
5318 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5320 /* We can call simplify_and_const_int only if we don't lose
5321 any (sign) bits when converting INTVAL (op1) to
5322 "unsigned HOST_WIDE_INT". */
5323 if (GET_CODE (op1) == CONST_INT
5324 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5325 || INTVAL (op1) > 0))
5327 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5329 /* If we have (ior (and (X C1) C2)) and the next restart would be
5330 the last, simplify this by making C1 as small as possible
5333 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5334 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5335 && GET_CODE (op1) == CONST_INT)
5336 return gen_binary (IOR, mode,
5337 gen_binary (AND, mode, XEXP (op0, 0),
5338 GEN_INT (INTVAL (XEXP (op0, 1))
5339 & ~INTVAL (op1))), op1);
5341 if (GET_CODE (x) != AND)
5344 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5345 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5346 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5349 /* Convert (A | B) & A to A. */
5350 if (GET_CODE (op0) == IOR
5351 && (rtx_equal_p (XEXP (op0, 0), op1)
5352 || rtx_equal_p (XEXP (op0, 1), op1))
5353 && ! side_effects_p (XEXP (op0, 0))
5354 && ! side_effects_p (XEXP (op0, 1)))
5357 /* In the following group of tests (and those in case IOR below),
5358 we start with some combination of logical operations and apply
5359 the distributive law followed by the inverse distributive law.
5360 Most of the time, this results in no change. However, if some of
5361 the operands are the same or inverses of each other, simplifications
5364 For example, (and (ior A B) (not B)) can occur as the result of
5365 expanding a bit field assignment. When we apply the distributive
5366 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5367 which then simplifies to (and (A (not B))).
5369 If we have (and (ior A B) C), apply the distributive law and then
5370 the inverse distributive law to see if things simplify. */
5372 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5374 x = apply_distributive_law
5375 (gen_binary (GET_CODE (op0), mode,
5376 gen_binary (AND, mode, XEXP (op0, 0), op1),
5377 gen_binary (AND, mode, XEXP (op0, 1),
5379 if (GET_CODE (x) != AND)
5383 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5384 return apply_distributive_law
5385 (gen_binary (GET_CODE (op1), mode,
5386 gen_binary (AND, mode, XEXP (op1, 0), op0),
5387 gen_binary (AND, mode, XEXP (op1, 1),
5390 /* Similarly, taking advantage of the fact that
5391 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5393 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5394 return apply_distributive_law
5395 (gen_binary (XOR, mode,
5396 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5397 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5400 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5401 return apply_distributive_law
5402 (gen_binary (XOR, mode,
5403 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5404 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5408 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5409 if (GET_CODE (op1) == CONST_INT
5410 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5411 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5414 /* Convert (A & B) | A to A. */
5415 if (GET_CODE (op0) == AND
5416 && (rtx_equal_p (XEXP (op0, 0), op1)
5417 || rtx_equal_p (XEXP (op0, 1), op1))
5418 && ! side_effects_p (XEXP (op0, 0))
5419 && ! side_effects_p (XEXP (op0, 1)))
5422 /* If we have (ior (and A B) C), apply the distributive law and then
5423 the inverse distributive law to see if things simplify. */
5425 if (GET_CODE (op0) == AND)
5427 x = apply_distributive_law
5428 (gen_binary (AND, mode,
5429 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5430 gen_binary (IOR, mode, XEXP (op0, 1),
5433 if (GET_CODE (x) != IOR)
5437 if (GET_CODE (op1) == AND)
5439 x = apply_distributive_law
5440 (gen_binary (AND, mode,
5441 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5442 gen_binary (IOR, mode, XEXP (op1, 1),
5445 if (GET_CODE (x) != IOR)
5449 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5450 mode size to (rotate A CX). */
5452 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5453 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5454 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5455 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5456 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5457 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5458 == GET_MODE_BITSIZE (mode)))
5459 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5460 (GET_CODE (op0) == ASHIFT
5461 ? XEXP (op0, 1) : XEXP (op1, 1)));
5463 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5464 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5465 does not affect any of the bits in OP1, it can really be done
5466 as a PLUS and we can associate. We do this by seeing if OP1
5467 can be safely shifted left C bits. */
5468 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5469 && GET_CODE (XEXP (op0, 0)) == PLUS
5470 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5471 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5472 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5474 int count = INTVAL (XEXP (op0, 1));
5475 HOST_WIDE_INT mask = INTVAL (op1) << count;
5477 if (mask >> count == INTVAL (op1)
5478 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5480 SUBST (XEXP (XEXP (op0, 0), 1),
5481 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5488 /* If we are XORing two things that have no bits in common,
5489 convert them into an IOR. This helps to detect rotation encoded
5490 using those methods and possibly other simplifications. */
5492 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5493 && (nonzero_bits (op0, mode)
5494 & nonzero_bits (op1, mode)) == 0)
5495 return (gen_binary (IOR, mode, op0, op1));
5497 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5498 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5501 int num_negated = 0;
5503 if (GET_CODE (op0) == NOT)
5504 num_negated++, op0 = XEXP (op0, 0);
5505 if (GET_CODE (op1) == NOT)
5506 num_negated++, op1 = XEXP (op1, 0);
5508 if (num_negated == 2)
5510 SUBST (XEXP (x, 0), op0);
5511 SUBST (XEXP (x, 1), op1);
5513 else if (num_negated == 1)
5514 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5517 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5518 correspond to a machine insn or result in further simplifications
5519 if B is a constant. */
5521 if (GET_CODE (op0) == AND
5522 && rtx_equal_p (XEXP (op0, 1), op1)
5523 && ! side_effects_p (op1))
5524 return gen_binary (AND, mode,
5525 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5528 else if (GET_CODE (op0) == AND
5529 && rtx_equal_p (XEXP (op0, 0), op1)
5530 && ! side_effects_p (op1))
5531 return gen_binary (AND, mode,
5532 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5535 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5536 comparison if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE == 1
5538 && op1 == const1_rtx
5539 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5540 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5544 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5545 is (lt foo (const_int 0)), so we can perform the above
5546 simplification if STORE_FLAG_VALUE is 1. */
5548 if (STORE_FLAG_VALUE == 1
5549 && op1 == const1_rtx
5550 && GET_CODE (op0) == LSHIFTRT
5551 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5552 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5553 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5555 /* (xor (comparison foo bar) (const_int sign-bit))
5556 when STORE_FLAG_VALUE is the sign bit. */
5557 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5558 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5559 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5560 && op1 == const_true_rtx
5561 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5562 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5575 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5576 operations" because they can be replaced with two more basic operations.
5577 ZERO_EXTEND is also considered "compound" because it can be replaced with
5578 an AND operation, which is simpler, though only one operation.
5580 The function expand_compound_operation is called with an rtx expression
5581 and will convert it to the appropriate shifts and AND operations,
5582 simplifying at each stage.
5584 The function make_compound_operation is called to convert an expression
5585 consisting of shifts and ANDs into the equivalent compound expression.
5586 It is the inverse of this function, loosely speaking. */
5589 expand_compound_operation (x)
5592 unsigned HOST_WIDE_INT pos = 0, len;
5594 unsigned int modewidth;
5597 switch (GET_CODE (x))
5602 /* We can't necessarily use a const_int for a multiword mode;
5603 it depends on implicitly extending the value.
5604 Since we don't know the right way to extend it,
5605 we can't tell whether the implicit way is right.
5607 Even for a mode that is no wider than a const_int,
5608 we can't win, because we need to sign extend one of its bits through
5609 the rest of it, and we don't know which bit. */
5610 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5613 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5614 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5615 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5616 reloaded. If not for that, MEM's would very rarely be safe.
5618 Reject MODEs bigger than a word, because we might not be able
5619 to reference a two-register group starting with an arbitrary register
5620 (and currently gen_lowpart might crash for a SUBREG). */
5622 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5625 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5626 /* If the inner object has VOIDmode (the only way this can happen
5627 is if it is a ASM_OPERANDS), we can't do anything since we don't
5628 know how much masking to do. */
5637 /* If the operand is a CLOBBER, just return it. */
5638 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5641 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5642 || GET_CODE (XEXP (x, 2)) != CONST_INT
5643 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5646 len = INTVAL (XEXP (x, 1));
5647 pos = INTVAL (XEXP (x, 2));
5649 /* If this goes outside the object being extracted, replace the object
5650 with a (use (mem ...)) construct that only combine understands
5651 and is used only for this purpose. */
5652 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5653 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5655 if (BITS_BIG_ENDIAN)
5656 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5663 /* Convert sign extension to zero extension, if we know that the high
5664 bit is not set, as this is easier to optimize. It will be converted
5665 back to cheaper alternative in make_extraction. */
5666 if (GET_CODE (x) == SIGN_EXTEND
5667 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5668 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5669 & ~(((unsigned HOST_WIDE_INT)
5670 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5674 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5675 return expand_compound_operation (temp);
5678 /* We can optimize some special cases of ZERO_EXTEND. */
5679 if (GET_CODE (x) == ZERO_EXTEND)
5681 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5682 know that the last value didn't have any inappropriate bits
5684 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5685 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5686 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5687 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5688 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5689 return XEXP (XEXP (x, 0), 0);
5691 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5692 if (GET_CODE (XEXP (x, 0)) == SUBREG
5693 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5694 && subreg_lowpart_p (XEXP (x, 0))
5695 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5696 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5697 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5698 return SUBREG_REG (XEXP (x, 0));
5700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5701 is a comparison and STORE_FLAG_VALUE permits. This is like
5702 the first case, but it works even when GET_MODE (x) is larger
5703 than HOST_WIDE_INT. */
5704 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5705 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5706 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5707 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5708 <= HOST_BITS_PER_WIDE_INT)
5709 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5710 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5711 return XEXP (XEXP (x, 0), 0);
5713 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5714 if (GET_CODE (XEXP (x, 0)) == SUBREG
5715 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5716 && subreg_lowpart_p (XEXP (x, 0))
5717 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5719 <= HOST_BITS_PER_WIDE_INT)
5720 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5722 return SUBREG_REG (XEXP (x, 0));
5726 /* If we reach here, we want to return a pair of shifts. The inner
5727 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5728 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5729 logical depending on the value of UNSIGNEDP.
5731 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5732 converted into an AND of a shift.
5734 We must check for the case where the left shift would have a negative
5735 count. This can happen in a case like (x >> 31) & 255 on machines
5736 that can't shift by a constant. On those machines, we would first
5737 combine the shift with the AND to produce a variable-position
5738 extraction. Then the constant of 31 would be substituted in to produce
5739 a such a position. */
5741 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5742 if (modewidth + len >= pos)
5743 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5745 simplify_shift_const (NULL_RTX, ASHIFT,
5748 modewidth - pos - len),
5751 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5752 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5753 simplify_shift_const (NULL_RTX, LSHIFTRT,
5756 ((HOST_WIDE_INT) 1 << len) - 1);
5758 /* Any other cases we can't handle. */
5761 /* If we couldn't do this for some reason, return the original
5763 if (GET_CODE (tem) == CLOBBER)
5769 /* X is a SET which contains an assignment of one object into
5770 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5771 or certain SUBREGS). If possible, convert it into a series of
5774 We half-heartedly support variable positions, but do not at all
5775 support variable lengths. */
5778 expand_field_assignment (x)
5782 rtx pos; /* Always counts from low bit. */
5785 enum machine_mode compute_mode;
5787 /* Loop until we find something we can't simplify. */
5790 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5791 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5793 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5794 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5795 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5797 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5798 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5800 inner = XEXP (SET_DEST (x), 0);
5801 len = INTVAL (XEXP (SET_DEST (x), 1));
5802 pos = XEXP (SET_DEST (x), 2);
5804 /* If the position is constant and spans the width of INNER,
5805 surround INNER with a USE to indicate this. */
5806 if (GET_CODE (pos) == CONST_INT
5807 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5808 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5810 if (BITS_BIG_ENDIAN)
5812 if (GET_CODE (pos) == CONST_INT)
5813 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5815 else if (GET_CODE (pos) == MINUS
5816 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5817 && (INTVAL (XEXP (pos, 1))
5818 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5819 /* If position is ADJUST - X, new position is X. */
5820 pos = XEXP (pos, 0);
5822 pos = gen_binary (MINUS, GET_MODE (pos),
5823 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5829 /* A SUBREG between two modes that occupy the same numbers of words
5830 can be done by moving the SUBREG to the source. */
5831 else if (GET_CODE (SET_DEST (x)) == SUBREG
5832 /* We need SUBREGs to compute nonzero_bits properly. */
5833 && nonzero_sign_valid
5834 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5835 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5836 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5837 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5839 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5840 gen_lowpart_for_combine
5841 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5848 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5849 inner = SUBREG_REG (inner);
5851 compute_mode = GET_MODE (inner);
5853 /* Don't attempt bitwise arithmetic on non-integral modes. */
5854 if (! INTEGRAL_MODE_P (compute_mode))
5856 enum machine_mode imode;
5858 /* Something is probably seriously wrong if this matches. */
5859 if (! FLOAT_MODE_P (compute_mode))
5862 /* Try to find an integral mode to pun with. */
5863 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5864 if (imode == BLKmode)
5867 compute_mode = imode;
5868 inner = gen_lowpart_for_combine (imode, inner);
5871 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5872 if (len < HOST_BITS_PER_WIDE_INT)
5873 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5877 /* Now compute the equivalent expression. Make a copy of INNER
5878 for the SET_DEST in case it is a MEM into which we will substitute;
5879 we don't want shared RTL in that case. */
5881 (VOIDmode, copy_rtx (inner),
5882 gen_binary (IOR, compute_mode,
5883 gen_binary (AND, compute_mode,
5884 gen_unary (NOT, compute_mode,
5890 gen_binary (ASHIFT, compute_mode,
5891 gen_binary (AND, compute_mode,
5892 gen_lowpart_for_combine
5893 (compute_mode, SET_SRC (x)),
5901 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5902 it is an RTX that represents a variable starting position; otherwise,
5903 POS is the (constant) starting bit position (counted from the LSB).
5905 INNER may be a USE. This will occur when we started with a bitfield
5906 that went outside the boundary of the object in memory, which is
5907 allowed on most machines. To isolate this case, we produce a USE
5908 whose mode is wide enough and surround the MEM with it. The only
5909 code that understands the USE is this routine. If it is not removed,
5910 it will cause the resulting insn not to match.
5912 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5915 IN_DEST is non-zero if this is a reference in the destination of a
5916 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5917 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5920 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5921 ZERO_EXTRACT should be built even for bits starting at bit 0.
5923 MODE is the desired mode of the result (if IN_DEST == 0).
5925 The result is an RTX for the extraction or NULL_RTX if the target
5929 make_extraction (mode, inner, pos, pos_rtx, len,
5930 unsignedp, in_dest, in_compare)
5931 enum machine_mode mode;
5935 unsigned HOST_WIDE_INT len;
5937 int in_dest, in_compare;
5939 /* This mode describes the size of the storage area
5940 to fetch the overall value from. Within that, we
5941 ignore the POS lowest bits, etc. */
5942 enum machine_mode is_mode = GET_MODE (inner);
5943 enum machine_mode inner_mode;
5944 enum machine_mode wanted_inner_mode = byte_mode;
5945 enum machine_mode wanted_inner_reg_mode = word_mode;
5946 enum machine_mode pos_mode = word_mode;
5947 enum machine_mode extraction_mode = word_mode;
5948 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5951 rtx orig_pos_rtx = pos_rtx;
5952 HOST_WIDE_INT orig_pos;
5954 /* Get some information about INNER and get the innermost object. */
5955 if (GET_CODE (inner) == USE)
5956 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5957 /* We don't need to adjust the position because we set up the USE
5958 to pretend that it was a full-word object. */
5959 spans_byte = 1, inner = XEXP (inner, 0);
5960 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5962 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5963 consider just the QI as the memory to extract from.
5964 The subreg adds or removes high bits; its mode is
5965 irrelevant to the meaning of this extraction,
5966 since POS and LEN count from the lsb. */
5967 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5968 is_mode = GET_MODE (SUBREG_REG (inner));
5969 inner = SUBREG_REG (inner);
5972 inner_mode = GET_MODE (inner);
5974 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5975 pos = INTVAL (pos_rtx), pos_rtx = 0;
5977 /* See if this can be done without an extraction. We never can if the
5978 width of the field is not the same as that of some integer mode. For
5979 registers, we can only avoid the extraction if the position is at the
5980 low-order bit and this is either not in the destination or we have the
5981 appropriate STRICT_LOW_PART operation available.
5983 For MEM, we can avoid an extract if the field starts on an appropriate
5984 boundary and we can change the mode of the memory reference. However,
5985 we cannot directly access the MEM if we have a USE and the underlying
5986 MEM is not TMODE. This combination means that MEM was being used in a
5987 context where bits outside its mode were being referenced; that is only
5988 valid in bit-field insns. */
5990 if (tmode != BLKmode
5991 && ! (spans_byte && inner_mode != tmode)
5992 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5993 && GET_CODE (inner) != MEM
5995 || (GET_CODE (inner) == REG
5996 && (movstrict_optab->handlers[(int) tmode].insn_code
5997 != CODE_FOR_nothing))))
5998 || (GET_CODE (inner) == MEM && pos_rtx == 0
6000 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6001 : BITS_PER_UNIT)) == 0
6002 /* We can't do this if we are widening INNER_MODE (it
6003 may not be aligned, for one thing). */
6004 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6005 && (inner_mode == tmode
6006 || (! mode_dependent_address_p (XEXP (inner, 0))
6007 && ! MEM_VOLATILE_P (inner))))))
6009 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6010 field. If the original and current mode are the same, we need not
6011 adjust the offset. Otherwise, we do if bytes big endian.
6013 If INNER is not a MEM, get a piece consisting of just the field
6014 of interest (in this case POS % BITS_PER_WORD must be 0). */
6016 if (GET_CODE (inner) == MEM)
6019 /* POS counts from lsb, but make OFFSET count in memory order. */
6020 if (BYTES_BIG_ENDIAN)
6021 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6023 offset = pos / BITS_PER_UNIT;
6025 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
6026 MEM_COPY_ATTRIBUTES (new, inner);
6028 else if (GET_CODE (inner) == REG)
6030 /* We can't call gen_lowpart_for_combine here since we always want
6031 a SUBREG and it would sometimes return a new hard register. */
6032 if (tmode != inner_mode)
6033 new = gen_rtx_SUBREG (tmode, inner,
6035 && (GET_MODE_SIZE (inner_mode)
6037 ? (((GET_MODE_SIZE (inner_mode)
6038 - GET_MODE_SIZE (tmode))
6040 - pos / BITS_PER_WORD)
6041 : pos / BITS_PER_WORD));
6046 new = force_to_mode (inner, tmode,
6047 len >= HOST_BITS_PER_WIDE_INT
6048 ? ~(unsigned HOST_WIDE_INT) 0
6049 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6052 /* If this extraction is going into the destination of a SET,
6053 make a STRICT_LOW_PART unless we made a MEM. */
6056 return (GET_CODE (new) == MEM ? new
6057 : (GET_CODE (new) != SUBREG
6058 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6059 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
6064 /* If we know that no extraneous bits are set, and that the high
6065 bit is not set, convert the extraction to the cheaper of
6066 sign and zero extension, that are equivalent in these cases. */
6067 if (flag_expensive_optimizations
6068 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6069 && ((nonzero_bits (new, tmode)
6070 & ~(((unsigned HOST_WIDE_INT)
6071 GET_MODE_MASK (tmode))
6075 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6076 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6078 /* Prefer ZERO_EXTENSION, since it gives more information to
6080 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6085 /* Otherwise, sign- or zero-extend unless we already are in the
6088 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6092 /* Unless this is a COMPARE or we have a funny memory reference,
6093 don't do anything with zero-extending field extracts starting at
6094 the low-order bit since they are simple AND operations. */
6095 if (pos_rtx == 0 && pos == 0 && ! in_dest
6096 && ! in_compare && ! spans_byte && unsignedp)
6099 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6100 we would be spanning bytes or if the position is not a constant and the
6101 length is not 1. In all other cases, we would only be going outside
6102 our object in cases when an original shift would have been
6104 if (! spans_byte && GET_CODE (inner) == MEM
6105 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6106 || (pos_rtx != 0 && len != 1)))
6109 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6110 and the mode for the result. */
6114 wanted_inner_reg_mode
6115 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6116 if (wanted_inner_reg_mode == VOIDmode)
6117 wanted_inner_reg_mode = word_mode;
6119 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6120 if (pos_mode == VOIDmode)
6121 pos_mode = word_mode;
6123 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6124 if (extraction_mode == VOIDmode)
6125 extraction_mode = word_mode;
6130 if (! in_dest && unsignedp)
6132 wanted_inner_reg_mode
6133 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6134 if (wanted_inner_reg_mode == VOIDmode)
6135 wanted_inner_reg_mode = word_mode;
6137 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6138 if (pos_mode == VOIDmode)
6139 pos_mode = word_mode;
6141 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6142 if (extraction_mode == VOIDmode)
6143 extraction_mode = word_mode;
6148 if (! in_dest && ! unsignedp)
6150 wanted_inner_reg_mode
6151 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6152 if (wanted_inner_reg_mode == VOIDmode)
6153 wanted_inner_reg_mode = word_mode;
6155 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6156 if (pos_mode == VOIDmode)
6157 pos_mode = word_mode;
6159 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6160 if (extraction_mode == VOIDmode)
6161 extraction_mode = word_mode;
6165 /* Never narrow an object, since that might not be safe. */
6167 if (mode != VOIDmode
6168 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6169 extraction_mode = mode;
6171 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6172 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6173 pos_mode = GET_MODE (pos_rtx);
6175 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6176 if we have to change the mode of memory and cannot, the desired mode is
6178 if (GET_CODE (inner) != MEM)
6179 wanted_inner_mode = wanted_inner_reg_mode;
6180 else if (inner_mode != wanted_inner_mode
6181 && (mode_dependent_address_p (XEXP (inner, 0))
6182 || MEM_VOLATILE_P (inner)))
6183 wanted_inner_mode = extraction_mode;
6187 if (BITS_BIG_ENDIAN)
6189 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6190 BITS_BIG_ENDIAN style. If position is constant, compute new
6191 position. Otherwise, build subtraction.
6192 Note that POS is relative to the mode of the original argument.
6193 If it's a MEM we need to recompute POS relative to that.
6194 However, if we're extracting from (or inserting into) a register,
6195 we want to recompute POS relative to wanted_inner_mode. */
6196 int width = (GET_CODE (inner) == MEM
6197 ? GET_MODE_BITSIZE (is_mode)
6198 : GET_MODE_BITSIZE (wanted_inner_mode));
6201 pos = width - len - pos;
6204 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6205 GEN_INT (width - len), pos_rtx);
6206 /* POS may be less than 0 now, but we check for that below.
6207 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6210 /* If INNER has a wider mode, make it smaller. If this is a constant
6211 extract, try to adjust the byte to point to the byte containing
6213 if (wanted_inner_mode != VOIDmode
6214 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6215 && ((GET_CODE (inner) == MEM
6216 && (inner_mode == wanted_inner_mode
6217 || (! mode_dependent_address_p (XEXP (inner, 0))
6218 && ! MEM_VOLATILE_P (inner))))))
6222 /* The computations below will be correct if the machine is big
6223 endian in both bits and bytes or little endian in bits and bytes.
6224 If it is mixed, we must adjust. */
6226 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6227 adjust OFFSET to compensate. */
6228 if (BYTES_BIG_ENDIAN
6230 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6231 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6233 /* If this is a constant position, we can move to the desired byte. */
6236 offset += pos / BITS_PER_UNIT;
6237 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6240 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6242 && is_mode != wanted_inner_mode)
6243 offset = (GET_MODE_SIZE (is_mode)
6244 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6246 if (offset != 0 || inner_mode != wanted_inner_mode)
6248 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6249 plus_constant (XEXP (inner, 0), offset));
6251 MEM_COPY_ATTRIBUTES (newmem, inner);
6256 /* If INNER is not memory, we can always get it into the proper mode. If we
6257 are changing its mode, POS must be a constant and smaller than the size
6259 else if (GET_CODE (inner) != MEM)
6261 if (GET_MODE (inner) != wanted_inner_mode
6263 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6266 inner = force_to_mode (inner, wanted_inner_mode,
6268 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6269 ? ~(unsigned HOST_WIDE_INT) 0
6270 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6275 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6276 have to zero extend. Otherwise, we can just use a SUBREG. */
6278 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6280 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6282 /* If we know that no extraneous bits are set, and that the high
6283 bit is not set, convert extraction to cheaper one - eighter
6284 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6286 if (flag_expensive_optimizations
6287 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6288 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6289 & ~(((unsigned HOST_WIDE_INT)
6290 GET_MODE_MASK (GET_MODE (pos_rtx)))
6294 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6296 /* Prefer ZERO_EXTENSION, since it gives more information to
6298 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6303 else if (pos_rtx != 0
6304 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6305 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6307 /* Make POS_RTX unless we already have it and it is correct. If we don't
6308 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6310 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6311 pos_rtx = orig_pos_rtx;
6313 else if (pos_rtx == 0)
6314 pos_rtx = GEN_INT (pos);
6316 /* Make the required operation. See if we can use existing rtx. */
6317 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6318 extraction_mode, inner, GEN_INT (len), pos_rtx);
6320 new = gen_lowpart_for_combine (mode, new);
6325 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6326 with any other operations in X. Return X without that shift if so. */
6329 extract_left_shift (x, count)
6333 enum rtx_code code = GET_CODE (x);
6334 enum machine_mode mode = GET_MODE (x);
6340 /* This is the shift itself. If it is wide enough, we will return
6341 either the value being shifted if the shift count is equal to
6342 COUNT or a shift for the difference. */
6343 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6344 && INTVAL (XEXP (x, 1)) >= count)
6345 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6346 INTVAL (XEXP (x, 1)) - count);
6350 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6351 return gen_unary (code, mode, mode, tem);
6355 case PLUS: case IOR: case XOR: case AND:
6356 /* If we can safely shift this constant and we find the inner shift,
6357 make a new operation. */
6358 if (GET_CODE (XEXP (x,1)) == CONST_INT
6359 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6360 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6361 return gen_binary (code, mode, tem,
6362 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6373 /* Look at the expression rooted at X. Look for expressions
6374 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6375 Form these expressions.
6377 Return the new rtx, usually just X.
6379 Also, for machines like the Vax that don't have logical shift insns,
6380 try to convert logical to arithmetic shift operations in cases where
6381 they are equivalent. This undoes the canonicalizations to logical
6382 shifts done elsewhere.
6384 We try, as much as possible, to re-use rtl expressions to save memory.
6386 IN_CODE says what kind of expression we are processing. Normally, it is
6387 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6388 being kludges), it is MEM. When processing the arguments of a comparison
6389 or a COMPARE against zero, it is COMPARE. */
6392 make_compound_operation (x, in_code)
6394 enum rtx_code in_code;
6396 enum rtx_code code = GET_CODE (x);
6397 enum machine_mode mode = GET_MODE (x);
6398 int mode_width = GET_MODE_BITSIZE (mode);
6400 enum rtx_code next_code;
6406 /* Select the code to be used in recursive calls. Once we are inside an
6407 address, we stay there. If we have a comparison, set to COMPARE,
6408 but once inside, go back to our default of SET. */
6410 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6411 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6412 && XEXP (x, 1) == const0_rtx) ? COMPARE
6413 : in_code == COMPARE ? SET : in_code);
6415 /* Process depending on the code of this operation. If NEW is set
6416 non-zero, it will be returned. */
6421 /* Convert shifts by constants into multiplications if inside
6423 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6424 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6425 && INTVAL (XEXP (x, 1)) >= 0)
6427 new = make_compound_operation (XEXP (x, 0), next_code);
6428 new = gen_rtx_combine (MULT, mode, new,
6429 GEN_INT ((HOST_WIDE_INT) 1
6430 << INTVAL (XEXP (x, 1))));
6435 /* If the second operand is not a constant, we can't do anything
6437 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6440 /* If the constant is a power of two minus one and the first operand
6441 is a logical right shift, make an extraction. */
6442 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6443 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6445 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6446 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6447 0, in_code == COMPARE);
6450 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6451 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6452 && subreg_lowpart_p (XEXP (x, 0))
6453 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6454 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6456 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6458 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6459 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6460 0, in_code == COMPARE);
6462 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6463 else if ((GET_CODE (XEXP (x, 0)) == XOR
6464 || GET_CODE (XEXP (x, 0)) == IOR)
6465 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6466 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6467 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6469 /* Apply the distributive law, and then try to make extractions. */
6470 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6471 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6473 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6475 new = make_compound_operation (new, in_code);
6478 /* If we are have (and (rotate X C) M) and C is larger than the number
6479 of bits in M, this is an extraction. */
6481 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6482 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6483 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6484 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6486 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6487 new = make_extraction (mode, new,
6488 (GET_MODE_BITSIZE (mode)
6489 - INTVAL (XEXP (XEXP (x, 0), 1))),
6490 NULL_RTX, i, 1, 0, in_code == COMPARE);
6493 /* On machines without logical shifts, if the operand of the AND is
6494 a logical shift and our mask turns off all the propagated sign
6495 bits, we can replace the logical shift with an arithmetic shift. */
6496 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6497 && (lshr_optab->handlers[(int) mode].insn_code
6498 == CODE_FOR_nothing)
6499 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6500 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6501 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6502 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6503 && mode_width <= HOST_BITS_PER_WIDE_INT)
6505 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6507 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6508 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6510 gen_rtx_combine (ASHIFTRT, mode,
6511 make_compound_operation (XEXP (XEXP (x, 0), 0),
6513 XEXP (XEXP (x, 0), 1)));
6516 /* If the constant is one less than a power of two, this might be
6517 representable by an extraction even if no shift is present.
6518 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6519 we are in a COMPARE. */
6520 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6521 new = make_extraction (mode,
6522 make_compound_operation (XEXP (x, 0),
6524 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6526 /* If we are in a comparison and this is an AND with a power of two,
6527 convert this into the appropriate bit extract. */
6528 else if (in_code == COMPARE
6529 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6530 new = make_extraction (mode,
6531 make_compound_operation (XEXP (x, 0),
6533 i, NULL_RTX, 1, 1, 0, 1);
6538 /* If the sign bit is known to be zero, replace this with an
6539 arithmetic shift. */
6540 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6541 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6542 && mode_width <= HOST_BITS_PER_WIDE_INT
6543 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6545 new = gen_rtx_combine (ASHIFTRT, mode,
6546 make_compound_operation (XEXP (x, 0),
6552 /* ... fall through ... */
6558 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6559 this is a SIGN_EXTRACT. */
6560 if (GET_CODE (rhs) == CONST_INT
6561 && GET_CODE (lhs) == ASHIFT
6562 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6563 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6565 new = make_compound_operation (XEXP (lhs, 0), next_code);
6566 new = make_extraction (mode, new,
6567 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6568 NULL_RTX, mode_width - INTVAL (rhs),
6569 code == LSHIFTRT, 0, in_code == COMPARE);
6573 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6574 If so, try to merge the shifts into a SIGN_EXTEND. We could
6575 also do this for some cases of SIGN_EXTRACT, but it doesn't
6576 seem worth the effort; the case checked for occurs on Alpha. */
6578 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6579 && ! (GET_CODE (lhs) == SUBREG
6580 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6581 && GET_CODE (rhs) == CONST_INT
6582 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6583 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6584 new = make_extraction (mode, make_compound_operation (new, next_code),
6585 0, NULL_RTX, mode_width - INTVAL (rhs),
6586 code == LSHIFTRT, 0, in_code == COMPARE);
6591 /* Call ourselves recursively on the inner expression. If we are
6592 narrowing the object and it has a different RTL code from
6593 what it originally did, do this SUBREG as a force_to_mode. */
6595 tem = make_compound_operation (SUBREG_REG (x), in_code);
6596 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6597 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6598 && subreg_lowpart_p (x))
6600 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6603 /* If we have something other than a SUBREG, we might have
6604 done an expansion, so rerun outselves. */
6605 if (GET_CODE (newer) != SUBREG)
6606 newer = make_compound_operation (newer, in_code);
6611 /* If this is a paradoxical subreg, and the new code is a sign or
6612 zero extension, omit the subreg and widen the extension. If it
6613 is a regular subreg, we can still get rid of the subreg by not
6614 widening so much, or in fact removing the extension entirely. */
6615 if ((GET_CODE (tem) == SIGN_EXTEND
6616 || GET_CODE (tem) == ZERO_EXTEND)
6617 && subreg_lowpart_p (x))
6619 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6620 || (GET_MODE_SIZE (mode) >
6621 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6622 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6624 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6635 x = gen_lowpart_for_combine (mode, new);
6636 code = GET_CODE (x);
6639 /* Now recursively process each operand of this operation. */
6640 fmt = GET_RTX_FORMAT (code);
6641 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6644 new = make_compound_operation (XEXP (x, i), next_code);
6645 SUBST (XEXP (x, i), new);
6651 /* Given M see if it is a value that would select a field of bits
6652 within an item, but not the entire word. Return -1 if not.
6653 Otherwise, return the starting position of the field, where 0 is the
6656 *PLEN is set to the length of the field. */
6659 get_pos_from_mask (m, plen)
6660 unsigned HOST_WIDE_INT m;
6661 unsigned HOST_WIDE_INT *plen;
6663 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6664 int pos = exact_log2 (m & -m);
6670 /* Now shift off the low-order zero bits and see if we have a power of
6672 len = exact_log2 ((m >> pos) + 1);
6681 /* See if X can be simplified knowing that we will only refer to it in
6682 MODE and will only refer to those bits that are nonzero in MASK.
6683 If other bits are being computed or if masking operations are done
6684 that select a superset of the bits in MASK, they can sometimes be
6687 Return a possibly simplified expression, but always convert X to
6688 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6690 Also, if REG is non-zero and X is a register equal in value to REG,
6693 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6694 are all off in X. This is used when X will be complemented, by either
6695 NOT, NEG, or XOR. */
6698 force_to_mode (x, mode, mask, reg, just_select)
6700 enum machine_mode mode;
6701 unsigned HOST_WIDE_INT mask;
6705 enum rtx_code code = GET_CODE (x);
6706 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6707 enum machine_mode op_mode;
6708 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6711 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6712 code below will do the wrong thing since the mode of such an
6713 expression is VOIDmode.
6715 Also do nothing if X is a CLOBBER; this can happen if X was
6716 the return value from a call to gen_lowpart_for_combine. */
6717 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6720 /* We want to perform the operation is its present mode unless we know
6721 that the operation is valid in MODE, in which case we do the operation
6723 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6724 && code_to_optab[(int) code] != 0
6725 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6726 != CODE_FOR_nothing))
6727 ? mode : GET_MODE (x));
6729 /* It is not valid to do a right-shift in a narrower mode
6730 than the one it came in with. */
6731 if ((code == LSHIFTRT || code == ASHIFTRT)
6732 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6733 op_mode = GET_MODE (x);
6735 /* Truncate MASK to fit OP_MODE. */
6737 mask &= GET_MODE_MASK (op_mode);
6739 /* When we have an arithmetic operation, or a shift whose count we
6740 do not know, we need to assume that all bit the up to the highest-order
6741 bit in MASK will be needed. This is how we form such a mask. */
6743 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6744 ? GET_MODE_MASK (op_mode)
6745 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6748 fuller_mask = ~(HOST_WIDE_INT) 0;
6750 /* Determine what bits of X are guaranteed to be (non)zero. */
6751 nonzero = nonzero_bits (x, mode);
6753 /* If none of the bits in X are needed, return a zero. */
6754 if (! just_select && (nonzero & mask) == 0)
6757 /* If X is a CONST_INT, return a new one. Do this here since the
6758 test below will fail. */
6759 if (GET_CODE (x) == CONST_INT)
6761 HOST_WIDE_INT cval = INTVAL (x) & mask;
6762 int width = GET_MODE_BITSIZE (mode);
6764 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6765 number, sign extend it. */
6766 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6767 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6768 cval |= (HOST_WIDE_INT) -1 << width;
6770 return GEN_INT (cval);
6773 /* If X is narrower than MODE and we want all the bits in X's mode, just
6774 get X in the proper mode. */
6775 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6776 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6777 return gen_lowpart_for_combine (mode, x);
6779 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6780 MASK are already known to be zero in X, we need not do anything. */
6781 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6787 /* If X is a (clobber (const_int)), return it since we know we are
6788 generating something that won't match. */
6792 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6793 spanned the boundary of the MEM. If we are now masking so it is
6794 within that boundary, we don't need the USE any more. */
6795 if (! BITS_BIG_ENDIAN
6796 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6797 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6804 x = expand_compound_operation (x);
6805 if (GET_CODE (x) != code)
6806 return force_to_mode (x, mode, mask, reg, next_select);
6810 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6811 || rtx_equal_p (reg, get_last_value (x))))
6816 if (subreg_lowpart_p (x)
6817 /* We can ignore the effect of this SUBREG if it narrows the mode or
6818 if the constant masks to zero all the bits the mode doesn't
6820 && ((GET_MODE_SIZE (GET_MODE (x))
6821 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6823 & GET_MODE_MASK (GET_MODE (x))
6824 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6825 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6829 /* If this is an AND with a constant, convert it into an AND
6830 whose constant is the AND of that constant with MASK. If it
6831 remains an AND of MASK, delete it since it is redundant. */
6833 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6835 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6836 mask & INTVAL (XEXP (x, 1)));
6838 /* If X is still an AND, see if it is an AND with a mask that
6839 is just some low-order bits. If so, and it is MASK, we don't
6842 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6843 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6846 /* If it remains an AND, try making another AND with the bits
6847 in the mode mask that aren't in MASK turned on. If the
6848 constant in the AND is wide enough, this might make a
6849 cheaper constant. */
6851 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6852 && GET_MODE_MASK (GET_MODE (x)) != mask
6853 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6855 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6856 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6857 int width = GET_MODE_BITSIZE (GET_MODE (x));
6860 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6861 number, sign extend it. */
6862 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6863 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6864 cval |= (HOST_WIDE_INT) -1 << width;
6866 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6867 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6877 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6878 low-order bits (as in an alignment operation) and FOO is already
6879 aligned to that boundary, mask C1 to that boundary as well.
6880 This may eliminate that PLUS and, later, the AND. */
6883 unsigned int width = GET_MODE_BITSIZE (mode);
6884 unsigned HOST_WIDE_INT smask = mask;
6886 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6887 number, sign extend it. */
6889 if (width < HOST_BITS_PER_WIDE_INT
6890 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6891 smask |= (HOST_WIDE_INT) -1 << width;
6893 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6894 && exact_log2 (- smask) >= 0)
6898 && (XEXP (x, 0) == stack_pointer_rtx
6899 || XEXP (x, 0) == frame_pointer_rtx))
6901 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6902 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6904 sp_mask &= ~(sp_alignment - 1);
6905 if ((sp_mask & ~smask) == 0
6906 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6907 return force_to_mode (plus_constant (XEXP (x, 0),
6908 ((INTVAL (XEXP (x, 1)) -
6909 STACK_BIAS) & smask)
6911 mode, smask, reg, next_select);
6914 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6915 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6916 return force_to_mode (plus_constant (XEXP (x, 0),
6917 (INTVAL (XEXP (x, 1))
6919 mode, smask, reg, next_select);
6923 /* ... fall through ... */
6926 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6927 most significant bit in MASK since carries from those bits will
6928 affect the bits we are interested in. */
6933 /* If X is (minus C Y) where C's least set bit is larger than any bit
6934 in the mask, then we may replace with (neg Y). */
6935 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6936 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6937 & -INTVAL (XEXP (x, 0))))
6940 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6941 return force_to_mode (x, mode, mask, reg, next_select);
6944 /* Similarly, if C contains every bit in the mask, then we may
6945 replace with (not Y). */
6946 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6947 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6948 == INTVAL (XEXP (x, 0))))
6950 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6951 return force_to_mode (x, mode, mask, reg, next_select);
6959 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6960 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6961 operation which may be a bitfield extraction. Ensure that the
6962 constant we form is not wider than the mode of X. */
6964 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6965 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6966 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6967 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6968 && GET_CODE (XEXP (x, 1)) == CONST_INT
6969 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6970 + floor_log2 (INTVAL (XEXP (x, 1))))
6971 < GET_MODE_BITSIZE (GET_MODE (x)))
6972 && (INTVAL (XEXP (x, 1))
6973 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6975 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6976 << INTVAL (XEXP (XEXP (x, 0), 1)));
6977 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6978 XEXP (XEXP (x, 0), 0), temp);
6979 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6980 XEXP (XEXP (x, 0), 1));
6981 return force_to_mode (x, mode, mask, reg, next_select);
6985 /* For most binary operations, just propagate into the operation and
6986 change the mode if we have an operation of that mode. */
6988 op0 = gen_lowpart_for_combine (op_mode,
6989 force_to_mode (XEXP (x, 0), mode, mask,
6991 op1 = gen_lowpart_for_combine (op_mode,
6992 force_to_mode (XEXP (x, 1), mode, mask,
6995 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6996 MASK since OP1 might have been sign-extended but we never want
6997 to turn on extra bits, since combine might have previously relied
6998 on them being off. */
6999 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
7000 && (INTVAL (op1) & mask) != 0)
7001 op1 = GEN_INT (INTVAL (op1) & mask);
7003 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7004 x = gen_binary (code, op_mode, op0, op1);
7008 /* For left shifts, do the same, but just for the first operand.
7009 However, we cannot do anything with shifts where we cannot
7010 guarantee that the counts are smaller than the size of the mode
7011 because such a count will have a different meaning in a
7014 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7015 && INTVAL (XEXP (x, 1)) >= 0
7016 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7017 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7018 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7019 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7022 /* If the shift count is a constant and we can do arithmetic in
7023 the mode of the shift, refine which bits we need. Otherwise, use the
7024 conservative form of the mask. */
7025 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7026 && INTVAL (XEXP (x, 1)) >= 0
7027 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7028 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7029 mask >>= INTVAL (XEXP (x, 1));
7033 op0 = gen_lowpart_for_combine (op_mode,
7034 force_to_mode (XEXP (x, 0), op_mode,
7035 mask, reg, next_select));
7037 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7038 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7042 /* Here we can only do something if the shift count is a constant,
7043 this shift constant is valid for the host, and we can do arithmetic
7046 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7047 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7048 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7050 rtx inner = XEXP (x, 0);
7051 unsigned HOST_WIDE_INT inner_mask;
7053 /* Select the mask of the bits we need for the shift operand. */
7054 inner_mask = mask << INTVAL (XEXP (x, 1));
7056 /* We can only change the mode of the shift if we can do arithmetic
7057 in the mode of the shift and INNER_MASK is no wider than the
7058 width of OP_MODE. */
7059 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7060 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7061 op_mode = GET_MODE (x);
7063 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7065 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7066 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7069 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7070 shift and AND produces only copies of the sign bit (C2 is one less
7071 than a power of two), we can do this with just a shift. */
7073 if (GET_CODE (x) == LSHIFTRT
7074 && GET_CODE (XEXP (x, 1)) == CONST_INT
7075 /* The shift puts one of the sign bit copies in the least significant
7077 && ((INTVAL (XEXP (x, 1))
7078 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7079 >= GET_MODE_BITSIZE (GET_MODE (x)))
7080 && exact_log2 (mask + 1) >= 0
7081 /* Number of bits left after the shift must be more than the mask
7083 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7084 <= GET_MODE_BITSIZE (GET_MODE (x)))
7085 /* Must be more sign bit copies than the mask needs. */
7086 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7087 >= exact_log2 (mask + 1)))
7088 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7089 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7090 - exact_log2 (mask + 1)));
7095 /* If we are just looking for the sign bit, we don't need this shift at
7096 all, even if it has a variable count. */
7097 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7098 && (mask == ((unsigned HOST_WIDE_INT) 1
7099 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7100 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7102 /* If this is a shift by a constant, get a mask that contains those bits
7103 that are not copies of the sign bit. We then have two cases: If
7104 MASK only includes those bits, this can be a logical shift, which may
7105 allow simplifications. If MASK is a single-bit field not within
7106 those bits, we are requesting a copy of the sign bit and hence can
7107 shift the sign bit to the appropriate location. */
7109 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7110 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7114 /* If the considered data is wider then HOST_WIDE_INT, we can't
7115 represent a mask for all its bits in a single scalar.
7116 But we only care about the lower bits, so calculate these. */
7118 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7120 nonzero = ~(HOST_WIDE_INT) 0;
7122 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7123 is the number of bits a full-width mask would have set.
7124 We need only shift if these are fewer than nonzero can
7125 hold. If not, we must keep all bits set in nonzero. */
7127 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7128 < HOST_BITS_PER_WIDE_INT)
7129 nonzero >>= INTVAL (XEXP (x, 1))
7130 + HOST_BITS_PER_WIDE_INT
7131 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7135 nonzero = GET_MODE_MASK (GET_MODE (x));
7136 nonzero >>= INTVAL (XEXP (x, 1));
7139 if ((mask & ~nonzero) == 0
7140 || (i = exact_log2 (mask)) >= 0)
7142 x = simplify_shift_const
7143 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7144 i < 0 ? INTVAL (XEXP (x, 1))
7145 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7147 if (GET_CODE (x) != ASHIFTRT)
7148 return force_to_mode (x, mode, mask, reg, next_select);
7152 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7153 even if the shift count isn't a constant. */
7155 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7159 /* If this is a zero- or sign-extension operation that just affects bits
7160 we don't care about, remove it. Be sure the call above returned
7161 something that is still a shift. */
7163 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7164 && GET_CODE (XEXP (x, 1)) == CONST_INT
7165 && INTVAL (XEXP (x, 1)) >= 0
7166 && (INTVAL (XEXP (x, 1))
7167 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7168 && GET_CODE (XEXP (x, 0)) == ASHIFT
7169 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7170 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7171 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7178 /* If the shift count is constant and we can do computations
7179 in the mode of X, compute where the bits we care about are.
7180 Otherwise, we can't do anything. Don't change the mode of
7181 the shift or propagate MODE into the shift, though. */
7182 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7183 && INTVAL (XEXP (x, 1)) >= 0)
7185 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7186 GET_MODE (x), GEN_INT (mask),
7188 if (temp && GET_CODE(temp) == CONST_INT)
7190 force_to_mode (XEXP (x, 0), GET_MODE (x),
7191 INTVAL (temp), reg, next_select));
7196 /* If we just want the low-order bit, the NEG isn't needed since it
7197 won't change the low-order bit. */
7199 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7201 /* We need any bits less significant than the most significant bit in
7202 MASK since carries from those bits will affect the bits we are
7208 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7209 same as the XOR case above. Ensure that the constant we form is not
7210 wider than the mode of X. */
7212 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7213 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7214 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7215 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7216 < GET_MODE_BITSIZE (GET_MODE (x)))
7217 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7219 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7220 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7221 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7223 return force_to_mode (x, mode, mask, reg, next_select);
7226 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7227 use the full mask inside the NOT. */
7231 op0 = gen_lowpart_for_combine (op_mode,
7232 force_to_mode (XEXP (x, 0), mode, mask,
7234 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7235 x = gen_unary (code, op_mode, op_mode, op0);
7239 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7240 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7241 which is equal to STORE_FLAG_VALUE. */
7242 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7243 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7244 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7245 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7250 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7251 written in a narrower mode. We play it safe and do not do so. */
7254 gen_lowpart_for_combine (GET_MODE (x),
7255 force_to_mode (XEXP (x, 1), mode,
7256 mask, reg, next_select)));
7258 gen_lowpart_for_combine (GET_MODE (x),
7259 force_to_mode (XEXP (x, 2), mode,
7260 mask, reg,next_select)));
7267 /* Ensure we return a value of the proper mode. */
7268 return gen_lowpart_for_combine (mode, x);
7271 /* Return nonzero if X is an expression that has one of two values depending on
7272 whether some other value is zero or nonzero. In that case, we return the
7273 value that is being tested, *PTRUE is set to the value if the rtx being
7274 returned has a nonzero value, and *PFALSE is set to the other alternative.
7276 If we return zero, we set *PTRUE and *PFALSE to X. */
7279 if_then_else_cond (x, ptrue, pfalse)
7281 rtx *ptrue, *pfalse;
7283 enum machine_mode mode = GET_MODE (x);
7284 enum rtx_code code = GET_CODE (x);
7285 rtx cond0, cond1, true0, true1, false0, false1;
7286 unsigned HOST_WIDE_INT nz;
7288 /* If we are comparing a value against zero, we are done. */
7289 if ((code == NE || code == EQ)
7290 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7292 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7293 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7297 /* If this is a unary operation whose operand has one of two values, apply
7298 our opcode to compute those values. */
7299 else if (GET_RTX_CLASS (code) == '1'
7300 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7302 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7303 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7307 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7308 make can't possibly match and would suppress other optimizations. */
7309 else if (code == COMPARE)
7312 /* If this is a binary operation, see if either side has only one of two
7313 values. If either one does or if both do and they are conditional on
7314 the same value, compute the new true and false values. */
7315 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7316 || GET_RTX_CLASS (code) == '<')
7318 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7319 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7321 if ((cond0 != 0 || cond1 != 0)
7322 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7324 /* If if_then_else_cond returned zero, then true/false are the
7325 same rtl. We must copy one of them to prevent invalid rtl
7328 true0 = copy_rtx (true0);
7329 else if (cond1 == 0)
7330 true1 = copy_rtx (true1);
7332 *ptrue = gen_binary (code, mode, true0, true1);
7333 *pfalse = gen_binary (code, mode, false0, false1);
7334 return cond0 ? cond0 : cond1;
7337 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7338 operands is zero when the other is non-zero, and vice-versa,
7339 and STORE_FLAG_VALUE is 1 or -1. */
7341 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7342 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7344 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7346 rtx op0 = XEXP (XEXP (x, 0), 1);
7347 rtx op1 = XEXP (XEXP (x, 1), 1);
7349 cond0 = XEXP (XEXP (x, 0), 0);
7350 cond1 = XEXP (XEXP (x, 1), 0);
7352 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7353 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7354 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7355 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7356 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7357 || ((swap_condition (GET_CODE (cond0))
7358 == combine_reversed_comparison_code (cond1))
7359 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7360 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7361 && ! side_effects_p (x))
7363 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7364 *pfalse = gen_binary (MULT, mode,
7366 ? gen_unary (NEG, mode, mode, op1) : op1),
7372 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7374 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7375 && (code == MULT || code == AND || code == UMIN)
7376 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7378 cond0 = XEXP (XEXP (x, 0), 0);
7379 cond1 = XEXP (XEXP (x, 1), 0);
7381 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7382 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7383 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7384 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7385 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7386 || ((swap_condition (GET_CODE (cond0))
7387 == combine_reversed_comparison_code (cond1))
7388 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7389 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7390 && ! side_effects_p (x))
7392 *ptrue = *pfalse = const0_rtx;
7398 else if (code == IF_THEN_ELSE)
7400 /* If we have IF_THEN_ELSE already, extract the condition and
7401 canonicalize it if it is NE or EQ. */
7402 cond0 = XEXP (x, 0);
7403 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7404 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7405 return XEXP (cond0, 0);
7406 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7408 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7409 return XEXP (cond0, 0);
7415 /* If X is a normal SUBREG with both inner and outer modes integral,
7416 we can narrow both the true and false values of the inner expression,
7417 if there is a condition. */
7418 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7419 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7420 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7421 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7424 if ((GET_CODE (SUBREG_REG (x)) == REG
7425 || GET_CODE (SUBREG_REG (x)) == MEM
7426 || CONSTANT_P (SUBREG_REG (x)))
7427 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7428 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7430 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7431 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7433 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7435 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7440 /* If X is a constant, this isn't special and will cause confusions
7441 if we treat it as such. Likewise if it is equivalent to a constant. */
7442 else if (CONSTANT_P (x)
7443 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7446 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7447 will be least confusing to the rest of the compiler. */
7448 else if (mode == BImode)
7450 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7454 /* If X is known to be either 0 or -1, those are the true and
7455 false values when testing X. */
7456 else if (x == constm1_rtx || x == const0_rtx
7457 || (mode != VOIDmode
7458 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7460 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7464 /* Likewise for 0 or a single bit. */
7465 else if (mode != VOIDmode
7466 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7467 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7469 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7473 /* Otherwise fail; show no condition with true and false values the same. */
7474 *ptrue = *pfalse = x;
7478 /* Return the value of expression X given the fact that condition COND
7479 is known to be true when applied to REG as its first operand and VAL
7480 as its second. X is known to not be shared and so can be modified in
7483 We only handle the simplest cases, and specifically those cases that
7484 arise with IF_THEN_ELSE expressions. */
7487 known_cond (x, cond, reg, val)
7492 enum rtx_code code = GET_CODE (x);
7497 if (side_effects_p (x))
7500 if (cond == EQ && rtx_equal_p (x, reg) && !FLOAT_MODE_P (cond))
7502 if (cond == UNEQ && rtx_equal_p (x, reg))
7505 /* If X is (abs REG) and we know something about REG's relationship
7506 with zero, we may be able to simplify this. */
7508 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7511 case GE: case GT: case EQ:
7514 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7520 /* The only other cases we handle are MIN, MAX, and comparisons if the
7521 operands are the same as REG and VAL. */
7523 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7525 if (rtx_equal_p (XEXP (x, 0), val))
7526 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7528 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7530 if (GET_RTX_CLASS (code) == '<')
7532 if (comparison_dominates_p (cond, code))
7533 return const_true_rtx;
7535 code = combine_reversed_comparison_code (x);
7537 && comparison_dominates_p (cond, code))
7542 else if (code == SMAX || code == SMIN
7543 || code == UMIN || code == UMAX)
7545 int unsignedp = (code == UMIN || code == UMAX);
7547 if (code == SMAX || code == UMAX)
7548 cond = reverse_condition (cond);
7553 return unsignedp ? x : XEXP (x, 1);
7555 return unsignedp ? x : XEXP (x, 0);
7557 return unsignedp ? XEXP (x, 1) : x;
7559 return unsignedp ? XEXP (x, 0) : x;
7567 fmt = GET_RTX_FORMAT (code);
7568 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7571 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7572 else if (fmt[i] == 'E')
7573 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7574 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7581 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7582 assignment as a field assignment. */
7585 rtx_equal_for_field_assignment_p (x, y)
7589 if (x == y || rtx_equal_p (x, y))
7592 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7595 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7596 Note that all SUBREGs of MEM are paradoxical; otherwise they
7597 would have been rewritten. */
7598 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7599 && GET_CODE (SUBREG_REG (y)) == MEM
7600 && rtx_equal_p (SUBREG_REG (y),
7601 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7604 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7605 && GET_CODE (SUBREG_REG (x)) == MEM
7606 && rtx_equal_p (SUBREG_REG (x),
7607 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7610 /* We used to see if get_last_value of X and Y were the same but that's
7611 not correct. In one direction, we'll cause the assignment to have
7612 the wrong destination and in the case, we'll import a register into this
7613 insn that might have already have been dead. So fail if none of the
7614 above cases are true. */
7618 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7619 Return that assignment if so.
7621 We only handle the most common cases. */
7624 make_field_assignment (x)
7627 rtx dest = SET_DEST (x);
7628 rtx src = SET_SRC (x);
7633 unsigned HOST_WIDE_INT len;
7635 enum machine_mode mode;
7637 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7638 a clear of a one-bit field. We will have changed it to
7639 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7642 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7643 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7644 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7645 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7647 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7650 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7654 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7655 && subreg_lowpart_p (XEXP (src, 0))
7656 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7657 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7658 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7659 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7660 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7662 assign = make_extraction (VOIDmode, dest, 0,
7663 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7666 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7670 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7672 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7673 && XEXP (XEXP (src, 0), 0) == const1_rtx
7674 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7676 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7679 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7683 /* The other case we handle is assignments into a constant-position
7684 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7685 a mask that has all one bits except for a group of zero bits and
7686 OTHER is known to have zeros where C1 has ones, this is such an
7687 assignment. Compute the position and length from C1. Shift OTHER
7688 to the appropriate position, force it to the required mode, and
7689 make the extraction. Check for the AND in both operands. */
7691 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7694 rhs = expand_compound_operation (XEXP (src, 0));
7695 lhs = expand_compound_operation (XEXP (src, 1));
7697 if (GET_CODE (rhs) == AND
7698 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7699 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7700 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7701 else if (GET_CODE (lhs) == AND
7702 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7703 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7704 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7708 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7709 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7710 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7711 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7714 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7718 /* The mode to use for the source is the mode of the assignment, or of
7719 what is inside a possible STRICT_LOW_PART. */
7720 mode = (GET_CODE (assign) == STRICT_LOW_PART
7721 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7723 /* Shift OTHER right POS places and make it the source, restricting it
7724 to the proper length and mode. */
7726 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7727 GET_MODE (src), other, pos),
7729 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7730 ? ~(unsigned HOST_WIDE_INT) 0
7731 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7734 return gen_rtx_combine (SET, VOIDmode, assign, src);
7737 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7741 apply_distributive_law (x)
7744 enum rtx_code code = GET_CODE (x);
7745 rtx lhs, rhs, other;
7747 enum rtx_code inner_code;
7749 /* Distributivity is not true for floating point.
7750 It can change the value. So don't do it.
7751 -- rms and moshier@world.std.com. */
7752 if (FLOAT_MODE_P (GET_MODE (x)))
7755 /* The outer operation can only be one of the following: */
7756 if (code != IOR && code != AND && code != XOR
7757 && code != PLUS && code != MINUS)
7760 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7762 /* If either operand is a primitive we can't do anything, so get out
7764 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7765 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7768 lhs = expand_compound_operation (lhs);
7769 rhs = expand_compound_operation (rhs);
7770 inner_code = GET_CODE (lhs);
7771 if (inner_code != GET_CODE (rhs))
7774 /* See if the inner and outer operations distribute. */
7781 /* These all distribute except over PLUS. */
7782 if (code == PLUS || code == MINUS)
7787 if (code != PLUS && code != MINUS)
7792 /* This is also a multiply, so it distributes over everything. */
7796 /* Non-paradoxical SUBREGs distributes over all operations, provided
7797 the inner modes and word numbers are the same, this is an extraction
7798 of a low-order part, we don't convert an fp operation to int or
7799 vice versa, and we would not be converting a single-word
7800 operation into a multi-word operation. The latter test is not
7801 required, but it prevents generating unneeded multi-word operations.
7802 Some of the previous tests are redundant given the latter test, but
7803 are retained because they are required for correctness.
7805 We produce the result slightly differently in this case. */
7807 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7808 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7809 || ! subreg_lowpart_p (lhs)
7810 || (GET_MODE_CLASS (GET_MODE (lhs))
7811 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7812 || (GET_MODE_SIZE (GET_MODE (lhs))
7813 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7814 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7817 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7818 SUBREG_REG (lhs), SUBREG_REG (rhs));
7819 return gen_lowpart_for_combine (GET_MODE (x), tem);
7825 /* Set LHS and RHS to the inner operands (A and B in the example
7826 above) and set OTHER to the common operand (C in the example).
7827 These is only one way to do this unless the inner operation is
7829 if (GET_RTX_CLASS (inner_code) == 'c'
7830 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7831 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7832 else if (GET_RTX_CLASS (inner_code) == 'c'
7833 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7834 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7835 else if (GET_RTX_CLASS (inner_code) == 'c'
7836 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7837 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7838 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7839 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7843 /* Form the new inner operation, seeing if it simplifies first. */
7844 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7846 /* There is one exception to the general way of distributing:
7847 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7848 if (code == XOR && inner_code == IOR)
7851 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7854 /* We may be able to continuing distributing the result, so call
7855 ourselves recursively on the inner operation before forming the
7856 outer operation, which we return. */
7857 return gen_binary (inner_code, GET_MODE (x),
7858 apply_distributive_law (tem), other);
7861 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7864 Return an equivalent form, if different from X. Otherwise, return X. If
7865 X is zero, we are to always construct the equivalent form. */
7868 simplify_and_const_int (x, mode, varop, constop)
7870 enum machine_mode mode;
7872 unsigned HOST_WIDE_INT constop;
7874 unsigned HOST_WIDE_INT nonzero;
7877 /* Simplify VAROP knowing that we will be only looking at some of the
7879 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7881 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7882 CONST_INT, we are done. */
7883 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7886 /* See what bits may be nonzero in VAROP. Unlike the general case of
7887 a call to nonzero_bits, here we don't care about bits outside
7890 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7891 nonzero = trunc_int_for_mode (nonzero, mode);
7893 /* Turn off all bits in the constant that are known to already be zero.
7894 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7895 which is tested below. */
7899 /* If we don't have any bits left, return zero. */
7903 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7904 a power of two, we can replace this with a ASHIFT. */
7905 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7906 && (i = exact_log2 (constop)) >= 0)
7907 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7909 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7910 or XOR, then try to apply the distributive law. This may eliminate
7911 operations if either branch can be simplified because of the AND.
7912 It may also make some cases more complex, but those cases probably
7913 won't match a pattern either with or without this. */
7915 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7917 gen_lowpart_for_combine
7919 apply_distributive_law
7920 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7921 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7922 XEXP (varop, 0), constop),
7923 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7924 XEXP (varop, 1), constop))));
7926 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7927 if we already had one (just check for the simplest cases). */
7928 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7929 && GET_MODE (XEXP (x, 0)) == mode
7930 && SUBREG_REG (XEXP (x, 0)) == varop)
7931 varop = XEXP (x, 0);
7933 varop = gen_lowpart_for_combine (mode, varop);
7935 /* If we can't make the SUBREG, try to return what we were given. */
7936 if (GET_CODE (varop) == CLOBBER)
7937 return x ? x : varop;
7939 /* If we are only masking insignificant bits, return VAROP. */
7940 if (constop == nonzero)
7943 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7944 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7945 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7949 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7950 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7951 SUBST (XEXP (x, 1), GEN_INT (constop));
7953 SUBST (XEXP (x, 0), varop);
7959 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7960 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7961 is less useful. We can't allow both, because that results in exponential
7962 run time recursion. There is a nullstone testcase that triggered
7963 this. This macro avoids accidental uses of num_sign_bit_copies. */
7964 #define num_sign_bit_copies()
7966 /* Given an expression, X, compute which bits in X can be non-zero.
7967 We don't care about bits outside of those defined in MODE.
7969 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7970 a shift, AND, or zero_extract, we can do better. */
7972 static unsigned HOST_WIDE_INT
7973 nonzero_bits (x, mode)
7975 enum machine_mode mode;
7977 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7978 unsigned HOST_WIDE_INT inner_nz;
7980 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7983 /* For floating-point values, assume all bits are needed. */
7984 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7987 /* If X is wider than MODE, use its mode instead. */
7988 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7990 mode = GET_MODE (x);
7991 nonzero = GET_MODE_MASK (mode);
7992 mode_width = GET_MODE_BITSIZE (mode);
7995 if (mode_width > HOST_BITS_PER_WIDE_INT)
7996 /* Our only callers in this case look for single bit values. So
7997 just return the mode mask. Those tests will then be false. */
8000 #ifndef WORD_REGISTER_OPERATIONS
8001 /* If MODE is wider than X, but both are a single word for both the host
8002 and target machines, we can compute this from which bits of the
8003 object might be nonzero in its own mode, taking into account the fact
8004 that on many CISC machines, accessing an object in a wider mode
8005 causes the high-order bits to become undefined. So they are
8006 not known to be zero. */
8008 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8009 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8010 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8011 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8013 nonzero &= nonzero_bits (x, GET_MODE (x));
8014 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8019 code = GET_CODE (x);
8023 #ifdef POINTERS_EXTEND_UNSIGNED
8024 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8025 all the bits above ptr_mode are known to be zero. */
8026 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8028 nonzero &= GET_MODE_MASK (ptr_mode);
8031 #ifdef STACK_BOUNDARY
8032 /* If this is the stack pointer, we may know something about its
8033 alignment. If PUSH_ROUNDING is defined, it is possible for the
8034 stack to be momentarily aligned only to that amount, so we pick
8035 the least alignment. */
8037 /* We can't check for arg_pointer_rtx here, because it is not
8038 guaranteed to have as much alignment as the stack pointer.
8039 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8040 alignment but the argument pointer has only 64 bit alignment. */
8042 if ((x == frame_pointer_rtx
8043 || x == stack_pointer_rtx
8044 || x == hard_frame_pointer_rtx
8045 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
8046 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
8052 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8054 #ifdef PUSH_ROUNDING
8055 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
8056 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
8059 /* We must return here, otherwise we may get a worse result from
8060 one of the choices below. There is nothing useful below as
8061 far as the stack pointer is concerned. */
8062 return nonzero &= ~(sp_alignment - 1);
8066 /* If X is a register whose nonzero bits value is current, use it.
8067 Otherwise, if X is a register whose value we can find, use that
8068 value. Otherwise, use the previously-computed global nonzero bits
8069 for this register. */
8071 if (reg_last_set_value[REGNO (x)] != 0
8072 && reg_last_set_mode[REGNO (x)] == mode
8073 && (reg_last_set_label[REGNO (x)] == label_tick
8074 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8075 && REG_N_SETS (REGNO (x)) == 1
8076 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8078 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8079 return reg_last_set_nonzero_bits[REGNO (x)];
8081 tem = get_last_value (x);
8085 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8086 /* If X is narrower than MODE and TEM is a non-negative
8087 constant that would appear negative in the mode of X,
8088 sign-extend it for use in reg_nonzero_bits because some
8089 machines (maybe most) will actually do the sign-extension
8090 and this is the conservative approach.
8092 ??? For 2.5, try to tighten up the MD files in this regard
8093 instead of this kludge. */
8095 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8096 && GET_CODE (tem) == CONST_INT
8098 && 0 != (INTVAL (tem)
8099 & ((HOST_WIDE_INT) 1
8100 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8101 tem = GEN_INT (INTVAL (tem)
8102 | ((HOST_WIDE_INT) (-1)
8103 << GET_MODE_BITSIZE (GET_MODE (x))));
8105 return nonzero_bits (tem, mode);
8107 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8108 return reg_nonzero_bits[REGNO (x)] & nonzero;
8113 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8114 /* If X is negative in MODE, sign-extend the value. */
8115 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8116 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8117 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8123 #ifdef LOAD_EXTEND_OP
8124 /* In many, if not most, RISC machines, reading a byte from memory
8125 zeros the rest of the register. Noticing that fact saves a lot
8126 of extra zero-extends. */
8127 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8128 nonzero &= GET_MODE_MASK (GET_MODE (x));
8133 case UNEQ: case LTGT:
8134 case GT: case GTU: case UNGT:
8135 case LT: case LTU: case UNLT:
8136 case GE: case GEU: case UNGE:
8137 case LE: case LEU: case UNLE:
8138 case UNORDERED: case ORDERED:
8140 /* If this produces an integer result, we know which bits are set.
8141 Code here used to clear bits outside the mode of X, but that is
8144 if (GET_MODE_CLASS (mode) == MODE_INT
8145 && mode_width <= HOST_BITS_PER_WIDE_INT)
8146 nonzero = STORE_FLAG_VALUE;
8151 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8152 and num_sign_bit_copies. */
8153 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8154 == GET_MODE_BITSIZE (GET_MODE (x)))
8158 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8159 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8164 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8165 and num_sign_bit_copies. */
8166 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8167 == GET_MODE_BITSIZE (GET_MODE (x)))
8173 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8177 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8178 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8179 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8183 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8184 Otherwise, show all the bits in the outer mode but not the inner
8186 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8187 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8189 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8191 & (((HOST_WIDE_INT) 1
8192 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8193 inner_nz |= (GET_MODE_MASK (mode)
8194 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8197 nonzero &= inner_nz;
8201 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8202 & nonzero_bits (XEXP (x, 1), mode));
8206 case UMIN: case UMAX: case SMIN: case SMAX:
8207 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8208 | nonzero_bits (XEXP (x, 1), mode));
8211 case PLUS: case MINUS:
8213 case DIV: case UDIV:
8214 case MOD: case UMOD:
8215 /* We can apply the rules of arithmetic to compute the number of
8216 high- and low-order zero bits of these operations. We start by
8217 computing the width (position of the highest-order non-zero bit)
8218 and the number of low-order zero bits for each value. */
8220 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8221 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8222 int width0 = floor_log2 (nz0) + 1;
8223 int width1 = floor_log2 (nz1) + 1;
8224 int low0 = floor_log2 (nz0 & -nz0);
8225 int low1 = floor_log2 (nz1 & -nz1);
8226 HOST_WIDE_INT op0_maybe_minusp
8227 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8228 HOST_WIDE_INT op1_maybe_minusp
8229 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8230 unsigned int result_width = mode_width;
8238 && (XEXP (x, 0) == stack_pointer_rtx
8239 || XEXP (x, 0) == frame_pointer_rtx)
8240 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8242 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8244 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8245 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8246 width0 = floor_log2 (nz0) + 1;
8247 width1 = floor_log2 (nz1) + 1;
8248 low0 = floor_log2 (nz0 & -nz0);
8249 low1 = floor_log2 (nz1 & -nz1);
8252 result_width = MAX (width0, width1) + 1;
8253 result_low = MIN (low0, low1);
8256 result_low = MIN (low0, low1);
8259 result_width = width0 + width1;
8260 result_low = low0 + low1;
8263 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8264 result_width = width0;
8267 result_width = width0;
8270 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8271 result_width = MIN (width0, width1);
8272 result_low = MIN (low0, low1);
8275 result_width = MIN (width0, width1);
8276 result_low = MIN (low0, low1);
8282 if (result_width < mode_width)
8283 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8286 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8291 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8292 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8293 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8297 /* If this is a SUBREG formed for a promoted variable that has
8298 been zero-extended, we know that at least the high-order bits
8299 are zero, though others might be too. */
8301 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8302 nonzero = (GET_MODE_MASK (GET_MODE (x))
8303 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8305 /* If the inner mode is a single word for both the host and target
8306 machines, we can compute this from which bits of the inner
8307 object might be nonzero. */
8308 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8309 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8310 <= HOST_BITS_PER_WIDE_INT))
8312 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8314 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8315 /* If this is a typical RISC machine, we only have to worry
8316 about the way loads are extended. */
8317 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8319 & (((unsigned HOST_WIDE_INT) 1
8320 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8322 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8325 /* On many CISC machines, accessing an object in a wider mode
8326 causes the high-order bits to become undefined. So they are
8327 not known to be zero. */
8328 if (GET_MODE_SIZE (GET_MODE (x))
8329 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8330 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8331 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8340 /* The nonzero bits are in two classes: any bits within MODE
8341 that aren't in GET_MODE (x) are always significant. The rest of the
8342 nonzero bits are those that are significant in the operand of
8343 the shift when shifted the appropriate number of bits. This
8344 shows that high-order bits are cleared by the right shift and
8345 low-order bits by left shifts. */
8346 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8347 && INTVAL (XEXP (x, 1)) >= 0
8348 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8350 enum machine_mode inner_mode = GET_MODE (x);
8351 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8352 int count = INTVAL (XEXP (x, 1));
8353 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8354 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8355 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8356 unsigned HOST_WIDE_INT outer = 0;
8358 if (mode_width > width)
8359 outer = (op_nonzero & nonzero & ~mode_mask);
8361 if (code == LSHIFTRT)
8363 else if (code == ASHIFTRT)
8367 /* If the sign bit may have been nonzero before the shift, we
8368 need to mark all the places it could have been copied to
8369 by the shift as possibly nonzero. */
8370 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8371 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8373 else if (code == ASHIFT)
8376 inner = ((inner << (count % width)
8377 | (inner >> (width - (count % width)))) & mode_mask);
8379 nonzero &= (outer | inner);
8384 /* This is at most the number of bits in the mode. */
8385 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8389 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8390 | nonzero_bits (XEXP (x, 2), mode));
8400 /* See the macro definition above. */
8401 #undef num_sign_bit_copies
8403 /* Return the number of bits at the high-order end of X that are known to
8404 be equal to the sign bit. X will be used in mode MODE; if MODE is
8405 VOIDmode, X will be used in its own mode. The returned value will always
8406 be between 1 and the number of bits in MODE. */
8409 num_sign_bit_copies (x, mode)
8411 enum machine_mode mode;
8413 enum rtx_code code = GET_CODE (x);
8414 unsigned int bitwidth;
8415 int num0, num1, result;
8416 unsigned HOST_WIDE_INT nonzero;
8419 /* If we weren't given a mode, use the mode of X. If the mode is still
8420 VOIDmode, we don't know anything. Likewise if one of the modes is
8423 if (mode == VOIDmode)
8424 mode = GET_MODE (x);
8426 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8429 bitwidth = GET_MODE_BITSIZE (mode);
8431 /* For a smaller object, just ignore the high bits. */
8432 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8434 num0 = num_sign_bit_copies (x, GET_MODE (x));
8436 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8439 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8441 #ifndef WORD_REGISTER_OPERATIONS
8442 /* If this machine does not do all register operations on the entire
8443 register and MODE is wider than the mode of X, we can say nothing
8444 at all about the high-order bits. */
8447 /* Likewise on machines that do, if the mode of the object is smaller
8448 than a word and loads of that size don't sign extend, we can say
8449 nothing about the high order bits. */
8450 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8451 #ifdef LOAD_EXTEND_OP
8452 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8463 #ifdef POINTERS_EXTEND_UNSIGNED
8464 /* If pointers extend signed and this is a pointer in Pmode, say that
8465 all the bits above ptr_mode are known to be sign bit copies. */
8466 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8468 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8471 if (reg_last_set_value[REGNO (x)] != 0
8472 && reg_last_set_mode[REGNO (x)] == mode
8473 && (reg_last_set_label[REGNO (x)] == label_tick
8474 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8475 && REG_N_SETS (REGNO (x)) == 1
8476 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8478 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8479 return reg_last_set_sign_bit_copies[REGNO (x)];
8481 tem = get_last_value (x);
8483 return num_sign_bit_copies (tem, mode);
8485 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8486 return reg_sign_bit_copies[REGNO (x)];
8490 #ifdef LOAD_EXTEND_OP
8491 /* Some RISC machines sign-extend all loads of smaller than a word. */
8492 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8493 return MAX (1, ((int) bitwidth
8494 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8499 /* If the constant is negative, take its 1's complement and remask.
8500 Then see how many zero bits we have. */
8501 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8502 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8503 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8504 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8506 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8509 /* If this is a SUBREG for a promoted object that is sign-extended
8510 and we are looking at it in a wider mode, we know that at least the
8511 high-order bits are known to be sign bit copies. */
8513 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8515 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8516 return MAX ((int) bitwidth
8517 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8521 /* For a smaller object, just ignore the high bits. */
8522 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8524 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8525 return MAX (1, (num0
8526 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8530 #ifdef WORD_REGISTER_OPERATIONS
8531 #ifdef LOAD_EXTEND_OP
8532 /* For paradoxical SUBREGs on machines where all register operations
8533 affect the entire register, just look inside. Note that we are
8534 passing MODE to the recursive call, so the number of sign bit copies
8535 will remain relative to that mode, not the inner mode. */
8537 /* This works only if loads sign extend. Otherwise, if we get a
8538 reload for the inner part, it may be loaded from the stack, and
8539 then we lose all sign bit copies that existed before the store
8542 if ((GET_MODE_SIZE (GET_MODE (x))
8543 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8544 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8545 return num_sign_bit_copies (SUBREG_REG (x), mode);
8551 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8552 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8556 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8557 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8560 /* For a smaller object, just ignore the high bits. */
8561 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8562 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8566 return num_sign_bit_copies (XEXP (x, 0), mode);
8568 case ROTATE: case ROTATERT:
8569 /* If we are rotating left by a number of bits less than the number
8570 of sign bit copies, we can just subtract that amount from the
8572 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8573 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8575 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8576 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8577 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8582 /* In general, this subtracts one sign bit copy. But if the value
8583 is known to be positive, the number of sign bit copies is the
8584 same as that of the input. Finally, if the input has just one bit
8585 that might be nonzero, all the bits are copies of the sign bit. */
8586 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8587 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8588 return num0 > 1 ? num0 - 1 : 1;
8590 nonzero = nonzero_bits (XEXP (x, 0), mode);
8595 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8600 case IOR: case AND: case XOR:
8601 case SMIN: case SMAX: case UMIN: case UMAX:
8602 /* Logical operations will preserve the number of sign-bit copies.
8603 MIN and MAX operations always return one of the operands. */
8604 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8605 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8606 return MIN (num0, num1);
8608 case PLUS: case MINUS:
8609 /* For addition and subtraction, we can have a 1-bit carry. However,
8610 if we are subtracting 1 from a positive number, there will not
8611 be such a carry. Furthermore, if the positive number is known to
8612 be 0 or 1, we know the result is either -1 or 0. */
8614 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8615 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8617 nonzero = nonzero_bits (XEXP (x, 0), mode);
8618 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8619 return (nonzero == 1 || nonzero == 0 ? bitwidth
8620 : bitwidth - floor_log2 (nonzero) - 1);
8623 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8624 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8625 return MAX (1, MIN (num0, num1) - 1);
8628 /* The number of bits of the product is the sum of the number of
8629 bits of both terms. However, unless one of the terms if known
8630 to be positive, we must allow for an additional bit since negating
8631 a negative number can remove one sign bit copy. */
8633 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8634 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8636 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8638 && (bitwidth > HOST_BITS_PER_WIDE_INT
8639 || (((nonzero_bits (XEXP (x, 0), mode)
8640 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8641 && ((nonzero_bits (XEXP (x, 1), mode)
8642 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8645 return MAX (1, result);
8648 /* The result must be <= the first operand. If the first operand
8649 has the high bit set, we know nothing about the number of sign
8651 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8653 else if ((nonzero_bits (XEXP (x, 0), mode)
8654 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8657 return num_sign_bit_copies (XEXP (x, 0), mode);
8660 /* The result must be <= the scond operand. */
8661 return num_sign_bit_copies (XEXP (x, 1), mode);
8664 /* Similar to unsigned division, except that we have to worry about
8665 the case where the divisor is negative, in which case we have
8667 result = num_sign_bit_copies (XEXP (x, 0), mode);
8669 && (bitwidth > HOST_BITS_PER_WIDE_INT
8670 || (nonzero_bits (XEXP (x, 1), mode)
8671 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8677 result = num_sign_bit_copies (XEXP (x, 1), mode);
8679 && (bitwidth > HOST_BITS_PER_WIDE_INT
8680 || (nonzero_bits (XEXP (x, 1), mode)
8681 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8687 /* Shifts by a constant add to the number of bits equal to the
8689 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8690 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8691 && INTVAL (XEXP (x, 1)) > 0)
8692 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8697 /* Left shifts destroy copies. */
8698 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8699 || INTVAL (XEXP (x, 1)) < 0
8700 || INTVAL (XEXP (x, 1)) >= bitwidth)
8703 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8704 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8707 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8708 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8709 return MIN (num0, num1);
8711 case EQ: case NE: case GE: case GT: case LE: case LT:
8712 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8713 case GEU: case GTU: case LEU: case LTU:
8714 case UNORDERED: case ORDERED:
8715 /* If the constant is negative, take its 1's complement and remask.
8716 Then see how many zero bits we have. */
8717 nonzero = STORE_FLAG_VALUE;
8718 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8719 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8720 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8722 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8729 /* If we haven't been able to figure it out by one of the above rules,
8730 see if some of the high-order bits are known to be zero. If so,
8731 count those bits and return one less than that amount. If we can't
8732 safely compute the mask for this mode, always return BITWIDTH. */
8734 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8737 nonzero = nonzero_bits (x, mode);
8738 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8739 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8742 /* Return the number of "extended" bits there are in X, when interpreted
8743 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8744 unsigned quantities, this is the number of high-order zero bits.
8745 For signed quantities, this is the number of copies of the sign bit
8746 minus 1. In both case, this function returns the number of "spare"
8747 bits. For example, if two quantities for which this function returns
8748 at least 1 are added, the addition is known not to overflow.
8750 This function will always return 0 unless called during combine, which
8751 implies that it must be called from a define_split. */
8754 extended_count (x, mode, unsignedp)
8756 enum machine_mode mode;
8759 if (nonzero_sign_valid == 0)
8763 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8764 ? (GET_MODE_BITSIZE (mode) - 1
8765 - floor_log2 (nonzero_bits (x, mode)))
8767 : num_sign_bit_copies (x, mode) - 1);
8770 /* This function is called from `simplify_shift_const' to merge two
8771 outer operations. Specifically, we have already found that we need
8772 to perform operation *POP0 with constant *PCONST0 at the outermost
8773 position. We would now like to also perform OP1 with constant CONST1
8774 (with *POP0 being done last).
8776 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8777 the resulting operation. *PCOMP_P is set to 1 if we would need to
8778 complement the innermost operand, otherwise it is unchanged.
8780 MODE is the mode in which the operation will be done. No bits outside
8781 the width of this mode matter. It is assumed that the width of this mode
8782 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8784 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8785 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8786 result is simply *PCONST0.
8788 If the resulting operation cannot be expressed as one operation, we
8789 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8792 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8793 enum rtx_code *pop0;
8794 HOST_WIDE_INT *pconst0;
8796 HOST_WIDE_INT const1;
8797 enum machine_mode mode;
8800 enum rtx_code op0 = *pop0;
8801 HOST_WIDE_INT const0 = *pconst0;
8803 const0 &= GET_MODE_MASK (mode);
8804 const1 &= GET_MODE_MASK (mode);
8806 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8810 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8813 if (op1 == NIL || op0 == SET)
8816 else if (op0 == NIL)
8817 op0 = op1, const0 = const1;
8819 else if (op0 == op1)
8843 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8844 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8847 /* If the two constants aren't the same, we can't do anything. The
8848 remaining six cases can all be done. */
8849 else if (const0 != const1)
8857 /* (a & b) | b == b */
8859 else /* op1 == XOR */
8860 /* (a ^ b) | b == a | b */
8866 /* (a & b) ^ b == (~a) & b */
8867 op0 = AND, *pcomp_p = 1;
8868 else /* op1 == IOR */
8869 /* (a | b) ^ b == a & ~b */
8870 op0 = AND, *pconst0 = ~const0;
8875 /* (a | b) & b == b */
8877 else /* op1 == XOR */
8878 /* (a ^ b) & b) == (~a) & b */
8885 /* Check for NO-OP cases. */
8886 const0 &= GET_MODE_MASK (mode);
8888 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8890 else if (const0 == 0 && op0 == AND)
8892 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8896 /* ??? Slightly redundant with the above mask, but not entirely.
8897 Moving this above means we'd have to sign-extend the mode mask
8898 for the final test. */
8899 const0 = trunc_int_for_mode (const0, mode);
8907 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8908 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8909 that we started with.
8911 The shift is normally computed in the widest mode we find in VAROP, as
8912 long as it isn't a different number of words than RESULT_MODE. Exceptions
8913 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8916 simplify_shift_const (x, code, result_mode, varop, input_count)
8919 enum machine_mode result_mode;
8923 enum rtx_code orig_code = code;
8924 int orig_count = input_count;
8927 enum machine_mode mode = result_mode;
8928 enum machine_mode shift_mode, tmode;
8929 unsigned int mode_words
8930 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8931 /* We form (outer_op (code varop count) (outer_const)). */
8932 enum rtx_code outer_op = NIL;
8933 HOST_WIDE_INT outer_const = 0;
8935 int complement_p = 0;
8938 /* If we were given an invalid count, don't do anything except exactly
8939 what was requested. */
8941 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8946 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8949 count = input_count;
8951 /* Make sure and truncate the "natural" shift on the way in. We don't
8952 want to do this inside the loop as it makes it more difficult to
8954 #ifdef SHIFT_COUNT_TRUNCATED
8955 if (SHIFT_COUNT_TRUNCATED)
8956 count %= GET_MODE_BITSIZE (mode);
8959 /* Unless one of the branches of the `if' in this loop does a `continue',
8960 we will `break' the loop after the `if'. */
8964 /* If we have an operand of (clobber (const_int 0)), just return that
8966 if (GET_CODE (varop) == CLOBBER)
8969 /* If we discovered we had to complement VAROP, leave. Making a NOT
8970 here would cause an infinite loop. */
8974 /* Convert ROTATERT to ROTATE. */
8975 if (code == ROTATERT)
8976 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8978 /* We need to determine what mode we will do the shift in. If the
8979 shift is a right shift or a ROTATE, we must always do it in the mode
8980 it was originally done in. Otherwise, we can do it in MODE, the
8981 widest mode encountered. */
8983 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8984 ? result_mode : mode);
8986 /* Handle cases where the count is greater than the size of the mode
8987 minus 1. For ASHIFT, use the size minus one as the count (this can
8988 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8989 take the count modulo the size. For other shifts, the result is
8992 Since these shifts are being produced by the compiler by combining
8993 multiple operations, each of which are defined, we know what the
8994 result is supposed to be. */
8996 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8998 if (code == ASHIFTRT)
8999 count = GET_MODE_BITSIZE (shift_mode) - 1;
9000 else if (code == ROTATE || code == ROTATERT)
9001 count %= GET_MODE_BITSIZE (shift_mode);
9004 /* We can't simply return zero because there may be an
9012 /* An arithmetic right shift of a quantity known to be -1 or 0
9014 if (code == ASHIFTRT
9015 && (num_sign_bit_copies (varop, shift_mode)
9016 == GET_MODE_BITSIZE (shift_mode)))
9022 /* If we are doing an arithmetic right shift and discarding all but
9023 the sign bit copies, this is equivalent to doing a shift by the
9024 bitsize minus one. Convert it into that shift because it will often
9025 allow other simplifications. */
9027 if (code == ASHIFTRT
9028 && (count + num_sign_bit_copies (varop, shift_mode)
9029 >= GET_MODE_BITSIZE (shift_mode)))
9030 count = GET_MODE_BITSIZE (shift_mode) - 1;
9032 /* We simplify the tests below and elsewhere by converting
9033 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9034 `make_compound_operation' will convert it to a ASHIFTRT for
9035 those machines (such as Vax) that don't have a LSHIFTRT. */
9036 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9038 && ((nonzero_bits (varop, shift_mode)
9039 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9043 switch (GET_CODE (varop))
9049 new = expand_compound_operation (varop);
9058 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9059 minus the width of a smaller mode, we can do this with a
9060 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9061 if ((code == ASHIFTRT || code == LSHIFTRT)
9062 && ! mode_dependent_address_p (XEXP (varop, 0))
9063 && ! MEM_VOLATILE_P (varop)
9064 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9065 MODE_INT, 1)) != BLKmode)
9067 if (BYTES_BIG_ENDIAN)
9068 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
9070 new = gen_rtx_MEM (tmode,
9071 plus_constant (XEXP (varop, 0),
9072 count / BITS_PER_UNIT));
9074 MEM_COPY_ATTRIBUTES (new, varop);
9075 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9076 : ZERO_EXTEND, mode, new);
9083 /* Similar to the case above, except that we can only do this if
9084 the resulting mode is the same as that of the underlying
9085 MEM and adjust the address depending on the *bits* endianness
9086 because of the way that bit-field extract insns are defined. */
9087 if ((code == ASHIFTRT || code == LSHIFTRT)
9088 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9089 MODE_INT, 1)) != BLKmode
9090 && tmode == GET_MODE (XEXP (varop, 0)))
9092 if (BITS_BIG_ENDIAN)
9093 new = XEXP (varop, 0);
9096 new = copy_rtx (XEXP (varop, 0));
9097 SUBST (XEXP (new, 0),
9098 plus_constant (XEXP (new, 0),
9099 count / BITS_PER_UNIT));
9102 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9103 : ZERO_EXTEND, mode, new);
9110 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9111 the same number of words as what we've seen so far. Then store
9112 the widest mode in MODE. */
9113 if (subreg_lowpart_p (varop)
9114 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9115 > GET_MODE_SIZE (GET_MODE (varop)))
9116 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9117 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9120 varop = SUBREG_REG (varop);
9121 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9122 mode = GET_MODE (varop);
9128 /* Some machines use MULT instead of ASHIFT because MULT
9129 is cheaper. But it is still better on those machines to
9130 merge two shifts into one. */
9131 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9132 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9135 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9136 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9142 /* Similar, for when divides are cheaper. */
9143 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9144 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9147 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9148 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9154 /* If we are extracting just the sign bit of an arithmetic
9155 right shift, that shift is not needed. However, the sign
9156 bit of a wider mode may be different from what would be
9157 interpreted as the sign bit in a narrower mode, so, if
9158 the result is narrower, don't discard the shift. */
9159 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9160 && (GET_MODE_BITSIZE (result_mode)
9161 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9163 varop = XEXP (varop, 0);
9167 /* ... fall through ... */
9172 /* Here we have two nested shifts. The result is usually the
9173 AND of a new shift with a mask. We compute the result below. */
9174 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9175 && INTVAL (XEXP (varop, 1)) >= 0
9176 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9177 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9180 enum rtx_code first_code = GET_CODE (varop);
9181 unsigned int first_count = INTVAL (XEXP (varop, 1));
9182 unsigned HOST_WIDE_INT mask;
9185 /* We have one common special case. We can't do any merging if
9186 the inner code is an ASHIFTRT of a smaller mode. However, if
9187 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9188 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9189 we can convert it to
9190 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9191 This simplifies certain SIGN_EXTEND operations. */
9192 if (code == ASHIFT && first_code == ASHIFTRT
9193 && (GET_MODE_BITSIZE (result_mode)
9194 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9196 /* C3 has the low-order C1 bits zero. */
9198 mask = (GET_MODE_MASK (mode)
9199 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9201 varop = simplify_and_const_int (NULL_RTX, result_mode,
9202 XEXP (varop, 0), mask);
9203 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9205 count = first_count;
9210 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9211 than C1 high-order bits equal to the sign bit, we can convert
9212 this to either an ASHIFT or a ASHIFTRT depending on the
9215 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9217 if (code == ASHIFTRT && first_code == ASHIFT
9218 && GET_MODE (varop) == shift_mode
9219 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9222 varop = XEXP (varop, 0);
9224 signed_count = count - first_count;
9225 if (signed_count < 0)
9226 count = -signed_count, code = ASHIFT;
9228 count = signed_count;
9233 /* There are some cases we can't do. If CODE is ASHIFTRT,
9234 we can only do this if FIRST_CODE is also ASHIFTRT.
9236 We can't do the case when CODE is ROTATE and FIRST_CODE is
9239 If the mode of this shift is not the mode of the outer shift,
9240 we can't do this if either shift is a right shift or ROTATE.
9242 Finally, we can't do any of these if the mode is too wide
9243 unless the codes are the same.
9245 Handle the case where the shift codes are the same
9248 if (code == first_code)
9250 if (GET_MODE (varop) != result_mode
9251 && (code == ASHIFTRT || code == LSHIFTRT
9255 count += first_count;
9256 varop = XEXP (varop, 0);
9260 if (code == ASHIFTRT
9261 || (code == ROTATE && first_code == ASHIFTRT)
9262 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9263 || (GET_MODE (varop) != result_mode
9264 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9265 || first_code == ROTATE
9266 || code == ROTATE)))
9269 /* To compute the mask to apply after the shift, shift the
9270 nonzero bits of the inner shift the same way the
9271 outer shift will. */
9273 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9276 = simplify_binary_operation (code, result_mode, mask_rtx,
9279 /* Give up if we can't compute an outer operation to use. */
9281 || GET_CODE (mask_rtx) != CONST_INT
9282 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9284 result_mode, &complement_p))
9287 /* If the shifts are in the same direction, we add the
9288 counts. Otherwise, we subtract them. */
9289 signed_count = count;
9290 if ((code == ASHIFTRT || code == LSHIFTRT)
9291 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9292 signed_count += first_count;
9294 signed_count -= first_count;
9296 /* If COUNT is positive, the new shift is usually CODE,
9297 except for the two exceptions below, in which case it is
9298 FIRST_CODE. If the count is negative, FIRST_CODE should
9300 if (signed_count > 0
9301 && ((first_code == ROTATE && code == ASHIFT)
9302 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9303 code = first_code, count = signed_count;
9304 else if (signed_count < 0)
9305 code = first_code, count = -signed_count;
9307 count = signed_count;
9309 varop = XEXP (varop, 0);
9313 /* If we have (A << B << C) for any shift, we can convert this to
9314 (A << C << B). This wins if A is a constant. Only try this if
9315 B is not a constant. */
9317 else if (GET_CODE (varop) == code
9318 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9320 = simplify_binary_operation (code, mode,
9324 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9331 /* Make this fit the case below. */
9332 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9333 GEN_INT (GET_MODE_MASK (mode)));
9339 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9340 with C the size of VAROP - 1 and the shift is logical if
9341 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9342 we have an (le X 0) operation. If we have an arithmetic shift
9343 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9344 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9346 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9347 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9348 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9349 && (code == LSHIFTRT || code == ASHIFTRT)
9350 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9351 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9354 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9357 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9358 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9363 /* If we have (shift (logical)), move the logical to the outside
9364 to allow it to possibly combine with another logical and the
9365 shift to combine with another shift. This also canonicalizes to
9366 what a ZERO_EXTRACT looks like. Also, some machines have
9367 (and (shift)) insns. */
9369 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9370 && (new = simplify_binary_operation (code, result_mode,
9372 GEN_INT (count))) != 0
9373 && GET_CODE (new) == CONST_INT
9374 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9375 INTVAL (new), result_mode, &complement_p))
9377 varop = XEXP (varop, 0);
9381 /* If we can't do that, try to simplify the shift in each arm of the
9382 logical expression, make a new logical expression, and apply
9383 the inverse distributive law. */
9385 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9386 XEXP (varop, 0), count);
9387 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9388 XEXP (varop, 1), count);
9390 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9391 varop = apply_distributive_law (varop);
9398 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9399 says that the sign bit can be tested, FOO has mode MODE, C is
9400 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9401 that may be nonzero. */
9402 if (code == LSHIFTRT
9403 && XEXP (varop, 1) == const0_rtx
9404 && GET_MODE (XEXP (varop, 0)) == result_mode
9405 && count == GET_MODE_BITSIZE (result_mode) - 1
9406 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9407 && ((STORE_FLAG_VALUE
9408 & ((HOST_WIDE_INT) 1
9409 < (GET_MODE_BITSIZE (result_mode) - 1))))
9410 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9411 && merge_outer_ops (&outer_op, &outer_const, XOR,
9412 (HOST_WIDE_INT) 1, result_mode,
9415 varop = XEXP (varop, 0);
9422 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9423 than the number of bits in the mode is equivalent to A. */
9424 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9425 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9427 varop = XEXP (varop, 0);
9432 /* NEG commutes with ASHIFT since it is multiplication. Move the
9433 NEG outside to allow shifts to combine. */
9435 && merge_outer_ops (&outer_op, &outer_const, NEG,
9436 (HOST_WIDE_INT) 0, result_mode,
9439 varop = XEXP (varop, 0);
9445 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9446 is one less than the number of bits in the mode is
9447 equivalent to (xor A 1). */
9448 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9449 && XEXP (varop, 1) == constm1_rtx
9450 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9451 && merge_outer_ops (&outer_op, &outer_const, XOR,
9452 (HOST_WIDE_INT) 1, result_mode,
9456 varop = XEXP (varop, 0);
9460 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9461 that might be nonzero in BAR are those being shifted out and those
9462 bits are known zero in FOO, we can replace the PLUS with FOO.
9463 Similarly in the other operand order. This code occurs when
9464 we are computing the size of a variable-size array. */
9466 if ((code == ASHIFTRT || code == LSHIFTRT)
9467 && count < HOST_BITS_PER_WIDE_INT
9468 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9469 && (nonzero_bits (XEXP (varop, 1), result_mode)
9470 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9472 varop = XEXP (varop, 0);
9475 else if ((code == ASHIFTRT || code == LSHIFTRT)
9476 && count < HOST_BITS_PER_WIDE_INT
9477 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9478 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9480 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9481 & nonzero_bits (XEXP (varop, 1),
9484 varop = XEXP (varop, 1);
9488 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9490 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9491 && (new = simplify_binary_operation (ASHIFT, result_mode,
9493 GEN_INT (count))) != 0
9494 && GET_CODE (new) == CONST_INT
9495 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9496 INTVAL (new), result_mode, &complement_p))
9498 varop = XEXP (varop, 0);
9504 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9505 with C the size of VAROP - 1 and the shift is logical if
9506 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9507 we have a (gt X 0) operation. If the shift is arithmetic with
9508 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9509 we have a (neg (gt X 0)) operation. */
9511 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9512 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9513 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9514 && (code == LSHIFTRT || code == ASHIFTRT)
9515 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9516 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9517 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9520 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9523 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9524 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9531 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9532 if the truncate does not affect the value. */
9533 if (code == LSHIFTRT
9534 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9535 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9536 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9537 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9538 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9540 rtx varop_inner = XEXP (varop, 0);
9543 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9544 XEXP (varop_inner, 0),
9546 + INTVAL (XEXP (varop_inner, 1))));
9547 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9561 /* We need to determine what mode to do the shift in. If the shift is
9562 a right shift or ROTATE, we must always do it in the mode it was
9563 originally done in. Otherwise, we can do it in MODE, the widest mode
9564 encountered. The code we care about is that of the shift that will
9565 actually be done, not the shift that was originally requested. */
9567 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9568 ? result_mode : mode);
9570 /* We have now finished analyzing the shift. The result should be
9571 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9572 OUTER_OP is non-NIL, it is an operation that needs to be applied
9573 to the result of the shift. OUTER_CONST is the relevant constant,
9574 but we must turn off all bits turned off in the shift.
9576 If we were passed a value for X, see if we can use any pieces of
9577 it. If not, make new rtx. */
9579 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9580 && GET_CODE (XEXP (x, 1)) == CONST_INT
9581 && INTVAL (XEXP (x, 1)) == count)
9582 const_rtx = XEXP (x, 1);
9584 const_rtx = GEN_INT (count);
9586 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9587 && GET_MODE (XEXP (x, 0)) == shift_mode
9588 && SUBREG_REG (XEXP (x, 0)) == varop)
9589 varop = XEXP (x, 0);
9590 else if (GET_MODE (varop) != shift_mode)
9591 varop = gen_lowpart_for_combine (shift_mode, varop);
9593 /* If we can't make the SUBREG, try to return what we were given. */
9594 if (GET_CODE (varop) == CLOBBER)
9595 return x ? x : varop;
9597 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9602 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9603 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9605 SUBST (XEXP (x, 0), varop);
9606 SUBST (XEXP (x, 1), const_rtx);
9609 /* If we have an outer operation and we just made a shift, it is
9610 possible that we could have simplified the shift were it not
9611 for the outer operation. So try to do the simplification
9614 if (outer_op != NIL && GET_CODE (x) == code
9615 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9616 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9617 INTVAL (XEXP (x, 1)));
9619 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9620 turn off all the bits that the shift would have turned off. */
9621 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9622 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9623 GET_MODE_MASK (result_mode) >> orig_count);
9625 /* Do the remainder of the processing in RESULT_MODE. */
9626 x = gen_lowpart_for_combine (result_mode, x);
9628 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9631 x = gen_unary (NOT, result_mode, result_mode, x);
9633 if (outer_op != NIL)
9635 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9636 outer_const = trunc_int_for_mode (outer_const, result_mode);
9638 if (outer_op == AND)
9639 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9640 else if (outer_op == SET)
9641 /* This means that we have determined that the result is
9642 equivalent to a constant. This should be rare. */
9643 x = GEN_INT (outer_const);
9644 else if (GET_RTX_CLASS (outer_op) == '1')
9645 x = gen_unary (outer_op, result_mode, result_mode, x);
9647 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9653 /* Like recog, but we receive the address of a pointer to a new pattern.
9654 We try to match the rtx that the pointer points to.
9655 If that fails, we may try to modify or replace the pattern,
9656 storing the replacement into the same pointer object.
9658 Modifications include deletion or addition of CLOBBERs.
9660 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9661 the CLOBBERs are placed.
9663 The value is the final insn code from the pattern ultimately matched,
9667 recog_for_combine (pnewpat, insn, pnotes)
9672 register rtx pat = *pnewpat;
9673 int insn_code_number;
9674 int num_clobbers_to_add = 0;
9679 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9680 we use to indicate that something didn't match. If we find such a
9681 thing, force rejection. */
9682 if (GET_CODE (pat) == PARALLEL)
9683 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9684 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9685 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9688 /* Remove the old notes prior to trying to recognize the new pattern. */
9689 old_notes = REG_NOTES (insn);
9690 REG_NOTES (insn) = 0;
9692 /* Is the result of combination a valid instruction? */
9693 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9695 /* If it isn't, there is the possibility that we previously had an insn
9696 that clobbered some register as a side effect, but the combined
9697 insn doesn't need to do that. So try once more without the clobbers
9698 unless this represents an ASM insn. */
9700 if (insn_code_number < 0 && ! check_asm_operands (pat)
9701 && GET_CODE (pat) == PARALLEL)
9705 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9706 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9709 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9713 SUBST_INT (XVECLEN (pat, 0), pos);
9716 pat = XVECEXP (pat, 0, 0);
9718 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9721 REG_NOTES (insn) = old_notes;
9723 /* If we had any clobbers to add, make a new pattern than contains
9724 them. Then check to make sure that all of them are dead. */
9725 if (num_clobbers_to_add)
9727 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9728 rtvec_alloc (GET_CODE (pat) == PARALLEL
9730 + num_clobbers_to_add)
9731 : num_clobbers_to_add + 1));
9733 if (GET_CODE (pat) == PARALLEL)
9734 for (i = 0; i < XVECLEN (pat, 0); i++)
9735 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9737 XVECEXP (newpat, 0, 0) = pat;
9739 add_clobbers (newpat, insn_code_number);
9741 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9742 i < XVECLEN (newpat, 0); i++)
9744 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9745 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9747 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9748 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9756 return insn_code_number;
9759 /* Like gen_lowpart but for use by combine. In combine it is not possible
9760 to create any new pseudoregs. However, it is safe to create
9761 invalid memory addresses, because combine will try to recognize
9762 them and all they will do is make the combine attempt fail.
9764 If for some reason this cannot do its job, an rtx
9765 (clobber (const_int 0)) is returned.
9766 An insn containing that will not be recognized. */
9771 gen_lowpart_for_combine (mode, x)
9772 enum machine_mode mode;
9777 if (GET_MODE (x) == mode)
9780 /* We can only support MODE being wider than a word if X is a
9781 constant integer or has a mode the same size. */
9783 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9784 && ! ((GET_MODE (x) == VOIDmode
9785 && (GET_CODE (x) == CONST_INT
9786 || GET_CODE (x) == CONST_DOUBLE))
9787 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9788 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9790 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9791 won't know what to do. So we will strip off the SUBREG here and
9792 process normally. */
9793 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9796 if (GET_MODE (x) == mode)
9800 result = gen_lowpart_common (mode, x);
9801 #ifdef CLASS_CANNOT_CHANGE_MODE
9803 && GET_CODE (result) == SUBREG
9804 && GET_CODE (SUBREG_REG (result)) == REG
9805 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9806 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9807 GET_MODE (SUBREG_REG (result))))
9808 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9814 if (GET_CODE (x) == MEM)
9816 register int offset = 0;
9819 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9821 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9822 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9824 /* If we want to refer to something bigger than the original memref,
9825 generate a perverse subreg instead. That will force a reload
9826 of the original memref X. */
9827 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9828 return gen_rtx_SUBREG (mode, x, 0);
9830 if (WORDS_BIG_ENDIAN)
9831 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9832 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9834 if (BYTES_BIG_ENDIAN)
9836 /* Adjust the address so that the address-after-the-data is
9838 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9839 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9841 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9842 MEM_COPY_ATTRIBUTES (new, x);
9846 /* If X is a comparison operator, rewrite it in a new mode. This
9847 probably won't match, but may allow further simplifications. */
9848 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9849 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9851 /* If we couldn't simplify X any other way, just enclose it in a
9852 SUBREG. Normally, this SUBREG won't match, but some patterns may
9853 include an explicit SUBREG or we may simplify it further in combine. */
9858 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9859 word = ((GET_MODE_SIZE (GET_MODE (x))
9860 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9862 return gen_rtx_SUBREG (mode, x, word);
9866 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9867 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9869 If the identical expression was previously in the insn (in the undobuf),
9870 it will be returned. Only if it is not found will a new expression
9875 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9877 #ifndef ANSI_PROTOTYPES
9879 enum machine_mode mode;
9891 #ifndef ANSI_PROTOTYPES
9892 code = va_arg (p, enum rtx_code);
9893 mode = va_arg (p, enum machine_mode);
9896 n_args = GET_RTX_LENGTH (code);
9897 fmt = GET_RTX_FORMAT (code);
9899 if (n_args == 0 || n_args > 3)
9902 /* Get each arg and verify that it is supposed to be an expression. */
9903 for (j = 0; j < n_args; j++)
9908 args[j] = va_arg (p, rtx);
9913 /* See if this is in undobuf. Be sure we don't use objects that came
9914 from another insn; this could produce circular rtl structures. */
9916 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9918 && GET_CODE (undo->old_contents.r) == code
9919 && GET_MODE (undo->old_contents.r) == mode)
9921 for (j = 0; j < n_args; j++)
9922 if (XEXP (undo->old_contents.r, j) != args[j])
9926 return undo->old_contents.r;
9929 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9930 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9931 rt = rtx_alloc (code);
9932 PUT_MODE (rt, mode);
9933 XEXP (rt, 0) = args[0];
9936 XEXP (rt, 1) = args[1];
9938 XEXP (rt, 2) = args[2];
9943 /* These routines make binary and unary operations by first seeing if they
9944 fold; if not, a new expression is allocated. */
9947 gen_binary (code, mode, op0, op1)
9949 enum machine_mode mode;
9955 if (GET_RTX_CLASS (code) == 'c'
9956 && (GET_CODE (op0) == CONST_INT
9957 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9958 tem = op0, op0 = op1, op1 = tem;
9960 if (GET_RTX_CLASS (code) == '<')
9962 enum machine_mode op_mode = GET_MODE (op0);
9964 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9965 just (REL_OP X Y). */
9966 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9968 op1 = XEXP (op0, 1);
9969 op0 = XEXP (op0, 0);
9970 op_mode = GET_MODE (op0);
9973 if (op_mode == VOIDmode)
9974 op_mode = GET_MODE (op1);
9975 result = simplify_relational_operation (code, op_mode, op0, op1);
9978 result = simplify_binary_operation (code, mode, op0, op1);
9983 /* Put complex operands first and constants second. */
9984 if (GET_RTX_CLASS (code) == 'c'
9985 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9986 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9987 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9988 || (GET_CODE (op0) == SUBREG
9989 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9990 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9991 return gen_rtx_combine (code, mode, op1, op0);
9993 /* If we are turning off bits already known off in OP0, we need not do
9995 else if (code == AND && GET_CODE (op1) == CONST_INT
9996 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9997 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10000 return gen_rtx_combine (code, mode, op0, op1);
10004 gen_unary (code, mode, op0_mode, op0)
10005 enum rtx_code code;
10006 enum machine_mode mode, op0_mode;
10009 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
10014 return gen_rtx_combine (code, mode, op0);
10017 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10018 comparison code that will be tested.
10020 The result is a possibly different comparison code to use. *POP0 and
10021 *POP1 may be updated.
10023 It is possible that we might detect that a comparison is either always
10024 true or always false. However, we do not perform general constant
10025 folding in combine, so this knowledge isn't useful. Such tautologies
10026 should have been detected earlier. Hence we ignore all such cases. */
10028 static enum rtx_code
10029 simplify_comparison (code, pop0, pop1)
10030 enum rtx_code code;
10038 enum machine_mode mode, tmode;
10040 /* Try a few ways of applying the same transformation to both operands. */
10043 #ifndef WORD_REGISTER_OPERATIONS
10044 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10045 so check specially. */
10046 if (code != GTU && code != GEU && code != LTU && code != LEU
10047 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10048 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10049 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10050 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10051 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10052 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10053 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10054 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10055 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10056 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10057 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10058 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10059 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10060 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10061 && (INTVAL (XEXP (op0, 1))
10062 == (GET_MODE_BITSIZE (GET_MODE (op0))
10063 - (GET_MODE_BITSIZE
10064 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10066 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10067 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10071 /* If both operands are the same constant shift, see if we can ignore the
10072 shift. We can if the shift is a rotate or if the bits shifted out of
10073 this shift are known to be zero for both inputs and if the type of
10074 comparison is compatible with the shift. */
10075 if (GET_CODE (op0) == GET_CODE (op1)
10076 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10077 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10078 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10079 && (code != GT && code != LT && code != GE && code != LE))
10080 || (GET_CODE (op0) == ASHIFTRT
10081 && (code != GTU && code != LTU
10082 && code != GEU && code != GEU)))
10083 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10084 && INTVAL (XEXP (op0, 1)) >= 0
10085 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10086 && XEXP (op0, 1) == XEXP (op1, 1))
10088 enum machine_mode mode = GET_MODE (op0);
10089 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10090 int shift_count = INTVAL (XEXP (op0, 1));
10092 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10093 mask &= (mask >> shift_count) << shift_count;
10094 else if (GET_CODE (op0) == ASHIFT)
10095 mask = (mask & (mask << shift_count)) >> shift_count;
10097 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10098 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10099 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10104 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10105 SUBREGs are of the same mode, and, in both cases, the AND would
10106 be redundant if the comparison was done in the narrower mode,
10107 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10108 and the operand's possibly nonzero bits are 0xffffff01; in that case
10109 if we only care about QImode, we don't need the AND). This case
10110 occurs if the output mode of an scc insn is not SImode and
10111 STORE_FLAG_VALUE == 1 (e.g., the 386).
10113 Similarly, check for a case where the AND's are ZERO_EXTEND
10114 operations from some narrower mode even though a SUBREG is not
10117 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10118 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10119 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10121 rtx inner_op0 = XEXP (op0, 0);
10122 rtx inner_op1 = XEXP (op1, 0);
10123 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10124 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10127 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10128 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10129 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10130 && (GET_MODE (SUBREG_REG (inner_op0))
10131 == GET_MODE (SUBREG_REG (inner_op1)))
10132 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10133 <= HOST_BITS_PER_WIDE_INT)
10134 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10135 GET_MODE (SUBREG_REG (inner_op0)))))
10136 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10137 GET_MODE (SUBREG_REG (inner_op1))))))
10139 op0 = SUBREG_REG (inner_op0);
10140 op1 = SUBREG_REG (inner_op1);
10142 /* The resulting comparison is always unsigned since we masked
10143 off the original sign bit. */
10144 code = unsigned_condition (code);
10150 for (tmode = GET_CLASS_NARROWEST_MODE
10151 (GET_MODE_CLASS (GET_MODE (op0)));
10152 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10153 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10155 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10156 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10157 code = unsigned_condition (code);
10166 /* If both operands are NOT, we can strip off the outer operation
10167 and adjust the comparison code for swapped operands; similarly for
10168 NEG, except that this must be an equality comparison. */
10169 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10170 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10171 && (code == EQ || code == NE)))
10172 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10178 /* If the first operand is a constant, swap the operands and adjust the
10179 comparison code appropriately, but don't do this if the second operand
10180 is already a constant integer. */
10181 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10183 tem = op0, op0 = op1, op1 = tem;
10184 code = swap_condition (code);
10187 /* We now enter a loop during which we will try to simplify the comparison.
10188 For the most part, we only are concerned with comparisons with zero,
10189 but some things may really be comparisons with zero but not start
10190 out looking that way. */
10192 while (GET_CODE (op1) == CONST_INT)
10194 enum machine_mode mode = GET_MODE (op0);
10195 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10196 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10197 int equality_comparison_p;
10198 int sign_bit_comparison_p;
10199 int unsigned_comparison_p;
10200 HOST_WIDE_INT const_op;
10202 /* We only want to handle integral modes. This catches VOIDmode,
10203 CCmode, and the floating-point modes. An exception is that we
10204 can handle VOIDmode if OP0 is a COMPARE or a comparison
10207 if (GET_MODE_CLASS (mode) != MODE_INT
10208 && ! (mode == VOIDmode
10209 && (GET_CODE (op0) == COMPARE
10210 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10213 /* Get the constant we are comparing against and turn off all bits
10214 not on in our mode. */
10215 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10217 /* If we are comparing against a constant power of two and the value
10218 being compared can only have that single bit nonzero (e.g., it was
10219 `and'ed with that bit), we can replace this with a comparison
10222 && (code == EQ || code == NE || code == GE || code == GEU
10223 || code == LT || code == LTU)
10224 && mode_width <= HOST_BITS_PER_WIDE_INT
10225 && exact_log2 (const_op) >= 0
10226 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10228 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10229 op1 = const0_rtx, const_op = 0;
10232 /* Similarly, if we are comparing a value known to be either -1 or
10233 0 with -1, change it to the opposite comparison against zero. */
10236 && (code == EQ || code == NE || code == GT || code == LE
10237 || code == GEU || code == LTU)
10238 && num_sign_bit_copies (op0, mode) == mode_width)
10240 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10241 op1 = const0_rtx, const_op = 0;
10244 /* Do some canonicalizations based on the comparison code. We prefer
10245 comparisons against zero and then prefer equality comparisons.
10246 If we can reduce the size of a constant, we will do that too. */
10251 /* < C is equivalent to <= (C - 1) */
10255 op1 = GEN_INT (const_op);
10257 /* ... fall through to LE case below. */
10263 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10267 op1 = GEN_INT (const_op);
10271 /* If we are doing a <= 0 comparison on a value known to have
10272 a zero sign bit, we can replace this with == 0. */
10273 else if (const_op == 0
10274 && mode_width <= HOST_BITS_PER_WIDE_INT
10275 && (nonzero_bits (op0, mode)
10276 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10281 /* >= C is equivalent to > (C - 1). */
10285 op1 = GEN_INT (const_op);
10287 /* ... fall through to GT below. */
10293 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10297 op1 = GEN_INT (const_op);
10301 /* If we are doing a > 0 comparison on a value known to have
10302 a zero sign bit, we can replace this with != 0. */
10303 else if (const_op == 0
10304 && mode_width <= HOST_BITS_PER_WIDE_INT
10305 && (nonzero_bits (op0, mode)
10306 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10311 /* < C is equivalent to <= (C - 1). */
10315 op1 = GEN_INT (const_op);
10317 /* ... fall through ... */
10320 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10321 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10322 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10324 const_op = 0, op1 = const0_rtx;
10332 /* unsigned <= 0 is equivalent to == 0 */
10336 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10337 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10338 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10340 const_op = 0, op1 = const0_rtx;
10346 /* >= C is equivalent to < (C - 1). */
10350 op1 = GEN_INT (const_op);
10352 /* ... fall through ... */
10355 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10356 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10357 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10359 const_op = 0, op1 = const0_rtx;
10367 /* unsigned > 0 is equivalent to != 0 */
10371 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10372 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10373 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10375 const_op = 0, op1 = const0_rtx;
10384 /* Compute some predicates to simplify code below. */
10386 equality_comparison_p = (code == EQ || code == NE);
10387 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10388 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10391 /* If this is a sign bit comparison and we can do arithmetic in
10392 MODE, say that we will only be needing the sign bit of OP0. */
10393 if (sign_bit_comparison_p
10394 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10395 op0 = force_to_mode (op0, mode,
10397 << (GET_MODE_BITSIZE (mode) - 1)),
10400 /* Now try cases based on the opcode of OP0. If none of the cases
10401 does a "continue", we exit this loop immediately after the
10404 switch (GET_CODE (op0))
10407 /* If we are extracting a single bit from a variable position in
10408 a constant that has only a single bit set and are comparing it
10409 with zero, we can convert this into an equality comparison
10410 between the position and the location of the single bit. */
10412 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10413 && XEXP (op0, 1) == const1_rtx
10414 && equality_comparison_p && const_op == 0
10415 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10417 if (BITS_BIG_ENDIAN)
10420 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10421 if (mode == VOIDmode)
10423 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10425 i = BITS_PER_WORD - 1 - i;
10429 op0 = XEXP (op0, 2);
10433 /* Result is nonzero iff shift count is equal to I. */
10434 code = reverse_condition (code);
10438 /* ... fall through ... */
10441 tem = expand_compound_operation (op0);
10450 /* If testing for equality, we can take the NOT of the constant. */
10451 if (equality_comparison_p
10452 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10454 op0 = XEXP (op0, 0);
10459 /* If just looking at the sign bit, reverse the sense of the
10461 if (sign_bit_comparison_p)
10463 op0 = XEXP (op0, 0);
10464 code = (code == GE ? LT : GE);
10470 /* If testing for equality, we can take the NEG of the constant. */
10471 if (equality_comparison_p
10472 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10474 op0 = XEXP (op0, 0);
10479 /* The remaining cases only apply to comparisons with zero. */
10483 /* When X is ABS or is known positive,
10484 (neg X) is < 0 if and only if X != 0. */
10486 if (sign_bit_comparison_p
10487 && (GET_CODE (XEXP (op0, 0)) == ABS
10488 || (mode_width <= HOST_BITS_PER_WIDE_INT
10489 && (nonzero_bits (XEXP (op0, 0), mode)
10490 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10492 op0 = XEXP (op0, 0);
10493 code = (code == LT ? NE : EQ);
10497 /* If we have NEG of something whose two high-order bits are the
10498 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10499 if (num_sign_bit_copies (op0, mode) >= 2)
10501 op0 = XEXP (op0, 0);
10502 code = swap_condition (code);
10508 /* If we are testing equality and our count is a constant, we
10509 can perform the inverse operation on our RHS. */
10510 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10511 && (tem = simplify_binary_operation (ROTATERT, mode,
10512 op1, XEXP (op0, 1))) != 0)
10514 op0 = XEXP (op0, 0);
10519 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10520 a particular bit. Convert it to an AND of a constant of that
10521 bit. This will be converted into a ZERO_EXTRACT. */
10522 if (const_op == 0 && sign_bit_comparison_p
10523 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10524 && mode_width <= HOST_BITS_PER_WIDE_INT)
10526 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10529 - INTVAL (XEXP (op0, 1)))));
10530 code = (code == LT ? NE : EQ);
10534 /* Fall through. */
10537 /* ABS is ignorable inside an equality comparison with zero. */
10538 if (const_op == 0 && equality_comparison_p)
10540 op0 = XEXP (op0, 0);
10546 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10547 to (compare FOO CONST) if CONST fits in FOO's mode and we
10548 are either testing inequality or have an unsigned comparison
10549 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10550 if (! unsigned_comparison_p
10551 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10552 <= HOST_BITS_PER_WIDE_INT)
10553 && ((unsigned HOST_WIDE_INT) const_op
10554 < (((unsigned HOST_WIDE_INT) 1
10555 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10557 op0 = XEXP (op0, 0);
10563 /* Check for the case where we are comparing A - C1 with C2,
10564 both constants are smaller than 1/2 the maximum positive
10565 value in MODE, and the comparison is equality or unsigned.
10566 In that case, if A is either zero-extended to MODE or has
10567 sufficient sign bits so that the high-order bit in MODE
10568 is a copy of the sign in the inner mode, we can prove that it is
10569 safe to do the operation in the wider mode. This simplifies
10570 many range checks. */
10572 if (mode_width <= HOST_BITS_PER_WIDE_INT
10573 && subreg_lowpart_p (op0)
10574 && GET_CODE (SUBREG_REG (op0)) == PLUS
10575 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10576 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10577 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10578 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10579 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10580 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10581 GET_MODE (SUBREG_REG (op0)))
10582 & ~GET_MODE_MASK (mode))
10583 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10584 GET_MODE (SUBREG_REG (op0)))
10585 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10586 - GET_MODE_BITSIZE (mode)))))
10588 op0 = SUBREG_REG (op0);
10592 /* If the inner mode is narrower and we are extracting the low part,
10593 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10594 if (subreg_lowpart_p (op0)
10595 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10596 /* Fall through */ ;
10600 /* ... fall through ... */
10603 if ((unsigned_comparison_p || equality_comparison_p)
10604 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10605 <= HOST_BITS_PER_WIDE_INT)
10606 && ((unsigned HOST_WIDE_INT) const_op
10607 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10609 op0 = XEXP (op0, 0);
10615 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10616 this for equality comparisons due to pathological cases involving
10618 if (equality_comparison_p
10619 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10620 op1, XEXP (op0, 1))))
10622 op0 = XEXP (op0, 0);
10627 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10628 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10629 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10631 op0 = XEXP (XEXP (op0, 0), 0);
10632 code = (code == LT ? EQ : NE);
10638 /* We used to optimize signed comparisons against zero, but that
10639 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10640 arrive here as equality comparisons, or (GEU, LTU) are
10641 optimized away. No need to special-case them. */
10643 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10644 (eq B (minus A C)), whichever simplifies. We can only do
10645 this for equality comparisons due to pathological cases involving
10647 if (equality_comparison_p
10648 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10649 XEXP (op0, 1), op1)))
10651 op0 = XEXP (op0, 0);
10656 if (equality_comparison_p
10657 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10658 XEXP (op0, 0), op1)))
10660 op0 = XEXP (op0, 1);
10665 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10666 of bits in X minus 1, is one iff X > 0. */
10667 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10668 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10669 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10670 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10672 op0 = XEXP (op0, 1);
10673 code = (code == GE ? LE : GT);
10679 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10680 if C is zero or B is a constant. */
10681 if (equality_comparison_p
10682 && 0 != (tem = simplify_binary_operation (XOR, mode,
10683 XEXP (op0, 1), op1)))
10685 op0 = XEXP (op0, 0);
10692 case UNEQ: case LTGT:
10693 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10694 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10695 case UNORDERED: case ORDERED:
10696 /* We can't do anything if OP0 is a condition code value, rather
10697 than an actual data value. */
10700 || XEXP (op0, 0) == cc0_rtx
10702 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10705 /* Get the two operands being compared. */
10706 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10707 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10709 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10711 /* Check for the cases where we simply want the result of the
10712 earlier test or the opposite of that result. */
10713 if (code == NE || code == EQ
10714 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10715 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10716 && (STORE_FLAG_VALUE
10717 & (((HOST_WIDE_INT) 1
10718 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10719 && (code == LT || code == GE)))
10721 enum rtx_code new_code;
10722 if (code == LT || code == NE)
10723 new_code = GET_CODE (op0);
10725 new_code = combine_reversed_comparison_code (op0);
10727 if (new_code != UNKNOWN)
10738 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10740 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10741 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10742 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10744 op0 = XEXP (op0, 1);
10745 code = (code == GE ? GT : LE);
10751 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10752 will be converted to a ZERO_EXTRACT later. */
10753 if (const_op == 0 && equality_comparison_p
10754 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10755 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10757 op0 = simplify_and_const_int
10758 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10760 XEXP (XEXP (op0, 0), 1)),
10761 (HOST_WIDE_INT) 1);
10765 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10766 zero and X is a comparison and C1 and C2 describe only bits set
10767 in STORE_FLAG_VALUE, we can compare with X. */
10768 if (const_op == 0 && equality_comparison_p
10769 && mode_width <= HOST_BITS_PER_WIDE_INT
10770 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10771 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10772 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10773 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10774 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10776 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10777 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10778 if ((~STORE_FLAG_VALUE & mask) == 0
10779 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10780 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10781 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10783 op0 = XEXP (XEXP (op0, 0), 0);
10788 /* If we are doing an equality comparison of an AND of a bit equal
10789 to the sign bit, replace this with a LT or GE comparison of
10790 the underlying value. */
10791 if (equality_comparison_p
10793 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10794 && mode_width <= HOST_BITS_PER_WIDE_INT
10795 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10796 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10798 op0 = XEXP (op0, 0);
10799 code = (code == EQ ? GE : LT);
10803 /* If this AND operation is really a ZERO_EXTEND from a narrower
10804 mode, the constant fits within that mode, and this is either an
10805 equality or unsigned comparison, try to do this comparison in
10806 the narrower mode. */
10807 if ((equality_comparison_p || unsigned_comparison_p)
10808 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10809 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10810 & GET_MODE_MASK (mode))
10812 && const_op >> i == 0
10813 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10815 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10819 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10820 in both M1 and M2 and the SUBREG is either paradoxical or
10821 represents the low part, permute the SUBREG and the AND and
10823 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10825 #ifdef WORD_REGISTER_OPERATIONS
10827 > (GET_MODE_BITSIZE
10828 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10829 && mode_width <= BITS_PER_WORD)
10832 <= (GET_MODE_BITSIZE
10833 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10834 && subreg_lowpart_p (XEXP (op0, 0))))
10835 #ifndef WORD_REGISTER_OPERATIONS
10836 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10837 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10838 As originally written the upper bits have a defined value
10839 due to the AND operation. However, if we commute the AND
10840 inside the SUBREG then they no longer have defined values
10841 and the meaning of the code has been changed. */
10842 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10843 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10845 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10846 && mode_width <= HOST_BITS_PER_WIDE_INT
10847 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10848 <= HOST_BITS_PER_WIDE_INT)
10849 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10850 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10851 & INTVAL (XEXP (op0, 1)))
10852 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10853 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10854 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10858 = gen_lowpart_for_combine
10860 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10861 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10865 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10866 (eq (and (lshiftrt X) 1) 0). */
10867 if (const_op == 0 && equality_comparison_p
10868 && XEXP (op0, 1) == const1_rtx
10869 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10870 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10872 op0 = simplify_and_const_int
10873 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10874 XEXP (XEXP (XEXP (op0, 0), 0), 0),
10875 XEXP (XEXP (op0, 0), 1)),
10876 (HOST_WIDE_INT) 1);
10877 code = (code == NE ? EQ : NE);
10883 /* If we have (compare (ashift FOO N) (const_int C)) and
10884 the high order N bits of FOO (N+1 if an inequality comparison)
10885 are known to be zero, we can do this by comparing FOO with C
10886 shifted right N bits so long as the low-order N bits of C are
10888 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10889 && INTVAL (XEXP (op0, 1)) >= 0
10890 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10891 < HOST_BITS_PER_WIDE_INT)
10893 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10894 && mode_width <= HOST_BITS_PER_WIDE_INT
10895 && (nonzero_bits (XEXP (op0, 0), mode)
10896 & ~(mask >> (INTVAL (XEXP (op0, 1))
10897 + ! equality_comparison_p))) == 0)
10899 /* We must perform a logical shift, not an arithmetic one,
10900 as we want the top N bits of C to be zero. */
10901 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10903 temp >>= INTVAL (XEXP (op0, 1));
10904 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10905 op0 = XEXP (op0, 0);
10909 /* If we are doing a sign bit comparison, it means we are testing
10910 a particular bit. Convert it to the appropriate AND. */
10911 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10912 && mode_width <= HOST_BITS_PER_WIDE_INT)
10914 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10917 - INTVAL (XEXP (op0, 1)))));
10918 code = (code == LT ? NE : EQ);
10922 /* If this an equality comparison with zero and we are shifting
10923 the low bit to the sign bit, we can convert this to an AND of the
10925 if (const_op == 0 && equality_comparison_p
10926 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10927 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10929 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10930 (HOST_WIDE_INT) 1);
10936 /* If this is an equality comparison with zero, we can do this
10937 as a logical shift, which might be much simpler. */
10938 if (equality_comparison_p && const_op == 0
10939 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10941 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10943 INTVAL (XEXP (op0, 1)));
10947 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10948 do the comparison in a narrower mode. */
10949 if (! unsigned_comparison_p
10950 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10951 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10952 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10953 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10954 MODE_INT, 1)) != BLKmode
10955 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10956 || ((unsigned HOST_WIDE_INT) -const_op
10957 <= GET_MODE_MASK (tmode))))
10959 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10963 /* Likewise if OP0 is a PLUS of a sign extension with a
10964 constant, which is usually represented with the PLUS
10965 between the shifts. */
10966 if (! unsigned_comparison_p
10967 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10968 && GET_CODE (XEXP (op0, 0)) == PLUS
10969 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10970 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10971 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10972 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10973 MODE_INT, 1)) != BLKmode
10974 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10975 || ((unsigned HOST_WIDE_INT) -const_op
10976 <= GET_MODE_MASK (tmode))))
10978 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10979 rtx add_const = XEXP (XEXP (op0, 0), 1);
10980 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10983 op0 = gen_binary (PLUS, tmode,
10984 gen_lowpart_for_combine (tmode, inner),
10989 /* ... fall through ... */
10991 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10992 the low order N bits of FOO are known to be zero, we can do this
10993 by comparing FOO with C shifted left N bits so long as no
10994 overflow occurs. */
10995 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10996 && INTVAL (XEXP (op0, 1)) >= 0
10997 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10998 && mode_width <= HOST_BITS_PER_WIDE_INT
10999 && (nonzero_bits (XEXP (op0, 0), mode)
11000 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11002 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
11005 const_op <<= INTVAL (XEXP (op0, 1));
11006 op1 = GEN_INT (const_op);
11007 op0 = XEXP (op0, 0);
11011 /* If we are using this shift to extract just the sign bit, we
11012 can replace this with an LT or GE comparison. */
11014 && (equality_comparison_p || sign_bit_comparison_p)
11015 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11016 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
11018 op0 = XEXP (op0, 0);
11019 code = (code == NE || code == GT ? LT : GE);
11031 /* Now make any compound operations involved in this comparison. Then,
11032 check for an outmost SUBREG on OP0 that is not doing anything or is
11033 paradoxical. The latter case can only occur when it is known that the
11034 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11035 We can never remove a SUBREG for a non-equality comparison because the
11036 sign bit is in a different place in the underlying object. */
11038 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11039 op1 = make_compound_operation (op1, SET);
11041 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11042 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11043 && (code == NE || code == EQ)
11044 && ((GET_MODE_SIZE (GET_MODE (op0))
11045 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
11047 op0 = SUBREG_REG (op0);
11048 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11051 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11052 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11053 && (code == NE || code == EQ)
11054 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11055 <= HOST_BITS_PER_WIDE_INT)
11056 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
11057 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
11058 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
11060 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11061 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
11062 op0 = SUBREG_REG (op0), op1 = tem;
11064 /* We now do the opposite procedure: Some machines don't have compare
11065 insns in all modes. If OP0's mode is an integer mode smaller than a
11066 word and we can't do a compare in that mode, see if there is a larger
11067 mode for which we can do the compare. There are a number of cases in
11068 which we can use the wider mode. */
11070 mode = GET_MODE (op0);
11071 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11072 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11073 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
11074 for (tmode = GET_MODE_WIDER_MODE (mode);
11076 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11077 tmode = GET_MODE_WIDER_MODE (tmode))
11078 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
11080 /* If the only nonzero bits in OP0 and OP1 are those in the
11081 narrower mode and this is an equality or unsigned comparison,
11082 we can use the wider mode. Similarly for sign-extended
11083 values, in which case it is true for all comparisons. */
11084 if (((code == EQ || code == NE
11085 || code == GEU || code == GTU || code == LEU || code == LTU)
11086 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
11087 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
11088 || ((num_sign_bit_copies (op0, tmode)
11089 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11090 && (num_sign_bit_copies (op1, tmode)
11091 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11093 /* If OP0 is an AND and we don't have an AND in MODE either,
11094 make a new AND in the proper mode. */
11095 if (GET_CODE (op0) == AND
11096 && (add_optab->handlers[(int) mode].insn_code
11097 == CODE_FOR_nothing))
11098 op0 = gen_binary (AND, tmode,
11099 gen_lowpart_for_combine (tmode,
11101 gen_lowpart_for_combine (tmode,
11104 op0 = gen_lowpart_for_combine (tmode, op0);
11105 op1 = gen_lowpart_for_combine (tmode, op1);
11109 /* If this is a test for negative, we can make an explicit
11110 test of the sign bit. */
11112 if (op1 == const0_rtx && (code == LT || code == GE)
11113 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11115 op0 = gen_binary (AND, tmode,
11116 gen_lowpart_for_combine (tmode, op0),
11117 GEN_INT ((HOST_WIDE_INT) 1
11118 << (GET_MODE_BITSIZE (mode) - 1)));
11119 code = (code == LT) ? NE : EQ;
11124 #ifdef CANONICALIZE_COMPARISON
11125 /* If this machine only supports a subset of valid comparisons, see if we
11126 can convert an unsupported one into a supported one. */
11127 CANONICALIZE_COMPARISON (code, op0, op1);
11136 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11137 searching backward. */
11138 static enum rtx_code
11139 combine_reversed_comparison_code (exp)
11142 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11145 if (code1 != UNKNOWN
11146 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11148 /* Otherwise try and find where the condition codes were last set and
11150 x = get_last_value (XEXP (exp, 0));
11151 if (!x || GET_CODE (x) != COMPARE)
11153 return reversed_comparison_code_parts (GET_CODE (exp),
11154 XEXP (x, 0), XEXP (x, 1), NULL);
11156 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11157 Return NULL_RTX in case we fail to do the reversal. */
11159 reversed_comparison (exp, mode, op0, op1)
11161 enum machine_mode mode;
11163 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11164 if (reversed_code == UNKNOWN)
11167 return gen_binary (reversed_code, mode, op0, op1);
11170 /* Utility function for following routine. Called when X is part of a value
11171 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11172 for each register mentioned. Similar to mention_regs in cse.c */
11175 update_table_tick (x)
11178 register enum rtx_code code = GET_CODE (x);
11179 register const char *fmt = GET_RTX_FORMAT (code);
11184 unsigned int regno = REGNO (x);
11185 unsigned int endregno
11186 = regno + (regno < FIRST_PSEUDO_REGISTER
11187 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11190 for (r = regno; r < endregno; r++)
11191 reg_last_set_table_tick[r] = label_tick;
11196 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11197 /* Note that we can't have an "E" in values stored; see
11198 get_last_value_validate. */
11200 update_table_tick (XEXP (x, i));
11203 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11204 are saying that the register is clobbered and we no longer know its
11205 value. If INSN is zero, don't update reg_last_set; this is only permitted
11206 with VALUE also zero and is used to invalidate the register. */
11209 record_value_for_reg (reg, insn, value)
11214 unsigned int regno = REGNO (reg);
11215 unsigned int endregno
11216 = regno + (regno < FIRST_PSEUDO_REGISTER
11217 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11220 /* If VALUE contains REG and we have a previous value for REG, substitute
11221 the previous value. */
11222 if (value && insn && reg_overlap_mentioned_p (reg, value))
11226 /* Set things up so get_last_value is allowed to see anything set up to
11228 subst_low_cuid = INSN_CUID (insn);
11229 tem = get_last_value (reg);
11231 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11232 it isn't going to be useful and will take a lot of time to process,
11233 so just use the CLOBBER. */
11237 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11238 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11239 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11240 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11241 tem = XEXP (tem, 0);
11243 value = replace_rtx (copy_rtx (value), reg, tem);
11247 /* For each register modified, show we don't know its value, that
11248 we don't know about its bitwise content, that its value has been
11249 updated, and that we don't know the location of the death of the
11251 for (i = regno; i < endregno; i++)
11254 reg_last_set[i] = insn;
11256 reg_last_set_value[i] = 0;
11257 reg_last_set_mode[i] = 0;
11258 reg_last_set_nonzero_bits[i] = 0;
11259 reg_last_set_sign_bit_copies[i] = 0;
11260 reg_last_death[i] = 0;
11263 /* Mark registers that are being referenced in this value. */
11265 update_table_tick (value);
11267 /* Now update the status of each register being set.
11268 If someone is using this register in this block, set this register
11269 to invalid since we will get confused between the two lives in this
11270 basic block. This makes using this register always invalid. In cse, we
11271 scan the table to invalidate all entries using this register, but this
11272 is too much work for us. */
11274 for (i = regno; i < endregno; i++)
11276 reg_last_set_label[i] = label_tick;
11277 if (value && reg_last_set_table_tick[i] == label_tick)
11278 reg_last_set_invalid[i] = 1;
11280 reg_last_set_invalid[i] = 0;
11283 /* The value being assigned might refer to X (like in "x++;"). In that
11284 case, we must replace it with (clobber (const_int 0)) to prevent
11286 if (value && ! get_last_value_validate (&value, insn,
11287 reg_last_set_label[regno], 0))
11289 value = copy_rtx (value);
11290 if (! get_last_value_validate (&value, insn,
11291 reg_last_set_label[regno], 1))
11295 /* For the main register being modified, update the value, the mode, the
11296 nonzero bits, and the number of sign bit copies. */
11298 reg_last_set_value[regno] = value;
11302 subst_low_cuid = INSN_CUID (insn);
11303 reg_last_set_mode[regno] = GET_MODE (reg);
11304 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11305 reg_last_set_sign_bit_copies[regno]
11306 = num_sign_bit_copies (value, GET_MODE (reg));
11310 /* Called via note_stores from record_dead_and_set_regs to handle one
11311 SET or CLOBBER in an insn. DATA is the instruction in which the
11312 set is occurring. */
11315 record_dead_and_set_regs_1 (dest, setter, data)
11319 rtx record_dead_insn = (rtx) data;
11321 if (GET_CODE (dest) == SUBREG)
11322 dest = SUBREG_REG (dest);
11324 if (GET_CODE (dest) == REG)
11326 /* If we are setting the whole register, we know its value. Otherwise
11327 show that we don't know the value. We can handle SUBREG in
11329 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11330 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11331 else if (GET_CODE (setter) == SET
11332 && GET_CODE (SET_DEST (setter)) == SUBREG
11333 && SUBREG_REG (SET_DEST (setter)) == dest
11334 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11335 && subreg_lowpart_p (SET_DEST (setter)))
11336 record_value_for_reg (dest, record_dead_insn,
11337 gen_lowpart_for_combine (GET_MODE (dest),
11338 SET_SRC (setter)));
11340 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11342 else if (GET_CODE (dest) == MEM
11343 /* Ignore pushes, they clobber nothing. */
11344 && ! push_operand (dest, GET_MODE (dest)))
11345 mem_last_set = INSN_CUID (record_dead_insn);
11348 /* Update the records of when each REG was most recently set or killed
11349 for the things done by INSN. This is the last thing done in processing
11350 INSN in the combiner loop.
11352 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11353 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11354 and also the similar information mem_last_set (which insn most recently
11355 modified memory) and last_call_cuid (which insn was the most recent
11356 subroutine call). */
11359 record_dead_and_set_regs (insn)
11365 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11367 if (REG_NOTE_KIND (link) == REG_DEAD
11368 && GET_CODE (XEXP (link, 0)) == REG)
11370 unsigned int regno = REGNO (XEXP (link, 0));
11371 unsigned int endregno
11372 = regno + (regno < FIRST_PSEUDO_REGISTER
11373 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11376 for (i = regno; i < endregno; i++)
11377 reg_last_death[i] = insn;
11379 else if (REG_NOTE_KIND (link) == REG_INC)
11380 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11383 if (GET_CODE (insn) == CALL_INSN)
11385 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11386 if (call_used_regs[i])
11388 reg_last_set_value[i] = 0;
11389 reg_last_set_mode[i] = 0;
11390 reg_last_set_nonzero_bits[i] = 0;
11391 reg_last_set_sign_bit_copies[i] = 0;
11392 reg_last_death[i] = 0;
11395 last_call_cuid = mem_last_set = INSN_CUID (insn);
11398 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11401 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11402 register present in the SUBREG, so for each such SUBREG go back and
11403 adjust nonzero and sign bit information of the registers that are
11404 known to have some zero/sign bits set.
11406 This is needed because when combine blows the SUBREGs away, the
11407 information on zero/sign bits is lost and further combines can be
11408 missed because of that. */
11411 record_promoted_value (insn, subreg)
11416 unsigned int regno = REGNO (SUBREG_REG (subreg));
11417 enum machine_mode mode = GET_MODE (subreg);
11419 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11422 for (links = LOG_LINKS (insn); links;)
11424 insn = XEXP (links, 0);
11425 set = single_set (insn);
11427 if (! set || GET_CODE (SET_DEST (set)) != REG
11428 || REGNO (SET_DEST (set)) != regno
11429 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11431 links = XEXP (links, 1);
11435 if (reg_last_set[regno] == insn)
11437 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11438 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11441 if (GET_CODE (SET_SRC (set)) == REG)
11443 regno = REGNO (SET_SRC (set));
11444 links = LOG_LINKS (insn);
11451 /* Scan X for promoted SUBREGs. For each one found,
11452 note what it implies to the registers used in it. */
11455 check_promoted_subreg (insn, x)
11459 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11460 && GET_CODE (SUBREG_REG (x)) == REG)
11461 record_promoted_value (insn, x);
11464 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11467 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11471 check_promoted_subreg (insn, XEXP (x, i));
11475 if (XVEC (x, i) != 0)
11476 for (j = 0; j < XVECLEN (x, i); j++)
11477 check_promoted_subreg (insn, XVECEXP (x, i, j));
11483 /* Utility routine for the following function. Verify that all the registers
11484 mentioned in *LOC are valid when *LOC was part of a value set when
11485 label_tick == TICK. Return 0 if some are not.
11487 If REPLACE is non-zero, replace the invalid reference with
11488 (clobber (const_int 0)) and return 1. This replacement is useful because
11489 we often can get useful information about the form of a value (e.g., if
11490 it was produced by a shift that always produces -1 or 0) even though
11491 we don't know exactly what registers it was produced from. */
11494 get_last_value_validate (loc, insn, tick, replace)
11501 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11502 int len = GET_RTX_LENGTH (GET_CODE (x));
11505 if (GET_CODE (x) == REG)
11507 unsigned int regno = REGNO (x);
11508 unsigned int endregno
11509 = regno + (regno < FIRST_PSEUDO_REGISTER
11510 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11513 for (j = regno; j < endregno; j++)
11514 if (reg_last_set_invalid[j]
11515 /* If this is a pseudo-register that was only set once and not
11516 live at the beginning of the function, it is always valid. */
11517 || (! (regno >= FIRST_PSEUDO_REGISTER
11518 && REG_N_SETS (regno) == 1
11519 && (! REGNO_REG_SET_P
11520 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11521 && reg_last_set_label[j] > tick))
11524 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11530 /* If this is a memory reference, make sure that there were
11531 no stores after it that might have clobbered the value. We don't
11532 have alias info, so we assume any store invalidates it. */
11533 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11534 && INSN_CUID (insn) <= mem_last_set)
11537 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11541 for (i = 0; i < len; i++)
11543 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11544 /* Don't bother with these. They shouldn't occur anyway. */
11548 /* If we haven't found a reason for it to be invalid, it is valid. */
11552 /* Get the last value assigned to X, if known. Some registers
11553 in the value may be replaced with (clobber (const_int 0)) if their value
11554 is known longer known reliably. */
11560 unsigned int regno;
11563 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11564 then convert it to the desired mode. If this is a paradoxical SUBREG,
11565 we cannot predict what values the "extra" bits might have. */
11566 if (GET_CODE (x) == SUBREG
11567 && subreg_lowpart_p (x)
11568 && (GET_MODE_SIZE (GET_MODE (x))
11569 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11570 && (value = get_last_value (SUBREG_REG (x))) != 0)
11571 return gen_lowpart_for_combine (GET_MODE (x), value);
11573 if (GET_CODE (x) != REG)
11577 value = reg_last_set_value[regno];
11579 /* If we don't have a value, or if it isn't for this basic block and
11580 it's either a hard register, set more than once, or it's a live
11581 at the beginning of the function, return 0.
11583 Because if it's not live at the beginnning of the function then the reg
11584 is always set before being used (is never used without being set).
11585 And, if it's set only once, and it's always set before use, then all
11586 uses must have the same last value, even if it's not from this basic
11590 || (reg_last_set_label[regno] != label_tick
11591 && (regno < FIRST_PSEUDO_REGISTER
11592 || REG_N_SETS (regno) != 1
11593 || (REGNO_REG_SET_P
11594 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11597 /* If the value was set in a later insn than the ones we are processing,
11598 we can't use it even if the register was only set once. */
11599 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11602 /* If the value has all its registers valid, return it. */
11603 if (get_last_value_validate (&value, reg_last_set[regno],
11604 reg_last_set_label[regno], 0))
11607 /* Otherwise, make a copy and replace any invalid register with
11608 (clobber (const_int 0)). If that fails for some reason, return 0. */
11610 value = copy_rtx (value);
11611 if (get_last_value_validate (&value, reg_last_set[regno],
11612 reg_last_set_label[regno], 1))
11618 /* Return nonzero if expression X refers to a REG or to memory
11619 that is set in an instruction more recent than FROM_CUID. */
11622 use_crosses_set_p (x, from_cuid)
11626 register const char *fmt;
11628 register enum rtx_code code = GET_CODE (x);
11632 unsigned int regno = REGNO (x);
11633 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11634 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11636 #ifdef PUSH_ROUNDING
11637 /* Don't allow uses of the stack pointer to be moved,
11638 because we don't know whether the move crosses a push insn. */
11639 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11642 for (; regno < endreg; regno++)
11643 if (reg_last_set[regno]
11644 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11649 if (code == MEM && mem_last_set > from_cuid)
11652 fmt = GET_RTX_FORMAT (code);
11654 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11660 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11663 else if (fmt[i] == 'e'
11664 && use_crosses_set_p (XEXP (x, i), from_cuid))
11670 /* Define three variables used for communication between the following
11673 static unsigned int reg_dead_regno, reg_dead_endregno;
11674 static int reg_dead_flag;
11676 /* Function called via note_stores from reg_dead_at_p.
11678 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11679 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11682 reg_dead_at_p_1 (dest, x, data)
11685 void *data ATTRIBUTE_UNUSED;
11687 unsigned int regno, endregno;
11689 if (GET_CODE (dest) != REG)
11692 regno = REGNO (dest);
11693 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11694 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11696 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11697 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11700 /* Return non-zero if REG is known to be dead at INSN.
11702 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11703 referencing REG, it is dead. If we hit a SET referencing REG, it is
11704 live. Otherwise, see if it is live or dead at the start of the basic
11705 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11706 must be assumed to be always live. */
11709 reg_dead_at_p (reg, insn)
11716 /* Set variables for reg_dead_at_p_1. */
11717 reg_dead_regno = REGNO (reg);
11718 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11719 ? HARD_REGNO_NREGS (reg_dead_regno,
11725 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11726 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11728 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11729 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11733 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11734 beginning of function. */
11735 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11736 insn = prev_nonnote_insn (insn))
11738 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11740 return reg_dead_flag == 1 ? 1 : 0;
11742 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11746 /* Get the basic block number that we were in. */
11751 for (block = 0; block < n_basic_blocks; block++)
11752 if (insn == BLOCK_HEAD (block))
11755 if (block == n_basic_blocks)
11759 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11760 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11766 /* Note hard registers in X that are used. This code is similar to
11767 that in flow.c, but much simpler since we don't care about pseudos. */
11770 mark_used_regs_combine (x)
11773 RTX_CODE code = GET_CODE (x);
11774 unsigned int regno;
11786 case ADDR_DIFF_VEC:
11789 /* CC0 must die in the insn after it is set, so we don't need to take
11790 special note of it here. */
11796 /* If we are clobbering a MEM, mark any hard registers inside the
11797 address as used. */
11798 if (GET_CODE (XEXP (x, 0)) == MEM)
11799 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11804 /* A hard reg in a wide mode may really be multiple registers.
11805 If so, mark all of them just like the first. */
11806 if (regno < FIRST_PSEUDO_REGISTER)
11808 unsigned int endregno, r;
11810 /* None of this applies to the stack, frame or arg pointers */
11811 if (regno == STACK_POINTER_REGNUM
11812 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11813 || regno == HARD_FRAME_POINTER_REGNUM
11815 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11816 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11818 || regno == FRAME_POINTER_REGNUM)
11821 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11822 for (r = regno; r < endregno; r++)
11823 SET_HARD_REG_BIT (newpat_used_regs, r);
11829 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11831 register rtx testreg = SET_DEST (x);
11833 while (GET_CODE (testreg) == SUBREG
11834 || GET_CODE (testreg) == ZERO_EXTRACT
11835 || GET_CODE (testreg) == SIGN_EXTRACT
11836 || GET_CODE (testreg) == STRICT_LOW_PART)
11837 testreg = XEXP (testreg, 0);
11839 if (GET_CODE (testreg) == MEM)
11840 mark_used_regs_combine (XEXP (testreg, 0));
11842 mark_used_regs_combine (SET_SRC (x));
11850 /* Recursively scan the operands of this expression. */
11853 register const char *fmt = GET_RTX_FORMAT (code);
11855 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11858 mark_used_regs_combine (XEXP (x, i));
11859 else if (fmt[i] == 'E')
11863 for (j = 0; j < XVECLEN (x, i); j++)
11864 mark_used_regs_combine (XVECEXP (x, i, j));
11870 /* Remove register number REGNO from the dead registers list of INSN.
11872 Return the note used to record the death, if there was one. */
11875 remove_death (regno, insn)
11876 unsigned int regno;
11879 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11883 REG_N_DEATHS (regno)--;
11884 remove_note (insn, note);
11890 /* For each register (hardware or pseudo) used within expression X, if its
11891 death is in an instruction with cuid between FROM_CUID (inclusive) and
11892 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11893 list headed by PNOTES.
11895 That said, don't move registers killed by maybe_kill_insn.
11897 This is done when X is being merged by combination into TO_INSN. These
11898 notes will then be distributed as needed. */
11901 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11903 rtx maybe_kill_insn;
11908 register const char *fmt;
11909 register int len, i;
11910 register enum rtx_code code = GET_CODE (x);
11914 unsigned int regno = REGNO (x);
11915 register rtx where_dead = reg_last_death[regno];
11916 register rtx before_dead, after_dead;
11918 /* Don't move the register if it gets killed in between from and to */
11919 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11920 && ! reg_referenced_p (x, maybe_kill_insn))
11923 /* WHERE_DEAD could be a USE insn made by combine, so first we
11924 make sure that we have insns with valid INSN_CUID values. */
11925 before_dead = where_dead;
11926 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11927 before_dead = PREV_INSN (before_dead);
11929 after_dead = where_dead;
11930 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11931 after_dead = NEXT_INSN (after_dead);
11933 if (before_dead && after_dead
11934 && INSN_CUID (before_dead) >= from_cuid
11935 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11936 || (where_dead != after_dead
11937 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11939 rtx note = remove_death (regno, where_dead);
11941 /* It is possible for the call above to return 0. This can occur
11942 when reg_last_death points to I2 or I1 that we combined with.
11943 In that case make a new note.
11945 We must also check for the case where X is a hard register
11946 and NOTE is a death note for a range of hard registers
11947 including X. In that case, we must put REG_DEAD notes for
11948 the remaining registers in place of NOTE. */
11950 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11951 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11952 > GET_MODE_SIZE (GET_MODE (x))))
11954 unsigned int deadregno = REGNO (XEXP (note, 0));
11955 unsigned int deadend
11956 = (deadregno + HARD_REGNO_NREGS (deadregno,
11957 GET_MODE (XEXP (note, 0))));
11958 unsigned int ourend
11959 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11962 for (i = deadregno; i < deadend; i++)
11963 if (i < regno || i >= ourend)
11964 REG_NOTES (where_dead)
11965 = gen_rtx_EXPR_LIST (REG_DEAD,
11966 gen_rtx_REG (reg_raw_mode[i], i),
11967 REG_NOTES (where_dead));
11970 /* If we didn't find any note, or if we found a REG_DEAD note that
11971 covers only part of the given reg, and we have a multi-reg hard
11972 register, then to be safe we must check for REG_DEAD notes
11973 for each register other than the first. They could have
11974 their own REG_DEAD notes lying around. */
11975 else if ((note == 0
11977 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11978 < GET_MODE_SIZE (GET_MODE (x)))))
11979 && regno < FIRST_PSEUDO_REGISTER
11980 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11982 unsigned int ourend
11983 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11984 unsigned int i, offset;
11988 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11992 for (i = regno + offset; i < ourend; i++)
11993 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11994 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11997 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11999 XEXP (note, 1) = *pnotes;
12003 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12005 REG_N_DEATHS (regno)++;
12011 else if (GET_CODE (x) == SET)
12013 rtx dest = SET_DEST (x);
12015 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12017 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12018 that accesses one word of a multi-word item, some
12019 piece of everything register in the expression is used by
12020 this insn, so remove any old death. */
12022 if (GET_CODE (dest) == ZERO_EXTRACT
12023 || GET_CODE (dest) == STRICT_LOW_PART
12024 || (GET_CODE (dest) == SUBREG
12025 && (((GET_MODE_SIZE (GET_MODE (dest))
12026 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12027 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12028 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12030 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12034 /* If this is some other SUBREG, we know it replaces the entire
12035 value, so use that as the destination. */
12036 if (GET_CODE (dest) == SUBREG)
12037 dest = SUBREG_REG (dest);
12039 /* If this is a MEM, adjust deaths of anything used in the address.
12040 For a REG (the only other possibility), the entire value is
12041 being replaced so the old value is not used in this insn. */
12043 if (GET_CODE (dest) == MEM)
12044 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12049 else if (GET_CODE (x) == CLOBBER)
12052 len = GET_RTX_LENGTH (code);
12053 fmt = GET_RTX_FORMAT (code);
12055 for (i = 0; i < len; i++)
12060 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12061 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12064 else if (fmt[i] == 'e')
12065 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12069 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12070 pattern of an insn. X must be a REG. */
12073 reg_bitfield_target_p (x, body)
12079 if (GET_CODE (body) == SET)
12081 rtx dest = SET_DEST (body);
12083 unsigned int regno, tregno, endregno, endtregno;
12085 if (GET_CODE (dest) == ZERO_EXTRACT)
12086 target = XEXP (dest, 0);
12087 else if (GET_CODE (dest) == STRICT_LOW_PART)
12088 target = SUBREG_REG (XEXP (dest, 0));
12092 if (GET_CODE (target) == SUBREG)
12093 target = SUBREG_REG (target);
12095 if (GET_CODE (target) != REG)
12098 tregno = REGNO (target), regno = REGNO (x);
12099 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12100 return target == x;
12102 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12103 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12105 return endregno > tregno && regno < endtregno;
12108 else if (GET_CODE (body) == PARALLEL)
12109 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12110 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12116 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12117 as appropriate. I3 and I2 are the insns resulting from the combination
12118 insns including FROM (I2 may be zero).
12120 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12121 not need REG_DEAD notes because they are being substituted for. This
12122 saves searching in the most common cases.
12124 Each note in the list is either ignored or placed on some insns, depending
12125 on the type of note. */
12128 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12132 rtx elim_i2, elim_i1;
12134 rtx note, next_note;
12137 for (note = notes; note; note = next_note)
12139 rtx place = 0, place2 = 0;
12141 /* If this NOTE references a pseudo register, ensure it references
12142 the latest copy of that register. */
12143 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12144 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12145 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12147 next_note = XEXP (note, 1);
12148 switch (REG_NOTE_KIND (note))
12151 case REG_EXEC_COUNT:
12152 /* Doesn't matter much where we put this, as long as it's somewhere.
12153 It is preferable to keep these notes on branches, which is most
12154 likely to be i3. */
12158 case REG_NON_LOCAL_GOTO:
12159 if (GET_CODE (i3) == JUMP_INSN)
12161 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12167 case REG_EH_REGION:
12168 case REG_EH_RETHROW:
12170 /* These notes must remain with the call. It should not be
12171 possible for both I2 and I3 to be a call. */
12172 if (GET_CODE (i3) == CALL_INSN)
12174 else if (i2 && GET_CODE (i2) == CALL_INSN)
12181 /* Any clobbers for i3 may still exist, and so we must process
12182 REG_UNUSED notes from that insn.
12184 Any clobbers from i2 or i1 can only exist if they were added by
12185 recog_for_combine. In that case, recog_for_combine created the
12186 necessary REG_UNUSED notes. Trying to keep any original
12187 REG_UNUSED notes from these insns can cause incorrect output
12188 if it is for the same register as the original i3 dest.
12189 In that case, we will notice that the register is set in i3,
12190 and then add a REG_UNUSED note for the destination of i3, which
12191 is wrong. However, it is possible to have REG_UNUSED notes from
12192 i2 or i1 for register which were both used and clobbered, so
12193 we keep notes from i2 or i1 if they will turn into REG_DEAD
12196 /* If this register is set or clobbered in I3, put the note there
12197 unless there is one already. */
12198 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12200 if (from_insn != i3)
12203 if (! (GET_CODE (XEXP (note, 0)) == REG
12204 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12205 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12208 /* Otherwise, if this register is used by I3, then this register
12209 now dies here, so we must put a REG_DEAD note here unless there
12211 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12212 && ! (GET_CODE (XEXP (note, 0)) == REG
12213 ? find_regno_note (i3, REG_DEAD,
12214 REGNO (XEXP (note, 0)))
12215 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12217 PUT_REG_NOTE_KIND (note, REG_DEAD);
12225 /* These notes say something about results of an insn. We can
12226 only support them if they used to be on I3 in which case they
12227 remain on I3. Otherwise they are ignored.
12229 If the note refers to an expression that is not a constant, we
12230 must also ignore the note since we cannot tell whether the
12231 equivalence is still true. It might be possible to do
12232 slightly better than this (we only have a problem if I2DEST
12233 or I1DEST is present in the expression), but it doesn't
12234 seem worth the trouble. */
12236 if (from_insn == i3
12237 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12242 case REG_NO_CONFLICT:
12243 /* These notes say something about how a register is used. They must
12244 be present on any use of the register in I2 or I3. */
12245 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12248 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12258 /* This can show up in several ways -- either directly in the
12259 pattern, or hidden off in the constant pool with (or without?)
12260 a REG_EQUAL note. */
12261 /* ??? Ignore the without-reg_equal-note problem for now. */
12262 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12263 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12264 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12265 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12269 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12270 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12271 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12272 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12283 /* These notes say something about the value of a register prior
12284 to the execution of an insn. It is too much trouble to see
12285 if the note is still correct in all situations. It is better
12286 to simply delete it. */
12290 /* If the insn previously containing this note still exists,
12291 put it back where it was. Otherwise move it to the previous
12292 insn. Adjust the corresponding REG_LIBCALL note. */
12293 if (GET_CODE (from_insn) != NOTE)
12297 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12298 place = prev_real_insn (from_insn);
12300 XEXP (tem, 0) = place;
12301 /* If we're deleting the last remaining instruction of a
12302 libcall sequence, don't add the notes. */
12303 else if (XEXP (note, 0) == from_insn)
12309 /* This is handled similarly to REG_RETVAL. */
12310 if (GET_CODE (from_insn) != NOTE)
12314 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12315 place = next_real_insn (from_insn);
12317 XEXP (tem, 0) = place;
12318 /* If we're deleting the last remaining instruction of a
12319 libcall sequence, don't add the notes. */
12320 else if (XEXP (note, 0) == from_insn)
12326 /* If the register is used as an input in I3, it dies there.
12327 Similarly for I2, if it is non-zero and adjacent to I3.
12329 If the register is not used as an input in either I3 or I2
12330 and it is not one of the registers we were supposed to eliminate,
12331 there are two possibilities. We might have a non-adjacent I2
12332 or we might have somehow eliminated an additional register
12333 from a computation. For example, we might have had A & B where
12334 we discover that B will always be zero. In this case we will
12335 eliminate the reference to A.
12337 In both cases, we must search to see if we can find a previous
12338 use of A and put the death note there. */
12341 && GET_CODE (from_insn) == CALL_INSN
12342 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12344 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12346 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12347 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12350 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12351 || rtx_equal_p (XEXP (note, 0), elim_i1))
12356 basic_block bb = BASIC_BLOCK (this_basic_block);
12358 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12360 if (! INSN_P (tem))
12362 if (tem == bb->head)
12367 /* If the register is being set at TEM, see if that is all
12368 TEM is doing. If so, delete TEM. Otherwise, make this
12369 into a REG_UNUSED note instead. */
12370 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12372 rtx set = single_set (tem);
12373 rtx inner_dest = 0;
12375 rtx cc0_setter = NULL_RTX;
12379 for (inner_dest = SET_DEST (set);
12380 (GET_CODE (inner_dest) == STRICT_LOW_PART
12381 || GET_CODE (inner_dest) == SUBREG
12382 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12383 inner_dest = XEXP (inner_dest, 0))
12386 /* Verify that it was the set, and not a clobber that
12387 modified the register.
12389 CC0 targets must be careful to maintain setter/user
12390 pairs. If we cannot delete the setter due to side
12391 effects, mark the user with an UNUSED note instead
12394 if (set != 0 && ! side_effects_p (SET_SRC (set))
12395 && rtx_equal_p (XEXP (note, 0), inner_dest)
12397 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12398 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12399 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12403 /* Move the notes and links of TEM elsewhere.
12404 This might delete other dead insns recursively.
12405 First set the pattern to something that won't use
12408 PATTERN (tem) = pc_rtx;
12410 distribute_notes (REG_NOTES (tem), tem, tem,
12411 NULL_RTX, NULL_RTX, NULL_RTX);
12412 distribute_links (LOG_LINKS (tem));
12414 PUT_CODE (tem, NOTE);
12415 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12416 NOTE_SOURCE_FILE (tem) = 0;
12419 /* Delete the setter too. */
12422 PATTERN (cc0_setter) = pc_rtx;
12424 distribute_notes (REG_NOTES (cc0_setter),
12425 cc0_setter, cc0_setter,
12426 NULL_RTX, NULL_RTX, NULL_RTX);
12427 distribute_links (LOG_LINKS (cc0_setter));
12429 PUT_CODE (cc0_setter, NOTE);
12430 NOTE_LINE_NUMBER (cc0_setter)
12431 = NOTE_INSN_DELETED;
12432 NOTE_SOURCE_FILE (cc0_setter) = 0;
12436 /* If the register is both set and used here, put the
12437 REG_DEAD note here, but place a REG_UNUSED note
12438 here too unless there already is one. */
12439 else if (reg_referenced_p (XEXP (note, 0),
12444 if (! find_regno_note (tem, REG_UNUSED,
12445 REGNO (XEXP (note, 0))))
12447 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12452 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12454 /* If there isn't already a REG_UNUSED note, put one
12456 if (! find_regno_note (tem, REG_UNUSED,
12457 REGNO (XEXP (note, 0))))
12462 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12463 || (GET_CODE (tem) == CALL_INSN
12464 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12468 /* If we are doing a 3->2 combination, and we have a
12469 register which formerly died in i3 and was not used
12470 by i2, which now no longer dies in i3 and is used in
12471 i2 but does not die in i2, and place is between i2
12472 and i3, then we may need to move a link from place to
12474 if (i2 && INSN_UID (place) <= max_uid_cuid
12475 && INSN_CUID (place) > INSN_CUID (i2)
12477 && INSN_CUID (from_insn) > INSN_CUID (i2)
12478 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12480 rtx links = LOG_LINKS (place);
12481 LOG_LINKS (place) = 0;
12482 distribute_links (links);
12487 if (tem == bb->head)
12491 /* We haven't found an insn for the death note and it
12492 is still a REG_DEAD note, but we have hit the beginning
12493 of the block. If the existing life info says the reg
12494 was dead, there's nothing left to do. Otherwise, we'll
12495 need to do a global life update after combine. */
12496 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12497 && REGNO_REG_SET_P (bb->global_live_at_start,
12498 REGNO (XEXP (note, 0))))
12500 SET_BIT (refresh_blocks, this_basic_block);
12505 /* If the register is set or already dead at PLACE, we needn't do
12506 anything with this note if it is still a REG_DEAD note.
12507 We can here if it is set at all, not if is it totally replace,
12508 which is what `dead_or_set_p' checks, so also check for it being
12511 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12513 unsigned int regno = REGNO (XEXP (note, 0));
12515 if (dead_or_set_p (place, XEXP (note, 0))
12516 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12518 /* Unless the register previously died in PLACE, clear
12519 reg_last_death. [I no longer understand why this is
12521 if (reg_last_death[regno] != place)
12522 reg_last_death[regno] = 0;
12526 reg_last_death[regno] = place;
12528 /* If this is a death note for a hard reg that is occupying
12529 multiple registers, ensure that we are still using all
12530 parts of the object. If we find a piece of the object
12531 that is unused, we must arrange for an appropriate REG_DEAD
12532 note to be added for it. However, we can't just emit a USE
12533 and tag the note to it, since the register might actually
12534 be dead; so we recourse, and the recursive call then finds
12535 the previous insn that used this register. */
12537 if (place && regno < FIRST_PSEUDO_REGISTER
12538 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12540 unsigned int endregno
12541 = regno + HARD_REGNO_NREGS (regno,
12542 GET_MODE (XEXP (note, 0)));
12546 for (i = regno; i < endregno; i++)
12547 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12548 && ! find_regno_fusage (place, USE, i))
12549 || dead_or_set_regno_p (place, i))
12554 /* Put only REG_DEAD notes for pieces that are
12555 not already dead or set. */
12557 for (i = regno; i < endregno;
12558 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12560 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12561 basic_block bb = BASIC_BLOCK (this_basic_block);
12563 if (! dead_or_set_p (place, piece)
12564 && ! reg_bitfield_target_p (piece,
12568 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12570 distribute_notes (new_note, place, place,
12571 NULL_RTX, NULL_RTX, NULL_RTX);
12573 else if (! refers_to_regno_p (i, i + 1,
12574 PATTERN (place), 0)
12575 && ! find_regno_fusage (place, USE, i))
12576 for (tem = PREV_INSN (place); ;
12577 tem = PREV_INSN (tem))
12579 if (! INSN_P (tem))
12581 if (tem == bb->head)
12583 SET_BIT (refresh_blocks,
12590 if (dead_or_set_p (tem, piece)
12591 || reg_bitfield_target_p (piece,
12595 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12610 /* Any other notes should not be present at this point in the
12617 XEXP (note, 1) = REG_NOTES (place);
12618 REG_NOTES (place) = note;
12620 else if ((REG_NOTE_KIND (note) == REG_DEAD
12621 || REG_NOTE_KIND (note) == REG_UNUSED)
12622 && GET_CODE (XEXP (note, 0)) == REG)
12623 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12627 if ((REG_NOTE_KIND (note) == REG_DEAD
12628 || REG_NOTE_KIND (note) == REG_UNUSED)
12629 && GET_CODE (XEXP (note, 0)) == REG)
12630 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12632 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12633 REG_NOTE_KIND (note),
12635 REG_NOTES (place2));
12640 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12641 I3, I2, and I1 to new locations. This is also called in one case to
12642 add a link pointing at I3 when I3's destination is changed. */
12645 distribute_links (links)
12648 rtx link, next_link;
12650 for (link = links; link; link = next_link)
12656 next_link = XEXP (link, 1);
12658 /* If the insn that this link points to is a NOTE or isn't a single
12659 set, ignore it. In the latter case, it isn't clear what we
12660 can do other than ignore the link, since we can't tell which
12661 register it was for. Such links wouldn't be used by combine
12664 It is not possible for the destination of the target of the link to
12665 have been changed by combine. The only potential of this is if we
12666 replace I3, I2, and I1 by I3 and I2. But in that case the
12667 destination of I2 also remains unchanged. */
12669 if (GET_CODE (XEXP (link, 0)) == NOTE
12670 || (set = single_set (XEXP (link, 0))) == 0)
12673 reg = SET_DEST (set);
12674 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12675 || GET_CODE (reg) == SIGN_EXTRACT
12676 || GET_CODE (reg) == STRICT_LOW_PART)
12677 reg = XEXP (reg, 0);
12679 /* A LOG_LINK is defined as being placed on the first insn that uses
12680 a register and points to the insn that sets the register. Start
12681 searching at the next insn after the target of the link and stop
12682 when we reach a set of the register or the end of the basic block.
12684 Note that this correctly handles the link that used to point from
12685 I3 to I2. Also note that not much searching is typically done here
12686 since most links don't point very far away. */
12688 for (insn = NEXT_INSN (XEXP (link, 0));
12689 (insn && (this_basic_block == n_basic_blocks - 1
12690 || BLOCK_HEAD (this_basic_block + 1) != insn));
12691 insn = NEXT_INSN (insn))
12692 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12694 if (reg_referenced_p (reg, PATTERN (insn)))
12698 else if (GET_CODE (insn) == CALL_INSN
12699 && find_reg_fusage (insn, USE, reg))
12705 /* If we found a place to put the link, place it there unless there
12706 is already a link to the same insn as LINK at that point. */
12712 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12713 if (XEXP (link2, 0) == XEXP (link, 0))
12718 XEXP (link, 1) = LOG_LINKS (place);
12719 LOG_LINKS (place) = link;
12721 /* Set added_links_insn to the earliest insn we added a
12723 if (added_links_insn == 0
12724 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12725 added_links_insn = place;
12731 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12737 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12738 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12739 insn = NEXT_INSN (insn);
12741 if (INSN_UID (insn) > max_uid_cuid)
12744 return INSN_CUID (insn);
12748 dump_combine_stats (file)
12753 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12754 combine_attempts, combine_merges, combine_extras, combine_successes);
12758 dump_combine_total_stats (file)
12763 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12764 total_attempts, total_merges, total_extras, total_successes);