1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
82 #include "basic-block.h"
83 #include "insn-config.h"
84 #include "insn-flags.h"
85 #include "insn-codes.h"
86 #include "insn-attr.h"
91 /* It is not safe to use ordinary gen_lowpart in combine.
92 Use gen_lowpart_for_combine instead. See comments there. */
93 #define gen_lowpart dont_use_gen_lowpart_you_dummy
95 /* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND
96 for cases when we don't care which is true. Define LOAD_EXTEND to
97 be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */
99 #ifdef BYTE_LOADS_ZERO_EXTEND
100 #define BYTE_LOADS_EXTEND
101 #define LOAD_EXTEND ZERO_EXTEND
104 #ifdef BYTE_LOAD_SIGN_EXTEND
105 #define BYTE_LOADS_EXTEND
106 #define LOAD_EXTEND SIGN_EXTEND
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* Vector mapping INSN_UIDs to cuids.
130 The cuids are like uids but increase monotonically always.
131 Combine always uses cuids so that it can compare them.
132 But actually renumbering the uids, which we used to do,
133 proves to be a bad idea because it makes it hard to compare
134 the dumps produced by earlier passes with those from later passes. */
136 static int *uid_cuid;
138 /* Get the cuid of an insn. */
140 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx *reg_last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx *reg_last_set;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn;
172 /* This is the lowest CUID that `subst' is currently dealing with.
173 get_last_value will not return a value if the register was set at or
174 after this CUID. If not for this mechanism, we could get confused if
175 I2 or I1 in try_combine were an insn that used the old value of a register
176 to obtain a new value. In that case, we might erroneously get the
177 new value of the register when we wanted the old one. */
179 static int subst_low_cuid;
181 /* This is the value of undobuf.num_undo when we started processing this
182 substitution. This will prevent gen_rtx_combine from re-used a piece
183 from the previous expression. Doing so can produce circular rtl
186 static int previous_num_undos;
188 /* The next group of arrays allows the recording of the last value assigned
189 to (hard or pseudo) register n. We use this information to see if a
190 operation being processed is redundant given a prior operation performed
191 on the register. For example, an `and' with a constant is redundant if
192 all the zero bits are already known to be turned off.
194 We use an approach similar to that used by cse, but change it in the
197 (1) We do not want to reinitialize at each label.
198 (2) It is useful, but not critical, to know the actual value assigned
199 to a register. Often just its form is helpful.
201 Therefore, we maintain the following arrays:
203 reg_last_set_value the last value assigned
204 reg_last_set_label records the value of label_tick when the
205 register was assigned
206 reg_last_set_table_tick records the value of label_tick when a
207 value using the register is assigned
208 reg_last_set_invalid set to non-zero when it is not valid
209 to use the value of this register in some
212 To understand the usage of these tables, it is important to understand
213 the distinction between the value in reg_last_set_value being valid
214 and the register being validly contained in some other expression in the
217 Entry I in reg_last_set_value is valid if it is non-zero, and either
218 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
220 Register I may validly appear in any expression returned for the value
221 of another register if reg_n_sets[i] is 1. It may also appear in the
222 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
223 reg_last_set_invalid[j] is zero.
225 If an expression is found in the table containing a register which may
226 not validly appear in an expression, the register is replaced by
227 something that won't match, (clobber (const_int 0)).
229 reg_last_set_invalid[i] is set non-zero when register I is being assigned
230 to and reg_last_set_table_tick[i] == label_tick. */
232 /* Record last value assigned to (hard or pseudo) register n. */
234 static rtx *reg_last_set_value;
236 /* Record the value of label_tick when the value for register n is placed in
237 reg_last_set_value[n]. */
239 static short *reg_last_set_label;
241 /* Record the value of label_tick when an expression involving register n
242 is placed in reg_last_set_value. */
244 static short *reg_last_set_table_tick;
246 /* Set non-zero if references to register n in expressions should not be
249 static char *reg_last_set_invalid;
251 /* Incremented for each label. */
253 static short label_tick;
255 /* Some registers that are set more than once and used in more than one
256 basic block are nevertheless always set in similar ways. For example,
257 a QImode register may be loaded from memory in two places on a machine
258 where byte loads zero extend.
260 We record in the following array what we know about the nonzero
261 bits of a register, specifically which bits are known to be zero.
263 If an entry is zero, it means that we don't know anything special. */
265 static HOST_WIDE_INT *reg_nonzero_bits;
267 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
268 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
270 static enum machine_mode nonzero_bits_mode;
272 /* Nonzero if we know that a register has some leading bits that are always
273 equal to the sign bit. */
275 static char *reg_sign_bit_copies;
277 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
278 It is zero while computing them and after combine has completed. This
279 former test prevents propagating values based on previously set values,
280 which can be incorrect if a variable is modified in a loop. */
282 static int nonzero_sign_valid;
284 /* Record one modification to rtl structure
285 to be undone by storing old_contents into *where.
286 is_int is 1 if the contents are an int. */
291 union {rtx rtx; int i;} old_contents;
292 union {rtx *rtx; int *i;} where;
295 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
296 num_undo says how many are currently recorded.
298 storage is nonzero if we must undo the allocation of new storage.
299 The value of storage is what to pass to obfree.
301 other_insn is nonzero if we have modified some other insn in the process
302 of working on subst_insn. It must be verified too. */
310 struct undo undo[MAX_UNDO];
314 static struct undobuf undobuf;
316 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
317 insn. The substitution can be undone by undo_all. If INTO is already
318 set to NEWVAL, do not record this change. Because computing NEWVAL might
319 also call SUBST, we have to compute it before we put anything into
322 #define SUBST(INTO, NEWVAL) \
323 do { rtx _new = (NEWVAL); \
324 if (undobuf.num_undo < MAX_UNDO) \
326 undobuf.undo[undobuf.num_undo].is_int = 0; \
327 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
328 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
330 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
331 undobuf.num_undo++; \
335 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
337 Note that substitution for the value of a CONST_INT is not safe. */
339 #define SUBST_INT(INTO, NEWVAL) \
340 do { if (undobuf.num_undo < MAX_UNDO) \
342 undobuf.undo[undobuf.num_undo].is_int = 1; \
343 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
344 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
346 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
347 undobuf.num_undo++; \
351 /* Number of times the pseudo being substituted for
352 was found and replaced. */
354 static int n_occurrences;
356 static void set_nonzero_bits_and_sign_copies ();
357 static void setup_incoming_promotions ();
358 static void move_deaths ();
360 static void record_value_for_reg ();
361 static void record_dead_and_set_regs ();
362 static int use_crosses_set_p ();
363 static rtx try_combine ();
364 static rtx *find_split_point ();
366 static void undo_all ();
367 static int reg_dead_at_p ();
368 static rtx expand_compound_operation ();
369 static rtx expand_field_assignment ();
370 static rtx make_extraction ();
371 static int get_pos_from_mask ();
372 static rtx force_to_mode ();
373 static rtx known_cond ();
374 static rtx make_field_assignment ();
375 static rtx make_compound_operation ();
376 static rtx apply_distributive_law ();
377 static rtx simplify_and_const_int ();
378 static unsigned HOST_WIDE_INT nonzero_bits ();
379 static int num_sign_bit_copies ();
380 static int merge_outer_ops ();
381 static rtx simplify_shift_const ();
382 static int recog_for_combine ();
383 static rtx gen_lowpart_for_combine ();
384 static rtx gen_rtx_combine ();
385 static rtx gen_binary ();
386 static rtx gen_unary ();
387 static enum rtx_code simplify_comparison ();
388 static int reversible_comparison_p ();
389 static int get_last_value_validate ();
390 static rtx get_last_value ();
391 static void distribute_notes ();
392 static void distribute_links ();
394 /* Main entry point for combiner. F is the first insn of the function.
395 NREGS is the first unused pseudo-reg number. */
398 combine_instructions (f, nregs)
402 register rtx insn, next, prev;
404 register rtx links, nextlinks;
406 combine_attempts = 0;
409 combine_successes = 0;
410 undobuf.num_undo = previous_num_undos = 0;
412 combine_max_regno = nregs;
414 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
415 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
416 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
417 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
418 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
419 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
420 reg_nonzero_bits = (HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
421 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
423 bzero (reg_last_death, nregs * sizeof (rtx));
424 bzero (reg_last_set, nregs * sizeof (rtx));
425 bzero (reg_last_set_value, nregs * sizeof (rtx));
426 bzero (reg_last_set_table_tick, nregs * sizeof (short));
427 bzero (reg_last_set_label, nregs * sizeof (short));
428 bzero (reg_last_set_invalid, nregs * sizeof (char));
429 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
430 bzero (reg_sign_bit_copies, nregs * sizeof (char));
432 init_recog_no_volatile ();
434 /* Compute maximum uid value so uid_cuid can be allocated. */
436 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
437 if (INSN_UID (insn) > i)
440 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
442 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
444 /* Don't use reg_nonzero_bits when computing it. This can cause problems
445 when, for example, we have j <<= 1 in a loop. */
447 nonzero_sign_valid = 0;
449 /* Compute the mapping from uids to cuids.
450 Cuids are numbers assigned to insns, like uids,
451 except that cuids increase monotonically through the code.
453 Scan all SETs and see if we can deduce anything about what
454 bits are known to be zero for some registers and how many copies
455 of the sign bit are known to exist for those registers.
457 Also set any known values so that we can use it while searching
458 for what bits are known to be set. */
462 setup_incoming_promotions ();
464 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
466 INSN_CUID (insn) = ++i;
470 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
472 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
473 record_dead_and_set_regs (insn);
476 if (GET_CODE (insn) == CODE_LABEL)
480 nonzero_sign_valid = 1;
482 /* Now scan all the insns in forward order. */
487 bzero (reg_last_death, nregs * sizeof (rtx));
488 bzero (reg_last_set, nregs * sizeof (rtx));
489 bzero (reg_last_set_value, nregs * sizeof (rtx));
490 bzero (reg_last_set_table_tick, nregs * sizeof (short));
491 bzero (reg_last_set_label, nregs * sizeof (short));
492 bzero (reg_last_set_invalid, nregs * sizeof (char));
494 setup_incoming_promotions ();
496 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
500 if (GET_CODE (insn) == CODE_LABEL)
503 else if (GET_CODE (insn) == INSN
504 || GET_CODE (insn) == CALL_INSN
505 || GET_CODE (insn) == JUMP_INSN)
507 /* Try this insn with each insn it links back to. */
509 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
510 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
513 /* Try each sequence of three linked insns ending with this one. */
515 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
516 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
517 nextlinks = XEXP (nextlinks, 1))
518 if ((next = try_combine (insn, XEXP (links, 0),
519 XEXP (nextlinks, 0))) != 0)
523 /* Try to combine a jump insn that uses CC0
524 with a preceding insn that sets CC0, and maybe with its
525 logical predecessor as well.
526 This is how we make decrement-and-branch insns.
527 We need this special code because data flow connections
528 via CC0 do not get entered in LOG_LINKS. */
530 if (GET_CODE (insn) == JUMP_INSN
531 && (prev = prev_nonnote_insn (insn)) != 0
532 && GET_CODE (prev) == INSN
533 && sets_cc0_p (PATTERN (prev)))
535 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
538 for (nextlinks = LOG_LINKS (prev); nextlinks;
539 nextlinks = XEXP (nextlinks, 1))
540 if ((next = try_combine (insn, prev,
541 XEXP (nextlinks, 0))) != 0)
545 /* Do the same for an insn that explicitly references CC0. */
546 if (GET_CODE (insn) == INSN
547 && (prev = prev_nonnote_insn (insn)) != 0
548 && GET_CODE (prev) == INSN
549 && sets_cc0_p (PATTERN (prev))
550 && GET_CODE (PATTERN (insn)) == SET
551 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
553 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
556 for (nextlinks = LOG_LINKS (prev); nextlinks;
557 nextlinks = XEXP (nextlinks, 1))
558 if ((next = try_combine (insn, prev,
559 XEXP (nextlinks, 0))) != 0)
563 /* Finally, see if any of the insns that this insn links to
564 explicitly references CC0. If so, try this insn, that insn,
565 and its predecessor if it sets CC0. */
566 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
567 if (GET_CODE (XEXP (links, 0)) == INSN
568 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
569 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
570 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
571 && GET_CODE (prev) == INSN
572 && sets_cc0_p (PATTERN (prev))
573 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
577 /* Try combining an insn with two different insns whose results it
579 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
580 for (nextlinks = XEXP (links, 1); nextlinks;
581 nextlinks = XEXP (nextlinks, 1))
582 if ((next = try_combine (insn, XEXP (links, 0),
583 XEXP (nextlinks, 0))) != 0)
586 if (GET_CODE (insn) != NOTE)
587 record_dead_and_set_regs (insn);
594 total_attempts += combine_attempts;
595 total_merges += combine_merges;
596 total_extras += combine_extras;
597 total_successes += combine_successes;
599 nonzero_sign_valid = 0;
602 /* Set up any promoted values for incoming argument registers. */
605 setup_incoming_promotions ()
607 #ifdef PROMOTE_FUNCTION_ARGS
610 enum machine_mode mode;
612 rtx first = get_insns ();
614 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
615 if (FUNCTION_ARG_REGNO_P (regno)
616 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
617 record_value_for_reg (reg, first,
618 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
620 gen_rtx (CLOBBER, VOIDmode, const0_rtx)));
624 /* Called via note_stores. If X is a pseudo that is used in more than
625 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
626 set, record what bits are known zero. If we are clobbering X,
627 ignore this "set" because the clobbered value won't be used.
629 If we are setting only a portion of X and we can't figure out what
630 portion, assume all bits will be used since we don't know what will
633 Similarly, set how many bits of X are known to be copies of the sign bit
634 at all locations in the function. This is the smallest number implied
638 set_nonzero_bits_and_sign_copies (x, set)
644 if (GET_CODE (x) == REG
645 && REGNO (x) >= FIRST_PSEUDO_REGISTER
646 && reg_n_sets[REGNO (x)] > 1
647 && reg_basic_block[REGNO (x)] < 0
648 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
650 if (GET_CODE (set) == CLOBBER)
653 /* If this is a complex assignment, see if we can convert it into a
654 simple assignment. */
655 set = expand_field_assignment (set);
657 /* If this is a simple assignment, or we have a paradoxical SUBREG,
658 set what we know about X. */
660 if (SET_DEST (set) == x
661 || (GET_CODE (SET_DEST (set)) == SUBREG
662 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
663 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
664 && SUBREG_REG (SET_DEST (set)) == x))
666 reg_nonzero_bits[REGNO (x)]
667 |= nonzero_bits (SET_SRC (set), nonzero_bits_mode);
668 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
669 if (reg_sign_bit_copies[REGNO (x)] == 0
670 || reg_sign_bit_copies[REGNO (x)] > num)
671 reg_sign_bit_copies[REGNO (x)] = num;
675 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
676 reg_sign_bit_copies[REGNO (x)] = 0;
681 /* See if INSN can be combined into I3. PRED and SUCC are optionally
682 insns that were previously combined into I3 or that will be combined
683 into the merger of INSN and I3.
685 Return 0 if the combination is not allowed for any reason.
687 If the combination is allowed, *PDEST will be set to the single
688 destination of INSN and *PSRC to the single source, and this function
692 can_combine_p (insn, i3, pred, succ, pdest, psrc)
699 rtx set = 0, src, dest;
701 int all_adjacent = (succ ? (next_active_insn (insn) == succ
702 && next_active_insn (succ) == i3)
703 : next_active_insn (insn) == i3);
705 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
706 or a PARALLEL consisting of such a SET and CLOBBERs.
708 If INSN has CLOBBER parallel parts, ignore them for our processing.
709 By definition, these happen during the execution of the insn. When it
710 is merged with another insn, all bets are off. If they are, in fact,
711 needed and aren't also supplied in I3, they may be added by
712 recog_for_combine. Otherwise, it won't match.
714 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
717 Get the source and destination of INSN. If more than one, can't
720 if (GET_CODE (PATTERN (insn)) == SET)
721 set = PATTERN (insn);
722 else if (GET_CODE (PATTERN (insn)) == PARALLEL
723 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
725 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
727 rtx elt = XVECEXP (PATTERN (insn), 0, i);
729 switch (GET_CODE (elt))
731 /* We can ignore CLOBBERs. */
736 /* Ignore SETs whose result isn't used but not those that
737 have side-effects. */
738 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
739 && ! side_effects_p (elt))
742 /* If we have already found a SET, this is a second one and
743 so we cannot combine with this insn. */
751 /* Anything else means we can't combine. */
757 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
758 so don't do anything with it. */
759 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
768 set = expand_field_assignment (set);
769 src = SET_SRC (set), dest = SET_DEST (set);
771 /* Don't eliminate a store in the stack pointer. */
772 if (dest == stack_pointer_rtx
773 /* Don't install a subreg involving two modes not tieable.
774 It can worsen register allocation, and can even make invalid reload
775 insns, since the reg inside may need to be copied from in the
776 outside mode, and that may be invalid if it is an fp reg copied in
777 integer mode. As a special exception, we can allow this if
778 I3 is simply copying DEST, a REG, to CC0. */
779 || (GET_CODE (src) == SUBREG
780 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
782 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
783 && SET_DEST (PATTERN (i3)) == cc0_rtx
784 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
787 /* If we couldn't eliminate a field assignment, we can't combine. */
788 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
789 /* Don't combine with an insn that sets a register to itself if it has
790 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
791 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
792 /* Can't merge a function call. */
793 || GET_CODE (src) == CALL
794 /* Don't substitute into an incremented register. */
795 || FIND_REG_INC_NOTE (i3, dest)
796 || (succ && FIND_REG_INC_NOTE (succ, dest))
797 /* Don't combine the end of a libcall into anything. */
798 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
799 /* Make sure that DEST is not used after SUCC but before I3. */
800 || (succ && ! all_adjacent
801 && reg_used_between_p (dest, succ, i3))
802 /* Make sure that the value that is to be substituted for the register
803 does not use any registers whose values alter in between. However,
804 If the insns are adjacent, a use can't cross a set even though we
805 think it might (this can happen for a sequence of insns each setting
806 the same destination; reg_last_set of that register might point to
807 a NOTE). Also, don't move a volatile asm across any other insns. */
809 && (use_crosses_set_p (src, INSN_CUID (insn))
810 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
811 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
812 better register allocation by not doing the combine. */
813 || find_reg_note (i3, REG_NO_CONFLICT, dest)
814 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
815 /* Don't combine across a CALL_INSN, because that would possibly
816 change whether the life span of some REGs crosses calls or not,
817 and it is a pain to update that information.
818 Exception: if source is a constant, moving it later can't hurt.
819 Accept that special case, because it helps -fforce-addr a lot. */
820 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
823 /* DEST must either be a REG or CC0. */
824 if (GET_CODE (dest) == REG)
826 /* If register alignment is being enforced for multi-word items in all
827 cases except for parameters, it is possible to have a register copy
828 insn referencing a hard register that is not allowed to contain the
829 mode being copied and which would not be valid as an operand of most
830 insns. Eliminate this problem by not combining with such an insn.
832 Also, on some machines we don't want to extend the life of a hard
835 if (GET_CODE (src) == REG
836 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
837 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
838 #ifdef SMALL_REGISTER_CLASSES
839 /* Don't extend the life of a hard register. */
840 || REGNO (src) < FIRST_PSEUDO_REGISTER
842 || (REGNO (src) < FIRST_PSEUDO_REGISTER
843 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
848 else if (GET_CODE (dest) != CC0)
851 /* Don't substitute for a register intended as a clobberable operand.
852 Similarly, don't substitute an expression containing a register that
853 will be clobbered in I3. */
854 if (GET_CODE (PATTERN (i3)) == PARALLEL)
855 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
856 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
857 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
859 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
862 /* If INSN contains anything volatile, or is an `asm' (whether volatile
863 or not), reject, unless nothing volatile comes between it and I3,
864 with the exception of SUCC. */
866 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
867 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
868 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
869 && p != succ && volatile_refs_p (PATTERN (p)))
872 /* If INSN or I2 contains an autoincrement or autodecrement,
873 make sure that register is not used between there and I3,
874 and not already used in I3 either.
875 Also insist that I3 not be a jump; if it were one
876 and the incremented register were spilled, we would lose. */
879 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
880 if (REG_NOTE_KIND (link) == REG_INC
881 && (GET_CODE (i3) == JUMP_INSN
882 || reg_used_between_p (XEXP (link, 0), insn, i3)
883 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
888 /* Don't combine an insn that follows a CC0-setting insn.
889 An insn that uses CC0 must not be separated from the one that sets it.
890 We do, however, allow I2 to follow a CC0-setting insn if that insn
891 is passed as I1; in that case it will be deleted also.
892 We also allow combining in this case if all the insns are adjacent
893 because that would leave the two CC0 insns adjacent as well.
894 It would be more logical to test whether CC0 occurs inside I1 or I2,
895 but that would be much slower, and this ought to be equivalent. */
897 p = prev_nonnote_insn (insn);
898 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
903 /* If we get here, we have passed all the tests and the combination is
912 /* LOC is the location within I3 that contains its pattern or the component
913 of a PARALLEL of the pattern. We validate that it is valid for combining.
915 One problem is if I3 modifies its output, as opposed to replacing it
916 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
917 so would produce an insn that is not equivalent to the original insns.
921 (set (reg:DI 101) (reg:DI 100))
922 (set (subreg:SI (reg:DI 101) 0) <foo>)
924 This is NOT equivalent to:
926 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
927 (set (reg:DI 101) (reg:DI 100))])
929 Not only does this modify 100 (in which case it might still be valid
930 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
932 We can also run into a problem if I2 sets a register that I1
933 uses and I1 gets directly substituted into I3 (not via I2). In that
934 case, we would be getting the wrong value of I2DEST into I3, so we
935 must reject the combination. This case occurs when I2 and I1 both
936 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
937 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
938 of a SET must prevent combination from occurring.
940 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
941 if the destination of a SET is a hard register.
943 Before doing the above check, we first try to expand a field assignment
944 into a set of logical operations.
946 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
947 we place a register that is both set and used within I3. If more than one
948 such register is detected, we fail.
950 Return 1 if the combination is valid, zero otherwise. */
953 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
963 if (GET_CODE (x) == SET)
965 rtx set = expand_field_assignment (x);
966 rtx dest = SET_DEST (set);
967 rtx src = SET_SRC (set);
968 rtx inner_dest = dest, inner_src = src;
972 while (GET_CODE (inner_dest) == STRICT_LOW_PART
973 || GET_CODE (inner_dest) == SUBREG
974 || GET_CODE (inner_dest) == ZERO_EXTRACT)
975 inner_dest = XEXP (inner_dest, 0);
977 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
980 while (GET_CODE (inner_src) == STRICT_LOW_PART
981 || GET_CODE (inner_src) == SUBREG
982 || GET_CODE (inner_src) == ZERO_EXTRACT)
983 inner_src = XEXP (inner_src, 0);
985 /* If it is better that two different modes keep two different pseudos,
986 avoid combining them. This avoids producing the following pattern
988 (set (subreg:SI (reg/v:QI 21) 0)
989 (lshiftrt:SI (reg/v:SI 20)
991 If that were made, reload could not handle the pair of
992 reg 20/21, since it would try to get any GENERAL_REGS
993 but some of them don't handle QImode. */
995 if (rtx_equal_p (inner_src, i2dest)
996 && GET_CODE (inner_dest) == REG
997 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1001 /* Check for the case where I3 modifies its output, as
1003 if ((inner_dest != dest
1004 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1005 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1006 /* This is the same test done in can_combine_p except that we
1007 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1009 || (GET_CODE (inner_dest) == REG
1010 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1011 #ifdef SMALL_REGISTER_CLASSES
1012 && GET_CODE (src) != CALL
1014 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1015 GET_MODE (inner_dest))
1019 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1022 /* If DEST is used in I3, it is being killed in this insn,
1023 so record that for later. */
1024 if (pi3dest_killed && GET_CODE (dest) == REG
1025 && reg_referenced_p (dest, PATTERN (i3)))
1027 if (*pi3dest_killed)
1030 *pi3dest_killed = dest;
1034 else if (GET_CODE (x) == PARALLEL)
1038 for (i = 0; i < XVECLEN (x, 0); i++)
1039 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1040 i1_not_in_src, pi3dest_killed))
1047 /* Try to combine the insns I1 and I2 into I3.
1048 Here I1 and I2 appear earlier than I3.
1049 I1 can be zero; then we combine just I2 into I3.
1051 It we are combining three insns and the resulting insn is not recognized,
1052 try splitting it into two insns. If that happens, I2 and I3 are retained
1053 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1056 If we created two insns, return I2; otherwise return I3.
1057 Return 0 if the combination does not work. Then nothing is changed. */
1060 try_combine (i3, i2, i1)
1061 register rtx i3, i2, i1;
1063 /* New patterns for I3 and I3, respectively. */
1064 rtx newpat, newi2pat = 0;
1065 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1066 int added_sets_1, added_sets_2;
1067 /* Total number of SETs to put into I3. */
1069 /* Nonzero is I2's body now appears in I3. */
1071 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1072 int insn_code_number, i2_code_number, other_code_number;
1073 /* Contains I3 if the destination of I3 is used in its source, which means
1074 that the old life of I3 is being killed. If that usage is placed into
1075 I2 and not in I3, a REG_DEAD note must be made. */
1076 rtx i3dest_killed = 0;
1077 /* SET_DEST and SET_SRC of I2 and I1. */
1078 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1079 /* PATTERN (I2), or a copy of it in certain cases. */
1081 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1082 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1083 int i1_feeds_i3 = 0;
1084 /* Notes that must be added to REG_NOTES in I3 and I2. */
1085 rtx new_i3_notes, new_i2_notes;
1092 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1093 This can occur when flow deletes an insn that it has merged into an
1094 auto-increment address. We also can't do anything if I3 has a
1095 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1098 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1099 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1100 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1101 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1106 undobuf.num_undo = previous_num_undos = 0;
1107 undobuf.other_insn = 0;
1109 /* Save the current high-water-mark so we can free storage if we didn't
1110 accept this combination. */
1111 undobuf.storage = (char *) oballoc (0);
1113 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1114 code below, set I1 to be the earlier of the two insns. */
1115 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1116 temp = i1, i1 = i2, i2 = temp;
1118 /* First check for one important special-case that the code below will
1119 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1120 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1121 we may be able to replace that destination with the destination of I3.
1122 This occurs in the common code where we compute both a quotient and
1123 remainder into a structure, in which case we want to do the computation
1124 directly into the structure to avoid register-register copies.
1126 We make very conservative checks below and only try to handle the
1127 most common cases of this. For example, we only handle the case
1128 where I2 and I3 are adjacent to avoid making difficult register
1131 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1132 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1133 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1134 #ifdef SMALL_REGISTER_CLASSES
1135 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1136 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1138 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1139 && GET_CODE (PATTERN (i2)) == PARALLEL
1140 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1141 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1142 below would need to check what is inside (and reg_overlap_mentioned_p
1143 doesn't support those codes anyway). Don't allow those destinations;
1144 the resulting insn isn't likely to be recognized anyway. */
1145 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1146 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1147 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1148 SET_DEST (PATTERN (i3)))
1149 && next_real_insn (i2) == i3)
1151 rtx p2 = PATTERN (i2);
1153 /* Make sure that the destination of I3,
1154 which we are going to substitute into one output of I2,
1155 is not used within another output of I2. We must avoid making this:
1156 (parallel [(set (mem (reg 69)) ...)
1157 (set (reg 69) ...)])
1158 which is not well-defined as to order of actions.
1159 (Besides, reload can't handle output reloads for this.)
1161 The problem can also happen if the dest of I3 is a memory ref,
1162 if another dest in I2 is an indirect memory ref. */
1163 for (i = 0; i < XVECLEN (p2, 0); i++)
1164 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1165 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1166 SET_DEST (XVECEXP (p2, 0, i))))
1169 if (i == XVECLEN (p2, 0))
1170 for (i = 0; i < XVECLEN (p2, 0); i++)
1171 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1176 subst_low_cuid = INSN_CUID (i2);
1179 i2dest = SET_SRC (PATTERN (i3));
1181 /* Replace the dest in I2 with our dest and make the resulting
1182 insn the new pattern for I3. Then skip to where we
1183 validate the pattern. Everything was set up above. */
1184 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1185 SET_DEST (PATTERN (i3)));
1188 goto validate_replacement;
1193 /* If we have no I1 and I2 looks like:
1194 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1196 make up a dummy I1 that is
1199 (set (reg:CC X) (compare:CC Y (const_int 0)))
1201 (We can ignore any trailing CLOBBERs.)
1203 This undoes a previous combination and allows us to match a branch-and-
1206 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1207 && XVECLEN (PATTERN (i2), 0) >= 2
1208 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1209 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1211 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1212 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1213 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1214 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1215 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1216 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1218 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1219 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1224 /* We make I1 with the same INSN_UID as I2. This gives it
1225 the same INSN_CUID for value tracking. Our fake I1 will
1226 never appear in the insn stream so giving it the same INSN_UID
1227 as I2 will not cause a problem. */
1229 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1230 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1232 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1233 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1234 SET_DEST (PATTERN (i1)));
1239 /* Verify that I2 and I1 are valid for combining. */
1240 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1241 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1247 /* Record whether I2DEST is used in I2SRC and similarly for the other
1248 cases. Knowing this will help in register status updating below. */
1249 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1250 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1251 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1253 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1255 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1257 /* Ensure that I3's pattern can be the destination of combines. */
1258 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1259 i1 && i2dest_in_i1src && i1_feeds_i3,
1266 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1267 We used to do this EXCEPT in one case: I3 has a post-inc in an
1268 output operand. However, that exception can give rise to insns like
1270 which is a famous insn on the PDP-11 where the value of r3 used as the
1271 source was model-dependent. Avoid this sort of thing. */
1274 if (!(GET_CODE (PATTERN (i3)) == SET
1275 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1276 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1277 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1278 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1279 /* It's not the exception. */
1282 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1283 if (REG_NOTE_KIND (link) == REG_INC
1284 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1286 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1293 /* See if the SETs in I1 or I2 need to be kept around in the merged
1294 instruction: whenever the value set there is still needed past I3.
1295 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1297 For the SET in I1, we have two cases: If I1 and I2 independently
1298 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1299 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1300 in I1 needs to be kept around unless I1DEST dies or is set in either
1301 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1302 I1DEST. If so, we know I1 feeds into I2. */
1304 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1307 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1308 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1310 /* If the set in I2 needs to be kept around, we must make a copy of
1311 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1312 PATTERN (I2), we are only substituting for the original I1DEST, not into
1313 an already-substituted copy. This also prevents making self-referential
1314 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1317 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1318 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1322 i2pat = copy_rtx (i2pat);
1326 /* Substitute in the latest insn for the regs set by the earlier ones. */
1328 maxreg = max_reg_num ();
1332 /* It is possible that the source of I2 or I1 may be performing an
1333 unneeded operation, such as a ZERO_EXTEND of something that is known
1334 to have the high part zero. Handle that case by letting subst look at
1335 the innermost one of them.
1337 Another way to do this would be to have a function that tries to
1338 simplify a single insn instead of merging two or more insns. We don't
1339 do this because of the potential of infinite loops and because
1340 of the potential extra memory required. However, doing it the way
1341 we are is a bit of a kludge and doesn't catch all cases.
1343 But only do this if -fexpensive-optimizations since it slows things down
1344 and doesn't usually win. */
1346 if (flag_expensive_optimizations)
1348 /* Pass pc_rtx so no substitutions are done, just simplifications.
1349 The cases that we are interested in here do not involve the few
1350 cases were is_replaced is checked. */
1353 subst_low_cuid = INSN_CUID (i1);
1354 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1358 subst_low_cuid = INSN_CUID (i2);
1359 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1362 previous_num_undos = undobuf.num_undo;
1366 /* Many machines that don't use CC0 have insns that can both perform an
1367 arithmetic operation and set the condition code. These operations will
1368 be represented as a PARALLEL with the first element of the vector
1369 being a COMPARE of an arithmetic operation with the constant zero.
1370 The second element of the vector will set some pseudo to the result
1371 of the same arithmetic operation. If we simplify the COMPARE, we won't
1372 match such a pattern and so will generate an extra insn. Here we test
1373 for this case, where both the comparison and the operation result are
1374 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1375 I2SRC. Later we will make the PARALLEL that contains I2. */
1377 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1378 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1379 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1380 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1383 enum machine_mode compare_mode;
1385 newpat = PATTERN (i3);
1386 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1390 #ifdef EXTRA_CC_MODES
1391 /* See if a COMPARE with the operand we substituted in should be done
1392 with the mode that is currently being used. If not, do the same
1393 processing we do in `subst' for a SET; namely, if the destination
1394 is used only once, try to replace it with a register of the proper
1395 mode and also replace the COMPARE. */
1396 if (undobuf.other_insn == 0
1397 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1398 &undobuf.other_insn))
1399 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1401 != GET_MODE (SET_DEST (newpat))))
1403 int regno = REGNO (SET_DEST (newpat));
1404 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1406 if (regno < FIRST_PSEUDO_REGISTER
1407 || (reg_n_sets[regno] == 1 && ! added_sets_2
1408 && ! REG_USERVAR_P (SET_DEST (newpat))))
1410 if (regno >= FIRST_PSEUDO_REGISTER)
1411 SUBST (regno_reg_rtx[regno], new_dest);
1413 SUBST (SET_DEST (newpat), new_dest);
1414 SUBST (XEXP (*cc_use, 0), new_dest);
1415 SUBST (SET_SRC (newpat),
1416 gen_rtx_combine (COMPARE, compare_mode,
1417 i2src, const0_rtx));
1420 undobuf.other_insn = 0;
1427 n_occurrences = 0; /* `subst' counts here */
1429 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1430 need to make a unique copy of I2SRC each time we substitute it
1431 to avoid self-referential rtl. */
1433 subst_low_cuid = INSN_CUID (i2);
1434 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1435 ! i1_feeds_i3 && i1dest_in_i1src);
1436 previous_num_undos = undobuf.num_undo;
1438 /* Record whether i2's body now appears within i3's body. */
1439 i2_is_used = n_occurrences;
1442 /* If we already got a failure, don't try to do more. Otherwise,
1443 try to substitute in I1 if we have it. */
1445 if (i1 && GET_CODE (newpat) != CLOBBER)
1447 /* Before we can do this substitution, we must redo the test done
1448 above (see detailed comments there) that ensures that I1DEST
1449 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1451 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1459 subst_low_cuid = INSN_CUID (i1);
1460 newpat = subst (newpat, i1dest, i1src, 0, 0);
1461 previous_num_undos = undobuf.num_undo;
1464 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1465 to count all the ways that I2SRC and I1SRC can be used. */
1466 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1467 && i2_is_used + added_sets_2 > 1)
1468 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1469 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1471 /* Fail if we tried to make a new register (we used to abort, but there's
1472 really no reason to). */
1473 || max_reg_num () != maxreg
1474 /* Fail if we couldn't do something and have a CLOBBER. */
1475 || GET_CODE (newpat) == CLOBBER)
1481 /* If the actions of the earlier insns must be kept
1482 in addition to substituting them into the latest one,
1483 we must make a new PARALLEL for the latest insn
1484 to hold additional the SETs. */
1486 if (added_sets_1 || added_sets_2)
1490 if (GET_CODE (newpat) == PARALLEL)
1492 rtvec old = XVEC (newpat, 0);
1493 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1494 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1495 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1496 sizeof (old->elem[0]) * old->num_elem);
1501 total_sets = 1 + added_sets_1 + added_sets_2;
1502 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1503 XVECEXP (newpat, 0, 0) = old;
1507 XVECEXP (newpat, 0, --total_sets)
1508 = (GET_CODE (PATTERN (i1)) == PARALLEL
1509 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1513 /* If there is no I1, use I2's body as is. We used to also not do
1514 the subst call below if I2 was substituted into I3,
1515 but that could lose a simplification. */
1517 XVECEXP (newpat, 0, --total_sets) = i2pat;
1519 /* See comment where i2pat is assigned. */
1520 XVECEXP (newpat, 0, --total_sets)
1521 = subst (i2pat, i1dest, i1src, 0, 0);
1525 /* We come here when we are replacing a destination in I2 with the
1526 destination of I3. */
1527 validate_replacement:
1529 /* Is the result of combination a valid instruction? */
1530 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1532 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1533 the second SET's destination is a register that is unused. In that case,
1534 we just need the first SET. This can occur when simplifying a divmod
1535 insn. We *must* test for this case here because the code below that
1536 splits two independent SETs doesn't handle this case correctly when it
1537 updates the register status. Also check the case where the first
1538 SET's destination is unused. That would not cause incorrect code, but
1539 does cause an unneeded insn to remain. */
1541 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1542 && XVECLEN (newpat, 0) == 2
1543 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1544 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1545 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1546 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1547 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1548 && asm_noperands (newpat) < 0)
1550 newpat = XVECEXP (newpat, 0, 0);
1551 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1554 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1555 && XVECLEN (newpat, 0) == 2
1556 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1557 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1558 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1559 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1560 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1561 && asm_noperands (newpat) < 0)
1563 newpat = XVECEXP (newpat, 0, 1);
1564 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1567 /* See if this is an XOR. If so, perhaps the problem is that the
1568 constant is out of range. Replace it with a complemented XOR with
1569 a complemented constant; it might be in range. */
1571 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1572 && GET_CODE (SET_SRC (newpat)) == XOR
1573 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1574 && ((temp = simplify_unary_operation (NOT,
1575 GET_MODE (SET_SRC (newpat)),
1576 XEXP (SET_SRC (newpat), 1),
1577 GET_MODE (SET_SRC (newpat))))
1580 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1582 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1583 gen_unary (NOT, i_mode,
1584 gen_binary (XOR, i_mode,
1585 XEXP (SET_SRC (newpat), 0),
1588 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1589 if (insn_code_number >= 0)
1593 /* If we were combining three insns and the result is a simple SET
1594 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1595 insns. There are two ways to do this. It can be split using a
1596 machine-specific method (like when you have an addition of a large
1597 constant) or by combine in the function find_split_point. */
1599 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1600 && asm_noperands (newpat) < 0)
1602 rtx m_split, *split;
1603 rtx ni2dest = i2dest;
1605 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1606 use I2DEST as a scratch register will help. In the latter case,
1607 convert I2DEST to the mode of the source of NEWPAT if we can. */
1609 m_split = split_insns (newpat, i3);
1611 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1612 inputs of NEWPAT. */
1614 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1615 possible to try that as a scratch reg. This would require adding
1616 more code to make it work though. */
1618 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1620 /* If I2DEST is a hard register or the only use of a pseudo,
1621 we can change its mode. */
1622 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1623 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1624 && GET_CODE (i2dest) == REG
1625 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1626 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1627 && ! REG_USERVAR_P (i2dest))))
1628 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1631 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1632 gen_rtvec (2, newpat,
1639 if (m_split && GET_CODE (m_split) == SEQUENCE
1640 && XVECLEN (m_split, 0) == 2
1641 && (next_real_insn (i2) == i3
1642 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1646 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1647 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1649 i3set = single_set (XVECEXP (m_split, 0, 1));
1650 i2set = single_set (XVECEXP (m_split, 0, 0));
1652 /* In case we changed the mode of I2DEST, replace it in the
1653 pseudo-register table here. We can't do it above in case this
1654 code doesn't get executed and we do a split the other way. */
1656 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1657 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1659 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1661 /* If I2 or I3 has multiple SETs, we won't know how to track
1662 register status, so don't use these insns. */
1664 if (i2_code_number >= 0 && i2set && i3set)
1665 insn_code_number = recog_for_combine (&newi3pat, i3,
1668 if (insn_code_number >= 0)
1671 /* It is possible that both insns now set the destination of I3.
1672 If so, we must show an extra use of it. */
1674 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1675 && GET_CODE (SET_DEST (i2set)) == REG
1676 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1677 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1680 /* If we can split it and use I2DEST, go ahead and see if that
1681 helps things be recognized. Verify that none of the registers
1682 are set between I2 and I3. */
1683 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1685 && GET_CODE (i2dest) == REG
1687 /* We need I2DEST in the proper mode. If it is a hard register
1688 or the only use of a pseudo, we can change its mode. */
1689 && (GET_MODE (*split) == GET_MODE (i2dest)
1690 || GET_MODE (*split) == VOIDmode
1691 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1692 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1693 && ! REG_USERVAR_P (i2dest)))
1694 && (next_real_insn (i2) == i3
1695 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1696 /* We can't overwrite I2DEST if its value is still used by
1698 && ! reg_referenced_p (i2dest, newpat))
1700 rtx newdest = i2dest;
1702 /* Get NEWDEST as a register in the proper mode. We have already
1703 validated that we can do this. */
1704 if (GET_MODE (i2dest) != GET_MODE (*split)
1705 && GET_MODE (*split) != VOIDmode)
1707 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1709 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1710 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1713 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1714 an ASHIFT. This can occur if it was inside a PLUS and hence
1715 appeared to be a memory address. This is a kludge. */
1716 if (GET_CODE (*split) == MULT
1717 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1718 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1719 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1720 XEXP (*split, 0), GEN_INT (i)));
1722 #ifdef INSN_SCHEDULING
1723 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1724 be written as a ZERO_EXTEND. */
1725 if (GET_CODE (*split) == SUBREG
1726 && GET_CODE (SUBREG_REG (*split)) == MEM)
1727 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1731 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1732 SUBST (*split, newdest);
1733 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1734 if (i2_code_number >= 0)
1735 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1739 /* Check for a case where we loaded from memory in a narrow mode and
1740 then sign extended it, but we need both registers. In that case,
1741 we have a PARALLEL with both loads from the same memory location.
1742 We can split this into a load from memory followed by a register-register
1743 copy. This saves at least one insn, more if register allocation can
1744 eliminate the copy. */
1746 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1747 && GET_CODE (newpat) == PARALLEL
1748 && XVECLEN (newpat, 0) == 2
1749 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1750 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1751 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1752 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1753 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1754 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1756 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1757 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1758 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1759 SET_SRC (XVECEXP (newpat, 0, 1)))
1760 && ! find_reg_note (i3, REG_UNUSED,
1761 SET_DEST (XVECEXP (newpat, 0, 0))))
1765 newi2pat = XVECEXP (newpat, 0, 0);
1766 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1767 newpat = XVECEXP (newpat, 0, 1);
1768 SUBST (SET_SRC (newpat),
1769 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1770 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1771 if (i2_code_number >= 0)
1772 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1774 if (insn_code_number >= 0)
1779 /* If we will be able to accept this, we have made a change to the
1780 destination of I3. This can invalidate a LOG_LINKS pointing
1781 to I3. No other part of combine.c makes such a transformation.
1783 The new I3 will have a destination that was previously the
1784 destination of I1 or I2 and which was used in i2 or I3. Call
1785 distribute_links to make a LOG_LINK from the next use of
1786 that destination. */
1788 PATTERN (i3) = newpat;
1789 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1791 /* I3 now uses what used to be its destination and which is
1792 now I2's destination. That means we need a LOG_LINK from
1793 I3 to I2. But we used to have one, so we still will.
1795 However, some later insn might be using I2's dest and have
1796 a LOG_LINK pointing at I3. We must remove this link.
1797 The simplest way to remove the link is to point it at I1,
1798 which we know will be a NOTE. */
1800 for (insn = NEXT_INSN (i3);
1801 insn && GET_CODE (insn) != CODE_LABEL
1802 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1803 insn = NEXT_INSN (insn))
1805 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1806 && reg_referenced_p (ni2dest, PATTERN (insn)))
1808 for (link = LOG_LINKS (insn); link;
1809 link = XEXP (link, 1))
1810 if (XEXP (link, 0) == i3)
1811 XEXP (link, 0) = i1;
1819 /* Similarly, check for a case where we have a PARALLEL of two independent
1820 SETs but we started with three insns. In this case, we can do the sets
1821 as two separate insns. This case occurs when some SET allows two
1822 other insns to combine, but the destination of that SET is still live. */
1824 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1825 && GET_CODE (newpat) == PARALLEL
1826 && XVECLEN (newpat, 0) == 2
1827 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1828 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1829 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1830 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1831 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1832 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1833 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1835 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1836 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1837 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1838 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1839 XVECEXP (newpat, 0, 0))
1840 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1841 XVECEXP (newpat, 0, 1)))
1843 newi2pat = XVECEXP (newpat, 0, 1);
1844 newpat = XVECEXP (newpat, 0, 0);
1846 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1847 if (i2_code_number >= 0)
1848 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1851 /* If it still isn't recognized, fail and change things back the way they
1853 if ((insn_code_number < 0
1854 /* Is the result a reasonable ASM_OPERANDS? */
1855 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1861 /* If we had to change another insn, make sure it is valid also. */
1862 if (undobuf.other_insn)
1864 rtx other_notes = REG_NOTES (undobuf.other_insn);
1865 rtx other_pat = PATTERN (undobuf.other_insn);
1866 rtx new_other_notes;
1869 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1872 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1878 PATTERN (undobuf.other_insn) = other_pat;
1880 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1881 are still valid. Then add any non-duplicate notes added by
1882 recog_for_combine. */
1883 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1885 next = XEXP (note, 1);
1887 if (REG_NOTE_KIND (note) == REG_UNUSED
1888 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1890 if (GET_CODE (XEXP (note, 0)) == REG)
1891 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1893 remove_note (undobuf.other_insn, note);
1897 for (note = new_other_notes; note; note = XEXP (note, 1))
1898 if (GET_CODE (XEXP (note, 0)) == REG)
1899 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1901 distribute_notes (new_other_notes, undobuf.other_insn,
1902 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1905 /* We now know that we can do this combination. Merge the insns and
1906 update the status of registers and LOG_LINKS. */
1909 rtx i3notes, i2notes, i1notes = 0;
1910 rtx i3links, i2links, i1links = 0;
1912 int all_adjacent = (next_real_insn (i2) == i3
1913 && (i1 == 0 || next_real_insn (i1) == i2));
1915 /* Compute which registers we expect to eliminate. */
1916 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1918 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1920 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1922 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1923 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1925 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1927 /* Ensure that we do not have something that should not be shared but
1928 occurs multiple times in the new insns. Check this by first
1929 resetting all the `used' flags and then copying anything is shared. */
1931 reset_used_flags (i3notes);
1932 reset_used_flags (i2notes);
1933 reset_used_flags (i1notes);
1934 reset_used_flags (newpat);
1935 reset_used_flags (newi2pat);
1936 if (undobuf.other_insn)
1937 reset_used_flags (PATTERN (undobuf.other_insn));
1939 i3notes = copy_rtx_if_shared (i3notes);
1940 i2notes = copy_rtx_if_shared (i2notes);
1941 i1notes = copy_rtx_if_shared (i1notes);
1942 newpat = copy_rtx_if_shared (newpat);
1943 newi2pat = copy_rtx_if_shared (newi2pat);
1944 if (undobuf.other_insn)
1945 reset_used_flags (PATTERN (undobuf.other_insn));
1947 INSN_CODE (i3) = insn_code_number;
1948 PATTERN (i3) = newpat;
1949 if (undobuf.other_insn)
1950 INSN_CODE (undobuf.other_insn) = other_code_number;
1952 /* We had one special case above where I2 had more than one set and
1953 we replaced a destination of one of those sets with the destination
1954 of I3. In that case, we have to update LOG_LINKS of insns later
1955 in this basic block. Note that this (expensive) case is rare. */
1957 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1958 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1959 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1960 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1961 && ! find_reg_note (i2, REG_UNUSED,
1962 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1966 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1968 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1969 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1970 if (XEXP (link, 0) == i2)
1971 XEXP (link, 0) = i3;
1973 if (GET_CODE (insn) == CODE_LABEL
1974 || GET_CODE (insn) == JUMP_INSN)
1986 INSN_CODE (i2) = i2_code_number;
1987 PATTERN (i2) = newi2pat;
1991 PUT_CODE (i2, NOTE);
1992 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1993 NOTE_SOURCE_FILE (i2) = 0;
2000 PUT_CODE (i1, NOTE);
2001 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2002 NOTE_SOURCE_FILE (i1) = 0;
2005 /* Get death notes for everything that is now used in either I3 or
2006 I2 and used to die in a previous insn. */
2008 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2010 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2012 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2014 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2017 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2020 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2023 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2026 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2027 know these are REG_UNUSED and want them to go to the desired insn,
2028 so we always pass it as i3. We have not counted the notes in
2029 reg_n_deaths yet, so we need to do so now. */
2031 if (newi2pat && new_i2_notes)
2033 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2034 if (GET_CODE (XEXP (temp, 0)) == REG)
2035 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2037 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2042 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2043 if (GET_CODE (XEXP (temp, 0)) == REG)
2044 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2046 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2049 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2050 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2051 Show an additional death due to the REG_DEAD note we make here. If
2052 we discard it in distribute_notes, we will decrement it again. */
2056 if (GET_CODE (i3dest_killed) == REG)
2057 reg_n_deaths[REGNO (i3dest_killed)]++;
2059 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2061 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2062 NULL_RTX, NULL_RTX);
2065 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2066 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2067 we passed I3 in that case, it might delete I2. */
2069 if (i2dest_in_i2src)
2071 if (GET_CODE (i2dest) == REG)
2072 reg_n_deaths[REGNO (i2dest)]++;
2074 if (newi2pat && reg_set_p (i2dest, newi2pat))
2075 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2076 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2078 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2079 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2080 NULL_RTX, NULL_RTX);
2083 if (i1dest_in_i1src)
2085 if (GET_CODE (i1dest) == REG)
2086 reg_n_deaths[REGNO (i1dest)]++;
2088 if (newi2pat && reg_set_p (i1dest, newi2pat))
2089 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2090 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2092 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2093 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2094 NULL_RTX, NULL_RTX);
2097 distribute_links (i3links);
2098 distribute_links (i2links);
2099 distribute_links (i1links);
2101 if (GET_CODE (i2dest) == REG)
2104 rtx i2_insn = 0, i2_val = 0, set;
2106 /* The insn that used to set this register doesn't exist, and
2107 this life of the register may not exist either. See if one of
2108 I3's links points to an insn that sets I2DEST. If it does,
2109 that is now the last known value for I2DEST. If we don't update
2110 this and I2 set the register to a value that depended on its old
2111 contents, we will get confused. If this insn is used, thing
2112 will be set correctly in combine_instructions. */
2114 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2115 if ((set = single_set (XEXP (link, 0))) != 0
2116 && rtx_equal_p (i2dest, SET_DEST (set)))
2117 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2119 record_value_for_reg (i2dest, i2_insn, i2_val);
2121 /* If the reg formerly set in I2 died only once and that was in I3,
2122 zero its use count so it won't make `reload' do any work. */
2123 if (! added_sets_2 && newi2pat == 0)
2125 regno = REGNO (i2dest);
2126 reg_n_sets[regno]--;
2127 if (reg_n_sets[regno] == 0
2128 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2129 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2130 reg_n_refs[regno] = 0;
2134 if (i1 && GET_CODE (i1dest) == REG)
2137 rtx i1_insn = 0, i1_val = 0, set;
2139 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2140 if ((set = single_set (XEXP (link, 0))) != 0
2141 && rtx_equal_p (i1dest, SET_DEST (set)))
2142 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2144 record_value_for_reg (i1dest, i1_insn, i1_val);
2146 regno = REGNO (i1dest);
2149 reg_n_sets[regno]--;
2150 if (reg_n_sets[regno] == 0
2151 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2152 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2153 reg_n_refs[regno] = 0;
2157 /* Update reg_nonzero_bits et al for any changes that may have been made
2160 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2162 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2164 /* If I3 is now an unconditional jump, ensure that it has a
2165 BARRIER following it since it may have initially been a
2166 conditional jump. It may also be the last nonnote insn. */
2168 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2169 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2170 || GET_CODE (temp) != BARRIER))
2171 emit_barrier_after (i3);
2174 combine_successes++;
2176 return newi2pat ? i2 : i3;
2179 /* Undo all the modifications recorded in undobuf. */
2185 if (undobuf.num_undo > MAX_UNDO)
2186 undobuf.num_undo = MAX_UNDO;
2187 for (i = undobuf.num_undo - 1; i >= 0; i--)
2189 if (undobuf.undo[i].is_int)
2190 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2192 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2196 obfree (undobuf.storage);
2197 undobuf.num_undo = 0;
2200 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2201 where we have an arithmetic expression and return that point. LOC will
2204 try_combine will call this function to see if an insn can be split into
2208 find_split_point (loc, insn)
2213 enum rtx_code code = GET_CODE (x);
2215 int len = 0, pos, unsignedp;
2218 /* First special-case some codes. */
2222 #ifdef INSN_SCHEDULING
2223 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2225 if (GET_CODE (SUBREG_REG (x)) == MEM)
2228 return find_split_point (&SUBREG_REG (x), insn);
2232 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2233 using LO_SUM and HIGH. */
2234 if (GET_CODE (XEXP (x, 0)) == CONST
2235 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2238 gen_rtx_combine (LO_SUM, Pmode,
2239 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2241 return &XEXP (XEXP (x, 0), 0);
2245 /* If we have a PLUS whose second operand is a constant and the
2246 address is not valid, perhaps will can split it up using
2247 the machine-specific way to split large constants. We use
2248 the first psuedo-reg (one of the virtual regs) as a placeholder;
2249 it will not remain in the result. */
2250 if (GET_CODE (XEXP (x, 0)) == PLUS
2251 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2252 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2254 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2255 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2258 /* This should have produced two insns, each of which sets our
2259 placeholder. If the source of the second is a valid address,
2260 we can make put both sources together and make a split point
2263 if (seq && XVECLEN (seq, 0) == 2
2264 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2265 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2266 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2267 && ! reg_mentioned_p (reg,
2268 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2269 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2270 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2271 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2272 && memory_address_p (GET_MODE (x),
2273 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2275 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2276 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2278 /* Replace the placeholder in SRC2 with SRC1. If we can
2279 find where in SRC2 it was placed, that can become our
2280 split point and we can replace this address with SRC2.
2281 Just try two obvious places. */
2283 src2 = replace_rtx (src2, reg, src1);
2285 if (XEXP (src2, 0) == src1)
2286 split = &XEXP (src2, 0);
2287 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2288 && XEXP (XEXP (src2, 0), 0) == src1)
2289 split = &XEXP (XEXP (src2, 0), 0);
2293 SUBST (XEXP (x, 0), src2);
2298 /* If that didn't work, perhaps the first operand is complex and
2299 needs to be computed separately, so make a split point there.
2300 This will occur on machines that just support REG + CONST
2301 and have a constant moved through some previous computation. */
2303 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2304 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2305 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2307 return &XEXP (XEXP (x, 0), 0);
2313 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2314 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2315 we need to put the operand into a register. So split at that
2318 if (SET_DEST (x) == cc0_rtx
2319 && GET_CODE (SET_SRC (x)) != COMPARE
2320 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2321 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2322 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2323 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2324 return &SET_SRC (x);
2327 /* See if we can split SET_SRC as it stands. */
2328 split = find_split_point (&SET_SRC (x), insn);
2329 if (split && split != &SET_SRC (x))
2332 /* See if this is a bitfield assignment with everything constant. If
2333 so, this is an IOR of an AND, so split it into that. */
2334 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2335 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2336 <= HOST_BITS_PER_WIDE_INT)
2337 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2338 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2339 && GET_CODE (SET_SRC (x)) == CONST_INT
2340 && ((INTVAL (XEXP (SET_DEST (x), 1))
2341 + INTVAL (XEXP (SET_DEST (x), 2)))
2342 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2343 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2345 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2346 int len = INTVAL (XEXP (SET_DEST (x), 1));
2347 int src = INTVAL (SET_SRC (x));
2348 rtx dest = XEXP (SET_DEST (x), 0);
2349 enum machine_mode mode = GET_MODE (dest);
2350 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2353 pos = GET_MODE_BITSIZE (mode) - len - pos;
2358 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2361 gen_binary (IOR, mode,
2362 gen_binary (AND, mode, dest,
2363 GEN_INT (~ (mask << pos)
2364 & GET_MODE_MASK (mode))),
2365 GEN_INT (src << pos)));
2367 SUBST (SET_DEST (x), dest);
2369 split = find_split_point (&SET_SRC (x), insn);
2370 if (split && split != &SET_SRC (x))
2374 /* Otherwise, see if this is an operation that we can split into two.
2375 If so, try to split that. */
2376 code = GET_CODE (SET_SRC (x));
2381 /* If we are AND'ing with a large constant that is only a single
2382 bit and the result is only being used in a context where we
2383 need to know if it is zero or non-zero, replace it with a bit
2384 extraction. This will avoid the large constant, which might
2385 have taken more than one insn to make. If the constant were
2386 not a valid argument to the AND but took only one insn to make,
2387 this is no worse, but if it took more than one insn, it will
2390 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2391 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2392 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2393 && GET_CODE (SET_DEST (x)) == REG
2394 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2395 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2396 && XEXP (*split, 0) == SET_DEST (x)
2397 && XEXP (*split, 1) == const0_rtx)
2400 make_extraction (GET_MODE (SET_DEST (x)),
2401 XEXP (SET_SRC (x), 0),
2402 pos, NULL_RTX, 1, 1, 0, 0));
2403 return find_split_point (loc, insn);
2408 inner = XEXP (SET_SRC (x), 0);
2410 len = GET_MODE_BITSIZE (GET_MODE (inner));
2416 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2417 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2419 inner = XEXP (SET_SRC (x), 0);
2420 len = INTVAL (XEXP (SET_SRC (x), 1));
2421 pos = INTVAL (XEXP (SET_SRC (x), 2));
2424 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2426 unsignedp = (code == ZERO_EXTRACT);
2431 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2433 enum machine_mode mode = GET_MODE (SET_SRC (x));
2435 /* For unsigned, we have a choice of a shift followed by an
2436 AND or two shifts. Use two shifts for field sizes where the
2437 constant might be too large. We assume here that we can
2438 always at least get 8-bit constants in an AND insn, which is
2439 true for every current RISC. */
2441 if (unsignedp && len <= 8)
2446 gen_rtx_combine (LSHIFTRT, mode,
2447 gen_lowpart_for_combine (mode, inner),
2449 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2451 split = find_split_point (&SET_SRC (x), insn);
2452 if (split && split != &SET_SRC (x))
2459 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2460 gen_rtx_combine (ASHIFT, mode,
2461 gen_lowpart_for_combine (mode, inner),
2462 GEN_INT (GET_MODE_BITSIZE (mode)
2464 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2466 split = find_split_point (&SET_SRC (x), insn);
2467 if (split && split != &SET_SRC (x))
2472 /* See if this is a simple operation with a constant as the second
2473 operand. It might be that this constant is out of range and hence
2474 could be used as a split point. */
2475 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2476 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2477 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2478 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2479 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2480 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2481 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2483 return &XEXP (SET_SRC (x), 1);
2485 /* Finally, see if this is a simple operation with its first operand
2486 not in a register. The operation might require this operand in a
2487 register, so return it as a split point. We can always do this
2488 because if the first operand were another operation, we would have
2489 already found it as a split point. */
2490 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2491 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2492 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2493 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2494 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2495 return &XEXP (SET_SRC (x), 0);
2501 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2502 it is better to write this as (not (ior A B)) so we can split it.
2503 Similarly for IOR. */
2504 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2507 gen_rtx_combine (NOT, GET_MODE (x),
2508 gen_rtx_combine (code == IOR ? AND : IOR,
2510 XEXP (XEXP (x, 0), 0),
2511 XEXP (XEXP (x, 1), 0))));
2512 return find_split_point (loc, insn);
2515 /* Many RISC machines have a large set of logical insns. If the
2516 second operand is a NOT, put it first so we will try to split the
2517 other operand first. */
2518 if (GET_CODE (XEXP (x, 1)) == NOT)
2520 rtx tem = XEXP (x, 0);
2521 SUBST (XEXP (x, 0), XEXP (x, 1));
2522 SUBST (XEXP (x, 1), tem);
2527 /* Otherwise, select our actions depending on our rtx class. */
2528 switch (GET_RTX_CLASS (code))
2530 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2532 split = find_split_point (&XEXP (x, 2), insn);
2535 /* ... fall through ... */
2539 split = find_split_point (&XEXP (x, 1), insn);
2542 /* ... fall through ... */
2544 /* Some machines have (and (shift ...) ...) insns. If X is not
2545 an AND, but XEXP (X, 0) is, use it as our split point. */
2546 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2547 return &XEXP (x, 0);
2549 split = find_split_point (&XEXP (x, 0), insn);
2555 /* Otherwise, we don't have a split point. */
2559 /* Throughout X, replace FROM with TO, and return the result.
2560 The result is TO if X is FROM;
2561 otherwise the result is X, but its contents may have been modified.
2562 If they were modified, a record was made in undobuf so that
2563 undo_all will (among other things) return X to its original state.
2565 If the number of changes necessary is too much to record to undo,
2566 the excess changes are not made, so the result is invalid.
2567 The changes already made can still be undone.
2568 undobuf.num_undo is incremented for such changes, so by testing that
2569 the caller can tell whether the result is valid.
2571 `n_occurrences' is incremented each time FROM is replaced.
2573 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2575 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2576 by copying if `n_occurrences' is non-zero. */
2579 subst (x, from, to, in_dest, unique_copy)
2580 register rtx x, from, to;
2585 register int len, i;
2586 register enum rtx_code code = GET_CODE (x), orig_code = code;
2588 enum machine_mode mode = GET_MODE (x);
2589 enum machine_mode op0_mode = VOIDmode;
2594 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2595 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2596 If it is 0, that cannot be done. We can now do this for any MEM
2597 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2598 If not for that, MEM's would very rarely be safe. */
2600 /* Reject MODEs bigger than a word, because we might not be able
2601 to reference a two-register group starting with an arbitrary register
2602 (and currently gen_lowpart might crash for a SUBREG). */
2604 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2605 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2607 /* Two expressions are equal if they are identical copies of a shared
2608 RTX or if they are both registers with the same register number
2611 #define COMBINE_RTX_EQUAL_P(X,Y) \
2613 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2614 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2616 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2619 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2622 /* If X and FROM are the same register but different modes, they will
2623 not have been seen as equal above. However, flow.c will make a
2624 LOG_LINKS entry for that case. If we do nothing, we will try to
2625 rerecognize our original insn and, when it succeeds, we will
2626 delete the feeding insn, which is incorrect.
2628 So force this insn not to match in this (rare) case. */
2629 if (! in_dest && code == REG && GET_CODE (from) == REG
2630 && REGNO (x) == REGNO (from))
2631 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2633 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2634 of which may contain things that can be combined. */
2635 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2638 /* It is possible to have a subexpression appear twice in the insn.
2639 Suppose that FROM is a register that appears within TO.
2640 Then, after that subexpression has been scanned once by `subst',
2641 the second time it is scanned, TO may be found. If we were
2642 to scan TO here, we would find FROM within it and create a
2643 self-referent rtl structure which is completely wrong. */
2644 if (COMBINE_RTX_EQUAL_P (x, to))
2647 len = GET_RTX_LENGTH (code);
2648 fmt = GET_RTX_FORMAT (code);
2650 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2651 set up to skip this common case. All other cases where we want to
2652 suppress replacing something inside a SET_SRC are handled via the
2655 && (GET_CODE (SET_DEST (x)) == REG
2656 || GET_CODE (SET_DEST (x)) == CC0
2657 || GET_CODE (SET_DEST (x)) == PC))
2660 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2662 op0_mode = GET_MODE (XEXP (x, 0));
2664 for (i = 0; i < len; i++)
2669 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2672 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2674 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2679 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2681 /* If this substitution failed, this whole thing fails. */
2682 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2686 SUBST (XVECEXP (x, i, j), new);
2689 else if (fmt[i] == 'e')
2693 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2695 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2699 /* If we are in a SET_DEST, suppress most cases unless we
2700 have gone inside a MEM, in which case we want to
2701 simplify the address. We assume here that things that
2702 are actually part of the destination have their inner
2703 parts in the first expression. This is true for SUBREG,
2704 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2705 things aside from REG and MEM that should appear in a
2707 new = subst (XEXP (x, i), from, to,
2709 && (code == SUBREG || code == STRICT_LOW_PART
2710 || code == ZERO_EXTRACT))
2712 && i == 0), unique_copy);
2714 /* If we found that we will have to reject this combination,
2715 indicate that by returning the CLOBBER ourselves, rather than
2716 an expression containing it. This will speed things up as
2717 well as prevent accidents where two CLOBBERs are considered
2718 to be equal, thus producing an incorrect simplification. */
2720 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2723 SUBST (XEXP (x, i), new);
2727 /* We come back to here if we have replaced the expression with one of
2728 a different code and it is likely that further simplification will be
2733 /* If we have restarted more than 4 times, we are probably looping, so
2735 if (++n_restarts > 4)
2738 /* If we are restarting at all, it means that we no longer know the
2739 original mode of operand 0 (since we have probably changed the
2743 op0_mode = VOIDmode;
2745 code = GET_CODE (x);
2747 /* If this is a commutative operation, put a constant last and a complex
2748 expression first. We don't need to do this for comparisons here. */
2749 if (GET_RTX_CLASS (code) == 'c'
2750 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2751 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2752 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2753 || (GET_CODE (XEXP (x, 0)) == SUBREG
2754 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2755 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2758 SUBST (XEXP (x, 0), XEXP (x, 1));
2759 SUBST (XEXP (x, 1), temp);
2762 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2763 sign extension of a PLUS with a constant, reverse the order of the sign
2764 extension and the addition. Note that this not the same as the original
2765 code, but overflow is undefined for signed values. Also note that the
2766 PLUS will have been partially moved "inside" the sign-extension, so that
2767 the first operand of X will really look like:
2768 (ashiftrt (plus (ashift A C4) C5) C4).
2770 (plus (ashiftrt (ashift A C4) C2) C4)
2771 and replace the first operand of X with that expression. Later parts
2772 of this function may simplify the expression further.
2774 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2775 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2776 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2778 We do this to simplify address expressions. */
2780 if ((code == PLUS || code == MINUS || code == MULT)
2781 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2782 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2783 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2784 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2785 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2786 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2787 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2788 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2789 XEXP (XEXP (XEXP (x, 0), 0), 1),
2790 XEXP (XEXP (x, 0), 1))) != 0)
2793 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2794 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2795 INTVAL (XEXP (XEXP (x, 0), 1)));
2797 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2798 INTVAL (XEXP (XEXP (x, 0), 1)));
2800 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2803 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2804 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2805 things. Don't deal with operations that change modes here. */
2807 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2808 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2810 /* Don't do this by using SUBST inside X since we might be messing
2811 up a shared expression. */
2812 rtx cond = XEXP (XEXP (x, 0), 0);
2813 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2815 pc_rtx, pc_rtx, 0, 0);
2816 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2818 pc_rtx, pc_rtx, 0, 0);
2821 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2825 else if (GET_RTX_CLASS (code) == '1'
2826 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2827 && GET_MODE (XEXP (x, 0)) == mode)
2829 rtx cond = XEXP (XEXP (x, 0), 0);
2830 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2831 pc_rtx, pc_rtx, 0, 0);
2832 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2833 pc_rtx, pc_rtx, 0, 0);
2835 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2839 /* Try to fold this expression in case we have constants that weren't
2842 switch (GET_RTX_CLASS (code))
2845 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2848 temp = simplify_relational_operation (code, op0_mode,
2849 XEXP (x, 0), XEXP (x, 1));
2850 #ifdef FLOAT_STORE_FLAG_VALUE
2851 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2852 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2853 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2858 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2862 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2863 XEXP (x, 1), XEXP (x, 2));
2868 x = temp, code = GET_CODE (temp);
2870 /* First see if we can apply the inverse distributive law. */
2871 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2873 x = apply_distributive_law (x);
2874 code = GET_CODE (x);
2877 /* If CODE is an associative operation not otherwise handled, see if we
2878 can associate some operands. This can win if they are constants or
2879 if they are logically related (i.e. (a & b) & a. */
2880 if ((code == PLUS || code == MINUS
2881 || code == MULT || code == AND || code == IOR || code == XOR
2882 || code == DIV || code == UDIV
2883 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2884 && GET_MODE_CLASS (mode) == MODE_INT)
2886 if (GET_CODE (XEXP (x, 0)) == code)
2888 rtx other = XEXP (XEXP (x, 0), 0);
2889 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2890 rtx inner_op1 = XEXP (x, 1);
2893 /* Make sure we pass the constant operand if any as the second
2894 one if this is a commutative operation. */
2895 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2897 rtx tem = inner_op0;
2898 inner_op0 = inner_op1;
2901 inner = simplify_binary_operation (code == MINUS ? PLUS
2902 : code == DIV ? MULT
2903 : code == UDIV ? MULT
2905 mode, inner_op0, inner_op1);
2907 /* For commutative operations, try the other pair if that one
2909 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2911 other = XEXP (XEXP (x, 0), 1);
2912 inner = simplify_binary_operation (code, mode,
2913 XEXP (XEXP (x, 0), 0),
2919 x = gen_binary (code, mode, other, inner);
2926 /* A little bit of algebraic simplification here. */
2930 /* Ensure that our address has any ASHIFTs converted to MULT in case
2931 address-recognizing predicates are called later. */
2932 temp = make_compound_operation (XEXP (x, 0), MEM);
2933 SUBST (XEXP (x, 0), temp);
2937 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2938 is paradoxical. If we can't do that safely, then it becomes
2939 something nonsensical so that this combination won't take place. */
2941 if (GET_CODE (SUBREG_REG (x)) == MEM
2942 && (GET_MODE_SIZE (mode)
2943 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2945 rtx inner = SUBREG_REG (x);
2946 int endian_offset = 0;
2947 /* Don't change the mode of the MEM
2948 if that would change the meaning of the address. */
2949 if (MEM_VOLATILE_P (SUBREG_REG (x))
2950 || mode_dependent_address_p (XEXP (inner, 0)))
2951 return gen_rtx (CLOBBER, mode, const0_rtx);
2953 #if BYTES_BIG_ENDIAN
2954 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2955 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2956 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2957 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2959 /* Note if the plus_constant doesn't make a valid address
2960 then this combination won't be accepted. */
2961 x = gen_rtx (MEM, mode,
2962 plus_constant (XEXP (inner, 0),
2963 (SUBREG_WORD (x) * UNITS_PER_WORD
2965 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2966 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2967 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2971 /* If we are in a SET_DEST, these other cases can't apply. */
2975 /* Changing mode twice with SUBREG => just change it once,
2976 or not at all if changing back to starting mode. */
2977 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2979 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2980 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2981 return SUBREG_REG (SUBREG_REG (x));
2983 SUBST_INT (SUBREG_WORD (x),
2984 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2985 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2988 /* SUBREG of a hard register => just change the register number
2989 and/or mode. If the hard register is not valid in that mode,
2990 suppress this combination. If the hard register is the stack,
2991 frame, or argument pointer, leave this as a SUBREG. */
2993 if (GET_CODE (SUBREG_REG (x)) == REG
2994 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
2995 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
2996 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2997 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
2999 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3001 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3003 return gen_rtx (REG, mode,
3004 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3006 return gen_rtx (CLOBBER, mode, const0_rtx);
3009 /* For a constant, try to pick up the part we want. Handle a full
3010 word and low-order part. Only do this if we are narrowing
3011 the constant; if it is being widened, we have no idea what
3012 the extra bits will have been set to. */
3014 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3015 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3016 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3017 && GET_MODE_CLASS (mode) == MODE_INT)
3019 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3025 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3026 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
3027 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3029 /* If we are narrowing the object, we need to see if we can simplify
3030 the expression for the object knowing that we only need the
3033 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3034 && subreg_lowpart_p (x))
3035 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
3040 /* (not (plus X -1)) can become (neg X). */
3041 if (GET_CODE (XEXP (x, 0)) == PLUS
3042 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3044 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3048 /* Similarly, (not (neg X)) is (plus X -1). */
3049 if (GET_CODE (XEXP (x, 0)) == NEG)
3051 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3055 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3056 if (GET_CODE (XEXP (x, 0)) == XOR
3057 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3058 && (temp = simplify_unary_operation (NOT, mode,
3059 XEXP (XEXP (x, 0), 1),
3062 SUBST (XEXP (XEXP (x, 0), 1), temp);
3066 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3067 other than 1, but that is not valid. We could do a similar
3068 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3069 but this doesn't seem common enough to bother with. */
3070 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3071 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3073 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3074 XEXP (XEXP (x, 0), 1));
3078 if (GET_CODE (XEXP (x, 0)) == SUBREG
3079 && subreg_lowpart_p (XEXP (x, 0))
3080 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3081 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3082 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3083 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3085 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3087 x = gen_rtx (ROTATE, inner_mode,
3088 gen_unary (NOT, inner_mode, const1_rtx),
3089 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3090 x = gen_lowpart_for_combine (mode, x);
3094 #if STORE_FLAG_VALUE == -1
3095 /* (not (comparison foo bar)) can be done by reversing the comparison
3097 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3098 && reversible_comparison_p (XEXP (x, 0)))
3099 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3100 mode, XEXP (XEXP (x, 0), 0),
3101 XEXP (XEXP (x, 0), 1));
3104 /* Apply De Morgan's laws to reduce number of patterns for machines
3105 with negating logical insns (and-not, nand, etc.). If result has
3106 only one NOT, put it first, since that is how the patterns are
3109 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3111 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3113 if (GET_CODE (in1) == NOT)
3114 in1 = XEXP (in1, 0);
3116 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3118 if (GET_CODE (in2) == NOT)
3119 in2 = XEXP (in2, 0);
3120 else if (GET_CODE (in2) == CONST_INT
3121 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3122 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3124 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3126 if (GET_CODE (in2) == NOT)
3129 in2 = in1; in1 = tem;
3132 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3139 /* (neg (plus X 1)) can become (not X). */
3140 if (GET_CODE (XEXP (x, 0)) == PLUS
3141 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3143 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3147 /* Similarly, (neg (not X)) is (plus X 1). */
3148 if (GET_CODE (XEXP (x, 0)) == NOT)
3150 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3154 /* (neg (minus X Y)) can become (minus Y X). */
3155 if (GET_CODE (XEXP (x, 0)) == MINUS
3156 && (GET_MODE_CLASS (mode) != MODE_FLOAT
3157 /* x-y != -(y-x) with IEEE floating point. */
3158 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3160 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3161 XEXP (XEXP (x, 0), 0));
3165 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3166 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3167 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3169 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3173 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3174 if we can then eliminate the NEG (e.g.,
3175 if the operand is a constant). */
3177 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3179 temp = simplify_unary_operation (NEG, mode,
3180 XEXP (XEXP (x, 0), 0), mode);
3183 SUBST (XEXP (XEXP (x, 0), 0), temp);
3188 temp = expand_compound_operation (XEXP (x, 0));
3190 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3191 replaced by (lshiftrt X C). This will convert
3192 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3194 if (GET_CODE (temp) == ASHIFTRT
3195 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3196 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3198 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3199 INTVAL (XEXP (temp, 1)));
3203 /* If X has only a single bit that might be nonzero, say, bit I, convert
3204 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3205 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3206 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3207 or a SUBREG of one since we'd be making the expression more
3208 complex if it was just a register. */
3210 if (GET_CODE (temp) != REG
3211 && ! (GET_CODE (temp) == SUBREG
3212 && GET_CODE (SUBREG_REG (temp)) == REG)
3213 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3215 rtx temp1 = simplify_shift_const
3216 (NULL_RTX, ASHIFTRT, mode,
3217 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3218 GET_MODE_BITSIZE (mode) - 1 - i),
3219 GET_MODE_BITSIZE (mode) - 1 - i);
3221 /* If all we did was surround TEMP with the two shifts, we
3222 haven't improved anything, so don't use it. Otherwise,
3223 we are better off with TEMP1. */
3224 if (GET_CODE (temp1) != ASHIFTRT
3225 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3226 || XEXP (XEXP (temp1, 0), 0) != temp)
3234 case FLOAT_TRUNCATE:
3235 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3236 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3237 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3238 return XEXP (XEXP (x, 0), 0);
3243 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3244 using cc0, in which case we want to leave it as a COMPARE
3245 so we can distinguish it from a register-register-copy. */
3246 if (XEXP (x, 1) == const0_rtx)
3249 /* In IEEE floating point, x-0 is not the same as x. */
3250 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3251 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3252 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3258 /* (const (const X)) can become (const X). Do it this way rather than
3259 returning the inner CONST since CONST can be shared with a
3261 if (GET_CODE (XEXP (x, 0)) == CONST)
3262 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3267 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3268 can add in an offset. find_split_point will split this address up
3269 again if it doesn't match. */
3270 if (GET_CODE (XEXP (x, 0)) == HIGH
3271 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3277 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3278 outermost. That's because that's the way indexed addresses are
3279 supposed to appear. This code used to check many more cases, but
3280 they are now checked elsewhere. */
3281 if (GET_CODE (XEXP (x, 0)) == PLUS
3282 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3283 return gen_binary (PLUS, mode,
3284 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3286 XEXP (XEXP (x, 0), 1));
3288 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3289 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3290 bit-field and can be replaced by either a sign_extend or a
3291 sign_extract. The `and' may be a zero_extend. */
3292 if (GET_CODE (XEXP (x, 0)) == XOR
3293 && GET_CODE (XEXP (x, 1)) == CONST_INT
3294 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3295 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3296 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3297 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3298 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3299 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3300 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3301 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3302 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3303 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3306 x = simplify_shift_const
3307 (NULL_RTX, ASHIFTRT, mode,
3308 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3309 XEXP (XEXP (XEXP (x, 0), 0), 0),
3310 GET_MODE_BITSIZE (mode) - (i + 1)),
3311 GET_MODE_BITSIZE (mode) - (i + 1));
3315 /* If only the low-order bit of X is possible nonzero, (plus x -1)
3316 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3317 the bitsize of the mode - 1. This allows simplification of
3318 "a = (b & 8) == 0;" */
3319 if (XEXP (x, 1) == constm1_rtx
3320 && GET_CODE (XEXP (x, 0)) != REG
3321 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3322 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3323 && nonzero_bits (XEXP (x, 0), mode) == 1)
3325 x = simplify_shift_const
3326 (NULL_RTX, ASHIFTRT, mode,
3327 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3328 gen_rtx_combine (XOR, mode,
3329 XEXP (x, 0), const1_rtx),
3330 GET_MODE_BITSIZE (mode) - 1),
3331 GET_MODE_BITSIZE (mode) - 1);
3335 /* If we are adding two things that have no bits in common, convert
3336 the addition into an IOR. This will often be further simplified,
3337 for example in cases like ((a & 1) + (a & 2)), which can
3340 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3341 && (nonzero_bits (XEXP (x, 0), mode)
3342 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3344 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3350 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3351 (and <foo> (const_int pow2-1)) */
3352 if (GET_CODE (XEXP (x, 1)) == AND
3353 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3354 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3355 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3357 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3358 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3364 /* If we have (mult (plus A B) C), apply the distributive law and then
3365 the inverse distributive law to see if things simplify. This
3366 occurs mostly in addresses, often when unrolling loops. */
3368 if (GET_CODE (XEXP (x, 0)) == PLUS)
3370 x = apply_distributive_law
3371 (gen_binary (PLUS, mode,
3372 gen_binary (MULT, mode,
3373 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3374 gen_binary (MULT, mode,
3375 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3377 if (GET_CODE (x) != MULT)
3381 /* If this is multiplication by a power of two and its first operand is
3382 a shift, treat the multiply as a shift to allow the shifts to
3383 possibly combine. */
3384 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3385 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3386 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3387 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3388 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3389 || GET_CODE (XEXP (x, 0)) == ROTATE
3390 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3392 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3396 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3397 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3398 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3399 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3400 XEXP (XEXP (x, 0), 1));
3404 /* If this is a divide by a power of two, treat it as a shift if
3405 its first operand is a shift. */
3406 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3407 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3408 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3409 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3410 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3411 || GET_CODE (XEXP (x, 0)) == ROTATE
3412 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3414 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3420 case GT: case GTU: case GE: case GEU:
3421 case LT: case LTU: case LE: case LEU:
3422 /* If the first operand is a condition code, we can't do anything
3424 if (GET_CODE (XEXP (x, 0)) == COMPARE
3425 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3427 && XEXP (x, 0) != cc0_rtx
3431 rtx op0 = XEXP (x, 0);
3432 rtx op1 = XEXP (x, 1);
3433 enum rtx_code new_code;
3435 if (GET_CODE (op0) == COMPARE)
3436 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3438 /* Simplify our comparison, if possible. */
3439 new_code = simplify_comparison (code, &op0, &op1);
3441 #if STORE_FLAG_VALUE == 1
3442 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3443 if only the low-order bit is possibly nonzero in X (such as when
3444 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3445 EQ to (xor X 1). Remove any ZERO_EXTRACT we made when thinking
3446 this was a comparison. It may now be simpler to use, e.g., an
3447 AND. If a ZERO_EXTRACT is indeed appropriate, it will
3448 be placed back by the call to make_compound_operation in the
3450 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3451 && op1 == const0_rtx
3452 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3453 return gen_lowpart_for_combine (mode,
3454 expand_compound_operation (op0));
3455 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3456 && op1 == const0_rtx
3457 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3459 op0 = expand_compound_operation (op0);
3461 x = gen_rtx_combine (XOR, mode,
3462 gen_lowpart_for_combine (mode, op0),
3468 #if STORE_FLAG_VALUE == -1
3469 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3470 to (neg x) if only the low-order bit of X can be nonzero.
3471 This converts (ne (zero_extract X 1 Y) 0) to
3472 (sign_extract X 1 Y). */
3473 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3474 && op1 == const0_rtx
3475 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3477 op0 = expand_compound_operation (op0);
3478 x = gen_rtx_combine (NEG, mode,
3479 gen_lowpart_for_combine (mode, op0));
3484 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3485 one bit that might be nonzero, we can convert (ne x 0) to
3486 (ashift x c) where C puts the bit in the sign bit. Remove any
3487 AND with STORE_FLAG_VALUE when we are done, since we are only
3488 going to test the sign bit. */
3489 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3490 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3491 && (STORE_FLAG_VALUE
3492 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3493 && op1 == const0_rtx
3494 && mode == GET_MODE (op0)
3495 && (i = exact_log2 (nonzero_bits (op0, GET_MODE (op0)))) >= 0)
3497 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3498 expand_compound_operation (op0),
3499 GET_MODE_BITSIZE (mode) - 1 - i);
3500 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3506 /* If the code changed, return a whole new comparison. */
3507 if (new_code != code)
3508 return gen_rtx_combine (new_code, mode, op0, op1);
3510 /* Otherwise, keep this operation, but maybe change its operands.
3511 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3512 SUBST (XEXP (x, 0), op0);
3513 SUBST (XEXP (x, 1), op1);
3518 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3519 used in it is being compared against certain values. Get the
3520 true and false comparisons and see if that says anything about the
3521 value of each arm. */
3523 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3524 && reversible_comparison_p (XEXP (x, 0))
3525 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3528 rtx from = XEXP (XEXP (x, 0), 0);
3529 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3530 enum rtx_code false_code = reverse_condition (true_code);
3531 rtx true_val = XEXP (XEXP (x, 0), 1);
3532 rtx false_val = true_val;
3533 rtx true_arm = XEXP (x, 1);
3534 rtx false_arm = XEXP (x, 2);
3537 /* If FALSE_CODE is EQ, swap the codes and arms. */
3539 if (false_code == EQ)
3541 swapped = 1, true_code = EQ, false_code = NE;
3542 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3545 /* If we are comparing against zero and the expression being tested
3546 has only a single bit that might be nonzero, that is its value
3547 when it is not equal to zero. Similarly if it is known to be
3550 if (true_code == EQ && true_val == const0_rtx
3551 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3552 false_code = EQ, false_val = GEN_INT (nzb);
3553 else if (true_code == EQ && true_val == const0_rtx
3554 && (num_sign_bit_copies (from, GET_MODE (from))
3555 == GET_MODE_BITSIZE (GET_MODE (from))))
3556 false_code = EQ, false_val = constm1_rtx;
3558 /* Now simplify an arm if we know the value of the register
3559 in the branch and it is used in the arm. Be carefull due to
3560 the potential of locally-shared RTL. */
3562 if (reg_mentioned_p (from, true_arm))
3563 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3565 pc_rtx, pc_rtx, 0, 0);
3566 if (reg_mentioned_p (from, false_arm))
3567 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3569 pc_rtx, pc_rtx, 0, 0);
3571 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3572 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3575 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3576 reversed, do so to avoid needing two sets of patterns for
3577 subtract-and-branch insns. Similarly if we have a constant in that
3578 position or if the third operand is the same as the first operand
3579 of the comparison. */
3581 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3582 && reversible_comparison_p (XEXP (x, 0))
3583 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3584 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3587 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3588 GET_MODE (XEXP (x, 0)),
3589 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3592 SUBST (XEXP (x, 1), XEXP (x, 2));
3593 SUBST (XEXP (x, 2), temp);
3596 /* If the two arms are identical, we don't need the comparison. */
3598 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3599 && ! side_effects_p (XEXP (x, 0)))
3602 /* Look for cases where we have (abs x) or (neg (abs X)). */
3604 if (GET_MODE_CLASS (mode) == MODE_INT
3605 && GET_CODE (XEXP (x, 2)) == NEG
3606 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3607 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3608 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3609 && ! side_effects_p (XEXP (x, 1)))
3610 switch (GET_CODE (XEXP (x, 0)))
3614 x = gen_unary (ABS, mode, XEXP (x, 1));
3618 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3622 /* Look for MIN or MAX. */
3624 if (GET_MODE_CLASS (mode) == MODE_INT
3625 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3626 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3627 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3628 && ! side_effects_p (XEXP (x, 0)))
3629 switch (GET_CODE (XEXP (x, 0)))
3633 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3637 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3641 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3645 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3649 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3650 A is known to be either 0 or 1, and OP is an identity when its
3651 second operand is zero, this can be done as (OP X (mult A C)).
3652 Similarly if A is known to be 0 or -1 and also similarly if we have
3653 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3654 we don't destroy it). */
3656 if (mode != VOIDmode
3657 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3658 && XEXP (XEXP (x, 0), 1) == const0_rtx
3659 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3660 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3661 == GET_MODE_BITSIZE (mode))))
3663 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3664 ? XEXP (x, 1) : XEXP (x, 2));
3665 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3666 rtx dir = (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3667 ? const1_rtx : constm1_rtx);
3669 enum machine_mode m = mode;
3670 enum rtx_code op, extend_op = 0;
3672 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3673 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3674 || GET_CODE (nz) == ASHIFT
3675 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3676 && rtx_equal_p (XEXP (nz, 0), z))
3677 c = XEXP (nz, 1), op = GET_CODE (nz);
3678 else if (GET_CODE (nz) == SIGN_EXTEND
3679 && (GET_CODE (XEXP (nz, 0)) == PLUS
3680 || GET_CODE (XEXP (nz, 0)) == MINUS
3681 || GET_CODE (XEXP (nz, 0)) == IOR
3682 || GET_CODE (XEXP (nz, 0)) == XOR
3683 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3684 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3685 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3686 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3687 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3688 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3689 && (num_sign_bit_copies (z, GET_MODE (z))
3690 >= (GET_MODE_BITSIZE (mode)
3691 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3693 c = XEXP (XEXP (nz, 0), 1);
3694 op = GET_CODE (XEXP (nz, 0));
3695 extend_op = SIGN_EXTEND;
3696 m = GET_MODE (XEXP (nz, 0));
3698 else if (GET_CODE (nz) == ZERO_EXTEND
3699 && (GET_CODE (XEXP (nz, 0)) == PLUS
3700 || GET_CODE (XEXP (nz, 0)) == MINUS
3701 || GET_CODE (XEXP (nz, 0)) == IOR
3702 || GET_CODE (XEXP (nz, 0)) == XOR
3703 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3704 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3705 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3706 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3707 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3708 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3709 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3710 && ((nonzero_bits (z, GET_MODE (z))
3711 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3714 c = XEXP (XEXP (nz, 0), 1);
3715 op = GET_CODE (XEXP (nz, 0));
3716 extend_op = ZERO_EXTEND;
3717 m = GET_MODE (XEXP (nz, 0));
3720 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3723 = gen_binary (MULT, m,
3724 gen_lowpart_for_combine (m,
3725 XEXP (XEXP (x, 0), 0)),
3726 gen_binary (MULT, m, c, dir));
3728 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3731 temp = gen_unary (extend_op, mode, temp);
3742 /* If we are processing SET_DEST, we are done. */
3746 x = expand_compound_operation (x);
3747 if (GET_CODE (x) != code)
3752 /* (set (pc) (return)) gets written as (return). */
3753 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3756 /* Convert this into a field assignment operation, if possible. */
3757 x = make_field_assignment (x);
3759 /* If we are setting CC0 or if the source is a COMPARE, look for the
3760 use of the comparison result and try to simplify it unless we already
3761 have used undobuf.other_insn. */
3762 if ((GET_CODE (SET_SRC (x)) == COMPARE
3764 || SET_DEST (x) == cc0_rtx
3767 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3769 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3770 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3771 && XEXP (*cc_use, 0) == SET_DEST (x))
3773 enum rtx_code old_code = GET_CODE (*cc_use);
3774 enum rtx_code new_code;
3776 int other_changed = 0;
3777 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3779 if (GET_CODE (SET_SRC (x)) == COMPARE)
3780 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3782 op0 = SET_SRC (x), op1 = const0_rtx;
3784 /* Simplify our comparison, if possible. */
3785 new_code = simplify_comparison (old_code, &op0, &op1);
3787 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3788 /* If this machine has CC modes other than CCmode, check to see
3789 if we need to use a different CC mode here. */
3790 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3792 /* If the mode changed, we have to change SET_DEST, the mode
3793 in the compare, and the mode in the place SET_DEST is used.
3794 If SET_DEST is a hard register, just build new versions with
3795 the proper mode. If it is a pseudo, we lose unless it is only
3796 time we set the pseudo, in which case we can safely change
3798 if (compare_mode != GET_MODE (SET_DEST (x)))
3800 int regno = REGNO (SET_DEST (x));
3801 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3803 if (regno < FIRST_PSEUDO_REGISTER
3804 || (reg_n_sets[regno] == 1
3805 && ! REG_USERVAR_P (SET_DEST (x))))
3807 if (regno >= FIRST_PSEUDO_REGISTER)
3808 SUBST (regno_reg_rtx[regno], new_dest);
3810 SUBST (SET_DEST (x), new_dest);
3811 SUBST (XEXP (*cc_use, 0), new_dest);
3817 /* If the code changed, we have to build a new comparison
3818 in undobuf.other_insn. */
3819 if (new_code != old_code)
3821 unsigned HOST_WIDE_INT mask;
3823 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3824 SET_DEST (x), const0_rtx));
3826 /* If the only change we made was to change an EQ into an
3827 NE or vice versa, OP0 has only one bit that might be nonzero,
3828 and OP1 is zero, check if changing the user of the condition
3829 code will produce a valid insn. If it won't, we can keep
3830 the original code in that insn by surrounding our operation
3833 if (((old_code == NE && new_code == EQ)
3834 || (old_code == EQ && new_code == NE))
3835 && ! other_changed && op1 == const0_rtx
3836 && (GET_MODE_BITSIZE (GET_MODE (op0))
3837 <= HOST_BITS_PER_WIDE_INT)
3838 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
3841 rtx pat = PATTERN (other_insn), note = 0;
3843 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
3844 && ! check_asm_operands (pat)))
3846 PUT_CODE (*cc_use, old_code);
3849 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3858 undobuf.other_insn = other_insn;
3861 /* If we are now comparing against zero, change our source if
3862 needed. If we do not use cc0, we always have a COMPARE. */
3863 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3864 SUBST (SET_SRC (x), op0);
3868 /* Otherwise, if we didn't previously have a COMPARE in the
3869 correct mode, we need one. */
3870 if (GET_CODE (SET_SRC (x)) != COMPARE
3871 || GET_MODE (SET_SRC (x)) != compare_mode)
3872 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3876 /* Otherwise, update the COMPARE if needed. */
3877 SUBST (XEXP (SET_SRC (x), 0), op0);
3878 SUBST (XEXP (SET_SRC (x), 1), op1);
3883 /* Get SET_SRC in a form where we have placed back any
3884 compound expressions. Then do the checks below. */
3885 temp = make_compound_operation (SET_SRC (x), SET);
3886 SUBST (SET_SRC (x), temp);
3889 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3890 operation, and X being a REG or (subreg (reg)), we may be able to
3891 convert this to (set (subreg:m2 x) (op)).
3893 We can always do this if M1 is narrower than M2 because that
3894 means that we only care about the low bits of the result.
3896 However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND
3897 nor BYTES_LOADS_SIGN_EXTEND defined), we cannot perform a
3898 narrower operation that requested since the high-order bits will
3899 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
3900 however, this transformation is safe as long as M1 and M2 have
3901 the same number of words. */
3903 if (GET_CODE (SET_SRC (x)) == SUBREG
3904 && subreg_lowpart_p (SET_SRC (x))
3905 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3906 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3908 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3909 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3910 #ifndef BYTE_LOADS_EXTEND
3911 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3912 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3914 && (GET_CODE (SET_DEST (x)) == REG
3915 || (GET_CODE (SET_DEST (x)) == SUBREG
3916 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3918 SUBST (SET_DEST (x),
3919 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
3921 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3924 #ifdef BYTE_LOADS_EXTEND
3925 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3926 M wider than N, this would require a paradoxical subreg.
3927 Replace the subreg with a zero_extend to avoid the reload that
3928 would otherwise be required. */
3930 if (GET_CODE (SET_SRC (x)) == SUBREG
3931 && subreg_lowpart_p (SET_SRC (x))
3932 && SUBREG_WORD (SET_SRC (x)) == 0
3933 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3934 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3935 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3936 SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND,
3937 GET_MODE (SET_SRC (x)),
3938 XEXP (SET_SRC (x), 0)));
3941 #ifndef HAVE_conditional_move
3943 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
3944 and we are comparing an item known to be 0 or -1 against 0, use a
3945 logical operation instead. Check for one of the arms being an IOR
3946 of the other arm with some value. We compute three terms to be
3947 IOR'ed together. In practice, at most two will be nonzero. Then
3950 if (GET_CODE (SET_DEST (x)) != PC
3951 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
3952 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
3953 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
3954 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
3955 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
3956 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
3957 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
3958 && ! side_effects_p (SET_SRC (x)))
3960 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3961 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
3962 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3963 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
3964 rtx term1 = const0_rtx, term2, term3;
3966 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
3967 term1 = false, true = XEXP (true, 1), false = const0_rtx;
3968 else if (GET_CODE (true) == IOR
3969 && rtx_equal_p (XEXP (true, 1), false))
3970 term1 = false, true = XEXP (true, 0), false = const0_rtx;
3971 else if (GET_CODE (false) == IOR
3972 && rtx_equal_p (XEXP (false, 0), true))
3973 term1 = true, false = XEXP (false, 1), true = const0_rtx;
3974 else if (GET_CODE (false) == IOR
3975 && rtx_equal_p (XEXP (false, 1), true))
3976 term1 = true, false = XEXP (false, 0), true = const0_rtx;
3978 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3979 XEXP (XEXP (SET_SRC (x), 0), 0), true);
3980 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3981 gen_unary (NOT, GET_MODE (SET_SRC (x)),
3982 XEXP (XEXP (SET_SRC (x), 0), 0)),
3986 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3987 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3995 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3997 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3998 INTVAL (XEXP (x, 1)));
4000 /* If we have (ior (and (X C1) C2)) and the next restart would be
4001 the last, simplify this by making C1 as small as possible
4003 if (n_restarts >= 3 && GET_CODE (x) == IOR
4004 && GET_CODE (XEXP (x, 0)) == AND
4005 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4006 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4008 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
4009 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
4010 & ~ INTVAL (XEXP (x, 1))));
4011 return gen_binary (IOR, mode, temp, XEXP (x, 1));
4014 if (GET_CODE (x) != AND)
4018 /* Convert (A | B) & A to A. */
4019 if (GET_CODE (XEXP (x, 0)) == IOR
4020 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4021 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4022 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4023 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4026 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4027 insn (and may simplify more). */
4028 else if (GET_CODE (XEXP (x, 0)) == XOR
4029 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4030 && ! side_effects_p (XEXP (x, 1)))
4032 x = gen_binary (AND, mode,
4033 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4037 else if (GET_CODE (XEXP (x, 0)) == XOR
4038 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4039 && ! side_effects_p (XEXP (x, 1)))
4041 x = gen_binary (AND, mode,
4042 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4047 /* Similarly for (~ (A ^ B)) & A. */
4048 else if (GET_CODE (XEXP (x, 0)) == NOT
4049 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4050 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
4051 && ! side_effects_p (XEXP (x, 1)))
4053 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
4057 else if (GET_CODE (XEXP (x, 0)) == NOT
4058 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4059 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
4060 && ! side_effects_p (XEXP (x, 1)))
4062 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
4067 /* If we have (and A B) with A not an object but that is known to
4068 be -1 or 0, this is equivalent to the expression
4069 (if_then_else (ne A (const_int 0)) B (const_int 0))
4070 We make this conversion because it may allow further
4071 simplifications and then allow use of conditional move insns.
4072 If the machine doesn't have condition moves, code in case SET
4073 will convert the IF_THEN_ELSE back to the logical operation.
4074 We build the IF_THEN_ELSE here in case further simplification
4075 is possible (e.g., we can convert it to ABS). */
4077 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4078 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4079 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4080 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4081 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4083 rtx op0 = XEXP (x, 0);
4084 rtx op1 = const0_rtx;
4085 enum rtx_code comp_code
4086 = simplify_comparison (NE, &op0, &op1);
4088 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4089 gen_binary (comp_code, VOIDmode, op0, op1),
4090 XEXP (x, 1), const0_rtx);
4094 /* In the following group of tests (and those in case IOR below),
4095 we start with some combination of logical operations and apply
4096 the distributive law followed by the inverse distributive law.
4097 Most of the time, this results in no change. However, if some of
4098 the operands are the same or inverses of each other, simplifications
4101 For example, (and (ior A B) (not B)) can occur as the result of
4102 expanding a bit field assignment. When we apply the distributive
4103 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4104 which then simplifies to (and (A (not B))). */
4106 /* If we have (and (ior A B) C), apply the distributive law and then
4107 the inverse distributive law to see if things simplify. */
4109 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4111 x = apply_distributive_law
4112 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4113 gen_binary (AND, mode,
4114 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4115 gen_binary (AND, mode,
4116 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4117 if (GET_CODE (x) != AND)
4121 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4123 x = apply_distributive_law
4124 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4125 gen_binary (AND, mode,
4126 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4127 gen_binary (AND, mode,
4128 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4129 if (GET_CODE (x) != AND)
4133 /* Similarly, taking advantage of the fact that
4134 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4136 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4138 x = apply_distributive_law
4139 (gen_binary (XOR, mode,
4140 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4141 XEXP (XEXP (x, 1), 0)),
4142 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4143 XEXP (XEXP (x, 1), 1))));
4144 if (GET_CODE (x) != AND)
4148 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4150 x = apply_distributive_law
4151 (gen_binary (XOR, mode,
4152 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4153 XEXP (XEXP (x, 0), 0)),
4154 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4155 XEXP (XEXP (x, 0), 1))));
4156 if (GET_CODE (x) != AND)
4162 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4163 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4164 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4165 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4168 /* Convert (A & B) | A to A. */
4169 if (GET_CODE (XEXP (x, 0)) == AND
4170 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4171 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4172 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4173 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4176 /* If we have (ior (and A B) C), apply the distributive law and then
4177 the inverse distributive law to see if things simplify. */
4179 if (GET_CODE (XEXP (x, 0)) == AND)
4181 x = apply_distributive_law
4182 (gen_binary (AND, mode,
4183 gen_binary (IOR, mode,
4184 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4185 gen_binary (IOR, mode,
4186 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4188 if (GET_CODE (x) != IOR)
4192 if (GET_CODE (XEXP (x, 1)) == AND)
4194 x = apply_distributive_law
4195 (gen_binary (AND, mode,
4196 gen_binary (IOR, mode,
4197 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4198 gen_binary (IOR, mode,
4199 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4201 if (GET_CODE (x) != IOR)
4205 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4206 mode size to (rotate A CX). */
4208 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4209 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4210 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4211 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4212 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4213 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4214 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4215 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4216 == GET_MODE_BITSIZE (mode)))
4220 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4221 shift_count = XEXP (XEXP (x, 0), 1);
4223 shift_count = XEXP (XEXP (x, 1), 1);
4224 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4230 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4231 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4234 int num_negated = 0;
4235 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4237 if (GET_CODE (in1) == NOT)
4238 num_negated++, in1 = XEXP (in1, 0);
4239 if (GET_CODE (in2) == NOT)
4240 num_negated++, in2 = XEXP (in2, 0);
4242 if (num_negated == 2)
4244 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4245 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4247 else if (num_negated == 1)
4249 x = gen_unary (NOT, mode,
4250 gen_binary (XOR, mode, in1, in2));
4255 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4256 correspond to a machine insn or result in further simplifications
4257 if B is a constant. */
4259 if (GET_CODE (XEXP (x, 0)) == AND
4260 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4261 && ! side_effects_p (XEXP (x, 1)))
4263 x = gen_binary (AND, mode,
4264 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4268 else if (GET_CODE (XEXP (x, 0)) == AND
4269 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4270 && ! side_effects_p (XEXP (x, 1)))
4272 x = gen_binary (AND, mode,
4273 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4279 #if STORE_FLAG_VALUE == 1
4280 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4282 if (XEXP (x, 1) == const1_rtx
4283 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4284 && reversible_comparison_p (XEXP (x, 0)))
4285 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4286 mode, XEXP (XEXP (x, 0), 0),
4287 XEXP (XEXP (x, 0), 1));
4290 /* (xor (comparison foo bar) (const_int sign-bit))
4291 when STORE_FLAG_VALUE is the sign bit. */
4292 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4293 && (STORE_FLAG_VALUE
4294 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4295 && XEXP (x, 1) == const_true_rtx
4296 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4297 && reversible_comparison_p (XEXP (x, 0)))
4298 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4299 mode, XEXP (XEXP (x, 0), 0),
4300 XEXP (XEXP (x, 0), 1));
4304 /* (abs (neg <foo>)) -> (abs <foo>) */
4305 if (GET_CODE (XEXP (x, 0)) == NEG)
4306 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4308 /* If operand is something known to be positive, ignore the ABS. */
4309 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4310 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4311 <= HOST_BITS_PER_WIDE_INT)
4312 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4313 & ((HOST_WIDE_INT) 1
4314 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4319 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4320 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4322 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4328 /* (ffs (*_extend <X>)) = (ffs <X>) */
4329 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4330 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4331 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4335 /* (float (sign_extend <X>)) = (float <X>). */
4336 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4337 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4346 /* If this is a shift by a constant amount, simplify it. */
4347 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4349 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4350 INTVAL (XEXP (x, 1)));
4351 if (GET_CODE (x) != code)
4355 #ifdef SHIFT_COUNT_TRUNCATED
4356 else if (GET_CODE (XEXP (x, 1)) != REG)
4358 force_to_mode (XEXP (x, 1), GET_MODE (x),
4359 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4369 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4370 operations" because they can be replaced with two more basic operations.
4371 ZERO_EXTEND is also considered "compound" because it can be replaced with
4372 an AND operation, which is simpler, though only one operation.
4374 The function expand_compound_operation is called with an rtx expression
4375 and will convert it to the appropriate shifts and AND operations,
4376 simplifying at each stage.
4378 The function make_compound_operation is called to convert an expression
4379 consisting of shifts and ANDs into the equivalent compound expression.
4380 It is the inverse of this function, loosely speaking. */
4383 expand_compound_operation (x)
4391 switch (GET_CODE (x))
4396 /* We can't necessarily use a const_int for a multiword mode;
4397 it depends on implicitly extending the value.
4398 Since we don't know the right way to extend it,
4399 we can't tell whether the implicit way is right.
4401 Even for a mode that is no wider than a const_int,
4402 we can't win, because we need to sign extend one of its bits through
4403 the rest of it, and we don't know which bit. */
4404 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4407 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4410 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4411 /* If the inner object has VOIDmode (the only way this can happen
4412 is if it is a ASM_OPERANDS), we can't do anything since we don't
4413 know how much masking to do. */
4422 /* If the operand is a CLOBBER, just return it. */
4423 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4426 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4427 || GET_CODE (XEXP (x, 2)) != CONST_INT
4428 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4431 len = INTVAL (XEXP (x, 1));
4432 pos = INTVAL (XEXP (x, 2));
4434 /* If this goes outside the object being extracted, replace the object
4435 with a (use (mem ...)) construct that only combine understands
4436 and is used only for this purpose. */
4437 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4438 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4441 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4449 /* If we reach here, we want to return a pair of shifts. The inner
4450 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4451 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4452 logical depending on the value of UNSIGNEDP.
4454 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4455 converted into an AND of a shift.
4457 We must check for the case where the left shift would have a negative
4458 count. This can happen in a case like (x >> 31) & 255 on machines
4459 that can't shift by a constant. On those machines, we would first
4460 combine the shift with the AND to produce a variable-position
4461 extraction. Then the constant of 31 would be substituted in to produce
4462 a such a position. */
4464 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4465 if (modewidth >= pos - len)
4466 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4468 simplify_shift_const (NULL_RTX, ASHIFT,
4471 modewidth - pos - len),
4474 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4475 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4476 simplify_shift_const (NULL_RTX, LSHIFTRT,
4479 ((HOST_WIDE_INT) 1 << len) - 1);
4481 /* Any other cases we can't handle. */
4485 /* If we couldn't do this for some reason, return the original
4487 if (GET_CODE (tem) == CLOBBER)
4493 /* X is a SET which contains an assignment of one object into
4494 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4495 or certain SUBREGS). If possible, convert it into a series of
4498 We half-heartedly support variable positions, but do not at all
4499 support variable lengths. */
4502 expand_field_assignment (x)
4506 rtx pos; /* Always counts from low bit. */
4509 enum machine_mode compute_mode;
4511 /* Loop until we find something we can't simplify. */
4514 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4515 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4517 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4518 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4521 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4522 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4524 inner = XEXP (SET_DEST (x), 0);
4525 len = INTVAL (XEXP (SET_DEST (x), 1));
4526 pos = XEXP (SET_DEST (x), 2);
4528 /* If the position is constant and spans the width of INNER,
4529 surround INNER with a USE to indicate this. */
4530 if (GET_CODE (pos) == CONST_INT
4531 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4532 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4535 if (GET_CODE (pos) == CONST_INT)
4536 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4538 else if (GET_CODE (pos) == MINUS
4539 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4540 && (INTVAL (XEXP (pos, 1))
4541 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4542 /* If position is ADJUST - X, new position is X. */
4543 pos = XEXP (pos, 0);
4545 pos = gen_binary (MINUS, GET_MODE (pos),
4546 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4552 /* A SUBREG between two modes that occupy the same numbers of words
4553 can be done by moving the SUBREG to the source. */
4554 else if (GET_CODE (SET_DEST (x)) == SUBREG
4555 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4556 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4557 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4558 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4560 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4561 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4568 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4569 inner = SUBREG_REG (inner);
4571 compute_mode = GET_MODE (inner);
4573 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4574 if (len < HOST_BITS_PER_WIDE_INT)
4575 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4579 /* Now compute the equivalent expression. Make a copy of INNER
4580 for the SET_DEST in case it is a MEM into which we will substitute;
4581 we don't want shared RTL in that case. */
4582 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4583 gen_binary (IOR, compute_mode,
4584 gen_binary (AND, compute_mode,
4585 gen_unary (NOT, compute_mode,
4590 gen_binary (ASHIFT, compute_mode,
4591 gen_binary (AND, compute_mode,
4592 gen_lowpart_for_combine
4602 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4603 it is an RTX that represents a variable starting position; otherwise,
4604 POS is the (constant) starting bit position (counted from the LSB).
4606 INNER may be a USE. This will occur when we started with a bitfield
4607 that went outside the boundary of the object in memory, which is
4608 allowed on most machines. To isolate this case, we produce a USE
4609 whose mode is wide enough and surround the MEM with it. The only
4610 code that understands the USE is this routine. If it is not removed,
4611 it will cause the resulting insn not to match.
4613 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4616 IN_DEST is non-zero if this is a reference in the destination of a
4617 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4618 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4621 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4622 ZERO_EXTRACT should be built even for bits starting at bit 0.
4624 MODE is the desired mode of the result (if IN_DEST == 0). */
4627 make_extraction (mode, inner, pos, pos_rtx, len,
4628 unsignedp, in_dest, in_compare)
4629 enum machine_mode mode;
4635 int in_dest, in_compare;
4637 /* This mode describes the size of the storage area
4638 to fetch the overall value from. Within that, we
4639 ignore the POS lowest bits, etc. */
4640 enum machine_mode is_mode = GET_MODE (inner);
4641 enum machine_mode inner_mode;
4642 enum machine_mode wanted_mem_mode = byte_mode;
4643 enum machine_mode pos_mode = word_mode;
4644 enum machine_mode extraction_mode = word_mode;
4645 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4648 rtx orig_pos_rtx = pos_rtx;
4650 /* Get some information about INNER and get the innermost object. */
4651 if (GET_CODE (inner) == USE)
4652 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4653 /* We don't need to adjust the position because we set up the USE
4654 to pretend that it was a full-word object. */
4655 spans_byte = 1, inner = XEXP (inner, 0);
4656 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4658 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4659 consider just the QI as the memory to extract from.
4660 The subreg adds or removes high bits; its mode is
4661 irrelevant to the meaning of this extraction,
4662 since POS and LEN count from the lsb. */
4663 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4664 is_mode = GET_MODE (SUBREG_REG (inner));
4665 inner = SUBREG_REG (inner);
4668 inner_mode = GET_MODE (inner);
4670 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4671 pos = INTVAL (pos_rtx), pos_rtx = 0;
4673 /* See if this can be done without an extraction. We never can if the
4674 width of the field is not the same as that of some integer mode. For
4675 registers, we can only avoid the extraction if the position is at the
4676 low-order bit and this is either not in the destination or we have the
4677 appropriate STRICT_LOW_PART operation available.
4679 For MEM, we can avoid an extract if the field starts on an appropriate
4680 boundary and we can change the mode of the memory reference. However,
4681 we cannot directly access the MEM if we have a USE and the underlying
4682 MEM is not TMODE. This combination means that MEM was being used in a
4683 context where bits outside its mode were being referenced; that is only
4684 valid in bit-field insns. */
4686 if (tmode != BLKmode
4687 && ! (spans_byte && inner_mode != tmode)
4688 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
4690 || (GET_CODE (inner) == REG
4691 && (movstrict_optab->handlers[(int) tmode].insn_code
4692 != CODE_FOR_nothing))))
4693 || (GET_CODE (inner) == MEM && pos_rtx == 0
4695 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4696 : BITS_PER_UNIT)) == 0
4697 /* We can't do this if we are widening INNER_MODE (it
4698 may not be aligned, for one thing). */
4699 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4700 && (inner_mode == tmode
4701 || (! mode_dependent_address_p (XEXP (inner, 0))
4702 && ! MEM_VOLATILE_P (inner))))))
4704 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4705 field. If the original and current mode are the same, we need not
4706 adjust the offset. Otherwise, we do if bytes big endian.
4708 If INNER is not a MEM, get a piece consisting of the just the field
4709 of interest (in this case POS must be 0). */
4711 if (GET_CODE (inner) == MEM)
4714 /* POS counts from lsb, but make OFFSET count in memory order. */
4715 if (BYTES_BIG_ENDIAN)
4716 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4718 offset = pos / BITS_PER_UNIT;
4720 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4721 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4722 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4723 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4725 else if (GET_CODE (inner) == REG)
4726 /* We can't call gen_lowpart_for_combine here since we always want
4727 a SUBREG and it would sometimes return a new hard register. */
4728 new = gen_rtx (SUBREG, tmode, inner,
4730 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4731 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
4735 new = force_to_mode (inner, tmode, len, NULL_RTX);
4737 /* If this extraction is going into the destination of a SET,
4738 make a STRICT_LOW_PART unless we made a MEM. */
4741 return (GET_CODE (new) == MEM ? new
4742 : (GET_CODE (new) != SUBREG
4743 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4744 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4746 /* Otherwise, sign- or zero-extend unless we already are in the
4749 return (mode == tmode ? new
4750 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4754 /* Unless this is a COMPARE or we have a funny memory reference,
4755 don't do anything with zero-extending field extracts starting at
4756 the low-order bit since they are simple AND operations. */
4757 if (pos_rtx == 0 && pos == 0 && ! in_dest
4758 && ! in_compare && ! spans_byte && unsignedp)
4761 /* Get the mode to use should INNER be a MEM, the mode for the position,
4762 and the mode for the result. */
4766 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4767 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4768 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4773 if (! in_dest && unsignedp)
4775 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4776 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4777 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4782 if (! in_dest && ! unsignedp)
4784 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4785 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4786 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4790 /* Never narrow an object, since that might not be safe. */
4792 if (mode != VOIDmode
4793 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4794 extraction_mode = mode;
4796 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4797 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4798 pos_mode = GET_MODE (pos_rtx);
4800 /* If this is not from memory or we have to change the mode of memory and
4801 cannot, the desired mode is EXTRACTION_MODE. */
4802 if (GET_CODE (inner) != MEM
4803 || (inner_mode != wanted_mem_mode
4804 && (mode_dependent_address_p (XEXP (inner, 0))
4805 || MEM_VOLATILE_P (inner))))
4806 wanted_mem_mode = extraction_mode;
4809 /* If position is constant, compute new position. Otherwise, build
4812 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4816 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4817 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4818 GET_MODE_BITSIZE (wanted_mem_mode))
4823 /* If INNER has a wider mode, make it smaller. If this is a constant
4824 extract, try to adjust the byte to point to the byte containing
4826 if (wanted_mem_mode != VOIDmode
4827 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4828 && ((GET_CODE (inner) == MEM
4829 && (inner_mode == wanted_mem_mode
4830 || (! mode_dependent_address_p (XEXP (inner, 0))
4831 && ! MEM_VOLATILE_P (inner))))))
4835 /* The computations below will be correct if the machine is big
4836 endian in both bits and bytes or little endian in bits and bytes.
4837 If it is mixed, we must adjust. */
4839 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4840 if (! spans_byte && is_mode != wanted_mem_mode)
4841 offset = (GET_MODE_SIZE (is_mode)
4842 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4845 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4846 adjust OFFSET to compensate. */
4847 #if BYTES_BIG_ENDIAN
4849 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4850 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4853 /* If this is a constant position, we can move to the desired byte. */
4856 offset += pos / BITS_PER_UNIT;
4857 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4860 if (offset != 0 || inner_mode != wanted_mem_mode)
4862 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4863 plus_constant (XEXP (inner, 0), offset));
4864 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4865 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4866 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4871 /* If INNER is not memory, we can always get it into the proper mode. */
4872 else if (GET_CODE (inner) != MEM)
4873 inner = force_to_mode (inner, extraction_mode,
4874 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4878 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4879 have to zero extend. Otherwise, we can just use a SUBREG. */
4881 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4882 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4883 else if (pos_rtx != 0
4884 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4885 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4887 /* Make POS_RTX unless we already have it and it is correct. If we don't
4888 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
4890 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
4891 pos_rtx = orig_pos_rtx;
4893 else if (pos_rtx == 0)
4894 pos_rtx = GEN_INT (pos);
4896 /* Make the required operation. See if we can use existing rtx. */
4897 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4898 extraction_mode, inner, GEN_INT (len), pos_rtx);
4900 new = gen_lowpart_for_combine (mode, new);
4905 /* Look at the expression rooted at X. Look for expressions
4906 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4907 Form these expressions.
4909 Return the new rtx, usually just X.
4911 Also, for machines like the Vax that don't have logical shift insns,
4912 try to convert logical to arithmetic shift operations in cases where
4913 they are equivalent. This undoes the canonicalizations to logical
4914 shifts done elsewhere.
4916 We try, as much as possible, to re-use rtl expressions to save memory.
4918 IN_CODE says what kind of expression we are processing. Normally, it is
4919 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4920 being kludges), it is MEM. When processing the arguments of a comparison
4921 or a COMPARE against zero, it is COMPARE. */
4924 make_compound_operation (x, in_code)
4926 enum rtx_code in_code;
4928 enum rtx_code code = GET_CODE (x);
4929 enum machine_mode mode = GET_MODE (x);
4930 int mode_width = GET_MODE_BITSIZE (mode);
4931 enum rtx_code next_code;
4936 /* Select the code to be used in recursive calls. Once we are inside an
4937 address, we stay there. If we have a comparison, set to COMPARE,
4938 but once inside, go back to our default of SET. */
4940 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4941 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4942 && XEXP (x, 1) == const0_rtx) ? COMPARE
4943 : in_code == COMPARE ? SET : in_code);
4945 /* Process depending on the code of this operation. If NEW is set
4946 non-zero, it will be returned. */
4952 /* Convert shifts by constants into multiplications if inside
4954 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4955 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
4956 && INTVAL (XEXP (x, 1)) >= 0)
4957 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4958 GEN_INT ((HOST_WIDE_INT) 1
4959 << INTVAL (XEXP (x, 1))));
4963 /* If the second operand is not a constant, we can't do anything
4965 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4968 /* If the constant is a power of two minus one and the first operand
4969 is a logical right shift, make an extraction. */
4970 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4971 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4972 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), 0,
4973 XEXP (XEXP (x, 0), 1), i, 1,
4974 0, in_code == COMPARE);
4976 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4977 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4978 && subreg_lowpart_p (XEXP (x, 0))
4979 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4980 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4981 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4982 XEXP (SUBREG_REG (XEXP (x, 0)), 0), 0,
4983 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4984 0, in_code == COMPARE);
4987 /* If we are have (and (rotate X C) M) and C is larger than the number
4988 of bits in M, this is an extraction. */
4990 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4991 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4992 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4993 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4994 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4995 (GET_MODE_BITSIZE (mode)
4996 - INTVAL (XEXP (XEXP (x, 0), 1))),
4997 NULL_RTX, i, 1, 0, in_code == COMPARE);
4999 /* On machines without logical shifts, if the operand of the AND is
5000 a logical shift and our mask turns off all the propagated sign
5001 bits, we can replace the logical shift with an arithmetic shift. */
5002 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5003 && (lshr_optab->handlers[(int) mode].insn_code
5004 == CODE_FOR_nothing)
5005 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5006 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5007 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5008 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5009 && mode_width <= HOST_BITS_PER_WIDE_INT)
5011 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5013 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5014 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5016 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
5017 XEXP (XEXP (x, 0), 1)));
5020 /* If the constant is one less than a power of two, this might be
5021 representable by an extraction even if no shift is present.
5022 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5023 we are in a COMPARE. */
5024 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5025 new = make_extraction (mode, XEXP (x, 0), 0, NULL_RTX, i, 1,
5026 0, in_code == COMPARE);
5028 /* If we are in a comparison and this is an AND with a power of two,
5029 convert this into the appropriate bit extract. */
5030 else if (in_code == COMPARE
5031 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5032 new = make_extraction (mode, XEXP (x, 0), i, NULL_RTX, 1, 1, 0, 1);
5037 /* If the sign bit is known to be zero, replace this with an
5038 arithmetic shift. */
5039 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5040 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5041 && mode_width <= HOST_BITS_PER_WIDE_INT
5042 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5044 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
5048 /* ... fall through ... */
5051 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5052 this is a SIGN_EXTRACT. */
5053 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5054 && GET_CODE (XEXP (x, 0)) == ASHIFT
5055 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5056 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5057 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
5058 (INTVAL (XEXP (x, 1))
5059 - INTVAL (XEXP (XEXP (x, 0), 1))),
5060 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5061 code == LSHIFTRT, 0, in_code == COMPARE);
5063 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5064 cases, we are better off returning a SIGN_EXTEND of the operation. */
5066 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5067 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5068 || GET_CODE (XEXP (x, 0)) == XOR
5069 || GET_CODE (XEXP (x, 0)) == PLUS)
5070 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5071 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5072 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5073 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5074 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5075 && (INTVAL (XEXP (XEXP (x, 0), 1))
5076 & (((HOST_WIDE_INT) 1
5077 << INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) - 1)) == 0)
5079 HOST_WIDE_INT newop1
5080 = (INTVAL (XEXP (XEXP (x, 0), 1))
5081 >> INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
5083 new = make_extraction (mode,
5084 gen_binary (GET_CODE (XEXP (x, 0)), mode,
5085 XEXP (XEXP (XEXP (x, 0), 0), 0),
5087 (INTVAL (XEXP (x, 1))
5088 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5089 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5090 code == LSHIFTRT, 0, in_code == COMPARE);
5093 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5094 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5095 && GET_CODE (XEXP (x, 0)) == NEG
5096 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5097 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5098 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5099 new = make_extraction (mode,
5100 gen_unary (GET_CODE (XEXP (x, 0)), mode,
5101 XEXP (XEXP (XEXP (x, 0), 0), 0)),
5102 (INTVAL (XEXP (x, 1))
5103 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5104 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5105 code == LSHIFTRT, 0, in_code == COMPARE);
5111 x = gen_lowpart_for_combine (mode, new);
5112 code = GET_CODE (x);
5115 /* Now recursively process each operand of this operation. */
5116 fmt = GET_RTX_FORMAT (code);
5117 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5120 new = make_compound_operation (XEXP (x, i), next_code);
5121 SUBST (XEXP (x, i), new);
5127 /* Given M see if it is a value that would select a field of bits
5128 within an item, but not the entire word. Return -1 if not.
5129 Otherwise, return the starting position of the field, where 0 is the
5132 *PLEN is set to the length of the field. */
5135 get_pos_from_mask (m, plen)
5136 unsigned HOST_WIDE_INT m;
5139 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5140 int pos = exact_log2 (m & - m);
5145 /* Now shift off the low-order zero bits and see if we have a power of
5147 *plen = exact_log2 ((m >> pos) + 1);
5155 /* Rewrite X so that it is an expression in MODE. We only care about the
5156 low-order BITS bits so we can ignore AND operations that just clear
5159 Also, if REG is non-zero and X is a register equal in value to REG,
5160 replace X with REG. */
5163 force_to_mode (x, mode, bits, reg)
5165 enum machine_mode mode;
5169 enum rtx_code code = GET_CODE (x);
5170 enum machine_mode op_mode = mode;
5172 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5173 just get X in the proper mode. */
5175 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5176 || bits > GET_MODE_BITSIZE (mode))
5177 return gen_lowpart_for_combine (mode, x);
5185 x = expand_compound_operation (x);
5186 if (GET_CODE (x) != code)
5187 return force_to_mode (x, mode, bits, reg);
5191 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5192 || rtx_equal_p (reg, get_last_value (x))))
5197 if (bits < HOST_BITS_PER_WIDE_INT)
5198 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5202 /* Ignore low-order SUBREGs. */
5203 if (subreg_lowpart_p (x))
5204 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5208 /* If this is an AND with a constant. Otherwise, we fall through to
5209 do the general binary case. */
5211 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5213 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5214 int len = exact_log2 (mask + 1);
5215 rtx op = XEXP (x, 0);
5217 /* If this is masking some low-order bits, we may be able to
5218 impose a stricter constraint on what bits of the operand are
5221 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5224 if (bits < HOST_BITS_PER_WIDE_INT)
5225 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5227 /* If we have no AND in MODE, use the original mode for the
5230 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5231 op_mode = GET_MODE (x);
5233 x = simplify_and_const_int (x, op_mode, op, mask);
5235 /* If X is still an AND, see if it is an AND with a mask that
5236 is just some low-order bits. If so, and it is BITS wide (it
5237 can't be wider), we don't need it. */
5239 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5240 && bits < HOST_BITS_PER_WIDE_INT
5241 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5247 /* ... fall through ... */
5254 /* For most binary operations, just propagate into the operation and
5255 change the mode if we have an operation of that mode. */
5258 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5260 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5261 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5262 == CODE_FOR_nothing))
5264 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5266 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5267 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5268 == CODE_FOR_nothing)))
5269 op_mode = GET_MODE (x);
5271 x = gen_binary (code, op_mode,
5272 gen_lowpart_for_combine (op_mode,
5273 force_to_mode (XEXP (x, 0),
5276 gen_lowpart_for_combine (op_mode,
5277 force_to_mode (XEXP (x, 1),
5284 /* For left shifts, do the same, but just for the first operand.
5285 If the shift count is a constant, we need even fewer bits of the
5288 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5289 bits -= INTVAL (XEXP (x, 1));
5292 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5293 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5294 == CODE_FOR_nothing)))
5295 op_mode = GET_MODE (x);
5297 x = gen_binary (code, op_mode,
5298 gen_lowpart_for_combine (op_mode,
5299 force_to_mode (XEXP (x, 0),
5306 /* Here we can only do something if the shift count is a constant and
5307 the count plus BITS is no larger than the width of MODE, we can do
5308 the shift in MODE. */
5310 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5311 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5313 rtx inner = force_to_mode (XEXP (x, 0), mode,
5314 bits + INTVAL (XEXP (x, 1)), reg);
5316 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5317 op_mode = GET_MODE (x);
5319 x = gen_binary (LSHIFTRT, op_mode,
5320 gen_lowpart_for_combine (op_mode, inner),
5326 /* If this is a sign-extension operation that just affects bits
5327 we don't care about, remove it. */
5329 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5330 && INTVAL (XEXP (x, 1)) >= 0
5331 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5332 && GET_CODE (XEXP (x, 0)) == ASHIFT
5333 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5334 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5335 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5341 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5342 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5343 == CODE_FOR_nothing)))
5344 op_mode = GET_MODE (x);
5346 /* Handle these similarly to the way we handle most binary operations. */
5347 x = gen_unary (code, op_mode,
5348 gen_lowpart_for_combine (op_mode,
5349 force_to_mode (XEXP (x, 0), mode,
5354 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5355 written in a narrower mode. We play it safe and do not do so. */
5358 gen_lowpart_for_combine (GET_MODE (x),
5359 force_to_mode (XEXP (x, 1), mode,
5362 gen_lowpart_for_combine (GET_MODE (x),
5363 force_to_mode (XEXP (x, 2), mode,
5368 /* Ensure we return a value of the proper mode. */
5369 return gen_lowpart_for_combine (mode, x);
5372 /* Return the value of expression X given the fact that condition COND
5373 is known to be true when applied to REG as its first operand and VAL
5374 as its second. X is known to not be shared and so can be modified in
5377 We only handle the simplest cases, and specifically those cases that
5378 arise with IF_THEN_ELSE expressions. */
5381 known_cond (x, cond, reg, val)
5386 enum rtx_code code = GET_CODE (x);
5391 if (side_effects_p (x))
5394 if (cond == EQ && rtx_equal_p (x, reg))
5397 /* If X is (abs REG) and we know something about REG's relationship
5398 with zero, we may be able to simplify this. */
5400 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5403 case GE: case GT: case EQ:
5406 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5409 /* The only other cases we handle are MIN, MAX, and comparisons if the
5410 operands are the same as REG and VAL. */
5412 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5414 if (rtx_equal_p (XEXP (x, 0), val))
5415 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5417 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5419 if (GET_RTX_CLASS (code) == '<')
5420 return (comparison_dominates_p (cond, code) ? const_true_rtx
5421 : (comparison_dominates_p (cond,
5422 reverse_condition (code))
5425 else if (code == SMAX || code == SMIN
5426 || code == UMIN || code == UMAX)
5428 int unsignedp = (code == UMIN || code == UMAX);
5430 if (code == SMAX || code == UMAX)
5431 cond = reverse_condition (cond);
5436 return unsignedp ? x : XEXP (x, 1);
5438 return unsignedp ? x : XEXP (x, 0);
5440 return unsignedp ? XEXP (x, 1) : x;
5442 return unsignedp ? XEXP (x, 0) : x;
5448 fmt = GET_RTX_FORMAT (code);
5449 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5452 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5453 else if (fmt[i] == 'E')
5454 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5455 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5462 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5463 Return that assignment if so.
5465 We only handle the most common cases. */
5468 make_field_assignment (x)
5471 rtx dest = SET_DEST (x);
5472 rtx src = SET_SRC (x);
5478 enum machine_mode mode;
5480 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5481 a clear of a one-bit field. We will have changed it to
5482 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5485 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5486 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5487 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5488 && (rtx_equal_p (dest, XEXP (src, 1))
5489 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5490 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5492 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5494 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5497 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5498 && subreg_lowpart_p (XEXP (src, 0))
5499 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5500 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5501 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5502 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5503 && (rtx_equal_p (dest, XEXP (src, 1))
5504 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5505 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5507 assign = make_extraction (VOIDmode, dest, 0,
5508 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5510 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5513 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5515 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5516 && XEXP (XEXP (src, 0), 0) == const1_rtx
5517 && (rtx_equal_p (dest, XEXP (src, 1))
5518 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5519 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5521 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5523 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5526 /* The other case we handle is assignments into a constant-position
5527 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5528 a mask that has all one bits except for a group of zero bits and
5529 OTHER is known to have zeros where C1 has ones, this is such an
5530 assignment. Compute the position and length from C1. Shift OTHER
5531 to the appropriate position, force it to the required mode, and
5532 make the extraction. Check for the AND in both operands. */
5534 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5535 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5536 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5537 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5538 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5539 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5540 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5541 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5542 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5543 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5544 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5546 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5550 pos = get_pos_from_mask (~c1, &len);
5551 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5552 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5553 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
5556 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5558 /* The mode to use for the source is the mode of the assignment, or of
5559 what is inside a possible STRICT_LOW_PART. */
5560 mode = (GET_CODE (assign) == STRICT_LOW_PART
5561 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5563 /* Shift OTHER right POS places and make it the source, restricting it
5564 to the proper length and mode. */
5566 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5567 GET_MODE (src), other, pos),
5570 return gen_rtx_combine (SET, VOIDmode, assign, src);
5573 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5577 apply_distributive_law (x)
5580 enum rtx_code code = GET_CODE (x);
5581 rtx lhs, rhs, other;
5583 enum rtx_code inner_code;
5585 /* Distributivity is not true for floating point.
5586 It can change the value. So don't do it.
5587 -- rms and moshier@world.std.com. */
5588 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5591 /* The outer operation can only be one of the following: */
5592 if (code != IOR && code != AND && code != XOR
5593 && code != PLUS && code != MINUS)
5596 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5598 /* If either operand is a primitive we can't do anything, so get out fast. */
5599 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5600 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5603 lhs = expand_compound_operation (lhs);
5604 rhs = expand_compound_operation (rhs);
5605 inner_code = GET_CODE (lhs);
5606 if (inner_code != GET_CODE (rhs))
5609 /* See if the inner and outer operations distribute. */
5616 /* These all distribute except over PLUS. */
5617 if (code == PLUS || code == MINUS)
5622 if (code != PLUS && code != MINUS)
5628 /* These are also multiplies, so they distribute over everything. */
5632 /* Non-paradoxical SUBREGs distributes over all operations, provided
5633 the inner modes and word numbers are the same, this is an extraction
5634 of a low-order part, we don't convert an fp operation to int or
5635 vice versa, and we would not be converting a single-word
5636 operation into a multi-word operation. The latter test is not
5637 required, but it prevents generating unneeded multi-word operations.
5638 Some of the previous tests are redundant given the latter test, but
5639 are retained because they are required for correctness.
5641 We produce the result slightly differently in this case. */
5643 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5644 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5645 || ! subreg_lowpart_p (lhs)
5646 || (GET_MODE_CLASS (GET_MODE (lhs))
5647 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5648 || (GET_MODE_SIZE (GET_MODE (lhs))
5649 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5650 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5653 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5654 SUBREG_REG (lhs), SUBREG_REG (rhs));
5655 return gen_lowpart_for_combine (GET_MODE (x), tem);
5661 /* Set LHS and RHS to the inner operands (A and B in the example
5662 above) and set OTHER to the common operand (C in the example).
5663 These is only one way to do this unless the inner operation is
5665 if (GET_RTX_CLASS (inner_code) == 'c'
5666 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5667 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5668 else if (GET_RTX_CLASS (inner_code) == 'c'
5669 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5670 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5671 else if (GET_RTX_CLASS (inner_code) == 'c'
5672 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5673 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5674 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5675 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5679 /* Form the new inner operation, seeing if it simplifies first. */
5680 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5682 /* There is one exception to the general way of distributing:
5683 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5684 if (code == XOR && inner_code == IOR)
5687 other = gen_unary (NOT, GET_MODE (x), other);
5690 /* We may be able to continuing distributing the result, so call
5691 ourselves recursively on the inner operation before forming the
5692 outer operation, which we return. */
5693 return gen_binary (inner_code, GET_MODE (x),
5694 apply_distributive_law (tem), other);
5697 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5700 Return an equivalent form, if different from X. Otherwise, return X. If
5701 X is zero, we are to always construct the equivalent form. */
5704 simplify_and_const_int (x, mode, varop, constop)
5706 enum machine_mode mode;
5708 unsigned HOST_WIDE_INT constop;
5710 register enum machine_mode tmode;
5712 unsigned HOST_WIDE_INT nonzero;
5714 /* There is a large class of optimizations based on the principle that
5715 some operations produce results where certain bits are known to be zero,
5716 and hence are not significant to the AND. For example, if we have just
5717 done a left shift of one bit, the low-order bit is known to be zero and
5718 hence an AND with a mask of ~1 would not do anything.
5720 At the end of the following loop, we set:
5722 VAROP to be the item to be AND'ed with;
5723 CONSTOP to the constant value to AND it with. */
5727 /* If we ever encounter a mode wider than the host machine's widest
5728 integer size, we can't compute the masks accurately, so give up. */
5729 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5732 /* Unless one of the cases below does a `continue',
5733 a `break' will be executed to exit the loop. */
5735 switch (GET_CODE (varop))
5738 /* If VAROP is a (clobber (const_int)), return it since we know
5739 we are generating something that won't match. */
5742 #if ! BITS_BIG_ENDIAN
5744 /* VAROP is a (use (mem ..)) that was made from a bit-field
5745 extraction that spanned the boundary of the MEM. If we are
5746 now masking so it is within that boundary, we don't need the
5748 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5750 varop = XEXP (varop, 0);
5757 if (subreg_lowpart_p (varop)
5758 /* We can ignore the effect this SUBREG if it narrows the mode
5759 or, on machines where byte operations extend, if the
5760 constant masks to zero all the bits the mode doesn't have. */
5761 && ((GET_MODE_SIZE (GET_MODE (varop))
5762 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5763 #ifdef BYTE_LOADS_EXTEND
5765 & GET_MODE_MASK (GET_MODE (varop))
5766 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5770 varop = SUBREG_REG (varop);
5779 /* Try to expand these into a series of shifts and then work
5780 with that result. If we can't, for example, if the extract
5781 isn't at a fixed position, give up. */
5782 temp = expand_compound_operation (varop);
5791 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5793 constop &= INTVAL (XEXP (varop, 1));
5794 varop = XEXP (varop, 0);
5801 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5802 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5803 operation which may be a bitfield extraction. */
5805 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5806 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5807 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5808 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5809 && GET_CODE (XEXP (varop, 1)) == CONST_INT
5810 && (INTVAL (XEXP (varop, 1))
5811 & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0))
5813 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
5814 << INTVAL (XEXP (XEXP (varop, 0), 1)));
5815 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5816 XEXP (XEXP (varop, 0), 0), temp);
5817 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5818 temp, XEXP (varop, 1));
5822 /* Apply the AND to both branches of the IOR or XOR, then try to
5823 apply the distributive law. This may eliminate operations
5824 if either branch can be simplified because of the AND.
5825 It may also make some cases more complex, but those cases
5826 probably won't match a pattern either with or without this. */
5828 gen_lowpart_for_combine
5829 (mode, apply_distributive_law
5831 (GET_CODE (varop), GET_MODE (varop),
5832 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5833 XEXP (varop, 0), constop),
5834 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5835 XEXP (varop, 1), constop))));
5838 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5839 LSHIFTRT we can do the same as above. */
5841 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5842 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5843 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5844 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5846 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
5847 temp = gen_binary (XOR, GET_MODE (varop),
5848 XEXP (XEXP (varop, 0), 0), temp);
5849 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5850 temp, XEXP (XEXP (varop, 0), 1));
5856 /* If we are just looking for the sign bit, we don't need this
5857 shift at all, even if it has a variable count. */
5858 if (constop == ((HOST_WIDE_INT) 1
5859 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
5861 varop = XEXP (varop, 0);
5865 /* If this is a shift by a constant, get a mask that contains
5866 those bits that are not copies of the sign bit. We then have
5867 two cases: If CONSTOP only includes those bits, this can be
5868 a logical shift, which may allow simplifications. If CONSTOP
5869 is a single-bit field not within those bits, we are requesting
5870 a copy of the sign bit and hence can shift the sign bit to
5871 the appropriate location. */
5872 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5873 && INTVAL (XEXP (varop, 1)) >= 0
5874 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
5878 nonzero = GET_MODE_MASK (GET_MODE (varop));
5879 nonzero >>= INTVAL (XEXP (varop, 1));
5881 if ((constop & ~ nonzero) == 0
5882 || (i = exact_log2 (constop)) >= 0)
5884 varop = simplify_shift_const
5885 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5886 i < 0 ? INTVAL (XEXP (varop, 1))
5887 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
5888 if (GET_CODE (varop) != ASHIFTRT)
5893 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5894 even if the shift count isn't a constant. */
5896 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5897 XEXP (varop, 0), XEXP (varop, 1));
5901 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5902 included in STORE_FLAG_VALUE and FOO has no bits that might be
5903 nonzero not in CONST. */
5904 if ((constop & ~ STORE_FLAG_VALUE) == 0
5905 && XEXP (varop, 0) == const0_rtx
5906 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5908 varop = XEXP (varop, 0);
5914 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5915 low-order bits (as in an alignment operation) and FOO is already
5916 aligned to that boundary, we can convert remove this AND
5917 and possibly the PLUS if it is now adding zero. */
5918 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5919 && exact_log2 (-constop) >= 0
5920 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5922 varop = plus_constant (XEXP (varop, 0),
5923 INTVAL (XEXP (varop, 1)) & constop);
5928 /* ... fall through ... */
5931 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5932 less than powers of two and M2 is narrower than M1, we can
5933 eliminate the inner AND. This occurs when incrementing
5936 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5937 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5938 SUBST (XEXP (varop, 0),
5939 expand_compound_operation (XEXP (varop, 0)));
5941 if (GET_CODE (XEXP (varop, 0)) == AND
5942 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5943 && exact_log2 (constop + 1) >= 0
5944 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5945 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5946 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5953 /* If we have reached a constant, this whole thing is constant. */
5954 if (GET_CODE (varop) == CONST_INT)
5955 return GEN_INT (constop & INTVAL (varop));
5957 /* See what bits may be nonzero in VAROP. Unlike the general case of
5958 a call to nonzero_bits, here we don't care about bits outside
5961 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
5963 /* Turn off all bits in the constant that are known to already be zero.
5964 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
5965 which is tested below. */
5969 /* If we don't have any bits left, return zero. */
5973 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5974 if we already had one (just check for the simplest cases). */
5975 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5976 && GET_MODE (XEXP (x, 0)) == mode
5977 && SUBREG_REG (XEXP (x, 0)) == varop)
5978 varop = XEXP (x, 0);
5980 varop = gen_lowpart_for_combine (mode, varop);
5982 /* If we can't make the SUBREG, try to return what we were given. */
5983 if (GET_CODE (varop) == CLOBBER)
5984 return x ? x : varop;
5986 /* If we are only masking insignificant bits, return VAROP. */
5987 if (constop == nonzero)
5990 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5991 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5992 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
5996 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5997 || INTVAL (XEXP (x, 1)) != constop)
5998 SUBST (XEXP (x, 1), GEN_INT (constop));
6000 SUBST (XEXP (x, 0), varop);
6006 /* Given an expression, X, compute which bits in X can be non-zero.
6007 We don't care about bits outside of those defined in MODE.
6009 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6010 a shift, AND, or zero_extract, we can do better. */
6012 static unsigned HOST_WIDE_INT
6013 nonzero_bits (x, mode)
6015 enum machine_mode mode;
6017 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6018 unsigned HOST_WIDE_INT inner_nz;
6020 int mode_width = GET_MODE_BITSIZE (mode);
6023 /* If X is wider than MODE, use its mode instead. */
6024 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6026 mode = GET_MODE (x);
6027 nonzero = GET_MODE_MASK (mode);
6028 mode_width = GET_MODE_BITSIZE (mode);
6031 if (mode_width > HOST_BITS_PER_WIDE_INT)
6032 /* Our only callers in this case look for single bit values. So
6033 just return the mode mask. Those tests will then be false. */
6036 code = GET_CODE (x);
6040 #ifdef STACK_BOUNDARY
6041 /* If this is the stack pointer, we may know something about its
6042 alignment. If PUSH_ROUNDING is defined, it is possible for the
6043 stack to be momentarily aligned only to that amount, so we pick
6044 the least alignment. */
6046 if (x == stack_pointer_rtx)
6048 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6050 #ifdef PUSH_ROUNDING
6051 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6054 return nonzero & ~ (sp_alignment - 1);
6058 /* If X is a register whose value we can find, use that value.
6059 Otherwise, use the previously-computed nonzero bits for this
6062 tem = get_last_value (x);
6064 return nonzero_bits (tem, mode);
6065 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6066 return reg_nonzero_bits[REGNO (x)] & nonzero;
6073 #ifdef BYTE_LOADS_ZERO_EXTEND
6075 /* In many, if not most, RISC machines, reading a byte from memory
6076 zeros the rest of the register. Noticing that fact saves a lot
6077 of extra zero-extends. */
6078 nonzero &= GET_MODE_MASK (GET_MODE (x));
6082 #if STORE_FLAG_VALUE == 1
6089 if (GET_MODE_CLASS (mode) == MODE_INT)
6092 /* A comparison operation only sets the bits given by its mode. The
6093 rest are set undefined. */
6094 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6095 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6100 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6101 == GET_MODE_BITSIZE (GET_MODE (x)))
6104 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6105 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6109 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6110 == GET_MODE_BITSIZE (GET_MODE (x)))
6115 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6119 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6120 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6121 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6125 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6126 Otherwise, show all the bits in the outer mode but not the inner
6128 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6129 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6131 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6134 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6135 inner_nz |= (GET_MODE_MASK (mode)
6136 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6139 nonzero &= inner_nz;
6143 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6144 & nonzero_bits (XEXP (x, 1), mode));
6148 case UMIN: case UMAX: case SMIN: case SMAX:
6149 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6150 | nonzero_bits (XEXP (x, 1), mode));
6153 case PLUS: case MINUS:
6155 case DIV: case UDIV:
6156 case MOD: case UMOD:
6157 /* We can apply the rules of arithmetic to compute the number of
6158 high- and low-order zero bits of these operations. We start by
6159 computing the width (position of the highest-order non-zero bit)
6160 and the number of low-order zero bits for each value. */
6162 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6163 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6164 int width0 = floor_log2 (nz0) + 1;
6165 int width1 = floor_log2 (nz1) + 1;
6166 int low0 = floor_log2 (nz0 & -nz0);
6167 int low1 = floor_log2 (nz1 & -nz1);
6168 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6169 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6170 int result_width = mode_width;
6176 result_width = MAX (width0, width1) + 1;
6177 result_low = MIN (low0, low1);
6180 result_low = MIN (low0, low1);
6183 result_width = width0 + width1;
6184 result_low = low0 + low1;
6187 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6188 result_width = width0;
6191 result_width = width0;
6194 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6195 result_width = MIN (width0, width1);
6196 result_low = MIN (low0, low1);
6199 result_width = MIN (width0, width1);
6200 result_low = MIN (low0, low1);
6204 if (result_width < mode_width)
6205 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6208 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6213 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6214 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6215 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6219 /* If this is a SUBREG formed for a promoted variable that has
6220 been zero-extended, we know that at least the high-order bits
6221 are zero, though others might be too. */
6223 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6224 nonzero = (GET_MODE_MASK (GET_MODE (x))
6225 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6227 /* If the inner mode is a single word for both the host and target
6228 machines, we can compute this from which bits of the inner
6229 object might be nonzero. */
6230 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6231 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6232 <= HOST_BITS_PER_WIDE_INT))
6234 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6235 #ifndef BYTE_LOADS_EXTEND
6236 /* On many CISC machines, accessing an object in a wider mode
6237 causes the high-order bits to become undefined. So they are
6238 not known to be zero. */
6239 if (GET_MODE_SIZE (GET_MODE (x))
6240 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6241 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6242 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6252 /* The nonzero bits are in two classes: any bits within MODE
6253 that aren't in GET_MODE (x) are always significant. The rest of the
6254 nonzero bits are those that are significant in the operand of
6255 the shift when shifted the appropriate number of bits. This
6256 shows that high-order bits are cleared by the right shift and
6257 low-order bits by left shifts. */
6258 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6259 && INTVAL (XEXP (x, 1)) >= 0
6260 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6262 enum machine_mode inner_mode = GET_MODE (x);
6263 int width = GET_MODE_BITSIZE (inner_mode);
6264 int count = INTVAL (XEXP (x, 1));
6265 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6266 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6267 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6268 unsigned HOST_WIDE_INT outer = 0;
6270 if (mode_width > width)
6271 outer = (op_nonzero & nonzero & ~ mode_mask);
6273 if (code == LSHIFTRT)
6275 else if (code == ASHIFTRT)
6279 /* If the sign bit may have been nonzero before the shift, we
6280 need to mark all the places it could have been copied to
6281 by the shift as possibly nonzero. */
6282 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6283 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6285 else if (code == LSHIFT || code == ASHIFT)
6288 inner = ((inner << (count % width)
6289 | (inner >> (width - (count % width)))) & mode_mask);
6291 nonzero &= (outer | inner);
6296 /* This is at most the number of bits in the mode. */
6297 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6301 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6302 | nonzero_bits (XEXP (x, 2), mode));
6309 /* Return the number of bits at the high-order end of X that are known to
6310 be equal to the sign bit. This number will always be between 1 and
6311 the number of bits in the mode of X. MODE is the mode to be used
6312 if X is VOIDmode. */
6315 num_sign_bit_copies (x, mode)
6317 enum machine_mode mode;
6319 enum rtx_code code = GET_CODE (x);
6321 int num0, num1, result;
6322 unsigned HOST_WIDE_INT nonzero;
6325 /* If we weren't given a mode, use the mode of X. If the mode is still
6326 VOIDmode, we don't know anything. */
6328 if (mode == VOIDmode)
6329 mode = GET_MODE (x);
6331 if (mode == VOIDmode)
6334 bitwidth = GET_MODE_BITSIZE (mode);
6339 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6340 return reg_sign_bit_copies[REGNO (x)];
6342 tem = get_last_value (x);
6344 return num_sign_bit_copies (tem, mode);
6347 #ifdef BYTE_LOADS_SIGN_EXTEND
6349 /* Some RISC machines sign-extend all loads of smaller than a word. */
6350 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6354 /* If the constant is negative, take its 1's complement and remask.
6355 Then see how many zero bits we have. */
6356 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6357 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6358 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6359 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6361 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6364 /* If this is a SUBREG for a promoted object that is sign-extended
6365 and we are looking at it in a wider mode, we know that at least the
6366 high-order bits are known to be sign bit copies. */
6368 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6369 return (GET_MODE_BITSIZE (mode) - GET_MODE_BITSIZE (GET_MODE (x))
6370 + num_sign_bit_copies (SUBREG_REG (x), GET_MODE (x)));
6372 /* For a smaller object, just ignore the high bits. */
6373 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6375 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6376 return MAX (1, (num0
6377 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6381 #ifdef BYTE_LOADS_EXTEND
6382 /* For paradoxical SUBREGs, just look inside since, on machines with
6383 one of these defined, we assume that operations are actually
6384 performed on the full register. Note that we are passing MODE
6385 to the recursive call, so the number of sign bit copies will
6386 remain relative to that mode, not the inner mode. */
6388 if (GET_MODE_SIZE (GET_MODE (x))
6389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6390 return num_sign_bit_copies (SUBREG_REG (x), mode);
6396 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6397 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6401 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6402 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6405 /* For a smaller object, just ignore the high bits. */
6406 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6407 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6411 return num_sign_bit_copies (XEXP (x, 0), mode);
6413 case ROTATE: case ROTATERT:
6414 /* If we are rotating left by a number of bits less than the number
6415 of sign bit copies, we can just subtract that amount from the
6417 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6418 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6420 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6421 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6422 : bitwidth - INTVAL (XEXP (x, 1))));
6427 /* In general, this subtracts one sign bit copy. But if the value
6428 is known to be positive, the number of sign bit copies is the
6429 same as that of the input. Finally, if the input has just one bit
6430 that might be nonzero, all the bits are copies of the sign bit. */
6431 nonzero = nonzero_bits (XEXP (x, 0), mode);
6435 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6437 && bitwidth <= HOST_BITS_PER_WIDE_INT
6438 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6443 case IOR: case AND: case XOR:
6444 case SMIN: case SMAX: case UMIN: case UMAX:
6445 /* Logical operations will preserve the number of sign-bit copies.
6446 MIN and MAX operations always return one of the operands. */
6447 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6448 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6449 return MIN (num0, num1);
6451 case PLUS: case MINUS:
6452 /* For addition and subtraction, we can have a 1-bit carry. However,
6453 if we are subtracting 1 from a positive number, there will not
6454 be such a carry. Furthermore, if the positive number is known to
6455 be 0 or 1, we know the result is either -1 or 0. */
6457 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6458 && bitwidth <= HOST_BITS_PER_INT)
6460 nonzero = nonzero_bits (XEXP (x, 0), mode);
6461 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6462 return (nonzero == 1 || nonzero == 0 ? bitwidth
6463 : bitwidth - floor_log2 (nonzero) - 1);
6466 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6467 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6468 return MAX (1, MIN (num0, num1) - 1);
6471 /* The number of bits of the product is the sum of the number of
6472 bits of both terms. However, unless one of the terms if known
6473 to be positive, we must allow for an additional bit since negating
6474 a negative number can remove one sign bit copy. */
6476 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6477 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6479 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6481 && bitwidth <= HOST_BITS_PER_INT
6482 && ((nonzero_bits (XEXP (x, 0), mode)
6483 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6484 && (nonzero_bits (XEXP (x, 1), mode)
6485 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6488 return MAX (1, result);
6491 /* The result must be <= the first operand. */
6492 return num_sign_bit_copies (XEXP (x, 0), mode);
6495 /* The result must be <= the scond operand. */
6496 return num_sign_bit_copies (XEXP (x, 1), mode);
6499 /* Similar to unsigned division, except that we have to worry about
6500 the case where the divisor is negative, in which case we have
6502 result = num_sign_bit_copies (XEXP (x, 0), mode);
6504 && bitwidth <= HOST_BITS_PER_WIDE_INT
6505 && (nonzero_bits (XEXP (x, 1), mode)
6506 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6512 result = num_sign_bit_copies (XEXP (x, 1), mode);
6514 && bitwidth <= HOST_BITS_PER_WIDE_INT
6515 && (nonzero_bits (XEXP (x, 1), mode)
6516 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6522 /* Shifts by a constant add to the number of bits equal to the
6524 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6525 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6526 && INTVAL (XEXP (x, 1)) > 0)
6527 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6533 /* Left shifts destroy copies. */
6534 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6535 || INTVAL (XEXP (x, 1)) < 0
6536 || INTVAL (XEXP (x, 1)) >= bitwidth)
6539 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6540 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6543 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6544 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6545 return MIN (num0, num1);
6547 #if STORE_FLAG_VALUE == -1
6548 case EQ: case NE: case GE: case GT: case LE: case LT:
6549 case GEU: case GTU: case LEU: case LTU:
6554 /* If we haven't been able to figure it out by one of the above rules,
6555 see if some of the high-order bits are known to be zero. If so,
6556 count those bits and return one less than that amount. If we can't
6557 safely compute the mask for this mode, always return BITWIDTH. */
6559 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6562 nonzero = nonzero_bits (x, mode);
6563 return (nonzero == GET_MODE_MASK (mode)
6564 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
6567 /* Return the number of "extended" bits there are in X, when interpreted
6568 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6569 unsigned quantities, this is the number of high-order zero bits.
6570 For signed quantities, this is the number of copies of the sign bit
6571 minus 1. In both case, this function returns the number of "spare"
6572 bits. For example, if two quantities for which this function returns
6573 at least 1 are added, the addition is known not to overflow.
6575 This function will always return 0 unless called during combine, which
6576 implies that it must be called from a define_split. */
6579 extended_count (x, mode, unsignedp)
6581 enum machine_mode mode;
6584 if (nonzero_sign_valid == 0)
6588 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6589 && (GET_MODE_BITSIZE (mode) - 1
6590 - floor_log2 (nonzero_bits (x, mode))))
6591 : num_sign_bit_copies (x, mode) - 1);
6594 /* This function is called from `simplify_shift_const' to merge two
6595 outer operations. Specifically, we have already found that we need
6596 to perform operation *POP0 with constant *PCONST0 at the outermost
6597 position. We would now like to also perform OP1 with constant CONST1
6598 (with *POP0 being done last).
6600 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6601 the resulting operation. *PCOMP_P is set to 1 if we would need to
6602 complement the innermost operand, otherwise it is unchanged.
6604 MODE is the mode in which the operation will be done. No bits outside
6605 the width of this mode matter. It is assumed that the width of this mode
6606 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6608 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6609 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6610 result is simply *PCONST0.
6612 If the resulting operation cannot be expressed as one operation, we
6613 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6616 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6617 enum rtx_code *pop0;
6618 HOST_WIDE_INT *pconst0;
6620 HOST_WIDE_INT const1;
6621 enum machine_mode mode;
6624 enum rtx_code op0 = *pop0;
6625 HOST_WIDE_INT const0 = *pconst0;
6627 const0 &= GET_MODE_MASK (mode);
6628 const1 &= GET_MODE_MASK (mode);
6630 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6634 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6637 if (op1 == NIL || op0 == SET)
6640 else if (op0 == NIL)
6641 op0 = op1, const0 = const1;
6643 else if (op0 == op1)
6665 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6666 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6669 /* If the two constants aren't the same, we can't do anything. The
6670 remaining six cases can all be done. */
6671 else if (const0 != const1)
6679 /* (a & b) | b == b */
6681 else /* op1 == XOR */
6682 /* (a ^ b) | b == a | b */
6688 /* (a & b) ^ b == (~a) & b */
6689 op0 = AND, *pcomp_p = 1;
6690 else /* op1 == IOR */
6691 /* (a | b) ^ b == a & ~b */
6692 op0 = AND, *pconst0 = ~ const0;
6697 /* (a | b) & b == b */
6699 else /* op1 == XOR */
6700 /* (a ^ b) & b) == (~a) & b */
6705 /* Check for NO-OP cases. */
6706 const0 &= GET_MODE_MASK (mode);
6708 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6710 else if (const0 == 0 && op0 == AND)
6712 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6721 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6722 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6723 that we started with.
6725 The shift is normally computed in the widest mode we find in VAROP, as
6726 long as it isn't a different number of words than RESULT_MODE. Exceptions
6727 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6730 simplify_shift_const (x, code, result_mode, varop, count)
6733 enum machine_mode result_mode;
6737 enum rtx_code orig_code = code;
6738 int orig_count = count;
6739 enum machine_mode mode = result_mode;
6740 enum machine_mode shift_mode, tmode;
6742 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6743 /* We form (outer_op (code varop count) (outer_const)). */
6744 enum rtx_code outer_op = NIL;
6745 HOST_WIDE_INT outer_const;
6747 int complement_p = 0;
6750 /* If we were given an invalid count, don't do anything except exactly
6751 what was requested. */
6753 if (count < 0 || count > GET_MODE_BITSIZE (mode))
6758 return gen_rtx (code, mode, varop, GEN_INT (count));
6761 /* Unless one of the branches of the `if' in this loop does a `continue',
6762 we will `break' the loop after the `if'. */
6766 /* If we have an operand of (clobber (const_int 0)), just return that
6768 if (GET_CODE (varop) == CLOBBER)
6771 /* If we discovered we had to complement VAROP, leave. Making a NOT
6772 here would cause an infinite loop. */
6776 /* Convert ROTATETRT to ROTATE. */
6777 if (code == ROTATERT)
6778 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6780 /* Canonicalize LSHIFT to ASHIFT. */
6784 /* We need to determine what mode we will do the shift in. If the
6785 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6786 was originally done in. Otherwise, we can do it in MODE, the widest
6787 mode encountered. */
6788 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6790 /* Handle cases where the count is greater than the size of the mode
6791 minus 1. For ASHIFT, use the size minus one as the count (this can
6792 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6793 take the count modulo the size. For other shifts, the result is
6796 Since these shifts are being produced by the compiler by combining
6797 multiple operations, each of which are defined, we know what the
6798 result is supposed to be. */
6800 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6802 if (code == ASHIFTRT)
6803 count = GET_MODE_BITSIZE (shift_mode) - 1;
6804 else if (code == ROTATE || code == ROTATERT)
6805 count %= GET_MODE_BITSIZE (shift_mode);
6808 /* We can't simply return zero because there may be an
6816 /* Negative counts are invalid and should not have been made (a
6817 programmer-specified negative count should have been handled
6822 /* An arithmetic right shift of a quantity known to be -1 or 0
6824 if (code == ASHIFTRT
6825 && (num_sign_bit_copies (varop, shift_mode)
6826 == GET_MODE_BITSIZE (shift_mode)))
6832 /* We simplify the tests below and elsewhere by converting
6833 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6834 `make_compound_operation' will convert it to a ASHIFTRT for
6835 those machines (such as Vax) that don't have a LSHIFTRT. */
6836 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
6838 && ((nonzero_bits (varop, shift_mode)
6839 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
6843 switch (GET_CODE (varop))
6849 new = expand_compound_operation (varop);
6858 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
6859 minus the width of a smaller mode, we can do this with a
6860 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
6861 if ((code == ASHIFTRT || code == LSHIFTRT)
6862 && ! mode_dependent_address_p (XEXP (varop, 0))
6863 && ! MEM_VOLATILE_P (varop)
6864 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6865 MODE_INT, 1)) != BLKmode)
6867 #if BYTES_BIG_ENDIAN
6868 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
6870 new = gen_rtx (MEM, tmode,
6871 plus_constant (XEXP (varop, 0),
6872 count / BITS_PER_UNIT));
6873 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
6874 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
6875 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
6877 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6878 : ZERO_EXTEND, mode, new);
6885 /* Similar to the case above, except that we can only do this if
6886 the resulting mode is the same as that of the underlying
6887 MEM and adjust the address depending on the *bits* endianness
6888 because of the way that bit-field extract insns are defined. */
6889 if ((code == ASHIFTRT || code == LSHIFTRT)
6890 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6891 MODE_INT, 1)) != BLKmode
6892 && tmode == GET_MODE (XEXP (varop, 0)))
6895 new = XEXP (varop, 0);
6897 new = copy_rtx (XEXP (varop, 0));
6898 SUBST (XEXP (new, 0),
6899 plus_constant (XEXP (new, 0),
6900 count / BITS_PER_UNIT));
6903 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6904 : ZERO_EXTEND, mode, new);
6911 /* If VAROP is a SUBREG, strip it as long as the inner operand has
6912 the same number of words as what we've seen so far. Then store
6913 the widest mode in MODE. */
6914 if (subreg_lowpart_p (varop)
6915 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6916 > GET_MODE_SIZE (GET_MODE (varop)))
6917 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6918 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6921 varop = SUBREG_REG (varop);
6922 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
6923 mode = GET_MODE (varop);
6929 /* Some machines use MULT instead of ASHIFT because MULT
6930 is cheaper. But it is still better on those machines to
6931 merge two shifts into one. */
6932 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6933 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6935 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
6936 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
6942 /* Similar, for when divides are cheaper. */
6943 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6944 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6946 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6947 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
6953 /* If we are extracting just the sign bit of an arithmetic right
6954 shift, that shift is not needed. */
6955 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
6957 varop = XEXP (varop, 0);
6961 /* ... fall through ... */
6967 /* Here we have two nested shifts. The result is usually the
6968 AND of a new shift with a mask. We compute the result below. */
6969 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6970 && INTVAL (XEXP (varop, 1)) >= 0
6971 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
6972 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
6973 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6975 enum rtx_code first_code = GET_CODE (varop);
6976 int first_count = INTVAL (XEXP (varop, 1));
6977 unsigned HOST_WIDE_INT mask;
6981 if (first_code == LSHIFT)
6982 first_code = ASHIFT;
6984 /* We have one common special case. We can't do any merging if
6985 the inner code is an ASHIFTRT of a smaller mode. However, if
6986 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
6987 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
6988 we can convert it to
6989 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
6990 This simplifies certain SIGN_EXTEND operations. */
6991 if (code == ASHIFT && first_code == ASHIFTRT
6992 && (GET_MODE_BITSIZE (result_mode)
6993 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
6995 /* C3 has the low-order C1 bits zero. */
6997 mask = (GET_MODE_MASK (mode)
6998 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7000 varop = simplify_and_const_int (NULL_RTX, result_mode,
7001 XEXP (varop, 0), mask);
7002 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7004 count = first_count;
7009 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7010 than C1 high-order bits equal to the sign bit, we can convert
7011 this to either an ASHIFT or a ASHIFTRT depending on the
7014 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7016 if (code == ASHIFTRT && first_code == ASHIFT
7017 && GET_MODE (varop) == shift_mode
7018 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7021 count -= first_count;
7023 count = - count, code = ASHIFT;
7024 varop = XEXP (varop, 0);
7028 /* There are some cases we can't do. If CODE is ASHIFTRT,
7029 we can only do this if FIRST_CODE is also ASHIFTRT.
7031 We can't do the case when CODE is ROTATE and FIRST_CODE is
7034 If the mode of this shift is not the mode of the outer shift,
7035 we can't do this if either shift is ASHIFTRT or ROTATE.
7037 Finally, we can't do any of these if the mode is too wide
7038 unless the codes are the same.
7040 Handle the case where the shift codes are the same
7043 if (code == first_code)
7045 if (GET_MODE (varop) != result_mode
7046 && (code == ASHIFTRT || code == ROTATE))
7049 count += first_count;
7050 varop = XEXP (varop, 0);
7054 if (code == ASHIFTRT
7055 || (code == ROTATE && first_code == ASHIFTRT)
7056 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7057 || (GET_MODE (varop) != result_mode
7058 && (first_code == ASHIFTRT || first_code == ROTATE
7059 || code == ROTATE)))
7062 /* To compute the mask to apply after the shift, shift the
7063 nonzero bits of the inner shift the same way the
7064 outer shift will. */
7066 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7069 = simplify_binary_operation (code, result_mode, mask_rtx,
7072 /* Give up if we can't compute an outer operation to use. */
7074 || GET_CODE (mask_rtx) != CONST_INT
7075 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7077 result_mode, &complement_p))
7080 /* If the shifts are in the same direction, we add the
7081 counts. Otherwise, we subtract them. */
7082 if ((code == ASHIFTRT || code == LSHIFTRT)
7083 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7084 count += first_count;
7086 count -= first_count;
7088 /* If COUNT is positive, the new shift is usually CODE,
7089 except for the two exceptions below, in which case it is
7090 FIRST_CODE. If the count is negative, FIRST_CODE should
7093 && ((first_code == ROTATE && code == ASHIFT)
7094 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7097 code = first_code, count = - count;
7099 varop = XEXP (varop, 0);
7103 /* If we have (A << B << C) for any shift, we can convert this to
7104 (A << C << B). This wins if A is a constant. Only try this if
7105 B is not a constant. */
7107 else if (GET_CODE (varop) == code
7108 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7110 = simplify_binary_operation (code, mode,
7114 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7121 /* Make this fit the case below. */
7122 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7123 GEN_INT (GET_MODE_MASK (mode)));
7129 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7130 with C the size of VAROP - 1 and the shift is logical if
7131 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7132 we have an (le X 0) operation. If we have an arithmetic shift
7133 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7134 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7136 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7137 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7138 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7139 && (code == LSHIFTRT || code == ASHIFTRT)
7140 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7141 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7144 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7147 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7148 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7153 /* If we have (shift (logical)), move the logical to the outside
7154 to allow it to possibly combine with another logical and the
7155 shift to combine with another shift. This also canonicalizes to
7156 what a ZERO_EXTRACT looks like. Also, some machines have
7157 (and (shift)) insns. */
7159 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7160 && (new = simplify_binary_operation (code, result_mode,
7162 GEN_INT (count))) != 0
7163 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7164 INTVAL (new), result_mode, &complement_p))
7166 varop = XEXP (varop, 0);
7170 /* If we can't do that, try to simplify the shift in each arm of the
7171 logical expression, make a new logical expression, and apply
7172 the inverse distributive law. */
7174 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7175 XEXP (varop, 0), count);
7176 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7177 XEXP (varop, 1), count);
7179 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7180 varop = apply_distributive_law (varop);
7187 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7188 says that the sign bit can be tested, FOO has mode MODE, C is
7189 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7192 && XEXP (varop, 1) == const0_rtx
7193 && GET_MODE (XEXP (varop, 0)) == result_mode
7194 && count == GET_MODE_BITSIZE (result_mode) - 1
7195 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7196 && ((STORE_FLAG_VALUE
7197 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7198 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7199 && merge_outer_ops (&outer_op, &outer_const, XOR,
7200 (HOST_WIDE_INT) 1, result_mode,
7203 varop = XEXP (varop, 0);
7210 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7211 than the number of bits in the mode is equivalent to A. */
7212 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7213 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7215 varop = XEXP (varop, 0);
7220 /* NEG commutes with ASHIFT since it is multiplication. Move the
7221 NEG outside to allow shifts to combine. */
7223 && merge_outer_ops (&outer_op, &outer_const, NEG,
7224 (HOST_WIDE_INT) 0, result_mode,
7227 varop = XEXP (varop, 0);
7233 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7234 is one less than the number of bits in the mode is
7235 equivalent to (xor A 1). */
7236 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7237 && XEXP (varop, 1) == constm1_rtx
7238 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7239 && merge_outer_ops (&outer_op, &outer_const, XOR,
7240 (HOST_WIDE_INT) 1, result_mode,
7244 varop = XEXP (varop, 0);
7248 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7249 that might be nonzero in BAR are those being shifted out and those
7250 bits are known zero in FOO, we can replace the PLUS with FOO.
7251 Similarly in the other operand order. This code occurs when
7252 we are computing the size of a variable-size array. */
7254 if ((code == ASHIFTRT || code == LSHIFTRT)
7255 && count < HOST_BITS_PER_WIDE_INT
7256 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7257 && (nonzero_bits (XEXP (varop, 1), result_mode)
7258 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7260 varop = XEXP (varop, 0);
7263 else if ((code == ASHIFTRT || code == LSHIFTRT)
7264 && count < HOST_BITS_PER_WIDE_INT
7265 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7266 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7268 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7269 & nonzero_bits (XEXP (varop, 1),
7272 varop = XEXP (varop, 1);
7276 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7278 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7279 && (new = simplify_binary_operation (ASHIFT, result_mode,
7281 GEN_INT (count))) != 0
7282 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7283 INTVAL (new), result_mode, &complement_p))
7285 varop = XEXP (varop, 0);
7291 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7292 with C the size of VAROP - 1 and the shift is logical if
7293 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7294 we have a (gt X 0) operation. If the shift is arithmetic with
7295 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7296 we have a (neg (gt X 0)) operation. */
7298 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7299 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7300 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7301 && (code == LSHIFTRT || code == ASHIFTRT)
7302 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7303 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7304 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7307 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7310 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7311 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7321 /* We need to determine what mode to do the shift in. If the shift is
7322 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7323 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7324 The code we care about is that of the shift that will actually be done,
7325 not the shift that was originally requested. */
7326 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7328 /* We have now finished analyzing the shift. The result should be
7329 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7330 OUTER_OP is non-NIL, it is an operation that needs to be applied
7331 to the result of the shift. OUTER_CONST is the relevant constant,
7332 but we must turn off all bits turned off in the shift.
7334 If we were passed a value for X, see if we can use any pieces of
7335 it. If not, make new rtx. */
7337 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7338 && GET_CODE (XEXP (x, 1)) == CONST_INT
7339 && INTVAL (XEXP (x, 1)) == count)
7340 const_rtx = XEXP (x, 1);
7342 const_rtx = GEN_INT (count);
7344 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7345 && GET_MODE (XEXP (x, 0)) == shift_mode
7346 && SUBREG_REG (XEXP (x, 0)) == varop)
7347 varop = XEXP (x, 0);
7348 else if (GET_MODE (varop) != shift_mode)
7349 varop = gen_lowpart_for_combine (shift_mode, varop);
7351 /* If we can't make the SUBREG, try to return what we were given. */
7352 if (GET_CODE (varop) == CLOBBER)
7353 return x ? x : varop;
7355 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7360 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7361 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7363 SUBST (XEXP (x, 0), varop);
7364 SUBST (XEXP (x, 1), const_rtx);
7367 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7368 turn off all the bits that the shift would have turned off. */
7369 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7370 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7371 GET_MODE_MASK (result_mode) >> orig_count);
7373 /* Do the remainder of the processing in RESULT_MODE. */
7374 x = gen_lowpart_for_combine (result_mode, x);
7376 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7379 x = gen_unary (NOT, result_mode, x);
7381 if (outer_op != NIL)
7383 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7384 outer_const &= GET_MODE_MASK (result_mode);
7386 if (outer_op == AND)
7387 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7388 else if (outer_op == SET)
7389 /* This means that we have determined that the result is
7390 equivalent to a constant. This should be rare. */
7391 x = GEN_INT (outer_const);
7392 else if (GET_RTX_CLASS (outer_op) == '1')
7393 x = gen_unary (outer_op, result_mode, x);
7395 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7401 /* Like recog, but we receive the address of a pointer to a new pattern.
7402 We try to match the rtx that the pointer points to.
7403 If that fails, we may try to modify or replace the pattern,
7404 storing the replacement into the same pointer object.
7406 Modifications include deletion or addition of CLOBBERs.
7408 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7409 the CLOBBERs are placed.
7411 The value is the final insn code from the pattern ultimately matched,
7415 recog_for_combine (pnewpat, insn, pnotes)
7420 register rtx pat = *pnewpat;
7421 int insn_code_number;
7422 int num_clobbers_to_add = 0;
7426 /* Is the result of combination a valid instruction? */
7427 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7429 /* If it isn't, there is the possibility that we previously had an insn
7430 that clobbered some register as a side effect, but the combined
7431 insn doesn't need to do that. So try once more without the clobbers
7432 unless this represents an ASM insn. */
7434 if (insn_code_number < 0 && ! check_asm_operands (pat)
7435 && GET_CODE (pat) == PARALLEL)
7439 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7440 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7443 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7447 SUBST_INT (XVECLEN (pat, 0), pos);
7450 pat = XVECEXP (pat, 0, 0);
7452 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7455 /* If we had any clobbers to add, make a new pattern than contains
7456 them. Then check to make sure that all of them are dead. */
7457 if (num_clobbers_to_add)
7459 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7460 gen_rtvec (GET_CODE (pat) == PARALLEL
7461 ? XVECLEN (pat, 0) + num_clobbers_to_add
7462 : num_clobbers_to_add + 1));
7464 if (GET_CODE (pat) == PARALLEL)
7465 for (i = 0; i < XVECLEN (pat, 0); i++)
7466 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7468 XVECEXP (newpat, 0, 0) = pat;
7470 add_clobbers (newpat, insn_code_number);
7472 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7473 i < XVECLEN (newpat, 0); i++)
7475 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7476 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7478 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7479 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7487 return insn_code_number;
7490 /* Like gen_lowpart but for use by combine. In combine it is not possible
7491 to create any new pseudoregs. However, it is safe to create
7492 invalid memory addresses, because combine will try to recognize
7493 them and all they will do is make the combine attempt fail.
7495 If for some reason this cannot do its job, an rtx
7496 (clobber (const_int 0)) is returned.
7497 An insn containing that will not be recognized. */
7502 gen_lowpart_for_combine (mode, x)
7503 enum machine_mode mode;
7508 if (GET_MODE (x) == mode)
7511 /* We can only support MODE being wider than a word if X is a
7512 constant integer or has a mode the same size. */
7514 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7515 && ! ((GET_MODE (x) == VOIDmode
7516 && (GET_CODE (x) == CONST_INT
7517 || GET_CODE (x) == CONST_DOUBLE))
7518 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7519 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7521 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7522 won't know what to do. So we will strip off the SUBREG here and
7523 process normally. */
7524 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7527 if (GET_MODE (x) == mode)
7531 result = gen_lowpart_common (mode, x);
7535 if (GET_CODE (x) == MEM)
7537 register int offset = 0;
7540 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7542 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7543 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7545 /* If we want to refer to something bigger than the original memref,
7546 generate a perverse subreg instead. That will force a reload
7547 of the original memref X. */
7548 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7549 return gen_rtx (SUBREG, mode, x, 0);
7551 #if WORDS_BIG_ENDIAN
7552 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7553 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7555 #if BYTES_BIG_ENDIAN
7556 /* Adjust the address so that the address-after-the-data
7558 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7559 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7561 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7562 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7563 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7564 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7568 /* If X is a comparison operator, rewrite it in a new mode. This
7569 probably won't match, but may allow further simplifications. */
7570 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7571 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7573 /* If we couldn't simplify X any other way, just enclose it in a
7574 SUBREG. Normally, this SUBREG won't match, but some patterns may
7575 include an explicit SUBREG or we may simplify it further in combine. */
7580 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7581 word = ((GET_MODE_SIZE (GET_MODE (x))
7582 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7584 return gen_rtx (SUBREG, mode, x, word);
7588 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7589 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7591 If the identical expression was previously in the insn (in the undobuf),
7592 it will be returned. Only if it is not found will a new expression
7597 gen_rtx_combine (va_alist)
7602 enum machine_mode mode;
7610 code = va_arg (p, enum rtx_code);
7611 mode = va_arg (p, enum machine_mode);
7612 n_args = GET_RTX_LENGTH (code);
7613 fmt = GET_RTX_FORMAT (code);
7615 if (n_args == 0 || n_args > 3)
7618 /* Get each arg and verify that it is supposed to be an expression. */
7619 for (j = 0; j < n_args; j++)
7624 args[j] = va_arg (p, rtx);
7627 /* See if this is in undobuf. Be sure we don't use objects that came
7628 from another insn; this could produce circular rtl structures. */
7630 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7631 if (!undobuf.undo[i].is_int
7632 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7633 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7635 for (j = 0; j < n_args; j++)
7636 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7640 return undobuf.undo[i].old_contents.rtx;
7643 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7644 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7645 rt = rtx_alloc (code);
7646 PUT_MODE (rt, mode);
7647 XEXP (rt, 0) = args[0];
7650 XEXP (rt, 1) = args[1];
7652 XEXP (rt, 2) = args[2];
7657 /* These routines make binary and unary operations by first seeing if they
7658 fold; if not, a new expression is allocated. */
7661 gen_binary (code, mode, op0, op1)
7663 enum machine_mode mode;
7669 if (GET_RTX_CLASS (code) == 'c'
7670 && (GET_CODE (op0) == CONST_INT
7671 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7672 tem = op0, op0 = op1, op1 = tem;
7674 if (GET_RTX_CLASS (code) == '<')
7676 enum machine_mode op_mode = GET_MODE (op0);
7677 if (op_mode == VOIDmode)
7678 op_mode = GET_MODE (op1);
7679 result = simplify_relational_operation (code, op_mode, op0, op1);
7682 result = simplify_binary_operation (code, mode, op0, op1);
7687 /* Put complex operands first and constants second. */
7688 if (GET_RTX_CLASS (code) == 'c'
7689 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7690 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7691 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7692 || (GET_CODE (op0) == SUBREG
7693 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7694 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7695 return gen_rtx_combine (code, mode, op1, op0);
7697 return gen_rtx_combine (code, mode, op0, op1);
7701 gen_unary (code, mode, op0)
7703 enum machine_mode mode;
7706 rtx result = simplify_unary_operation (code, mode, op0, mode);
7711 return gen_rtx_combine (code, mode, op0);
7714 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7715 comparison code that will be tested.
7717 The result is a possibly different comparison code to use. *POP0 and
7718 *POP1 may be updated.
7720 It is possible that we might detect that a comparison is either always
7721 true or always false. However, we do not perform general constant
7722 folding in combine, so this knowledge isn't useful. Such tautologies
7723 should have been detected earlier. Hence we ignore all such cases. */
7725 static enum rtx_code
7726 simplify_comparison (code, pop0, pop1)
7735 enum machine_mode mode, tmode;
7737 /* Try a few ways of applying the same transformation to both operands. */
7740 /* If both operands are the same constant shift, see if we can ignore the
7741 shift. We can if the shift is a rotate or if the bits shifted out of
7742 this shift are known to be zero for both inputs and if the type of
7743 comparison is compatible with the shift. */
7744 if (GET_CODE (op0) == GET_CODE (op1)
7745 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
7746 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7747 || ((GET_CODE (op0) == LSHIFTRT
7748 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7749 && (code != GT && code != LT && code != GE && code != LE))
7750 || (GET_CODE (op0) == ASHIFTRT
7751 && (code != GTU && code != LTU
7752 && code != GEU && code != GEU)))
7753 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7754 && INTVAL (XEXP (op0, 1)) >= 0
7755 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
7756 && XEXP (op0, 1) == XEXP (op1, 1))
7758 enum machine_mode mode = GET_MODE (op0);
7759 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7760 int shift_count = INTVAL (XEXP (op0, 1));
7762 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7763 mask &= (mask >> shift_count) << shift_count;
7764 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7765 mask = (mask & (mask << shift_count)) >> shift_count;
7767 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7768 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7769 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7774 /* If both operands are AND's of a paradoxical SUBREG by constant, the
7775 SUBREGs are of the same mode, and, in both cases, the AND would
7776 be redundant if the comparison was done in the narrower mode,
7777 do the comparison in the narrower mode (e.g., we are AND'ing with 1
7778 and the operand's possibly nonzero bits are 0xffffff01; in that case
7779 if we only care about QImode, we don't need the AND). This case
7780 occurs if the output mode of an scc insn is not SImode and
7781 STORE_FLAG_VALUE == 1 (e.g., the 386). */
7783 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7784 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7785 && GET_CODE (XEXP (op1, 1)) == CONST_INT
7786 && GET_CODE (XEXP (op0, 0)) == SUBREG
7787 && GET_CODE (XEXP (op1, 0)) == SUBREG
7788 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7789 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7790 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7791 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7792 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7793 <= HOST_BITS_PER_WIDE_INT)
7794 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
7795 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7796 & ~ INTVAL (XEXP (op0, 1))) == 0
7797 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
7798 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7799 & ~ INTVAL (XEXP (op1, 1))) == 0)
7801 op0 = SUBREG_REG (XEXP (op0, 0));
7802 op1 = SUBREG_REG (XEXP (op1, 0));
7804 /* the resulting comparison is always unsigned since we masked off
7805 the original sign bit. */
7806 code = unsigned_condition (code);
7812 /* If the first operand is a constant, swap the operands and adjust the
7813 comparison code appropriately. */
7814 if (CONSTANT_P (op0))
7816 tem = op0, op0 = op1, op1 = tem;
7817 code = swap_condition (code);
7820 /* We now enter a loop during which we will try to simplify the comparison.
7821 For the most part, we only are concerned with comparisons with zero,
7822 but some things may really be comparisons with zero but not start
7823 out looking that way. */
7825 while (GET_CODE (op1) == CONST_INT)
7827 enum machine_mode mode = GET_MODE (op0);
7828 int mode_width = GET_MODE_BITSIZE (mode);
7829 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7830 int equality_comparison_p;
7831 int sign_bit_comparison_p;
7832 int unsigned_comparison_p;
7833 HOST_WIDE_INT const_op;
7835 /* We only want to handle integral modes. This catches VOIDmode,
7836 CCmode, and the floating-point modes. An exception is that we
7837 can handle VOIDmode if OP0 is a COMPARE or a comparison
7840 if (GET_MODE_CLASS (mode) != MODE_INT
7841 && ! (mode == VOIDmode
7842 && (GET_CODE (op0) == COMPARE
7843 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
7846 /* Get the constant we are comparing against and turn off all bits
7847 not on in our mode. */
7848 const_op = INTVAL (op1);
7849 if (mode_width <= HOST_BITS_PER_WIDE_INT)
7852 /* If we are comparing against a constant power of two and the value
7853 being compared can only have that single bit nonzero (e.g., it was
7854 `and'ed with that bit), we can replace this with a comparison
7857 && (code == EQ || code == NE || code == GE || code == GEU
7858 || code == LT || code == LTU)
7859 && mode_width <= HOST_BITS_PER_WIDE_INT
7860 && exact_log2 (const_op) >= 0
7861 && nonzero_bits (op0, mode) == const_op)
7863 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
7864 op1 = const0_rtx, const_op = 0;
7867 /* Similarly, if we are comparing a value known to be either -1 or
7868 0 with -1, change it to the opposite comparison against zero. */
7871 && (code == EQ || code == NE || code == GT || code == LE
7872 || code == GEU || code == LTU)
7873 && num_sign_bit_copies (op0, mode) == mode_width)
7875 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
7876 op1 = const0_rtx, const_op = 0;
7879 /* Do some canonicalizations based on the comparison code. We prefer
7880 comparisons against zero and then prefer equality comparisons.
7881 If we can reduce the size of a constant, we will do that too. */
7886 /* < C is equivalent to <= (C - 1) */
7890 op1 = GEN_INT (const_op);
7892 /* ... fall through to LE case below. */
7898 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
7902 op1 = GEN_INT (const_op);
7906 /* If we are doing a <= 0 comparison on a value known to have
7907 a zero sign bit, we can replace this with == 0. */
7908 else if (const_op == 0
7909 && mode_width <= HOST_BITS_PER_WIDE_INT
7910 && (nonzero_bits (op0, mode)
7911 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7916 /* >= C is equivalent to > (C - 1). */
7920 op1 = GEN_INT (const_op);
7922 /* ... fall through to GT below. */
7928 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
7932 op1 = GEN_INT (const_op);
7936 /* If we are doing a > 0 comparison on a value known to have
7937 a zero sign bit, we can replace this with != 0. */
7938 else if (const_op == 0
7939 && mode_width <= HOST_BITS_PER_WIDE_INT
7940 && (nonzero_bits (op0, mode)
7941 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7946 /* < C is equivalent to <= (C - 1). */
7950 op1 = GEN_INT (const_op);
7952 /* ... fall through ... */
7955 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
7956 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7958 const_op = 0, op1 = const0_rtx;
7966 /* unsigned <= 0 is equivalent to == 0 */
7970 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
7971 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7973 const_op = 0, op1 = const0_rtx;
7979 /* >= C is equivalent to < (C - 1). */
7983 op1 = GEN_INT (const_op);
7985 /* ... fall through ... */
7988 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
7989 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7991 const_op = 0, op1 = const0_rtx;
7998 /* unsigned > 0 is equivalent to != 0 */
8002 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8003 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8005 const_op = 0, op1 = const0_rtx;
8011 /* Compute some predicates to simplify code below. */
8013 equality_comparison_p = (code == EQ || code == NE);
8014 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8015 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8018 /* Now try cases based on the opcode of OP0. If none of the cases
8019 does a "continue", we exit this loop immediately after the
8022 switch (GET_CODE (op0))
8025 /* If we are extracting a single bit from a variable position in
8026 a constant that has only a single bit set and are comparing it
8027 with zero, we can convert this into an equality comparison
8028 between the position and the location of the single bit. We can't
8029 do this if bit endian and we don't have an extzv since we then
8030 can't know what mode to use for the endianness adjustment. */
8032 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8033 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8034 && XEXP (op0, 1) == const1_rtx
8035 && equality_comparison_p && const_op == 0
8036 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8039 i = (GET_MODE_BITSIZE
8040 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8043 op0 = XEXP (op0, 2);
8047 /* Result is nonzero iff shift count is equal to I. */
8048 code = reverse_condition (code);
8053 /* ... fall through ... */
8056 tem = expand_compound_operation (op0);
8065 /* If testing for equality, we can take the NOT of the constant. */
8066 if (equality_comparison_p
8067 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8069 op0 = XEXP (op0, 0);
8074 /* If just looking at the sign bit, reverse the sense of the
8076 if (sign_bit_comparison_p)
8078 op0 = XEXP (op0, 0);
8079 code = (code == GE ? LT : GE);
8085 /* If testing for equality, we can take the NEG of the constant. */
8086 if (equality_comparison_p
8087 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8089 op0 = XEXP (op0, 0);
8094 /* The remaining cases only apply to comparisons with zero. */
8098 /* When X is ABS or is known positive,
8099 (neg X) is < 0 if and only if X != 0. */
8101 if (sign_bit_comparison_p
8102 && (GET_CODE (XEXP (op0, 0)) == ABS
8103 || (mode_width <= HOST_BITS_PER_WIDE_INT
8104 && (nonzero_bits (XEXP (op0, 0), mode)
8105 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8107 op0 = XEXP (op0, 0);
8108 code = (code == LT ? NE : EQ);
8112 /* If we have NEG of something whose two high-order bits are the
8113 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8114 if (num_sign_bit_copies (op0, mode) >= 2)
8116 op0 = XEXP (op0, 0);
8117 code = swap_condition (code);
8123 /* If we are testing equality and our count is a constant, we
8124 can perform the inverse operation on our RHS. */
8125 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8126 && (tem = simplify_binary_operation (ROTATERT, mode,
8127 op1, XEXP (op0, 1))) != 0)
8129 op0 = XEXP (op0, 0);
8134 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8135 a particular bit. Convert it to an AND of a constant of that
8136 bit. This will be converted into a ZERO_EXTRACT. */
8137 if (const_op == 0 && sign_bit_comparison_p
8138 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8139 && mode_width <= HOST_BITS_PER_WIDE_INT)
8141 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8144 - INTVAL (XEXP (op0, 1)))));
8145 code = (code == LT ? NE : EQ);
8149 /* ... fall through ... */
8152 /* ABS is ignorable inside an equality comparison with zero. */
8153 if (const_op == 0 && equality_comparison_p)
8155 op0 = XEXP (op0, 0);
8162 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8163 to (compare FOO CONST) if CONST fits in FOO's mode and we
8164 are either testing inequality or have an unsigned comparison
8165 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8166 if (! unsigned_comparison_p
8167 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8168 <= HOST_BITS_PER_WIDE_INT)
8169 && ((unsigned HOST_WIDE_INT) const_op
8170 < (((HOST_WIDE_INT) 1
8171 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8173 op0 = XEXP (op0, 0);
8179 /* Check for the case where we are comparing A - C1 with C2,
8180 both constants are smaller than 1/2 the maxium positive
8181 value in MODE, and the comparison is equality or unsigned.
8182 In that case, if A is either zero-extended to MODE or has
8183 sufficient sign bits so that the high-order bit in MODE
8184 is a copy of the sign in the inner mode, we can prove that it is
8185 safe to do the operation in the wider mode. This simplifies
8186 many range checks. */
8188 if (mode_width <= HOST_BITS_PER_WIDE_INT
8189 && subreg_lowpart_p (op0)
8190 && GET_CODE (SUBREG_REG (op0)) == PLUS
8191 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8192 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8193 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8194 < GET_MODE_MASK (mode) / 2)
8195 && (unsigned) const_op < GET_MODE_MASK (mode) / 2
8196 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8197 GET_MODE (SUBREG_REG (op0)))
8198 & ~ GET_MODE_MASK (mode))
8199 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8200 GET_MODE (SUBREG_REG (op0)))
8201 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8202 - GET_MODE_BITSIZE (mode)))))
8204 op0 = SUBREG_REG (op0);
8208 /* If the inner mode is narrower and we are extracting the low part,
8209 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8210 if (subreg_lowpart_p (op0)
8211 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8212 /* Fall through */ ;
8216 /* ... fall through ... */
8219 if ((unsigned_comparison_p || equality_comparison_p)
8220 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8221 <= HOST_BITS_PER_WIDE_INT)
8222 && ((unsigned HOST_WIDE_INT) const_op
8223 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8225 op0 = XEXP (op0, 0);
8231 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
8232 this for equality comparisons due to pathological cases involving
8234 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8235 && (tem = simplify_binary_operation (MINUS, mode, op1,
8236 XEXP (op0, 1))) != 0)
8238 op0 = XEXP (op0, 0);
8243 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8244 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8245 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8247 op0 = XEXP (XEXP (op0, 0), 0);
8248 code = (code == LT ? EQ : NE);
8254 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8255 of bits in X minus 1, is one iff X > 0. */
8256 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8257 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8258 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8259 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8261 op0 = XEXP (op0, 1);
8262 code = (code == GE ? LE : GT);
8268 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8269 if C is zero or B is a constant. */
8270 if (equality_comparison_p
8271 && 0 != (tem = simplify_binary_operation (XOR, mode,
8272 XEXP (op0, 1), op1)))
8274 op0 = XEXP (op0, 0);
8281 case LT: case LTU: case LE: case LEU:
8282 case GT: case GTU: case GE: case GEU:
8283 /* We can't do anything if OP0 is a condition code value, rather
8284 than an actual data value. */
8287 || XEXP (op0, 0) == cc0_rtx
8289 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8292 /* Get the two operands being compared. */
8293 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8294 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8296 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8298 /* Check for the cases where we simply want the result of the
8299 earlier test or the opposite of that result. */
8301 || (code == EQ && reversible_comparison_p (op0))
8302 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8303 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8304 && (STORE_FLAG_VALUE
8305 & (((HOST_WIDE_INT) 1
8306 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8308 || (code == GE && reversible_comparison_p (op0)))))
8310 code = (code == LT || code == NE
8311 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8312 op0 = tem, op1 = tem1;
8318 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8320 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8321 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8322 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8324 op0 = XEXP (op0, 1);
8325 code = (code == GE ? GT : LE);
8331 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8332 will be converted to a ZERO_EXTRACT later. */
8333 if (const_op == 0 && equality_comparison_p
8334 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8335 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8336 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8338 op0 = simplify_and_const_int
8339 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8341 XEXP (XEXP (op0, 0), 1)),
8346 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8347 zero and X is a comparison and C1 and C2 describe only bits set
8348 in STORE_FLAG_VALUE, we can compare with X. */
8349 if (const_op == 0 && equality_comparison_p
8350 && mode_width <= HOST_BITS_PER_WIDE_INT
8351 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8352 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8353 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8354 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8355 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8357 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8358 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8359 if ((~ STORE_FLAG_VALUE & mask) == 0
8360 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8361 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8362 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8364 op0 = XEXP (XEXP (op0, 0), 0);
8369 /* If we are doing an equality comparison of an AND of a bit equal
8370 to the sign bit, replace this with a LT or GE comparison of
8371 the underlying value. */
8372 if (equality_comparison_p
8374 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8375 && mode_width <= HOST_BITS_PER_WIDE_INT
8376 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8377 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8379 op0 = XEXP (op0, 0);
8380 code = (code == EQ ? GE : LT);
8384 /* If this AND operation is really a ZERO_EXTEND from a narrower
8385 mode, the constant fits within that mode, and this is either an
8386 equality or unsigned comparison, try to do this comparison in
8387 the narrower mode. */
8388 if ((equality_comparison_p || unsigned_comparison_p)
8389 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8390 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8391 & GET_MODE_MASK (mode))
8393 && const_op >> i == 0
8394 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8396 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8403 /* If we have (compare (xshift FOO N) (const_int C)) and
8404 the high order N bits of FOO (N+1 if an inequality comparison)
8405 are known to be zero, we can do this by comparing FOO with C
8406 shifted right N bits so long as the low-order N bits of C are
8408 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8409 && INTVAL (XEXP (op0, 1)) >= 0
8410 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8411 < HOST_BITS_PER_WIDE_INT)
8413 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8414 && mode_width <= HOST_BITS_PER_WIDE_INT
8415 && (nonzero_bits (XEXP (op0, 0), mode)
8416 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8417 + ! equality_comparison_p))) == 0)
8419 const_op >>= INTVAL (XEXP (op0, 1));
8420 op1 = GEN_INT (const_op);
8421 op0 = XEXP (op0, 0);
8425 /* If we are doing a sign bit comparison, it means we are testing
8426 a particular bit. Convert it to the appropriate AND. */
8427 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8428 && mode_width <= HOST_BITS_PER_WIDE_INT)
8430 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8433 - INTVAL (XEXP (op0, 1)))));
8434 code = (code == LT ? NE : EQ);
8438 /* If this an equality comparison with zero and we are shifting
8439 the low bit to the sign bit, we can convert this to an AND of the
8441 if (const_op == 0 && equality_comparison_p
8442 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8443 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8445 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8452 /* If this is an equality comparison with zero, we can do this
8453 as a logical shift, which might be much simpler. */
8454 if (equality_comparison_p && const_op == 0
8455 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8457 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8459 INTVAL (XEXP (op0, 1)));
8463 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8464 do the comparison in a narrower mode. */
8465 if (! unsigned_comparison_p
8466 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8467 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8468 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8469 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8470 MODE_INT, 1)) != BLKmode
8471 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8472 || ((unsigned HOST_WIDE_INT) - const_op
8473 <= GET_MODE_MASK (tmode))))
8475 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8479 /* ... fall through ... */
8481 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8482 the low order N bits of FOO are known to be zero, we can do this
8483 by comparing FOO with C shifted left N bits so long as no
8485 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8486 && INTVAL (XEXP (op0, 1)) >= 0
8487 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8488 && mode_width <= HOST_BITS_PER_WIDE_INT
8489 && (nonzero_bits (XEXP (op0, 0), mode)
8490 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8492 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8495 const_op <<= INTVAL (XEXP (op0, 1));
8496 op1 = GEN_INT (const_op);
8497 op0 = XEXP (op0, 0);
8501 /* If we are using this shift to extract just the sign bit, we
8502 can replace this with an LT or GE comparison. */
8504 && (equality_comparison_p || sign_bit_comparison_p)
8505 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8506 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8508 op0 = XEXP (op0, 0);
8509 code = (code == NE || code == GT ? LT : GE);
8518 /* Now make any compound operations involved in this comparison. Then,
8519 check for an outmost SUBREG on OP0 that isn't doing anything or is
8520 paradoxical. The latter case can only occur when it is known that the
8521 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8522 We can never remove a SUBREG for a non-equality comparison because the
8523 sign bit is in a different place in the underlying object. */
8525 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8526 op1 = make_compound_operation (op1, SET);
8528 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8529 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8530 && (code == NE || code == EQ)
8531 && ((GET_MODE_SIZE (GET_MODE (op0))
8532 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8534 op0 = SUBREG_REG (op0);
8535 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8538 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8539 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8540 && (code == NE || code == EQ)
8541 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8542 <= HOST_BITS_PER_WIDE_INT)
8543 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8544 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8545 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8547 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
8548 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8549 op0 = SUBREG_REG (op0), op1 = tem;
8551 /* We now do the opposite procedure: Some machines don't have compare
8552 insns in all modes. If OP0's mode is an integer mode smaller than a
8553 word and we can't do a compare in that mode, see if there is a larger
8554 mode for which we can do the compare. There are a number of cases in
8555 which we can use the wider mode. */
8557 mode = GET_MODE (op0);
8558 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8559 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8560 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8561 for (tmode = GET_MODE_WIDER_MODE (mode);
8563 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8564 tmode = GET_MODE_WIDER_MODE (tmode))
8565 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8567 /* If the only nonzero bits in OP0 and OP1 are those in the
8568 narrower mode and this is an equality or unsigned comparison,
8569 we can use the wider mode. Similarly for sign-extended
8570 values and equality or signed comparisons. */
8571 if (((code == EQ || code == NE
8572 || code == GEU || code == GTU || code == LEU || code == LTU)
8573 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
8574 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
8575 || ((code == EQ || code == NE
8576 || code == GE || code == GT || code == LE || code == LT)
8577 && (num_sign_bit_copies (op0, tmode)
8578 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8579 && (num_sign_bit_copies (op1, tmode)
8580 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8582 op0 = gen_lowpart_for_combine (tmode, op0);
8583 op1 = gen_lowpart_for_combine (tmode, op1);
8587 /* If this is a test for negative, we can make an explicit
8588 test of the sign bit. */
8590 if (op1 == const0_rtx && (code == LT || code == GE)
8591 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8593 op0 = gen_binary (AND, tmode,
8594 gen_lowpart_for_combine (tmode, op0),
8595 GEN_INT ((HOST_WIDE_INT) 1
8596 << (GET_MODE_BITSIZE (mode) - 1)));
8597 code = (code == LT) ? NE : EQ;
8608 /* Return 1 if we know that X, a comparison operation, is not operating
8609 on a floating-point value or is EQ or NE, meaning that we can safely
8613 reversible_comparison_p (x)
8616 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8617 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8620 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8626 x = get_last_value (XEXP (x, 0));
8627 return (x && GET_CODE (x) == COMPARE
8628 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8634 /* Utility function for following routine. Called when X is part of a value
8635 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8636 for each register mentioned. Similar to mention_regs in cse.c */
8639 update_table_tick (x)
8642 register enum rtx_code code = GET_CODE (x);
8643 register char *fmt = GET_RTX_FORMAT (code);
8648 int regno = REGNO (x);
8649 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8650 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8652 for (i = regno; i < endregno; i++)
8653 reg_last_set_table_tick[i] = label_tick;
8658 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8659 /* Note that we can't have an "E" in values stored; see
8660 get_last_value_validate. */
8662 update_table_tick (XEXP (x, i));
8665 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8666 are saying that the register is clobbered and we no longer know its
8667 value. If INSN is zero, don't update reg_last_set; this is only permitted
8668 with VALUE also zero and is used to invalidate the register. */
8671 record_value_for_reg (reg, insn, value)
8676 int regno = REGNO (reg);
8677 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8678 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8681 /* If VALUE contains REG and we have a previous value for REG, substitute
8682 the previous value. */
8683 if (value && insn && reg_overlap_mentioned_p (reg, value))
8687 /* Set things up so get_last_value is allowed to see anything set up to
8689 subst_low_cuid = INSN_CUID (insn);
8690 tem = get_last_value (reg);
8693 value = replace_rtx (copy_rtx (value), reg, tem);
8696 /* For each register modified, show we don't know its value, that
8697 its value has been updated, and that we don't know the location of
8698 the death of the register. */
8699 for (i = regno; i < endregno; i ++)
8702 reg_last_set[i] = insn;
8703 reg_last_set_value[i] = 0;
8704 reg_last_death[i] = 0;
8707 /* Mark registers that are being referenced in this value. */
8709 update_table_tick (value);
8711 /* Now update the status of each register being set.
8712 If someone is using this register in this block, set this register
8713 to invalid since we will get confused between the two lives in this
8714 basic block. This makes using this register always invalid. In cse, we
8715 scan the table to invalidate all entries using this register, but this
8716 is too much work for us. */
8718 for (i = regno; i < endregno; i++)
8720 reg_last_set_label[i] = label_tick;
8721 if (value && reg_last_set_table_tick[i] == label_tick)
8722 reg_last_set_invalid[i] = 1;
8724 reg_last_set_invalid[i] = 0;
8727 /* The value being assigned might refer to X (like in "x++;"). In that
8728 case, we must replace it with (clobber (const_int 0)) to prevent
8730 if (value && ! get_last_value_validate (&value,
8731 reg_last_set_label[regno], 0))
8733 value = copy_rtx (value);
8734 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8738 /* For the main register being modified, update the value. */
8739 reg_last_set_value[regno] = value;
8743 /* Used for communication between the following two routines. */
8744 static rtx record_dead_insn;
8746 /* Called via note_stores from record_dead_and_set_regs to handle one
8747 SET or CLOBBER in an insn. */
8750 record_dead_and_set_regs_1 (dest, setter)
8753 if (GET_CODE (dest) == REG)
8755 /* If we are setting the whole register, we know its value. Otherwise
8756 show that we don't know the value. We can handle SUBREG in
8758 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8759 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8760 else if (GET_CODE (setter) == SET
8761 && GET_CODE (SET_DEST (setter)) == SUBREG
8762 && SUBREG_REG (SET_DEST (setter)) == dest
8763 && subreg_lowpart_p (SET_DEST (setter)))
8764 record_value_for_reg (dest, record_dead_insn,
8765 gen_lowpart_for_combine (GET_MODE (dest),
8768 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
8770 else if (GET_CODE (dest) == MEM
8771 /* Ignore pushes, they clobber nothing. */
8772 && ! push_operand (dest, GET_MODE (dest)))
8773 mem_last_set = INSN_CUID (record_dead_insn);
8776 /* Update the records of when each REG was most recently set or killed
8777 for the things done by INSN. This is the last thing done in processing
8778 INSN in the combiner loop.
8780 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8781 similar information mem_last_set (which insn most recently modified memory)
8782 and last_call_cuid (which insn was the most recent subroutine call). */
8785 record_dead_and_set_regs (insn)
8789 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8791 if (REG_NOTE_KIND (link) == REG_DEAD)
8792 reg_last_death[REGNO (XEXP (link, 0))] = insn;
8793 else if (REG_NOTE_KIND (link) == REG_INC)
8794 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
8797 if (GET_CODE (insn) == CALL_INSN)
8798 last_call_cuid = mem_last_set = INSN_CUID (insn);
8800 record_dead_insn = insn;
8801 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
8804 /* Utility routine for the following function. Verify that all the registers
8805 mentioned in *LOC are valid when *LOC was part of a value set when
8806 label_tick == TICK. Return 0 if some are not.
8808 If REPLACE is non-zero, replace the invalid reference with
8809 (clobber (const_int 0)) and return 1. This replacement is useful because
8810 we often can get useful information about the form of a value (e.g., if
8811 it was produced by a shift that always produces -1 or 0) even though
8812 we don't know exactly what registers it was produced from. */
8815 get_last_value_validate (loc, tick, replace)
8821 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
8822 int len = GET_RTX_LENGTH (GET_CODE (x));
8825 if (GET_CODE (x) == REG)
8827 int regno = REGNO (x);
8828 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8829 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8832 for (j = regno; j < endregno; j++)
8833 if (reg_last_set_invalid[j]
8834 /* If this is a pseudo-register that was only set once, it is
8836 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
8837 && reg_last_set_label[j] > tick))
8840 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8847 for (i = 0; i < len; i++)
8849 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
8850 /* Don't bother with these. They shouldn't occur anyway. */
8854 /* If we haven't found a reason for it to be invalid, it is valid. */
8858 /* Get the last value assigned to X, if known. Some registers
8859 in the value may be replaced with (clobber (const_int 0)) if their value
8860 is known longer known reliably. */
8869 /* If this is a non-paradoxical SUBREG, get the value of its operand and
8870 then convert it to the desired mode. If this is a paradoxical SUBREG,
8871 we cannot predict what values the "extra" bits might have. */
8872 if (GET_CODE (x) == SUBREG
8873 && subreg_lowpart_p (x)
8874 && (GET_MODE_SIZE (GET_MODE (x))
8875 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8876 && (value = get_last_value (SUBREG_REG (x))) != 0)
8877 return gen_lowpart_for_combine (GET_MODE (x), value);
8879 if (GET_CODE (x) != REG)
8883 value = reg_last_set_value[regno];
8885 /* If we don't have a value or if it isn't for this basic block, return 0. */
8888 || (reg_n_sets[regno] != 1
8889 && (reg_last_set_label[regno] != label_tick)))
8892 /* If the value was set in a later insn that the ones we are processing,
8893 we can't use it even if the register was only set once, but make a quick
8894 check to see if the previous insn set it to something. This is commonly
8895 the case when the same pseudo is used by repeated insns. */
8897 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
8901 for (insn = prev_nonnote_insn (subst_insn);
8902 insn && INSN_CUID (insn) >= subst_low_cuid;
8903 insn = prev_nonnote_insn (insn))
8907 && (set = single_set (insn)) != 0
8908 && rtx_equal_p (SET_DEST (set), x))
8910 value = SET_SRC (set);
8912 /* Make sure that VALUE doesn't reference X. Replace any
8913 expliit references with a CLOBBER. If there are any remaining
8914 references (rare), don't use the value. */
8916 if (reg_mentioned_p (x, value))
8917 value = replace_rtx (copy_rtx (value), x,
8918 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
8920 if (reg_overlap_mentioned_p (x, value))
8927 /* If the value has all its registers valid, return it. */
8928 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
8931 /* Otherwise, make a copy and replace any invalid register with
8932 (clobber (const_int 0)). If that fails for some reason, return 0. */
8934 value = copy_rtx (value);
8935 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
8941 /* Return nonzero if expression X refers to a REG or to memory
8942 that is set in an instruction more recent than FROM_CUID. */
8945 use_crosses_set_p (x, from_cuid)
8951 register enum rtx_code code = GET_CODE (x);
8955 register int regno = REGNO (x);
8956 #ifdef PUSH_ROUNDING
8957 /* Don't allow uses of the stack pointer to be moved,
8958 because we don't know whether the move crosses a push insn. */
8959 if (regno == STACK_POINTER_REGNUM)
8962 return (reg_last_set[regno]
8963 && INSN_CUID (reg_last_set[regno]) > from_cuid);
8966 if (code == MEM && mem_last_set > from_cuid)
8969 fmt = GET_RTX_FORMAT (code);
8971 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8976 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8977 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
8980 else if (fmt[i] == 'e'
8981 && use_crosses_set_p (XEXP (x, i), from_cuid))
8987 /* Define three variables used for communication between the following
8990 static int reg_dead_regno, reg_dead_endregno;
8991 static int reg_dead_flag;
8993 /* Function called via note_stores from reg_dead_at_p.
8995 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
8996 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
8999 reg_dead_at_p_1 (dest, x)
9003 int regno, endregno;
9005 if (GET_CODE (dest) != REG)
9008 regno = REGNO (dest);
9009 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9010 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9012 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9013 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9016 /* Return non-zero if REG is known to be dead at INSN.
9018 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9019 referencing REG, it is dead. If we hit a SET referencing REG, it is
9020 live. Otherwise, see if it is live or dead at the start of the basic
9024 reg_dead_at_p (reg, insn)
9030 /* Set variables for reg_dead_at_p_1. */
9031 reg_dead_regno = REGNO (reg);
9032 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9033 ? HARD_REGNO_NREGS (reg_dead_regno,
9039 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9040 beginning of function. */
9041 for (; insn && GET_CODE (insn) != CODE_LABEL;
9042 insn = prev_nonnote_insn (insn))
9044 note_stores (PATTERN (insn), reg_dead_at_p_1);
9046 return reg_dead_flag == 1 ? 1 : 0;
9048 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9052 /* Get the basic block number that we were in. */
9057 for (block = 0; block < n_basic_blocks; block++)
9058 if (insn == basic_block_head[block])
9061 if (block == n_basic_blocks)
9065 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9066 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9067 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9073 /* Remove register number REGNO from the dead registers list of INSN.
9075 Return the note used to record the death, if there was one. */
9078 remove_death (regno, insn)
9082 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9086 reg_n_deaths[regno]--;
9087 remove_note (insn, note);
9093 /* For each register (hardware or pseudo) used within expression X, if its
9094 death is in an instruction with cuid between FROM_CUID (inclusive) and
9095 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9096 list headed by PNOTES.
9098 This is done when X is being merged by combination into TO_INSN. These
9099 notes will then be distributed as needed. */
9102 move_deaths (x, from_cuid, to_insn, pnotes)
9109 register int len, i;
9110 register enum rtx_code code = GET_CODE (x);
9114 register int regno = REGNO (x);
9115 register rtx where_dead = reg_last_death[regno];
9117 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9118 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9120 rtx note = remove_death (regno, reg_last_death[regno]);
9122 /* It is possible for the call above to return 0. This can occur
9123 when reg_last_death points to I2 or I1 that we combined with.
9124 In that case make a new note. */
9128 XEXP (note, 1) = *pnotes;
9132 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9134 reg_n_deaths[regno]++;
9140 else if (GET_CODE (x) == SET)
9142 rtx dest = SET_DEST (x);
9144 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9146 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9147 that accesses one word of a multi-word item, some
9148 piece of everything register in the expression is used by
9149 this insn, so remove any old death. */
9151 if (GET_CODE (dest) == ZERO_EXTRACT
9152 || GET_CODE (dest) == STRICT_LOW_PART
9153 || (GET_CODE (dest) == SUBREG
9154 && (((GET_MODE_SIZE (GET_MODE (dest))
9155 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9156 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9157 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9159 move_deaths (dest, from_cuid, to_insn, pnotes);
9163 /* If this is some other SUBREG, we know it replaces the entire
9164 value, so use that as the destination. */
9165 if (GET_CODE (dest) == SUBREG)
9166 dest = SUBREG_REG (dest);
9168 /* If this is a MEM, adjust deaths of anything used in the address.
9169 For a REG (the only other possibility), the entire value is
9170 being replaced so the old value is not used in this insn. */
9172 if (GET_CODE (dest) == MEM)
9173 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9177 else if (GET_CODE (x) == CLOBBER)
9180 len = GET_RTX_LENGTH (code);
9181 fmt = GET_RTX_FORMAT (code);
9183 for (i = 0; i < len; i++)
9188 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9189 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9191 else if (fmt[i] == 'e')
9192 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9196 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9197 pattern of an insn. X must be a REG. */
9200 reg_bitfield_target_p (x, body)
9206 if (GET_CODE (body) == SET)
9208 rtx dest = SET_DEST (body);
9210 int regno, tregno, endregno, endtregno;
9212 if (GET_CODE (dest) == ZERO_EXTRACT)
9213 target = XEXP (dest, 0);
9214 else if (GET_CODE (dest) == STRICT_LOW_PART)
9215 target = SUBREG_REG (XEXP (dest, 0));
9219 if (GET_CODE (target) == SUBREG)
9220 target = SUBREG_REG (target);
9222 if (GET_CODE (target) != REG)
9225 tregno = REGNO (target), regno = REGNO (x);
9226 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9229 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9230 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9232 return endregno > tregno && regno < endtregno;
9235 else if (GET_CODE (body) == PARALLEL)
9236 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9237 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9243 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9244 as appropriate. I3 and I2 are the insns resulting from the combination
9245 insns including FROM (I2 may be zero).
9247 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9248 not need REG_DEAD notes because they are being substituted for. This
9249 saves searching in the most common cases.
9251 Each note in the list is either ignored or placed on some insns, depending
9252 on the type of note. */
9255 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9259 rtx elim_i2, elim_i1;
9261 rtx note, next_note;
9264 for (note = notes; note; note = next_note)
9266 rtx place = 0, place2 = 0;
9268 /* If this NOTE references a pseudo register, ensure it references
9269 the latest copy of that register. */
9270 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9271 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9272 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9274 next_note = XEXP (note, 1);
9275 switch (REG_NOTE_KIND (note))
9278 /* If this register is set or clobbered in I3, put the note there
9279 unless there is one already. */
9280 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9282 if (! (GET_CODE (XEXP (note, 0)) == REG
9283 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9284 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9287 /* Otherwise, if this register is used by I3, then this register
9288 now dies here, so we must put a REG_DEAD note here unless there
9290 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9291 && ! (GET_CODE (XEXP (note, 0)) == REG
9292 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9293 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9295 PUT_REG_NOTE_KIND (note, REG_DEAD);
9303 /* These notes say something about results of an insn. We can
9304 only support them if they used to be on I3 in which case they
9305 remain on I3. Otherwise they are ignored.
9307 If the note refers to an expression that is not a constant, we
9308 must also ignore the note since we cannot tell whether the
9309 equivalence is still true. It might be possible to do
9310 slightly better than this (we only have a problem if I2DEST
9311 or I1DEST is present in the expression), but it doesn't
9312 seem worth the trouble. */
9315 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9320 case REG_NO_CONFLICT:
9322 /* These notes say something about how a register is used. They must
9323 be present on any use of the register in I2 or I3. */
9324 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9327 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9337 /* It is too much trouble to try to see if this note is still
9338 correct in all situations. It is better to simply delete it. */
9342 /* If the insn previously containing this note still exists,
9343 put it back where it was. Otherwise move it to the previous
9344 insn. Adjust the corresponding REG_LIBCALL note. */
9345 if (GET_CODE (from_insn) != NOTE)
9349 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9350 place = prev_real_insn (from_insn);
9352 XEXP (tem, 0) = place;
9357 /* This is handled similarly to REG_RETVAL. */
9358 if (GET_CODE (from_insn) != NOTE)
9362 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9363 place = next_real_insn (from_insn);
9365 XEXP (tem, 0) = place;
9370 /* If the register is used as an input in I3, it dies there.
9371 Similarly for I2, if it is non-zero and adjacent to I3.
9373 If the register is not used as an input in either I3 or I2
9374 and it is not one of the registers we were supposed to eliminate,
9375 there are two possibilities. We might have a non-adjacent I2
9376 or we might have somehow eliminated an additional register
9377 from a computation. For example, we might have had A & B where
9378 we discover that B will always be zero. In this case we will
9379 eliminate the reference to A.
9381 In both cases, we must search to see if we can find a previous
9382 use of A and put the death note there. */
9384 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9386 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9387 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9390 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9393 /* If the register is used in both I2 and I3 and it dies in I3,
9394 we might have added another reference to it. If reg_n_refs
9395 was 2, bump it to 3. This has to be correct since the
9396 register must have been set somewhere. The reason this is
9397 done is because local-alloc.c treats 2 references as a
9400 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9401 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9402 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9403 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9406 for (tem = prev_nonnote_insn (i3);
9407 tem && (GET_CODE (tem) == INSN
9408 || GET_CODE (tem) == CALL_INSN);
9409 tem = prev_nonnote_insn (tem))
9411 /* If the register is being set at TEM, see if that is all
9412 TEM is doing. If so, delete TEM. Otherwise, make this
9413 into a REG_UNUSED note instead. */
9414 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9416 rtx set = single_set (tem);
9418 /* Verify that it was the set, and not a clobber that
9419 modified the register. */
9421 if (set != 0 && ! side_effects_p (SET_SRC (set))
9422 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9424 /* Move the notes and links of TEM elsewhere.
9425 This might delete other dead insns recursively.
9426 First set the pattern to something that won't use
9429 PATTERN (tem) = pc_rtx;
9431 distribute_notes (REG_NOTES (tem), tem, tem,
9432 NULL_RTX, NULL_RTX, NULL_RTX);
9433 distribute_links (LOG_LINKS (tem));
9435 PUT_CODE (tem, NOTE);
9436 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9437 NOTE_SOURCE_FILE (tem) = 0;
9441 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9443 /* If there isn't already a REG_UNUSED note, put one
9445 if (! find_regno_note (tem, REG_UNUSED,
9446 REGNO (XEXP (note, 0))))
9451 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9458 /* If the register is set or already dead at PLACE, we needn't do
9459 anything with this note if it is still a REG_DEAD note.
9461 Note that we cannot use just `dead_or_set_p' here since we can
9462 convert an assignment to a register into a bit-field assignment.
9463 Therefore, we must also omit the note if the register is the
9464 target of a bitfield assignment. */
9466 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9468 int regno = REGNO (XEXP (note, 0));
9470 if (dead_or_set_p (place, XEXP (note, 0))
9471 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9473 /* Unless the register previously died in PLACE, clear
9474 reg_last_death. [I no longer understand why this is
9476 if (reg_last_death[regno] != place)
9477 reg_last_death[regno] = 0;
9481 reg_last_death[regno] = place;
9483 /* If this is a death note for a hard reg that is occupying
9484 multiple registers, ensure that we are still using all
9485 parts of the object. If we find a piece of the object
9486 that is unused, we must add a USE for that piece before
9487 PLACE and put the appropriate REG_DEAD note on it.
9489 An alternative would be to put a REG_UNUSED for the pieces
9490 on the insn that set the register, but that can't be done if
9491 it is not in the same block. It is simpler, though less
9492 efficient, to add the USE insns. */
9494 if (place && regno < FIRST_PSEUDO_REGISTER
9495 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9498 = regno + HARD_REGNO_NREGS (regno,
9499 GET_MODE (XEXP (note, 0)));
9503 for (i = regno; i < endregno; i++)
9504 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9506 rtx piece = gen_rtx (REG, word_mode, i);
9509 /* See if we already placed a USE note for this
9510 register in front of PLACE. */
9512 GET_CODE (PREV_INSN (p)) == INSN
9513 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9515 if (rtx_equal_p (piece,
9516 XEXP (PATTERN (PREV_INSN (p)), 0)))
9525 = emit_insn_before (gen_rtx (USE, VOIDmode,
9528 REG_NOTES (use_insn)
9529 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9530 REG_NOTES (use_insn));
9538 /* Put only REG_DEAD notes for pieces that are
9539 still used and that are not already dead or set. */
9541 for (i = regno; i < endregno; i++)
9543 rtx piece = gen_rtx (REG, word_mode, i);
9545 if (reg_referenced_p (piece, PATTERN (place))
9546 && ! dead_or_set_p (place, piece)
9547 && ! reg_bitfield_target_p (piece,
9549 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9561 /* Any other notes should not be present at this point in the
9568 XEXP (note, 1) = REG_NOTES (place);
9569 REG_NOTES (place) = note;
9571 else if ((REG_NOTE_KIND (note) == REG_DEAD
9572 || REG_NOTE_KIND (note) == REG_UNUSED)
9573 && GET_CODE (XEXP (note, 0)) == REG)
9574 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9578 if ((REG_NOTE_KIND (note) == REG_DEAD
9579 || REG_NOTE_KIND (note) == REG_UNUSED)
9580 && GET_CODE (XEXP (note, 0)) == REG)
9581 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9583 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9584 XEXP (note, 0), REG_NOTES (place2));
9589 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9590 I3, I2, and I1 to new locations. This is also called in one case to
9591 add a link pointing at I3 when I3's destination is changed. */
9594 distribute_links (links)
9597 rtx link, next_link;
9599 for (link = links; link; link = next_link)
9605 next_link = XEXP (link, 1);
9607 /* If the insn that this link points to is a NOTE or isn't a single
9608 set, ignore it. In the latter case, it isn't clear what we
9609 can do other than ignore the link, since we can't tell which
9610 register it was for. Such links wouldn't be used by combine
9613 It is not possible for the destination of the target of the link to
9614 have been changed by combine. The only potential of this is if we
9615 replace I3, I2, and I1 by I3 and I2. But in that case the
9616 destination of I2 also remains unchanged. */
9618 if (GET_CODE (XEXP (link, 0)) == NOTE
9619 || (set = single_set (XEXP (link, 0))) == 0)
9622 reg = SET_DEST (set);
9623 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9624 || GET_CODE (reg) == SIGN_EXTRACT
9625 || GET_CODE (reg) == STRICT_LOW_PART)
9626 reg = XEXP (reg, 0);
9628 /* A LOG_LINK is defined as being placed on the first insn that uses
9629 a register and points to the insn that sets the register. Start
9630 searching at the next insn after the target of the link and stop
9631 when we reach a set of the register or the end of the basic block.
9633 Note that this correctly handles the link that used to point from
9634 I3 to I2. Also note that not much searching is typically done here
9635 since most links don't point very far away. */
9637 for (insn = NEXT_INSN (XEXP (link, 0));
9638 (insn && GET_CODE (insn) != CODE_LABEL
9639 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9640 insn = NEXT_INSN (insn))
9641 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9642 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9644 if (reg_referenced_p (reg, PATTERN (insn)))
9649 /* If we found a place to put the link, place it there unless there
9650 is already a link to the same insn as LINK at that point. */
9656 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9657 if (XEXP (link2, 0) == XEXP (link, 0))
9662 XEXP (link, 1) = LOG_LINKS (place);
9663 LOG_LINKS (place) = link;
9670 dump_combine_stats (file)
9675 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9676 combine_attempts, combine_merges, combine_extras, combine_successes);
9680 dump_combine_total_stats (file)
9685 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9686 total_attempts, total_merges, total_extras, total_successes);