1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
428 buf = undobuf.frees, undobuf.frees = buf->next;
430 buf = (struct undo *) xmalloc (sizeof (struct undo));
434 buf->old_contents.r = oldval;
437 buf->next = undobuf.undos, undobuf.undos = buf;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into, newval)
448 unsigned int *into, newval;
451 unsigned int oldval = *into;
453 if (oldval == newval)
457 buf = undobuf.frees, undobuf.frees = buf->next;
459 buf = (struct undo *) xmalloc (sizeof (struct undo));
463 buf->old_contents.i = oldval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f, nregs)
486 rtx links, nextlinks;
488 int new_direct_jump_p = 0;
490 combine_attempts = 0;
493 combine_successes = 0;
495 combine_max_regno = nregs;
497 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
498 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
500 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
502 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
503 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
504 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
505 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
506 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
507 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
509 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs * sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
522 if (INSN_UID (insn) > i)
525 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
528 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid = 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn = NULL_RTX;
552 setup_incoming_promotions ();
554 refresh_blocks = sbitmap_alloc (n_basic_blocks);
555 sbitmap_zero (refresh_blocks);
558 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
560 uid_cuid[INSN_UID (insn)] = ++i;
566 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
568 record_dead_and_set_regs (insn);
571 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
572 if (REG_NOTE_KIND (links) == REG_INC)
573 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
578 if (GET_CODE (insn) == CODE_LABEL)
582 nonzero_sign_valid = 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block = -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block + 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block + 1) == insn)
602 if (GET_CODE (insn) == CODE_LABEL)
605 else if (INSN_P (insn))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn, PATTERN (insn));
611 /* Try this insn with each insn it links back to. */
613 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
614 if ((next = try_combine (insn, XEXP (links, 0),
615 NULL_RTX, &new_direct_jump_p)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
622 rtx link = XEXP (links, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in pursuing this chain any further. */
626 if (GET_CODE (link) == NOTE)
629 for (nextlinks = LOG_LINKS (link);
631 nextlinks = XEXP (nextlinks, 1))
632 if ((next = try_combine (insn, link,
634 &new_direct_jump_p)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn) == JUMP_INSN
647 && (prev = prev_nonnote_insn (insn)) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev)))
651 if ((next = try_combine (insn, prev,
652 NULL_RTX, &new_direct_jump_p)) != 0)
655 for (nextlinks = LOG_LINKS (prev); nextlinks;
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, prev,
659 &new_direct_jump_p)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn) == INSN
665 && (prev = prev_nonnote_insn (insn)) != 0
666 && GET_CODE (prev) == INSN
667 && sets_cc0_p (PATTERN (prev))
668 && GET_CODE (PATTERN (insn)) == SET
669 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
671 if ((next = try_combine (insn, prev,
672 NULL_RTX, &new_direct_jump_p)) != 0)
675 for (nextlinks = LOG_LINKS (prev); nextlinks;
676 nextlinks = XEXP (nextlinks, 1))
677 if ((next = try_combine (insn, prev,
679 &new_direct_jump_p)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
687 if (GET_CODE (XEXP (links, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
689 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
690 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && (next = try_combine (insn, XEXP (links, 0),
694 prev, &new_direct_jump_p)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
701 for (nextlinks = XEXP (links, 1); nextlinks;
702 nextlinks = XEXP (nextlinks, 1))
703 if ((next = try_combine (insn, XEXP (links, 0),
705 &new_direct_jump_p)) != 0)
708 if (GET_CODE (insn) != NOTE)
709 record_dead_and_set_regs (insn);
716 delete_noop_moves (f);
720 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
725 sbitmap_free (refresh_blocks);
726 free (reg_nonzero_bits);
727 free (reg_sign_bit_copies);
728 free (reg_last_death);
730 free (reg_last_set_value);
731 free (reg_last_set_table_tick);
732 free (reg_last_set_label);
733 free (reg_last_set_invalid);
734 free (reg_last_set_mode);
735 free (reg_last_set_nonzero_bits);
736 free (reg_last_set_sign_bit_copies);
740 struct undo *undo, *next;
741 for (undo = undobuf.frees; undo; undo = next)
749 total_attempts += combine_attempts;
750 total_merges += combine_merges;
751 total_extras += combine_extras;
752 total_successes += combine_successes;
754 nonzero_sign_valid = 0;
756 /* Make recognizer allow volatile MEMs again. */
759 return new_direct_jump_p;
762 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
765 init_reg_last_arrays ()
767 unsigned int nregs = combine_max_regno;
769 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
770 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
771 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
772 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
773 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
774 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
775 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
776 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
777 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
780 /* Set up any promoted values for incoming argument registers. */
783 setup_incoming_promotions ()
785 #ifdef PROMOTE_FUNCTION_ARGS
788 enum machine_mode mode;
790 rtx first = get_insns ();
792 #ifndef OUTGOING_REGNO
793 #define OUTGOING_REGNO(N) N
795 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
796 /* Check whether this register can hold an incoming pointer
797 argument. FUNCTION_ARG_REGNO_P tests outgoing register
798 numbers, so translate if necessary due to register windows. */
799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
800 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
803 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
806 gen_rtx_CLOBBER (mode, const0_rtx)));
811 /* Called via note_stores. If X is a pseudo that is narrower than
812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
814 If we are setting only a portion of X and we can't figure out what
815 portion, assume all bits will be used since we don't know what will
818 Similarly, set how many bits of X are known to be copies of the sign bit
819 at all locations in the function. This is the smallest number implied
823 set_nonzero_bits_and_sign_copies (x, set, data)
826 void *data ATTRIBUTE_UNUSED;
830 if (GET_CODE (x) == REG
831 && REGNO (x) >= FIRST_PSEUDO_REGISTER
832 /* If this register is undefined at the start of the file, we can't
833 say what its contents were. */
834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
835 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
837 if (set == 0 || GET_CODE (set) == CLOBBER)
839 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
840 reg_sign_bit_copies[REGNO (x)] = 1;
844 /* If this is a complex assignment, see if we can convert it into a
845 simple assignment. */
846 set = expand_field_assignment (set);
848 /* If this is a simple assignment, or we have a paradoxical SUBREG,
849 set what we know about X. */
851 if (SET_DEST (set) == x
852 || (GET_CODE (SET_DEST (set)) == SUBREG
853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
855 && SUBREG_REG (SET_DEST (set)) == x))
857 rtx src = SET_SRC (set);
859 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
860 /* If X is narrower than a word and SRC is a non-negative
861 constant that would appear negative in the mode of X,
862 sign-extend it for use in reg_nonzero_bits because some
863 machines (maybe most) will actually do the sign-extension
864 and this is the conservative approach.
866 ??? For 2.5, try to tighten up the MD files in this regard
867 instead of this kludge. */
869 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
870 && GET_CODE (src) == CONST_INT
872 && 0 != (INTVAL (src)
874 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
875 src = GEN_INT (INTVAL (src)
876 | ((HOST_WIDE_INT) (-1)
877 << GET_MODE_BITSIZE (GET_MODE (x))));
880 reg_nonzero_bits[REGNO (x)]
881 |= nonzero_bits (src, nonzero_bits_mode);
882 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
883 if (reg_sign_bit_copies[REGNO (x)] == 0
884 || reg_sign_bit_copies[REGNO (x)] > num)
885 reg_sign_bit_copies[REGNO (x)] = num;
889 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
890 reg_sign_bit_copies[REGNO (x)] = 1;
895 /* See if INSN can be combined into I3. PRED and SUCC are optionally
896 insns that were previously combined into I3 or that will be combined
897 into the merger of INSN and I3.
899 Return 0 if the combination is not allowed for any reason.
901 If the combination is allowed, *PDEST will be set to the single
902 destination of INSN and *PSRC to the single source, and this function
906 can_combine_p (insn, i3, pred, succ, pdest, psrc)
909 rtx pred ATTRIBUTE_UNUSED;
914 rtx set = 0, src, dest;
919 int all_adjacent = (succ ? (next_active_insn (insn) == succ
920 && next_active_insn (succ) == i3)
921 : next_active_insn (insn) == i3);
923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
924 or a PARALLEL consisting of such a SET and CLOBBERs.
926 If INSN has CLOBBER parallel parts, ignore them for our processing.
927 By definition, these happen during the execution of the insn. When it
928 is merged with another insn, all bets are off. If they are, in fact,
929 needed and aren't also supplied in I3, they may be added by
930 recog_for_combine. Otherwise, it won't match.
932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
935 Get the source and destination of INSN. If more than one, can't
938 if (GET_CODE (PATTERN (insn)) == SET)
939 set = PATTERN (insn);
940 else if (GET_CODE (PATTERN (insn)) == PARALLEL
941 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
943 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
945 rtx elt = XVECEXP (PATTERN (insn), 0, i);
947 switch (GET_CODE (elt))
949 /* This is important to combine floating point insns
952 /* Combining an isolated USE doesn't make sense.
953 We depend here on combinable_i3pat to reject them. */
954 /* The code below this loop only verifies that the inputs of
955 the SET in INSN do not change. We call reg_set_between_p
956 to verify that the REG in the USE does not change between
958 If the USE in INSN was for a pseudo register, the matching
959 insn pattern will likely match any register; combining this
960 with any other USE would only be safe if we knew that the
961 used registers have identical values, or if there was
962 something to tell them apart, e.g. different modes. For
963 now, we forgo such complicated tests and simply disallow
964 combining of USES of pseudo registers with any other USE. */
965 if (GET_CODE (XEXP (elt, 0)) == REG
966 && GET_CODE (PATTERN (i3)) == PARALLEL)
968 rtx i3pat = PATTERN (i3);
969 int i = XVECLEN (i3pat, 0) - 1;
970 unsigned int regno = REGNO (XEXP (elt, 0));
974 rtx i3elt = XVECEXP (i3pat, 0, i);
976 if (GET_CODE (i3elt) == USE
977 && GET_CODE (XEXP (i3elt, 0)) == REG
978 && (REGNO (XEXP (i3elt, 0)) == regno
979 ? reg_set_between_p (XEXP (elt, 0),
980 PREV_INSN (insn), i3)
981 : regno >= FIRST_PSEUDO_REGISTER))
988 /* We can ignore CLOBBERs. */
993 /* Ignore SETs whose result isn't used but not those that
994 have side-effects. */
995 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
996 && ! side_effects_p (elt))
999 /* If we have already found a SET, this is a second one and
1000 so we cannot combine with this insn. */
1008 /* Anything else means we can't combine. */
1014 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1015 so don't do anything with it. */
1016 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1025 set = expand_field_assignment (set);
1026 src = SET_SRC (set), dest = SET_DEST (set);
1028 /* Don't eliminate a store in the stack pointer. */
1029 if (dest == stack_pointer_rtx
1030 /* If we couldn't eliminate a field assignment, we can't combine. */
1031 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1032 /* Don't combine with an insn that sets a register to itself if it has
1033 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1034 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1035 /* Can't merge an ASM_OPERANDS. */
1036 || GET_CODE (src) == ASM_OPERANDS
1037 /* Can't merge a function call. */
1038 || GET_CODE (src) == CALL
1039 /* Don't eliminate a function call argument. */
1040 || (GET_CODE (i3) == CALL_INSN
1041 && (find_reg_fusage (i3, USE, dest)
1042 || (GET_CODE (dest) == REG
1043 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1044 && global_regs[REGNO (dest)])))
1045 /* Don't substitute into an incremented register. */
1046 || FIND_REG_INC_NOTE (i3, dest)
1047 || (succ && FIND_REG_INC_NOTE (succ, dest))
1049 /* Don't combine the end of a libcall into anything. */
1050 /* ??? This gives worse code, and appears to be unnecessary, since no
1051 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1052 use REG_RETVAL notes for noconflict blocks, but other code here
1053 makes sure that those insns don't disappear. */
1054 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1056 /* Make sure that DEST is not used after SUCC but before I3. */
1057 || (succ && ! all_adjacent
1058 && reg_used_between_p (dest, succ, i3))
1059 /* Make sure that the value that is to be substituted for the register
1060 does not use any registers whose values alter in between. However,
1061 If the insns are adjacent, a use can't cross a set even though we
1062 think it might (this can happen for a sequence of insns each setting
1063 the same destination; reg_last_set of that register might point to
1064 a NOTE). If INSN has a REG_EQUIV note, the register is always
1065 equivalent to the memory so the substitution is valid even if there
1066 are intervening stores. Also, don't move a volatile asm or
1067 UNSPEC_VOLATILE across any other insns. */
1069 && (((GET_CODE (src) != MEM
1070 || ! find_reg_note (insn, REG_EQUIV, src))
1071 && use_crosses_set_p (src, INSN_CUID (insn)))
1072 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1073 || GET_CODE (src) == UNSPEC_VOLATILE))
1074 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1075 better register allocation by not doing the combine. */
1076 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1077 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1078 /* Don't combine across a CALL_INSN, because that would possibly
1079 change whether the life span of some REGs crosses calls or not,
1080 and it is a pain to update that information.
1081 Exception: if source is a constant, moving it later can't hurt.
1082 Accept that special case, because it helps -fforce-addr a lot. */
1083 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1086 /* DEST must either be a REG or CC0. */
1087 if (GET_CODE (dest) == REG)
1089 /* If register alignment is being enforced for multi-word items in all
1090 cases except for parameters, it is possible to have a register copy
1091 insn referencing a hard register that is not allowed to contain the
1092 mode being copied and which would not be valid as an operand of most
1093 insns. Eliminate this problem by not combining with such an insn.
1095 Also, on some machines we don't want to extend the life of a hard
1098 if (GET_CODE (src) == REG
1099 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1100 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1101 /* Don't extend the life of a hard register unless it is
1102 user variable (if we have few registers) or it can't
1103 fit into the desired register (meaning something special
1105 Also avoid substituting a return register into I3, because
1106 reload can't handle a conflict with constraints of other
1108 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1109 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1112 else if (GET_CODE (dest) != CC0)
1115 /* Don't substitute for a register intended as a clobberable operand.
1116 Similarly, don't substitute an expression containing a register that
1117 will be clobbered in I3. */
1118 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1119 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1120 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1121 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1123 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1126 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1127 or not), reject, unless nothing volatile comes between it and I3 */
1129 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1131 /* Make sure succ doesn't contain a volatile reference. */
1132 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1135 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1136 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1140 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1141 to be an explicit register variable, and was chosen for a reason. */
1143 if (GET_CODE (src) == ASM_OPERANDS
1144 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1147 /* If there are any volatile insns between INSN and I3, reject, because
1148 they might affect machine state. */
1150 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1151 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1154 /* If INSN or I2 contains an autoincrement or autodecrement,
1155 make sure that register is not used between there and I3,
1156 and not already used in I3 either.
1157 Also insist that I3 not be a jump; if it were one
1158 and the incremented register were spilled, we would lose. */
1161 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1162 if (REG_NOTE_KIND (link) == REG_INC
1163 && (GET_CODE (i3) == JUMP_INSN
1164 || reg_used_between_p (XEXP (link, 0), insn, i3)
1165 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1170 /* Don't combine an insn that follows a CC0-setting insn.
1171 An insn that uses CC0 must not be separated from the one that sets it.
1172 We do, however, allow I2 to follow a CC0-setting insn if that insn
1173 is passed as I1; in that case it will be deleted also.
1174 We also allow combining in this case if all the insns are adjacent
1175 because that would leave the two CC0 insns adjacent as well.
1176 It would be more logical to test whether CC0 occurs inside I1 or I2,
1177 but that would be much slower, and this ought to be equivalent. */
1179 p = prev_nonnote_insn (insn);
1180 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1185 /* If we get here, we have passed all the tests and the combination is
1194 /* Check if PAT is an insn - or a part of it - used to set up an
1195 argument for a function in a hard register. */
1198 sets_function_arg_p (pat)
1204 switch (GET_CODE (pat))
1207 return sets_function_arg_p (PATTERN (pat));
1210 for (i = XVECLEN (pat, 0); --i >= 0;)
1211 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1217 inner_dest = SET_DEST (pat);
1218 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1219 || GET_CODE (inner_dest) == SUBREG
1220 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1221 inner_dest = XEXP (inner_dest, 0);
1223 return (GET_CODE (inner_dest) == REG
1224 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1225 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1234 /* LOC is the location within I3 that contains its pattern or the component
1235 of a PARALLEL of the pattern. We validate that it is valid for combining.
1237 One problem is if I3 modifies its output, as opposed to replacing it
1238 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1239 so would produce an insn that is not equivalent to the original insns.
1243 (set (reg:DI 101) (reg:DI 100))
1244 (set (subreg:SI (reg:DI 101) 0) <foo>)
1246 This is NOT equivalent to:
1248 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1249 (set (reg:DI 101) (reg:DI 100))])
1251 Not only does this modify 100 (in which case it might still be valid
1252 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1254 We can also run into a problem if I2 sets a register that I1
1255 uses and I1 gets directly substituted into I3 (not via I2). In that
1256 case, we would be getting the wrong value of I2DEST into I3, so we
1257 must reject the combination. This case occurs when I2 and I1 both
1258 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1259 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1260 of a SET must prevent combination from occurring.
1262 Before doing the above check, we first try to expand a field assignment
1263 into a set of logical operations.
1265 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1266 we place a register that is both set and used within I3. If more than one
1267 such register is detected, we fail.
1269 Return 1 if the combination is valid, zero otherwise. */
1272 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1278 rtx *pi3dest_killed;
1282 if (GET_CODE (x) == SET)
1284 rtx set = expand_field_assignment (x);
1285 rtx dest = SET_DEST (set);
1286 rtx src = SET_SRC (set);
1287 rtx inner_dest = dest;
1290 rtx inner_src = src;
1295 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1296 || GET_CODE (inner_dest) == SUBREG
1297 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1298 inner_dest = XEXP (inner_dest, 0);
1300 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1303 while (GET_CODE (inner_src) == STRICT_LOW_PART
1304 || GET_CODE (inner_src) == SUBREG
1305 || GET_CODE (inner_src) == ZERO_EXTRACT)
1306 inner_src = XEXP (inner_src, 0);
1308 /* If it is better that two different modes keep two different pseudos,
1309 avoid combining them. This avoids producing the following pattern
1311 (set (subreg:SI (reg/v:QI 21) 0)
1312 (lshiftrt:SI (reg/v:SI 20)
1314 If that were made, reload could not handle the pair of
1315 reg 20/21, since it would try to get any GENERAL_REGS
1316 but some of them don't handle QImode. */
1318 if (rtx_equal_p (inner_src, i2dest)
1319 && GET_CODE (inner_dest) == REG
1320 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1324 /* Check for the case where I3 modifies its output, as
1326 if ((inner_dest != dest
1327 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1328 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1330 /* This is the same test done in can_combine_p except we can't test
1331 all_adjacent; we don't have to, since this instruction will stay
1332 in place, thus we are not considering increasing the lifetime of
1335 Also, if this insn sets a function argument, combining it with
1336 something that might need a spill could clobber a previous
1337 function argument; the all_adjacent test in can_combine_p also
1338 checks this; here, we do a more specific test for this case. */
1340 || (GET_CODE (inner_dest) == REG
1341 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1342 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1343 GET_MODE (inner_dest))))
1344 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1347 /* If DEST is used in I3, it is being killed in this insn,
1348 so record that for later.
1349 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1350 STACK_POINTER_REGNUM, since these are always considered to be
1351 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1352 if (pi3dest_killed && GET_CODE (dest) == REG
1353 && reg_referenced_p (dest, PATTERN (i3))
1354 && REGNO (dest) != FRAME_POINTER_REGNUM
1355 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1356 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1358 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1359 && (REGNO (dest) != ARG_POINTER_REGNUM
1360 || ! fixed_regs [REGNO (dest)])
1362 && REGNO (dest) != STACK_POINTER_REGNUM)
1364 if (*pi3dest_killed)
1367 *pi3dest_killed = dest;
1371 else if (GET_CODE (x) == PARALLEL)
1375 for (i = 0; i < XVECLEN (x, 0); i++)
1376 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1377 i1_not_in_src, pi3dest_killed))
1384 /* Return 1 if X is an arithmetic expression that contains a multiplication
1385 and division. We don't count multiplications by powers of two here. */
1391 switch (GET_CODE (x))
1393 case MOD: case DIV: case UMOD: case UDIV:
1397 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1398 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1400 switch (GET_RTX_CLASS (GET_CODE (x)))
1402 case 'c': case '<': case '2':
1403 return contains_muldiv (XEXP (x, 0))
1404 || contains_muldiv (XEXP (x, 1));
1407 return contains_muldiv (XEXP (x, 0));
1415 /* Determine whether INSN can be used in a combination. Return nonzero if
1416 not. This is used in try_combine to detect early some cases where we
1417 can't perform combinations. */
1420 cant_combine_insn_p (insn)
1426 /* If this isn't really an insn, we can't do anything.
1427 This can occur when flow deletes an insn that it has merged into an
1428 auto-increment address. */
1429 if (! INSN_P (insn))
1432 /* Never combine loads and stores involving hard regs. The register
1433 allocator can usually handle such reg-reg moves by tying. If we allow
1434 the combiner to make substitutions of hard regs, we risk aborting in
1435 reload on machines that have SMALL_REGISTER_CLASSES.
1436 As an exception, we allow combinations involving fixed regs; these are
1437 not available to the register allocator so there's no risk involved. */
1439 set = single_set (insn);
1442 src = SET_SRC (set);
1443 dest = SET_DEST (set);
1444 if (GET_CODE (src) == SUBREG)
1445 src = SUBREG_REG (src);
1446 if (GET_CODE (dest) == SUBREG)
1447 dest = SUBREG_REG (dest);
1448 if (REG_P (src) && REG_P (dest)
1449 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1450 && ! fixed_regs[REGNO (src)])
1451 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1452 && ! fixed_regs[REGNO (dest)])))
1458 /* Try to combine the insns I1 and I2 into I3.
1459 Here I1 and I2 appear earlier than I3.
1460 I1 can be zero; then we combine just I2 into I3.
1462 If we are combining three insns and the resulting insn is not recognized,
1463 try splitting it into two insns. If that happens, I2 and I3 are retained
1464 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1467 Return 0 if the combination does not work. Then nothing is changed.
1468 If we did the combination, return the insn at which combine should
1471 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1472 new direct jump instruction. */
1475 try_combine (i3, i2, i1, new_direct_jump_p)
1477 int *new_direct_jump_p;
1479 /* New patterns for I3 and I2, respectively. */
1480 rtx newpat, newi2pat = 0;
1481 int substed_i2 = 0, substed_i1 = 0;
1482 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1483 int added_sets_1, added_sets_2;
1484 /* Total number of SETs to put into I3. */
1486 /* Nonzero is I2's body now appears in I3. */
1488 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1489 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1490 /* Contains I3 if the destination of I3 is used in its source, which means
1491 that the old life of I3 is being killed. If that usage is placed into
1492 I2 and not in I3, a REG_DEAD note must be made. */
1493 rtx i3dest_killed = 0;
1494 /* SET_DEST and SET_SRC of I2 and I1. */
1495 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1496 /* PATTERN (I2), or a copy of it in certain cases. */
1498 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1499 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1500 int i1_feeds_i3 = 0;
1501 /* Notes that must be added to REG_NOTES in I3 and I2. */
1502 rtx new_i3_notes, new_i2_notes;
1503 /* Notes that we substituted I3 into I2 instead of the normal case. */
1504 int i3_subst_into_i2 = 0;
1505 /* Notes that I1, I2 or I3 is a MULT operation. */
1513 /* Exit early if one of the insns involved can't be used for
1515 if (cant_combine_insn_p (i3)
1516 || cant_combine_insn_p (i2)
1517 || (i1 && cant_combine_insn_p (i1))
1518 /* We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 /* ??? This gives worse code, and appears to be unnecessary, since no
1523 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1524 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1530 undobuf.other_insn = 0;
1532 /* Reset the hard register usage information. */
1533 CLEAR_HARD_REG_SET (newpat_used_regs);
1535 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1536 code below, set I1 to be the earlier of the two insns. */
1537 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1538 temp = i1, i1 = i2, i2 = temp;
1540 added_links_insn = 0;
1542 /* First check for one important special-case that the code below will
1543 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1544 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1545 we may be able to replace that destination with the destination of I3.
1546 This occurs in the common code where we compute both a quotient and
1547 remainder into a structure, in which case we want to do the computation
1548 directly into the structure to avoid register-register copies.
1550 Note that this case handles both multiple sets in I2 and also
1551 cases where I2 has a number of CLOBBER or PARALLELs.
1553 We make very conservative checks below and only try to handle the
1554 most common cases of this. For example, we only handle the case
1555 where I2 and I3 are adjacent to avoid making difficult register
1558 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1560 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1561 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1562 && GET_CODE (PATTERN (i2)) == PARALLEL
1563 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1564 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1565 below would need to check what is inside (and reg_overlap_mentioned_p
1566 doesn't support those codes anyway). Don't allow those destinations;
1567 the resulting insn isn't likely to be recognized anyway. */
1568 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1569 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1570 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1571 SET_DEST (PATTERN (i3)))
1572 && next_real_insn (i2) == i3)
1574 rtx p2 = PATTERN (i2);
1576 /* Make sure that the destination of I3,
1577 which we are going to substitute into one output of I2,
1578 is not used within another output of I2. We must avoid making this:
1579 (parallel [(set (mem (reg 69)) ...)
1580 (set (reg 69) ...)])
1581 which is not well-defined as to order of actions.
1582 (Besides, reload can't handle output reloads for this.)
1584 The problem can also happen if the dest of I3 is a memory ref,
1585 if another dest in I2 is an indirect memory ref. */
1586 for (i = 0; i < XVECLEN (p2, 0); i++)
1587 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1588 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1589 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1590 SET_DEST (XVECEXP (p2, 0, i))))
1593 if (i == XVECLEN (p2, 0))
1594 for (i = 0; i < XVECLEN (p2, 0); i++)
1595 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1596 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1597 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1602 subst_low_cuid = INSN_CUID (i2);
1604 added_sets_2 = added_sets_1 = 0;
1605 i2dest = SET_SRC (PATTERN (i3));
1607 /* Replace the dest in I2 with our dest and make the resulting
1608 insn the new pattern for I3. Then skip to where we
1609 validate the pattern. Everything was set up above. */
1610 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1611 SET_DEST (PATTERN (i3)));
1614 i3_subst_into_i2 = 1;
1615 goto validate_replacement;
1619 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1620 one of those words to another constant, merge them by making a new
1623 && (temp = single_set (i2)) != 0
1624 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1625 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1626 && GET_CODE (SET_DEST (temp)) == REG
1627 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1628 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1629 && GET_CODE (PATTERN (i3)) == SET
1630 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1631 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1632 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1633 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1634 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1636 HOST_WIDE_INT lo, hi;
1638 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1639 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1642 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1643 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1646 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1648 /* We don't handle the case of the target word being wider
1649 than a host wide int. */
1650 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1653 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1654 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1655 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1657 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1658 hi = INTVAL (SET_SRC (PATTERN (i3)));
1659 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1661 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1662 >> (HOST_BITS_PER_WIDE_INT - 1));
1664 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1665 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1666 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1667 (INTVAL (SET_SRC (PATTERN (i3)))));
1669 hi = lo < 0 ? -1 : 0;
1672 /* We don't handle the case of the higher word not fitting
1673 entirely in either hi or lo. */
1678 subst_low_cuid = INSN_CUID (i2);
1679 added_sets_2 = added_sets_1 = 0;
1680 i2dest = SET_DEST (temp);
1682 SUBST (SET_SRC (temp),
1683 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1685 newpat = PATTERN (i2);
1686 goto validate_replacement;
1690 /* If we have no I1 and I2 looks like:
1691 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1693 make up a dummy I1 that is
1696 (set (reg:CC X) (compare:CC Y (const_int 0)))
1698 (We can ignore any trailing CLOBBERs.)
1700 This undoes a previous combination and allows us to match a branch-and-
1703 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1704 && XVECLEN (PATTERN (i2), 0) >= 2
1705 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1706 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1708 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1709 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1710 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1711 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1712 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1713 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1715 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1716 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1721 /* We make I1 with the same INSN_UID as I2. This gives it
1722 the same INSN_CUID for value tracking. Our fake I1 will
1723 never appear in the insn stream so giving it the same INSN_UID
1724 as I2 will not cause a problem. */
1726 subst_prev_insn = i1
1727 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1728 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1731 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1732 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1733 SET_DEST (PATTERN (i1)));
1738 /* Verify that I2 and I1 are valid for combining. */
1739 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1740 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1746 /* Record whether I2DEST is used in I2SRC and similarly for the other
1747 cases. Knowing this will help in register status updating below. */
1748 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1749 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1750 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1752 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1754 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1756 /* Ensure that I3's pattern can be the destination of combines. */
1757 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1758 i1 && i2dest_in_i1src && i1_feeds_i3,
1765 /* See if any of the insns is a MULT operation. Unless one is, we will
1766 reject a combination that is, since it must be slower. Be conservative
1768 if (GET_CODE (i2src) == MULT
1769 || (i1 != 0 && GET_CODE (i1src) == MULT)
1770 || (GET_CODE (PATTERN (i3)) == SET
1771 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1774 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1775 We used to do this EXCEPT in one case: I3 has a post-inc in an
1776 output operand. However, that exception can give rise to insns like
1778 which is a famous insn on the PDP-11 where the value of r3 used as the
1779 source was model-dependent. Avoid this sort of thing. */
1782 if (!(GET_CODE (PATTERN (i3)) == SET
1783 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1784 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1785 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1786 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1787 /* It's not the exception. */
1790 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1791 if (REG_NOTE_KIND (link) == REG_INC
1792 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1794 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1801 /* See if the SETs in I1 or I2 need to be kept around in the merged
1802 instruction: whenever the value set there is still needed past I3.
1803 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1805 For the SET in I1, we have two cases: If I1 and I2 independently
1806 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1807 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1808 in I1 needs to be kept around unless I1DEST dies or is set in either
1809 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1810 I1DEST. If so, we know I1 feeds into I2. */
1812 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1815 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1816 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1818 /* If the set in I2 needs to be kept around, we must make a copy of
1819 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1820 PATTERN (I2), we are only substituting for the original I1DEST, not into
1821 an already-substituted copy. This also prevents making self-referential
1822 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1825 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1826 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1830 i2pat = copy_rtx (i2pat);
1834 /* Substitute in the latest insn for the regs set by the earlier ones. */
1836 maxreg = max_reg_num ();
1840 /* It is possible that the source of I2 or I1 may be performing an
1841 unneeded operation, such as a ZERO_EXTEND of something that is known
1842 to have the high part zero. Handle that case by letting subst look at
1843 the innermost one of them.
1845 Another way to do this would be to have a function that tries to
1846 simplify a single insn instead of merging two or more insns. We don't
1847 do this because of the potential of infinite loops and because
1848 of the potential extra memory required. However, doing it the way
1849 we are is a bit of a kludge and doesn't catch all cases.
1851 But only do this if -fexpensive-optimizations since it slows things down
1852 and doesn't usually win. */
1854 if (flag_expensive_optimizations)
1856 /* Pass pc_rtx so no substitutions are done, just simplifications.
1857 The cases that we are interested in here do not involve the few
1858 cases were is_replaced is checked. */
1861 subst_low_cuid = INSN_CUID (i1);
1862 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1866 subst_low_cuid = INSN_CUID (i2);
1867 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1872 /* Many machines that don't use CC0 have insns that can both perform an
1873 arithmetic operation and set the condition code. These operations will
1874 be represented as a PARALLEL with the first element of the vector
1875 being a COMPARE of an arithmetic operation with the constant zero.
1876 The second element of the vector will set some pseudo to the result
1877 of the same arithmetic operation. If we simplify the COMPARE, we won't
1878 match such a pattern and so will generate an extra insn. Here we test
1879 for this case, where both the comparison and the operation result are
1880 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1881 I2SRC. Later we will make the PARALLEL that contains I2. */
1883 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1884 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1885 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1886 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1888 #ifdef EXTRA_CC_MODES
1890 enum machine_mode compare_mode;
1893 newpat = PATTERN (i3);
1894 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1898 #ifdef EXTRA_CC_MODES
1899 /* See if a COMPARE with the operand we substituted in should be done
1900 with the mode that is currently being used. If not, do the same
1901 processing we do in `subst' for a SET; namely, if the destination
1902 is used only once, try to replace it with a register of the proper
1903 mode and also replace the COMPARE. */
1904 if (undobuf.other_insn == 0
1905 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1906 &undobuf.other_insn))
1907 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1909 != GET_MODE (SET_DEST (newpat))))
1911 unsigned int regno = REGNO (SET_DEST (newpat));
1912 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1914 if (regno < FIRST_PSEUDO_REGISTER
1915 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1916 && ! REG_USERVAR_P (SET_DEST (newpat))))
1918 if (regno >= FIRST_PSEUDO_REGISTER)
1919 SUBST (regno_reg_rtx[regno], new_dest);
1921 SUBST (SET_DEST (newpat), new_dest);
1922 SUBST (XEXP (*cc_use, 0), new_dest);
1923 SUBST (SET_SRC (newpat),
1924 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1927 undobuf.other_insn = 0;
1934 n_occurrences = 0; /* `subst' counts here */
1936 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1937 need to make a unique copy of I2SRC each time we substitute it
1938 to avoid self-referential rtl. */
1940 subst_low_cuid = INSN_CUID (i2);
1941 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1942 ! i1_feeds_i3 && i1dest_in_i1src);
1945 /* Record whether i2's body now appears within i3's body. */
1946 i2_is_used = n_occurrences;
1949 /* If we already got a failure, don't try to do more. Otherwise,
1950 try to substitute in I1 if we have it. */
1952 if (i1 && GET_CODE (newpat) != CLOBBER)
1954 /* Before we can do this substitution, we must redo the test done
1955 above (see detailed comments there) that ensures that I1DEST
1956 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1958 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1966 subst_low_cuid = INSN_CUID (i1);
1967 newpat = subst (newpat, i1dest, i1src, 0, 0);
1971 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1972 to count all the ways that I2SRC and I1SRC can be used. */
1973 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1974 && i2_is_used + added_sets_2 > 1)
1975 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1976 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1978 /* Fail if we tried to make a new register (we used to abort, but there's
1979 really no reason to). */
1980 || max_reg_num () != maxreg
1981 /* Fail if we couldn't do something and have a CLOBBER. */
1982 || GET_CODE (newpat) == CLOBBER
1983 /* Fail if this new pattern is a MULT and we didn't have one before
1984 at the outer level. */
1985 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1992 /* If the actions of the earlier insns must be kept
1993 in addition to substituting them into the latest one,
1994 we must make a new PARALLEL for the latest insn
1995 to hold additional the SETs. */
1997 if (added_sets_1 || added_sets_2)
2001 if (GET_CODE (newpat) == PARALLEL)
2003 rtvec old = XVEC (newpat, 0);
2004 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2005 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2006 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2007 sizeof (old->elem[0]) * old->num_elem);
2012 total_sets = 1 + added_sets_1 + added_sets_2;
2013 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2014 XVECEXP (newpat, 0, 0) = old;
2018 XVECEXP (newpat, 0, --total_sets)
2019 = (GET_CODE (PATTERN (i1)) == PARALLEL
2020 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2024 /* If there is no I1, use I2's body as is. We used to also not do
2025 the subst call below if I2 was substituted into I3,
2026 but that could lose a simplification. */
2028 XVECEXP (newpat, 0, --total_sets) = i2pat;
2030 /* See comment where i2pat is assigned. */
2031 XVECEXP (newpat, 0, --total_sets)
2032 = subst (i2pat, i1dest, i1src, 0, 0);
2036 /* We come here when we are replacing a destination in I2 with the
2037 destination of I3. */
2038 validate_replacement:
2040 /* Note which hard regs this insn has as inputs. */
2041 mark_used_regs_combine (newpat);
2043 /* Is the result of combination a valid instruction? */
2044 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2046 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2047 the second SET's destination is a register that is unused. In that case,
2048 we just need the first SET. This can occur when simplifying a divmod
2049 insn. We *must* test for this case here because the code below that
2050 splits two independent SETs doesn't handle this case correctly when it
2051 updates the register status. Also check the case where the first
2052 SET's destination is unused. That would not cause incorrect code, but
2053 does cause an unneeded insn to remain. */
2055 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2056 && XVECLEN (newpat, 0) == 2
2057 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2058 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2059 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2060 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2061 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2062 && asm_noperands (newpat) < 0)
2064 newpat = XVECEXP (newpat, 0, 0);
2065 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2068 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2069 && XVECLEN (newpat, 0) == 2
2070 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2071 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2072 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2073 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2074 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2075 && asm_noperands (newpat) < 0)
2077 newpat = XVECEXP (newpat, 0, 1);
2078 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2081 /* If we were combining three insns and the result is a simple SET
2082 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2083 insns. There are two ways to do this. It can be split using a
2084 machine-specific method (like when you have an addition of a large
2085 constant) or by combine in the function find_split_point. */
2087 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2088 && asm_noperands (newpat) < 0)
2090 rtx m_split, *split;
2091 rtx ni2dest = i2dest;
2093 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2094 use I2DEST as a scratch register will help. In the latter case,
2095 convert I2DEST to the mode of the source of NEWPAT if we can. */
2097 m_split = split_insns (newpat, i3);
2099 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2100 inputs of NEWPAT. */
2102 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2103 possible to try that as a scratch reg. This would require adding
2104 more code to make it work though. */
2106 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2108 /* If I2DEST is a hard register or the only use of a pseudo,
2109 we can change its mode. */
2110 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2111 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2112 && GET_CODE (i2dest) == REG
2113 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2114 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2115 && ! REG_USERVAR_P (i2dest))))
2116 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2119 m_split = split_insns (gen_rtx_PARALLEL
2121 gen_rtvec (2, newpat,
2122 gen_rtx_CLOBBER (VOIDmode,
2125 /* If the split with the mode-changed register didn't work, try
2126 the original register. */
2127 if (! m_split && ni2dest != i2dest)
2130 m_split = split_insns (gen_rtx_PARALLEL
2132 gen_rtvec (2, newpat,
2133 gen_rtx_CLOBBER (VOIDmode,
2139 /* If we've split a jump pattern, we'll wind up with a sequence even
2140 with one instruction. We can handle that below, so extract it. */
2141 if (m_split && GET_CODE (m_split) == SEQUENCE
2142 && XVECLEN (m_split, 0) == 1)
2143 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2145 if (m_split && GET_CODE (m_split) != SEQUENCE)
2147 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2148 if (insn_code_number >= 0)
2151 else if (m_split && GET_CODE (m_split) == SEQUENCE
2152 && XVECLEN (m_split, 0) == 2
2153 && (next_real_insn (i2) == i3
2154 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2158 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2159 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2161 i3set = single_set (XVECEXP (m_split, 0, 1));
2162 i2set = single_set (XVECEXP (m_split, 0, 0));
2164 /* In case we changed the mode of I2DEST, replace it in the
2165 pseudo-register table here. We can't do it above in case this
2166 code doesn't get executed and we do a split the other way. */
2168 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2169 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2171 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2173 /* If I2 or I3 has multiple SETs, we won't know how to track
2174 register status, so don't use these insns. If I2's destination
2175 is used between I2 and I3, we also can't use these insns. */
2177 if (i2_code_number >= 0 && i2set && i3set
2178 && (next_real_insn (i2) == i3
2179 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2180 insn_code_number = recog_for_combine (&newi3pat, i3,
2182 if (insn_code_number >= 0)
2185 /* It is possible that both insns now set the destination of I3.
2186 If so, we must show an extra use of it. */
2188 if (insn_code_number >= 0)
2190 rtx new_i3_dest = SET_DEST (i3set);
2191 rtx new_i2_dest = SET_DEST (i2set);
2193 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2194 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2195 || GET_CODE (new_i3_dest) == SUBREG)
2196 new_i3_dest = XEXP (new_i3_dest, 0);
2198 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2199 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2200 || GET_CODE (new_i2_dest) == SUBREG)
2201 new_i2_dest = XEXP (new_i2_dest, 0);
2203 if (GET_CODE (new_i3_dest) == REG
2204 && GET_CODE (new_i2_dest) == REG
2205 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2206 REG_N_SETS (REGNO (new_i2_dest))++;
2210 /* If we can split it and use I2DEST, go ahead and see if that
2211 helps things be recognized. Verify that none of the registers
2212 are set between I2 and I3. */
2213 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2215 && GET_CODE (i2dest) == REG
2217 /* We need I2DEST in the proper mode. If it is a hard register
2218 or the only use of a pseudo, we can change its mode. */
2219 && (GET_MODE (*split) == GET_MODE (i2dest)
2220 || GET_MODE (*split) == VOIDmode
2221 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2222 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2223 && ! REG_USERVAR_P (i2dest)))
2224 && (next_real_insn (i2) == i3
2225 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2226 /* We can't overwrite I2DEST if its value is still used by
2228 && ! reg_referenced_p (i2dest, newpat))
2230 rtx newdest = i2dest;
2231 enum rtx_code split_code = GET_CODE (*split);
2232 enum machine_mode split_mode = GET_MODE (*split);
2234 /* Get NEWDEST as a register in the proper mode. We have already
2235 validated that we can do this. */
2236 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2238 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2240 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2241 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2244 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2245 an ASHIFT. This can occur if it was inside a PLUS and hence
2246 appeared to be a memory address. This is a kludge. */
2247 if (split_code == MULT
2248 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2249 && INTVAL (XEXP (*split, 1)) > 0
2250 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2252 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2253 XEXP (*split, 0), GEN_INT (i)));
2254 /* Update split_code because we may not have a multiply
2256 split_code = GET_CODE (*split);
2259 #ifdef INSN_SCHEDULING
2260 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2261 be written as a ZERO_EXTEND. */
2262 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2263 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2264 SUBREG_REG (*split)));
2267 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2268 SUBST (*split, newdest);
2269 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2271 /* If the split point was a MULT and we didn't have one before,
2272 don't use one now. */
2273 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2274 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2278 /* Check for a case where we loaded from memory in a narrow mode and
2279 then sign extended it, but we need both registers. In that case,
2280 we have a PARALLEL with both loads from the same memory location.
2281 We can split this into a load from memory followed by a register-register
2282 copy. This saves at least one insn, more if register allocation can
2285 We cannot do this if the destination of the second assignment is
2286 a register that we have already assumed is zero-extended. Similarly
2287 for a SUBREG of such a register. */
2289 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2290 && GET_CODE (newpat) == PARALLEL
2291 && XVECLEN (newpat, 0) == 2
2292 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2293 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2294 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2295 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2296 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2297 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2299 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2300 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2301 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2302 (GET_CODE (temp) == REG
2303 && reg_nonzero_bits[REGNO (temp)] != 0
2304 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2305 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2306 && (reg_nonzero_bits[REGNO (temp)]
2307 != GET_MODE_MASK (word_mode))))
2308 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2309 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2310 (GET_CODE (temp) == REG
2311 && reg_nonzero_bits[REGNO (temp)] != 0
2312 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2313 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2314 && (reg_nonzero_bits[REGNO (temp)]
2315 != GET_MODE_MASK (word_mode)))))
2316 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2317 SET_SRC (XVECEXP (newpat, 0, 1)))
2318 && ! find_reg_note (i3, REG_UNUSED,
2319 SET_DEST (XVECEXP (newpat, 0, 0))))
2323 newi2pat = XVECEXP (newpat, 0, 0);
2324 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2325 newpat = XVECEXP (newpat, 0, 1);
2326 SUBST (SET_SRC (newpat),
2327 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2328 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2330 if (i2_code_number >= 0)
2331 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2333 if (insn_code_number >= 0)
2338 /* If we will be able to accept this, we have made a change to the
2339 destination of I3. This can invalidate a LOG_LINKS pointing
2340 to I3. No other part of combine.c makes such a transformation.
2342 The new I3 will have a destination that was previously the
2343 destination of I1 or I2 and which was used in i2 or I3. Call
2344 distribute_links to make a LOG_LINK from the next use of
2345 that destination. */
2347 PATTERN (i3) = newpat;
2348 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2350 /* I3 now uses what used to be its destination and which is
2351 now I2's destination. That means we need a LOG_LINK from
2352 I3 to I2. But we used to have one, so we still will.
2354 However, some later insn might be using I2's dest and have
2355 a LOG_LINK pointing at I3. We must remove this link.
2356 The simplest way to remove the link is to point it at I1,
2357 which we know will be a NOTE. */
2359 for (insn = NEXT_INSN (i3);
2360 insn && (this_basic_block == n_basic_blocks - 1
2361 || insn != BLOCK_HEAD (this_basic_block + 1));
2362 insn = NEXT_INSN (insn))
2364 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2366 for (link = LOG_LINKS (insn); link;
2367 link = XEXP (link, 1))
2368 if (XEXP (link, 0) == i3)
2369 XEXP (link, 0) = i1;
2377 /* Similarly, check for a case where we have a PARALLEL of two independent
2378 SETs but we started with three insns. In this case, we can do the sets
2379 as two separate insns. This case occurs when some SET allows two
2380 other insns to combine, but the destination of that SET is still live. */
2382 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2383 && GET_CODE (newpat) == PARALLEL
2384 && XVECLEN (newpat, 0) == 2
2385 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2387 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2388 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2389 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2390 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2391 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2393 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2394 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2395 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2396 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2397 XVECEXP (newpat, 0, 0))
2398 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2399 XVECEXP (newpat, 0, 1))
2400 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2401 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2403 /* Normally, it doesn't matter which of the two is done first,
2404 but it does if one references cc0. In that case, it has to
2407 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2409 newi2pat = XVECEXP (newpat, 0, 0);
2410 newpat = XVECEXP (newpat, 0, 1);
2415 newi2pat = XVECEXP (newpat, 0, 1);
2416 newpat = XVECEXP (newpat, 0, 0);
2419 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2421 if (i2_code_number >= 0)
2422 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2425 /* If it still isn't recognized, fail and change things back the way they
2427 if ((insn_code_number < 0
2428 /* Is the result a reasonable ASM_OPERANDS? */
2429 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2435 /* If we had to change another insn, make sure it is valid also. */
2436 if (undobuf.other_insn)
2438 rtx other_pat = PATTERN (undobuf.other_insn);
2439 rtx new_other_notes;
2442 CLEAR_HARD_REG_SET (newpat_used_regs);
2444 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2447 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2453 PATTERN (undobuf.other_insn) = other_pat;
2455 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2456 are still valid. Then add any non-duplicate notes added by
2457 recog_for_combine. */
2458 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2460 next = XEXP (note, 1);
2462 if (REG_NOTE_KIND (note) == REG_UNUSED
2463 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2465 if (GET_CODE (XEXP (note, 0)) == REG)
2466 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2468 remove_note (undobuf.other_insn, note);
2472 for (note = new_other_notes; note; note = XEXP (note, 1))
2473 if (GET_CODE (XEXP (note, 0)) == REG)
2474 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2476 distribute_notes (new_other_notes, undobuf.other_insn,
2477 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2480 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2481 they are adjacent to each other or not. */
2483 rtx p = prev_nonnote_insn (i3);
2484 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2485 && sets_cc0_p (newi2pat))
2493 /* We now know that we can do this combination. Merge the insns and
2494 update the status of registers and LOG_LINKS. */
2497 rtx i3notes, i2notes, i1notes = 0;
2498 rtx i3links, i2links, i1links = 0;
2501 /* Compute which registers we expect to eliminate. newi2pat may be setting
2502 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2503 same as i3dest, in which case newi2pat may be setting i1dest. */
2504 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2505 || i2dest_in_i2src || i2dest_in_i1src
2507 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2508 || (newi2pat && reg_set_p (i1dest, newi2pat))
2511 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2513 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2514 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2516 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2518 /* Ensure that we do not have something that should not be shared but
2519 occurs multiple times in the new insns. Check this by first
2520 resetting all the `used' flags and then copying anything is shared. */
2522 reset_used_flags (i3notes);
2523 reset_used_flags (i2notes);
2524 reset_used_flags (i1notes);
2525 reset_used_flags (newpat);
2526 reset_used_flags (newi2pat);
2527 if (undobuf.other_insn)
2528 reset_used_flags (PATTERN (undobuf.other_insn));
2530 i3notes = copy_rtx_if_shared (i3notes);
2531 i2notes = copy_rtx_if_shared (i2notes);
2532 i1notes = copy_rtx_if_shared (i1notes);
2533 newpat = copy_rtx_if_shared (newpat);
2534 newi2pat = copy_rtx_if_shared (newi2pat);
2535 if (undobuf.other_insn)
2536 reset_used_flags (PATTERN (undobuf.other_insn));
2538 INSN_CODE (i3) = insn_code_number;
2539 PATTERN (i3) = newpat;
2541 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2543 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2545 reset_used_flags (call_usage);
2546 call_usage = copy_rtx (call_usage);
2549 replace_rtx (call_usage, i2dest, i2src);
2552 replace_rtx (call_usage, i1dest, i1src);
2554 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2557 if (undobuf.other_insn)
2558 INSN_CODE (undobuf.other_insn) = other_code_number;
2560 /* We had one special case above where I2 had more than one set and
2561 we replaced a destination of one of those sets with the destination
2562 of I3. In that case, we have to update LOG_LINKS of insns later
2563 in this basic block. Note that this (expensive) case is rare.
2565 Also, in this case, we must pretend that all REG_NOTEs for I2
2566 actually came from I3, so that REG_UNUSED notes from I2 will be
2567 properly handled. */
2569 if (i3_subst_into_i2)
2571 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2572 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2573 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2574 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2575 && ! find_reg_note (i2, REG_UNUSED,
2576 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2577 for (temp = NEXT_INSN (i2);
2578 temp && (this_basic_block == n_basic_blocks - 1
2579 || BLOCK_HEAD (this_basic_block) != temp);
2580 temp = NEXT_INSN (temp))
2581 if (temp != i3 && INSN_P (temp))
2582 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2583 if (XEXP (link, 0) == i2)
2584 XEXP (link, 0) = i3;
2589 while (XEXP (link, 1))
2590 link = XEXP (link, 1);
2591 XEXP (link, 1) = i2notes;
2605 INSN_CODE (i2) = i2_code_number;
2606 PATTERN (i2) = newi2pat;
2610 PUT_CODE (i2, NOTE);
2611 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2612 NOTE_SOURCE_FILE (i2) = 0;
2619 PUT_CODE (i1, NOTE);
2620 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2621 NOTE_SOURCE_FILE (i1) = 0;
2624 /* Get death notes for everything that is now used in either I3 or
2625 I2 and used to die in a previous insn. If we built two new
2626 patterns, move from I1 to I2 then I2 to I3 so that we get the
2627 proper movement on registers that I2 modifies. */
2631 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2632 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2635 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2638 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2640 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2643 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2646 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2649 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2652 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2653 know these are REG_UNUSED and want them to go to the desired insn,
2654 so we always pass it as i3. We have not counted the notes in
2655 reg_n_deaths yet, so we need to do so now. */
2657 if (newi2pat && new_i2_notes)
2659 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2660 if (GET_CODE (XEXP (temp, 0)) == REG)
2661 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2663 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2668 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2669 if (GET_CODE (XEXP (temp, 0)) == REG)
2670 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2672 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2675 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2676 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2677 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2678 in that case, it might delete I2. Similarly for I2 and I1.
2679 Show an additional death due to the REG_DEAD note we make here. If
2680 we discard it in distribute_notes, we will decrement it again. */
2684 if (GET_CODE (i3dest_killed) == REG)
2685 REG_N_DEATHS (REGNO (i3dest_killed))++;
2687 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2688 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2690 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2694 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2698 if (i2dest_in_i2src)
2700 if (GET_CODE (i2dest) == REG)
2701 REG_N_DEATHS (REGNO (i2dest))++;
2703 if (newi2pat && reg_set_p (i2dest, newi2pat))
2704 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2705 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2707 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2708 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2709 NULL_RTX, NULL_RTX);
2712 if (i1dest_in_i1src)
2714 if (GET_CODE (i1dest) == REG)
2715 REG_N_DEATHS (REGNO (i1dest))++;
2717 if (newi2pat && reg_set_p (i1dest, newi2pat))
2718 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2719 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2721 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2722 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2723 NULL_RTX, NULL_RTX);
2726 distribute_links (i3links);
2727 distribute_links (i2links);
2728 distribute_links (i1links);
2730 if (GET_CODE (i2dest) == REG)
2733 rtx i2_insn = 0, i2_val = 0, set;
2735 /* The insn that used to set this register doesn't exist, and
2736 this life of the register may not exist either. See if one of
2737 I3's links points to an insn that sets I2DEST. If it does,
2738 that is now the last known value for I2DEST. If we don't update
2739 this and I2 set the register to a value that depended on its old
2740 contents, we will get confused. If this insn is used, thing
2741 will be set correctly in combine_instructions. */
2743 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2744 if ((set = single_set (XEXP (link, 0))) != 0
2745 && rtx_equal_p (i2dest, SET_DEST (set)))
2746 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2748 record_value_for_reg (i2dest, i2_insn, i2_val);
2750 /* If the reg formerly set in I2 died only once and that was in I3,
2751 zero its use count so it won't make `reload' do any work. */
2753 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2754 && ! i2dest_in_i2src)
2756 regno = REGNO (i2dest);
2757 REG_N_SETS (regno)--;
2761 if (i1 && GET_CODE (i1dest) == REG)
2764 rtx i1_insn = 0, i1_val = 0, set;
2766 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2767 if ((set = single_set (XEXP (link, 0))) != 0
2768 && rtx_equal_p (i1dest, SET_DEST (set)))
2769 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2771 record_value_for_reg (i1dest, i1_insn, i1_val);
2773 regno = REGNO (i1dest);
2774 if (! added_sets_1 && ! i1dest_in_i1src)
2775 REG_N_SETS (regno)--;
2778 /* Update reg_nonzero_bits et al for any changes that may have been made
2779 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2780 important. Because newi2pat can affect nonzero_bits of newpat */
2782 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2783 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2785 /* Set new_direct_jump_p if a new return or simple jump instruction
2788 If I3 is now an unconditional jump, ensure that it has a
2789 BARRIER following it since it may have initially been a
2790 conditional jump. It may also be the last nonnote insn. */
2792 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2794 *new_direct_jump_p = 1;
2796 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2797 || GET_CODE (temp) != BARRIER)
2798 emit_barrier_after (i3);
2800 /* An NOOP jump does not need barrier, but it does need cleaning up
2802 if (GET_CODE (newpat) == SET
2803 && SET_SRC (newpat) == pc_rtx
2804 && SET_DEST (newpat) == pc_rtx)
2805 *new_direct_jump_p = 1;
2808 combine_successes++;
2811 /* Clear this here, so that subsequent get_last_value calls are not
2813 subst_prev_insn = NULL_RTX;
2815 if (added_links_insn
2816 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2817 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2818 return added_links_insn;
2820 return newi2pat ? i2 : i3;
2823 /* Undo all the modifications recorded in undobuf. */
2828 struct undo *undo, *next;
2830 for (undo = undobuf.undos; undo; undo = next)
2834 *undo->where.i = undo->old_contents.i;
2836 *undo->where.r = undo->old_contents.r;
2838 undo->next = undobuf.frees;
2839 undobuf.frees = undo;
2844 /* Clear this here, so that subsequent get_last_value calls are not
2846 subst_prev_insn = NULL_RTX;
2849 /* We've committed to accepting the changes we made. Move all
2850 of the undos to the free list. */
2855 struct undo *undo, *next;
2857 for (undo = undobuf.undos; undo; undo = next)
2860 undo->next = undobuf.frees;
2861 undobuf.frees = undo;
2867 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2868 where we have an arithmetic expression and return that point. LOC will
2871 try_combine will call this function to see if an insn can be split into
2875 find_split_point (loc, insn)
2880 enum rtx_code code = GET_CODE (x);
2882 unsigned HOST_WIDE_INT len = 0;
2883 HOST_WIDE_INT pos = 0;
2885 rtx inner = NULL_RTX;
2887 /* First special-case some codes. */
2891 #ifdef INSN_SCHEDULING
2892 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2894 if (GET_CODE (SUBREG_REG (x)) == MEM)
2897 return find_split_point (&SUBREG_REG (x), insn);
2901 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2902 using LO_SUM and HIGH. */
2903 if (GET_CODE (XEXP (x, 0)) == CONST
2904 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2907 gen_rtx_LO_SUM (Pmode,
2908 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2910 return &XEXP (XEXP (x, 0), 0);
2914 /* If we have a PLUS whose second operand is a constant and the
2915 address is not valid, perhaps will can split it up using
2916 the machine-specific way to split large constants. We use
2917 the first pseudo-reg (one of the virtual regs) as a placeholder;
2918 it will not remain in the result. */
2919 if (GET_CODE (XEXP (x, 0)) == PLUS
2920 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2921 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2923 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2924 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2927 /* This should have produced two insns, each of which sets our
2928 placeholder. If the source of the second is a valid address,
2929 we can make put both sources together and make a split point
2932 if (seq && XVECLEN (seq, 0) == 2
2933 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2934 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2935 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2936 && ! reg_mentioned_p (reg,
2937 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2938 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2939 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2940 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2941 && memory_address_p (GET_MODE (x),
2942 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2944 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2945 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2947 /* Replace the placeholder in SRC2 with SRC1. If we can
2948 find where in SRC2 it was placed, that can become our
2949 split point and we can replace this address with SRC2.
2950 Just try two obvious places. */
2952 src2 = replace_rtx (src2, reg, src1);
2954 if (XEXP (src2, 0) == src1)
2955 split = &XEXP (src2, 0);
2956 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2957 && XEXP (XEXP (src2, 0), 0) == src1)
2958 split = &XEXP (XEXP (src2, 0), 0);
2962 SUBST (XEXP (x, 0), src2);
2967 /* If that didn't work, perhaps the first operand is complex and
2968 needs to be computed separately, so make a split point there.
2969 This will occur on machines that just support REG + CONST
2970 and have a constant moved through some previous computation. */
2972 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2973 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2974 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2976 return &XEXP (XEXP (x, 0), 0);
2982 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2983 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2984 we need to put the operand into a register. So split at that
2987 if (SET_DEST (x) == cc0_rtx
2988 && GET_CODE (SET_SRC (x)) != COMPARE
2989 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2990 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2991 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2992 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2993 return &SET_SRC (x);
2996 /* See if we can split SET_SRC as it stands. */
2997 split = find_split_point (&SET_SRC (x), insn);
2998 if (split && split != &SET_SRC (x))
3001 /* See if we can split SET_DEST as it stands. */
3002 split = find_split_point (&SET_DEST (x), insn);
3003 if (split && split != &SET_DEST (x))
3006 /* See if this is a bitfield assignment with everything constant. If
3007 so, this is an IOR of an AND, so split it into that. */
3008 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3009 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3010 <= HOST_BITS_PER_WIDE_INT)
3011 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3012 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3013 && GET_CODE (SET_SRC (x)) == CONST_INT
3014 && ((INTVAL (XEXP (SET_DEST (x), 1))
3015 + INTVAL (XEXP (SET_DEST (x), 2)))
3016 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3017 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3019 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3020 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3021 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3022 rtx dest = XEXP (SET_DEST (x), 0);
3023 enum machine_mode mode = GET_MODE (dest);
3024 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3026 if (BITS_BIG_ENDIAN)
3027 pos = GET_MODE_BITSIZE (mode) - len - pos;
3031 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3034 gen_binary (IOR, mode,
3035 gen_binary (AND, mode, dest,
3036 GEN_INT (~(mask << pos)
3037 & GET_MODE_MASK (mode))),
3038 GEN_INT (src << pos)));
3040 SUBST (SET_DEST (x), dest);
3042 split = find_split_point (&SET_SRC (x), insn);
3043 if (split && split != &SET_SRC (x))
3047 /* Otherwise, see if this is an operation that we can split into two.
3048 If so, try to split that. */
3049 code = GET_CODE (SET_SRC (x));
3054 /* If we are AND'ing with a large constant that is only a single
3055 bit and the result is only being used in a context where we
3056 need to know if it is zero or non-zero, replace it with a bit
3057 extraction. This will avoid the large constant, which might
3058 have taken more than one insn to make. If the constant were
3059 not a valid argument to the AND but took only one insn to make,
3060 this is no worse, but if it took more than one insn, it will
3063 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3064 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3065 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3066 && GET_CODE (SET_DEST (x)) == REG
3067 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3068 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3069 && XEXP (*split, 0) == SET_DEST (x)
3070 && XEXP (*split, 1) == const0_rtx)
3072 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3073 XEXP (SET_SRC (x), 0),
3074 pos, NULL_RTX, 1, 1, 0, 0);
3075 if (extraction != 0)
3077 SUBST (SET_SRC (x), extraction);
3078 return find_split_point (loc, insn);
3084 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3085 is known to be on, this can be converted into a NEG of a shift. */
3086 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3087 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3088 && 1 <= (pos = exact_log2
3089 (nonzero_bits (XEXP (SET_SRC (x), 0),
3090 GET_MODE (XEXP (SET_SRC (x), 0))))))
3092 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3096 gen_rtx_LSHIFTRT (mode,
3097 XEXP (SET_SRC (x), 0),
3100 split = find_split_point (&SET_SRC (x), insn);
3101 if (split && split != &SET_SRC (x))
3107 inner = XEXP (SET_SRC (x), 0);
3109 /* We can't optimize if either mode is a partial integer
3110 mode as we don't know how many bits are significant
3112 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3113 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3117 len = GET_MODE_BITSIZE (GET_MODE (inner));
3123 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3124 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3126 inner = XEXP (SET_SRC (x), 0);
3127 len = INTVAL (XEXP (SET_SRC (x), 1));
3128 pos = INTVAL (XEXP (SET_SRC (x), 2));
3130 if (BITS_BIG_ENDIAN)
3131 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3132 unsignedp = (code == ZERO_EXTRACT);
3140 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3142 enum machine_mode mode = GET_MODE (SET_SRC (x));
3144 /* For unsigned, we have a choice of a shift followed by an
3145 AND or two shifts. Use two shifts for field sizes where the
3146 constant might be too large. We assume here that we can
3147 always at least get 8-bit constants in an AND insn, which is
3148 true for every current RISC. */
3150 if (unsignedp && len <= 8)
3155 (mode, gen_lowpart_for_combine (mode, inner),
3157 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3159 split = find_split_point (&SET_SRC (x), insn);
3160 if (split && split != &SET_SRC (x))
3167 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3168 gen_rtx_ASHIFT (mode,
3169 gen_lowpart_for_combine (mode, inner),
3170 GEN_INT (GET_MODE_BITSIZE (mode)
3172 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3174 split = find_split_point (&SET_SRC (x), insn);
3175 if (split && split != &SET_SRC (x))
3180 /* See if this is a simple operation with a constant as the second
3181 operand. It might be that this constant is out of range and hence
3182 could be used as a split point. */
3183 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3184 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3185 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3186 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3187 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3188 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3189 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3191 return &XEXP (SET_SRC (x), 1);
3193 /* Finally, see if this is a simple operation with its first operand
3194 not in a register. The operation might require this operand in a
3195 register, so return it as a split point. We can always do this
3196 because if the first operand were another operation, we would have
3197 already found it as a split point. */
3198 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3199 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3200 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3201 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3202 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3203 return &XEXP (SET_SRC (x), 0);
3209 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3210 it is better to write this as (not (ior A B)) so we can split it.
3211 Similarly for IOR. */
3212 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3215 gen_rtx_NOT (GET_MODE (x),
3216 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3218 XEXP (XEXP (x, 0), 0),
3219 XEXP (XEXP (x, 1), 0))));
3220 return find_split_point (loc, insn);
3223 /* Many RISC machines have a large set of logical insns. If the
3224 second operand is a NOT, put it first so we will try to split the
3225 other operand first. */
3226 if (GET_CODE (XEXP (x, 1)) == NOT)
3228 rtx tem = XEXP (x, 0);
3229 SUBST (XEXP (x, 0), XEXP (x, 1));
3230 SUBST (XEXP (x, 1), tem);
3238 /* Otherwise, select our actions depending on our rtx class. */
3239 switch (GET_RTX_CLASS (code))
3241 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3243 split = find_split_point (&XEXP (x, 2), insn);
3246 /* ... fall through ... */
3250 split = find_split_point (&XEXP (x, 1), insn);
3253 /* ... fall through ... */
3255 /* Some machines have (and (shift ...) ...) insns. If X is not
3256 an AND, but XEXP (X, 0) is, use it as our split point. */
3257 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3258 return &XEXP (x, 0);
3260 split = find_split_point (&XEXP (x, 0), insn);
3266 /* Otherwise, we don't have a split point. */
3270 /* Throughout X, replace FROM with TO, and return the result.
3271 The result is TO if X is FROM;
3272 otherwise the result is X, but its contents may have been modified.
3273 If they were modified, a record was made in undobuf so that
3274 undo_all will (among other things) return X to its original state.
3276 If the number of changes necessary is too much to record to undo,
3277 the excess changes are not made, so the result is invalid.
3278 The changes already made can still be undone.
3279 undobuf.num_undo is incremented for such changes, so by testing that
3280 the caller can tell whether the result is valid.
3282 `n_occurrences' is incremented each time FROM is replaced.
3284 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3286 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3287 by copying if `n_occurrences' is non-zero. */
3290 subst (x, from, to, in_dest, unique_copy)
3295 enum rtx_code code = GET_CODE (x);
3296 enum machine_mode op0_mode = VOIDmode;
3301 /* Two expressions are equal if they are identical copies of a shared
3302 RTX or if they are both registers with the same register number
3305 #define COMBINE_RTX_EQUAL_P(X,Y) \
3307 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3308 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3310 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3313 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3316 /* If X and FROM are the same register but different modes, they will
3317 not have been seen as equal above. However, flow.c will make a
3318 LOG_LINKS entry for that case. If we do nothing, we will try to
3319 rerecognize our original insn and, when it succeeds, we will
3320 delete the feeding insn, which is incorrect.
3322 So force this insn not to match in this (rare) case. */
3323 if (! in_dest && code == REG && GET_CODE (from) == REG
3324 && REGNO (x) == REGNO (from))
3325 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3327 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3328 of which may contain things that can be combined. */
3329 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3332 /* It is possible to have a subexpression appear twice in the insn.
3333 Suppose that FROM is a register that appears within TO.
3334 Then, after that subexpression has been scanned once by `subst',
3335 the second time it is scanned, TO may be found. If we were
3336 to scan TO here, we would find FROM within it and create a
3337 self-referent rtl structure which is completely wrong. */
3338 if (COMBINE_RTX_EQUAL_P (x, to))
3341 /* Parallel asm_operands need special attention because all of the
3342 inputs are shared across the arms. Furthermore, unsharing the
3343 rtl results in recognition failures. Failure to handle this case
3344 specially can result in circular rtl.
3346 Solve this by doing a normal pass across the first entry of the
3347 parallel, and only processing the SET_DESTs of the subsequent
3350 if (code == PARALLEL
3351 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3352 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3354 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3356 /* If this substitution failed, this whole thing fails. */
3357 if (GET_CODE (new) == CLOBBER
3358 && XEXP (new, 0) == const0_rtx)
3361 SUBST (XVECEXP (x, 0, 0), new);
3363 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3365 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3367 if (GET_CODE (dest) != REG
3368 && GET_CODE (dest) != CC0
3369 && GET_CODE (dest) != PC)
3371 new = subst (dest, from, to, 0, unique_copy);
3373 /* If this substitution failed, this whole thing fails. */
3374 if (GET_CODE (new) == CLOBBER
3375 && XEXP (new, 0) == const0_rtx)
3378 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3384 len = GET_RTX_LENGTH (code);
3385 fmt = GET_RTX_FORMAT (code);
3387 /* We don't need to process a SET_DEST that is a register, CC0,
3388 or PC, so set up to skip this common case. All other cases
3389 where we want to suppress replacing something inside a
3390 SET_SRC are handled via the IN_DEST operand. */
3392 && (GET_CODE (SET_DEST (x)) == REG
3393 || GET_CODE (SET_DEST (x)) == CC0
3394 || GET_CODE (SET_DEST (x)) == PC))
3397 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3400 op0_mode = GET_MODE (XEXP (x, 0));
3402 for (i = 0; i < len; i++)
3407 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3409 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3411 new = (unique_copy && n_occurrences
3412 ? copy_rtx (to) : to);
3417 new = subst (XVECEXP (x, i, j), from, to, 0,
3420 /* If this substitution failed, this whole thing
3422 if (GET_CODE (new) == CLOBBER
3423 && XEXP (new, 0) == const0_rtx)
3427 SUBST (XVECEXP (x, i, j), new);
3430 else if (fmt[i] == 'e')
3432 /* If this is a register being set, ignore it. */
3435 && (code == SUBREG || code == STRICT_LOW_PART
3436 || code == ZERO_EXTRACT)
3438 && GET_CODE (new) == REG)
3441 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3443 /* In general, don't install a subreg involving two
3444 modes not tieable. It can worsen register
3445 allocation, and can even make invalid reload
3446 insns, since the reg inside may need to be copied
3447 from in the outside mode, and that may be invalid
3448 if it is an fp reg copied in integer mode.
3450 We allow two exceptions to this: It is valid if
3451 it is inside another SUBREG and the mode of that
3452 SUBREG and the mode of the inside of TO is
3453 tieable and it is valid if X is a SET that copies
3456 if (GET_CODE (to) == SUBREG
3457 && ! MODES_TIEABLE_P (GET_MODE (to),
3458 GET_MODE (SUBREG_REG (to)))
3459 && ! (code == SUBREG
3460 && MODES_TIEABLE_P (GET_MODE (x),
3461 GET_MODE (SUBREG_REG (to))))
3463 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3466 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3468 #ifdef CLASS_CANNOT_CHANGE_MODE
3470 && GET_CODE (to) == REG
3471 && REGNO (to) < FIRST_PSEUDO_REGISTER
3472 && (TEST_HARD_REG_BIT
3473 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3475 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3477 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3480 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3484 /* If we are in a SET_DEST, suppress most cases unless we
3485 have gone inside a MEM, in which case we want to
3486 simplify the address. We assume here that things that
3487 are actually part of the destination have their inner
3488 parts in the first expression. This is true for SUBREG,
3489 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3490 things aside from REG and MEM that should appear in a
3492 new = subst (XEXP (x, i), from, to,
3494 && (code == SUBREG || code == STRICT_LOW_PART
3495 || code == ZERO_EXTRACT))
3497 && i == 0), unique_copy);
3499 /* If we found that we will have to reject this combination,
3500 indicate that by returning the CLOBBER ourselves, rather than
3501 an expression containing it. This will speed things up as
3502 well as prevent accidents where two CLOBBERs are considered
3503 to be equal, thus producing an incorrect simplification. */
3505 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3508 SUBST (XEXP (x, i), new);
3513 /* Try to simplify X. If the simplification changed the code, it is likely
3514 that further simplification will help, so loop, but limit the number
3515 of repetitions that will be performed. */
3517 for (i = 0; i < 4; i++)
3519 /* If X is sufficiently simple, don't bother trying to do anything
3521 if (code != CONST_INT && code != REG && code != CLOBBER)
3522 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3524 if (GET_CODE (x) == code)
3527 code = GET_CODE (x);
3529 /* We no longer know the original mode of operand 0 since we
3530 have changed the form of X) */
3531 op0_mode = VOIDmode;
3537 /* Simplify X, a piece of RTL. We just operate on the expression at the
3538 outer level; call `subst' to simplify recursively. Return the new
3541 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3542 will be the iteration even if an expression with a code different from
3543 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3546 combine_simplify_rtx (x, op0_mode, last, in_dest)
3548 enum machine_mode op0_mode;
3552 enum rtx_code code = GET_CODE (x);
3553 enum machine_mode mode = GET_MODE (x);
3558 /* If this is a commutative operation, put a constant last and a complex
3559 expression first. We don't need to do this for comparisons here. */
3560 if (GET_RTX_CLASS (code) == 'c'
3561 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3564 SUBST (XEXP (x, 0), XEXP (x, 1));
3565 SUBST (XEXP (x, 1), temp);
3568 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3569 sign extension of a PLUS with a constant, reverse the order of the sign
3570 extension and the addition. Note that this not the same as the original
3571 code, but overflow is undefined for signed values. Also note that the
3572 PLUS will have been partially moved "inside" the sign-extension, so that
3573 the first operand of X will really look like:
3574 (ashiftrt (plus (ashift A C4) C5) C4).
3576 (plus (ashiftrt (ashift A C4) C2) C4)
3577 and replace the first operand of X with that expression. Later parts
3578 of this function may simplify the expression further.
3580 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3581 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3582 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3584 We do this to simplify address expressions. */
3586 if ((code == PLUS || code == MINUS || code == MULT)
3587 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3588 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3589 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3590 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3591 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3592 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3593 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3594 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3595 XEXP (XEXP (XEXP (x, 0), 0), 1),
3596 XEXP (XEXP (x, 0), 1))) != 0)
3599 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3600 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3601 INTVAL (XEXP (XEXP (x, 0), 1)));
3603 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3604 INTVAL (XEXP (XEXP (x, 0), 1)));
3606 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3609 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3610 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3611 things. Check for cases where both arms are testing the same
3614 Don't do anything if all operands are very simple. */
3616 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3617 || GET_RTX_CLASS (code) == '<')
3618 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3619 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3620 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3622 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3623 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3624 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3626 || (GET_RTX_CLASS (code) == '1'
3627 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3628 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3629 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3632 rtx cond, true_rtx, false_rtx;
3634 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3636 /* If everything is a comparison, what we have is highly unlikely
3637 to be simpler, so don't use it. */
3638 && ! (GET_RTX_CLASS (code) == '<'
3639 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3640 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3642 rtx cop1 = const0_rtx;
3643 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3645 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3648 /* Simplify the alternative arms; this may collapse the true and
3649 false arms to store-flag values. */
3650 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3651 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3653 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3654 is unlikely to be simpler. */
3655 if (general_operand (true_rtx, VOIDmode)
3656 && general_operand (false_rtx, VOIDmode))
3658 /* Restarting if we generate a store-flag expression will cause
3659 us to loop. Just drop through in this case. */
3661 /* If the result values are STORE_FLAG_VALUE and zero, we can
3662 just make the comparison operation. */
3663 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3664 x = gen_binary (cond_code, mode, cond, cop1);
3665 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3666 && reverse_condition (cond_code) != UNKNOWN)
3667 x = gen_binary (reverse_condition (cond_code),
3670 /* Likewise, we can make the negate of a comparison operation
3671 if the result values are - STORE_FLAG_VALUE and zero. */
3672 else if (GET_CODE (true_rtx) == CONST_INT
3673 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3674 && false_rtx == const0_rtx)
3675 x = simplify_gen_unary (NEG, mode,
3676 gen_binary (cond_code, mode, cond,
3679 else if (GET_CODE (false_rtx) == CONST_INT
3680 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3681 && true_rtx == const0_rtx)
3682 x = simplify_gen_unary (NEG, mode,
3683 gen_binary (reverse_condition
3688 return gen_rtx_IF_THEN_ELSE (mode,
3689 gen_binary (cond_code, VOIDmode,
3691 true_rtx, false_rtx);
3693 code = GET_CODE (x);
3694 op0_mode = VOIDmode;
3699 /* Try to fold this expression in case we have constants that weren't
3702 switch (GET_RTX_CLASS (code))
3705 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3709 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3710 if (cmp_mode == VOIDmode)
3712 cmp_mode = GET_MODE (XEXP (x, 1));
3713 if (cmp_mode == VOIDmode)
3714 cmp_mode = op0_mode;
3716 temp = simplify_relational_operation (code, cmp_mode,
3717 XEXP (x, 0), XEXP (x, 1));
3719 #ifdef FLOAT_STORE_FLAG_VALUE
3720 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3722 if (temp == const0_rtx)
3723 temp = CONST0_RTX (mode);
3725 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3731 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3735 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3736 XEXP (x, 1), XEXP (x, 2));
3743 code = GET_CODE (temp);
3744 op0_mode = VOIDmode;
3745 mode = GET_MODE (temp);
3748 /* First see if we can apply the inverse distributive law. */
3749 if (code == PLUS || code == MINUS
3750 || code == AND || code == IOR || code == XOR)
3752 x = apply_distributive_law (x);
3753 code = GET_CODE (x);
3754 op0_mode = VOIDmode;
3757 /* If CODE is an associative operation not otherwise handled, see if we
3758 can associate some operands. This can win if they are constants or
3759 if they are logically related (i.e. (a & b) & a). */
3760 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3761 || code == AND || code == IOR || code == XOR
3762 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3763 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3764 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3766 if (GET_CODE (XEXP (x, 0)) == code)
3768 rtx other = XEXP (XEXP (x, 0), 0);
3769 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3770 rtx inner_op1 = XEXP (x, 1);
3773 /* Make sure we pass the constant operand if any as the second
3774 one if this is a commutative operation. */
3775 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3777 rtx tem = inner_op0;
3778 inner_op0 = inner_op1;
3781 inner = simplify_binary_operation (code == MINUS ? PLUS
3782 : code == DIV ? MULT
3784 mode, inner_op0, inner_op1);
3786 /* For commutative operations, try the other pair if that one
3788 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3790 other = XEXP (XEXP (x, 0), 1);
3791 inner = simplify_binary_operation (code, mode,
3792 XEXP (XEXP (x, 0), 0),
3797 return gen_binary (code, mode, other, inner);
3801 /* A little bit of algebraic simplification here. */
3805 /* Ensure that our address has any ASHIFTs converted to MULT in case
3806 address-recognizing predicates are called later. */
3807 temp = make_compound_operation (XEXP (x, 0), MEM);
3808 SUBST (XEXP (x, 0), temp);
3812 if (op0_mode == VOIDmode)
3813 op0_mode = GET_MODE (SUBREG_REG (x));
3815 /* simplify_subreg can't use gen_lowpart_for_combine. */
3816 if (CONSTANT_P (SUBREG_REG (x))
3817 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3818 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3820 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3824 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3830 /* Note that we cannot do any narrowing for non-constants since
3831 we might have been counting on using the fact that some bits were
3832 zero. We now do this in the SET. */
3837 /* (not (plus X -1)) can become (neg X). */
3838 if (GET_CODE (XEXP (x, 0)) == PLUS
3839 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3840 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3842 /* Similarly, (not (neg X)) is (plus X -1). */
3843 if (GET_CODE (XEXP (x, 0)) == NEG)
3844 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3846 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3847 if (GET_CODE (XEXP (x, 0)) == XOR
3848 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3849 && (temp = simplify_unary_operation (NOT, mode,
3850 XEXP (XEXP (x, 0), 1),
3852 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3854 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3855 other than 1, but that is not valid. We could do a similar
3856 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3857 but this doesn't seem common enough to bother with. */
3858 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3859 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3860 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3862 XEXP (XEXP (x, 0), 1));
3864 if (GET_CODE (XEXP (x, 0)) == SUBREG
3865 && subreg_lowpart_p (XEXP (x, 0))
3866 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3867 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3868 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3869 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3871 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3873 x = gen_rtx_ROTATE (inner_mode,
3874 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3876 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3877 return gen_lowpart_for_combine (mode, x);
3880 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3881 reversing the comparison code if valid. */
3882 if (STORE_FLAG_VALUE == -1
3883 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3884 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3885 XEXP (XEXP (x, 0), 1))))
3888 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3889 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3890 perform the above simplification. */
3892 if (STORE_FLAG_VALUE == -1
3893 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3895 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3896 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3898 /* Apply De Morgan's laws to reduce number of patterns for machines
3899 with negating logical insns (and-not, nand, etc.). If result has
3900 only one NOT, put it first, since that is how the patterns are
3903 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3905 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3906 enum machine_mode op_mode;
3908 op_mode = GET_MODE (in1);
3909 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3911 op_mode = GET_MODE (in2);
3912 if (op_mode == VOIDmode)
3914 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3916 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3919 in2 = in1; in1 = tem;
3922 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3928 /* (neg (plus X 1)) can become (not X). */
3929 if (GET_CODE (XEXP (x, 0)) == PLUS
3930 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3931 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3933 /* Similarly, (neg (not X)) is (plus X 1). */
3934 if (GET_CODE (XEXP (x, 0)) == NOT)
3935 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3937 /* (neg (minus X Y)) can become (minus Y X). */
3938 if (GET_CODE (XEXP (x, 0)) == MINUS
3939 && (! FLOAT_MODE_P (mode)
3940 /* x-y != -(y-x) with IEEE floating point. */
3941 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3942 || flag_unsafe_math_optimizations))
3943 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3944 XEXP (XEXP (x, 0), 0));
3946 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3947 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3948 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3949 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3951 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3952 if we can then eliminate the NEG (e.g.,
3953 if the operand is a constant). */
3955 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3957 temp = simplify_unary_operation (NEG, mode,
3958 XEXP (XEXP (x, 0), 0), mode);
3960 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3963 temp = expand_compound_operation (XEXP (x, 0));
3965 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3966 replaced by (lshiftrt X C). This will convert
3967 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3969 if (GET_CODE (temp) == ASHIFTRT
3970 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3971 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3972 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3973 INTVAL (XEXP (temp, 1)));
3975 /* If X has only a single bit that might be nonzero, say, bit I, convert
3976 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3977 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3978 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3979 or a SUBREG of one since we'd be making the expression more
3980 complex if it was just a register. */
3982 if (GET_CODE (temp) != REG
3983 && ! (GET_CODE (temp) == SUBREG
3984 && GET_CODE (SUBREG_REG (temp)) == REG)
3985 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3987 rtx temp1 = simplify_shift_const
3988 (NULL_RTX, ASHIFTRT, mode,
3989 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3990 GET_MODE_BITSIZE (mode) - 1 - i),
3991 GET_MODE_BITSIZE (mode) - 1 - i);
3993 /* If all we did was surround TEMP with the two shifts, we
3994 haven't improved anything, so don't use it. Otherwise,
3995 we are better off with TEMP1. */
3996 if (GET_CODE (temp1) != ASHIFTRT
3997 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3998 || XEXP (XEXP (temp1, 0), 0) != temp)
4004 /* We can't handle truncation to a partial integer mode here
4005 because we don't know the real bitsize of the partial
4007 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4010 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4011 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4012 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4014 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4015 GET_MODE_MASK (mode), NULL_RTX, 0));
4017 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4018 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4019 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4020 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4021 return XEXP (XEXP (x, 0), 0);
4023 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4024 (OP:SI foo:SI) if OP is NEG or ABS. */
4025 if ((GET_CODE (XEXP (x, 0)) == ABS
4026 || GET_CODE (XEXP (x, 0)) == NEG)
4027 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4028 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4029 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4030 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4031 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4033 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4035 if (GET_CODE (XEXP (x, 0)) == SUBREG
4036 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4037 && subreg_lowpart_p (XEXP (x, 0)))
4038 return SUBREG_REG (XEXP (x, 0));
4040 /* If we know that the value is already truncated, we can
4041 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4042 is nonzero for the corresponding modes. But don't do this
4043 for an (LSHIFTRT (MULT ...)) since this will cause problems
4044 with the umulXi3_highpart patterns. */
4045 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4046 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4047 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4048 >= GET_MODE_BITSIZE (mode) + 1
4049 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4050 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4051 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4053 /* A truncate of a comparison can be replaced with a subreg if
4054 STORE_FLAG_VALUE permits. This is like the previous test,
4055 but it works even if the comparison is done in a mode larger
4056 than HOST_BITS_PER_WIDE_INT. */
4057 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4058 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4059 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4060 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4062 /* Similarly, a truncate of a register whose value is a
4063 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4065 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4066 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4067 && (temp = get_last_value (XEXP (x, 0)))
4068 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4069 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4073 case FLOAT_TRUNCATE:
4074 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4075 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4076 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4077 return XEXP (XEXP (x, 0), 0);
4079 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4080 (OP:SF foo:SF) if OP is NEG or ABS. */
4081 if ((GET_CODE (XEXP (x, 0)) == ABS
4082 || GET_CODE (XEXP (x, 0)) == NEG)
4083 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4084 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4085 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4086 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4088 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4089 is (float_truncate:SF x). */
4090 if (GET_CODE (XEXP (x, 0)) == SUBREG
4091 && subreg_lowpart_p (XEXP (x, 0))
4092 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4093 return SUBREG_REG (XEXP (x, 0));
4098 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4099 using cc0, in which case we want to leave it as a COMPARE
4100 so we can distinguish it from a register-register-copy. */
4101 if (XEXP (x, 1) == const0_rtx)
4104 /* In IEEE floating point, x-0 is not the same as x. */
4105 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4106 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4107 || flag_unsafe_math_optimizations)
4108 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4114 /* (const (const X)) can become (const X). Do it this way rather than
4115 returning the inner CONST since CONST can be shared with a
4117 if (GET_CODE (XEXP (x, 0)) == CONST)
4118 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4123 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4124 can add in an offset. find_split_point will split this address up
4125 again if it doesn't match. */
4126 if (GET_CODE (XEXP (x, 0)) == HIGH
4127 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4133 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4134 outermost. That's because that's the way indexed addresses are
4135 supposed to appear. This code used to check many more cases, but
4136 they are now checked elsewhere. */
4137 if (GET_CODE (XEXP (x, 0)) == PLUS
4138 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4139 return gen_binary (PLUS, mode,
4140 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4142 XEXP (XEXP (x, 0), 1));
4144 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4145 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4146 bit-field and can be replaced by either a sign_extend or a
4147 sign_extract. The `and' may be a zero_extend and the two
4148 <c>, -<c> constants may be reversed. */
4149 if (GET_CODE (XEXP (x, 0)) == XOR
4150 && GET_CODE (XEXP (x, 1)) == CONST_INT
4151 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4152 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4153 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4154 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4155 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4156 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4157 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4158 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4159 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4160 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4161 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4162 == (unsigned int) i + 1))))
4163 return simplify_shift_const
4164 (NULL_RTX, ASHIFTRT, mode,
4165 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4166 XEXP (XEXP (XEXP (x, 0), 0), 0),
4167 GET_MODE_BITSIZE (mode) - (i + 1)),
4168 GET_MODE_BITSIZE (mode) - (i + 1));
4170 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4171 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4172 is 1. This produces better code than the alternative immediately
4174 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4175 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4176 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4177 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4178 XEXP (XEXP (x, 0), 0),
4179 XEXP (XEXP (x, 0), 1))))
4181 simplify_gen_unary (NEG, mode, reversed, mode);
4183 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4184 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4185 the bitsize of the mode - 1. This allows simplification of
4186 "a = (b & 8) == 0;" */
4187 if (XEXP (x, 1) == constm1_rtx
4188 && GET_CODE (XEXP (x, 0)) != REG
4189 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4190 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4191 && nonzero_bits (XEXP (x, 0), mode) == 1)
4192 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4193 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4194 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4195 GET_MODE_BITSIZE (mode) - 1),
4196 GET_MODE_BITSIZE (mode) - 1);
4198 /* If we are adding two things that have no bits in common, convert
4199 the addition into an IOR. This will often be further simplified,
4200 for example in cases like ((a & 1) + (a & 2)), which can
4203 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4204 && (nonzero_bits (XEXP (x, 0), mode)
4205 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4207 /* Try to simplify the expression further. */
4208 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4209 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4211 /* If we could, great. If not, do not go ahead with the IOR
4212 replacement, since PLUS appears in many special purpose
4213 address arithmetic instructions. */
4214 if (GET_CODE (temp) != CLOBBER && temp != tor)
4220 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4221 by reversing the comparison code if valid. */
4222 if (STORE_FLAG_VALUE == 1
4223 && XEXP (x, 0) == const1_rtx
4224 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4225 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4226 XEXP (XEXP (x, 1), 0),
4227 XEXP (XEXP (x, 1), 1))))
4230 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4231 (and <foo> (const_int pow2-1)) */
4232 if (GET_CODE (XEXP (x, 1)) == AND
4233 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4234 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4235 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4236 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4237 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4239 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4241 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4242 return gen_binary (MINUS, mode,
4243 gen_binary (MINUS, mode, XEXP (x, 0),
4244 XEXP (XEXP (x, 1), 0)),
4245 XEXP (XEXP (x, 1), 1));
4249 /* If we have (mult (plus A B) C), apply the distributive law and then
4250 the inverse distributive law to see if things simplify. This
4251 occurs mostly in addresses, often when unrolling loops. */
4253 if (GET_CODE (XEXP (x, 0)) == PLUS)
4255 x = apply_distributive_law
4256 (gen_binary (PLUS, mode,
4257 gen_binary (MULT, mode,
4258 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4259 gen_binary (MULT, mode,
4260 XEXP (XEXP (x, 0), 1),
4261 copy_rtx (XEXP (x, 1)))));
4263 if (GET_CODE (x) != MULT)
4266 /* Try simplify a*(b/c) as (a*b)/c. */
4267 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4268 && GET_CODE (XEXP (x, 0)) == DIV)
4270 rtx tem = simplify_binary_operation (MULT, mode,
4271 XEXP (XEXP (x, 0), 0),
4274 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4279 /* If this is a divide by a power of two, treat it as a shift if
4280 its first operand is a shift. */
4281 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4282 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4283 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4284 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4285 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4286 || GET_CODE (XEXP (x, 0)) == ROTATE
4287 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4288 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4292 case GT: case GTU: case GE: case GEU:
4293 case LT: case LTU: case LE: case LEU:
4294 case UNEQ: case LTGT:
4295 case UNGT: case UNGE:
4296 case UNLT: case UNLE:
4297 case UNORDERED: case ORDERED:
4298 /* If the first operand is a condition code, we can't do anything
4300 if (GET_CODE (XEXP (x, 0)) == COMPARE
4301 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4303 && XEXP (x, 0) != cc0_rtx
4307 rtx op0 = XEXP (x, 0);
4308 rtx op1 = XEXP (x, 1);
4309 enum rtx_code new_code;
4311 if (GET_CODE (op0) == COMPARE)
4312 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4314 /* Simplify our comparison, if possible. */
4315 new_code = simplify_comparison (code, &op0, &op1);
4317 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4318 if only the low-order bit is possibly nonzero in X (such as when
4319 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4320 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4321 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4324 Remove any ZERO_EXTRACT we made when thinking this was a
4325 comparison. It may now be simpler to use, e.g., an AND. If a
4326 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4327 the call to make_compound_operation in the SET case. */
4329 if (STORE_FLAG_VALUE == 1
4330 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4331 && op1 == const0_rtx
4332 && mode == GET_MODE (op0)
4333 && nonzero_bits (op0, mode) == 1)
4334 return gen_lowpart_for_combine (mode,
4335 expand_compound_operation (op0));
4337 else if (STORE_FLAG_VALUE == 1
4338 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4339 && op1 == const0_rtx
4340 && mode == GET_MODE (op0)
4341 && (num_sign_bit_copies (op0, mode)
4342 == GET_MODE_BITSIZE (mode)))
4344 op0 = expand_compound_operation (op0);
4345 return simplify_gen_unary (NEG, mode,
4346 gen_lowpart_for_combine (mode, op0),
4350 else if (STORE_FLAG_VALUE == 1
4351 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4352 && op1 == const0_rtx
4353 && mode == GET_MODE (op0)
4354 && nonzero_bits (op0, mode) == 1)
4356 op0 = expand_compound_operation (op0);
4357 return gen_binary (XOR, mode,
4358 gen_lowpart_for_combine (mode, op0),
4362 else if (STORE_FLAG_VALUE == 1
4363 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4364 && op1 == const0_rtx
4365 && mode == GET_MODE (op0)
4366 && (num_sign_bit_copies (op0, mode)
4367 == GET_MODE_BITSIZE (mode)))
4369 op0 = expand_compound_operation (op0);
4370 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4373 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4375 if (STORE_FLAG_VALUE == -1
4376 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4377 && op1 == const0_rtx
4378 && (num_sign_bit_copies (op0, mode)
4379 == GET_MODE_BITSIZE (mode)))
4380 return gen_lowpart_for_combine (mode,
4381 expand_compound_operation (op0));
4383 else if (STORE_FLAG_VALUE == -1
4384 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4385 && op1 == const0_rtx
4386 && mode == GET_MODE (op0)
4387 && nonzero_bits (op0, mode) == 1)
4389 op0 = expand_compound_operation (op0);
4390 return simplify_gen_unary (NEG, mode,
4391 gen_lowpart_for_combine (mode, op0),
4395 else if (STORE_FLAG_VALUE == -1
4396 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4397 && op1 == const0_rtx
4398 && mode == GET_MODE (op0)
4399 && (num_sign_bit_copies (op0, mode)
4400 == GET_MODE_BITSIZE (mode)))
4402 op0 = expand_compound_operation (op0);
4403 return simplify_gen_unary (NOT, mode,
4404 gen_lowpart_for_combine (mode, op0),
4408 /* If X is 0/1, (eq X 0) is X-1. */
4409 else if (STORE_FLAG_VALUE == -1
4410 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4411 && op1 == const0_rtx
4412 && mode == GET_MODE (op0)
4413 && nonzero_bits (op0, mode) == 1)
4415 op0 = expand_compound_operation (op0);
4416 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4419 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4420 one bit that might be nonzero, we can convert (ne x 0) to
4421 (ashift x c) where C puts the bit in the sign bit. Remove any
4422 AND with STORE_FLAG_VALUE when we are done, since we are only
4423 going to test the sign bit. */
4424 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4425 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4426 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4427 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4428 && op1 == const0_rtx
4429 && mode == GET_MODE (op0)
4430 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4432 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4433 expand_compound_operation (op0),
4434 GET_MODE_BITSIZE (mode) - 1 - i);
4435 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4441 /* If the code changed, return a whole new comparison. */
4442 if (new_code != code)
4443 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4445 /* Otherwise, keep this operation, but maybe change its operands.
4446 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4447 SUBST (XEXP (x, 0), op0);
4448 SUBST (XEXP (x, 1), op1);
4453 return simplify_if_then_else (x);
4459 /* If we are processing SET_DEST, we are done. */
4463 return expand_compound_operation (x);
4466 return simplify_set (x);
4471 return simplify_logical (x, last);
4474 /* (abs (neg <foo>)) -> (abs <foo>) */
4475 if (GET_CODE (XEXP (x, 0)) == NEG)
4476 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4478 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4480 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4483 /* If operand is something known to be positive, ignore the ABS. */
4484 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4485 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4486 <= HOST_BITS_PER_WIDE_INT)
4487 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4488 & ((HOST_WIDE_INT) 1
4489 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4493 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4494 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4495 return gen_rtx_NEG (mode, XEXP (x, 0));
4500 /* (ffs (*_extend <X>)) = (ffs <X>) */
4501 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4502 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4503 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4507 /* (float (sign_extend <X>)) = (float <X>). */
4508 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4509 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4517 /* If this is a shift by a constant amount, simplify it. */
4518 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4519 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4520 INTVAL (XEXP (x, 1)));
4522 #ifdef SHIFT_COUNT_TRUNCATED
4523 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4525 force_to_mode (XEXP (x, 1), GET_MODE (x),
4527 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4536 rtx op0 = XEXP (x, 0);
4537 rtx op1 = XEXP (x, 1);
4540 if (GET_CODE (op1) != PARALLEL)
4542 len = XVECLEN (op1, 0);
4544 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4545 && GET_CODE (op0) == VEC_CONCAT)
4547 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4549 /* Try to find the element in the VEC_CONCAT. */
4552 if (GET_MODE (op0) == GET_MODE (x))
4554 if (GET_CODE (op0) == VEC_CONCAT)
4556 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4557 if (op0_size < offset)
4558 op0 = XEXP (op0, 0);
4562 op0 = XEXP (op0, 1);
4580 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4583 simplify_if_then_else (x)
4586 enum machine_mode mode = GET_MODE (x);
4587 rtx cond = XEXP (x, 0);
4588 rtx true_rtx = XEXP (x, 1);
4589 rtx false_rtx = XEXP (x, 2);
4590 enum rtx_code true_code = GET_CODE (cond);
4591 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4594 enum rtx_code false_code;
4597 /* Simplify storing of the truth value. */
4598 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4599 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4601 /* Also when the truth value has to be reversed. */
4603 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4604 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4608 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4609 in it is being compared against certain values. Get the true and false
4610 comparisons and see if that says anything about the value of each arm. */
4613 && ((false_code = combine_reversed_comparison_code (cond))
4615 && GET_CODE (XEXP (cond, 0)) == REG)
4618 rtx from = XEXP (cond, 0);
4619 rtx true_val = XEXP (cond, 1);
4620 rtx false_val = true_val;
4623 /* If FALSE_CODE is EQ, swap the codes and arms. */
4625 if (false_code == EQ)
4627 swapped = 1, true_code = EQ, false_code = NE;
4628 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4631 /* If we are comparing against zero and the expression being tested has
4632 only a single bit that might be nonzero, that is its value when it is
4633 not equal to zero. Similarly if it is known to be -1 or 0. */
4635 if (true_code == EQ && true_val == const0_rtx
4636 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4637 false_code = EQ, false_val = GEN_INT (nzb);
4638 else if (true_code == EQ && true_val == const0_rtx
4639 && (num_sign_bit_copies (from, GET_MODE (from))
4640 == GET_MODE_BITSIZE (GET_MODE (from))))
4641 false_code = EQ, false_val = constm1_rtx;
4643 /* Now simplify an arm if we know the value of the register in the
4644 branch and it is used in the arm. Be careful due to the potential
4645 of locally-shared RTL. */
4647 if (reg_mentioned_p (from, true_rtx))
4648 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4650 pc_rtx, pc_rtx, 0, 0);
4651 if (reg_mentioned_p (from, false_rtx))
4652 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4654 pc_rtx, pc_rtx, 0, 0);
4656 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4657 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4659 true_rtx = XEXP (x, 1);
4660 false_rtx = XEXP (x, 2);
4661 true_code = GET_CODE (cond);
4664 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4665 reversed, do so to avoid needing two sets of patterns for
4666 subtract-and-branch insns. Similarly if we have a constant in the true
4667 arm, the false arm is the same as the first operand of the comparison, or
4668 the false arm is more complicated than the true arm. */
4671 && combine_reversed_comparison_code (cond) != UNKNOWN
4672 && (true_rtx == pc_rtx
4673 || (CONSTANT_P (true_rtx)
4674 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4675 || true_rtx == const0_rtx
4676 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4677 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4678 || (GET_CODE (true_rtx) == SUBREG
4679 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4680 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4681 || reg_mentioned_p (true_rtx, false_rtx)
4682 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4684 true_code = reversed_comparison_code (cond, NULL);
4686 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4689 SUBST (XEXP (x, 1), false_rtx);
4690 SUBST (XEXP (x, 2), true_rtx);
4692 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4695 /* It is possible that the conditional has been simplified out. */
4696 true_code = GET_CODE (cond);
4697 comparison_p = GET_RTX_CLASS (true_code) == '<';
4700 /* If the two arms are identical, we don't need the comparison. */
4702 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4705 /* Convert a == b ? b : a to "a". */
4706 if (true_code == EQ && ! side_effects_p (cond)
4707 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4708 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4709 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4711 else if (true_code == NE && ! side_effects_p (cond)
4712 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4713 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4714 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4717 /* Look for cases where we have (abs x) or (neg (abs X)). */
4719 if (GET_MODE_CLASS (mode) == MODE_INT
4720 && GET_CODE (false_rtx) == NEG
4721 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4723 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4724 && ! side_effects_p (true_rtx))
4729 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4733 simplify_gen_unary (NEG, mode,
4734 simplify_gen_unary (ABS, mode, true_rtx, mode),
4740 /* Look for MIN or MAX. */
4742 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4744 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4745 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4746 && ! side_effects_p (cond))
4751 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4754 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4757 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4760 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4765 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4766 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4767 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4768 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4769 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4770 neither 1 or -1, but it isn't worth checking for. */
4772 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4773 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4775 rtx t = make_compound_operation (true_rtx, SET);
4776 rtx f = make_compound_operation (false_rtx, SET);
4777 rtx cond_op0 = XEXP (cond, 0);
4778 rtx cond_op1 = XEXP (cond, 1);
4779 enum rtx_code op = NIL, extend_op = NIL;
4780 enum machine_mode m = mode;
4781 rtx z = 0, c1 = NULL_RTX;
4783 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4784 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4785 || GET_CODE (t) == ASHIFT
4786 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4787 && rtx_equal_p (XEXP (t, 0), f))
4788 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4790 /* If an identity-zero op is commutative, check whether there
4791 would be a match if we swapped the operands. */
4792 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4793 || GET_CODE (t) == XOR)
4794 && rtx_equal_p (XEXP (t, 1), f))
4795 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4796 else if (GET_CODE (t) == SIGN_EXTEND
4797 && (GET_CODE (XEXP (t, 0)) == PLUS
4798 || GET_CODE (XEXP (t, 0)) == MINUS
4799 || GET_CODE (XEXP (t, 0)) == IOR
4800 || GET_CODE (XEXP (t, 0)) == XOR
4801 || GET_CODE (XEXP (t, 0)) == ASHIFT
4802 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4803 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4804 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4805 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4806 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4807 && (num_sign_bit_copies (f, GET_MODE (f))
4808 > (GET_MODE_BITSIZE (mode)
4809 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4811 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4812 extend_op = SIGN_EXTEND;
4813 m = GET_MODE (XEXP (t, 0));
4815 else if (GET_CODE (t) == SIGN_EXTEND
4816 && (GET_CODE (XEXP (t, 0)) == PLUS
4817 || GET_CODE (XEXP (t, 0)) == IOR
4818 || GET_CODE (XEXP (t, 0)) == XOR)
4819 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4820 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4821 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4822 && (num_sign_bit_copies (f, GET_MODE (f))
4823 > (GET_MODE_BITSIZE (mode)
4824 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4826 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4827 extend_op = SIGN_EXTEND;
4828 m = GET_MODE (XEXP (t, 0));
4830 else if (GET_CODE (t) == ZERO_EXTEND
4831 && (GET_CODE (XEXP (t, 0)) == PLUS
4832 || GET_CODE (XEXP (t, 0)) == MINUS
4833 || GET_CODE (XEXP (t, 0)) == IOR
4834 || GET_CODE (XEXP (t, 0)) == XOR
4835 || GET_CODE (XEXP (t, 0)) == ASHIFT
4836 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4837 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4838 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4839 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4840 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4841 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4842 && ((nonzero_bits (f, GET_MODE (f))
4843 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4846 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4847 extend_op = ZERO_EXTEND;
4848 m = GET_MODE (XEXP (t, 0));
4850 else if (GET_CODE (t) == ZERO_EXTEND
4851 && (GET_CODE (XEXP (t, 0)) == PLUS
4852 || GET_CODE (XEXP (t, 0)) == IOR
4853 || GET_CODE (XEXP (t, 0)) == XOR)
4854 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4855 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4856 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4857 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4858 && ((nonzero_bits (f, GET_MODE (f))
4859 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4862 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4863 extend_op = ZERO_EXTEND;
4864 m = GET_MODE (XEXP (t, 0));
4869 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4870 pc_rtx, pc_rtx, 0, 0);
4871 temp = gen_binary (MULT, m, temp,
4872 gen_binary (MULT, m, c1, const_true_rtx));
4873 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4874 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4876 if (extend_op != NIL)
4877 temp = simplify_gen_unary (extend_op, mode, temp, m);
4883 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4884 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4885 negation of a single bit, we can convert this operation to a shift. We
4886 can actually do this more generally, but it doesn't seem worth it. */
4888 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4889 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4890 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4891 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4892 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4893 == GET_MODE_BITSIZE (mode))
4894 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4896 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4897 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4902 /* Simplify X, a SET expression. Return the new expression. */
4908 rtx src = SET_SRC (x);
4909 rtx dest = SET_DEST (x);
4910 enum machine_mode mode
4911 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4915 /* (set (pc) (return)) gets written as (return). */
4916 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4919 /* Now that we know for sure which bits of SRC we are using, see if we can
4920 simplify the expression for the object knowing that we only need the
4923 if (GET_MODE_CLASS (mode) == MODE_INT)
4925 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4926 SUBST (SET_SRC (x), src);
4929 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4930 the comparison result and try to simplify it unless we already have used
4931 undobuf.other_insn. */
4932 if ((GET_CODE (src) == COMPARE
4937 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4938 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4939 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4940 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4942 enum rtx_code old_code = GET_CODE (*cc_use);
4943 enum rtx_code new_code;
4945 int other_changed = 0;
4946 enum machine_mode compare_mode = GET_MODE (dest);
4948 if (GET_CODE (src) == COMPARE)
4949 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4951 op0 = src, op1 = const0_rtx;
4953 /* Simplify our comparison, if possible. */
4954 new_code = simplify_comparison (old_code, &op0, &op1);
4956 #ifdef EXTRA_CC_MODES
4957 /* If this machine has CC modes other than CCmode, check to see if we
4958 need to use a different CC mode here. */
4959 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4960 #endif /* EXTRA_CC_MODES */
4962 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4963 /* If the mode changed, we have to change SET_DEST, the mode in the
4964 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4965 a hard register, just build new versions with the proper mode. If it
4966 is a pseudo, we lose unless it is only time we set the pseudo, in
4967 which case we can safely change its mode. */
4968 if (compare_mode != GET_MODE (dest))
4970 unsigned int regno = REGNO (dest);
4971 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4973 if (regno < FIRST_PSEUDO_REGISTER
4974 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4976 if (regno >= FIRST_PSEUDO_REGISTER)
4977 SUBST (regno_reg_rtx[regno], new_dest);
4979 SUBST (SET_DEST (x), new_dest);
4980 SUBST (XEXP (*cc_use, 0), new_dest);
4988 /* If the code changed, we have to build a new comparison in
4989 undobuf.other_insn. */
4990 if (new_code != old_code)
4992 unsigned HOST_WIDE_INT mask;
4994 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
4997 /* If the only change we made was to change an EQ into an NE or
4998 vice versa, OP0 has only one bit that might be nonzero, and OP1
4999 is zero, check if changing the user of the condition code will
5000 produce a valid insn. If it won't, we can keep the original code
5001 in that insn by surrounding our operation with an XOR. */
5003 if (((old_code == NE && new_code == EQ)
5004 || (old_code == EQ && new_code == NE))
5005 && ! other_changed && op1 == const0_rtx
5006 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5007 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5009 rtx pat = PATTERN (other_insn), note = 0;
5011 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5012 && ! check_asm_operands (pat)))
5014 PUT_CODE (*cc_use, old_code);
5017 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5025 undobuf.other_insn = other_insn;
5028 /* If we are now comparing against zero, change our source if
5029 needed. If we do not use cc0, we always have a COMPARE. */
5030 if (op1 == const0_rtx && dest == cc0_rtx)
5032 SUBST (SET_SRC (x), op0);
5038 /* Otherwise, if we didn't previously have a COMPARE in the
5039 correct mode, we need one. */
5040 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5042 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5047 /* Otherwise, update the COMPARE if needed. */
5048 SUBST (XEXP (src, 0), op0);
5049 SUBST (XEXP (src, 1), op1);
5054 /* Get SET_SRC in a form where we have placed back any
5055 compound expressions. Then do the checks below. */
5056 src = make_compound_operation (src, SET);
5057 SUBST (SET_SRC (x), src);
5060 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5061 and X being a REG or (subreg (reg)), we may be able to convert this to
5062 (set (subreg:m2 x) (op)).
5064 We can always do this if M1 is narrower than M2 because that means that
5065 we only care about the low bits of the result.
5067 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5068 perform a narrower operation than requested since the high-order bits will
5069 be undefined. On machine where it is defined, this transformation is safe
5070 as long as M1 and M2 have the same number of words. */
5072 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5073 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5074 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5076 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5077 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5078 #ifndef WORD_REGISTER_OPERATIONS
5079 && (GET_MODE_SIZE (GET_MODE (src))
5080 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5082 #ifdef CLASS_CANNOT_CHANGE_MODE
5083 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5084 && (TEST_HARD_REG_BIT
5085 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5087 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5088 GET_MODE (SUBREG_REG (src))))
5090 && (GET_CODE (dest) == REG
5091 || (GET_CODE (dest) == SUBREG
5092 && GET_CODE (SUBREG_REG (dest)) == REG)))
5094 SUBST (SET_DEST (x),
5095 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5097 SUBST (SET_SRC (x), SUBREG_REG (src));
5099 src = SET_SRC (x), dest = SET_DEST (x);
5102 #ifdef LOAD_EXTEND_OP
5103 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5104 would require a paradoxical subreg. Replace the subreg with a
5105 zero_extend to avoid the reload that would otherwise be required. */
5107 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5108 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5109 && SUBREG_BYTE (src) == 0
5110 && (GET_MODE_SIZE (GET_MODE (src))
5111 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5112 && GET_CODE (SUBREG_REG (src)) == MEM)
5115 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5116 GET_MODE (src), SUBREG_REG (src)));
5122 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5123 are comparing an item known to be 0 or -1 against 0, use a logical
5124 operation instead. Check for one of the arms being an IOR of the other
5125 arm with some value. We compute three terms to be IOR'ed together. In
5126 practice, at most two will be nonzero. Then we do the IOR's. */
5128 if (GET_CODE (dest) != PC
5129 && GET_CODE (src) == IF_THEN_ELSE
5130 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5131 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5132 && XEXP (XEXP (src, 0), 1) == const0_rtx
5133 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5134 #ifdef HAVE_conditional_move
5135 && ! can_conditionally_move_p (GET_MODE (src))
5137 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5138 GET_MODE (XEXP (XEXP (src, 0), 0)))
5139 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5140 && ! side_effects_p (src))
5142 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5143 ? XEXP (src, 1) : XEXP (src, 2));
5144 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5145 ? XEXP (src, 2) : XEXP (src, 1));
5146 rtx term1 = const0_rtx, term2, term3;
5148 if (GET_CODE (true_rtx) == IOR
5149 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5150 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5151 else if (GET_CODE (true_rtx) == IOR
5152 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5153 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5154 else if (GET_CODE (false_rtx) == IOR
5155 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5156 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5157 else if (GET_CODE (false_rtx) == IOR
5158 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5159 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5161 term2 = gen_binary (AND, GET_MODE (src),
5162 XEXP (XEXP (src, 0), 0), true_rtx);
5163 term3 = gen_binary (AND, GET_MODE (src),
5164 simplify_gen_unary (NOT, GET_MODE (src),
5165 XEXP (XEXP (src, 0), 0),
5170 gen_binary (IOR, GET_MODE (src),
5171 gen_binary (IOR, GET_MODE (src), term1, term2),
5177 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5178 whole thing fail. */
5179 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5181 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5184 /* Convert this into a field assignment operation, if possible. */
5185 return make_field_assignment (x);
5188 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5189 result. LAST is nonzero if this is the last retry. */
5192 simplify_logical (x, last)
5196 enum machine_mode mode = GET_MODE (x);
5197 rtx op0 = XEXP (x, 0);
5198 rtx op1 = XEXP (x, 1);
5201 switch (GET_CODE (x))
5204 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5205 insn (and may simplify more). */
5206 if (GET_CODE (op0) == XOR
5207 && rtx_equal_p (XEXP (op0, 0), op1)
5208 && ! side_effects_p (op1))
5209 x = gen_binary (AND, mode,
5210 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5213 if (GET_CODE (op0) == XOR
5214 && rtx_equal_p (XEXP (op0, 1), op1)
5215 && ! side_effects_p (op1))
5216 x = gen_binary (AND, mode,
5217 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5220 /* Similarly for (~(A ^ B)) & A. */
5221 if (GET_CODE (op0) == NOT
5222 && GET_CODE (XEXP (op0, 0)) == XOR
5223 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5224 && ! side_effects_p (op1))
5225 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5227 if (GET_CODE (op0) == NOT
5228 && GET_CODE (XEXP (op0, 0)) == XOR
5229 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5230 && ! side_effects_p (op1))
5231 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5233 /* We can call simplify_and_const_int only if we don't lose
5234 any (sign) bits when converting INTVAL (op1) to
5235 "unsigned HOST_WIDE_INT". */
5236 if (GET_CODE (op1) == CONST_INT
5237 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5238 || INTVAL (op1) > 0))
5240 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5242 /* If we have (ior (and (X C1) C2)) and the next restart would be
5243 the last, simplify this by making C1 as small as possible
5246 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5247 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5248 && GET_CODE (op1) == CONST_INT)
5249 return gen_binary (IOR, mode,
5250 gen_binary (AND, mode, XEXP (op0, 0),
5251 GEN_INT (INTVAL (XEXP (op0, 1))
5252 & ~INTVAL (op1))), op1);
5254 if (GET_CODE (x) != AND)
5257 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5258 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5259 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5262 /* Convert (A | B) & A to A. */
5263 if (GET_CODE (op0) == IOR
5264 && (rtx_equal_p (XEXP (op0, 0), op1)
5265 || rtx_equal_p (XEXP (op0, 1), op1))
5266 && ! side_effects_p (XEXP (op0, 0))
5267 && ! side_effects_p (XEXP (op0, 1)))
5270 /* In the following group of tests (and those in case IOR below),
5271 we start with some combination of logical operations and apply
5272 the distributive law followed by the inverse distributive law.
5273 Most of the time, this results in no change. However, if some of
5274 the operands are the same or inverses of each other, simplifications
5277 For example, (and (ior A B) (not B)) can occur as the result of
5278 expanding a bit field assignment. When we apply the distributive
5279 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5280 which then simplifies to (and (A (not B))).
5282 If we have (and (ior A B) C), apply the distributive law and then
5283 the inverse distributive law to see if things simplify. */
5285 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5287 x = apply_distributive_law
5288 (gen_binary (GET_CODE (op0), mode,
5289 gen_binary (AND, mode, XEXP (op0, 0), op1),
5290 gen_binary (AND, mode, XEXP (op0, 1),
5292 if (GET_CODE (x) != AND)
5296 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5297 return apply_distributive_law
5298 (gen_binary (GET_CODE (op1), mode,
5299 gen_binary (AND, mode, XEXP (op1, 0), op0),
5300 gen_binary (AND, mode, XEXP (op1, 1),
5303 /* Similarly, taking advantage of the fact that
5304 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5306 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5307 return apply_distributive_law
5308 (gen_binary (XOR, mode,
5309 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5310 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5313 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5314 return apply_distributive_law
5315 (gen_binary (XOR, mode,
5316 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5317 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5321 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5322 if (GET_CODE (op1) == CONST_INT
5323 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5324 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5327 /* Convert (A & B) | A to A. */
5328 if (GET_CODE (op0) == AND
5329 && (rtx_equal_p (XEXP (op0, 0), op1)
5330 || rtx_equal_p (XEXP (op0, 1), op1))
5331 && ! side_effects_p (XEXP (op0, 0))
5332 && ! side_effects_p (XEXP (op0, 1)))
5335 /* If we have (ior (and A B) C), apply the distributive law and then
5336 the inverse distributive law to see if things simplify. */
5338 if (GET_CODE (op0) == AND)
5340 x = apply_distributive_law
5341 (gen_binary (AND, mode,
5342 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5343 gen_binary (IOR, mode, XEXP (op0, 1),
5346 if (GET_CODE (x) != IOR)
5350 if (GET_CODE (op1) == AND)
5352 x = apply_distributive_law
5353 (gen_binary (AND, mode,
5354 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5355 gen_binary (IOR, mode, XEXP (op1, 1),
5358 if (GET_CODE (x) != IOR)
5362 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5363 mode size to (rotate A CX). */
5365 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5366 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5367 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5368 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5369 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5370 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5371 == GET_MODE_BITSIZE (mode)))
5372 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5373 (GET_CODE (op0) == ASHIFT
5374 ? XEXP (op0, 1) : XEXP (op1, 1)));
5376 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5377 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5378 does not affect any of the bits in OP1, it can really be done
5379 as a PLUS and we can associate. We do this by seeing if OP1
5380 can be safely shifted left C bits. */
5381 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5382 && GET_CODE (XEXP (op0, 0)) == PLUS
5383 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5384 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5385 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5387 int count = INTVAL (XEXP (op0, 1));
5388 HOST_WIDE_INT mask = INTVAL (op1) << count;
5390 if (mask >> count == INTVAL (op1)
5391 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5393 SUBST (XEXP (XEXP (op0, 0), 1),
5394 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5401 /* If we are XORing two things that have no bits in common,
5402 convert them into an IOR. This helps to detect rotation encoded
5403 using those methods and possibly other simplifications. */
5405 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5406 && (nonzero_bits (op0, mode)
5407 & nonzero_bits (op1, mode)) == 0)
5408 return (gen_binary (IOR, mode, op0, op1));
5410 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5411 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5414 int num_negated = 0;
5416 if (GET_CODE (op0) == NOT)
5417 num_negated++, op0 = XEXP (op0, 0);
5418 if (GET_CODE (op1) == NOT)
5419 num_negated++, op1 = XEXP (op1, 0);
5421 if (num_negated == 2)
5423 SUBST (XEXP (x, 0), op0);
5424 SUBST (XEXP (x, 1), op1);
5426 else if (num_negated == 1)
5428 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5432 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5433 correspond to a machine insn or result in further simplifications
5434 if B is a constant. */
5436 if (GET_CODE (op0) == AND
5437 && rtx_equal_p (XEXP (op0, 1), op1)
5438 && ! side_effects_p (op1))
5439 return gen_binary (AND, mode,
5440 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5443 else if (GET_CODE (op0) == AND
5444 && rtx_equal_p (XEXP (op0, 0), op1)
5445 && ! side_effects_p (op1))
5446 return gen_binary (AND, mode,
5447 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5450 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5451 comparison if STORE_FLAG_VALUE is 1. */
5452 if (STORE_FLAG_VALUE == 1
5453 && op1 == const1_rtx
5454 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5455 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5459 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5460 is (lt foo (const_int 0)), so we can perform the above
5461 simplification if STORE_FLAG_VALUE is 1. */
5463 if (STORE_FLAG_VALUE == 1
5464 && op1 == const1_rtx
5465 && GET_CODE (op0) == LSHIFTRT
5466 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5467 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5468 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5470 /* (xor (comparison foo bar) (const_int sign-bit))
5471 when STORE_FLAG_VALUE is the sign bit. */
5472 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5473 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5474 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5475 && op1 == const_true_rtx
5476 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5477 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5490 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5491 operations" because they can be replaced with two more basic operations.
5492 ZERO_EXTEND is also considered "compound" because it can be replaced with
5493 an AND operation, which is simpler, though only one operation.
5495 The function expand_compound_operation is called with an rtx expression
5496 and will convert it to the appropriate shifts and AND operations,
5497 simplifying at each stage.
5499 The function make_compound_operation is called to convert an expression
5500 consisting of shifts and ANDs into the equivalent compound expression.
5501 It is the inverse of this function, loosely speaking. */
5504 expand_compound_operation (x)
5507 unsigned HOST_WIDE_INT pos = 0, len;
5509 unsigned int modewidth;
5512 switch (GET_CODE (x))
5517 /* We can't necessarily use a const_int for a multiword mode;
5518 it depends on implicitly extending the value.
5519 Since we don't know the right way to extend it,
5520 we can't tell whether the implicit way is right.
5522 Even for a mode that is no wider than a const_int,
5523 we can't win, because we need to sign extend one of its bits through
5524 the rest of it, and we don't know which bit. */
5525 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5528 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5529 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5530 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5531 reloaded. If not for that, MEM's would very rarely be safe.
5533 Reject MODEs bigger than a word, because we might not be able
5534 to reference a two-register group starting with an arbitrary register
5535 (and currently gen_lowpart might crash for a SUBREG). */
5537 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5540 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5541 /* If the inner object has VOIDmode (the only way this can happen
5542 is if it is a ASM_OPERANDS), we can't do anything since we don't
5543 know how much masking to do. */
5552 /* If the operand is a CLOBBER, just return it. */
5553 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5556 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5557 || GET_CODE (XEXP (x, 2)) != CONST_INT
5558 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5561 len = INTVAL (XEXP (x, 1));
5562 pos = INTVAL (XEXP (x, 2));
5564 /* If this goes outside the object being extracted, replace the object
5565 with a (use (mem ...)) construct that only combine understands
5566 and is used only for this purpose. */
5567 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5568 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5570 if (BITS_BIG_ENDIAN)
5571 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5578 /* Convert sign extension to zero extension, if we know that the high
5579 bit is not set, as this is easier to optimize. It will be converted
5580 back to cheaper alternative in make_extraction. */
5581 if (GET_CODE (x) == SIGN_EXTEND
5582 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5583 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5584 & ~(((unsigned HOST_WIDE_INT)
5585 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5589 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5590 return expand_compound_operation (temp);
5593 /* We can optimize some special cases of ZERO_EXTEND. */
5594 if (GET_CODE (x) == ZERO_EXTEND)
5596 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5597 know that the last value didn't have any inappropriate bits
5599 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5600 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5601 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5602 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5603 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5604 return XEXP (XEXP (x, 0), 0);
5606 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5607 if (GET_CODE (XEXP (x, 0)) == SUBREG
5608 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5609 && subreg_lowpart_p (XEXP (x, 0))
5610 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5611 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5612 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5613 return SUBREG_REG (XEXP (x, 0));
5615 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5616 is a comparison and STORE_FLAG_VALUE permits. This is like
5617 the first case, but it works even when GET_MODE (x) is larger
5618 than HOST_WIDE_INT. */
5619 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5620 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5621 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5622 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5623 <= HOST_BITS_PER_WIDE_INT)
5624 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5625 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5626 return XEXP (XEXP (x, 0), 0);
5628 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5629 if (GET_CODE (XEXP (x, 0)) == SUBREG
5630 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5631 && subreg_lowpart_p (XEXP (x, 0))
5632 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5633 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5634 <= HOST_BITS_PER_WIDE_INT)
5635 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5636 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5637 return SUBREG_REG (XEXP (x, 0));
5641 /* If we reach here, we want to return a pair of shifts. The inner
5642 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5643 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5644 logical depending on the value of UNSIGNEDP.
5646 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5647 converted into an AND of a shift.
5649 We must check for the case where the left shift would have a negative
5650 count. This can happen in a case like (x >> 31) & 255 on machines
5651 that can't shift by a constant. On those machines, we would first
5652 combine the shift with the AND to produce a variable-position
5653 extraction. Then the constant of 31 would be substituted in to produce
5654 a such a position. */
5656 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5657 if (modewidth + len >= pos)
5658 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5660 simplify_shift_const (NULL_RTX, ASHIFT,
5663 modewidth - pos - len),
5666 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5667 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5668 simplify_shift_const (NULL_RTX, LSHIFTRT,
5671 ((HOST_WIDE_INT) 1 << len) - 1);
5673 /* Any other cases we can't handle. */
5676 /* If we couldn't do this for some reason, return the original
5678 if (GET_CODE (tem) == CLOBBER)
5684 /* X is a SET which contains an assignment of one object into
5685 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5686 or certain SUBREGS). If possible, convert it into a series of
5689 We half-heartedly support variable positions, but do not at all
5690 support variable lengths. */
5693 expand_field_assignment (x)
5697 rtx pos; /* Always counts from low bit. */
5700 enum machine_mode compute_mode;
5702 /* Loop until we find something we can't simplify. */
5705 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5706 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5708 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5709 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5710 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5712 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5713 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5715 inner = XEXP (SET_DEST (x), 0);
5716 len = INTVAL (XEXP (SET_DEST (x), 1));
5717 pos = XEXP (SET_DEST (x), 2);
5719 /* If the position is constant and spans the width of INNER,
5720 surround INNER with a USE to indicate this. */
5721 if (GET_CODE (pos) == CONST_INT
5722 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5723 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5725 if (BITS_BIG_ENDIAN)
5727 if (GET_CODE (pos) == CONST_INT)
5728 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5730 else if (GET_CODE (pos) == MINUS
5731 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5732 && (INTVAL (XEXP (pos, 1))
5733 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5734 /* If position is ADJUST - X, new position is X. */
5735 pos = XEXP (pos, 0);
5737 pos = gen_binary (MINUS, GET_MODE (pos),
5738 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5744 /* A SUBREG between two modes that occupy the same numbers of words
5745 can be done by moving the SUBREG to the source. */
5746 else if (GET_CODE (SET_DEST (x)) == SUBREG
5747 /* We need SUBREGs to compute nonzero_bits properly. */
5748 && nonzero_sign_valid
5749 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5750 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5751 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5752 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5754 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5755 gen_lowpart_for_combine
5756 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5763 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5764 inner = SUBREG_REG (inner);
5766 compute_mode = GET_MODE (inner);
5768 /* Don't attempt bitwise arithmetic on non-integral modes. */
5769 if (! INTEGRAL_MODE_P (compute_mode))
5771 enum machine_mode imode;
5773 /* Something is probably seriously wrong if this matches. */
5774 if (! FLOAT_MODE_P (compute_mode))
5777 /* Try to find an integral mode to pun with. */
5778 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5779 if (imode == BLKmode)
5782 compute_mode = imode;
5783 inner = gen_lowpart_for_combine (imode, inner);
5786 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5787 if (len < HOST_BITS_PER_WIDE_INT)
5788 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5792 /* Now compute the equivalent expression. Make a copy of INNER
5793 for the SET_DEST in case it is a MEM into which we will substitute;
5794 we don't want shared RTL in that case. */
5796 (VOIDmode, copy_rtx (inner),
5797 gen_binary (IOR, compute_mode,
5798 gen_binary (AND, compute_mode,
5799 simplify_gen_unary (NOT, compute_mode,
5805 gen_binary (ASHIFT, compute_mode,
5806 gen_binary (AND, compute_mode,
5807 gen_lowpart_for_combine
5808 (compute_mode, SET_SRC (x)),
5816 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5817 it is an RTX that represents a variable starting position; otherwise,
5818 POS is the (constant) starting bit position (counted from the LSB).
5820 INNER may be a USE. This will occur when we started with a bitfield
5821 that went outside the boundary of the object in memory, which is
5822 allowed on most machines. To isolate this case, we produce a USE
5823 whose mode is wide enough and surround the MEM with it. The only
5824 code that understands the USE is this routine. If it is not removed,
5825 it will cause the resulting insn not to match.
5827 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5830 IN_DEST is non-zero if this is a reference in the destination of a
5831 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5832 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5835 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5836 ZERO_EXTRACT should be built even for bits starting at bit 0.
5838 MODE is the desired mode of the result (if IN_DEST == 0).
5840 The result is an RTX for the extraction or NULL_RTX if the target
5844 make_extraction (mode, inner, pos, pos_rtx, len,
5845 unsignedp, in_dest, in_compare)
5846 enum machine_mode mode;
5850 unsigned HOST_WIDE_INT len;
5852 int in_dest, in_compare;
5854 /* This mode describes the size of the storage area
5855 to fetch the overall value from. Within that, we
5856 ignore the POS lowest bits, etc. */
5857 enum machine_mode is_mode = GET_MODE (inner);
5858 enum machine_mode inner_mode;
5859 enum machine_mode wanted_inner_mode = byte_mode;
5860 enum machine_mode wanted_inner_reg_mode = word_mode;
5861 enum machine_mode pos_mode = word_mode;
5862 enum machine_mode extraction_mode = word_mode;
5863 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5866 rtx orig_pos_rtx = pos_rtx;
5867 HOST_WIDE_INT orig_pos;
5869 /* Get some information about INNER and get the innermost object. */
5870 if (GET_CODE (inner) == USE)
5871 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5872 /* We don't need to adjust the position because we set up the USE
5873 to pretend that it was a full-word object. */
5874 spans_byte = 1, inner = XEXP (inner, 0);
5875 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5877 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5878 consider just the QI as the memory to extract from.
5879 The subreg adds or removes high bits; its mode is
5880 irrelevant to the meaning of this extraction,
5881 since POS and LEN count from the lsb. */
5882 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5883 is_mode = GET_MODE (SUBREG_REG (inner));
5884 inner = SUBREG_REG (inner);
5887 inner_mode = GET_MODE (inner);
5889 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5890 pos = INTVAL (pos_rtx), pos_rtx = 0;
5892 /* See if this can be done without an extraction. We never can if the
5893 width of the field is not the same as that of some integer mode. For
5894 registers, we can only avoid the extraction if the position is at the
5895 low-order bit and this is either not in the destination or we have the
5896 appropriate STRICT_LOW_PART operation available.
5898 For MEM, we can avoid an extract if the field starts on an appropriate
5899 boundary and we can change the mode of the memory reference. However,
5900 we cannot directly access the MEM if we have a USE and the underlying
5901 MEM is not TMODE. This combination means that MEM was being used in a
5902 context where bits outside its mode were being referenced; that is only
5903 valid in bit-field insns. */
5905 if (tmode != BLKmode
5906 && ! (spans_byte && inner_mode != tmode)
5907 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5908 && GET_CODE (inner) != MEM
5910 || (GET_CODE (inner) == REG
5911 && have_insn_for (STRICT_LOW_PART, tmode))))
5912 || (GET_CODE (inner) == MEM && pos_rtx == 0
5914 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5915 : BITS_PER_UNIT)) == 0
5916 /* We can't do this if we are widening INNER_MODE (it
5917 may not be aligned, for one thing). */
5918 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5919 && (inner_mode == tmode
5920 || (! mode_dependent_address_p (XEXP (inner, 0))
5921 && ! MEM_VOLATILE_P (inner))))))
5923 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5924 field. If the original and current mode are the same, we need not
5925 adjust the offset. Otherwise, we do if bytes big endian.
5927 If INNER is not a MEM, get a piece consisting of just the field
5928 of interest (in this case POS % BITS_PER_WORD must be 0). */
5930 if (GET_CODE (inner) == MEM)
5932 HOST_WIDE_INT offset;
5934 /* POS counts from lsb, but make OFFSET count in memory order. */
5935 if (BYTES_BIG_ENDIAN)
5936 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5938 offset = pos / BITS_PER_UNIT;
5940 new = adjust_address_nv (inner, tmode, offset);
5942 else if (GET_CODE (inner) == REG)
5944 /* We can't call gen_lowpart_for_combine here since we always want
5945 a SUBREG and it would sometimes return a new hard register. */
5946 if (tmode != inner_mode)
5948 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5950 if (WORDS_BIG_ENDIAN
5951 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5952 final_word = ((GET_MODE_SIZE (inner_mode)
5953 - GET_MODE_SIZE (tmode))
5954 / UNITS_PER_WORD) - final_word;
5956 final_word *= UNITS_PER_WORD;
5957 if (BYTES_BIG_ENDIAN &&
5958 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5959 final_word += (GET_MODE_SIZE (inner_mode)
5960 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5962 new = gen_rtx_SUBREG (tmode, inner, final_word);
5968 new = force_to_mode (inner, tmode,
5969 len >= HOST_BITS_PER_WIDE_INT
5970 ? ~(unsigned HOST_WIDE_INT) 0
5971 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5974 /* If this extraction is going into the destination of a SET,
5975 make a STRICT_LOW_PART unless we made a MEM. */
5978 return (GET_CODE (new) == MEM ? new
5979 : (GET_CODE (new) != SUBREG
5980 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5981 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5986 /* If we know that no extraneous bits are set, and that the high
5987 bit is not set, convert the extraction to the cheaper of
5988 sign and zero extension, that are equivalent in these cases. */
5989 if (flag_expensive_optimizations
5990 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5991 && ((nonzero_bits (new, tmode)
5992 & ~(((unsigned HOST_WIDE_INT)
5993 GET_MODE_MASK (tmode))
5997 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5998 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6000 /* Prefer ZERO_EXTENSION, since it gives more information to
6002 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6007 /* Otherwise, sign- or zero-extend unless we already are in the
6010 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6014 /* Unless this is a COMPARE or we have a funny memory reference,
6015 don't do anything with zero-extending field extracts starting at
6016 the low-order bit since they are simple AND operations. */
6017 if (pos_rtx == 0 && pos == 0 && ! in_dest
6018 && ! in_compare && ! spans_byte && unsignedp)
6021 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6022 we would be spanning bytes or if the position is not a constant and the
6023 length is not 1. In all other cases, we would only be going outside
6024 our object in cases when an original shift would have been
6026 if (! spans_byte && GET_CODE (inner) == MEM
6027 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6028 || (pos_rtx != 0 && len != 1)))
6031 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6032 and the mode for the result. */
6033 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6035 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6036 pos_mode = mode_for_extraction (EP_insv, 2);
6037 extraction_mode = mode_for_extraction (EP_insv, 3);
6040 if (! in_dest && unsignedp
6041 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6043 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6044 pos_mode = mode_for_extraction (EP_extzv, 3);
6045 extraction_mode = mode_for_extraction (EP_extzv, 0);
6048 if (! in_dest && ! unsignedp
6049 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6051 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6052 pos_mode = mode_for_extraction (EP_extv, 3);
6053 extraction_mode = mode_for_extraction (EP_extv, 0);
6056 /* Never narrow an object, since that might not be safe. */
6058 if (mode != VOIDmode
6059 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6060 extraction_mode = mode;
6062 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6063 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6064 pos_mode = GET_MODE (pos_rtx);
6066 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6067 if we have to change the mode of memory and cannot, the desired mode is
6069 if (GET_CODE (inner) != MEM)
6070 wanted_inner_mode = wanted_inner_reg_mode;
6071 else if (inner_mode != wanted_inner_mode
6072 && (mode_dependent_address_p (XEXP (inner, 0))
6073 || MEM_VOLATILE_P (inner)))
6074 wanted_inner_mode = extraction_mode;
6078 if (BITS_BIG_ENDIAN)
6080 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6081 BITS_BIG_ENDIAN style. If position is constant, compute new
6082 position. Otherwise, build subtraction.
6083 Note that POS is relative to the mode of the original argument.
6084 If it's a MEM we need to recompute POS relative to that.
6085 However, if we're extracting from (or inserting into) a register,
6086 we want to recompute POS relative to wanted_inner_mode. */
6087 int width = (GET_CODE (inner) == MEM
6088 ? GET_MODE_BITSIZE (is_mode)
6089 : GET_MODE_BITSIZE (wanted_inner_mode));
6092 pos = width - len - pos;
6095 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6096 /* POS may be less than 0 now, but we check for that below.
6097 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6100 /* If INNER has a wider mode, make it smaller. If this is a constant
6101 extract, try to adjust the byte to point to the byte containing
6103 if (wanted_inner_mode != VOIDmode
6104 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6105 && ((GET_CODE (inner) == MEM
6106 && (inner_mode == wanted_inner_mode
6107 || (! mode_dependent_address_p (XEXP (inner, 0))
6108 && ! MEM_VOLATILE_P (inner))))))
6112 /* The computations below will be correct if the machine is big
6113 endian in both bits and bytes or little endian in bits and bytes.
6114 If it is mixed, we must adjust. */
6116 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6117 adjust OFFSET to compensate. */
6118 if (BYTES_BIG_ENDIAN
6120 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6121 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6123 /* If this is a constant position, we can move to the desired byte. */
6126 offset += pos / BITS_PER_UNIT;
6127 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6130 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6132 && is_mode != wanted_inner_mode)
6133 offset = (GET_MODE_SIZE (is_mode)
6134 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6136 if (offset != 0 || inner_mode != wanted_inner_mode)
6137 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6140 /* If INNER is not memory, we can always get it into the proper mode. If we
6141 are changing its mode, POS must be a constant and smaller than the size
6143 else if (GET_CODE (inner) != MEM)
6145 if (GET_MODE (inner) != wanted_inner_mode
6147 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6150 inner = force_to_mode (inner, wanted_inner_mode,
6152 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6153 ? ~(unsigned HOST_WIDE_INT) 0
6154 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6159 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6160 have to zero extend. Otherwise, we can just use a SUBREG. */
6162 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6164 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6166 /* If we know that no extraneous bits are set, and that the high
6167 bit is not set, convert extraction to cheaper one - either
6168 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6170 if (flag_expensive_optimizations
6171 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6172 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6173 & ~(((unsigned HOST_WIDE_INT)
6174 GET_MODE_MASK (GET_MODE (pos_rtx)))
6178 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6180 /* Prefer ZERO_EXTENSION, since it gives more information to
6182 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6187 else if (pos_rtx != 0
6188 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6189 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6191 /* Make POS_RTX unless we already have it and it is correct. If we don't
6192 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6194 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6195 pos_rtx = orig_pos_rtx;
6197 else if (pos_rtx == 0)
6198 pos_rtx = GEN_INT (pos);
6200 /* Make the required operation. See if we can use existing rtx. */
6201 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6202 extraction_mode, inner, GEN_INT (len), pos_rtx);
6204 new = gen_lowpart_for_combine (mode, new);
6209 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6210 with any other operations in X. Return X without that shift if so. */
6213 extract_left_shift (x, count)
6217 enum rtx_code code = GET_CODE (x);
6218 enum machine_mode mode = GET_MODE (x);
6224 /* This is the shift itself. If it is wide enough, we will return
6225 either the value being shifted if the shift count is equal to
6226 COUNT or a shift for the difference. */
6227 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6228 && INTVAL (XEXP (x, 1)) >= count)
6229 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6230 INTVAL (XEXP (x, 1)) - count);
6234 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6235 return simplify_gen_unary (code, mode, tem, mode);
6239 case PLUS: case IOR: case XOR: case AND:
6240 /* If we can safely shift this constant and we find the inner shift,
6241 make a new operation. */
6242 if (GET_CODE (XEXP (x,1)) == CONST_INT
6243 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6244 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6245 return gen_binary (code, mode, tem,
6246 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6257 /* Look at the expression rooted at X. Look for expressions
6258 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6259 Form these expressions.
6261 Return the new rtx, usually just X.
6263 Also, for machines like the VAX that don't have logical shift insns,
6264 try to convert logical to arithmetic shift operations in cases where
6265 they are equivalent. This undoes the canonicalizations to logical
6266 shifts done elsewhere.
6268 We try, as much as possible, to re-use rtl expressions to save memory.
6270 IN_CODE says what kind of expression we are processing. Normally, it is
6271 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6272 being kludges), it is MEM. When processing the arguments of a comparison
6273 or a COMPARE against zero, it is COMPARE. */
6276 make_compound_operation (x, in_code)
6278 enum rtx_code in_code;
6280 enum rtx_code code = GET_CODE (x);
6281 enum machine_mode mode = GET_MODE (x);
6282 int mode_width = GET_MODE_BITSIZE (mode);
6284 enum rtx_code next_code;
6290 /* Select the code to be used in recursive calls. Once we are inside an
6291 address, we stay there. If we have a comparison, set to COMPARE,
6292 but once inside, go back to our default of SET. */
6294 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6295 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6296 && XEXP (x, 1) == const0_rtx) ? COMPARE
6297 : in_code == COMPARE ? SET : in_code);
6299 /* Process depending on the code of this operation. If NEW is set
6300 non-zero, it will be returned. */
6305 /* Convert shifts by constants into multiplications if inside
6307 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6308 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6309 && INTVAL (XEXP (x, 1)) >= 0)
6311 new = make_compound_operation (XEXP (x, 0), next_code);
6312 new = gen_rtx_MULT (mode, new,
6313 GEN_INT ((HOST_WIDE_INT) 1
6314 << INTVAL (XEXP (x, 1))));
6319 /* If the second operand is not a constant, we can't do anything
6321 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6324 /* If the constant is a power of two minus one and the first operand
6325 is a logical right shift, make an extraction. */
6326 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6327 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6329 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6330 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6331 0, in_code == COMPARE);
6334 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6335 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6336 && subreg_lowpart_p (XEXP (x, 0))
6337 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6338 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6340 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6342 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6343 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6344 0, in_code == COMPARE);
6346 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6347 else if ((GET_CODE (XEXP (x, 0)) == XOR
6348 || GET_CODE (XEXP (x, 0)) == IOR)
6349 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6350 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6351 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6353 /* Apply the distributive law, and then try to make extractions. */
6354 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6355 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6357 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6359 new = make_compound_operation (new, in_code);
6362 /* If we are have (and (rotate X C) M) and C is larger than the number
6363 of bits in M, this is an extraction. */
6365 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6366 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6367 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6368 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6370 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6371 new = make_extraction (mode, new,
6372 (GET_MODE_BITSIZE (mode)
6373 - INTVAL (XEXP (XEXP (x, 0), 1))),
6374 NULL_RTX, i, 1, 0, in_code == COMPARE);
6377 /* On machines without logical shifts, if the operand of the AND is
6378 a logical shift and our mask turns off all the propagated sign
6379 bits, we can replace the logical shift with an arithmetic shift. */
6380 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6381 && !have_insn_for (LSHIFTRT, mode)
6382 && have_insn_for (ASHIFTRT, mode)
6383 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6384 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6385 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6386 && mode_width <= HOST_BITS_PER_WIDE_INT)
6388 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6390 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6391 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6393 gen_rtx_ASHIFTRT (mode,
6394 make_compound_operation
6395 (XEXP (XEXP (x, 0), 0), next_code),
6396 XEXP (XEXP (x, 0), 1)));
6399 /* If the constant is one less than a power of two, this might be
6400 representable by an extraction even if no shift is present.
6401 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6402 we are in a COMPARE. */
6403 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6404 new = make_extraction (mode,
6405 make_compound_operation (XEXP (x, 0),
6407 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6409 /* If we are in a comparison and this is an AND with a power of two,
6410 convert this into the appropriate bit extract. */
6411 else if (in_code == COMPARE
6412 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6413 new = make_extraction (mode,
6414 make_compound_operation (XEXP (x, 0),
6416 i, NULL_RTX, 1, 1, 0, 1);
6421 /* If the sign bit is known to be zero, replace this with an
6422 arithmetic shift. */
6423 if (have_insn_for (ASHIFTRT, mode)
6424 && ! have_insn_for (LSHIFTRT, mode)
6425 && mode_width <= HOST_BITS_PER_WIDE_INT
6426 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6428 new = gen_rtx_ASHIFTRT (mode,
6429 make_compound_operation (XEXP (x, 0),
6435 /* ... fall through ... */
6441 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6442 this is a SIGN_EXTRACT. */
6443 if (GET_CODE (rhs) == CONST_INT
6444 && GET_CODE (lhs) == ASHIFT
6445 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6446 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6448 new = make_compound_operation (XEXP (lhs, 0), next_code);
6449 new = make_extraction (mode, new,
6450 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6451 NULL_RTX, mode_width - INTVAL (rhs),
6452 code == LSHIFTRT, 0, in_code == COMPARE);
6456 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6457 If so, try to merge the shifts into a SIGN_EXTEND. We could
6458 also do this for some cases of SIGN_EXTRACT, but it doesn't
6459 seem worth the effort; the case checked for occurs on Alpha. */
6461 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6462 && ! (GET_CODE (lhs) == SUBREG
6463 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6464 && GET_CODE (rhs) == CONST_INT
6465 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6466 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6467 new = make_extraction (mode, make_compound_operation (new, next_code),
6468 0, NULL_RTX, mode_width - INTVAL (rhs),
6469 code == LSHIFTRT, 0, in_code == COMPARE);
6474 /* Call ourselves recursively on the inner expression. If we are
6475 narrowing the object and it has a different RTL code from
6476 what it originally did, do this SUBREG as a force_to_mode. */
6478 tem = make_compound_operation (SUBREG_REG (x), in_code);
6479 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6480 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6481 && subreg_lowpart_p (x))
6483 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6486 /* If we have something other than a SUBREG, we might have
6487 done an expansion, so rerun ourselves. */
6488 if (GET_CODE (newer) != SUBREG)
6489 newer = make_compound_operation (newer, in_code);
6494 /* If this is a paradoxical subreg, and the new code is a sign or
6495 zero extension, omit the subreg and widen the extension. If it
6496 is a regular subreg, we can still get rid of the subreg by not
6497 widening so much, or in fact removing the extension entirely. */
6498 if ((GET_CODE (tem) == SIGN_EXTEND
6499 || GET_CODE (tem) == ZERO_EXTEND)
6500 && subreg_lowpart_p (x))
6502 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6503 || (GET_MODE_SIZE (mode) >
6504 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6505 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6507 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6518 x = gen_lowpart_for_combine (mode, new);
6519 code = GET_CODE (x);
6522 /* Now recursively process each operand of this operation. */
6523 fmt = GET_RTX_FORMAT (code);
6524 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6527 new = make_compound_operation (XEXP (x, i), next_code);
6528 SUBST (XEXP (x, i), new);
6534 /* Given M see if it is a value that would select a field of bits
6535 within an item, but not the entire word. Return -1 if not.
6536 Otherwise, return the starting position of the field, where 0 is the
6539 *PLEN is set to the length of the field. */
6542 get_pos_from_mask (m, plen)
6543 unsigned HOST_WIDE_INT m;
6544 unsigned HOST_WIDE_INT *plen;
6546 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6547 int pos = exact_log2 (m & -m);
6553 /* Now shift off the low-order zero bits and see if we have a power of
6555 len = exact_log2 ((m >> pos) + 1);
6564 /* See if X can be simplified knowing that we will only refer to it in
6565 MODE and will only refer to those bits that are nonzero in MASK.
6566 If other bits are being computed or if masking operations are done
6567 that select a superset of the bits in MASK, they can sometimes be
6570 Return a possibly simplified expression, but always convert X to
6571 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6573 Also, if REG is non-zero and X is a register equal in value to REG,
6576 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6577 are all off in X. This is used when X will be complemented, by either
6578 NOT, NEG, or XOR. */
6581 force_to_mode (x, mode, mask, reg, just_select)
6583 enum machine_mode mode;
6584 unsigned HOST_WIDE_INT mask;
6588 enum rtx_code code = GET_CODE (x);
6589 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6590 enum machine_mode op_mode;
6591 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6594 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6595 code below will do the wrong thing since the mode of such an
6596 expression is VOIDmode.
6598 Also do nothing if X is a CLOBBER; this can happen if X was
6599 the return value from a call to gen_lowpart_for_combine. */
6600 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6603 /* We want to perform the operation is its present mode unless we know
6604 that the operation is valid in MODE, in which case we do the operation
6606 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6607 && have_insn_for (code, mode))
6608 ? mode : GET_MODE (x));
6610 /* It is not valid to do a right-shift in a narrower mode
6611 than the one it came in with. */
6612 if ((code == LSHIFTRT || code == ASHIFTRT)
6613 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6614 op_mode = GET_MODE (x);
6616 /* Truncate MASK to fit OP_MODE. */
6618 mask &= GET_MODE_MASK (op_mode);
6620 /* When we have an arithmetic operation, or a shift whose count we
6621 do not know, we need to assume that all bit the up to the highest-order
6622 bit in MASK will be needed. This is how we form such a mask. */
6624 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6625 ? GET_MODE_MASK (op_mode)
6626 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6629 fuller_mask = ~(HOST_WIDE_INT) 0;
6631 /* Determine what bits of X are guaranteed to be (non)zero. */
6632 nonzero = nonzero_bits (x, mode);
6634 /* If none of the bits in X are needed, return a zero. */
6635 if (! just_select && (nonzero & mask) == 0)
6638 /* If X is a CONST_INT, return a new one. Do this here since the
6639 test below will fail. */
6640 if (GET_CODE (x) == CONST_INT)
6642 HOST_WIDE_INT cval = INTVAL (x) & mask;
6643 int width = GET_MODE_BITSIZE (mode);
6645 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6646 number, sign extend it. */
6647 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6648 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6649 cval |= (HOST_WIDE_INT) -1 << width;
6651 return GEN_INT (cval);
6654 /* If X is narrower than MODE and we want all the bits in X's mode, just
6655 get X in the proper mode. */
6656 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6657 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6658 return gen_lowpart_for_combine (mode, x);
6660 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6661 MASK are already known to be zero in X, we need not do anything. */
6662 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6668 /* If X is a (clobber (const_int)), return it since we know we are
6669 generating something that won't match. */
6673 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6674 spanned the boundary of the MEM. If we are now masking so it is
6675 within that boundary, we don't need the USE any more. */
6676 if (! BITS_BIG_ENDIAN
6677 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6678 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6685 x = expand_compound_operation (x);
6686 if (GET_CODE (x) != code)
6687 return force_to_mode (x, mode, mask, reg, next_select);
6691 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6692 || rtx_equal_p (reg, get_last_value (x))))
6697 if (subreg_lowpart_p (x)
6698 /* We can ignore the effect of this SUBREG if it narrows the mode or
6699 if the constant masks to zero all the bits the mode doesn't
6701 && ((GET_MODE_SIZE (GET_MODE (x))
6702 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6704 & GET_MODE_MASK (GET_MODE (x))
6705 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6706 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6710 /* If this is an AND with a constant, convert it into an AND
6711 whose constant is the AND of that constant with MASK. If it
6712 remains an AND of MASK, delete it since it is redundant. */
6714 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6716 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6717 mask & INTVAL (XEXP (x, 1)));
6719 /* If X is still an AND, see if it is an AND with a mask that
6720 is just some low-order bits. If so, and it is MASK, we don't
6723 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6724 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6725 == (HOST_WIDE_INT) mask))
6728 /* If it remains an AND, try making another AND with the bits
6729 in the mode mask that aren't in MASK turned on. If the
6730 constant in the AND is wide enough, this might make a
6731 cheaper constant. */
6733 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6734 && GET_MODE_MASK (GET_MODE (x)) != mask
6735 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6737 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6738 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6739 int width = GET_MODE_BITSIZE (GET_MODE (x));
6742 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6743 number, sign extend it. */
6744 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6745 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6746 cval |= (HOST_WIDE_INT) -1 << width;
6748 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6749 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6759 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6760 low-order bits (as in an alignment operation) and FOO is already
6761 aligned to that boundary, mask C1 to that boundary as well.
6762 This may eliminate that PLUS and, later, the AND. */
6765 unsigned int width = GET_MODE_BITSIZE (mode);
6766 unsigned HOST_WIDE_INT smask = mask;
6768 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6769 number, sign extend it. */
6771 if (width < HOST_BITS_PER_WIDE_INT
6772 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6773 smask |= (HOST_WIDE_INT) -1 << width;
6775 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6776 && exact_log2 (- smask) >= 0
6777 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6778 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6779 return force_to_mode (plus_constant (XEXP (x, 0),
6780 (INTVAL (XEXP (x, 1)) & smask)),
6781 mode, smask, reg, next_select);
6784 /* ... fall through ... */
6787 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6788 most significant bit in MASK since carries from those bits will
6789 affect the bits we are interested in. */
6794 /* If X is (minus C Y) where C's least set bit is larger than any bit
6795 in the mask, then we may replace with (neg Y). */
6796 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6797 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6798 & -INTVAL (XEXP (x, 0))))
6801 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6803 return force_to_mode (x, mode, mask, reg, next_select);
6806 /* Similarly, if C contains every bit in the mask, then we may
6807 replace with (not Y). */
6808 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6809 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6810 == INTVAL (XEXP (x, 0))))
6812 x = simplify_gen_unary (NOT, GET_MODE (x),
6813 XEXP (x, 1), GET_MODE (x));
6814 return force_to_mode (x, mode, mask, reg, next_select);
6822 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6823 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6824 operation which may be a bitfield extraction. Ensure that the
6825 constant we form is not wider than the mode of X. */
6827 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6828 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6829 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6830 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6831 && GET_CODE (XEXP (x, 1)) == CONST_INT
6832 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6833 + floor_log2 (INTVAL (XEXP (x, 1))))
6834 < GET_MODE_BITSIZE (GET_MODE (x)))
6835 && (INTVAL (XEXP (x, 1))
6836 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6838 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6839 << INTVAL (XEXP (XEXP (x, 0), 1)));
6840 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6841 XEXP (XEXP (x, 0), 0), temp);
6842 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6843 XEXP (XEXP (x, 0), 1));
6844 return force_to_mode (x, mode, mask, reg, next_select);
6848 /* For most binary operations, just propagate into the operation and
6849 change the mode if we have an operation of that mode. */
6851 op0 = gen_lowpart_for_combine (op_mode,
6852 force_to_mode (XEXP (x, 0), mode, mask,
6854 op1 = gen_lowpart_for_combine (op_mode,
6855 force_to_mode (XEXP (x, 1), mode, mask,
6858 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6859 MASK since OP1 might have been sign-extended but we never want
6860 to turn on extra bits, since combine might have previously relied
6861 on them being off. */
6862 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6863 && (INTVAL (op1) & mask) != 0)
6864 op1 = GEN_INT (INTVAL (op1) & mask);
6866 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6867 x = gen_binary (code, op_mode, op0, op1);
6871 /* For left shifts, do the same, but just for the first operand.
6872 However, we cannot do anything with shifts where we cannot
6873 guarantee that the counts are smaller than the size of the mode
6874 because such a count will have a different meaning in a
6877 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6878 && INTVAL (XEXP (x, 1)) >= 0
6879 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6880 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6881 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6882 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6885 /* If the shift count is a constant and we can do arithmetic in
6886 the mode of the shift, refine which bits we need. Otherwise, use the
6887 conservative form of the mask. */
6888 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6889 && INTVAL (XEXP (x, 1)) >= 0
6890 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6891 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6892 mask >>= INTVAL (XEXP (x, 1));
6896 op0 = gen_lowpart_for_combine (op_mode,
6897 force_to_mode (XEXP (x, 0), op_mode,
6898 mask, reg, next_select));
6900 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6901 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6905 /* Here we can only do something if the shift count is a constant,
6906 this shift constant is valid for the host, and we can do arithmetic
6909 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6910 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6911 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6913 rtx inner = XEXP (x, 0);
6914 unsigned HOST_WIDE_INT inner_mask;
6916 /* Select the mask of the bits we need for the shift operand. */
6917 inner_mask = mask << INTVAL (XEXP (x, 1));
6919 /* We can only change the mode of the shift if we can do arithmetic
6920 in the mode of the shift and INNER_MASK is no wider than the
6921 width of OP_MODE. */
6922 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6923 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6924 op_mode = GET_MODE (x);
6926 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6928 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6929 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6932 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6933 shift and AND produces only copies of the sign bit (C2 is one less
6934 than a power of two), we can do this with just a shift. */
6936 if (GET_CODE (x) == LSHIFTRT
6937 && GET_CODE (XEXP (x, 1)) == CONST_INT
6938 /* The shift puts one of the sign bit copies in the least significant
6940 && ((INTVAL (XEXP (x, 1))
6941 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6942 >= GET_MODE_BITSIZE (GET_MODE (x)))
6943 && exact_log2 (mask + 1) >= 0
6944 /* Number of bits left after the shift must be more than the mask
6946 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6947 <= GET_MODE_BITSIZE (GET_MODE (x)))
6948 /* Must be more sign bit copies than the mask needs. */
6949 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6950 >= exact_log2 (mask + 1)))
6951 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6952 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6953 - exact_log2 (mask + 1)));
6958 /* If we are just looking for the sign bit, we don't need this shift at
6959 all, even if it has a variable count. */
6960 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6961 && (mask == ((unsigned HOST_WIDE_INT) 1
6962 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6963 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6965 /* If this is a shift by a constant, get a mask that contains those bits
6966 that are not copies of the sign bit. We then have two cases: If
6967 MASK only includes those bits, this can be a logical shift, which may
6968 allow simplifications. If MASK is a single-bit field not within
6969 those bits, we are requesting a copy of the sign bit and hence can
6970 shift the sign bit to the appropriate location. */
6972 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6973 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6977 /* If the considered data is wider than HOST_WIDE_INT, we can't
6978 represent a mask for all its bits in a single scalar.
6979 But we only care about the lower bits, so calculate these. */
6981 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6983 nonzero = ~(HOST_WIDE_INT) 0;
6985 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6986 is the number of bits a full-width mask would have set.
6987 We need only shift if these are fewer than nonzero can
6988 hold. If not, we must keep all bits set in nonzero. */
6990 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6991 < HOST_BITS_PER_WIDE_INT)
6992 nonzero >>= INTVAL (XEXP (x, 1))
6993 + HOST_BITS_PER_WIDE_INT
6994 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6998 nonzero = GET_MODE_MASK (GET_MODE (x));
6999 nonzero >>= INTVAL (XEXP (x, 1));
7002 if ((mask & ~nonzero) == 0
7003 || (i = exact_log2 (mask)) >= 0)
7005 x = simplify_shift_const
7006 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7007 i < 0 ? INTVAL (XEXP (x, 1))
7008 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7010 if (GET_CODE (x) != ASHIFTRT)
7011 return force_to_mode (x, mode, mask, reg, next_select);
7015 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7016 even if the shift count isn't a constant. */
7018 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7022 /* If this is a zero- or sign-extension operation that just affects bits
7023 we don't care about, remove it. Be sure the call above returned
7024 something that is still a shift. */
7026 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7027 && GET_CODE (XEXP (x, 1)) == CONST_INT
7028 && INTVAL (XEXP (x, 1)) >= 0
7029 && (INTVAL (XEXP (x, 1))
7030 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7031 && GET_CODE (XEXP (x, 0)) == ASHIFT
7032 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7033 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7034 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7041 /* If the shift count is constant and we can do computations
7042 in the mode of X, compute where the bits we care about are.
7043 Otherwise, we can't do anything. Don't change the mode of
7044 the shift or propagate MODE into the shift, though. */
7045 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7046 && INTVAL (XEXP (x, 1)) >= 0)
7048 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7049 GET_MODE (x), GEN_INT (mask),
7051 if (temp && GET_CODE(temp) == CONST_INT)
7053 force_to_mode (XEXP (x, 0), GET_MODE (x),
7054 INTVAL (temp), reg, next_select));
7059 /* If we just want the low-order bit, the NEG isn't needed since it
7060 won't change the low-order bit. */
7062 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7064 /* We need any bits less significant than the most significant bit in
7065 MASK since carries from those bits will affect the bits we are
7071 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7072 same as the XOR case above. Ensure that the constant we form is not
7073 wider than the mode of X. */
7075 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7077 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7078 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7079 < GET_MODE_BITSIZE (GET_MODE (x)))
7080 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7082 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7083 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7084 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7086 return force_to_mode (x, mode, mask, reg, next_select);
7089 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7090 use the full mask inside the NOT. */
7094 op0 = gen_lowpart_for_combine (op_mode,
7095 force_to_mode (XEXP (x, 0), mode, mask,
7097 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7098 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7102 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7103 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7104 which is equal to STORE_FLAG_VALUE. */
7105 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7106 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7107 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7108 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7113 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7114 written in a narrower mode. We play it safe and do not do so. */
7117 gen_lowpart_for_combine (GET_MODE (x),
7118 force_to_mode (XEXP (x, 1), mode,
7119 mask, reg, next_select)));
7121 gen_lowpart_for_combine (GET_MODE (x),
7122 force_to_mode (XEXP (x, 2), mode,
7123 mask, reg,next_select)));
7130 /* Ensure we return a value of the proper mode. */
7131 return gen_lowpart_for_combine (mode, x);
7134 /* Return nonzero if X is an expression that has one of two values depending on
7135 whether some other value is zero or nonzero. In that case, we return the
7136 value that is being tested, *PTRUE is set to the value if the rtx being
7137 returned has a nonzero value, and *PFALSE is set to the other alternative.
7139 If we return zero, we set *PTRUE and *PFALSE to X. */
7142 if_then_else_cond (x, ptrue, pfalse)
7144 rtx *ptrue, *pfalse;
7146 enum machine_mode mode = GET_MODE (x);
7147 enum rtx_code code = GET_CODE (x);
7148 rtx cond0, cond1, true0, true1, false0, false1;
7149 unsigned HOST_WIDE_INT nz;
7151 /* If we are comparing a value against zero, we are done. */
7152 if ((code == NE || code == EQ)
7153 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7155 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7156 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7160 /* If this is a unary operation whose operand has one of two values, apply
7161 our opcode to compute those values. */
7162 else if (GET_RTX_CLASS (code) == '1'
7163 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7165 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7166 *pfalse = simplify_gen_unary (code, mode, false0,
7167 GET_MODE (XEXP (x, 0)));
7171 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7172 make can't possibly match and would suppress other optimizations. */
7173 else if (code == COMPARE)
7176 /* If this is a binary operation, see if either side has only one of two
7177 values. If either one does or if both do and they are conditional on
7178 the same value, compute the new true and false values. */
7179 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7180 || GET_RTX_CLASS (code) == '<')
7182 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7183 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7185 if ((cond0 != 0 || cond1 != 0)
7186 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7188 /* If if_then_else_cond returned zero, then true/false are the
7189 same rtl. We must copy one of them to prevent invalid rtl
7192 true0 = copy_rtx (true0);
7193 else if (cond1 == 0)
7194 true1 = copy_rtx (true1);
7196 *ptrue = gen_binary (code, mode, true0, true1);
7197 *pfalse = gen_binary (code, mode, false0, false1);
7198 return cond0 ? cond0 : cond1;
7201 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7202 operands is zero when the other is non-zero, and vice-versa,
7203 and STORE_FLAG_VALUE is 1 or -1. */
7205 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7206 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7208 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7210 rtx op0 = XEXP (XEXP (x, 0), 1);
7211 rtx op1 = XEXP (XEXP (x, 1), 1);
7213 cond0 = XEXP (XEXP (x, 0), 0);
7214 cond1 = XEXP (XEXP (x, 1), 0);
7216 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7217 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7218 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7219 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7220 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7221 || ((swap_condition (GET_CODE (cond0))
7222 == combine_reversed_comparison_code (cond1))
7223 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7224 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7225 && ! side_effects_p (x))
7227 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7228 *pfalse = gen_binary (MULT, mode,
7230 ? simplify_gen_unary (NEG, mode, op1,
7238 /* Similarly for MULT, AND and UMIN, except that for these the result
7240 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7241 && (code == MULT || code == AND || code == UMIN)
7242 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7244 cond0 = XEXP (XEXP (x, 0), 0);
7245 cond1 = XEXP (XEXP (x, 1), 0);
7247 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7248 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7249 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7250 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7251 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7252 || ((swap_condition (GET_CODE (cond0))
7253 == combine_reversed_comparison_code (cond1))
7254 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7255 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7256 && ! side_effects_p (x))
7258 *ptrue = *pfalse = const0_rtx;
7264 else if (code == IF_THEN_ELSE)
7266 /* If we have IF_THEN_ELSE already, extract the condition and
7267 canonicalize it if it is NE or EQ. */
7268 cond0 = XEXP (x, 0);
7269 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7270 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7271 return XEXP (cond0, 0);
7272 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7274 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7275 return XEXP (cond0, 0);
7281 /* If X is a SUBREG, we can narrow both the true and false values
7282 if the inner expression, if there is a condition. */
7283 else if (code == SUBREG
7284 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7287 *ptrue = simplify_gen_subreg (mode, true0,
7288 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7289 *pfalse = simplify_gen_subreg (mode, false0,
7290 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7295 /* If X is a constant, this isn't special and will cause confusions
7296 if we treat it as such. Likewise if it is equivalent to a constant. */
7297 else if (CONSTANT_P (x)
7298 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7301 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7302 will be least confusing to the rest of the compiler. */
7303 else if (mode == BImode)
7305 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7309 /* If X is known to be either 0 or -1, those are the true and
7310 false values when testing X. */
7311 else if (x == constm1_rtx || x == const0_rtx
7312 || (mode != VOIDmode
7313 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7315 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7319 /* Likewise for 0 or a single bit. */
7320 else if (mode != VOIDmode
7321 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7322 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7324 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7328 /* Otherwise fail; show no condition with true and false values the same. */
7329 *ptrue = *pfalse = x;
7333 /* Return the value of expression X given the fact that condition COND
7334 is known to be true when applied to REG as its first operand and VAL
7335 as its second. X is known to not be shared and so can be modified in
7338 We only handle the simplest cases, and specifically those cases that
7339 arise with IF_THEN_ELSE expressions. */
7342 known_cond (x, cond, reg, val)
7347 enum rtx_code code = GET_CODE (x);
7352 if (side_effects_p (x))
7355 /* If either operand of the condition is a floating point value,
7356 then we have to avoid collapsing an EQ comparison. */
7358 && rtx_equal_p (x, reg)
7359 && ! FLOAT_MODE_P (GET_MODE (x))
7360 && ! FLOAT_MODE_P (GET_MODE (val)))
7363 if (cond == UNEQ && rtx_equal_p (x, reg))
7366 /* If X is (abs REG) and we know something about REG's relationship
7367 with zero, we may be able to simplify this. */
7369 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7372 case GE: case GT: case EQ:
7375 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7377 GET_MODE (XEXP (x, 0)));
7382 /* The only other cases we handle are MIN, MAX, and comparisons if the
7383 operands are the same as REG and VAL. */
7385 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7387 if (rtx_equal_p (XEXP (x, 0), val))
7388 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7390 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7392 if (GET_RTX_CLASS (code) == '<')
7394 if (comparison_dominates_p (cond, code))
7395 return const_true_rtx;
7397 code = combine_reversed_comparison_code (x);
7399 && comparison_dominates_p (cond, code))
7404 else if (code == SMAX || code == SMIN
7405 || code == UMIN || code == UMAX)
7407 int unsignedp = (code == UMIN || code == UMAX);
7409 /* Do not reverse the condition when it is NE or EQ.
7410 This is because we cannot conclude anything about
7411 the value of 'SMAX (x, y)' when x is not equal to y,
7412 but we can when x equals y. */
7413 if ((code == SMAX || code == UMAX)
7414 && ! (cond == EQ || cond == NE))
7415 cond = reverse_condition (cond);
7420 return unsignedp ? x : XEXP (x, 1);
7422 return unsignedp ? x : XEXP (x, 0);
7424 return unsignedp ? XEXP (x, 1) : x;
7426 return unsignedp ? XEXP (x, 0) : x;
7434 fmt = GET_RTX_FORMAT (code);
7435 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7438 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7439 else if (fmt[i] == 'E')
7440 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7441 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7448 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7449 assignment as a field assignment. */
7452 rtx_equal_for_field_assignment_p (x, y)
7456 if (x == y || rtx_equal_p (x, y))
7459 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7462 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7463 Note that all SUBREGs of MEM are paradoxical; otherwise they
7464 would have been rewritten. */
7465 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7466 && GET_CODE (SUBREG_REG (y)) == MEM
7467 && rtx_equal_p (SUBREG_REG (y),
7468 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7471 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7472 && GET_CODE (SUBREG_REG (x)) == MEM
7473 && rtx_equal_p (SUBREG_REG (x),
7474 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7477 /* We used to see if get_last_value of X and Y were the same but that's
7478 not correct. In one direction, we'll cause the assignment to have
7479 the wrong destination and in the case, we'll import a register into this
7480 insn that might have already have been dead. So fail if none of the
7481 above cases are true. */
7485 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7486 Return that assignment if so.
7488 We only handle the most common cases. */
7491 make_field_assignment (x)
7494 rtx dest = SET_DEST (x);
7495 rtx src = SET_SRC (x);
7500 unsigned HOST_WIDE_INT len;
7502 enum machine_mode mode;
7504 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7505 a clear of a one-bit field. We will have changed it to
7506 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7509 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7510 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7511 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7512 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7514 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7517 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7521 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7522 && subreg_lowpart_p (XEXP (src, 0))
7523 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7524 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7525 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7526 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7527 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7529 assign = make_extraction (VOIDmode, dest, 0,
7530 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7533 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7537 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7539 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7540 && XEXP (XEXP (src, 0), 0) == const1_rtx
7541 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7543 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7546 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7550 /* The other case we handle is assignments into a constant-position
7551 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7552 a mask that has all one bits except for a group of zero bits and
7553 OTHER is known to have zeros where C1 has ones, this is such an
7554 assignment. Compute the position and length from C1. Shift OTHER
7555 to the appropriate position, force it to the required mode, and
7556 make the extraction. Check for the AND in both operands. */
7558 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7561 rhs = expand_compound_operation (XEXP (src, 0));
7562 lhs = expand_compound_operation (XEXP (src, 1));
7564 if (GET_CODE (rhs) == AND
7565 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7566 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7567 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7568 else if (GET_CODE (lhs) == AND
7569 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7570 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7571 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7575 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7576 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7577 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7578 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7581 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7585 /* The mode to use for the source is the mode of the assignment, or of
7586 what is inside a possible STRICT_LOW_PART. */
7587 mode = (GET_CODE (assign) == STRICT_LOW_PART
7588 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7590 /* Shift OTHER right POS places and make it the source, restricting it
7591 to the proper length and mode. */
7593 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7594 GET_MODE (src), other, pos),
7596 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7597 ? ~(unsigned HOST_WIDE_INT) 0
7598 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7601 return gen_rtx_SET (VOIDmode, assign, src);
7604 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7608 apply_distributive_law (x)
7611 enum rtx_code code = GET_CODE (x);
7612 rtx lhs, rhs, other;
7614 enum rtx_code inner_code;
7616 /* Distributivity is not true for floating point.
7617 It can change the value. So don't do it.
7618 -- rms and moshier@world.std.com. */
7619 if (FLOAT_MODE_P (GET_MODE (x)))
7622 /* The outer operation can only be one of the following: */
7623 if (code != IOR && code != AND && code != XOR
7624 && code != PLUS && code != MINUS)
7627 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7629 /* If either operand is a primitive we can't do anything, so get out
7631 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7632 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7635 lhs = expand_compound_operation (lhs);
7636 rhs = expand_compound_operation (rhs);
7637 inner_code = GET_CODE (lhs);
7638 if (inner_code != GET_CODE (rhs))
7641 /* See if the inner and outer operations distribute. */
7648 /* These all distribute except over PLUS. */
7649 if (code == PLUS || code == MINUS)
7654 if (code != PLUS && code != MINUS)
7659 /* This is also a multiply, so it distributes over everything. */
7663 /* Non-paradoxical SUBREGs distributes over all operations, provided
7664 the inner modes and byte offsets are the same, this is an extraction
7665 of a low-order part, we don't convert an fp operation to int or
7666 vice versa, and we would not be converting a single-word
7667 operation into a multi-word operation. The latter test is not
7668 required, but it prevents generating unneeded multi-word operations.
7669 Some of the previous tests are redundant given the latter test, but
7670 are retained because they are required for correctness.
7672 We produce the result slightly differently in this case. */
7674 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7675 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7676 || ! subreg_lowpart_p (lhs)
7677 || (GET_MODE_CLASS (GET_MODE (lhs))
7678 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7679 || (GET_MODE_SIZE (GET_MODE (lhs))
7680 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7681 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7684 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7685 SUBREG_REG (lhs), SUBREG_REG (rhs));
7686 return gen_lowpart_for_combine (GET_MODE (x), tem);
7692 /* Set LHS and RHS to the inner operands (A and B in the example
7693 above) and set OTHER to the common operand (C in the example).
7694 These is only one way to do this unless the inner operation is
7696 if (GET_RTX_CLASS (inner_code) == 'c'
7697 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7698 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7699 else if (GET_RTX_CLASS (inner_code) == 'c'
7700 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7701 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7702 else if (GET_RTX_CLASS (inner_code) == 'c'
7703 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7704 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7705 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7706 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7710 /* Form the new inner operation, seeing if it simplifies first. */
7711 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7713 /* There is one exception to the general way of distributing:
7714 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7715 if (code == XOR && inner_code == IOR)
7718 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7721 /* We may be able to continuing distributing the result, so call
7722 ourselves recursively on the inner operation before forming the
7723 outer operation, which we return. */
7724 return gen_binary (inner_code, GET_MODE (x),
7725 apply_distributive_law (tem), other);
7728 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7731 Return an equivalent form, if different from X. Otherwise, return X. If
7732 X is zero, we are to always construct the equivalent form. */
7735 simplify_and_const_int (x, mode, varop, constop)
7737 enum machine_mode mode;
7739 unsigned HOST_WIDE_INT constop;
7741 unsigned HOST_WIDE_INT nonzero;
7744 /* Simplify VAROP knowing that we will be only looking at some of the
7746 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7748 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7749 CONST_INT, we are done. */
7750 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7753 /* See what bits may be nonzero in VAROP. Unlike the general case of
7754 a call to nonzero_bits, here we don't care about bits outside
7757 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7759 /* Turn off all bits in the constant that are known to already be zero.
7760 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7761 which is tested below. */
7765 /* If we don't have any bits left, return zero. */
7769 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7770 a power of two, we can replace this with a ASHIFT. */
7771 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7772 && (i = exact_log2 (constop)) >= 0)
7773 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7775 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7776 or XOR, then try to apply the distributive law. This may eliminate
7777 operations if either branch can be simplified because of the AND.
7778 It may also make some cases more complex, but those cases probably
7779 won't match a pattern either with or without this. */
7781 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7783 gen_lowpart_for_combine
7785 apply_distributive_law
7786 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7787 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7788 XEXP (varop, 0), constop),
7789 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7790 XEXP (varop, 1), constop))));
7792 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7793 the AND and see if one of the operands simplifies to zero. If so, we
7794 may eliminate it. */
7796 if (GET_CODE (varop) == PLUS
7797 && exact_log2 (constop + 1) >= 0)
7801 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7802 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7803 if (o0 == const0_rtx)
7805 if (o1 == const0_rtx)
7809 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7810 if we already had one (just check for the simplest cases). */
7811 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7812 && GET_MODE (XEXP (x, 0)) == mode
7813 && SUBREG_REG (XEXP (x, 0)) == varop)
7814 varop = XEXP (x, 0);
7816 varop = gen_lowpart_for_combine (mode, varop);
7818 /* If we can't make the SUBREG, try to return what we were given. */
7819 if (GET_CODE (varop) == CLOBBER)
7820 return x ? x : varop;
7822 /* If we are only masking insignificant bits, return VAROP. */
7823 if (constop == nonzero)
7827 /* Otherwise, return an AND. */
7828 constop = trunc_int_for_mode (constop, mode);
7829 /* See how much, if any, of X we can use. */
7830 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7831 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7835 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7836 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7837 SUBST (XEXP (x, 1), GEN_INT (constop));
7839 SUBST (XEXP (x, 0), varop);
7846 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7847 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7848 is less useful. We can't allow both, because that results in exponential
7849 run time recursion. There is a nullstone testcase that triggered
7850 this. This macro avoids accidental uses of num_sign_bit_copies. */
7851 #define num_sign_bit_copies()
7853 /* Given an expression, X, compute which bits in X can be non-zero.
7854 We don't care about bits outside of those defined in MODE.
7856 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7857 a shift, AND, or zero_extract, we can do better. */
7859 static unsigned HOST_WIDE_INT
7860 nonzero_bits (x, mode)
7862 enum machine_mode mode;
7864 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7865 unsigned HOST_WIDE_INT inner_nz;
7867 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7870 /* For floating-point values, assume all bits are needed. */
7871 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7874 /* If X is wider than MODE, use its mode instead. */
7875 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7877 mode = GET_MODE (x);
7878 nonzero = GET_MODE_MASK (mode);
7879 mode_width = GET_MODE_BITSIZE (mode);
7882 if (mode_width > HOST_BITS_PER_WIDE_INT)
7883 /* Our only callers in this case look for single bit values. So
7884 just return the mode mask. Those tests will then be false. */
7887 #ifndef WORD_REGISTER_OPERATIONS
7888 /* If MODE is wider than X, but both are a single word for both the host
7889 and target machines, we can compute this from which bits of the
7890 object might be nonzero in its own mode, taking into account the fact
7891 that on many CISC machines, accessing an object in a wider mode
7892 causes the high-order bits to become undefined. So they are
7893 not known to be zero. */
7895 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7896 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7897 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7898 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7900 nonzero &= nonzero_bits (x, GET_MODE (x));
7901 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7906 code = GET_CODE (x);
7910 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7911 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7912 all the bits above ptr_mode are known to be zero. */
7913 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7915 nonzero &= GET_MODE_MASK (ptr_mode);
7918 /* Include declared information about alignment of pointers. */
7919 /* ??? We don't properly preserve REG_POINTER changes across
7920 pointer-to-integer casts, so we can't trust it except for
7921 things that we know must be pointers. See execute/960116-1.c. */
7922 if ((x == stack_pointer_rtx
7923 || x == frame_pointer_rtx
7924 || x == arg_pointer_rtx)
7925 && REGNO_POINTER_ALIGN (REGNO (x)))
7927 unsigned HOST_WIDE_INT alignment
7928 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
7930 #ifdef PUSH_ROUNDING
7931 /* If PUSH_ROUNDING is defined, it is possible for the
7932 stack to be momentarily aligned only to that amount,
7933 so we pick the least alignment. */
7934 if (x == stack_pointer_rtx && PUSH_ARGS)
7935 alignment = MIN (PUSH_ROUNDING (1), alignment);
7938 nonzero &= ~(alignment - 1);
7941 /* If X is a register whose nonzero bits value is current, use it.
7942 Otherwise, if X is a register whose value we can find, use that
7943 value. Otherwise, use the previously-computed global nonzero bits
7944 for this register. */
7946 if (reg_last_set_value[REGNO (x)] != 0
7947 && reg_last_set_mode[REGNO (x)] == mode
7948 && (reg_last_set_label[REGNO (x)] == label_tick
7949 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7950 && REG_N_SETS (REGNO (x)) == 1
7951 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7953 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7954 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
7956 tem = get_last_value (x);
7960 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7961 /* If X is narrower than MODE and TEM is a non-negative
7962 constant that would appear negative in the mode of X,
7963 sign-extend it for use in reg_nonzero_bits because some
7964 machines (maybe most) will actually do the sign-extension
7965 and this is the conservative approach.
7967 ??? For 2.5, try to tighten up the MD files in this regard
7968 instead of this kludge. */
7970 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7971 && GET_CODE (tem) == CONST_INT
7973 && 0 != (INTVAL (tem)
7974 & ((HOST_WIDE_INT) 1
7975 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7976 tem = GEN_INT (INTVAL (tem)
7977 | ((HOST_WIDE_INT) (-1)
7978 << GET_MODE_BITSIZE (GET_MODE (x))));
7980 return nonzero_bits (tem, mode) & nonzero;
7982 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7984 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
7986 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
7987 /* We don't know anything about the upper bits. */
7988 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
7989 return nonzero & mask;
7995 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7996 /* If X is negative in MODE, sign-extend the value. */
7997 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7998 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7999 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8005 #ifdef LOAD_EXTEND_OP
8006 /* In many, if not most, RISC machines, reading a byte from memory
8007 zeros the rest of the register. Noticing that fact saves a lot
8008 of extra zero-extends. */
8009 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8010 nonzero &= GET_MODE_MASK (GET_MODE (x));
8015 case UNEQ: case LTGT:
8016 case GT: case GTU: case UNGT:
8017 case LT: case LTU: case UNLT:
8018 case GE: case GEU: case UNGE:
8019 case LE: case LEU: case UNLE:
8020 case UNORDERED: case ORDERED:
8022 /* If this produces an integer result, we know which bits are set.
8023 Code here used to clear bits outside the mode of X, but that is
8026 if (GET_MODE_CLASS (mode) == MODE_INT
8027 && mode_width <= HOST_BITS_PER_WIDE_INT)
8028 nonzero = STORE_FLAG_VALUE;
8033 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8034 and num_sign_bit_copies. */
8035 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8036 == GET_MODE_BITSIZE (GET_MODE (x)))
8040 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8041 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8046 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8047 and num_sign_bit_copies. */
8048 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8049 == GET_MODE_BITSIZE (GET_MODE (x)))
8055 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8059 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8060 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8061 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8065 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8066 Otherwise, show all the bits in the outer mode but not the inner
8068 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8069 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8071 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8073 & (((HOST_WIDE_INT) 1
8074 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8075 inner_nz |= (GET_MODE_MASK (mode)
8076 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8079 nonzero &= inner_nz;
8083 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8084 & nonzero_bits (XEXP (x, 1), mode));
8088 case UMIN: case UMAX: case SMIN: case SMAX:
8089 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8090 | nonzero_bits (XEXP (x, 1), mode));
8093 case PLUS: case MINUS:
8095 case DIV: case UDIV:
8096 case MOD: case UMOD:
8097 /* We can apply the rules of arithmetic to compute the number of
8098 high- and low-order zero bits of these operations. We start by
8099 computing the width (position of the highest-order non-zero bit)
8100 and the number of low-order zero bits for each value. */
8102 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8103 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8104 int width0 = floor_log2 (nz0) + 1;
8105 int width1 = floor_log2 (nz1) + 1;
8106 int low0 = floor_log2 (nz0 & -nz0);
8107 int low1 = floor_log2 (nz1 & -nz1);
8108 HOST_WIDE_INT op0_maybe_minusp
8109 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8110 HOST_WIDE_INT op1_maybe_minusp
8111 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8112 unsigned int result_width = mode_width;
8118 result_width = MAX (width0, width1) + 1;
8119 result_low = MIN (low0, low1);
8122 result_low = MIN (low0, low1);
8125 result_width = width0 + width1;
8126 result_low = low0 + low1;
8131 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8132 result_width = width0;
8137 result_width = width0;
8142 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8143 result_width = MIN (width0, width1);
8144 result_low = MIN (low0, low1);
8149 result_width = MIN (width0, width1);
8150 result_low = MIN (low0, low1);
8156 if (result_width < mode_width)
8157 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8160 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8162 #ifdef POINTERS_EXTEND_UNSIGNED
8163 /* If pointers extend unsigned and this is an addition or subtraction
8164 to a pointer in Pmode, all the bits above ptr_mode are known to be
8166 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8167 && (code == PLUS || code == MINUS)
8168 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8169 nonzero &= GET_MODE_MASK (ptr_mode);
8175 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8176 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8177 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8181 /* If this is a SUBREG formed for a promoted variable that has
8182 been zero-extended, we know that at least the high-order bits
8183 are zero, though others might be too. */
8185 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8186 nonzero = (GET_MODE_MASK (GET_MODE (x))
8187 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8189 /* If the inner mode is a single word for both the host and target
8190 machines, we can compute this from which bits of the inner
8191 object might be nonzero. */
8192 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8193 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8194 <= HOST_BITS_PER_WIDE_INT))
8196 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8198 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8199 /* If this is a typical RISC machine, we only have to worry
8200 about the way loads are extended. */
8201 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8203 & (((unsigned HOST_WIDE_INT) 1
8204 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8206 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8209 /* On many CISC machines, accessing an object in a wider mode
8210 causes the high-order bits to become undefined. So they are
8211 not known to be zero. */
8212 if (GET_MODE_SIZE (GET_MODE (x))
8213 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8214 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8215 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8224 /* The nonzero bits are in two classes: any bits within MODE
8225 that aren't in GET_MODE (x) are always significant. The rest of the
8226 nonzero bits are those that are significant in the operand of
8227 the shift when shifted the appropriate number of bits. This
8228 shows that high-order bits are cleared by the right shift and
8229 low-order bits by left shifts. */
8230 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8231 && INTVAL (XEXP (x, 1)) >= 0
8232 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8234 enum machine_mode inner_mode = GET_MODE (x);
8235 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8236 int count = INTVAL (XEXP (x, 1));
8237 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8238 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8239 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8240 unsigned HOST_WIDE_INT outer = 0;
8242 if (mode_width > width)
8243 outer = (op_nonzero & nonzero & ~mode_mask);
8245 if (code == LSHIFTRT)
8247 else if (code == ASHIFTRT)
8251 /* If the sign bit may have been nonzero before the shift, we
8252 need to mark all the places it could have been copied to
8253 by the shift as possibly nonzero. */
8254 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8255 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8257 else if (code == ASHIFT)
8260 inner = ((inner << (count % width)
8261 | (inner >> (width - (count % width)))) & mode_mask);
8263 nonzero &= (outer | inner);
8268 /* This is at most the number of bits in the mode. */
8269 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8273 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8274 | nonzero_bits (XEXP (x, 2), mode));
8284 /* See the macro definition above. */
8285 #undef num_sign_bit_copies
8287 /* Return the number of bits at the high-order end of X that are known to
8288 be equal to the sign bit. X will be used in mode MODE; if MODE is
8289 VOIDmode, X will be used in its own mode. The returned value will always
8290 be between 1 and the number of bits in MODE. */
8293 num_sign_bit_copies (x, mode)
8295 enum machine_mode mode;
8297 enum rtx_code code = GET_CODE (x);
8298 unsigned int bitwidth;
8299 int num0, num1, result;
8300 unsigned HOST_WIDE_INT nonzero;
8303 /* If we weren't given a mode, use the mode of X. If the mode is still
8304 VOIDmode, we don't know anything. Likewise if one of the modes is
8307 if (mode == VOIDmode)
8308 mode = GET_MODE (x);
8310 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8313 bitwidth = GET_MODE_BITSIZE (mode);
8315 /* For a smaller object, just ignore the high bits. */
8316 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8318 num0 = num_sign_bit_copies (x, GET_MODE (x));
8320 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8323 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8325 #ifndef WORD_REGISTER_OPERATIONS
8326 /* If this machine does not do all register operations on the entire
8327 register and MODE is wider than the mode of X, we can say nothing
8328 at all about the high-order bits. */
8331 /* Likewise on machines that do, if the mode of the object is smaller
8332 than a word and loads of that size don't sign extend, we can say
8333 nothing about the high order bits. */
8334 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8335 #ifdef LOAD_EXTEND_OP
8336 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8347 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8348 /* If pointers extend signed and this is a pointer in Pmode, say that
8349 all the bits above ptr_mode are known to be sign bit copies. */
8350 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8352 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8355 if (reg_last_set_value[REGNO (x)] != 0
8356 && reg_last_set_mode[REGNO (x)] == mode
8357 && (reg_last_set_label[REGNO (x)] == label_tick
8358 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8359 && REG_N_SETS (REGNO (x)) == 1
8360 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8362 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8363 return reg_last_set_sign_bit_copies[REGNO (x)];
8365 tem = get_last_value (x);
8367 return num_sign_bit_copies (tem, mode);
8369 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8370 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8371 return reg_sign_bit_copies[REGNO (x)];
8375 #ifdef LOAD_EXTEND_OP
8376 /* Some RISC machines sign-extend all loads of smaller than a word. */
8377 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8378 return MAX (1, ((int) bitwidth
8379 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8384 /* If the constant is negative, take its 1's complement and remask.
8385 Then see how many zero bits we have. */
8386 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8387 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8388 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8389 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8391 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8394 /* If this is a SUBREG for a promoted object that is sign-extended
8395 and we are looking at it in a wider mode, we know that at least the
8396 high-order bits are known to be sign bit copies. */
8398 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8400 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8401 return MAX ((int) bitwidth
8402 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8406 /* For a smaller object, just ignore the high bits. */
8407 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8409 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8410 return MAX (1, (num0
8411 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8415 #ifdef WORD_REGISTER_OPERATIONS
8416 #ifdef LOAD_EXTEND_OP
8417 /* For paradoxical SUBREGs on machines where all register operations
8418 affect the entire register, just look inside. Note that we are
8419 passing MODE to the recursive call, so the number of sign bit copies
8420 will remain relative to that mode, not the inner mode. */
8422 /* This works only if loads sign extend. Otherwise, if we get a
8423 reload for the inner part, it may be loaded from the stack, and
8424 then we lose all sign bit copies that existed before the store
8427 if ((GET_MODE_SIZE (GET_MODE (x))
8428 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8429 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8430 return num_sign_bit_copies (SUBREG_REG (x), mode);
8436 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8437 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8441 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8442 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8445 /* For a smaller object, just ignore the high bits. */
8446 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8447 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8451 return num_sign_bit_copies (XEXP (x, 0), mode);
8453 case ROTATE: case ROTATERT:
8454 /* If we are rotating left by a number of bits less than the number
8455 of sign bit copies, we can just subtract that amount from the
8457 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8458 && INTVAL (XEXP (x, 1)) >= 0
8459 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8461 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8462 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8463 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8468 /* In general, this subtracts one sign bit copy. But if the value
8469 is known to be positive, the number of sign bit copies is the
8470 same as that of the input. Finally, if the input has just one bit
8471 that might be nonzero, all the bits are copies of the sign bit. */
8472 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8473 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8474 return num0 > 1 ? num0 - 1 : 1;
8476 nonzero = nonzero_bits (XEXP (x, 0), mode);
8481 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8486 case IOR: case AND: case XOR:
8487 case SMIN: case SMAX: case UMIN: case UMAX:
8488 /* Logical operations will preserve the number of sign-bit copies.
8489 MIN and MAX operations always return one of the operands. */
8490 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8491 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8492 return MIN (num0, num1);
8494 case PLUS: case MINUS:
8495 /* For addition and subtraction, we can have a 1-bit carry. However,
8496 if we are subtracting 1 from a positive number, there will not
8497 be such a carry. Furthermore, if the positive number is known to
8498 be 0 or 1, we know the result is either -1 or 0. */
8500 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8501 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8503 nonzero = nonzero_bits (XEXP (x, 0), mode);
8504 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8505 return (nonzero == 1 || nonzero == 0 ? bitwidth
8506 : bitwidth - floor_log2 (nonzero) - 1);
8509 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8510 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8511 result = MAX (1, MIN (num0, num1) - 1);
8513 #ifdef POINTERS_EXTEND_UNSIGNED
8514 /* If pointers extend signed and this is an addition or subtraction
8515 to a pointer in Pmode, all the bits above ptr_mode are known to be
8517 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8518 && (code == PLUS || code == MINUS)
8519 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8520 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8521 - GET_MODE_BITSIZE (ptr_mode) + 1),
8527 /* The number of bits of the product is the sum of the number of
8528 bits of both terms. However, unless one of the terms if known
8529 to be positive, we must allow for an additional bit since negating
8530 a negative number can remove one sign bit copy. */
8532 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8533 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8535 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8537 && (bitwidth > HOST_BITS_PER_WIDE_INT
8538 || (((nonzero_bits (XEXP (x, 0), mode)
8539 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8540 && ((nonzero_bits (XEXP (x, 1), mode)
8541 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8544 return MAX (1, result);
8547 /* The result must be <= the first operand. If the first operand
8548 has the high bit set, we know nothing about the number of sign
8550 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8552 else if ((nonzero_bits (XEXP (x, 0), mode)
8553 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8556 return num_sign_bit_copies (XEXP (x, 0), mode);
8559 /* The result must be <= the second operand. */
8560 return num_sign_bit_copies (XEXP (x, 1), mode);
8563 /* Similar to unsigned division, except that we have to worry about
8564 the case where the divisor is negative, in which case we have
8566 result = num_sign_bit_copies (XEXP (x, 0), mode);
8568 && (bitwidth > HOST_BITS_PER_WIDE_INT
8569 || (nonzero_bits (XEXP (x, 1), mode)
8570 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8576 result = num_sign_bit_copies (XEXP (x, 1), mode);
8578 && (bitwidth > HOST_BITS_PER_WIDE_INT
8579 || (nonzero_bits (XEXP (x, 1), mode)
8580 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8586 /* Shifts by a constant add to the number of bits equal to the
8588 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8589 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8590 && INTVAL (XEXP (x, 1)) > 0)
8591 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8596 /* Left shifts destroy copies. */
8597 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8598 || INTVAL (XEXP (x, 1)) < 0
8599 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8602 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8603 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8606 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8607 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8608 return MIN (num0, num1);
8610 case EQ: case NE: case GE: case GT: case LE: case LT:
8611 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8612 case GEU: case GTU: case LEU: case LTU:
8613 case UNORDERED: case ORDERED:
8614 /* If the constant is negative, take its 1's complement and remask.
8615 Then see how many zero bits we have. */
8616 nonzero = STORE_FLAG_VALUE;
8617 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8618 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8619 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8621 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8628 /* If we haven't been able to figure it out by one of the above rules,
8629 see if some of the high-order bits are known to be zero. If so,
8630 count those bits and return one less than that amount. If we can't
8631 safely compute the mask for this mode, always return BITWIDTH. */
8633 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8636 nonzero = nonzero_bits (x, mode);
8637 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8638 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8641 /* Return the number of "extended" bits there are in X, when interpreted
8642 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8643 unsigned quantities, this is the number of high-order zero bits.
8644 For signed quantities, this is the number of copies of the sign bit
8645 minus 1. In both case, this function returns the number of "spare"
8646 bits. For example, if two quantities for which this function returns
8647 at least 1 are added, the addition is known not to overflow.
8649 This function will always return 0 unless called during combine, which
8650 implies that it must be called from a define_split. */
8653 extended_count (x, mode, unsignedp)
8655 enum machine_mode mode;
8658 if (nonzero_sign_valid == 0)
8662 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8663 ? (GET_MODE_BITSIZE (mode) - 1
8664 - floor_log2 (nonzero_bits (x, mode)))
8666 : num_sign_bit_copies (x, mode) - 1);
8669 /* This function is called from `simplify_shift_const' to merge two
8670 outer operations. Specifically, we have already found that we need
8671 to perform operation *POP0 with constant *PCONST0 at the outermost
8672 position. We would now like to also perform OP1 with constant CONST1
8673 (with *POP0 being done last).
8675 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8676 the resulting operation. *PCOMP_P is set to 1 if we would need to
8677 complement the innermost operand, otherwise it is unchanged.
8679 MODE is the mode in which the operation will be done. No bits outside
8680 the width of this mode matter. It is assumed that the width of this mode
8681 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8683 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8684 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8685 result is simply *PCONST0.
8687 If the resulting operation cannot be expressed as one operation, we
8688 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8691 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8692 enum rtx_code *pop0;
8693 HOST_WIDE_INT *pconst0;
8695 HOST_WIDE_INT const1;
8696 enum machine_mode mode;
8699 enum rtx_code op0 = *pop0;
8700 HOST_WIDE_INT const0 = *pconst0;
8702 const0 &= GET_MODE_MASK (mode);
8703 const1 &= GET_MODE_MASK (mode);
8705 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8709 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8712 if (op1 == NIL || op0 == SET)
8715 else if (op0 == NIL)
8716 op0 = op1, const0 = const1;
8718 else if (op0 == op1)
8742 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8743 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8746 /* If the two constants aren't the same, we can't do anything. The
8747 remaining six cases can all be done. */
8748 else if (const0 != const1)
8756 /* (a & b) | b == b */
8758 else /* op1 == XOR */
8759 /* (a ^ b) | b == a | b */
8765 /* (a & b) ^ b == (~a) & b */
8766 op0 = AND, *pcomp_p = 1;
8767 else /* op1 == IOR */
8768 /* (a | b) ^ b == a & ~b */
8769 op0 = AND, *pconst0 = ~const0;
8774 /* (a | b) & b == b */
8776 else /* op1 == XOR */
8777 /* (a ^ b) & b) == (~a) & b */
8784 /* Check for NO-OP cases. */
8785 const0 &= GET_MODE_MASK (mode);
8787 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8789 else if (const0 == 0 && op0 == AND)
8791 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8795 /* ??? Slightly redundant with the above mask, but not entirely.
8796 Moving this above means we'd have to sign-extend the mode mask
8797 for the final test. */
8798 const0 = trunc_int_for_mode (const0, mode);
8806 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8807 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8808 that we started with.
8810 The shift is normally computed in the widest mode we find in VAROP, as
8811 long as it isn't a different number of words than RESULT_MODE. Exceptions
8812 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8815 simplify_shift_const (x, code, result_mode, varop, orig_count)
8818 enum machine_mode result_mode;
8822 enum rtx_code orig_code = code;
8825 enum machine_mode mode = result_mode;
8826 enum machine_mode shift_mode, tmode;
8827 unsigned int mode_words
8828 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8829 /* We form (outer_op (code varop count) (outer_const)). */
8830 enum rtx_code outer_op = NIL;
8831 HOST_WIDE_INT outer_const = 0;
8833 int complement_p = 0;
8836 /* Make sure and truncate the "natural" shift on the way in. We don't
8837 want to do this inside the loop as it makes it more difficult to
8839 #ifdef SHIFT_COUNT_TRUNCATED
8840 if (SHIFT_COUNT_TRUNCATED)
8841 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8844 /* If we were given an invalid count, don't do anything except exactly
8845 what was requested. */
8847 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8852 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8857 /* Unless one of the branches of the `if' in this loop does a `continue',
8858 we will `break' the loop after the `if'. */
8862 /* If we have an operand of (clobber (const_int 0)), just return that
8864 if (GET_CODE (varop) == CLOBBER)
8867 /* If we discovered we had to complement VAROP, leave. Making a NOT
8868 here would cause an infinite loop. */
8872 /* Convert ROTATERT to ROTATE. */
8873 if (code == ROTATERT)
8874 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8876 /* We need to determine what mode we will do the shift in. If the
8877 shift is a right shift or a ROTATE, we must always do it in the mode
8878 it was originally done in. Otherwise, we can do it in MODE, the
8879 widest mode encountered. */
8881 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8882 ? result_mode : mode);
8884 /* Handle cases where the count is greater than the size of the mode
8885 minus 1. For ASHIFT, use the size minus one as the count (this can
8886 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8887 take the count modulo the size. For other shifts, the result is
8890 Since these shifts are being produced by the compiler by combining
8891 multiple operations, each of which are defined, we know what the
8892 result is supposed to be. */
8894 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8896 if (code == ASHIFTRT)
8897 count = GET_MODE_BITSIZE (shift_mode) - 1;
8898 else if (code == ROTATE || code == ROTATERT)
8899 count %= GET_MODE_BITSIZE (shift_mode);
8902 /* We can't simply return zero because there may be an
8910 /* An arithmetic right shift of a quantity known to be -1 or 0
8912 if (code == ASHIFTRT
8913 && (num_sign_bit_copies (varop, shift_mode)
8914 == GET_MODE_BITSIZE (shift_mode)))
8920 /* If we are doing an arithmetic right shift and discarding all but
8921 the sign bit copies, this is equivalent to doing a shift by the
8922 bitsize minus one. Convert it into that shift because it will often
8923 allow other simplifications. */
8925 if (code == ASHIFTRT
8926 && (count + num_sign_bit_copies (varop, shift_mode)
8927 >= GET_MODE_BITSIZE (shift_mode)))
8928 count = GET_MODE_BITSIZE (shift_mode) - 1;
8930 /* We simplify the tests below and elsewhere by converting
8931 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8932 `make_compound_operation' will convert it to a ASHIFTRT for
8933 those machines (such as VAX) that don't have a LSHIFTRT. */
8934 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8936 && ((nonzero_bits (varop, shift_mode)
8937 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8941 switch (GET_CODE (varop))
8947 new = expand_compound_operation (varop);
8956 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8957 minus the width of a smaller mode, we can do this with a
8958 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8959 if ((code == ASHIFTRT || code == LSHIFTRT)
8960 && ! mode_dependent_address_p (XEXP (varop, 0))
8961 && ! MEM_VOLATILE_P (varop)
8962 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8963 MODE_INT, 1)) != BLKmode)
8965 new = adjust_address_nv (varop, tmode,
8966 BYTES_BIG_ENDIAN ? 0
8967 : count / BITS_PER_UNIT);
8969 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8970 : ZERO_EXTEND, mode, new);
8977 /* Similar to the case above, except that we can only do this if
8978 the resulting mode is the same as that of the underlying
8979 MEM and adjust the address depending on the *bits* endianness
8980 because of the way that bit-field extract insns are defined. */
8981 if ((code == ASHIFTRT || code == LSHIFTRT)
8982 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8983 MODE_INT, 1)) != BLKmode
8984 && tmode == GET_MODE (XEXP (varop, 0)))
8986 if (BITS_BIG_ENDIAN)
8987 new = XEXP (varop, 0);
8990 new = copy_rtx (XEXP (varop, 0));
8991 SUBST (XEXP (new, 0),
8992 plus_constant (XEXP (new, 0),
8993 count / BITS_PER_UNIT));
8996 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8997 : ZERO_EXTEND, mode, new);
9004 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9005 the same number of words as what we've seen so far. Then store
9006 the widest mode in MODE. */
9007 if (subreg_lowpart_p (varop)
9008 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9009 > GET_MODE_SIZE (GET_MODE (varop)))
9010 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9011 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9014 varop = SUBREG_REG (varop);
9015 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9016 mode = GET_MODE (varop);
9022 /* Some machines use MULT instead of ASHIFT because MULT
9023 is cheaper. But it is still better on those machines to
9024 merge two shifts into one. */
9025 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9026 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9029 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9030 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9036 /* Similar, for when divides are cheaper. */
9037 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9038 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9041 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9042 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9048 /* If we are extracting just the sign bit of an arithmetic
9049 right shift, that shift is not needed. However, the sign
9050 bit of a wider mode may be different from what would be
9051 interpreted as the sign bit in a narrower mode, so, if
9052 the result is narrower, don't discard the shift. */
9053 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9054 && (GET_MODE_BITSIZE (result_mode)
9055 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9057 varop = XEXP (varop, 0);
9061 /* ... fall through ... */
9066 /* Here we have two nested shifts. The result is usually the
9067 AND of a new shift with a mask. We compute the result below. */
9068 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9069 && INTVAL (XEXP (varop, 1)) >= 0
9070 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9071 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9072 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9074 enum rtx_code first_code = GET_CODE (varop);
9075 unsigned int first_count = INTVAL (XEXP (varop, 1));
9076 unsigned HOST_WIDE_INT mask;
9079 /* We have one common special case. We can't do any merging if
9080 the inner code is an ASHIFTRT of a smaller mode. However, if
9081 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9082 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9083 we can convert it to
9084 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9085 This simplifies certain SIGN_EXTEND operations. */
9086 if (code == ASHIFT && first_code == ASHIFTRT
9087 && (GET_MODE_BITSIZE (result_mode)
9088 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9090 /* C3 has the low-order C1 bits zero. */
9092 mask = (GET_MODE_MASK (mode)
9093 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9095 varop = simplify_and_const_int (NULL_RTX, result_mode,
9096 XEXP (varop, 0), mask);
9097 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9099 count = first_count;
9104 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9105 than C1 high-order bits equal to the sign bit, we can convert
9106 this to either an ASHIFT or a ASHIFTRT depending on the
9109 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9111 if (code == ASHIFTRT && first_code == ASHIFT
9112 && GET_MODE (varop) == shift_mode
9113 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9116 varop = XEXP (varop, 0);
9118 signed_count = count - first_count;
9119 if (signed_count < 0)
9120 count = -signed_count, code = ASHIFT;
9122 count = signed_count;
9127 /* There are some cases we can't do. If CODE is ASHIFTRT,
9128 we can only do this if FIRST_CODE is also ASHIFTRT.
9130 We can't do the case when CODE is ROTATE and FIRST_CODE is
9133 If the mode of this shift is not the mode of the outer shift,
9134 we can't do this if either shift is a right shift or ROTATE.
9136 Finally, we can't do any of these if the mode is too wide
9137 unless the codes are the same.
9139 Handle the case where the shift codes are the same
9142 if (code == first_code)
9144 if (GET_MODE (varop) != result_mode
9145 && (code == ASHIFTRT || code == LSHIFTRT
9149 count += first_count;
9150 varop = XEXP (varop, 0);
9154 if (code == ASHIFTRT
9155 || (code == ROTATE && first_code == ASHIFTRT)
9156 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9157 || (GET_MODE (varop) != result_mode
9158 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9159 || first_code == ROTATE
9160 || code == ROTATE)))
9163 /* To compute the mask to apply after the shift, shift the
9164 nonzero bits of the inner shift the same way the
9165 outer shift will. */
9167 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9170 = simplify_binary_operation (code, result_mode, mask_rtx,
9173 /* Give up if we can't compute an outer operation to use. */
9175 || GET_CODE (mask_rtx) != CONST_INT
9176 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9178 result_mode, &complement_p))
9181 /* If the shifts are in the same direction, we add the
9182 counts. Otherwise, we subtract them. */
9183 signed_count = count;
9184 if ((code == ASHIFTRT || code == LSHIFTRT)
9185 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9186 signed_count += first_count;
9188 signed_count -= first_count;
9190 /* If COUNT is positive, the new shift is usually CODE,
9191 except for the two exceptions below, in which case it is
9192 FIRST_CODE. If the count is negative, FIRST_CODE should
9194 if (signed_count > 0
9195 && ((first_code == ROTATE && code == ASHIFT)
9196 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9197 code = first_code, count = signed_count;
9198 else if (signed_count < 0)
9199 code = first_code, count = -signed_count;
9201 count = signed_count;
9203 varop = XEXP (varop, 0);
9207 /* If we have (A << B << C) for any shift, we can convert this to
9208 (A << C << B). This wins if A is a constant. Only try this if
9209 B is not a constant. */
9211 else if (GET_CODE (varop) == code
9212 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9214 = simplify_binary_operation (code, mode,
9218 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9225 /* Make this fit the case below. */
9226 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9227 GEN_INT (GET_MODE_MASK (mode)));
9233 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9234 with C the size of VAROP - 1 and the shift is logical if
9235 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9236 we have an (le X 0) operation. If we have an arithmetic shift
9237 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9238 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9240 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9241 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9242 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9243 && (code == LSHIFTRT || code == ASHIFTRT)
9244 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9245 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9248 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9251 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9252 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9257 /* If we have (shift (logical)), move the logical to the outside
9258 to allow it to possibly combine with another logical and the
9259 shift to combine with another shift. This also canonicalizes to
9260 what a ZERO_EXTRACT looks like. Also, some machines have
9261 (and (shift)) insns. */
9263 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9264 && (new = simplify_binary_operation (code, result_mode,
9266 GEN_INT (count))) != 0
9267 && GET_CODE (new) == CONST_INT
9268 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9269 INTVAL (new), result_mode, &complement_p))
9271 varop = XEXP (varop, 0);
9275 /* If we can't do that, try to simplify the shift in each arm of the
9276 logical expression, make a new logical expression, and apply
9277 the inverse distributive law. */
9279 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9280 XEXP (varop, 0), count);
9281 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9282 XEXP (varop, 1), count);
9284 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9285 varop = apply_distributive_law (varop);
9292 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9293 says that the sign bit can be tested, FOO has mode MODE, C is
9294 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9295 that may be nonzero. */
9296 if (code == LSHIFTRT
9297 && XEXP (varop, 1) == const0_rtx
9298 && GET_MODE (XEXP (varop, 0)) == result_mode
9299 && count == GET_MODE_BITSIZE (result_mode) - 1
9300 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9301 && ((STORE_FLAG_VALUE
9302 & ((HOST_WIDE_INT) 1
9303 < (GET_MODE_BITSIZE (result_mode) - 1))))
9304 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9305 && merge_outer_ops (&outer_op, &outer_const, XOR,
9306 (HOST_WIDE_INT) 1, result_mode,
9309 varop = XEXP (varop, 0);
9316 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9317 than the number of bits in the mode is equivalent to A. */
9318 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9319 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9321 varop = XEXP (varop, 0);
9326 /* NEG commutes with ASHIFT since it is multiplication. Move the
9327 NEG outside to allow shifts to combine. */
9329 && merge_outer_ops (&outer_op, &outer_const, NEG,
9330 (HOST_WIDE_INT) 0, result_mode,
9333 varop = XEXP (varop, 0);
9339 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9340 is one less than the number of bits in the mode is
9341 equivalent to (xor A 1). */
9342 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9343 && XEXP (varop, 1) == constm1_rtx
9344 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9345 && merge_outer_ops (&outer_op, &outer_const, XOR,
9346 (HOST_WIDE_INT) 1, result_mode,
9350 varop = XEXP (varop, 0);
9354 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9355 that might be nonzero in BAR are those being shifted out and those
9356 bits are known zero in FOO, we can replace the PLUS with FOO.
9357 Similarly in the other operand order. This code occurs when
9358 we are computing the size of a variable-size array. */
9360 if ((code == ASHIFTRT || code == LSHIFTRT)
9361 && count < HOST_BITS_PER_WIDE_INT
9362 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9363 && (nonzero_bits (XEXP (varop, 1), result_mode)
9364 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9366 varop = XEXP (varop, 0);
9369 else if ((code == ASHIFTRT || code == LSHIFTRT)
9370 && count < HOST_BITS_PER_WIDE_INT
9371 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9372 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9374 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9375 & nonzero_bits (XEXP (varop, 1),
9378 varop = XEXP (varop, 1);
9382 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9384 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9385 && (new = simplify_binary_operation (ASHIFT, result_mode,
9387 GEN_INT (count))) != 0
9388 && GET_CODE (new) == CONST_INT
9389 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9390 INTVAL (new), result_mode, &complement_p))
9392 varop = XEXP (varop, 0);
9398 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9399 with C the size of VAROP - 1 and the shift is logical if
9400 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9401 we have a (gt X 0) operation. If the shift is arithmetic with
9402 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9403 we have a (neg (gt X 0)) operation. */
9405 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9406 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9407 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9408 && (code == LSHIFTRT || code == ASHIFTRT)
9409 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9410 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9411 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9414 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9417 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9418 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9425 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9426 if the truncate does not affect the value. */
9427 if (code == LSHIFTRT
9428 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9429 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9430 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9431 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9432 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9434 rtx varop_inner = XEXP (varop, 0);
9437 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9438 XEXP (varop_inner, 0),
9440 (count + INTVAL (XEXP (varop_inner, 1))));
9441 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9454 /* We need to determine what mode to do the shift in. If the shift is
9455 a right shift or ROTATE, we must always do it in the mode it was
9456 originally done in. Otherwise, we can do it in MODE, the widest mode
9457 encountered. The code we care about is that of the shift that will
9458 actually be done, not the shift that was originally requested. */
9460 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9461 ? result_mode : mode);
9463 /* We have now finished analyzing the shift. The result should be
9464 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9465 OUTER_OP is non-NIL, it is an operation that needs to be applied
9466 to the result of the shift. OUTER_CONST is the relevant constant,
9467 but we must turn off all bits turned off in the shift.
9469 If we were passed a value for X, see if we can use any pieces of
9470 it. If not, make new rtx. */
9472 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9473 && GET_CODE (XEXP (x, 1)) == CONST_INT
9474 && INTVAL (XEXP (x, 1)) == count)
9475 const_rtx = XEXP (x, 1);
9477 const_rtx = GEN_INT (count);
9479 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9480 && GET_MODE (XEXP (x, 0)) == shift_mode
9481 && SUBREG_REG (XEXP (x, 0)) == varop)
9482 varop = XEXP (x, 0);
9483 else if (GET_MODE (varop) != shift_mode)
9484 varop = gen_lowpart_for_combine (shift_mode, varop);
9486 /* If we can't make the SUBREG, try to return what we were given. */
9487 if (GET_CODE (varop) == CLOBBER)
9488 return x ? x : varop;
9490 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9494 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9496 /* If we have an outer operation and we just made a shift, it is
9497 possible that we could have simplified the shift were it not
9498 for the outer operation. So try to do the simplification
9501 if (outer_op != NIL && GET_CODE (x) == code
9502 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9503 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9504 INTVAL (XEXP (x, 1)));
9506 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9507 turn off all the bits that the shift would have turned off. */
9508 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9509 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9510 GET_MODE_MASK (result_mode) >> orig_count);
9512 /* Do the remainder of the processing in RESULT_MODE. */
9513 x = gen_lowpart_for_combine (result_mode, x);
9515 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9518 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9520 if (outer_op != NIL)
9522 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9523 outer_const = trunc_int_for_mode (outer_const, result_mode);
9525 if (outer_op == AND)
9526 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9527 else if (outer_op == SET)
9528 /* This means that we have determined that the result is
9529 equivalent to a constant. This should be rare. */
9530 x = GEN_INT (outer_const);
9531 else if (GET_RTX_CLASS (outer_op) == '1')
9532 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9534 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9540 /* Like recog, but we receive the address of a pointer to a new pattern.
9541 We try to match the rtx that the pointer points to.
9542 If that fails, we may try to modify or replace the pattern,
9543 storing the replacement into the same pointer object.
9545 Modifications include deletion or addition of CLOBBERs.
9547 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9548 the CLOBBERs are placed.
9550 The value is the final insn code from the pattern ultimately matched,
9554 recog_for_combine (pnewpat, insn, pnotes)
9560 int insn_code_number;
9561 int num_clobbers_to_add = 0;
9566 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9567 we use to indicate that something didn't match. If we find such a
9568 thing, force rejection. */
9569 if (GET_CODE (pat) == PARALLEL)
9570 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9571 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9572 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9575 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9576 instruction for pattern recognition. */
9577 dummy_insn = shallow_copy_rtx (insn);
9578 PATTERN (dummy_insn) = pat;
9579 REG_NOTES (dummy_insn) = 0;
9581 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9583 /* If it isn't, there is the possibility that we previously had an insn
9584 that clobbered some register as a side effect, but the combined
9585 insn doesn't need to do that. So try once more without the clobbers
9586 unless this represents an ASM insn. */
9588 if (insn_code_number < 0 && ! check_asm_operands (pat)
9589 && GET_CODE (pat) == PARALLEL)
9593 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9594 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9597 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9601 SUBST_INT (XVECLEN (pat, 0), pos);
9604 pat = XVECEXP (pat, 0, 0);
9606 PATTERN (dummy_insn) = pat;
9607 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9610 /* Recognize all noop sets, these will be killed by followup pass. */
9611 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9612 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9614 /* If we had any clobbers to add, make a new pattern than contains
9615 them. Then check to make sure that all of them are dead. */
9616 if (num_clobbers_to_add)
9618 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9619 rtvec_alloc (GET_CODE (pat) == PARALLEL
9621 + num_clobbers_to_add)
9622 : num_clobbers_to_add + 1));
9624 if (GET_CODE (pat) == PARALLEL)
9625 for (i = 0; i < XVECLEN (pat, 0); i++)
9626 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9628 XVECEXP (newpat, 0, 0) = pat;
9630 add_clobbers (newpat, insn_code_number);
9632 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9633 i < XVECLEN (newpat, 0); i++)
9635 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9636 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9638 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9639 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9647 return insn_code_number;
9650 /* Like gen_lowpart but for use by combine. In combine it is not possible
9651 to create any new pseudoregs. However, it is safe to create
9652 invalid memory addresses, because combine will try to recognize
9653 them and all they will do is make the combine attempt fail.
9655 If for some reason this cannot do its job, an rtx
9656 (clobber (const_int 0)) is returned.
9657 An insn containing that will not be recognized. */
9662 gen_lowpart_for_combine (mode, x)
9663 enum machine_mode mode;
9668 if (GET_MODE (x) == mode)
9671 /* We can only support MODE being wider than a word if X is a
9672 constant integer or has a mode the same size. */
9674 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9675 && ! ((GET_MODE (x) == VOIDmode
9676 && (GET_CODE (x) == CONST_INT
9677 || GET_CODE (x) == CONST_DOUBLE))
9678 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9679 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9681 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9682 won't know what to do. So we will strip off the SUBREG here and
9683 process normally. */
9684 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9687 if (GET_MODE (x) == mode)
9691 result = gen_lowpart_common (mode, x);
9692 #ifdef CLASS_CANNOT_CHANGE_MODE
9694 && GET_CODE (result) == SUBREG
9695 && GET_CODE (SUBREG_REG (result)) == REG
9696 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9697 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9698 GET_MODE (SUBREG_REG (result))))
9699 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9705 if (GET_CODE (x) == MEM)
9709 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9711 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9712 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9714 /* If we want to refer to something bigger than the original memref,
9715 generate a perverse subreg instead. That will force a reload
9716 of the original memref X. */
9717 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9718 return gen_rtx_SUBREG (mode, x, 0);
9720 if (WORDS_BIG_ENDIAN)
9721 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9722 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9724 if (BYTES_BIG_ENDIAN)
9726 /* Adjust the address so that the address-after-the-data is
9728 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9729 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9732 return adjust_address_nv (x, mode, offset);
9735 /* If X is a comparison operator, rewrite it in a new mode. This
9736 probably won't match, but may allow further simplifications. */
9737 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9738 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9740 /* If we couldn't simplify X any other way, just enclose it in a
9741 SUBREG. Normally, this SUBREG won't match, but some patterns may
9742 include an explicit SUBREG or we may simplify it further in combine. */
9748 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9749 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9752 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9756 /* These routines make binary and unary operations by first seeing if they
9757 fold; if not, a new expression is allocated. */
9760 gen_binary (code, mode, op0, op1)
9762 enum machine_mode mode;
9768 if (GET_RTX_CLASS (code) == 'c'
9769 && swap_commutative_operands_p (op0, op1))
9770 tem = op0, op0 = op1, op1 = tem;
9772 if (GET_RTX_CLASS (code) == '<')
9774 enum machine_mode op_mode = GET_MODE (op0);
9776 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9777 just (REL_OP X Y). */
9778 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9780 op1 = XEXP (op0, 1);
9781 op0 = XEXP (op0, 0);
9782 op_mode = GET_MODE (op0);
9785 if (op_mode == VOIDmode)
9786 op_mode = GET_MODE (op1);
9787 result = simplify_relational_operation (code, op_mode, op0, op1);
9790 result = simplify_binary_operation (code, mode, op0, op1);
9795 /* Put complex operands first and constants second. */
9796 if (GET_RTX_CLASS (code) == 'c'
9797 && swap_commutative_operands_p (op0, op1))
9798 return gen_rtx_fmt_ee (code, mode, op1, op0);
9800 /* If we are turning off bits already known off in OP0, we need not do
9802 else if (code == AND && GET_CODE (op1) == CONST_INT
9803 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9804 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9807 return gen_rtx_fmt_ee (code, mode, op0, op1);
9810 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9811 comparison code that will be tested.
9813 The result is a possibly different comparison code to use. *POP0 and
9814 *POP1 may be updated.
9816 It is possible that we might detect that a comparison is either always
9817 true or always false. However, we do not perform general constant
9818 folding in combine, so this knowledge isn't useful. Such tautologies
9819 should have been detected earlier. Hence we ignore all such cases. */
9821 static enum rtx_code
9822 simplify_comparison (code, pop0, pop1)
9831 enum machine_mode mode, tmode;
9833 /* Try a few ways of applying the same transformation to both operands. */
9836 #ifndef WORD_REGISTER_OPERATIONS
9837 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9838 so check specially. */
9839 if (code != GTU && code != GEU && code != LTU && code != LEU
9840 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9841 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9842 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9843 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9844 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9845 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9846 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9847 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9848 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9849 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9850 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9851 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9852 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9853 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9854 && (INTVAL (XEXP (op0, 1))
9855 == (GET_MODE_BITSIZE (GET_MODE (op0))
9857 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9859 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9860 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9864 /* If both operands are the same constant shift, see if we can ignore the
9865 shift. We can if the shift is a rotate or if the bits shifted out of
9866 this shift are known to be zero for both inputs and if the type of
9867 comparison is compatible with the shift. */
9868 if (GET_CODE (op0) == GET_CODE (op1)
9869 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9870 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9871 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9872 && (code != GT && code != LT && code != GE && code != LE))
9873 || (GET_CODE (op0) == ASHIFTRT
9874 && (code != GTU && code != LTU
9875 && code != GEU && code != LEU)))
9876 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9877 && INTVAL (XEXP (op0, 1)) >= 0
9878 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9879 && XEXP (op0, 1) == XEXP (op1, 1))
9881 enum machine_mode mode = GET_MODE (op0);
9882 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9883 int shift_count = INTVAL (XEXP (op0, 1));
9885 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9886 mask &= (mask >> shift_count) << shift_count;
9887 else if (GET_CODE (op0) == ASHIFT)
9888 mask = (mask & (mask << shift_count)) >> shift_count;
9890 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9891 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9892 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9897 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9898 SUBREGs are of the same mode, and, in both cases, the AND would
9899 be redundant if the comparison was done in the narrower mode,
9900 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9901 and the operand's possibly nonzero bits are 0xffffff01; in that case
9902 if we only care about QImode, we don't need the AND). This case
9903 occurs if the output mode of an scc insn is not SImode and
9904 STORE_FLAG_VALUE == 1 (e.g., the 386).
9906 Similarly, check for a case where the AND's are ZERO_EXTEND
9907 operations from some narrower mode even though a SUBREG is not
9910 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9911 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9912 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9914 rtx inner_op0 = XEXP (op0, 0);
9915 rtx inner_op1 = XEXP (op1, 0);
9916 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9917 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9920 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9921 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9922 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9923 && (GET_MODE (SUBREG_REG (inner_op0))
9924 == GET_MODE (SUBREG_REG (inner_op1)))
9925 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9926 <= HOST_BITS_PER_WIDE_INT)
9927 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9928 GET_MODE (SUBREG_REG (inner_op0)))))
9929 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9930 GET_MODE (SUBREG_REG (inner_op1))))))
9932 op0 = SUBREG_REG (inner_op0);
9933 op1 = SUBREG_REG (inner_op1);
9935 /* The resulting comparison is always unsigned since we masked
9936 off the original sign bit. */
9937 code = unsigned_condition (code);
9943 for (tmode = GET_CLASS_NARROWEST_MODE
9944 (GET_MODE_CLASS (GET_MODE (op0)));
9945 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9946 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9948 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9949 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9950 code = unsigned_condition (code);
9959 /* If both operands are NOT, we can strip off the outer operation
9960 and adjust the comparison code for swapped operands; similarly for
9961 NEG, except that this must be an equality comparison. */
9962 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9963 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9964 && (code == EQ || code == NE)))
9965 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9971 /* If the first operand is a constant, swap the operands and adjust the
9972 comparison code appropriately, but don't do this if the second operand
9973 is already a constant integer. */
9974 if (swap_commutative_operands_p (op0, op1))
9976 tem = op0, op0 = op1, op1 = tem;
9977 code = swap_condition (code);
9980 /* We now enter a loop during which we will try to simplify the comparison.
9981 For the most part, we only are concerned with comparisons with zero,
9982 but some things may really be comparisons with zero but not start
9983 out looking that way. */
9985 while (GET_CODE (op1) == CONST_INT)
9987 enum machine_mode mode = GET_MODE (op0);
9988 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9989 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9990 int equality_comparison_p;
9991 int sign_bit_comparison_p;
9992 int unsigned_comparison_p;
9993 HOST_WIDE_INT const_op;
9995 /* We only want to handle integral modes. This catches VOIDmode,
9996 CCmode, and the floating-point modes. An exception is that we
9997 can handle VOIDmode if OP0 is a COMPARE or a comparison
10000 if (GET_MODE_CLASS (mode) != MODE_INT
10001 && ! (mode == VOIDmode
10002 && (GET_CODE (op0) == COMPARE
10003 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10006 /* Get the constant we are comparing against and turn off all bits
10007 not on in our mode. */
10008 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10009 op1 = GEN_INT (const_op);
10011 /* If we are comparing against a constant power of two and the value
10012 being compared can only have that single bit nonzero (e.g., it was
10013 `and'ed with that bit), we can replace this with a comparison
10016 && (code == EQ || code == NE || code == GE || code == GEU
10017 || code == LT || code == LTU)
10018 && mode_width <= HOST_BITS_PER_WIDE_INT
10019 && exact_log2 (const_op) >= 0
10020 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10022 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10023 op1 = const0_rtx, const_op = 0;
10026 /* Similarly, if we are comparing a value known to be either -1 or
10027 0 with -1, change it to the opposite comparison against zero. */
10030 && (code == EQ || code == NE || code == GT || code == LE
10031 || code == GEU || code == LTU)
10032 && num_sign_bit_copies (op0, mode) == mode_width)
10034 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10035 op1 = const0_rtx, const_op = 0;
10038 /* Do some canonicalizations based on the comparison code. We prefer
10039 comparisons against zero and then prefer equality comparisons.
10040 If we can reduce the size of a constant, we will do that too. */
10045 /* < C is equivalent to <= (C - 1) */
10049 op1 = GEN_INT (const_op);
10051 /* ... fall through to LE case below. */
10057 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10061 op1 = GEN_INT (const_op);
10065 /* If we are doing a <= 0 comparison on a value known to have
10066 a zero sign bit, we can replace this with == 0. */
10067 else if (const_op == 0
10068 && mode_width <= HOST_BITS_PER_WIDE_INT
10069 && (nonzero_bits (op0, mode)
10070 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10075 /* >= C is equivalent to > (C - 1). */
10079 op1 = GEN_INT (const_op);
10081 /* ... fall through to GT below. */
10087 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10091 op1 = GEN_INT (const_op);
10095 /* If we are doing a > 0 comparison on a value known to have
10096 a zero sign bit, we can replace this with != 0. */
10097 else if (const_op == 0
10098 && mode_width <= HOST_BITS_PER_WIDE_INT
10099 && (nonzero_bits (op0, mode)
10100 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10105 /* < C is equivalent to <= (C - 1). */
10109 op1 = GEN_INT (const_op);
10111 /* ... fall through ... */
10114 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10115 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10116 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10118 const_op = 0, op1 = const0_rtx;
10126 /* unsigned <= 0 is equivalent to == 0 */
10130 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10131 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10132 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10134 const_op = 0, op1 = const0_rtx;
10140 /* >= C is equivalent to < (C - 1). */
10144 op1 = GEN_INT (const_op);
10146 /* ... fall through ... */
10149 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10150 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10151 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10153 const_op = 0, op1 = const0_rtx;
10161 /* unsigned > 0 is equivalent to != 0 */
10165 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10166 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10167 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10169 const_op = 0, op1 = const0_rtx;
10178 /* Compute some predicates to simplify code below. */
10180 equality_comparison_p = (code == EQ || code == NE);
10181 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10182 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10185 /* If this is a sign bit comparison and we can do arithmetic in
10186 MODE, say that we will only be needing the sign bit of OP0. */
10187 if (sign_bit_comparison_p
10188 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10189 op0 = force_to_mode (op0, mode,
10191 << (GET_MODE_BITSIZE (mode) - 1)),
10194 /* Now try cases based on the opcode of OP0. If none of the cases
10195 does a "continue", we exit this loop immediately after the
10198 switch (GET_CODE (op0))
10201 /* If we are extracting a single bit from a variable position in
10202 a constant that has only a single bit set and are comparing it
10203 with zero, we can convert this into an equality comparison
10204 between the position and the location of the single bit. */
10206 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10207 && XEXP (op0, 1) == const1_rtx
10208 && equality_comparison_p && const_op == 0
10209 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10211 if (BITS_BIG_ENDIAN)
10213 enum machine_mode new_mode
10214 = mode_for_extraction (EP_extzv, 1);
10215 if (new_mode == MAX_MACHINE_MODE)
10216 i = BITS_PER_WORD - 1 - i;
10220 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10224 op0 = XEXP (op0, 2);
10228 /* Result is nonzero iff shift count is equal to I. */
10229 code = reverse_condition (code);
10233 /* ... fall through ... */
10236 tem = expand_compound_operation (op0);
10245 /* If testing for equality, we can take the NOT of the constant. */
10246 if (equality_comparison_p
10247 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10249 op0 = XEXP (op0, 0);
10254 /* If just looking at the sign bit, reverse the sense of the
10256 if (sign_bit_comparison_p)
10258 op0 = XEXP (op0, 0);
10259 code = (code == GE ? LT : GE);
10265 /* If testing for equality, we can take the NEG of the constant. */
10266 if (equality_comparison_p
10267 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10269 op0 = XEXP (op0, 0);
10274 /* The remaining cases only apply to comparisons with zero. */
10278 /* When X is ABS or is known positive,
10279 (neg X) is < 0 if and only if X != 0. */
10281 if (sign_bit_comparison_p
10282 && (GET_CODE (XEXP (op0, 0)) == ABS
10283 || (mode_width <= HOST_BITS_PER_WIDE_INT
10284 && (nonzero_bits (XEXP (op0, 0), mode)
10285 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10287 op0 = XEXP (op0, 0);
10288 code = (code == LT ? NE : EQ);
10292 /* If we have NEG of something whose two high-order bits are the
10293 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10294 if (num_sign_bit_copies (op0, mode) >= 2)
10296 op0 = XEXP (op0, 0);
10297 code = swap_condition (code);
10303 /* If we are testing equality and our count is a constant, we
10304 can perform the inverse operation on our RHS. */
10305 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10306 && (tem = simplify_binary_operation (ROTATERT, mode,
10307 op1, XEXP (op0, 1))) != 0)
10309 op0 = XEXP (op0, 0);
10314 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10315 a particular bit. Convert it to an AND of a constant of that
10316 bit. This will be converted into a ZERO_EXTRACT. */
10317 if (const_op == 0 && sign_bit_comparison_p
10318 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10319 && mode_width <= HOST_BITS_PER_WIDE_INT)
10321 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10324 - INTVAL (XEXP (op0, 1)))));
10325 code = (code == LT ? NE : EQ);
10329 /* Fall through. */
10332 /* ABS is ignorable inside an equality comparison with zero. */
10333 if (const_op == 0 && equality_comparison_p)
10335 op0 = XEXP (op0, 0);
10341 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10342 to (compare FOO CONST) if CONST fits in FOO's mode and we
10343 are either testing inequality or have an unsigned comparison
10344 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10345 if (! unsigned_comparison_p
10346 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10347 <= HOST_BITS_PER_WIDE_INT)
10348 && ((unsigned HOST_WIDE_INT) const_op
10349 < (((unsigned HOST_WIDE_INT) 1
10350 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10352 op0 = XEXP (op0, 0);
10358 /* Check for the case where we are comparing A - C1 with C2,
10359 both constants are smaller than 1/2 the maximum positive
10360 value in MODE, and the comparison is equality or unsigned.
10361 In that case, if A is either zero-extended to MODE or has
10362 sufficient sign bits so that the high-order bit in MODE
10363 is a copy of the sign in the inner mode, we can prove that it is
10364 safe to do the operation in the wider mode. This simplifies
10365 many range checks. */
10367 if (mode_width <= HOST_BITS_PER_WIDE_INT
10368 && subreg_lowpart_p (op0)
10369 && GET_CODE (SUBREG_REG (op0)) == PLUS
10370 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10371 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10372 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10373 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10374 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10375 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10376 GET_MODE (SUBREG_REG (op0)))
10377 & ~GET_MODE_MASK (mode))
10378 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10379 GET_MODE (SUBREG_REG (op0)))
10380 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10381 - GET_MODE_BITSIZE (mode)))))
10383 op0 = SUBREG_REG (op0);
10387 /* If the inner mode is narrower and we are extracting the low part,
10388 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10389 if (subreg_lowpart_p (op0)
10390 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10391 /* Fall through */ ;
10395 /* ... fall through ... */
10398 if ((unsigned_comparison_p || equality_comparison_p)
10399 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10400 <= HOST_BITS_PER_WIDE_INT)
10401 && ((unsigned HOST_WIDE_INT) const_op
10402 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10404 op0 = XEXP (op0, 0);
10410 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10411 this for equality comparisons due to pathological cases involving
10413 if (equality_comparison_p
10414 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10415 op1, XEXP (op0, 1))))
10417 op0 = XEXP (op0, 0);
10422 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10423 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10424 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10426 op0 = XEXP (XEXP (op0, 0), 0);
10427 code = (code == LT ? EQ : NE);
10433 /* We used to optimize signed comparisons against zero, but that
10434 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10435 arrive here as equality comparisons, or (GEU, LTU) are
10436 optimized away. No need to special-case them. */
10438 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10439 (eq B (minus A C)), whichever simplifies. We can only do
10440 this for equality comparisons due to pathological cases involving
10442 if (equality_comparison_p
10443 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10444 XEXP (op0, 1), op1)))
10446 op0 = XEXP (op0, 0);
10451 if (equality_comparison_p
10452 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10453 XEXP (op0, 0), op1)))
10455 op0 = XEXP (op0, 1);
10460 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10461 of bits in X minus 1, is one iff X > 0. */
10462 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10463 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10464 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10465 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10467 op0 = XEXP (op0, 1);
10468 code = (code == GE ? LE : GT);
10474 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10475 if C is zero or B is a constant. */
10476 if (equality_comparison_p
10477 && 0 != (tem = simplify_binary_operation (XOR, mode,
10478 XEXP (op0, 1), op1)))
10480 op0 = XEXP (op0, 0);
10487 case UNEQ: case LTGT:
10488 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10489 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10490 case UNORDERED: case ORDERED:
10491 /* We can't do anything if OP0 is a condition code value, rather
10492 than an actual data value. */
10495 || XEXP (op0, 0) == cc0_rtx
10497 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10500 /* Get the two operands being compared. */
10501 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10502 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10504 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10506 /* Check for the cases where we simply want the result of the
10507 earlier test or the opposite of that result. */
10508 if (code == NE || code == EQ
10509 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10510 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10511 && (STORE_FLAG_VALUE
10512 & (((HOST_WIDE_INT) 1
10513 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10514 && (code == LT || code == GE)))
10516 enum rtx_code new_code;
10517 if (code == LT || code == NE)
10518 new_code = GET_CODE (op0);
10520 new_code = combine_reversed_comparison_code (op0);
10522 if (new_code != UNKNOWN)
10533 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10535 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10536 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10537 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10539 op0 = XEXP (op0, 1);
10540 code = (code == GE ? GT : LE);
10546 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10547 will be converted to a ZERO_EXTRACT later. */
10548 if (const_op == 0 && equality_comparison_p
10549 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10550 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10552 op0 = simplify_and_const_int
10553 (op0, mode, gen_rtx_LSHIFTRT (mode,
10555 XEXP (XEXP (op0, 0), 1)),
10556 (HOST_WIDE_INT) 1);
10560 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10561 zero and X is a comparison and C1 and C2 describe only bits set
10562 in STORE_FLAG_VALUE, we can compare with X. */
10563 if (const_op == 0 && equality_comparison_p
10564 && mode_width <= HOST_BITS_PER_WIDE_INT
10565 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10566 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10567 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10568 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10569 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10571 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10572 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10573 if ((~STORE_FLAG_VALUE & mask) == 0
10574 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10575 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10576 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10578 op0 = XEXP (XEXP (op0, 0), 0);
10583 /* If we are doing an equality comparison of an AND of a bit equal
10584 to the sign bit, replace this with a LT or GE comparison of
10585 the underlying value. */
10586 if (equality_comparison_p
10588 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10589 && mode_width <= HOST_BITS_PER_WIDE_INT
10590 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10591 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10593 op0 = XEXP (op0, 0);
10594 code = (code == EQ ? GE : LT);
10598 /* If this AND operation is really a ZERO_EXTEND from a narrower
10599 mode, the constant fits within that mode, and this is either an
10600 equality or unsigned comparison, try to do this comparison in
10601 the narrower mode. */
10602 if ((equality_comparison_p || unsigned_comparison_p)
10603 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10604 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10605 & GET_MODE_MASK (mode))
10607 && const_op >> i == 0
10608 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10610 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10614 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10615 in both M1 and M2 and the SUBREG is either paradoxical or
10616 represents the low part, permute the SUBREG and the AND and
10618 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10620 #ifdef WORD_REGISTER_OPERATIONS
10622 > (GET_MODE_BITSIZE
10623 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10624 && mode_width <= BITS_PER_WORD)
10627 <= (GET_MODE_BITSIZE
10628 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10629 && subreg_lowpart_p (XEXP (op0, 0))))
10630 #ifndef WORD_REGISTER_OPERATIONS
10631 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10632 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10633 As originally written the upper bits have a defined value
10634 due to the AND operation. However, if we commute the AND
10635 inside the SUBREG then they no longer have defined values
10636 and the meaning of the code has been changed. */
10637 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10638 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10640 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10641 && mode_width <= HOST_BITS_PER_WIDE_INT
10642 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10643 <= HOST_BITS_PER_WIDE_INT)
10644 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10645 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10646 & INTVAL (XEXP (op0, 1)))
10647 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10648 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10649 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10653 = gen_lowpart_for_combine
10655 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10656 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10660 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10661 (eq (and (lshiftrt X) 1) 0). */
10662 if (const_op == 0 && equality_comparison_p
10663 && XEXP (op0, 1) == const1_rtx
10664 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10665 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10667 op0 = simplify_and_const_int
10669 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10670 XEXP (XEXP (op0, 0), 1)),
10671 (HOST_WIDE_INT) 1);
10672 code = (code == NE ? EQ : NE);
10678 /* If we have (compare (ashift FOO N) (const_int C)) and
10679 the high order N bits of FOO (N+1 if an inequality comparison)
10680 are known to be zero, we can do this by comparing FOO with C
10681 shifted right N bits so long as the low-order N bits of C are
10683 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10684 && INTVAL (XEXP (op0, 1)) >= 0
10685 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10686 < HOST_BITS_PER_WIDE_INT)
10688 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10689 && mode_width <= HOST_BITS_PER_WIDE_INT
10690 && (nonzero_bits (XEXP (op0, 0), mode)
10691 & ~(mask >> (INTVAL (XEXP (op0, 1))
10692 + ! equality_comparison_p))) == 0)
10694 /* We must perform a logical shift, not an arithmetic one,
10695 as we want the top N bits of C to be zero. */
10696 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10698 temp >>= INTVAL (XEXP (op0, 1));
10699 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10700 op0 = XEXP (op0, 0);
10704 /* If we are doing a sign bit comparison, it means we are testing
10705 a particular bit. Convert it to the appropriate AND. */
10706 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10707 && mode_width <= HOST_BITS_PER_WIDE_INT)
10709 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10712 - INTVAL (XEXP (op0, 1)))));
10713 code = (code == LT ? NE : EQ);
10717 /* If this an equality comparison with zero and we are shifting
10718 the low bit to the sign bit, we can convert this to an AND of the
10720 if (const_op == 0 && equality_comparison_p
10721 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10722 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10724 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10725 (HOST_WIDE_INT) 1);
10731 /* If this is an equality comparison with zero, we can do this
10732 as a logical shift, which might be much simpler. */
10733 if (equality_comparison_p && const_op == 0
10734 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10736 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10738 INTVAL (XEXP (op0, 1)));
10742 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10743 do the comparison in a narrower mode. */
10744 if (! unsigned_comparison_p
10745 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10746 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10747 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10748 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10749 MODE_INT, 1)) != BLKmode
10750 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10751 || ((unsigned HOST_WIDE_INT) -const_op
10752 <= GET_MODE_MASK (tmode))))
10754 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10758 /* Likewise if OP0 is a PLUS of a sign extension with a
10759 constant, which is usually represented with the PLUS
10760 between the shifts. */
10761 if (! unsigned_comparison_p
10762 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10763 && GET_CODE (XEXP (op0, 0)) == PLUS
10764 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10765 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10766 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10767 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10768 MODE_INT, 1)) != BLKmode
10769 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10770 || ((unsigned HOST_WIDE_INT) -const_op
10771 <= GET_MODE_MASK (tmode))))
10773 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10774 rtx add_const = XEXP (XEXP (op0, 0), 1);
10775 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10778 op0 = gen_binary (PLUS, tmode,
10779 gen_lowpart_for_combine (tmode, inner),
10784 /* ... fall through ... */
10786 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10787 the low order N bits of FOO are known to be zero, we can do this
10788 by comparing FOO with C shifted left N bits so long as no
10789 overflow occurs. */
10790 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10791 && INTVAL (XEXP (op0, 1)) >= 0
10792 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10793 && mode_width <= HOST_BITS_PER_WIDE_INT
10794 && (nonzero_bits (XEXP (op0, 0), mode)
10795 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10797 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10800 const_op <<= INTVAL (XEXP (op0, 1));
10801 op1 = GEN_INT (const_op);
10802 op0 = XEXP (op0, 0);
10806 /* If we are using this shift to extract just the sign bit, we
10807 can replace this with an LT or GE comparison. */
10809 && (equality_comparison_p || sign_bit_comparison_p)
10810 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10811 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10813 op0 = XEXP (op0, 0);
10814 code = (code == NE || code == GT ? LT : GE);
10826 /* Now make any compound operations involved in this comparison. Then,
10827 check for an outmost SUBREG on OP0 that is not doing anything or is
10828 paradoxical. The latter case can only occur when it is known that the
10829 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10830 We can never remove a SUBREG for a non-equality comparison because the
10831 sign bit is in a different place in the underlying object. */
10833 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10834 op1 = make_compound_operation (op1, SET);
10836 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10837 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10838 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10839 && (code == NE || code == EQ)
10840 && ((GET_MODE_SIZE (GET_MODE (op0))
10841 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10843 op0 = SUBREG_REG (op0);
10844 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10847 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10848 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10849 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10850 && (code == NE || code == EQ)
10851 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10852 <= HOST_BITS_PER_WIDE_INT)
10853 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10854 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10855 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10857 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10858 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10859 op0 = SUBREG_REG (op0), op1 = tem;
10861 /* We now do the opposite procedure: Some machines don't have compare
10862 insns in all modes. If OP0's mode is an integer mode smaller than a
10863 word and we can't do a compare in that mode, see if there is a larger
10864 mode for which we can do the compare. There are a number of cases in
10865 which we can use the wider mode. */
10867 mode = GET_MODE (op0);
10868 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10869 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10870 && ! have_insn_for (COMPARE, mode))
10871 for (tmode = GET_MODE_WIDER_MODE (mode);
10873 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10874 tmode = GET_MODE_WIDER_MODE (tmode))
10875 if (have_insn_for (COMPARE, tmode))
10877 /* If the only nonzero bits in OP0 and OP1 are those in the
10878 narrower mode and this is an equality or unsigned comparison,
10879 we can use the wider mode. Similarly for sign-extended
10880 values, in which case it is true for all comparisons. */
10881 if (((code == EQ || code == NE
10882 || code == GEU || code == GTU || code == LEU || code == LTU)
10883 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
10884 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
10885 || ((num_sign_bit_copies (op0, tmode)
10886 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10887 && (num_sign_bit_copies (op1, tmode)
10888 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10890 /* If OP0 is an AND and we don't have an AND in MODE either,
10891 make a new AND in the proper mode. */
10892 if (GET_CODE (op0) == AND
10893 && !have_insn_for (AND, mode))
10894 op0 = gen_binary (AND, tmode,
10895 gen_lowpart_for_combine (tmode,
10897 gen_lowpart_for_combine (tmode,
10900 op0 = gen_lowpart_for_combine (tmode, op0);
10901 op1 = gen_lowpart_for_combine (tmode, op1);
10905 /* If this is a test for negative, we can make an explicit
10906 test of the sign bit. */
10908 if (op1 == const0_rtx && (code == LT || code == GE)
10909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10911 op0 = gen_binary (AND, tmode,
10912 gen_lowpart_for_combine (tmode, op0),
10913 GEN_INT ((HOST_WIDE_INT) 1
10914 << (GET_MODE_BITSIZE (mode) - 1)));
10915 code = (code == LT) ? NE : EQ;
10920 #ifdef CANONICALIZE_COMPARISON
10921 /* If this machine only supports a subset of valid comparisons, see if we
10922 can convert an unsupported one into a supported one. */
10923 CANONICALIZE_COMPARISON (code, op0, op1);
10932 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10933 searching backward. */
10934 static enum rtx_code
10935 combine_reversed_comparison_code (exp)
10938 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10941 if (code1 != UNKNOWN
10942 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10944 /* Otherwise try and find where the condition codes were last set and
10946 x = get_last_value (XEXP (exp, 0));
10947 if (!x || GET_CODE (x) != COMPARE)
10949 return reversed_comparison_code_parts (GET_CODE (exp),
10950 XEXP (x, 0), XEXP (x, 1), NULL);
10952 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10953 Return NULL_RTX in case we fail to do the reversal. */
10955 reversed_comparison (exp, mode, op0, op1)
10957 enum machine_mode mode;
10959 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10960 if (reversed_code == UNKNOWN)
10963 return gen_binary (reversed_code, mode, op0, op1);
10966 /* Utility function for following routine. Called when X is part of a value
10967 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10968 for each register mentioned. Similar to mention_regs in cse.c */
10971 update_table_tick (x)
10974 enum rtx_code code = GET_CODE (x);
10975 const char *fmt = GET_RTX_FORMAT (code);
10980 unsigned int regno = REGNO (x);
10981 unsigned int endregno
10982 = regno + (regno < FIRST_PSEUDO_REGISTER
10983 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10986 for (r = regno; r < endregno; r++)
10987 reg_last_set_table_tick[r] = label_tick;
10992 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10993 /* Note that we can't have an "E" in values stored; see
10994 get_last_value_validate. */
10996 update_table_tick (XEXP (x, i));
10999 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11000 are saying that the register is clobbered and we no longer know its
11001 value. If INSN is zero, don't update reg_last_set; this is only permitted
11002 with VALUE also zero and is used to invalidate the register. */
11005 record_value_for_reg (reg, insn, value)
11010 unsigned int regno = REGNO (reg);
11011 unsigned int endregno
11012 = regno + (regno < FIRST_PSEUDO_REGISTER
11013 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11016 /* If VALUE contains REG and we have a previous value for REG, substitute
11017 the previous value. */
11018 if (value && insn && reg_overlap_mentioned_p (reg, value))
11022 /* Set things up so get_last_value is allowed to see anything set up to
11024 subst_low_cuid = INSN_CUID (insn);
11025 tem = get_last_value (reg);
11027 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11028 it isn't going to be useful and will take a lot of time to process,
11029 so just use the CLOBBER. */
11033 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11034 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11035 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11036 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11037 tem = XEXP (tem, 0);
11039 value = replace_rtx (copy_rtx (value), reg, tem);
11043 /* For each register modified, show we don't know its value, that
11044 we don't know about its bitwise content, that its value has been
11045 updated, and that we don't know the location of the death of the
11047 for (i = regno; i < endregno; i++)
11050 reg_last_set[i] = insn;
11052 reg_last_set_value[i] = 0;
11053 reg_last_set_mode[i] = 0;
11054 reg_last_set_nonzero_bits[i] = 0;
11055 reg_last_set_sign_bit_copies[i] = 0;
11056 reg_last_death[i] = 0;
11059 /* Mark registers that are being referenced in this value. */
11061 update_table_tick (value);
11063 /* Now update the status of each register being set.
11064 If someone is using this register in this block, set this register
11065 to invalid since we will get confused between the two lives in this
11066 basic block. This makes using this register always invalid. In cse, we
11067 scan the table to invalidate all entries using this register, but this
11068 is too much work for us. */
11070 for (i = regno; i < endregno; i++)
11072 reg_last_set_label[i] = label_tick;
11073 if (value && reg_last_set_table_tick[i] == label_tick)
11074 reg_last_set_invalid[i] = 1;
11076 reg_last_set_invalid[i] = 0;
11079 /* The value being assigned might refer to X (like in "x++;"). In that
11080 case, we must replace it with (clobber (const_int 0)) to prevent
11082 if (value && ! get_last_value_validate (&value, insn,
11083 reg_last_set_label[regno], 0))
11085 value = copy_rtx (value);
11086 if (! get_last_value_validate (&value, insn,
11087 reg_last_set_label[regno], 1))
11091 /* For the main register being modified, update the value, the mode, the
11092 nonzero bits, and the number of sign bit copies. */
11094 reg_last_set_value[regno] = value;
11098 subst_low_cuid = INSN_CUID (insn);
11099 reg_last_set_mode[regno] = GET_MODE (reg);
11100 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11101 reg_last_set_sign_bit_copies[regno]
11102 = num_sign_bit_copies (value, GET_MODE (reg));
11106 /* Called via note_stores from record_dead_and_set_regs to handle one
11107 SET or CLOBBER in an insn. DATA is the instruction in which the
11108 set is occurring. */
11111 record_dead_and_set_regs_1 (dest, setter, data)
11115 rtx record_dead_insn = (rtx) data;
11117 if (GET_CODE (dest) == SUBREG)
11118 dest = SUBREG_REG (dest);
11120 if (GET_CODE (dest) == REG)
11122 /* If we are setting the whole register, we know its value. Otherwise
11123 show that we don't know the value. We can handle SUBREG in
11125 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11126 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11127 else if (GET_CODE (setter) == SET
11128 && GET_CODE (SET_DEST (setter)) == SUBREG
11129 && SUBREG_REG (SET_DEST (setter)) == dest
11130 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11131 && subreg_lowpart_p (SET_DEST (setter)))
11132 record_value_for_reg (dest, record_dead_insn,
11133 gen_lowpart_for_combine (GET_MODE (dest),
11134 SET_SRC (setter)));
11136 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11138 else if (GET_CODE (dest) == MEM
11139 /* Ignore pushes, they clobber nothing. */
11140 && ! push_operand (dest, GET_MODE (dest)))
11141 mem_last_set = INSN_CUID (record_dead_insn);
11144 /* Update the records of when each REG was most recently set or killed
11145 for the things done by INSN. This is the last thing done in processing
11146 INSN in the combiner loop.
11148 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11149 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11150 and also the similar information mem_last_set (which insn most recently
11151 modified memory) and last_call_cuid (which insn was the most recent
11152 subroutine call). */
11155 record_dead_and_set_regs (insn)
11161 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11163 if (REG_NOTE_KIND (link) == REG_DEAD
11164 && GET_CODE (XEXP (link, 0)) == REG)
11166 unsigned int regno = REGNO (XEXP (link, 0));
11167 unsigned int endregno
11168 = regno + (regno < FIRST_PSEUDO_REGISTER
11169 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11172 for (i = regno; i < endregno; i++)
11173 reg_last_death[i] = insn;
11175 else if (REG_NOTE_KIND (link) == REG_INC)
11176 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11179 if (GET_CODE (insn) == CALL_INSN)
11181 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11182 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11184 reg_last_set_value[i] = 0;
11185 reg_last_set_mode[i] = 0;
11186 reg_last_set_nonzero_bits[i] = 0;
11187 reg_last_set_sign_bit_copies[i] = 0;
11188 reg_last_death[i] = 0;
11191 last_call_cuid = mem_last_set = INSN_CUID (insn);
11193 /* Don't bother recording what this insn does. It might set the
11194 return value register, but we can't combine into a call
11195 pattern anyway, so there's no point trying (and it may cause
11196 a crash, if e.g. we wind up asking for last_set_value of a
11197 SUBREG of the return value register). */
11201 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11204 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11205 register present in the SUBREG, so for each such SUBREG go back and
11206 adjust nonzero and sign bit information of the registers that are
11207 known to have some zero/sign bits set.
11209 This is needed because when combine blows the SUBREGs away, the
11210 information on zero/sign bits is lost and further combines can be
11211 missed because of that. */
11214 record_promoted_value (insn, subreg)
11219 unsigned int regno = REGNO (SUBREG_REG (subreg));
11220 enum machine_mode mode = GET_MODE (subreg);
11222 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11225 for (links = LOG_LINKS (insn); links;)
11227 insn = XEXP (links, 0);
11228 set = single_set (insn);
11230 if (! set || GET_CODE (SET_DEST (set)) != REG
11231 || REGNO (SET_DEST (set)) != regno
11232 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11234 links = XEXP (links, 1);
11238 if (reg_last_set[regno] == insn)
11240 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11241 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11244 if (GET_CODE (SET_SRC (set)) == REG)
11246 regno = REGNO (SET_SRC (set));
11247 links = LOG_LINKS (insn);
11254 /* Scan X for promoted SUBREGs. For each one found,
11255 note what it implies to the registers used in it. */
11258 check_promoted_subreg (insn, x)
11262 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11263 && GET_CODE (SUBREG_REG (x)) == REG)
11264 record_promoted_value (insn, x);
11267 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11270 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11274 check_promoted_subreg (insn, XEXP (x, i));
11278 if (XVEC (x, i) != 0)
11279 for (j = 0; j < XVECLEN (x, i); j++)
11280 check_promoted_subreg (insn, XVECEXP (x, i, j));
11286 /* Utility routine for the following function. Verify that all the registers
11287 mentioned in *LOC are valid when *LOC was part of a value set when
11288 label_tick == TICK. Return 0 if some are not.
11290 If REPLACE is non-zero, replace the invalid reference with
11291 (clobber (const_int 0)) and return 1. This replacement is useful because
11292 we often can get useful information about the form of a value (e.g., if
11293 it was produced by a shift that always produces -1 or 0) even though
11294 we don't know exactly what registers it was produced from. */
11297 get_last_value_validate (loc, insn, tick, replace)
11304 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11305 int len = GET_RTX_LENGTH (GET_CODE (x));
11308 if (GET_CODE (x) == REG)
11310 unsigned int regno = REGNO (x);
11311 unsigned int endregno
11312 = regno + (regno < FIRST_PSEUDO_REGISTER
11313 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11316 for (j = regno; j < endregno; j++)
11317 if (reg_last_set_invalid[j]
11318 /* If this is a pseudo-register that was only set once and not
11319 live at the beginning of the function, it is always valid. */
11320 || (! (regno >= FIRST_PSEUDO_REGISTER
11321 && REG_N_SETS (regno) == 1
11322 && (! REGNO_REG_SET_P
11323 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11324 && reg_last_set_label[j] > tick))
11327 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11333 /* If this is a memory reference, make sure that there were
11334 no stores after it that might have clobbered the value. We don't
11335 have alias info, so we assume any store invalidates it. */
11336 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11337 && INSN_CUID (insn) <= mem_last_set)
11340 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11344 for (i = 0; i < len; i++)
11346 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11347 /* Don't bother with these. They shouldn't occur anyway. */
11351 /* If we haven't found a reason for it to be invalid, it is valid. */
11355 /* Get the last value assigned to X, if known. Some registers
11356 in the value may be replaced with (clobber (const_int 0)) if their value
11357 is known longer known reliably. */
11363 unsigned int regno;
11366 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11367 then convert it to the desired mode. If this is a paradoxical SUBREG,
11368 we cannot predict what values the "extra" bits might have. */
11369 if (GET_CODE (x) == SUBREG
11370 && subreg_lowpart_p (x)
11371 && (GET_MODE_SIZE (GET_MODE (x))
11372 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11373 && (value = get_last_value (SUBREG_REG (x))) != 0)
11374 return gen_lowpart_for_combine (GET_MODE (x), value);
11376 if (GET_CODE (x) != REG)
11380 value = reg_last_set_value[regno];
11382 /* If we don't have a value, or if it isn't for this basic block and
11383 it's either a hard register, set more than once, or it's a live
11384 at the beginning of the function, return 0.
11386 Because if it's not live at the beginning of the function then the reg
11387 is always set before being used (is never used without being set).
11388 And, if it's set only once, and it's always set before use, then all
11389 uses must have the same last value, even if it's not from this basic
11393 || (reg_last_set_label[regno] != label_tick
11394 && (regno < FIRST_PSEUDO_REGISTER
11395 || REG_N_SETS (regno) != 1
11396 || (REGNO_REG_SET_P
11397 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11400 /* If the value was set in a later insn than the ones we are processing,
11401 we can't use it even if the register was only set once. */
11402 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11405 /* If the value has all its registers valid, return it. */
11406 if (get_last_value_validate (&value, reg_last_set[regno],
11407 reg_last_set_label[regno], 0))
11410 /* Otherwise, make a copy and replace any invalid register with
11411 (clobber (const_int 0)). If that fails for some reason, return 0. */
11413 value = copy_rtx (value);
11414 if (get_last_value_validate (&value, reg_last_set[regno],
11415 reg_last_set_label[regno], 1))
11421 /* Return nonzero if expression X refers to a REG or to memory
11422 that is set in an instruction more recent than FROM_CUID. */
11425 use_crosses_set_p (x, from_cuid)
11431 enum rtx_code code = GET_CODE (x);
11435 unsigned int regno = REGNO (x);
11436 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11437 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11439 #ifdef PUSH_ROUNDING
11440 /* Don't allow uses of the stack pointer to be moved,
11441 because we don't know whether the move crosses a push insn. */
11442 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11445 for (; regno < endreg; regno++)
11446 if (reg_last_set[regno]
11447 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11452 if (code == MEM && mem_last_set > from_cuid)
11455 fmt = GET_RTX_FORMAT (code);
11457 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11462 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11463 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11466 else if (fmt[i] == 'e'
11467 && use_crosses_set_p (XEXP (x, i), from_cuid))
11473 /* Define three variables used for communication between the following
11476 static unsigned int reg_dead_regno, reg_dead_endregno;
11477 static int reg_dead_flag;
11479 /* Function called via note_stores from reg_dead_at_p.
11481 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11482 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11485 reg_dead_at_p_1 (dest, x, data)
11488 void *data ATTRIBUTE_UNUSED;
11490 unsigned int regno, endregno;
11492 if (GET_CODE (dest) != REG)
11495 regno = REGNO (dest);
11496 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11497 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11499 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11500 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11503 /* Return non-zero if REG is known to be dead at INSN.
11505 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11506 referencing REG, it is dead. If we hit a SET referencing REG, it is
11507 live. Otherwise, see if it is live or dead at the start of the basic
11508 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11509 must be assumed to be always live. */
11512 reg_dead_at_p (reg, insn)
11519 /* Set variables for reg_dead_at_p_1. */
11520 reg_dead_regno = REGNO (reg);
11521 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11522 ? HARD_REGNO_NREGS (reg_dead_regno,
11528 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11529 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11531 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11532 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11536 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11537 beginning of function. */
11538 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11539 insn = prev_nonnote_insn (insn))
11541 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11543 return reg_dead_flag == 1 ? 1 : 0;
11545 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11549 /* Get the basic block number that we were in. */
11554 for (block = 0; block < n_basic_blocks; block++)
11555 if (insn == BLOCK_HEAD (block))
11558 if (block == n_basic_blocks)
11562 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11563 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11569 /* Note hard registers in X that are used. This code is similar to
11570 that in flow.c, but much simpler since we don't care about pseudos. */
11573 mark_used_regs_combine (x)
11576 RTX_CODE code = GET_CODE (x);
11577 unsigned int regno;
11589 case ADDR_DIFF_VEC:
11592 /* CC0 must die in the insn after it is set, so we don't need to take
11593 special note of it here. */
11599 /* If we are clobbering a MEM, mark any hard registers inside the
11600 address as used. */
11601 if (GET_CODE (XEXP (x, 0)) == MEM)
11602 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11607 /* A hard reg in a wide mode may really be multiple registers.
11608 If so, mark all of them just like the first. */
11609 if (regno < FIRST_PSEUDO_REGISTER)
11611 unsigned int endregno, r;
11613 /* None of this applies to the stack, frame or arg pointers */
11614 if (regno == STACK_POINTER_REGNUM
11615 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11616 || regno == HARD_FRAME_POINTER_REGNUM
11618 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11619 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11621 || regno == FRAME_POINTER_REGNUM)
11624 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11625 for (r = regno; r < endregno; r++)
11626 SET_HARD_REG_BIT (newpat_used_regs, r);
11632 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11634 rtx testreg = SET_DEST (x);
11636 while (GET_CODE (testreg) == SUBREG
11637 || GET_CODE (testreg) == ZERO_EXTRACT
11638 || GET_CODE (testreg) == SIGN_EXTRACT
11639 || GET_CODE (testreg) == STRICT_LOW_PART)
11640 testreg = XEXP (testreg, 0);
11642 if (GET_CODE (testreg) == MEM)
11643 mark_used_regs_combine (XEXP (testreg, 0));
11645 mark_used_regs_combine (SET_SRC (x));
11653 /* Recursively scan the operands of this expression. */
11656 const char *fmt = GET_RTX_FORMAT (code);
11658 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11661 mark_used_regs_combine (XEXP (x, i));
11662 else if (fmt[i] == 'E')
11666 for (j = 0; j < XVECLEN (x, i); j++)
11667 mark_used_regs_combine (XVECEXP (x, i, j));
11673 /* Remove register number REGNO from the dead registers list of INSN.
11675 Return the note used to record the death, if there was one. */
11678 remove_death (regno, insn)
11679 unsigned int regno;
11682 rtx note = find_regno_note (insn, REG_DEAD, regno);
11686 REG_N_DEATHS (regno)--;
11687 remove_note (insn, note);
11693 /* For each register (hardware or pseudo) used within expression X, if its
11694 death is in an instruction with cuid between FROM_CUID (inclusive) and
11695 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11696 list headed by PNOTES.
11698 That said, don't move registers killed by maybe_kill_insn.
11700 This is done when X is being merged by combination into TO_INSN. These
11701 notes will then be distributed as needed. */
11704 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11706 rtx maybe_kill_insn;
11713 enum rtx_code code = GET_CODE (x);
11717 unsigned int regno = REGNO (x);
11718 rtx where_dead = reg_last_death[regno];
11719 rtx before_dead, after_dead;
11721 /* Don't move the register if it gets killed in between from and to */
11722 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11723 && ! reg_referenced_p (x, maybe_kill_insn))
11726 /* WHERE_DEAD could be a USE insn made by combine, so first we
11727 make sure that we have insns with valid INSN_CUID values. */
11728 before_dead = where_dead;
11729 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11730 before_dead = PREV_INSN (before_dead);
11732 after_dead = where_dead;
11733 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11734 after_dead = NEXT_INSN (after_dead);
11736 if (before_dead && after_dead
11737 && INSN_CUID (before_dead) >= from_cuid
11738 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11739 || (where_dead != after_dead
11740 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11742 rtx note = remove_death (regno, where_dead);
11744 /* It is possible for the call above to return 0. This can occur
11745 when reg_last_death points to I2 or I1 that we combined with.
11746 In that case make a new note.
11748 We must also check for the case where X is a hard register
11749 and NOTE is a death note for a range of hard registers
11750 including X. In that case, we must put REG_DEAD notes for
11751 the remaining registers in place of NOTE. */
11753 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11754 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11755 > GET_MODE_SIZE (GET_MODE (x))))
11757 unsigned int deadregno = REGNO (XEXP (note, 0));
11758 unsigned int deadend
11759 = (deadregno + HARD_REGNO_NREGS (deadregno,
11760 GET_MODE (XEXP (note, 0))));
11761 unsigned int ourend
11762 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11765 for (i = deadregno; i < deadend; i++)
11766 if (i < regno || i >= ourend)
11767 REG_NOTES (where_dead)
11768 = gen_rtx_EXPR_LIST (REG_DEAD,
11769 gen_rtx_REG (reg_raw_mode[i], i),
11770 REG_NOTES (where_dead));
11773 /* If we didn't find any note, or if we found a REG_DEAD note that
11774 covers only part of the given reg, and we have a multi-reg hard
11775 register, then to be safe we must check for REG_DEAD notes
11776 for each register other than the first. They could have
11777 their own REG_DEAD notes lying around. */
11778 else if ((note == 0
11780 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11781 < GET_MODE_SIZE (GET_MODE (x)))))
11782 && regno < FIRST_PSEUDO_REGISTER
11783 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11785 unsigned int ourend
11786 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11787 unsigned int i, offset;
11791 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11795 for (i = regno + offset; i < ourend; i++)
11796 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11797 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11800 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11802 XEXP (note, 1) = *pnotes;
11806 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11808 REG_N_DEATHS (regno)++;
11814 else if (GET_CODE (x) == SET)
11816 rtx dest = SET_DEST (x);
11818 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11820 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11821 that accesses one word of a multi-word item, some
11822 piece of everything register in the expression is used by
11823 this insn, so remove any old death. */
11824 /* ??? So why do we test for equality of the sizes? */
11826 if (GET_CODE (dest) == ZERO_EXTRACT
11827 || GET_CODE (dest) == STRICT_LOW_PART
11828 || (GET_CODE (dest) == SUBREG
11829 && (((GET_MODE_SIZE (GET_MODE (dest))
11830 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11831 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11832 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11834 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11838 /* If this is some other SUBREG, we know it replaces the entire
11839 value, so use that as the destination. */
11840 if (GET_CODE (dest) == SUBREG)
11841 dest = SUBREG_REG (dest);
11843 /* If this is a MEM, adjust deaths of anything used in the address.
11844 For a REG (the only other possibility), the entire value is
11845 being replaced so the old value is not used in this insn. */
11847 if (GET_CODE (dest) == MEM)
11848 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11853 else if (GET_CODE (x) == CLOBBER)
11856 len = GET_RTX_LENGTH (code);
11857 fmt = GET_RTX_FORMAT (code);
11859 for (i = 0; i < len; i++)
11864 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11865 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11868 else if (fmt[i] == 'e')
11869 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11873 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11874 pattern of an insn. X must be a REG. */
11877 reg_bitfield_target_p (x, body)
11883 if (GET_CODE (body) == SET)
11885 rtx dest = SET_DEST (body);
11887 unsigned int regno, tregno, endregno, endtregno;
11889 if (GET_CODE (dest) == ZERO_EXTRACT)
11890 target = XEXP (dest, 0);
11891 else if (GET_CODE (dest) == STRICT_LOW_PART)
11892 target = SUBREG_REG (XEXP (dest, 0));
11896 if (GET_CODE (target) == SUBREG)
11897 target = SUBREG_REG (target);
11899 if (GET_CODE (target) != REG)
11902 tregno = REGNO (target), regno = REGNO (x);
11903 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11904 return target == x;
11906 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11907 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11909 return endregno > tregno && regno < endtregno;
11912 else if (GET_CODE (body) == PARALLEL)
11913 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11914 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11920 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11921 as appropriate. I3 and I2 are the insns resulting from the combination
11922 insns including FROM (I2 may be zero).
11924 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11925 not need REG_DEAD notes because they are being substituted for. This
11926 saves searching in the most common cases.
11928 Each note in the list is either ignored or placed on some insns, depending
11929 on the type of note. */
11932 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11936 rtx elim_i2, elim_i1;
11938 rtx note, next_note;
11941 for (note = notes; note; note = next_note)
11943 rtx place = 0, place2 = 0;
11945 /* If this NOTE references a pseudo register, ensure it references
11946 the latest copy of that register. */
11947 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11948 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11949 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11951 next_note = XEXP (note, 1);
11952 switch (REG_NOTE_KIND (note))
11956 case REG_EXEC_COUNT:
11957 /* Doesn't matter much where we put this, as long as it's somewhere.
11958 It is preferable to keep these notes on branches, which is most
11959 likely to be i3. */
11963 case REG_VTABLE_REF:
11964 /* ??? Should remain with *a particular* memory load. Given the
11965 nature of vtable data, the last insn seems relatively safe. */
11969 case REG_NON_LOCAL_GOTO:
11970 if (GET_CODE (i3) == JUMP_INSN)
11972 else if (i2 && GET_CODE (i2) == JUMP_INSN)
11978 case REG_EH_REGION:
11979 /* These notes must remain with the call or trapping instruction. */
11980 if (GET_CODE (i3) == CALL_INSN)
11982 else if (i2 && GET_CODE (i2) == CALL_INSN)
11984 else if (flag_non_call_exceptions)
11986 if (may_trap_p (i3))
11988 else if (i2 && may_trap_p (i2))
11990 /* ??? Otherwise assume we've combined things such that we
11991 can now prove that the instructions can't trap. Drop the
11992 note in this case. */
12000 /* These notes must remain with the call. It should not be
12001 possible for both I2 and I3 to be a call. */
12002 if (GET_CODE (i3) == CALL_INSN)
12004 else if (i2 && GET_CODE (i2) == CALL_INSN)
12011 /* Any clobbers for i3 may still exist, and so we must process
12012 REG_UNUSED notes from that insn.
12014 Any clobbers from i2 or i1 can only exist if they were added by
12015 recog_for_combine. In that case, recog_for_combine created the
12016 necessary REG_UNUSED notes. Trying to keep any original
12017 REG_UNUSED notes from these insns can cause incorrect output
12018 if it is for the same register as the original i3 dest.
12019 In that case, we will notice that the register is set in i3,
12020 and then add a REG_UNUSED note for the destination of i3, which
12021 is wrong. However, it is possible to have REG_UNUSED notes from
12022 i2 or i1 for register which were both used and clobbered, so
12023 we keep notes from i2 or i1 if they will turn into REG_DEAD
12026 /* If this register is set or clobbered in I3, put the note there
12027 unless there is one already. */
12028 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12030 if (from_insn != i3)
12033 if (! (GET_CODE (XEXP (note, 0)) == REG
12034 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12035 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12038 /* Otherwise, if this register is used by I3, then this register
12039 now dies here, so we must put a REG_DEAD note here unless there
12041 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12042 && ! (GET_CODE (XEXP (note, 0)) == REG
12043 ? find_regno_note (i3, REG_DEAD,
12044 REGNO (XEXP (note, 0)))
12045 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12047 PUT_REG_NOTE_KIND (note, REG_DEAD);
12055 /* These notes say something about results of an insn. We can
12056 only support them if they used to be on I3 in which case they
12057 remain on I3. Otherwise they are ignored.
12059 If the note refers to an expression that is not a constant, we
12060 must also ignore the note since we cannot tell whether the
12061 equivalence is still true. It might be possible to do
12062 slightly better than this (we only have a problem if I2DEST
12063 or I1DEST is present in the expression), but it doesn't
12064 seem worth the trouble. */
12066 if (from_insn == i3
12067 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12072 case REG_NO_CONFLICT:
12073 /* These notes say something about how a register is used. They must
12074 be present on any use of the register in I2 or I3. */
12075 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12078 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12088 /* This can show up in several ways -- either directly in the
12089 pattern, or hidden off in the constant pool with (or without?)
12090 a REG_EQUAL note. */
12091 /* ??? Ignore the without-reg_equal-note problem for now. */
12092 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12093 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12094 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12095 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12099 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12100 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12101 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12102 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12110 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12111 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12112 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12114 if (JUMP_LABEL (place) != XEXP (note, 0))
12116 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12117 LABEL_NUSES (JUMP_LABEL (place))--;
12120 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12122 if (JUMP_LABEL (place2) != XEXP (note, 0))
12124 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12125 LABEL_NUSES (JUMP_LABEL (place2))--;
12132 /* These notes say something about the value of a register prior
12133 to the execution of an insn. It is too much trouble to see
12134 if the note is still correct in all situations. It is better
12135 to simply delete it. */
12139 /* If the insn previously containing this note still exists,
12140 put it back where it was. Otherwise move it to the previous
12141 insn. Adjust the corresponding REG_LIBCALL note. */
12142 if (GET_CODE (from_insn) != NOTE)
12146 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12147 place = prev_real_insn (from_insn);
12149 XEXP (tem, 0) = place;
12150 /* If we're deleting the last remaining instruction of a
12151 libcall sequence, don't add the notes. */
12152 else if (XEXP (note, 0) == from_insn)
12158 /* This is handled similarly to REG_RETVAL. */
12159 if (GET_CODE (from_insn) != NOTE)
12163 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12164 place = next_real_insn (from_insn);
12166 XEXP (tem, 0) = place;
12167 /* If we're deleting the last remaining instruction of a
12168 libcall sequence, don't add the notes. */
12169 else if (XEXP (note, 0) == from_insn)
12175 /* If the register is used as an input in I3, it dies there.
12176 Similarly for I2, if it is non-zero and adjacent to I3.
12178 If the register is not used as an input in either I3 or I2
12179 and it is not one of the registers we were supposed to eliminate,
12180 there are two possibilities. We might have a non-adjacent I2
12181 or we might have somehow eliminated an additional register
12182 from a computation. For example, we might have had A & B where
12183 we discover that B will always be zero. In this case we will
12184 eliminate the reference to A.
12186 In both cases, we must search to see if we can find a previous
12187 use of A and put the death note there. */
12190 && GET_CODE (from_insn) == CALL_INSN
12191 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12193 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12195 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12196 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12199 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12200 || rtx_equal_p (XEXP (note, 0), elim_i1))
12205 basic_block bb = BASIC_BLOCK (this_basic_block);
12207 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12209 if (! INSN_P (tem))
12211 if (tem == bb->head)
12216 /* If the register is being set at TEM, see if that is all
12217 TEM is doing. If so, delete TEM. Otherwise, make this
12218 into a REG_UNUSED note instead. */
12219 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12221 rtx set = single_set (tem);
12222 rtx inner_dest = 0;
12224 rtx cc0_setter = NULL_RTX;
12228 for (inner_dest = SET_DEST (set);
12229 (GET_CODE (inner_dest) == STRICT_LOW_PART
12230 || GET_CODE (inner_dest) == SUBREG
12231 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12232 inner_dest = XEXP (inner_dest, 0))
12235 /* Verify that it was the set, and not a clobber that
12236 modified the register.
12238 CC0 targets must be careful to maintain setter/user
12239 pairs. If we cannot delete the setter due to side
12240 effects, mark the user with an UNUSED note instead
12243 if (set != 0 && ! side_effects_p (SET_SRC (set))
12244 && rtx_equal_p (XEXP (note, 0), inner_dest)
12246 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12247 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12248 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12252 /* Move the notes and links of TEM elsewhere.
12253 This might delete other dead insns recursively.
12254 First set the pattern to something that won't use
12257 PATTERN (tem) = pc_rtx;
12259 distribute_notes (REG_NOTES (tem), tem, tem,
12260 NULL_RTX, NULL_RTX, NULL_RTX);
12261 distribute_links (LOG_LINKS (tem));
12263 PUT_CODE (tem, NOTE);
12264 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12265 NOTE_SOURCE_FILE (tem) = 0;
12268 /* Delete the setter too. */
12271 PATTERN (cc0_setter) = pc_rtx;
12273 distribute_notes (REG_NOTES (cc0_setter),
12274 cc0_setter, cc0_setter,
12275 NULL_RTX, NULL_RTX, NULL_RTX);
12276 distribute_links (LOG_LINKS (cc0_setter));
12278 PUT_CODE (cc0_setter, NOTE);
12279 NOTE_LINE_NUMBER (cc0_setter)
12280 = NOTE_INSN_DELETED;
12281 NOTE_SOURCE_FILE (cc0_setter) = 0;
12285 /* If the register is both set and used here, put the
12286 REG_DEAD note here, but place a REG_UNUSED note
12287 here too unless there already is one. */
12288 else if (reg_referenced_p (XEXP (note, 0),
12293 if (! find_regno_note (tem, REG_UNUSED,
12294 REGNO (XEXP (note, 0))))
12296 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12301 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12303 /* If there isn't already a REG_UNUSED note, put one
12305 if (! find_regno_note (tem, REG_UNUSED,
12306 REGNO (XEXP (note, 0))))
12311 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12312 || (GET_CODE (tem) == CALL_INSN
12313 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12317 /* If we are doing a 3->2 combination, and we have a
12318 register which formerly died in i3 and was not used
12319 by i2, which now no longer dies in i3 and is used in
12320 i2 but does not die in i2, and place is between i2
12321 and i3, then we may need to move a link from place to
12323 if (i2 && INSN_UID (place) <= max_uid_cuid
12324 && INSN_CUID (place) > INSN_CUID (i2)
12326 && INSN_CUID (from_insn) > INSN_CUID (i2)
12327 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12329 rtx links = LOG_LINKS (place);
12330 LOG_LINKS (place) = 0;
12331 distribute_links (links);
12336 if (tem == bb->head)
12340 /* We haven't found an insn for the death note and it
12341 is still a REG_DEAD note, but we have hit the beginning
12342 of the block. If the existing life info says the reg
12343 was dead, there's nothing left to do. Otherwise, we'll
12344 need to do a global life update after combine. */
12345 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12346 && REGNO_REG_SET_P (bb->global_live_at_start,
12347 REGNO (XEXP (note, 0))))
12349 SET_BIT (refresh_blocks, this_basic_block);
12354 /* If the register is set or already dead at PLACE, we needn't do
12355 anything with this note if it is still a REG_DEAD note.
12356 We can here if it is set at all, not if is it totally replace,
12357 which is what `dead_or_set_p' checks, so also check for it being
12360 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12362 unsigned int regno = REGNO (XEXP (note, 0));
12364 /* Similarly, if the instruction on which we want to place
12365 the note is a noop, we'll need do a global live update
12366 after we remove them in delete_noop_moves. */
12367 if (noop_move_p (place))
12369 SET_BIT (refresh_blocks, this_basic_block);
12373 if (dead_or_set_p (place, XEXP (note, 0))
12374 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12376 /* Unless the register previously died in PLACE, clear
12377 reg_last_death. [I no longer understand why this is
12379 if (reg_last_death[regno] != place)
12380 reg_last_death[regno] = 0;
12384 reg_last_death[regno] = place;
12386 /* If this is a death note for a hard reg that is occupying
12387 multiple registers, ensure that we are still using all
12388 parts of the object. If we find a piece of the object
12389 that is unused, we must arrange for an appropriate REG_DEAD
12390 note to be added for it. However, we can't just emit a USE
12391 and tag the note to it, since the register might actually
12392 be dead; so we recourse, and the recursive call then finds
12393 the previous insn that used this register. */
12395 if (place && regno < FIRST_PSEUDO_REGISTER
12396 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12398 unsigned int endregno
12399 = regno + HARD_REGNO_NREGS (regno,
12400 GET_MODE (XEXP (note, 0)));
12404 for (i = regno; i < endregno; i++)
12405 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12406 && ! find_regno_fusage (place, USE, i))
12407 || dead_or_set_regno_p (place, i))
12412 /* Put only REG_DEAD notes for pieces that are
12413 not already dead or set. */
12415 for (i = regno; i < endregno;
12416 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12418 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12419 basic_block bb = BASIC_BLOCK (this_basic_block);
12421 if (! dead_or_set_p (place, piece)
12422 && ! reg_bitfield_target_p (piece,
12426 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12428 distribute_notes (new_note, place, place,
12429 NULL_RTX, NULL_RTX, NULL_RTX);
12431 else if (! refers_to_regno_p (i, i + 1,
12432 PATTERN (place), 0)
12433 && ! find_regno_fusage (place, USE, i))
12434 for (tem = PREV_INSN (place); ;
12435 tem = PREV_INSN (tem))
12437 if (! INSN_P (tem))
12439 if (tem == bb->head)
12441 SET_BIT (refresh_blocks,
12448 if (dead_or_set_p (tem, piece)
12449 || reg_bitfield_target_p (piece,
12453 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12468 /* Any other notes should not be present at this point in the
12475 XEXP (note, 1) = REG_NOTES (place);
12476 REG_NOTES (place) = note;
12478 else if ((REG_NOTE_KIND (note) == REG_DEAD
12479 || REG_NOTE_KIND (note) == REG_UNUSED)
12480 && GET_CODE (XEXP (note, 0)) == REG)
12481 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12485 if ((REG_NOTE_KIND (note) == REG_DEAD
12486 || REG_NOTE_KIND (note) == REG_UNUSED)
12487 && GET_CODE (XEXP (note, 0)) == REG)
12488 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12490 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12491 REG_NOTE_KIND (note),
12493 REG_NOTES (place2));
12498 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12499 I3, I2, and I1 to new locations. This is also called in one case to
12500 add a link pointing at I3 when I3's destination is changed. */
12503 distribute_links (links)
12506 rtx link, next_link;
12508 for (link = links; link; link = next_link)
12514 next_link = XEXP (link, 1);
12516 /* If the insn that this link points to is a NOTE or isn't a single
12517 set, ignore it. In the latter case, it isn't clear what we
12518 can do other than ignore the link, since we can't tell which
12519 register it was for. Such links wouldn't be used by combine
12522 It is not possible for the destination of the target of the link to
12523 have been changed by combine. The only potential of this is if we
12524 replace I3, I2, and I1 by I3 and I2. But in that case the
12525 destination of I2 also remains unchanged. */
12527 if (GET_CODE (XEXP (link, 0)) == NOTE
12528 || (set = single_set (XEXP (link, 0))) == 0)
12531 reg = SET_DEST (set);
12532 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12533 || GET_CODE (reg) == SIGN_EXTRACT
12534 || GET_CODE (reg) == STRICT_LOW_PART)
12535 reg = XEXP (reg, 0);
12537 /* A LOG_LINK is defined as being placed on the first insn that uses
12538 a register and points to the insn that sets the register. Start
12539 searching at the next insn after the target of the link and stop
12540 when we reach a set of the register or the end of the basic block.
12542 Note that this correctly handles the link that used to point from
12543 I3 to I2. Also note that not much searching is typically done here
12544 since most links don't point very far away. */
12546 for (insn = NEXT_INSN (XEXP (link, 0));
12547 (insn && (this_basic_block == n_basic_blocks - 1
12548 || BLOCK_HEAD (this_basic_block + 1) != insn));
12549 insn = NEXT_INSN (insn))
12550 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12552 if (reg_referenced_p (reg, PATTERN (insn)))
12556 else if (GET_CODE (insn) == CALL_INSN
12557 && find_reg_fusage (insn, USE, reg))
12563 /* If we found a place to put the link, place it there unless there
12564 is already a link to the same insn as LINK at that point. */
12570 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12571 if (XEXP (link2, 0) == XEXP (link, 0))
12576 XEXP (link, 1) = LOG_LINKS (place);
12577 LOG_LINKS (place) = link;
12579 /* Set added_links_insn to the earliest insn we added a
12581 if (added_links_insn == 0
12582 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12583 added_links_insn = place;
12589 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12595 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12596 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12597 insn = NEXT_INSN (insn);
12599 if (INSN_UID (insn) > max_uid_cuid)
12602 return INSN_CUID (insn);
12606 dump_combine_stats (file)
12611 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12612 combine_attempts, combine_merges, combine_extras, combine_successes);
12616 dump_combine_total_stats (file)
12621 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12622 total_attempts, total_merges, total_extras, total_successes);