1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
675 && CONST_INT_P (newval))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval)
680 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval))));
690 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval, 0))));
695 buf = undobuf.frees, undobuf.frees = buf->next;
697 buf = XNEW (struct undo);
699 buf->kind = UNDO_RTX;
701 buf->old_contents.r = oldval;
704 buf->next = undobuf.undos, undobuf.undos = buf;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into, int newval)
719 if (oldval == newval)
723 buf = undobuf.frees, undobuf.frees = buf->next;
725 buf = XNEW (struct undo);
727 buf->kind = UNDO_INT;
729 buf->old_contents.i = oldval;
732 buf->next = undobuf.undos, undobuf.undos = buf;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx *into, enum machine_mode newval)
746 enum machine_mode oldval = GET_MODE (*into);
748 if (oldval == newval)
752 buf = undobuf.frees, undobuf.frees = buf->next;
754 buf = XNEW (struct undo);
756 buf->kind = UNDO_MODE;
758 buf->old_contents.m = oldval;
759 adjust_reg_mode (*into, newval);
761 buf->next = undobuf.undos, undobuf.undos = buf;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
779 int i1_cost, i2_cost, i3_cost;
780 int new_i2_cost, new_i3_cost;
781 int old_cost, new_cost;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost = INSN_COST (i2);
785 i3_cost = INSN_COST (i3);
789 i1_cost = INSN_COST (i1);
790 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
791 ? i1_cost + i2_cost + i3_cost : 0;
795 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
799 /* Calculate the replacement insn_rtx_costs. */
800 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
803 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
804 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
805 ? new_i2_cost + new_i3_cost : 0;
809 new_cost = new_i3_cost;
813 if (undobuf.other_insn)
815 int old_other_cost, new_other_cost;
817 old_other_cost = INSN_COST (undobuf.other_insn);
818 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
819 if (old_other_cost > 0 && new_other_cost > 0)
821 old_cost += old_other_cost;
822 new_cost += new_other_cost;
828 /* Disallow this recombination if both new_cost and old_cost are
829 greater than zero, and new_cost is greater than old cost. */
831 && new_cost > old_cost)
838 "rejecting combination of insns %d, %d and %d\n",
839 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
840 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
841 i1_cost, i2_cost, i3_cost, old_cost);
846 "rejecting combination of insns %d and %d\n",
847 INSN_UID (i2), INSN_UID (i3));
848 fprintf (dump_file, "original costs %d + %d = %d\n",
849 i2_cost, i3_cost, old_cost);
854 fprintf (dump_file, "replacement costs %d + %d = %d\n",
855 new_i2_cost, new_i3_cost, new_cost);
858 fprintf (dump_file, "replacement cost %d\n", new_cost);
864 /* Update the uid_insn_cost array with the replacement costs. */
865 INSN_COST (i2) = new_i2_cost;
866 INSN_COST (i3) = new_i3_cost;
874 /* Delete any insns that copy a register to itself. */
877 delete_noop_moves (void)
884 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
886 next = NEXT_INSN (insn);
887 if (INSN_P (insn) && noop_move_p (insn))
890 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
892 delete_insn_and_edges (insn);
899 /* Fill in log links field for all insns. */
902 create_log_links (void)
906 df_ref *def_vec, *use_vec;
908 next_use = XCNEWVEC (rtx, max_reg_num ());
910 /* Pass through each block from the end, recording the uses of each
911 register and establishing log links when def is encountered.
912 Note that we do not clear next_use array in order to save time,
913 so we have to test whether the use is in the same basic block as def.
915 There are a few cases below when we do not consider the definition or
916 usage -- these are taken from original flow.c did. Don't ask me why it is
917 done this way; I don't know and if it works, I don't want to know. */
921 FOR_BB_INSNS_REVERSE (bb, insn)
923 if (!NONDEBUG_INSN_P (insn))
926 /* Log links are created only once. */
927 gcc_assert (!LOG_LINKS (insn));
929 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
931 df_ref def = *def_vec;
932 int regno = DF_REF_REGNO (def);
935 if (!next_use[regno])
938 /* Do not consider if it is pre/post modification in MEM. */
939 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
942 /* Do not make the log link for frame pointer. */
943 if ((regno == FRAME_POINTER_REGNUM
944 && (! reload_completed || frame_pointer_needed))
945 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
946 || (regno == HARD_FRAME_POINTER_REGNUM
947 && (! reload_completed || frame_pointer_needed))
949 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
950 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
955 use_insn = next_use[regno];
956 if (BLOCK_FOR_INSN (use_insn) == bb)
960 We don't build a LOG_LINK for hard registers contained
961 in ASM_OPERANDs. If these registers get replaced,
962 we might wind up changing the semantics of the insn,
963 even if reload can make what appear to be valid
964 assignments later. */
965 if (regno >= FIRST_PSEUDO_REGISTER
966 || asm_noperands (PATTERN (use_insn)) < 0)
968 /* Don't add duplicate links between instructions. */
970 for (links = LOG_LINKS (use_insn); links;
971 links = XEXP (links, 1))
972 if (insn == XEXP (links, 0))
976 LOG_LINKS (use_insn) =
977 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
980 next_use[regno] = NULL_RTX;
983 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
985 df_ref use = *use_vec;
986 int regno = DF_REF_REGNO (use);
988 /* Do not consider the usage of the stack pointer
990 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
993 next_use[regno] = insn;
1001 /* Clear LOG_LINKS fields of insns. */
1004 clear_log_links (void)
1008 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1010 free_INSN_LIST_list (&LOG_LINKS (insn));
1013 /* Main entry point for combiner. F is the first insn of the function.
1014 NREGS is the first unused pseudo-reg number.
1016 Return nonzero if the combiner has turned an indirect jump
1017 instruction into a direct jump. */
1019 combine_instructions (rtx f, unsigned int nregs)
1025 rtx links, nextlinks;
1027 basic_block last_bb;
1029 int new_direct_jump_p = 0;
1031 for (first = f; first && !INSN_P (first); )
1032 first = NEXT_INSN (first);
1036 combine_attempts = 0;
1039 combine_successes = 0;
1041 rtl_hooks = combine_rtl_hooks;
1043 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1045 init_recog_no_volatile ();
1047 /* Allocate array for insn info. */
1048 max_uid_known = get_max_uid ();
1049 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1050 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1052 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1054 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1055 problems when, for example, we have j <<= 1 in a loop. */
1057 nonzero_sign_valid = 0;
1058 label_tick = label_tick_ebb_start = 1;
1060 /* Scan all SETs and see if we can deduce anything about what
1061 bits are known to be zero for some registers and how many copies
1062 of the sign bit are known to exist for those registers.
1064 Also set any known values so that we can use it while searching
1065 for what bits are known to be set. */
1067 setup_incoming_promotions (first);
1068 /* Allow the entry block and the first block to fall into the same EBB.
1069 Conceptually the incoming promotions are assigned to the entry block. */
1070 last_bb = ENTRY_BLOCK_PTR;
1072 create_log_links ();
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1080 if (!single_pred_p (this_basic_block)
1081 || single_pred (this_basic_block) != last_bb)
1082 label_tick_ebb_start = label_tick;
1083 last_bb = this_basic_block;
1085 FOR_BB_INSNS (this_basic_block, insn)
1086 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1088 subst_low_luid = DF_INSN_LUID (insn);
1091 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1093 record_dead_and_set_regs (insn);
1096 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1097 if (REG_NOTE_KIND (links) == REG_INC)
1098 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1102 /* Record the current insn_rtx_cost of this instruction. */
1103 if (NONJUMP_INSN_P (insn))
1104 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1105 optimize_this_for_speed_p);
1107 fprintf(dump_file, "insn_cost %d: %d\n",
1108 INSN_UID (insn), INSN_COST (insn));
1112 nonzero_sign_valid = 1;
1114 /* Now scan all the insns in forward order. */
1115 label_tick = label_tick_ebb_start = 1;
1117 setup_incoming_promotions (first);
1118 last_bb = ENTRY_BLOCK_PTR;
1120 FOR_EACH_BB (this_basic_block)
1122 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1127 if (!single_pred_p (this_basic_block)
1128 || single_pred (this_basic_block) != last_bb)
1129 label_tick_ebb_start = label_tick;
1130 last_bb = this_basic_block;
1132 rtl_profile_for_bb (this_basic_block);
1133 for (insn = BB_HEAD (this_basic_block);
1134 insn != NEXT_INSN (BB_END (this_basic_block));
1135 insn = next ? next : NEXT_INSN (insn))
1138 if (NONDEBUG_INSN_P (insn))
1140 /* See if we know about function return values before this
1141 insn based upon SUBREG flags. */
1142 check_promoted_subreg (insn, PATTERN (insn));
1144 /* See if we can find hardregs and subreg of pseudos in
1145 narrower modes. This could help turning TRUNCATEs
1147 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1149 /* Try this insn with each insn it links back to. */
1151 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1152 if ((next = try_combine (insn, XEXP (links, 0),
1153 NULL_RTX, &new_direct_jump_p)) != 0)
1156 /* Try each sequence of three linked insns ending with this one. */
1158 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1160 rtx link = XEXP (links, 0);
1162 /* If the linked insn has been replaced by a note, then there
1163 is no point in pursuing this chain any further. */
1167 for (nextlinks = LOG_LINKS (link);
1169 nextlinks = XEXP (nextlinks, 1))
1170 if ((next = try_combine (insn, link,
1171 XEXP (nextlinks, 0),
1172 &new_direct_jump_p)) != 0)
1177 /* Try to combine a jump insn that uses CC0
1178 with a preceding insn that sets CC0, and maybe with its
1179 logical predecessor as well.
1180 This is how we make decrement-and-branch insns.
1181 We need this special code because data flow connections
1182 via CC0 do not get entered in LOG_LINKS. */
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev)))
1189 if ((next = try_combine (insn, prev,
1190 NULL_RTX, &new_direct_jump_p)) != 0)
1193 for (nextlinks = LOG_LINKS (prev); nextlinks;
1194 nextlinks = XEXP (nextlinks, 1))
1195 if ((next = try_combine (insn, prev,
1196 XEXP (nextlinks, 0),
1197 &new_direct_jump_p)) != 0)
1201 /* Do the same for an insn that explicitly references CC0. */
1202 if (NONJUMP_INSN_P (insn)
1203 && (prev = prev_nonnote_insn (insn)) != 0
1204 && NONJUMP_INSN_P (prev)
1205 && sets_cc0_p (PATTERN (prev))
1206 && GET_CODE (PATTERN (insn)) == SET
1207 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1209 if ((next = try_combine (insn, prev,
1210 NULL_RTX, &new_direct_jump_p)) != 0)
1213 for (nextlinks = LOG_LINKS (prev); nextlinks;
1214 nextlinks = XEXP (nextlinks, 1))
1215 if ((next = try_combine (insn, prev,
1216 XEXP (nextlinks, 0),
1217 &new_direct_jump_p)) != 0)
1221 /* Finally, see if any of the insns that this insn links to
1222 explicitly references CC0. If so, try this insn, that insn,
1223 and its predecessor if it sets CC0. */
1224 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1225 if (NONJUMP_INSN_P (XEXP (links, 0))
1226 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1227 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1228 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1229 && NONJUMP_INSN_P (prev)
1230 && sets_cc0_p (PATTERN (prev))
1231 && (next = try_combine (insn, XEXP (links, 0),
1232 prev, &new_direct_jump_p)) != 0)
1236 /* Try combining an insn with two different insns whose results it
1238 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1239 for (nextlinks = XEXP (links, 1); nextlinks;
1240 nextlinks = XEXP (nextlinks, 1))
1241 if ((next = try_combine (insn, XEXP (links, 0),
1242 XEXP (nextlinks, 0),
1243 &new_direct_jump_p)) != 0)
1246 /* Try this insn with each REG_EQUAL note it links back to. */
1247 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1250 rtx temp = XEXP (links, 0);
1251 if ((set = single_set (temp)) != 0
1252 && (note = find_reg_equal_equiv_note (temp)) != 0
1253 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1254 /* Avoid using a register that may already been marked
1255 dead by an earlier instruction. */
1256 && ! unmentioned_reg_p (note, SET_SRC (set))
1257 && (GET_MODE (note) == VOIDmode
1258 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1259 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1261 /* Temporarily replace the set's source with the
1262 contents of the REG_EQUAL note. The insn will
1263 be deleted or recognized by try_combine. */
1264 rtx orig = SET_SRC (set);
1265 SET_SRC (set) = note;
1267 i2mod_old_rhs = copy_rtx (orig);
1268 i2mod_new_rhs = copy_rtx (note);
1269 next = try_combine (insn, i2mod, NULL_RTX,
1270 &new_direct_jump_p);
1274 SET_SRC (set) = orig;
1279 record_dead_and_set_regs (insn);
1287 default_rtl_profile ();
1290 new_direct_jump_p |= purge_all_dead_edges ();
1291 delete_noop_moves ();
1294 free (uid_log_links);
1295 free (uid_insn_cost);
1296 VEC_free (reg_stat_type, heap, reg_stat);
1299 struct undo *undo, *next;
1300 for (undo = undobuf.frees; undo; undo = next)
1308 total_attempts += combine_attempts;
1309 total_merges += combine_merges;
1310 total_extras += combine_extras;
1311 total_successes += combine_successes;
1313 nonzero_sign_valid = 0;
1314 rtl_hooks = general_rtl_hooks;
1316 /* Make recognizer allow volatile MEMs again. */
1319 return new_direct_jump_p;
1322 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1325 init_reg_last (void)
1330 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1331 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1334 /* Set up any promoted values for incoming argument registers. */
1337 setup_incoming_promotions (rtx first)
1340 bool strictly_local = false;
1342 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1343 arg = TREE_CHAIN (arg))
1345 rtx x, reg = DECL_INCOMING_RTL (arg);
1347 enum machine_mode mode1, mode2, mode3, mode4;
1349 /* Only continue if the incoming argument is in a register. */
1353 /* Determine, if possible, whether all call sites of the current
1354 function lie within the current compilation unit. (This does
1355 take into account the exporting of a function via taking its
1356 address, and so forth.) */
1357 strictly_local = cgraph_local_info (current_function_decl)->local;
1359 /* The mode and signedness of the argument before any promotions happen
1360 (equal to the mode of the pseudo holding it at that stage). */
1361 mode1 = TYPE_MODE (TREE_TYPE (arg));
1362 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1364 /* The mode and signedness of the argument after any source language and
1365 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1366 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1367 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1369 /* The mode and signedness of the argument as it is actually passed,
1370 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1371 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1372 TREE_TYPE (cfun->decl), 0);
1374 /* The mode of the register in which the argument is being passed. */
1375 mode4 = GET_MODE (reg);
1377 /* Eliminate sign extensions in the callee when:
1378 (a) A mode promotion has occurred; */
1381 /* (b) The mode of the register is the same as the mode of
1382 the argument as it is passed; */
1385 /* (c) There's no language level extension; */
1388 /* (c.1) All callers are from the current compilation unit. If that's
1389 the case we don't have to rely on an ABI, we only have to know
1390 what we're generating right now, and we know that we will do the
1391 mode1 to mode2 promotion with the given sign. */
1392 else if (!strictly_local)
1394 /* (c.2) The combination of the two promotions is useful. This is
1395 true when the signs match, or if the first promotion is unsigned.
1396 In the later case, (sign_extend (zero_extend x)) is the same as
1397 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1403 /* Record that the value was promoted from mode1 to mode3,
1404 so that any sign extension at the head of the current
1405 function may be eliminated. */
1406 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1407 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1408 record_value_for_reg (reg, first, x);
1412 /* Called via note_stores. If X is a pseudo that is narrower than
1413 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1415 If we are setting only a portion of X and we can't figure out what
1416 portion, assume all bits will be used since we don't know what will
1419 Similarly, set how many bits of X are known to be copies of the sign bit
1420 at all locations in the function. This is the smallest number implied
1424 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1426 rtx insn = (rtx) data;
1430 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1431 /* If this register is undefined at the start of the file, we can't
1432 say what its contents were. */
1433 && ! REGNO_REG_SET_P
1434 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1435 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1437 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1439 if (set == 0 || GET_CODE (set) == CLOBBER)
1441 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1442 rsp->sign_bit_copies = 1;
1446 /* If this register is being initialized using itself, and the
1447 register is uninitialized in this basic block, and there are
1448 no LOG_LINKS which set the register, then part of the
1449 register is uninitialized. In that case we can't assume
1450 anything about the number of nonzero bits.
1452 ??? We could do better if we checked this in
1453 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1454 could avoid making assumptions about the insn which initially
1455 sets the register, while still using the information in other
1456 insns. We would have to be careful to check every insn
1457 involved in the combination. */
1460 && reg_referenced_p (x, PATTERN (insn))
1461 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1466 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1468 if (dead_or_set_p (XEXP (link, 0), x))
1473 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1474 rsp->sign_bit_copies = 1;
1479 /* If this is a complex assignment, see if we can convert it into a
1480 simple assignment. */
1481 set = expand_field_assignment (set);
1483 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1484 set what we know about X. */
1486 if (SET_DEST (set) == x
1487 || (GET_CODE (SET_DEST (set)) == SUBREG
1488 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1489 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1490 && SUBREG_REG (SET_DEST (set)) == x))
1492 rtx src = SET_SRC (set);
1494 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1495 /* If X is narrower than a word and SRC is a non-negative
1496 constant that would appear negative in the mode of X,
1497 sign-extend it for use in reg_stat[].nonzero_bits because some
1498 machines (maybe most) will actually do the sign-extension
1499 and this is the conservative approach.
1501 ??? For 2.5, try to tighten up the MD files in this regard
1502 instead of this kludge. */
1504 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1505 && CONST_INT_P (src)
1507 && 0 != (INTVAL (src)
1508 & ((HOST_WIDE_INT) 1
1509 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1510 src = GEN_INT (INTVAL (src)
1511 | ((HOST_WIDE_INT) (-1)
1512 << GET_MODE_BITSIZE (GET_MODE (x))));
1515 /* Don't call nonzero_bits if it cannot change anything. */
1516 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1517 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1518 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1519 if (rsp->sign_bit_copies == 0
1520 || rsp->sign_bit_copies > num)
1521 rsp->sign_bit_copies = num;
1525 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1526 rsp->sign_bit_copies = 1;
1531 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1532 insns that were previously combined into I3 or that will be combined
1533 into the merger of INSN and I3.
1535 Return 0 if the combination is not allowed for any reason.
1537 If the combination is allowed, *PDEST will be set to the single
1538 destination of INSN and *PSRC to the single source, and this function
1542 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1543 rtx *pdest, rtx *psrc)
1552 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1553 && next_active_insn (succ) == i3)
1554 : next_active_insn (insn) == i3);
1556 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1557 or a PARALLEL consisting of such a SET and CLOBBERs.
1559 If INSN has CLOBBER parallel parts, ignore them for our processing.
1560 By definition, these happen during the execution of the insn. When it
1561 is merged with another insn, all bets are off. If they are, in fact,
1562 needed and aren't also supplied in I3, they may be added by
1563 recog_for_combine. Otherwise, it won't match.
1565 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1568 Get the source and destination of INSN. If more than one, can't
1571 if (GET_CODE (PATTERN (insn)) == SET)
1572 set = PATTERN (insn);
1573 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1574 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1576 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1578 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1580 switch (GET_CODE (elt))
1582 /* This is important to combine floating point insns
1583 for the SH4 port. */
1585 /* Combining an isolated USE doesn't make sense.
1586 We depend here on combinable_i3pat to reject them. */
1587 /* The code below this loop only verifies that the inputs of
1588 the SET in INSN do not change. We call reg_set_between_p
1589 to verify that the REG in the USE does not change between
1591 If the USE in INSN was for a pseudo register, the matching
1592 insn pattern will likely match any register; combining this
1593 with any other USE would only be safe if we knew that the
1594 used registers have identical values, or if there was
1595 something to tell them apart, e.g. different modes. For
1596 now, we forgo such complicated tests and simply disallow
1597 combining of USES of pseudo registers with any other USE. */
1598 if (REG_P (XEXP (elt, 0))
1599 && GET_CODE (PATTERN (i3)) == PARALLEL)
1601 rtx i3pat = PATTERN (i3);
1602 int i = XVECLEN (i3pat, 0) - 1;
1603 unsigned int regno = REGNO (XEXP (elt, 0));
1607 rtx i3elt = XVECEXP (i3pat, 0, i);
1609 if (GET_CODE (i3elt) == USE
1610 && REG_P (XEXP (i3elt, 0))
1611 && (REGNO (XEXP (i3elt, 0)) == regno
1612 ? reg_set_between_p (XEXP (elt, 0),
1613 PREV_INSN (insn), i3)
1614 : regno >= FIRST_PSEUDO_REGISTER))
1621 /* We can ignore CLOBBERs. */
1626 /* Ignore SETs whose result isn't used but not those that
1627 have side-effects. */
1628 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1629 && insn_nothrow_p (insn)
1630 && !side_effects_p (elt))
1633 /* If we have already found a SET, this is a second one and
1634 so we cannot combine with this insn. */
1642 /* Anything else means we can't combine. */
1648 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1649 so don't do anything with it. */
1650 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1659 set = expand_field_assignment (set);
1660 src = SET_SRC (set), dest = SET_DEST (set);
1662 /* Don't eliminate a store in the stack pointer. */
1663 if (dest == stack_pointer_rtx
1664 /* Don't combine with an insn that sets a register to itself if it has
1665 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1666 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1667 /* Can't merge an ASM_OPERANDS. */
1668 || GET_CODE (src) == ASM_OPERANDS
1669 /* Can't merge a function call. */
1670 || GET_CODE (src) == CALL
1671 /* Don't eliminate a function call argument. */
1673 && (find_reg_fusage (i3, USE, dest)
1675 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1676 && global_regs[REGNO (dest)])))
1677 /* Don't substitute into an incremented register. */
1678 || FIND_REG_INC_NOTE (i3, dest)
1679 || (succ && FIND_REG_INC_NOTE (succ, dest))
1680 /* Don't substitute into a non-local goto, this confuses CFG. */
1681 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1682 /* Make sure that DEST is not used after SUCC but before I3. */
1683 || (succ && ! all_adjacent
1684 && reg_used_between_p (dest, succ, i3))
1685 /* Make sure that the value that is to be substituted for the register
1686 does not use any registers whose values alter in between. However,
1687 If the insns are adjacent, a use can't cross a set even though we
1688 think it might (this can happen for a sequence of insns each setting
1689 the same destination; last_set of that register might point to
1690 a NOTE). If INSN has a REG_EQUIV note, the register is always
1691 equivalent to the memory so the substitution is valid even if there
1692 are intervening stores. Also, don't move a volatile asm or
1693 UNSPEC_VOLATILE across any other insns. */
1696 || ! find_reg_note (insn, REG_EQUIV, src))
1697 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1698 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1699 || GET_CODE (src) == UNSPEC_VOLATILE))
1700 /* Don't combine across a CALL_INSN, because that would possibly
1701 change whether the life span of some REGs crosses calls or not,
1702 and it is a pain to update that information.
1703 Exception: if source is a constant, moving it later can't hurt.
1704 Accept that as a special case. */
1705 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1708 /* DEST must either be a REG or CC0. */
1711 /* If register alignment is being enforced for multi-word items in all
1712 cases except for parameters, it is possible to have a register copy
1713 insn referencing a hard register that is not allowed to contain the
1714 mode being copied and which would not be valid as an operand of most
1715 insns. Eliminate this problem by not combining with such an insn.
1717 Also, on some machines we don't want to extend the life of a hard
1721 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1722 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1723 /* Don't extend the life of a hard register unless it is
1724 user variable (if we have few registers) or it can't
1725 fit into the desired register (meaning something special
1727 Also avoid substituting a return register into I3, because
1728 reload can't handle a conflict with constraints of other
1730 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1731 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1734 else if (GET_CODE (dest) != CC0)
1738 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1739 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1740 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1742 /* Don't substitute for a register intended as a clobberable
1744 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1745 if (rtx_equal_p (reg, dest))
1748 /* If the clobber represents an earlyclobber operand, we must not
1749 substitute an expression containing the clobbered register.
1750 As we do not analyze the constraint strings here, we have to
1751 make the conservative assumption. However, if the register is
1752 a fixed hard reg, the clobber cannot represent any operand;
1753 we leave it up to the machine description to either accept or
1754 reject use-and-clobber patterns. */
1756 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1757 || !fixed_regs[REGNO (reg)])
1758 if (reg_overlap_mentioned_p (reg, src))
1762 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1763 or not), reject, unless nothing volatile comes between it and I3 */
1765 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1767 /* Make sure succ doesn't contain a volatile reference. */
1768 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1772 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1776 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1777 to be an explicit register variable, and was chosen for a reason. */
1779 if (GET_CODE (src) == ASM_OPERANDS
1780 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1783 /* If there are any volatile insns between INSN and I3, reject, because
1784 they might affect machine state. */
1786 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1787 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1790 /* If INSN contains an autoincrement or autodecrement, make sure that
1791 register is not used between there and I3, and not already used in
1792 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1793 Also insist that I3 not be a jump; if it were one
1794 and the incremented register were spilled, we would lose. */
1797 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1798 if (REG_NOTE_KIND (link) == REG_INC
1800 || reg_used_between_p (XEXP (link, 0), insn, i3)
1801 || (pred != NULL_RTX
1802 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1803 || (succ != NULL_RTX
1804 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1805 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1810 /* Don't combine an insn that follows a CC0-setting insn.
1811 An insn that uses CC0 must not be separated from the one that sets it.
1812 We do, however, allow I2 to follow a CC0-setting insn if that insn
1813 is passed as I1; in that case it will be deleted also.
1814 We also allow combining in this case if all the insns are adjacent
1815 because that would leave the two CC0 insns adjacent as well.
1816 It would be more logical to test whether CC0 occurs inside I1 or I2,
1817 but that would be much slower, and this ought to be equivalent. */
1819 p = prev_nonnote_insn (insn);
1820 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1825 /* If we get here, we have passed all the tests and the combination is
1834 /* LOC is the location within I3 that contains its pattern or the component
1835 of a PARALLEL of the pattern. We validate that it is valid for combining.
1837 One problem is if I3 modifies its output, as opposed to replacing it
1838 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1839 so would produce an insn that is not equivalent to the original insns.
1843 (set (reg:DI 101) (reg:DI 100))
1844 (set (subreg:SI (reg:DI 101) 0) <foo>)
1846 This is NOT equivalent to:
1848 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1849 (set (reg:DI 101) (reg:DI 100))])
1851 Not only does this modify 100 (in which case it might still be valid
1852 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1854 We can also run into a problem if I2 sets a register that I1
1855 uses and I1 gets directly substituted into I3 (not via I2). In that
1856 case, we would be getting the wrong value of I2DEST into I3, so we
1857 must reject the combination. This case occurs when I2 and I1 both
1858 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1859 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1860 of a SET must prevent combination from occurring.
1862 Before doing the above check, we first try to expand a field assignment
1863 into a set of logical operations.
1865 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1866 we place a register that is both set and used within I3. If more than one
1867 such register is detected, we fail.
1869 Return 1 if the combination is valid, zero otherwise. */
1872 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1873 int i1_not_in_src, rtx *pi3dest_killed)
1877 if (GET_CODE (x) == SET)
1880 rtx dest = SET_DEST (set);
1881 rtx src = SET_SRC (set);
1882 rtx inner_dest = dest;
1885 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1886 || GET_CODE (inner_dest) == SUBREG
1887 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1888 inner_dest = XEXP (inner_dest, 0);
1890 /* Check for the case where I3 modifies its output, as discussed
1891 above. We don't want to prevent pseudos from being combined
1892 into the address of a MEM, so only prevent the combination if
1893 i1 or i2 set the same MEM. */
1894 if ((inner_dest != dest &&
1895 (!MEM_P (inner_dest)
1896 || rtx_equal_p (i2dest, inner_dest)
1897 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1898 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1899 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1901 /* This is the same test done in can_combine_p except we can't test
1902 all_adjacent; we don't have to, since this instruction will stay
1903 in place, thus we are not considering increasing the lifetime of
1906 Also, if this insn sets a function argument, combining it with
1907 something that might need a spill could clobber a previous
1908 function argument; the all_adjacent test in can_combine_p also
1909 checks this; here, we do a more specific test for this case. */
1911 || (REG_P (inner_dest)
1912 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1913 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1914 GET_MODE (inner_dest))))
1915 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1918 /* If DEST is used in I3, it is being killed in this insn, so
1919 record that for later. We have to consider paradoxical
1920 subregs here, since they kill the whole register, but we
1921 ignore partial subregs, STRICT_LOW_PART, etc.
1922 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1923 STACK_POINTER_REGNUM, since these are always considered to be
1924 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1926 if (GET_CODE (subdest) == SUBREG
1927 && (GET_MODE_SIZE (GET_MODE (subdest))
1928 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1929 subdest = SUBREG_REG (subdest);
1932 && reg_referenced_p (subdest, PATTERN (i3))
1933 && REGNO (subdest) != FRAME_POINTER_REGNUM
1934 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1935 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1937 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1938 && (REGNO (subdest) != ARG_POINTER_REGNUM
1939 || ! fixed_regs [REGNO (subdest)])
1941 && REGNO (subdest) != STACK_POINTER_REGNUM)
1943 if (*pi3dest_killed)
1946 *pi3dest_killed = subdest;
1950 else if (GET_CODE (x) == PARALLEL)
1954 for (i = 0; i < XVECLEN (x, 0); i++)
1955 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1956 i1_not_in_src, pi3dest_killed))
1963 /* Return 1 if X is an arithmetic expression that contains a multiplication
1964 and division. We don't count multiplications by powers of two here. */
1967 contains_muldiv (rtx x)
1969 switch (GET_CODE (x))
1971 case MOD: case DIV: case UMOD: case UDIV:
1975 return ! (CONST_INT_P (XEXP (x, 1))
1976 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1979 return contains_muldiv (XEXP (x, 0))
1980 || contains_muldiv (XEXP (x, 1));
1983 return contains_muldiv (XEXP (x, 0));
1989 /* Determine whether INSN can be used in a combination. Return nonzero if
1990 not. This is used in try_combine to detect early some cases where we
1991 can't perform combinations. */
1994 cant_combine_insn_p (rtx insn)
1999 /* If this isn't really an insn, we can't do anything.
2000 This can occur when flow deletes an insn that it has merged into an
2001 auto-increment address. */
2002 if (! INSN_P (insn))
2005 /* Never combine loads and stores involving hard regs that are likely
2006 to be spilled. The register allocator can usually handle such
2007 reg-reg moves by tying. If we allow the combiner to make
2008 substitutions of likely-spilled regs, reload might die.
2009 As an exception, we allow combinations involving fixed regs; these are
2010 not available to the register allocator so there's no risk involved. */
2012 set = single_set (insn);
2015 src = SET_SRC (set);
2016 dest = SET_DEST (set);
2017 if (GET_CODE (src) == SUBREG)
2018 src = SUBREG_REG (src);
2019 if (GET_CODE (dest) == SUBREG)
2020 dest = SUBREG_REG (dest);
2021 if (REG_P (src) && REG_P (dest)
2022 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2023 && ! fixed_regs[REGNO (src)]
2024 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2025 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2026 && ! fixed_regs[REGNO (dest)]
2027 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2033 struct likely_spilled_retval_info
2035 unsigned regno, nregs;
2039 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2040 hard registers that are known to be written to / clobbered in full. */
2042 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2044 struct likely_spilled_retval_info *const info =
2045 (struct likely_spilled_retval_info *) data;
2046 unsigned regno, nregs;
2049 if (!REG_P (XEXP (set, 0)))
2052 if (regno >= info->regno + info->nregs)
2054 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2055 if (regno + nregs <= info->regno)
2057 new_mask = (2U << (nregs - 1)) - 1;
2058 if (regno < info->regno)
2059 new_mask >>= info->regno - regno;
2061 new_mask <<= regno - info->regno;
2062 info->mask &= ~new_mask;
2065 /* Return nonzero iff part of the return value is live during INSN, and
2066 it is likely spilled. This can happen when more than one insn is needed
2067 to copy the return value, e.g. when we consider to combine into the
2068 second copy insn for a complex value. */
2071 likely_spilled_retval_p (rtx insn)
2073 rtx use = BB_END (this_basic_block);
2075 unsigned regno, nregs;
2076 /* We assume here that no machine mode needs more than
2077 32 hard registers when the value overlaps with a register
2078 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2080 struct likely_spilled_retval_info info;
2082 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2084 reg = XEXP (PATTERN (use), 0);
2085 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2087 regno = REGNO (reg);
2088 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2091 mask = (2U << (nregs - 1)) - 1;
2093 /* Disregard parts of the return value that are set later. */
2097 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2099 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2102 /* Check if any of the (probably) live return value registers is
2107 if ((mask & 1 << nregs)
2108 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2114 /* Adjust INSN after we made a change to its destination.
2116 Changing the destination can invalidate notes that say something about
2117 the results of the insn and a LOG_LINK pointing to the insn. */
2120 adjust_for_new_dest (rtx insn)
2122 /* For notes, be conservative and simply remove them. */
2123 remove_reg_equal_equiv_notes (insn);
2125 /* The new insn will have a destination that was previously the destination
2126 of an insn just above it. Call distribute_links to make a LOG_LINK from
2127 the next use of that destination. */
2128 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2130 df_insn_rescan (insn);
2133 /* Return TRUE if combine can reuse reg X in mode MODE.
2134 ADDED_SETS is nonzero if the original set is still required. */
2136 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2144 /* Allow hard registers if the new mode is legal, and occupies no more
2145 registers than the old mode. */
2146 if (regno < FIRST_PSEUDO_REGISTER)
2147 return (HARD_REGNO_MODE_OK (regno, mode)
2148 && (hard_regno_nregs[regno][GET_MODE (x)]
2149 >= hard_regno_nregs[regno][mode]));
2151 /* Or a pseudo that is only used once. */
2152 return (REG_N_SETS (regno) == 1 && !added_sets
2153 && !REG_USERVAR_P (x));
2157 /* Check whether X, the destination of a set, refers to part of
2158 the register specified by REG. */
2161 reg_subword_p (rtx x, rtx reg)
2163 /* Check that reg is an integer mode register. */
2164 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2167 if (GET_CODE (x) == STRICT_LOW_PART
2168 || GET_CODE (x) == ZERO_EXTRACT)
2171 return GET_CODE (x) == SUBREG
2172 && SUBREG_REG (x) == reg
2173 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2177 /* Replace auto-increment addressing modes with explicit operations to
2178 access the same addresses without modifying the corresponding
2179 registers. If AFTER holds, SRC is meant to be reused after the
2180 side effect, otherwise it is to be reused before that. */
2183 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2186 const RTX_CODE code = GET_CODE (x);
2202 /* SCRATCH must be shared because they represent distinct values. */
2205 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2210 if (shared_const_p (x))
2215 mem_mode = GET_MODE (x);
2222 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2223 if (after == (code == PRE_INC || code == PRE_DEC))
2224 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2226 x = gen_rtx_PLUS (GET_MODE (x),
2227 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2228 GEN_INT ((code == PRE_INC || code == POST_INC)
2229 ? GET_MODE_SIZE (mem_mode)
2230 : -GET_MODE_SIZE (mem_mode)));
2235 if (after == (code == PRE_MODIFY))
2239 return cleanup_auto_inc_dec (x, after, mem_mode);
2245 /* Copy the various flags, fields, and other information. We assume
2246 that all fields need copying, and then clear the fields that should
2247 not be copied. That is the sensible default behavior, and forces
2248 us to explicitly document why we are *not* copying a flag. */
2249 x = shallow_copy_rtx (x);
2251 /* We do not copy the USED flag, which is used as a mark bit during
2252 walks over the RTL. */
2253 RTX_FLAG (x, used) = 0;
2255 /* We do not copy FRAME_RELATED for INSNs. */
2257 RTX_FLAG (x, frame_related) = 0;
2259 fmt = GET_RTX_FORMAT (code);
2260 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2262 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2263 else if (fmt[i] == 'E' || fmt[i] == 'V')
2266 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2267 for (j = 0; j < XVECLEN (x, i); j++)
2269 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2275 /* Auxiliary data structure for propagate_for_debug_stmt. */
2277 struct rtx_subst_pair
2284 /* DATA points to an rtx_subst_pair. Return the value that should be
2288 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2290 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2292 if (!rtx_equal_p (from, old_rtx))
2294 if (!pair->adjusted)
2296 pair->adjusted = true;
2297 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2300 return copy_rtx (pair->to);
2304 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2305 and LAST. If MOVE holds, debug insns must also be moved past
2309 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2311 rtx next, move_pos = move ? last : NULL_RTX, loc;
2315 struct rtx_subst_pair p;
2322 next = NEXT_INSN (insn);
2323 while (next != last)
2326 next = NEXT_INSN (insn);
2327 if (DEBUG_INSN_P (insn))
2331 src = make_compound_operation (src, SET);
2335 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2336 dest, propagate_for_debug_subst, &p);
2338 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2340 if (loc == INSN_VAR_LOCATION_LOC (insn))
2342 INSN_VAR_LOCATION_LOC (insn) = loc;
2346 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2347 move_pos = emit_debug_insn_after (insn, move_pos);
2350 df_insn_rescan (insn);
2355 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2356 Note that the INSN should be deleted *after* removing dead edges, so
2357 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2358 but not for a (set (pc) (label_ref FOO)). */
2361 update_cfg_for_uncondjump (rtx insn)
2363 basic_block bb = BLOCK_FOR_INSN (insn);
2364 bool at_end = (BB_END (bb) == insn);
2367 purge_dead_edges (bb);
2370 if (at_end && EDGE_COUNT (bb->succs) == 1)
2371 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2375 /* Try to combine the insns I1 and I2 into I3.
2376 Here I1 and I2 appear earlier than I3.
2377 I1 can be zero; then we combine just I2 into I3.
2379 If we are combining three insns and the resulting insn is not recognized,
2380 try splitting it into two insns. If that happens, I2 and I3 are retained
2381 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2384 Return 0 if the combination does not work. Then nothing is changed.
2385 If we did the combination, return the insn at which combine should
2388 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2389 new direct jump instruction. */
2392 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2394 /* New patterns for I3 and I2, respectively. */
2395 rtx newpat, newi2pat = 0;
2396 rtvec newpat_vec_with_clobbers = 0;
2397 int substed_i2 = 0, substed_i1 = 0;
2398 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2399 int added_sets_1, added_sets_2;
2400 /* Total number of SETs to put into I3. */
2402 /* Nonzero if I2's body now appears in I3. */
2404 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2405 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2406 /* Contains I3 if the destination of I3 is used in its source, which means
2407 that the old life of I3 is being killed. If that usage is placed into
2408 I2 and not in I3, a REG_DEAD note must be made. */
2409 rtx i3dest_killed = 0;
2410 /* SET_DEST and SET_SRC of I2 and I1. */
2411 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2412 /* Set if I2DEST was reused as a scratch register. */
2413 bool i2scratch = false;
2414 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2415 rtx i1pat = 0, i2pat = 0;
2416 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2417 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2418 int i2dest_killed = 0, i1dest_killed = 0;
2419 int i1_feeds_i3 = 0;
2420 /* Notes that must be added to REG_NOTES in I3 and I2. */
2421 rtx new_i3_notes, new_i2_notes;
2422 /* Notes that we substituted I3 into I2 instead of the normal case. */
2423 int i3_subst_into_i2 = 0;
2424 /* Notes that I1, I2 or I3 is a MULT operation. */
2427 int changed_i3_dest = 0;
2433 rtx new_other_notes;
2436 /* Exit early if one of the insns involved can't be used for
2438 if (cant_combine_insn_p (i3)
2439 || cant_combine_insn_p (i2)
2440 || (i1 && cant_combine_insn_p (i1))
2441 || likely_spilled_retval_p (i3))
2445 undobuf.other_insn = 0;
2447 /* Reset the hard register usage information. */
2448 CLEAR_HARD_REG_SET (newpat_used_regs);
2450 if (dump_file && (dump_flags & TDF_DETAILS))
2453 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2454 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2456 fprintf (dump_file, "\nTrying %d -> %d:\n",
2457 INSN_UID (i2), INSN_UID (i3));
2460 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2461 code below, set I1 to be the earlier of the two insns. */
2462 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2463 temp = i1, i1 = i2, i2 = temp;
2465 added_links_insn = 0;
2467 /* First check for one important special-case that the code below will
2468 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2469 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2470 we may be able to replace that destination with the destination of I3.
2471 This occurs in the common code where we compute both a quotient and
2472 remainder into a structure, in which case we want to do the computation
2473 directly into the structure to avoid register-register copies.
2475 Note that this case handles both multiple sets in I2 and also
2476 cases where I2 has a number of CLOBBER or PARALLELs.
2478 We make very conservative checks below and only try to handle the
2479 most common cases of this. For example, we only handle the case
2480 where I2 and I3 are adjacent to avoid making difficult register
2483 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2484 && REG_P (SET_SRC (PATTERN (i3)))
2485 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2486 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2487 && GET_CODE (PATTERN (i2)) == PARALLEL
2488 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2489 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2490 below would need to check what is inside (and reg_overlap_mentioned_p
2491 doesn't support those codes anyway). Don't allow those destinations;
2492 the resulting insn isn't likely to be recognized anyway. */
2493 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2494 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2495 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2496 SET_DEST (PATTERN (i3)))
2497 && next_active_insn (i2) == i3)
2499 rtx p2 = PATTERN (i2);
2501 /* Make sure that the destination of I3,
2502 which we are going to substitute into one output of I2,
2503 is not used within another output of I2. We must avoid making this:
2504 (parallel [(set (mem (reg 69)) ...)
2505 (set (reg 69) ...)])
2506 which is not well-defined as to order of actions.
2507 (Besides, reload can't handle output reloads for this.)
2509 The problem can also happen if the dest of I3 is a memory ref,
2510 if another dest in I2 is an indirect memory ref. */
2511 for (i = 0; i < XVECLEN (p2, 0); i++)
2512 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2513 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2514 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2515 SET_DEST (XVECEXP (p2, 0, i))))
2518 if (i == XVECLEN (p2, 0))
2519 for (i = 0; i < XVECLEN (p2, 0); i++)
2520 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2521 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2522 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2527 subst_low_luid = DF_INSN_LUID (i2);
2529 added_sets_2 = added_sets_1 = 0;
2530 i2src = SET_DEST (PATTERN (i3));
2531 i2dest = SET_SRC (PATTERN (i3));
2532 i2dest_killed = dead_or_set_p (i2, i2dest);
2534 /* Replace the dest in I2 with our dest and make the resulting
2535 insn the new pattern for I3. Then skip to where we
2536 validate the pattern. Everything was set up above. */
2537 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2538 SET_DEST (PATTERN (i3)));
2541 i3_subst_into_i2 = 1;
2542 goto validate_replacement;
2546 /* If I2 is setting a pseudo to a constant and I3 is setting some
2547 sub-part of it to another constant, merge them by making a new
2550 && (temp = single_set (i2)) != 0
2551 && (CONST_INT_P (SET_SRC (temp))
2552 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2553 && GET_CODE (PATTERN (i3)) == SET
2554 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2555 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2556 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2558 rtx dest = SET_DEST (PATTERN (i3));
2562 if (GET_CODE (dest) == ZERO_EXTRACT)
2564 if (CONST_INT_P (XEXP (dest, 1))
2565 && CONST_INT_P (XEXP (dest, 2)))
2567 width = INTVAL (XEXP (dest, 1));
2568 offset = INTVAL (XEXP (dest, 2));
2569 dest = XEXP (dest, 0);
2570 if (BITS_BIG_ENDIAN)
2571 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2576 if (GET_CODE (dest) == STRICT_LOW_PART)
2577 dest = XEXP (dest, 0);
2578 width = GET_MODE_BITSIZE (GET_MODE (dest));
2584 /* If this is the low part, we're done. */
2585 if (subreg_lowpart_p (dest))
2587 /* Handle the case where inner is twice the size of outer. */
2588 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2589 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2590 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2591 /* Otherwise give up for now. */
2597 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2598 <= HOST_BITS_PER_DOUBLE_INT))
2601 rtx inner = SET_SRC (PATTERN (i3));
2602 rtx outer = SET_SRC (temp);
2604 o = rtx_to_double_int (outer);
2605 i = rtx_to_double_int (inner);
2607 m = double_int_mask (width);
2608 i = double_int_and (i, m);
2609 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2610 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2611 o = double_int_ior (double_int_and (o, double_int_not (m)), i);
2615 subst_low_luid = DF_INSN_LUID (i2);
2616 added_sets_2 = added_sets_1 = 0;
2617 i2dest = SET_DEST (temp);
2618 i2dest_killed = dead_or_set_p (i2, i2dest);
2620 /* Replace the source in I2 with the new constant and make the
2621 resulting insn the new pattern for I3. Then skip to where we
2622 validate the pattern. Everything was set up above. */
2623 SUBST (SET_SRC (temp),
2624 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2626 newpat = PATTERN (i2);
2628 /* The dest of I3 has been replaced with the dest of I2. */
2629 changed_i3_dest = 1;
2630 goto validate_replacement;
2635 /* If we have no I1 and I2 looks like:
2636 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2638 make up a dummy I1 that is
2641 (set (reg:CC X) (compare:CC Y (const_int 0)))
2643 (We can ignore any trailing CLOBBERs.)
2645 This undoes a previous combination and allows us to match a branch-and-
2648 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2649 && XVECLEN (PATTERN (i2), 0) >= 2
2650 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2651 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2653 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2654 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2655 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2656 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2657 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2658 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2660 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2661 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2666 /* We make I1 with the same INSN_UID as I2. This gives it
2667 the same DF_INSN_LUID for value tracking. Our fake I1 will
2668 never appear in the insn stream so giving it the same INSN_UID
2669 as I2 will not cause a problem. */
2671 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2672 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2673 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2675 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2676 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2677 SET_DEST (PATTERN (i1)));
2682 /* Verify that I2 and I1 are valid for combining. */
2683 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2684 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2690 /* Record whether I2DEST is used in I2SRC and similarly for the other
2691 cases. Knowing this will help in register status updating below. */
2692 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2693 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2694 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2695 i2dest_killed = dead_or_set_p (i2, i2dest);
2696 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2698 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2700 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2702 /* Ensure that I3's pattern can be the destination of combines. */
2703 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2704 i1 && i2dest_in_i1src && i1_feeds_i3,
2711 /* See if any of the insns is a MULT operation. Unless one is, we will
2712 reject a combination that is, since it must be slower. Be conservative
2714 if (GET_CODE (i2src) == MULT
2715 || (i1 != 0 && GET_CODE (i1src) == MULT)
2716 || (GET_CODE (PATTERN (i3)) == SET
2717 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2720 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2721 We used to do this EXCEPT in one case: I3 has a post-inc in an
2722 output operand. However, that exception can give rise to insns like
2724 which is a famous insn on the PDP-11 where the value of r3 used as the
2725 source was model-dependent. Avoid this sort of thing. */
2728 if (!(GET_CODE (PATTERN (i3)) == SET
2729 && REG_P (SET_SRC (PATTERN (i3)))
2730 && MEM_P (SET_DEST (PATTERN (i3)))
2731 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2732 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2733 /* It's not the exception. */
2736 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2737 if (REG_NOTE_KIND (link) == REG_INC
2738 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2740 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2747 /* See if the SETs in I1 or I2 need to be kept around in the merged
2748 instruction: whenever the value set there is still needed past I3.
2749 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2751 For the SET in I1, we have two cases: If I1 and I2 independently
2752 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2753 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2754 in I1 needs to be kept around unless I1DEST dies or is set in either
2755 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2756 I1DEST. If so, we know I1 feeds into I2. */
2758 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2761 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2762 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2764 /* If the set in I2 needs to be kept around, we must make a copy of
2765 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2766 PATTERN (I2), we are only substituting for the original I1DEST, not into
2767 an already-substituted copy. This also prevents making self-referential
2768 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2773 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2774 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2776 i2pat = copy_rtx (PATTERN (i2));
2781 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2782 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2784 i1pat = copy_rtx (PATTERN (i1));
2789 /* Substitute in the latest insn for the regs set by the earlier ones. */
2791 maxreg = max_reg_num ();
2796 /* Many machines that don't use CC0 have insns that can both perform an
2797 arithmetic operation and set the condition code. These operations will
2798 be represented as a PARALLEL with the first element of the vector
2799 being a COMPARE of an arithmetic operation with the constant zero.
2800 The second element of the vector will set some pseudo to the result
2801 of the same arithmetic operation. If we simplify the COMPARE, we won't
2802 match such a pattern and so will generate an extra insn. Here we test
2803 for this case, where both the comparison and the operation result are
2804 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2805 I2SRC. Later we will make the PARALLEL that contains I2. */
2807 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2808 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2809 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2810 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2812 #ifdef SELECT_CC_MODE
2814 enum machine_mode compare_mode;
2817 newpat = PATTERN (i3);
2818 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2822 #ifdef SELECT_CC_MODE
2823 /* See if a COMPARE with the operand we substituted in should be done
2824 with the mode that is currently being used. If not, do the same
2825 processing we do in `subst' for a SET; namely, if the destination
2826 is used only once, try to replace it with a register of the proper
2827 mode and also replace the COMPARE. */
2828 if (undobuf.other_insn == 0
2829 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2830 &undobuf.other_insn))
2831 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2833 != GET_MODE (SET_DEST (newpat))))
2835 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2838 unsigned int regno = REGNO (SET_DEST (newpat));
2841 if (regno < FIRST_PSEUDO_REGISTER)
2842 new_dest = gen_rtx_REG (compare_mode, regno);
2845 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2846 new_dest = regno_reg_rtx[regno];
2849 SUBST (SET_DEST (newpat), new_dest);
2850 SUBST (XEXP (*cc_use, 0), new_dest);
2851 SUBST (SET_SRC (newpat),
2852 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2855 undobuf.other_insn = 0;
2862 /* It is possible that the source of I2 or I1 may be performing
2863 an unneeded operation, such as a ZERO_EXTEND of something
2864 that is known to have the high part zero. Handle that case
2865 by letting subst look at the innermost one of them.
2867 Another way to do this would be to have a function that tries
2868 to simplify a single insn instead of merging two or more
2869 insns. We don't do this because of the potential of infinite
2870 loops and because of the potential extra memory required.
2871 However, doing it the way we are is a bit of a kludge and
2872 doesn't catch all cases.
2874 But only do this if -fexpensive-optimizations since it slows
2875 things down and doesn't usually win.
2877 This is not done in the COMPARE case above because the
2878 unmodified I2PAT is used in the PARALLEL and so a pattern
2879 with a modified I2SRC would not match. */
2881 if (flag_expensive_optimizations)
2883 /* Pass pc_rtx so no substitutions are done, just
2887 subst_low_luid = DF_INSN_LUID (i1);
2888 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2892 subst_low_luid = DF_INSN_LUID (i2);
2893 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2897 n_occurrences = 0; /* `subst' counts here */
2899 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2900 need to make a unique copy of I2SRC each time we substitute it
2901 to avoid self-referential rtl. */
2903 subst_low_luid = DF_INSN_LUID (i2);
2904 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2905 ! i1_feeds_i3 && i1dest_in_i1src);
2908 /* Record whether i2's body now appears within i3's body. */
2909 i2_is_used = n_occurrences;
2912 /* If we already got a failure, don't try to do more. Otherwise,
2913 try to substitute in I1 if we have it. */
2915 if (i1 && GET_CODE (newpat) != CLOBBER)
2917 /* Check that an autoincrement side-effect on I1 has not been lost.
2918 This happens if I1DEST is mentioned in I2 and dies there, and
2919 has disappeared from the new pattern. */
2920 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2922 && dead_or_set_p (i2, i1dest)
2923 && !reg_overlap_mentioned_p (i1dest, newpat))
2924 /* Before we can do this substitution, we must redo the test done
2925 above (see detailed comments there) that ensures that I1DEST
2926 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2927 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2934 subst_low_luid = DF_INSN_LUID (i1);
2935 newpat = subst (newpat, i1dest, i1src, 0, 0);
2939 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2940 to count all the ways that I2SRC and I1SRC can be used. */
2941 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2942 && i2_is_used + added_sets_2 > 1)
2943 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2944 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2946 /* Fail if we tried to make a new register. */
2947 || max_reg_num () != maxreg
2948 /* Fail if we couldn't do something and have a CLOBBER. */
2949 || GET_CODE (newpat) == CLOBBER
2950 /* Fail if this new pattern is a MULT and we didn't have one before
2951 at the outer level. */
2952 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2959 /* If the actions of the earlier insns must be kept
2960 in addition to substituting them into the latest one,
2961 we must make a new PARALLEL for the latest insn
2962 to hold additional the SETs. */
2964 if (added_sets_1 || added_sets_2)
2968 if (GET_CODE (newpat) == PARALLEL)
2970 rtvec old = XVEC (newpat, 0);
2971 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2972 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2973 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2974 sizeof (old->elem[0]) * old->num_elem);
2979 total_sets = 1 + added_sets_1 + added_sets_2;
2980 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2981 XVECEXP (newpat, 0, 0) = old;
2985 XVECEXP (newpat, 0, --total_sets) = i1pat;
2989 /* If there is no I1, use I2's body as is. We used to also not do
2990 the subst call below if I2 was substituted into I3,
2991 but that could lose a simplification. */
2993 XVECEXP (newpat, 0, --total_sets) = i2pat;
2995 /* See comment where i2pat is assigned. */
2996 XVECEXP (newpat, 0, --total_sets)
2997 = subst (i2pat, i1dest, i1src, 0, 0);
3001 validate_replacement:
3003 /* Note which hard regs this insn has as inputs. */
3004 mark_used_regs_combine (newpat);
3006 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3007 consider splitting this pattern, we might need these clobbers. */
3008 if (i1 && GET_CODE (newpat) == PARALLEL
3009 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3011 int len = XVECLEN (newpat, 0);
3013 newpat_vec_with_clobbers = rtvec_alloc (len);
3014 for (i = 0; i < len; i++)
3015 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3018 /* Is the result of combination a valid instruction? */
3019 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3021 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3022 the second SET's destination is a register that is unused and isn't
3023 marked as an instruction that might trap in an EH region. In that case,
3024 we just need the first SET. This can occur when simplifying a divmod
3025 insn. We *must* test for this case here because the code below that
3026 splits two independent SETs doesn't handle this case correctly when it
3027 updates the register status.
3029 It's pointless doing this if we originally had two sets, one from
3030 i3, and one from i2. Combining then splitting the parallel results
3031 in the original i2 again plus an invalid insn (which we delete).
3032 The net effect is only to move instructions around, which makes
3033 debug info less accurate.
3035 Also check the case where the first SET's destination is unused.
3036 That would not cause incorrect code, but does cause an unneeded
3039 if (insn_code_number < 0
3040 && !(added_sets_2 && i1 == 0)
3041 && GET_CODE (newpat) == PARALLEL
3042 && XVECLEN (newpat, 0) == 2
3043 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3044 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3045 && asm_noperands (newpat) < 0)
3047 rtx set0 = XVECEXP (newpat, 0, 0);
3048 rtx set1 = XVECEXP (newpat, 0, 1);
3050 if (((REG_P (SET_DEST (set1))
3051 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3052 || (GET_CODE (SET_DEST (set1)) == SUBREG
3053 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3054 && insn_nothrow_p (i3)
3055 && !side_effects_p (SET_SRC (set1)))
3058 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3061 else if (((REG_P (SET_DEST (set0))
3062 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3063 || (GET_CODE (SET_DEST (set0)) == SUBREG
3064 && find_reg_note (i3, REG_UNUSED,
3065 SUBREG_REG (SET_DEST (set0)))))
3066 && insn_nothrow_p (i3)
3067 && !side_effects_p (SET_SRC (set0)))
3070 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3072 if (insn_code_number >= 0)
3073 changed_i3_dest = 1;
3077 /* If we were combining three insns and the result is a simple SET
3078 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3079 insns. There are two ways to do this. It can be split using a
3080 machine-specific method (like when you have an addition of a large
3081 constant) or by combine in the function find_split_point. */
3083 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3084 && asm_noperands (newpat) < 0)
3086 rtx parallel, m_split, *split;
3088 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3089 use I2DEST as a scratch register will help. In the latter case,
3090 convert I2DEST to the mode of the source of NEWPAT if we can. */
3092 m_split = combine_split_insns (newpat, i3);
3094 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3095 inputs of NEWPAT. */
3097 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3098 possible to try that as a scratch reg. This would require adding
3099 more code to make it work though. */
3101 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3103 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3105 /* First try to split using the original register as a
3106 scratch register. */
3107 parallel = gen_rtx_PARALLEL (VOIDmode,
3108 gen_rtvec (2, newpat,
3109 gen_rtx_CLOBBER (VOIDmode,
3111 m_split = combine_split_insns (parallel, i3);
3113 /* If that didn't work, try changing the mode of I2DEST if
3116 && new_mode != GET_MODE (i2dest)
3117 && new_mode != VOIDmode
3118 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3120 enum machine_mode old_mode = GET_MODE (i2dest);
3123 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3124 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3127 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3128 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3131 parallel = (gen_rtx_PARALLEL
3133 gen_rtvec (2, newpat,
3134 gen_rtx_CLOBBER (VOIDmode,
3136 m_split = combine_split_insns (parallel, i3);
3139 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3143 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3144 buf = undobuf.undos;
3145 undobuf.undos = buf->next;
3146 buf->next = undobuf.frees;
3147 undobuf.frees = buf;
3151 i2scratch = m_split != 0;
3154 /* If recog_for_combine has discarded clobbers, try to use them
3155 again for the split. */
3156 if (m_split == 0 && newpat_vec_with_clobbers)
3158 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3159 m_split = combine_split_insns (parallel, i3);
3162 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3164 m_split = PATTERN (m_split);
3165 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3166 if (insn_code_number >= 0)
3169 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3170 && (next_real_insn (i2) == i3
3171 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3174 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3175 newi2pat = PATTERN (m_split);
3177 i3set = single_set (NEXT_INSN (m_split));
3178 i2set = single_set (m_split);
3180 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3182 /* If I2 or I3 has multiple SETs, we won't know how to track
3183 register status, so don't use these insns. If I2's destination
3184 is used between I2 and I3, we also can't use these insns. */
3186 if (i2_code_number >= 0 && i2set && i3set
3187 && (next_real_insn (i2) == i3
3188 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3189 insn_code_number = recog_for_combine (&newi3pat, i3,
3191 if (insn_code_number >= 0)
3194 /* It is possible that both insns now set the destination of I3.
3195 If so, we must show an extra use of it. */
3197 if (insn_code_number >= 0)
3199 rtx new_i3_dest = SET_DEST (i3set);
3200 rtx new_i2_dest = SET_DEST (i2set);
3202 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3203 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3204 || GET_CODE (new_i3_dest) == SUBREG)
3205 new_i3_dest = XEXP (new_i3_dest, 0);
3207 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3208 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3209 || GET_CODE (new_i2_dest) == SUBREG)
3210 new_i2_dest = XEXP (new_i2_dest, 0);
3212 if (REG_P (new_i3_dest)
3213 && REG_P (new_i2_dest)
3214 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3215 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3219 /* If we can split it and use I2DEST, go ahead and see if that
3220 helps things be recognized. Verify that none of the registers
3221 are set between I2 and I3. */
3222 if (insn_code_number < 0
3223 && (split = find_split_point (&newpat, i3, false)) != 0
3227 /* We need I2DEST in the proper mode. If it is a hard register
3228 or the only use of a pseudo, we can change its mode.
3229 Make sure we don't change a hard register to have a mode that
3230 isn't valid for it, or change the number of registers. */
3231 && (GET_MODE (*split) == GET_MODE (i2dest)
3232 || GET_MODE (*split) == VOIDmode
3233 || can_change_dest_mode (i2dest, added_sets_2,
3235 && (next_real_insn (i2) == i3
3236 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3237 /* We can't overwrite I2DEST if its value is still used by
3239 && ! reg_referenced_p (i2dest, newpat))
3241 rtx newdest = i2dest;
3242 enum rtx_code split_code = GET_CODE (*split);
3243 enum machine_mode split_mode = GET_MODE (*split);
3244 bool subst_done = false;
3245 newi2pat = NULL_RTX;
3249 /* *SPLIT may be part of I2SRC, so make sure we have the
3250 original expression around for later debug processing.
3251 We should not need I2SRC any more in other cases. */
3252 if (MAY_HAVE_DEBUG_INSNS)
3253 i2src = copy_rtx (i2src);
3257 /* Get NEWDEST as a register in the proper mode. We have already
3258 validated that we can do this. */
3259 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3261 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3262 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3265 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3266 newdest = regno_reg_rtx[REGNO (i2dest)];
3270 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3271 an ASHIFT. This can occur if it was inside a PLUS and hence
3272 appeared to be a memory address. This is a kludge. */
3273 if (split_code == MULT
3274 && CONST_INT_P (XEXP (*split, 1))
3275 && INTVAL (XEXP (*split, 1)) > 0
3276 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3278 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3279 XEXP (*split, 0), GEN_INT (i)));
3280 /* Update split_code because we may not have a multiply
3282 split_code = GET_CODE (*split);
3285 #ifdef INSN_SCHEDULING
3286 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3287 be written as a ZERO_EXTEND. */
3288 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3290 #ifdef LOAD_EXTEND_OP
3291 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3292 what it really is. */
3293 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3295 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3296 SUBREG_REG (*split)));
3299 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3300 SUBREG_REG (*split)));
3304 /* Attempt to split binary operators using arithmetic identities. */
3305 if (BINARY_P (SET_SRC (newpat))
3306 && split_mode == GET_MODE (SET_SRC (newpat))
3307 && ! side_effects_p (SET_SRC (newpat)))
3309 rtx setsrc = SET_SRC (newpat);
3310 enum machine_mode mode = GET_MODE (setsrc);
3311 enum rtx_code code = GET_CODE (setsrc);
3312 rtx src_op0 = XEXP (setsrc, 0);
3313 rtx src_op1 = XEXP (setsrc, 1);
3315 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3316 if (rtx_equal_p (src_op0, src_op1))
3318 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3319 SUBST (XEXP (setsrc, 0), newdest);
3320 SUBST (XEXP (setsrc, 1), newdest);
3323 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3324 else if ((code == PLUS || code == MULT)
3325 && GET_CODE (src_op0) == code
3326 && GET_CODE (XEXP (src_op0, 0)) == code
3327 && (INTEGRAL_MODE_P (mode)
3328 || (FLOAT_MODE_P (mode)
3329 && flag_unsafe_math_optimizations)))
3331 rtx p = XEXP (XEXP (src_op0, 0), 0);
3332 rtx q = XEXP (XEXP (src_op0, 0), 1);
3333 rtx r = XEXP (src_op0, 1);
3336 /* Split both "((X op Y) op X) op Y" and
3337 "((X op Y) op Y) op X" as "T op T" where T is
3339 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3340 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3342 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3344 SUBST (XEXP (setsrc, 0), newdest);
3345 SUBST (XEXP (setsrc, 1), newdest);
3348 /* Split "((X op X) op Y) op Y)" as "T op T" where
3350 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3352 rtx tmp = simplify_gen_binary (code, mode, p, r);
3353 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3354 SUBST (XEXP (setsrc, 0), newdest);
3355 SUBST (XEXP (setsrc, 1), newdest);
3363 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3364 SUBST (*split, newdest);
3367 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3369 /* recog_for_combine might have added CLOBBERs to newi2pat.
3370 Make sure NEWPAT does not depend on the clobbered regs. */
3371 if (GET_CODE (newi2pat) == PARALLEL)
3372 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3373 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3375 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3376 if (reg_overlap_mentioned_p (reg, newpat))
3383 /* If the split point was a MULT and we didn't have one before,
3384 don't use one now. */
3385 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3386 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3390 /* Check for a case where we loaded from memory in a narrow mode and
3391 then sign extended it, but we need both registers. In that case,
3392 we have a PARALLEL with both loads from the same memory location.
3393 We can split this into a load from memory followed by a register-register
3394 copy. This saves at least one insn, more if register allocation can
3397 We cannot do this if the destination of the first assignment is a
3398 condition code register or cc0. We eliminate this case by making sure
3399 the SET_DEST and SET_SRC have the same mode.
3401 We cannot do this if the destination of the second assignment is
3402 a register that we have already assumed is zero-extended. Similarly
3403 for a SUBREG of such a register. */
3405 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3406 && GET_CODE (newpat) == PARALLEL
3407 && XVECLEN (newpat, 0) == 2
3408 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3409 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3410 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3411 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3412 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3413 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3414 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3415 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3419 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3421 && VEC_index (reg_stat_type, reg_stat,
3422 REGNO (temp))->nonzero_bits != 0
3423 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3424 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3425 && (VEC_index (reg_stat_type, reg_stat,
3426 REGNO (temp))->nonzero_bits
3427 != GET_MODE_MASK (word_mode))))
3428 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3429 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3431 && VEC_index (reg_stat_type, reg_stat,
3432 REGNO (temp))->nonzero_bits != 0
3433 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3434 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3435 && (VEC_index (reg_stat_type, reg_stat,
3436 REGNO (temp))->nonzero_bits
3437 != GET_MODE_MASK (word_mode)))))
3438 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3439 SET_SRC (XVECEXP (newpat, 0, 1)))
3440 && ! find_reg_note (i3, REG_UNUSED,
3441 SET_DEST (XVECEXP (newpat, 0, 0))))
3445 newi2pat = XVECEXP (newpat, 0, 0);
3446 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3447 newpat = XVECEXP (newpat, 0, 1);
3448 SUBST (SET_SRC (newpat),
3449 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3450 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3452 if (i2_code_number >= 0)
3453 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3455 if (insn_code_number >= 0)
3459 /* Similarly, check for a case where we have a PARALLEL of two independent
3460 SETs but we started with three insns. In this case, we can do the sets
3461 as two separate insns. This case occurs when some SET allows two
3462 other insns to combine, but the destination of that SET is still live. */
3464 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3465 && GET_CODE (newpat) == PARALLEL
3466 && XVECLEN (newpat, 0) == 2
3467 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3468 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3469 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3470 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3471 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3472 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3473 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3475 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3476 XVECEXP (newpat, 0, 0))
3477 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3478 XVECEXP (newpat, 0, 1))
3479 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3480 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3482 /* We cannot split the parallel into two sets if both sets
3484 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3485 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3489 /* Normally, it doesn't matter which of the two is done first,
3490 but it does if one references cc0. In that case, it has to
3493 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3495 newi2pat = XVECEXP (newpat, 0, 0);
3496 newpat = XVECEXP (newpat, 0, 1);
3501 newi2pat = XVECEXP (newpat, 0, 1);
3502 newpat = XVECEXP (newpat, 0, 0);
3505 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3507 if (i2_code_number >= 0)
3508 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3511 /* If it still isn't recognized, fail and change things back the way they
3513 if ((insn_code_number < 0
3514 /* Is the result a reasonable ASM_OPERANDS? */
3515 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3521 /* If we had to change another insn, make sure it is valid also. */
3522 if (undobuf.other_insn)
3524 CLEAR_HARD_REG_SET (newpat_used_regs);
3526 other_pat = PATTERN (undobuf.other_insn);
3527 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3530 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3538 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3539 they are adjacent to each other or not. */
3541 rtx p = prev_nonnote_insn (i3);
3542 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3543 && sets_cc0_p (newi2pat))
3551 /* Only allow this combination if insn_rtx_costs reports that the
3552 replacement instructions are cheaper than the originals. */
3553 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3559 if (MAY_HAVE_DEBUG_INSNS)
3563 for (undo = undobuf.undos; undo; undo = undo->next)
3564 if (undo->kind == UNDO_MODE)
3566 rtx reg = *undo->where.r;
3567 enum machine_mode new_mode = GET_MODE (reg);
3568 enum machine_mode old_mode = undo->old_contents.m;
3570 /* Temporarily revert mode back. */
3571 adjust_reg_mode (reg, old_mode);
3573 if (reg == i2dest && i2scratch)
3575 /* If we used i2dest as a scratch register with a
3576 different mode, substitute it for the original
3577 i2src while its original mode is temporarily
3578 restored, and then clear i2scratch so that we don't
3579 do it again later. */
3580 propagate_for_debug (i2, i3, reg, i2src, false);
3582 /* Put back the new mode. */
3583 adjust_reg_mode (reg, new_mode);
3587 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3598 last = undobuf.other_insn;
3602 /* We're dealing with a reg that changed mode but not
3603 meaning, so we want to turn it into a subreg for
3604 the new mode. However, because of REG sharing and
3605 because its mode had already changed, we have to do
3606 it in two steps. First, replace any debug uses of
3607 reg, with its original mode temporarily restored,
3608 with this copy we have created; then, replace the
3609 copy with the SUBREG of the original shared reg,
3610 once again changed to the new mode. */
3611 propagate_for_debug (first, last, reg, tempreg, false);
3612 adjust_reg_mode (reg, new_mode);
3613 propagate_for_debug (first, last, tempreg,
3614 lowpart_subreg (old_mode, reg, new_mode),
3620 /* If we will be able to accept this, we have made a
3621 change to the destination of I3. This requires us to
3622 do a few adjustments. */
3624 if (changed_i3_dest)
3626 PATTERN (i3) = newpat;
3627 adjust_for_new_dest (i3);
3630 /* We now know that we can do this combination. Merge the insns and
3631 update the status of registers and LOG_LINKS. */
3633 if (undobuf.other_insn)
3637 PATTERN (undobuf.other_insn) = other_pat;
3639 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3640 are still valid. Then add any non-duplicate notes added by
3641 recog_for_combine. */
3642 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3644 next = XEXP (note, 1);
3646 if (REG_NOTE_KIND (note) == REG_UNUSED
3647 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3648 remove_note (undobuf.other_insn, note);
3651 distribute_notes (new_other_notes, undobuf.other_insn,
3652 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3661 /* I3 now uses what used to be its destination and which is now
3662 I2's destination. This requires us to do a few adjustments. */
3663 PATTERN (i3) = newpat;
3664 adjust_for_new_dest (i3);
3666 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3669 However, some later insn might be using I2's dest and have
3670 a LOG_LINK pointing at I3. We must remove this link.
3671 The simplest way to remove the link is to point it at I1,
3672 which we know will be a NOTE. */
3674 /* newi2pat is usually a SET here; however, recog_for_combine might
3675 have added some clobbers. */
3676 if (GET_CODE (newi2pat) == PARALLEL)
3677 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3679 ni2dest = SET_DEST (newi2pat);
3681 for (insn = NEXT_INSN (i3);
3682 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3683 || insn != BB_HEAD (this_basic_block->next_bb));
3684 insn = NEXT_INSN (insn))
3686 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3688 for (link = LOG_LINKS (insn); link;
3689 link = XEXP (link, 1))
3690 if (XEXP (link, 0) == i3)
3691 XEXP (link, 0) = i1;
3699 rtx i3notes, i2notes, i1notes = 0;
3700 rtx i3links, i2links, i1links = 0;
3703 /* Compute which registers we expect to eliminate. newi2pat may be setting
3704 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3705 same as i3dest, in which case newi2pat may be setting i1dest. */
3706 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3707 || i2dest_in_i2src || i2dest_in_i1src
3710 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3711 || (newi2pat && reg_set_p (i1dest, newi2pat))
3715 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3717 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3718 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3720 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3722 /* Ensure that we do not have something that should not be shared but
3723 occurs multiple times in the new insns. Check this by first
3724 resetting all the `used' flags and then copying anything is shared. */
3726 reset_used_flags (i3notes);
3727 reset_used_flags (i2notes);
3728 reset_used_flags (i1notes);
3729 reset_used_flags (newpat);
3730 reset_used_flags (newi2pat);
3731 if (undobuf.other_insn)
3732 reset_used_flags (PATTERN (undobuf.other_insn));
3734 i3notes = copy_rtx_if_shared (i3notes);
3735 i2notes = copy_rtx_if_shared (i2notes);
3736 i1notes = copy_rtx_if_shared (i1notes);
3737 newpat = copy_rtx_if_shared (newpat);
3738 newi2pat = copy_rtx_if_shared (newi2pat);
3739 if (undobuf.other_insn)
3740 reset_used_flags (PATTERN (undobuf.other_insn));
3742 INSN_CODE (i3) = insn_code_number;
3743 PATTERN (i3) = newpat;
3745 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3747 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3749 reset_used_flags (call_usage);
3750 call_usage = copy_rtx (call_usage);
3754 /* I2SRC must still be meaningful at this point. Some splitting
3755 operations can invalidate I2SRC, but those operations do not
3758 replace_rtx (call_usage, i2dest, i2src);
3762 replace_rtx (call_usage, i1dest, i1src);
3764 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3767 if (undobuf.other_insn)
3768 INSN_CODE (undobuf.other_insn) = other_code_number;
3770 /* We had one special case above where I2 had more than one set and
3771 we replaced a destination of one of those sets with the destination
3772 of I3. In that case, we have to update LOG_LINKS of insns later
3773 in this basic block. Note that this (expensive) case is rare.
3775 Also, in this case, we must pretend that all REG_NOTEs for I2
3776 actually came from I3, so that REG_UNUSED notes from I2 will be
3777 properly handled. */
3779 if (i3_subst_into_i2)
3781 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3782 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3783 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3784 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3785 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3786 && ! find_reg_note (i2, REG_UNUSED,
3787 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3788 for (temp = NEXT_INSN (i2);
3789 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3790 || BB_HEAD (this_basic_block) != temp);
3791 temp = NEXT_INSN (temp))
3792 if (temp != i3 && INSN_P (temp))
3793 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3794 if (XEXP (link, 0) == i2)
3795 XEXP (link, 0) = i3;
3800 while (XEXP (link, 1))
3801 link = XEXP (link, 1);
3802 XEXP (link, 1) = i2notes;
3816 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3817 propagate_for_debug (i2, i3, i2dest, i2src, false);
3818 INSN_CODE (i2) = i2_code_number;
3819 PATTERN (i2) = newi2pat;
3823 if (MAY_HAVE_DEBUG_INSNS && i2src)
3824 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3825 SET_INSN_DELETED (i2);
3832 if (MAY_HAVE_DEBUG_INSNS)
3833 propagate_for_debug (i1, i3, i1dest, i1src, false);
3834 SET_INSN_DELETED (i1);
3837 /* Get death notes for everything that is now used in either I3 or
3838 I2 and used to die in a previous insn. If we built two new
3839 patterns, move from I1 to I2 then I2 to I3 so that we get the
3840 proper movement on registers that I2 modifies. */
3844 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3845 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3848 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3851 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3853 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3856 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3859 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3862 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3865 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3866 know these are REG_UNUSED and want them to go to the desired insn,
3867 so we always pass it as i3. */
3869 if (newi2pat && new_i2_notes)
3870 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3873 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3875 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3876 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3877 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3878 in that case, it might delete I2. Similarly for I2 and I1.
3879 Show an additional death due to the REG_DEAD note we make here. If
3880 we discard it in distribute_notes, we will decrement it again. */
3884 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3885 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3887 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3889 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3891 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3895 if (i2dest_in_i2src)
3897 if (newi2pat && reg_set_p (i2dest, newi2pat))
3898 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3899 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3901 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3902 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3903 NULL_RTX, NULL_RTX);
3906 if (i1dest_in_i1src)
3908 if (newi2pat && reg_set_p (i1dest, newi2pat))
3909 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3910 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3912 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3913 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3914 NULL_RTX, NULL_RTX);
3917 distribute_links (i3links);
3918 distribute_links (i2links);
3919 distribute_links (i1links);
3924 rtx i2_insn = 0, i2_val = 0, set;
3926 /* The insn that used to set this register doesn't exist, and
3927 this life of the register may not exist either. See if one of
3928 I3's links points to an insn that sets I2DEST. If it does,
3929 that is now the last known value for I2DEST. If we don't update
3930 this and I2 set the register to a value that depended on its old
3931 contents, we will get confused. If this insn is used, thing
3932 will be set correctly in combine_instructions. */
3934 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3935 if ((set = single_set (XEXP (link, 0))) != 0
3936 && rtx_equal_p (i2dest, SET_DEST (set)))
3937 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3939 record_value_for_reg (i2dest, i2_insn, i2_val);
3941 /* If the reg formerly set in I2 died only once and that was in I3,
3942 zero its use count so it won't make `reload' do any work. */
3944 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3945 && ! i2dest_in_i2src)
3947 regno = REGNO (i2dest);
3948 INC_REG_N_SETS (regno, -1);
3952 if (i1 && REG_P (i1dest))
3955 rtx i1_insn = 0, i1_val = 0, set;
3957 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3958 if ((set = single_set (XEXP (link, 0))) != 0
3959 && rtx_equal_p (i1dest, SET_DEST (set)))
3960 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3962 record_value_for_reg (i1dest, i1_insn, i1_val);
3964 regno = REGNO (i1dest);
3965 if (! added_sets_1 && ! i1dest_in_i1src)
3966 INC_REG_N_SETS (regno, -1);
3969 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3970 been made to this insn. The order of
3971 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3972 can affect nonzero_bits of newpat */
3974 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3975 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3978 if (undobuf.other_insn != NULL_RTX)
3982 fprintf (dump_file, "modifying other_insn ");
3983 dump_insn_slim (dump_file, undobuf.other_insn);
3985 df_insn_rescan (undobuf.other_insn);
3988 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3992 fprintf (dump_file, "modifying insn i1 ");
3993 dump_insn_slim (dump_file, i1);
3995 df_insn_rescan (i1);
3998 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4002 fprintf (dump_file, "modifying insn i2 ");
4003 dump_insn_slim (dump_file, i2);
4005 df_insn_rescan (i2);
4008 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4012 fprintf (dump_file, "modifying insn i3 ");
4013 dump_insn_slim (dump_file, i3);
4015 df_insn_rescan (i3);
4018 /* Set new_direct_jump_p if a new return or simple jump instruction
4019 has been created. Adjust the CFG accordingly. */
4021 if (returnjump_p (i3) || any_uncondjump_p (i3))
4023 *new_direct_jump_p = 1;
4024 mark_jump_label (PATTERN (i3), i3, 0);
4025 update_cfg_for_uncondjump (i3);
4028 if (undobuf.other_insn != NULL_RTX
4029 && (returnjump_p (undobuf.other_insn)
4030 || any_uncondjump_p (undobuf.other_insn)))
4032 *new_direct_jump_p = 1;
4033 update_cfg_for_uncondjump (undobuf.other_insn);
4036 /* A noop might also need cleaning up of CFG, if it comes from the
4037 simplification of a jump. */
4038 if (GET_CODE (newpat) == SET
4039 && SET_SRC (newpat) == pc_rtx
4040 && SET_DEST (newpat) == pc_rtx)
4042 *new_direct_jump_p = 1;
4043 update_cfg_for_uncondjump (i3);
4046 combine_successes++;
4049 if (added_links_insn
4050 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4051 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4052 return added_links_insn;
4054 return newi2pat ? i2 : i3;
4057 /* Undo all the modifications recorded in undobuf. */
4062 struct undo *undo, *next;
4064 for (undo = undobuf.undos; undo; undo = next)
4070 *undo->where.r = undo->old_contents.r;
4073 *undo->where.i = undo->old_contents.i;
4076 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4082 undo->next = undobuf.frees;
4083 undobuf.frees = undo;
4089 /* We've committed to accepting the changes we made. Move all
4090 of the undos to the free list. */
4095 struct undo *undo, *next;
4097 for (undo = undobuf.undos; undo; undo = next)
4100 undo->next = undobuf.frees;
4101 undobuf.frees = undo;
4106 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4107 where we have an arithmetic expression and return that point. LOC will
4110 try_combine will call this function to see if an insn can be split into
4114 find_split_point (rtx *loc, rtx insn, bool set_src)
4117 enum rtx_code code = GET_CODE (x);
4119 unsigned HOST_WIDE_INT len = 0;
4120 HOST_WIDE_INT pos = 0;
4122 rtx inner = NULL_RTX;
4124 /* First special-case some codes. */
4128 #ifdef INSN_SCHEDULING
4129 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4131 if (MEM_P (SUBREG_REG (x)))
4134 return find_split_point (&SUBREG_REG (x), insn, false);
4138 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4139 using LO_SUM and HIGH. */
4140 if (GET_CODE (XEXP (x, 0)) == CONST
4141 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4143 enum machine_mode address_mode
4144 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4147 gen_rtx_LO_SUM (address_mode,
4148 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4150 return &XEXP (XEXP (x, 0), 0);
4154 /* If we have a PLUS whose second operand is a constant and the
4155 address is not valid, perhaps will can split it up using
4156 the machine-specific way to split large constants. We use
4157 the first pseudo-reg (one of the virtual regs) as a placeholder;
4158 it will not remain in the result. */
4159 if (GET_CODE (XEXP (x, 0)) == PLUS
4160 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4161 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4162 MEM_ADDR_SPACE (x)))
4164 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4165 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4169 /* This should have produced two insns, each of which sets our
4170 placeholder. If the source of the second is a valid address,
4171 we can make put both sources together and make a split point
4175 && NEXT_INSN (seq) != NULL_RTX
4176 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4177 && NONJUMP_INSN_P (seq)
4178 && GET_CODE (PATTERN (seq)) == SET
4179 && SET_DEST (PATTERN (seq)) == reg
4180 && ! reg_mentioned_p (reg,
4181 SET_SRC (PATTERN (seq)))
4182 && NONJUMP_INSN_P (NEXT_INSN (seq))
4183 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4184 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4185 && memory_address_addr_space_p
4186 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4187 MEM_ADDR_SPACE (x)))
4189 rtx src1 = SET_SRC (PATTERN (seq));
4190 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4192 /* Replace the placeholder in SRC2 with SRC1. If we can
4193 find where in SRC2 it was placed, that can become our
4194 split point and we can replace this address with SRC2.
4195 Just try two obvious places. */
4197 src2 = replace_rtx (src2, reg, src1);
4199 if (XEXP (src2, 0) == src1)
4200 split = &XEXP (src2, 0);
4201 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4202 && XEXP (XEXP (src2, 0), 0) == src1)
4203 split = &XEXP (XEXP (src2, 0), 0);
4207 SUBST (XEXP (x, 0), src2);
4212 /* If that didn't work, perhaps the first operand is complex and
4213 needs to be computed separately, so make a split point there.
4214 This will occur on machines that just support REG + CONST
4215 and have a constant moved through some previous computation. */
4217 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4218 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4219 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4220 return &XEXP (XEXP (x, 0), 0);
4223 /* If we have a PLUS whose first operand is complex, try computing it
4224 separately by making a split there. */
4225 if (GET_CODE (XEXP (x, 0)) == PLUS
4226 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4228 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4229 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4230 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4231 return &XEXP (XEXP (x, 0), 0);
4236 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4237 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4238 we need to put the operand into a register. So split at that
4241 if (SET_DEST (x) == cc0_rtx
4242 && GET_CODE (SET_SRC (x)) != COMPARE
4243 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4244 && !OBJECT_P (SET_SRC (x))
4245 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4246 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4247 return &SET_SRC (x);
4250 /* See if we can split SET_SRC as it stands. */
4251 split = find_split_point (&SET_SRC (x), insn, true);
4252 if (split && split != &SET_SRC (x))
4255 /* See if we can split SET_DEST as it stands. */
4256 split = find_split_point (&SET_DEST (x), insn, false);
4257 if (split && split != &SET_DEST (x))
4260 /* See if this is a bitfield assignment with everything constant. If
4261 so, this is an IOR of an AND, so split it into that. */
4262 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4263 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4264 <= HOST_BITS_PER_WIDE_INT)
4265 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4266 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4267 && CONST_INT_P (SET_SRC (x))
4268 && ((INTVAL (XEXP (SET_DEST (x), 1))
4269 + INTVAL (XEXP (SET_DEST (x), 2)))
4270 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4271 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4273 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4274 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4275 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4276 rtx dest = XEXP (SET_DEST (x), 0);
4277 enum machine_mode mode = GET_MODE (dest);
4278 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4281 if (BITS_BIG_ENDIAN)
4282 pos = GET_MODE_BITSIZE (mode) - len - pos;
4284 or_mask = gen_int_mode (src << pos, mode);
4287 simplify_gen_binary (IOR, mode, dest, or_mask));
4290 rtx negmask = gen_int_mode (~(mask << pos), mode);
4292 simplify_gen_binary (IOR, mode,
4293 simplify_gen_binary (AND, mode,
4298 SUBST (SET_DEST (x), dest);
4300 split = find_split_point (&SET_SRC (x), insn, true);
4301 if (split && split != &SET_SRC (x))
4305 /* Otherwise, see if this is an operation that we can split into two.
4306 If so, try to split that. */
4307 code = GET_CODE (SET_SRC (x));
4312 /* If we are AND'ing with a large constant that is only a single
4313 bit and the result is only being used in a context where we
4314 need to know if it is zero or nonzero, replace it with a bit
4315 extraction. This will avoid the large constant, which might
4316 have taken more than one insn to make. If the constant were
4317 not a valid argument to the AND but took only one insn to make,
4318 this is no worse, but if it took more than one insn, it will
4321 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4322 && REG_P (XEXP (SET_SRC (x), 0))
4323 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4324 && REG_P (SET_DEST (x))
4325 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4326 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4327 && XEXP (*split, 0) == SET_DEST (x)
4328 && XEXP (*split, 1) == const0_rtx)
4330 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4331 XEXP (SET_SRC (x), 0),
4332 pos, NULL_RTX, 1, 1, 0, 0);
4333 if (extraction != 0)
4335 SUBST (SET_SRC (x), extraction);
4336 return find_split_point (loc, insn, false);
4342 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4343 is known to be on, this can be converted into a NEG of a shift. */
4344 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4345 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4346 && 1 <= (pos = exact_log2
4347 (nonzero_bits (XEXP (SET_SRC (x), 0),
4348 GET_MODE (XEXP (SET_SRC (x), 0))))))
4350 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4354 gen_rtx_LSHIFTRT (mode,
4355 XEXP (SET_SRC (x), 0),
4358 split = find_split_point (&SET_SRC (x), insn, true);
4359 if (split && split != &SET_SRC (x))
4365 inner = XEXP (SET_SRC (x), 0);
4367 /* We can't optimize if either mode is a partial integer
4368 mode as we don't know how many bits are significant
4370 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4371 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4375 len = GET_MODE_BITSIZE (GET_MODE (inner));
4381 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4382 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4384 inner = XEXP (SET_SRC (x), 0);
4385 len = INTVAL (XEXP (SET_SRC (x), 1));
4386 pos = INTVAL (XEXP (SET_SRC (x), 2));
4388 if (BITS_BIG_ENDIAN)
4389 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4390 unsignedp = (code == ZERO_EXTRACT);
4398 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4400 enum machine_mode mode = GET_MODE (SET_SRC (x));
4402 /* For unsigned, we have a choice of a shift followed by an
4403 AND or two shifts. Use two shifts for field sizes where the
4404 constant might be too large. We assume here that we can
4405 always at least get 8-bit constants in an AND insn, which is
4406 true for every current RISC. */
4408 if (unsignedp && len <= 8)
4413 (mode, gen_lowpart (mode, inner),
4415 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4417 split = find_split_point (&SET_SRC (x), insn, true);
4418 if (split && split != &SET_SRC (x))
4425 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4426 gen_rtx_ASHIFT (mode,
4427 gen_lowpart (mode, inner),
4428 GEN_INT (GET_MODE_BITSIZE (mode)
4430 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4432 split = find_split_point (&SET_SRC (x), insn, true);
4433 if (split && split != &SET_SRC (x))
4438 /* See if this is a simple operation with a constant as the second
4439 operand. It might be that this constant is out of range and hence
4440 could be used as a split point. */
4441 if (BINARY_P (SET_SRC (x))
4442 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4443 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4444 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4445 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4446 return &XEXP (SET_SRC (x), 1);
4448 /* Finally, see if this is a simple operation with its first operand
4449 not in a register. The operation might require this operand in a
4450 register, so return it as a split point. We can always do this
4451 because if the first operand were another operation, we would have
4452 already found it as a split point. */
4453 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4454 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4455 return &XEXP (SET_SRC (x), 0);
4461 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4462 it is better to write this as (not (ior A B)) so we can split it.
4463 Similarly for IOR. */
4464 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4467 gen_rtx_NOT (GET_MODE (x),
4468 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4470 XEXP (XEXP (x, 0), 0),
4471 XEXP (XEXP (x, 1), 0))));
4472 return find_split_point (loc, insn, set_src);
4475 /* Many RISC machines have a large set of logical insns. If the
4476 second operand is a NOT, put it first so we will try to split the
4477 other operand first. */
4478 if (GET_CODE (XEXP (x, 1)) == NOT)
4480 rtx tem = XEXP (x, 0);
4481 SUBST (XEXP (x, 0), XEXP (x, 1));
4482 SUBST (XEXP (x, 1), tem);
4488 /* Split at a multiply-accumulate instruction. However if this is
4489 the SET_SRC, we likely do not have such an instruction and it's
4490 worthless to try this split. */
4491 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4498 /* Otherwise, select our actions depending on our rtx class. */
4499 switch (GET_RTX_CLASS (code))
4501 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4503 split = find_split_point (&XEXP (x, 2), insn, false);
4506 /* ... fall through ... */
4508 case RTX_COMM_ARITH:
4510 case RTX_COMM_COMPARE:
4511 split = find_split_point (&XEXP (x, 1), insn, false);
4514 /* ... fall through ... */
4516 /* Some machines have (and (shift ...) ...) insns. If X is not
4517 an AND, but XEXP (X, 0) is, use it as our split point. */
4518 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4519 return &XEXP (x, 0);
4521 split = find_split_point (&XEXP (x, 0), insn, false);
4527 /* Otherwise, we don't have a split point. */
4532 /* Throughout X, replace FROM with TO, and return the result.
4533 The result is TO if X is FROM;
4534 otherwise the result is X, but its contents may have been modified.
4535 If they were modified, a record was made in undobuf so that
4536 undo_all will (among other things) return X to its original state.
4538 If the number of changes necessary is too much to record to undo,
4539 the excess changes are not made, so the result is invalid.
4540 The changes already made can still be undone.
4541 undobuf.num_undo is incremented for such changes, so by testing that
4542 the caller can tell whether the result is valid.
4544 `n_occurrences' is incremented each time FROM is replaced.
4546 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4548 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4549 by copying if `n_occurrences' is nonzero. */
4552 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4554 enum rtx_code code = GET_CODE (x);
4555 enum machine_mode op0_mode = VOIDmode;
4560 /* Two expressions are equal if they are identical copies of a shared
4561 RTX or if they are both registers with the same register number
4564 #define COMBINE_RTX_EQUAL_P(X,Y) \
4566 || (REG_P (X) && REG_P (Y) \
4567 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4569 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4572 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4575 /* If X and FROM are the same register but different modes, they
4576 will not have been seen as equal above. However, the log links code
4577 will make a LOG_LINKS entry for that case. If we do nothing, we
4578 will try to rerecognize our original insn and, when it succeeds,
4579 we will delete the feeding insn, which is incorrect.
4581 So force this insn not to match in this (rare) case. */
4582 if (! in_dest && code == REG && REG_P (from)
4583 && reg_overlap_mentioned_p (x, from))
4584 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4586 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4587 of which may contain things that can be combined. */
4588 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4591 /* It is possible to have a subexpression appear twice in the insn.
4592 Suppose that FROM is a register that appears within TO.
4593 Then, after that subexpression has been scanned once by `subst',
4594 the second time it is scanned, TO may be found. If we were
4595 to scan TO here, we would find FROM within it and create a
4596 self-referent rtl structure which is completely wrong. */
4597 if (COMBINE_RTX_EQUAL_P (x, to))
4600 /* Parallel asm_operands need special attention because all of the
4601 inputs are shared across the arms. Furthermore, unsharing the
4602 rtl results in recognition failures. Failure to handle this case
4603 specially can result in circular rtl.
4605 Solve this by doing a normal pass across the first entry of the
4606 parallel, and only processing the SET_DESTs of the subsequent
4609 if (code == PARALLEL
4610 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4611 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4613 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4615 /* If this substitution failed, this whole thing fails. */
4616 if (GET_CODE (new_rtx) == CLOBBER
4617 && XEXP (new_rtx, 0) == const0_rtx)
4620 SUBST (XVECEXP (x, 0, 0), new_rtx);
4622 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4624 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4627 && GET_CODE (dest) != CC0
4628 && GET_CODE (dest) != PC)
4630 new_rtx = subst (dest, from, to, 0, unique_copy);
4632 /* If this substitution failed, this whole thing fails. */
4633 if (GET_CODE (new_rtx) == CLOBBER
4634 && XEXP (new_rtx, 0) == const0_rtx)
4637 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4643 len = GET_RTX_LENGTH (code);
4644 fmt = GET_RTX_FORMAT (code);
4646 /* We don't need to process a SET_DEST that is a register, CC0,
4647 or PC, so set up to skip this common case. All other cases
4648 where we want to suppress replacing something inside a
4649 SET_SRC are handled via the IN_DEST operand. */
4651 && (REG_P (SET_DEST (x))
4652 || GET_CODE (SET_DEST (x)) == CC0
4653 || GET_CODE (SET_DEST (x)) == PC))
4656 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4659 op0_mode = GET_MODE (XEXP (x, 0));
4661 for (i = 0; i < len; i++)
4666 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4668 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4670 new_rtx = (unique_copy && n_occurrences
4671 ? copy_rtx (to) : to);
4676 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4679 /* If this substitution failed, this whole thing
4681 if (GET_CODE (new_rtx) == CLOBBER
4682 && XEXP (new_rtx, 0) == const0_rtx)
4686 SUBST (XVECEXP (x, i, j), new_rtx);
4689 else if (fmt[i] == 'e')
4691 /* If this is a register being set, ignore it. */
4692 new_rtx = XEXP (x, i);
4695 && (((code == SUBREG || code == ZERO_EXTRACT)
4697 || code == STRICT_LOW_PART))
4700 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4702 /* In general, don't install a subreg involving two
4703 modes not tieable. It can worsen register
4704 allocation, and can even make invalid reload
4705 insns, since the reg inside may need to be copied
4706 from in the outside mode, and that may be invalid
4707 if it is an fp reg copied in integer mode.
4709 We allow two exceptions to this: It is valid if
4710 it is inside another SUBREG and the mode of that
4711 SUBREG and the mode of the inside of TO is
4712 tieable and it is valid if X is a SET that copies
4715 if (GET_CODE (to) == SUBREG
4716 && ! MODES_TIEABLE_P (GET_MODE (to),
4717 GET_MODE (SUBREG_REG (to)))
4718 && ! (code == SUBREG
4719 && MODES_TIEABLE_P (GET_MODE (x),
4720 GET_MODE (SUBREG_REG (to))))
4722 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4725 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4727 #ifdef CANNOT_CHANGE_MODE_CLASS
4730 && REGNO (to) < FIRST_PSEUDO_REGISTER
4731 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4734 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4737 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4741 /* If we are in a SET_DEST, suppress most cases unless we
4742 have gone inside a MEM, in which case we want to
4743 simplify the address. We assume here that things that
4744 are actually part of the destination have their inner
4745 parts in the first expression. This is true for SUBREG,
4746 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4747 things aside from REG and MEM that should appear in a
4749 new_rtx = subst (XEXP (x, i), from, to,
4751 && (code == SUBREG || code == STRICT_LOW_PART
4752 || code == ZERO_EXTRACT))
4754 && i == 0), unique_copy);
4756 /* If we found that we will have to reject this combination,
4757 indicate that by returning the CLOBBER ourselves, rather than
4758 an expression containing it. This will speed things up as
4759 well as prevent accidents where two CLOBBERs are considered
4760 to be equal, thus producing an incorrect simplification. */
4762 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4765 if (GET_CODE (x) == SUBREG
4766 && (CONST_INT_P (new_rtx)
4767 || GET_CODE (new_rtx) == CONST_DOUBLE))
4769 enum machine_mode mode = GET_MODE (x);
4771 x = simplify_subreg (GET_MODE (x), new_rtx,
4772 GET_MODE (SUBREG_REG (x)),
4775 x = gen_rtx_CLOBBER (mode, const0_rtx);
4777 else if (CONST_INT_P (new_rtx)
4778 && GET_CODE (x) == ZERO_EXTEND)
4780 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4781 new_rtx, GET_MODE (XEXP (x, 0)));
4785 SUBST (XEXP (x, i), new_rtx);
4790 /* Check if we are loading something from the constant pool via float
4791 extension; in this case we would undo compress_float_constant
4792 optimization and degenerate constant load to an immediate value. */
4793 if (GET_CODE (x) == FLOAT_EXTEND
4794 && MEM_P (XEXP (x, 0))
4795 && MEM_READONLY_P (XEXP (x, 0)))
4797 rtx tmp = avoid_constant_pool_reference (x);
4802 /* Try to simplify X. If the simplification changed the code, it is likely
4803 that further simplification will help, so loop, but limit the number
4804 of repetitions that will be performed. */
4806 for (i = 0; i < 4; i++)
4808 /* If X is sufficiently simple, don't bother trying to do anything
4810 if (code != CONST_INT && code != REG && code != CLOBBER)
4811 x = combine_simplify_rtx (x, op0_mode, in_dest);
4813 if (GET_CODE (x) == code)
4816 code = GET_CODE (x);
4818 /* We no longer know the original mode of operand 0 since we
4819 have changed the form of X) */
4820 op0_mode = VOIDmode;
4826 /* Simplify X, a piece of RTL. We just operate on the expression at the
4827 outer level; call `subst' to simplify recursively. Return the new
4830 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4831 if we are inside a SET_DEST. */
4834 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4836 enum rtx_code code = GET_CODE (x);
4837 enum machine_mode mode = GET_MODE (x);
4841 /* If this is a commutative operation, put a constant last and a complex
4842 expression first. We don't need to do this for comparisons here. */
4843 if (COMMUTATIVE_ARITH_P (x)
4844 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4847 SUBST (XEXP (x, 0), XEXP (x, 1));
4848 SUBST (XEXP (x, 1), temp);
4851 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4852 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4853 things. Check for cases where both arms are testing the same
4856 Don't do anything if all operands are very simple. */
4859 && ((!OBJECT_P (XEXP (x, 0))
4860 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4861 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4862 || (!OBJECT_P (XEXP (x, 1))
4863 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4864 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4866 && (!OBJECT_P (XEXP (x, 0))
4867 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4868 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4870 rtx cond, true_rtx, false_rtx;
4872 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4874 /* If everything is a comparison, what we have is highly unlikely
4875 to be simpler, so don't use it. */
4876 && ! (COMPARISON_P (x)
4877 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4879 rtx cop1 = const0_rtx;
4880 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4882 if (cond_code == NE && COMPARISON_P (cond))
4885 /* Simplify the alternative arms; this may collapse the true and
4886 false arms to store-flag values. Be careful to use copy_rtx
4887 here since true_rtx or false_rtx might share RTL with x as a
4888 result of the if_then_else_cond call above. */
4889 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4890 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4892 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4893 is unlikely to be simpler. */
4894 if (general_operand (true_rtx, VOIDmode)
4895 && general_operand (false_rtx, VOIDmode))
4897 enum rtx_code reversed;
4899 /* Restarting if we generate a store-flag expression will cause
4900 us to loop. Just drop through in this case. */
4902 /* If the result values are STORE_FLAG_VALUE and zero, we can
4903 just make the comparison operation. */
4904 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4905 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4907 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4908 && ((reversed = reversed_comparison_code_parts
4909 (cond_code, cond, cop1, NULL))
4911 x = simplify_gen_relational (reversed, mode, VOIDmode,
4914 /* Likewise, we can make the negate of a comparison operation
4915 if the result values are - STORE_FLAG_VALUE and zero. */
4916 else if (CONST_INT_P (true_rtx)
4917 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4918 && false_rtx == const0_rtx)
4919 x = simplify_gen_unary (NEG, mode,
4920 simplify_gen_relational (cond_code,
4924 else if (CONST_INT_P (false_rtx)
4925 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4926 && true_rtx == const0_rtx
4927 && ((reversed = reversed_comparison_code_parts
4928 (cond_code, cond, cop1, NULL))
4930 x = simplify_gen_unary (NEG, mode,
4931 simplify_gen_relational (reversed,
4936 return gen_rtx_IF_THEN_ELSE (mode,
4937 simplify_gen_relational (cond_code,
4942 true_rtx, false_rtx);
4944 code = GET_CODE (x);
4945 op0_mode = VOIDmode;
4950 /* Try to fold this expression in case we have constants that weren't
4953 switch (GET_RTX_CLASS (code))
4956 if (op0_mode == VOIDmode)
4957 op0_mode = GET_MODE (XEXP (x, 0));
4958 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4961 case RTX_COMM_COMPARE:
4963 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4964 if (cmp_mode == VOIDmode)
4966 cmp_mode = GET_MODE (XEXP (x, 1));
4967 if (cmp_mode == VOIDmode)
4968 cmp_mode = op0_mode;
4970 temp = simplify_relational_operation (code, mode, cmp_mode,
4971 XEXP (x, 0), XEXP (x, 1));
4974 case RTX_COMM_ARITH:
4976 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4978 case RTX_BITFIELD_OPS:
4980 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4981 XEXP (x, 1), XEXP (x, 2));
4990 code = GET_CODE (temp);
4991 op0_mode = VOIDmode;
4992 mode = GET_MODE (temp);
4995 /* First see if we can apply the inverse distributive law. */
4996 if (code == PLUS || code == MINUS
4997 || code == AND || code == IOR || code == XOR)
4999 x = apply_distributive_law (x);
5000 code = GET_CODE (x);
5001 op0_mode = VOIDmode;
5004 /* If CODE is an associative operation not otherwise handled, see if we
5005 can associate some operands. This can win if they are constants or
5006 if they are logically related (i.e. (a & b) & a). */
5007 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5008 || code == AND || code == IOR || code == XOR
5009 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5010 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5011 || (flag_associative_math && FLOAT_MODE_P (mode))))
5013 if (GET_CODE (XEXP (x, 0)) == code)
5015 rtx other = XEXP (XEXP (x, 0), 0);
5016 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5017 rtx inner_op1 = XEXP (x, 1);
5020 /* Make sure we pass the constant operand if any as the second
5021 one if this is a commutative operation. */
5022 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5024 rtx tem = inner_op0;
5025 inner_op0 = inner_op1;
5028 inner = simplify_binary_operation (code == MINUS ? PLUS
5029 : code == DIV ? MULT
5031 mode, inner_op0, inner_op1);
5033 /* For commutative operations, try the other pair if that one
5035 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5037 other = XEXP (XEXP (x, 0), 1);
5038 inner = simplify_binary_operation (code, mode,
5039 XEXP (XEXP (x, 0), 0),
5044 return simplify_gen_binary (code, mode, other, inner);
5048 /* A little bit of algebraic simplification here. */
5052 /* Ensure that our address has any ASHIFTs converted to MULT in case
5053 address-recognizing predicates are called later. */
5054 temp = make_compound_operation (XEXP (x, 0), MEM);
5055 SUBST (XEXP (x, 0), temp);
5059 if (op0_mode == VOIDmode)
5060 op0_mode = GET_MODE (SUBREG_REG (x));
5062 /* See if this can be moved to simplify_subreg. */
5063 if (CONSTANT_P (SUBREG_REG (x))
5064 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5065 /* Don't call gen_lowpart if the inner mode
5066 is VOIDmode and we cannot simplify it, as SUBREG without
5067 inner mode is invalid. */
5068 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5069 || gen_lowpart_common (mode, SUBREG_REG (x))))
5070 return gen_lowpart (mode, SUBREG_REG (x));
5072 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5076 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5082 /* Don't change the mode of the MEM if that would change the meaning
5084 if (MEM_P (SUBREG_REG (x))
5085 && (MEM_VOLATILE_P (SUBREG_REG (x))
5086 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5087 return gen_rtx_CLOBBER (mode, const0_rtx);
5089 /* Note that we cannot do any narrowing for non-constants since
5090 we might have been counting on using the fact that some bits were
5091 zero. We now do this in the SET. */
5096 temp = expand_compound_operation (XEXP (x, 0));
5098 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5099 replaced by (lshiftrt X C). This will convert
5100 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5102 if (GET_CODE (temp) == ASHIFTRT
5103 && CONST_INT_P (XEXP (temp, 1))
5104 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5105 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5106 INTVAL (XEXP (temp, 1)));
5108 /* If X has only a single bit that might be nonzero, say, bit I, convert
5109 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5110 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5111 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5112 or a SUBREG of one since we'd be making the expression more
5113 complex if it was just a register. */
5116 && ! (GET_CODE (temp) == SUBREG
5117 && REG_P (SUBREG_REG (temp)))
5118 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5120 rtx temp1 = simplify_shift_const
5121 (NULL_RTX, ASHIFTRT, mode,
5122 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5123 GET_MODE_BITSIZE (mode) - 1 - i),
5124 GET_MODE_BITSIZE (mode) - 1 - i);
5126 /* If all we did was surround TEMP with the two shifts, we
5127 haven't improved anything, so don't use it. Otherwise,
5128 we are better off with TEMP1. */
5129 if (GET_CODE (temp1) != ASHIFTRT
5130 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5131 || XEXP (XEXP (temp1, 0), 0) != temp)
5137 /* We can't handle truncation to a partial integer mode here
5138 because we don't know the real bitsize of the partial
5140 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5143 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5145 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5146 GET_MODE_MASK (mode), 0));
5148 /* We can truncate a constant value and return it. */
5149 if (CONST_INT_P (XEXP (x, 0)))
5150 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5152 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5153 whose value is a comparison can be replaced with a subreg if
5154 STORE_FLAG_VALUE permits. */
5155 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5156 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5157 && (temp = get_last_value (XEXP (x, 0)))
5158 && COMPARISON_P (temp))
5159 return gen_lowpart (mode, XEXP (x, 0));
5163 /* (const (const X)) can become (const X). Do it this way rather than
5164 returning the inner CONST since CONST can be shared with a
5166 if (GET_CODE (XEXP (x, 0)) == CONST)
5167 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5172 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5173 can add in an offset. find_split_point will split this address up
5174 again if it doesn't match. */
5175 if (GET_CODE (XEXP (x, 0)) == HIGH
5176 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5182 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5183 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5184 bit-field and can be replaced by either a sign_extend or a
5185 sign_extract. The `and' may be a zero_extend and the two
5186 <c>, -<c> constants may be reversed. */
5187 if (GET_CODE (XEXP (x, 0)) == XOR
5188 && CONST_INT_P (XEXP (x, 1))
5189 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5190 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5191 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5192 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5193 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5194 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5195 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5196 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5197 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5198 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5199 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5200 == (unsigned int) i + 1))))
5201 return simplify_shift_const
5202 (NULL_RTX, ASHIFTRT, mode,
5203 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5204 XEXP (XEXP (XEXP (x, 0), 0), 0),
5205 GET_MODE_BITSIZE (mode) - (i + 1)),
5206 GET_MODE_BITSIZE (mode) - (i + 1));
5208 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5209 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5210 the bitsize of the mode - 1. This allows simplification of
5211 "a = (b & 8) == 0;" */
5212 if (XEXP (x, 1) == constm1_rtx
5213 && !REG_P (XEXP (x, 0))
5214 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5215 && REG_P (SUBREG_REG (XEXP (x, 0))))
5216 && nonzero_bits (XEXP (x, 0), mode) == 1)
5217 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5218 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5219 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5220 GET_MODE_BITSIZE (mode) - 1),
5221 GET_MODE_BITSIZE (mode) - 1);
5223 /* If we are adding two things that have no bits in common, convert
5224 the addition into an IOR. This will often be further simplified,
5225 for example in cases like ((a & 1) + (a & 2)), which can
5228 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5229 && (nonzero_bits (XEXP (x, 0), mode)
5230 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5232 /* Try to simplify the expression further. */
5233 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5234 temp = combine_simplify_rtx (tor, mode, in_dest);
5236 /* If we could, great. If not, do not go ahead with the IOR
5237 replacement, since PLUS appears in many special purpose
5238 address arithmetic instructions. */
5239 if (GET_CODE (temp) != CLOBBER && temp != tor)
5245 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5246 (and <foo> (const_int pow2-1)) */
5247 if (GET_CODE (XEXP (x, 1)) == AND
5248 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5249 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5250 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5251 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5252 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5256 /* If we have (mult (plus A B) C), apply the distributive law and then
5257 the inverse distributive law to see if things simplify. This
5258 occurs mostly in addresses, often when unrolling loops. */
5260 if (GET_CODE (XEXP (x, 0)) == PLUS)
5262 rtx result = distribute_and_simplify_rtx (x, 0);
5267 /* Try simplify a*(b/c) as (a*b)/c. */
5268 if (FLOAT_MODE_P (mode) && flag_associative_math
5269 && GET_CODE (XEXP (x, 0)) == DIV)
5271 rtx tem = simplify_binary_operation (MULT, mode,
5272 XEXP (XEXP (x, 0), 0),
5275 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5280 /* If this is a divide by a power of two, treat it as a shift if
5281 its first operand is a shift. */
5282 if (CONST_INT_P (XEXP (x, 1))
5283 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5284 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5285 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5286 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5287 || GET_CODE (XEXP (x, 0)) == ROTATE
5288 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5289 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5293 case GT: case GTU: case GE: case GEU:
5294 case LT: case LTU: case LE: case LEU:
5295 case UNEQ: case LTGT:
5296 case UNGT: case UNGE:
5297 case UNLT: case UNLE:
5298 case UNORDERED: case ORDERED:
5299 /* If the first operand is a condition code, we can't do anything
5301 if (GET_CODE (XEXP (x, 0)) == COMPARE
5302 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5303 && ! CC0_P (XEXP (x, 0))))
5305 rtx op0 = XEXP (x, 0);
5306 rtx op1 = XEXP (x, 1);
5307 enum rtx_code new_code;
5309 if (GET_CODE (op0) == COMPARE)
5310 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5312 /* Simplify our comparison, if possible. */
5313 new_code = simplify_comparison (code, &op0, &op1);
5315 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5316 if only the low-order bit is possibly nonzero in X (such as when
5317 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5318 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5319 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5322 Remove any ZERO_EXTRACT we made when thinking this was a
5323 comparison. It may now be simpler to use, e.g., an AND. If a
5324 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5325 the call to make_compound_operation in the SET case. */
5327 if (STORE_FLAG_VALUE == 1
5328 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5329 && op1 == const0_rtx
5330 && mode == GET_MODE (op0)
5331 && nonzero_bits (op0, mode) == 1)
5332 return gen_lowpart (mode,
5333 expand_compound_operation (op0));
5335 else if (STORE_FLAG_VALUE == 1
5336 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5337 && op1 == const0_rtx
5338 && mode == GET_MODE (op0)
5339 && (num_sign_bit_copies (op0, mode)
5340 == GET_MODE_BITSIZE (mode)))
5342 op0 = expand_compound_operation (op0);
5343 return simplify_gen_unary (NEG, mode,
5344 gen_lowpart (mode, op0),
5348 else if (STORE_FLAG_VALUE == 1
5349 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5350 && op1 == const0_rtx
5351 && mode == GET_MODE (op0)
5352 && nonzero_bits (op0, mode) == 1)
5354 op0 = expand_compound_operation (op0);
5355 return simplify_gen_binary (XOR, mode,
5356 gen_lowpart (mode, op0),
5360 else if (STORE_FLAG_VALUE == 1
5361 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5362 && op1 == const0_rtx
5363 && mode == GET_MODE (op0)
5364 && (num_sign_bit_copies (op0, mode)
5365 == GET_MODE_BITSIZE (mode)))
5367 op0 = expand_compound_operation (op0);
5368 return plus_constant (gen_lowpart (mode, op0), 1);
5371 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5373 if (STORE_FLAG_VALUE == -1
5374 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5375 && op1 == const0_rtx
5376 && (num_sign_bit_copies (op0, mode)
5377 == GET_MODE_BITSIZE (mode)))
5378 return gen_lowpart (mode,
5379 expand_compound_operation (op0));
5381 else if (STORE_FLAG_VALUE == -1
5382 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5383 && op1 == const0_rtx
5384 && mode == GET_MODE (op0)
5385 && nonzero_bits (op0, mode) == 1)
5387 op0 = expand_compound_operation (op0);
5388 return simplify_gen_unary (NEG, mode,
5389 gen_lowpart (mode, op0),
5393 else if (STORE_FLAG_VALUE == -1
5394 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5395 && op1 == const0_rtx
5396 && mode == GET_MODE (op0)
5397 && (num_sign_bit_copies (op0, mode)
5398 == GET_MODE_BITSIZE (mode)))
5400 op0 = expand_compound_operation (op0);
5401 return simplify_gen_unary (NOT, mode,
5402 gen_lowpart (mode, op0),
5406 /* If X is 0/1, (eq X 0) is X-1. */
5407 else if (STORE_FLAG_VALUE == -1
5408 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5409 && op1 == const0_rtx
5410 && mode == GET_MODE (op0)
5411 && nonzero_bits (op0, mode) == 1)
5413 op0 = expand_compound_operation (op0);
5414 return plus_constant (gen_lowpart (mode, op0), -1);
5417 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5418 one bit that might be nonzero, we can convert (ne x 0) to
5419 (ashift x c) where C puts the bit in the sign bit. Remove any
5420 AND with STORE_FLAG_VALUE when we are done, since we are only
5421 going to test the sign bit. */
5422 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5423 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5424 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5425 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5426 && op1 == const0_rtx
5427 && mode == GET_MODE (op0)
5428 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5430 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5431 expand_compound_operation (op0),
5432 GET_MODE_BITSIZE (mode) - 1 - i);
5433 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5439 /* If the code changed, return a whole new comparison. */
5440 if (new_code != code)
5441 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5443 /* Otherwise, keep this operation, but maybe change its operands.
5444 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5445 SUBST (XEXP (x, 0), op0);
5446 SUBST (XEXP (x, 1), op1);
5451 return simplify_if_then_else (x);
5457 /* If we are processing SET_DEST, we are done. */
5461 return expand_compound_operation (x);
5464 return simplify_set (x);
5468 return simplify_logical (x);
5475 /* If this is a shift by a constant amount, simplify it. */
5476 if (CONST_INT_P (XEXP (x, 1)))
5477 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5478 INTVAL (XEXP (x, 1)));
5480 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5482 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5484 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5496 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5499 simplify_if_then_else (rtx x)
5501 enum machine_mode mode = GET_MODE (x);
5502 rtx cond = XEXP (x, 0);
5503 rtx true_rtx = XEXP (x, 1);
5504 rtx false_rtx = XEXP (x, 2);
5505 enum rtx_code true_code = GET_CODE (cond);
5506 int comparison_p = COMPARISON_P (cond);
5509 enum rtx_code false_code;
5512 /* Simplify storing of the truth value. */
5513 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5514 return simplify_gen_relational (true_code, mode, VOIDmode,
5515 XEXP (cond, 0), XEXP (cond, 1));
5517 /* Also when the truth value has to be reversed. */
5519 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5520 && (reversed = reversed_comparison (cond, mode)))
5523 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5524 in it is being compared against certain values. Get the true and false
5525 comparisons and see if that says anything about the value of each arm. */
5528 && ((false_code = reversed_comparison_code (cond, NULL))
5530 && REG_P (XEXP (cond, 0)))
5533 rtx from = XEXP (cond, 0);
5534 rtx true_val = XEXP (cond, 1);
5535 rtx false_val = true_val;
5538 /* If FALSE_CODE is EQ, swap the codes and arms. */
5540 if (false_code == EQ)
5542 swapped = 1, true_code = EQ, false_code = NE;
5543 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5546 /* If we are comparing against zero and the expression being tested has
5547 only a single bit that might be nonzero, that is its value when it is
5548 not equal to zero. Similarly if it is known to be -1 or 0. */
5550 if (true_code == EQ && true_val == const0_rtx
5551 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5554 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5556 else if (true_code == EQ && true_val == const0_rtx
5557 && (num_sign_bit_copies (from, GET_MODE (from))
5558 == GET_MODE_BITSIZE (GET_MODE (from))))
5561 false_val = constm1_rtx;
5564 /* Now simplify an arm if we know the value of the register in the
5565 branch and it is used in the arm. Be careful due to the potential
5566 of locally-shared RTL. */
5568 if (reg_mentioned_p (from, true_rtx))
5569 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5571 pc_rtx, pc_rtx, 0, 0);
5572 if (reg_mentioned_p (from, false_rtx))
5573 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5575 pc_rtx, pc_rtx, 0, 0);
5577 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5578 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5580 true_rtx = XEXP (x, 1);
5581 false_rtx = XEXP (x, 2);
5582 true_code = GET_CODE (cond);
5585 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5586 reversed, do so to avoid needing two sets of patterns for
5587 subtract-and-branch insns. Similarly if we have a constant in the true
5588 arm, the false arm is the same as the first operand of the comparison, or
5589 the false arm is more complicated than the true arm. */
5592 && reversed_comparison_code (cond, NULL) != UNKNOWN
5593 && (true_rtx == pc_rtx
5594 || (CONSTANT_P (true_rtx)
5595 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5596 || true_rtx == const0_rtx
5597 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5598 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5599 && !OBJECT_P (false_rtx))
5600 || reg_mentioned_p (true_rtx, false_rtx)
5601 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5603 true_code = reversed_comparison_code (cond, NULL);
5604 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5605 SUBST (XEXP (x, 1), false_rtx);
5606 SUBST (XEXP (x, 2), true_rtx);
5608 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5611 /* It is possible that the conditional has been simplified out. */
5612 true_code = GET_CODE (cond);
5613 comparison_p = COMPARISON_P (cond);
5616 /* If the two arms are identical, we don't need the comparison. */
5618 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5621 /* Convert a == b ? b : a to "a". */
5622 if (true_code == EQ && ! side_effects_p (cond)
5623 && !HONOR_NANS (mode)
5624 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5625 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5627 else if (true_code == NE && ! side_effects_p (cond)
5628 && !HONOR_NANS (mode)
5629 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5630 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5633 /* Look for cases where we have (abs x) or (neg (abs X)). */
5635 if (GET_MODE_CLASS (mode) == MODE_INT
5637 && XEXP (cond, 1) == const0_rtx
5638 && GET_CODE (false_rtx) == NEG
5639 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5640 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5641 && ! side_effects_p (true_rtx))
5646 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5650 simplify_gen_unary (NEG, mode,
5651 simplify_gen_unary (ABS, mode, true_rtx, mode),
5657 /* Look for MIN or MAX. */
5659 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5661 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5662 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5663 && ! side_effects_p (cond))
5668 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5671 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5674 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5677 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5682 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5683 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5684 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5685 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5686 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5687 neither 1 or -1, but it isn't worth checking for. */
5689 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5691 && GET_MODE_CLASS (mode) == MODE_INT
5692 && ! side_effects_p (x))
5694 rtx t = make_compound_operation (true_rtx, SET);
5695 rtx f = make_compound_operation (false_rtx, SET);
5696 rtx cond_op0 = XEXP (cond, 0);
5697 rtx cond_op1 = XEXP (cond, 1);
5698 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5699 enum machine_mode m = mode;
5700 rtx z = 0, c1 = NULL_RTX;
5702 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5703 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5704 || GET_CODE (t) == ASHIFT
5705 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5706 && rtx_equal_p (XEXP (t, 0), f))
5707 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5709 /* If an identity-zero op is commutative, check whether there
5710 would be a match if we swapped the operands. */
5711 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5712 || GET_CODE (t) == XOR)
5713 && rtx_equal_p (XEXP (t, 1), f))
5714 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5715 else if (GET_CODE (t) == SIGN_EXTEND
5716 && (GET_CODE (XEXP (t, 0)) == PLUS
5717 || GET_CODE (XEXP (t, 0)) == MINUS
5718 || GET_CODE (XEXP (t, 0)) == IOR
5719 || GET_CODE (XEXP (t, 0)) == XOR
5720 || GET_CODE (XEXP (t, 0)) == ASHIFT
5721 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5722 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5723 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5724 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5725 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5726 && (num_sign_bit_copies (f, GET_MODE (f))
5728 (GET_MODE_BITSIZE (mode)
5729 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5731 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5732 extend_op = SIGN_EXTEND;
5733 m = GET_MODE (XEXP (t, 0));
5735 else if (GET_CODE (t) == SIGN_EXTEND
5736 && (GET_CODE (XEXP (t, 0)) == PLUS
5737 || GET_CODE (XEXP (t, 0)) == IOR
5738 || GET_CODE (XEXP (t, 0)) == XOR)
5739 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5740 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5741 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5742 && (num_sign_bit_copies (f, GET_MODE (f))
5744 (GET_MODE_BITSIZE (mode)
5745 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5747 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5748 extend_op = SIGN_EXTEND;
5749 m = GET_MODE (XEXP (t, 0));
5751 else if (GET_CODE (t) == ZERO_EXTEND
5752 && (GET_CODE (XEXP (t, 0)) == PLUS
5753 || GET_CODE (XEXP (t, 0)) == MINUS
5754 || GET_CODE (XEXP (t, 0)) == IOR
5755 || GET_CODE (XEXP (t, 0)) == XOR
5756 || GET_CODE (XEXP (t, 0)) == ASHIFT
5757 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5758 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5759 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5760 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5761 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5762 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5763 && ((nonzero_bits (f, GET_MODE (f))
5764 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5767 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5768 extend_op = ZERO_EXTEND;
5769 m = GET_MODE (XEXP (t, 0));
5771 else if (GET_CODE (t) == ZERO_EXTEND
5772 && (GET_CODE (XEXP (t, 0)) == PLUS
5773 || GET_CODE (XEXP (t, 0)) == IOR
5774 || GET_CODE (XEXP (t, 0)) == XOR)
5775 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5776 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5777 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5778 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5779 && ((nonzero_bits (f, GET_MODE (f))
5780 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5783 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5784 extend_op = ZERO_EXTEND;
5785 m = GET_MODE (XEXP (t, 0));
5790 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5791 cond_op0, cond_op1),
5792 pc_rtx, pc_rtx, 0, 0);
5793 temp = simplify_gen_binary (MULT, m, temp,
5794 simplify_gen_binary (MULT, m, c1,
5796 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5797 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5799 if (extend_op != UNKNOWN)
5800 temp = simplify_gen_unary (extend_op, mode, temp, m);
5806 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5807 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5808 negation of a single bit, we can convert this operation to a shift. We
5809 can actually do this more generally, but it doesn't seem worth it. */
5811 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5812 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5813 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5814 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5815 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5816 == GET_MODE_BITSIZE (mode))
5817 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5819 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5820 gen_lowpart (mode, XEXP (cond, 0)), i);
5822 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5823 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5824 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5825 && GET_MODE (XEXP (cond, 0)) == mode
5826 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5827 == nonzero_bits (XEXP (cond, 0), mode)
5828 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5829 return XEXP (cond, 0);
5834 /* Simplify X, a SET expression. Return the new expression. */
5837 simplify_set (rtx x)
5839 rtx src = SET_SRC (x);
5840 rtx dest = SET_DEST (x);
5841 enum machine_mode mode
5842 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5846 /* (set (pc) (return)) gets written as (return). */
5847 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5850 /* Now that we know for sure which bits of SRC we are using, see if we can
5851 simplify the expression for the object knowing that we only need the
5854 if (GET_MODE_CLASS (mode) == MODE_INT
5855 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5857 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5858 SUBST (SET_SRC (x), src);
5861 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5862 the comparison result and try to simplify it unless we already have used
5863 undobuf.other_insn. */
5864 if ((GET_MODE_CLASS (mode) == MODE_CC
5865 || GET_CODE (src) == COMPARE
5867 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5868 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5869 && COMPARISON_P (*cc_use)
5870 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5872 enum rtx_code old_code = GET_CODE (*cc_use);
5873 enum rtx_code new_code;
5875 int other_changed = 0;
5876 enum machine_mode compare_mode = GET_MODE (dest);
5878 if (GET_CODE (src) == COMPARE)
5879 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5881 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5883 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5886 new_code = old_code;
5887 else if (!CONSTANT_P (tmp))
5889 new_code = GET_CODE (tmp);
5890 op0 = XEXP (tmp, 0);
5891 op1 = XEXP (tmp, 1);
5895 rtx pat = PATTERN (other_insn);
5896 undobuf.other_insn = other_insn;
5897 SUBST (*cc_use, tmp);
5899 /* Attempt to simplify CC user. */
5900 if (GET_CODE (pat) == SET)
5902 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5903 if (new_rtx != NULL_RTX)
5904 SUBST (SET_SRC (pat), new_rtx);
5907 /* Convert X into a no-op move. */
5908 SUBST (SET_DEST (x), pc_rtx);
5909 SUBST (SET_SRC (x), pc_rtx);
5913 /* Simplify our comparison, if possible. */
5914 new_code = simplify_comparison (new_code, &op0, &op1);
5916 #ifdef SELECT_CC_MODE
5917 /* If this machine has CC modes other than CCmode, check to see if we
5918 need to use a different CC mode here. */
5919 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5920 compare_mode = GET_MODE (op0);
5922 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5925 /* If the mode changed, we have to change SET_DEST, the mode in the
5926 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5927 a hard register, just build new versions with the proper mode. If it
5928 is a pseudo, we lose unless it is only time we set the pseudo, in
5929 which case we can safely change its mode. */
5930 if (compare_mode != GET_MODE (dest))
5932 if (can_change_dest_mode (dest, 0, compare_mode))
5934 unsigned int regno = REGNO (dest);
5937 if (regno < FIRST_PSEUDO_REGISTER)
5938 new_dest = gen_rtx_REG (compare_mode, regno);
5941 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5942 new_dest = regno_reg_rtx[regno];
5945 SUBST (SET_DEST (x), new_dest);
5946 SUBST (XEXP (*cc_use, 0), new_dest);
5953 #endif /* SELECT_CC_MODE */
5955 /* If the code changed, we have to build a new comparison in
5956 undobuf.other_insn. */
5957 if (new_code != old_code)
5959 int other_changed_previously = other_changed;
5960 unsigned HOST_WIDE_INT mask;
5961 rtx old_cc_use = *cc_use;
5963 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5967 /* If the only change we made was to change an EQ into an NE or
5968 vice versa, OP0 has only one bit that might be nonzero, and OP1
5969 is zero, check if changing the user of the condition code will
5970 produce a valid insn. If it won't, we can keep the original code
5971 in that insn by surrounding our operation with an XOR. */
5973 if (((old_code == NE && new_code == EQ)
5974 || (old_code == EQ && new_code == NE))
5975 && ! other_changed_previously && op1 == const0_rtx
5976 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5977 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5979 rtx pat = PATTERN (other_insn), note = 0;
5981 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5982 && ! check_asm_operands (pat)))
5984 *cc_use = old_cc_use;
5987 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5988 op0, GEN_INT (mask));
5994 undobuf.other_insn = other_insn;
5996 /* Otherwise, if we didn't previously have a COMPARE in the
5997 correct mode, we need one. */
5998 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6000 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6003 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6005 SUBST (SET_SRC (x), op0);
6008 /* Otherwise, update the COMPARE if needed. */
6009 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6011 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6017 /* Get SET_SRC in a form where we have placed back any
6018 compound expressions. Then do the checks below. */
6019 src = make_compound_operation (src, SET);
6020 SUBST (SET_SRC (x), src);
6023 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6024 and X being a REG or (subreg (reg)), we may be able to convert this to
6025 (set (subreg:m2 x) (op)).
6027 We can always do this if M1 is narrower than M2 because that means that
6028 we only care about the low bits of the result.
6030 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6031 perform a narrower operation than requested since the high-order bits will
6032 be undefined. On machine where it is defined, this transformation is safe
6033 as long as M1 and M2 have the same number of words. */
6035 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6036 && !OBJECT_P (SUBREG_REG (src))
6037 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6039 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6040 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6041 #ifndef WORD_REGISTER_OPERATIONS
6042 && (GET_MODE_SIZE (GET_MODE (src))
6043 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6045 #ifdef CANNOT_CHANGE_MODE_CLASS
6046 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6047 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6048 GET_MODE (SUBREG_REG (src)),
6052 || (GET_CODE (dest) == SUBREG
6053 && REG_P (SUBREG_REG (dest)))))
6055 SUBST (SET_DEST (x),
6056 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6058 SUBST (SET_SRC (x), SUBREG_REG (src));
6060 src = SET_SRC (x), dest = SET_DEST (x);
6064 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6067 && GET_CODE (src) == SUBREG
6068 && subreg_lowpart_p (src)
6069 && (GET_MODE_BITSIZE (GET_MODE (src))
6070 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6072 rtx inner = SUBREG_REG (src);
6073 enum machine_mode inner_mode = GET_MODE (inner);
6075 /* Here we make sure that we don't have a sign bit on. */
6076 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6077 && (nonzero_bits (inner, inner_mode)
6078 < ((unsigned HOST_WIDE_INT) 1
6079 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6081 SUBST (SET_SRC (x), inner);
6087 #ifdef LOAD_EXTEND_OP
6088 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6089 would require a paradoxical subreg. Replace the subreg with a
6090 zero_extend to avoid the reload that would otherwise be required. */
6092 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6093 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6094 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6095 && SUBREG_BYTE (src) == 0
6096 && (GET_MODE_SIZE (GET_MODE (src))
6097 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6098 && MEM_P (SUBREG_REG (src)))
6101 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6102 GET_MODE (src), SUBREG_REG (src)));
6108 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6109 are comparing an item known to be 0 or -1 against 0, use a logical
6110 operation instead. Check for one of the arms being an IOR of the other
6111 arm with some value. We compute three terms to be IOR'ed together. In
6112 practice, at most two will be nonzero. Then we do the IOR's. */
6114 if (GET_CODE (dest) != PC
6115 && GET_CODE (src) == IF_THEN_ELSE
6116 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6117 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6118 && XEXP (XEXP (src, 0), 1) == const0_rtx
6119 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6120 #ifdef HAVE_conditional_move
6121 && ! can_conditionally_move_p (GET_MODE (src))
6123 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6124 GET_MODE (XEXP (XEXP (src, 0), 0)))
6125 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6126 && ! side_effects_p (src))
6128 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6129 ? XEXP (src, 1) : XEXP (src, 2));
6130 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6131 ? XEXP (src, 2) : XEXP (src, 1));
6132 rtx term1 = const0_rtx, term2, term3;
6134 if (GET_CODE (true_rtx) == IOR
6135 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6136 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6137 else if (GET_CODE (true_rtx) == IOR
6138 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6139 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6140 else if (GET_CODE (false_rtx) == IOR
6141 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6142 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6143 else if (GET_CODE (false_rtx) == IOR
6144 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6145 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6147 term2 = simplify_gen_binary (AND, GET_MODE (src),
6148 XEXP (XEXP (src, 0), 0), true_rtx);
6149 term3 = simplify_gen_binary (AND, GET_MODE (src),
6150 simplify_gen_unary (NOT, GET_MODE (src),
6151 XEXP (XEXP (src, 0), 0),
6156 simplify_gen_binary (IOR, GET_MODE (src),
6157 simplify_gen_binary (IOR, GET_MODE (src),
6164 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6165 whole thing fail. */
6166 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6168 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6171 /* Convert this into a field assignment operation, if possible. */
6172 return make_field_assignment (x);
6175 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6179 simplify_logical (rtx x)
6181 enum machine_mode mode = GET_MODE (x);
6182 rtx op0 = XEXP (x, 0);
6183 rtx op1 = XEXP (x, 1);
6185 switch (GET_CODE (x))
6188 /* We can call simplify_and_const_int only if we don't lose
6189 any (sign) bits when converting INTVAL (op1) to
6190 "unsigned HOST_WIDE_INT". */
6191 if (CONST_INT_P (op1)
6192 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6193 || INTVAL (op1) > 0))
6195 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6196 if (GET_CODE (x) != AND)
6203 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6204 apply the distributive law and then the inverse distributive
6205 law to see if things simplify. */
6206 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6208 rtx result = distribute_and_simplify_rtx (x, 0);
6212 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6214 rtx result = distribute_and_simplify_rtx (x, 1);
6221 /* If we have (ior (and A B) C), apply the distributive law and then
6222 the inverse distributive law to see if things simplify. */
6224 if (GET_CODE (op0) == AND)
6226 rtx result = distribute_and_simplify_rtx (x, 0);
6231 if (GET_CODE (op1) == AND)
6233 rtx result = distribute_and_simplify_rtx (x, 1);
6246 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6247 operations" because they can be replaced with two more basic operations.
6248 ZERO_EXTEND is also considered "compound" because it can be replaced with
6249 an AND operation, which is simpler, though only one operation.
6251 The function expand_compound_operation is called with an rtx expression
6252 and will convert it to the appropriate shifts and AND operations,
6253 simplifying at each stage.
6255 The function make_compound_operation is called to convert an expression
6256 consisting of shifts and ANDs into the equivalent compound expression.
6257 It is the inverse of this function, loosely speaking. */
6260 expand_compound_operation (rtx x)
6262 unsigned HOST_WIDE_INT pos = 0, len;
6264 unsigned int modewidth;
6267 switch (GET_CODE (x))
6272 /* We can't necessarily use a const_int for a multiword mode;
6273 it depends on implicitly extending the value.
6274 Since we don't know the right way to extend it,
6275 we can't tell whether the implicit way is right.
6277 Even for a mode that is no wider than a const_int,
6278 we can't win, because we need to sign extend one of its bits through
6279 the rest of it, and we don't know which bit. */
6280 if (CONST_INT_P (XEXP (x, 0)))
6283 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6284 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6285 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6286 reloaded. If not for that, MEM's would very rarely be safe.
6288 Reject MODEs bigger than a word, because we might not be able
6289 to reference a two-register group starting with an arbitrary register
6290 (and currently gen_lowpart might crash for a SUBREG). */
6292 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6295 /* Reject MODEs that aren't scalar integers because turning vector
6296 or complex modes into shifts causes problems. */
6298 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6301 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6302 /* If the inner object has VOIDmode (the only way this can happen
6303 is if it is an ASM_OPERANDS), we can't do anything since we don't
6304 know how much masking to do. */
6313 /* ... fall through ... */
6316 /* If the operand is a CLOBBER, just return it. */
6317 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6320 if (!CONST_INT_P (XEXP (x, 1))
6321 || !CONST_INT_P (XEXP (x, 2))
6322 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6325 /* Reject MODEs that aren't scalar integers because turning vector
6326 or complex modes into shifts causes problems. */
6328 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6331 len = INTVAL (XEXP (x, 1));
6332 pos = INTVAL (XEXP (x, 2));
6334 /* This should stay within the object being extracted, fail otherwise. */
6335 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6338 if (BITS_BIG_ENDIAN)
6339 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6346 /* Convert sign extension to zero extension, if we know that the high
6347 bit is not set, as this is easier to optimize. It will be converted
6348 back to cheaper alternative in make_extraction. */
6349 if (GET_CODE (x) == SIGN_EXTEND
6350 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6351 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6352 & ~(((unsigned HOST_WIDE_INT)
6353 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6357 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6358 rtx temp2 = expand_compound_operation (temp);
6360 /* Make sure this is a profitable operation. */
6361 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6362 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6364 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6365 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6371 /* We can optimize some special cases of ZERO_EXTEND. */
6372 if (GET_CODE (x) == ZERO_EXTEND)
6374 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6375 know that the last value didn't have any inappropriate bits
6377 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6378 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6379 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6380 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6381 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6382 return XEXP (XEXP (x, 0), 0);
6384 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6385 if (GET_CODE (XEXP (x, 0)) == SUBREG
6386 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6387 && subreg_lowpart_p (XEXP (x, 0))
6388 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6389 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6390 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6391 return SUBREG_REG (XEXP (x, 0));
6393 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6394 is a comparison and STORE_FLAG_VALUE permits. This is like
6395 the first case, but it works even when GET_MODE (x) is larger
6396 than HOST_WIDE_INT. */
6397 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6398 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6399 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6400 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6401 <= HOST_BITS_PER_WIDE_INT)
6402 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6403 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6404 return XEXP (XEXP (x, 0), 0);
6406 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6407 if (GET_CODE (XEXP (x, 0)) == SUBREG
6408 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6409 && subreg_lowpart_p (XEXP (x, 0))
6410 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6411 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6412 <= HOST_BITS_PER_WIDE_INT)
6413 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6414 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6415 return SUBREG_REG (XEXP (x, 0));
6419 /* If we reach here, we want to return a pair of shifts. The inner
6420 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6421 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6422 logical depending on the value of UNSIGNEDP.
6424 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6425 converted into an AND of a shift.
6427 We must check for the case where the left shift would have a negative
6428 count. This can happen in a case like (x >> 31) & 255 on machines
6429 that can't shift by a constant. On those machines, we would first
6430 combine the shift with the AND to produce a variable-position
6431 extraction. Then the constant of 31 would be substituted in to produce
6432 a such a position. */
6434 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6435 if (modewidth + len >= pos)
6437 enum machine_mode mode = GET_MODE (x);
6438 tem = gen_lowpart (mode, XEXP (x, 0));
6439 if (!tem || GET_CODE (tem) == CLOBBER)
6441 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6442 tem, modewidth - pos - len);
6443 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6444 mode, tem, modewidth - len);
6446 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6447 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6448 simplify_shift_const (NULL_RTX, LSHIFTRT,
6451 ((HOST_WIDE_INT) 1 << len) - 1);
6453 /* Any other cases we can't handle. */
6456 /* If we couldn't do this for some reason, return the original
6458 if (GET_CODE (tem) == CLOBBER)
6464 /* X is a SET which contains an assignment of one object into
6465 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6466 or certain SUBREGS). If possible, convert it into a series of
6469 We half-heartedly support variable positions, but do not at all
6470 support variable lengths. */
6473 expand_field_assignment (const_rtx x)
6476 rtx pos; /* Always counts from low bit. */
6478 rtx mask, cleared, masked;
6479 enum machine_mode compute_mode;
6481 /* Loop until we find something we can't simplify. */
6484 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6485 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6487 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6488 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6489 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6491 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6492 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6494 inner = XEXP (SET_DEST (x), 0);
6495 len = INTVAL (XEXP (SET_DEST (x), 1));
6496 pos = XEXP (SET_DEST (x), 2);
6498 /* A constant position should stay within the width of INNER. */
6499 if (CONST_INT_P (pos)
6500 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6503 if (BITS_BIG_ENDIAN)
6505 if (CONST_INT_P (pos))
6506 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6508 else if (GET_CODE (pos) == MINUS
6509 && CONST_INT_P (XEXP (pos, 1))
6510 && (INTVAL (XEXP (pos, 1))
6511 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6512 /* If position is ADJUST - X, new position is X. */
6513 pos = XEXP (pos, 0);
6515 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6516 GEN_INT (GET_MODE_BITSIZE (
6523 /* A SUBREG between two modes that occupy the same numbers of words
6524 can be done by moving the SUBREG to the source. */
6525 else if (GET_CODE (SET_DEST (x)) == SUBREG
6526 /* We need SUBREGs to compute nonzero_bits properly. */
6527 && nonzero_sign_valid
6528 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6530 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6533 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6535 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6542 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6543 inner = SUBREG_REG (inner);
6545 compute_mode = GET_MODE (inner);
6547 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6548 if (! SCALAR_INT_MODE_P (compute_mode))
6550 enum machine_mode imode;
6552 /* Don't do anything for vector or complex integral types. */
6553 if (! FLOAT_MODE_P (compute_mode))
6556 /* Try to find an integral mode to pun with. */
6557 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6558 if (imode == BLKmode)
6561 compute_mode = imode;
6562 inner = gen_lowpart (imode, inner);
6565 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6566 if (len >= HOST_BITS_PER_WIDE_INT)
6569 /* Now compute the equivalent expression. Make a copy of INNER
6570 for the SET_DEST in case it is a MEM into which we will substitute;
6571 we don't want shared RTL in that case. */
6572 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6573 cleared = simplify_gen_binary (AND, compute_mode,
6574 simplify_gen_unary (NOT, compute_mode,
6575 simplify_gen_binary (ASHIFT,
6580 masked = simplify_gen_binary (ASHIFT, compute_mode,
6581 simplify_gen_binary (
6583 gen_lowpart (compute_mode, SET_SRC (x)),
6587 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6588 simplify_gen_binary (IOR, compute_mode,
6595 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6596 it is an RTX that represents a variable starting position; otherwise,
6597 POS is the (constant) starting bit position (counted from the LSB).
6599 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6602 IN_DEST is nonzero if this is a reference in the destination of a
6603 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6604 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6607 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6608 ZERO_EXTRACT should be built even for bits starting at bit 0.
6610 MODE is the desired mode of the result (if IN_DEST == 0).
6612 The result is an RTX for the extraction or NULL_RTX if the target
6616 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6617 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6618 int in_dest, int in_compare)
6620 /* This mode describes the size of the storage area
6621 to fetch the overall value from. Within that, we
6622 ignore the POS lowest bits, etc. */
6623 enum machine_mode is_mode = GET_MODE (inner);
6624 enum machine_mode inner_mode;
6625 enum machine_mode wanted_inner_mode;
6626 enum machine_mode wanted_inner_reg_mode = word_mode;
6627 enum machine_mode pos_mode = word_mode;
6628 enum machine_mode extraction_mode = word_mode;
6629 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6631 rtx orig_pos_rtx = pos_rtx;
6632 HOST_WIDE_INT orig_pos;
6634 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6636 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6637 consider just the QI as the memory to extract from.
6638 The subreg adds or removes high bits; its mode is
6639 irrelevant to the meaning of this extraction,
6640 since POS and LEN count from the lsb. */
6641 if (MEM_P (SUBREG_REG (inner)))
6642 is_mode = GET_MODE (SUBREG_REG (inner));
6643 inner = SUBREG_REG (inner);
6645 else if (GET_CODE (inner) == ASHIFT
6646 && CONST_INT_P (XEXP (inner, 1))
6647 && pos_rtx == 0 && pos == 0
6648 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6650 /* We're extracting the least significant bits of an rtx
6651 (ashift X (const_int C)), where LEN > C. Extract the
6652 least significant (LEN - C) bits of X, giving an rtx
6653 whose mode is MODE, then shift it left C times. */
6654 new_rtx = make_extraction (mode, XEXP (inner, 0),
6655 0, 0, len - INTVAL (XEXP (inner, 1)),
6656 unsignedp, in_dest, in_compare);
6658 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6661 inner_mode = GET_MODE (inner);
6663 if (pos_rtx && CONST_INT_P (pos_rtx))
6664 pos = INTVAL (pos_rtx), pos_rtx = 0;
6666 /* See if this can be done without an extraction. We never can if the
6667 width of the field is not the same as that of some integer mode. For
6668 registers, we can only avoid the extraction if the position is at the
6669 low-order bit and this is either not in the destination or we have the
6670 appropriate STRICT_LOW_PART operation available.
6672 For MEM, we can avoid an extract if the field starts on an appropriate
6673 boundary and we can change the mode of the memory reference. */
6675 if (tmode != BLKmode
6676 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6678 && (inner_mode == tmode
6680 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6681 GET_MODE_BITSIZE (inner_mode))
6682 || reg_truncated_to_mode (tmode, inner))
6685 && have_insn_for (STRICT_LOW_PART, tmode))))
6686 || (MEM_P (inner) && pos_rtx == 0
6688 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6689 : BITS_PER_UNIT)) == 0
6690 /* We can't do this if we are widening INNER_MODE (it
6691 may not be aligned, for one thing). */
6692 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6693 && (inner_mode == tmode
6694 || (! mode_dependent_address_p (XEXP (inner, 0))
6695 && ! MEM_VOLATILE_P (inner))))))
6697 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6698 field. If the original and current mode are the same, we need not
6699 adjust the offset. Otherwise, we do if bytes big endian.
6701 If INNER is not a MEM, get a piece consisting of just the field
6702 of interest (in this case POS % BITS_PER_WORD must be 0). */
6706 HOST_WIDE_INT offset;
6708 /* POS counts from lsb, but make OFFSET count in memory order. */
6709 if (BYTES_BIG_ENDIAN)
6710 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6712 offset = pos / BITS_PER_UNIT;
6714 new_rtx = adjust_address_nv (inner, tmode, offset);
6716 else if (REG_P (inner))
6718 if (tmode != inner_mode)
6720 /* We can't call gen_lowpart in a DEST since we
6721 always want a SUBREG (see below) and it would sometimes
6722 return a new hard register. */
6725 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6727 if (WORDS_BIG_ENDIAN
6728 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6729 final_word = ((GET_MODE_SIZE (inner_mode)
6730 - GET_MODE_SIZE (tmode))
6731 / UNITS_PER_WORD) - final_word;
6733 final_word *= UNITS_PER_WORD;
6734 if (BYTES_BIG_ENDIAN &&
6735 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6736 final_word += (GET_MODE_SIZE (inner_mode)
6737 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6739 /* Avoid creating invalid subregs, for example when
6740 simplifying (x>>32)&255. */
6741 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6744 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6747 new_rtx = gen_lowpart (tmode, inner);
6753 new_rtx = force_to_mode (inner, tmode,
6754 len >= HOST_BITS_PER_WIDE_INT
6755 ? ~(unsigned HOST_WIDE_INT) 0
6756 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6759 /* If this extraction is going into the destination of a SET,
6760 make a STRICT_LOW_PART unless we made a MEM. */
6763 return (MEM_P (new_rtx) ? new_rtx
6764 : (GET_CODE (new_rtx) != SUBREG
6765 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6766 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6771 if (CONST_INT_P (new_rtx)
6772 || GET_CODE (new_rtx) == CONST_DOUBLE)
6773 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6774 mode, new_rtx, tmode);
6776 /* If we know that no extraneous bits are set, and that the high
6777 bit is not set, convert the extraction to the cheaper of
6778 sign and zero extension, that are equivalent in these cases. */
6779 if (flag_expensive_optimizations
6780 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6781 && ((nonzero_bits (new_rtx, tmode)
6782 & ~(((unsigned HOST_WIDE_INT)
6783 GET_MODE_MASK (tmode))
6787 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6788 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6790 /* Prefer ZERO_EXTENSION, since it gives more information to
6792 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6793 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6798 /* Otherwise, sign- or zero-extend unless we already are in the
6801 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6805 /* Unless this is a COMPARE or we have a funny memory reference,
6806 don't do anything with zero-extending field extracts starting at
6807 the low-order bit since they are simple AND operations. */
6808 if (pos_rtx == 0 && pos == 0 && ! in_dest
6809 && ! in_compare && unsignedp)
6812 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6813 if the position is not a constant and the length is not 1. In all
6814 other cases, we would only be going outside our object in cases when
6815 an original shift would have been undefined. */
6817 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6818 || (pos_rtx != 0 && len != 1)))
6821 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6822 and the mode for the result. */
6823 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6825 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6826 pos_mode = mode_for_extraction (EP_insv, 2);
6827 extraction_mode = mode_for_extraction (EP_insv, 3);
6830 if (! in_dest && unsignedp
6831 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6833 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6834 pos_mode = mode_for_extraction (EP_extzv, 3);
6835 extraction_mode = mode_for_extraction (EP_extzv, 0);
6838 if (! in_dest && ! unsignedp
6839 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6841 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6842 pos_mode = mode_for_extraction (EP_extv, 3);
6843 extraction_mode = mode_for_extraction (EP_extv, 0);
6846 /* Never narrow an object, since that might not be safe. */
6848 if (mode != VOIDmode
6849 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6850 extraction_mode = mode;
6852 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6853 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6854 pos_mode = GET_MODE (pos_rtx);
6856 /* If this is not from memory, the desired mode is the preferred mode
6857 for an extraction pattern's first input operand, or word_mode if there
6860 wanted_inner_mode = wanted_inner_reg_mode;
6863 /* Be careful not to go beyond the extracted object and maintain the
6864 natural alignment of the memory. */
6865 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6866 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6867 > GET_MODE_BITSIZE (wanted_inner_mode))
6869 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6870 gcc_assert (wanted_inner_mode != VOIDmode);
6873 /* If we have to change the mode of memory and cannot, the desired mode
6874 is EXTRACTION_MODE. */
6875 if (inner_mode != wanted_inner_mode
6876 && (mode_dependent_address_p (XEXP (inner, 0))
6877 || MEM_VOLATILE_P (inner)
6879 wanted_inner_mode = extraction_mode;
6884 if (BITS_BIG_ENDIAN)
6886 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6887 BITS_BIG_ENDIAN style. If position is constant, compute new
6888 position. Otherwise, build subtraction.
6889 Note that POS is relative to the mode of the original argument.
6890 If it's a MEM we need to recompute POS relative to that.
6891 However, if we're extracting from (or inserting into) a register,
6892 we want to recompute POS relative to wanted_inner_mode. */
6893 int width = (MEM_P (inner)
6894 ? GET_MODE_BITSIZE (is_mode)
6895 : GET_MODE_BITSIZE (wanted_inner_mode));
6898 pos = width - len - pos;
6901 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6902 /* POS may be less than 0 now, but we check for that below.
6903 Note that it can only be less than 0 if !MEM_P (inner). */
6906 /* If INNER has a wider mode, and this is a constant extraction, try to
6907 make it smaller and adjust the byte to point to the byte containing
6909 if (wanted_inner_mode != VOIDmode
6910 && inner_mode != wanted_inner_mode
6912 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6914 && ! mode_dependent_address_p (XEXP (inner, 0))
6915 && ! MEM_VOLATILE_P (inner))
6919 /* The computations below will be correct if the machine is big
6920 endian in both bits and bytes or little endian in bits and bytes.
6921 If it is mixed, we must adjust. */
6923 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6924 adjust OFFSET to compensate. */
6925 if (BYTES_BIG_ENDIAN
6926 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6927 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6929 /* We can now move to the desired byte. */
6930 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6931 * GET_MODE_SIZE (wanted_inner_mode);
6932 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6934 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6935 && is_mode != wanted_inner_mode)
6936 offset = (GET_MODE_SIZE (is_mode)
6937 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6939 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6942 /* If INNER is not memory, get it into the proper mode. If we are changing
6943 its mode, POS must be a constant and smaller than the size of the new
6945 else if (!MEM_P (inner))
6947 /* On the LHS, don't create paradoxical subregs implicitely truncating
6948 the register unless TRULY_NOOP_TRUNCATION. */
6950 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6951 GET_MODE_BITSIZE (wanted_inner_mode)))
6954 if (GET_MODE (inner) != wanted_inner_mode
6956 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6962 inner = force_to_mode (inner, wanted_inner_mode,
6964 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6965 ? ~(unsigned HOST_WIDE_INT) 0
6966 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6971 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6972 have to zero extend. Otherwise, we can just use a SUBREG. */
6974 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6976 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6978 /* If we know that no extraneous bits are set, and that the high
6979 bit is not set, convert extraction to cheaper one - either
6980 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6982 if (flag_expensive_optimizations
6983 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6984 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6985 & ~(((unsigned HOST_WIDE_INT)
6986 GET_MODE_MASK (GET_MODE (pos_rtx)))
6990 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6992 /* Prefer ZERO_EXTENSION, since it gives more information to
6994 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6995 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7000 else if (pos_rtx != 0
7001 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7002 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7004 /* Make POS_RTX unless we already have it and it is correct. If we don't
7005 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7007 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7008 pos_rtx = orig_pos_rtx;
7010 else if (pos_rtx == 0)
7011 pos_rtx = GEN_INT (pos);
7013 /* Make the required operation. See if we can use existing rtx. */
7014 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7015 extraction_mode, inner, GEN_INT (len), pos_rtx);
7017 new_rtx = gen_lowpart (mode, new_rtx);
7022 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7023 with any other operations in X. Return X without that shift if so. */
7026 extract_left_shift (rtx x, int count)
7028 enum rtx_code code = GET_CODE (x);
7029 enum machine_mode mode = GET_MODE (x);
7035 /* This is the shift itself. If it is wide enough, we will return
7036 either the value being shifted if the shift count is equal to
7037 COUNT or a shift for the difference. */
7038 if (CONST_INT_P (XEXP (x, 1))
7039 && INTVAL (XEXP (x, 1)) >= count)
7040 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7041 INTVAL (XEXP (x, 1)) - count);
7045 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7046 return simplify_gen_unary (code, mode, tem, mode);
7050 case PLUS: case IOR: case XOR: case AND:
7051 /* If we can safely shift this constant and we find the inner shift,
7052 make a new operation. */
7053 if (CONST_INT_P (XEXP (x, 1))
7054 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7055 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7056 return simplify_gen_binary (code, mode, tem,
7057 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7068 /* Look at the expression rooted at X. Look for expressions
7069 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7070 Form these expressions.
7072 Return the new rtx, usually just X.
7074 Also, for machines like the VAX that don't have logical shift insns,
7075 try to convert logical to arithmetic shift operations in cases where
7076 they are equivalent. This undoes the canonicalizations to logical
7077 shifts done elsewhere.
7079 We try, as much as possible, to re-use rtl expressions to save memory.
7081 IN_CODE says what kind of expression we are processing. Normally, it is
7082 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7083 being kludges), it is MEM. When processing the arguments of a comparison
7084 or a COMPARE against zero, it is COMPARE. */
7087 make_compound_operation (rtx x, enum rtx_code in_code)
7089 enum rtx_code code = GET_CODE (x);
7090 enum machine_mode mode = GET_MODE (x);
7091 int mode_width = GET_MODE_BITSIZE (mode);
7093 enum rtx_code next_code;
7099 /* Select the code to be used in recursive calls. Once we are inside an
7100 address, we stay there. If we have a comparison, set to COMPARE,
7101 but once inside, go back to our default of SET. */
7103 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7104 : ((code == COMPARE || COMPARISON_P (x))
7105 && XEXP (x, 1) == const0_rtx) ? COMPARE
7106 : in_code == COMPARE ? SET : in_code);
7108 /* Process depending on the code of this operation. If NEW is set
7109 nonzero, it will be returned. */
7114 /* Convert shifts by constants into multiplications if inside
7116 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7117 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7118 && INTVAL (XEXP (x, 1)) >= 0)
7120 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7121 new_rtx = gen_rtx_MULT (mode, new_rtx,
7122 GEN_INT ((HOST_WIDE_INT) 1
7123 << INTVAL (XEXP (x, 1))));
7128 /* If the second operand is not a constant, we can't do anything
7130 if (!CONST_INT_P (XEXP (x, 1)))
7133 /* If the constant is a power of two minus one and the first operand
7134 is a logical right shift, make an extraction. */
7135 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7136 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7138 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7139 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7140 0, in_code == COMPARE);
7143 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7144 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7145 && subreg_lowpart_p (XEXP (x, 0))
7146 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7147 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7149 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7151 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7152 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7153 0, in_code == COMPARE);
7155 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7156 else if ((GET_CODE (XEXP (x, 0)) == XOR
7157 || GET_CODE (XEXP (x, 0)) == IOR)
7158 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7159 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7160 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7162 /* Apply the distributive law, and then try to make extractions. */
7163 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7164 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7166 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7168 new_rtx = make_compound_operation (new_rtx, in_code);
7171 /* If we are have (and (rotate X C) M) and C is larger than the number
7172 of bits in M, this is an extraction. */
7174 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7175 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7176 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7177 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7179 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7180 new_rtx = make_extraction (mode, new_rtx,
7181 (GET_MODE_BITSIZE (mode)
7182 - INTVAL (XEXP (XEXP (x, 0), 1))),
7183 NULL_RTX, i, 1, 0, in_code == COMPARE);
7186 /* On machines without logical shifts, if the operand of the AND is
7187 a logical shift and our mask turns off all the propagated sign
7188 bits, we can replace the logical shift with an arithmetic shift. */
7189 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7190 && !have_insn_for (LSHIFTRT, mode)
7191 && have_insn_for (ASHIFTRT, mode)
7192 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7193 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7194 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7195 && mode_width <= HOST_BITS_PER_WIDE_INT)
7197 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7199 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7200 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7202 gen_rtx_ASHIFTRT (mode,
7203 make_compound_operation
7204 (XEXP (XEXP (x, 0), 0), next_code),
7205 XEXP (XEXP (x, 0), 1)));
7208 /* If the constant is one less than a power of two, this might be
7209 representable by an extraction even if no shift is present.
7210 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7211 we are in a COMPARE. */
7212 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7213 new_rtx = make_extraction (mode,
7214 make_compound_operation (XEXP (x, 0),
7216 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7218 /* If we are in a comparison and this is an AND with a power of two,
7219 convert this into the appropriate bit extract. */
7220 else if (in_code == COMPARE
7221 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7222 new_rtx = make_extraction (mode,
7223 make_compound_operation (XEXP (x, 0),
7225 i, NULL_RTX, 1, 1, 0, 1);
7230 /* If the sign bit is known to be zero, replace this with an
7231 arithmetic shift. */
7232 if (have_insn_for (ASHIFTRT, mode)
7233 && ! have_insn_for (LSHIFTRT, mode)
7234 && mode_width <= HOST_BITS_PER_WIDE_INT
7235 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7237 new_rtx = gen_rtx_ASHIFTRT (mode,
7238 make_compound_operation (XEXP (x, 0),
7244 /* ... fall through ... */
7250 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7251 this is a SIGN_EXTRACT. */
7252 if (CONST_INT_P (rhs)
7253 && GET_CODE (lhs) == ASHIFT
7254 && CONST_INT_P (XEXP (lhs, 1))
7255 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7256 && INTVAL (rhs) < mode_width)
7258 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7259 new_rtx = make_extraction (mode, new_rtx,
7260 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7261 NULL_RTX, mode_width - INTVAL (rhs),
7262 code == LSHIFTRT, 0, in_code == COMPARE);
7266 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7267 If so, try to merge the shifts into a SIGN_EXTEND. We could
7268 also do this for some cases of SIGN_EXTRACT, but it doesn't
7269 seem worth the effort; the case checked for occurs on Alpha. */
7272 && ! (GET_CODE (lhs) == SUBREG
7273 && (OBJECT_P (SUBREG_REG (lhs))))
7274 && CONST_INT_P (rhs)
7275 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7276 && INTVAL (rhs) < mode_width
7277 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7278 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7279 0, NULL_RTX, mode_width - INTVAL (rhs),
7280 code == LSHIFTRT, 0, in_code == COMPARE);
7285 /* Call ourselves recursively on the inner expression. If we are
7286 narrowing the object and it has a different RTL code from
7287 what it originally did, do this SUBREG as a force_to_mode. */
7289 tem = make_compound_operation (SUBREG_REG (x), in_code);
7292 rtx simplified = simplify_subreg (mode, tem, GET_MODE (SUBREG_REG (x)),
7298 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7299 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7300 && subreg_lowpart_p (x))
7302 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7305 /* If we have something other than a SUBREG, we might have
7306 done an expansion, so rerun ourselves. */
7307 if (GET_CODE (newer) != SUBREG)
7308 newer = make_compound_operation (newer, in_code);
7310 /* force_to_mode can expand compounds. If it just re-expanded the
7311 compound use gen_lowpart instead to convert to the desired
7313 if (rtx_equal_p (newer, x))
7314 return gen_lowpart (GET_MODE (x), tem);
7330 x = gen_lowpart (mode, new_rtx);
7331 code = GET_CODE (x);
7334 /* Now recursively process each operand of this operation. */
7335 fmt = GET_RTX_FORMAT (code);
7336 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7339 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7340 SUBST (XEXP (x, i), new_rtx);
7342 else if (fmt[i] == 'E')
7343 for (j = 0; j < XVECLEN (x, i); j++)
7345 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7346 SUBST (XVECEXP (x, i, j), new_rtx);
7349 /* If this is a commutative operation, the changes to the operands
7350 may have made it noncanonical. */
7351 if (COMMUTATIVE_ARITH_P (x)
7352 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7355 SUBST (XEXP (x, 0), XEXP (x, 1));
7356 SUBST (XEXP (x, 1), tem);
7362 /* Given M see if it is a value that would select a field of bits
7363 within an item, but not the entire word. Return -1 if not.
7364 Otherwise, return the starting position of the field, where 0 is the
7367 *PLEN is set to the length of the field. */
7370 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7372 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7373 int pos = exact_log2 (m & -m);
7377 /* Now shift off the low-order zero bits and see if we have a
7378 power of two minus 1. */
7379 len = exact_log2 ((m >> pos) + 1);
7388 /* If X refers to a register that equals REG in value, replace these
7389 references with REG. */
7391 canon_reg_for_combine (rtx x, rtx reg)
7398 enum rtx_code code = GET_CODE (x);
7399 switch (GET_RTX_CLASS (code))
7402 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7403 if (op0 != XEXP (x, 0))
7404 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7409 case RTX_COMM_ARITH:
7410 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7411 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7412 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7413 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7417 case RTX_COMM_COMPARE:
7418 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7419 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7420 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7421 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7422 GET_MODE (op0), op0, op1);
7426 case RTX_BITFIELD_OPS:
7427 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7428 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7429 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7430 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7431 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7432 GET_MODE (op0), op0, op1, op2);
7437 if (rtx_equal_p (get_last_value (reg), x)
7438 || rtx_equal_p (reg, get_last_value (x)))
7447 fmt = GET_RTX_FORMAT (code);
7449 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7452 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7453 if (op != XEXP (x, i))
7463 else if (fmt[i] == 'E')
7466 for (j = 0; j < XVECLEN (x, i); j++)
7468 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7469 if (op != XVECEXP (x, i, j))
7476 XVECEXP (x, i, j) = op;
7487 /* Return X converted to MODE. If the value is already truncated to
7488 MODE we can just return a subreg even though in the general case we
7489 would need an explicit truncation. */
7492 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7494 if (!CONST_INT_P (x)
7495 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7496 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7497 GET_MODE_BITSIZE (GET_MODE (x)))
7498 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7500 /* Bit-cast X into an integer mode. */
7501 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7502 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7503 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7507 return gen_lowpart (mode, x);
7510 /* See if X can be simplified knowing that we will only refer to it in
7511 MODE and will only refer to those bits that are nonzero in MASK.
7512 If other bits are being computed or if masking operations are done
7513 that select a superset of the bits in MASK, they can sometimes be
7516 Return a possibly simplified expression, but always convert X to
7517 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7519 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7520 are all off in X. This is used when X will be complemented, by either
7521 NOT, NEG, or XOR. */
7524 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7527 enum rtx_code code = GET_CODE (x);
7528 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7529 enum machine_mode op_mode;
7530 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7533 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7534 code below will do the wrong thing since the mode of such an
7535 expression is VOIDmode.
7537 Also do nothing if X is a CLOBBER; this can happen if X was
7538 the return value from a call to gen_lowpart. */
7539 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7542 /* We want to perform the operation is its present mode unless we know
7543 that the operation is valid in MODE, in which case we do the operation
7545 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7546 && have_insn_for (code, mode))
7547 ? mode : GET_MODE (x));
7549 /* It is not valid to do a right-shift in a narrower mode
7550 than the one it came in with. */
7551 if ((code == LSHIFTRT || code == ASHIFTRT)
7552 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7553 op_mode = GET_MODE (x);
7555 /* Truncate MASK to fit OP_MODE. */
7557 mask &= GET_MODE_MASK (op_mode);
7559 /* When we have an arithmetic operation, or a shift whose count we
7560 do not know, we need to assume that all bits up to the highest-order
7561 bit in MASK will be needed. This is how we form such a mask. */
7562 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7563 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7565 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7568 /* Determine what bits of X are guaranteed to be (non)zero. */
7569 nonzero = nonzero_bits (x, mode);
7571 /* If none of the bits in X are needed, return a zero. */
7572 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7575 /* If X is a CONST_INT, return a new one. Do this here since the
7576 test below will fail. */
7577 if (CONST_INT_P (x))
7579 if (SCALAR_INT_MODE_P (mode))
7580 return gen_int_mode (INTVAL (x) & mask, mode);
7583 x = GEN_INT (INTVAL (x) & mask);
7584 return gen_lowpart_common (mode, x);
7588 /* If X is narrower than MODE and we want all the bits in X's mode, just
7589 get X in the proper mode. */
7590 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7591 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7592 return gen_lowpart (mode, x);
7594 /* We can ignore the effect of a SUBREG if it narrows the mode or
7595 if the constant masks to zero all the bits the mode doesn't have. */
7596 if (GET_CODE (x) == SUBREG
7597 && subreg_lowpart_p (x)
7598 && ((GET_MODE_SIZE (GET_MODE (x))
7599 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7601 & GET_MODE_MASK (GET_MODE (x))
7602 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7603 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7605 /* The arithmetic simplifications here only work for scalar integer modes. */
7606 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7607 return gen_lowpart_or_truncate (mode, x);
7612 /* If X is a (clobber (const_int)), return it since we know we are
7613 generating something that won't match. */
7620 x = expand_compound_operation (x);
7621 if (GET_CODE (x) != code)
7622 return force_to_mode (x, mode, mask, next_select);
7626 /* Similarly for a truncate. */
7627 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7630 /* If this is an AND with a constant, convert it into an AND
7631 whose constant is the AND of that constant with MASK. If it
7632 remains an AND of MASK, delete it since it is redundant. */
7634 if (CONST_INT_P (XEXP (x, 1)))
7636 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7637 mask & INTVAL (XEXP (x, 1)));
7639 /* If X is still an AND, see if it is an AND with a mask that
7640 is just some low-order bits. If so, and it is MASK, we don't
7643 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7644 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7648 /* If it remains an AND, try making another AND with the bits
7649 in the mode mask that aren't in MASK turned on. If the
7650 constant in the AND is wide enough, this might make a
7651 cheaper constant. */
7653 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7654 && GET_MODE_MASK (GET_MODE (x)) != mask
7655 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7657 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7658 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7659 int width = GET_MODE_BITSIZE (GET_MODE (x));
7662 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7663 number, sign extend it. */
7664 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7665 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7666 cval |= (HOST_WIDE_INT) -1 << width;
7668 y = simplify_gen_binary (AND, GET_MODE (x),
7669 XEXP (x, 0), GEN_INT (cval));
7670 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7671 < rtx_cost (x, SET, optimize_this_for_speed_p))
7681 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7682 low-order bits (as in an alignment operation) and FOO is already
7683 aligned to that boundary, mask C1 to that boundary as well.
7684 This may eliminate that PLUS and, later, the AND. */
7687 unsigned int width = GET_MODE_BITSIZE (mode);
7688 unsigned HOST_WIDE_INT smask = mask;
7690 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7691 number, sign extend it. */
7693 if (width < HOST_BITS_PER_WIDE_INT
7694 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7695 smask |= (HOST_WIDE_INT) -1 << width;
7697 if (CONST_INT_P (XEXP (x, 1))
7698 && exact_log2 (- smask) >= 0
7699 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7700 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7701 return force_to_mode (plus_constant (XEXP (x, 0),
7702 (INTVAL (XEXP (x, 1)) & smask)),
7703 mode, smask, next_select);
7706 /* ... fall through ... */
7709 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7710 most significant bit in MASK since carries from those bits will
7711 affect the bits we are interested in. */
7716 /* If X is (minus C Y) where C's least set bit is larger than any bit
7717 in the mask, then we may replace with (neg Y). */
7718 if (CONST_INT_P (XEXP (x, 0))
7719 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7720 & -INTVAL (XEXP (x, 0))))
7723 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7725 return force_to_mode (x, mode, mask, next_select);
7728 /* Similarly, if C contains every bit in the fuller_mask, then we may
7729 replace with (not Y). */
7730 if (CONST_INT_P (XEXP (x, 0))
7731 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7732 == INTVAL (XEXP (x, 0))))
7734 x = simplify_gen_unary (NOT, GET_MODE (x),
7735 XEXP (x, 1), GET_MODE (x));
7736 return force_to_mode (x, mode, mask, next_select);
7744 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7745 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7746 operation which may be a bitfield extraction. Ensure that the
7747 constant we form is not wider than the mode of X. */
7749 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7750 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7751 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7752 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7753 && CONST_INT_P (XEXP (x, 1))
7754 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7755 + floor_log2 (INTVAL (XEXP (x, 1))))
7756 < GET_MODE_BITSIZE (GET_MODE (x)))
7757 && (INTVAL (XEXP (x, 1))
7758 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7760 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7761 << INTVAL (XEXP (XEXP (x, 0), 1)));
7762 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7763 XEXP (XEXP (x, 0), 0), temp);
7764 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7765 XEXP (XEXP (x, 0), 1));
7766 return force_to_mode (x, mode, mask, next_select);
7770 /* For most binary operations, just propagate into the operation and
7771 change the mode if we have an operation of that mode. */
7773 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7774 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7776 /* If we ended up truncating both operands, truncate the result of the
7777 operation instead. */
7778 if (GET_CODE (op0) == TRUNCATE
7779 && GET_CODE (op1) == TRUNCATE)
7781 op0 = XEXP (op0, 0);
7782 op1 = XEXP (op1, 0);
7785 op0 = gen_lowpart_or_truncate (op_mode, op0);
7786 op1 = gen_lowpart_or_truncate (op_mode, op1);
7788 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7789 x = simplify_gen_binary (code, op_mode, op0, op1);
7793 /* For left shifts, do the same, but just for the first operand.
7794 However, we cannot do anything with shifts where we cannot
7795 guarantee that the counts are smaller than the size of the mode
7796 because such a count will have a different meaning in a
7799 if (! (CONST_INT_P (XEXP (x, 1))
7800 && INTVAL (XEXP (x, 1)) >= 0
7801 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7802 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7803 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7804 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7807 /* If the shift count is a constant and we can do arithmetic in
7808 the mode of the shift, refine which bits we need. Otherwise, use the
7809 conservative form of the mask. */
7810 if (CONST_INT_P (XEXP (x, 1))
7811 && INTVAL (XEXP (x, 1)) >= 0
7812 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7813 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7814 mask >>= INTVAL (XEXP (x, 1));
7818 op0 = gen_lowpart_or_truncate (op_mode,
7819 force_to_mode (XEXP (x, 0), op_mode,
7820 mask, next_select));
7822 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7823 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7827 /* Here we can only do something if the shift count is a constant,
7828 this shift constant is valid for the host, and we can do arithmetic
7831 if (CONST_INT_P (XEXP (x, 1))
7832 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7833 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7835 rtx inner = XEXP (x, 0);
7836 unsigned HOST_WIDE_INT inner_mask;
7838 /* Select the mask of the bits we need for the shift operand. */
7839 inner_mask = mask << INTVAL (XEXP (x, 1));
7841 /* We can only change the mode of the shift if we can do arithmetic
7842 in the mode of the shift and INNER_MASK is no wider than the
7843 width of X's mode. */
7844 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7845 op_mode = GET_MODE (x);
7847 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7849 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7850 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7853 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7854 shift and AND produces only copies of the sign bit (C2 is one less
7855 than a power of two), we can do this with just a shift. */
7857 if (GET_CODE (x) == LSHIFTRT
7858 && CONST_INT_P (XEXP (x, 1))
7859 /* The shift puts one of the sign bit copies in the least significant
7861 && ((INTVAL (XEXP (x, 1))
7862 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7863 >= GET_MODE_BITSIZE (GET_MODE (x)))
7864 && exact_log2 (mask + 1) >= 0
7865 /* Number of bits left after the shift must be more than the mask
7867 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7868 <= GET_MODE_BITSIZE (GET_MODE (x)))
7869 /* Must be more sign bit copies than the mask needs. */
7870 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7871 >= exact_log2 (mask + 1)))
7872 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7873 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7874 - exact_log2 (mask + 1)));
7879 /* If we are just looking for the sign bit, we don't need this shift at
7880 all, even if it has a variable count. */
7881 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7882 && (mask == ((unsigned HOST_WIDE_INT) 1
7883 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7884 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7886 /* If this is a shift by a constant, get a mask that contains those bits
7887 that are not copies of the sign bit. We then have two cases: If
7888 MASK only includes those bits, this can be a logical shift, which may
7889 allow simplifications. If MASK is a single-bit field not within
7890 those bits, we are requesting a copy of the sign bit and hence can
7891 shift the sign bit to the appropriate location. */
7893 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7894 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7898 /* If the considered data is wider than HOST_WIDE_INT, we can't
7899 represent a mask for all its bits in a single scalar.
7900 But we only care about the lower bits, so calculate these. */
7902 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7904 nonzero = ~(HOST_WIDE_INT) 0;
7906 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7907 is the number of bits a full-width mask would have set.
7908 We need only shift if these are fewer than nonzero can
7909 hold. If not, we must keep all bits set in nonzero. */
7911 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7912 < HOST_BITS_PER_WIDE_INT)
7913 nonzero >>= INTVAL (XEXP (x, 1))
7914 + HOST_BITS_PER_WIDE_INT
7915 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7919 nonzero = GET_MODE_MASK (GET_MODE (x));
7920 nonzero >>= INTVAL (XEXP (x, 1));
7923 if ((mask & ~nonzero) == 0)
7925 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7926 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7927 if (GET_CODE (x) != ASHIFTRT)
7928 return force_to_mode (x, mode, mask, next_select);
7931 else if ((i = exact_log2 (mask)) >= 0)
7933 x = simplify_shift_const
7934 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7935 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7937 if (GET_CODE (x) != ASHIFTRT)
7938 return force_to_mode (x, mode, mask, next_select);
7942 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7943 even if the shift count isn't a constant. */
7945 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7946 XEXP (x, 0), XEXP (x, 1));
7950 /* If this is a zero- or sign-extension operation that just affects bits
7951 we don't care about, remove it. Be sure the call above returned
7952 something that is still a shift. */
7954 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7955 && CONST_INT_P (XEXP (x, 1))
7956 && INTVAL (XEXP (x, 1)) >= 0
7957 && (INTVAL (XEXP (x, 1))
7958 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7959 && GET_CODE (XEXP (x, 0)) == ASHIFT
7960 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7961 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7968 /* If the shift count is constant and we can do computations
7969 in the mode of X, compute where the bits we care about are.
7970 Otherwise, we can't do anything. Don't change the mode of
7971 the shift or propagate MODE into the shift, though. */
7972 if (CONST_INT_P (XEXP (x, 1))
7973 && INTVAL (XEXP (x, 1)) >= 0)
7975 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7976 GET_MODE (x), GEN_INT (mask),
7978 if (temp && CONST_INT_P (temp))
7980 force_to_mode (XEXP (x, 0), GET_MODE (x),
7981 INTVAL (temp), next_select));
7986 /* If we just want the low-order bit, the NEG isn't needed since it
7987 won't change the low-order bit. */
7989 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7991 /* We need any bits less significant than the most significant bit in
7992 MASK since carries from those bits will affect the bits we are
7998 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7999 same as the XOR case above. Ensure that the constant we form is not
8000 wider than the mode of X. */
8002 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8003 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8004 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8005 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8006 < GET_MODE_BITSIZE (GET_MODE (x)))
8007 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8009 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8011 temp = simplify_gen_binary (XOR, GET_MODE (x),
8012 XEXP (XEXP (x, 0), 0), temp);
8013 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8014 temp, XEXP (XEXP (x, 0), 1));
8016 return force_to_mode (x, mode, mask, next_select);
8019 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8020 use the full mask inside the NOT. */
8024 op0 = gen_lowpart_or_truncate (op_mode,
8025 force_to_mode (XEXP (x, 0), mode, mask,
8027 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8028 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8032 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8033 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8034 which is equal to STORE_FLAG_VALUE. */
8035 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8036 && GET_MODE (XEXP (x, 0)) == mode
8037 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8038 && (nonzero_bits (XEXP (x, 0), mode)
8039 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8040 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8045 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8046 written in a narrower mode. We play it safe and do not do so. */
8049 gen_lowpart_or_truncate (GET_MODE (x),
8050 force_to_mode (XEXP (x, 1), mode,
8051 mask, next_select)));
8053 gen_lowpart_or_truncate (GET_MODE (x),
8054 force_to_mode (XEXP (x, 2), mode,
8055 mask, next_select)));
8062 /* Ensure we return a value of the proper mode. */
8063 return gen_lowpart_or_truncate (mode, x);
8066 /* Return nonzero if X is an expression that has one of two values depending on
8067 whether some other value is zero or nonzero. In that case, we return the
8068 value that is being tested, *PTRUE is set to the value if the rtx being
8069 returned has a nonzero value, and *PFALSE is set to the other alternative.
8071 If we return zero, we set *PTRUE and *PFALSE to X. */
8074 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8076 enum machine_mode mode = GET_MODE (x);
8077 enum rtx_code code = GET_CODE (x);
8078 rtx cond0, cond1, true0, true1, false0, false1;
8079 unsigned HOST_WIDE_INT nz;
8081 /* If we are comparing a value against zero, we are done. */
8082 if ((code == NE || code == EQ)
8083 && XEXP (x, 1) == const0_rtx)
8085 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8086 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8090 /* If this is a unary operation whose operand has one of two values, apply
8091 our opcode to compute those values. */
8092 else if (UNARY_P (x)
8093 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8095 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8096 *pfalse = simplify_gen_unary (code, mode, false0,
8097 GET_MODE (XEXP (x, 0)));
8101 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8102 make can't possibly match and would suppress other optimizations. */
8103 else if (code == COMPARE)
8106 /* If this is a binary operation, see if either side has only one of two
8107 values. If either one does or if both do and they are conditional on
8108 the same value, compute the new true and false values. */
8109 else if (BINARY_P (x))
8111 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8112 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8114 if ((cond0 != 0 || cond1 != 0)
8115 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8117 /* If if_then_else_cond returned zero, then true/false are the
8118 same rtl. We must copy one of them to prevent invalid rtl
8121 true0 = copy_rtx (true0);
8122 else if (cond1 == 0)
8123 true1 = copy_rtx (true1);
8125 if (COMPARISON_P (x))
8127 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8129 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8134 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8135 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8138 return cond0 ? cond0 : cond1;
8141 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8142 operands is zero when the other is nonzero, and vice-versa,
8143 and STORE_FLAG_VALUE is 1 or -1. */
8145 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8146 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8148 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8150 rtx op0 = XEXP (XEXP (x, 0), 1);
8151 rtx op1 = XEXP (XEXP (x, 1), 1);
8153 cond0 = XEXP (XEXP (x, 0), 0);
8154 cond1 = XEXP (XEXP (x, 1), 0);
8156 if (COMPARISON_P (cond0)
8157 && COMPARISON_P (cond1)
8158 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8159 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8160 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8161 || ((swap_condition (GET_CODE (cond0))
8162 == reversed_comparison_code (cond1, NULL))
8163 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8164 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8165 && ! side_effects_p (x))
8167 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8168 *pfalse = simplify_gen_binary (MULT, mode,
8170 ? simplify_gen_unary (NEG, mode,
8178 /* Similarly for MULT, AND and UMIN, except that for these the result
8180 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8181 && (code == MULT || code == AND || code == UMIN)
8182 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8184 cond0 = XEXP (XEXP (x, 0), 0);
8185 cond1 = XEXP (XEXP (x, 1), 0);
8187 if (COMPARISON_P (cond0)
8188 && COMPARISON_P (cond1)
8189 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8190 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8191 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8192 || ((swap_condition (GET_CODE (cond0))
8193 == reversed_comparison_code (cond1, NULL))
8194 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8195 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8196 && ! side_effects_p (x))
8198 *ptrue = *pfalse = const0_rtx;
8204 else if (code == IF_THEN_ELSE)
8206 /* If we have IF_THEN_ELSE already, extract the condition and
8207 canonicalize it if it is NE or EQ. */
8208 cond0 = XEXP (x, 0);
8209 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8210 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8211 return XEXP (cond0, 0);
8212 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8214 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8215 return XEXP (cond0, 0);
8221 /* If X is a SUBREG, we can narrow both the true and false values
8222 if the inner expression, if there is a condition. */
8223 else if (code == SUBREG
8224 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8227 true0 = simplify_gen_subreg (mode, true0,
8228 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8229 false0 = simplify_gen_subreg (mode, false0,
8230 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8231 if (true0 && false0)
8239 /* If X is a constant, this isn't special and will cause confusions
8240 if we treat it as such. Likewise if it is equivalent to a constant. */
8241 else if (CONSTANT_P (x)
8242 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8245 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8246 will be least confusing to the rest of the compiler. */
8247 else if (mode == BImode)
8249 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8253 /* If X is known to be either 0 or -1, those are the true and
8254 false values when testing X. */
8255 else if (x == constm1_rtx || x == const0_rtx
8256 || (mode != VOIDmode
8257 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8259 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8263 /* Likewise for 0 or a single bit. */
8264 else if (SCALAR_INT_MODE_P (mode)
8265 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8266 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8268 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8272 /* Otherwise fail; show no condition with true and false values the same. */
8273 *ptrue = *pfalse = x;
8277 /* Return the value of expression X given the fact that condition COND
8278 is known to be true when applied to REG as its first operand and VAL
8279 as its second. X is known to not be shared and so can be modified in
8282 We only handle the simplest cases, and specifically those cases that
8283 arise with IF_THEN_ELSE expressions. */
8286 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8288 enum rtx_code code = GET_CODE (x);
8293 if (side_effects_p (x))
8296 /* If either operand of the condition is a floating point value,
8297 then we have to avoid collapsing an EQ comparison. */
8299 && rtx_equal_p (x, reg)
8300 && ! FLOAT_MODE_P (GET_MODE (x))
8301 && ! FLOAT_MODE_P (GET_MODE (val)))
8304 if (cond == UNEQ && rtx_equal_p (x, reg))
8307 /* If X is (abs REG) and we know something about REG's relationship
8308 with zero, we may be able to simplify this. */
8310 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8313 case GE: case GT: case EQ:
8316 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8318 GET_MODE (XEXP (x, 0)));
8323 /* The only other cases we handle are MIN, MAX, and comparisons if the
8324 operands are the same as REG and VAL. */
8326 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8328 if (rtx_equal_p (XEXP (x, 0), val))
8329 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8331 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8333 if (COMPARISON_P (x))
8335 if (comparison_dominates_p (cond, code))
8336 return const_true_rtx;
8338 code = reversed_comparison_code (x, NULL);
8340 && comparison_dominates_p (cond, code))
8345 else if (code == SMAX || code == SMIN
8346 || code == UMIN || code == UMAX)
8348 int unsignedp = (code == UMIN || code == UMAX);
8350 /* Do not reverse the condition when it is NE or EQ.
8351 This is because we cannot conclude anything about
8352 the value of 'SMAX (x, y)' when x is not equal to y,
8353 but we can when x equals y. */
8354 if ((code == SMAX || code == UMAX)
8355 && ! (cond == EQ || cond == NE))
8356 cond = reverse_condition (cond);
8361 return unsignedp ? x : XEXP (x, 1);
8363 return unsignedp ? x : XEXP (x, 0);
8365 return unsignedp ? XEXP (x, 1) : x;
8367 return unsignedp ? XEXP (x, 0) : x;
8374 else if (code == SUBREG)
8376 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8377 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8379 if (SUBREG_REG (x) != r)
8381 /* We must simplify subreg here, before we lose track of the
8382 original inner_mode. */
8383 new_rtx = simplify_subreg (GET_MODE (x), r,
8384 inner_mode, SUBREG_BYTE (x));
8388 SUBST (SUBREG_REG (x), r);
8393 /* We don't have to handle SIGN_EXTEND here, because even in the
8394 case of replacing something with a modeless CONST_INT, a
8395 CONST_INT is already (supposed to be) a valid sign extension for
8396 its narrower mode, which implies it's already properly
8397 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8398 story is different. */
8399 else if (code == ZERO_EXTEND)
8401 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8402 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8404 if (XEXP (x, 0) != r)
8406 /* We must simplify the zero_extend here, before we lose
8407 track of the original inner_mode. */
8408 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8413 SUBST (XEXP (x, 0), r);
8419 fmt = GET_RTX_FORMAT (code);
8420 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8423 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8424 else if (fmt[i] == 'E')
8425 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8426 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8433 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8434 assignment as a field assignment. */
8437 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8439 if (x == y || rtx_equal_p (x, y))
8442 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8445 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8446 Note that all SUBREGs of MEM are paradoxical; otherwise they
8447 would have been rewritten. */
8448 if (MEM_P (x) && GET_CODE (y) == SUBREG
8449 && MEM_P (SUBREG_REG (y))
8450 && rtx_equal_p (SUBREG_REG (y),
8451 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8454 if (MEM_P (y) && GET_CODE (x) == SUBREG
8455 && MEM_P (SUBREG_REG (x))
8456 && rtx_equal_p (SUBREG_REG (x),
8457 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8460 /* We used to see if get_last_value of X and Y were the same but that's
8461 not correct. In one direction, we'll cause the assignment to have
8462 the wrong destination and in the case, we'll import a register into this
8463 insn that might have already have been dead. So fail if none of the
8464 above cases are true. */
8468 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8469 Return that assignment if so.
8471 We only handle the most common cases. */
8474 make_field_assignment (rtx x)
8476 rtx dest = SET_DEST (x);
8477 rtx src = SET_SRC (x);
8482 unsigned HOST_WIDE_INT len;
8484 enum machine_mode mode;
8486 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8487 a clear of a one-bit field. We will have changed it to
8488 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8491 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8492 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8493 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8494 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8496 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8499 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8503 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8504 && subreg_lowpart_p (XEXP (src, 0))
8505 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8506 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8507 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8508 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8509 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8510 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8512 assign = make_extraction (VOIDmode, dest, 0,
8513 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8516 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8520 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8522 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8523 && XEXP (XEXP (src, 0), 0) == const1_rtx
8524 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8526 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8529 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8533 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8534 SRC is an AND with all bits of that field set, then we can discard
8536 if (GET_CODE (dest) == ZERO_EXTRACT
8537 && CONST_INT_P (XEXP (dest, 1))
8538 && GET_CODE (src) == AND
8539 && CONST_INT_P (XEXP (src, 1)))
8541 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8542 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8543 unsigned HOST_WIDE_INT ze_mask;
8545 if (width >= HOST_BITS_PER_WIDE_INT)
8548 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8550 /* Complete overlap. We can remove the source AND. */
8551 if ((and_mask & ze_mask) == ze_mask)
8552 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8554 /* Partial overlap. We can reduce the source AND. */
8555 if ((and_mask & ze_mask) != and_mask)
8557 mode = GET_MODE (src);
8558 src = gen_rtx_AND (mode, XEXP (src, 0),
8559 gen_int_mode (and_mask & ze_mask, mode));
8560 return gen_rtx_SET (VOIDmode, dest, src);
8564 /* The other case we handle is assignments into a constant-position
8565 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8566 a mask that has all one bits except for a group of zero bits and
8567 OTHER is known to have zeros where C1 has ones, this is such an
8568 assignment. Compute the position and length from C1. Shift OTHER
8569 to the appropriate position, force it to the required mode, and
8570 make the extraction. Check for the AND in both operands. */
8572 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8575 rhs = expand_compound_operation (XEXP (src, 0));
8576 lhs = expand_compound_operation (XEXP (src, 1));
8578 if (GET_CODE (rhs) == AND
8579 && CONST_INT_P (XEXP (rhs, 1))
8580 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8581 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8582 else if (GET_CODE (lhs) == AND
8583 && CONST_INT_P (XEXP (lhs, 1))
8584 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8585 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8589 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8590 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8591 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8592 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8595 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8599 /* The mode to use for the source is the mode of the assignment, or of
8600 what is inside a possible STRICT_LOW_PART. */
8601 mode = (GET_CODE (assign) == STRICT_LOW_PART
8602 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8604 /* Shift OTHER right POS places and make it the source, restricting it
8605 to the proper length and mode. */
8607 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8611 src = force_to_mode (src, mode,
8612 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8613 ? ~(unsigned HOST_WIDE_INT) 0
8614 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8617 /* If SRC is masked by an AND that does not make a difference in
8618 the value being stored, strip it. */
8619 if (GET_CODE (assign) == ZERO_EXTRACT
8620 && CONST_INT_P (XEXP (assign, 1))
8621 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8622 && GET_CODE (src) == AND
8623 && CONST_INT_P (XEXP (src, 1))
8624 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8625 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8626 src = XEXP (src, 0);
8628 return gen_rtx_SET (VOIDmode, assign, src);
8631 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8635 apply_distributive_law (rtx x)
8637 enum rtx_code code = GET_CODE (x);
8638 enum rtx_code inner_code;
8639 rtx lhs, rhs, other;
8642 /* Distributivity is not true for floating point as it can change the
8643 value. So we don't do it unless -funsafe-math-optimizations. */
8644 if (FLOAT_MODE_P (GET_MODE (x))
8645 && ! flag_unsafe_math_optimizations)
8648 /* The outer operation can only be one of the following: */
8649 if (code != IOR && code != AND && code != XOR
8650 && code != PLUS && code != MINUS)
8656 /* If either operand is a primitive we can't do anything, so get out
8658 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8661 lhs = expand_compound_operation (lhs);
8662 rhs = expand_compound_operation (rhs);
8663 inner_code = GET_CODE (lhs);
8664 if (inner_code != GET_CODE (rhs))
8667 /* See if the inner and outer operations distribute. */
8674 /* These all distribute except over PLUS. */
8675 if (code == PLUS || code == MINUS)
8680 if (code != PLUS && code != MINUS)
8685 /* This is also a multiply, so it distributes over everything. */
8689 /* Non-paradoxical SUBREGs distributes over all operations,
8690 provided the inner modes and byte offsets are the same, this
8691 is an extraction of a low-order part, we don't convert an fp
8692 operation to int or vice versa, this is not a vector mode,
8693 and we would not be converting a single-word operation into a
8694 multi-word operation. The latter test is not required, but
8695 it prevents generating unneeded multi-word operations. Some
8696 of the previous tests are redundant given the latter test,
8697 but are retained because they are required for correctness.
8699 We produce the result slightly differently in this case. */
8701 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8702 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8703 || ! subreg_lowpart_p (lhs)
8704 || (GET_MODE_CLASS (GET_MODE (lhs))
8705 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8706 || (GET_MODE_SIZE (GET_MODE (lhs))
8707 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8708 || VECTOR_MODE_P (GET_MODE (lhs))
8709 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8710 /* Result might need to be truncated. Don't change mode if
8711 explicit truncation is needed. */
8712 || !TRULY_NOOP_TRUNCATION
8713 (GET_MODE_BITSIZE (GET_MODE (x)),
8714 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8717 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8718 SUBREG_REG (lhs), SUBREG_REG (rhs));
8719 return gen_lowpart (GET_MODE (x), tem);
8725 /* Set LHS and RHS to the inner operands (A and B in the example
8726 above) and set OTHER to the common operand (C in the example).
8727 There is only one way to do this unless the inner operation is
8729 if (COMMUTATIVE_ARITH_P (lhs)
8730 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8731 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8732 else if (COMMUTATIVE_ARITH_P (lhs)
8733 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8734 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8735 else if (COMMUTATIVE_ARITH_P (lhs)
8736 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8737 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8738 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8739 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8743 /* Form the new inner operation, seeing if it simplifies first. */
8744 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8746 /* There is one exception to the general way of distributing:
8747 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8748 if (code == XOR && inner_code == IOR)
8751 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8754 /* We may be able to continuing distributing the result, so call
8755 ourselves recursively on the inner operation before forming the
8756 outer operation, which we return. */
8757 return simplify_gen_binary (inner_code, GET_MODE (x),
8758 apply_distributive_law (tem), other);
8761 /* See if X is of the form (* (+ A B) C), and if so convert to
8762 (+ (* A C) (* B C)) and try to simplify.
8764 Most of the time, this results in no change. However, if some of
8765 the operands are the same or inverses of each other, simplifications
8768 For example, (and (ior A B) (not B)) can occur as the result of
8769 expanding a bit field assignment. When we apply the distributive
8770 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8771 which then simplifies to (and (A (not B))).
8773 Note that no checks happen on the validity of applying the inverse
8774 distributive law. This is pointless since we can do it in the
8775 few places where this routine is called.
8777 N is the index of the term that is decomposed (the arithmetic operation,
8778 i.e. (+ A B) in the first example above). !N is the index of the term that
8779 is distributed, i.e. of C in the first example above. */
8781 distribute_and_simplify_rtx (rtx x, int n)
8783 enum machine_mode mode;
8784 enum rtx_code outer_code, inner_code;
8785 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8787 /* Distributivity is not true for floating point as it can change the
8788 value. So we don't do it unless -funsafe-math-optimizations. */
8789 if (FLOAT_MODE_P (GET_MODE (x))
8790 && ! flag_unsafe_math_optimizations)
8793 decomposed = XEXP (x, n);
8794 if (!ARITHMETIC_P (decomposed))
8797 mode = GET_MODE (x);
8798 outer_code = GET_CODE (x);
8799 distributed = XEXP (x, !n);
8801 inner_code = GET_CODE (decomposed);
8802 inner_op0 = XEXP (decomposed, 0);
8803 inner_op1 = XEXP (decomposed, 1);
8805 /* Special case (and (xor B C) (not A)), which is equivalent to
8806 (xor (ior A B) (ior A C)) */
8807 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8809 distributed = XEXP (distributed, 0);
8815 /* Distribute the second term. */
8816 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8817 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8821 /* Distribute the first term. */
8822 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8823 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8826 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8828 if (GET_CODE (tmp) != outer_code
8829 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8830 < rtx_cost (x, SET, optimize_this_for_speed_p))
8836 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8837 in MODE. Return an equivalent form, if different from (and VAROP
8838 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8841 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8842 unsigned HOST_WIDE_INT constop)
8844 unsigned HOST_WIDE_INT nonzero;
8845 unsigned HOST_WIDE_INT orig_constop;
8850 orig_constop = constop;
8851 if (GET_CODE (varop) == CLOBBER)
8854 /* Simplify VAROP knowing that we will be only looking at some of the
8857 Note by passing in CONSTOP, we guarantee that the bits not set in
8858 CONSTOP are not significant and will never be examined. We must
8859 ensure that is the case by explicitly masking out those bits
8860 before returning. */
8861 varop = force_to_mode (varop, mode, constop, 0);
8863 /* If VAROP is a CLOBBER, we will fail so return it. */
8864 if (GET_CODE (varop) == CLOBBER)
8867 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8868 to VAROP and return the new constant. */
8869 if (CONST_INT_P (varop))
8870 return gen_int_mode (INTVAL (varop) & constop, mode);
8872 /* See what bits may be nonzero in VAROP. Unlike the general case of
8873 a call to nonzero_bits, here we don't care about bits outside
8876 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8878 /* Turn off all bits in the constant that are known to already be zero.
8879 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8880 which is tested below. */
8884 /* If we don't have any bits left, return zero. */
8888 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8889 a power of two, we can replace this with an ASHIFT. */
8890 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8891 && (i = exact_log2 (constop)) >= 0)
8892 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8894 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8895 or XOR, then try to apply the distributive law. This may eliminate
8896 operations if either branch can be simplified because of the AND.
8897 It may also make some cases more complex, but those cases probably
8898 won't match a pattern either with or without this. */
8900 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8904 apply_distributive_law
8905 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8906 simplify_and_const_int (NULL_RTX,
8910 simplify_and_const_int (NULL_RTX,
8915 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8916 the AND and see if one of the operands simplifies to zero. If so, we
8917 may eliminate it. */
8919 if (GET_CODE (varop) == PLUS
8920 && exact_log2 (constop + 1) >= 0)
8924 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8925 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8926 if (o0 == const0_rtx)
8928 if (o1 == const0_rtx)
8932 /* Make a SUBREG if necessary. If we can't make it, fail. */
8933 varop = gen_lowpart (mode, varop);
8934 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8937 /* If we are only masking insignificant bits, return VAROP. */
8938 if (constop == nonzero)
8941 if (varop == orig_varop && constop == orig_constop)
8944 /* Otherwise, return an AND. */
8945 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8949 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8952 Return an equivalent form, if different from X. Otherwise, return X. If
8953 X is zero, we are to always construct the equivalent form. */
8956 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8957 unsigned HOST_WIDE_INT constop)
8959 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8964 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8965 gen_int_mode (constop, mode));
8966 if (GET_MODE (x) != mode)
8967 x = gen_lowpart (mode, x);
8971 /* Given a REG, X, compute which bits in X can be nonzero.
8972 We don't care about bits outside of those defined in MODE.
8974 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8975 a shift, AND, or zero_extract, we can do better. */
8978 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8979 const_rtx known_x ATTRIBUTE_UNUSED,
8980 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8981 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8982 unsigned HOST_WIDE_INT *nonzero)
8987 /* If X is a register whose nonzero bits value is current, use it.
8988 Otherwise, if X is a register whose value we can find, use that
8989 value. Otherwise, use the previously-computed global nonzero bits
8990 for this register. */
8992 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8993 if (rsp->last_set_value != 0
8994 && (rsp->last_set_mode == mode
8995 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8996 && GET_MODE_CLASS (mode) == MODE_INT))
8997 && ((rsp->last_set_label >= label_tick_ebb_start
8998 && rsp->last_set_label < label_tick)
8999 || (rsp->last_set_label == label_tick
9000 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9001 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9002 && REG_N_SETS (REGNO (x)) == 1
9004 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9006 *nonzero &= rsp->last_set_nonzero_bits;
9010 tem = get_last_value (x);
9014 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9015 /* If X is narrower than MODE and TEM is a non-negative
9016 constant that would appear negative in the mode of X,
9017 sign-extend it for use in reg_nonzero_bits because some
9018 machines (maybe most) will actually do the sign-extension
9019 and this is the conservative approach.
9021 ??? For 2.5, try to tighten up the MD files in this regard
9022 instead of this kludge. */
9024 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9025 && CONST_INT_P (tem)
9027 && 0 != (INTVAL (tem)
9028 & ((HOST_WIDE_INT) 1
9029 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9030 tem = GEN_INT (INTVAL (tem)
9031 | ((HOST_WIDE_INT) (-1)
9032 << GET_MODE_BITSIZE (GET_MODE (x))));
9036 else if (nonzero_sign_valid && rsp->nonzero_bits)
9038 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9040 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9041 /* We don't know anything about the upper bits. */
9042 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9049 /* Return the number of bits at the high-order end of X that are known to
9050 be equal to the sign bit. X will be used in mode MODE; if MODE is
9051 VOIDmode, X will be used in its own mode. The returned value will always
9052 be between 1 and the number of bits in MODE. */
9055 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9056 const_rtx known_x ATTRIBUTE_UNUSED,
9057 enum machine_mode known_mode
9059 unsigned int known_ret ATTRIBUTE_UNUSED,
9060 unsigned int *result)
9065 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9066 if (rsp->last_set_value != 0
9067 && rsp->last_set_mode == mode
9068 && ((rsp->last_set_label >= label_tick_ebb_start
9069 && rsp->last_set_label < label_tick)
9070 || (rsp->last_set_label == label_tick
9071 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9072 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9073 && REG_N_SETS (REGNO (x)) == 1
9075 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9077 *result = rsp->last_set_sign_bit_copies;
9081 tem = get_last_value (x);
9085 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9086 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9087 *result = rsp->sign_bit_copies;
9092 /* Return the number of "extended" bits there are in X, when interpreted
9093 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9094 unsigned quantities, this is the number of high-order zero bits.
9095 For signed quantities, this is the number of copies of the sign bit
9096 minus 1. In both case, this function returns the number of "spare"
9097 bits. For example, if two quantities for which this function returns
9098 at least 1 are added, the addition is known not to overflow.
9100 This function will always return 0 unless called during combine, which
9101 implies that it must be called from a define_split. */
9104 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9106 if (nonzero_sign_valid == 0)
9110 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9111 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9112 - floor_log2 (nonzero_bits (x, mode)))
9114 : num_sign_bit_copies (x, mode) - 1);
9117 /* This function is called from `simplify_shift_const' to merge two
9118 outer operations. Specifically, we have already found that we need
9119 to perform operation *POP0 with constant *PCONST0 at the outermost
9120 position. We would now like to also perform OP1 with constant CONST1
9121 (with *POP0 being done last).
9123 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9124 the resulting operation. *PCOMP_P is set to 1 if we would need to
9125 complement the innermost operand, otherwise it is unchanged.
9127 MODE is the mode in which the operation will be done. No bits outside
9128 the width of this mode matter. It is assumed that the width of this mode
9129 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9131 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9132 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9133 result is simply *PCONST0.
9135 If the resulting operation cannot be expressed as one operation, we
9136 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9139 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9141 enum rtx_code op0 = *pop0;
9142 HOST_WIDE_INT const0 = *pconst0;
9144 const0 &= GET_MODE_MASK (mode);
9145 const1 &= GET_MODE_MASK (mode);
9147 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9151 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9154 if (op1 == UNKNOWN || op0 == SET)
9157 else if (op0 == UNKNOWN)
9158 op0 = op1, const0 = const1;
9160 else if (op0 == op1)
9184 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9185 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9188 /* If the two constants aren't the same, we can't do anything. The
9189 remaining six cases can all be done. */
9190 else if (const0 != const1)
9198 /* (a & b) | b == b */
9200 else /* op1 == XOR */
9201 /* (a ^ b) | b == a | b */
9207 /* (a & b) ^ b == (~a) & b */
9208 op0 = AND, *pcomp_p = 1;
9209 else /* op1 == IOR */
9210 /* (a | b) ^ b == a & ~b */
9211 op0 = AND, const0 = ~const0;
9216 /* (a | b) & b == b */
9218 else /* op1 == XOR */
9219 /* (a ^ b) & b) == (~a) & b */
9226 /* Check for NO-OP cases. */
9227 const0 &= GET_MODE_MASK (mode);
9229 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9231 else if (const0 == 0 && op0 == AND)
9233 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9239 /* ??? Slightly redundant with the above mask, but not entirely.
9240 Moving this above means we'd have to sign-extend the mode mask
9241 for the final test. */
9242 if (op0 != UNKNOWN && op0 != NEG)
9243 *pconst0 = trunc_int_for_mode (const0, mode);
9248 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9249 the shift in. The original shift operation CODE is performed on OP in
9250 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9251 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9252 result of the shift is subject to operation OUTER_CODE with operand
9255 static enum machine_mode
9256 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9257 enum machine_mode orig_mode, enum machine_mode mode,
9258 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9260 if (orig_mode == mode)
9262 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9264 /* In general we can't perform in wider mode for right shift and rotate. */
9268 /* We can still widen if the bits brought in from the left are identical
9269 to the sign bit of ORIG_MODE. */
9270 if (num_sign_bit_copies (op, mode)
9271 > (unsigned) (GET_MODE_BITSIZE (mode)
9272 - GET_MODE_BITSIZE (orig_mode)))
9277 /* Similarly here but with zero bits. */
9278 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9279 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9282 /* We can also widen if the bits brought in will be masked off. This
9283 operation is performed in ORIG_MODE. */
9284 if (outer_code == AND)
9286 int care_bits = low_bitmask_len (orig_mode, outer_const);
9289 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9305 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9306 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9307 simplify it. Otherwise, return a simplified value.
9309 The shift is normally computed in the widest mode we find in VAROP, as
9310 long as it isn't a different number of words than RESULT_MODE. Exceptions
9311 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9314 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9315 rtx varop, int orig_count)
9317 enum rtx_code orig_code = code;
9318 rtx orig_varop = varop;
9320 enum machine_mode mode = result_mode;
9321 enum machine_mode shift_mode, tmode;
9322 unsigned int mode_words
9323 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9324 /* We form (outer_op (code varop count) (outer_const)). */
9325 enum rtx_code outer_op = UNKNOWN;
9326 HOST_WIDE_INT outer_const = 0;
9327 int complement_p = 0;
9330 /* Make sure and truncate the "natural" shift on the way in. We don't
9331 want to do this inside the loop as it makes it more difficult to
9333 if (SHIFT_COUNT_TRUNCATED)
9334 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9336 /* If we were given an invalid count, don't do anything except exactly
9337 what was requested. */
9339 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9344 /* Unless one of the branches of the `if' in this loop does a `continue',
9345 we will `break' the loop after the `if'. */
9349 /* If we have an operand of (clobber (const_int 0)), fail. */
9350 if (GET_CODE (varop) == CLOBBER)
9353 /* Convert ROTATERT to ROTATE. */
9354 if (code == ROTATERT)
9356 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9358 if (VECTOR_MODE_P (result_mode))
9359 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9361 count = bitsize - count;
9364 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9365 mode, outer_op, outer_const);
9367 /* Handle cases where the count is greater than the size of the mode
9368 minus 1. For ASHIFT, use the size minus one as the count (this can
9369 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9370 take the count modulo the size. For other shifts, the result is
9373 Since these shifts are being produced by the compiler by combining
9374 multiple operations, each of which are defined, we know what the
9375 result is supposed to be. */
9377 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9379 if (code == ASHIFTRT)
9380 count = GET_MODE_BITSIZE (shift_mode) - 1;
9381 else if (code == ROTATE || code == ROTATERT)
9382 count %= GET_MODE_BITSIZE (shift_mode);
9385 /* We can't simply return zero because there may be an
9393 /* If we discovered we had to complement VAROP, leave. Making a NOT
9394 here would cause an infinite loop. */
9398 /* An arithmetic right shift of a quantity known to be -1 or 0
9400 if (code == ASHIFTRT
9401 && (num_sign_bit_copies (varop, shift_mode)
9402 == GET_MODE_BITSIZE (shift_mode)))
9408 /* If we are doing an arithmetic right shift and discarding all but
9409 the sign bit copies, this is equivalent to doing a shift by the
9410 bitsize minus one. Convert it into that shift because it will often
9411 allow other simplifications. */
9413 if (code == ASHIFTRT
9414 && (count + num_sign_bit_copies (varop, shift_mode)
9415 >= GET_MODE_BITSIZE (shift_mode)))
9416 count = GET_MODE_BITSIZE (shift_mode) - 1;
9418 /* We simplify the tests below and elsewhere by converting
9419 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9420 `make_compound_operation' will convert it to an ASHIFTRT for
9421 those machines (such as VAX) that don't have an LSHIFTRT. */
9422 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9424 && ((nonzero_bits (varop, shift_mode)
9425 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9429 if (((code == LSHIFTRT
9430 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9431 && !(nonzero_bits (varop, shift_mode) >> count))
9433 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9434 && !((nonzero_bits (varop, shift_mode) << count)
9435 & GET_MODE_MASK (shift_mode))))
9436 && !side_effects_p (varop))
9439 switch (GET_CODE (varop))
9445 new_rtx = expand_compound_operation (varop);
9446 if (new_rtx != varop)
9454 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9455 minus the width of a smaller mode, we can do this with a
9456 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9457 if ((code == ASHIFTRT || code == LSHIFTRT)
9458 && ! mode_dependent_address_p (XEXP (varop, 0))
9459 && ! MEM_VOLATILE_P (varop)
9460 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9461 MODE_INT, 1)) != BLKmode)
9463 new_rtx = adjust_address_nv (varop, tmode,
9464 BYTES_BIG_ENDIAN ? 0
9465 : count / BITS_PER_UNIT);
9467 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9468 : ZERO_EXTEND, mode, new_rtx);
9475 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9476 the same number of words as what we've seen so far. Then store
9477 the widest mode in MODE. */
9478 if (subreg_lowpart_p (varop)
9479 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9480 > GET_MODE_SIZE (GET_MODE (varop)))
9481 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9482 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9485 varop = SUBREG_REG (varop);
9486 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9487 mode = GET_MODE (varop);
9493 /* Some machines use MULT instead of ASHIFT because MULT
9494 is cheaper. But it is still better on those machines to
9495 merge two shifts into one. */
9496 if (CONST_INT_P (XEXP (varop, 1))
9497 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9500 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9502 GEN_INT (exact_log2 (
9503 INTVAL (XEXP (varop, 1)))));
9509 /* Similar, for when divides are cheaper. */
9510 if (CONST_INT_P (XEXP (varop, 1))
9511 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9514 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9516 GEN_INT (exact_log2 (
9517 INTVAL (XEXP (varop, 1)))));
9523 /* If we are extracting just the sign bit of an arithmetic
9524 right shift, that shift is not needed. However, the sign
9525 bit of a wider mode may be different from what would be
9526 interpreted as the sign bit in a narrower mode, so, if
9527 the result is narrower, don't discard the shift. */
9528 if (code == LSHIFTRT
9529 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9530 && (GET_MODE_BITSIZE (result_mode)
9531 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9533 varop = XEXP (varop, 0);
9537 /* ... fall through ... */
9542 /* Here we have two nested shifts. The result is usually the
9543 AND of a new shift with a mask. We compute the result below. */
9544 if (CONST_INT_P (XEXP (varop, 1))
9545 && INTVAL (XEXP (varop, 1)) >= 0
9546 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9547 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9548 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9549 && !VECTOR_MODE_P (result_mode))
9551 enum rtx_code first_code = GET_CODE (varop);
9552 unsigned int first_count = INTVAL (XEXP (varop, 1));
9553 unsigned HOST_WIDE_INT mask;
9556 /* We have one common special case. We can't do any merging if
9557 the inner code is an ASHIFTRT of a smaller mode. However, if
9558 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9559 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9560 we can convert it to
9561 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9562 This simplifies certain SIGN_EXTEND operations. */
9563 if (code == ASHIFT && first_code == ASHIFTRT
9564 && count == (GET_MODE_BITSIZE (result_mode)
9565 - GET_MODE_BITSIZE (GET_MODE (varop))))
9567 /* C3 has the low-order C1 bits zero. */
9569 mask = (GET_MODE_MASK (mode)
9570 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9572 varop = simplify_and_const_int (NULL_RTX, result_mode,
9573 XEXP (varop, 0), mask);
9574 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9576 count = first_count;
9581 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9582 than C1 high-order bits equal to the sign bit, we can convert
9583 this to either an ASHIFT or an ASHIFTRT depending on the
9586 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9588 if (code == ASHIFTRT && first_code == ASHIFT
9589 && GET_MODE (varop) == shift_mode
9590 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9593 varop = XEXP (varop, 0);
9594 count -= first_count;
9604 /* There are some cases we can't do. If CODE is ASHIFTRT,
9605 we can only do this if FIRST_CODE is also ASHIFTRT.
9607 We can't do the case when CODE is ROTATE and FIRST_CODE is
9610 If the mode of this shift is not the mode of the outer shift,
9611 we can't do this if either shift is a right shift or ROTATE.
9613 Finally, we can't do any of these if the mode is too wide
9614 unless the codes are the same.
9616 Handle the case where the shift codes are the same
9619 if (code == first_code)
9621 if (GET_MODE (varop) != result_mode
9622 && (code == ASHIFTRT || code == LSHIFTRT
9626 count += first_count;
9627 varop = XEXP (varop, 0);
9631 if (code == ASHIFTRT
9632 || (code == ROTATE && first_code == ASHIFTRT)
9633 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9634 || (GET_MODE (varop) != result_mode
9635 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9636 || first_code == ROTATE
9637 || code == ROTATE)))
9640 /* To compute the mask to apply after the shift, shift the
9641 nonzero bits of the inner shift the same way the
9642 outer shift will. */
9644 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9647 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9650 /* Give up if we can't compute an outer operation to use. */
9652 || !CONST_INT_P (mask_rtx)
9653 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9655 result_mode, &complement_p))
9658 /* If the shifts are in the same direction, we add the
9659 counts. Otherwise, we subtract them. */
9660 if ((code == ASHIFTRT || code == LSHIFTRT)
9661 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9662 count += first_count;
9664 count -= first_count;
9666 /* If COUNT is positive, the new shift is usually CODE,
9667 except for the two exceptions below, in which case it is
9668 FIRST_CODE. If the count is negative, FIRST_CODE should
9671 && ((first_code == ROTATE && code == ASHIFT)
9672 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9675 code = first_code, count = -count;
9677 varop = XEXP (varop, 0);
9681 /* If we have (A << B << C) for any shift, we can convert this to
9682 (A << C << B). This wins if A is a constant. Only try this if
9683 B is not a constant. */
9685 else if (GET_CODE (varop) == code
9686 && CONST_INT_P (XEXP (varop, 0))
9687 && !CONST_INT_P (XEXP (varop, 1)))
9689 rtx new_rtx = simplify_const_binary_operation (code, mode,
9692 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9699 if (VECTOR_MODE_P (mode))
9702 /* Make this fit the case below. */
9703 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9704 GEN_INT (GET_MODE_MASK (mode)));
9710 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9711 with C the size of VAROP - 1 and the shift is logical if
9712 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9713 we have an (le X 0) operation. If we have an arithmetic shift
9714 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9715 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9717 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9718 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9719 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9720 && (code == LSHIFTRT || code == ASHIFTRT)
9721 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9722 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9725 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9728 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9729 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9734 /* If we have (shift (logical)), move the logical to the outside
9735 to allow it to possibly combine with another logical and the
9736 shift to combine with another shift. This also canonicalizes to
9737 what a ZERO_EXTRACT looks like. Also, some machines have
9738 (and (shift)) insns. */
9740 if (CONST_INT_P (XEXP (varop, 1))
9741 /* We can't do this if we have (ashiftrt (xor)) and the
9742 constant has its sign bit set in shift_mode. */
9743 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9744 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9746 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9748 GEN_INT (count))) != 0
9749 && CONST_INT_P (new_rtx)
9750 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9751 INTVAL (new_rtx), result_mode, &complement_p))
9753 varop = XEXP (varop, 0);
9757 /* If we can't do that, try to simplify the shift in each arm of the
9758 logical expression, make a new logical expression, and apply
9759 the inverse distributive law. This also can't be done
9760 for some (ashiftrt (xor)). */
9761 if (CONST_INT_P (XEXP (varop, 1))
9762 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9763 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9766 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9767 XEXP (varop, 0), count);
9768 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9769 XEXP (varop, 1), count);
9771 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9773 varop = apply_distributive_law (varop);
9781 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9782 says that the sign bit can be tested, FOO has mode MODE, C is
9783 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9784 that may be nonzero. */
9785 if (code == LSHIFTRT
9786 && XEXP (varop, 1) == const0_rtx
9787 && GET_MODE (XEXP (varop, 0)) == result_mode
9788 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9789 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9790 && STORE_FLAG_VALUE == -1
9791 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9792 && merge_outer_ops (&outer_op, &outer_const, XOR,
9793 (HOST_WIDE_INT) 1, result_mode,
9796 varop = XEXP (varop, 0);
9803 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9804 than the number of bits in the mode is equivalent to A. */
9805 if (code == LSHIFTRT
9806 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9807 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9809 varop = XEXP (varop, 0);
9814 /* NEG commutes with ASHIFT since it is multiplication. Move the
9815 NEG outside to allow shifts to combine. */
9817 && merge_outer_ops (&outer_op, &outer_const, NEG,
9818 (HOST_WIDE_INT) 0, result_mode,
9821 varop = XEXP (varop, 0);
9827 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9828 is one less than the number of bits in the mode is
9829 equivalent to (xor A 1). */
9830 if (code == LSHIFTRT
9831 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9832 && XEXP (varop, 1) == constm1_rtx
9833 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9834 && merge_outer_ops (&outer_op, &outer_const, XOR,
9835 (HOST_WIDE_INT) 1, result_mode,
9839 varop = XEXP (varop, 0);
9843 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9844 that might be nonzero in BAR are those being shifted out and those
9845 bits are known zero in FOO, we can replace the PLUS with FOO.
9846 Similarly in the other operand order. This code occurs when
9847 we are computing the size of a variable-size array. */
9849 if ((code == ASHIFTRT || code == LSHIFTRT)
9850 && count < HOST_BITS_PER_WIDE_INT
9851 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9852 && (nonzero_bits (XEXP (varop, 1), result_mode)
9853 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9855 varop = XEXP (varop, 0);
9858 else if ((code == ASHIFTRT || code == LSHIFTRT)
9859 && count < HOST_BITS_PER_WIDE_INT
9860 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9861 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9863 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9864 & nonzero_bits (XEXP (varop, 1),
9867 varop = XEXP (varop, 1);
9871 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9873 && CONST_INT_P (XEXP (varop, 1))
9874 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9876 GEN_INT (count))) != 0
9877 && CONST_INT_P (new_rtx)
9878 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9879 INTVAL (new_rtx), result_mode, &complement_p))
9881 varop = XEXP (varop, 0);
9885 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9886 signbit', and attempt to change the PLUS to an XOR and move it to
9887 the outer operation as is done above in the AND/IOR/XOR case
9888 leg for shift(logical). See details in logical handling above
9889 for reasoning in doing so. */
9890 if (code == LSHIFTRT
9891 && CONST_INT_P (XEXP (varop, 1))
9892 && mode_signbit_p (result_mode, XEXP (varop, 1))
9893 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9895 GEN_INT (count))) != 0
9896 && CONST_INT_P (new_rtx)
9897 && merge_outer_ops (&outer_op, &outer_const, XOR,
9898 INTVAL (new_rtx), result_mode, &complement_p))
9900 varop = XEXP (varop, 0);
9907 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9908 with C the size of VAROP - 1 and the shift is logical if
9909 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9910 we have a (gt X 0) operation. If the shift is arithmetic with
9911 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9912 we have a (neg (gt X 0)) operation. */
9914 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9915 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9916 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9917 && (code == LSHIFTRT || code == ASHIFTRT)
9918 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9919 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9920 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9923 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9926 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9927 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9934 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9935 if the truncate does not affect the value. */
9936 if (code == LSHIFTRT
9937 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9938 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9939 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9940 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9941 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9943 rtx varop_inner = XEXP (varop, 0);
9946 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9947 XEXP (varop_inner, 0),
9949 (count + INTVAL (XEXP (varop_inner, 1))));
9950 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9963 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9964 outer_op, outer_const);
9966 /* We have now finished analyzing the shift. The result should be
9967 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9968 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9969 to the result of the shift. OUTER_CONST is the relevant constant,
9970 but we must turn off all bits turned off in the shift. */
9972 if (outer_op == UNKNOWN
9973 && orig_code == code && orig_count == count
9974 && varop == orig_varop
9975 && shift_mode == GET_MODE (varop))
9978 /* Make a SUBREG if necessary. If we can't make it, fail. */
9979 varop = gen_lowpart (shift_mode, varop);
9980 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9983 /* If we have an outer operation and we just made a shift, it is
9984 possible that we could have simplified the shift were it not
9985 for the outer operation. So try to do the simplification
9988 if (outer_op != UNKNOWN)
9989 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9994 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9996 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9997 turn off all the bits that the shift would have turned off. */
9998 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9999 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10000 GET_MODE_MASK (result_mode) >> orig_count);
10002 /* Do the remainder of the processing in RESULT_MODE. */
10003 x = gen_lowpart_or_truncate (result_mode, x);
10005 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10008 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10010 if (outer_op != UNKNOWN)
10012 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10013 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10014 outer_const = trunc_int_for_mode (outer_const, result_mode);
10016 if (outer_op == AND)
10017 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10018 else if (outer_op == SET)
10020 /* This means that we have determined that the result is
10021 equivalent to a constant. This should be rare. */
10022 if (!side_effects_p (x))
10023 x = GEN_INT (outer_const);
10025 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10026 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10028 x = simplify_gen_binary (outer_op, result_mode, x,
10029 GEN_INT (outer_const));
10035 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10036 The result of the shift is RESULT_MODE. If we cannot simplify it,
10037 return X or, if it is NULL, synthesize the expression with
10038 simplify_gen_binary. Otherwise, return a simplified value.
10040 The shift is normally computed in the widest mode we find in VAROP, as
10041 long as it isn't a different number of words than RESULT_MODE. Exceptions
10042 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10045 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10046 rtx varop, int count)
10048 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10053 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10054 if (GET_MODE (x) != result_mode)
10055 x = gen_lowpart (result_mode, x);
10060 /* Like recog, but we receive the address of a pointer to a new pattern.
10061 We try to match the rtx that the pointer points to.
10062 If that fails, we may try to modify or replace the pattern,
10063 storing the replacement into the same pointer object.
10065 Modifications include deletion or addition of CLOBBERs.
10067 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10068 the CLOBBERs are placed.
10070 The value is the final insn code from the pattern ultimately matched,
10074 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10076 rtx pat = *pnewpat;
10077 int insn_code_number;
10078 int num_clobbers_to_add = 0;
10081 rtx old_notes, old_pat;
10083 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10084 we use to indicate that something didn't match. If we find such a
10085 thing, force rejection. */
10086 if (GET_CODE (pat) == PARALLEL)
10087 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10088 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10089 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10092 old_pat = PATTERN (insn);
10093 old_notes = REG_NOTES (insn);
10094 PATTERN (insn) = pat;
10095 REG_NOTES (insn) = 0;
10097 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10098 if (dump_file && (dump_flags & TDF_DETAILS))
10100 if (insn_code_number < 0)
10101 fputs ("Failed to match this instruction:\n", dump_file);
10103 fputs ("Successfully matched this instruction:\n", dump_file);
10104 print_rtl_single (dump_file, pat);
10107 /* If it isn't, there is the possibility that we previously had an insn
10108 that clobbered some register as a side effect, but the combined
10109 insn doesn't need to do that. So try once more without the clobbers
10110 unless this represents an ASM insn. */
10112 if (insn_code_number < 0 && ! check_asm_operands (pat)
10113 && GET_CODE (pat) == PARALLEL)
10117 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10118 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10121 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10125 SUBST_INT (XVECLEN (pat, 0), pos);
10128 pat = XVECEXP (pat, 0, 0);
10130 PATTERN (insn) = pat;
10131 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10132 if (dump_file && (dump_flags & TDF_DETAILS))
10134 if (insn_code_number < 0)
10135 fputs ("Failed to match this instruction:\n", dump_file);
10137 fputs ("Successfully matched this instruction:\n", dump_file);
10138 print_rtl_single (dump_file, pat);
10141 PATTERN (insn) = old_pat;
10142 REG_NOTES (insn) = old_notes;
10144 /* Recognize all noop sets, these will be killed by followup pass. */
10145 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10146 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10148 /* If we had any clobbers to add, make a new pattern than contains
10149 them. Then check to make sure that all of them are dead. */
10150 if (num_clobbers_to_add)
10152 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10153 rtvec_alloc (GET_CODE (pat) == PARALLEL
10154 ? (XVECLEN (pat, 0)
10155 + num_clobbers_to_add)
10156 : num_clobbers_to_add + 1));
10158 if (GET_CODE (pat) == PARALLEL)
10159 for (i = 0; i < XVECLEN (pat, 0); i++)
10160 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10162 XVECEXP (newpat, 0, 0) = pat;
10164 add_clobbers (newpat, insn_code_number);
10166 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10167 i < XVECLEN (newpat, 0); i++)
10169 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10170 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10172 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10174 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10175 notes = alloc_reg_note (REG_UNUSED,
10176 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10185 return insn_code_number;
10188 /* Like gen_lowpart_general but for use by combine. In combine it
10189 is not possible to create any new pseudoregs. However, it is
10190 safe to create invalid memory addresses, because combine will
10191 try to recognize them and all they will do is make the combine
10194 If for some reason this cannot do its job, an rtx
10195 (clobber (const_int 0)) is returned.
10196 An insn containing that will not be recognized. */
10199 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10201 enum machine_mode imode = GET_MODE (x);
10202 unsigned int osize = GET_MODE_SIZE (omode);
10203 unsigned int isize = GET_MODE_SIZE (imode);
10206 if (omode == imode)
10209 /* Return identity if this is a CONST or symbolic reference. */
10211 && (GET_CODE (x) == CONST
10212 || GET_CODE (x) == SYMBOL_REF
10213 || GET_CODE (x) == LABEL_REF))
10216 /* We can only support MODE being wider than a word if X is a
10217 constant integer or has a mode the same size. */
10218 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10219 && ! ((imode == VOIDmode
10220 && (CONST_INT_P (x)
10221 || GET_CODE (x) == CONST_DOUBLE))
10222 || isize == osize))
10225 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10226 won't know what to do. So we will strip off the SUBREG here and
10227 process normally. */
10228 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10230 x = SUBREG_REG (x);
10232 /* For use in case we fall down into the address adjustments
10233 further below, we need to adjust the known mode and size of
10234 x; imode and isize, since we just adjusted x. */
10235 imode = GET_MODE (x);
10237 if (imode == omode)
10240 isize = GET_MODE_SIZE (imode);
10243 result = gen_lowpart_common (omode, x);
10252 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10254 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10257 /* If we want to refer to something bigger than the original memref,
10258 generate a paradoxical subreg instead. That will force a reload
10259 of the original memref X. */
10261 return gen_rtx_SUBREG (omode, x, 0);
10263 if (WORDS_BIG_ENDIAN)
10264 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10266 /* Adjust the address so that the address-after-the-data is
10268 if (BYTES_BIG_ENDIAN)
10269 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10271 return adjust_address_nv (x, omode, offset);
10274 /* If X is a comparison operator, rewrite it in a new mode. This
10275 probably won't match, but may allow further simplifications. */
10276 else if (COMPARISON_P (x))
10277 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10279 /* If we couldn't simplify X any other way, just enclose it in a
10280 SUBREG. Normally, this SUBREG won't match, but some patterns may
10281 include an explicit SUBREG or we may simplify it further in combine. */
10287 offset = subreg_lowpart_offset (omode, imode);
10288 if (imode == VOIDmode)
10290 imode = int_mode_for_mode (omode);
10291 x = gen_lowpart_common (imode, x);
10295 res = simplify_gen_subreg (omode, x, imode, offset);
10301 return gen_rtx_CLOBBER (omode, const0_rtx);
10304 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10305 comparison code that will be tested.
10307 The result is a possibly different comparison code to use. *POP0 and
10308 *POP1 may be updated.
10310 It is possible that we might detect that a comparison is either always
10311 true or always false. However, we do not perform general constant
10312 folding in combine, so this knowledge isn't useful. Such tautologies
10313 should have been detected earlier. Hence we ignore all such cases. */
10315 static enum rtx_code
10316 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10322 enum machine_mode mode, tmode;
10324 /* Try a few ways of applying the same transformation to both operands. */
10327 #ifndef WORD_REGISTER_OPERATIONS
10328 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10329 so check specially. */
10330 if (code != GTU && code != GEU && code != LTU && code != LEU
10331 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10332 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10333 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10334 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10335 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10336 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10337 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10338 && CONST_INT_P (XEXP (op0, 1))
10339 && XEXP (op0, 1) == XEXP (op1, 1)
10340 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10341 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10342 && (INTVAL (XEXP (op0, 1))
10343 == (GET_MODE_BITSIZE (GET_MODE (op0))
10344 - (GET_MODE_BITSIZE
10345 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10347 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10348 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10352 /* If both operands are the same constant shift, see if we can ignore the
10353 shift. We can if the shift is a rotate or if the bits shifted out of
10354 this shift are known to be zero for both inputs and if the type of
10355 comparison is compatible with the shift. */
10356 if (GET_CODE (op0) == GET_CODE (op1)
10357 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10358 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10359 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10360 && (code != GT && code != LT && code != GE && code != LE))
10361 || (GET_CODE (op0) == ASHIFTRT
10362 && (code != GTU && code != LTU
10363 && code != GEU && code != LEU)))
10364 && CONST_INT_P (XEXP (op0, 1))
10365 && INTVAL (XEXP (op0, 1)) >= 0
10366 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10367 && XEXP (op0, 1) == XEXP (op1, 1))
10369 enum machine_mode mode = GET_MODE (op0);
10370 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10371 int shift_count = INTVAL (XEXP (op0, 1));
10373 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10374 mask &= (mask >> shift_count) << shift_count;
10375 else if (GET_CODE (op0) == ASHIFT)
10376 mask = (mask & (mask << shift_count)) >> shift_count;
10378 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10379 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10380 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10385 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10386 SUBREGs are of the same mode, and, in both cases, the AND would
10387 be redundant if the comparison was done in the narrower mode,
10388 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10389 and the operand's possibly nonzero bits are 0xffffff01; in that case
10390 if we only care about QImode, we don't need the AND). This case
10391 occurs if the output mode of an scc insn is not SImode and
10392 STORE_FLAG_VALUE == 1 (e.g., the 386).
10394 Similarly, check for a case where the AND's are ZERO_EXTEND
10395 operations from some narrower mode even though a SUBREG is not
10398 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10399 && CONST_INT_P (XEXP (op0, 1))
10400 && CONST_INT_P (XEXP (op1, 1)))
10402 rtx inner_op0 = XEXP (op0, 0);
10403 rtx inner_op1 = XEXP (op1, 0);
10404 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10405 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10408 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10409 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10410 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10411 && (GET_MODE (SUBREG_REG (inner_op0))
10412 == GET_MODE (SUBREG_REG (inner_op1)))
10413 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10414 <= HOST_BITS_PER_WIDE_INT)
10415 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10416 GET_MODE (SUBREG_REG (inner_op0)))))
10417 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10418 GET_MODE (SUBREG_REG (inner_op1))))))
10420 op0 = SUBREG_REG (inner_op0);
10421 op1 = SUBREG_REG (inner_op1);
10423 /* The resulting comparison is always unsigned since we masked
10424 off the original sign bit. */
10425 code = unsigned_condition (code);
10431 for (tmode = GET_CLASS_NARROWEST_MODE
10432 (GET_MODE_CLASS (GET_MODE (op0)));
10433 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10434 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10436 op0 = gen_lowpart (tmode, inner_op0);
10437 op1 = gen_lowpart (tmode, inner_op1);
10438 code = unsigned_condition (code);
10447 /* If both operands are NOT, we can strip off the outer operation
10448 and adjust the comparison code for swapped operands; similarly for
10449 NEG, except that this must be an equality comparison. */
10450 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10451 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10452 && (code == EQ || code == NE)))
10453 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10459 /* If the first operand is a constant, swap the operands and adjust the
10460 comparison code appropriately, but don't do this if the second operand
10461 is already a constant integer. */
10462 if (swap_commutative_operands_p (op0, op1))
10464 tem = op0, op0 = op1, op1 = tem;
10465 code = swap_condition (code);
10468 /* We now enter a loop during which we will try to simplify the comparison.
10469 For the most part, we only are concerned with comparisons with zero,
10470 but some things may really be comparisons with zero but not start
10471 out looking that way. */
10473 while (CONST_INT_P (op1))
10475 enum machine_mode mode = GET_MODE (op0);
10476 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10477 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10478 int equality_comparison_p;
10479 int sign_bit_comparison_p;
10480 int unsigned_comparison_p;
10481 HOST_WIDE_INT const_op;
10483 /* We only want to handle integral modes. This catches VOIDmode,
10484 CCmode, and the floating-point modes. An exception is that we
10485 can handle VOIDmode if OP0 is a COMPARE or a comparison
10488 if (GET_MODE_CLASS (mode) != MODE_INT
10489 && ! (mode == VOIDmode
10490 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10493 /* Get the constant we are comparing against and turn off all bits
10494 not on in our mode. */
10495 const_op = INTVAL (op1);
10496 if (mode != VOIDmode)
10497 const_op = trunc_int_for_mode (const_op, mode);
10498 op1 = GEN_INT (const_op);
10500 /* If we are comparing against a constant power of two and the value
10501 being compared can only have that single bit nonzero (e.g., it was
10502 `and'ed with that bit), we can replace this with a comparison
10505 && (code == EQ || code == NE || code == GE || code == GEU
10506 || code == LT || code == LTU)
10507 && mode_width <= HOST_BITS_PER_WIDE_INT
10508 && exact_log2 (const_op) >= 0
10509 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10511 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10512 op1 = const0_rtx, const_op = 0;
10515 /* Similarly, if we are comparing a value known to be either -1 or
10516 0 with -1, change it to the opposite comparison against zero. */
10519 && (code == EQ || code == NE || code == GT || code == LE
10520 || code == GEU || code == LTU)
10521 && num_sign_bit_copies (op0, mode) == mode_width)
10523 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10524 op1 = const0_rtx, const_op = 0;
10527 /* Do some canonicalizations based on the comparison code. We prefer
10528 comparisons against zero and then prefer equality comparisons.
10529 If we can reduce the size of a constant, we will do that too. */
10534 /* < C is equivalent to <= (C - 1) */
10538 op1 = GEN_INT (const_op);
10540 /* ... fall through to LE case below. */
10546 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10550 op1 = GEN_INT (const_op);
10554 /* If we are doing a <= 0 comparison on a value known to have
10555 a zero sign bit, we can replace this with == 0. */
10556 else if (const_op == 0
10557 && mode_width <= HOST_BITS_PER_WIDE_INT
10558 && (nonzero_bits (op0, mode)
10559 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10564 /* >= C is equivalent to > (C - 1). */
10568 op1 = GEN_INT (const_op);
10570 /* ... fall through to GT below. */
10576 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10580 op1 = GEN_INT (const_op);
10584 /* If we are doing a > 0 comparison on a value known to have
10585 a zero sign bit, we can replace this with != 0. */
10586 else if (const_op == 0
10587 && mode_width <= HOST_BITS_PER_WIDE_INT
10588 && (nonzero_bits (op0, mode)
10589 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10594 /* < C is equivalent to <= (C - 1). */
10598 op1 = GEN_INT (const_op);
10600 /* ... fall through ... */
10603 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10604 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10605 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10607 const_op = 0, op1 = const0_rtx;
10615 /* unsigned <= 0 is equivalent to == 0 */
10619 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10620 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10621 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10623 const_op = 0, op1 = const0_rtx;
10629 /* >= C is equivalent to > (C - 1). */
10633 op1 = GEN_INT (const_op);
10635 /* ... fall through ... */
10638 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10639 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10640 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10642 const_op = 0, op1 = const0_rtx;
10650 /* unsigned > 0 is equivalent to != 0 */
10654 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10655 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10656 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10658 const_op = 0, op1 = const0_rtx;
10667 /* Compute some predicates to simplify code below. */
10669 equality_comparison_p = (code == EQ || code == NE);
10670 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10671 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10674 /* If this is a sign bit comparison and we can do arithmetic in
10675 MODE, say that we will only be needing the sign bit of OP0. */
10676 if (sign_bit_comparison_p
10677 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10678 op0 = force_to_mode (op0, mode,
10680 << (GET_MODE_BITSIZE (mode) - 1)),
10683 /* Now try cases based on the opcode of OP0. If none of the cases
10684 does a "continue", we exit this loop immediately after the
10687 switch (GET_CODE (op0))
10690 /* If we are extracting a single bit from a variable position in
10691 a constant that has only a single bit set and are comparing it
10692 with zero, we can convert this into an equality comparison
10693 between the position and the location of the single bit. */
10694 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10695 have already reduced the shift count modulo the word size. */
10696 if (!SHIFT_COUNT_TRUNCATED
10697 && CONST_INT_P (XEXP (op0, 0))
10698 && XEXP (op0, 1) == const1_rtx
10699 && equality_comparison_p && const_op == 0
10700 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10702 if (BITS_BIG_ENDIAN)
10704 enum machine_mode new_mode
10705 = mode_for_extraction (EP_extzv, 1);
10706 if (new_mode == MAX_MACHINE_MODE)
10707 i = BITS_PER_WORD - 1 - i;
10711 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10715 op0 = XEXP (op0, 2);
10719 /* Result is nonzero iff shift count is equal to I. */
10720 code = reverse_condition (code);
10724 /* ... fall through ... */
10727 tem = expand_compound_operation (op0);
10736 /* If testing for equality, we can take the NOT of the constant. */
10737 if (equality_comparison_p
10738 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10740 op0 = XEXP (op0, 0);
10745 /* If just looking at the sign bit, reverse the sense of the
10747 if (sign_bit_comparison_p)
10749 op0 = XEXP (op0, 0);
10750 code = (code == GE ? LT : GE);
10756 /* If testing for equality, we can take the NEG of the constant. */
10757 if (equality_comparison_p
10758 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10760 op0 = XEXP (op0, 0);
10765 /* The remaining cases only apply to comparisons with zero. */
10769 /* When X is ABS or is known positive,
10770 (neg X) is < 0 if and only if X != 0. */
10772 if (sign_bit_comparison_p
10773 && (GET_CODE (XEXP (op0, 0)) == ABS
10774 || (mode_width <= HOST_BITS_PER_WIDE_INT
10775 && (nonzero_bits (XEXP (op0, 0), mode)
10776 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10778 op0 = XEXP (op0, 0);
10779 code = (code == LT ? NE : EQ);
10783 /* If we have NEG of something whose two high-order bits are the
10784 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10785 if (num_sign_bit_copies (op0, mode) >= 2)
10787 op0 = XEXP (op0, 0);
10788 code = swap_condition (code);
10794 /* If we are testing equality and our count is a constant, we
10795 can perform the inverse operation on our RHS. */
10796 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10797 && (tem = simplify_binary_operation (ROTATERT, mode,
10798 op1, XEXP (op0, 1))) != 0)
10800 op0 = XEXP (op0, 0);
10805 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10806 a particular bit. Convert it to an AND of a constant of that
10807 bit. This will be converted into a ZERO_EXTRACT. */
10808 if (const_op == 0 && sign_bit_comparison_p
10809 && CONST_INT_P (XEXP (op0, 1))
10810 && mode_width <= HOST_BITS_PER_WIDE_INT)
10812 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10815 - INTVAL (XEXP (op0, 1)))));
10816 code = (code == LT ? NE : EQ);
10820 /* Fall through. */
10823 /* ABS is ignorable inside an equality comparison with zero. */
10824 if (const_op == 0 && equality_comparison_p)
10826 op0 = XEXP (op0, 0);
10832 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10833 (compare FOO CONST) if CONST fits in FOO's mode and we
10834 are either testing inequality or have an unsigned
10835 comparison with ZERO_EXTEND or a signed comparison with
10836 SIGN_EXTEND. But don't do it if we don't have a compare
10837 insn of the given mode, since we'd have to revert it
10838 later on, and then we wouldn't know whether to sign- or
10840 mode = GET_MODE (XEXP (op0, 0));
10841 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10842 && ! unsigned_comparison_p
10843 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10844 && ((unsigned HOST_WIDE_INT) const_op
10845 < (((unsigned HOST_WIDE_INT) 1
10846 << (GET_MODE_BITSIZE (mode) - 1))))
10847 && have_insn_for (COMPARE, mode))
10849 op0 = XEXP (op0, 0);
10855 /* Check for the case where we are comparing A - C1 with C2, that is
10857 (subreg:MODE (plus (A) (-C1))) op (C2)
10859 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10860 comparison in the wider mode. One of the following two conditions
10861 must be true in order for this to be valid:
10863 1. The mode extension results in the same bit pattern being added
10864 on both sides and the comparison is equality or unsigned. As
10865 C2 has been truncated to fit in MODE, the pattern can only be
10868 2. The mode extension results in the sign bit being copied on
10871 The difficulty here is that we have predicates for A but not for
10872 (A - C1) so we need to check that C1 is within proper bounds so
10873 as to perturbate A as little as possible. */
10875 if (mode_width <= HOST_BITS_PER_WIDE_INT
10876 && subreg_lowpart_p (op0)
10877 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10878 && GET_CODE (SUBREG_REG (op0)) == PLUS
10879 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10881 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10882 rtx a = XEXP (SUBREG_REG (op0), 0);
10883 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10886 && (unsigned HOST_WIDE_INT) c1
10887 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10888 && (equality_comparison_p || unsigned_comparison_p)
10889 /* (A - C1) zero-extends if it is positive and sign-extends
10890 if it is negative, C2 both zero- and sign-extends. */
10891 && ((0 == (nonzero_bits (a, inner_mode)
10892 & ~GET_MODE_MASK (mode))
10894 /* (A - C1) sign-extends if it is positive and 1-extends
10895 if it is negative, C2 both sign- and 1-extends. */
10896 || (num_sign_bit_copies (a, inner_mode)
10897 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10900 || ((unsigned HOST_WIDE_INT) c1
10901 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10902 /* (A - C1) always sign-extends, like C2. */
10903 && num_sign_bit_copies (a, inner_mode)
10904 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10905 - (mode_width - 1))))
10907 op0 = SUBREG_REG (op0);
10912 /* If the inner mode is narrower and we are extracting the low part,
10913 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10914 if (subreg_lowpart_p (op0)
10915 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10916 /* Fall through */ ;
10920 /* ... fall through ... */
10923 mode = GET_MODE (XEXP (op0, 0));
10924 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10925 && (unsigned_comparison_p || equality_comparison_p)
10926 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10927 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10928 && have_insn_for (COMPARE, mode))
10930 op0 = XEXP (op0, 0);
10936 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10937 this for equality comparisons due to pathological cases involving
10939 if (equality_comparison_p
10940 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10941 op1, XEXP (op0, 1))))
10943 op0 = XEXP (op0, 0);
10948 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10949 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10950 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10952 op0 = XEXP (XEXP (op0, 0), 0);
10953 code = (code == LT ? EQ : NE);
10959 /* We used to optimize signed comparisons against zero, but that
10960 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10961 arrive here as equality comparisons, or (GEU, LTU) are
10962 optimized away. No need to special-case them. */
10964 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10965 (eq B (minus A C)), whichever simplifies. We can only do
10966 this for equality comparisons due to pathological cases involving
10968 if (equality_comparison_p
10969 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10970 XEXP (op0, 1), op1)))
10972 op0 = XEXP (op0, 0);
10977 if (equality_comparison_p
10978 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10979 XEXP (op0, 0), op1)))
10981 op0 = XEXP (op0, 1);
10986 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10987 of bits in X minus 1, is one iff X > 0. */
10988 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10989 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10990 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10992 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10994 op0 = XEXP (op0, 1);
10995 code = (code == GE ? LE : GT);
11001 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11002 if C is zero or B is a constant. */
11003 if (equality_comparison_p
11004 && 0 != (tem = simplify_binary_operation (XOR, mode,
11005 XEXP (op0, 1), op1)))
11007 op0 = XEXP (op0, 0);
11014 case UNEQ: case LTGT:
11015 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11016 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11017 case UNORDERED: case ORDERED:
11018 /* We can't do anything if OP0 is a condition code value, rather
11019 than an actual data value. */
11021 || CC0_P (XEXP (op0, 0))
11022 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11025 /* Get the two operands being compared. */
11026 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11027 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11029 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11031 /* Check for the cases where we simply want the result of the
11032 earlier test or the opposite of that result. */
11033 if (code == NE || code == EQ
11034 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11035 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11036 && (STORE_FLAG_VALUE
11037 & (((HOST_WIDE_INT) 1
11038 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11039 && (code == LT || code == GE)))
11041 enum rtx_code new_code;
11042 if (code == LT || code == NE)
11043 new_code = GET_CODE (op0);
11045 new_code = reversed_comparison_code (op0, NULL);
11047 if (new_code != UNKNOWN)
11058 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11060 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11061 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11062 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11064 op0 = XEXP (op0, 1);
11065 code = (code == GE ? GT : LE);
11071 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11072 will be converted to a ZERO_EXTRACT later. */
11073 if (const_op == 0 && equality_comparison_p
11074 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11075 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11077 op0 = simplify_and_const_int
11078 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11080 XEXP (XEXP (op0, 0), 1)),
11081 (HOST_WIDE_INT) 1);
11085 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11086 zero and X is a comparison and C1 and C2 describe only bits set
11087 in STORE_FLAG_VALUE, we can compare with X. */
11088 if (const_op == 0 && equality_comparison_p
11089 && mode_width <= HOST_BITS_PER_WIDE_INT
11090 && CONST_INT_P (XEXP (op0, 1))
11091 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11092 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11093 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11094 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11096 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11097 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11098 if ((~STORE_FLAG_VALUE & mask) == 0
11099 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11100 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11101 && COMPARISON_P (tem))))
11103 op0 = XEXP (XEXP (op0, 0), 0);
11108 /* If we are doing an equality comparison of an AND of a bit equal
11109 to the sign bit, replace this with a LT or GE comparison of
11110 the underlying value. */
11111 if (equality_comparison_p
11113 && CONST_INT_P (XEXP (op0, 1))
11114 && mode_width <= HOST_BITS_PER_WIDE_INT
11115 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11116 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11118 op0 = XEXP (op0, 0);
11119 code = (code == EQ ? GE : LT);
11123 /* If this AND operation is really a ZERO_EXTEND from a narrower
11124 mode, the constant fits within that mode, and this is either an
11125 equality or unsigned comparison, try to do this comparison in
11130 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11131 -> (ne:DI (reg:SI 4) (const_int 0))
11133 unless TRULY_NOOP_TRUNCATION allows it or the register is
11134 known to hold a value of the required mode the
11135 transformation is invalid. */
11136 if ((equality_comparison_p || unsigned_comparison_p)
11137 && CONST_INT_P (XEXP (op0, 1))
11138 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11139 & GET_MODE_MASK (mode))
11141 && const_op >> i == 0
11142 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11143 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11144 GET_MODE_BITSIZE (GET_MODE (op0)))
11145 || (REG_P (XEXP (op0, 0))
11146 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11148 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11152 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11153 fits in both M1 and M2 and the SUBREG is either paradoxical
11154 or represents the low part, permute the SUBREG and the AND
11156 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11158 unsigned HOST_WIDE_INT c1;
11159 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11160 /* Require an integral mode, to avoid creating something like
11162 if (SCALAR_INT_MODE_P (tmode)
11163 /* It is unsafe to commute the AND into the SUBREG if the
11164 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11165 not defined. As originally written the upper bits
11166 have a defined value due to the AND operation.
11167 However, if we commute the AND inside the SUBREG then
11168 they no longer have defined values and the meaning of
11169 the code has been changed. */
11171 #ifdef WORD_REGISTER_OPERATIONS
11172 || (mode_width > GET_MODE_BITSIZE (tmode)
11173 && mode_width <= BITS_PER_WORD)
11175 || (mode_width <= GET_MODE_BITSIZE (tmode)
11176 && subreg_lowpart_p (XEXP (op0, 0))))
11177 && CONST_INT_P (XEXP (op0, 1))
11178 && mode_width <= HOST_BITS_PER_WIDE_INT
11179 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11180 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11181 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11183 && c1 != GET_MODE_MASK (tmode))
11185 op0 = simplify_gen_binary (AND, tmode,
11186 SUBREG_REG (XEXP (op0, 0)),
11187 gen_int_mode (c1, tmode));
11188 op0 = gen_lowpart (mode, op0);
11193 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11194 if (const_op == 0 && equality_comparison_p
11195 && XEXP (op0, 1) == const1_rtx
11196 && GET_CODE (XEXP (op0, 0)) == NOT)
11198 op0 = simplify_and_const_int
11199 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11200 code = (code == NE ? EQ : NE);
11204 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11205 (eq (and (lshiftrt X) 1) 0).
11206 Also handle the case where (not X) is expressed using xor. */
11207 if (const_op == 0 && equality_comparison_p
11208 && XEXP (op0, 1) == const1_rtx
11209 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11211 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11212 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11214 if (GET_CODE (shift_op) == NOT
11215 || (GET_CODE (shift_op) == XOR
11216 && CONST_INT_P (XEXP (shift_op, 1))
11217 && CONST_INT_P (shift_count)
11218 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11219 && (INTVAL (XEXP (shift_op, 1))
11220 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11222 op0 = simplify_and_const_int
11224 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11225 (HOST_WIDE_INT) 1);
11226 code = (code == NE ? EQ : NE);
11233 /* If we have (compare (ashift FOO N) (const_int C)) and
11234 the high order N bits of FOO (N+1 if an inequality comparison)
11235 are known to be zero, we can do this by comparing FOO with C
11236 shifted right N bits so long as the low-order N bits of C are
11238 if (CONST_INT_P (XEXP (op0, 1))
11239 && INTVAL (XEXP (op0, 1)) >= 0
11240 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11241 < HOST_BITS_PER_WIDE_INT)
11243 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11244 && mode_width <= HOST_BITS_PER_WIDE_INT
11245 && (nonzero_bits (XEXP (op0, 0), mode)
11246 & ~(mask >> (INTVAL (XEXP (op0, 1))
11247 + ! equality_comparison_p))) == 0)
11249 /* We must perform a logical shift, not an arithmetic one,
11250 as we want the top N bits of C to be zero. */
11251 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11253 temp >>= INTVAL (XEXP (op0, 1));
11254 op1 = gen_int_mode (temp, mode);
11255 op0 = XEXP (op0, 0);
11259 /* If we are doing a sign bit comparison, it means we are testing
11260 a particular bit. Convert it to the appropriate AND. */
11261 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11262 && mode_width <= HOST_BITS_PER_WIDE_INT)
11264 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11267 - INTVAL (XEXP (op0, 1)))));
11268 code = (code == LT ? NE : EQ);
11272 /* If this an equality comparison with zero and we are shifting
11273 the low bit to the sign bit, we can convert this to an AND of the
11275 if (const_op == 0 && equality_comparison_p
11276 && CONST_INT_P (XEXP (op0, 1))
11277 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11280 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11281 (HOST_WIDE_INT) 1);
11287 /* If this is an equality comparison with zero, we can do this
11288 as a logical shift, which might be much simpler. */
11289 if (equality_comparison_p && const_op == 0
11290 && CONST_INT_P (XEXP (op0, 1)))
11292 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11294 INTVAL (XEXP (op0, 1)));
11298 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11299 do the comparison in a narrower mode. */
11300 if (! unsigned_comparison_p
11301 && CONST_INT_P (XEXP (op0, 1))
11302 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11303 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11304 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11305 MODE_INT, 1)) != BLKmode
11306 && (((unsigned HOST_WIDE_INT) const_op
11307 + (GET_MODE_MASK (tmode) >> 1) + 1)
11308 <= GET_MODE_MASK (tmode)))
11310 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11314 /* Likewise if OP0 is a PLUS of a sign extension with a
11315 constant, which is usually represented with the PLUS
11316 between the shifts. */
11317 if (! unsigned_comparison_p
11318 && CONST_INT_P (XEXP (op0, 1))
11319 && GET_CODE (XEXP (op0, 0)) == PLUS
11320 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11321 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11322 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11323 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11324 MODE_INT, 1)) != BLKmode
11325 && (((unsigned HOST_WIDE_INT) const_op
11326 + (GET_MODE_MASK (tmode) >> 1) + 1)
11327 <= GET_MODE_MASK (tmode)))
11329 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11330 rtx add_const = XEXP (XEXP (op0, 0), 1);
11331 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11332 add_const, XEXP (op0, 1));
11334 op0 = simplify_gen_binary (PLUS, tmode,
11335 gen_lowpart (tmode, inner),
11340 /* ... fall through ... */
11342 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11343 the low order N bits of FOO are known to be zero, we can do this
11344 by comparing FOO with C shifted left N bits so long as no
11345 overflow occurs. */
11346 if (CONST_INT_P (XEXP (op0, 1))
11347 && INTVAL (XEXP (op0, 1)) >= 0
11348 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11349 && mode_width <= HOST_BITS_PER_WIDE_INT
11350 && (nonzero_bits (XEXP (op0, 0), mode)
11351 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11352 && (((unsigned HOST_WIDE_INT) const_op
11353 + (GET_CODE (op0) != LSHIFTRT
11354 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11357 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11359 /* If the shift was logical, then we must make the condition
11361 if (GET_CODE (op0) == LSHIFTRT)
11362 code = unsigned_condition (code);
11364 const_op <<= INTVAL (XEXP (op0, 1));
11365 op1 = GEN_INT (const_op);
11366 op0 = XEXP (op0, 0);
11370 /* If we are using this shift to extract just the sign bit, we
11371 can replace this with an LT or GE comparison. */
11373 && (equality_comparison_p || sign_bit_comparison_p)
11374 && CONST_INT_P (XEXP (op0, 1))
11375 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11378 op0 = XEXP (op0, 0);
11379 code = (code == NE || code == GT ? LT : GE);
11391 /* Now make any compound operations involved in this comparison. Then,
11392 check for an outmost SUBREG on OP0 that is not doing anything or is
11393 paradoxical. The latter transformation must only be performed when
11394 it is known that the "extra" bits will be the same in op0 and op1 or
11395 that they don't matter. There are three cases to consider:
11397 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11398 care bits and we can assume they have any convenient value. So
11399 making the transformation is safe.
11401 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11402 In this case the upper bits of op0 are undefined. We should not make
11403 the simplification in that case as we do not know the contents of
11406 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11407 UNKNOWN. In that case we know those bits are zeros or ones. We must
11408 also be sure that they are the same as the upper bits of op1.
11410 We can never remove a SUBREG for a non-equality comparison because
11411 the sign bit is in a different place in the underlying object. */
11413 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11414 op1 = make_compound_operation (op1, SET);
11416 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11417 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11418 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11419 && (code == NE || code == EQ))
11421 if (GET_MODE_SIZE (GET_MODE (op0))
11422 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11424 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11426 if (REG_P (SUBREG_REG (op0)))
11428 op0 = SUBREG_REG (op0);
11429 op1 = gen_lowpart (GET_MODE (op0), op1);
11432 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11433 <= HOST_BITS_PER_WIDE_INT)
11434 && (nonzero_bits (SUBREG_REG (op0),
11435 GET_MODE (SUBREG_REG (op0)))
11436 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11438 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11440 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11441 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11442 op0 = SUBREG_REG (op0), op1 = tem;
11446 /* We now do the opposite procedure: Some machines don't have compare
11447 insns in all modes. If OP0's mode is an integer mode smaller than a
11448 word and we can't do a compare in that mode, see if there is a larger
11449 mode for which we can do the compare. There are a number of cases in
11450 which we can use the wider mode. */
11452 mode = GET_MODE (op0);
11453 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11454 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11455 && ! have_insn_for (COMPARE, mode))
11456 for (tmode = GET_MODE_WIDER_MODE (mode);
11458 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11459 tmode = GET_MODE_WIDER_MODE (tmode))
11460 if (have_insn_for (COMPARE, tmode))
11464 /* If this is a test for negative, we can make an explicit
11465 test of the sign bit. Test this first so we can use
11466 a paradoxical subreg to extend OP0. */
11468 if (op1 == const0_rtx && (code == LT || code == GE)
11469 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11471 op0 = simplify_gen_binary (AND, tmode,
11472 gen_lowpart (tmode, op0),
11473 GEN_INT ((HOST_WIDE_INT) 1
11474 << (GET_MODE_BITSIZE (mode)
11476 code = (code == LT) ? NE : EQ;
11480 /* If the only nonzero bits in OP0 and OP1 are those in the
11481 narrower mode and this is an equality or unsigned comparison,
11482 we can use the wider mode. Similarly for sign-extended
11483 values, in which case it is true for all comparisons. */
11484 zero_extended = ((code == EQ || code == NE
11485 || code == GEU || code == GTU
11486 || code == LEU || code == LTU)
11487 && (nonzero_bits (op0, tmode)
11488 & ~GET_MODE_MASK (mode)) == 0
11489 && ((CONST_INT_P (op1)
11490 || (nonzero_bits (op1, tmode)
11491 & ~GET_MODE_MASK (mode)) == 0)));
11494 || ((num_sign_bit_copies (op0, tmode)
11495 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11496 - GET_MODE_BITSIZE (mode)))
11497 && (num_sign_bit_copies (op1, tmode)
11498 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11499 - GET_MODE_BITSIZE (mode)))))
11501 /* If OP0 is an AND and we don't have an AND in MODE either,
11502 make a new AND in the proper mode. */
11503 if (GET_CODE (op0) == AND
11504 && !have_insn_for (AND, mode))
11505 op0 = simplify_gen_binary (AND, tmode,
11506 gen_lowpart (tmode,
11508 gen_lowpart (tmode,
11514 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11515 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11519 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11520 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11527 #ifdef CANONICALIZE_COMPARISON
11528 /* If this machine only supports a subset of valid comparisons, see if we
11529 can convert an unsupported one into a supported one. */
11530 CANONICALIZE_COMPARISON (code, op0, op1);
11539 /* Utility function for record_value_for_reg. Count number of
11544 enum rtx_code code = GET_CODE (x);
11548 if (GET_RTX_CLASS (code) == '2'
11549 || GET_RTX_CLASS (code) == 'c')
11551 rtx x0 = XEXP (x, 0);
11552 rtx x1 = XEXP (x, 1);
11555 return 1 + 2 * count_rtxs (x0);
11557 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11558 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11559 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11560 return 2 + 2 * count_rtxs (x0)
11561 + count_rtxs (x == XEXP (x1, 0)
11562 ? XEXP (x1, 1) : XEXP (x1, 0));
11564 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11565 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11566 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11567 return 2 + 2 * count_rtxs (x1)
11568 + count_rtxs (x == XEXP (x0, 0)
11569 ? XEXP (x0, 1) : XEXP (x0, 0));
11572 fmt = GET_RTX_FORMAT (code);
11573 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11575 ret += count_rtxs (XEXP (x, i));
11576 else if (fmt[i] == 'E')
11577 for (j = 0; j < XVECLEN (x, i); j++)
11578 ret += count_rtxs (XVECEXP (x, i, j));
11583 /* Utility function for following routine. Called when X is part of a value
11584 being stored into last_set_value. Sets last_set_table_tick
11585 for each register mentioned. Similar to mention_regs in cse.c */
11588 update_table_tick (rtx x)
11590 enum rtx_code code = GET_CODE (x);
11591 const char *fmt = GET_RTX_FORMAT (code);
11596 unsigned int regno = REGNO (x);
11597 unsigned int endregno = END_REGNO (x);
11600 for (r = regno; r < endregno; r++)
11602 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11603 rsp->last_set_table_tick = label_tick;
11609 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11612 /* Check for identical subexpressions. If x contains
11613 identical subexpression we only have to traverse one of
11615 if (i == 0 && ARITHMETIC_P (x))
11617 /* Note that at this point x1 has already been
11619 rtx x0 = XEXP (x, 0);
11620 rtx x1 = XEXP (x, 1);
11622 /* If x0 and x1 are identical then there is no need to
11627 /* If x0 is identical to a subexpression of x1 then while
11628 processing x1, x0 has already been processed. Thus we
11629 are done with x. */
11630 if (ARITHMETIC_P (x1)
11631 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11634 /* If x1 is identical to a subexpression of x0 then we
11635 still have to process the rest of x0. */
11636 if (ARITHMETIC_P (x0)
11637 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11639 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11644 update_table_tick (XEXP (x, i));
11646 else if (fmt[i] == 'E')
11647 for (j = 0; j < XVECLEN (x, i); j++)
11648 update_table_tick (XVECEXP (x, i, j));
11651 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11652 are saying that the register is clobbered and we no longer know its
11653 value. If INSN is zero, don't update reg_stat[].last_set; this is
11654 only permitted with VALUE also zero and is used to invalidate the
11658 record_value_for_reg (rtx reg, rtx insn, rtx value)
11660 unsigned int regno = REGNO (reg);
11661 unsigned int endregno = END_REGNO (reg);
11663 reg_stat_type *rsp;
11665 /* If VALUE contains REG and we have a previous value for REG, substitute
11666 the previous value. */
11667 if (value && insn && reg_overlap_mentioned_p (reg, value))
11671 /* Set things up so get_last_value is allowed to see anything set up to
11673 subst_low_luid = DF_INSN_LUID (insn);
11674 tem = get_last_value (reg);
11676 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11677 it isn't going to be useful and will take a lot of time to process,
11678 so just use the CLOBBER. */
11682 if (ARITHMETIC_P (tem)
11683 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11684 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11685 tem = XEXP (tem, 0);
11686 else if (count_occurrences (value, reg, 1) >= 2)
11688 /* If there are two or more occurrences of REG in VALUE,
11689 prevent the value from growing too much. */
11690 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11691 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11694 value = replace_rtx (copy_rtx (value), reg, tem);
11698 /* For each register modified, show we don't know its value, that
11699 we don't know about its bitwise content, that its value has been
11700 updated, and that we don't know the location of the death of the
11702 for (i = regno; i < endregno; i++)
11704 rsp = VEC_index (reg_stat_type, reg_stat, i);
11707 rsp->last_set = insn;
11709 rsp->last_set_value = 0;
11710 rsp->last_set_mode = VOIDmode;
11711 rsp->last_set_nonzero_bits = 0;
11712 rsp->last_set_sign_bit_copies = 0;
11713 rsp->last_death = 0;
11714 rsp->truncated_to_mode = VOIDmode;
11717 /* Mark registers that are being referenced in this value. */
11719 update_table_tick (value);
11721 /* Now update the status of each register being set.
11722 If someone is using this register in this block, set this register
11723 to invalid since we will get confused between the two lives in this
11724 basic block. This makes using this register always invalid. In cse, we
11725 scan the table to invalidate all entries using this register, but this
11726 is too much work for us. */
11728 for (i = regno; i < endregno; i++)
11730 rsp = VEC_index (reg_stat_type, reg_stat, i);
11731 rsp->last_set_label = label_tick;
11733 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11734 rsp->last_set_invalid = 1;
11736 rsp->last_set_invalid = 0;
11739 /* The value being assigned might refer to X (like in "x++;"). In that
11740 case, we must replace it with (clobber (const_int 0)) to prevent
11742 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11743 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11745 value = copy_rtx (value);
11746 if (!get_last_value_validate (&value, insn, label_tick, 1))
11750 /* For the main register being modified, update the value, the mode, the
11751 nonzero bits, and the number of sign bit copies. */
11753 rsp->last_set_value = value;
11757 enum machine_mode mode = GET_MODE (reg);
11758 subst_low_luid = DF_INSN_LUID (insn);
11759 rsp->last_set_mode = mode;
11760 if (GET_MODE_CLASS (mode) == MODE_INT
11761 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11762 mode = nonzero_bits_mode;
11763 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11764 rsp->last_set_sign_bit_copies
11765 = num_sign_bit_copies (value, GET_MODE (reg));
11769 /* Called via note_stores from record_dead_and_set_regs to handle one
11770 SET or CLOBBER in an insn. DATA is the instruction in which the
11771 set is occurring. */
11774 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11776 rtx record_dead_insn = (rtx) data;
11778 if (GET_CODE (dest) == SUBREG)
11779 dest = SUBREG_REG (dest);
11781 if (!record_dead_insn)
11784 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11790 /* If we are setting the whole register, we know its value. Otherwise
11791 show that we don't know the value. We can handle SUBREG in
11793 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11794 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11795 else if (GET_CODE (setter) == SET
11796 && GET_CODE (SET_DEST (setter)) == SUBREG
11797 && SUBREG_REG (SET_DEST (setter)) == dest
11798 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11799 && subreg_lowpart_p (SET_DEST (setter)))
11800 record_value_for_reg (dest, record_dead_insn,
11801 gen_lowpart (GET_MODE (dest),
11802 SET_SRC (setter)));
11804 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11806 else if (MEM_P (dest)
11807 /* Ignore pushes, they clobber nothing. */
11808 && ! push_operand (dest, GET_MODE (dest)))
11809 mem_last_set = DF_INSN_LUID (record_dead_insn);
11812 /* Update the records of when each REG was most recently set or killed
11813 for the things done by INSN. This is the last thing done in processing
11814 INSN in the combiner loop.
11816 We update reg_stat[], in particular fields last_set, last_set_value,
11817 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11818 last_death, and also the similar information mem_last_set (which insn
11819 most recently modified memory) and last_call_luid (which insn was the
11820 most recent subroutine call). */
11823 record_dead_and_set_regs (rtx insn)
11828 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11830 if (REG_NOTE_KIND (link) == REG_DEAD
11831 && REG_P (XEXP (link, 0)))
11833 unsigned int regno = REGNO (XEXP (link, 0));
11834 unsigned int endregno = END_REGNO (XEXP (link, 0));
11836 for (i = regno; i < endregno; i++)
11838 reg_stat_type *rsp;
11840 rsp = VEC_index (reg_stat_type, reg_stat, i);
11841 rsp->last_death = insn;
11844 else if (REG_NOTE_KIND (link) == REG_INC)
11845 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11850 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11851 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11853 reg_stat_type *rsp;
11855 rsp = VEC_index (reg_stat_type, reg_stat, i);
11856 rsp->last_set_invalid = 1;
11857 rsp->last_set = insn;
11858 rsp->last_set_value = 0;
11859 rsp->last_set_mode = VOIDmode;
11860 rsp->last_set_nonzero_bits = 0;
11861 rsp->last_set_sign_bit_copies = 0;
11862 rsp->last_death = 0;
11863 rsp->truncated_to_mode = VOIDmode;
11866 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11868 /* We can't combine into a call pattern. Remember, though, that
11869 the return value register is set at this LUID. We could
11870 still replace a register with the return value from the
11871 wrong subroutine call! */
11872 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11875 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11878 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11879 register present in the SUBREG, so for each such SUBREG go back and
11880 adjust nonzero and sign bit information of the registers that are
11881 known to have some zero/sign bits set.
11883 This is needed because when combine blows the SUBREGs away, the
11884 information on zero/sign bits is lost and further combines can be
11885 missed because of that. */
11888 record_promoted_value (rtx insn, rtx subreg)
11891 unsigned int regno = REGNO (SUBREG_REG (subreg));
11892 enum machine_mode mode = GET_MODE (subreg);
11894 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11897 for (links = LOG_LINKS (insn); links;)
11899 reg_stat_type *rsp;
11901 insn = XEXP (links, 0);
11902 set = single_set (insn);
11904 if (! set || !REG_P (SET_DEST (set))
11905 || REGNO (SET_DEST (set)) != regno
11906 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11908 links = XEXP (links, 1);
11912 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11913 if (rsp->last_set == insn)
11915 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11916 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11919 if (REG_P (SET_SRC (set)))
11921 regno = REGNO (SET_SRC (set));
11922 links = LOG_LINKS (insn);
11929 /* Check if X, a register, is known to contain a value already
11930 truncated to MODE. In this case we can use a subreg to refer to
11931 the truncated value even though in the generic case we would need
11932 an explicit truncation. */
11935 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11937 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11938 enum machine_mode truncated = rsp->truncated_to_mode;
11941 || rsp->truncation_label < label_tick_ebb_start)
11943 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11945 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11946 GET_MODE_BITSIZE (truncated)))
11951 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11952 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11953 might be able to turn a truncate into a subreg using this information.
11954 Return -1 if traversing *P is complete or 0 otherwise. */
11957 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11960 enum machine_mode truncated_mode;
11961 reg_stat_type *rsp;
11963 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11965 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11966 truncated_mode = GET_MODE (x);
11968 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11971 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11972 GET_MODE_BITSIZE (original_mode)))
11975 x = SUBREG_REG (x);
11977 /* ??? For hard-regs we now record everything. We might be able to
11978 optimize this using last_set_mode. */
11979 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11980 truncated_mode = GET_MODE (x);
11984 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11985 if (rsp->truncated_to_mode == 0
11986 || rsp->truncation_label < label_tick_ebb_start
11987 || (GET_MODE_SIZE (truncated_mode)
11988 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11990 rsp->truncated_to_mode = truncated_mode;
11991 rsp->truncation_label = label_tick;
11997 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11998 the modes they are used in. This can help truning TRUNCATEs into
12002 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12004 for_each_rtx (x, record_truncated_value, NULL);
12007 /* Scan X for promoted SUBREGs. For each one found,
12008 note what it implies to the registers used in it. */
12011 check_promoted_subreg (rtx insn, rtx x)
12013 if (GET_CODE (x) == SUBREG
12014 && SUBREG_PROMOTED_VAR_P (x)
12015 && REG_P (SUBREG_REG (x)))
12016 record_promoted_value (insn, x);
12019 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12022 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12026 check_promoted_subreg (insn, XEXP (x, i));
12030 if (XVEC (x, i) != 0)
12031 for (j = 0; j < XVECLEN (x, i); j++)
12032 check_promoted_subreg (insn, XVECEXP (x, i, j));
12038 /* Verify that all the registers and memory references mentioned in *LOC are
12039 still valid. *LOC was part of a value set in INSN when label_tick was
12040 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12041 the invalid references with (clobber (const_int 0)) and return 1. This
12042 replacement is useful because we often can get useful information about
12043 the form of a value (e.g., if it was produced by a shift that always
12044 produces -1 or 0) even though we don't know exactly what registers it
12045 was produced from. */
12048 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12051 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12052 int len = GET_RTX_LENGTH (GET_CODE (x));
12057 unsigned int regno = REGNO (x);
12058 unsigned int endregno = END_REGNO (x);
12061 for (j = regno; j < endregno; j++)
12063 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12064 if (rsp->last_set_invalid
12065 /* If this is a pseudo-register that was only set once and not
12066 live at the beginning of the function, it is always valid. */
12067 || (! (regno >= FIRST_PSEUDO_REGISTER
12068 && REG_N_SETS (regno) == 1
12069 && (!REGNO_REG_SET_P
12070 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12071 && rsp->last_set_label > tick))
12074 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12081 /* If this is a memory reference, make sure that there were no stores after
12082 it that might have clobbered the value. We don't have alias info, so we
12083 assume any store invalidates it. Moreover, we only have local UIDs, so
12084 we also assume that there were stores in the intervening basic blocks. */
12085 else if (MEM_P (x) && !MEM_READONLY_P (x)
12086 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12089 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12093 for (i = 0; i < len; i++)
12097 /* Check for identical subexpressions. If x contains
12098 identical subexpression we only have to traverse one of
12100 if (i == 1 && ARITHMETIC_P (x))
12102 /* Note that at this point x0 has already been checked
12103 and found valid. */
12104 rtx x0 = XEXP (x, 0);
12105 rtx x1 = XEXP (x, 1);
12107 /* If x0 and x1 are identical then x is also valid. */
12111 /* If x1 is identical to a subexpression of x0 then
12112 while checking x0, x1 has already been checked. Thus
12113 it is valid and so as x. */
12114 if (ARITHMETIC_P (x0)
12115 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12118 /* If x0 is identical to a subexpression of x1 then x is
12119 valid iff the rest of x1 is valid. */
12120 if (ARITHMETIC_P (x1)
12121 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12123 get_last_value_validate (&XEXP (x1,
12124 x0 == XEXP (x1, 0) ? 1 : 0),
12125 insn, tick, replace);
12128 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12132 else if (fmt[i] == 'E')
12133 for (j = 0; j < XVECLEN (x, i); j++)
12134 if (get_last_value_validate (&XVECEXP (x, i, j),
12135 insn, tick, replace) == 0)
12139 /* If we haven't found a reason for it to be invalid, it is valid. */
12143 /* Get the last value assigned to X, if known. Some registers
12144 in the value may be replaced with (clobber (const_int 0)) if their value
12145 is known longer known reliably. */
12148 get_last_value (const_rtx x)
12150 unsigned int regno;
12152 reg_stat_type *rsp;
12154 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12155 then convert it to the desired mode. If this is a paradoxical SUBREG,
12156 we cannot predict what values the "extra" bits might have. */
12157 if (GET_CODE (x) == SUBREG
12158 && subreg_lowpart_p (x)
12159 && (GET_MODE_SIZE (GET_MODE (x))
12160 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12161 && (value = get_last_value (SUBREG_REG (x))) != 0)
12162 return gen_lowpart (GET_MODE (x), value);
12168 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12169 value = rsp->last_set_value;
12171 /* If we don't have a value, or if it isn't for this basic block and
12172 it's either a hard register, set more than once, or it's a live
12173 at the beginning of the function, return 0.
12175 Because if it's not live at the beginning of the function then the reg
12176 is always set before being used (is never used without being set).
12177 And, if it's set only once, and it's always set before use, then all
12178 uses must have the same last value, even if it's not from this basic
12182 || (rsp->last_set_label < label_tick_ebb_start
12183 && (regno < FIRST_PSEUDO_REGISTER
12184 || REG_N_SETS (regno) != 1
12186 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12189 /* If the value was set in a later insn than the ones we are processing,
12190 we can't use it even if the register was only set once. */
12191 if (rsp->last_set_label == label_tick
12192 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12195 /* If the value has all its registers valid, return it. */
12196 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12199 /* Otherwise, make a copy and replace any invalid register with
12200 (clobber (const_int 0)). If that fails for some reason, return 0. */
12202 value = copy_rtx (value);
12203 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12209 /* Return nonzero if expression X refers to a REG or to memory
12210 that is set in an instruction more recent than FROM_LUID. */
12213 use_crosses_set_p (const_rtx x, int from_luid)
12217 enum rtx_code code = GET_CODE (x);
12221 unsigned int regno = REGNO (x);
12222 unsigned endreg = END_REGNO (x);
12224 #ifdef PUSH_ROUNDING
12225 /* Don't allow uses of the stack pointer to be moved,
12226 because we don't know whether the move crosses a push insn. */
12227 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12230 for (; regno < endreg; regno++)
12232 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12234 && rsp->last_set_label == label_tick
12235 && DF_INSN_LUID (rsp->last_set) > from_luid)
12241 if (code == MEM && mem_last_set > from_luid)
12244 fmt = GET_RTX_FORMAT (code);
12246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12251 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12252 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12255 else if (fmt[i] == 'e'
12256 && use_crosses_set_p (XEXP (x, i), from_luid))
12262 /* Define three variables used for communication between the following
12265 static unsigned int reg_dead_regno, reg_dead_endregno;
12266 static int reg_dead_flag;
12268 /* Function called via note_stores from reg_dead_at_p.
12270 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12271 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12274 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12276 unsigned int regno, endregno;
12281 regno = REGNO (dest);
12282 endregno = END_REGNO (dest);
12283 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12284 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12287 /* Return nonzero if REG is known to be dead at INSN.
12289 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12290 referencing REG, it is dead. If we hit a SET referencing REG, it is
12291 live. Otherwise, see if it is live or dead at the start of the basic
12292 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12293 must be assumed to be always live. */
12296 reg_dead_at_p (rtx reg, rtx insn)
12301 /* Set variables for reg_dead_at_p_1. */
12302 reg_dead_regno = REGNO (reg);
12303 reg_dead_endregno = END_REGNO (reg);
12307 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12308 we allow the machine description to decide whether use-and-clobber
12309 patterns are OK. */
12310 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12312 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12313 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12317 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12318 beginning of basic block. */
12319 block = BLOCK_FOR_INSN (insn);
12324 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12326 return reg_dead_flag == 1 ? 1 : 0;
12328 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12332 if (insn == BB_HEAD (block))
12335 insn = PREV_INSN (insn);
12338 /* Look at live-in sets for the basic block that we were in. */
12339 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12340 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12346 /* Note hard registers in X that are used. */
12349 mark_used_regs_combine (rtx x)
12351 RTX_CODE code = GET_CODE (x);
12352 unsigned int regno;
12365 case ADDR_DIFF_VEC:
12368 /* CC0 must die in the insn after it is set, so we don't need to take
12369 special note of it here. */
12375 /* If we are clobbering a MEM, mark any hard registers inside the
12376 address as used. */
12377 if (MEM_P (XEXP (x, 0)))
12378 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12383 /* A hard reg in a wide mode may really be multiple registers.
12384 If so, mark all of them just like the first. */
12385 if (regno < FIRST_PSEUDO_REGISTER)
12387 /* None of this applies to the stack, frame or arg pointers. */
12388 if (regno == STACK_POINTER_REGNUM
12389 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12390 || regno == HARD_FRAME_POINTER_REGNUM
12392 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12393 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12395 || regno == FRAME_POINTER_REGNUM)
12398 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12404 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12406 rtx testreg = SET_DEST (x);
12408 while (GET_CODE (testreg) == SUBREG
12409 || GET_CODE (testreg) == ZERO_EXTRACT
12410 || GET_CODE (testreg) == STRICT_LOW_PART)
12411 testreg = XEXP (testreg, 0);
12413 if (MEM_P (testreg))
12414 mark_used_regs_combine (XEXP (testreg, 0));
12416 mark_used_regs_combine (SET_SRC (x));
12424 /* Recursively scan the operands of this expression. */
12427 const char *fmt = GET_RTX_FORMAT (code);
12429 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12432 mark_used_regs_combine (XEXP (x, i));
12433 else if (fmt[i] == 'E')
12437 for (j = 0; j < XVECLEN (x, i); j++)
12438 mark_used_regs_combine (XVECEXP (x, i, j));
12444 /* Remove register number REGNO from the dead registers list of INSN.
12446 Return the note used to record the death, if there was one. */
12449 remove_death (unsigned int regno, rtx insn)
12451 rtx note = find_regno_note (insn, REG_DEAD, regno);
12454 remove_note (insn, note);
12459 /* For each register (hardware or pseudo) used within expression X, if its
12460 death is in an instruction with luid between FROM_LUID (inclusive) and
12461 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12462 list headed by PNOTES.
12464 That said, don't move registers killed by maybe_kill_insn.
12466 This is done when X is being merged by combination into TO_INSN. These
12467 notes will then be distributed as needed. */
12470 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12475 enum rtx_code code = GET_CODE (x);
12479 unsigned int regno = REGNO (x);
12480 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12482 /* Don't move the register if it gets killed in between from and to. */
12483 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12484 && ! reg_referenced_p (x, maybe_kill_insn))
12488 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12489 && DF_INSN_LUID (where_dead) >= from_luid
12490 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12492 rtx note = remove_death (regno, where_dead);
12494 /* It is possible for the call above to return 0. This can occur
12495 when last_death points to I2 or I1 that we combined with.
12496 In that case make a new note.
12498 We must also check for the case where X is a hard register
12499 and NOTE is a death note for a range of hard registers
12500 including X. In that case, we must put REG_DEAD notes for
12501 the remaining registers in place of NOTE. */
12503 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12504 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12505 > GET_MODE_SIZE (GET_MODE (x))))
12507 unsigned int deadregno = REGNO (XEXP (note, 0));
12508 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12509 unsigned int ourend = END_HARD_REGNO (x);
12512 for (i = deadregno; i < deadend; i++)
12513 if (i < regno || i >= ourend)
12514 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12517 /* If we didn't find any note, or if we found a REG_DEAD note that
12518 covers only part of the given reg, and we have a multi-reg hard
12519 register, then to be safe we must check for REG_DEAD notes
12520 for each register other than the first. They could have
12521 their own REG_DEAD notes lying around. */
12522 else if ((note == 0
12524 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12525 < GET_MODE_SIZE (GET_MODE (x)))))
12526 && regno < FIRST_PSEUDO_REGISTER
12527 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12529 unsigned int ourend = END_HARD_REGNO (x);
12530 unsigned int i, offset;
12534 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12538 for (i = regno + offset; i < ourend; i++)
12539 move_deaths (regno_reg_rtx[i],
12540 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12543 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12545 XEXP (note, 1) = *pnotes;
12549 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12555 else if (GET_CODE (x) == SET)
12557 rtx dest = SET_DEST (x);
12559 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12561 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12562 that accesses one word of a multi-word item, some
12563 piece of everything register in the expression is used by
12564 this insn, so remove any old death. */
12565 /* ??? So why do we test for equality of the sizes? */
12567 if (GET_CODE (dest) == ZERO_EXTRACT
12568 || GET_CODE (dest) == STRICT_LOW_PART
12569 || (GET_CODE (dest) == SUBREG
12570 && (((GET_MODE_SIZE (GET_MODE (dest))
12571 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12572 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12573 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12575 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12579 /* If this is some other SUBREG, we know it replaces the entire
12580 value, so use that as the destination. */
12581 if (GET_CODE (dest) == SUBREG)
12582 dest = SUBREG_REG (dest);
12584 /* If this is a MEM, adjust deaths of anything used in the address.
12585 For a REG (the only other possibility), the entire value is
12586 being replaced so the old value is not used in this insn. */
12589 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12594 else if (GET_CODE (x) == CLOBBER)
12597 len = GET_RTX_LENGTH (code);
12598 fmt = GET_RTX_FORMAT (code);
12600 for (i = 0; i < len; i++)
12605 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12606 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12609 else if (fmt[i] == 'e')
12610 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12614 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12615 pattern of an insn. X must be a REG. */
12618 reg_bitfield_target_p (rtx x, rtx body)
12622 if (GET_CODE (body) == SET)
12624 rtx dest = SET_DEST (body);
12626 unsigned int regno, tregno, endregno, endtregno;
12628 if (GET_CODE (dest) == ZERO_EXTRACT)
12629 target = XEXP (dest, 0);
12630 else if (GET_CODE (dest) == STRICT_LOW_PART)
12631 target = SUBREG_REG (XEXP (dest, 0));
12635 if (GET_CODE (target) == SUBREG)
12636 target = SUBREG_REG (target);
12638 if (!REG_P (target))
12641 tregno = REGNO (target), regno = REGNO (x);
12642 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12643 return target == x;
12645 endtregno = end_hard_regno (GET_MODE (target), tregno);
12646 endregno = end_hard_regno (GET_MODE (x), regno);
12648 return endregno > tregno && regno < endtregno;
12651 else if (GET_CODE (body) == PARALLEL)
12652 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12653 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12659 /* Return the next insn after INSN that is neither a NOTE nor a
12660 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12663 next_nonnote_nondebug_insn (rtx insn)
12667 insn = NEXT_INSN (insn);
12672 if (DEBUG_INSN_P (insn))
12682 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12683 as appropriate. I3 and I2 are the insns resulting from the combination
12684 insns including FROM (I2 may be zero).
12686 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12687 not need REG_DEAD notes because they are being substituted for. This
12688 saves searching in the most common cases.
12690 Each note in the list is either ignored or placed on some insns, depending
12691 on the type of note. */
12694 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12697 rtx note, next_note;
12700 for (note = notes; note; note = next_note)
12702 rtx place = 0, place2 = 0;
12704 next_note = XEXP (note, 1);
12705 switch (REG_NOTE_KIND (note))
12709 /* Doesn't matter much where we put this, as long as it's somewhere.
12710 It is preferable to keep these notes on branches, which is most
12711 likely to be i3. */
12715 case REG_VALUE_PROFILE:
12716 /* Just get rid of this note, as it is unused later anyway. */
12719 case REG_NON_LOCAL_GOTO:
12724 gcc_assert (i2 && JUMP_P (i2));
12729 case REG_EH_REGION:
12730 /* These notes must remain with the call or trapping instruction. */
12733 else if (i2 && CALL_P (i2))
12737 gcc_assert (cfun->can_throw_non_call_exceptions);
12738 if (may_trap_p (i3))
12740 else if (i2 && may_trap_p (i2))
12742 /* ??? Otherwise assume we've combined things such that we
12743 can now prove that the instructions can't trap. Drop the
12744 note in this case. */
12750 /* These notes must remain with the call. It should not be
12751 possible for both I2 and I3 to be a call. */
12756 gcc_assert (i2 && CALL_P (i2));
12762 /* Any clobbers for i3 may still exist, and so we must process
12763 REG_UNUSED notes from that insn.
12765 Any clobbers from i2 or i1 can only exist if they were added by
12766 recog_for_combine. In that case, recog_for_combine created the
12767 necessary REG_UNUSED notes. Trying to keep any original
12768 REG_UNUSED notes from these insns can cause incorrect output
12769 if it is for the same register as the original i3 dest.
12770 In that case, we will notice that the register is set in i3,
12771 and then add a REG_UNUSED note for the destination of i3, which
12772 is wrong. However, it is possible to have REG_UNUSED notes from
12773 i2 or i1 for register which were both used and clobbered, so
12774 we keep notes from i2 or i1 if they will turn into REG_DEAD
12777 /* If this register is set or clobbered in I3, put the note there
12778 unless there is one already. */
12779 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12781 if (from_insn != i3)
12784 if (! (REG_P (XEXP (note, 0))
12785 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12786 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12789 /* Otherwise, if this register is used by I3, then this register
12790 now dies here, so we must put a REG_DEAD note here unless there
12792 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12793 && ! (REG_P (XEXP (note, 0))
12794 ? find_regno_note (i3, REG_DEAD,
12795 REGNO (XEXP (note, 0)))
12796 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12798 PUT_REG_NOTE_KIND (note, REG_DEAD);
12806 /* These notes say something about results of an insn. We can
12807 only support them if they used to be on I3 in which case they
12808 remain on I3. Otherwise they are ignored.
12810 If the note refers to an expression that is not a constant, we
12811 must also ignore the note since we cannot tell whether the
12812 equivalence is still true. It might be possible to do
12813 slightly better than this (we only have a problem if I2DEST
12814 or I1DEST is present in the expression), but it doesn't
12815 seem worth the trouble. */
12817 if (from_insn == i3
12818 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12823 /* These notes say something about how a register is used. They must
12824 be present on any use of the register in I2 or I3. */
12825 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12828 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12837 case REG_LABEL_TARGET:
12838 case REG_LABEL_OPERAND:
12839 /* This can show up in several ways -- either directly in the
12840 pattern, or hidden off in the constant pool with (or without?)
12841 a REG_EQUAL note. */
12842 /* ??? Ignore the without-reg_equal-note problem for now. */
12843 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12844 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12845 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12846 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12850 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12851 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12852 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12853 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12861 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12862 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12864 if (place && JUMP_P (place)
12865 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12866 && (JUMP_LABEL (place) == NULL
12867 || JUMP_LABEL (place) == XEXP (note, 0)))
12869 rtx label = JUMP_LABEL (place);
12872 JUMP_LABEL (place) = XEXP (note, 0);
12873 else if (LABEL_P (label))
12874 LABEL_NUSES (label)--;
12877 if (place2 && JUMP_P (place2)
12878 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12879 && (JUMP_LABEL (place2) == NULL
12880 || JUMP_LABEL (place2) == XEXP (note, 0)))
12882 rtx label = JUMP_LABEL (place2);
12885 JUMP_LABEL (place2) = XEXP (note, 0);
12886 else if (LABEL_P (label))
12887 LABEL_NUSES (label)--;
12893 /* This note says something about the value of a register prior
12894 to the execution of an insn. It is too much trouble to see
12895 if the note is still correct in all situations. It is better
12896 to simply delete it. */
12900 /* If we replaced the right hand side of FROM_INSN with a
12901 REG_EQUAL note, the original use of the dying register
12902 will not have been combined into I3 and I2. In such cases,
12903 FROM_INSN is guaranteed to be the first of the combined
12904 instructions, so we simply need to search back before
12905 FROM_INSN for the previous use or set of this register,
12906 then alter the notes there appropriately.
12908 If the register is used as an input in I3, it dies there.
12909 Similarly for I2, if it is nonzero and adjacent to I3.
12911 If the register is not used as an input in either I3 or I2
12912 and it is not one of the registers we were supposed to eliminate,
12913 there are two possibilities. We might have a non-adjacent I2
12914 or we might have somehow eliminated an additional register
12915 from a computation. For example, we might have had A & B where
12916 we discover that B will always be zero. In this case we will
12917 eliminate the reference to A.
12919 In both cases, we must search to see if we can find a previous
12920 use of A and put the death note there. */
12923 && from_insn == i2mod
12924 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12929 && CALL_P (from_insn)
12930 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12932 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12934 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12935 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12937 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12939 && reg_overlap_mentioned_p (XEXP (note, 0),
12941 || rtx_equal_p (XEXP (note, 0), elim_i1))
12948 basic_block bb = this_basic_block;
12950 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12952 if (!NONDEBUG_INSN_P (tem))
12954 if (tem == BB_HEAD (bb))
12959 /* If the register is being set at TEM, see if that is all
12960 TEM is doing. If so, delete TEM. Otherwise, make this
12961 into a REG_UNUSED note instead. Don't delete sets to
12962 global register vars. */
12963 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12964 || !global_regs[REGNO (XEXP (note, 0))])
12965 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12967 rtx set = single_set (tem);
12968 rtx inner_dest = 0;
12970 rtx cc0_setter = NULL_RTX;
12974 for (inner_dest = SET_DEST (set);
12975 (GET_CODE (inner_dest) == STRICT_LOW_PART
12976 || GET_CODE (inner_dest) == SUBREG
12977 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12978 inner_dest = XEXP (inner_dest, 0))
12981 /* Verify that it was the set, and not a clobber that
12982 modified the register.
12984 CC0 targets must be careful to maintain setter/user
12985 pairs. If we cannot delete the setter due to side
12986 effects, mark the user with an UNUSED note instead
12989 if (set != 0 && ! side_effects_p (SET_SRC (set))
12990 && rtx_equal_p (XEXP (note, 0), inner_dest)
12992 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12993 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12994 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12998 /* Move the notes and links of TEM elsewhere.
12999 This might delete other dead insns recursively.
13000 First set the pattern to something that won't use
13002 rtx old_notes = REG_NOTES (tem);
13004 PATTERN (tem) = pc_rtx;
13005 REG_NOTES (tem) = NULL;
13007 distribute_notes (old_notes, tem, tem, NULL_RTX,
13008 NULL_RTX, NULL_RTX);
13009 distribute_links (LOG_LINKS (tem));
13011 SET_INSN_DELETED (tem);
13016 /* Delete the setter too. */
13019 PATTERN (cc0_setter) = pc_rtx;
13020 old_notes = REG_NOTES (cc0_setter);
13021 REG_NOTES (cc0_setter) = NULL;
13023 distribute_notes (old_notes, cc0_setter,
13024 cc0_setter, NULL_RTX,
13025 NULL_RTX, NULL_RTX);
13026 distribute_links (LOG_LINKS (cc0_setter));
13028 SET_INSN_DELETED (cc0_setter);
13029 if (cc0_setter == i2)
13036 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13038 /* If there isn't already a REG_UNUSED note, put one
13039 here. Do not place a REG_DEAD note, even if
13040 the register is also used here; that would not
13041 match the algorithm used in lifetime analysis
13042 and can cause the consistency check in the
13043 scheduler to fail. */
13044 if (! find_regno_note (tem, REG_UNUSED,
13045 REGNO (XEXP (note, 0))))
13050 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13052 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13056 /* If we are doing a 3->2 combination, and we have a
13057 register which formerly died in i3 and was not used
13058 by i2, which now no longer dies in i3 and is used in
13059 i2 but does not die in i2, and place is between i2
13060 and i3, then we may need to move a link from place to
13062 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13064 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13065 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13067 rtx links = LOG_LINKS (place);
13068 LOG_LINKS (place) = 0;
13069 distribute_links (links);
13074 if (tem == BB_HEAD (bb))
13080 /* If the register is set or already dead at PLACE, we needn't do
13081 anything with this note if it is still a REG_DEAD note.
13082 We check here if it is set at all, not if is it totally replaced,
13083 which is what `dead_or_set_p' checks, so also check for it being
13086 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13088 unsigned int regno = REGNO (XEXP (note, 0));
13089 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13091 if (dead_or_set_p (place, XEXP (note, 0))
13092 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13094 /* Unless the register previously died in PLACE, clear
13095 last_death. [I no longer understand why this is
13097 if (rsp->last_death != place)
13098 rsp->last_death = 0;
13102 rsp->last_death = place;
13104 /* If this is a death note for a hard reg that is occupying
13105 multiple registers, ensure that we are still using all
13106 parts of the object. If we find a piece of the object
13107 that is unused, we must arrange for an appropriate REG_DEAD
13108 note to be added for it. However, we can't just emit a USE
13109 and tag the note to it, since the register might actually
13110 be dead; so we recourse, and the recursive call then finds
13111 the previous insn that used this register. */
13113 if (place && regno < FIRST_PSEUDO_REGISTER
13114 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13116 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13120 for (i = regno; i < endregno; i++)
13121 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13122 && ! find_regno_fusage (place, USE, i))
13123 || dead_or_set_regno_p (place, i))
13128 /* Put only REG_DEAD notes for pieces that are
13129 not already dead or set. */
13131 for (i = regno; i < endregno;
13132 i += hard_regno_nregs[i][reg_raw_mode[i]])
13134 rtx piece = regno_reg_rtx[i];
13135 basic_block bb = this_basic_block;
13137 if (! dead_or_set_p (place, piece)
13138 && ! reg_bitfield_target_p (piece,
13141 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13144 distribute_notes (new_note, place, place,
13145 NULL_RTX, NULL_RTX, NULL_RTX);
13147 else if (! refers_to_regno_p (i, i + 1,
13148 PATTERN (place), 0)
13149 && ! find_regno_fusage (place, USE, i))
13150 for (tem = PREV_INSN (place); ;
13151 tem = PREV_INSN (tem))
13153 if (!NONDEBUG_INSN_P (tem))
13155 if (tem == BB_HEAD (bb))
13159 if (dead_or_set_p (tem, piece)
13160 || reg_bitfield_target_p (piece,
13163 add_reg_note (tem, REG_UNUSED, piece);
13177 /* Any other notes should not be present at this point in the
13179 gcc_unreachable ();
13184 XEXP (note, 1) = REG_NOTES (place);
13185 REG_NOTES (place) = note;
13189 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13193 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13194 I3, I2, and I1 to new locations. This is also called to add a link
13195 pointing at I3 when I3's destination is changed. */
13198 distribute_links (rtx links)
13200 rtx link, next_link;
13202 for (link = links; link; link = next_link)
13208 next_link = XEXP (link, 1);
13210 /* If the insn that this link points to is a NOTE or isn't a single
13211 set, ignore it. In the latter case, it isn't clear what we
13212 can do other than ignore the link, since we can't tell which
13213 register it was for. Such links wouldn't be used by combine
13216 It is not possible for the destination of the target of the link to
13217 have been changed by combine. The only potential of this is if we
13218 replace I3, I2, and I1 by I3 and I2. But in that case the
13219 destination of I2 also remains unchanged. */
13221 if (NOTE_P (XEXP (link, 0))
13222 || (set = single_set (XEXP (link, 0))) == 0)
13225 reg = SET_DEST (set);
13226 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13227 || GET_CODE (reg) == STRICT_LOW_PART)
13228 reg = XEXP (reg, 0);
13230 /* A LOG_LINK is defined as being placed on the first insn that uses
13231 a register and points to the insn that sets the register. Start
13232 searching at the next insn after the target of the link and stop
13233 when we reach a set of the register or the end of the basic block.
13235 Note that this correctly handles the link that used to point from
13236 I3 to I2. Also note that not much searching is typically done here
13237 since most links don't point very far away. */
13239 for (insn = NEXT_INSN (XEXP (link, 0));
13240 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13241 || BB_HEAD (this_basic_block->next_bb) != insn));
13242 insn = NEXT_INSN (insn))
13243 if (DEBUG_INSN_P (insn))
13245 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13247 if (reg_referenced_p (reg, PATTERN (insn)))
13251 else if (CALL_P (insn)
13252 && find_reg_fusage (insn, USE, reg))
13257 else if (INSN_P (insn) && reg_set_p (reg, insn))
13260 /* If we found a place to put the link, place it there unless there
13261 is already a link to the same insn as LINK at that point. */
13267 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13268 if (XEXP (link2, 0) == XEXP (link, 0))
13273 XEXP (link, 1) = LOG_LINKS (place);
13274 LOG_LINKS (place) = link;
13276 /* Set added_links_insn to the earliest insn we added a
13278 if (added_links_insn == 0
13279 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13280 added_links_insn = place;
13286 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13287 Check whether the expression pointer to by LOC is a register or
13288 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13289 Otherwise return zero. */
13292 unmentioned_reg_p_1 (rtx *loc, void *expr)
13297 && (REG_P (x) || MEM_P (x))
13298 && ! reg_mentioned_p (x, (rtx) expr))
13303 /* Check for any register or memory mentioned in EQUIV that is not
13304 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13305 of EXPR where some registers may have been replaced by constants. */
13308 unmentioned_reg_p (rtx equiv, rtx expr)
13310 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13314 dump_combine_stats (FILE *file)
13318 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13319 combine_attempts, combine_merges, combine_extras, combine_successes);
13323 dump_combine_total_stats (FILE *file)
13327 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13328 total_attempts, total_merges, total_extras, total_successes);
13332 gate_handle_combine (void)
13334 return (optimize > 0);
13337 /* Try combining insns through substitution. */
13338 static unsigned int
13339 rest_of_handle_combine (void)
13341 int rebuild_jump_labels_after_combine;
13343 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13344 df_note_add_problem ();
13347 regstat_init_n_sets_and_refs ();
13349 rebuild_jump_labels_after_combine
13350 = combine_instructions (get_insns (), max_reg_num ());
13352 /* Combining insns may have turned an indirect jump into a
13353 direct jump. Rebuild the JUMP_LABEL fields of jumping
13355 if (rebuild_jump_labels_after_combine)
13357 timevar_push (TV_JUMP);
13358 rebuild_jump_labels (get_insns ());
13360 timevar_pop (TV_JUMP);
13363 regstat_free_n_sets_and_refs ();
13367 struct rtl_opt_pass pass_combine =
13371 "combine", /* name */
13372 gate_handle_combine, /* gate */
13373 rest_of_handle_combine, /* execute */
13376 0, /* static_pass_number */
13377 TV_COMBINE, /* tv_id */
13378 PROP_cfglayout, /* properties_required */
13379 0, /* properties_provided */
13380 0, /* properties_destroyed */
13381 0, /* todo_flags_start */
13383 TODO_df_finish | TODO_verify_rtl_sharing |
13384 TODO_ggc_collect, /* todo_flags_finish */
OSDN Git Service
