1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
97 /* Number of attempts to combine instructions in this function. */
99 static int combine_attempts;
101 /* Number of attempts that got as far as substitution in this function. */
103 static int combine_merges;
105 /* Number of instructions combined with added SETs in this function. */
107 static int combine_extras;
109 /* Number of instructions combined in this function. */
111 static int combine_successes;
113 /* Totals over entire compilation. */
115 static int total_attempts, total_merges, total_extras, total_successes;
118 /* Vector mapping INSN_UIDs to cuids.
119 The cuids are like uids but increase monotonically always.
120 Combine always uses cuids so that it can compare them.
121 But actually renumbering the uids, which we used to do,
122 proves to be a bad idea because it makes it hard to compare
123 the dumps produced by earlier passes with those from later passes. */
125 static int *uid_cuid;
126 static int max_uid_cuid;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) \
131 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
133 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
134 BITS_PER_WORD would invoke undefined behavior. Work around it. */
136 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
137 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
139 /* Maximum register number, which is the size of the tables below. */
141 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
147 /* Record last point of modification of (hard or pseudo) register n. */
150 /* The next group of fields allows the recording of the last value assigned
151 to (hard or pseudo) register n. We use this information to see if an
152 operation being processed is redundant given a prior operation performed
153 on the register. For example, an `and' with a constant is redundant if
154 all the zero bits are already known to be turned off.
156 We use an approach similar to that used by cse, but change it in the
159 (1) We do not want to reinitialize at each label.
160 (2) It is useful, but not critical, to know the actual value assigned
161 to a register. Often just its form is helpful.
163 Therefore, we maintain the following fields:
165 last_set_value the last value assigned
166 last_set_label records the value of label_tick when the
167 register was assigned
168 last_set_table_tick records the value of label_tick when a
169 value using the register is assigned
170 last_set_invalid set to nonzero when it is not valid
171 to use the value of this register in some
174 To understand the usage of these tables, it is important to understand
175 the distinction between the value in last_set_value being valid and
176 the register being validly contained in some other expression in the
179 (The next two parameters are out of date).
181 reg_stat[i].last_set_value is valid if it is nonzero, and either
182 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
184 Register I may validly appear in any expression returned for the value
185 of another register if reg_n_sets[i] is 1. It may also appear in the
186 value for register J if reg_stat[j].last_set_invalid is zero, or
187 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
189 If an expression is found in the table containing a register which may
190 not validly appear in an expression, the register is replaced by
191 something that won't match, (clobber (const_int 0)). */
193 /* Record last value assigned to (hard or pseudo) register n. */
197 /* Record the value of label_tick when an expression involving register n
198 is placed in last_set_value. */
200 int last_set_table_tick;
202 /* Record the value of label_tick when the value for register n is placed in
207 /* These fields are maintained in parallel with last_set_value and are
208 used to store the mode in which the register was last set, te bits
209 that were known to be zero when it was last set, and the number of
210 sign bits copies it was known to have when it was last set. */
212 unsigned HOST_WIDE_INT last_set_nonzero_bits;
213 char last_set_sign_bit_copies;
214 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
216 /* Set nonzero if references to register n in expressions should not be
217 used. last_set_invalid is set nonzero when this register is being
218 assigned to and last_set_table_tick == label_tick. */
220 char last_set_invalid;
222 /* Some registers that are set more than once and used in more than one
223 basic block are nevertheless always set in similar ways. For example,
224 a QImode register may be loaded from memory in two places on a machine
225 where byte loads zero extend.
227 We record in the following fields if a register has some leading bits
228 that are always equal to the sign bit, and what we know about the
229 nonzero bits of a register, specifically which bits are known to be
232 If an entry is zero, it means that we don't know anything special. */
234 unsigned char sign_bit_copies;
236 unsigned HOST_WIDE_INT nonzero_bits;
239 static struct reg_stat *reg_stat;
241 /* Record the cuid of the last insn that invalidated memory
242 (anything that writes memory, and subroutine calls, but not pushes). */
244 static int mem_last_set;
246 /* Record the cuid of the last CALL_INSN
247 so we can tell whether a potential combination crosses any calls. */
249 static int last_call_cuid;
251 /* When `subst' is called, this is the insn that is being modified
252 (by combining in a previous insn). The PATTERN of this insn
253 is still the old pattern partially modified and it should not be
254 looked at, but this may be used to examine the successors of the insn
255 to judge whether a simplification is valid. */
257 static rtx subst_insn;
259 /* This is the lowest CUID that `subst' is currently dealing with.
260 get_last_value will not return a value if the register was set at or
261 after this CUID. If not for this mechanism, we could get confused if
262 I2 or I1 in try_combine were an insn that used the old value of a register
263 to obtain a new value. In that case, we might erroneously get the
264 new value of the register when we wanted the old one. */
266 static int subst_low_cuid;
268 /* This contains any hard registers that are used in newpat; reg_dead_at_p
269 must consider all these registers to be always live. */
271 static HARD_REG_SET newpat_used_regs;
273 /* This is an insn to which a LOG_LINKS entry has been added. If this
274 insn is the earlier than I2 or I3, combine should rescan starting at
277 static rtx added_links_insn;
279 /* Basic block in which we are performing combines. */
280 static basic_block this_basic_block;
282 /* A bitmap indicating which blocks had registers go dead at entry.
283 After combine, we'll need to re-do global life analysis with
284 those blocks as starting points. */
285 static sbitmap refresh_blocks;
287 /* The following array records the combine_insn_cost for every insn
288 in the instruction stream. */
290 static int *uid_insn_cost;
292 /* Length of the currently allocated uid_insn_cost array. */
294 static int last_insn_cost;
296 /* Incremented for each label. */
298 static int label_tick;
300 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
301 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
306 be safely used. It is zero while computing them and after combine has
307 completed. This former test prevents propagating values based on
308 previously set values, which can be incorrect if a variable is modified
311 static int nonzero_sign_valid;
314 /* Record one modification to rtl structure
315 to be undone by storing old_contents into *where.
316 is_int is 1 if the contents are an int. */
322 union {rtx r; int i;} old_contents;
323 union {rtx *r; int *i;} where;
326 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
327 num_undo says how many are currently recorded.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too. */
339 static struct undobuf undobuf;
341 /* Number of times the pseudo being substituted for
342 was found and replaced. */
344 static int n_occurrences;
346 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT,
349 unsigned HOST_WIDE_INT *);
350 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
352 unsigned int, unsigned int *);
353 static void do_SUBST (rtx *, rtx);
354 static void do_SUBST_INT (int *, int);
355 static void init_reg_last (void);
356 static void setup_incoming_promotions (void);
357 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
358 static int cant_combine_insn_p (rtx);
359 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
360 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
361 static int contains_muldiv (rtx);
362 static rtx try_combine (rtx, rtx, rtx, int *);
363 static void undo_all (void);
364 static void undo_commit (void);
365 static rtx *find_split_point (rtx *, rtx);
366 static rtx subst (rtx, rtx, rtx, int, int);
367 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
368 static rtx simplify_if_then_else (rtx);
369 static rtx simplify_set (rtx);
370 static rtx simplify_logical (rtx);
371 static rtx expand_compound_operation (rtx);
372 static rtx expand_field_assignment (rtx);
373 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
374 rtx, unsigned HOST_WIDE_INT, int, int, int);
375 static rtx extract_left_shift (rtx, int);
376 static rtx make_compound_operation (rtx, enum rtx_code);
377 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx force_to_mode (rtx, enum machine_mode,
380 unsigned HOST_WIDE_INT, rtx, int);
381 static rtx if_then_else_cond (rtx, rtx *, rtx *);
382 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
383 static int rtx_equal_for_field_assignment_p (rtx, rtx);
384 static rtx make_field_assignment (rtx);
385 static rtx apply_distributive_law (rtx);
386 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT);
388 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
389 HOST_WIDE_INT, enum machine_mode, int *);
390 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
392 static int recog_for_combine (rtx *, rtx, rtx *);
393 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
394 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
395 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
396 static void update_table_tick (rtx);
397 static void record_value_for_reg (rtx, rtx, rtx);
398 static void check_promoted_subreg (rtx, rtx);
399 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
400 static void record_dead_and_set_regs (rtx);
401 static int get_last_value_validate (rtx *, rtx, int, int);
402 static rtx get_last_value (rtx);
403 static int use_crosses_set_p (rtx, int);
404 static void reg_dead_at_p_1 (rtx, rtx, void *);
405 static int reg_dead_at_p (rtx, rtx);
406 static void move_deaths (rtx, rtx, int, rtx, rtx *);
407 static int reg_bitfield_target_p (rtx, rtx);
408 static void distribute_notes (rtx, rtx, rtx, rtx);
409 static void distribute_links (rtx);
410 static void mark_used_regs_combine (rtx);
411 static int insn_cuid (rtx);
412 static void record_promoted_value (rtx, rtx);
413 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
414 static enum rtx_code combine_reversed_comparison_code (rtx);
415 static int unmentioned_reg_p_1 (rtx *, void *);
416 static bool unmentioned_reg_p (rtx, rtx);
419 /* It is not safe to use ordinary gen_lowpart in combine.
420 See comments in gen_lowpart_for_combine. */
421 #undef RTL_HOOKS_GEN_LOWPART
422 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
424 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
425 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
427 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
428 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
430 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
433 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
434 insn. The substitution can be undone by undo_all. If INTO is already
435 set to NEWVAL, do not record this change. Because computing NEWVAL might
436 also call SUBST, we have to compute it before we put anything into
440 do_SUBST (rtx *into, rtx newval)
445 if (oldval == newval)
448 /* We'd like to catch as many invalid transformations here as
449 possible. Unfortunately, there are way too many mode changes
450 that are perfectly valid, so we'd waste too much effort for
451 little gain doing the checks here. Focus on catching invalid
452 transformations involving integer constants. */
453 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
454 && GET_CODE (newval) == CONST_INT)
456 /* Sanity check that we're replacing oldval with a CONST_INT
457 that is a valid sign-extension for the original mode. */
458 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
462 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
463 CONST_INT is not valid, because after the replacement, the
464 original mode would be gone. Unfortunately, we can't tell
465 when do_SUBST is called to replace the operand thereof, so we
466 perform this test on oldval instead, checking whether an
467 invalid replacement took place before we got here. */
468 if ((GET_CODE (oldval) == SUBREG
469 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
470 || (GET_CODE (oldval) == ZERO_EXTEND
471 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
476 buf = undobuf.frees, undobuf.frees = buf->next;
478 buf = xmalloc (sizeof (struct undo));
482 buf->old_contents.r = oldval;
485 buf->next = undobuf.undos, undobuf.undos = buf;
488 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
490 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
491 for the value of a HOST_WIDE_INT value (including CONST_INT) is
495 do_SUBST_INT (int *into, int newval)
500 if (oldval == newval)
504 buf = undobuf.frees, undobuf.frees = buf->next;
506 buf = xmalloc (sizeof (struct undo));
510 buf->old_contents.i = oldval;
513 buf->next = undobuf.undos, undobuf.undos = buf;
516 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
518 /* Calculate the rtx_cost of a single instruction. A return value of zero
519 indicates an instruction without a known cost. */
522 combine_insn_cost (rtx pat)
527 /* Extract the single set rtx from the instruction pattern.
528 We can't use single_set since we only have the pattern. */
529 if (GET_CODE (pat) == SET)
531 else if (GET_CODE (pat) == PARALLEL)
534 for (i = 0; i < XVECLEN (pat, 0); i++)
536 rtx x = XVECEXP (pat, 0, i);
537 if (GET_CODE (x) == SET)
550 cost = rtx_cost (SET_SRC (set), SET);
551 return cost > 0 ? cost : COSTS_N_INSNS (1);
554 /* Subroutine of try_combine. Determine whether the combine replacement
555 patterns NEWPAT and NEWI2PAT are cheaper according to combine_insn_cost
556 that the original instruction sequence I1, I2 and I3. Note that I1
557 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
558 costs of all instructions can be estimated, and the replacements are
559 more expensive than the original sequence. */
562 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
564 int i1_cost, i2_cost, i3_cost;
565 int new_i2_cost, new_i3_cost;
566 int old_cost, new_cost;
568 /* Lookup the original combine_insn_costs. */
569 i2_cost = INSN_UID (i2) <= last_insn_cost
570 ? uid_insn_cost[INSN_UID (i2)] : 0;
571 i3_cost = INSN_UID (i3) <= last_insn_cost
572 ? uid_insn_cost[INSN_UID (i3)] : 0;
576 i1_cost = INSN_UID (i1) <= last_insn_cost
577 ? uid_insn_cost[INSN_UID (i1)] : 0;
578 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
579 ? i1_cost + i2_cost + i3_cost : 0;
583 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
587 /* Calculate the replacement combine_insn_costs. */
588 new_i3_cost = combine_insn_cost (newpat);
591 new_i2_cost = combine_insn_cost (newi2pat);
592 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
593 ? new_i2_cost + new_i3_cost : 0;
597 new_cost = new_i3_cost;
601 /* Disallow this recombination if both new_cost and old_cost are
602 greater than zero, and new_cost is greater than old cost. */
603 if (!undobuf.other_insn
605 && new_cost > old_cost)
612 "rejecting combination of insns %d, %d and %d\n",
613 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
614 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
615 i1_cost, i2_cost, i3_cost, old_cost);
620 "rejecting combination of insns %d and %d\n",
621 INSN_UID (i2), INSN_UID (i3));
622 fprintf (dump_file, "original costs %d + %d = %d\n",
623 i2_cost, i3_cost, old_cost);
628 fprintf (dump_file, "replacement costs %d + %d = %d\n",
629 new_i2_cost, new_i3_cost, new_cost);
632 fprintf (dump_file, "replacement cost %d\n", new_cost);
638 /* Update the uid_insn_cost array with the replacement costs. */
639 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
640 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
642 uid_insn_cost[INSN_UID (i1)] = 0;
647 /* Main entry point for combiner. F is the first insn of the function.
648 NREGS is the first unused pseudo-reg number.
650 Return nonzero if the combiner has turned an indirect jump
651 instruction into a direct jump. */
653 combine_instructions (rtx f, unsigned int nregs)
660 rtx links, nextlinks;
662 int new_direct_jump_p = 0;
664 combine_attempts = 0;
667 combine_successes = 0;
669 combine_max_regno = nregs;
671 rtl_hooks = combine_rtl_hooks;
673 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
675 init_recog_no_volatile ();
677 /* Compute maximum uid value so uid_cuid can be allocated. */
679 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
680 if (INSN_UID (insn) > i)
683 uid_cuid = xmalloc ((i + 1) * sizeof (int));
686 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
688 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
689 problems when, for example, we have j <<= 1 in a loop. */
691 nonzero_sign_valid = 0;
693 /* Compute the mapping from uids to cuids.
694 Cuids are numbers assigned to insns, like uids,
695 except that cuids increase monotonically through the code.
697 Scan all SETs and see if we can deduce anything about what
698 bits are known to be zero for some registers and how many copies
699 of the sign bit are known to exist for those registers.
701 Also set any known values so that we can use it while searching
702 for what bits are known to be set. */
706 setup_incoming_promotions ();
708 refresh_blocks = sbitmap_alloc (last_basic_block);
709 sbitmap_zero (refresh_blocks);
711 /* Allocate array of current combine_insn_costs. */
712 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
713 last_insn_cost = max_uid_cuid;
715 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
717 uid_cuid[INSN_UID (insn)] = ++i;
723 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
725 record_dead_and_set_regs (insn);
728 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
729 if (REG_NOTE_KIND (links) == REG_INC)
730 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
734 /* Record the current combine_insn_cost of this instruction. */
735 uid_insn_cost[INSN_UID (insn)] = combine_insn_cost (PATTERN (insn));
737 fprintf(dump_file, "insn_cost %d: %d\n",
738 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
741 if (GET_CODE (insn) == CODE_LABEL)
745 nonzero_sign_valid = 1;
747 /* Now scan all the insns in forward order. */
753 setup_incoming_promotions ();
755 FOR_EACH_BB (this_basic_block)
757 for (insn = BB_HEAD (this_basic_block);
758 insn != NEXT_INSN (BB_END (this_basic_block));
759 insn = next ? next : NEXT_INSN (insn))
763 if (GET_CODE (insn) == CODE_LABEL)
766 else if (INSN_P (insn))
768 /* See if we know about function return values before this
769 insn based upon SUBREG flags. */
770 check_promoted_subreg (insn, PATTERN (insn));
772 /* Try this insn with each insn it links back to. */
774 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
775 if ((next = try_combine (insn, XEXP (links, 0),
776 NULL_RTX, &new_direct_jump_p)) != 0)
779 /* Try each sequence of three linked insns ending with this one. */
781 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
783 rtx link = XEXP (links, 0);
785 /* If the linked insn has been replaced by a note, then there
786 is no point in pursuing this chain any further. */
787 if (GET_CODE (link) == NOTE)
790 for (nextlinks = LOG_LINKS (link);
792 nextlinks = XEXP (nextlinks, 1))
793 if ((next = try_combine (insn, link,
795 &new_direct_jump_p)) != 0)
800 /* Try to combine a jump insn that uses CC0
801 with a preceding insn that sets CC0, and maybe with its
802 logical predecessor as well.
803 This is how we make decrement-and-branch insns.
804 We need this special code because data flow connections
805 via CC0 do not get entered in LOG_LINKS. */
807 if (GET_CODE (insn) == JUMP_INSN
808 && (prev = prev_nonnote_insn (insn)) != 0
809 && GET_CODE (prev) == INSN
810 && sets_cc0_p (PATTERN (prev)))
812 if ((next = try_combine (insn, prev,
813 NULL_RTX, &new_direct_jump_p)) != 0)
816 for (nextlinks = LOG_LINKS (prev); nextlinks;
817 nextlinks = XEXP (nextlinks, 1))
818 if ((next = try_combine (insn, prev,
820 &new_direct_jump_p)) != 0)
824 /* Do the same for an insn that explicitly references CC0. */
825 if (GET_CODE (insn) == INSN
826 && (prev = prev_nonnote_insn (insn)) != 0
827 && GET_CODE (prev) == INSN
828 && sets_cc0_p (PATTERN (prev))
829 && GET_CODE (PATTERN (insn)) == SET
830 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
832 if ((next = try_combine (insn, prev,
833 NULL_RTX, &new_direct_jump_p)) != 0)
836 for (nextlinks = LOG_LINKS (prev); nextlinks;
837 nextlinks = XEXP (nextlinks, 1))
838 if ((next = try_combine (insn, prev,
840 &new_direct_jump_p)) != 0)
844 /* Finally, see if any of the insns that this insn links to
845 explicitly references CC0. If so, try this insn, that insn,
846 and its predecessor if it sets CC0. */
847 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
848 if (GET_CODE (XEXP (links, 0)) == INSN
849 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
850 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
851 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
852 && GET_CODE (prev) == INSN
853 && sets_cc0_p (PATTERN (prev))
854 && (next = try_combine (insn, XEXP (links, 0),
855 prev, &new_direct_jump_p)) != 0)
859 /* Try combining an insn with two different insns whose results it
861 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
862 for (nextlinks = XEXP (links, 1); nextlinks;
863 nextlinks = XEXP (nextlinks, 1))
864 if ((next = try_combine (insn, XEXP (links, 0),
866 &new_direct_jump_p)) != 0)
869 /* Try this insn with each REG_EQUAL note it links back to. */
870 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
873 rtx temp = XEXP (links, 0);
874 if ((set = single_set (temp)) != 0
875 && (note = find_reg_equal_equiv_note (temp)) != 0
876 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
877 /* Avoid using a register that may already been marked
878 dead by an earlier instruction. */
879 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
881 /* Temporarily replace the set's source with the
882 contents of the REG_EQUAL note. The insn will
883 be deleted or recognized by try_combine. */
884 rtx orig = SET_SRC (set);
885 SET_SRC (set) = XEXP (note, 0);
886 next = try_combine (insn, temp, NULL_RTX,
890 SET_SRC (set) = orig;
894 if (GET_CODE (insn) != NOTE)
895 record_dead_and_set_regs (insn);
904 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
905 BASIC_BLOCK (i)->flags |= BB_DIRTY);
906 new_direct_jump_p |= purge_all_dead_edges (0);
907 delete_noop_moves ();
909 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
910 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
911 | PROP_KILL_DEAD_CODE);
914 sbitmap_free (refresh_blocks);
915 free (uid_insn_cost);
920 struct undo *undo, *next;
921 for (undo = undobuf.frees; undo; undo = next)
929 total_attempts += combine_attempts;
930 total_merges += combine_merges;
931 total_extras += combine_extras;
932 total_successes += combine_successes;
934 nonzero_sign_valid = 0;
935 rtl_hooks = general_rtl_hooks;
937 /* Make recognizer allow volatile MEMs again. */
940 return new_direct_jump_p;
943 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
949 for (i = 0; i < combine_max_regno; i++)
950 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
953 /* Set up any promoted values for incoming argument registers. */
956 setup_incoming_promotions (void)
960 enum machine_mode mode;
962 rtx first = get_insns ();
964 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
966 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
967 /* Check whether this register can hold an incoming pointer
968 argument. FUNCTION_ARG_REGNO_P tests outgoing register
969 numbers, so translate if necessary due to register windows. */
970 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
971 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
974 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
977 gen_rtx_CLOBBER (mode, const0_rtx)));
982 /* Called via note_stores. If X is a pseudo that is narrower than
983 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
985 If we are setting only a portion of X and we can't figure out what
986 portion, assume all bits will be used since we don't know what will
989 Similarly, set how many bits of X are known to be copies of the sign bit
990 at all locations in the function. This is the smallest number implied
994 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
995 void *data ATTRIBUTE_UNUSED)
1000 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1001 /* If this register is undefined at the start of the file, we can't
1002 say what its contents were. */
1003 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
1004 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1006 if (set == 0 || GET_CODE (set) == CLOBBER)
1008 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1009 reg_stat[REGNO (x)].sign_bit_copies = 1;
1013 /* If this is a complex assignment, see if we can convert it into a
1014 simple assignment. */
1015 set = expand_field_assignment (set);
1017 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1018 set what we know about X. */
1020 if (SET_DEST (set) == x
1021 || (GET_CODE (SET_DEST (set)) == SUBREG
1022 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1023 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1024 && SUBREG_REG (SET_DEST (set)) == x))
1026 rtx src = SET_SRC (set);
1028 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1029 /* If X is narrower than a word and SRC is a non-negative
1030 constant that would appear negative in the mode of X,
1031 sign-extend it for use in reg_stat[].nonzero_bits because some
1032 machines (maybe most) will actually do the sign-extension
1033 and this is the conservative approach.
1035 ??? For 2.5, try to tighten up the MD files in this regard
1036 instead of this kludge. */
1038 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1039 && GET_CODE (src) == CONST_INT
1041 && 0 != (INTVAL (src)
1042 & ((HOST_WIDE_INT) 1
1043 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1044 src = GEN_INT (INTVAL (src)
1045 | ((HOST_WIDE_INT) (-1)
1046 << GET_MODE_BITSIZE (GET_MODE (x))));
1049 /* Don't call nonzero_bits if it cannot change anything. */
1050 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1051 reg_stat[REGNO (x)].nonzero_bits
1052 |= nonzero_bits (src, nonzero_bits_mode);
1053 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1054 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1055 || reg_stat[REGNO (x)].sign_bit_copies > num)
1056 reg_stat[REGNO (x)].sign_bit_copies = num;
1060 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1061 reg_stat[REGNO (x)].sign_bit_copies = 1;
1066 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1067 insns that were previously combined into I3 or that will be combined
1068 into the merger of INSN and I3.
1070 Return 0 if the combination is not allowed for any reason.
1072 If the combination is allowed, *PDEST will be set to the single
1073 destination of INSN and *PSRC to the single source, and this function
1077 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1078 rtx *pdest, rtx *psrc)
1081 rtx set = 0, src, dest;
1086 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1087 && next_active_insn (succ) == i3)
1088 : next_active_insn (insn) == i3);
1090 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1091 or a PARALLEL consisting of such a SET and CLOBBERs.
1093 If INSN has CLOBBER parallel parts, ignore them for our processing.
1094 By definition, these happen during the execution of the insn. When it
1095 is merged with another insn, all bets are off. If they are, in fact,
1096 needed and aren't also supplied in I3, they may be added by
1097 recog_for_combine. Otherwise, it won't match.
1099 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1102 Get the source and destination of INSN. If more than one, can't
1105 if (GET_CODE (PATTERN (insn)) == SET)
1106 set = PATTERN (insn);
1107 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1108 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1110 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1112 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1115 switch (GET_CODE (elt))
1117 /* This is important to combine floating point insns
1118 for the SH4 port. */
1120 /* Combining an isolated USE doesn't make sense.
1121 We depend here on combinable_i3pat to reject them. */
1122 /* The code below this loop only verifies that the inputs of
1123 the SET in INSN do not change. We call reg_set_between_p
1124 to verify that the REG in the USE does not change between
1126 If the USE in INSN was for a pseudo register, the matching
1127 insn pattern will likely match any register; combining this
1128 with any other USE would only be safe if we knew that the
1129 used registers have identical values, or if there was
1130 something to tell them apart, e.g. different modes. For
1131 now, we forgo such complicated tests and simply disallow
1132 combining of USES of pseudo registers with any other USE. */
1133 if (REG_P (XEXP (elt, 0))
1134 && GET_CODE (PATTERN (i3)) == PARALLEL)
1136 rtx i3pat = PATTERN (i3);
1137 int i = XVECLEN (i3pat, 0) - 1;
1138 unsigned int regno = REGNO (XEXP (elt, 0));
1142 rtx i3elt = XVECEXP (i3pat, 0, i);
1144 if (GET_CODE (i3elt) == USE
1145 && REG_P (XEXP (i3elt, 0))
1146 && (REGNO (XEXP (i3elt, 0)) == regno
1147 ? reg_set_between_p (XEXP (elt, 0),
1148 PREV_INSN (insn), i3)
1149 : regno >= FIRST_PSEUDO_REGISTER))
1156 /* We can ignore CLOBBERs. */
1161 /* Ignore SETs whose result isn't used but not those that
1162 have side-effects. */
1163 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1164 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1165 || INTVAL (XEXP (note, 0)) <= 0)
1166 && ! side_effects_p (elt))
1169 /* If we have already found a SET, this is a second one and
1170 so we cannot combine with this insn. */
1178 /* Anything else means we can't combine. */
1184 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1185 so don't do anything with it. */
1186 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1195 set = expand_field_assignment (set);
1196 src = SET_SRC (set), dest = SET_DEST (set);
1198 /* Don't eliminate a store in the stack pointer. */
1199 if (dest == stack_pointer_rtx
1200 /* Don't combine with an insn that sets a register to itself if it has
1201 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1202 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1203 /* Can't merge an ASM_OPERANDS. */
1204 || GET_CODE (src) == ASM_OPERANDS
1205 /* Can't merge a function call. */
1206 || GET_CODE (src) == CALL
1207 /* Don't eliminate a function call argument. */
1208 || (GET_CODE (i3) == CALL_INSN
1209 && (find_reg_fusage (i3, USE, dest)
1211 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1212 && global_regs[REGNO (dest)])))
1213 /* Don't substitute into an incremented register. */
1214 || FIND_REG_INC_NOTE (i3, dest)
1215 || (succ && FIND_REG_INC_NOTE (succ, dest))
1217 /* Don't combine the end of a libcall into anything. */
1218 /* ??? This gives worse code, and appears to be unnecessary, since no
1219 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1220 use REG_RETVAL notes for noconflict blocks, but other code here
1221 makes sure that those insns don't disappear. */
1222 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1224 /* Make sure that DEST is not used after SUCC but before I3. */
1225 || (succ && ! all_adjacent
1226 && reg_used_between_p (dest, succ, i3))
1227 /* Make sure that the value that is to be substituted for the register
1228 does not use any registers whose values alter in between. However,
1229 If the insns are adjacent, a use can't cross a set even though we
1230 think it might (this can happen for a sequence of insns each setting
1231 the same destination; last_set of that register might point to
1232 a NOTE). If INSN has a REG_EQUIV note, the register is always
1233 equivalent to the memory so the substitution is valid even if there
1234 are intervening stores. Also, don't move a volatile asm or
1235 UNSPEC_VOLATILE across any other insns. */
1238 || ! find_reg_note (insn, REG_EQUIV, src))
1239 && use_crosses_set_p (src, INSN_CUID (insn)))
1240 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1241 || GET_CODE (src) == UNSPEC_VOLATILE))
1242 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1243 better register allocation by not doing the combine. */
1244 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1245 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1246 /* Don't combine across a CALL_INSN, because that would possibly
1247 change whether the life span of some REGs crosses calls or not,
1248 and it is a pain to update that information.
1249 Exception: if source is a constant, moving it later can't hurt.
1250 Accept that special case, because it helps -fforce-addr a lot. */
1251 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1254 /* DEST must either be a REG or CC0. */
1257 /* If register alignment is being enforced for multi-word items in all
1258 cases except for parameters, it is possible to have a register copy
1259 insn referencing a hard register that is not allowed to contain the
1260 mode being copied and which would not be valid as an operand of most
1261 insns. Eliminate this problem by not combining with such an insn.
1263 Also, on some machines we don't want to extend the life of a hard
1267 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1268 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1269 /* Don't extend the life of a hard register unless it is
1270 user variable (if we have few registers) or it can't
1271 fit into the desired register (meaning something special
1273 Also avoid substituting a return register into I3, because
1274 reload can't handle a conflict with constraints of other
1276 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1277 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1280 else if (GET_CODE (dest) != CC0)
1284 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1285 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1286 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1288 /* Don't substitute for a register intended as a clobberable
1290 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1291 if (rtx_equal_p (reg, dest))
1294 /* If the clobber represents an earlyclobber operand, we must not
1295 substitute an expression containing the clobbered register.
1296 As we do not analyse the constraint strings here, we have to
1297 make the conservative assumption. However, if the register is
1298 a fixed hard reg, the clobber cannot represent any operand;
1299 we leave it up to the machine description to either accept or
1300 reject use-and-clobber patterns. */
1302 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1303 || !fixed_regs[REGNO (reg)])
1304 if (reg_overlap_mentioned_p (reg, src))
1308 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1309 or not), reject, unless nothing volatile comes between it and I3 */
1311 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1313 /* Make sure succ doesn't contain a volatile reference. */
1314 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1317 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1318 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1322 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1323 to be an explicit register variable, and was chosen for a reason. */
1325 if (GET_CODE (src) == ASM_OPERANDS
1326 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1329 /* If there are any volatile insns between INSN and I3, reject, because
1330 they might affect machine state. */
1332 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1333 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1336 /* If INSN or I2 contains an autoincrement or autodecrement,
1337 make sure that register is not used between there and I3,
1338 and not already used in I3 either.
1339 Also insist that I3 not be a jump; if it were one
1340 and the incremented register were spilled, we would lose. */
1343 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1344 if (REG_NOTE_KIND (link) == REG_INC
1345 && (GET_CODE (i3) == JUMP_INSN
1346 || reg_used_between_p (XEXP (link, 0), insn, i3)
1347 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1352 /* Don't combine an insn that follows a CC0-setting insn.
1353 An insn that uses CC0 must not be separated from the one that sets it.
1354 We do, however, allow I2 to follow a CC0-setting insn if that insn
1355 is passed as I1; in that case it will be deleted also.
1356 We also allow combining in this case if all the insns are adjacent
1357 because that would leave the two CC0 insns adjacent as well.
1358 It would be more logical to test whether CC0 occurs inside I1 or I2,
1359 but that would be much slower, and this ought to be equivalent. */
1361 p = prev_nonnote_insn (insn);
1362 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1367 /* If we get here, we have passed all the tests and the combination is
1376 /* LOC is the location within I3 that contains its pattern or the component
1377 of a PARALLEL of the pattern. We validate that it is valid for combining.
1379 One problem is if I3 modifies its output, as opposed to replacing it
1380 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1381 so would produce an insn that is not equivalent to the original insns.
1385 (set (reg:DI 101) (reg:DI 100))
1386 (set (subreg:SI (reg:DI 101) 0) <foo>)
1388 This is NOT equivalent to:
1390 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1391 (set (reg:DI 101) (reg:DI 100))])
1393 Not only does this modify 100 (in which case it might still be valid
1394 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1396 We can also run into a problem if I2 sets a register that I1
1397 uses and I1 gets directly substituted into I3 (not via I2). In that
1398 case, we would be getting the wrong value of I2DEST into I3, so we
1399 must reject the combination. This case occurs when I2 and I1 both
1400 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1401 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1402 of a SET must prevent combination from occurring.
1404 Before doing the above check, we first try to expand a field assignment
1405 into a set of logical operations.
1407 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1408 we place a register that is both set and used within I3. If more than one
1409 such register is detected, we fail.
1411 Return 1 if the combination is valid, zero otherwise. */
1414 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1415 int i1_not_in_src, rtx *pi3dest_killed)
1419 if (GET_CODE (x) == SET)
1422 rtx dest = SET_DEST (set);
1423 rtx src = SET_SRC (set);
1424 rtx inner_dest = dest;
1426 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1427 || GET_CODE (inner_dest) == SUBREG
1428 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1429 inner_dest = XEXP (inner_dest, 0);
1431 /* Check for the case where I3 modifies its output, as discussed
1432 above. We don't want to prevent pseudos from being combined
1433 into the address of a MEM, so only prevent the combination if
1434 i1 or i2 set the same MEM. */
1435 if ((inner_dest != dest &&
1436 (!MEM_P (inner_dest)
1437 || rtx_equal_p (i2dest, inner_dest)
1438 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1439 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1440 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1442 /* This is the same test done in can_combine_p except we can't test
1443 all_adjacent; we don't have to, since this instruction will stay
1444 in place, thus we are not considering increasing the lifetime of
1447 Also, if this insn sets a function argument, combining it with
1448 something that might need a spill could clobber a previous
1449 function argument; the all_adjacent test in can_combine_p also
1450 checks this; here, we do a more specific test for this case. */
1452 || (REG_P (inner_dest)
1453 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1454 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1455 GET_MODE (inner_dest))))
1456 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1459 /* If DEST is used in I3, it is being killed in this insn,
1460 so record that for later.
1461 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1462 STACK_POINTER_REGNUM, since these are always considered to be
1463 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1464 if (pi3dest_killed && REG_P (dest)
1465 && reg_referenced_p (dest, PATTERN (i3))
1466 && REGNO (dest) != FRAME_POINTER_REGNUM
1467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1468 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1470 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1471 && (REGNO (dest) != ARG_POINTER_REGNUM
1472 || ! fixed_regs [REGNO (dest)])
1474 && REGNO (dest) != STACK_POINTER_REGNUM)
1476 if (*pi3dest_killed)
1479 *pi3dest_killed = dest;
1483 else if (GET_CODE (x) == PARALLEL)
1487 for (i = 0; i < XVECLEN (x, 0); i++)
1488 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1489 i1_not_in_src, pi3dest_killed))
1496 /* Return 1 if X is an arithmetic expression that contains a multiplication
1497 and division. We don't count multiplications by powers of two here. */
1500 contains_muldiv (rtx x)
1502 switch (GET_CODE (x))
1504 case MOD: case DIV: case UMOD: case UDIV:
1508 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1509 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1512 return contains_muldiv (XEXP (x, 0))
1513 || contains_muldiv (XEXP (x, 1));
1516 return contains_muldiv (XEXP (x, 0));
1522 /* Determine whether INSN can be used in a combination. Return nonzero if
1523 not. This is used in try_combine to detect early some cases where we
1524 can't perform combinations. */
1527 cant_combine_insn_p (rtx insn)
1532 /* If this isn't really an insn, we can't do anything.
1533 This can occur when flow deletes an insn that it has merged into an
1534 auto-increment address. */
1535 if (! INSN_P (insn))
1538 /* Never combine loads and stores involving hard regs that are likely
1539 to be spilled. The register allocator can usually handle such
1540 reg-reg moves by tying. If we allow the combiner to make
1541 substitutions of likely-spilled regs, we may abort in reload.
1542 As an exception, we allow combinations involving fixed regs; these are
1543 not available to the register allocator so there's no risk involved. */
1545 set = single_set (insn);
1548 src = SET_SRC (set);
1549 dest = SET_DEST (set);
1550 if (GET_CODE (src) == SUBREG)
1551 src = SUBREG_REG (src);
1552 if (GET_CODE (dest) == SUBREG)
1553 dest = SUBREG_REG (dest);
1554 if (REG_P (src) && REG_P (dest)
1555 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1556 && ! fixed_regs[REGNO (src)]
1557 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1558 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1559 && ! fixed_regs[REGNO (dest)]
1560 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1566 /* Adjust INSN after we made a change to its destination.
1568 Changing the destination can invalidate notes that say something about
1569 the results of the insn and a LOG_LINK pointing to the insn. */
1572 adjust_for_new_dest (rtx insn)
1576 /* For notes, be conservative and simply remove them. */
1577 loc = ®_NOTES (insn);
1580 enum reg_note kind = REG_NOTE_KIND (*loc);
1581 if (kind == REG_EQUAL || kind == REG_EQUIV)
1582 *loc = XEXP (*loc, 1);
1584 loc = &XEXP (*loc, 1);
1587 /* The new insn will have a destination that was previously the destination
1588 of an insn just above it. Call distribute_links to make a LOG_LINK from
1589 the next use of that destination. */
1590 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1593 /* Try to combine the insns I1 and I2 into I3.
1594 Here I1 and I2 appear earlier than I3.
1595 I1 can be zero; then we combine just I2 into I3.
1597 If we are combining three insns and the resulting insn is not recognized,
1598 try splitting it into two insns. If that happens, I2 and I3 are retained
1599 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1602 Return 0 if the combination does not work. Then nothing is changed.
1603 If we did the combination, return the insn at which combine should
1606 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1607 new direct jump instruction. */
1610 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1612 /* New patterns for I3 and I2, respectively. */
1613 rtx newpat, newi2pat = 0;
1614 int substed_i2 = 0, substed_i1 = 0;
1615 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1616 int added_sets_1, added_sets_2;
1617 /* Total number of SETs to put into I3. */
1619 /* Nonzero if I2's body now appears in I3. */
1621 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1622 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1623 /* Contains I3 if the destination of I3 is used in its source, which means
1624 that the old life of I3 is being killed. If that usage is placed into
1625 I2 and not in I3, a REG_DEAD note must be made. */
1626 rtx i3dest_killed = 0;
1627 /* SET_DEST and SET_SRC of I2 and I1. */
1628 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1629 /* PATTERN (I2), or a copy of it in certain cases. */
1631 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1632 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1633 int i1_feeds_i3 = 0;
1634 /* Notes that must be added to REG_NOTES in I3 and I2. */
1635 rtx new_i3_notes, new_i2_notes;
1636 /* Notes that we substituted I3 into I2 instead of the normal case. */
1637 int i3_subst_into_i2 = 0;
1638 /* Notes that I1, I2 or I3 is a MULT operation. */
1646 /* Exit early if one of the insns involved can't be used for
1648 if (cant_combine_insn_p (i3)
1649 || cant_combine_insn_p (i2)
1650 || (i1 && cant_combine_insn_p (i1))
1651 /* We also can't do anything if I3 has a
1652 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1655 /* ??? This gives worse code, and appears to be unnecessary, since no
1656 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1657 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1663 undobuf.other_insn = 0;
1665 /* Reset the hard register usage information. */
1666 CLEAR_HARD_REG_SET (newpat_used_regs);
1668 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1669 code below, set I1 to be the earlier of the two insns. */
1670 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1671 temp = i1, i1 = i2, i2 = temp;
1673 added_links_insn = 0;
1675 /* First check for one important special-case that the code below will
1676 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1677 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1678 we may be able to replace that destination with the destination of I3.
1679 This occurs in the common code where we compute both a quotient and
1680 remainder into a structure, in which case we want to do the computation
1681 directly into the structure to avoid register-register copies.
1683 Note that this case handles both multiple sets in I2 and also
1684 cases where I2 has a number of CLOBBER or PARALLELs.
1686 We make very conservative checks below and only try to handle the
1687 most common cases of this. For example, we only handle the case
1688 where I2 and I3 are adjacent to avoid making difficult register
1691 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1692 && REG_P (SET_SRC (PATTERN (i3)))
1693 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1694 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1695 && GET_CODE (PATTERN (i2)) == PARALLEL
1696 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1697 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1698 below would need to check what is inside (and reg_overlap_mentioned_p
1699 doesn't support those codes anyway). Don't allow those destinations;
1700 the resulting insn isn't likely to be recognized anyway. */
1701 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1702 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1703 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1704 SET_DEST (PATTERN (i3)))
1705 && next_real_insn (i2) == i3)
1707 rtx p2 = PATTERN (i2);
1709 /* Make sure that the destination of I3,
1710 which we are going to substitute into one output of I2,
1711 is not used within another output of I2. We must avoid making this:
1712 (parallel [(set (mem (reg 69)) ...)
1713 (set (reg 69) ...)])
1714 which is not well-defined as to order of actions.
1715 (Besides, reload can't handle output reloads for this.)
1717 The problem can also happen if the dest of I3 is a memory ref,
1718 if another dest in I2 is an indirect memory ref. */
1719 for (i = 0; i < XVECLEN (p2, 0); i++)
1720 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1721 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1722 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1723 SET_DEST (XVECEXP (p2, 0, i))))
1726 if (i == XVECLEN (p2, 0))
1727 for (i = 0; i < XVECLEN (p2, 0); i++)
1728 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1729 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1730 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1735 subst_low_cuid = INSN_CUID (i2);
1737 added_sets_2 = added_sets_1 = 0;
1738 i2dest = SET_SRC (PATTERN (i3));
1740 /* Replace the dest in I2 with our dest and make the resulting
1741 insn the new pattern for I3. Then skip to where we
1742 validate the pattern. Everything was set up above. */
1743 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1744 SET_DEST (PATTERN (i3)));
1747 i3_subst_into_i2 = 1;
1748 goto validate_replacement;
1752 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1753 one of those words to another constant, merge them by making a new
1756 && (temp = single_set (i2)) != 0
1757 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1758 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1759 && REG_P (SET_DEST (temp))
1760 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1761 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1762 && GET_CODE (PATTERN (i3)) == SET
1763 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1764 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1765 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1766 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1767 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1769 HOST_WIDE_INT lo, hi;
1771 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1772 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1775 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1776 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1779 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1781 /* We don't handle the case of the target word being wider
1782 than a host wide int. */
1783 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1786 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1787 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1788 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1790 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1791 hi = INTVAL (SET_SRC (PATTERN (i3)));
1792 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1794 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1795 >> (HOST_BITS_PER_WIDE_INT - 1));
1797 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1798 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1799 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1800 (INTVAL (SET_SRC (PATTERN (i3)))));
1802 hi = lo < 0 ? -1 : 0;
1805 /* We don't handle the case of the higher word not fitting
1806 entirely in either hi or lo. */
1811 subst_low_cuid = INSN_CUID (i2);
1812 added_sets_2 = added_sets_1 = 0;
1813 i2dest = SET_DEST (temp);
1815 SUBST (SET_SRC (temp),
1816 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1818 newpat = PATTERN (i2);
1819 goto validate_replacement;
1823 /* If we have no I1 and I2 looks like:
1824 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1826 make up a dummy I1 that is
1829 (set (reg:CC X) (compare:CC Y (const_int 0)))
1831 (We can ignore any trailing CLOBBERs.)
1833 This undoes a previous combination and allows us to match a branch-and-
1836 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1837 && XVECLEN (PATTERN (i2), 0) >= 2
1838 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1839 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1841 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1842 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1843 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1844 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1845 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1846 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1848 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1849 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1854 /* We make I1 with the same INSN_UID as I2. This gives it
1855 the same INSN_CUID for value tracking. Our fake I1 will
1856 never appear in the insn stream so giving it the same INSN_UID
1857 as I2 will not cause a problem. */
1859 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1860 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1861 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1864 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1865 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1866 SET_DEST (PATTERN (i1)));
1871 /* Verify that I2 and I1 are valid for combining. */
1872 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1873 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1879 /* Record whether I2DEST is used in I2SRC and similarly for the other
1880 cases. Knowing this will help in register status updating below. */
1881 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1882 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1883 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1885 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1887 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1889 /* Ensure that I3's pattern can be the destination of combines. */
1890 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1891 i1 && i2dest_in_i1src && i1_feeds_i3,
1898 /* See if any of the insns is a MULT operation. Unless one is, we will
1899 reject a combination that is, since it must be slower. Be conservative
1901 if (GET_CODE (i2src) == MULT
1902 || (i1 != 0 && GET_CODE (i1src) == MULT)
1903 || (GET_CODE (PATTERN (i3)) == SET
1904 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1907 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1908 We used to do this EXCEPT in one case: I3 has a post-inc in an
1909 output operand. However, that exception can give rise to insns like
1911 which is a famous insn on the PDP-11 where the value of r3 used as the
1912 source was model-dependent. Avoid this sort of thing. */
1915 if (!(GET_CODE (PATTERN (i3)) == SET
1916 && REG_P (SET_SRC (PATTERN (i3)))
1917 && MEM_P (SET_DEST (PATTERN (i3)))
1918 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1919 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1920 /* It's not the exception. */
1923 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1924 if (REG_NOTE_KIND (link) == REG_INC
1925 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1927 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1934 /* See if the SETs in I1 or I2 need to be kept around in the merged
1935 instruction: whenever the value set there is still needed past I3.
1936 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1938 For the SET in I1, we have two cases: If I1 and I2 independently
1939 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1940 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1941 in I1 needs to be kept around unless I1DEST dies or is set in either
1942 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1943 I1DEST. If so, we know I1 feeds into I2. */
1945 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1948 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1949 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1951 /* If the set in I2 needs to be kept around, we must make a copy of
1952 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1953 PATTERN (I2), we are only substituting for the original I1DEST, not into
1954 an already-substituted copy. This also prevents making self-referential
1955 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1958 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1959 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1963 i2pat = copy_rtx (i2pat);
1967 /* Substitute in the latest insn for the regs set by the earlier ones. */
1969 maxreg = max_reg_num ();
1973 /* It is possible that the source of I2 or I1 may be performing an
1974 unneeded operation, such as a ZERO_EXTEND of something that is known
1975 to have the high part zero. Handle that case by letting subst look at
1976 the innermost one of them.
1978 Another way to do this would be to have a function that tries to
1979 simplify a single insn instead of merging two or more insns. We don't
1980 do this because of the potential of infinite loops and because
1981 of the potential extra memory required. However, doing it the way
1982 we are is a bit of a kludge and doesn't catch all cases.
1984 But only do this if -fexpensive-optimizations since it slows things down
1985 and doesn't usually win. */
1987 if (flag_expensive_optimizations)
1989 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1992 subst_low_cuid = INSN_CUID (i1);
1993 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1997 subst_low_cuid = INSN_CUID (i2);
1998 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2003 /* Many machines that don't use CC0 have insns that can both perform an
2004 arithmetic operation and set the condition code. These operations will
2005 be represented as a PARALLEL with the first element of the vector
2006 being a COMPARE of an arithmetic operation with the constant zero.
2007 The second element of the vector will set some pseudo to the result
2008 of the same arithmetic operation. If we simplify the COMPARE, we won't
2009 match such a pattern and so will generate an extra insn. Here we test
2010 for this case, where both the comparison and the operation result are
2011 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2012 I2SRC. Later we will make the PARALLEL that contains I2. */
2014 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2015 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2016 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2017 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2019 #ifdef SELECT_CC_MODE
2021 enum machine_mode compare_mode;
2024 newpat = PATTERN (i3);
2025 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2029 #ifdef SELECT_CC_MODE
2030 /* See if a COMPARE with the operand we substituted in should be done
2031 with the mode that is currently being used. If not, do the same
2032 processing we do in `subst' for a SET; namely, if the destination
2033 is used only once, try to replace it with a register of the proper
2034 mode and also replace the COMPARE. */
2035 if (undobuf.other_insn == 0
2036 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2037 &undobuf.other_insn))
2038 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2040 != GET_MODE (SET_DEST (newpat))))
2042 unsigned int regno = REGNO (SET_DEST (newpat));
2043 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2045 if (regno < FIRST_PSEUDO_REGISTER
2046 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2047 && ! REG_USERVAR_P (SET_DEST (newpat))))
2049 if (regno >= FIRST_PSEUDO_REGISTER)
2050 SUBST (regno_reg_rtx[regno], new_dest);
2052 SUBST (SET_DEST (newpat), new_dest);
2053 SUBST (XEXP (*cc_use, 0), new_dest);
2054 SUBST (SET_SRC (newpat),
2055 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2058 undobuf.other_insn = 0;
2065 n_occurrences = 0; /* `subst' counts here */
2067 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2068 need to make a unique copy of I2SRC each time we substitute it
2069 to avoid self-referential rtl. */
2071 subst_low_cuid = INSN_CUID (i2);
2072 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2073 ! i1_feeds_i3 && i1dest_in_i1src);
2076 /* Record whether i2's body now appears within i3's body. */
2077 i2_is_used = n_occurrences;
2080 /* If we already got a failure, don't try to do more. Otherwise,
2081 try to substitute in I1 if we have it. */
2083 if (i1 && GET_CODE (newpat) != CLOBBER)
2085 /* Before we can do this substitution, we must redo the test done
2086 above (see detailed comments there) that ensures that I1DEST
2087 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2089 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2097 subst_low_cuid = INSN_CUID (i1);
2098 newpat = subst (newpat, i1dest, i1src, 0, 0);
2102 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2103 to count all the ways that I2SRC and I1SRC can be used. */
2104 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2105 && i2_is_used + added_sets_2 > 1)
2106 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2107 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2109 /* Fail if we tried to make a new register (we used to abort, but there's
2110 really no reason to). */
2111 || max_reg_num () != maxreg
2112 /* Fail if we couldn't do something and have a CLOBBER. */
2113 || GET_CODE (newpat) == CLOBBER
2114 /* Fail if this new pattern is a MULT and we didn't have one before
2115 at the outer level. */
2116 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2123 /* If the actions of the earlier insns must be kept
2124 in addition to substituting them into the latest one,
2125 we must make a new PARALLEL for the latest insn
2126 to hold additional the SETs. */
2128 if (added_sets_1 || added_sets_2)
2132 if (GET_CODE (newpat) == PARALLEL)
2134 rtvec old = XVEC (newpat, 0);
2135 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2136 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2137 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2138 sizeof (old->elem[0]) * old->num_elem);
2143 total_sets = 1 + added_sets_1 + added_sets_2;
2144 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2145 XVECEXP (newpat, 0, 0) = old;
2149 XVECEXP (newpat, 0, --total_sets)
2150 = (GET_CODE (PATTERN (i1)) == PARALLEL
2151 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2155 /* If there is no I1, use I2's body as is. We used to also not do
2156 the subst call below if I2 was substituted into I3,
2157 but that could lose a simplification. */
2159 XVECEXP (newpat, 0, --total_sets) = i2pat;
2161 /* See comment where i2pat is assigned. */
2162 XVECEXP (newpat, 0, --total_sets)
2163 = subst (i2pat, i1dest, i1src, 0, 0);
2167 /* We come here when we are replacing a destination in I2 with the
2168 destination of I3. */
2169 validate_replacement:
2171 /* Note which hard regs this insn has as inputs. */
2172 mark_used_regs_combine (newpat);
2174 /* Is the result of combination a valid instruction? */
2175 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2177 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2178 the second SET's destination is a register that is unused and isn't
2179 marked as an instruction that might trap in an EH region. In that case,
2180 we just need the first SET. This can occur when simplifying a divmod
2181 insn. We *must* test for this case here because the code below that
2182 splits two independent SETs doesn't handle this case correctly when it
2183 updates the register status.
2185 It's pointless doing this if we originally had two sets, one from
2186 i3, and one from i2. Combining then splitting the parallel results
2187 in the original i2 again plus an invalid insn (which we delete).
2188 The net effect is only to move instructions around, which makes
2189 debug info less accurate.
2191 Also check the case where the first SET's destination is unused.
2192 That would not cause incorrect code, but does cause an unneeded
2195 if (insn_code_number < 0
2196 && !(added_sets_2 && i1 == 0)
2197 && GET_CODE (newpat) == PARALLEL
2198 && XVECLEN (newpat, 0) == 2
2199 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2200 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2201 && asm_noperands (newpat) < 0)
2203 rtx set0 = XVECEXP (newpat, 0, 0);
2204 rtx set1 = XVECEXP (newpat, 0, 1);
2207 if (((REG_P (SET_DEST (set1))
2208 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2209 || (GET_CODE (SET_DEST (set1)) == SUBREG
2210 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2211 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2212 || INTVAL (XEXP (note, 0)) <= 0)
2213 && ! side_effects_p (SET_SRC (set1)))
2216 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2219 else if (((REG_P (SET_DEST (set0))
2220 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2221 || (GET_CODE (SET_DEST (set0)) == SUBREG
2222 && find_reg_note (i3, REG_UNUSED,
2223 SUBREG_REG (SET_DEST (set0)))))
2224 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2225 || INTVAL (XEXP (note, 0)) <= 0)
2226 && ! side_effects_p (SET_SRC (set0)))
2229 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2231 if (insn_code_number >= 0)
2233 /* If we will be able to accept this, we have made a
2234 change to the destination of I3. This requires us to
2235 do a few adjustments. */
2237 PATTERN (i3) = newpat;
2238 adjust_for_new_dest (i3);
2243 /* If we were combining three insns and the result is a simple SET
2244 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2245 insns. There are two ways to do this. It can be split using a
2246 machine-specific method (like when you have an addition of a large
2247 constant) or by combine in the function find_split_point. */
2249 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2250 && asm_noperands (newpat) < 0)
2252 rtx m_split, *split;
2253 rtx ni2dest = i2dest;
2255 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2256 use I2DEST as a scratch register will help. In the latter case,
2257 convert I2DEST to the mode of the source of NEWPAT if we can. */
2259 m_split = split_insns (newpat, i3);
2261 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2262 inputs of NEWPAT. */
2264 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2265 possible to try that as a scratch reg. This would require adding
2266 more code to make it work though. */
2268 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2270 /* If I2DEST is a hard register or the only use of a pseudo,
2271 we can change its mode. */
2272 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2273 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2275 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2276 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2277 && ! REG_USERVAR_P (i2dest))))
2278 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2281 m_split = split_insns (gen_rtx_PARALLEL
2283 gen_rtvec (2, newpat,
2284 gen_rtx_CLOBBER (VOIDmode,
2287 /* If the split with the mode-changed register didn't work, try
2288 the original register. */
2289 if (! m_split && ni2dest != i2dest)
2292 m_split = split_insns (gen_rtx_PARALLEL
2294 gen_rtvec (2, newpat,
2295 gen_rtx_CLOBBER (VOIDmode,
2301 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2303 m_split = PATTERN (m_split);
2304 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2305 if (insn_code_number >= 0)
2308 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2309 && (next_real_insn (i2) == i3
2310 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2313 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2314 newi2pat = PATTERN (m_split);
2316 i3set = single_set (NEXT_INSN (m_split));
2317 i2set = single_set (m_split);
2319 /* In case we changed the mode of I2DEST, replace it in the
2320 pseudo-register table here. We can't do it above in case this
2321 code doesn't get executed and we do a split the other way. */
2323 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2324 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2326 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2328 /* If I2 or I3 has multiple SETs, we won't know how to track
2329 register status, so don't use these insns. If I2's destination
2330 is used between I2 and I3, we also can't use these insns. */
2332 if (i2_code_number >= 0 && i2set && i3set
2333 && (next_real_insn (i2) == i3
2334 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2335 insn_code_number = recog_for_combine (&newi3pat, i3,
2337 if (insn_code_number >= 0)
2340 /* It is possible that both insns now set the destination of I3.
2341 If so, we must show an extra use of it. */
2343 if (insn_code_number >= 0)
2345 rtx new_i3_dest = SET_DEST (i3set);
2346 rtx new_i2_dest = SET_DEST (i2set);
2348 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2349 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2350 || GET_CODE (new_i3_dest) == SUBREG)
2351 new_i3_dest = XEXP (new_i3_dest, 0);
2353 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2354 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2355 || GET_CODE (new_i2_dest) == SUBREG)
2356 new_i2_dest = XEXP (new_i2_dest, 0);
2358 if (REG_P (new_i3_dest)
2359 && REG_P (new_i2_dest)
2360 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2361 REG_N_SETS (REGNO (new_i2_dest))++;
2365 /* If we can split it and use I2DEST, go ahead and see if that
2366 helps things be recognized. Verify that none of the registers
2367 are set between I2 and I3. */
2368 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2372 /* We need I2DEST in the proper mode. If it is a hard register
2373 or the only use of a pseudo, we can change its mode. */
2374 && (GET_MODE (*split) == GET_MODE (i2dest)
2375 || GET_MODE (*split) == VOIDmode
2376 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2377 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2378 && ! REG_USERVAR_P (i2dest)))
2379 && (next_real_insn (i2) == i3
2380 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2381 /* We can't overwrite I2DEST if its value is still used by
2383 && ! reg_referenced_p (i2dest, newpat))
2385 rtx newdest = i2dest;
2386 enum rtx_code split_code = GET_CODE (*split);
2387 enum machine_mode split_mode = GET_MODE (*split);
2389 /* Get NEWDEST as a register in the proper mode. We have already
2390 validated that we can do this. */
2391 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2393 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2395 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2396 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2399 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2400 an ASHIFT. This can occur if it was inside a PLUS and hence
2401 appeared to be a memory address. This is a kludge. */
2402 if (split_code == MULT
2403 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2404 && INTVAL (XEXP (*split, 1)) > 0
2405 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2407 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2408 XEXP (*split, 0), GEN_INT (i)));
2409 /* Update split_code because we may not have a multiply
2411 split_code = GET_CODE (*split);
2414 #ifdef INSN_SCHEDULING
2415 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2416 be written as a ZERO_EXTEND. */
2417 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2419 #ifdef LOAD_EXTEND_OP
2420 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2421 what it really is. */
2422 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2424 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2425 SUBREG_REG (*split)));
2428 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2429 SUBREG_REG (*split)));
2433 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2434 SUBST (*split, newdest);
2435 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2437 /* If the split point was a MULT and we didn't have one before,
2438 don't use one now. */
2439 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2440 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2444 /* Check for a case where we loaded from memory in a narrow mode and
2445 then sign extended it, but we need both registers. In that case,
2446 we have a PARALLEL with both loads from the same memory location.
2447 We can split this into a load from memory followed by a register-register
2448 copy. This saves at least one insn, more if register allocation can
2451 We cannot do this if the destination of the first assignment is a
2452 condition code register or cc0. We eliminate this case by making sure
2453 the SET_DEST and SET_SRC have the same mode.
2455 We cannot do this if the destination of the second assignment is
2456 a register that we have already assumed is zero-extended. Similarly
2457 for a SUBREG of such a register. */
2459 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2460 && GET_CODE (newpat) == PARALLEL
2461 && XVECLEN (newpat, 0) == 2
2462 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2463 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2464 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2465 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2466 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2467 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2468 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2469 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2471 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2472 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2473 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2475 && reg_stat[REGNO (temp)].nonzero_bits != 0
2476 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2477 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2478 && (reg_stat[REGNO (temp)].nonzero_bits
2479 != GET_MODE_MASK (word_mode))))
2480 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2481 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2483 && reg_stat[REGNO (temp)].nonzero_bits != 0
2484 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2485 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2486 && (reg_stat[REGNO (temp)].nonzero_bits
2487 != GET_MODE_MASK (word_mode)))))
2488 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2489 SET_SRC (XVECEXP (newpat, 0, 1)))
2490 && ! find_reg_note (i3, REG_UNUSED,
2491 SET_DEST (XVECEXP (newpat, 0, 0))))
2495 newi2pat = XVECEXP (newpat, 0, 0);
2496 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2497 newpat = XVECEXP (newpat, 0, 1);
2498 SUBST (SET_SRC (newpat),
2499 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2500 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2502 if (i2_code_number >= 0)
2503 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2505 if (insn_code_number >= 0)
2510 /* If we will be able to accept this, we have made a change to the
2511 destination of I3. This requires us to do a few adjustments. */
2512 PATTERN (i3) = newpat;
2513 adjust_for_new_dest (i3);
2515 /* I3 now uses what used to be its destination and which is
2516 now I2's destination. That means we need a LOG_LINK from
2517 I3 to I2. But we used to have one, so we still will.
2519 However, some later insn might be using I2's dest and have
2520 a LOG_LINK pointing at I3. We must remove this link.
2521 The simplest way to remove the link is to point it at I1,
2522 which we know will be a NOTE. */
2524 for (insn = NEXT_INSN (i3);
2525 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2526 || insn != BB_HEAD (this_basic_block->next_bb));
2527 insn = NEXT_INSN (insn))
2529 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2531 for (link = LOG_LINKS (insn); link;
2532 link = XEXP (link, 1))
2533 if (XEXP (link, 0) == i3)
2534 XEXP (link, 0) = i1;
2542 /* Similarly, check for a case where we have a PARALLEL of two independent
2543 SETs but we started with three insns. In this case, we can do the sets
2544 as two separate insns. This case occurs when some SET allows two
2545 other insns to combine, but the destination of that SET is still live. */
2547 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2548 && GET_CODE (newpat) == PARALLEL
2549 && XVECLEN (newpat, 0) == 2
2550 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2551 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2552 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2553 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2554 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2555 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2556 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2558 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2559 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2560 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2561 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2562 XVECEXP (newpat, 0, 0))
2563 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2564 XVECEXP (newpat, 0, 1))
2565 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2566 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2568 /* Normally, it doesn't matter which of the two is done first,
2569 but it does if one references cc0. In that case, it has to
2572 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2574 newi2pat = XVECEXP (newpat, 0, 0);
2575 newpat = XVECEXP (newpat, 0, 1);
2580 newi2pat = XVECEXP (newpat, 0, 1);
2581 newpat = XVECEXP (newpat, 0, 0);
2584 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2586 if (i2_code_number >= 0)
2587 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2590 /* If it still isn't recognized, fail and change things back the way they
2592 if ((insn_code_number < 0
2593 /* Is the result a reasonable ASM_OPERANDS? */
2594 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2600 /* If we had to change another insn, make sure it is valid also. */
2601 if (undobuf.other_insn)
2603 rtx other_pat = PATTERN (undobuf.other_insn);
2604 rtx new_other_notes;
2607 CLEAR_HARD_REG_SET (newpat_used_regs);
2609 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2612 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2618 PATTERN (undobuf.other_insn) = other_pat;
2620 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2621 are still valid. Then add any non-duplicate notes added by
2622 recog_for_combine. */
2623 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2625 next = XEXP (note, 1);
2627 if (REG_NOTE_KIND (note) == REG_UNUSED
2628 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2630 if (REG_P (XEXP (note, 0)))
2631 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2633 remove_note (undobuf.other_insn, note);
2637 for (note = new_other_notes; note; note = XEXP (note, 1))
2638 if (REG_P (XEXP (note, 0)))
2639 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2641 distribute_notes (new_other_notes, undobuf.other_insn,
2642 undobuf.other_insn, NULL_RTX);
2645 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2646 they are adjacent to each other or not. */
2648 rtx p = prev_nonnote_insn (i3);
2649 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2650 && sets_cc0_p (newi2pat))
2658 /* Only allow this combination if combine_insn_costs reports that the
2659 replacement instructions are cheaper than the originals. */
2660 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2666 /* We now know that we can do this combination. Merge the insns and
2667 update the status of registers and LOG_LINKS. */
2670 rtx i3notes, i2notes, i1notes = 0;
2671 rtx i3links, i2links, i1links = 0;
2675 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2677 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2678 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2680 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2682 /* Ensure that we do not have something that should not be shared but
2683 occurs multiple times in the new insns. Check this by first
2684 resetting all the `used' flags and then copying anything is shared. */
2686 reset_used_flags (i3notes);
2687 reset_used_flags (i2notes);
2688 reset_used_flags (i1notes);
2689 reset_used_flags (newpat);
2690 reset_used_flags (newi2pat);
2691 if (undobuf.other_insn)
2692 reset_used_flags (PATTERN (undobuf.other_insn));
2694 i3notes = copy_rtx_if_shared (i3notes);
2695 i2notes = copy_rtx_if_shared (i2notes);
2696 i1notes = copy_rtx_if_shared (i1notes);
2697 newpat = copy_rtx_if_shared (newpat);
2698 newi2pat = copy_rtx_if_shared (newi2pat);
2699 if (undobuf.other_insn)
2700 reset_used_flags (PATTERN (undobuf.other_insn));
2702 INSN_CODE (i3) = insn_code_number;
2703 PATTERN (i3) = newpat;
2705 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2707 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2709 reset_used_flags (call_usage);
2710 call_usage = copy_rtx (call_usage);
2713 replace_rtx (call_usage, i2dest, i2src);
2716 replace_rtx (call_usage, i1dest, i1src);
2718 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2721 if (undobuf.other_insn)
2722 INSN_CODE (undobuf.other_insn) = other_code_number;
2724 /* We had one special case above where I2 had more than one set and
2725 we replaced a destination of one of those sets with the destination
2726 of I3. In that case, we have to update LOG_LINKS of insns later
2727 in this basic block. Note that this (expensive) case is rare.
2729 Also, in this case, we must pretend that all REG_NOTEs for I2
2730 actually came from I3, so that REG_UNUSED notes from I2 will be
2731 properly handled. */
2733 if (i3_subst_into_i2)
2735 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2736 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2737 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2738 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2739 && ! find_reg_note (i2, REG_UNUSED,
2740 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2741 for (temp = NEXT_INSN (i2);
2742 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2743 || BB_HEAD (this_basic_block) != temp);
2744 temp = NEXT_INSN (temp))
2745 if (temp != i3 && INSN_P (temp))
2746 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2747 if (XEXP (link, 0) == i2)
2748 XEXP (link, 0) = i3;
2753 while (XEXP (link, 1))
2754 link = XEXP (link, 1);
2755 XEXP (link, 1) = i2notes;
2769 INSN_CODE (i2) = i2_code_number;
2770 PATTERN (i2) = newi2pat;
2773 SET_INSN_DELETED (i2);
2779 SET_INSN_DELETED (i1);
2782 /* Get death notes for everything that is now used in either I3 or
2783 I2 and used to die in a previous insn. If we built two new
2784 patterns, move from I1 to I2 then I2 to I3 so that we get the
2785 proper movement on registers that I2 modifies. */
2789 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2790 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2793 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2796 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2798 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2800 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2802 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2804 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2806 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2807 know these are REG_UNUSED and want them to go to the desired insn,
2808 so we always pass it as i3. We have not counted the notes in
2809 reg_n_deaths yet, so we need to do so now. */
2811 if (newi2pat && new_i2_notes)
2813 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2814 if (REG_P (XEXP (temp, 0)))
2815 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2817 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2822 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2823 if (REG_P (XEXP (temp, 0)))
2824 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2826 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2829 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2830 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2831 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2832 in that case, it might delete I2. Similarly for I2 and I1.
2833 Show an additional death due to the REG_DEAD note we make here. If
2834 we discard it in distribute_notes, we will decrement it again. */
2838 if (REG_P (i3dest_killed))
2839 REG_N_DEATHS (REGNO (i3dest_killed))++;
2841 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2842 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2844 NULL_RTX, i2, NULL_RTX);
2846 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2848 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2851 if (i2dest_in_i2src)
2854 REG_N_DEATHS (REGNO (i2dest))++;
2856 if (newi2pat && reg_set_p (i2dest, newi2pat))
2857 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2858 NULL_RTX, i2, NULL_RTX);
2860 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2861 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2864 if (i1dest_in_i1src)
2867 REG_N_DEATHS (REGNO (i1dest))++;
2869 if (newi2pat && reg_set_p (i1dest, newi2pat))
2870 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2871 NULL_RTX, i2, NULL_RTX);
2873 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2874 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2877 distribute_links (i3links);
2878 distribute_links (i2links);
2879 distribute_links (i1links);
2884 rtx i2_insn = 0, i2_val = 0, set;
2886 /* The insn that used to set this register doesn't exist, and
2887 this life of the register may not exist either. See if one of
2888 I3's links points to an insn that sets I2DEST. If it does,
2889 that is now the last known value for I2DEST. If we don't update
2890 this and I2 set the register to a value that depended on its old
2891 contents, we will get confused. If this insn is used, thing
2892 will be set correctly in combine_instructions. */
2894 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2895 if ((set = single_set (XEXP (link, 0))) != 0
2896 && rtx_equal_p (i2dest, SET_DEST (set)))
2897 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2899 record_value_for_reg (i2dest, i2_insn, i2_val);
2901 /* If the reg formerly set in I2 died only once and that was in I3,
2902 zero its use count so it won't make `reload' do any work. */
2904 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2905 && ! i2dest_in_i2src)
2907 regno = REGNO (i2dest);
2908 REG_N_SETS (regno)--;
2912 if (i1 && REG_P (i1dest))
2915 rtx i1_insn = 0, i1_val = 0, set;
2917 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2918 if ((set = single_set (XEXP (link, 0))) != 0
2919 && rtx_equal_p (i1dest, SET_DEST (set)))
2920 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2922 record_value_for_reg (i1dest, i1_insn, i1_val);
2924 regno = REGNO (i1dest);
2925 if (! added_sets_1 && ! i1dest_in_i1src)
2926 REG_N_SETS (regno)--;
2929 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2930 been made to this insn. The order of
2931 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2932 can affect nonzero_bits of newpat */
2934 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2935 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2937 /* Set new_direct_jump_p if a new return or simple jump instruction
2940 If I3 is now an unconditional jump, ensure that it has a
2941 BARRIER following it since it may have initially been a
2942 conditional jump. It may also be the last nonnote insn. */
2944 if (returnjump_p (i3) || any_uncondjump_p (i3))
2946 *new_direct_jump_p = 1;
2947 mark_jump_label (PATTERN (i3), i3, 0);
2949 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2950 || GET_CODE (temp) != BARRIER)
2951 emit_barrier_after (i3);
2954 if (undobuf.other_insn != NULL_RTX
2955 && (returnjump_p (undobuf.other_insn)
2956 || any_uncondjump_p (undobuf.other_insn)))
2958 *new_direct_jump_p = 1;
2960 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2961 || GET_CODE (temp) != BARRIER)
2962 emit_barrier_after (undobuf.other_insn);
2965 /* An NOOP jump does not need barrier, but it does need cleaning up
2967 if (GET_CODE (newpat) == SET
2968 && SET_SRC (newpat) == pc_rtx
2969 && SET_DEST (newpat) == pc_rtx)
2970 *new_direct_jump_p = 1;
2973 combine_successes++;
2976 if (added_links_insn
2977 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2978 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2979 return added_links_insn;
2981 return newi2pat ? i2 : i3;
2984 /* Undo all the modifications recorded in undobuf. */
2989 struct undo *undo, *next;
2991 for (undo = undobuf.undos; undo; undo = next)
2995 *undo->where.i = undo->old_contents.i;
2997 *undo->where.r = undo->old_contents.r;
2999 undo->next = undobuf.frees;
3000 undobuf.frees = undo;
3006 /* We've committed to accepting the changes we made. Move all
3007 of the undos to the free list. */
3012 struct undo *undo, *next;
3014 for (undo = undobuf.undos; undo; undo = next)
3017 undo->next = undobuf.frees;
3018 undobuf.frees = undo;
3024 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3025 where we have an arithmetic expression and return that point. LOC will
3028 try_combine will call this function to see if an insn can be split into
3032 find_split_point (rtx *loc, rtx insn)
3035 enum rtx_code code = GET_CODE (x);
3037 unsigned HOST_WIDE_INT len = 0;
3038 HOST_WIDE_INT pos = 0;
3040 rtx inner = NULL_RTX;
3042 /* First special-case some codes. */
3046 #ifdef INSN_SCHEDULING
3047 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3049 if (MEM_P (SUBREG_REG (x)))
3052 return find_split_point (&SUBREG_REG (x), insn);
3056 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3057 using LO_SUM and HIGH. */
3058 if (GET_CODE (XEXP (x, 0)) == CONST
3059 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3062 gen_rtx_LO_SUM (Pmode,
3063 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3065 return &XEXP (XEXP (x, 0), 0);
3069 /* If we have a PLUS whose second operand is a constant and the
3070 address is not valid, perhaps will can split it up using
3071 the machine-specific way to split large constants. We use
3072 the first pseudo-reg (one of the virtual regs) as a placeholder;
3073 it will not remain in the result. */
3074 if (GET_CODE (XEXP (x, 0)) == PLUS
3075 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3076 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3078 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3079 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3082 /* This should have produced two insns, each of which sets our
3083 placeholder. If the source of the second is a valid address,
3084 we can make put both sources together and make a split point
3088 && NEXT_INSN (seq) != NULL_RTX
3089 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3090 && GET_CODE (seq) == INSN
3091 && GET_CODE (PATTERN (seq)) == SET
3092 && SET_DEST (PATTERN (seq)) == reg
3093 && ! reg_mentioned_p (reg,
3094 SET_SRC (PATTERN (seq)))
3095 && GET_CODE (NEXT_INSN (seq)) == INSN
3096 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3097 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3098 && memory_address_p (GET_MODE (x),
3099 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3101 rtx src1 = SET_SRC (PATTERN (seq));
3102 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3104 /* Replace the placeholder in SRC2 with SRC1. If we can
3105 find where in SRC2 it was placed, that can become our
3106 split point and we can replace this address with SRC2.
3107 Just try two obvious places. */
3109 src2 = replace_rtx (src2, reg, src1);
3111 if (XEXP (src2, 0) == src1)
3112 split = &XEXP (src2, 0);
3113 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3114 && XEXP (XEXP (src2, 0), 0) == src1)
3115 split = &XEXP (XEXP (src2, 0), 0);
3119 SUBST (XEXP (x, 0), src2);
3124 /* If that didn't work, perhaps the first operand is complex and
3125 needs to be computed separately, so make a split point there.
3126 This will occur on machines that just support REG + CONST
3127 and have a constant moved through some previous computation. */
3129 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3130 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3131 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3132 return &XEXP (XEXP (x, 0), 0);
3138 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3139 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3140 we need to put the operand into a register. So split at that
3143 if (SET_DEST (x) == cc0_rtx
3144 && GET_CODE (SET_SRC (x)) != COMPARE
3145 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3146 && !OBJECT_P (SET_SRC (x))
3147 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3148 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3149 return &SET_SRC (x);
3152 /* See if we can split SET_SRC as it stands. */
3153 split = find_split_point (&SET_SRC (x), insn);
3154 if (split && split != &SET_SRC (x))
3157 /* See if we can split SET_DEST as it stands. */
3158 split = find_split_point (&SET_DEST (x), insn);
3159 if (split && split != &SET_DEST (x))
3162 /* See if this is a bitfield assignment with everything constant. If
3163 so, this is an IOR of an AND, so split it into that. */
3164 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3165 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3166 <= HOST_BITS_PER_WIDE_INT)
3167 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3168 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3169 && GET_CODE (SET_SRC (x)) == CONST_INT
3170 && ((INTVAL (XEXP (SET_DEST (x), 1))
3171 + INTVAL (XEXP (SET_DEST (x), 2)))
3172 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3173 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3175 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3176 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3177 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3178 rtx dest = XEXP (SET_DEST (x), 0);
3179 enum machine_mode mode = GET_MODE (dest);
3180 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3182 if (BITS_BIG_ENDIAN)
3183 pos = GET_MODE_BITSIZE (mode) - len - pos;
3187 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3190 gen_binary (IOR, mode,
3191 gen_binary (AND, mode, dest,
3192 gen_int_mode (~(mask << pos),
3194 GEN_INT (src << pos)));
3196 SUBST (SET_DEST (x), dest);
3198 split = find_split_point (&SET_SRC (x), insn);
3199 if (split && split != &SET_SRC (x))
3203 /* Otherwise, see if this is an operation that we can split into two.
3204 If so, try to split that. */
3205 code = GET_CODE (SET_SRC (x));
3210 /* If we are AND'ing with a large constant that is only a single
3211 bit and the result is only being used in a context where we
3212 need to know if it is zero or nonzero, replace it with a bit
3213 extraction. This will avoid the large constant, which might
3214 have taken more than one insn to make. If the constant were
3215 not a valid argument to the AND but took only one insn to make,
3216 this is no worse, but if it took more than one insn, it will
3219 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3220 && REG_P (XEXP (SET_SRC (x), 0))
3221 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3222 && REG_P (SET_DEST (x))
3223 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3224 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3225 && XEXP (*split, 0) == SET_DEST (x)
3226 && XEXP (*split, 1) == const0_rtx)
3228 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3229 XEXP (SET_SRC (x), 0),
3230 pos, NULL_RTX, 1, 1, 0, 0);
3231 if (extraction != 0)
3233 SUBST (SET_SRC (x), extraction);
3234 return find_split_point (loc, insn);
3240 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3241 is known to be on, this can be converted into a NEG of a shift. */
3242 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3243 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3244 && 1 <= (pos = exact_log2
3245 (nonzero_bits (XEXP (SET_SRC (x), 0),
3246 GET_MODE (XEXP (SET_SRC (x), 0))))))
3248 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3252 gen_rtx_LSHIFTRT (mode,
3253 XEXP (SET_SRC (x), 0),
3256 split = find_split_point (&SET_SRC (x), insn);
3257 if (split && split != &SET_SRC (x))
3263 inner = XEXP (SET_SRC (x), 0);
3265 /* We can't optimize if either mode is a partial integer
3266 mode as we don't know how many bits are significant
3268 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3269 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3273 len = GET_MODE_BITSIZE (GET_MODE (inner));
3279 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3280 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3282 inner = XEXP (SET_SRC (x), 0);
3283 len = INTVAL (XEXP (SET_SRC (x), 1));
3284 pos = INTVAL (XEXP (SET_SRC (x), 2));
3286 if (BITS_BIG_ENDIAN)
3287 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3288 unsignedp = (code == ZERO_EXTRACT);
3296 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3298 enum machine_mode mode = GET_MODE (SET_SRC (x));
3300 /* For unsigned, we have a choice of a shift followed by an
3301 AND or two shifts. Use two shifts for field sizes where the
3302 constant might be too large. We assume here that we can
3303 always at least get 8-bit constants in an AND insn, which is
3304 true for every current RISC. */
3306 if (unsignedp && len <= 8)
3311 (mode, gen_lowpart (mode, inner),
3313 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3315 split = find_split_point (&SET_SRC (x), insn);
3316 if (split && split != &SET_SRC (x))
3323 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3324 gen_rtx_ASHIFT (mode,
3325 gen_lowpart (mode, inner),
3326 GEN_INT (GET_MODE_BITSIZE (mode)
3328 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3330 split = find_split_point (&SET_SRC (x), insn);
3331 if (split && split != &SET_SRC (x))
3336 /* See if this is a simple operation with a constant as the second
3337 operand. It might be that this constant is out of range and hence
3338 could be used as a split point. */
3339 if (BINARY_P (SET_SRC (x))
3340 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3341 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3342 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3343 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3344 return &XEXP (SET_SRC (x), 1);
3346 /* Finally, see if this is a simple operation with its first operand
3347 not in a register. The operation might require this operand in a
3348 register, so return it as a split point. We can always do this
3349 because if the first operand were another operation, we would have
3350 already found it as a split point. */
3351 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3352 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3353 return &XEXP (SET_SRC (x), 0);
3359 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3360 it is better to write this as (not (ior A B)) so we can split it.
3361 Similarly for IOR. */
3362 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3365 gen_rtx_NOT (GET_MODE (x),
3366 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3368 XEXP (XEXP (x, 0), 0),
3369 XEXP (XEXP (x, 1), 0))));
3370 return find_split_point (loc, insn);
3373 /* Many RISC machines have a large set of logical insns. If the
3374 second operand is a NOT, put it first so we will try to split the
3375 other operand first. */
3376 if (GET_CODE (XEXP (x, 1)) == NOT)
3378 rtx tem = XEXP (x, 0);
3379 SUBST (XEXP (x, 0), XEXP (x, 1));
3380 SUBST (XEXP (x, 1), tem);
3388 /* Otherwise, select our actions depending on our rtx class. */
3389 switch (GET_RTX_CLASS (code))
3391 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3393 split = find_split_point (&XEXP (x, 2), insn);
3396 /* ... fall through ... */
3398 case RTX_COMM_ARITH:
3400 case RTX_COMM_COMPARE:
3401 split = find_split_point (&XEXP (x, 1), insn);
3404 /* ... fall through ... */
3406 /* Some machines have (and (shift ...) ...) insns. If X is not
3407 an AND, but XEXP (X, 0) is, use it as our split point. */
3408 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3409 return &XEXP (x, 0);
3411 split = find_split_point (&XEXP (x, 0), insn);
3417 /* Otherwise, we don't have a split point. */
3422 /* Throughout X, replace FROM with TO, and return the result.
3423 The result is TO if X is FROM;
3424 otherwise the result is X, but its contents may have been modified.
3425 If they were modified, a record was made in undobuf so that
3426 undo_all will (among other things) return X to its original state.
3428 If the number of changes necessary is too much to record to undo,
3429 the excess changes are not made, so the result is invalid.
3430 The changes already made can still be undone.
3431 undobuf.num_undo is incremented for such changes, so by testing that
3432 the caller can tell whether the result is valid.
3434 `n_occurrences' is incremented each time FROM is replaced.
3436 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3438 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3439 by copying if `n_occurrences' is nonzero. */
3442 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3444 enum rtx_code code = GET_CODE (x);
3445 enum machine_mode op0_mode = VOIDmode;
3450 /* Two expressions are equal if they are identical copies of a shared
3451 RTX or if they are both registers with the same register number
3454 #define COMBINE_RTX_EQUAL_P(X,Y) \
3456 || (REG_P (X) && REG_P (Y) \
3457 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3459 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3462 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3465 /* If X and FROM are the same register but different modes, they will
3466 not have been seen as equal above. However, flow.c will make a
3467 LOG_LINKS entry for that case. If we do nothing, we will try to
3468 rerecognize our original insn and, when it succeeds, we will
3469 delete the feeding insn, which is incorrect.
3471 So force this insn not to match in this (rare) case. */
3472 if (! in_dest && code == REG && REG_P (from)
3473 && REGNO (x) == REGNO (from))
3474 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3476 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3477 of which may contain things that can be combined. */
3478 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3481 /* It is possible to have a subexpression appear twice in the insn.
3482 Suppose that FROM is a register that appears within TO.
3483 Then, after that subexpression has been scanned once by `subst',
3484 the second time it is scanned, TO may be found. If we were
3485 to scan TO here, we would find FROM within it and create a
3486 self-referent rtl structure which is completely wrong. */
3487 if (COMBINE_RTX_EQUAL_P (x, to))
3490 /* Parallel asm_operands need special attention because all of the
3491 inputs are shared across the arms. Furthermore, unsharing the
3492 rtl results in recognition failures. Failure to handle this case
3493 specially can result in circular rtl.
3495 Solve this by doing a normal pass across the first entry of the
3496 parallel, and only processing the SET_DESTs of the subsequent
3499 if (code == PARALLEL
3500 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3501 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3503 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3505 /* If this substitution failed, this whole thing fails. */
3506 if (GET_CODE (new) == CLOBBER
3507 && XEXP (new, 0) == const0_rtx)
3510 SUBST (XVECEXP (x, 0, 0), new);
3512 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3514 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3517 && GET_CODE (dest) != CC0
3518 && GET_CODE (dest) != PC)
3520 new = subst (dest, from, to, 0, unique_copy);
3522 /* If this substitution failed, this whole thing fails. */
3523 if (GET_CODE (new) == CLOBBER
3524 && XEXP (new, 0) == const0_rtx)
3527 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3533 len = GET_RTX_LENGTH (code);
3534 fmt = GET_RTX_FORMAT (code);
3536 /* We don't need to process a SET_DEST that is a register, CC0,
3537 or PC, so set up to skip this common case. All other cases
3538 where we want to suppress replacing something inside a
3539 SET_SRC are handled via the IN_DEST operand. */
3541 && (REG_P (SET_DEST (x))
3542 || GET_CODE (SET_DEST (x)) == CC0
3543 || GET_CODE (SET_DEST (x)) == PC))
3546 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3549 op0_mode = GET_MODE (XEXP (x, 0));
3551 for (i = 0; i < len; i++)
3556 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3558 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3560 new = (unique_copy && n_occurrences
3561 ? copy_rtx (to) : to);
3566 new = subst (XVECEXP (x, i, j), from, to, 0,
3569 /* If this substitution failed, this whole thing
3571 if (GET_CODE (new) == CLOBBER
3572 && XEXP (new, 0) == const0_rtx)
3576 SUBST (XVECEXP (x, i, j), new);
3579 else if (fmt[i] == 'e')
3581 /* If this is a register being set, ignore it. */
3584 && (code == SUBREG || code == STRICT_LOW_PART
3585 || code == ZERO_EXTRACT)
3590 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3592 /* In general, don't install a subreg involving two
3593 modes not tieable. It can worsen register
3594 allocation, and can even make invalid reload
3595 insns, since the reg inside may need to be copied
3596 from in the outside mode, and that may be invalid
3597 if it is an fp reg copied in integer mode.
3599 We allow two exceptions to this: It is valid if
3600 it is inside another SUBREG and the mode of that
3601 SUBREG and the mode of the inside of TO is
3602 tieable and it is valid if X is a SET that copies
3605 if (GET_CODE (to) == SUBREG
3606 && ! MODES_TIEABLE_P (GET_MODE (to),
3607 GET_MODE (SUBREG_REG (to)))
3608 && ! (code == SUBREG
3609 && MODES_TIEABLE_P (GET_MODE (x),
3610 GET_MODE (SUBREG_REG (to))))
3612 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3615 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3617 #ifdef CANNOT_CHANGE_MODE_CLASS
3620 && REGNO (to) < FIRST_PSEUDO_REGISTER
3621 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3624 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3627 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3631 /* If we are in a SET_DEST, suppress most cases unless we
3632 have gone inside a MEM, in which case we want to
3633 simplify the address. We assume here that things that
3634 are actually part of the destination have their inner
3635 parts in the first expression. This is true for SUBREG,
3636 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3637 things aside from REG and MEM that should appear in a
3639 new = subst (XEXP (x, i), from, to,
3641 && (code == SUBREG || code == STRICT_LOW_PART
3642 || code == ZERO_EXTRACT))
3644 && i == 0), unique_copy);
3646 /* If we found that we will have to reject this combination,
3647 indicate that by returning the CLOBBER ourselves, rather than
3648 an expression containing it. This will speed things up as
3649 well as prevent accidents where two CLOBBERs are considered
3650 to be equal, thus producing an incorrect simplification. */
3652 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3655 if (GET_CODE (x) == SUBREG
3656 && (GET_CODE (new) == CONST_INT
3657 || GET_CODE (new) == CONST_DOUBLE))
3659 enum machine_mode mode = GET_MODE (x);
3661 x = simplify_subreg (GET_MODE (x), new,
3662 GET_MODE (SUBREG_REG (x)),
3665 x = gen_rtx_CLOBBER (mode, const0_rtx);
3667 else if (GET_CODE (new) == CONST_INT
3668 && GET_CODE (x) == ZERO_EXTEND)
3670 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3671 new, GET_MODE (XEXP (x, 0)));
3676 SUBST (XEXP (x, i), new);
3681 /* Try to simplify X. If the simplification changed the code, it is likely
3682 that further simplification will help, so loop, but limit the number
3683 of repetitions that will be performed. */
3685 for (i = 0; i < 4; i++)
3687 /* If X is sufficiently simple, don't bother trying to do anything
3689 if (code != CONST_INT && code != REG && code != CLOBBER)
3690 x = combine_simplify_rtx (x, op0_mode, in_dest);
3692 if (GET_CODE (x) == code)
3695 code = GET_CODE (x);
3697 /* We no longer know the original mode of operand 0 since we
3698 have changed the form of X) */
3699 op0_mode = VOIDmode;
3705 /* Simplify X, a piece of RTL. We just operate on the expression at the
3706 outer level; call `subst' to simplify recursively. Return the new
3709 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3710 if we are inside a SET_DEST. */
3713 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3715 enum rtx_code code = GET_CODE (x);
3716 enum machine_mode mode = GET_MODE (x);
3721 /* If this is a commutative operation, put a constant last and a complex
3722 expression first. We don't need to do this for comparisons here. */
3723 if (COMMUTATIVE_ARITH_P (x)
3724 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3727 SUBST (XEXP (x, 0), XEXP (x, 1));
3728 SUBST (XEXP (x, 1), temp);
3731 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3732 sign extension of a PLUS with a constant, reverse the order of the sign
3733 extension and the addition. Note that this not the same as the original
3734 code, but overflow is undefined for signed values. Also note that the
3735 PLUS will have been partially moved "inside" the sign-extension, so that
3736 the first operand of X will really look like:
3737 (ashiftrt (plus (ashift A C4) C5) C4).
3739 (plus (ashiftrt (ashift A C4) C2) C4)
3740 and replace the first operand of X with that expression. Later parts
3741 of this function may simplify the expression further.
3743 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3744 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3745 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3747 We do this to simplify address expressions. */
3749 if ((code == PLUS || code == MINUS || code == MULT)
3750 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3751 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3752 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3753 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3754 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3755 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3756 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3757 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3758 XEXP (XEXP (XEXP (x, 0), 0), 1),
3759 XEXP (XEXP (x, 0), 1))) != 0)
3762 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3763 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3764 INTVAL (XEXP (XEXP (x, 0), 1)));
3766 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3767 INTVAL (XEXP (XEXP (x, 0), 1)));
3769 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3772 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3773 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3774 things. Check for cases where both arms are testing the same
3777 Don't do anything if all operands are very simple. */
3780 && ((!OBJECT_P (XEXP (x, 0))
3781 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3782 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3783 || (!OBJECT_P (XEXP (x, 1))
3784 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3785 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3787 && (!OBJECT_P (XEXP (x, 0))
3788 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3789 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3791 rtx cond, true_rtx, false_rtx;
3793 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3795 /* If everything is a comparison, what we have is highly unlikely
3796 to be simpler, so don't use it. */
3797 && ! (COMPARISON_P (x)
3798 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3800 rtx cop1 = const0_rtx;
3801 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3803 if (cond_code == NE && COMPARISON_P (cond))
3806 /* Simplify the alternative arms; this may collapse the true and
3807 false arms to store-flag values. Be careful to use copy_rtx
3808 here since true_rtx or false_rtx might share RTL with x as a
3809 result of the if_then_else_cond call above. */
3810 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3811 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3813 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3814 is unlikely to be simpler. */
3815 if (general_operand (true_rtx, VOIDmode)
3816 && general_operand (false_rtx, VOIDmode))
3818 enum rtx_code reversed;
3820 /* Restarting if we generate a store-flag expression will cause
3821 us to loop. Just drop through in this case. */
3823 /* If the result values are STORE_FLAG_VALUE and zero, we can
3824 just make the comparison operation. */
3825 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3826 x = gen_binary (cond_code, mode, cond, cop1);
3827 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3828 && ((reversed = reversed_comparison_code_parts
3829 (cond_code, cond, cop1, NULL))
3831 x = gen_binary (reversed, mode, cond, cop1);
3833 /* Likewise, we can make the negate of a comparison operation
3834 if the result values are - STORE_FLAG_VALUE and zero. */
3835 else if (GET_CODE (true_rtx) == CONST_INT
3836 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3837 && false_rtx == const0_rtx)
3838 x = simplify_gen_unary (NEG, mode,
3839 gen_binary (cond_code, mode, cond,
3842 else if (GET_CODE (false_rtx) == CONST_INT
3843 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3844 && true_rtx == const0_rtx
3845 && ((reversed = reversed_comparison_code_parts
3846 (cond_code, cond, cop1, NULL))
3848 x = simplify_gen_unary (NEG, mode,
3849 gen_binary (reversed, mode,
3853 return gen_rtx_IF_THEN_ELSE (mode,
3854 gen_binary (cond_code, VOIDmode,
3856 true_rtx, false_rtx);
3858 code = GET_CODE (x);
3859 op0_mode = VOIDmode;
3864 /* Try to fold this expression in case we have constants that weren't
3867 switch (GET_RTX_CLASS (code))
3870 if (op0_mode == VOIDmode)
3871 op0_mode = GET_MODE (XEXP (x, 0));
3872 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3875 case RTX_COMM_COMPARE:
3877 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3878 if (cmp_mode == VOIDmode)
3880 cmp_mode = GET_MODE (XEXP (x, 1));
3881 if (cmp_mode == VOIDmode)
3882 cmp_mode = op0_mode;
3884 temp = simplify_relational_operation (code, mode, cmp_mode,
3885 XEXP (x, 0), XEXP (x, 1));
3888 case RTX_COMM_ARITH:
3890 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3892 case RTX_BITFIELD_OPS:
3894 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3895 XEXP (x, 1), XEXP (x, 2));
3904 code = GET_CODE (temp);
3905 op0_mode = VOIDmode;
3906 mode = GET_MODE (temp);
3909 /* First see if we can apply the inverse distributive law. */
3910 if (code == PLUS || code == MINUS
3911 || code == AND || code == IOR || code == XOR)
3913 x = apply_distributive_law (x);
3914 code = GET_CODE (x);
3915 op0_mode = VOIDmode;
3918 /* If CODE is an associative operation not otherwise handled, see if we
3919 can associate some operands. This can win if they are constants or
3920 if they are logically related (i.e. (a & b) & a). */
3921 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3922 || code == AND || code == IOR || code == XOR
3923 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3924 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3925 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3927 if (GET_CODE (XEXP (x, 0)) == code)
3929 rtx other = XEXP (XEXP (x, 0), 0);
3930 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3931 rtx inner_op1 = XEXP (x, 1);
3934 /* Make sure we pass the constant operand if any as the second
3935 one if this is a commutative operation. */
3936 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3938 rtx tem = inner_op0;
3939 inner_op0 = inner_op1;
3942 inner = simplify_binary_operation (code == MINUS ? PLUS
3943 : code == DIV ? MULT
3945 mode, inner_op0, inner_op1);
3947 /* For commutative operations, try the other pair if that one
3949 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3951 other = XEXP (XEXP (x, 0), 1);
3952 inner = simplify_binary_operation (code, mode,
3953 XEXP (XEXP (x, 0), 0),
3958 return gen_binary (code, mode, other, inner);
3962 /* A little bit of algebraic simplification here. */
3966 /* Ensure that our address has any ASHIFTs converted to MULT in case
3967 address-recognizing predicates are called later. */
3968 temp = make_compound_operation (XEXP (x, 0), MEM);
3969 SUBST (XEXP (x, 0), temp);
3973 if (op0_mode == VOIDmode)
3974 op0_mode = GET_MODE (SUBREG_REG (x));
3976 /* See if this can be moved to simplify_subreg. */
3977 if (CONSTANT_P (SUBREG_REG (x))
3978 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3979 /* Don't call gen_lowpart if the inner mode
3980 is VOIDmode and we cannot simplify it, as SUBREG without
3981 inner mode is invalid. */
3982 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3983 || gen_lowpart_common (mode, SUBREG_REG (x))))
3984 return gen_lowpart (mode, SUBREG_REG (x));
3986 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3990 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3996 /* Don't change the mode of the MEM if that would change the meaning
3998 if (MEM_P (SUBREG_REG (x))
3999 && (MEM_VOLATILE_P (SUBREG_REG (x))
4000 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4001 return gen_rtx_CLOBBER (mode, const0_rtx);
4003 /* Note that we cannot do any narrowing for non-constants since
4004 we might have been counting on using the fact that some bits were
4005 zero. We now do this in the SET. */
4010 if (GET_CODE (XEXP (x, 0)) == SUBREG
4011 && subreg_lowpart_p (XEXP (x, 0))
4012 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4013 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4014 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4015 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4017 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4019 x = gen_rtx_ROTATE (inner_mode,
4020 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4022 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4023 return gen_lowpart (mode, x);
4026 /* Apply De Morgan's laws to reduce number of patterns for machines
4027 with negating logical insns (and-not, nand, etc.). If result has
4028 only one NOT, put it first, since that is how the patterns are
4031 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4033 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4034 enum machine_mode op_mode;
4036 op_mode = GET_MODE (in1);
4037 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4039 op_mode = GET_MODE (in2);
4040 if (op_mode == VOIDmode)
4042 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4044 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4047 in2 = in1; in1 = tem;
4050 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4056 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4057 if (GET_CODE (XEXP (x, 0)) == XOR
4058 && XEXP (XEXP (x, 0), 1) == const1_rtx
4059 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4060 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4062 temp = expand_compound_operation (XEXP (x, 0));
4064 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4065 replaced by (lshiftrt X C). This will convert
4066 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4068 if (GET_CODE (temp) == ASHIFTRT
4069 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4070 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4071 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4072 INTVAL (XEXP (temp, 1)));
4074 /* If X has only a single bit that might be nonzero, say, bit I, convert
4075 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4076 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4077 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4078 or a SUBREG of one since we'd be making the expression more
4079 complex if it was just a register. */
4082 && ! (GET_CODE (temp) == SUBREG
4083 && REG_P (SUBREG_REG (temp)))
4084 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4086 rtx temp1 = simplify_shift_const
4087 (NULL_RTX, ASHIFTRT, mode,
4088 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4089 GET_MODE_BITSIZE (mode) - 1 - i),
4090 GET_MODE_BITSIZE (mode) - 1 - i);
4092 /* If all we did was surround TEMP with the two shifts, we
4093 haven't improved anything, so don't use it. Otherwise,
4094 we are better off with TEMP1. */
4095 if (GET_CODE (temp1) != ASHIFTRT
4096 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4097 || XEXP (XEXP (temp1, 0), 0) != temp)
4103 /* We can't handle truncation to a partial integer mode here
4104 because we don't know the real bitsize of the partial
4106 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4109 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4110 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4111 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4113 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4114 GET_MODE_MASK (mode), NULL_RTX, 0));
4116 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4117 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4118 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4119 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4120 return XEXP (XEXP (x, 0), 0);
4122 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4123 (OP:SI foo:SI) if OP is NEG or ABS. */
4124 if ((GET_CODE (XEXP (x, 0)) == ABS
4125 || GET_CODE (XEXP (x, 0)) == NEG)
4126 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4127 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4128 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4129 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4130 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4132 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4134 if (GET_CODE (XEXP (x, 0)) == SUBREG
4135 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4136 && subreg_lowpart_p (XEXP (x, 0)))
4137 return SUBREG_REG (XEXP (x, 0));
4139 /* If we know that the value is already truncated, we can
4140 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4141 is nonzero for the corresponding modes. But don't do this
4142 for an (LSHIFTRT (MULT ...)) since this will cause problems
4143 with the umulXi3_highpart patterns. */
4144 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4145 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4146 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4147 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4148 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4150 return gen_lowpart (mode, XEXP (x, 0));
4152 /* A truncate of a comparison can be replaced with a subreg if
4153 STORE_FLAG_VALUE permits. This is like the previous test,
4154 but it works even if the comparison is done in a mode larger
4155 than HOST_BITS_PER_WIDE_INT. */
4156 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4157 && COMPARISON_P (XEXP (x, 0))
4158 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4159 return gen_lowpart (mode, XEXP (x, 0));
4161 /* Similarly, a truncate of a register whose value is a
4162 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4164 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4165 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4166 && (temp = get_last_value (XEXP (x, 0)))
4167 && COMPARISON_P (temp))
4168 return gen_lowpart (mode, XEXP (x, 0));
4172 case FLOAT_TRUNCATE:
4173 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4174 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4175 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4176 return XEXP (XEXP (x, 0), 0);
4178 /* (float_truncate:SF (float_truncate:DF foo:XF))
4179 = (float_truncate:SF foo:XF).
4180 This may eliminate double rounding, so it is unsafe.
4182 (float_truncate:SF (float_extend:XF foo:DF))
4183 = (float_truncate:SF foo:DF).
4185 (float_truncate:DF (float_extend:XF foo:SF))
4186 = (float_extend:SF foo:DF). */
4187 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4188 && flag_unsafe_math_optimizations)
4189 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4190 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4192 > GET_MODE_SIZE (mode)
4193 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4195 XEXP (XEXP (x, 0), 0), mode);
4197 /* (float_truncate (float x)) is (float x) */
4198 if (GET_CODE (XEXP (x, 0)) == FLOAT
4199 && (flag_unsafe_math_optimizations
4200 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4201 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4202 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4203 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4204 return simplify_gen_unary (FLOAT, mode,
4205 XEXP (XEXP (x, 0), 0),
4206 GET_MODE (XEXP (XEXP (x, 0), 0)));
4208 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4209 (OP:SF foo:SF) if OP is NEG or ABS. */
4210 if ((GET_CODE (XEXP (x, 0)) == ABS
4211 || GET_CODE (XEXP (x, 0)) == NEG)
4212 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4213 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4214 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4215 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4217 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4218 is (float_truncate:SF x). */
4219 if (GET_CODE (XEXP (x, 0)) == SUBREG
4220 && subreg_lowpart_p (XEXP (x, 0))
4221 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4222 return SUBREG_REG (XEXP (x, 0));
4225 /* (float_extend (float_extend x)) is (float_extend x)
4227 (float_extend (float x)) is (float x) assuming that double
4228 rounding can't happen.
4230 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4231 || (GET_CODE (XEXP (x, 0)) == FLOAT
4232 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4233 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4234 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4235 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4236 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4237 XEXP (XEXP (x, 0), 0),
4238 GET_MODE (XEXP (XEXP (x, 0), 0)));
4243 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4244 using cc0, in which case we want to leave it as a COMPARE
4245 so we can distinguish it from a register-register-copy. */
4246 if (XEXP (x, 1) == const0_rtx)
4249 /* x - 0 is the same as x unless x's mode has signed zeros and
4250 allows rounding towards -infinity. Under those conditions,
4252 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4253 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4254 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4260 /* (const (const X)) can become (const X). Do it this way rather than
4261 returning the inner CONST since CONST can be shared with a
4263 if (GET_CODE (XEXP (x, 0)) == CONST)
4264 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4269 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4270 can add in an offset. find_split_point will split this address up
4271 again if it doesn't match. */
4272 if (GET_CODE (XEXP (x, 0)) == HIGH
4273 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4279 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4281 if (GET_CODE (XEXP (x, 0)) == MULT
4282 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4286 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4287 in2 = XEXP (XEXP (x, 0), 1);
4288 return gen_binary (MINUS, mode, XEXP (x, 1),
4289 gen_binary (MULT, mode, in1, in2));
4292 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4293 outermost. That's because that's the way indexed addresses are
4294 supposed to appear. This code used to check many more cases, but
4295 they are now checked elsewhere. */
4296 if (GET_CODE (XEXP (x, 0)) == PLUS
4297 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4298 return gen_binary (PLUS, mode,
4299 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4301 XEXP (XEXP (x, 0), 1));
4303 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4304 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4305 bit-field and can be replaced by either a sign_extend or a
4306 sign_extract. The `and' may be a zero_extend and the two
4307 <c>, -<c> constants may be reversed. */
4308 if (GET_CODE (XEXP (x, 0)) == XOR
4309 && GET_CODE (XEXP (x, 1)) == CONST_INT
4310 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4311 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4312 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4313 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4314 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4315 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4316 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4317 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4318 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4319 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4320 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4321 == (unsigned int) i + 1))))
4322 return simplify_shift_const
4323 (NULL_RTX, ASHIFTRT, mode,
4324 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4325 XEXP (XEXP (XEXP (x, 0), 0), 0),
4326 GET_MODE_BITSIZE (mode) - (i + 1)),
4327 GET_MODE_BITSIZE (mode) - (i + 1));
4329 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4330 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4331 is 1. This produces better code than the alternative immediately
4333 if (COMPARISON_P (XEXP (x, 0))
4334 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4335 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4336 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4337 XEXP (XEXP (x, 0), 0),
4338 XEXP (XEXP (x, 0), 1))))
4340 simplify_gen_unary (NEG, mode, reversed, mode);
4342 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4343 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4344 the bitsize of the mode - 1. This allows simplification of
4345 "a = (b & 8) == 0;" */
4346 if (XEXP (x, 1) == constm1_rtx
4347 && !REG_P (XEXP (x, 0))
4348 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4349 && REG_P (SUBREG_REG (XEXP (x, 0))))
4350 && nonzero_bits (XEXP (x, 0), mode) == 1)
4351 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4352 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4353 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4354 GET_MODE_BITSIZE (mode) - 1),
4355 GET_MODE_BITSIZE (mode) - 1);
4357 /* If we are adding two things that have no bits in common, convert
4358 the addition into an IOR. This will often be further simplified,
4359 for example in cases like ((a & 1) + (a & 2)), which can
4362 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4363 && (nonzero_bits (XEXP (x, 0), mode)
4364 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4366 /* Try to simplify the expression further. */
4367 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4368 temp = combine_simplify_rtx (tor, mode, in_dest);
4370 /* If we could, great. If not, do not go ahead with the IOR
4371 replacement, since PLUS appears in many special purpose
4372 address arithmetic instructions. */
4373 if (GET_CODE (temp) != CLOBBER && temp != tor)
4379 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4380 by reversing the comparison code if valid. */
4381 if (STORE_FLAG_VALUE == 1
4382 && XEXP (x, 0) == const1_rtx
4383 && COMPARISON_P (XEXP (x, 1))
4384 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4385 XEXP (XEXP (x, 1), 0),
4386 XEXP (XEXP (x, 1), 1))))
4389 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4390 (and <foo> (const_int pow2-1)) */
4391 if (GET_CODE (XEXP (x, 1)) == AND
4392 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4393 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4394 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4395 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4396 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4398 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4400 if (GET_CODE (XEXP (x, 1)) == MULT
4401 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4405 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4406 in2 = XEXP (XEXP (x, 1), 1);
4407 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4411 /* Canonicalize (minus (neg A) (mult B C)) to
4412 (minus (mult (neg B) C) A). */
4413 if (GET_CODE (XEXP (x, 1)) == MULT
4414 && GET_CODE (XEXP (x, 0)) == NEG)
4418 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4419 in2 = XEXP (XEXP (x, 1), 1);
4420 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4421 XEXP (XEXP (x, 0), 0));
4424 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4426 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4427 return gen_binary (MINUS, mode,
4428 gen_binary (MINUS, mode, XEXP (x, 0),
4429 XEXP (XEXP (x, 1), 0)),
4430 XEXP (XEXP (x, 1), 1));
4434 /* If we have (mult (plus A B) C), apply the distributive law and then
4435 the inverse distributive law to see if things simplify. This
4436 occurs mostly in addresses, often when unrolling loops. */
4438 if (GET_CODE (XEXP (x, 0)) == PLUS)
4440 x = apply_distributive_law
4441 (gen_binary (PLUS, mode,
4442 gen_binary (MULT, mode,
4443 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4444 gen_binary (MULT, mode,
4445 XEXP (XEXP (x, 0), 1),
4446 copy_rtx (XEXP (x, 1)))));
4448 if (GET_CODE (x) != MULT)
4451 /* Try simplify a*(b/c) as (a*b)/c. */
4452 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4453 && GET_CODE (XEXP (x, 0)) == DIV)
4455 rtx tem = simplify_binary_operation (MULT, mode,
4456 XEXP (XEXP (x, 0), 0),
4459 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4464 /* If this is a divide by a power of two, treat it as a shift if
4465 its first operand is a shift. */
4466 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4467 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4468 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4469 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4470 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4471 || GET_CODE (XEXP (x, 0)) == ROTATE
4472 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4473 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4477 case GT: case GTU: case GE: case GEU:
4478 case LT: case LTU: case LE: case LEU:
4479 case UNEQ: case LTGT:
4480 case UNGT: case UNGE:
4481 case UNLT: case UNLE:
4482 case UNORDERED: case ORDERED:
4483 /* If the first operand is a condition code, we can't do anything
4485 if (GET_CODE (XEXP (x, 0)) == COMPARE
4486 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4487 && ! CC0_P (XEXP (x, 0))))
4489 rtx op0 = XEXP (x, 0);
4490 rtx op1 = XEXP (x, 1);
4491 enum rtx_code new_code;
4493 if (GET_CODE (op0) == COMPARE)
4494 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4496 /* Simplify our comparison, if possible. */
4497 new_code = simplify_comparison (code, &op0, &op1);
4499 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4500 if only the low-order bit is possibly nonzero in X (such as when
4501 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4502 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4503 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4506 Remove any ZERO_EXTRACT we made when thinking this was a
4507 comparison. It may now be simpler to use, e.g., an AND. If a
4508 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4509 the call to make_compound_operation in the SET case. */
4511 if (STORE_FLAG_VALUE == 1
4512 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4513 && op1 == const0_rtx
4514 && mode == GET_MODE (op0)
4515 && nonzero_bits (op0, mode) == 1)
4516 return gen_lowpart (mode,
4517 expand_compound_operation (op0));
4519 else if (STORE_FLAG_VALUE == 1
4520 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4521 && op1 == const0_rtx
4522 && mode == GET_MODE (op0)
4523 && (num_sign_bit_copies (op0, mode)
4524 == GET_MODE_BITSIZE (mode)))
4526 op0 = expand_compound_operation (op0);
4527 return simplify_gen_unary (NEG, mode,
4528 gen_lowpart (mode, op0),
4532 else if (STORE_FLAG_VALUE == 1
4533 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4534 && op1 == const0_rtx
4535 && mode == GET_MODE (op0)
4536 && nonzero_bits (op0, mode) == 1)
4538 op0 = expand_compound_operation (op0);
4539 return gen_binary (XOR, mode,
4540 gen_lowpart (mode, op0),
4544 else if (STORE_FLAG_VALUE == 1
4545 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4546 && op1 == const0_rtx
4547 && mode == GET_MODE (op0)
4548 && (num_sign_bit_copies (op0, mode)
4549 == GET_MODE_BITSIZE (mode)))
4551 op0 = expand_compound_operation (op0);
4552 return plus_constant (gen_lowpart (mode, op0), 1);
4555 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4557 if (STORE_FLAG_VALUE == -1
4558 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4559 && op1 == const0_rtx
4560 && (num_sign_bit_copies (op0, mode)
4561 == GET_MODE_BITSIZE (mode)))
4562 return gen_lowpart (mode,
4563 expand_compound_operation (op0));
4565 else if (STORE_FLAG_VALUE == -1
4566 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4567 && op1 == const0_rtx
4568 && mode == GET_MODE (op0)
4569 && nonzero_bits (op0, mode) == 1)
4571 op0 = expand_compound_operation (op0);
4572 return simplify_gen_unary (NEG, mode,
4573 gen_lowpart (mode, op0),
4577 else if (STORE_FLAG_VALUE == -1
4578 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4579 && op1 == const0_rtx
4580 && mode == GET_MODE (op0)
4581 && (num_sign_bit_copies (op0, mode)
4582 == GET_MODE_BITSIZE (mode)))
4584 op0 = expand_compound_operation (op0);
4585 return simplify_gen_unary (NOT, mode,
4586 gen_lowpart (mode, op0),
4590 /* If X is 0/1, (eq X 0) is X-1. */
4591 else if (STORE_FLAG_VALUE == -1
4592 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4593 && op1 == const0_rtx
4594 && mode == GET_MODE (op0)
4595 && nonzero_bits (op0, mode) == 1)
4597 op0 = expand_compound_operation (op0);
4598 return plus_constant (gen_lowpart (mode, op0), -1);
4601 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4602 one bit that might be nonzero, we can convert (ne x 0) to
4603 (ashift x c) where C puts the bit in the sign bit. Remove any
4604 AND with STORE_FLAG_VALUE when we are done, since we are only
4605 going to test the sign bit. */
4606 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4607 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4608 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4609 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4610 && op1 == const0_rtx
4611 && mode == GET_MODE (op0)
4612 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4614 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4615 expand_compound_operation (op0),
4616 GET_MODE_BITSIZE (mode) - 1 - i);
4617 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4623 /* If the code changed, return a whole new comparison. */
4624 if (new_code != code)
4625 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4627 /* Otherwise, keep this operation, but maybe change its operands.
4628 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4629 SUBST (XEXP (x, 0), op0);
4630 SUBST (XEXP (x, 1), op1);
4635 return simplify_if_then_else (x);
4641 /* If we are processing SET_DEST, we are done. */
4645 return expand_compound_operation (x);
4648 return simplify_set (x);
4653 return simplify_logical (x);
4656 /* (abs (neg <foo>)) -> (abs <foo>) */
4657 if (GET_CODE (XEXP (x, 0)) == NEG)
4658 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4660 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4662 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4665 /* If operand is something known to be positive, ignore the ABS. */
4666 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4667 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4668 <= HOST_BITS_PER_WIDE_INT)
4669 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4670 & ((HOST_WIDE_INT) 1
4671 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4675 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4676 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4677 return gen_rtx_NEG (mode, XEXP (x, 0));
4682 /* (ffs (*_extend <X>)) = (ffs <X>) */
4683 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4684 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4685 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4690 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4691 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4692 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4696 /* (float (sign_extend <X>)) = (float <X>). */
4697 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4698 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4706 /* If this is a shift by a constant amount, simplify it. */
4707 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4708 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4709 INTVAL (XEXP (x, 1)));
4711 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4713 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4715 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4722 rtx op0 = XEXP (x, 0);
4723 rtx op1 = XEXP (x, 1);
4726 if (GET_CODE (op1) != PARALLEL)
4728 len = XVECLEN (op1, 0);
4730 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4731 && GET_CODE (op0) == VEC_CONCAT)
4733 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4735 /* Try to find the element in the VEC_CONCAT. */
4738 if (GET_MODE (op0) == GET_MODE (x))
4740 if (GET_CODE (op0) == VEC_CONCAT)
4742 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4743 if (op0_size < offset)
4744 op0 = XEXP (op0, 0);
4748 op0 = XEXP (op0, 1);
4766 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4769 simplify_if_then_else (rtx x)
4771 enum machine_mode mode = GET_MODE (x);
4772 rtx cond = XEXP (x, 0);
4773 rtx true_rtx = XEXP (x, 1);
4774 rtx false_rtx = XEXP (x, 2);
4775 enum rtx_code true_code = GET_CODE (cond);
4776 int comparison_p = COMPARISON_P (cond);
4779 enum rtx_code false_code;
4782 /* Simplify storing of the truth value. */
4783 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4784 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4786 /* Also when the truth value has to be reversed. */
4788 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4789 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4793 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4794 in it is being compared against certain values. Get the true and false
4795 comparisons and see if that says anything about the value of each arm. */
4798 && ((false_code = combine_reversed_comparison_code (cond))
4800 && REG_P (XEXP (cond, 0)))
4803 rtx from = XEXP (cond, 0);
4804 rtx true_val = XEXP (cond, 1);
4805 rtx false_val = true_val;
4808 /* If FALSE_CODE is EQ, swap the codes and arms. */
4810 if (false_code == EQ)
4812 swapped = 1, true_code = EQ, false_code = NE;
4813 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4816 /* If we are comparing against zero and the expression being tested has
4817 only a single bit that might be nonzero, that is its value when it is
4818 not equal to zero. Similarly if it is known to be -1 or 0. */
4820 if (true_code == EQ && true_val == const0_rtx
4821 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4822 false_code = EQ, false_val = GEN_INT (nzb);
4823 else if (true_code == EQ && true_val == const0_rtx
4824 && (num_sign_bit_copies (from, GET_MODE (from))
4825 == GET_MODE_BITSIZE (GET_MODE (from))))
4826 false_code = EQ, false_val = constm1_rtx;
4828 /* Now simplify an arm if we know the value of the register in the
4829 branch and it is used in the arm. Be careful due to the potential
4830 of locally-shared RTL. */
4832 if (reg_mentioned_p (from, true_rtx))
4833 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4835 pc_rtx, pc_rtx, 0, 0);
4836 if (reg_mentioned_p (from, false_rtx))
4837 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4839 pc_rtx, pc_rtx, 0, 0);
4841 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4842 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4844 true_rtx = XEXP (x, 1);
4845 false_rtx = XEXP (x, 2);
4846 true_code = GET_CODE (cond);
4849 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4850 reversed, do so to avoid needing two sets of patterns for
4851 subtract-and-branch insns. Similarly if we have a constant in the true
4852 arm, the false arm is the same as the first operand of the comparison, or
4853 the false arm is more complicated than the true arm. */
4856 && combine_reversed_comparison_code (cond) != UNKNOWN
4857 && (true_rtx == pc_rtx
4858 || (CONSTANT_P (true_rtx)
4859 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4860 || true_rtx == const0_rtx
4861 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4862 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4863 && !OBJECT_P (false_rtx))
4864 || reg_mentioned_p (true_rtx, false_rtx)
4865 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4867 true_code = reversed_comparison_code (cond, NULL);
4869 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4872 SUBST (XEXP (x, 1), false_rtx);
4873 SUBST (XEXP (x, 2), true_rtx);
4875 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4878 /* It is possible that the conditional has been simplified out. */
4879 true_code = GET_CODE (cond);
4880 comparison_p = COMPARISON_P (cond);
4883 /* If the two arms are identical, we don't need the comparison. */
4885 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4888 /* Convert a == b ? b : a to "a". */
4889 if (true_code == EQ && ! side_effects_p (cond)
4890 && !HONOR_NANS (mode)
4891 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4892 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4894 else if (true_code == NE && ! side_effects_p (cond)
4895 && !HONOR_NANS (mode)
4896 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4897 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4900 /* Look for cases where we have (abs x) or (neg (abs X)). */
4902 if (GET_MODE_CLASS (mode) == MODE_INT
4903 && GET_CODE (false_rtx) == NEG
4904 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4906 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4907 && ! side_effects_p (true_rtx))
4912 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4916 simplify_gen_unary (NEG, mode,
4917 simplify_gen_unary (ABS, mode, true_rtx, mode),
4923 /* Look for MIN or MAX. */
4925 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4927 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4928 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4929 && ! side_effects_p (cond))
4934 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4937 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4940 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4943 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4948 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4949 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4950 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4951 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4952 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4953 neither 1 or -1, but it isn't worth checking for. */
4955 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4957 && GET_MODE_CLASS (mode) == MODE_INT
4958 && ! side_effects_p (x))
4960 rtx t = make_compound_operation (true_rtx, SET);
4961 rtx f = make_compound_operation (false_rtx, SET);
4962 rtx cond_op0 = XEXP (cond, 0);
4963 rtx cond_op1 = XEXP (cond, 1);
4964 enum rtx_code op = NIL, extend_op = NIL;
4965 enum machine_mode m = mode;
4966 rtx z = 0, c1 = NULL_RTX;
4968 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4969 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4970 || GET_CODE (t) == ASHIFT
4971 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4972 && rtx_equal_p (XEXP (t, 0), f))
4973 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4975 /* If an identity-zero op is commutative, check whether there
4976 would be a match if we swapped the operands. */
4977 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4978 || GET_CODE (t) == XOR)
4979 && rtx_equal_p (XEXP (t, 1), f))
4980 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4981 else if (GET_CODE (t) == SIGN_EXTEND
4982 && (GET_CODE (XEXP (t, 0)) == PLUS
4983 || GET_CODE (XEXP (t, 0)) == MINUS
4984 || GET_CODE (XEXP (t, 0)) == IOR
4985 || GET_CODE (XEXP (t, 0)) == XOR
4986 || GET_CODE (XEXP (t, 0)) == ASHIFT
4987 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4988 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4989 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4990 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4991 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4992 && (num_sign_bit_copies (f, GET_MODE (f))
4994 (GET_MODE_BITSIZE (mode)
4995 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4997 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4998 extend_op = SIGN_EXTEND;
4999 m = GET_MODE (XEXP (t, 0));
5001 else if (GET_CODE (t) == SIGN_EXTEND
5002 && (GET_CODE (XEXP (t, 0)) == PLUS
5003 || GET_CODE (XEXP (t, 0)) == IOR
5004 || GET_CODE (XEXP (t, 0)) == XOR)
5005 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5006 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5007 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5008 && (num_sign_bit_copies (f, GET_MODE (f))
5010 (GET_MODE_BITSIZE (mode)
5011 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5013 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5014 extend_op = SIGN_EXTEND;
5015 m = GET_MODE (XEXP (t, 0));
5017 else if (GET_CODE (t) == ZERO_EXTEND
5018 && (GET_CODE (XEXP (t, 0)) == PLUS
5019 || GET_CODE (XEXP (t, 0)) == MINUS
5020 || GET_CODE (XEXP (t, 0)) == IOR
5021 || GET_CODE (XEXP (t, 0)) == XOR
5022 || GET_CODE (XEXP (t, 0)) == ASHIFT
5023 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5024 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5025 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5026 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5027 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5028 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5029 && ((nonzero_bits (f, GET_MODE (f))
5030 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5033 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5034 extend_op = ZERO_EXTEND;
5035 m = GET_MODE (XEXP (t, 0));
5037 else if (GET_CODE (t) == ZERO_EXTEND
5038 && (GET_CODE (XEXP (t, 0)) == PLUS
5039 || GET_CODE (XEXP (t, 0)) == IOR
5040 || GET_CODE (XEXP (t, 0)) == XOR)
5041 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5042 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5043 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5044 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5045 && ((nonzero_bits (f, GET_MODE (f))
5046 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5049 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5050 extend_op = ZERO_EXTEND;
5051 m = GET_MODE (XEXP (t, 0));
5056 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5057 pc_rtx, pc_rtx, 0, 0);
5058 temp = gen_binary (MULT, m, temp,
5059 gen_binary (MULT, m, c1, const_true_rtx));
5060 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5061 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
5063 if (extend_op != NIL)
5064 temp = simplify_gen_unary (extend_op, mode, temp, m);
5070 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5071 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5072 negation of a single bit, we can convert this operation to a shift. We
5073 can actually do this more generally, but it doesn't seem worth it. */
5075 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5076 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5077 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5078 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5079 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5080 == GET_MODE_BITSIZE (mode))
5081 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5083 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5084 gen_lowpart (mode, XEXP (cond, 0)), i);
5086 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5087 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5088 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5089 && GET_MODE (XEXP (cond, 0)) == mode
5090 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5091 == nonzero_bits (XEXP (cond, 0), mode)
5092 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5093 return XEXP (cond, 0);
5098 /* Simplify X, a SET expression. Return the new expression. */
5101 simplify_set (rtx x)
5103 rtx src = SET_SRC (x);
5104 rtx dest = SET_DEST (x);
5105 enum machine_mode mode
5106 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5110 /* (set (pc) (return)) gets written as (return). */
5111 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5114 /* Now that we know for sure which bits of SRC we are using, see if we can
5115 simplify the expression for the object knowing that we only need the
5118 if (GET_MODE_CLASS (mode) == MODE_INT
5119 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5121 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5122 SUBST (SET_SRC (x), src);
5125 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5126 the comparison result and try to simplify it unless we already have used
5127 undobuf.other_insn. */
5128 if ((GET_MODE_CLASS (mode) == MODE_CC
5129 || GET_CODE (src) == COMPARE
5131 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5132 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5133 && COMPARISON_P (*cc_use)
5134 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5136 enum rtx_code old_code = GET_CODE (*cc_use);
5137 enum rtx_code new_code;
5139 int other_changed = 0;
5140 enum machine_mode compare_mode = GET_MODE (dest);
5142 if (GET_CODE (src) == COMPARE)
5143 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5145 op0 = src, op1 = const0_rtx;
5147 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5150 new_code = old_code;
5151 else if (!CONSTANT_P (tmp))
5153 new_code = GET_CODE (tmp);
5154 op0 = XEXP (tmp, 0);
5155 op1 = XEXP (tmp, 1);
5159 rtx pat = PATTERN (other_insn);
5160 undobuf.other_insn = other_insn;
5161 SUBST (*cc_use, tmp);
5163 /* Attempt to simplify CC user. */
5164 if (GET_CODE (pat) == SET)
5166 rtx new = simplify_rtx (SET_SRC (pat));
5167 if (new != NULL_RTX)
5168 SUBST (SET_SRC (pat), new);
5171 /* Convert X into a no-op move. */
5172 SUBST (SET_DEST (x), pc_rtx);
5173 SUBST (SET_SRC (x), pc_rtx);
5177 /* Simplify our comparison, if possible. */
5178 new_code = simplify_comparison (new_code, &op0, &op1);
5180 #ifdef SELECT_CC_MODE
5181 /* If this machine has CC modes other than CCmode, check to see if we
5182 need to use a different CC mode here. */
5183 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5184 compare_mode = GET_MODE (op0);
5186 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5189 /* If the mode changed, we have to change SET_DEST, the mode in the
5190 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5191 a hard register, just build new versions with the proper mode. If it
5192 is a pseudo, we lose unless it is only time we set the pseudo, in
5193 which case we can safely change its mode. */
5194 if (compare_mode != GET_MODE (dest))
5196 unsigned int regno = REGNO (dest);
5197 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5199 if (regno < FIRST_PSEUDO_REGISTER
5200 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5202 if (regno >= FIRST_PSEUDO_REGISTER)
5203 SUBST (regno_reg_rtx[regno], new_dest);
5205 SUBST (SET_DEST (x), new_dest);
5206 SUBST (XEXP (*cc_use, 0), new_dest);
5213 #endif /* SELECT_CC_MODE */
5215 /* If the code changed, we have to build a new comparison in
5216 undobuf.other_insn. */
5217 if (new_code != old_code)
5219 int other_changed_previously = other_changed;
5220 unsigned HOST_WIDE_INT mask;
5222 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5226 /* If the only change we made was to change an EQ into an NE or
5227 vice versa, OP0 has only one bit that might be nonzero, and OP1
5228 is zero, check if changing the user of the condition code will
5229 produce a valid insn. If it won't, we can keep the original code
5230 in that insn by surrounding our operation with an XOR. */
5232 if (((old_code == NE && new_code == EQ)
5233 || (old_code == EQ && new_code == NE))
5234 && ! other_changed_previously && op1 == const0_rtx
5235 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5236 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5238 rtx pat = PATTERN (other_insn), note = 0;
5240 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5241 && ! check_asm_operands (pat)))
5243 PUT_CODE (*cc_use, old_code);
5246 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5252 undobuf.other_insn = other_insn;
5255 /* If we are now comparing against zero, change our source if
5256 needed. If we do not use cc0, we always have a COMPARE. */
5257 if (op1 == const0_rtx && dest == cc0_rtx)
5259 SUBST (SET_SRC (x), op0);
5265 /* Otherwise, if we didn't previously have a COMPARE in the
5266 correct mode, we need one. */
5267 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5269 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5274 /* Otherwise, update the COMPARE if needed. */
5275 SUBST (XEXP (src, 0), op0);
5276 SUBST (XEXP (src, 1), op1);
5281 /* Get SET_SRC in a form where we have placed back any
5282 compound expressions. Then do the checks below. */
5283 src = make_compound_operation (src, SET);
5284 SUBST (SET_SRC (x), src);
5287 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5288 and X being a REG or (subreg (reg)), we may be able to convert this to
5289 (set (subreg:m2 x) (op)).
5291 We can always do this if M1 is narrower than M2 because that means that
5292 we only care about the low bits of the result.
5294 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5295 perform a narrower operation than requested since the high-order bits will
5296 be undefined. On machine where it is defined, this transformation is safe
5297 as long as M1 and M2 have the same number of words. */
5299 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5300 && !OBJECT_P (SUBREG_REG (src))
5301 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5303 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5304 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5305 #ifndef WORD_REGISTER_OPERATIONS
5306 && (GET_MODE_SIZE (GET_MODE (src))
5307 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5309 #ifdef CANNOT_CHANGE_MODE_CLASS
5310 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5311 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5312 GET_MODE (SUBREG_REG (src)),
5316 || (GET_CODE (dest) == SUBREG
5317 && REG_P (SUBREG_REG (dest)))))
5319 SUBST (SET_DEST (x),
5320 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5322 SUBST (SET_SRC (x), SUBREG_REG (src));
5324 src = SET_SRC (x), dest = SET_DEST (x);
5328 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5331 && GET_CODE (src) == SUBREG
5332 && subreg_lowpart_p (src)
5333 && (GET_MODE_BITSIZE (GET_MODE (src))
5334 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5336 rtx inner = SUBREG_REG (src);
5337 enum machine_mode inner_mode = GET_MODE (inner);
5339 /* Here we make sure that we don't have a sign bit on. */
5340 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5341 && (nonzero_bits (inner, inner_mode)
5342 < ((unsigned HOST_WIDE_INT) 1
5343 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5345 SUBST (SET_SRC (x), inner);
5351 #ifdef LOAD_EXTEND_OP
5352 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5353 would require a paradoxical subreg. Replace the subreg with a
5354 zero_extend to avoid the reload that would otherwise be required. */
5356 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5357 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5358 && SUBREG_BYTE (src) == 0
5359 && (GET_MODE_SIZE (GET_MODE (src))
5360 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5361 && MEM_P (SUBREG_REG (src)))
5364 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5365 GET_MODE (src), SUBREG_REG (src)));
5371 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5372 are comparing an item known to be 0 or -1 against 0, use a logical
5373 operation instead. Check for one of the arms being an IOR of the other
5374 arm with some value. We compute three terms to be IOR'ed together. In
5375 practice, at most two will be nonzero. Then we do the IOR's. */
5377 if (GET_CODE (dest) != PC
5378 && GET_CODE (src) == IF_THEN_ELSE
5379 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5380 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5381 && XEXP (XEXP (src, 0), 1) == const0_rtx
5382 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5383 #ifdef HAVE_conditional_move
5384 && ! can_conditionally_move_p (GET_MODE (src))
5386 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5387 GET_MODE (XEXP (XEXP (src, 0), 0)))
5388 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5389 && ! side_effects_p (src))
5391 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5392 ? XEXP (src, 1) : XEXP (src, 2));
5393 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5394 ? XEXP (src, 2) : XEXP (src, 1));
5395 rtx term1 = const0_rtx, term2, term3;
5397 if (GET_CODE (true_rtx) == IOR
5398 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5399 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5400 else if (GET_CODE (true_rtx) == IOR
5401 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5402 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5403 else if (GET_CODE (false_rtx) == IOR
5404 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5405 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5406 else if (GET_CODE (false_rtx) == IOR
5407 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5408 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5410 term2 = gen_binary (AND, GET_MODE (src),
5411 XEXP (XEXP (src, 0), 0), true_rtx);
5412 term3 = gen_binary (AND, GET_MODE (src),
5413 simplify_gen_unary (NOT, GET_MODE (src),
5414 XEXP (XEXP (src, 0), 0),
5419 gen_binary (IOR, GET_MODE (src),
5420 gen_binary (IOR, GET_MODE (src), term1, term2),
5426 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5427 whole thing fail. */
5428 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5430 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5433 /* Convert this into a field assignment operation, if possible. */
5434 return make_field_assignment (x);
5437 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5441 simplify_logical (rtx x)
5443 enum machine_mode mode = GET_MODE (x);
5444 rtx op0 = XEXP (x, 0);
5445 rtx op1 = XEXP (x, 1);
5448 switch (GET_CODE (x))
5451 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5452 insn (and may simplify more). */
5453 if (GET_CODE (op0) == XOR
5454 && rtx_equal_p (XEXP (op0, 0), op1)
5455 && ! side_effects_p (op1))
5456 x = gen_binary (AND, mode,
5457 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5460 if (GET_CODE (op0) == XOR
5461 && rtx_equal_p (XEXP (op0, 1), op1)
5462 && ! side_effects_p (op1))
5463 x = gen_binary (AND, mode,
5464 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5467 /* Similarly for (~(A ^ B)) & A. */
5468 if (GET_CODE (op0) == NOT
5469 && GET_CODE (XEXP (op0, 0)) == XOR
5470 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5471 && ! side_effects_p (op1))
5472 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5474 if (GET_CODE (op0) == NOT
5475 && GET_CODE (XEXP (op0, 0)) == XOR
5476 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5477 && ! side_effects_p (op1))
5478 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5480 /* We can call simplify_and_const_int only if we don't lose
5481 any (sign) bits when converting INTVAL (op1) to
5482 "unsigned HOST_WIDE_INT". */
5483 if (GET_CODE (op1) == CONST_INT
5484 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5485 || INTVAL (op1) > 0))
5487 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5489 /* If we have (ior (and (X C1) C2)) and the next restart would be
5490 the last, simplify this by making C1 as small as possible
5491 and then exit. Only do this if C1 actually changes: for now
5492 this only saves memory but, should this transformation be
5493 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5494 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5495 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5496 && GET_CODE (op1) == CONST_INT
5497 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5498 return gen_binary (IOR, mode,
5499 gen_binary (AND, mode, XEXP (op0, 0),
5500 GEN_INT (INTVAL (XEXP (op0, 1))
5501 & ~INTVAL (op1))), op1);
5503 if (GET_CODE (x) != AND)
5510 /* Convert (A | B) & A to A. */
5511 if (GET_CODE (op0) == IOR
5512 && (rtx_equal_p (XEXP (op0, 0), op1)
5513 || rtx_equal_p (XEXP (op0, 1), op1))
5514 && ! side_effects_p (XEXP (op0, 0))
5515 && ! side_effects_p (XEXP (op0, 1)))
5518 /* In the following group of tests (and those in case IOR below),
5519 we start with some combination of logical operations and apply
5520 the distributive law followed by the inverse distributive law.
5521 Most of the time, this results in no change. However, if some of
5522 the operands are the same or inverses of each other, simplifications
5525 For example, (and (ior A B) (not B)) can occur as the result of
5526 expanding a bit field assignment. When we apply the distributive
5527 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5528 which then simplifies to (and (A (not B))).
5530 If we have (and (ior A B) C), apply the distributive law and then
5531 the inverse distributive law to see if things simplify. */
5533 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5535 x = apply_distributive_law
5536 (gen_binary (GET_CODE (op0), mode,
5537 gen_binary (AND, mode, XEXP (op0, 0), op1),
5538 gen_binary (AND, mode, XEXP (op0, 1),
5540 if (GET_CODE (x) != AND)
5544 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5545 return apply_distributive_law
5546 (gen_binary (GET_CODE (op1), mode,
5547 gen_binary (AND, mode, XEXP (op1, 0), op0),
5548 gen_binary (AND, mode, XEXP (op1, 1),
5551 /* Similarly, taking advantage of the fact that
5552 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5554 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5555 return apply_distributive_law
5556 (gen_binary (XOR, mode,
5557 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5558 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5561 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5562 return apply_distributive_law
5563 (gen_binary (XOR, mode,
5564 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5565 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5569 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5570 if (GET_CODE (op1) == CONST_INT
5571 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5572 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5575 /* Convert (A & B) | A to A. */
5576 if (GET_CODE (op0) == AND
5577 && (rtx_equal_p (XEXP (op0, 0), op1)
5578 || rtx_equal_p (XEXP (op0, 1), op1))
5579 && ! side_effects_p (XEXP (op0, 0))
5580 && ! side_effects_p (XEXP (op0, 1)))
5583 /* If we have (ior (and A B) C), apply the distributive law and then
5584 the inverse distributive law to see if things simplify. */
5586 if (GET_CODE (op0) == AND)
5588 x = apply_distributive_law
5589 (gen_binary (AND, mode,
5590 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5591 gen_binary (IOR, mode, XEXP (op0, 1),
5594 if (GET_CODE (x) != IOR)
5598 if (GET_CODE (op1) == AND)
5600 x = apply_distributive_law
5601 (gen_binary (AND, mode,
5602 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5603 gen_binary (IOR, mode, XEXP (op1, 1),
5606 if (GET_CODE (x) != IOR)
5610 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5611 mode size to (rotate A CX). */
5613 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5614 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5615 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5616 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5617 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5618 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5619 == GET_MODE_BITSIZE (mode)))
5620 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5621 (GET_CODE (op0) == ASHIFT
5622 ? XEXP (op0, 1) : XEXP (op1, 1)));
5624 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5625 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5626 does not affect any of the bits in OP1, it can really be done
5627 as a PLUS and we can associate. We do this by seeing if OP1
5628 can be safely shifted left C bits. */
5629 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5630 && GET_CODE (XEXP (op0, 0)) == PLUS
5631 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5632 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5633 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5635 int count = INTVAL (XEXP (op0, 1));
5636 HOST_WIDE_INT mask = INTVAL (op1) << count;
5638 if (mask >> count == INTVAL (op1)
5639 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5641 SUBST (XEXP (XEXP (op0, 0), 1),
5642 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5649 /* If we are XORing two things that have no bits in common,
5650 convert them into an IOR. This helps to detect rotation encoded
5651 using those methods and possibly other simplifications. */
5653 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5654 && (nonzero_bits (op0, mode)
5655 & nonzero_bits (op1, mode)) == 0)
5656 return (gen_binary (IOR, mode, op0, op1));
5658 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5659 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5662 int num_negated = 0;
5664 if (GET_CODE (op0) == NOT)
5665 num_negated++, op0 = XEXP (op0, 0);
5666 if (GET_CODE (op1) == NOT)
5667 num_negated++, op1 = XEXP (op1, 0);
5669 if (num_negated == 2)
5671 SUBST (XEXP (x, 0), op0);
5672 SUBST (XEXP (x, 1), op1);
5674 else if (num_negated == 1)
5676 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5680 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5681 correspond to a machine insn or result in further simplifications
5682 if B is a constant. */
5684 if (GET_CODE (op0) == AND
5685 && rtx_equal_p (XEXP (op0, 1), op1)
5686 && ! side_effects_p (op1))
5687 return gen_binary (AND, mode,
5688 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5691 else if (GET_CODE (op0) == AND
5692 && rtx_equal_p (XEXP (op0, 0), op1)
5693 && ! side_effects_p (op1))
5694 return gen_binary (AND, mode,
5695 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5698 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5699 comparison if STORE_FLAG_VALUE is 1. */
5700 if (STORE_FLAG_VALUE == 1
5701 && op1 == const1_rtx
5702 && COMPARISON_P (op0)
5703 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5707 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5708 is (lt foo (const_int 0)), so we can perform the above
5709 simplification if STORE_FLAG_VALUE is 1. */
5711 if (STORE_FLAG_VALUE == 1
5712 && op1 == const1_rtx
5713 && GET_CODE (op0) == LSHIFTRT
5714 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5715 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5716 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5718 /* (xor (comparison foo bar) (const_int sign-bit))
5719 when STORE_FLAG_VALUE is the sign bit. */
5720 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5721 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5722 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5723 && op1 == const_true_rtx
5724 && COMPARISON_P (op0)
5725 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5738 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5739 operations" because they can be replaced with two more basic operations.
5740 ZERO_EXTEND is also considered "compound" because it can be replaced with
5741 an AND operation, which is simpler, though only one operation.
5743 The function expand_compound_operation is called with an rtx expression
5744 and will convert it to the appropriate shifts and AND operations,
5745 simplifying at each stage.
5747 The function make_compound_operation is called to convert an expression
5748 consisting of shifts and ANDs into the equivalent compound expression.
5749 It is the inverse of this function, loosely speaking. */
5752 expand_compound_operation (rtx x)
5754 unsigned HOST_WIDE_INT pos = 0, len;
5756 unsigned int modewidth;
5759 switch (GET_CODE (x))
5764 /* We can't necessarily use a const_int for a multiword mode;
5765 it depends on implicitly extending the value.
5766 Since we don't know the right way to extend it,
5767 we can't tell whether the implicit way is right.
5769 Even for a mode that is no wider than a const_int,
5770 we can't win, because we need to sign extend one of its bits through
5771 the rest of it, and we don't know which bit. */
5772 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5775 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5776 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5777 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5778 reloaded. If not for that, MEM's would very rarely be safe.
5780 Reject MODEs bigger than a word, because we might not be able
5781 to reference a two-register group starting with an arbitrary register
5782 (and currently gen_lowpart might crash for a SUBREG). */
5784 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5787 /* Reject MODEs that aren't scalar integers because turning vector
5788 or complex modes into shifts causes problems. */
5790 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5793 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5794 /* If the inner object has VOIDmode (the only way this can happen
5795 is if it is an ASM_OPERANDS), we can't do anything since we don't
5796 know how much masking to do. */
5805 /* If the operand is a CLOBBER, just return it. */
5806 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5809 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5810 || GET_CODE (XEXP (x, 2)) != CONST_INT
5811 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5814 /* Reject MODEs that aren't scalar integers because turning vector
5815 or complex modes into shifts causes problems. */
5817 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5820 len = INTVAL (XEXP (x, 1));
5821 pos = INTVAL (XEXP (x, 2));
5823 /* If this goes outside the object being extracted, replace the object
5824 with a (use (mem ...)) construct that only combine understands
5825 and is used only for this purpose. */
5826 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5827 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5829 if (BITS_BIG_ENDIAN)
5830 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5837 /* Convert sign extension to zero extension, if we know that the high
5838 bit is not set, as this is easier to optimize. It will be converted
5839 back to cheaper alternative in make_extraction. */
5840 if (GET_CODE (x) == SIGN_EXTEND
5841 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5842 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5843 & ~(((unsigned HOST_WIDE_INT)
5844 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5848 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5849 rtx temp2 = expand_compound_operation (temp);
5851 /* Make sure this is a profitable operation. */
5852 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5854 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5860 /* We can optimize some special cases of ZERO_EXTEND. */
5861 if (GET_CODE (x) == ZERO_EXTEND)
5863 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5864 know that the last value didn't have any inappropriate bits
5866 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5867 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5868 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5869 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5870 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5871 return XEXP (XEXP (x, 0), 0);
5873 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5874 if (GET_CODE (XEXP (x, 0)) == SUBREG
5875 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5876 && subreg_lowpart_p (XEXP (x, 0))
5877 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5878 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5879 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5880 return SUBREG_REG (XEXP (x, 0));
5882 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5883 is a comparison and STORE_FLAG_VALUE permits. This is like
5884 the first case, but it works even when GET_MODE (x) is larger
5885 than HOST_WIDE_INT. */
5886 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5887 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5888 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5889 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5890 <= HOST_BITS_PER_WIDE_INT)
5891 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5892 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5893 return XEXP (XEXP (x, 0), 0);
5895 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5896 if (GET_CODE (XEXP (x, 0)) == SUBREG
5897 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5898 && subreg_lowpart_p (XEXP (x, 0))
5899 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5900 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5901 <= HOST_BITS_PER_WIDE_INT)
5902 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5903 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5904 return SUBREG_REG (XEXP (x, 0));
5908 /* If we reach here, we want to return a pair of shifts. The inner
5909 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5910 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5911 logical depending on the value of UNSIGNEDP.
5913 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5914 converted into an AND of a shift.
5916 We must check for the case where the left shift would have a negative
5917 count. This can happen in a case like (x >> 31) & 255 on machines
5918 that can't shift by a constant. On those machines, we would first
5919 combine the shift with the AND to produce a variable-position
5920 extraction. Then the constant of 31 would be substituted in to produce
5921 a such a position. */
5923 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5924 if (modewidth + len >= pos)
5925 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5927 simplify_shift_const (NULL_RTX, ASHIFT,
5930 modewidth - pos - len),
5933 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5934 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5935 simplify_shift_const (NULL_RTX, LSHIFTRT,
5938 ((HOST_WIDE_INT) 1 << len) - 1);
5940 /* Any other cases we can't handle. */
5943 /* If we couldn't do this for some reason, return the original
5945 if (GET_CODE (tem) == CLOBBER)
5951 /* X is a SET which contains an assignment of one object into
5952 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5953 or certain SUBREGS). If possible, convert it into a series of
5956 We half-heartedly support variable positions, but do not at all
5957 support variable lengths. */
5960 expand_field_assignment (rtx x)
5963 rtx pos; /* Always counts from low bit. */
5966 enum machine_mode compute_mode;
5968 /* Loop until we find something we can't simplify. */
5971 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5972 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5974 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5975 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5976 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5978 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5979 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5981 inner = XEXP (SET_DEST (x), 0);
5982 len = INTVAL (XEXP (SET_DEST (x), 1));
5983 pos = XEXP (SET_DEST (x), 2);
5985 /* If the position is constant and spans the width of INNER,
5986 surround INNER with a USE to indicate this. */
5987 if (GET_CODE (pos) == CONST_INT
5988 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5989 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5991 if (BITS_BIG_ENDIAN)
5993 if (GET_CODE (pos) == CONST_INT)
5994 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5996 else if (GET_CODE (pos) == MINUS
5997 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5998 && (INTVAL (XEXP (pos, 1))
5999 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6000 /* If position is ADJUST - X, new position is X. */
6001 pos = XEXP (pos, 0);
6003 pos = gen_binary (MINUS, GET_MODE (pos),
6004 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
6010 /* A SUBREG between two modes that occupy the same numbers of words
6011 can be done by moving the SUBREG to the source. */
6012 else if (GET_CODE (SET_DEST (x)) == SUBREG
6013 /* We need SUBREGs to compute nonzero_bits properly. */
6014 && nonzero_sign_valid
6015 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6016 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6017 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6018 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6020 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6022 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6029 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6030 inner = SUBREG_REG (inner);
6032 compute_mode = GET_MODE (inner);
6034 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6035 if (! SCALAR_INT_MODE_P (compute_mode))
6037 enum machine_mode imode;
6039 /* Don't do anything for vector or complex integral types. */
6040 if (! FLOAT_MODE_P (compute_mode))
6043 /* Try to find an integral mode to pun with. */
6044 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6045 if (imode == BLKmode)
6048 compute_mode = imode;
6049 inner = gen_lowpart (imode, inner);
6052 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6053 if (len < HOST_BITS_PER_WIDE_INT)
6054 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6058 /* Now compute the equivalent expression. Make a copy of INNER
6059 for the SET_DEST in case it is a MEM into which we will substitute;
6060 we don't want shared RTL in that case. */
6062 (VOIDmode, copy_rtx (inner),
6063 gen_binary (IOR, compute_mode,
6064 gen_binary (AND, compute_mode,
6065 simplify_gen_unary (NOT, compute_mode,
6071 gen_binary (ASHIFT, compute_mode,
6072 gen_binary (AND, compute_mode,
6074 (compute_mode, SET_SRC (x)),
6082 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6083 it is an RTX that represents a variable starting position; otherwise,
6084 POS is the (constant) starting bit position (counted from the LSB).
6086 INNER may be a USE. This will occur when we started with a bitfield
6087 that went outside the boundary of the object in memory, which is
6088 allowed on most machines. To isolate this case, we produce a USE
6089 whose mode is wide enough and surround the MEM with it. The only
6090 code that understands the USE is this routine. If it is not removed,
6091 it will cause the resulting insn not to match.
6093 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6096 IN_DEST is nonzero if this is a reference in the destination of a
6097 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6098 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6101 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6102 ZERO_EXTRACT should be built even for bits starting at bit 0.
6104 MODE is the desired mode of the result (if IN_DEST == 0).
6106 The result is an RTX for the extraction or NULL_RTX if the target
6110 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6111 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6112 int in_dest, int in_compare)
6114 /* This mode describes the size of the storage area
6115 to fetch the overall value from. Within that, we
6116 ignore the POS lowest bits, etc. */
6117 enum machine_mode is_mode = GET_MODE (inner);
6118 enum machine_mode inner_mode;
6119 enum machine_mode wanted_inner_mode = byte_mode;
6120 enum machine_mode wanted_inner_reg_mode = word_mode;
6121 enum machine_mode pos_mode = word_mode;
6122 enum machine_mode extraction_mode = word_mode;
6123 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6126 rtx orig_pos_rtx = pos_rtx;
6127 HOST_WIDE_INT orig_pos;
6129 /* Get some information about INNER and get the innermost object. */
6130 if (GET_CODE (inner) == USE)
6131 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6132 /* We don't need to adjust the position because we set up the USE
6133 to pretend that it was a full-word object. */
6134 spans_byte = 1, inner = XEXP (inner, 0);
6135 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6137 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6138 consider just the QI as the memory to extract from.
6139 The subreg adds or removes high bits; its mode is
6140 irrelevant to the meaning of this extraction,
6141 since POS and LEN count from the lsb. */
6142 if (MEM_P (SUBREG_REG (inner)))
6143 is_mode = GET_MODE (SUBREG_REG (inner));
6144 inner = SUBREG_REG (inner);
6146 else if (GET_CODE (inner) == ASHIFT
6147 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6148 && pos_rtx == 0 && pos == 0
6149 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6151 /* We're extracting the least significant bits of an rtx
6152 (ashift X (const_int C)), where LEN > C. Extract the
6153 least significant (LEN - C) bits of X, giving an rtx
6154 whose mode is MODE, then shift it left C times. */
6155 new = make_extraction (mode, XEXP (inner, 0),
6156 0, 0, len - INTVAL (XEXP (inner, 1)),
6157 unsignedp, in_dest, in_compare);
6159 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6162 inner_mode = GET_MODE (inner);
6164 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6165 pos = INTVAL (pos_rtx), pos_rtx = 0;
6167 /* See if this can be done without an extraction. We never can if the
6168 width of the field is not the same as that of some integer mode. For
6169 registers, we can only avoid the extraction if the position is at the
6170 low-order bit and this is either not in the destination or we have the
6171 appropriate STRICT_LOW_PART operation available.
6173 For MEM, we can avoid an extract if the field starts on an appropriate
6174 boundary and we can change the mode of the memory reference. However,
6175 we cannot directly access the MEM if we have a USE and the underlying
6176 MEM is not TMODE. This combination means that MEM was being used in a
6177 context where bits outside its mode were being referenced; that is only
6178 valid in bit-field insns. */
6180 if (tmode != BLKmode
6181 && ! (spans_byte && inner_mode != tmode)
6182 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6186 && have_insn_for (STRICT_LOW_PART, tmode))))
6187 || (MEM_P (inner) && pos_rtx == 0
6189 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6190 : BITS_PER_UNIT)) == 0
6191 /* We can't do this if we are widening INNER_MODE (it
6192 may not be aligned, for one thing). */
6193 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6194 && (inner_mode == tmode
6195 || (! mode_dependent_address_p (XEXP (inner, 0))
6196 && ! MEM_VOLATILE_P (inner))))))
6198 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6199 field. If the original and current mode are the same, we need not
6200 adjust the offset. Otherwise, we do if bytes big endian.
6202 If INNER is not a MEM, get a piece consisting of just the field
6203 of interest (in this case POS % BITS_PER_WORD must be 0). */
6207 HOST_WIDE_INT offset;
6209 /* POS counts from lsb, but make OFFSET count in memory order. */
6210 if (BYTES_BIG_ENDIAN)
6211 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6213 offset = pos / BITS_PER_UNIT;
6215 new = adjust_address_nv (inner, tmode, offset);
6217 else if (REG_P (inner))
6219 if (tmode != inner_mode)
6221 /* We can't call gen_lowpart in a DEST since we
6222 always want a SUBREG (see below) and it would sometimes
6223 return a new hard register. */
6226 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6228 if (WORDS_BIG_ENDIAN
6229 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6230 final_word = ((GET_MODE_SIZE (inner_mode)
6231 - GET_MODE_SIZE (tmode))
6232 / UNITS_PER_WORD) - final_word;
6234 final_word *= UNITS_PER_WORD;
6235 if (BYTES_BIG_ENDIAN &&
6236 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6237 final_word += (GET_MODE_SIZE (inner_mode)
6238 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6240 /* Avoid creating invalid subregs, for example when
6241 simplifying (x>>32)&255. */
6242 if (final_word >= GET_MODE_SIZE (inner_mode))
6245 new = gen_rtx_SUBREG (tmode, inner, final_word);
6248 new = gen_lowpart (tmode, inner);
6254 new = force_to_mode (inner, tmode,
6255 len >= HOST_BITS_PER_WIDE_INT
6256 ? ~(unsigned HOST_WIDE_INT) 0
6257 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6260 /* If this extraction is going into the destination of a SET,
6261 make a STRICT_LOW_PART unless we made a MEM. */
6264 return (MEM_P (new) ? new
6265 : (GET_CODE (new) != SUBREG
6266 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6267 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6272 if (GET_CODE (new) == CONST_INT)
6273 return gen_int_mode (INTVAL (new), mode);
6275 /* If we know that no extraneous bits are set, and that the high
6276 bit is not set, convert the extraction to the cheaper of
6277 sign and zero extension, that are equivalent in these cases. */
6278 if (flag_expensive_optimizations
6279 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6280 && ((nonzero_bits (new, tmode)
6281 & ~(((unsigned HOST_WIDE_INT)
6282 GET_MODE_MASK (tmode))
6286 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6287 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6289 /* Prefer ZERO_EXTENSION, since it gives more information to
6291 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6296 /* Otherwise, sign- or zero-extend unless we already are in the
6299 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6303 /* Unless this is a COMPARE or we have a funny memory reference,
6304 don't do anything with zero-extending field extracts starting at
6305 the low-order bit since they are simple AND operations. */
6306 if (pos_rtx == 0 && pos == 0 && ! in_dest
6307 && ! in_compare && ! spans_byte && unsignedp)
6310 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6311 we would be spanning bytes or if the position is not a constant and the
6312 length is not 1. In all other cases, we would only be going outside
6313 our object in cases when an original shift would have been
6315 if (! spans_byte && MEM_P (inner)
6316 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6317 || (pos_rtx != 0 && len != 1)))
6320 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6321 and the mode for the result. */
6322 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6324 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6325 pos_mode = mode_for_extraction (EP_insv, 2);
6326 extraction_mode = mode_for_extraction (EP_insv, 3);
6329 if (! in_dest && unsignedp
6330 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6332 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6333 pos_mode = mode_for_extraction (EP_extzv, 3);
6334 extraction_mode = mode_for_extraction (EP_extzv, 0);
6337 if (! in_dest && ! unsignedp
6338 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6340 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6341 pos_mode = mode_for_extraction (EP_extv, 3);
6342 extraction_mode = mode_for_extraction (EP_extv, 0);
6345 /* Never narrow an object, since that might not be safe. */
6347 if (mode != VOIDmode
6348 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6349 extraction_mode = mode;
6351 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6352 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6353 pos_mode = GET_MODE (pos_rtx);
6355 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6356 if we have to change the mode of memory and cannot, the desired mode is
6359 wanted_inner_mode = wanted_inner_reg_mode;
6360 else if (inner_mode != wanted_inner_mode
6361 && (mode_dependent_address_p (XEXP (inner, 0))
6362 || MEM_VOLATILE_P (inner)))
6363 wanted_inner_mode = extraction_mode;
6367 if (BITS_BIG_ENDIAN)
6369 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6370 BITS_BIG_ENDIAN style. If position is constant, compute new
6371 position. Otherwise, build subtraction.
6372 Note that POS is relative to the mode of the original argument.
6373 If it's a MEM we need to recompute POS relative to that.
6374 However, if we're extracting from (or inserting into) a register,
6375 we want to recompute POS relative to wanted_inner_mode. */
6376 int width = (MEM_P (inner)
6377 ? GET_MODE_BITSIZE (is_mode)
6378 : GET_MODE_BITSIZE (wanted_inner_mode));
6381 pos = width - len - pos;
6384 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6385 /* POS may be less than 0 now, but we check for that below.
6386 Note that it can only be less than 0 if !MEM_P (inner). */
6389 /* If INNER has a wider mode, make it smaller. If this is a constant
6390 extract, try to adjust the byte to point to the byte containing
6392 if (wanted_inner_mode != VOIDmode
6393 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6395 && (inner_mode == wanted_inner_mode
6396 || (! mode_dependent_address_p (XEXP (inner, 0))
6397 && ! MEM_VOLATILE_P (inner))))))
6401 /* The computations below will be correct if the machine is big
6402 endian in both bits and bytes or little endian in bits and bytes.
6403 If it is mixed, we must adjust. */
6405 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6406 adjust OFFSET to compensate. */
6407 if (BYTES_BIG_ENDIAN
6409 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6410 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6412 /* If this is a constant position, we can move to the desired byte. */
6415 offset += pos / BITS_PER_UNIT;
6416 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6419 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6421 && is_mode != wanted_inner_mode)
6422 offset = (GET_MODE_SIZE (is_mode)
6423 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6425 if (offset != 0 || inner_mode != wanted_inner_mode)
6426 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6429 /* If INNER is not memory, we can always get it into the proper mode. If we
6430 are changing its mode, POS must be a constant and smaller than the size
6432 else if (!MEM_P (inner))
6434 if (GET_MODE (inner) != wanted_inner_mode
6436 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6439 inner = force_to_mode (inner, wanted_inner_mode,
6441 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6442 ? ~(unsigned HOST_WIDE_INT) 0
6443 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6448 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6449 have to zero extend. Otherwise, we can just use a SUBREG. */
6451 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6453 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6455 /* If we know that no extraneous bits are set, and that the high
6456 bit is not set, convert extraction to cheaper one - either
6457 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6459 if (flag_expensive_optimizations
6460 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6461 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6462 & ~(((unsigned HOST_WIDE_INT)
6463 GET_MODE_MASK (GET_MODE (pos_rtx)))
6467 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6469 /* Prefer ZERO_EXTENSION, since it gives more information to
6471 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6476 else if (pos_rtx != 0
6477 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6478 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6480 /* Make POS_RTX unless we already have it and it is correct. If we don't
6481 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6483 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6484 pos_rtx = orig_pos_rtx;
6486 else if (pos_rtx == 0)
6487 pos_rtx = GEN_INT (pos);
6489 /* Make the required operation. See if we can use existing rtx. */
6490 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6491 extraction_mode, inner, GEN_INT (len), pos_rtx);
6493 new = gen_lowpart (mode, new);
6498 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6499 with any other operations in X. Return X without that shift if so. */
6502 extract_left_shift (rtx x, int count)
6504 enum rtx_code code = GET_CODE (x);
6505 enum machine_mode mode = GET_MODE (x);
6511 /* This is the shift itself. If it is wide enough, we will return
6512 either the value being shifted if the shift count is equal to
6513 COUNT or a shift for the difference. */
6514 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6515 && INTVAL (XEXP (x, 1)) >= count)
6516 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6517 INTVAL (XEXP (x, 1)) - count);
6521 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6522 return simplify_gen_unary (code, mode, tem, mode);
6526 case PLUS: case IOR: case XOR: case AND:
6527 /* If we can safely shift this constant and we find the inner shift,
6528 make a new operation. */
6529 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6530 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6531 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6532 return gen_binary (code, mode, tem,
6533 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6544 /* Look at the expression rooted at X. Look for expressions
6545 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6546 Form these expressions.
6548 Return the new rtx, usually just X.
6550 Also, for machines like the VAX that don't have logical shift insns,
6551 try to convert logical to arithmetic shift operations in cases where
6552 they are equivalent. This undoes the canonicalizations to logical
6553 shifts done elsewhere.
6555 We try, as much as possible, to re-use rtl expressions to save memory.
6557 IN_CODE says what kind of expression we are processing. Normally, it is
6558 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6559 being kludges), it is MEM. When processing the arguments of a comparison
6560 or a COMPARE against zero, it is COMPARE. */
6563 make_compound_operation (rtx x, enum rtx_code in_code)
6565 enum rtx_code code = GET_CODE (x);
6566 enum machine_mode mode = GET_MODE (x);
6567 int mode_width = GET_MODE_BITSIZE (mode);
6569 enum rtx_code next_code;
6575 /* Select the code to be used in recursive calls. Once we are inside an
6576 address, we stay there. If we have a comparison, set to COMPARE,
6577 but once inside, go back to our default of SET. */
6579 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6580 : ((code == COMPARE || COMPARISON_P (x))
6581 && XEXP (x, 1) == const0_rtx) ? COMPARE
6582 : in_code == COMPARE ? SET : in_code);
6584 /* Process depending on the code of this operation. If NEW is set
6585 nonzero, it will be returned. */
6590 /* Convert shifts by constants into multiplications if inside
6592 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6593 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6594 && INTVAL (XEXP (x, 1)) >= 0)
6596 new = make_compound_operation (XEXP (x, 0), next_code);
6597 new = gen_rtx_MULT (mode, new,
6598 GEN_INT ((HOST_WIDE_INT) 1
6599 << INTVAL (XEXP (x, 1))));
6604 /* If the second operand is not a constant, we can't do anything
6606 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6609 /* If the constant is a power of two minus one and the first operand
6610 is a logical right shift, make an extraction. */
6611 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6612 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6614 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6615 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6616 0, in_code == COMPARE);
6619 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6620 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6621 && subreg_lowpart_p (XEXP (x, 0))
6622 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6623 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6625 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6627 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6628 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6629 0, in_code == COMPARE);
6631 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6632 else if ((GET_CODE (XEXP (x, 0)) == XOR
6633 || GET_CODE (XEXP (x, 0)) == IOR)
6634 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6635 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6636 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6638 /* Apply the distributive law, and then try to make extractions. */
6639 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6640 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6642 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6644 new = make_compound_operation (new, in_code);
6647 /* If we are have (and (rotate X C) M) and C is larger than the number
6648 of bits in M, this is an extraction. */
6650 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6651 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6652 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6653 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6655 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6656 new = make_extraction (mode, new,
6657 (GET_MODE_BITSIZE (mode)
6658 - INTVAL (XEXP (XEXP (x, 0), 1))),
6659 NULL_RTX, i, 1, 0, in_code == COMPARE);
6662 /* On machines without logical shifts, if the operand of the AND is
6663 a logical shift and our mask turns off all the propagated sign
6664 bits, we can replace the logical shift with an arithmetic shift. */
6665 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6666 && !have_insn_for (LSHIFTRT, mode)
6667 && have_insn_for (ASHIFTRT, mode)
6668 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6669 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6670 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6671 && mode_width <= HOST_BITS_PER_WIDE_INT)
6673 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6675 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6676 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6678 gen_rtx_ASHIFTRT (mode,
6679 make_compound_operation
6680 (XEXP (XEXP (x, 0), 0), next_code),
6681 XEXP (XEXP (x, 0), 1)));
6684 /* If the constant is one less than a power of two, this might be
6685 representable by an extraction even if no shift is present.
6686 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6687 we are in a COMPARE. */
6688 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6689 new = make_extraction (mode,
6690 make_compound_operation (XEXP (x, 0),
6692 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6694 /* If we are in a comparison and this is an AND with a power of two,
6695 convert this into the appropriate bit extract. */
6696 else if (in_code == COMPARE
6697 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6698 new = make_extraction (mode,
6699 make_compound_operation (XEXP (x, 0),
6701 i, NULL_RTX, 1, 1, 0, 1);
6706 /* If the sign bit is known to be zero, replace this with an
6707 arithmetic shift. */
6708 if (have_insn_for (ASHIFTRT, mode)
6709 && ! have_insn_for (LSHIFTRT, mode)
6710 && mode_width <= HOST_BITS_PER_WIDE_INT
6711 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6713 new = gen_rtx_ASHIFTRT (mode,
6714 make_compound_operation (XEXP (x, 0),
6720 /* ... fall through ... */
6726 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6727 this is a SIGN_EXTRACT. */
6728 if (GET_CODE (rhs) == CONST_INT
6729 && GET_CODE (lhs) == ASHIFT
6730 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6731 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6733 new = make_compound_operation (XEXP (lhs, 0), next_code);
6734 new = make_extraction (mode, new,
6735 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6736 NULL_RTX, mode_width - INTVAL (rhs),
6737 code == LSHIFTRT, 0, in_code == COMPARE);
6741 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6742 If so, try to merge the shifts into a SIGN_EXTEND. We could
6743 also do this for some cases of SIGN_EXTRACT, but it doesn't
6744 seem worth the effort; the case checked for occurs on Alpha. */
6747 && ! (GET_CODE (lhs) == SUBREG
6748 && (OBJECT_P (SUBREG_REG (lhs))))
6749 && GET_CODE (rhs) == CONST_INT
6750 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6751 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6752 new = make_extraction (mode, make_compound_operation (new, next_code),
6753 0, NULL_RTX, mode_width - INTVAL (rhs),
6754 code == LSHIFTRT, 0, in_code == COMPARE);
6759 /* Call ourselves recursively on the inner expression. If we are
6760 narrowing the object and it has a different RTL code from
6761 what it originally did, do this SUBREG as a force_to_mode. */
6763 tem = make_compound_operation (SUBREG_REG (x), in_code);
6764 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6765 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6766 && subreg_lowpart_p (x))
6768 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6771 /* If we have something other than a SUBREG, we might have
6772 done an expansion, so rerun ourselves. */
6773 if (GET_CODE (newer) != SUBREG)
6774 newer = make_compound_operation (newer, in_code);
6779 /* If this is a paradoxical subreg, and the new code is a sign or
6780 zero extension, omit the subreg and widen the extension. If it
6781 is a regular subreg, we can still get rid of the subreg by not
6782 widening so much, or in fact removing the extension entirely. */
6783 if ((GET_CODE (tem) == SIGN_EXTEND
6784 || GET_CODE (tem) == ZERO_EXTEND)
6785 && subreg_lowpart_p (x))
6787 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6788 || (GET_MODE_SIZE (mode) >
6789 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6791 if (! SCALAR_INT_MODE_P (mode))
6793 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6796 tem = gen_lowpart (mode, XEXP (tem, 0));
6807 x = gen_lowpart (mode, new);
6808 code = GET_CODE (x);
6811 /* Now recursively process each operand of this operation. */
6812 fmt = GET_RTX_FORMAT (code);
6813 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6816 new = make_compound_operation (XEXP (x, i), next_code);
6817 SUBST (XEXP (x, i), new);
6823 /* Given M see if it is a value that would select a field of bits
6824 within an item, but not the entire word. Return -1 if not.
6825 Otherwise, return the starting position of the field, where 0 is the
6828 *PLEN is set to the length of the field. */
6831 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6833 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6834 int pos = exact_log2 (m & -m);
6838 /* Now shift off the low-order zero bits and see if we have a
6839 power of two minus 1. */
6840 len = exact_log2 ((m >> pos) + 1);
6849 /* See if X can be simplified knowing that we will only refer to it in
6850 MODE and will only refer to those bits that are nonzero in MASK.
6851 If other bits are being computed or if masking operations are done
6852 that select a superset of the bits in MASK, they can sometimes be
6855 Return a possibly simplified expression, but always convert X to
6856 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6858 Also, if REG is nonzero and X is a register equal in value to REG,
6861 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6862 are all off in X. This is used when X will be complemented, by either
6863 NOT, NEG, or XOR. */
6866 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6867 rtx reg, int just_select)
6869 enum rtx_code code = GET_CODE (x);
6870 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6871 enum machine_mode op_mode;
6872 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6875 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6876 code below will do the wrong thing since the mode of such an
6877 expression is VOIDmode.
6879 Also do nothing if X is a CLOBBER; this can happen if X was
6880 the return value from a call to gen_lowpart. */
6881 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6884 /* We want to perform the operation is its present mode unless we know
6885 that the operation is valid in MODE, in which case we do the operation
6887 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6888 && have_insn_for (code, mode))
6889 ? mode : GET_MODE (x));
6891 /* It is not valid to do a right-shift in a narrower mode
6892 than the one it came in with. */
6893 if ((code == LSHIFTRT || code == ASHIFTRT)
6894 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6895 op_mode = GET_MODE (x);
6897 /* Truncate MASK to fit OP_MODE. */
6899 mask &= GET_MODE_MASK (op_mode);
6901 /* When we have an arithmetic operation, or a shift whose count we
6902 do not know, we need to assume that all bits up to the highest-order
6903 bit in MASK will be needed. This is how we form such a mask. */
6904 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6905 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6907 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6910 /* Determine what bits of X are guaranteed to be (non)zero. */
6911 nonzero = nonzero_bits (x, mode);
6913 /* If none of the bits in X are needed, return a zero. */
6914 if (! just_select && (nonzero & mask) == 0)
6917 /* If X is a CONST_INT, return a new one. Do this here since the
6918 test below will fail. */
6919 if (GET_CODE (x) == CONST_INT)
6921 if (SCALAR_INT_MODE_P (mode))
6922 return gen_int_mode (INTVAL (x) & mask, mode);
6925 x = GEN_INT (INTVAL (x) & mask);
6926 return gen_lowpart_common (mode, x);
6930 /* If X is narrower than MODE and we want all the bits in X's mode, just
6931 get X in the proper mode. */
6932 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6933 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6934 return gen_lowpart (mode, x);
6936 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6937 MASK are already known to be zero in X, we need not do anything. */
6938 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6944 /* If X is a (clobber (const_int)), return it since we know we are
6945 generating something that won't match. */
6949 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6950 spanned the boundary of the MEM. If we are now masking so it is
6951 within that boundary, we don't need the USE any more. */
6952 if (! BITS_BIG_ENDIAN
6953 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6954 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6961 x = expand_compound_operation (x);
6962 if (GET_CODE (x) != code)
6963 return force_to_mode (x, mode, mask, reg, next_select);
6967 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6968 || rtx_equal_p (reg, get_last_value (x))))
6973 if (subreg_lowpart_p (x)
6974 /* We can ignore the effect of this SUBREG if it narrows the mode or
6975 if the constant masks to zero all the bits the mode doesn't
6977 && ((GET_MODE_SIZE (GET_MODE (x))
6978 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6980 & GET_MODE_MASK (GET_MODE (x))
6981 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6982 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6986 /* If this is an AND with a constant, convert it into an AND
6987 whose constant is the AND of that constant with MASK. If it
6988 remains an AND of MASK, delete it since it is redundant. */
6990 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6992 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6993 mask & INTVAL (XEXP (x, 1)));
6995 /* If X is still an AND, see if it is an AND with a mask that
6996 is just some low-order bits. If so, and it is MASK, we don't
6999 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7000 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7004 /* If it remains an AND, try making another AND with the bits
7005 in the mode mask that aren't in MASK turned on. If the
7006 constant in the AND is wide enough, this might make a
7007 cheaper constant. */
7009 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7010 && GET_MODE_MASK (GET_MODE (x)) != mask
7011 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7013 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7014 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7015 int width = GET_MODE_BITSIZE (GET_MODE (x));
7018 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7019 number, sign extend it. */
7020 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7021 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7022 cval |= (HOST_WIDE_INT) -1 << width;
7024 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7025 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7035 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7036 low-order bits (as in an alignment operation) and FOO is already
7037 aligned to that boundary, mask C1 to that boundary as well.
7038 This may eliminate that PLUS and, later, the AND. */
7041 unsigned int width = GET_MODE_BITSIZE (mode);
7042 unsigned HOST_WIDE_INT smask = mask;
7044 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7045 number, sign extend it. */
7047 if (width < HOST_BITS_PER_WIDE_INT
7048 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7049 smask |= (HOST_WIDE_INT) -1 << width;
7051 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7052 && exact_log2 (- smask) >= 0
7053 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7054 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7055 return force_to_mode (plus_constant (XEXP (x, 0),
7056 (INTVAL (XEXP (x, 1)) & smask)),
7057 mode, smask, reg, next_select);
7060 /* ... fall through ... */
7063 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7064 most significant bit in MASK since carries from those bits will
7065 affect the bits we are interested in. */
7070 /* If X is (minus C Y) where C's least set bit is larger than any bit
7071 in the mask, then we may replace with (neg Y). */
7072 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7073 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7074 & -INTVAL (XEXP (x, 0))))
7077 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7079 return force_to_mode (x, mode, mask, reg, next_select);
7082 /* Similarly, if C contains every bit in the fuller_mask, then we may
7083 replace with (not Y). */
7084 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7085 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7086 == INTVAL (XEXP (x, 0))))
7088 x = simplify_gen_unary (NOT, GET_MODE (x),
7089 XEXP (x, 1), GET_MODE (x));
7090 return force_to_mode (x, mode, mask, reg, next_select);
7098 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7099 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7100 operation which may be a bitfield extraction. Ensure that the
7101 constant we form is not wider than the mode of X. */
7103 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7104 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7105 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7106 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7107 && GET_CODE (XEXP (x, 1)) == CONST_INT
7108 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7109 + floor_log2 (INTVAL (XEXP (x, 1))))
7110 < GET_MODE_BITSIZE (GET_MODE (x)))
7111 && (INTVAL (XEXP (x, 1))
7112 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7114 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7115 << INTVAL (XEXP (XEXP (x, 0), 1)));
7116 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7117 XEXP (XEXP (x, 0), 0), temp);
7118 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7119 XEXP (XEXP (x, 0), 1));
7120 return force_to_mode (x, mode, mask, reg, next_select);
7124 /* For most binary operations, just propagate into the operation and
7125 change the mode if we have an operation of that mode. */
7127 op0 = gen_lowpart (op_mode,
7128 force_to_mode (XEXP (x, 0), mode, mask,
7130 op1 = gen_lowpart (op_mode,
7131 force_to_mode (XEXP (x, 1), mode, mask,
7134 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7135 x = gen_binary (code, op_mode, op0, op1);
7139 /* For left shifts, do the same, but just for the first operand.
7140 However, we cannot do anything with shifts where we cannot
7141 guarantee that the counts are smaller than the size of the mode
7142 because such a count will have a different meaning in a
7145 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7146 && INTVAL (XEXP (x, 1)) >= 0
7147 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7148 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7149 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7150 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7153 /* If the shift count is a constant and we can do arithmetic in
7154 the mode of the shift, refine which bits we need. Otherwise, use the
7155 conservative form of the mask. */
7156 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7157 && INTVAL (XEXP (x, 1)) >= 0
7158 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7159 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7160 mask >>= INTVAL (XEXP (x, 1));
7164 op0 = gen_lowpart (op_mode,
7165 force_to_mode (XEXP (x, 0), op_mode,
7166 mask, reg, next_select));
7168 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7169 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7173 /* Here we can only do something if the shift count is a constant,
7174 this shift constant is valid for the host, and we can do arithmetic
7177 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7178 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7179 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7181 rtx inner = XEXP (x, 0);
7182 unsigned HOST_WIDE_INT inner_mask;
7184 /* Select the mask of the bits we need for the shift operand. */
7185 inner_mask = mask << INTVAL (XEXP (x, 1));
7187 /* We can only change the mode of the shift if we can do arithmetic
7188 in the mode of the shift and INNER_MASK is no wider than the
7189 width of OP_MODE. */
7190 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7191 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7192 op_mode = GET_MODE (x);
7194 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7196 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7197 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7200 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7201 shift and AND produces only copies of the sign bit (C2 is one less
7202 than a power of two), we can do this with just a shift. */
7204 if (GET_CODE (x) == LSHIFTRT
7205 && GET_CODE (XEXP (x, 1)) == CONST_INT
7206 /* The shift puts one of the sign bit copies in the least significant
7208 && ((INTVAL (XEXP (x, 1))
7209 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7210 >= GET_MODE_BITSIZE (GET_MODE (x)))
7211 && exact_log2 (mask + 1) >= 0
7212 /* Number of bits left after the shift must be more than the mask
7214 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7215 <= GET_MODE_BITSIZE (GET_MODE (x)))
7216 /* Must be more sign bit copies than the mask needs. */
7217 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7218 >= exact_log2 (mask + 1)))
7219 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7220 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7221 - exact_log2 (mask + 1)));
7226 /* If we are just looking for the sign bit, we don't need this shift at
7227 all, even if it has a variable count. */
7228 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7229 && (mask == ((unsigned HOST_WIDE_INT) 1
7230 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7231 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7233 /* If this is a shift by a constant, get a mask that contains those bits
7234 that are not copies of the sign bit. We then have two cases: If
7235 MASK only includes those bits, this can be a logical shift, which may
7236 allow simplifications. If MASK is a single-bit field not within
7237 those bits, we are requesting a copy of the sign bit and hence can
7238 shift the sign bit to the appropriate location. */
7240 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7241 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7245 /* If the considered data is wider than HOST_WIDE_INT, we can't
7246 represent a mask for all its bits in a single scalar.
7247 But we only care about the lower bits, so calculate these. */
7249 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7251 nonzero = ~(HOST_WIDE_INT) 0;
7253 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7254 is the number of bits a full-width mask would have set.
7255 We need only shift if these are fewer than nonzero can
7256 hold. If not, we must keep all bits set in nonzero. */
7258 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7259 < HOST_BITS_PER_WIDE_INT)
7260 nonzero >>= INTVAL (XEXP (x, 1))
7261 + HOST_BITS_PER_WIDE_INT
7262 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7266 nonzero = GET_MODE_MASK (GET_MODE (x));
7267 nonzero >>= INTVAL (XEXP (x, 1));
7270 if ((mask & ~nonzero) == 0
7271 || (i = exact_log2 (mask)) >= 0)
7273 x = simplify_shift_const
7274 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7275 i < 0 ? INTVAL (XEXP (x, 1))
7276 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7278 if (GET_CODE (x) != ASHIFTRT)
7279 return force_to_mode (x, mode, mask, reg, next_select);
7283 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7284 even if the shift count isn't a constant. */
7286 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7290 /* If this is a zero- or sign-extension operation that just affects bits
7291 we don't care about, remove it. Be sure the call above returned
7292 something that is still a shift. */
7294 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7295 && GET_CODE (XEXP (x, 1)) == CONST_INT
7296 && INTVAL (XEXP (x, 1)) >= 0
7297 && (INTVAL (XEXP (x, 1))
7298 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7299 && GET_CODE (XEXP (x, 0)) == ASHIFT
7300 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7301 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7308 /* If the shift count is constant and we can do computations
7309 in the mode of X, compute where the bits we care about are.
7310 Otherwise, we can't do anything. Don't change the mode of
7311 the shift or propagate MODE into the shift, though. */
7312 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7313 && INTVAL (XEXP (x, 1)) >= 0)
7315 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7316 GET_MODE (x), GEN_INT (mask),
7318 if (temp && GET_CODE (temp) == CONST_INT)
7320 force_to_mode (XEXP (x, 0), GET_MODE (x),
7321 INTVAL (temp), reg, next_select));
7326 /* If we just want the low-order bit, the NEG isn't needed since it
7327 won't change the low-order bit. */
7329 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7331 /* We need any bits less significant than the most significant bit in
7332 MASK since carries from those bits will affect the bits we are
7338 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7339 same as the XOR case above. Ensure that the constant we form is not
7340 wider than the mode of X. */
7342 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7343 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7344 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7345 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7346 < GET_MODE_BITSIZE (GET_MODE (x)))
7347 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7349 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7351 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7352 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7354 return force_to_mode (x, mode, mask, reg, next_select);
7357 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7358 use the full mask inside the NOT. */
7362 op0 = gen_lowpart (op_mode,
7363 force_to_mode (XEXP (x, 0), mode, mask,
7365 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7366 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7370 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7371 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7372 which is equal to STORE_FLAG_VALUE. */
7373 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7374 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7375 && (nonzero_bits (XEXP (x, 0), mode)
7376 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7377 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7382 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7383 written in a narrower mode. We play it safe and do not do so. */
7386 gen_lowpart (GET_MODE (x),
7387 force_to_mode (XEXP (x, 1), mode,
7388 mask, reg, next_select)));
7390 gen_lowpart (GET_MODE (x),
7391 force_to_mode (XEXP (x, 2), mode,
7392 mask, reg, next_select)));
7399 /* Ensure we return a value of the proper mode. */
7400 return gen_lowpart (mode, x);
7403 /* Return nonzero if X is an expression that has one of two values depending on
7404 whether some other value is zero or nonzero. In that case, we return the
7405 value that is being tested, *PTRUE is set to the value if the rtx being
7406 returned has a nonzero value, and *PFALSE is set to the other alternative.
7408 If we return zero, we set *PTRUE and *PFALSE to X. */
7411 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7413 enum machine_mode mode = GET_MODE (x);
7414 enum rtx_code code = GET_CODE (x);
7415 rtx cond0, cond1, true0, true1, false0, false1;
7416 unsigned HOST_WIDE_INT nz;
7418 /* If we are comparing a value against zero, we are done. */
7419 if ((code == NE || code == EQ)
7420 && XEXP (x, 1) == const0_rtx)
7422 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7423 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7427 /* If this is a unary operation whose operand has one of two values, apply
7428 our opcode to compute those values. */
7429 else if (UNARY_P (x)
7430 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7432 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7433 *pfalse = simplify_gen_unary (code, mode, false0,
7434 GET_MODE (XEXP (x, 0)));
7438 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7439 make can't possibly match and would suppress other optimizations. */
7440 else if (code == COMPARE)
7443 /* If this is a binary operation, see if either side has only one of two
7444 values. If either one does or if both do and they are conditional on
7445 the same value, compute the new true and false values. */
7446 else if (BINARY_P (x))
7448 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7449 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7451 if ((cond0 != 0 || cond1 != 0)
7452 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7454 /* If if_then_else_cond returned zero, then true/false are the
7455 same rtl. We must copy one of them to prevent invalid rtl
7458 true0 = copy_rtx (true0);
7459 else if (cond1 == 0)
7460 true1 = copy_rtx (true1);
7462 *ptrue = gen_binary (code, mode, true0, true1);
7463 *pfalse = gen_binary (code, mode, false0, false1);
7464 return cond0 ? cond0 : cond1;
7467 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7468 operands is zero when the other is nonzero, and vice-versa,
7469 and STORE_FLAG_VALUE is 1 or -1. */
7471 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7472 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7474 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7476 rtx op0 = XEXP (XEXP (x, 0), 1);
7477 rtx op1 = XEXP (XEXP (x, 1), 1);
7479 cond0 = XEXP (XEXP (x, 0), 0);
7480 cond1 = XEXP (XEXP (x, 1), 0);
7482 if (COMPARISON_P (cond0)
7483 && COMPARISON_P (cond1)
7484 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7485 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7486 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7487 || ((swap_condition (GET_CODE (cond0))
7488 == combine_reversed_comparison_code (cond1))
7489 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7490 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7491 && ! side_effects_p (x))
7493 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7494 *pfalse = gen_binary (MULT, mode,
7496 ? simplify_gen_unary (NEG, mode, op1,
7504 /* Similarly for MULT, AND and UMIN, except that for these the result
7506 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7507 && (code == MULT || code == AND || code == UMIN)
7508 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7510 cond0 = XEXP (XEXP (x, 0), 0);
7511 cond1 = XEXP (XEXP (x, 1), 0);
7513 if (COMPARISON_P (cond0)
7514 && COMPARISON_P (cond1)
7515 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7516 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7517 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7518 || ((swap_condition (GET_CODE (cond0))
7519 == combine_reversed_comparison_code (cond1))
7520 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7521 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7522 && ! side_effects_p (x))
7524 *ptrue = *pfalse = const0_rtx;
7530 else if (code == IF_THEN_ELSE)
7532 /* If we have IF_THEN_ELSE already, extract the condition and
7533 canonicalize it if it is NE or EQ. */
7534 cond0 = XEXP (x, 0);
7535 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7536 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7537 return XEXP (cond0, 0);
7538 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7540 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7541 return XEXP (cond0, 0);
7547 /* If X is a SUBREG, we can narrow both the true and false values
7548 if the inner expression, if there is a condition. */
7549 else if (code == SUBREG
7550 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7553 true0 = simplify_gen_subreg (mode, true0,
7554 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7555 false0 = simplify_gen_subreg (mode, false0,
7556 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7557 if (true0 && false0)
7565 /* If X is a constant, this isn't special and will cause confusions
7566 if we treat it as such. Likewise if it is equivalent to a constant. */
7567 else if (CONSTANT_P (x)
7568 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7571 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7572 will be least confusing to the rest of the compiler. */
7573 else if (mode == BImode)
7575 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7579 /* If X is known to be either 0 or -1, those are the true and
7580 false values when testing X. */
7581 else if (x == constm1_rtx || x == const0_rtx
7582 || (mode != VOIDmode
7583 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7585 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7589 /* Likewise for 0 or a single bit. */
7590 else if (SCALAR_INT_MODE_P (mode)
7591 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7592 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7594 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7598 /* Otherwise fail; show no condition with true and false values the same. */
7599 *ptrue = *pfalse = x;
7603 /* Return the value of expression X given the fact that condition COND
7604 is known to be true when applied to REG as its first operand and VAL
7605 as its second. X is known to not be shared and so can be modified in
7608 We only handle the simplest cases, and specifically those cases that
7609 arise with IF_THEN_ELSE expressions. */
7612 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7614 enum rtx_code code = GET_CODE (x);
7619 if (side_effects_p (x))
7622 /* If either operand of the condition is a floating point value,
7623 then we have to avoid collapsing an EQ comparison. */
7625 && rtx_equal_p (x, reg)
7626 && ! FLOAT_MODE_P (GET_MODE (x))
7627 && ! FLOAT_MODE_P (GET_MODE (val)))
7630 if (cond == UNEQ && rtx_equal_p (x, reg))
7633 /* If X is (abs REG) and we know something about REG's relationship
7634 with zero, we may be able to simplify this. */
7636 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7639 case GE: case GT: case EQ:
7642 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7644 GET_MODE (XEXP (x, 0)));
7649 /* The only other cases we handle are MIN, MAX, and comparisons if the
7650 operands are the same as REG and VAL. */
7652 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7654 if (rtx_equal_p (XEXP (x, 0), val))
7655 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7657 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7659 if (COMPARISON_P (x))
7661 if (comparison_dominates_p (cond, code))
7662 return const_true_rtx;
7664 code = combine_reversed_comparison_code (x);
7666 && comparison_dominates_p (cond, code))
7671 else if (code == SMAX || code == SMIN
7672 || code == UMIN || code == UMAX)
7674 int unsignedp = (code == UMIN || code == UMAX);
7676 /* Do not reverse the condition when it is NE or EQ.
7677 This is because we cannot conclude anything about
7678 the value of 'SMAX (x, y)' when x is not equal to y,
7679 but we can when x equals y. */
7680 if ((code == SMAX || code == UMAX)
7681 && ! (cond == EQ || cond == NE))
7682 cond = reverse_condition (cond);
7687 return unsignedp ? x : XEXP (x, 1);
7689 return unsignedp ? x : XEXP (x, 0);
7691 return unsignedp ? XEXP (x, 1) : x;
7693 return unsignedp ? XEXP (x, 0) : x;
7700 else if (code == SUBREG)
7702 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7703 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7705 if (SUBREG_REG (x) != r)
7707 /* We must simplify subreg here, before we lose track of the
7708 original inner_mode. */
7709 new = simplify_subreg (GET_MODE (x), r,
7710 inner_mode, SUBREG_BYTE (x));
7714 SUBST (SUBREG_REG (x), r);
7719 /* We don't have to handle SIGN_EXTEND here, because even in the
7720 case of replacing something with a modeless CONST_INT, a
7721 CONST_INT is already (supposed to be) a valid sign extension for
7722 its narrower mode, which implies it's already properly
7723 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7724 story is different. */
7725 else if (code == ZERO_EXTEND)
7727 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7728 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7730 if (XEXP (x, 0) != r)
7732 /* We must simplify the zero_extend here, before we lose
7733 track of the original inner_mode. */
7734 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7739 SUBST (XEXP (x, 0), r);
7745 fmt = GET_RTX_FORMAT (code);
7746 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7749 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7750 else if (fmt[i] == 'E')
7751 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7752 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7759 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7760 assignment as a field assignment. */
7763 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7765 if (x == y || rtx_equal_p (x, y))
7768 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7771 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7772 Note that all SUBREGs of MEM are paradoxical; otherwise they
7773 would have been rewritten. */
7774 if (MEM_P (x) && GET_CODE (y) == SUBREG
7775 && MEM_P (SUBREG_REG (y))
7776 && rtx_equal_p (SUBREG_REG (y),
7777 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7780 if (MEM_P (y) && GET_CODE (x) == SUBREG
7781 && MEM_P (SUBREG_REG (x))
7782 && rtx_equal_p (SUBREG_REG (x),
7783 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7786 /* We used to see if get_last_value of X and Y were the same but that's
7787 not correct. In one direction, we'll cause the assignment to have
7788 the wrong destination and in the case, we'll import a register into this
7789 insn that might have already have been dead. So fail if none of the
7790 above cases are true. */
7794 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7795 Return that assignment if so.
7797 We only handle the most common cases. */
7800 make_field_assignment (rtx x)
7802 rtx dest = SET_DEST (x);
7803 rtx src = SET_SRC (x);
7808 unsigned HOST_WIDE_INT len;
7810 enum machine_mode mode;
7812 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7813 a clear of a one-bit field. We will have changed it to
7814 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7817 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7818 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7819 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7820 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7822 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7825 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7829 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7830 && subreg_lowpart_p (XEXP (src, 0))
7831 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7832 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7833 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7834 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7835 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7836 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7838 assign = make_extraction (VOIDmode, dest, 0,
7839 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7842 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7846 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7848 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7849 && XEXP (XEXP (src, 0), 0) == const1_rtx
7850 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7852 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7855 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7859 /* The other case we handle is assignments into a constant-position
7860 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7861 a mask that has all one bits except for a group of zero bits and
7862 OTHER is known to have zeros where C1 has ones, this is such an
7863 assignment. Compute the position and length from C1. Shift OTHER
7864 to the appropriate position, force it to the required mode, and
7865 make the extraction. Check for the AND in both operands. */
7867 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7870 rhs = expand_compound_operation (XEXP (src, 0));
7871 lhs = expand_compound_operation (XEXP (src, 1));
7873 if (GET_CODE (rhs) == AND
7874 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7875 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7876 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7877 else if (GET_CODE (lhs) == AND
7878 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7879 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7880 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7884 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7885 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7886 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7887 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7890 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7894 /* The mode to use for the source is the mode of the assignment, or of
7895 what is inside a possible STRICT_LOW_PART. */
7896 mode = (GET_CODE (assign) == STRICT_LOW_PART
7897 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7899 /* Shift OTHER right POS places and make it the source, restricting it
7900 to the proper length and mode. */
7902 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7903 GET_MODE (src), other, pos),
7905 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7906 ? ~(unsigned HOST_WIDE_INT) 0
7907 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7910 /* If SRC is masked by an AND that does not make a difference in
7911 the value being stored, strip it. */
7912 if (GET_CODE (assign) == ZERO_EXTRACT
7913 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7914 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7915 && GET_CODE (src) == AND
7916 && GET_CODE (XEXP (src, 1)) == CONST_INT
7917 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7918 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7919 src = XEXP (src, 0);
7921 return gen_rtx_SET (VOIDmode, assign, src);
7924 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7928 apply_distributive_law (rtx x)
7930 enum rtx_code code = GET_CODE (x);
7931 enum rtx_code inner_code;
7932 rtx lhs, rhs, other;
7935 /* Distributivity is not true for floating point as it can change the
7936 value. So we don't do it unless -funsafe-math-optimizations. */
7937 if (FLOAT_MODE_P (GET_MODE (x))
7938 && ! flag_unsafe_math_optimizations)
7941 /* The outer operation can only be one of the following: */
7942 if (code != IOR && code != AND && code != XOR
7943 && code != PLUS && code != MINUS)
7949 /* If either operand is a primitive we can't do anything, so get out
7951 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7954 lhs = expand_compound_operation (lhs);
7955 rhs = expand_compound_operation (rhs);
7956 inner_code = GET_CODE (lhs);
7957 if (inner_code != GET_CODE (rhs))
7960 /* See if the inner and outer operations distribute. */
7967 /* These all distribute except over PLUS. */
7968 if (code == PLUS || code == MINUS)
7973 if (code != PLUS && code != MINUS)
7978 /* This is also a multiply, so it distributes over everything. */
7982 /* Non-paradoxical SUBREGs distributes over all operations, provided
7983 the inner modes and byte offsets are the same, this is an extraction
7984 of a low-order part, we don't convert an fp operation to int or
7985 vice versa, and we would not be converting a single-word
7986 operation into a multi-word operation. The latter test is not
7987 required, but it prevents generating unneeded multi-word operations.
7988 Some of the previous tests are redundant given the latter test, but
7989 are retained because they are required for correctness.
7991 We produce the result slightly differently in this case. */
7993 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7994 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7995 || ! subreg_lowpart_p (lhs)
7996 || (GET_MODE_CLASS (GET_MODE (lhs))
7997 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7998 || (GET_MODE_SIZE (GET_MODE (lhs))
7999 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8000 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8003 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8004 SUBREG_REG (lhs), SUBREG_REG (rhs));
8005 return gen_lowpart (GET_MODE (x), tem);
8011 /* Set LHS and RHS to the inner operands (A and B in the example
8012 above) and set OTHER to the common operand (C in the example).
8013 There is only one way to do this unless the inner operation is
8015 if (COMMUTATIVE_ARITH_P (lhs)
8016 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8017 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8018 else if (COMMUTATIVE_ARITH_P (lhs)
8019 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8020 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8021 else if (COMMUTATIVE_ARITH_P (lhs)
8022 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8023 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8024 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8025 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8029 /* Form the new inner operation, seeing if it simplifies first. */
8030 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8032 /* There is one exception to the general way of distributing:
8033 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8034 if (code == XOR && inner_code == IOR)
8037 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8040 /* We may be able to continuing distributing the result, so call
8041 ourselves recursively on the inner operation before forming the
8042 outer operation, which we return. */
8043 return gen_binary (inner_code, GET_MODE (x),
8044 apply_distributive_law (tem), other);
8047 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8050 Return an equivalent form, if different from X. Otherwise, return X. If
8051 X is zero, we are to always construct the equivalent form. */
8054 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8055 unsigned HOST_WIDE_INT constop)
8057 unsigned HOST_WIDE_INT nonzero;
8060 /* Simplify VAROP knowing that we will be only looking at some of the
8063 Note by passing in CONSTOP, we guarantee that the bits not set in
8064 CONSTOP are not significant and will never be examined. We must
8065 ensure that is the case by explicitly masking out those bits
8066 before returning. */
8067 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8069 /* If VAROP is a CLOBBER, we will fail so return it. */
8070 if (GET_CODE (varop) == CLOBBER)
8073 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8074 to VAROP and return the new constant. */
8075 if (GET_CODE (varop) == CONST_INT)
8076 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8078 /* See what bits may be nonzero in VAROP. Unlike the general case of
8079 a call to nonzero_bits, here we don't care about bits outside
8082 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8084 /* Turn off all bits in the constant that are known to already be zero.
8085 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8086 which is tested below. */
8090 /* If we don't have any bits left, return zero. */
8094 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8095 a power of two, we can replace this with an ASHIFT. */
8096 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8097 && (i = exact_log2 (constop)) >= 0)
8098 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8100 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8101 or XOR, then try to apply the distributive law. This may eliminate
8102 operations if either branch can be simplified because of the AND.
8103 It may also make some cases more complex, but those cases probably
8104 won't match a pattern either with or without this. */
8106 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8110 apply_distributive_law
8111 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8112 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8113 XEXP (varop, 0), constop),
8114 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8115 XEXP (varop, 1), constop))));
8117 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8118 the AND and see if one of the operands simplifies to zero. If so, we
8119 may eliminate it. */
8121 if (GET_CODE (varop) == PLUS
8122 && exact_log2 (constop + 1) >= 0)
8126 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8127 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8128 if (o0 == const0_rtx)
8130 if (o1 == const0_rtx)
8134 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8135 if we already had one (just check for the simplest cases). */
8136 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8137 && GET_MODE (XEXP (x, 0)) == mode
8138 && SUBREG_REG (XEXP (x, 0)) == varop)
8139 varop = XEXP (x, 0);
8141 varop = gen_lowpart (mode, varop);
8143 /* If we can't make the SUBREG, try to return what we were given. */
8144 if (GET_CODE (varop) == CLOBBER)
8145 return x ? x : varop;
8147 /* If we are only masking insignificant bits, return VAROP. */
8148 if (constop == nonzero)
8152 /* Otherwise, return an AND. */
8153 constop = trunc_int_for_mode (constop, mode);
8154 /* See how much, if any, of X we can use. */
8155 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8156 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8160 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8161 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8162 SUBST (XEXP (x, 1), GEN_INT (constop));
8164 SUBST (XEXP (x, 0), varop);
8171 /* Given a REG, X, compute which bits in X can be nonzero.
8172 We don't care about bits outside of those defined in MODE.
8174 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8175 a shift, AND, or zero_extract, we can do better. */
8178 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8179 rtx known_x ATTRIBUTE_UNUSED,
8180 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8181 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8182 unsigned HOST_WIDE_INT *nonzero)
8186 /* If X is a register whose nonzero bits value is current, use it.
8187 Otherwise, if X is a register whose value we can find, use that
8188 value. Otherwise, use the previously-computed global nonzero bits
8189 for this register. */
8191 if (reg_stat[REGNO (x)].last_set_value != 0
8192 && (reg_stat[REGNO (x)].last_set_mode == mode
8193 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8194 && GET_MODE_CLASS (mode) == MODE_INT))
8195 && (reg_stat[REGNO (x)].last_set_label == label_tick
8196 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8197 && REG_N_SETS (REGNO (x)) == 1
8198 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8200 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8202 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8206 tem = get_last_value (x);
8210 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8211 /* If X is narrower than MODE and TEM is a non-negative
8212 constant that would appear negative in the mode of X,
8213 sign-extend it for use in reg_nonzero_bits because some
8214 machines (maybe most) will actually do the sign-extension
8215 and this is the conservative approach.
8217 ??? For 2.5, try to tighten up the MD files in this regard
8218 instead of this kludge. */
8220 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8221 && GET_CODE (tem) == CONST_INT
8223 && 0 != (INTVAL (tem)
8224 & ((HOST_WIDE_INT) 1
8225 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8226 tem = GEN_INT (INTVAL (tem)
8227 | ((HOST_WIDE_INT) (-1)
8228 << GET_MODE_BITSIZE (GET_MODE (x))));
8232 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8234 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8236 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8237 /* We don't know anything about the upper bits. */
8238 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8245 /* Return the number of bits at the high-order end of X that are known to
8246 be equal to the sign bit. X will be used in mode MODE; if MODE is
8247 VOIDmode, X will be used in its own mode. The returned value will always
8248 be between 1 and the number of bits in MODE. */
8251 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8252 rtx known_x ATTRIBUTE_UNUSED,
8253 enum machine_mode known_mode
8255 unsigned int known_ret ATTRIBUTE_UNUSED,
8256 unsigned int *result)
8260 if (reg_stat[REGNO (x)].last_set_value != 0
8261 && reg_stat[REGNO (x)].last_set_mode == mode
8262 && (reg_stat[REGNO (x)].last_set_label == label_tick
8263 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8264 && REG_N_SETS (REGNO (x)) == 1
8265 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8267 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8269 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8273 tem = get_last_value (x);
8277 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8278 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8279 *result = reg_stat[REGNO (x)].sign_bit_copies;
8284 /* Return the number of "extended" bits there are in X, when interpreted
8285 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8286 unsigned quantities, this is the number of high-order zero bits.
8287 For signed quantities, this is the number of copies of the sign bit
8288 minus 1. In both case, this function returns the number of "spare"
8289 bits. For example, if two quantities for which this function returns
8290 at least 1 are added, the addition is known not to overflow.
8292 This function will always return 0 unless called during combine, which
8293 implies that it must be called from a define_split. */
8296 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8298 if (nonzero_sign_valid == 0)
8302 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8303 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8304 - floor_log2 (nonzero_bits (x, mode)))
8306 : num_sign_bit_copies (x, mode) - 1);
8309 /* This function is called from `simplify_shift_const' to merge two
8310 outer operations. Specifically, we have already found that we need
8311 to perform operation *POP0 with constant *PCONST0 at the outermost
8312 position. We would now like to also perform OP1 with constant CONST1
8313 (with *POP0 being done last).
8315 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8316 the resulting operation. *PCOMP_P is set to 1 if we would need to
8317 complement the innermost operand, otherwise it is unchanged.
8319 MODE is the mode in which the operation will be done. No bits outside
8320 the width of this mode matter. It is assumed that the width of this mode
8321 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8323 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8324 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8325 result is simply *PCONST0.
8327 If the resulting operation cannot be expressed as one operation, we
8328 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8331 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8333 enum rtx_code op0 = *pop0;
8334 HOST_WIDE_INT const0 = *pconst0;
8336 const0 &= GET_MODE_MASK (mode);
8337 const1 &= GET_MODE_MASK (mode);
8339 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8343 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8346 if (op1 == NIL || op0 == SET)
8349 else if (op0 == NIL)
8350 op0 = op1, const0 = const1;
8352 else if (op0 == op1)
8376 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8377 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8380 /* If the two constants aren't the same, we can't do anything. The
8381 remaining six cases can all be done. */
8382 else if (const0 != const1)
8390 /* (a & b) | b == b */
8392 else /* op1 == XOR */
8393 /* (a ^ b) | b == a | b */
8399 /* (a & b) ^ b == (~a) & b */
8400 op0 = AND, *pcomp_p = 1;
8401 else /* op1 == IOR */
8402 /* (a | b) ^ b == a & ~b */
8403 op0 = AND, const0 = ~const0;
8408 /* (a | b) & b == b */
8410 else /* op1 == XOR */
8411 /* (a ^ b) & b) == (~a) & b */
8418 /* Check for NO-OP cases. */
8419 const0 &= GET_MODE_MASK (mode);
8421 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8423 else if (const0 == 0 && op0 == AND)
8425 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8429 /* ??? Slightly redundant with the above mask, but not entirely.
8430 Moving this above means we'd have to sign-extend the mode mask
8431 for the final test. */
8432 const0 = trunc_int_for_mode (const0, mode);
8440 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8441 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8442 that we started with.
8444 The shift is normally computed in the widest mode we find in VAROP, as
8445 long as it isn't a different number of words than RESULT_MODE. Exceptions
8446 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8449 simplify_shift_const (rtx x, enum rtx_code code,
8450 enum machine_mode result_mode, rtx varop,
8453 enum rtx_code orig_code = code;
8456 enum machine_mode mode = result_mode;
8457 enum machine_mode shift_mode, tmode;
8458 unsigned int mode_words
8459 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8460 /* We form (outer_op (code varop count) (outer_const)). */
8461 enum rtx_code outer_op = NIL;
8462 HOST_WIDE_INT outer_const = 0;
8464 int complement_p = 0;
8467 /* Make sure and truncate the "natural" shift on the way in. We don't
8468 want to do this inside the loop as it makes it more difficult to
8470 if (SHIFT_COUNT_TRUNCATED)
8471 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8473 /* If we were given an invalid count, don't do anything except exactly
8474 what was requested. */
8476 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8481 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8486 /* Unless one of the branches of the `if' in this loop does a `continue',
8487 we will `break' the loop after the `if'. */
8491 /* If we have an operand of (clobber (const_int 0)), just return that
8493 if (GET_CODE (varop) == CLOBBER)
8496 /* If we discovered we had to complement VAROP, leave. Making a NOT
8497 here would cause an infinite loop. */
8501 /* Convert ROTATERT to ROTATE. */
8502 if (code == ROTATERT)
8504 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8506 if (VECTOR_MODE_P (result_mode))
8507 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8509 count = bitsize - count;
8512 /* We need to determine what mode we will do the shift in. If the
8513 shift is a right shift or a ROTATE, we must always do it in the mode
8514 it was originally done in. Otherwise, we can do it in MODE, the
8515 widest mode encountered. */
8517 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8518 ? result_mode : mode);
8520 /* Handle cases where the count is greater than the size of the mode
8521 minus 1. For ASHIFT, use the size minus one as the count (this can
8522 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8523 take the count modulo the size. For other shifts, the result is
8526 Since these shifts are being produced by the compiler by combining
8527 multiple operations, each of which are defined, we know what the
8528 result is supposed to be. */
8530 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8532 if (code == ASHIFTRT)
8533 count = GET_MODE_BITSIZE (shift_mode) - 1;
8534 else if (code == ROTATE || code == ROTATERT)
8535 count %= GET_MODE_BITSIZE (shift_mode);
8538 /* We can't simply return zero because there may be an
8546 /* An arithmetic right shift of a quantity known to be -1 or 0
8548 if (code == ASHIFTRT
8549 && (num_sign_bit_copies (varop, shift_mode)
8550 == GET_MODE_BITSIZE (shift_mode)))
8556 /* If we are doing an arithmetic right shift and discarding all but
8557 the sign bit copies, this is equivalent to doing a shift by the
8558 bitsize minus one. Convert it into that shift because it will often
8559 allow other simplifications. */
8561 if (code == ASHIFTRT
8562 && (count + num_sign_bit_copies (varop, shift_mode)
8563 >= GET_MODE_BITSIZE (shift_mode)))
8564 count = GET_MODE_BITSIZE (shift_mode) - 1;
8566 /* We simplify the tests below and elsewhere by converting
8567 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8568 `make_compound_operation' will convert it to an ASHIFTRT for
8569 those machines (such as VAX) that don't have an LSHIFTRT. */
8570 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8572 && ((nonzero_bits (varop, shift_mode)
8573 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8577 if (code == LSHIFTRT
8578 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8579 && !(nonzero_bits (varop, shift_mode) >> count))
8582 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8583 && !((nonzero_bits (varop, shift_mode) << count)
8584 & GET_MODE_MASK (shift_mode)))
8587 switch (GET_CODE (varop))
8593 new = expand_compound_operation (varop);
8602 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8603 minus the width of a smaller mode, we can do this with a
8604 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8605 if ((code == ASHIFTRT || code == LSHIFTRT)
8606 && ! mode_dependent_address_p (XEXP (varop, 0))
8607 && ! MEM_VOLATILE_P (varop)
8608 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8609 MODE_INT, 1)) != BLKmode)
8611 new = adjust_address_nv (varop, tmode,
8612 BYTES_BIG_ENDIAN ? 0
8613 : count / BITS_PER_UNIT);
8615 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8616 : ZERO_EXTEND, mode, new);
8623 /* Similar to the case above, except that we can only do this if
8624 the resulting mode is the same as that of the underlying
8625 MEM and adjust the address depending on the *bits* endianness
8626 because of the way that bit-field extract insns are defined. */
8627 if ((code == ASHIFTRT || code == LSHIFTRT)
8628 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8629 MODE_INT, 1)) != BLKmode
8630 && tmode == GET_MODE (XEXP (varop, 0)))
8632 if (BITS_BIG_ENDIAN)
8633 new = XEXP (varop, 0);
8636 new = copy_rtx (XEXP (varop, 0));
8637 SUBST (XEXP (new, 0),
8638 plus_constant (XEXP (new, 0),
8639 count / BITS_PER_UNIT));
8642 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8643 : ZERO_EXTEND, mode, new);
8650 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8651 the same number of words as what we've seen so far. Then store
8652 the widest mode in MODE. */
8653 if (subreg_lowpart_p (varop)
8654 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8655 > GET_MODE_SIZE (GET_MODE (varop)))
8656 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8657 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8660 varop = SUBREG_REG (varop);
8661 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8662 mode = GET_MODE (varop);
8668 /* Some machines use MULT instead of ASHIFT because MULT
8669 is cheaper. But it is still better on those machines to
8670 merge two shifts into one. */
8671 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8672 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8675 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8676 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8682 /* Similar, for when divides are cheaper. */
8683 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8684 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8687 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8688 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8694 /* If we are extracting just the sign bit of an arithmetic
8695 right shift, that shift is not needed. However, the sign
8696 bit of a wider mode may be different from what would be
8697 interpreted as the sign bit in a narrower mode, so, if
8698 the result is narrower, don't discard the shift. */
8699 if (code == LSHIFTRT
8700 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8701 && (GET_MODE_BITSIZE (result_mode)
8702 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8704 varop = XEXP (varop, 0);
8708 /* ... fall through ... */
8713 /* Here we have two nested shifts. The result is usually the
8714 AND of a new shift with a mask. We compute the result below. */
8715 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8716 && INTVAL (XEXP (varop, 1)) >= 0
8717 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8718 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8719 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8721 enum rtx_code first_code = GET_CODE (varop);
8722 unsigned int first_count = INTVAL (XEXP (varop, 1));
8723 unsigned HOST_WIDE_INT mask;
8726 /* We have one common special case. We can't do any merging if
8727 the inner code is an ASHIFTRT of a smaller mode. However, if
8728 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8729 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8730 we can convert it to
8731 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8732 This simplifies certain SIGN_EXTEND operations. */
8733 if (code == ASHIFT && first_code == ASHIFTRT
8734 && count == (unsigned int)
8735 (GET_MODE_BITSIZE (result_mode)
8736 - GET_MODE_BITSIZE (GET_MODE (varop))))
8738 /* C3 has the low-order C1 bits zero. */
8740 mask = (GET_MODE_MASK (mode)
8741 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8743 varop = simplify_and_const_int (NULL_RTX, result_mode,
8744 XEXP (varop, 0), mask);
8745 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8747 count = first_count;
8752 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8753 than C1 high-order bits equal to the sign bit, we can convert
8754 this to either an ASHIFT or an ASHIFTRT depending on the
8757 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8759 if (code == ASHIFTRT && first_code == ASHIFT
8760 && GET_MODE (varop) == shift_mode
8761 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8764 varop = XEXP (varop, 0);
8766 signed_count = count - first_count;
8767 if (signed_count < 0)
8768 count = -signed_count, code = ASHIFT;
8770 count = signed_count;
8775 /* There are some cases we can't do. If CODE is ASHIFTRT,
8776 we can only do this if FIRST_CODE is also ASHIFTRT.
8778 We can't do the case when CODE is ROTATE and FIRST_CODE is
8781 If the mode of this shift is not the mode of the outer shift,
8782 we can't do this if either shift is a right shift or ROTATE.
8784 Finally, we can't do any of these if the mode is too wide
8785 unless the codes are the same.
8787 Handle the case where the shift codes are the same
8790 if (code == first_code)
8792 if (GET_MODE (varop) != result_mode
8793 && (code == ASHIFTRT || code == LSHIFTRT
8797 count += first_count;
8798 varop = XEXP (varop, 0);
8802 if (code == ASHIFTRT
8803 || (code == ROTATE && first_code == ASHIFTRT)
8804 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8805 || (GET_MODE (varop) != result_mode
8806 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8807 || first_code == ROTATE
8808 || code == ROTATE)))
8811 /* To compute the mask to apply after the shift, shift the
8812 nonzero bits of the inner shift the same way the
8813 outer shift will. */
8815 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8818 = simplify_binary_operation (code, result_mode, mask_rtx,
8821 /* Give up if we can't compute an outer operation to use. */
8823 || GET_CODE (mask_rtx) != CONST_INT
8824 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8826 result_mode, &complement_p))
8829 /* If the shifts are in the same direction, we add the
8830 counts. Otherwise, we subtract them. */
8831 signed_count = count;
8832 if ((code == ASHIFTRT || code == LSHIFTRT)
8833 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8834 signed_count += first_count;
8836 signed_count -= first_count;
8838 /* If COUNT is positive, the new shift is usually CODE,
8839 except for the two exceptions below, in which case it is
8840 FIRST_CODE. If the count is negative, FIRST_CODE should
8842 if (signed_count > 0
8843 && ((first_code == ROTATE && code == ASHIFT)
8844 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8845 code = first_code, count = signed_count;
8846 else if (signed_count < 0)
8847 code = first_code, count = -signed_count;
8849 count = signed_count;
8851 varop = XEXP (varop, 0);
8855 /* If we have (A << B << C) for any shift, we can convert this to
8856 (A << C << B). This wins if A is a constant. Only try this if
8857 B is not a constant. */
8859 else if (GET_CODE (varop) == code
8860 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8862 = simplify_binary_operation (code, mode,
8866 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8873 /* Make this fit the case below. */
8874 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8875 GEN_INT (GET_MODE_MASK (mode)));
8881 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8882 with C the size of VAROP - 1 and the shift is logical if
8883 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8884 we have an (le X 0) operation. If we have an arithmetic shift
8885 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8886 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8888 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8889 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8890 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8891 && (code == LSHIFTRT || code == ASHIFTRT)
8892 && count == (unsigned int)
8893 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8894 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8897 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8900 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8901 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8906 /* If we have (shift (logical)), move the logical to the outside
8907 to allow it to possibly combine with another logical and the
8908 shift to combine with another shift. This also canonicalizes to
8909 what a ZERO_EXTRACT looks like. Also, some machines have
8910 (and (shift)) insns. */
8912 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8913 /* We can't do this if we have (ashiftrt (xor)) and the
8914 constant has its sign bit set in shift_mode. */
8915 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8916 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8918 && (new = simplify_binary_operation (code, result_mode,
8920 GEN_INT (count))) != 0
8921 && GET_CODE (new) == CONST_INT
8922 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8923 INTVAL (new), result_mode, &complement_p))
8925 varop = XEXP (varop, 0);
8929 /* If we can't do that, try to simplify the shift in each arm of the
8930 logical expression, make a new logical expression, and apply
8931 the inverse distributive law. This also can't be done
8932 for some (ashiftrt (xor)). */
8933 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8934 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8935 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8938 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8939 XEXP (varop, 0), count);
8940 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8941 XEXP (varop, 1), count);
8943 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8944 varop = apply_distributive_law (varop);
8952 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8953 says that the sign bit can be tested, FOO has mode MODE, C is
8954 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8955 that may be nonzero. */
8956 if (code == LSHIFTRT
8957 && XEXP (varop, 1) == const0_rtx
8958 && GET_MODE (XEXP (varop, 0)) == result_mode
8959 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8960 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8961 && ((STORE_FLAG_VALUE
8962 & ((HOST_WIDE_INT) 1
8963 < (GET_MODE_BITSIZE (result_mode) - 1))))
8964 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8965 && merge_outer_ops (&outer_op, &outer_const, XOR,
8966 (HOST_WIDE_INT) 1, result_mode,
8969 varop = XEXP (varop, 0);
8976 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8977 than the number of bits in the mode is equivalent to A. */
8978 if (code == LSHIFTRT
8979 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8980 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8982 varop = XEXP (varop, 0);
8987 /* NEG commutes with ASHIFT since it is multiplication. Move the
8988 NEG outside to allow shifts to combine. */
8990 && merge_outer_ops (&outer_op, &outer_const, NEG,
8991 (HOST_WIDE_INT) 0, result_mode,
8994 varop = XEXP (varop, 0);
9000 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9001 is one less than the number of bits in the mode is
9002 equivalent to (xor A 1). */
9003 if (code == LSHIFTRT
9004 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9005 && XEXP (varop, 1) == constm1_rtx
9006 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9007 && merge_outer_ops (&outer_op, &outer_const, XOR,
9008 (HOST_WIDE_INT) 1, result_mode,
9012 varop = XEXP (varop, 0);
9016 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9017 that might be nonzero in BAR are those being shifted out and those
9018 bits are known zero in FOO, we can replace the PLUS with FOO.
9019 Similarly in the other operand order. This code occurs when
9020 we are computing the size of a variable-size array. */
9022 if ((code == ASHIFTRT || code == LSHIFTRT)
9023 && count < HOST_BITS_PER_WIDE_INT
9024 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9025 && (nonzero_bits (XEXP (varop, 1), result_mode)
9026 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9028 varop = XEXP (varop, 0);
9031 else if ((code == ASHIFTRT || code == LSHIFTRT)
9032 && count < HOST_BITS_PER_WIDE_INT
9033 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9034 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9036 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9037 & nonzero_bits (XEXP (varop, 1),
9040 varop = XEXP (varop, 1);
9044 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9046 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9047 && (new = simplify_binary_operation (ASHIFT, result_mode,
9049 GEN_INT (count))) != 0
9050 && GET_CODE (new) == CONST_INT
9051 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9052 INTVAL (new), result_mode, &complement_p))
9054 varop = XEXP (varop, 0);
9060 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9061 with C the size of VAROP - 1 and the shift is logical if
9062 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9063 we have a (gt X 0) operation. If the shift is arithmetic with
9064 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9065 we have a (neg (gt X 0)) operation. */
9067 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9068 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9069 && count == (unsigned int)
9070 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9071 && (code == LSHIFTRT || code == ASHIFTRT)
9072 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9073 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9075 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9078 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9081 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9082 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9089 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9090 if the truncate does not affect the value. */
9091 if (code == LSHIFTRT
9092 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9093 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9094 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9095 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9096 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9098 rtx varop_inner = XEXP (varop, 0);
9101 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9102 XEXP (varop_inner, 0),
9104 (count + INTVAL (XEXP (varop_inner, 1))));
9105 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9118 /* We need to determine what mode to do the shift in. If the shift is
9119 a right shift or ROTATE, we must always do it in the mode it was
9120 originally done in. Otherwise, we can do it in MODE, the widest mode
9121 encountered. The code we care about is that of the shift that will
9122 actually be done, not the shift that was originally requested. */
9124 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9125 ? result_mode : mode);
9127 /* We have now finished analyzing the shift. The result should be
9128 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9129 OUTER_OP is non-NIL, it is an operation that needs to be applied
9130 to the result of the shift. OUTER_CONST is the relevant constant,
9131 but we must turn off all bits turned off in the shift.
9133 If we were passed a value for X, see if we can use any pieces of
9134 it. If not, make new rtx. */
9136 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9137 && GET_CODE (XEXP (x, 1)) == CONST_INT
9138 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9139 const_rtx = XEXP (x, 1);
9141 const_rtx = GEN_INT (count);
9143 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9144 && GET_MODE (XEXP (x, 0)) == shift_mode
9145 && SUBREG_REG (XEXP (x, 0)) == varop)
9146 varop = XEXP (x, 0);
9147 else if (GET_MODE (varop) != shift_mode)
9148 varop = gen_lowpart (shift_mode, varop);
9150 /* If we can't make the SUBREG, try to return what we were given. */
9151 if (GET_CODE (varop) == CLOBBER)
9152 return x ? x : varop;
9154 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9158 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9160 /* If we have an outer operation and we just made a shift, it is
9161 possible that we could have simplified the shift were it not
9162 for the outer operation. So try to do the simplification
9165 if (outer_op != NIL && GET_CODE (x) == code
9166 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9167 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9168 INTVAL (XEXP (x, 1)));
9170 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9171 turn off all the bits that the shift would have turned off. */
9172 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9173 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9174 GET_MODE_MASK (result_mode) >> orig_count);
9176 /* Do the remainder of the processing in RESULT_MODE. */
9177 x = gen_lowpart (result_mode, x);
9179 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9182 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9184 if (outer_op != NIL)
9186 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9187 outer_const = trunc_int_for_mode (outer_const, result_mode);
9189 if (outer_op == AND)
9190 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9191 else if (outer_op == SET)
9192 /* This means that we have determined that the result is
9193 equivalent to a constant. This should be rare. */
9194 x = GEN_INT (outer_const);
9195 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9196 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9198 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9204 /* Like recog, but we receive the address of a pointer to a new pattern.
9205 We try to match the rtx that the pointer points to.
9206 If that fails, we may try to modify or replace the pattern,
9207 storing the replacement into the same pointer object.
9209 Modifications include deletion or addition of CLOBBERs.
9211 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9212 the CLOBBERs are placed.
9214 The value is the final insn code from the pattern ultimately matched,
9218 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9221 int insn_code_number;
9222 int num_clobbers_to_add = 0;
9225 rtx old_notes, old_pat;
9227 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9228 we use to indicate that something didn't match. If we find such a
9229 thing, force rejection. */
9230 if (GET_CODE (pat) == PARALLEL)
9231 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9232 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9233 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9236 old_pat = PATTERN (insn);
9237 old_notes = REG_NOTES (insn);
9238 PATTERN (insn) = pat;
9239 REG_NOTES (insn) = 0;
9241 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9243 /* If it isn't, there is the possibility that we previously had an insn
9244 that clobbered some register as a side effect, but the combined
9245 insn doesn't need to do that. So try once more without the clobbers
9246 unless this represents an ASM insn. */
9248 if (insn_code_number < 0 && ! check_asm_operands (pat)
9249 && GET_CODE (pat) == PARALLEL)
9253 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9254 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9257 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9261 SUBST_INT (XVECLEN (pat, 0), pos);
9264 pat = XVECEXP (pat, 0, 0);
9266 PATTERN (insn) = pat;
9267 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9269 PATTERN (insn) = old_pat;
9270 REG_NOTES (insn) = old_notes;
9272 /* Recognize all noop sets, these will be killed by followup pass. */
9273 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9274 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9276 /* If we had any clobbers to add, make a new pattern than contains
9277 them. Then check to make sure that all of them are dead. */
9278 if (num_clobbers_to_add)
9280 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9281 rtvec_alloc (GET_CODE (pat) == PARALLEL
9283 + num_clobbers_to_add)
9284 : num_clobbers_to_add + 1));
9286 if (GET_CODE (pat) == PARALLEL)
9287 for (i = 0; i < XVECLEN (pat, 0); i++)
9288 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9290 XVECEXP (newpat, 0, 0) = pat;
9292 add_clobbers (newpat, insn_code_number);
9294 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9295 i < XVECLEN (newpat, 0); i++)
9297 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9298 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9300 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9301 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9309 return insn_code_number;
9312 /* Like gen_lowpart_general but for use by combine. In combine it
9313 is not possible to create any new pseudoregs. However, it is
9314 safe to create invalid memory addresses, because combine will
9315 try to recognize them and all they will do is make the combine
9318 If for some reason this cannot do its job, an rtx
9319 (clobber (const_int 0)) is returned.
9320 An insn containing that will not be recognized. */
9323 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9327 if (GET_MODE (x) == mode)
9330 /* Return identity if this is a CONST or symbolic
9333 && (GET_CODE (x) == CONST
9334 || GET_CODE (x) == SYMBOL_REF
9335 || GET_CODE (x) == LABEL_REF))
9338 /* We can only support MODE being wider than a word if X is a
9339 constant integer or has a mode the same size. */
9341 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9342 && ! ((GET_MODE (x) == VOIDmode
9343 && (GET_CODE (x) == CONST_INT
9344 || GET_CODE (x) == CONST_DOUBLE))
9345 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9346 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9348 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9349 won't know what to do. So we will strip off the SUBREG here and
9350 process normally. */
9351 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9354 if (GET_MODE (x) == mode)
9358 result = gen_lowpart_common (mode, x);
9359 #ifdef CANNOT_CHANGE_MODE_CLASS
9361 && GET_CODE (result) == SUBREG
9362 && REG_P (SUBREG_REG (result))
9363 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
9364 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
9366 + GET_MODE (result));
9376 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9378 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9379 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9381 /* If we want to refer to something bigger than the original memref,
9382 generate a paradoxical subreg instead. That will force a reload
9383 of the original memref X. */
9384 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9385 return gen_rtx_SUBREG (mode, x, 0);
9387 if (WORDS_BIG_ENDIAN)
9388 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9389 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9391 if (BYTES_BIG_ENDIAN)
9393 /* Adjust the address so that the address-after-the-data is
9395 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9396 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9399 return adjust_address_nv (x, mode, offset);
9402 /* If X is a comparison operator, rewrite it in a new mode. This
9403 probably won't match, but may allow further simplifications. */
9404 else if (COMPARISON_P (x))
9405 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9407 /* If we couldn't simplify X any other way, just enclose it in a
9408 SUBREG. Normally, this SUBREG won't match, but some patterns may
9409 include an explicit SUBREG or we may simplify it further in combine. */
9414 enum machine_mode sub_mode = GET_MODE (x);
9416 offset = subreg_lowpart_offset (mode, sub_mode);
9417 if (sub_mode == VOIDmode)
9419 sub_mode = int_mode_for_mode (mode);
9420 x = gen_lowpart_common (sub_mode, x);
9422 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
9424 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9427 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9431 /* These routines make binary and unary operations by first seeing if they
9432 fold; if not, a new expression is allocated. */
9435 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
9440 if (GET_CODE (op0) == CLOBBER)
9442 else if (GET_CODE (op1) == CLOBBER)
9445 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9446 && swap_commutative_operands_p (op0, op1))
9447 tem = op0, op0 = op1, op1 = tem;
9449 if (GET_RTX_CLASS (code) == RTX_COMPARE
9450 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9452 enum machine_mode op_mode = GET_MODE (op0);
9454 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9455 just (REL_OP X Y). */
9456 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9458 op1 = XEXP (op0, 1);
9459 op0 = XEXP (op0, 0);
9460 op_mode = GET_MODE (op0);
9463 if (op_mode == VOIDmode)
9464 op_mode = GET_MODE (op1);
9465 result = simplify_relational_operation (code, mode, op_mode, op0, op1);
9468 result = simplify_binary_operation (code, mode, op0, op1);
9473 /* Put complex operands first and constants second. */
9474 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9475 && swap_commutative_operands_p (op0, op1))
9476 return gen_rtx_fmt_ee (code, mode, op1, op0);
9478 /* If we are turning off bits already known off in OP0, we need not do
9480 else if (code == AND && GET_CODE (op1) == CONST_INT
9481 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9482 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9485 return gen_rtx_fmt_ee (code, mode, op0, op1);
9488 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9489 comparison code that will be tested.
9491 The result is a possibly different comparison code to use. *POP0 and
9492 *POP1 may be updated.
9494 It is possible that we might detect that a comparison is either always
9495 true or always false. However, we do not perform general constant
9496 folding in combine, so this knowledge isn't useful. Such tautologies
9497 should have been detected earlier. Hence we ignore all such cases. */
9499 static enum rtx_code
9500 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9506 enum machine_mode mode, tmode;
9508 /* Try a few ways of applying the same transformation to both operands. */
9511 #ifndef WORD_REGISTER_OPERATIONS
9512 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9513 so check specially. */
9514 if (code != GTU && code != GEU && code != LTU && code != LEU
9515 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9516 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9517 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9518 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9519 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9520 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9521 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9522 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9523 && XEXP (op0, 1) == XEXP (op1, 1)
9524 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9525 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9526 && (INTVAL (XEXP (op0, 1))
9527 == (GET_MODE_BITSIZE (GET_MODE (op0))
9529 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9531 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9532 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9536 /* If both operands are the same constant shift, see if we can ignore the
9537 shift. We can if the shift is a rotate or if the bits shifted out of
9538 this shift are known to be zero for both inputs and if the type of
9539 comparison is compatible with the shift. */
9540 if (GET_CODE (op0) == GET_CODE (op1)
9541 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9542 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9543 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9544 && (code != GT && code != LT && code != GE && code != LE))
9545 || (GET_CODE (op0) == ASHIFTRT
9546 && (code != GTU && code != LTU
9547 && code != GEU && code != LEU)))
9548 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9549 && INTVAL (XEXP (op0, 1)) >= 0
9550 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9551 && XEXP (op0, 1) == XEXP (op1, 1))
9553 enum machine_mode mode = GET_MODE (op0);
9554 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9555 int shift_count = INTVAL (XEXP (op0, 1));
9557 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9558 mask &= (mask >> shift_count) << shift_count;
9559 else if (GET_CODE (op0) == ASHIFT)
9560 mask = (mask & (mask << shift_count)) >> shift_count;
9562 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9563 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9564 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9569 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9570 SUBREGs are of the same mode, and, in both cases, the AND would
9571 be redundant if the comparison was done in the narrower mode,
9572 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9573 and the operand's possibly nonzero bits are 0xffffff01; in that case
9574 if we only care about QImode, we don't need the AND). This case
9575 occurs if the output mode of an scc insn is not SImode and
9576 STORE_FLAG_VALUE == 1 (e.g., the 386).
9578 Similarly, check for a case where the AND's are ZERO_EXTEND
9579 operations from some narrower mode even though a SUBREG is not
9582 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9583 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9584 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9586 rtx inner_op0 = XEXP (op0, 0);
9587 rtx inner_op1 = XEXP (op1, 0);
9588 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9589 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9592 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9593 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9594 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9595 && (GET_MODE (SUBREG_REG (inner_op0))
9596 == GET_MODE (SUBREG_REG (inner_op1)))
9597 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9598 <= HOST_BITS_PER_WIDE_INT)
9599 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9600 GET_MODE (SUBREG_REG (inner_op0)))))
9601 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9602 GET_MODE (SUBREG_REG (inner_op1))))))
9604 op0 = SUBREG_REG (inner_op0);
9605 op1 = SUBREG_REG (inner_op1);
9607 /* The resulting comparison is always unsigned since we masked
9608 off the original sign bit. */
9609 code = unsigned_condition (code);
9615 for (tmode = GET_CLASS_NARROWEST_MODE
9616 (GET_MODE_CLASS (GET_MODE (op0)));
9617 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9618 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9620 op0 = gen_lowpart (tmode, inner_op0);
9621 op1 = gen_lowpart (tmode, inner_op1);
9622 code = unsigned_condition (code);
9631 /* If both operands are NOT, we can strip off the outer operation
9632 and adjust the comparison code for swapped operands; similarly for
9633 NEG, except that this must be an equality comparison. */
9634 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9635 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9636 && (code == EQ || code == NE)))
9637 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9643 /* If the first operand is a constant, swap the operands and adjust the
9644 comparison code appropriately, but don't do this if the second operand
9645 is already a constant integer. */
9646 if (swap_commutative_operands_p (op0, op1))
9648 tem = op0, op0 = op1, op1 = tem;
9649 code = swap_condition (code);
9652 /* We now enter a loop during which we will try to simplify the comparison.
9653 For the most part, we only are concerned with comparisons with zero,
9654 but some things may really be comparisons with zero but not start
9655 out looking that way. */
9657 while (GET_CODE (op1) == CONST_INT)
9659 enum machine_mode mode = GET_MODE (op0);
9660 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9661 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9662 int equality_comparison_p;
9663 int sign_bit_comparison_p;
9664 int unsigned_comparison_p;
9665 HOST_WIDE_INT const_op;
9667 /* We only want to handle integral modes. This catches VOIDmode,
9668 CCmode, and the floating-point modes. An exception is that we
9669 can handle VOIDmode if OP0 is a COMPARE or a comparison
9672 if (GET_MODE_CLASS (mode) != MODE_INT
9673 && ! (mode == VOIDmode
9674 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9677 /* Get the constant we are comparing against and turn off all bits
9678 not on in our mode. */
9679 const_op = INTVAL (op1);
9680 if (mode != VOIDmode)
9681 const_op = trunc_int_for_mode (const_op, mode);
9682 op1 = GEN_INT (const_op);
9684 /* If we are comparing against a constant power of two and the value
9685 being compared can only have that single bit nonzero (e.g., it was
9686 `and'ed with that bit), we can replace this with a comparison
9689 && (code == EQ || code == NE || code == GE || code == GEU
9690 || code == LT || code == LTU)
9691 && mode_width <= HOST_BITS_PER_WIDE_INT
9692 && exact_log2 (const_op) >= 0
9693 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9695 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9696 op1 = const0_rtx, const_op = 0;
9699 /* Similarly, if we are comparing a value known to be either -1 or
9700 0 with -1, change it to the opposite comparison against zero. */
9703 && (code == EQ || code == NE || code == GT || code == LE
9704 || code == GEU || code == LTU)
9705 && num_sign_bit_copies (op0, mode) == mode_width)
9707 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9708 op1 = const0_rtx, const_op = 0;
9711 /* Do some canonicalizations based on the comparison code. We prefer
9712 comparisons against zero and then prefer equality comparisons.
9713 If we can reduce the size of a constant, we will do that too. */
9718 /* < C is equivalent to <= (C - 1) */
9722 op1 = GEN_INT (const_op);
9724 /* ... fall through to LE case below. */
9730 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9734 op1 = GEN_INT (const_op);
9738 /* If we are doing a <= 0 comparison on a value known to have
9739 a zero sign bit, we can replace this with == 0. */
9740 else if (const_op == 0
9741 && mode_width <= HOST_BITS_PER_WIDE_INT
9742 && (nonzero_bits (op0, mode)
9743 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9748 /* >= C is equivalent to > (C - 1). */
9752 op1 = GEN_INT (const_op);
9754 /* ... fall through to GT below. */
9760 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9764 op1 = GEN_INT (const_op);
9768 /* If we are doing a > 0 comparison on a value known to have
9769 a zero sign bit, we can replace this with != 0. */
9770 else if (const_op == 0
9771 && mode_width <= HOST_BITS_PER_WIDE_INT
9772 && (nonzero_bits (op0, mode)
9773 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9778 /* < C is equivalent to <= (C - 1). */
9782 op1 = GEN_INT (const_op);
9784 /* ... fall through ... */
9787 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9788 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9789 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9791 const_op = 0, op1 = const0_rtx;
9799 /* unsigned <= 0 is equivalent to == 0 */
9803 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9804 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9805 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9807 const_op = 0, op1 = const0_rtx;
9813 /* >= C is equivalent to > (C - 1). */
9817 op1 = GEN_INT (const_op);
9819 /* ... fall through ... */
9822 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9823 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9824 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9826 const_op = 0, op1 = const0_rtx;
9834 /* unsigned > 0 is equivalent to != 0 */
9838 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9839 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9840 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9842 const_op = 0, op1 = const0_rtx;
9851 /* Compute some predicates to simplify code below. */
9853 equality_comparison_p = (code == EQ || code == NE);
9854 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9855 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9858 /* If this is a sign bit comparison and we can do arithmetic in
9859 MODE, say that we will only be needing the sign bit of OP0. */
9860 if (sign_bit_comparison_p
9861 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9862 op0 = force_to_mode (op0, mode,
9864 << (GET_MODE_BITSIZE (mode) - 1)),
9867 /* Now try cases based on the opcode of OP0. If none of the cases
9868 does a "continue", we exit this loop immediately after the
9871 switch (GET_CODE (op0))
9874 /* If we are extracting a single bit from a variable position in
9875 a constant that has only a single bit set and are comparing it
9876 with zero, we can convert this into an equality comparison
9877 between the position and the location of the single bit. */
9878 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9879 have already reduced the shift count modulo the word size. */
9880 if (!SHIFT_COUNT_TRUNCATED
9881 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9882 && XEXP (op0, 1) == const1_rtx
9883 && equality_comparison_p && const_op == 0
9884 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9886 if (BITS_BIG_ENDIAN)
9888 enum machine_mode new_mode
9889 = mode_for_extraction (EP_extzv, 1);
9890 if (new_mode == MAX_MACHINE_MODE)
9891 i = BITS_PER_WORD - 1 - i;
9895 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9899 op0 = XEXP (op0, 2);
9903 /* Result is nonzero iff shift count is equal to I. */
9904 code = reverse_condition (code);
9908 /* ... fall through ... */
9911 tem = expand_compound_operation (op0);
9920 /* If testing for equality, we can take the NOT of the constant. */
9921 if (equality_comparison_p
9922 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9924 op0 = XEXP (op0, 0);
9929 /* If just looking at the sign bit, reverse the sense of the
9931 if (sign_bit_comparison_p)
9933 op0 = XEXP (op0, 0);
9934 code = (code == GE ? LT : GE);
9940 /* If testing for equality, we can take the NEG of the constant. */
9941 if (equality_comparison_p
9942 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9944 op0 = XEXP (op0, 0);
9949 /* The remaining cases only apply to comparisons with zero. */
9953 /* When X is ABS or is known positive,
9954 (neg X) is < 0 if and only if X != 0. */
9956 if (sign_bit_comparison_p
9957 && (GET_CODE (XEXP (op0, 0)) == ABS
9958 || (mode_width <= HOST_BITS_PER_WIDE_INT
9959 && (nonzero_bits (XEXP (op0, 0), mode)
9960 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9962 op0 = XEXP (op0, 0);
9963 code = (code == LT ? NE : EQ);
9967 /* If we have NEG of something whose two high-order bits are the
9968 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9969 if (num_sign_bit_copies (op0, mode) >= 2)
9971 op0 = XEXP (op0, 0);
9972 code = swap_condition (code);
9978 /* If we are testing equality and our count is a constant, we
9979 can perform the inverse operation on our RHS. */
9980 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9981 && (tem = simplify_binary_operation (ROTATERT, mode,
9982 op1, XEXP (op0, 1))) != 0)
9984 op0 = XEXP (op0, 0);
9989 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9990 a particular bit. Convert it to an AND of a constant of that
9991 bit. This will be converted into a ZERO_EXTRACT. */
9992 if (const_op == 0 && sign_bit_comparison_p
9993 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9994 && mode_width <= HOST_BITS_PER_WIDE_INT)
9996 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9999 - INTVAL (XEXP (op0, 1)))));
10000 code = (code == LT ? NE : EQ);
10004 /* Fall through. */
10007 /* ABS is ignorable inside an equality comparison with zero. */
10008 if (const_op == 0 && equality_comparison_p)
10010 op0 = XEXP (op0, 0);
10016 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10017 to (compare FOO CONST) if CONST fits in FOO's mode and we
10018 are either testing inequality or have an unsigned comparison
10019 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10020 if (! unsigned_comparison_p
10021 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10022 <= HOST_BITS_PER_WIDE_INT)
10023 && ((unsigned HOST_WIDE_INT) const_op
10024 < (((unsigned HOST_WIDE_INT) 1
10025 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10027 op0 = XEXP (op0, 0);
10033 /* Check for the case where we are comparing A - C1 with C2,
10034 both constants are smaller than 1/2 the maximum positive
10035 value in MODE, and the comparison is equality or unsigned.
10036 In that case, if A is either zero-extended to MODE or has
10037 sufficient sign bits so that the high-order bit in MODE
10038 is a copy of the sign in the inner mode, we can prove that it is
10039 safe to do the operation in the wider mode. This simplifies
10040 many range checks. */
10042 if (mode_width <= HOST_BITS_PER_WIDE_INT
10043 && subreg_lowpart_p (op0)
10044 && GET_CODE (SUBREG_REG (op0)) == PLUS
10045 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10046 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10047 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10048 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10049 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10050 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10051 GET_MODE (SUBREG_REG (op0)))
10052 & ~GET_MODE_MASK (mode))
10053 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10054 GET_MODE (SUBREG_REG (op0)))
10056 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10057 - GET_MODE_BITSIZE (mode)))))
10059 op0 = SUBREG_REG (op0);
10063 /* If the inner mode is narrower and we are extracting the low part,
10064 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10065 if (subreg_lowpart_p (op0)
10066 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10067 /* Fall through */ ;
10071 /* ... fall through ... */
10074 if ((unsigned_comparison_p || equality_comparison_p)
10075 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10076 <= HOST_BITS_PER_WIDE_INT)
10077 && ((unsigned HOST_WIDE_INT) const_op
10078 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10080 op0 = XEXP (op0, 0);
10086 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10087 this for equality comparisons due to pathological cases involving
10089 if (equality_comparison_p
10090 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10091 op1, XEXP (op0, 1))))
10093 op0 = XEXP (op0, 0);
10098 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10099 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10100 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10102 op0 = XEXP (XEXP (op0, 0), 0);
10103 code = (code == LT ? EQ : NE);
10109 /* We used to optimize signed comparisons against zero, but that
10110 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10111 arrive here as equality comparisons, or (GEU, LTU) are
10112 optimized away. No need to special-case them. */
10114 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10115 (eq B (minus A C)), whichever simplifies. We can only do
10116 this for equality comparisons due to pathological cases involving
10118 if (equality_comparison_p
10119 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10120 XEXP (op0, 1), op1)))
10122 op0 = XEXP (op0, 0);
10127 if (equality_comparison_p
10128 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10129 XEXP (op0, 0), op1)))
10131 op0 = XEXP (op0, 1);
10136 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10137 of bits in X minus 1, is one iff X > 0. */
10138 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10139 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10140 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10142 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10144 op0 = XEXP (op0, 1);
10145 code = (code == GE ? LE : GT);
10151 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10152 if C is zero or B is a constant. */
10153 if (equality_comparison_p
10154 && 0 != (tem = simplify_binary_operation (XOR, mode,
10155 XEXP (op0, 1), op1)))
10157 op0 = XEXP (op0, 0);
10164 case UNEQ: case LTGT:
10165 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10166 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10167 case UNORDERED: case ORDERED:
10168 /* We can't do anything if OP0 is a condition code value, rather
10169 than an actual data value. */
10171 || CC0_P (XEXP (op0, 0))
10172 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10175 /* Get the two operands being compared. */
10176 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10177 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10179 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10181 /* Check for the cases where we simply want the result of the
10182 earlier test or the opposite of that result. */
10183 if (code == NE || code == EQ
10184 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10185 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10186 && (STORE_FLAG_VALUE
10187 & (((HOST_WIDE_INT) 1
10188 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10189 && (code == LT || code == GE)))
10191 enum rtx_code new_code;
10192 if (code == LT || code == NE)
10193 new_code = GET_CODE (op0);
10195 new_code = combine_reversed_comparison_code (op0);
10197 if (new_code != UNKNOWN)
10208 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10210 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10211 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10212 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10214 op0 = XEXP (op0, 1);
10215 code = (code == GE ? GT : LE);
10221 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10222 will be converted to a ZERO_EXTRACT later. */
10223 if (const_op == 0 && equality_comparison_p
10224 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10225 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10227 op0 = simplify_and_const_int
10228 (op0, mode, gen_rtx_LSHIFTRT (mode,
10230 XEXP (XEXP (op0, 0), 1)),
10231 (HOST_WIDE_INT) 1);
10235 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10236 zero and X is a comparison and C1 and C2 describe only bits set
10237 in STORE_FLAG_VALUE, we can compare with X. */
10238 if (const_op == 0 && equality_comparison_p
10239 && mode_width <= HOST_BITS_PER_WIDE_INT
10240 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10241 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10242 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10243 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10244 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10246 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10247 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10248 if ((~STORE_FLAG_VALUE & mask) == 0
10249 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10250 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10251 && COMPARISON_P (tem))))
10253 op0 = XEXP (XEXP (op0, 0), 0);
10258 /* If we are doing an equality comparison of an AND of a bit equal
10259 to the sign bit, replace this with a LT or GE comparison of
10260 the underlying value. */
10261 if (equality_comparison_p
10263 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10264 && mode_width <= HOST_BITS_PER_WIDE_INT
10265 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10266 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10268 op0 = XEXP (op0, 0);
10269 code = (code == EQ ? GE : LT);
10273 /* If this AND operation is really a ZERO_EXTEND from a narrower
10274 mode, the constant fits within that mode, and this is either an
10275 equality or unsigned comparison, try to do this comparison in
10276 the narrower mode. */
10277 if ((equality_comparison_p || unsigned_comparison_p)
10278 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10279 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10280 & GET_MODE_MASK (mode))
10282 && const_op >> i == 0
10283 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10285 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10289 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10290 fits in both M1 and M2 and the SUBREG is either paradoxical
10291 or represents the low part, permute the SUBREG and the AND
10293 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10295 unsigned HOST_WIDE_INT c1;
10296 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10297 /* Require an integral mode, to avoid creating something like
10299 if (SCALAR_INT_MODE_P (tmode)
10300 /* It is unsafe to commute the AND into the SUBREG if the
10301 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10302 not defined. As originally written the upper bits
10303 have a defined value due to the AND operation.
10304 However, if we commute the AND inside the SUBREG then
10305 they no longer have defined values and the meaning of
10306 the code has been changed. */
10308 #ifdef WORD_REGISTER_OPERATIONS
10309 || (mode_width > GET_MODE_BITSIZE (tmode)
10310 && mode_width <= BITS_PER_WORD)
10312 || (mode_width <= GET_MODE_BITSIZE (tmode)
10313 && subreg_lowpart_p (XEXP (op0, 0))))
10314 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10315 && mode_width <= HOST_BITS_PER_WIDE_INT
10316 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10317 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10318 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10320 && c1 != GET_MODE_MASK (tmode))
10322 op0 = gen_binary (AND, tmode,
10323 SUBREG_REG (XEXP (op0, 0)),
10324 gen_int_mode (c1, tmode));
10325 op0 = gen_lowpart (mode, op0);
10330 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10331 if (const_op == 0 && equality_comparison_p
10332 && XEXP (op0, 1) == const1_rtx
10333 && GET_CODE (XEXP (op0, 0)) == NOT)
10335 op0 = simplify_and_const_int
10336 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10337 code = (code == NE ? EQ : NE);
10341 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10342 (eq (and (lshiftrt X) 1) 0).
10343 Also handle the case where (not X) is expressed using xor. */
10344 if (const_op == 0 && equality_comparison_p
10345 && XEXP (op0, 1) == const1_rtx
10346 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10348 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10349 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10351 if (GET_CODE (shift_op) == NOT
10352 || (GET_CODE (shift_op) == XOR
10353 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10354 && GET_CODE (shift_count) == CONST_INT
10355 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10356 && (INTVAL (XEXP (shift_op, 1))
10357 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10359 op0 = simplify_and_const_int
10361 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10362 (HOST_WIDE_INT) 1);
10363 code = (code == NE ? EQ : NE);
10370 /* If we have (compare (ashift FOO N) (const_int C)) and
10371 the high order N bits of FOO (N+1 if an inequality comparison)
10372 are known to be zero, we can do this by comparing FOO with C
10373 shifted right N bits so long as the low-order N bits of C are
10375 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10376 && INTVAL (XEXP (op0, 1)) >= 0
10377 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10378 < HOST_BITS_PER_WIDE_INT)
10380 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10381 && mode_width <= HOST_BITS_PER_WIDE_INT
10382 && (nonzero_bits (XEXP (op0, 0), mode)
10383 & ~(mask >> (INTVAL (XEXP (op0, 1))
10384 + ! equality_comparison_p))) == 0)
10386 /* We must perform a logical shift, not an arithmetic one,
10387 as we want the top N bits of C to be zero. */
10388 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10390 temp >>= INTVAL (XEXP (op0, 1));
10391 op1 = gen_int_mode (temp, mode);
10392 op0 = XEXP (op0, 0);
10396 /* If we are doing a sign bit comparison, it means we are testing
10397 a particular bit. Convert it to the appropriate AND. */
10398 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10399 && mode_width <= HOST_BITS_PER_WIDE_INT)
10401 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10404 - INTVAL (XEXP (op0, 1)))));
10405 code = (code == LT ? NE : EQ);
10409 /* If this an equality comparison with zero and we are shifting
10410 the low bit to the sign bit, we can convert this to an AND of the
10412 if (const_op == 0 && equality_comparison_p
10413 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10414 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10417 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10418 (HOST_WIDE_INT) 1);
10424 /* If this is an equality comparison with zero, we can do this
10425 as a logical shift, which might be much simpler. */
10426 if (equality_comparison_p && const_op == 0
10427 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10429 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10431 INTVAL (XEXP (op0, 1)));
10435 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10436 do the comparison in a narrower mode. */
10437 if (! unsigned_comparison_p
10438 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10439 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10440 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10441 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10442 MODE_INT, 1)) != BLKmode
10443 && (((unsigned HOST_WIDE_INT) const_op
10444 + (GET_MODE_MASK (tmode) >> 1) + 1)
10445 <= GET_MODE_MASK (tmode)))
10447 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10451 /* Likewise if OP0 is a PLUS of a sign extension with a
10452 constant, which is usually represented with the PLUS
10453 between the shifts. */
10454 if (! unsigned_comparison_p
10455 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10456 && GET_CODE (XEXP (op0, 0)) == PLUS
10457 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10458 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10459 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10460 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10461 MODE_INT, 1)) != BLKmode
10462 && (((unsigned HOST_WIDE_INT) const_op
10463 + (GET_MODE_MASK (tmode) >> 1) + 1)
10464 <= GET_MODE_MASK (tmode)))
10466 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10467 rtx add_const = XEXP (XEXP (op0, 0), 1);
10468 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10471 op0 = gen_binary (PLUS, tmode,
10472 gen_lowpart (tmode, inner),
10477 /* ... fall through ... */
10479 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10480 the low order N bits of FOO are known to be zero, we can do this
10481 by comparing FOO with C shifted left N bits so long as no
10482 overflow occurs. */
10483 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10484 && INTVAL (XEXP (op0, 1)) >= 0
10485 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10486 && mode_width <= HOST_BITS_PER_WIDE_INT
10487 && (nonzero_bits (XEXP (op0, 0), mode)
10488 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10489 && (((unsigned HOST_WIDE_INT) const_op
10490 + (GET_CODE (op0) != LSHIFTRT
10491 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10494 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10496 /* If the shift was logical, then we must make the condition
10498 if (GET_CODE (op0) == LSHIFTRT)
10499 code = unsigned_condition (code);
10501 const_op <<= INTVAL (XEXP (op0, 1));
10502 op1 = GEN_INT (const_op);
10503 op0 = XEXP (op0, 0);
10507 /* If we are using this shift to extract just the sign bit, we
10508 can replace this with an LT or GE comparison. */
10510 && (equality_comparison_p || sign_bit_comparison_p)
10511 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10512 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10515 op0 = XEXP (op0, 0);
10516 code = (code == NE || code == GT ? LT : GE);
10528 /* Now make any compound operations involved in this comparison. Then,
10529 check for an outmost SUBREG on OP0 that is not doing anything or is
10530 paradoxical. The latter transformation must only be performed when
10531 it is known that the "extra" bits will be the same in op0 and op1 or
10532 that they don't matter. There are three cases to consider:
10534 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10535 care bits and we can assume they have any convenient value. So
10536 making the transformation is safe.
10538 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10539 In this case the upper bits of op0 are undefined. We should not make
10540 the simplification in that case as we do not know the contents of
10543 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10544 NIL. In that case we know those bits are zeros or ones. We must
10545 also be sure that they are the same as the upper bits of op1.
10547 We can never remove a SUBREG for a non-equality comparison because
10548 the sign bit is in a different place in the underlying object. */
10550 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10551 op1 = make_compound_operation (op1, SET);
10553 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10554 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10555 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10556 && (code == NE || code == EQ))
10558 if (GET_MODE_SIZE (GET_MODE (op0))
10559 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10561 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10563 if (REG_P (SUBREG_REG (op0)))
10565 op0 = SUBREG_REG (op0);
10566 op1 = gen_lowpart (GET_MODE (op0), op1);
10569 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10570 <= HOST_BITS_PER_WIDE_INT)
10571 && (nonzero_bits (SUBREG_REG (op0),
10572 GET_MODE (SUBREG_REG (op0)))
10573 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10575 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10577 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10578 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10579 op0 = SUBREG_REG (op0), op1 = tem;
10583 /* We now do the opposite procedure: Some machines don't have compare
10584 insns in all modes. If OP0's mode is an integer mode smaller than a
10585 word and we can't do a compare in that mode, see if there is a larger
10586 mode for which we can do the compare. There are a number of cases in
10587 which we can use the wider mode. */
10589 mode = GET_MODE (op0);
10590 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10591 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10592 && ! have_insn_for (COMPARE, mode))
10593 for (tmode = GET_MODE_WIDER_MODE (mode);
10595 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10596 tmode = GET_MODE_WIDER_MODE (tmode))
10597 if (have_insn_for (COMPARE, tmode))
10601 /* If the only nonzero bits in OP0 and OP1 are those in the
10602 narrower mode and this is an equality or unsigned comparison,
10603 we can use the wider mode. Similarly for sign-extended
10604 values, in which case it is true for all comparisons. */
10605 zero_extended = ((code == EQ || code == NE
10606 || code == GEU || code == GTU
10607 || code == LEU || code == LTU)
10608 && (nonzero_bits (op0, tmode)
10609 & ~GET_MODE_MASK (mode)) == 0
10610 && ((GET_CODE (op1) == CONST_INT
10611 || (nonzero_bits (op1, tmode)
10612 & ~GET_MODE_MASK (mode)) == 0)));
10615 || ((num_sign_bit_copies (op0, tmode)
10616 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10617 - GET_MODE_BITSIZE (mode)))
10618 && (num_sign_bit_copies (op1, tmode)
10619 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10620 - GET_MODE_BITSIZE (mode)))))
10622 /* If OP0 is an AND and we don't have an AND in MODE either,
10623 make a new AND in the proper mode. */
10624 if (GET_CODE (op0) == AND
10625 && !have_insn_for (AND, mode))
10626 op0 = gen_binary (AND, tmode,
10627 gen_lowpart (tmode,
10629 gen_lowpart (tmode,
10632 op0 = gen_lowpart (tmode, op0);
10633 if (zero_extended && GET_CODE (op1) == CONST_INT)
10634 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10635 op1 = gen_lowpart (tmode, op1);
10639 /* If this is a test for negative, we can make an explicit
10640 test of the sign bit. */
10642 if (op1 == const0_rtx && (code == LT || code == GE)
10643 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10645 op0 = gen_binary (AND, tmode,
10646 gen_lowpart (tmode, op0),
10647 GEN_INT ((HOST_WIDE_INT) 1
10648 << (GET_MODE_BITSIZE (mode) - 1)));
10649 code = (code == LT) ? NE : EQ;
10654 #ifdef CANONICALIZE_COMPARISON
10655 /* If this machine only supports a subset of valid comparisons, see if we
10656 can convert an unsupported one into a supported one. */
10657 CANONICALIZE_COMPARISON (code, op0, op1);
10666 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10667 searching backward. */
10668 static enum rtx_code
10669 combine_reversed_comparison_code (rtx exp)
10671 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10674 if (code1 != UNKNOWN
10675 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10677 /* Otherwise try and find where the condition codes were last set and
10679 x = get_last_value (XEXP (exp, 0));
10680 if (!x || GET_CODE (x) != COMPARE)
10682 return reversed_comparison_code_parts (GET_CODE (exp),
10683 XEXP (x, 0), XEXP (x, 1), NULL);
10686 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10687 Return NULL_RTX in case we fail to do the reversal. */
10689 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10691 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10692 if (reversed_code == UNKNOWN)
10695 return gen_binary (reversed_code, mode, op0, op1);
10698 /* Utility function for following routine. Called when X is part of a value
10699 being stored into last_set_value. Sets last_set_table_tick
10700 for each register mentioned. Similar to mention_regs in cse.c */
10703 update_table_tick (rtx x)
10705 enum rtx_code code = GET_CODE (x);
10706 const char *fmt = GET_RTX_FORMAT (code);
10711 unsigned int regno = REGNO (x);
10712 unsigned int endregno
10713 = regno + (regno < FIRST_PSEUDO_REGISTER
10714 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10717 for (r = regno; r < endregno; r++)
10718 reg_stat[r].last_set_table_tick = label_tick;
10723 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10724 /* Note that we can't have an "E" in values stored; see
10725 get_last_value_validate. */
10728 /* Check for identical subexpressions. If x contains
10729 identical subexpression we only have to traverse one of
10731 if (i == 0 && ARITHMETIC_P (x))
10733 /* Note that at this point x1 has already been
10735 rtx x0 = XEXP (x, 0);
10736 rtx x1 = XEXP (x, 1);
10738 /* If x0 and x1 are identical then there is no need to
10743 /* If x0 is identical to a subexpression of x1 then while
10744 processing x1, x0 has already been processed. Thus we
10745 are done with x. */
10746 if (ARITHMETIC_P (x1)
10747 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10750 /* If x1 is identical to a subexpression of x0 then we
10751 still have to process the rest of x0. */
10752 if (ARITHMETIC_P (x0)
10753 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10755 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10760 update_table_tick (XEXP (x, i));
10764 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10765 are saying that the register is clobbered and we no longer know its
10766 value. If INSN is zero, don't update reg_stat[].last_set; this is
10767 only permitted with VALUE also zero and is used to invalidate the
10771 record_value_for_reg (rtx reg, rtx insn, rtx value)
10773 unsigned int regno = REGNO (reg);
10774 unsigned int endregno
10775 = regno + (regno < FIRST_PSEUDO_REGISTER
10776 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10779 /* If VALUE contains REG and we have a previous value for REG, substitute
10780 the previous value. */
10781 if (value && insn && reg_overlap_mentioned_p (reg, value))
10785 /* Set things up so get_last_value is allowed to see anything set up to
10787 subst_low_cuid = INSN_CUID (insn);
10788 tem = get_last_value (reg);
10790 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10791 it isn't going to be useful and will take a lot of time to process,
10792 so just use the CLOBBER. */
10796 if (ARITHMETIC_P (tem)
10797 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10798 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10799 tem = XEXP (tem, 0);
10801 value = replace_rtx (copy_rtx (value), reg, tem);
10805 /* For each register modified, show we don't know its value, that
10806 we don't know about its bitwise content, that its value has been
10807 updated, and that we don't know the location of the death of the
10809 for (i = regno; i < endregno; i++)
10812 reg_stat[i].last_set = insn;
10814 reg_stat[i].last_set_value = 0;
10815 reg_stat[i].last_set_mode = 0;
10816 reg_stat[i].last_set_nonzero_bits = 0;
10817 reg_stat[i].last_set_sign_bit_copies = 0;
10818 reg_stat[i].last_death = 0;
10821 /* Mark registers that are being referenced in this value. */
10823 update_table_tick (value);
10825 /* Now update the status of each register being set.
10826 If someone is using this register in this block, set this register
10827 to invalid since we will get confused between the two lives in this
10828 basic block. This makes using this register always invalid. In cse, we
10829 scan the table to invalidate all entries using this register, but this
10830 is too much work for us. */
10832 for (i = regno; i < endregno; i++)
10834 reg_stat[i].last_set_label = label_tick;
10835 if (value && reg_stat[i].last_set_table_tick == label_tick)
10836 reg_stat[i].last_set_invalid = 1;
10838 reg_stat[i].last_set_invalid = 0;
10841 /* The value being assigned might refer to X (like in "x++;"). In that
10842 case, we must replace it with (clobber (const_int 0)) to prevent
10844 if (value && ! get_last_value_validate (&value, insn,
10845 reg_stat[regno].last_set_label, 0))
10847 value = copy_rtx (value);
10848 if (! get_last_value_validate (&value, insn,
10849 reg_stat[regno].last_set_label, 1))
10853 /* For the main register being modified, update the value, the mode, the
10854 nonzero bits, and the number of sign bit copies. */
10856 reg_stat[regno].last_set_value = value;
10860 enum machine_mode mode = GET_MODE (reg);
10861 subst_low_cuid = INSN_CUID (insn);
10862 reg_stat[regno].last_set_mode = mode;
10863 if (GET_MODE_CLASS (mode) == MODE_INT
10864 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10865 mode = nonzero_bits_mode;
10866 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10867 reg_stat[regno].last_set_sign_bit_copies
10868 = num_sign_bit_copies (value, GET_MODE (reg));
10872 /* Called via note_stores from record_dead_and_set_regs to handle one
10873 SET or CLOBBER in an insn. DATA is the instruction in which the
10874 set is occurring. */
10877 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10879 rtx record_dead_insn = (rtx) data;
10881 if (GET_CODE (dest) == SUBREG)
10882 dest = SUBREG_REG (dest);
10886 /* If we are setting the whole register, we know its value. Otherwise
10887 show that we don't know the value. We can handle SUBREG in
10889 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10890 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10891 else if (GET_CODE (setter) == SET
10892 && GET_CODE (SET_DEST (setter)) == SUBREG
10893 && SUBREG_REG (SET_DEST (setter)) == dest
10894 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10895 && subreg_lowpart_p (SET_DEST (setter)))
10896 record_value_for_reg (dest, record_dead_insn,
10897 gen_lowpart (GET_MODE (dest),
10898 SET_SRC (setter)));
10900 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10902 else if (MEM_P (dest)
10903 /* Ignore pushes, they clobber nothing. */
10904 && ! push_operand (dest, GET_MODE (dest)))
10905 mem_last_set = INSN_CUID (record_dead_insn);
10908 /* Update the records of when each REG was most recently set or killed
10909 for the things done by INSN. This is the last thing done in processing
10910 INSN in the combiner loop.
10912 We update reg_stat[], in particular fields last_set, last_set_value,
10913 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10914 last_death, and also the similar information mem_last_set (which insn
10915 most recently modified memory) and last_call_cuid (which insn was the
10916 most recent subroutine call). */
10919 record_dead_and_set_regs (rtx insn)
10924 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10926 if (REG_NOTE_KIND (link) == REG_DEAD
10927 && REG_P (XEXP (link, 0)))
10929 unsigned int regno = REGNO (XEXP (link, 0));
10930 unsigned int endregno
10931 = regno + (regno < FIRST_PSEUDO_REGISTER
10932 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10935 for (i = regno; i < endregno; i++)
10936 reg_stat[i].last_death = insn;
10938 else if (REG_NOTE_KIND (link) == REG_INC)
10939 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10942 if (GET_CODE (insn) == CALL_INSN)
10944 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10945 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10947 reg_stat[i].last_set_value = 0;
10948 reg_stat[i].last_set_mode = 0;
10949 reg_stat[i].last_set_nonzero_bits = 0;
10950 reg_stat[i].last_set_sign_bit_copies = 0;
10951 reg_stat[i].last_death = 0;
10954 last_call_cuid = mem_last_set = INSN_CUID (insn);
10956 /* Don't bother recording what this insn does. It might set the
10957 return value register, but we can't combine into a call
10958 pattern anyway, so there's no point trying (and it may cause
10959 a crash, if e.g. we wind up asking for last_set_value of a
10960 SUBREG of the return value register). */
10964 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10967 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10968 register present in the SUBREG, so for each such SUBREG go back and
10969 adjust nonzero and sign bit information of the registers that are
10970 known to have some zero/sign bits set.
10972 This is needed because when combine blows the SUBREGs away, the
10973 information on zero/sign bits is lost and further combines can be
10974 missed because of that. */
10977 record_promoted_value (rtx insn, rtx subreg)
10980 unsigned int regno = REGNO (SUBREG_REG (subreg));
10981 enum machine_mode mode = GET_MODE (subreg);
10983 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10986 for (links = LOG_LINKS (insn); links;)
10988 insn = XEXP (links, 0);
10989 set = single_set (insn);
10991 if (! set || !REG_P (SET_DEST (set))
10992 || REGNO (SET_DEST (set)) != regno
10993 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10995 links = XEXP (links, 1);
10999 if (reg_stat[regno].last_set == insn)
11001 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11002 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11005 if (REG_P (SET_SRC (set)))
11007 regno = REGNO (SET_SRC (set));
11008 links = LOG_LINKS (insn);
11015 /* Scan X for promoted SUBREGs. For each one found,
11016 note what it implies to the registers used in it. */
11019 check_promoted_subreg (rtx insn, rtx x)
11021 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11022 && REG_P (SUBREG_REG (x)))
11023 record_promoted_value (insn, x);
11026 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11029 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11033 check_promoted_subreg (insn, XEXP (x, i));
11037 if (XVEC (x, i) != 0)
11038 for (j = 0; j < XVECLEN (x, i); j++)
11039 check_promoted_subreg (insn, XVECEXP (x, i, j));
11045 /* Utility routine for the following function. Verify that all the registers
11046 mentioned in *LOC are valid when *LOC was part of a value set when
11047 label_tick == TICK. Return 0 if some are not.
11049 If REPLACE is nonzero, replace the invalid reference with
11050 (clobber (const_int 0)) and return 1. This replacement is useful because
11051 we often can get useful information about the form of a value (e.g., if
11052 it was produced by a shift that always produces -1 or 0) even though
11053 we don't know exactly what registers it was produced from. */
11056 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11059 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11060 int len = GET_RTX_LENGTH (GET_CODE (x));
11065 unsigned int regno = REGNO (x);
11066 unsigned int endregno
11067 = regno + (regno < FIRST_PSEUDO_REGISTER
11068 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11071 for (j = regno; j < endregno; j++)
11072 if (reg_stat[j].last_set_invalid
11073 /* If this is a pseudo-register that was only set once and not
11074 live at the beginning of the function, it is always valid. */
11075 || (! (regno >= FIRST_PSEUDO_REGISTER
11076 && REG_N_SETS (regno) == 1
11077 && (! REGNO_REG_SET_P
11078 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11079 && reg_stat[j].last_set_label > tick))
11082 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11088 /* If this is a memory reference, make sure that there were
11089 no stores after it that might have clobbered the value. We don't
11090 have alias info, so we assume any store invalidates it. */
11091 else if (MEM_P (x) && ! RTX_UNCHANGING_P (x)
11092 && INSN_CUID (insn) <= mem_last_set)
11095 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11099 for (i = 0; i < len; i++)
11103 /* Check for identical subexpressions. If x contains
11104 identical subexpression we only have to traverse one of
11106 if (i == 1 && ARITHMETIC_P (x))
11108 /* Note that at this point x0 has already been checked
11109 and found valid. */
11110 rtx x0 = XEXP (x, 0);
11111 rtx x1 = XEXP (x, 1);
11113 /* If x0 and x1 are identical then x is also valid. */
11117 /* If x1 is identical to a subexpression of x0 then
11118 while checking x0, x1 has already been checked. Thus
11119 it is valid and so as x. */
11120 if (ARITHMETIC_P (x0)
11121 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11124 /* If x0 is identical to a subexpression of x1 then x is
11125 valid iff the rest of x1 is valid. */
11126 if (ARITHMETIC_P (x1)
11127 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11129 get_last_value_validate (&XEXP (x1,
11130 x0 == XEXP (x1, 0) ? 1 : 0),
11131 insn, tick, replace);
11134 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11138 /* Don't bother with these. They shouldn't occur anyway. */
11139 else if (fmt[i] == 'E')
11143 /* If we haven't found a reason for it to be invalid, it is valid. */
11147 /* Get the last value assigned to X, if known. Some registers
11148 in the value may be replaced with (clobber (const_int 0)) if their value
11149 is known longer known reliably. */
11152 get_last_value (rtx x)
11154 unsigned int regno;
11157 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11158 then convert it to the desired mode. If this is a paradoxical SUBREG,
11159 we cannot predict what values the "extra" bits might have. */
11160 if (GET_CODE (x) == SUBREG
11161 && subreg_lowpart_p (x)
11162 && (GET_MODE_SIZE (GET_MODE (x))
11163 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11164 && (value = get_last_value (SUBREG_REG (x))) != 0)
11165 return gen_lowpart (GET_MODE (x), value);
11171 value = reg_stat[regno].last_set_value;
11173 /* If we don't have a value, or if it isn't for this basic block and
11174 it's either a hard register, set more than once, or it's a live
11175 at the beginning of the function, return 0.
11177 Because if it's not live at the beginning of the function then the reg
11178 is always set before being used (is never used without being set).
11179 And, if it's set only once, and it's always set before use, then all
11180 uses must have the same last value, even if it's not from this basic
11184 || (reg_stat[regno].last_set_label != label_tick
11185 && (regno < FIRST_PSEUDO_REGISTER
11186 || REG_N_SETS (regno) != 1
11187 || (REGNO_REG_SET_P
11188 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11191 /* If the value was set in a later insn than the ones we are processing,
11192 we can't use it even if the register was only set once. */
11193 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11196 /* If the value has all its registers valid, return it. */
11197 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11198 reg_stat[regno].last_set_label, 0))
11201 /* Otherwise, make a copy and replace any invalid register with
11202 (clobber (const_int 0)). If that fails for some reason, return 0. */
11204 value = copy_rtx (value);
11205 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11206 reg_stat[regno].last_set_label, 1))
11212 /* Return nonzero if expression X refers to a REG or to memory
11213 that is set in an instruction more recent than FROM_CUID. */
11216 use_crosses_set_p (rtx x, int from_cuid)
11220 enum rtx_code code = GET_CODE (x);
11224 unsigned int regno = REGNO (x);
11225 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11226 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11228 #ifdef PUSH_ROUNDING
11229 /* Don't allow uses of the stack pointer to be moved,
11230 because we don't know whether the move crosses a push insn. */
11231 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11234 for (; regno < endreg; regno++)
11235 if (reg_stat[regno].last_set
11236 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11241 if (code == MEM && mem_last_set > from_cuid)
11244 fmt = GET_RTX_FORMAT (code);
11246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11251 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11252 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11255 else if (fmt[i] == 'e'
11256 && use_crosses_set_p (XEXP (x, i), from_cuid))
11262 /* Define three variables used for communication between the following
11265 static unsigned int reg_dead_regno, reg_dead_endregno;
11266 static int reg_dead_flag;
11268 /* Function called via note_stores from reg_dead_at_p.
11270 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11271 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11274 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11276 unsigned int regno, endregno;
11281 regno = REGNO (dest);
11282 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11283 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11285 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11286 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11289 /* Return nonzero if REG is known to be dead at INSN.
11291 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11292 referencing REG, it is dead. If we hit a SET referencing REG, it is
11293 live. Otherwise, see if it is live or dead at the start of the basic
11294 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11295 must be assumed to be always live. */
11298 reg_dead_at_p (rtx reg, rtx insn)
11303 /* Set variables for reg_dead_at_p_1. */
11304 reg_dead_regno = REGNO (reg);
11305 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11306 ? hard_regno_nregs[reg_dead_regno]
11312 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11313 we allow the machine description to decide whether use-and-clobber
11314 patterns are OK. */
11315 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11317 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11318 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11322 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11323 beginning of function. */
11324 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11325 insn = prev_nonnote_insn (insn))
11327 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11329 return reg_dead_flag == 1 ? 1 : 0;
11331 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11335 /* Get the basic block that we were in. */
11337 block = ENTRY_BLOCK_PTR->next_bb;
11340 FOR_EACH_BB (block)
11341 if (insn == BB_HEAD (block))
11344 if (block == EXIT_BLOCK_PTR)
11348 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11349 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11355 /* Note hard registers in X that are used. This code is similar to
11356 that in flow.c, but much simpler since we don't care about pseudos. */
11359 mark_used_regs_combine (rtx x)
11361 RTX_CODE code = GET_CODE (x);
11362 unsigned int regno;
11375 case ADDR_DIFF_VEC:
11378 /* CC0 must die in the insn after it is set, so we don't need to take
11379 special note of it here. */
11385 /* If we are clobbering a MEM, mark any hard registers inside the
11386 address as used. */
11387 if (MEM_P (XEXP (x, 0)))
11388 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11393 /* A hard reg in a wide mode may really be multiple registers.
11394 If so, mark all of them just like the first. */
11395 if (regno < FIRST_PSEUDO_REGISTER)
11397 unsigned int endregno, r;
11399 /* None of this applies to the stack, frame or arg pointers. */
11400 if (regno == STACK_POINTER_REGNUM
11401 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11402 || regno == HARD_FRAME_POINTER_REGNUM
11404 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11405 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11407 || regno == FRAME_POINTER_REGNUM)
11410 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11411 for (r = regno; r < endregno; r++)
11412 SET_HARD_REG_BIT (newpat_used_regs, r);
11418 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11420 rtx testreg = SET_DEST (x);
11422 while (GET_CODE (testreg) == SUBREG
11423 || GET_CODE (testreg) == ZERO_EXTRACT
11424 || GET_CODE (testreg) == SIGN_EXTRACT
11425 || GET_CODE (testreg) == STRICT_LOW_PART)
11426 testreg = XEXP (testreg, 0);
11428 if (MEM_P (testreg))
11429 mark_used_regs_combine (XEXP (testreg, 0));
11431 mark_used_regs_combine (SET_SRC (x));
11439 /* Recursively scan the operands of this expression. */
11442 const char *fmt = GET_RTX_FORMAT (code);
11444 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11447 mark_used_regs_combine (XEXP (x, i));
11448 else if (fmt[i] == 'E')
11452 for (j = 0; j < XVECLEN (x, i); j++)
11453 mark_used_regs_combine (XVECEXP (x, i, j));
11459 /* Remove register number REGNO from the dead registers list of INSN.
11461 Return the note used to record the death, if there was one. */
11464 remove_death (unsigned int regno, rtx insn)
11466 rtx note = find_regno_note (insn, REG_DEAD, regno);
11470 REG_N_DEATHS (regno)--;
11471 remove_note (insn, note);
11477 /* For each register (hardware or pseudo) used within expression X, if its
11478 death is in an instruction with cuid between FROM_CUID (inclusive) and
11479 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11480 list headed by PNOTES.
11482 That said, don't move registers killed by maybe_kill_insn.
11484 This is done when X is being merged by combination into TO_INSN. These
11485 notes will then be distributed as needed. */
11488 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11493 enum rtx_code code = GET_CODE (x);
11497 unsigned int regno = REGNO (x);
11498 rtx where_dead = reg_stat[regno].last_death;
11499 rtx before_dead, after_dead;
11501 /* Don't move the register if it gets killed in between from and to. */
11502 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11503 && ! reg_referenced_p (x, maybe_kill_insn))
11506 /* WHERE_DEAD could be a USE insn made by combine, so first we
11507 make sure that we have insns with valid INSN_CUID values. */
11508 before_dead = where_dead;
11509 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11510 before_dead = PREV_INSN (before_dead);
11512 after_dead = where_dead;
11513 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11514 after_dead = NEXT_INSN (after_dead);
11516 if (before_dead && after_dead
11517 && INSN_CUID (before_dead) >= from_cuid
11518 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11519 || (where_dead != after_dead
11520 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11522 rtx note = remove_death (regno, where_dead);
11524 /* It is possible for the call above to return 0. This can occur
11525 when last_death points to I2 or I1 that we combined with.
11526 In that case make a new note.
11528 We must also check for the case where X is a hard register
11529 and NOTE is a death note for a range of hard registers
11530 including X. In that case, we must put REG_DEAD notes for
11531 the remaining registers in place of NOTE. */
11533 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11534 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11535 > GET_MODE_SIZE (GET_MODE (x))))
11537 unsigned int deadregno = REGNO (XEXP (note, 0));
11538 unsigned int deadend
11539 = (deadregno + hard_regno_nregs[deadregno]
11540 [GET_MODE (XEXP (note, 0))]);
11541 unsigned int ourend
11542 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11545 for (i = deadregno; i < deadend; i++)
11546 if (i < regno || i >= ourend)
11547 REG_NOTES (where_dead)
11548 = gen_rtx_EXPR_LIST (REG_DEAD,
11550 REG_NOTES (where_dead));
11553 /* If we didn't find any note, or if we found a REG_DEAD note that
11554 covers only part of the given reg, and we have a multi-reg hard
11555 register, then to be safe we must check for REG_DEAD notes
11556 for each register other than the first. They could have
11557 their own REG_DEAD notes lying around. */
11558 else if ((note == 0
11560 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11561 < GET_MODE_SIZE (GET_MODE (x)))))
11562 && regno < FIRST_PSEUDO_REGISTER
11563 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11565 unsigned int ourend
11566 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11567 unsigned int i, offset;
11571 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11575 for (i = regno + offset; i < ourend; i++)
11576 move_deaths (regno_reg_rtx[i],
11577 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11580 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11582 XEXP (note, 1) = *pnotes;
11586 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11588 REG_N_DEATHS (regno)++;
11594 else if (GET_CODE (x) == SET)
11596 rtx dest = SET_DEST (x);
11598 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11600 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11601 that accesses one word of a multi-word item, some
11602 piece of everything register in the expression is used by
11603 this insn, so remove any old death. */
11604 /* ??? So why do we test for equality of the sizes? */
11606 if (GET_CODE (dest) == ZERO_EXTRACT
11607 || GET_CODE (dest) == STRICT_LOW_PART
11608 || (GET_CODE (dest) == SUBREG
11609 && (((GET_MODE_SIZE (GET_MODE (dest))
11610 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11611 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11612 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11614 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11618 /* If this is some other SUBREG, we know it replaces the entire
11619 value, so use that as the destination. */
11620 if (GET_CODE (dest) == SUBREG)
11621 dest = SUBREG_REG (dest);
11623 /* If this is a MEM, adjust deaths of anything used in the address.
11624 For a REG (the only other possibility), the entire value is
11625 being replaced so the old value is not used in this insn. */
11628 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11633 else if (GET_CODE (x) == CLOBBER)
11636 len = GET_RTX_LENGTH (code);
11637 fmt = GET_RTX_FORMAT (code);
11639 for (i = 0; i < len; i++)
11644 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11645 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11648 else if (fmt[i] == 'e')
11649 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11653 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11654 pattern of an insn. X must be a REG. */
11657 reg_bitfield_target_p (rtx x, rtx body)
11661 if (GET_CODE (body) == SET)
11663 rtx dest = SET_DEST (body);
11665 unsigned int regno, tregno, endregno, endtregno;
11667 if (GET_CODE (dest) == ZERO_EXTRACT)
11668 target = XEXP (dest, 0);
11669 else if (GET_CODE (dest) == STRICT_LOW_PART)
11670 target = SUBREG_REG (XEXP (dest, 0));
11674 if (GET_CODE (target) == SUBREG)
11675 target = SUBREG_REG (target);
11677 if (!REG_P (target))
11680 tregno = REGNO (target), regno = REGNO (x);
11681 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11682 return target == x;
11684 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11685 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11687 return endregno > tregno && regno < endtregno;
11690 else if (GET_CODE (body) == PARALLEL)
11691 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11692 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11698 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11699 as appropriate. I3 and I2 are the insns resulting from the combination
11700 insns including FROM (I2 may be zero).
11702 Each note in the list is either ignored or placed on some insns, depending
11703 on the type of note. */
11706 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11708 rtx note, next_note;
11711 for (note = notes; note; note = next_note)
11713 rtx place = 0, place2 = 0;
11715 /* If this NOTE references a pseudo register, ensure it references
11716 the latest copy of that register. */
11717 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11718 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11719 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11721 next_note = XEXP (note, 1);
11722 switch (REG_NOTE_KIND (note))
11726 /* Doesn't matter much where we put this, as long as it's somewhere.
11727 It is preferable to keep these notes on branches, which is most
11728 likely to be i3. */
11732 case REG_VALUE_PROFILE:
11733 /* Just get rid of this note, as it is unused later anyway. */
11736 case REG_VTABLE_REF:
11737 /* ??? Should remain with *a particular* memory load. Given the
11738 nature of vtable data, the last insn seems relatively safe. */
11742 case REG_NON_LOCAL_GOTO:
11743 if (GET_CODE (i3) == JUMP_INSN)
11745 else if (i2 && GET_CODE (i2) == JUMP_INSN)
11751 case REG_EH_REGION:
11752 /* These notes must remain with the call or trapping instruction. */
11753 if (GET_CODE (i3) == CALL_INSN)
11755 else if (i2 && GET_CODE (i2) == CALL_INSN)
11757 else if (flag_non_call_exceptions)
11759 if (may_trap_p (i3))
11761 else if (i2 && may_trap_p (i2))
11763 /* ??? Otherwise assume we've combined things such that we
11764 can now prove that the instructions can't trap. Drop the
11765 note in this case. */
11771 case REG_ALWAYS_RETURN:
11774 /* These notes must remain with the call. It should not be
11775 possible for both I2 and I3 to be a call. */
11776 if (GET_CODE (i3) == CALL_INSN)
11778 else if (i2 && GET_CODE (i2) == CALL_INSN)
11785 /* Any clobbers for i3 may still exist, and so we must process
11786 REG_UNUSED notes from that insn.
11788 Any clobbers from i2 or i1 can only exist if they were added by
11789 recog_for_combine. In that case, recog_for_combine created the
11790 necessary REG_UNUSED notes. Trying to keep any original
11791 REG_UNUSED notes from these insns can cause incorrect output
11792 if it is for the same register as the original i3 dest.
11793 In that case, we will notice that the register is set in i3,
11794 and then add a REG_UNUSED note for the destination of i3, which
11795 is wrong. However, it is possible to have REG_UNUSED notes from
11796 i2 or i1 for register which were both used and clobbered, so
11797 we keep notes from i2 or i1 if they will turn into REG_DEAD
11800 /* If this register is set or clobbered in I3, put the note there
11801 unless there is one already. */
11802 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11804 if (from_insn != i3)
11807 if (! (REG_P (XEXP (note, 0))
11808 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11809 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11812 /* Otherwise, if this register is used by I3, then this register
11813 now dies here, so we must put a REG_DEAD note here unless there
11815 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11816 && ! (REG_P (XEXP (note, 0))
11817 ? find_regno_note (i3, REG_DEAD,
11818 REGNO (XEXP (note, 0)))
11819 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11821 PUT_REG_NOTE_KIND (note, REG_DEAD);
11829 /* These notes say something about results of an insn. We can
11830 only support them if they used to be on I3 in which case they
11831 remain on I3. Otherwise they are ignored.
11833 If the note refers to an expression that is not a constant, we
11834 must also ignore the note since we cannot tell whether the
11835 equivalence is still true. It might be possible to do
11836 slightly better than this (we only have a problem if I2DEST
11837 or I1DEST is present in the expression), but it doesn't
11838 seem worth the trouble. */
11840 if (from_insn == i3
11841 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11846 case REG_NO_CONFLICT:
11847 /* These notes say something about how a register is used. They must
11848 be present on any use of the register in I2 or I3. */
11849 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11852 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11862 /* This can show up in several ways -- either directly in the
11863 pattern, or hidden off in the constant pool with (or without?)
11864 a REG_EQUAL note. */
11865 /* ??? Ignore the without-reg_equal-note problem for now. */
11866 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11867 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11868 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11869 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11873 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11874 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11875 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11876 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11884 /* Don't attach REG_LABEL note to a JUMP_INSN which has
11885 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
11886 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
11888 if (JUMP_LABEL (place) != XEXP (note, 0))
11890 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
11891 LABEL_NUSES (JUMP_LABEL (place))--;
11894 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
11896 if (JUMP_LABEL (place2) != XEXP (note, 0))
11898 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
11899 LABEL_NUSES (JUMP_LABEL (place2))--;
11905 /* This note says something about the value of a register prior
11906 to the execution of an insn. It is too much trouble to see
11907 if the note is still correct in all situations. It is better
11908 to simply delete it. */
11912 /* If the insn previously containing this note still exists,
11913 put it back where it was. Otherwise move it to the previous
11914 insn. Adjust the corresponding REG_LIBCALL note. */
11915 if (GET_CODE (from_insn) != NOTE)
11919 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11920 place = prev_real_insn (from_insn);
11922 XEXP (tem, 0) = place;
11923 /* If we're deleting the last remaining instruction of a
11924 libcall sequence, don't add the notes. */
11925 else if (XEXP (note, 0) == from_insn)
11927 /* Don't add the dangling REG_RETVAL note. */
11934 /* This is handled similarly to REG_RETVAL. */
11935 if (GET_CODE (from_insn) != NOTE)
11939 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11940 place = next_real_insn (from_insn);
11942 XEXP (tem, 0) = place;
11943 /* If we're deleting the last remaining instruction of a
11944 libcall sequence, don't add the notes. */
11945 else if (XEXP (note, 0) == from_insn)
11947 /* Don't add the dangling REG_LIBCALL note. */
11954 /* If the register is used as an input in I3, it dies there.
11955 Similarly for I2, if it is nonzero and adjacent to I3.
11957 If the register is not used as an input in either I3 or I2
11958 and it is not one of the registers we were supposed to eliminate,
11959 there are two possibilities. We might have a non-adjacent I2
11960 or we might have somehow eliminated an additional register
11961 from a computation. For example, we might have had A & B where
11962 we discover that B will always be zero. In this case we will
11963 eliminate the reference to A.
11965 In both cases, we must search to see if we can find a previous
11966 use of A and put the death note there. */
11969 && GET_CODE (from_insn) == CALL_INSN
11970 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11972 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11974 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11975 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11980 basic_block bb = this_basic_block;
11982 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11984 if (! INSN_P (tem))
11986 if (tem == BB_HEAD (bb))
11991 /* If the register is being set at TEM, see if that is all
11992 TEM is doing. If so, delete TEM. Otherwise, make this
11993 into a REG_UNUSED note instead. Don't delete sets to
11994 global register vars. */
11995 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11996 || !global_regs[REGNO (XEXP (note, 0))])
11997 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11999 rtx set = single_set (tem);
12000 rtx inner_dest = 0;
12002 rtx cc0_setter = NULL_RTX;
12006 for (inner_dest = SET_DEST (set);
12007 (GET_CODE (inner_dest) == STRICT_LOW_PART
12008 || GET_CODE (inner_dest) == SUBREG
12009 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12010 inner_dest = XEXP (inner_dest, 0))
12013 /* Verify that it was the set, and not a clobber that
12014 modified the register.
12016 CC0 targets must be careful to maintain setter/user
12017 pairs. If we cannot delete the setter due to side
12018 effects, mark the user with an UNUSED note instead
12021 if (set != 0 && ! side_effects_p (SET_SRC (set))
12022 && rtx_equal_p (XEXP (note, 0), inner_dest)
12024 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12025 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12026 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12030 /* Move the notes and links of TEM elsewhere.
12031 This might delete other dead insns recursively.
12032 First set the pattern to something that won't use
12034 rtx old_notes = REG_NOTES (tem);
12036 PATTERN (tem) = pc_rtx;
12037 REG_NOTES (tem) = NULL;
12039 distribute_notes (old_notes, tem, tem, NULL_RTX);
12040 distribute_links (LOG_LINKS (tem));
12042 SET_INSN_DELETED (tem);
12045 /* Delete the setter too. */
12048 PATTERN (cc0_setter) = pc_rtx;
12049 old_notes = REG_NOTES (cc0_setter);
12050 REG_NOTES (cc0_setter) = NULL;
12052 distribute_notes (old_notes, cc0_setter,
12053 cc0_setter, NULL_RTX);
12054 distribute_links (LOG_LINKS (cc0_setter));
12056 SET_INSN_DELETED (cc0_setter);
12062 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12064 /* If there isn't already a REG_UNUSED note, put one
12065 here. Do not place a REG_DEAD note, even if
12066 the register is also used here; that would not
12067 match the algorithm used in lifetime analysis
12068 and can cause the consistency check in the
12069 scheduler to fail. */
12070 if (! find_regno_note (tem, REG_UNUSED,
12071 REGNO (XEXP (note, 0))))
12076 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12077 || (GET_CODE (tem) == CALL_INSN
12078 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12082 /* If we are doing a 3->2 combination, and we have a
12083 register which formerly died in i3 and was not used
12084 by i2, which now no longer dies in i3 and is used in
12085 i2 but does not die in i2, and place is between i2
12086 and i3, then we may need to move a link from place to
12088 if (i2 && INSN_UID (place) <= max_uid_cuid
12089 && INSN_CUID (place) > INSN_CUID (i2)
12091 && INSN_CUID (from_insn) > INSN_CUID (i2)
12092 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12094 rtx links = LOG_LINKS (place);
12095 LOG_LINKS (place) = 0;
12096 distribute_links (links);
12101 if (tem == BB_HEAD (bb))
12105 /* We haven't found an insn for the death note and it
12106 is still a REG_DEAD note, but we have hit the beginning
12107 of the block. If the existing life info says the reg
12108 was dead, there's nothing left to do. Otherwise, we'll
12109 need to do a global life update after combine. */
12110 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12111 && REGNO_REG_SET_P (bb->global_live_at_start,
12112 REGNO (XEXP (note, 0))))
12113 SET_BIT (refresh_blocks, this_basic_block->index);
12116 /* If the register is set or already dead at PLACE, we needn't do
12117 anything with this note if it is still a REG_DEAD note.
12118 We check here if it is set at all, not if is it totally replaced,
12119 which is what `dead_or_set_p' checks, so also check for it being
12122 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12124 unsigned int regno = REGNO (XEXP (note, 0));
12126 /* Similarly, if the instruction on which we want to place
12127 the note is a noop, we'll need do a global live update
12128 after we remove them in delete_noop_moves. */
12129 if (noop_move_p (place))
12130 SET_BIT (refresh_blocks, this_basic_block->index);
12132 if (dead_or_set_p (place, XEXP (note, 0))
12133 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12135 /* Unless the register previously died in PLACE, clear
12136 last_death. [I no longer understand why this is
12138 if (reg_stat[regno].last_death != place)
12139 reg_stat[regno].last_death = 0;
12143 reg_stat[regno].last_death = place;
12145 /* If this is a death note for a hard reg that is occupying
12146 multiple registers, ensure that we are still using all
12147 parts of the object. If we find a piece of the object
12148 that is unused, we must arrange for an appropriate REG_DEAD
12149 note to be added for it. However, we can't just emit a USE
12150 and tag the note to it, since the register might actually
12151 be dead; so we recourse, and the recursive call then finds
12152 the previous insn that used this register. */
12154 if (place && regno < FIRST_PSEUDO_REGISTER
12155 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12157 unsigned int endregno
12158 = regno + hard_regno_nregs[regno]
12159 [GET_MODE (XEXP (note, 0))];
12163 for (i = regno; i < endregno; i++)
12164 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12165 && ! find_regno_fusage (place, USE, i))
12166 || dead_or_set_regno_p (place, i))
12171 /* Put only REG_DEAD notes for pieces that are
12172 not already dead or set. */
12174 for (i = regno; i < endregno;
12175 i += hard_regno_nregs[i][reg_raw_mode[i]])
12177 rtx piece = regno_reg_rtx[i];
12178 basic_block bb = this_basic_block;
12180 if (! dead_or_set_p (place, piece)
12181 && ! reg_bitfield_target_p (piece,
12185 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12187 distribute_notes (new_note, place, place,
12190 else if (! refers_to_regno_p (i, i + 1,
12191 PATTERN (place), 0)
12192 && ! find_regno_fusage (place, USE, i))
12193 for (tem = PREV_INSN (place); ;
12194 tem = PREV_INSN (tem))
12196 if (! INSN_P (tem))
12198 if (tem == BB_HEAD (bb))
12200 SET_BIT (refresh_blocks,
12201 this_basic_block->index);
12206 if (dead_or_set_p (tem, piece)
12207 || reg_bitfield_target_p (piece,
12211 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12226 /* Any other notes should not be present at this point in the
12233 XEXP (note, 1) = REG_NOTES (place);
12234 REG_NOTES (place) = note;
12236 else if ((REG_NOTE_KIND (note) == REG_DEAD
12237 || REG_NOTE_KIND (note) == REG_UNUSED)
12238 && REG_P (XEXP (note, 0)))
12239 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12243 if ((REG_NOTE_KIND (note) == REG_DEAD
12244 || REG_NOTE_KIND (note) == REG_UNUSED)
12245 && REG_P (XEXP (note, 0)))
12246 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12248 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12249 REG_NOTE_KIND (note),
12251 REG_NOTES (place2));
12256 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12257 I3, I2, and I1 to new locations. This is also called to add a link
12258 pointing at I3 when I3's destination is changed. */
12261 distribute_links (rtx links)
12263 rtx link, next_link;
12265 for (link = links; link; link = next_link)
12271 next_link = XEXP (link, 1);
12273 /* If the insn that this link points to is a NOTE or isn't a single
12274 set, ignore it. In the latter case, it isn't clear what we
12275 can do other than ignore the link, since we can't tell which
12276 register it was for. Such links wouldn't be used by combine
12279 It is not possible for the destination of the target of the link to
12280 have been changed by combine. The only potential of this is if we
12281 replace I3, I2, and I1 by I3 and I2. But in that case the
12282 destination of I2 also remains unchanged. */
12284 if (GET_CODE (XEXP (link, 0)) == NOTE
12285 || (set = single_set (XEXP (link, 0))) == 0)
12288 reg = SET_DEST (set);
12289 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12290 || GET_CODE (reg) == SIGN_EXTRACT
12291 || GET_CODE (reg) == STRICT_LOW_PART)
12292 reg = XEXP (reg, 0);
12294 /* A LOG_LINK is defined as being placed on the first insn that uses
12295 a register and points to the insn that sets the register. Start
12296 searching at the next insn after the target of the link and stop
12297 when we reach a set of the register or the end of the basic block.
12299 Note that this correctly handles the link that used to point from
12300 I3 to I2. Also note that not much searching is typically done here
12301 since most links don't point very far away. */
12303 for (insn = NEXT_INSN (XEXP (link, 0));
12304 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12305 || BB_HEAD (this_basic_block->next_bb) != insn));
12306 insn = NEXT_INSN (insn))
12307 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12309 if (reg_referenced_p (reg, PATTERN (insn)))
12313 else if (GET_CODE (insn) == CALL_INSN
12314 && find_reg_fusage (insn, USE, reg))
12319 else if (INSN_P (insn) && reg_set_p (reg, insn))
12322 /* If we found a place to put the link, place it there unless there
12323 is already a link to the same insn as LINK at that point. */
12329 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12330 if (XEXP (link2, 0) == XEXP (link, 0))
12335 XEXP (link, 1) = LOG_LINKS (place);
12336 LOG_LINKS (place) = link;
12338 /* Set added_links_insn to the earliest insn we added a
12340 if (added_links_insn == 0
12341 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12342 added_links_insn = place;
12348 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12349 Check whether the expression pointer to by LOC is a register or
12350 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12351 Otherwise return zero. */
12354 unmentioned_reg_p_1 (rtx *loc, void *expr)
12359 && (REG_P (x) || MEM_P (x))
12360 && ! reg_mentioned_p (x, (rtx) expr))
12365 /* Check for any register or memory mentioned in EQUIV that is not
12366 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12367 of EXPR where some registers may have been replaced by constants. */
12370 unmentioned_reg_p (rtx equiv, rtx expr)
12372 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12375 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12378 insn_cuid (rtx insn)
12380 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12381 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12382 insn = NEXT_INSN (insn);
12384 if (INSN_UID (insn) > max_uid_cuid)
12387 return INSN_CUID (insn);
12391 dump_combine_stats (FILE *file)
12395 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12396 combine_attempts, combine_merges, combine_extras, combine_successes);
12400 dump_combine_total_stats (FILE *file)
12404 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12405 total_attempts, total_merges, total_extras, total_successes);
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