1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-flags.h"
87 #include "insn-codes.h"
88 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
129 /* Maximum register number, which is the size of the tables below. */
131 static int combine_max_regno;
133 /* Record last point of death of (hard or pseudo) register n. */
135 static rtx *reg_last_death;
137 /* Record last point of modification of (hard or pseudo) register n. */
139 static rtx *reg_last_set;
141 /* Record the cuid of the last insn that invalidated memory
142 (anything that writes memory, and subroutine calls, but not pushes). */
144 static int mem_last_set;
146 /* Record the cuid of the last CALL_INSN
147 so we can tell whether a potential combination crosses any calls. */
149 static int last_call_cuid;
151 /* When `subst' is called, this is the insn that is being modified
152 (by combining in a previous insn). The PATTERN of this insn
153 is still the old pattern partially modified and it should not be
154 looked at, but this may be used to examine the successors of the insn
155 to judge whether a simplification is valid. */
157 static rtx subst_insn;
159 /* This is the lowest CUID that `subst' is currently dealing with.
160 get_last_value will not return a value if the register was set at or
161 after this CUID. If not for this mechanism, we could get confused if
162 I2 or I1 in try_combine were an insn that used the old value of a register
163 to obtain a new value. In that case, we might erroneously get the
164 new value of the register when we wanted the old one. */
166 static int subst_low_cuid;
168 /* This is the value of undobuf.num_undo when we started processing this
169 substitution. This will prevent gen_rtx_combine from re-used a piece
170 from the previous expression. Doing so can produce circular rtl
173 static int previous_num_undos;
175 /* The next group of arrays allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if a
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following arrays:
190 reg_last_set_value the last value assigned
191 reg_last_set_label records the value of label_tick when the
192 register was assigned
193 reg_last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 reg_last_set_invalid set to non-zero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in reg_last_set_value being valid
201 and the register being validly contained in some other expression in the
204 Entry I in reg_last_set_value is valid if it is non-zero, and either
205 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
207 Register I may validly appear in any expression returned for the value
208 of another register if reg_n_sets[i] is 1. It may also appear in the
209 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210 reg_last_set_invalid[j] is zero.
212 If an expression is found in the table containing a register which may
213 not validly appear in an expression, the register is replaced by
214 something that won't match, (clobber (const_int 0)).
216 reg_last_set_invalid[i] is set non-zero when register I is being assigned
217 to and reg_last_set_table_tick[i] == label_tick. */
219 /* Record last value assigned to (hard or pseudo) register n. */
221 static rtx *reg_last_set_value;
223 /* Record the value of label_tick when the value for register n is placed in
224 reg_last_set_value[n]. */
226 static short *reg_last_set_label;
228 /* Record the value of label_tick when an expression involving register n
229 is placed in reg_last_set_value. */
231 static short *reg_last_set_table_tick;
233 /* Set non-zero if references to register n in expressions should not be
236 static char *reg_last_set_invalid;
238 /* Incremented for each label. */
240 static short label_tick;
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
244 a QImode register may be loaded from memory in two places on a machine
245 where byte loads zero extend.
247 We record in the following array what we know about the significant
248 bits of a register, specifically which bits are known to be zero.
250 If an entry is zero, it means that we don't know anything special. */
252 static int *reg_significant;
254 /* Mode used to compute significance in reg_significant. It is the largest
255 integer mode that can fit in HOST_BITS_PER_INT. */
257 static enum machine_mode significant_mode;
259 /* Nonzero when reg_significant can be safely used. It is zero while
260 computing reg_significant. This prevents propagating values based
261 on previously set values, which can be incorrect if a variable
262 is modified in a loop. */
264 static int significant_valid;
266 /* Record one modification to rtl structure
267 to be undone by storing old_contents into *where.
268 is_int is 1 if the contents are an int. */
284 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285 num_undo says how many are currently recorded.
287 storage is nonzero if we must undo the allocation of new storage.
288 The value of storage is what to pass to obfree.
290 other_insn is nonzero if we have modified some other insn in the process
291 of working on subst_insn. It must be verified too. */
299 struct undo undo[MAX_UNDO];
303 static struct undobuf undobuf;
305 /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some
306 insn. The substitution can be undone by undo_all. If INTO is already
307 set to NEWVAL, do not record this change. */
309 #define SUBST(INTO, NEWVAL) \
310 do { if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].where = &INTO; \
313 undobuf.undo[undobuf.num_undo].old_contents = INTO; \
314 undobuf.undo[undobuf.num_undo].is_int = 0; \
316 if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
329 = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
330 u->where = (int *) &INTO; \
331 u->old_contents = INTO; \
334 if (u->old_contents != INTO) \
335 undobuf.num_undo++; \
339 /* Number of times the pseudo being substituted for
340 was found and replaced. */
342 static int n_occurrences;
344 static void set_significant ();
345 static void move_deaths ();
347 static void record_value_for_reg ();
348 static void record_dead_and_set_regs ();
349 static int use_crosses_set_p ();
350 static rtx try_combine ();
351 static rtx *find_split_point ();
353 static void undo_all ();
354 static int reg_dead_at_p ();
355 static rtx expand_compound_operation ();
356 static rtx expand_field_assignment ();
357 static rtx make_extraction ();
358 static int get_pos_from_mask ();
359 static rtx force_to_mode ();
360 static rtx make_field_assignment ();
361 static rtx make_compound_operation ();
362 static rtx apply_distributive_law ();
363 static rtx simplify_and_const_int ();
364 static unsigned significant_bits ();
365 static int merge_outer_ops ();
366 static rtx simplify_shift_const ();
367 static int recog_for_combine ();
368 static rtx gen_lowpart_for_combine ();
369 static rtx gen_rtx_combine ();
370 static rtx gen_binary ();
371 static rtx gen_unary ();
372 static enum rtx_code simplify_comparison ();
373 static int reversible_comparison_p ();
374 static int get_last_value_validate ();
375 static rtx get_last_value ();
376 static void distribute_notes ();
377 static void distribute_links ();
379 /* Main entry point for combiner. F is the first insn of the function.
380 NREGS is the first unused pseudo-reg number. */
383 combine_instructions (f, nregs)
387 register rtx insn, next, prev;
389 register rtx links, nextlinks;
391 combine_attempts = 0;
394 combine_successes = 0;
396 combine_max_regno = nregs;
398 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
401 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
403 reg_last_set_invalid = (char *) alloca (nregs * sizeof (short));
404 reg_significant = (int *) alloca (nregs * sizeof (int));
406 bzero (reg_last_death, nregs * sizeof (rtx));
407 bzero (reg_last_set, nregs * sizeof (rtx));
408 bzero (reg_last_set_value, nregs * sizeof (rtx));
409 bzero (reg_last_set_table_tick, nregs * sizeof (short));
410 bzero (reg_last_set_invalid, nregs * sizeof (char));
411 bzero (reg_significant, nregs * sizeof (int));
413 init_recog_no_volatile ();
415 /* Compute maximum uid value so uid_cuid can be allocated. */
417 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
418 if (INSN_UID (insn) > i)
421 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
423 significant_mode = mode_for_size (HOST_BITS_PER_INT, MODE_INT, 0);
425 /* Don't use reg_significant when computing it. This can cause problems
426 when, for example, we have j <<= 1 in a loop. */
428 significant_valid = 0;
430 /* Compute the mapping from uids to cuids.
431 Cuids are numbers assigned to insns, like uids,
432 except that cuids increase monotonically through the code.
434 Scan all SETs and see if we can deduce anything about what
435 bits are significant for some registers. */
437 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
439 INSN_CUID (insn) = ++i;
440 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
441 note_stores (PATTERN (insn), set_significant);
444 significant_valid = 1;
446 /* Now scan all the insns in forward order. */
452 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
456 if (GET_CODE (insn) == CODE_LABEL)
459 else if (GET_CODE (insn) == INSN
460 || GET_CODE (insn) == CALL_INSN
461 || GET_CODE (insn) == JUMP_INSN)
463 /* Try this insn with each insn it links back to. */
465 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
466 if ((next = try_combine (insn, XEXP (links, 0), 0)) != 0)
469 /* Try each sequence of three linked insns ending with this one. */
471 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
472 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
473 nextlinks = XEXP (nextlinks, 1))
474 if ((next = try_combine (insn, XEXP (links, 0),
475 XEXP (nextlinks, 0))) != 0)
479 /* Try to combine a jump insn that uses CC0
480 with a preceding insn that sets CC0, and maybe with its
481 logical predecessor as well.
482 This is how we make decrement-and-branch insns.
483 We need this special code because data flow connections
484 via CC0 do not get entered in LOG_LINKS. */
486 if (GET_CODE (insn) == JUMP_INSN
487 && (prev = prev_nonnote_insn (insn)) != 0
488 && GET_CODE (prev) == INSN
489 && sets_cc0_p (PATTERN (prev)))
491 if ((next = try_combine (insn, prev, 0)) != 0)
494 for (nextlinks = LOG_LINKS (prev); nextlinks;
495 nextlinks = XEXP (nextlinks, 1))
496 if ((next = try_combine (insn, prev,
497 XEXP (nextlinks, 0))) != 0)
501 /* Do the same for an insn that explicitly references CC0. */
502 if (GET_CODE (insn) == INSN
503 && (prev = prev_nonnote_insn (insn)) != 0
504 && GET_CODE (prev) == INSN
505 && sets_cc0_p (PATTERN (prev))
506 && GET_CODE (PATTERN (insn)) == SET
507 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
509 if ((next = try_combine (insn, prev, 0)) != 0)
512 for (nextlinks = LOG_LINKS (prev); nextlinks;
513 nextlinks = XEXP (nextlinks, 1))
514 if ((next = try_combine (insn, prev,
515 XEXP (nextlinks, 0))) != 0)
519 /* Finally, see if any of the insns that this insn links to
520 explicitly references CC0. If so, try this insn, that insn,
521 and its predecessor if it sets CC0. */
522 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
523 if (GET_CODE (XEXP (links, 0)) == INSN
524 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
525 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
526 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
527 && GET_CODE (prev) == INSN
528 && sets_cc0_p (PATTERN (prev))
529 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
533 /* Try combining an insn with two different insns whose results it
535 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
536 for (nextlinks = XEXP (links, 1); nextlinks;
537 nextlinks = XEXP (nextlinks, 1))
538 if ((next = try_combine (insn, XEXP (links, 0),
539 XEXP (nextlinks, 0))) != 0)
542 if (GET_CODE (insn) != NOTE)
543 record_dead_and_set_regs (insn);
550 total_attempts += combine_attempts;
551 total_merges += combine_merges;
552 total_extras += combine_extras;
553 total_successes += combine_successes;
556 /* Called via note_stores. If X is a pseudo that is used in more than
557 one basic block, is narrower that HOST_BITS_PER_INT, and is being
558 set, record what bits are significant. If we are clobbering X,
559 ignore this "set" because the clobbered value won't be used.
561 If we are setting only a portion of X and we can't figure out what
562 portion, assume all bits will be used since we don't know what will
566 set_significant (x, set)
570 if (GET_CODE (x) == REG
571 && REGNO (x) >= FIRST_PSEUDO_REGISTER
572 && reg_n_sets[REGNO (x)] > 1
573 && reg_basic_block[REGNO (x)] < 0
574 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_INT)
576 if (GET_CODE (set) == CLOBBER)
579 /* If this is a complex assignment, see if we can convert it into a
580 simple assignment. */
581 set = expand_field_assignment (set);
582 if (SET_DEST (set) == x)
583 reg_significant[REGNO (x)]
584 |= significant_bits (SET_SRC (set), significant_mode);
586 reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
590 /* See if INSN can be combined into I3. PRED and SUCC are optionally
591 insns that were previously combined into I3 or that will be combined
592 into the merger of INSN and I3.
594 Return 0 if the combination is not allowed for any reason.
596 If the combination is allowed, *PDEST will be set to the single
597 destination of INSN and *PSRC to the single source, and this function
601 can_combine_p (insn, i3, pred, succ, pdest, psrc)
608 rtx set = 0, src, dest;
610 int all_adjacent = (succ ? (next_active_insn (insn) == succ
611 && next_active_insn (succ) == i3)
612 : next_active_insn (insn) == i3);
614 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
615 or a PARALLEL consisting of such a SET and CLOBBERs.
617 If INSN has CLOBBER parallel parts, ignore them for our processing.
618 By definition, these happen during the execution of the insn. When it
619 is merged with another insn, all bets are off. If they are, in fact,
620 needed and aren't also supplied in I3, they may be added by
621 recog_for_combine. Otherwise, it won't match.
623 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
626 Get the source and destination of INSN. If more than one, can't
629 if (GET_CODE (PATTERN (insn)) == SET)
630 set = PATTERN (insn);
631 else if (GET_CODE (PATTERN (insn)) == PARALLEL
632 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
634 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
636 rtx elt = XVECEXP (PATTERN (insn), 0, i);
638 switch (GET_CODE (elt))
640 /* We can ignore CLOBBERs. */
645 /* Ignore SETs whose result isn't used but not those that
646 have side-effects. */
647 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
648 && ! side_effects_p (elt))
651 /* If we have already found a SET, this is a second one and
652 so we cannot combine with this insn. */
660 /* Anything else means we can't combine. */
666 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
667 so don't do anything with it. */
668 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
677 set = expand_field_assignment (set);
678 src = SET_SRC (set), dest = SET_DEST (set);
680 /* Don't eliminate a store in the stack pointer. */
681 if (dest == stack_pointer_rtx
682 /* Don't install a subreg involving two modes not tieable.
683 It can worsen register allocation, and can even make invalid reload
684 insns, since the reg inside may need to be copied from in the
685 outside mode, and that may be invalid if it is an fp reg copied in
686 integer mode. As a special exception, we can allow this if
687 I3 is simply copying DEST, a REG, to CC0. */
688 || (GET_CODE (src) == SUBREG
689 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
691 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
692 && SET_DEST (PATTERN (i3)) == cc0_rtx
693 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
696 /* If we couldn't eliminate a field assignment, we can't combine. */
697 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
698 /* Don't combine with an insn that sets a register to itself if it has
699 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
700 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, 0))
701 /* Can't merge a function call. */
702 || GET_CODE (src) == CALL
703 /* Don't substitute into an incremented register. */
704 || FIND_REG_INC_NOTE (i3, dest)
705 || (succ && FIND_REG_INC_NOTE (succ, dest))
706 /* Don't combine the end of a libcall into anything. */
707 || find_reg_note (insn, REG_RETVAL, 0)
708 /* Make sure that DEST is not used after SUCC but before I3. */
709 || (succ && ! all_adjacent
710 && reg_used_between_p (dest, succ, i3))
711 /* Make sure that the value that is to be substituted for the register
712 does not use any registers whose values alter in between. However,
713 If the insns are adjacent, a use can't cross a set even though we
714 think it might (this can happen for a sequence of insns each setting
715 the same destination; reg_last_set of that register might point to
716 a NOTE). Also, don't move a volatile asm across any other insns. */
718 && (use_crosses_set_p (src, INSN_CUID (insn))
719 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
720 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
721 better register allocation by not doing the combine. */
722 || find_reg_note (i3, REG_NO_CONFLICT, dest)
723 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
724 /* Don't combine across a CALL_INSN, because that would possibly
725 change whether the life span of some REGs crosses calls or not,
726 and it is a pain to update that information.
727 Exception: if source is a constant, moving it later can't hurt.
728 Accept that special case, because it helps -fforce-addr a lot. */
729 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
732 /* DEST must either be a REG or CC0. */
733 if (GET_CODE (dest) == REG)
735 /* If register alignment is being enforced for multi-word items in all
736 cases except for parameters, it is possible to have a register copy
737 insn referencing a hard register that is not allowed to contain the
738 mode being copied and which would not be valid as an operand of most
739 insns. Eliminate this problem by not combining with such an insn.
741 Also, on some machines we don't want to extend the life of a hard
744 if (GET_CODE (src) == REG
745 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
746 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
747 #ifdef SMALL_REGISTER_CLASSES
748 /* Don't extend the life of a hard register. */
749 || REGNO (src) < FIRST_PSEUDO_REGISTER
751 || (REGNO (src) < FIRST_PSEUDO_REGISTER
752 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
757 else if (GET_CODE (dest) != CC0)
760 /* Don't substitute for a register intended as a clobberable operand. */
761 if (GET_CODE (PATTERN (i3)) == PARALLEL)
762 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
763 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
764 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))
767 /* If INSN contains anything volatile, or is an `asm' (whether volatile
768 or not), reject, unless nothing volatile comes between it and I3,
769 with the exception of SUCC. */
771 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
772 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
773 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
774 && p != succ && volatile_refs_p (PATTERN (p)))
777 /* If INSN or I2 contains an autoincrement or autodecrement,
778 make sure that register is not used between there and I3,
779 and not already used in I3 either.
780 Also insist that I3 not be a jump; if it were one
781 and the incremented register were spilled, we would lose. */
784 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
785 if (REG_NOTE_KIND (link) == REG_INC
786 && (GET_CODE (i3) == JUMP_INSN
787 || reg_used_between_p (XEXP (link, 0), insn, i3)
788 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
793 /* Don't combine an insn that follows a CC0-setting insn.
794 An insn that uses CC0 must not be separated from the one that sets it.
795 We do, however, allow I2 to follow a CC0-setting insn if that insn
796 is passed as I1; in that case it will be deleted also.
797 We also allow combining in this case if all the insns are adjacent
798 because that would leave the two CC0 insns adjacent as well.
799 It would be more logical to test whether CC0 occurs inside I1 or I2,
800 but that would be much slower, and this ought to be equivalent. */
802 p = prev_nonnote_insn (insn);
803 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
808 /* If we get here, we have passed all the tests and the combination is
817 /* LOC is the location within I3 that contains its pattern or the component
818 of a PARALLEL of the pattern. We validate that it is valid for combining.
820 One problem is if I3 modifies its output, as opposed to replacing it
821 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
822 so would produce an insn that is not equivalent to the original insns.
826 (set (reg:DI 101) (reg:DI 100))
827 (set (subreg:SI (reg:DI 101) 0) <foo>)
829 This is NOT equivalent to:
831 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
832 (set (reg:DI 101) (reg:DI 100))])
834 Not only does this modify 100 (in which case it might still be valid
835 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
837 We can also run into a problem if I2 sets a register that I1
838 uses and I1 gets directly substituted into I3 (not via I2). In that
839 case, we would be getting the wrong value of I2DEST into I3, so we
840 must reject the combination. This case occurs when I2 and I1 both
841 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
842 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
843 of a SET must prevent combination from occurring.
845 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
846 if the destination of a SET is a hard register.
848 Before doing the above check, we first try to expand a field assignment
849 into a set of logical operations.
851 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
852 we place a register that is both set and used within I3. If more than one
853 such register is detected, we fail.
855 Return 1 if the combination is valid, zero otherwise. */
858 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
868 if (GET_CODE (x) == SET)
870 rtx set = expand_field_assignment (x);
871 rtx dest = SET_DEST (set);
872 rtx src = SET_SRC (set);
873 rtx inner_dest = dest, inner_src = src;
877 while (GET_CODE (inner_dest) == STRICT_LOW_PART
878 || GET_CODE (inner_dest) == SUBREG
879 || GET_CODE (inner_dest) == ZERO_EXTRACT)
880 inner_dest = XEXP (inner_dest, 0);
882 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
885 while (GET_CODE (inner_src) == STRICT_LOW_PART
886 || GET_CODE (inner_src) == SUBREG
887 || GET_CODE (inner_src) == ZERO_EXTRACT)
888 inner_src = XEXP (inner_src, 0);
890 /* If it is better that two different modes keep two different pseudos,
891 avoid combining them. This avoids producing the following pattern
893 (set (subreg:SI (reg/v:QI 21) 0)
894 (lshiftrt:SI (reg/v:SI 20)
896 If that were made, reload could not handle the pair of
897 reg 20/21, since it would try to get any GENERAL_REGS
898 but some of them don't handle QImode. */
900 if (rtx_equal_p (inner_src, i2dest)
901 && GET_CODE (inner_dest) == REG
902 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
906 /* Check for the case where I3 modifies its output, as
908 if ((inner_dest != dest
909 && (reg_overlap_mentioned_p (i2dest, inner_dest)
910 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
911 /* This is the same test done in can_combine_p except that we
912 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
914 || (GET_CODE (inner_dest) == REG
915 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
916 #ifdef SMALL_REGISTER_CLASSES
917 && GET_CODE (src) != CALL
919 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
920 GET_MODE (inner_dest))
924 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
927 /* If DEST is used in I3, it is being killed in this insn,
928 so record that for later. */
929 if (pi3dest_killed && GET_CODE (dest) == REG
930 && reg_referenced_p (dest, PATTERN (i3)))
935 *pi3dest_killed = dest;
939 else if (GET_CODE (x) == PARALLEL)
943 for (i = 0; i < XVECLEN (x, 0); i++)
944 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
945 i1_not_in_src, pi3dest_killed))
952 /* Try to combine the insns I1 and I2 into I3.
953 Here I1 and I2 appear earlier than I3.
954 I1 can be zero; then we combine just I2 into I3.
956 It we are combining three insns and the resulting insn is not recognized,
957 try splitting it into two insns. If that happens, I2 and I3 are retained
958 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
961 If we created two insns, return I2; otherwise return I3.
962 Return 0 if the combination does not work. Then nothing is changed. */
965 try_combine (i3, i2, i1)
966 register rtx i3, i2, i1;
968 /* New patterns for I3 and I3, respectively. */
969 rtx newpat, newi2pat = 0;
970 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
971 int added_sets_1, added_sets_2;
972 /* Total number of SETs to put into I3. */
974 /* Nonzero is I2's body now appears in I3. */
976 /* INSN_CODEs for new I3, new I2, and user of condition code. */
977 int insn_code_number, i2_code_number, other_code_number;
978 /* Contains I3 if the destination of I3 is used in its source, which means
979 that the old life of I3 is being killed. If that usage is placed into
980 I2 and not in I3, a REG_DEAD note must be made. */
981 rtx i3dest_killed = 0;
982 /* SET_DEST and SET_SRC of I2 and I1. */
983 rtx i2dest, i2src, i1dest = 0, i1src = 0;
984 /* PATTERN (I2), or a copy of it in certain cases. */
986 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
987 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
989 /* Notes that must be added to REG_NOTES in I3 and I2. */
990 rtx new_i3_notes, new_i2_notes;
997 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
998 This can occur when flow deletes an insn that it has merged into an
999 auto-increment address. We also can't do anything if I3 has a
1000 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1003 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1004 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1005 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1006 || find_reg_note (i3, REG_LIBCALL, 0))
1011 undobuf.num_undo = previous_num_undos = 0;
1012 undobuf.other_insn = 0;
1014 /* Save the current high-water-mark so we can free storage if we didn't
1015 accept this combination. */
1016 undobuf.storage = (char *) oballoc (0);
1018 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1019 code below, set I1 to be the earlier of the two insns. */
1020 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1021 temp = i1, i1 = i2, i2 = temp;
1023 /* First check for one important special-case that the code below will
1024 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1025 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1026 we may be able to replace that destination with the destination of I3.
1027 This occurs in the common code where we compute both a quotient and
1028 remainder into a structure, in which case we want to do the computation
1029 directly into the structure to avoid register-register copies.
1031 We make very conservative checks below and only try to handle the
1032 most common cases of this. For example, we only handle the case
1033 where I2 and I3 are adjacent to avoid making difficult register
1036 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1037 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1038 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1039 #ifdef SMALL_REGISTER_CLASSES
1040 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1041 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1043 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1044 && GET_CODE (PATTERN (i2)) == PARALLEL
1045 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1046 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1047 below would need to check what is inside (and reg_overlap_mentioned_p
1048 doesn't support those codes anyway). Don't allow those destinations;
1049 the resulting insn isn't likely to be recognized anyway. */
1050 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1051 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1052 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1053 SET_DEST (PATTERN (i3)))
1054 && next_real_insn (i2) == i3)
1056 rtx p2 = PATTERN (i2);
1058 /* Make sure that the destination of I3,
1059 which we are going to substitute into one output of I2,
1060 is not used within another output of I2. We must avoid making this:
1061 (parallel [(set (mem (reg 69)) ...)
1062 (set (reg 69) ...)])
1063 which is not well-defined as to order of actions.
1064 (Besides, reload can't handle output reloads for this.)
1066 The problem can also happen if the dest of I3 is a memory ref,
1067 if another dest in I2 is an indirect memory ref. */
1068 for (i = 0; i < XVECLEN (p2, 0); i++)
1069 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1070 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1071 SET_DEST (XVECEXP (p2, 0, i))))
1074 if (i == XVECLEN (p2, 0))
1075 for (i = 0; i < XVECLEN (p2, 0); i++)
1076 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1081 subst_low_cuid = INSN_CUID (i2);
1084 i2dest = SET_SRC (PATTERN (i3));
1086 /* Replace the dest in I2 with our dest and make the resulting
1087 insn the new pattern for I3. Then skip to where we
1088 validate the pattern. Everything was set up above. */
1089 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1090 SET_DEST (PATTERN (i3)));
1093 goto validate_replacement;
1098 /* If we have no I1 and I2 looks like:
1099 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1101 make up a dummy I1 that is
1104 (set (reg:CC X) (compare:CC Y (const_int 0)))
1106 (We can ignore any trailing CLOBBERs.)
1108 This undoes a previous combination and allows us to match a branch-and-
1111 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1112 && XVECLEN (PATTERN (i2), 0) >= 2
1113 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1114 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1116 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1117 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1118 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1119 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1120 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1121 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1123 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1124 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1129 /* We make I1 with the same INSN_UID as I2. This gives it
1130 the same INSN_CUID for value tracking. Our fake I1 will
1131 never appear in the insn stream so giving it the same INSN_UID
1132 as I2 will not cause a problem. */
1134 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1135 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1137 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1138 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1139 SET_DEST (PATTERN (i1)));
1144 /* Verify that I2 and I1 are valid for combining. */
1145 if (! can_combine_p (i2, i3, i1, 0, &i2dest, &i2src)
1146 || (i1 && ! can_combine_p (i1, i3, 0, i2, &i1dest, &i1src)))
1152 /* Record whether I2DEST is used in I2SRC and similarly for the other
1153 cases. Knowing this will help in register status updating below. */
1154 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1155 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1156 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1158 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1160 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1162 /* Ensure that I3's pattern can be the destination of combines. */
1163 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1164 i1 && i2dest_in_i1src && i1_feeds_i3,
1171 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1172 We used to do this EXCEPT in one case: I3 has a post-inc in an
1173 output operand. However, that exception can give rise to insns like
1175 which is a famous insn on the PDP-11 where the value of r3 used as the
1176 source was model-dependent. Avoid this sort of thing. */
1179 if (!(GET_CODE (PATTERN (i3)) == SET
1180 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1181 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1182 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1183 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1184 /* It's not the exception. */
1187 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1188 if (REG_NOTE_KIND (link) == REG_INC
1189 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1191 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1198 /* See if the SETs in I1 or I2 need to be kept around in the merged
1199 instruction: whenever the value set there is still needed past I3.
1200 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1202 For the SET in I1, we have two cases: If I1 and I2 independently
1203 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1204 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1205 in I1 needs to be kept around unless I1DEST dies or is set in either
1206 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1207 I1DEST. If so, we know I1 feeds into I2. */
1209 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1212 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1213 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1215 /* If the set in I2 needs to be kept around, we must make a copy of
1216 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1217 PATTERN (I2), we are only substituting for the original I1DEST, not into
1218 an already-substituted copy. This also prevents making self-referential
1219 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1222 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1223 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1227 i2pat = copy_rtx (i2pat);
1231 /* Substitute in the latest insn for the regs set by the earlier ones. */
1233 maxreg = max_reg_num ();
1236 subst_low_cuid = i1 ? INSN_CUID (i1) : INSN_CUID (i2);
1238 /* It is possible that the source of I2 or I1 may be performing an
1239 unneeded operation, such as a ZERO_EXTEND of something that is known
1240 to have the high part zero. Handle that case by letting subst look at
1241 the innermost one of them.
1243 Another way to do this would be to have a function that tries to
1244 simplify a single insn instead of merging two or more insns. We don't
1245 do this because of the potential of infinite loops and because
1246 of the potential extra memory required. However, doing it the way
1247 we are is a bit of a kludge and doesn't catch all cases.
1249 But only do this if -fexpensive-optimizations since it slows things down
1250 and doesn't usually win. */
1252 if (flag_expensive_optimizations)
1254 /* Pass pc_rtx so no substitutions are done, just simplifications.
1255 The cases that we are interested in here do not involve the few
1256 cases were is_replaced is checked. */
1258 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1260 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1262 previous_num_undos = undobuf.num_undo;
1266 /* Many machines that don't use CC0 have insns that can both perform an
1267 arithmetic operation and set the condition code. These operations will
1268 be represented as a PARALLEL with the first element of the vector
1269 being a COMPARE of an arithmetic operation with the constant zero.
1270 The second element of the vector will set some pseudo to the result
1271 of the same arithmetic operation. If we simplify the COMPARE, we won't
1272 match such a pattern and so will generate an extra insn. Here we test
1273 for this case, where both the comparison and the operation result are
1274 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1275 I2SRC. Later we will make the PARALLEL that contains I2. */
1277 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1278 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1279 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1280 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1283 enum machine_mode compare_mode;
1285 newpat = PATTERN (i3);
1286 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1290 #ifdef EXTRA_CC_MODES
1291 /* See if a COMPARE with the operand we substituted in should be done
1292 with the mode that is currently being used. If not, do the same
1293 processing we do in `subst' for a SET; namely, if the destination
1294 is used only once, try to replace it with a register of the proper
1295 mode and also replace the COMPARE. */
1296 if (undobuf.other_insn == 0
1297 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1298 &undobuf.other_insn))
1299 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1301 != GET_MODE (SET_DEST (newpat))))
1303 int regno = REGNO (SET_DEST (newpat));
1304 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1306 if (regno < FIRST_PSEUDO_REGISTER
1307 || (reg_n_sets[regno] == 1 && ! added_sets_2
1308 && ! REG_USERVAR_P (SET_DEST (newpat))))
1310 if (regno >= FIRST_PSEUDO_REGISTER)
1311 SUBST (regno_reg_rtx[regno], new_dest);
1313 SUBST (SET_DEST (newpat), new_dest);
1314 SUBST (XEXP (*cc_use, 0), new_dest);
1315 SUBST (SET_SRC (newpat),
1316 gen_rtx_combine (COMPARE, compare_mode,
1317 i2src, const0_rtx));
1320 undobuf.other_insn = 0;
1327 n_occurrences = 0; /* `subst' counts here */
1329 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1330 need to make a unique copy of I2SRC each time we substitute it
1331 to avoid self-referential rtl. */
1333 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1334 ! i1_feeds_i3 && i1dest_in_i1src);
1335 previous_num_undos = undobuf.num_undo;
1337 /* Record whether i2's body now appears within i3's body. */
1338 i2_is_used = n_occurrences;
1341 /* If we already got a failure, don't try to do more. Otherwise,
1342 try to substitute in I1 if we have it. */
1344 if (i1 && GET_CODE (newpat) != CLOBBER)
1346 /* Before we can do this substitution, we must redo the test done
1347 above (see detailed comments there) that ensures that I1DEST
1348 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1350 if (! combinable_i3pat (0, &newpat, i1dest, 0, 0, 0))
1357 newpat = subst (newpat, i1dest, i1src, 0, 0);
1358 previous_num_undos = undobuf.num_undo;
1361 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1362 to count all the ways that I2SRC and I1SRC can be used. */
1363 if ((FIND_REG_INC_NOTE (i2, 0) != 0
1364 && i2_is_used + added_sets_2 > 1)
1365 || (i1 != 0 && FIND_REG_INC_NOTE (i1, 0) != 0
1366 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1368 /* Fail if we tried to make a new register (we used to abort, but there's
1369 really no reason to). */
1370 || max_reg_num () != maxreg
1371 /* Fail if we couldn't do something and have a CLOBBER. */
1372 || GET_CODE (newpat) == CLOBBER)
1378 /* If the actions of the earlier insns must be kept
1379 in addition to substituting them into the latest one,
1380 we must make a new PARALLEL for the latest insn
1381 to hold additional the SETs. */
1383 if (added_sets_1 || added_sets_2)
1387 if (GET_CODE (newpat) == PARALLEL)
1389 rtvec old = XVEC (newpat, 0);
1390 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1391 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1392 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1393 sizeof (old->elem[0]) * old->num_elem);
1398 total_sets = 1 + added_sets_1 + added_sets_2;
1399 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1400 XVECEXP (newpat, 0, 0) = old;
1404 XVECEXP (newpat, 0, --total_sets)
1405 = (GET_CODE (PATTERN (i1)) == PARALLEL
1406 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1410 /* If there is no I1, use I2's body as is. We used to also not do
1411 the subst call below if I2 was substituted into I3,
1412 but that could lose a simplification. */
1414 XVECEXP (newpat, 0, --total_sets) = i2pat;
1416 /* See comment where i2pat is assigned. */
1417 XVECEXP (newpat, 0, --total_sets)
1418 = subst (i2pat, i1dest, i1src, 0, 0);
1422 /* We come here when we are replacing a destination in I2 with the
1423 destination of I3. */
1424 validate_replacement:
1426 /* Is the result of combination a valid instruction? */
1427 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1429 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1430 the second SET's destination is a register that is unused. In that case,
1431 we just need the first SET. This can occur when simplifying a divmod
1432 insn. We *must* test for this case here because the code below that
1433 splits two independent SETs doesn't handle this case correctly when it
1434 updates the register status. Also check the case where the first
1435 SET's destination is unused. That would not cause incorrect code, but
1436 does cause an unneeded insn to remain. */
1438 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1439 && XVECLEN (newpat, 0) == 2
1440 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1441 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1442 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1443 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1444 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1445 && asm_noperands (newpat) < 0)
1447 newpat = XVECEXP (newpat, 0, 0);
1448 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1451 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1452 && XVECLEN (newpat, 0) == 2
1453 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1454 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1455 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1456 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1457 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1458 && asm_noperands (newpat) < 0)
1460 newpat = XVECEXP (newpat, 0, 1);
1461 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1464 /* If we were combining three insns and the result is a simple SET
1465 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1466 insns. There are two ways to do this. It can be split using a
1467 machine-specific method (like when you have an addition of a large
1468 constant) or by combine in the function find_split_point. */
1470 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1471 && asm_noperands (newpat) < 0)
1473 rtx m_split, *split;
1474 rtx ni2dest = i2dest;
1476 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1477 use I2DEST as a scratch register will help. In the latter case,
1478 convert I2DEST to the mode of the source of NEWPAT if we can. */
1480 m_split = split_insns (newpat, i3);
1483 /* If I2DEST is a hard register or the only use of a pseudo,
1484 we can change its mode. */
1485 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1486 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1487 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1488 && ! REG_USERVAR_P (i2dest))))
1489 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1492 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1493 gen_rtvec (2, newpat,
1500 if (m_split && GET_CODE (m_split) == SEQUENCE
1501 && XVECLEN (m_split, 0) == 2
1502 && (next_real_insn (i2) == i3
1503 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1506 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1507 newpat = PATTERN (XVECEXP (m_split, 0, 1));
1509 /* In case we changed the mode of I2DEST, replace it in the
1510 pseudo-register table here. We can't do it above in case this
1511 code doesn't get executed and we do a split the other way. */
1513 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1514 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1516 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1517 if (i2_code_number >= 0)
1518 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1521 /* If we can split it and use I2DEST, go ahead and see if that
1522 helps things be recognized. Verify that none of the registers
1523 are set between I2 and I3. */
1524 else if ((split = find_split_point (&newpat)) != 0
1526 && GET_CODE (i2dest) == REG
1528 /* We need I2DEST in the proper mode. If it is a hard register
1529 or the only use of a pseudo, we can change its mode. */
1530 && (GET_MODE (*split) == GET_MODE (i2dest)
1531 || GET_MODE (*split) == VOIDmode
1532 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1533 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1534 && ! REG_USERVAR_P (i2dest)))
1535 && (next_real_insn (i2) == i3
1536 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1537 /* We can't overwrite I2DEST if its value is still used by
1539 && ! reg_referenced_p (i2dest, newpat))
1541 rtx newdest = i2dest;
1543 /* Get NEWDEST as a register in the proper mode. We have already
1544 validated that we can do this. */
1545 if (GET_MODE (i2dest) != GET_MODE (*split)
1546 && GET_MODE (*split) != VOIDmode)
1548 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1550 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1551 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1554 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1555 an ASHIFT. This can occur if it was inside a PLUS and hence
1556 appeared to be a memory address. This is a kludge. */
1557 if (GET_CODE (*split) == MULT
1558 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1559 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1560 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1562 gen_rtx (CONST_INT, VOIDmode, i)));
1564 #ifdef INSN_SCHEDULING
1565 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1566 be written as a ZERO_EXTEND. */
1567 if (GET_CODE (*split) == SUBREG
1568 && GET_CODE (SUBREG_REG (*split)) == MEM)
1569 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1573 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1574 SUBST (*split, newdest);
1575 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1576 if (i2_code_number >= 0)
1577 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1581 /* Check for a case where we loaded from memory in a narrow mode and
1582 then sign extended it, but we need both registers. In that case,
1583 we have a PARALLEL with both loads from the same memory location.
1584 We can split this into a load from memory followed by a register-register
1585 copy. This saves at least one insn, more if register allocation can
1586 eliminate the copy. */
1588 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1589 && GET_CODE (newpat) == PARALLEL
1590 && XVECLEN (newpat, 0) == 2
1591 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1592 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1593 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1594 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1595 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1596 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1598 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1599 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1600 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1601 SET_SRC (XVECEXP (newpat, 0, 1)))
1602 && ! find_reg_note (i3, REG_UNUSED,
1603 SET_DEST (XVECEXP (newpat, 0, 0))))
1605 newi2pat = XVECEXP (newpat, 0, 0);
1606 newpat = XVECEXP (newpat, 0, 1);
1607 SUBST (SET_SRC (newpat),
1608 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)),
1609 SET_DEST (newi2pat)));
1610 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1611 if (i2_code_number >= 0)
1612 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1614 if (insn_code_number >= 0)
1619 /* If we will be able to accept this, we have made a change to the
1620 destination of I3. This can invalidate a LOG_LINKS pointing
1621 to I3. No other part of combine.c makes such a transformation.
1623 The new I3 will have a destination that was previously the
1624 destination of I1 or I2 and which was used in i2 or I3. Call
1625 distribute_links to make a LOG_LINK from the next use of
1626 that destination. */
1628 PATTERN (i3) = newpat;
1629 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, 0));
1631 /* I3 now uses what used to be its destination and which is
1632 now I2's destination. That means we need a LOG_LINK from
1633 I3 to I2. But we used to have one, so we still will.
1635 However, some later insn might be using I2's dest and have
1636 a LOG_LINK pointing at I3. We must remove this link.
1637 The simplest way to remove the link is to point it at I1,
1638 which we know will be a NOTE. */
1640 for (insn = NEXT_INSN (i3);
1641 insn && GET_CODE (insn) != CODE_LABEL
1642 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1643 insn = NEXT_INSN (insn))
1645 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1646 && reg_referenced_p (SET_DEST (newi2pat), PATTERN (insn)))
1648 for (link = LOG_LINKS (insn); link;
1649 link = XEXP (link, 1))
1650 if (XEXP (link, 0) == i3)
1651 XEXP (link, 0) = i1;
1659 /* Similarly, check for a case where we have a PARALLEL of two independent
1660 SETs but we started with three insns. In this case, we can do the sets
1661 as two separate insns. This case occurs when some SET allows two
1662 other insns to combine, but the destination of that SET is still live. */
1664 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1665 && GET_CODE (newpat) == PARALLEL
1666 && XVECLEN (newpat, 0) == 2
1667 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1668 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1669 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1670 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1671 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1672 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1673 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1675 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1676 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1677 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1678 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1679 XVECEXP (newpat, 0, 0))
1680 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1681 XVECEXP (newpat, 0, 1)))
1683 newi2pat = XVECEXP (newpat, 0, 1);
1684 newpat = XVECEXP (newpat, 0, 0);
1686 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1687 if (i2_code_number >= 0)
1688 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1691 /* If it still isn't recognized, fail and change things back the way they
1693 if ((insn_code_number < 0
1694 /* Is the result a reasonable ASM_OPERANDS? */
1695 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1701 /* If we had to change another insn, make sure it is valid also. */
1702 if (undobuf.other_insn)
1704 rtx other_notes = REG_NOTES (undobuf.other_insn);
1705 rtx other_pat = PATTERN (undobuf.other_insn);
1706 rtx new_other_notes;
1709 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1712 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1718 PATTERN (undobuf.other_insn) = other_pat;
1720 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1721 are still valid. Then add any non-duplicate notes added by
1722 recog_for_combine. */
1723 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1725 next = XEXP (note, 1);
1727 if (REG_NOTE_KIND (note) == REG_UNUSED
1728 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1729 remove_note (undobuf.other_insn, note);
1732 distribute_notes (new_other_notes, undobuf.other_insn,
1733 undobuf.other_insn, 0, 0, 0);
1736 /* We now know that we can do this combination. Merge the insns and
1737 update the status of registers and LOG_LINKS. */
1740 rtx i3notes, i2notes, i1notes = 0;
1741 rtx i3links, i2links, i1links = 0;
1743 int all_adjacent = (next_real_insn (i2) == i3
1744 && (i1 == 0 || next_real_insn (i1) == i2));
1746 /* Compute which registers we expect to eliminate. */
1747 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1749 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1751 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1753 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1754 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1756 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1758 /* Ensure that we do not have something that should not be shared but
1759 occurs multiple times in the new insns. Check this by first
1760 resetting all the `used' flags and then copying anything is shared. */
1762 reset_used_flags (i3notes);
1763 reset_used_flags (i2notes);
1764 reset_used_flags (i1notes);
1765 reset_used_flags (newpat);
1766 reset_used_flags (newi2pat);
1767 if (undobuf.other_insn)
1768 reset_used_flags (PATTERN (undobuf.other_insn));
1770 i3notes = copy_rtx_if_shared (i3notes);
1771 i2notes = copy_rtx_if_shared (i2notes);
1772 i1notes = copy_rtx_if_shared (i1notes);
1773 newpat = copy_rtx_if_shared (newpat);
1774 newi2pat = copy_rtx_if_shared (newi2pat);
1775 if (undobuf.other_insn)
1776 reset_used_flags (PATTERN (undobuf.other_insn));
1778 INSN_CODE (i3) = insn_code_number;
1779 PATTERN (i3) = newpat;
1780 if (undobuf.other_insn)
1781 INSN_CODE (undobuf.other_insn) = other_code_number;
1783 /* We had one special case above where I2 had more than one set and
1784 we replaced a destination of one of those sets with the destination
1785 of I3. In that case, we have to update LOG_LINKS of insns later
1786 in this basic block. Note that this (expensive) case is rare. */
1788 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1789 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1790 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1791 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1792 && ! find_reg_note (i2, REG_UNUSED,
1793 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1797 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1799 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1800 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1801 if (XEXP (link, 0) == i2)
1802 XEXP (link, 0) = i3;
1804 if (GET_CODE (insn) == CODE_LABEL
1805 || GET_CODE (insn) == JUMP_INSN)
1817 INSN_CODE (i2) = i2_code_number;
1818 PATTERN (i2) = newi2pat;
1822 PUT_CODE (i2, NOTE);
1823 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1824 NOTE_SOURCE_FILE (i2) = 0;
1831 PUT_CODE (i1, NOTE);
1832 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1833 NOTE_SOURCE_FILE (i1) = 0;
1836 /* Get death notes for everything that is now used in either I3 or
1837 I2 and used to die in a previous insn. */
1839 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1841 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1843 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1845 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1847 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1849 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1851 distribute_notes (midnotes, 0, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1853 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1854 know these are REG_UNUSED and want them to go to the desired insn,
1855 so we always pass it as i3. */
1856 if (newi2pat && new_i2_notes)
1857 distribute_notes (new_i2_notes, i2, i2, 0, 0, 0);
1859 distribute_notes (new_i3_notes, i3, i3, 0, 0, 0);
1861 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1862 put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1864 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 0),
1865 0, i3, newi2pat ? i2 : 0, 0, 0);
1866 if (i2dest_in_i2src)
1867 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, 0),
1868 0, i3, newi2pat ? i2 : 0, 0, 0);
1869 if (i1dest_in_i1src)
1870 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, 0),
1871 0, i3, newi2pat ? i2 : 0, 0, 0);
1873 distribute_links (i3links);
1874 distribute_links (i2links);
1875 distribute_links (i1links);
1877 if (GET_CODE (i2dest) == REG)
1879 /* The insn that previously set this register doesn't exist, and
1880 this life of the register may not exist either. Show that
1881 we don't know its value any more. If we don't do this and
1882 I2 set the register to a value that depended on its old
1883 contents, we will get confused. If this insn is used, thing
1884 will be set correctly in combine_instructions. */
1885 record_value_for_reg (i2dest, 0, 0);
1887 /* If the reg formerly set in I2 died only once and that was in I3,
1888 zero its use count so it won't make `reload' do any work. */
1889 if (! added_sets_2 && newi2pat == 0)
1891 regno = REGNO (i2dest);
1892 reg_n_sets[regno]--;
1893 if (reg_n_sets[regno] == 0
1894 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1895 & (1 << (regno % HOST_BITS_PER_INT))))
1896 reg_n_refs[regno] = 0;
1900 if (i1 && GET_CODE (i1dest) == REG)
1902 record_value_for_reg (i1dest, 0, 0);
1903 regno = REGNO (i1dest);
1906 reg_n_sets[regno]--;
1907 if (reg_n_sets[regno] == 0
1908 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1909 & (1 << (regno % HOST_BITS_PER_INT))))
1910 reg_n_refs[regno] = 0;
1914 /* If I3 is now an unconditional jump, ensure that it has a
1915 BARRIER following it since it may have initially been a
1916 conditional jump. */
1918 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
1919 && GET_CODE (next_nonnote_insn (i3)) != BARRIER)
1920 emit_barrier_after (i3);
1923 combine_successes++;
1925 return newi2pat ? i2 : i3;
1928 /* Undo all the modifications recorded in undobuf. */
1934 if (undobuf.num_undo > MAX_UNDO)
1935 undobuf.num_undo = MAX_UNDO;
1936 for (i = undobuf.num_undo - 1; i >= 0; i--)
1937 *undobuf.undo[i].where = undobuf.undo[i].old_contents;
1939 obfree (undobuf.storage);
1940 undobuf.num_undo = 0;
1943 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1944 where we have an arithmetic expression and return that point.
1946 try_combine will call this function to see if an insn can be split into
1950 find_split_point (loc)
1954 enum rtx_code code = GET_CODE (x);
1956 int len = 0, pos, unsignedp;
1959 /* First special-case some codes. */
1963 #ifdef INSN_SCHEDULING
1964 /* If we are making a paradoxical SUBREG invalid, it becomes a split
1966 if (GET_CODE (SUBREG_REG (x)) == MEM)
1969 return find_split_point (&SUBREG_REG (x));
1973 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1974 using LO_SUM and HIGH. */
1975 if (GET_CODE (XEXP (x, 0)) == CONST
1976 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1979 gen_rtx_combine (LO_SUM, Pmode,
1980 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
1982 return &XEXP (XEXP (x, 0), 0);
1986 /* If we have a PLUS whose second operand is a constant and the
1987 address is not valid, perhaps will can split it up using
1988 the machine-specific way to split large constants. We use
1989 the first pseudo-reg (one of the virtual regs) as a placeholder;
1990 it will not remain in the result. */
1991 if (GET_CODE (XEXP (x, 0)) == PLUS
1992 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1993 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
1995 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
1996 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
1999 /* This should have produced two insns, each of which sets our
2000 placeholder. If the source of the second is a valid address,
2001 we can make put both sources together and make a split point
2004 if (seq && XVECLEN (seq, 0) == 2
2005 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2006 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2007 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2008 && ! reg_mentioned_p (reg,
2009 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2010 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2011 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2012 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2013 && memory_address_p (GET_MODE (x),
2014 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2016 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2017 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2019 /* Replace the placeholder in SRC2 with SRC1. If we can
2020 find where in SRC2 it was placed, that can become our
2021 split point and we can replace this address with SRC2.
2022 Just try two obvious places. */
2024 src2 = replace_rtx (src2, reg, src1);
2026 if (XEXP (src2, 0) == src1)
2027 split = &XEXP (src2, 0);
2028 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2029 && XEXP (XEXP (src2, 0), 0) == src1)
2030 split = &XEXP (XEXP (src2, 0), 0);
2034 SUBST (XEXP (x, 0), src2);
2043 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2044 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2045 we need to put the operand into a register. So split at that
2048 if (SET_DEST (x) == cc0_rtx
2049 && GET_CODE (SET_SRC (x)) != COMPARE
2050 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2051 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2052 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2053 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2054 return &SET_SRC (x);
2057 /* See if we can split SET_SRC as it stands. */
2058 split = find_split_point (&SET_SRC (x));
2059 if (split && split != &SET_SRC (x))
2062 /* See if this is a bitfield assignment with everything constant. If
2063 so, this is an IOR of an AND, so split it into that. */
2064 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2065 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2066 <= HOST_BITS_PER_INT)
2067 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2068 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2069 && GET_CODE (SET_SRC (x)) == CONST_INT
2070 && ((INTVAL (XEXP (SET_DEST (x), 1))
2071 + INTVAL (XEXP (SET_DEST (x), 2)))
2072 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2073 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2075 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2076 int len = INTVAL (XEXP (SET_DEST (x), 1));
2077 int src = INTVAL (SET_SRC (x));
2078 rtx dest = XEXP (SET_DEST (x), 0);
2079 enum machine_mode mode = GET_MODE (dest);
2080 unsigned int mask = (1 << len) - 1;
2083 pos = GET_MODE_BITSIZE (mode) - len - pos;
2088 gen_binary (IOR, mode, dest,
2089 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2092 gen_binary (IOR, mode,
2093 gen_binary (AND, mode, dest,
2094 gen_rtx (CONST_INT, VOIDmode,
2096 & GET_MODE_MASK (mode)))),
2097 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2099 SUBST (SET_DEST (x), dest);
2101 split = find_split_point (&SET_SRC (x));
2102 if (split && split != &SET_SRC (x))
2106 /* Otherwise, see if this is an operation that we can split into two.
2107 If so, try to split that. */
2108 code = GET_CODE (SET_SRC (x));
2113 inner = XEXP (SET_SRC (x), 0);
2115 len = GET_MODE_BITSIZE (GET_MODE (inner));
2121 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2122 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2124 inner = XEXP (SET_SRC (x), 0);
2125 len = INTVAL (XEXP (SET_SRC (x), 1));
2126 pos = INTVAL (XEXP (SET_SRC (x), 2));
2129 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2131 unsignedp = (code == ZERO_EXTRACT);
2136 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2138 enum machine_mode mode = GET_MODE (SET_SRC (x));
2140 if (unsignedp && len < HOST_BITS_PER_INT)
2145 gen_rtx_combine (LSHIFTRT, mode,
2146 gen_lowpart_for_combine (mode, inner),
2147 gen_rtx (CONST_INT, VOIDmode, pos)),
2148 gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1)));
2150 split = find_split_point (&SET_SRC (x));
2151 if (split && split != &SET_SRC (x))
2159 gen_rtx_combine (ASHIFT, mode,
2160 gen_lowpart_for_combine (mode, inner),
2161 gen_rtx (CONST_INT, VOIDmode,
2162 (GET_MODE_BITSIZE (mode)
2164 gen_rtx (CONST_INT, VOIDmode,
2165 GET_MODE_BITSIZE (mode) - len)));
2167 split = find_split_point (&SET_SRC (x));
2168 if (split && split != &SET_SRC (x))
2173 /* See if this is a simple operation with a constant as the second
2174 operand. It might be that this constant is out of range and hence
2175 could be used as a split point. */
2176 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2179 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2180 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2181 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2182 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2184 return &XEXP (SET_SRC (x), 1);
2186 /* Finally, see if this is a simple operation with its first operand
2187 not in a register. The operation might require this operand in a
2188 register, so return it as a split point. We can always do this
2189 because if the first operand were another operation, we would have
2190 already found it as a split point. */
2191 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2192 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2193 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2194 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2195 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2196 return &XEXP (SET_SRC (x), 0);
2202 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2203 it is better to write this as (not (ior A B)) so we can split it.
2204 Similarly for IOR. */
2205 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2208 gen_rtx_combine (NOT, GET_MODE (x),
2209 gen_rtx_combine (code == IOR ? AND : IOR,
2211 XEXP (XEXP (x, 0), 0),
2212 XEXP (XEXP (x, 1), 0))));
2213 return find_split_point (loc);
2216 /* Many RISC machines have a large set of logical insns. If the
2217 second operand is a NOT, put it first so we will try to split the
2218 other operand first. */
2219 if (GET_CODE (XEXP (x, 1)) == NOT)
2221 rtx tem = XEXP (x, 0);
2222 SUBST (XEXP (x, 0), XEXP (x, 1));
2223 SUBST (XEXP (x, 1), tem);
2228 /* Otherwise, select our actions depending on our rtx class. */
2229 switch (GET_RTX_CLASS (code))
2231 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2233 split = find_split_point (&XEXP (x, 2));
2236 /* ... fall through ... */
2240 split = find_split_point (&XEXP (x, 1));
2243 /* ... fall through ... */
2245 /* Some machines have (and (shift ...) ...) insns. If X is not
2246 an AND, but XEXP (X, 0) is, use it as our split point. */
2247 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2248 return &XEXP (x, 0);
2250 split = find_split_point (&XEXP (x, 0));
2256 /* Otherwise, we don't have a split point. */
2260 /* Throughout X, replace FROM with TO, and return the result.
2261 The result is TO if X is FROM;
2262 otherwise the result is X, but its contents may have been modified.
2263 If they were modified, a record was made in undobuf so that
2264 undo_all will (among other things) return X to its original state.
2266 If the number of changes necessary is too much to record to undo,
2267 the excess changes are not made, so the result is invalid.
2268 The changes already made can still be undone.
2269 undobuf.num_undo is incremented for such changes, so by testing that
2270 the caller can tell whether the result is valid.
2272 `n_occurrences' is incremented each time FROM is replaced.
2274 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2276 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2277 by copying if `n_occurrences' is non-zero. */
2280 subst (x, from, to, in_dest, unique_copy)
2281 register rtx x, from, to;
2286 register int len, i;
2287 register enum rtx_code code = GET_CODE (x), orig_code = code;
2289 enum machine_mode mode = GET_MODE (x);
2290 enum machine_mode op0_mode = VOIDmode;
2295 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2296 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2297 If it is 0, that cannot be done. We can now do this for any MEM
2298 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2299 If not for that, MEM's would very rarely be safe. */
2301 /* Reject MODEs bigger than a word, because we might not be able
2302 to reference a two-register group starting with an arbitrary register
2303 (and currently gen_lowpart might crash for a SUBREG). */
2305 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2306 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2308 /* Two expressions are equal if they are identical copies of a shared
2309 RTX or if they are both registers with the same register number
2312 #define COMBINE_RTX_EQUAL_P(X,Y) \
2314 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2315 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2317 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2320 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2323 /* If X and FROM are the same register but different modes, they will
2324 not have been seen as equal above. However, flow.c will make a
2325 LOG_LINKS entry for that case. If we do nothing, we will try to
2326 rerecognize our original insn and, when it succeeds, we will
2327 delete the feeding insn, which is incorrect.
2329 So force this insn not to match in this (rare) case. */
2330 if (! in_dest && code == REG && GET_CODE (from) == REG
2331 && REGNO (x) == REGNO (from))
2332 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2334 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2335 of which may contain things that can be combined. */
2336 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2339 /* It is possible to have a subexpression appear twice in the insn.
2340 Suppose that FROM is a register that appears within TO.
2341 Then, after that subexpression has been scanned once by `subst',
2342 the second time it is scanned, TO may be found. If we were
2343 to scan TO here, we would find FROM within it and create a
2344 self-referent rtl structure which is completely wrong. */
2345 if (COMBINE_RTX_EQUAL_P (x, to))
2348 len = GET_RTX_LENGTH (code);
2349 fmt = GET_RTX_FORMAT (code);
2351 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2352 set up to skip this common case. All other cases where we want to
2353 suppress replacing something inside a SET_SRC are handled via the
2356 && (GET_CODE (SET_DEST (x)) == REG
2357 || GET_CODE (SET_DEST (x)) == CC0
2358 || GET_CODE (SET_DEST (x)) == PC))
2361 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2363 op0_mode = GET_MODE (XEXP (x, 0));
2365 for (i = 0; i < len; i++)
2370 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2373 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2375 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2380 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2382 /* If this substitution failed, this whole thing fails. */
2383 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2387 SUBST (XVECEXP (x, i, j), new);
2390 else if (fmt[i] == 'e')
2394 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2396 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2400 /* If we are in a SET_DEST, suppress most cases unless we
2401 have gone inside a MEM, in which case we want to
2402 simplify the address. We assume here that things that
2403 are actually part of the destination have their inner
2404 parts in the first expression. This is true for SUBREG,
2405 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2406 things aside from REG and MEM that should appear in a
2408 new = subst (XEXP (x, i), from, to,
2410 && (code == SUBREG || code == STRICT_LOW_PART
2411 || code == ZERO_EXTRACT))
2413 && i == 0), unique_copy);
2415 /* If we found that we will have to reject this combination,
2416 indicate that by returning the CLOBBER ourselves, rather than
2417 an expression containing it. This will speed things up as
2418 well as prevent accidents where two CLOBBERs are considered
2419 to be equal, thus producing an incorrect simplification. */
2421 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2424 SUBST (XEXP (x, i), new);
2428 /* If this is a commutative operation, put a constant last and a complex
2429 expression first. We don't need to do this for comparisons here. */
2430 if (GET_RTX_CLASS (code) == 'c'
2431 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2432 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2433 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2434 || (GET_CODE (XEXP (x, 0)) == SUBREG
2435 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2436 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2439 SUBST (XEXP (x, 0), XEXP (x, 1));
2440 SUBST (XEXP (x, 1), temp);
2443 /* Try to fold this expression in case we have constants that weren't
2446 switch (GET_RTX_CLASS (code))
2449 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2452 temp = simplify_relational_operation (code, op0_mode,
2453 XEXP (x, 0), XEXP (x, 1));
2454 #ifdef FLOAT_STORE_FLAG_VALUE
2455 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2456 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2457 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2462 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2466 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2467 XEXP (x, 1), XEXP (x, 2));
2474 /* We come back to here if we have replaced the expression with one of
2475 a different code and it is likely that further simplification will be
2480 /* If we have restarted more than 4 times, we are probably looping, so
2482 if (++n_restarts > 4)
2485 code = GET_CODE (x);
2487 /* First see if we can apply the inverse distributive law. */
2488 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2490 x = apply_distributive_law (x);
2491 code = GET_CODE (x);
2494 /* If CODE is an associative operation not otherwise handled, see if we
2495 can associate some operands. This can win if they are constants or
2496 if they are logically related (i.e. (a & b) & a. */
2497 if ((code == PLUS || code == MINUS
2498 || code == MULT || code == AND || code == IOR || code == XOR
2499 || code == DIV || code == UDIV
2500 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2501 && GET_MODE_CLASS (mode) == MODE_INT)
2503 if (GET_CODE (XEXP (x, 0)) == code)
2505 rtx other = XEXP (XEXP (x, 0), 0);
2506 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2507 rtx inner_op1 = XEXP (x, 1);
2510 /* Make sure we pass the constant operand if any as the second
2511 one if this is a commutative operation. */
2512 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2514 rtx tem = inner_op0;
2515 inner_op0 = inner_op1;
2518 inner = simplify_binary_operation (code == MINUS ? PLUS
2519 : code == DIV ? MULT
2520 : code == UDIV ? MULT
2522 mode, inner_op0, inner_op1);
2524 /* For commutative operations, try the other pair if that one
2526 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2528 other = XEXP (XEXP (x, 0), 1);
2529 inner = simplify_binary_operation (code, mode,
2530 XEXP (XEXP (x, 0), 0),
2536 x = gen_binary (code, mode, other, inner);
2543 /* A little bit of algebraic simplification here. */
2547 /* Ensure that our address has any ASHIFTs converted to MULT in case
2548 address-recognizing predicates are called later. */
2549 temp = make_compound_operation (XEXP (x, 0), MEM);
2550 SUBST (XEXP (x, 0), temp);
2554 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2555 is paradoxical. If we can't do that safely, then it becomes
2556 something nonsensical so that this combination won't take place. */
2558 if (GET_CODE (SUBREG_REG (x)) == MEM
2559 && (GET_MODE_SIZE (mode)
2560 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2562 rtx inner = SUBREG_REG (x);
2563 int endian_offset = 0;
2564 /* Don't change the mode of the MEM
2565 if that would change the meaning of the address. */
2566 if (MEM_VOLATILE_P (SUBREG_REG (x))
2567 || mode_dependent_address_p (XEXP (inner, 0)))
2568 return gen_rtx (CLOBBER, mode, const0_rtx);
2570 #if BYTES_BIG_ENDIAN
2571 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2572 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2573 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2574 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2576 /* Note if the plus_constant doesn't make a valid address
2577 then this combination won't be accepted. */
2578 x = gen_rtx (MEM, mode,
2579 plus_constant (XEXP (inner, 0),
2580 (SUBREG_WORD (x) * UNITS_PER_WORD
2582 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2583 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2584 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2588 /* If we are in a SET_DEST, these other cases can't apply. */
2592 /* Changing mode twice with SUBREG => just change it once,
2593 or not at all if changing back to starting mode. */
2594 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2596 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2597 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2598 return SUBREG_REG (SUBREG_REG (x));
2600 SUBST_INT (SUBREG_WORD (x),
2601 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2602 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2605 /* SUBREG of a hard register => just change the register number
2606 and/or mode. If the hard register is not valid in that mode,
2607 suppress this combination. */
2609 if (GET_CODE (SUBREG_REG (x)) == REG
2610 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
2612 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2614 return gen_rtx (REG, mode,
2615 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2617 return gen_rtx (CLOBBER, mode, const0_rtx);
2620 /* For a constant, try to pick up the part we want. Handle a full
2621 word and low-order part. Only do this if we are narrowing
2622 the constant; if it is being widened, we have no idea what
2623 the extra bits will have been set to. */
2625 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2626 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2627 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2628 && GET_MODE_CLASS (mode) == MODE_INT)
2630 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2636 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2637 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2638 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2640 /* If we are narrowing the object, we need to see if we can simplify
2641 the expression for the object knowing that we only need the
2642 low-order bits. We do this by computing an AND of the object
2643 with only the bits we care about. That will produce any needed
2644 simplifications. If the resulting computation is just the
2645 AND with the significant bits, our operand is the first operand
2646 of the AND. Otherwise, it is the resulting expression. */
2647 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2648 && subreg_lowpart_p (x)
2649 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
2651 temp = simplify_and_const_int (0, GET_MODE (SUBREG_REG (x)),
2652 SUBREG_REG (x), GET_MODE_MASK (mode));
2653 if (GET_CODE (temp) == AND && GET_CODE (XEXP (temp, 1)) == CONST_INT
2654 && INTVAL (XEXP (temp, 1)) == GET_MODE_MASK (mode))
2655 temp = XEXP (temp, 0);
2656 return gen_lowpart_for_combine (mode, temp);
2662 /* (not (plus X -1)) can become (neg X). */
2663 if (GET_CODE (XEXP (x, 0)) == PLUS
2664 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2666 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2670 /* Similarly, (not (neg X)) is (plus X -1). */
2671 if (GET_CODE (XEXP (x, 0)) == NEG)
2673 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2677 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2678 other than 1, but that is not valid. We could do a similar
2679 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2680 but this doesn't seem common enough to bother with. */
2681 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2682 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2684 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
2685 XEXP (XEXP (x, 0), 1));
2689 if (GET_CODE (XEXP (x, 0)) == SUBREG
2690 && subreg_lowpart_p (XEXP (x, 0))
2691 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
2692 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
2693 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
2694 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
2696 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
2698 x = gen_rtx (ROTATE, inner_mode,
2699 gen_unary (NOT, inner_mode, const1_rtx),
2700 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
2701 x = gen_lowpart_for_combine (mode, x);
2705 #if STORE_FLAG_VALUE == -1
2706 /* (not (comparison foo bar)) can be done by reversing the comparison
2708 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
2709 && reversible_comparison_p (XEXP (x, 0)))
2710 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
2711 mode, XEXP (XEXP (x, 0), 0),
2712 XEXP (XEXP (x, 0), 1));
2715 /* Apply De Morgan's laws to reduce number of patterns for machines
2716 with negating logical insns (and-not, nand, etc.). If result has
2717 only one NOT, put it first, since that is how the patterns are
2720 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
2722 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
2724 if (GET_CODE (in1) == NOT)
2725 in1 = XEXP (in1, 0);
2727 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
2729 if (GET_CODE (in2) == NOT)
2730 in2 = XEXP (in2, 0);
2731 else if (GET_CODE (in2) == CONST_INT
2732 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
2733 in2 = gen_rtx (CONST_INT, VOIDmode,
2734 GET_MODE_MASK (mode) & ~ INTVAL (in2));
2736 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
2738 if (GET_CODE (in2) == NOT)
2741 in2 = in1; in1 = tem;
2744 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
2751 /* (neg (plus X 1)) can become (not X). */
2752 if (GET_CODE (XEXP (x, 0)) == PLUS
2753 && XEXP (XEXP (x, 0), 1) == const1_rtx)
2755 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
2759 /* Similarly, (neg (not X)) is (plus X 1). */
2760 if (GET_CODE (XEXP (x, 0)) == NOT)
2762 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
2766 /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2767 if (GET_CODE (XEXP (x, 0)) == ABS
2768 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTRACT
2769 && XEXP (XEXP (XEXP (x, 0), 0), 1) == const1_rtx)
2770 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFTRT
2771 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2772 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2773 == GET_MODE_BITSIZE (mode) - 1))
2774 || ((temp = get_last_value (XEXP (XEXP (x, 0), 0))) != 0
2775 && ((GET_CODE (temp) == SIGN_EXTRACT
2776 && XEXP (temp, 1) == const1_rtx)
2777 || (GET_CODE (temp) == ASHIFTRT
2778 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2779 && (INTVAL (XEXP (temp, 1))
2780 == GET_MODE_BITSIZE (mode) - 1))))))
2781 return XEXP (XEXP (x, 0), 0);
2783 /* (neg (minus X Y)) can become (minus Y X). */
2784 if (GET_CODE (XEXP (x, 0)) == MINUS
2785 && (GET_MODE_CLASS (mode) != MODE_FLOAT
2786 /* x-y != -(y-x) with IEEE floating point. */
2787 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
2789 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
2790 XEXP (XEXP (x, 0), 0));
2794 /* NEG commutes with ASHIFT since it is multiplication. Only do this
2795 if we can then eliminate the NEG (e.g.,
2796 if the operand is a constant). */
2798 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
2800 temp = simplify_unary_operation (NEG, mode,
2801 XEXP (XEXP (x, 0), 0), mode);
2804 SUBST (XEXP (XEXP (x, 0), 0), temp);
2809 temp = expand_compound_operation (XEXP (x, 0));
2811 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2812 replaced by (lshiftrt X C). This will convert
2813 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2815 if (GET_CODE (temp) == ASHIFTRT
2816 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2817 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
2819 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
2820 INTVAL (XEXP (temp, 1)));
2824 /* If X has only a single bit significant, say, bit I, convert
2825 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2826 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2827 (sign_extract X 1 Y). But only do this if TEMP isn't a register
2828 or a SUBREG of one since we'd be making the expression more
2829 complex if it was just a register. */
2831 if (GET_CODE (temp) != REG
2832 && ! (GET_CODE (temp) == SUBREG
2833 && GET_CODE (SUBREG_REG (temp)) == REG)
2834 && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
2836 rtx temp1 = simplify_shift_const
2838 simplify_shift_const (0, ASHIFT, mode, temp,
2839 GET_MODE_BITSIZE (mode) - 1 - i),
2840 GET_MODE_BITSIZE (mode) - 1 - i);
2842 /* If all we did was surround TEMP with the two shifts, we
2843 haven't improved anything, so don't use it. Otherwise,
2844 we are better off with TEMP1. */
2845 if (GET_CODE (temp1) != ASHIFTRT
2846 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
2847 || XEXP (XEXP (temp1, 0), 0) != temp)
2855 case FLOAT_TRUNCATE:
2856 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2857 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
2858 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
2859 return XEXP (XEXP (x, 0), 0);
2864 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2865 using cc0, in which case we want to leave it as a COMPARE
2866 so we can distinguish it from a register-register-copy. */
2867 if (XEXP (x, 1) == const0_rtx)
2870 /* In IEEE floating point, x-0 is not the same as x. */
2871 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
2872 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
2873 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
2879 /* (const (const X)) can become (const X). Do it this way rather than
2880 returning the inner CONST since CONST can be shared with a
2882 if (GET_CODE (XEXP (x, 0)) == CONST)
2883 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
2888 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2889 can add in an offset. find_split_point will split this address up
2890 again if it doesn't match. */
2891 if (GET_CODE (XEXP (x, 0)) == HIGH
2892 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
2898 /* If we have (plus (plus (A const) B)), associate it so that CONST is
2899 outermost. That's because that's the way indexed addresses are
2900 supposed to appear. This code used to check many more cases, but
2901 they are now checked elsewhere. */
2902 if (GET_CODE (XEXP (x, 0)) == PLUS
2903 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
2904 return gen_binary (PLUS, mode,
2905 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
2907 XEXP (XEXP (x, 0), 1));
2909 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2910 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2911 bit-field and can be replaced by either a sign_extend or a
2912 sign_extract. The `and' may be a zero_extend. */
2913 if (GET_CODE (XEXP (x, 0)) == XOR
2914 && GET_CODE (XEXP (x, 1)) == CONST_INT
2915 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2916 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
2917 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
2918 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2919 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
2920 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2921 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2922 == (1 << (i + 1)) - 1))
2923 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
2924 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
2927 x = simplify_shift_const
2929 simplify_shift_const (0, ASHIFT, mode,
2930 XEXP (XEXP (XEXP (x, 0), 0), 0),
2931 GET_MODE_BITSIZE (mode) - (i + 1)),
2932 GET_MODE_BITSIZE (mode) - (i + 1));
2936 /* If only the low-order bit of X is significant, (plus x -1)
2937 can become (ashiftrt (ashift (xor x 1) C) C) where C is
2938 the bitsize of the mode - 1. This allows simplification of
2939 "a = (b & 8) == 0;" */
2940 if (XEXP (x, 1) == constm1_rtx
2941 && GET_CODE (XEXP (x, 0)) != REG
2942 && ! (GET_CODE (XEXP (x,0)) == SUBREG
2943 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
2944 && significant_bits (XEXP (x, 0), mode) == 1)
2946 x = simplify_shift_const
2948 simplify_shift_const (0, ASHIFT, mode,
2949 gen_rtx_combine (XOR, mode,
2950 XEXP (x, 0), const1_rtx),
2951 GET_MODE_BITSIZE (mode) - 1),
2952 GET_MODE_BITSIZE (mode) - 1);
2958 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2959 (and <foo> (const_int pow2-1)) */
2960 if (GET_CODE (XEXP (x, 1)) == AND
2961 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2962 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
2963 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2965 x = simplify_and_const_int (0, mode, XEXP (x, 0),
2966 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
2970 /* If we are adding two things that have no bits in common, convert
2971 the addition into an IOR. This will often be further simplified,
2972 for example in cases like ((a & 1) + (a & 2)), which can
2975 if ((significant_bits (XEXP (x, 0), mode)
2976 & significant_bits (XEXP (x, 1), mode)) == 0)
2978 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
2984 /* If we have (mult (plus A B) C), apply the distributive law and then
2985 the inverse distributive law to see if things simplify. This
2986 occurs mostly in addresses, often when unrolling loops. */
2988 if (GET_CODE (XEXP (x, 0)) == PLUS)
2990 x = apply_distributive_law
2991 (gen_binary (PLUS, mode,
2992 gen_binary (MULT, mode,
2993 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
2994 gen_binary (MULT, mode,
2995 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
2997 if (GET_CODE (x) != MULT)
3001 /* If this is multiplication by a power of two and its first operand is
3002 a shift, treat the multiply as a shift to allow the shifts to
3003 possibly combine. */
3004 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3005 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3006 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3007 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3008 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3009 || GET_CODE (XEXP (x, 0)) == ROTATE
3010 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3012 x = simplify_shift_const (0, ASHIFT, mode, XEXP (x, 0), i);
3016 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3017 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3018 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3019 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3020 XEXP (XEXP (x, 0), 1));
3024 /* If this is a divide by a power of two, treat it as a shift if
3025 its first operand is a shift. */
3026 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3027 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3028 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3029 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3030 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3031 || GET_CODE (XEXP (x, 0)) == ROTATE
3032 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3034 x = simplify_shift_const (0, LSHIFTRT, mode, XEXP (x, 0), i);
3040 case GT: case GTU: case GE: case GEU:
3041 case LT: case LTU: case LE: case LEU:
3042 /* If the first operand is a condition code, we can't do anything
3044 if (GET_CODE (XEXP (x, 0)) == COMPARE
3045 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3047 && XEXP (x, 0) != cc0_rtx
3051 rtx op0 = XEXP (x, 0);
3052 rtx op1 = XEXP (x, 1);
3053 enum rtx_code new_code;
3055 if (GET_CODE (op0) == COMPARE)
3056 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3058 /* Simplify our comparison, if possible. */
3059 new_code = simplify_comparison (code, &op0, &op1);
3061 #if STORE_FLAG_VALUE == 1
3062 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3063 if only the low-order bit is significant in X (such as when
3064 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3066 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3067 && op1 == const0_rtx
3068 && significant_bits (op0, GET_MODE (op0)) == 1)
3069 return gen_lowpart_for_combine (mode, op0);
3070 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3071 && op1 == const0_rtx
3072 && significant_bits (op0, GET_MODE (op0)) == 1)
3073 return gen_rtx_combine (XOR, mode,
3074 gen_lowpart_for_combine (mode, op0),
3078 #if STORE_FLAG_VALUE == -1
3079 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3080 to (neg x) if only the low-order bit of X is significant.
3081 This converts (ne (zero_extract X 1 Y) 0) to
3082 (sign_extract X 1 Y). */
3083 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3084 && op1 == const0_rtx
3085 && significant_bits (op0, GET_MODE (op0)) == 1)
3087 x = gen_rtx_combine (NEG, mode,
3088 gen_lowpart_for_combine (mode, op0));
3093 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3094 one significant bit, we can convert (ne x 0) to (ashift x c)
3095 where C puts the bit in the sign bit. Remove any AND with
3096 STORE_FLAG_VALUE when we are done, since we are only going to
3097 test the sign bit. */
3098 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3099 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3100 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3101 && op1 == const0_rtx
3102 && mode == GET_MODE (op0)
3103 && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3105 x = simplify_shift_const (0, ASHIFT, mode, op0,
3106 GET_MODE_BITSIZE (mode) - 1 - i);
3107 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3113 /* If the code changed, return a whole new comparison. */
3114 if (new_code != code)
3115 return gen_rtx_combine (new_code, mode, op0, op1);
3117 /* Otherwise, keep this operation, but maybe change its operands.
3118 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3119 SUBST (XEXP (x, 0), op0);
3120 SUBST (XEXP (x, 1), op1);
3125 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3126 reversed, do so to avoid needing two sets of patterns for
3127 subtract-and-branch insns. */
3128 if (XEXP (x, 1) == pc_rtx
3129 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3130 && reversible_comparison_p (XEXP (x, 0)))
3133 gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3134 GET_MODE (XEXP (x, 0)),
3135 XEXP (XEXP (x, 0), 0),
3136 XEXP (XEXP (x, 0), 1)));
3137 SUBST (XEXP (x, 1), XEXP (x, 2));
3138 SUBST (XEXP (x, 2), pc_rtx);
3146 /* If we are processing SET_DEST, we are done. */
3150 x = expand_compound_operation (x);
3151 if (GET_CODE (x) != code)
3156 /* (set (pc) (return)) gets written as (return). */
3157 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3160 /* Convert this into a field assignment operation, if possible. */
3161 x = make_field_assignment (x);
3163 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3164 operation, and X being a REG or (subreg (reg)), we may be able to
3165 convert this to (set (subreg:m2 x) (op)).
3167 We can always do this if M1 is narrower than M2 because that
3168 means that we only care about the low bits of the result.
3170 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3171 not defined), we cannot perform a narrower operation that
3172 requested since the high-order bits will be undefined. On
3173 machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3174 transformation is safe as long as M1 and M2 have the same number
3177 if (GET_CODE (SET_SRC (x)) == SUBREG
3178 && subreg_lowpart_p (SET_SRC (x))
3179 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3180 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3182 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3183 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3184 #ifndef BYTE_LOADS_ZERO_EXTEND
3185 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3186 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3188 && (GET_CODE (SET_DEST (x)) == REG
3189 || (GET_CODE (SET_DEST (x)) == SUBREG
3190 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3192 /* Get the object that will be the SUBREG_REG of the
3193 SUBREG we are making. Note that SUBREG_WORD will always
3194 be zero because this will either be a paradoxical SUBREG
3195 or a SUBREG with the same number of words on the outside and
3197 rtx object = (GET_CODE (SET_DEST (x)) == REG ? SET_DEST (x)
3198 : SUBREG_REG (SET_DEST (x)));
3200 SUBST (SET_DEST (x),
3201 gen_rtx (SUBREG, GET_MODE (SUBREG_REG (SET_SRC (x))),
3203 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3206 /* If we are setting CC0 or if the source is a COMPARE, look for the
3207 use of the comparison result and try to simplify it unless we already
3208 have used undobuf.other_insn. */
3209 if ((GET_CODE (SET_SRC (x)) == COMPARE
3211 || SET_DEST (x) == cc0_rtx
3214 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3216 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3217 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3218 && XEXP (*cc_use, 0) == SET_DEST (x))
3220 enum rtx_code old_code = GET_CODE (*cc_use);
3221 enum rtx_code new_code;
3223 int other_changed = 0;
3224 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3226 if (GET_CODE (SET_SRC (x)) == COMPARE)
3227 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3229 op0 = SET_SRC (x), op1 = const0_rtx;
3231 /* Simplify our comparison, if possible. */
3232 new_code = simplify_comparison (old_code, &op0, &op1);
3234 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3235 /* If this machine has CC modes other than CCmode, check to see
3236 if we need to use a different CC mode here. */
3237 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3239 /* If the mode changed, we have to change SET_DEST, the mode
3240 in the compare, and the mode in the place SET_DEST is used.
3241 If SET_DEST is a hard register, just build new versions with
3242 the proper mode. If it is a pseudo, we lose unless it is only
3243 time we set the pseudo, in which case we can safely change
3245 if (compare_mode != GET_MODE (SET_DEST (x)))
3247 int regno = REGNO (SET_DEST (x));
3248 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3250 if (regno < FIRST_PSEUDO_REGISTER
3251 || (reg_n_sets[regno] == 1
3252 && ! REG_USERVAR_P (SET_DEST (x))))
3254 if (regno >= FIRST_PSEUDO_REGISTER)
3255 SUBST (regno_reg_rtx[regno], new_dest);
3257 SUBST (SET_DEST (x), new_dest);
3258 SUBST (XEXP (*cc_use, 0), new_dest);
3264 /* If the code changed, we have to build a new comparison
3265 in undobuf.other_insn. */
3266 if (new_code != old_code)
3270 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3271 SET_DEST (x), const0_rtx));
3273 /* If the only change we made was to change an EQ into an
3274 NE or vice versa, OP0 has only one significant bit,
3275 and OP1 is zero, check if changing the user of the condition
3276 code will produce a valid insn. If it won't, we can keep
3277 the original code in that insn by surrounding our operation
3280 if (((old_code == NE && new_code == EQ)
3281 || (old_code == EQ && new_code == NE))
3282 && ! other_changed && op1 == const0_rtx
3283 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
3284 && (exact_log2 (mask = significant_bits (op0,
3288 rtx pat = PATTERN (other_insn), note = 0;
3290 if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3291 && ! check_asm_operands (pat)))
3293 PUT_CODE (*cc_use, old_code);
3296 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3297 gen_rtx (CONST_INT, VOIDmode, mask));
3305 undobuf.other_insn = other_insn;
3308 /* If we are now comparing against zero, change our source if
3309 needed. If we do not use cc0, we always have a COMPARE. */
3310 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3311 SUBST (SET_SRC (x), op0);
3315 /* Otherwise, if we didn't previously have a COMPARE in the
3316 correct mode, we need one. */
3317 if (GET_CODE (SET_SRC (x)) != COMPARE
3318 || GET_MODE (SET_SRC (x)) != compare_mode)
3319 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3323 /* Otherwise, update the COMPARE if needed. */
3324 SUBST (XEXP (SET_SRC (x), 0), op0);
3325 SUBST (XEXP (SET_SRC (x), 1), op1);
3330 /* Get SET_SRC in a form where we have placed back any
3331 compound expressions. Then do the checks below. */
3332 temp = make_compound_operation (SET_SRC (x), SET);
3333 SUBST (SET_SRC (x), temp);
3336 #ifdef BYTE_LOADS_ZERO_EXTEND
3337 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3338 M wider than N, this would require a paradoxical subreg.
3339 Replace the subreg with a zero_extend to avoid the reload that
3340 would otherwise be required. */
3341 if (GET_CODE (SET_SRC (x)) == SUBREG
3342 && subreg_lowpart_p (SET_SRC (x))
3343 && SUBREG_WORD (SET_SRC (x)) == 0
3344 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3345 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3346 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3347 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3348 GET_MODE (SET_SRC (x)),
3349 XEXP (SET_SRC (x), 0)));
3355 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3357 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3358 INTVAL (XEXP (x, 1)));
3360 /* If we have (ior (and (X C1) C2)) and the next restart would be
3361 the last, simplify this by making C1 as small as possible
3363 if (n_restarts >= 3 && GET_CODE (x) == IOR
3364 && GET_CODE (XEXP (x, 0)) == AND
3365 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3366 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3368 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3369 gen_rtx (CONST_INT, VOIDmode,
3370 (INTVAL (XEXP (XEXP (x, 0), 1))
3371 & ~ INTVAL (XEXP (x, 1)))));
3372 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3375 if (GET_CODE (x) != AND)
3379 /* Convert (A | B) & A to A. */
3380 if (GET_CODE (XEXP (x, 0)) == IOR
3381 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3382 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3383 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3384 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3387 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3388 insn (and may simplify more). */
3389 else if (GET_CODE (XEXP (x, 0)) == XOR
3390 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3391 && ! side_effects_p (XEXP (x, 1)))
3393 x = gen_binary (AND, mode,
3394 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3398 else if (GET_CODE (XEXP (x, 0)) == XOR
3399 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3400 && ! side_effects_p (XEXP (x, 1)))
3402 x = gen_binary (AND, mode,
3403 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3408 /* Similarly for (~ (A ^ B)) & A. */
3409 else if (GET_CODE (XEXP (x, 0)) == NOT
3410 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3411 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3412 && ! side_effects_p (XEXP (x, 1)))
3414 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3418 else if (GET_CODE (XEXP (x, 0)) == NOT
3419 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3420 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3421 && ! side_effects_p (XEXP (x, 1)))
3423 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3428 /* In the follow group of tests (and those in case IOR below),
3429 we start with some combination of logical operations and apply
3430 the distributive law followed by the inverse distributive law.
3431 Most of the time, this results in no change. However, if some of
3432 the operands are the same or inverses of each other, simplifications
3435 For example, (and (ior A B) (not B)) can occur as the result of
3436 expanding a bit field assignment. When we apply the distributive
3437 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3438 which then simplifies to (and (A (not B))). */
3440 /* If we have (and (ior A B) C), apply the distributive law and then
3441 the inverse distributive law to see if things simplify. */
3443 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
3445 x = apply_distributive_law
3446 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
3447 gen_binary (AND, mode,
3448 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3449 gen_binary (AND, mode,
3450 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3451 if (GET_CODE (x) != AND)
3455 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
3457 x = apply_distributive_law
3458 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
3459 gen_binary (AND, mode,
3460 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3461 gen_binary (AND, mode,
3462 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3463 if (GET_CODE (x) != AND)
3467 /* Similarly, taking advantage of the fact that
3468 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3470 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
3472 x = apply_distributive_law
3473 (gen_binary (XOR, mode,
3474 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3475 XEXP (XEXP (x, 1), 0)),
3476 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3477 XEXP (XEXP (x, 1), 1))));
3478 if (GET_CODE (x) != AND)
3482 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
3484 x = apply_distributive_law
3485 (gen_binary (XOR, mode,
3486 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3487 XEXP (XEXP (x, 0), 0)),
3488 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3489 XEXP (XEXP (x, 0), 1))));
3490 if (GET_CODE (x) != AND)
3496 /* Convert (A & B) | A to A. */
3497 if (GET_CODE (XEXP (x, 0)) == AND
3498 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3499 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3500 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3501 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3504 /* If we have (ior (and A B) C), apply the distributive law and then
3505 the inverse distributive law to see if things simplify. */
3507 if (GET_CODE (XEXP (x, 0)) == AND)
3509 x = apply_distributive_law
3510 (gen_binary (AND, mode,
3511 gen_binary (IOR, mode,
3512 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3513 gen_binary (IOR, mode,
3514 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3516 if (GET_CODE (x) != IOR)
3520 if (GET_CODE (XEXP (x, 1)) == AND)
3522 x = apply_distributive_law
3523 (gen_binary (AND, mode,
3524 gen_binary (IOR, mode,
3525 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3526 gen_binary (IOR, mode,
3527 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3529 if (GET_CODE (x) != IOR)
3533 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3534 mode size to (rotate A CX). */
3536 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
3537 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
3538 || (GET_CODE (XEXP (x, 1)) == ASHIFT
3539 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
3540 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
3541 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3542 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3543 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
3544 == GET_MODE_BITSIZE (mode)))
3548 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3549 shift_count = XEXP (XEXP (x, 0), 1);
3551 shift_count = XEXP (XEXP (x, 1), 1);
3552 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
3558 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3559 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3562 int num_negated = 0;
3563 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
3565 if (GET_CODE (in1) == NOT)
3566 num_negated++, in1 = XEXP (in1, 0);
3567 if (GET_CODE (in2) == NOT)
3568 num_negated++, in2 = XEXP (in2, 0);
3570 if (num_negated == 2)
3572 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3573 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3575 else if (num_negated == 1)
3576 return gen_rtx_combine (NOT, mode,
3577 gen_rtx_combine (XOR, mode, in1, in2));
3580 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3581 correspond to a machine insn or result in further simplifications
3582 if B is a constant. */
3584 if (GET_CODE (XEXP (x, 0)) == AND
3585 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3586 && ! side_effects_p (XEXP (x, 1)))
3588 x = gen_binary (AND, mode,
3589 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3593 else if (GET_CODE (XEXP (x, 0)) == AND
3594 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3595 && ! side_effects_p (XEXP (x, 1)))
3597 x = gen_binary (AND, mode,
3598 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3604 #if STORE_FLAG_VALUE == 1
3605 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3607 if (XEXP (x, 1) == const1_rtx
3608 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3609 && reversible_comparison_p (XEXP (x, 0)))
3610 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3611 mode, XEXP (XEXP (x, 0), 0),
3612 XEXP (XEXP (x, 0), 1));
3615 /* (xor (comparison foo bar) (const_int sign-bit))
3616 when STORE_FLAG_VALUE is the sign bit. */
3617 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3618 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3619 && XEXP (x, 1) == const_true_rtx
3620 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3621 && reversible_comparison_p (XEXP (x, 0)))
3622 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3623 mode, XEXP (XEXP (x, 0), 0),
3624 XEXP (XEXP (x, 0), 1));
3628 /* (abs (neg <foo>)) -> (abs <foo>) */
3629 if (GET_CODE (XEXP (x, 0)) == NEG)
3630 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3632 /* If operand is something known to be positive, ignore the ABS. */
3633 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3634 || (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_INT
3635 && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3636 & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3641 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3642 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT
3643 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3644 || (GET_CODE (XEXP (x, 0)) == ASHIFTRT
3645 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3646 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3647 || ((temp = get_last_value (XEXP (x, 0))) != 0
3648 && ((GET_CODE (temp) == SIGN_EXTRACT
3649 && XEXP (temp, 1) == const1_rtx)
3650 || (GET_CODE (temp) == ASHIFTRT
3651 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3652 && (INTVAL (XEXP (temp, 1))
3653 == GET_MODE_BITSIZE (mode) - 1)))))
3655 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
3661 /* (ffs (*_extend <X>)) = (ffs <X>) */
3662 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3663 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3664 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3668 /* (float (sign_extend <X>)) = (float <X>). */
3669 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3670 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3679 /* If this is a shift by a constant amount, simplify it. */
3680 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3682 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
3683 INTVAL (XEXP (x, 1)));
3684 if (GET_CODE (x) != code)
3688 #ifdef SHIFT_COUNT_TRUNCATED
3689 else if (GET_CODE (XEXP (x, 1)) != REG)
3691 force_to_mode (XEXP (x, 1), GET_MODE (x),
3692 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
3702 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3703 operations" because they can be replaced with two more basic operations.
3704 ZERO_EXTEND is also considered "compound" because it can be replaced with
3705 an AND operation, which is simpler, though only one operation.
3707 The function expand_compound_operation is called with an rtx expression
3708 and will convert it to the appropriate shifts and AND operations,
3709 simplifying at each stage.
3711 The function make_compound_operation is called to convert an expression
3712 consisting of shifts and ANDs into the equivalent compound expression.
3713 It is the inverse of this function, loosely speaking. */
3716 expand_compound_operation (x)
3724 switch (GET_CODE (x))
3729 /* We can't necessarily use a const_int for a multiword mode;
3730 it depends on implicitly extending the value.
3731 Since we don't know the right way to extend it,
3732 we can't tell whether the implicit way is right.
3734 Even for a mode that is no wider than a const_int,
3735 we can't win, because we need to sign extend one of its bits through
3736 the rest of it, and we don't know which bit. */
3737 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3740 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
3743 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
3744 /* If the inner object has VOIDmode (the only way this can happen
3745 is if it is a ASM_OPERANDS), we can't do anything since we don't
3746 know how much masking to do. */
3755 /* If the operand is a CLOBBER, just return it. */
3756 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
3759 if (GET_CODE (XEXP (x, 1)) != CONST_INT
3760 || GET_CODE (XEXP (x, 2)) != CONST_INT
3761 || GET_MODE (XEXP (x, 0)) == VOIDmode)
3764 len = INTVAL (XEXP (x, 1));
3765 pos = INTVAL (XEXP (x, 2));
3767 /* If this goes outside the object being extracted, replace the object
3768 with a (use (mem ...)) construct that only combine understands
3769 and is used only for this purpose. */
3770 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3771 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
3774 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
3782 /* If we reach here, we want to return a pair of shifts. The inner
3783 shift is a left shift of BITSIZE - POS - LEN bits. The outer
3784 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3785 logical depending on the value of UNSIGNEDP.
3787 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3788 converted into an AND of a shift.
3790 We must check for the case where the left shift would have a negative
3791 count. This can happen in a case like (x >> 31) & 255 on machines
3792 that can't shift by a constant. On those machines, we would first
3793 combine the shift with the AND to produce a variable-position
3794 extraction. Then the constant of 31 would be substituted in to produce
3795 a such a position. */
3797 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
3798 if (modewidth >= pos - len)
3799 tem = simplify_shift_const (0, unsignedp ? LSHIFTRT : ASHIFTRT,
3801 simplify_shift_const (0, ASHIFT, GET_MODE (x),
3803 modewidth - pos - len),
3806 else if (unsignedp && len < HOST_BITS_PER_INT)
3807 tem = simplify_and_const_int (0, GET_MODE (x),
3808 simplify_shift_const (0, LSHIFTRT,
3813 /* Any other cases we can't handle. */
3817 /* If we couldn't do this for some reason, return the original
3819 if (GET_CODE (tem) == CLOBBER)
3825 /* X is a SET which contains an assignment of one object into
3826 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3827 or certain SUBREGS). If possible, convert it into a series of
3830 We half-heartedly support variable positions, but do not at all
3831 support variable lengths. */
3834 expand_field_assignment (x)
3838 rtx pos; /* Always counts from low bit. */
3841 enum machine_mode compute_mode;
3843 /* Loop until we find something we can't simplify. */
3846 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
3847 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
3849 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
3850 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
3853 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3854 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
3856 inner = XEXP (SET_DEST (x), 0);
3857 len = INTVAL (XEXP (SET_DEST (x), 1));
3858 pos = XEXP (SET_DEST (x), 2);
3860 /* If the position is constant and spans the width of INNER,
3861 surround INNER with a USE to indicate this. */
3862 if (GET_CODE (pos) == CONST_INT
3863 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
3864 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
3867 if (GET_CODE (pos) == CONST_INT)
3868 pos = gen_rtx (CONST_INT, VOIDmode,
3869 (GET_MODE_BITSIZE (GET_MODE (inner)) - len
3871 else if (GET_CODE (pos) == MINUS
3872 && GET_CODE (XEXP (pos, 1)) == CONST_INT
3873 && (INTVAL (XEXP (pos, 1))
3874 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
3875 /* If position is ADJUST - X, new position is X. */
3876 pos = XEXP (pos, 0);
3878 pos = gen_binary (MINUS, GET_MODE (pos),
3879 gen_rtx (CONST_INT, VOIDmode,
3880 (GET_MODE_BITSIZE (GET_MODE (inner))
3885 /* A SUBREG between two modes that occupy the same numbers of words
3886 can be done by moving the SUBREG to the source. */
3887 else if (GET_CODE (SET_DEST (x)) == SUBREG
3888 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
3889 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
3890 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
3891 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
3893 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
3894 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
3901 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3902 inner = SUBREG_REG (inner);
3904 compute_mode = GET_MODE (inner);
3906 /* Compute a mask of LEN bits, if we can do this on the host machine. */
3907 if (len < HOST_BITS_PER_INT)
3908 mask = gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1);
3912 /* Now compute the equivalent expression. Make a copy of INNER
3913 for the SET_DEST in case it is a MEM into which we will substitute;
3914 we don't want shared RTL in that case. */
3915 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
3916 gen_binary (IOR, compute_mode,
3917 gen_binary (AND, compute_mode,
3918 gen_unary (NOT, compute_mode,
3923 gen_binary (ASHIFT, compute_mode,
3924 gen_binary (AND, compute_mode,
3925 gen_lowpart_for_combine
3935 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3936 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3937 the starting bit position.
3939 INNER may be a USE. This will occur when we started with a bitfield
3940 that went outside the boundary of the object in memory, which is
3941 allowed on most machines. To isolate this case, we produce a USE
3942 whose mode is wide enough and surround the MEM with it. The only
3943 code that understands the USE is this routine. If it is not removed,
3944 it will cause the resulting insn not to match.
3946 UNSIGNEDP is non-zero for an unsigned reference and zero for a
3949 IN_DEST is non-zero if this is a reference in the destination of a
3950 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3951 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3954 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3955 ZERO_EXTRACT should be built even for bits starting at bit 0.
3957 MODE is the desired mode of the result (if IN_DEST == 0). */
3960 make_extraction (mode, inner, pos, pos_rtx, len,
3961 unsignedp, in_dest, in_compare)
3962 enum machine_mode mode;
3968 int in_dest, in_compare;
3970 enum machine_mode is_mode = GET_MODE (inner);
3971 enum machine_mode inner_mode;
3972 enum machine_mode wanted_mem_mode = byte_mode;
3973 enum machine_mode pos_mode = word_mode;
3974 enum machine_mode extraction_mode = word_mode;
3975 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
3979 /* Get some information about INNER and get the innermost object. */
3980 if (GET_CODE (inner) == USE)
3981 /* We don't need to adjust the position because we set up the USE
3982 to pretend that it was a full-word object. */
3983 spans_byte = 1, inner = XEXP (inner, 0);
3984 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3985 inner = SUBREG_REG (inner);
3987 inner_mode = GET_MODE (inner);
3989 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
3990 pos = INTVAL (pos_rtx);
3992 /* See if this can be done without an extraction. We never can if the
3993 width of the field is not the same as that of some integer mode. For
3994 registers, we can only avoid the extraction if the position is at the
3995 low-order bit and this is either not in the destination or we have the
3996 appropriate STRICT_LOW_PART operation available.
3998 For MEM, we can avoid an extract if the field starts on an appropriate
3999 boundary and we can change the mode of the memory reference. However,
4000 we cannot directly access the MEM if we have a USE and the underlying
4001 MEM is not TMODE. This combination means that MEM was being used in a
4002 context where bits outside its mode were being referenced; that is only
4003 valid in bit-field insns. */
4005 if (tmode != BLKmode
4006 && ! (spans_byte && inner_mode != tmode)
4007 && ((pos == 0 && GET_CODE (inner) == REG
4009 || (movstrict_optab->handlers[(int) tmode].insn_code
4010 != CODE_FOR_nothing)))
4011 || (GET_CODE (inner) == MEM && pos >= 0
4013 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4014 : BITS_PER_UNIT)) == 0
4015 /* We can't do this if we are widening INNER_MODE (it
4016 may not be aligned, for one thing). */
4017 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4018 && (inner_mode == tmode
4019 || (! mode_dependent_address_p (XEXP (inner, 0))
4020 && ! MEM_VOLATILE_P (inner))))))
4022 int offset = pos / BITS_PER_UNIT;
4024 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4025 field. If the original and current mode are the same, we need not
4026 adjust the offset. Otherwise, we do if bytes big endian.
4028 If INNER is not a MEM, get a piece consisting of the just the field
4029 of interest (in this case INNER must be a REG and POS must be 0). */
4031 if (GET_CODE (inner) == MEM)
4033 #if BYTES_BIG_ENDIAN
4034 if (inner_mode != tmode)
4035 offset = (GET_MODE_SIZE (inner_mode)
4036 - GET_MODE_SIZE (tmode) - offset);
4039 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4040 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4041 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4042 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4044 else if (GET_MODE (inner) == REG)
4045 /* We can't call gen_lowpart_for_combine here since we always want
4046 a SUBREG and it would sometimes return a new hard register. */
4047 new = gen_rtx (SUBREG, tmode, inner,
4049 && GET_MODE_SIZE (is_mode) > UNITS_PER_WORD)
4050 ? ((GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (tmode)
4054 new = gen_lowpart_for_combine (tmode, inner);
4056 /* If this extraction is going into the destination of a SET,
4057 make a STRICT_LOW_PART unless we made a MEM. */
4060 return (GET_CODE (new) == MEM ? new
4061 : (GET_CODE (new) != SUBREG
4062 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4063 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4065 /* Otherwise, sign- or zero-extend unless we already are in the
4068 return (mode == tmode ? new
4069 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4073 /* Unless this is in a COMPARE or we have a funny memory reference,
4074 don't do anything with field extracts starting at the low-order
4075 bit since they are simple AND operations. */
4076 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte)
4079 /* Get the mode to use should INNER be a MEM, the mode for the position,
4080 and the mode for the result. */
4084 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4085 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4086 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4091 if (! in_dest && unsignedp)
4093 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4094 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4095 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4100 if (! in_dest && ! unsignedp)
4102 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4103 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4104 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4108 /* Never narrow an object, since that might not be safe. */
4110 if (mode != VOIDmode
4111 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4112 extraction_mode = mode;
4114 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4115 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4116 pos_mode = GET_MODE (pos_rtx);
4118 /* If this is not from memory or we have to change the mode of memory and
4119 cannot, the desired mode is EXTRACTION_MODE. */
4120 if (GET_CODE (inner) != MEM
4121 || (inner_mode != wanted_mem_mode
4122 && (mode_dependent_address_p (XEXP (inner, 0))
4123 || MEM_VOLATILE_P (inner))))
4124 wanted_mem_mode = extraction_mode;
4127 /* If position is constant, compute new position. Otherwise, build
4130 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4134 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4135 gen_rtx (CONST_INT, VOIDmode,
4136 (MAX (GET_MODE_BITSIZE (is_mode),
4137 GET_MODE_BITSIZE (wanted_mem_mode))
4141 /* If INNER has a wider mode, make it smaller. If this is a constant
4142 extract, try to adjust the byte to point to the byte containing
4144 if (wanted_mem_mode != VOIDmode
4145 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4146 && ((GET_CODE (inner) == MEM
4147 && (inner_mode == wanted_mem_mode
4148 || (! mode_dependent_address_p (XEXP (inner, 0))
4149 && ! MEM_VOLATILE_P (inner))))))
4153 /* The computations below will be correct if the machine is big
4154 endian in both bits and bytes or little endian in bits and bytes.
4155 If it is mixed, we must adjust. */
4157 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4158 if (! spans_byte && is_mode != wanted_mem_mode)
4159 offset = (GET_MODE_SIZE (is_mode)
4160 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4163 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4164 adjust OFFSET to compensate. */
4165 #if BYTES_BIG_ENDIAN
4167 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4168 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4171 /* If this is a constant position, we can move to the desired byte. */
4174 offset += pos / BITS_PER_UNIT;
4175 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4178 if (offset != 0 || inner_mode != wanted_mem_mode)
4180 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4181 plus_constant (XEXP (inner, 0), offset));
4182 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4183 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4184 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4189 /* If INNER is not memory, we can always get it into the proper mode. */
4190 else if (GET_CODE (inner) != MEM)
4191 inner = gen_lowpart_for_combine (extraction_mode, inner);
4193 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4194 have to zero extend. Otherwise, we can just use a SUBREG. */
4196 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4197 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4199 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4200 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4202 /* Make POS_RTX unless we already have it and it is correct. */
4203 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4204 pos_rtx = gen_rtx (CONST_INT, VOIDmode, pos);
4206 /* Make the required operation. See if we can use existing rtx. */
4207 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4208 extraction_mode, inner,
4209 gen_rtx (CONST_INT, VOIDmode, len), pos_rtx);
4211 new = gen_lowpart_for_combine (mode, new);
4216 /* Look at the expression rooted at X. Look for expressions
4217 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4218 Form these expressions.
4220 Return the new rtx, usually just X.
4222 Also, for machines like the Vax that don't have logical shift insns,
4223 try to convert logical to arithmetic shift operations in cases where
4224 they are equivalent. This undoes the canonicalizations to logical
4225 shifts done elsewhere.
4227 We try, as much as possible, to re-use rtl expressions to save memory.
4229 IN_CODE says what kind of expression we are processing. Normally, it is
4230 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4231 being kludges), it is MEM. When processing the arguments of a comparison
4232 or a COMPARE against zero, it is COMPARE. */
4235 make_compound_operation (x, in_code)
4237 enum rtx_code in_code;
4239 enum rtx_code code = GET_CODE (x);
4240 enum machine_mode mode = GET_MODE (x);
4241 int mode_width = GET_MODE_BITSIZE (mode);
4242 enum rtx_code next_code;
4247 /* Select the code to be used in recursive calls. Once we are inside an
4248 address, we stay there. If we have a comparison, set to COMPARE,
4249 but once inside, go back to our default of SET. */
4251 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4252 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4253 && XEXP (x, 1) == const0_rtx) ? COMPARE
4254 : in_code == COMPARE ? SET : in_code);
4256 /* Process depending on the code of this operation. If NEW is set
4257 non-zero, it will be returned. */
4263 /* Convert shifts by constants into multiplications if inside
4265 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4266 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT
4267 && INTVAL (XEXP (x, 1)) >= 0)
4268 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4269 gen_rtx (CONST_INT, VOIDmode,
4270 1 << INTVAL (XEXP (x, 1))));
4274 /* If the second operand is not a constant, we can't do anything
4276 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4279 /* If the constant is a power of two minus one and the first operand
4280 is a logical right shift, make an extraction. */
4281 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4282 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4283 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4284 XEXP (XEXP (x, 0), 1), i, 1,
4285 0, in_code == COMPARE);
4287 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4288 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4289 && subreg_lowpart_p (XEXP (x, 0))
4290 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4291 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4292 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4293 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4294 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4295 0, in_code == COMPARE);
4298 /* If we are have (and (rotate X C) M) and C is larger than the number
4299 of bits in M, this is an extraction. */
4301 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4302 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4303 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4304 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4305 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4306 (GET_MODE_BITSIZE (mode)
4307 - INTVAL (XEXP (XEXP (x, 0), 1))),
4308 0, i, 1, 0, in_code == COMPARE);
4310 /* On machines without logical shifts, if the operand of the AND is
4311 a logical shift and our mask turns off all the propagated sign
4312 bits, we can replace the logical shift with an arithmetic shift. */
4324 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4325 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4326 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4327 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_INT
4328 && mode_width <= HOST_BITS_PER_INT)
4330 unsigned mask = GET_MODE_MASK (mode);
4332 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4333 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4335 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4336 XEXP (XEXP (x, 0), 1)));
4339 /* If the constant is one less than a power of two, this might be
4340 representable by an extraction even if no shift is present.
4341 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4342 we are in a COMPARE. */
4343 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4344 new = make_extraction (mode, XEXP (x, 0), 0, 0, i, 1,
4345 0, in_code == COMPARE);
4347 /* If we are in a comparison and this is an AND with a power of two,
4348 convert this into the appropriate bit extract. */
4349 else if (in_code == COMPARE
4350 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4351 new = make_extraction (mode, XEXP (x, 0), i, 0, 1, 1, 0, 1);
4356 /* If the sign bit is known to be zero, replace this with an
4357 arithmetic shift. */
4369 && mode_width <= HOST_BITS_PER_INT
4370 && (significant_bits (XEXP (x, 0), mode)
4371 & (1 << (mode_width - 1))) == 0)
4373 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4377 /* ... fall through ... */
4380 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4381 this is a SIGN_EXTRACT. */
4382 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4383 && GET_CODE (XEXP (x, 0)) == ASHIFT
4384 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4385 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4386 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4387 (INTVAL (XEXP (x, 1))
4388 - INTVAL (XEXP (XEXP (x, 0), 1))),
4389 0, mode_width - INTVAL (XEXP (x, 1)),
4390 code == LSHIFTRT, 0, in_code == COMPARE);
4397 code = GET_CODE (x);
4400 /* Now recursively process each operand of this operation. */
4401 fmt = GET_RTX_FORMAT (code);
4402 for (i = 0; i < GET_RTX_LENGTH (code); i++)
4405 new = make_compound_operation (XEXP (x, i), next_code);
4406 SUBST (XEXP (x, i), new);
4412 /* Given M see if it is a value that would select a field of bits
4413 within an item, but not the entire word. Return -1 if not.
4414 Otherwise, return the starting position of the field, where 0 is the
4417 *PLEN is set to the length of the field. */
4420 get_pos_from_mask (m, plen)
4424 /* Get the bit number of the first 1 bit from the right, -1 if none. */
4425 int pos = exact_log2 (m & - m);
4430 /* Now shift off the low-order zero bits and see if we have a power of
4432 *plen = exact_log2 ((m >> pos) + 1);
4440 /* Rewrite X so that it is an expression in MODE. We only care about the
4441 low-order BITS bits so we can ignore AND operations that just clear
4444 Also, if REG is non-zero and X is a register equal in value to REG,
4445 replace X with REG. */
4448 force_to_mode (x, mode, bits, reg)
4450 enum machine_mode mode;
4454 enum rtx_code code = GET_CODE (x);
4456 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
4457 just get X in the proper mode. */
4459 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
4460 || bits > GET_MODE_BITSIZE (mode))
4461 return gen_lowpart_for_combine (mode, x);
4469 x = expand_compound_operation (x);
4470 if (GET_CODE (x) != code)
4471 return force_to_mode (x, mode, bits, reg);
4475 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
4476 || rtx_equal_p (reg, get_last_value (x))))
4481 if (bits < HOST_BITS_PER_INT)
4482 x = gen_rtx (CONST_INT, VOIDmode, INTVAL (x) & ((1 << bits) - 1));
4486 /* Ignore low-order SUBREGs. */
4487 if (subreg_lowpart_p (x))
4488 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
4492 /* If this is an AND with a constant. Otherwise, we fall through to
4493 do the general binary case. */
4495 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4497 int mask = INTVAL (XEXP (x, 1));
4498 int len = exact_log2 (mask + 1);
4499 rtx op = XEXP (x, 0);
4501 /* If this is masking some low-order bits, we may be able to
4502 impose a stricter constraint on what bits of the operand are
4505 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
4508 if (bits < HOST_BITS_PER_INT)
4509 mask &= (1 << bits) - 1;
4511 x = simplify_and_const_int (x, mode, op, mask);
4513 /* If X is still an AND, see if it is an AND with a mask that
4514 is just some low-order bits. If so, and it is BITS wide (it
4515 can't be wider), we don't need it. */
4517 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
4518 && bits < HOST_BITS_PER_INT
4519 && INTVAL (XEXP (x, 1)) == (1 << bits) - 1)
4524 /* ... fall through ... */
4531 /* For most binary operations, just propagate into the operation and
4534 return gen_binary (code, mode,
4535 force_to_mode (XEXP (x, 0), mode, bits, reg),
4536 force_to_mode (XEXP (x, 1), mode, bits, reg));
4540 /* For left shifts, do the same, but just for the first operand.
4541 If the shift count is a constant, we need even fewer bits of the
4544 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
4545 bits -= INTVAL (XEXP (x, 1));
4547 return gen_binary (code, mode,
4548 force_to_mode (XEXP (x, 0), mode, bits, reg),
4552 /* Here we can only do something if the shift count is a constant and
4553 the count plus BITS is no larger than the width of MODE, we can do
4554 the shift in MODE. */
4556 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4557 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
4558 return gen_binary (LSHIFTRT, mode,
4559 force_to_mode (XEXP (x, 0), mode,
4560 bits + INTVAL (XEXP (x, 1)), reg),
4566 /* Handle these similarly to the way we handle most binary operations. */
4567 return gen_unary (code, mode,
4568 force_to_mode (XEXP (x, 0), mode, bits, reg));
4571 /* Otherwise, just do the operation canonically. */
4572 return gen_lowpart_for_combine (mode, x);
4575 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4576 Return that assignment if so.
4578 We only handle the most common cases. */
4581 make_field_assignment (x)
4584 rtx dest = SET_DEST (x);
4585 rtx src = SET_SRC (x);
4590 enum machine_mode mode;
4592 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4593 a clear of a one-bit field. We will have changed it to
4594 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4597 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
4598 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
4599 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
4600 && (rtx_equal_p (dest, XEXP (src, 1))
4601 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4602 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4604 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4606 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4609 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
4610 && subreg_lowpart_p (XEXP (src, 0))
4611 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
4612 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
4613 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
4614 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
4615 && (rtx_equal_p (dest, XEXP (src, 1))
4616 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4617 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4619 assign = make_extraction (VOIDmode, dest, -1,
4620 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
4622 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4625 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4627 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
4628 && XEXP (XEXP (src, 0), 0) == const1_rtx
4629 && (rtx_equal_p (dest, XEXP (src, 1))
4630 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4631 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4633 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4635 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
4638 /* The other case we handle is assignments into a constant-position
4639 field. They look like (ior (and DEST C1) OTHER). If C1 represents
4640 a mask that has all one bits except for a group of zero bits and
4641 OTHER is known to have zeros where C1 has ones, this is such an
4642 assignment. Compute the position and length from C1. Shift OTHER
4643 to the appropriate position, force it to the required mode, and
4644 make the extraction. Check for the AND in both operands. */
4646 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
4647 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
4648 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
4649 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
4650 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
4651 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
4652 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
4653 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
4654 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
4655 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
4656 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
4658 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
4662 pos = get_pos_from_mask (~c1, &len);
4663 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
4664 || (c1 & significant_bits (other, GET_MODE (other))) != 0)
4667 assign = make_extraction (VOIDmode, dest, pos, 0, len, 1, 1, 0);
4669 /* The mode to use for the source is the mode of the assignment, or of
4670 what is inside a possible STRICT_LOW_PART. */
4671 mode = (GET_CODE (assign) == STRICT_LOW_PART
4672 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
4674 /* Shift OTHER right POS places and make it the source, restricting it
4675 to the proper length and mode. */
4677 src = force_to_mode (simplify_shift_const (0, LSHIFTRT, GET_MODE (src),
4681 return gen_rtx_combine (SET, VOIDmode, assign, src);
4684 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4688 apply_distributive_law (x)
4691 enum rtx_code code = GET_CODE (x);
4692 rtx lhs, rhs, other;
4694 enum rtx_code inner_code;
4696 /* The outer operation can only be one of the following: */
4697 if (code != IOR && code != AND && code != XOR
4698 && code != PLUS && code != MINUS)
4701 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
4703 /* If either operand is a primitive we can't do anything, so get out fast. */
4704 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
4705 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
4708 lhs = expand_compound_operation (lhs);
4709 rhs = expand_compound_operation (rhs);
4710 inner_code = GET_CODE (lhs);
4711 if (inner_code != GET_CODE (rhs))
4714 /* See if the inner and outer operations distribute. */
4721 /* These all distribute except over PLUS. */
4722 if (code == PLUS || code == MINUS)
4727 if (code != PLUS && code != MINUS)
4733 /* These are also multiplies, so they distribute over everything. */
4737 /* Non-paradoxical SUBREGs distributes over all operations, provided
4738 the inner modes and word numbers are the same, this is an extraction
4739 of a low-order part, we don't convert an fp operation to int or
4740 vice versa, and we would not be converting a single-word
4741 operation into a multi-word operation. The latter test is not
4742 required, but it prevents generating unneeded multi-word operations.
4743 Some of the previous tests are redundant given the latter test, but
4744 are retained because they are required for correctness.
4746 We produce the result slightly differently in this case. */
4748 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
4749 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
4750 || ! subreg_lowpart_p (lhs)
4751 || (GET_MODE_CLASS (GET_MODE (lhs))
4752 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
4753 || (GET_MODE_SIZE (GET_MODE (lhs))
4754 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
4755 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
4758 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
4759 SUBREG_REG (lhs), SUBREG_REG (rhs));
4760 return gen_lowpart_for_combine (GET_MODE (x), tem);
4766 /* Set LHS and RHS to the inner operands (A and B in the example
4767 above) and set OTHER to the common operand (C in the example).
4768 These is only one way to do this unless the inner operation is
4770 if (GET_RTX_CLASS (inner_code) == 'c'
4771 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
4772 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
4773 else if (GET_RTX_CLASS (inner_code) == 'c'
4774 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
4775 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
4776 else if (GET_RTX_CLASS (inner_code) == 'c'
4777 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
4778 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
4779 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
4780 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
4784 /* Form the new inner operation, seeing if it simplifies first. */
4785 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
4787 /* There is one exception to the general way of distributing:
4788 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4789 if (code == XOR && inner_code == IOR)
4792 other = gen_unary (NOT, GET_MODE (x), other);
4795 /* We may be able to continuing distributing the result, so call
4796 ourselves recursively on the inner operation before forming the
4797 outer operation, which we return. */
4798 return gen_binary (inner_code, GET_MODE (x),
4799 apply_distributive_law (tem), other);
4802 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4805 Return an equivalent form, if different from X. Otherwise, return X. If
4806 X is zero, we are to always construct the equivalent form. */
4809 simplify_and_const_int (x, mode, varop, constop)
4811 enum machine_mode mode;
4815 register enum machine_mode tmode;
4817 unsigned significant;
4819 /* There is a large class of optimizations based on the principle that
4820 some operations produce results where certain bits are known to be zero,
4821 and hence are not significant to the AND. For example, if we have just
4822 done a left shift of one bit, the low-order bit is known to be zero and
4823 hence an AND with a mask of ~1 would not do anything.
4825 At the end of the following loop, we set:
4827 VAROP to be the item to be AND'ed with;
4828 CONSTOP to the constant value to AND it with. */
4832 /* If we ever encounter a mode wider than the host machine's word
4833 size, we can't compute the masks accurately, so give up. */
4834 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_INT)
4837 /* Unless one of the cases below does a `continue',
4838 a `break' will be executed to exit the loop. */
4840 switch (GET_CODE (varop))
4843 /* If VAROP is a (clobber (const_int)), return it since we know
4844 we are generating something that won't match. */
4847 #if ! BITS_BIG_ENDIAN
4849 /* VAROP is a (use (mem ..)) that was made from a bit-field
4850 extraction that spanned the boundary of the MEM. If we are
4851 now masking so it is within that boundary, we don't need the
4853 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
4855 varop = XEXP (varop, 0);
4862 if (subreg_lowpart_p (varop)
4863 /* We can ignore the effect this SUBREG if it narrows the mode
4864 or, on machines where byte operations zero extend, if the
4865 constant masks to zero all the bits the mode doesn't have. */
4866 && ((GET_MODE_SIZE (GET_MODE (varop))
4867 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
4868 #ifdef BYTE_LOADS_ZERO_EXTEND
4870 & GET_MODE_MASK (GET_MODE (varop))
4871 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
4875 varop = SUBREG_REG (varop);
4884 /* Try to expand these into a series of shifts and then work
4885 with that result. If we can't, for example, if the extract
4886 isn't at a fixed position, give up. */
4887 temp = expand_compound_operation (varop);
4896 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
4898 constop &= INTVAL (XEXP (varop, 1));
4899 varop = XEXP (varop, 0);
4906 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4907 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4908 operation which may be a bitfield extraction. */
4910 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4911 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4912 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4913 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT
4914 && GET_CODE (XEXP (varop, 1)) == CONST_INT
4915 && (INTVAL (XEXP (varop, 1))
4916 & ~ significant_bits (XEXP (varop, 0),
4917 GET_MODE (varop)) == 0))
4919 temp = gen_rtx (CONST_INT, VOIDmode,
4920 ((INTVAL (XEXP (varop, 1)) & constop)
4921 << INTVAL (XEXP (XEXP (varop, 0), 1))));
4922 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
4923 XEXP (XEXP (varop, 0), 0), temp);
4924 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4925 temp, XEXP (varop, 1));
4929 /* Apply the AND to both branches of the IOR or XOR, then try to
4930 apply the distributive law. This may eliminate operations
4931 if either branch can be simplified because of the AND.
4932 It may also make some cases more complex, but those cases
4933 probably won't match a pattern either with or without this. */
4935 gen_lowpart_for_combine
4936 (mode, apply_distributive_law
4938 (GET_CODE (varop), GET_MODE (varop),
4939 simplify_and_const_int (0, GET_MODE (varop),
4940 XEXP (varop, 0), constop),
4941 simplify_and_const_int (0, GET_MODE (varop),
4942 XEXP (varop, 1), constop))));
4945 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4946 LSHIFTRT we can do the same as above. */
4948 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4949 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4950 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4951 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT)
4953 temp = gen_rtx (CONST_INT, VOIDmode,
4954 constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
4955 temp = gen_binary (XOR, GET_MODE (varop),
4956 XEXP (XEXP (varop, 0), 0), temp);
4957 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4958 temp, XEXP (XEXP (varop, 0), 1));
4964 /* If we are just looking for the sign bit, we don't need this
4965 shift at all, even if it has a variable count. */
4966 if (constop == 1 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1))
4968 varop = XEXP (varop, 0);
4972 /* If this is a shift by a constant, get a mask that contains
4973 those bits that are not copies of the sign bit. We then have
4974 two cases: If CONSTOP only includes those bits, this can be
4975 a logical shift, which may allow simplifications. If CONSTOP
4976 is a single-bit field not within those bits, we are requesting
4977 a copy of the sign bit and hence can shift the sign bit to
4978 the appropriate location. */
4979 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4980 && INTVAL (XEXP (varop, 1)) >= 0
4981 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_INT)
4985 significant = GET_MODE_MASK (GET_MODE (varop));
4986 significant >>= INTVAL (XEXP (varop, 1));
4988 if ((constop & ~significant) == 0
4989 || (i = exact_log2 (constop)) >= 0)
4991 varop = simplify_shift_const
4992 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
4993 i < 0 ? INTVAL (XEXP (varop, 1))
4994 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
4995 if (GET_CODE (varop) != ASHIFTRT)
5000 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5001 even if the shift count isn't a constant. */
5003 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5004 XEXP (varop, 0), XEXP (varop, 1));
5008 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5009 included in STORE_FLAG_VALUE and FOO has no significant bits
5011 if ((constop & ~ STORE_FLAG_VALUE) == 0
5012 && XEXP (varop, 0) == const0_rtx
5013 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5015 varop = XEXP (varop, 0);
5021 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5022 low-order bits (as in an alignment operation) and FOO is already
5023 aligned to that boundary, we can convert remove this AND
5024 and possibly the PLUS if it is now adding zero. */
5025 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5026 && exact_log2 (-constop) >= 0
5027 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5029 varop = plus_constant (XEXP (varop, 0),
5030 INTVAL (XEXP (varop, 1)) & constop);
5035 /* ... fall through ... */
5038 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5039 less than powers of two and M2 is narrower than M1, we can
5040 eliminate the inner AND. This occurs when incrementing
5043 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5044 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5045 SUBST (XEXP (varop, 0),
5046 expand_compound_operation (XEXP (varop, 0)));
5048 if (GET_CODE (XEXP (varop, 0)) == AND
5049 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5050 && exact_log2 (constop + 1) >= 0
5051 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5052 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5053 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5060 /* If we have reached a constant, this whole thing is constant. */
5061 if (GET_CODE (varop) == CONST_INT)
5062 return gen_rtx (CONST_INT, VOIDmode, constop & INTVAL (varop));
5064 /* See what bits are significant in VAROP. */
5065 significant = significant_bits (varop, mode);
5067 /* Turn off all bits in the constant that are known to already be zero.
5068 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5069 which is tested below. */
5071 constop &= significant;
5073 /* If we don't have any bits left, return zero. */
5077 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5078 if we already had one (just check for the simplest cases). */
5079 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5080 && GET_MODE (XEXP (x, 0)) == mode
5081 && SUBREG_REG (XEXP (x, 0)) == varop)
5082 varop = XEXP (x, 0);
5084 varop = gen_lowpart_for_combine (mode, varop);
5086 /* If we can't make the SUBREG, try to return what we were given. */
5087 if (GET_CODE (varop) == CLOBBER)
5088 return x ? x : varop;
5090 /* If we are only masking insignificant bits, return VAROP. */
5091 if (constop == significant)
5094 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5095 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5096 x = gen_rtx_combine (AND, mode, varop,
5097 gen_rtx (CONST_INT, VOIDmode, constop));
5101 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5102 || INTVAL (XEXP (x, 1)) != constop)
5103 SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, constop));
5105 SUBST (XEXP (x, 0), varop);
5111 /* Given an expression, X, compute which bits in X can be non-zero.
5112 We don't care about bits outside of those defined in MODE.
5114 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5115 a shift, AND, or zero_extract, we can do better. */
5118 significant_bits (x, mode)
5120 enum machine_mode mode;
5122 unsigned significant = GET_MODE_MASK (mode);
5125 int mode_width = GET_MODE_BITSIZE (mode);
5128 /* If X is wider than MODE, use its mode instead. */
5129 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5131 mode = GET_MODE (x);
5132 significant = GET_MODE_MASK (mode);
5133 mode_width = GET_MODE_BITSIZE (mode);
5136 if (mode_width > HOST_BITS_PER_INT)
5137 /* Our only callers in this case look for single bit values. So
5138 just return the mode mask. Those tests will then be false. */
5141 code = GET_CODE (x);
5145 #ifdef STACK_BOUNDARY
5146 /* If this is the stack pointer, we may know something about its
5147 alignment. If PUSH_ROUNDING is defined, it is possible for the
5148 stack to be momentarily aligned only to that amount, so we pick
5149 the least alignment. */
5151 if (x == stack_pointer_rtx)
5153 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5155 #ifdef PUSH_ROUNDING
5156 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5159 return significant & ~ (sp_alignment - 1);
5163 /* If X is a register whose value we can find, use that value.
5164 Otherwise, use the previously-computed significant bits for this
5167 tem = get_last_value (x);
5169 return significant_bits (tem, mode);
5170 else if (significant_valid && reg_significant[REGNO (x)])
5171 return reg_significant[REGNO (x)] & significant;
5178 #ifdef BYTE_LOADS_ZERO_EXTEND
5180 /* In many, if not most, RISC machines, reading a byte from memory
5181 zeros the rest of the register. Noticing that fact saves a lot
5182 of extra zero-extends. */
5183 significant &= GET_MODE_MASK (GET_MODE (x));
5187 #if STORE_FLAG_VALUE == 1
5194 if (GET_MODE_CLASS (mode) == MODE_INT)
5197 /* A comparison operation only sets the bits given by its mode. The
5198 rest are set undefined. */
5199 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5200 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5204 #if STORE_FLAG_VALUE == -1
5206 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5207 || ((tem = get_last_value (XEXP (x, 0))) != 0
5208 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))
5211 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5212 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5217 significant &= (significant_bits (XEXP (x, 0), mode)
5218 & GET_MODE_MASK (mode));
5222 significant &= significant_bits (XEXP (x, 0), mode);
5223 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5224 significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5228 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5229 Otherwise, show all the bits in the outer mode but not the inner
5231 inner_sig = significant_bits (XEXP (x, 0), mode);
5232 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5234 inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5236 (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
5237 inner_sig |= (GET_MODE_MASK (mode)
5238 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
5241 significant &= inner_sig;
5245 significant &= (significant_bits (XEXP (x, 0), mode)
5246 & significant_bits (XEXP (x, 1), mode));
5251 significant &= (significant_bits (XEXP (x, 0), mode)
5252 | significant_bits (XEXP (x, 1), mode));
5255 case PLUS: case MINUS:
5257 case DIV: case UDIV:
5258 case MOD: case UMOD:
5259 /* We can apply the rules of arithmetic to compute the number of
5260 high- and low-order zero bits of these operations. We start by
5261 computing the width (position of the highest-order non-zero bit)
5262 and the number of low-order zero bits for each value. */
5264 unsigned sig0 = significant_bits (XEXP (x, 0), mode);
5265 unsigned sig1 = significant_bits (XEXP (x, 1), mode);
5266 int width0 = floor_log2 (sig0) + 1;
5267 int width1 = floor_log2 (sig1) + 1;
5268 int low0 = floor_log2 (sig0 & -sig0);
5269 int low1 = floor_log2 (sig1 & -sig1);
5270 int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
5271 int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
5272 int result_width = mode_width;
5278 result_width = MAX (width0, width1) + 1;
5279 result_low = MIN (low0, low1);
5282 result_low = MIN (low0, low1);
5285 result_width = width0 + width1;
5286 result_low = low0 + low1;
5289 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5290 result_width = width0;
5293 result_width = width0;
5296 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5297 result_width = MIN (width0, width1);
5298 result_low = MIN (low0, low1);
5301 result_width = MIN (width0, width1);
5302 result_low = MIN (low0, low1);
5306 if (result_width < mode_width)
5307 significant &= (1 << result_width) - 1;
5310 significant &= ~ ((1 << result_low) - 1);
5315 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5316 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5317 significant &= (1 << INTVAL (XEXP (x, 1))) - 1;
5321 /* If the inner mode is a single word for both the host and target
5322 machines, we can compute this from which bits of the inner
5323 object are known significant. */
5324 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5325 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
5327 significant &= significant_bits (SUBREG_REG (x), mode);
5328 #ifndef BYTE_LOADS_ZERO_EXTEND
5329 /* On many CISC machines, accessing an object in a wider mode
5330 causes the high-order bits to become undefined. So they are
5331 not known to be zero. */
5332 if (GET_MODE_SIZE (GET_MODE (x))
5333 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5334 significant |= (GET_MODE_MASK (GET_MODE (x))
5335 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
5345 /* The significant bits are in two classes: any bits within MODE
5346 that aren't in GET_MODE (x) are always significant. The rest of the
5347 significant bits are those that are significant in the operand of
5348 the shift when shifted the appropriate number of bits. This
5349 shows that high-order bits are cleared by the right shift and
5350 low-order bits by left shifts. */
5351 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5352 && INTVAL (XEXP (x, 1)) >= 0
5353 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5355 enum machine_mode inner_mode = GET_MODE (x);
5356 int width = GET_MODE_BITSIZE (inner_mode);
5357 int count = INTVAL (XEXP (x, 1));
5358 unsigned mode_mask = GET_MODE_MASK (inner_mode);
5359 unsigned op_significant = significant_bits (XEXP (x, 0), mode);
5360 unsigned inner = op_significant & mode_mask;
5363 if (mode_width > width)
5364 outer = (op_significant & significant & ~ mode_mask);
5366 if (code == LSHIFTRT)
5368 else if (code == ASHIFTRT)
5372 /* If the sign bit was significant at before the shift, we
5373 need to mark all the places it could have been copied to
5374 by the shift significant. */
5375 if (inner & (1 << (width - 1 - count)))
5376 inner |= ((1 << count) - 1) << (width - count);
5378 else if (code == LSHIFT || code == ASHIFT)
5381 inner = ((inner << (count % width)
5382 | (inner >> (width - (count % width)))) & mode_mask);
5384 significant &= (outer | inner);
5389 /* This is at most the number of bits in the mode. */
5390 significant = (1 << (floor_log2 (mode_width) + 1)) - 1;
5397 /* This function is called from `simplify_shift_const' to merge two
5398 outer operations. Specifically, we have already found that we need
5399 to perform operation *POP0 with constant *PCONST0 at the outermost
5400 position. We would now like to also perform OP1 with constant CONST1
5401 (with *POP0 being done last).
5403 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5404 the resulting operation. *PCOMP_P is set to 1 if we would need to
5405 complement the innermost operand, otherwise it is unchanged.
5407 MODE is the mode in which the operation will be done. No bits outside
5408 the width of this mode matter. It is assumed that the width of this mode
5409 is smaller than or equal to HOST_BITS_PER_INT.
5411 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5412 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5413 result is simply *PCONST0.
5415 If the resulting operation cannot be expressed as one operation, we
5416 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5419 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
5420 enum rtx_code *pop0;
5424 enum machine_mode mode;
5427 enum rtx_code op0 = *pop0;
5428 int const0 = *pconst0;
5430 const0 &= GET_MODE_MASK (mode);
5431 const1 &= GET_MODE_MASK (mode);
5433 /* If OP0 is an AND, clear unimportant bits in CONST1. */
5437 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5440 if (op1 == NIL || op0 == SET)
5443 else if (op0 == NIL)
5444 op0 = op1, const0 = const1;
5446 else if (op0 == op1)
5468 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5469 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
5472 /* If the two constants aren't the same, we can't do anything. The
5473 remaining six cases can all be done. */
5474 else if (const0 != const1)
5482 /* (a & b) | b == b */
5484 else /* op1 == XOR */
5485 /* (a ^ b) | b == a | b */
5491 /* (a & b) ^ b == (~a) & b */
5492 op0 = AND, *pcomp_p = 1;
5493 else /* op1 == IOR */
5494 /* (a | b) ^ b == a & ~b */
5495 op0 = AND, *pconst0 = ~ const0;
5500 /* (a | b) & b == b */
5502 else /* op1 == XOR */
5503 /* (a ^ b) & b) == (~a) & b */
5508 /* Check for NO-OP cases. */
5509 const0 &= GET_MODE_MASK (mode);
5511 && (op0 == IOR || op0 == XOR || op0 == PLUS))
5513 else if (const0 == 0 && op0 == AND)
5515 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
5524 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5525 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5526 that we started with.
5528 The shift is normally computed in the widest mode we find in VAROP, as
5529 long as it isn't a different number of words than RESULT_MODE. Exceptions
5530 are ASHIFTRT and ROTATE, which are always done in their original mode, */
5533 simplify_shift_const (x, code, result_mode, varop, count)
5536 enum machine_mode result_mode;
5540 enum rtx_code orig_code = code;
5541 int orig_count = count;
5542 enum machine_mode mode = result_mode;
5543 enum machine_mode shift_mode, tmode;
5545 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
5546 /* We form (outer_op (code varop count) (outer_const)). */
5547 enum rtx_code outer_op = NIL;
5550 int complement_p = 0;
5553 /* If we were given an invalid count, don't do anything except exactly
5554 what was requested. */
5556 if (count < 0 || count > GET_MODE_BITSIZE (mode))
5561 return gen_rtx (code, mode, varop, gen_rtx (CONST_INT, VOIDmode, count));
5564 /* Unless one of the branches of the `if' in this loop does a `continue',
5565 we will `break' the loop after the `if'. */
5569 /* If we have an operand of (clobber (const_int 0)), just return that
5571 if (GET_CODE (varop) == CLOBBER)
5574 /* If we discovered we had to complement VAROP, leave. Making a NOT
5575 here would cause an infinite loop. */
5579 /* Convert ROTATETRT to ROTATE. */
5580 if (code == ROTATERT)
5581 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
5583 /* Canonicalize LSHIFT to ASHIFT. */
5587 /* We need to determine what mode we will do the shift in. If the
5588 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5589 was originally done in. Otherwise, we can do it in MODE, the widest
5590 mode encountered. */
5591 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
5593 /* Handle cases where the count is greater than the size of the mode
5594 minus 1. For ASHIFT, use the size minus one as the count (this can
5595 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5596 take the count modulo the size. For other shifts, the result is
5599 Since these shifts are being produced by the compiler by combining
5600 multiple operations, each of which are defined, we know what the
5601 result is supposed to be. */
5603 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
5605 if (code == ASHIFTRT)
5606 count = GET_MODE_BITSIZE (shift_mode) - 1;
5607 else if (code == ROTATE || code == ROTATERT)
5608 count %= GET_MODE_BITSIZE (shift_mode);
5611 /* We can't simply return zero because there may be an
5619 /* Negative counts are invalid and should not have been made (a
5620 programmer-specified negative count should have been handled
5625 /* We simplify the tests below and elsewhere by converting
5626 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5627 `make_compound_operation' will convert it to a ASHIFTRT for
5628 those machines (such as Vax) that don't have a LSHIFTRT. */
5629 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_INT
5631 && (significant_bits (varop, shift_mode)
5632 & (1 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0)
5635 switch (GET_CODE (varop))
5641 new = expand_compound_operation (varop);
5650 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5651 minus the width of a smaller mode, we can do this with a
5652 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5653 if ((code == ASHIFTRT || code == LSHIFTRT)
5654 && ! mode_dependent_address_p (XEXP (varop, 0))
5655 && ! MEM_VOLATILE_P (varop)
5656 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5657 MODE_INT, 1)) != BLKmode)
5659 #if BYTES_BIG_ENDIAN
5660 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
5662 new = gen_rtx (MEM, tmode,
5663 plus_constant (XEXP (varop, 0),
5664 count / BITS_PER_UNIT));
5665 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
5666 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
5667 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
5669 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5670 : ZERO_EXTEND, mode, new);
5677 /* Similar to the case above, except that we can only do this if
5678 the resulting mode is the same as that of the underlying
5679 MEM and adjust the address depending on the *bits* endianness
5680 because of the way that bit-field extract insns are defined. */
5681 if ((code == ASHIFTRT || code == LSHIFTRT)
5682 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5683 MODE_INT, 1)) != BLKmode
5684 && tmode == GET_MODE (XEXP (varop, 0)))
5687 new = XEXP (varop, 0);
5689 new = copy_rtx (XEXP (varop, 0));
5690 SUBST (XEXP (new, 0),
5691 plus_constant (XEXP (new, 0),
5692 count / BITS_PER_UNIT));
5695 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5696 : ZERO_EXTEND, mode, new);
5703 /* If VAROP is a SUBREG, strip it as long as the inner operand has
5704 the same number of words as what we've seen so far. Then store
5705 the widest mode in MODE. */
5706 if (SUBREG_WORD (varop) == 0
5707 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
5708 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5711 varop = SUBREG_REG (varop);
5712 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
5713 mode = GET_MODE (varop);
5719 /* Some machines use MULT instead of ASHIFT because MULT
5720 is cheaper. But it is still better on those machines to
5721 merge two shifts into one. */
5722 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5723 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5725 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5726 gen_rtx (CONST_INT, VOIDmode,
5727 exact_log2 (INTVAL (XEXP (varop, 1)))));
5733 /* Similar, for when divides are cheaper. */
5734 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5735 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5737 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5738 gen_rtx (CONST_INT, VOIDmode,
5739 exact_log2 (INTVAL (XEXP (varop, 1)))));
5745 /* If we are extracting just the sign bit of an arithmetic right
5746 shift, that shift is not needed. */
5747 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
5749 varop = XEXP (varop, 0);
5753 /* ... fall through ... */
5759 /* Here we have two nested shifts. The result is usually the
5760 AND of a new shift with a mask. We compute the result below. */
5761 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5762 && INTVAL (XEXP (varop, 1)) >= 0
5763 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5764 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5765 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
5767 enum rtx_code first_code = GET_CODE (varop);
5768 int first_count = INTVAL (XEXP (varop, 1));
5773 if (first_code == LSHIFT)
5774 first_code = ASHIFT;
5776 /* We have one common special case. We can't do any merging if
5777 the inner code is an ASHIFTRT of a smaller mode. However, if
5778 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5779 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5780 we can convert it to
5781 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5782 This simplifies certain SIGN_EXTEND operations. */
5783 if (code == ASHIFT && first_code == ASHIFTRT
5784 && (GET_MODE_BITSIZE (result_mode)
5785 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
5787 /* C3 has the low-order C1 bits zero. */
5789 mask = GET_MODE_MASK (mode) & ~ ((1 << first_count) - 1);
5791 varop = simplify_and_const_int (0, result_mode,
5792 XEXP (varop, 0), mask);
5793 varop = simplify_shift_const (0, ASHIFT, result_mode,
5795 count = first_count;
5800 /* If this was (ashiftrt (ashift foo C1) C2) and we know
5801 something about FOO's previous value, we may be able to
5802 optimize this even though the code below can't handle this
5805 If FOO has J high-order bits equal to the sign bit with
5806 J > C1, then we can convert this to either an ASHIFT or
5807 a ASHIFTRT depending on the two counts.
5809 We cannot do this if VAROP's mode is not SHIFT_MODE. */
5811 if (code == ASHIFTRT && first_code == ASHIFT
5812 && GET_MODE (varop) == shift_mode
5813 && (inner = get_last_value (XEXP (varop, 0))) != 0)
5815 if ((GET_CODE (inner) == CONST_INT
5816 && (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == 0
5817 || (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == -1)))
5818 || (GET_CODE (inner) == SIGN_EXTEND
5819 && ((GET_MODE_BITSIZE (GET_MODE (inner))
5820 - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner))))
5822 || (GET_CODE (inner) == ASHIFTRT
5823 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5824 && INTVAL (XEXP (inner, 1)) >= first_count))
5826 count -= first_count;
5828 count = - count, code = ASHIFT;
5829 varop = XEXP (varop, 0);
5834 /* There are some cases we can't do. If CODE is ASHIFTRT,
5835 we can only do this if FIRST_CODE is also ASHIFTRT.
5837 We can't do the case when CODE is ROTATE and FIRST_CODE is
5840 If the mode of this shift is not the mode of the outer shift,
5841 we can't do this if either shift is ASHIFTRT or ROTATE.
5843 Finally, we can't do any of these if the mode is too wide
5844 unless the codes are the same.
5846 Handle the case where the shift codes are the same
5849 if (code == first_code)
5851 if (GET_MODE (varop) != result_mode
5852 && (code == ASHIFTRT || code == ROTATE))
5855 count += first_count;
5856 varop = XEXP (varop, 0);
5860 if (code == ASHIFTRT
5861 || (code == ROTATE && first_code == ASHIFTRT)
5862 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_INT
5863 || (GET_MODE (varop) != result_mode
5864 && (first_code == ASHIFTRT || first_code == ROTATE
5865 || code == ROTATE)))
5868 /* To compute the mask to apply after the shift, shift the
5869 significant bits of the inner shift the same way the
5870 outer shift will. */
5872 mask_rtx = gen_rtx (CONST_INT, VOIDmode,
5873 significant_bits (varop, GET_MODE (varop)));
5876 = simplify_binary_operation (code, result_mode, mask_rtx,
5877 gen_rtx (CONST_INT, VOIDmode,
5880 /* Give up if we can't compute an outer operation to use. */
5882 || GET_CODE (mask_rtx) != CONST_INT
5883 || ! merge_outer_ops (&outer_op, &outer_const, AND,
5885 result_mode, &complement_p))
5888 /* If the shifts are in the same direction, we add the
5889 counts. Otherwise, we subtract them. */
5890 if ((code == ASHIFTRT || code == LSHIFTRT)
5891 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
5892 count += first_count;
5894 count -= first_count;
5896 /* If COUNT is positive, the new shift is usually CODE,
5897 except for the two exceptions below, in which case it is
5898 FIRST_CODE. If the count is negative, FIRST_CODE should
5901 && ((first_code == ROTATE && code == ASHIFT)
5902 || (first_code == ASHIFTRT && code == LSHIFTRT)))
5905 code = first_code, count = - count;
5907 varop = XEXP (varop, 0);
5911 /* If we have (A << B << C) for any shift, we can convert this to
5912 (A << C << B). This wins if A is a constant. Only try this if
5913 B is not a constant. */
5915 else if (GET_CODE (varop) == code
5916 && GET_CODE (XEXP (varop, 1)) != CONST_INT
5918 = simplify_binary_operation (code, mode,
5924 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
5931 /* Make this fit the case below. */
5932 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5933 gen_rtx (CONST_INT, VOIDmode,
5934 GET_MODE_MASK (mode)));
5940 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5941 with C the size of VAROP - 1 and the shift is logical if
5942 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5943 we have an (le X 0) operation. If we have an arithmetic shift
5944 and STORE_FLAG_VALUE is 1 or we have a logical shift with
5945 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5947 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
5948 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
5949 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5950 && (code == LSHIFTRT || code == ASHIFTRT)
5951 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
5952 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
5955 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
5958 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
5959 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
5964 /* If we have (shift (logical)), move the logical to the outside
5965 to allow it to possibly combine with another logical and the
5966 shift to combine with another shift. This also canonicalizes to
5967 what a ZERO_EXTRACT looks like. Also, some machines have
5968 (and (shift)) insns. */
5970 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5971 && (new = simplify_binary_operation (code, result_mode,
5976 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
5977 INTVAL (new), result_mode, &complement_p))
5979 varop = XEXP (varop, 0);
5983 /* If we can't do that, try to simplify the shift in each arm of the
5984 logical expression, make a new logical expression, and apply
5985 the inverse distributive law. */
5987 rtx lhs = simplify_shift_const (0, code, result_mode,
5988 XEXP (varop, 0), count);
5989 rtx rhs = simplify_shift_const (0, code, result_mode,
5990 XEXP (varop, 1), count);
5992 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
5993 varop = apply_distributive_law (varop);
6000 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
6001 says that the sign bit can be tested, FOO has mode MODE, C is
6002 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
6005 && XEXP (varop, 1) == const0_rtx
6006 && GET_MODE (XEXP (varop, 0)) == result_mode
6007 && count == GET_MODE_BITSIZE (result_mode) - 1
6008 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
6009 && ((STORE_FLAG_VALUE
6010 & (1 << (GET_MODE_BITSIZE (result_mode) - 1))))
6011 && significant_bits (XEXP (varop, 0), result_mode) == 1
6012 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
6013 result_mode, &complement_p))
6015 varop = XEXP (varop, 0);
6022 /* If we are doing an arithmetic right shift of something known
6023 to be -1 or 0, we don't need the shift. */
6024 if (code == ASHIFTRT
6025 && significant_bits (XEXP (varop, 0), result_mode) == 1)
6031 /* NEG commutes with ASHIFT since it is multiplication. Move the
6032 NEG outside to allow shifts to combine. */
6034 && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
6035 result_mode, &complement_p))
6037 varop = XEXP (varop, 0);
6043 /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
6044 if (XEXP (varop, 1) == constm1_rtx && code == ASHIFTRT
6045 && significant_bits (XEXP (varop, 0), result_mode) == 1)
6051 /* If we have the same operands as above but we are shifting the
6052 sign bit into the low-order bit, we are exclusive-or'ing
6053 the operand of the PLUS with a one. */
6054 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
6055 && XEXP (varop, 1) == constm1_rtx
6056 && significant_bits (XEXP (varop, 0), result_mode) == 1
6057 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
6058 result_mode, &complement_p))
6061 varop = XEXP (varop, 0);
6065 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
6066 significant in BAR are those being shifted out and those
6067 bits are known zero in FOO, we can replace the PLUS with FOO.
6068 Similarly in the other operand order. This code occurs when
6069 we are computing the size of a variable-size array. */
6071 if ((code == ASHIFTRT || code == LSHIFTRT)
6072 && count < HOST_BITS_PER_INT
6073 && significant_bits (XEXP (varop, 1), result_mode) >> count == 0
6074 && (significant_bits (XEXP (varop, 1), result_mode)
6075 & significant_bits (XEXP (varop, 0), result_mode)) == 0)
6077 varop = XEXP (varop, 0);
6080 else if ((code == ASHIFTRT || code == LSHIFTRT)
6081 && count < HOST_BITS_PER_INT
6082 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
6084 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
6085 & significant_bits (XEXP (varop, 1),
6088 varop = XEXP (varop, 1);
6092 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
6094 && GET_CODE (XEXP (varop, 1)) == CONST_INT
6095 && (new = simplify_binary_operation (ASHIFT, result_mode,
6100 && merge_outer_ops (&outer_op, &outer_const, PLUS,
6101 INTVAL (new), result_mode, &complement_p))
6103 varop = XEXP (varop, 0);
6109 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
6110 with C the size of VAROP - 1 and the shift is logical if
6111 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6112 we have a (gt X 0) operation. If the shift is arithmetic with
6113 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
6114 we have a (neg (gt X 0)) operation. */
6116 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
6117 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
6118 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6119 && (code == LSHIFTRT || code == ASHIFTRT)
6120 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6121 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
6122 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
6125 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
6128 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
6129 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
6139 /* We need to determine what mode to do the shift in. If the shift is
6140 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
6141 done in. Otherwise, we can do it in MODE, the widest mode encountered.
6142 The code we care about is that of the shift that will actually be done,
6143 not the shift that was originally requested. */
6144 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6146 /* We have now finished analyzing the shift. The result should be
6147 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
6148 OUTER_OP is non-NIL, it is an operation that needs to be applied
6149 to the result of the shift. OUTER_CONST is the relevant constant,
6150 but we must turn off all bits turned off in the shift.
6152 If we were passed a value for X, see if we can use any pieces of
6153 it. If not, make new rtx. */
6155 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
6156 && GET_CODE (XEXP (x, 1)) == CONST_INT
6157 && INTVAL (XEXP (x, 1)) == count)
6158 const_rtx = XEXP (x, 1);
6160 const_rtx = gen_rtx (CONST_INT, VOIDmode, count);
6162 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6163 && GET_MODE (XEXP (x, 0)) == shift_mode
6164 && SUBREG_REG (XEXP (x, 0)) == varop)
6165 varop = XEXP (x, 0);
6166 else if (GET_MODE (varop) != shift_mode)
6167 varop = gen_lowpart_for_combine (shift_mode, varop);
6169 /* If we can't make the SUBREG, try to return what we were given. */
6170 if (GET_CODE (varop) == CLOBBER)
6171 return x ? x : varop;
6173 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
6178 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
6179 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
6181 SUBST (XEXP (x, 0), varop);
6182 SUBST (XEXP (x, 1), const_rtx);
6185 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
6186 turn off all the bits that the shift would have turned off. */
6187 if (orig_code == LSHIFTRT && result_mode != shift_mode)
6188 x = simplify_and_const_int (0, shift_mode, x,
6189 GET_MODE_MASK (result_mode) >> orig_count);
6191 /* Do the remainder of the processing in RESULT_MODE. */
6192 x = gen_lowpart_for_combine (result_mode, x);
6194 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6197 x = gen_unary (NOT, result_mode, x);
6199 if (outer_op != NIL)
6201 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_INT)
6202 outer_const &= GET_MODE_MASK (result_mode);
6204 if (outer_op == AND)
6205 x = simplify_and_const_int (0, result_mode, x, outer_const);
6206 else if (outer_op == SET)
6207 /* This means that we have determined that the result is
6208 equivalent to a constant. This should be rare. */
6209 x = gen_rtx (CONST_INT, VOIDmode, outer_const);
6210 else if (GET_RTX_CLASS (outer_op) == '1')
6211 x = gen_unary (outer_op, result_mode, x);
6213 x = gen_binary (outer_op, result_mode, x,
6214 gen_rtx (CONST_INT, VOIDmode, outer_const));
6220 /* Like recog, but we receive the address of a pointer to a new pattern.
6221 We try to match the rtx that the pointer points to.
6222 If that fails, we may try to modify or replace the pattern,
6223 storing the replacement into the same pointer object.
6225 Modifications include deletion or addition of CLOBBERs.
6227 PNOTES is a pointer to a location where any REG_UNUSED notes added for
6228 the CLOBBERs are placed.
6230 The value is the final insn code from the pattern ultimately matched,
6234 recog_for_combine (pnewpat, insn, pnotes)
6239 register rtx pat = *pnewpat;
6240 int insn_code_number;
6241 int num_clobbers_to_add = 0;
6245 /* Is the result of combination a valid instruction? */
6246 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6248 /* If it isn't, there is the possibility that we previously had an insn
6249 that clobbered some register as a side effect, but the combined
6250 insn doesn't need to do that. So try once more without the clobbers
6251 unless this represents an ASM insn. */
6253 if (insn_code_number < 0 && ! check_asm_operands (pat)
6254 && GET_CODE (pat) == PARALLEL)
6258 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
6259 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
6262 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
6266 SUBST_INT (XVECLEN (pat, 0), pos);
6269 pat = XVECEXP (pat, 0, 0);
6271 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6274 /* If we had any clobbers to add, make a new pattern than contains
6275 them. Then check to make sure that all of them are dead. */
6276 if (num_clobbers_to_add)
6278 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
6279 gen_rtvec (GET_CODE (pat) == PARALLEL
6280 ? XVECLEN (pat, 0) + num_clobbers_to_add
6281 : num_clobbers_to_add + 1));
6283 if (GET_CODE (pat) == PARALLEL)
6284 for (i = 0; i < XVECLEN (pat, 0); i++)
6285 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
6287 XVECEXP (newpat, 0, 0) = pat;
6289 add_clobbers (newpat, insn_code_number);
6291 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
6292 i < XVECLEN (newpat, 0); i++)
6294 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
6295 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
6297 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
6298 XEXP (XVECEXP (newpat, 0, i), 0), notes);
6306 return insn_code_number;
6309 /* Like gen_lowpart but for use by combine. In combine it is not possible
6310 to create any new pseudoregs. However, it is safe to create
6311 invalid memory addresses, because combine will try to recognize
6312 them and all they will do is make the combine attempt fail.
6314 If for some reason this cannot do its job, an rtx
6315 (clobber (const_int 0)) is returned.
6316 An insn containing that will not be recognized. */
6321 gen_lowpart_for_combine (mode, x)
6322 enum machine_mode mode;
6327 if (GET_MODE (x) == mode)
6330 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
6331 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6333 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6334 won't know what to do. So we will strip off the SUBREG here and
6335 process normally. */
6336 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
6339 if (GET_MODE (x) == mode)
6343 result = gen_lowpart_common (mode, x);
6347 if (GET_CODE (x) == MEM)
6349 register int offset = 0;
6352 /* Refuse to work on a volatile memory ref or one with a mode-dependent
6354 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
6355 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6357 /* If we want to refer to something bigger than the original memref,
6358 generate a perverse subreg instead. That will force a reload
6359 of the original memref X. */
6360 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
6361 return gen_rtx (SUBREG, mode, x, 0);
6363 #if WORDS_BIG_ENDIAN
6364 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
6365 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
6367 #if BYTES_BIG_ENDIAN
6368 /* Adjust the address so that the address-after-the-data
6370 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
6371 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
6373 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
6374 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
6375 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
6376 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
6380 /* If X is a comparison operator, rewrite it in a new mode. This
6381 probably won't match, but may allow further simplifications. */
6382 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
6383 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
6385 /* If we couldn't simplify X any other way, just enclose it in a
6386 SUBREG. Normally, this SUBREG won't match, but some patterns may
6387 include an explicit SUBREG or we may simplify it further in combine. */
6392 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
6393 word = ((GET_MODE_SIZE (GET_MODE (x))
6394 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
6396 return gen_rtx (SUBREG, mode, x, word);
6400 /* Make an rtx expression. This is a subset of gen_rtx and only supports
6401 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6403 If the identical expression was previously in the insn (in the undobuf),
6404 it will be returned. Only if it is not found will a new expression
6409 gen_rtx_combine (va_alist)
6414 enum machine_mode mode;
6422 code = va_arg (p, enum rtx_code);
6423 mode = va_arg (p, enum machine_mode);
6424 n_args = GET_RTX_LENGTH (code);
6425 fmt = GET_RTX_FORMAT (code);
6427 if (n_args == 0 || n_args > 3)
6430 /* Get each arg and verify that it is supposed to be an expression. */
6431 for (j = 0; j < n_args; j++)
6436 args[j] = va_arg (p, rtx);
6439 /* See if this is in undobuf. Be sure we don't use objects that came
6440 from another insn; this could produce circular rtl structures. */
6442 for (i = previous_num_undos; i < undobuf.num_undo; i++)
6443 if (!undobuf.undo[i].is_int
6444 && GET_CODE (undobuf.undo[i].old_contents) == code
6445 && GET_MODE (undobuf.undo[i].old_contents) == mode)
6447 for (j = 0; j < n_args; j++)
6448 if (XEXP (undobuf.undo[i].old_contents, j) != args[j])
6452 return undobuf.undo[i].old_contents;
6455 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6456 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6457 rt = rtx_alloc (code);
6458 PUT_MODE (rt, mode);
6459 XEXP (rt, 0) = args[0];
6462 XEXP (rt, 1) = args[1];
6464 XEXP (rt, 2) = args[2];
6469 /* These routines make binary and unary operations by first seeing if they
6470 fold; if not, a new expression is allocated. */
6473 gen_binary (code, mode, op0, op1)
6475 enum machine_mode mode;
6480 if (GET_RTX_CLASS (code) == '<')
6482 enum machine_mode op_mode = GET_MODE (op0);
6483 if (op_mode == VOIDmode)
6484 op_mode = GET_MODE (op1);
6485 result = simplify_relational_operation (code, op_mode, op0, op1);
6488 result = simplify_binary_operation (code, mode, op0, op1);
6493 /* Put complex operands first and constants second. */
6494 if (GET_RTX_CLASS (code) == 'c'
6495 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
6496 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
6497 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
6498 || (GET_CODE (op0) == SUBREG
6499 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
6500 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
6501 return gen_rtx_combine (code, mode, op1, op0);
6503 return gen_rtx_combine (code, mode, op0, op1);
6507 gen_unary (code, mode, op0)
6509 enum machine_mode mode;
6512 rtx result = simplify_unary_operation (code, mode, op0, mode);
6517 return gen_rtx_combine (code, mode, op0);
6520 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6521 comparison code that will be tested.
6523 The result is a possibly different comparison code to use. *POP0 and
6524 *POP1 may be updated.
6526 It is possible that we might detect that a comparison is either always
6527 true or always false. However, we do not perform general constant
6528 folding in combine, so this knowledge isn't useful. Such tautologies
6529 should have been detected earlier. Hence we ignore all such cases. */
6531 static enum rtx_code
6532 simplify_comparison (code, pop0, pop1)
6541 enum machine_mode mode, tmode;
6543 /* Try a few ways of applying the same transformation to both operands. */
6546 /* If both operands are the same constant shift, see if we can ignore the
6547 shift. We can if the shift is a rotate or if the bits shifted out of
6548 this shift are not significant for either input and if the type of
6549 comparison is compatible with the shift. */
6550 if (GET_CODE (op0) == GET_CODE (op1)
6551 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6552 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
6553 || ((GET_CODE (op0) == LSHIFTRT
6554 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6555 && (code != GT && code != LT && code != GE && code != LE))
6556 || (GET_CODE (op0) == ASHIFTRT
6557 && (code != GTU && code != LTU
6558 && code != GEU && code != GEU)))
6559 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6560 && INTVAL (XEXP (op0, 1)) >= 0
6561 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
6562 && XEXP (op0, 1) == XEXP (op1, 1))
6564 enum machine_mode mode = GET_MODE (op0);
6565 unsigned mask = GET_MODE_MASK (mode);
6566 int shift_count = INTVAL (XEXP (op0, 1));
6568 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
6569 mask &= (mask >> shift_count) << shift_count;
6570 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6571 mask = (mask & (mask << shift_count)) >> shift_count;
6573 if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
6574 && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
6575 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
6580 /* If both operands are AND's of a paradoxical SUBREG by constant, the
6581 SUBREGs are of the same mode, and, in both cases, the AND would
6582 be redundant if the comparison was done in the narrower mode,
6583 do the comparison in the narrower mode (e.g., we are AND'ing with 1
6584 and the operand's significant bits are 0xffffff01; in that case if
6585 we only care about QImode, we don't need the AND). This case occurs
6586 if the output mode of an scc insn is not SImode and
6587 STORE_FLAG_VALUE == 1 (e.g., the 386). */
6589 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
6590 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6591 && GET_CODE (XEXP (op1, 1)) == CONST_INT
6592 && GET_CODE (XEXP (op0, 0)) == SUBREG
6593 && GET_CODE (XEXP (op1, 0)) == SUBREG
6594 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
6595 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
6596 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
6597 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6598 && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
6599 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
6600 & ~ INTVAL (XEXP (op0, 1))) == 0
6601 && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
6602 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6603 & ~ INTVAL (XEXP (op1, 1))) == 0)
6605 op0 = SUBREG_REG (XEXP (op0, 0));
6606 op1 = SUBREG_REG (XEXP (op1, 0));
6608 /* the resulting comparison is always unsigned since we masked off
6609 the original sign bit. */
6610 code = unsigned_condition (code);
6616 /* If the first operand is a constant, swap the operands and adjust the
6617 comparison code appropriately. */
6618 if (CONSTANT_P (op0))
6620 tem = op0, op0 = op1, op1 = tem;
6621 code = swap_condition (code);
6624 /* We now enter a loop during which we will try to simplify the comparison.
6625 For the most part, we only are concerned with comparisons with zero,
6626 but some things may really be comparisons with zero but not start
6627 out looking that way. */
6629 while (GET_CODE (op1) == CONST_INT)
6631 enum machine_mode mode = GET_MODE (op0);
6632 int mode_width = GET_MODE_BITSIZE (mode);
6633 unsigned mask = GET_MODE_MASK (mode);
6634 int equality_comparison_p;
6635 int sign_bit_comparison_p;
6636 int unsigned_comparison_p;
6639 /* We only want to handle integral modes. This catches VOIDmode,
6640 CCmode, and the floating-point modes. An exception is that we
6641 can handle VOIDmode if OP0 is a COMPARE or a comparison
6644 if (GET_MODE_CLASS (mode) != MODE_INT
6645 && ! (mode == VOIDmode
6646 && (GET_CODE (op0) == COMPARE
6647 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
6650 /* Get the constant we are comparing against and turn off all bits
6651 not on in our mode. */
6652 const_op = INTVAL (op1);
6653 if (mode_width <= HOST_BITS_PER_INT)
6656 /* If we are comparing against a constant power of two and the value
6657 being compared has only that single significant bit (e.g., it was
6658 `and'ed with that bit), we can replace this with a comparison
6661 && (code == EQ || code == NE || code == GE || code == GEU
6662 || code == LT || code == LTU)
6663 && mode_width <= HOST_BITS_PER_INT
6664 && exact_log2 (const_op) >= 0
6665 && significant_bits (op0, mode) == const_op)
6667 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
6668 op1 = const0_rtx, const_op = 0;
6671 /* Do some canonicalizations based on the comparison code. We prefer
6672 comparisons against zero and then prefer equality comparisons.
6673 If we can reduce the size of a constant, we will do that too. */
6678 /* < C is equivalent to <= (C - 1) */
6682 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6684 /* ... fall through to LE case below. */
6690 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
6694 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6698 /* If we are doing a <= 0 comparison on a value known to have
6699 a zero sign bit, we can replace this with == 0. */
6700 else if (const_op == 0
6701 && mode_width <= HOST_BITS_PER_INT
6702 && (significant_bits (op0, mode)
6703 & (1 << (mode_width - 1))) == 0)
6708 /* >= C is equivalent to > (C - 1). */
6712 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6714 /* ... fall through to GT below. */
6720 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
6724 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6728 /* If we are doing a > 0 comparison on a value known to have
6729 a zero sign bit, we can replace this with != 0. */
6730 else if (const_op == 0
6731 && mode_width <= HOST_BITS_PER_INT
6732 && (significant_bits (op0, mode)
6733 & (1 << (mode_width - 1))) == 0)
6738 /* < C is equivalent to <= (C - 1). */
6742 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6744 /* ... fall through ... */
6750 /* unsigned <= 0 is equivalent to == 0 */
6756 /* >= C is equivalent to < (C - 1). */
6760 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6762 /* ... fall through ... */
6768 /* unsigned > 0 is equivalent to != 0 */
6774 /* Compute some predicates to simplify code below. */
6776 equality_comparison_p = (code == EQ || code == NE);
6777 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
6778 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
6781 /* Now try cases based on the opcode of OP0. If none of the cases
6782 does a "continue", we exit this loop immediately after the
6785 switch (GET_CODE (op0))
6788 /* If we are extracting a single bit from a variable position in
6789 a constant that has only a single bit set and are comparing it
6790 with zero, we can convert this into an equality comparison
6791 between the position and the location of the single bit. We can't
6792 do this if bit endian and we don't have an extzv since we then
6793 can't know what mode to use for the endianness adjustment. */
6795 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6796 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
6797 && XEXP (op0, 1) == const1_rtx
6798 && equality_comparison_p && const_op == 0
6799 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
6802 i = (GET_MODE_BITSIZE
6803 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
6806 op0 = XEXP (op0, 2);
6807 op1 = gen_rtx (CONST_INT, VOIDmode, i);
6810 /* Result is nonzero iff shift count is equal to I. */
6811 code = reverse_condition (code);
6816 /* ... fall through ... */
6819 tem = expand_compound_operation (op0);
6828 /* If testing for equality, we can take the NOT of the constant. */
6829 if (equality_comparison_p
6830 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
6832 op0 = XEXP (op0, 0);
6837 /* If just looking at the sign bit, reverse the sense of the
6839 if (sign_bit_comparison_p)
6841 op0 = XEXP (op0, 0);
6842 code = (code == GE ? LT : GE);
6848 /* If testing for equality, we can take the NEG of the constant. */
6849 if (equality_comparison_p
6850 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
6852 op0 = XEXP (op0, 0);
6857 /* The remaining cases only apply to comparisons with zero. */
6861 /* When X is ABS or is known positive,
6862 (neg X) is < 0 if and only if X != 0. */
6864 if (sign_bit_comparison_p
6865 && (GET_CODE (XEXP (op0, 0)) == ABS
6866 || (mode_width <= HOST_BITS_PER_INT
6867 && (significant_bits (XEXP (op0, 0), mode)
6868 & (1 << (mode_width - 1))) == 0)))
6870 op0 = XEXP (op0, 0);
6871 code = (code == LT ? NE : EQ);
6875 /* If we have NEG of something that is the result of a
6876 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6877 two high-order bits must be the same and hence that
6878 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6880 if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
6881 || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
6882 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6883 && (INTVAL (XEXP (XEXP (op0, 0), 1))
6884 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
6885 || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6886 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6887 && XEXP (XEXP (op0, 0), 1) != const0_rtx)
6888 || ((tem = get_last_value (XEXP (op0, 0))) != 0
6889 && (GET_CODE (tem) == SIGN_EXTEND
6890 || (GET_CODE (tem) == SIGN_EXTRACT
6891 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6892 && (INTVAL (XEXP (tem, 1))
6893 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
6894 || (GET_CODE (tem) == ASHIFTRT
6895 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6896 && XEXP (tem, 1) != const0_rtx))))
6898 op0 = XEXP (op0, 0);
6899 code = swap_condition (code);
6905 /* If we are testing equality and our count is a constant, we
6906 can perform the inverse operation on our RHS. */
6907 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6908 && (tem = simplify_binary_operation (ROTATERT, mode,
6909 op1, XEXP (op0, 1))) != 0)
6911 op0 = XEXP (op0, 0);
6916 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6917 a particular bit. Convert it to an AND of a constant of that
6918 bit. This will be converted into a ZERO_EXTRACT. */
6919 if (const_op == 0 && sign_bit_comparison_p
6920 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6921 && mode_width <= HOST_BITS_PER_INT)
6923 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
6924 1 << (mode_width - 1
6925 - INTVAL (XEXP (op0, 1))));
6926 code = (code == LT ? NE : EQ);
6930 /* ... fall through ... */
6933 /* ABS is ignorable inside an equality comparison with zero. */
6934 if (const_op == 0 && equality_comparison_p)
6936 op0 = XEXP (op0, 0);
6943 /* Can simplify (compare (zero/sign_extend FOO) CONST)
6944 to (compare FOO CONST) if CONST fits in FOO's mode and we
6945 are either testing inequality or have an unsigned comparison
6946 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6947 if (! unsigned_comparison_p
6948 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6949 <= HOST_BITS_PER_INT)
6950 && ((unsigned) const_op
6951 < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))
6953 op0 = XEXP (op0, 0);
6959 /* If the inner mode is smaller and we are extracting the low
6960 part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6961 if (! subreg_lowpart_p (op0)
6962 || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) >= mode_width)
6965 /* ... fall through ... */
6968 if ((unsigned_comparison_p || equality_comparison_p)
6969 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6970 <= HOST_BITS_PER_INT)
6971 && ((unsigned) const_op
6972 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
6974 op0 = XEXP (op0, 0);
6980 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
6981 this for equality comparisons due to pathological cases involving
6983 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6984 && (tem = simplify_binary_operation (MINUS, mode, op1,
6985 XEXP (op0, 1))) != 0)
6987 op0 = XEXP (op0, 0);
6992 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6993 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
6994 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
6996 op0 = XEXP (XEXP (op0, 0), 0);
6997 code = (code == LT ? EQ : NE);
7003 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
7004 of bits in X minus 1, is one iff X > 0. */
7005 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
7006 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
7007 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
7008 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
7010 op0 = XEXP (op0, 1);
7011 code = (code == GE ? LE : GT);
7017 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
7018 if C is zero or B is a constant. */
7019 if (equality_comparison_p
7020 && 0 != (tem = simplify_binary_operation (XOR, mode,
7021 XEXP (op0, 1), op1)))
7023 op0 = XEXP (op0, 0);
7030 case LT: case LTU: case LE: case LEU:
7031 case GT: case GTU: case GE: case GEU:
7032 /* We can't do anything if OP0 is a condition code value, rather
7033 than an actual data value. */
7036 || XEXP (op0, 0) == cc0_rtx
7038 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
7041 /* Get the two operands being compared. */
7042 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
7043 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
7045 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
7047 /* Check for the cases where we simply want the result of the
7048 earlier test or the opposite of that result. */
7050 || (code == EQ && reversible_comparison_p (op0))
7051 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
7052 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7053 && (STORE_FLAG_VALUE
7054 & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))
7056 || (code == GE && reversible_comparison_p (op0)))))
7058 code = (code == LT || code == NE
7059 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
7060 op0 = tem, op1 = tem1;
7066 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
7068 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
7069 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
7070 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
7072 op0 = XEXP (op0, 1);
7073 code = (code == GE ? GT : LE);
7079 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
7080 will be converted to a ZERO_EXTRACT later. */
7081 if (const_op == 0 && equality_comparison_p
7082 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
7083 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
7084 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
7086 op0 = simplify_and_const_int
7087 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
7089 XEXP (XEXP (op0, 0), 1)),
7094 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
7095 zero and X is a comparison and C1 and C2 describe only bits set
7096 in STORE_FLAG_VALUE, we can compare with X. */
7097 if (const_op == 0 && equality_comparison_p
7098 && mode_width <= HOST_BITS_PER_INT
7099 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7100 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
7101 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
7102 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
7103 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_INT)
7105 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
7106 << INTVAL (XEXP (XEXP (op0, 0), 1)));
7107 if ((~ STORE_FLAG_VALUE & mask) == 0
7108 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
7109 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
7110 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
7112 op0 = XEXP (XEXP (op0, 0), 0);
7117 /* If we are doing an equality comparison of an AND of a bit equal
7118 to the sign bit, replace this with a LT or GE comparison of
7119 the underlying value. */
7120 if (equality_comparison_p
7122 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7123 && mode_width <= HOST_BITS_PER_INT
7124 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
7125 == 1 << (mode_width - 1)))
7127 op0 = XEXP (op0, 0);
7128 code = (code == EQ ? GE : LT);
7132 /* If this AND operation is really a ZERO_EXTEND from a narrower
7133 mode, the constant fits within that mode, and this is either an
7134 equality or unsigned comparison, try to do this comparison in
7135 the narrower mode. */
7136 if ((equality_comparison_p || unsigned_comparison_p)
7137 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7138 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
7139 & GET_MODE_MASK (mode))
7141 && const_op >> i == 0
7142 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
7144 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
7151 /* If we have (compare (xshift FOO N) (const_int C)) and
7152 the high order N bits of FOO (N+1 if an inequality comparison)
7153 are not significant, we can do this by comparing FOO with C
7154 shifted right N bits so long as the low-order N bits of C are
7156 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7157 && INTVAL (XEXP (op0, 1)) >= 0
7158 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
7159 < HOST_BITS_PER_INT)
7160 && (const_op & ~ ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7161 && mode_width <= HOST_BITS_PER_INT
7162 && (significant_bits (XEXP (op0, 0), mode)
7163 & ~ (mask >> (INTVAL (XEXP (op0, 1))
7164 + ! equality_comparison_p))) == 0)
7166 const_op >>= INTVAL (XEXP (op0, 1));
7167 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7168 op0 = XEXP (op0, 0);
7172 /* If we are doing a sign bit comparison, it means we are testing
7173 a particular bit. Convert it to the appropriate AND. */
7174 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
7175 && mode_width <= HOST_BITS_PER_INT)
7177 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
7178 1 << ( mode_width - 1
7179 - INTVAL (XEXP (op0, 1))));
7180 code = (code == LT ? NE : EQ);
7184 /* If this an equality comparison with zero and we are shifting
7185 the low bit to the sign bit, we can convert this to an AND of the
7187 if (const_op == 0 && equality_comparison_p
7188 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7189 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7191 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), 1);
7197 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
7198 do the comparison in a narrower mode. */
7199 if (! unsigned_comparison_p
7200 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7201 && GET_CODE (XEXP (op0, 0)) == ASHIFT
7202 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
7203 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
7204 MODE_INT, 1)) != VOIDmode
7205 && ((unsigned) const_op <= GET_MODE_MASK (tmode)
7206 || (unsigned) - const_op <= GET_MODE_MASK (tmode)))
7208 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
7212 /* ... fall through ... */
7214 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7215 the low order N bits of FOO are not significant, we can do this
7216 by comparing FOO with C shifted left N bits so long as no
7218 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7219 && INTVAL (XEXP (op0, 1)) >= 0
7220 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
7221 && mode_width <= HOST_BITS_PER_INT
7222 && (significant_bits (XEXP (op0, 0), mode)
7223 & ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7225 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
7228 const_op <<= INTVAL (XEXP (op0, 1));
7229 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7230 op0 = XEXP (op0, 0);
7234 /* If we are using this shift to extract just the sign bit, we
7235 can replace this with an LT or GE comparison. */
7237 && (equality_comparison_p || sign_bit_comparison_p)
7238 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7239 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7241 op0 = XEXP (op0, 0);
7242 code = (code == NE || code == GT ? LT : GE);
7251 /* Now make any compound operations involved in this comparison. Then,
7252 check for an outmost SUBREG on OP0 that isn't doing anything or is
7253 paradoxical. The latter case can only occur when it is known that the
7254 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7255 We can never remove a SUBREG for a non-equality comparison because the
7256 sign bit is in a different place in the underlying object. */
7258 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
7259 op1 = make_compound_operation (op1, SET);
7261 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7262 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7263 && (code == NE || code == EQ)
7264 && ((GET_MODE_SIZE (GET_MODE (op0))
7265 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
7267 op0 = SUBREG_REG (op0);
7268 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
7271 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7272 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7273 && (code == NE || code == EQ)
7274 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
7275 && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
7276 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
7277 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
7279 (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
7280 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
7281 op0 = SUBREG_REG (op0), op1 = tem;
7283 /* We now do the opposite procedure: Some machines don't have compare
7284 insns in all modes. If OP0's mode is an integer mode smaller than a
7285 word and we can't do a compare in that mode, see if there is a larger
7286 mode for which we can do the compare and where the only significant
7287 bits in OP0 and OP1 are those in the narrower mode. We can do
7288 this if this is an equality comparison, in which case we can
7289 merely widen the operation, or if we are testing the sign bit, in
7290 which case we can explicitly put in the test. */
7292 mode = GET_MODE (op0);
7293 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
7294 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
7295 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
7296 for (tmode = GET_MODE_WIDER_MODE (mode);
7297 tmode != VOIDmode && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_INT;
7298 tmode = GET_MODE_WIDER_MODE (tmode))
7299 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing
7300 && (significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
7301 && (significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0
7302 && (code == EQ || code == NE
7303 || (op1 == const0_rtx && (code == LT || code == GE)
7304 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)))
7306 op0 = gen_lowpart_for_combine (tmode, op0);
7307 op1 = gen_lowpart_for_combine (tmode, op1);
7309 if (code == LT || code == GE)
7311 op0 = gen_binary (AND, tmode, op0,
7312 gen_rtx (CONST_INT, VOIDmode,
7313 1 << (GET_MODE_BITSIZE (mode) - 1)));
7314 code = (code == LT) ? NE : EQ;
7326 /* Return 1 if we know that X, a comparison operation, is not operating
7327 on a floating-point value or is EQ or NE, meaning that we can safely
7331 reversible_comparison_p (x)
7334 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7335 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
7338 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
7344 x = get_last_value (XEXP (x, 0));
7345 return (x && GET_CODE (x) == COMPARE
7346 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
7352 /* Utility function for following routine. Called when X is part of a value
7353 being stored into reg_last_set_value. Sets reg_last_set_table_tick
7354 for each register mentioned. Similar to mention_regs in cse.c */
7357 update_table_tick (x)
7360 register enum rtx_code code = GET_CODE (x);
7361 register char *fmt = GET_RTX_FORMAT (code);
7366 int regno = REGNO (x);
7367 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7368 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7370 for (i = regno; i < endregno; i++)
7371 reg_last_set_table_tick[i] = label_tick;
7376 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7377 /* Note that we can't have an "E" in values stored; see
7378 get_last_value_validate. */
7380 update_table_tick (XEXP (x, i));
7383 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7384 are saying that the register is clobbered and we no longer know its
7385 value. If INSN is zero, don't update reg_last_set; this call is normally
7386 done with VALUE also zero to invalidate the register. */
7389 record_value_for_reg (reg, insn, value)
7394 int regno = REGNO (reg);
7395 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7396 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
7399 /* If VALUE contains REG and we have a previous value for REG, substitute
7400 the previous value. */
7401 if (value && insn && reg_overlap_mentioned_p (reg, value))
7405 /* Set things up so get_last_value is allowed to see anything set up to
7407 subst_low_cuid = INSN_CUID (insn);
7408 tem = get_last_value (reg);
7411 value = replace_rtx (copy_rtx (value), reg, tem);
7414 /* For each register modified, show we don't know its value, that
7415 its value has been updated, and that we don't know the location of
7416 the death of the register. */
7417 for (i = regno; i < endregno; i ++)
7420 reg_last_set[i] = insn;
7421 reg_last_set_value[i] = 0;
7422 reg_last_death[i] = 0;
7425 /* Mark registers that are being referenced in this value. */
7427 update_table_tick (value);
7429 /* Now update the status of each register being set.
7430 If someone is using this register in this block, set this register
7431 to invalid since we will get confused between the two lives in this
7432 basic block. This makes using this register always invalid. In cse, we
7433 scan the table to invalidate all entries using this register, but this
7434 is too much work for us. */
7436 for (i = regno; i < endregno; i++)
7438 reg_last_set_label[i] = label_tick;
7439 if (value && reg_last_set_table_tick[i] == label_tick)
7440 reg_last_set_invalid[i] = 1;
7442 reg_last_set_invalid[i] = 0;
7445 /* The value being assigned might refer to X (like in "x++;"). In that
7446 case, we must replace it with (clobber (const_int 0)) to prevent
7448 if (value && ! get_last_value_validate (&value,
7449 reg_last_set_label[regno], 0))
7451 value = copy_rtx (value);
7452 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
7456 /* For the main register being modified, update the value. */
7457 reg_last_set_value[regno] = value;
7461 /* Used for communication between the following two routines. */
7462 static rtx record_dead_insn;
7464 /* Called via note_stores from record_dead_and_set_regs to handle one
7465 SET or CLOBBER in an insn. */
7468 record_dead_and_set_regs_1 (dest, setter)
7471 if (GET_CODE (dest) == REG)
7473 /* If we are setting the whole register, we know its value. Otherwise
7474 show that we don't know the value. We can handle SUBREG in
7476 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
7477 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
7478 else if (GET_CODE (setter) == SET
7479 && GET_CODE (SET_DEST (setter)) == SUBREG
7480 && SUBREG_REG (SET_DEST (setter)) == dest
7481 && subreg_lowpart_p (SET_DEST (setter)))
7482 record_value_for_reg
7483 (dest, record_dead_insn,
7484 gen_lowpart_for_combine (GET_MODE (SET_DEST (setter)),
7487 record_value_for_reg (dest, record_dead_insn, 0);
7489 else if (GET_CODE (dest) == MEM
7490 /* Ignore pushes, they clobber nothing. */
7491 && ! push_operand (dest, GET_MODE (dest)))
7492 mem_last_set = INSN_CUID (record_dead_insn);
7495 /* Update the records of when each REG was most recently set or killed
7496 for the things done by INSN. This is the last thing done in processing
7497 INSN in the combiner loop.
7499 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7500 similar information mem_last_set (which insn most recently modified memory)
7501 and last_call_cuid (which insn was the most recent subroutine call). */
7504 record_dead_and_set_regs (insn)
7508 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7510 if (REG_NOTE_KIND (link) == REG_DEAD)
7511 reg_last_death[REGNO (XEXP (link, 0))] = insn;
7512 else if (REG_NOTE_KIND (link) == REG_INC)
7513 record_value_for_reg (XEXP (link, 0), insn, 0);
7516 if (GET_CODE (insn) == CALL_INSN)
7517 last_call_cuid = mem_last_set = INSN_CUID (insn);
7519 record_dead_insn = insn;
7520 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
7523 /* Utility routine for the following function. Verify that all the registers
7524 mentioned in *LOC are valid when *LOC was part of a value set when
7525 label_tick == TICK. Return 0 if some are not.
7527 If REPLACE is non-zero, replace the invalid reference with
7528 (clobber (const_int 0)) and return 1. This replacement is useful because
7529 we often can get useful information about the form of a value (e.g., if
7530 it was produced by a shift that always produces -1 or 0) even though
7531 we don't know exactly what registers it was produced from. */
7534 get_last_value_validate (loc, tick, replace)
7540 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
7541 int len = GET_RTX_LENGTH (GET_CODE (x));
7544 if (GET_CODE (x) == REG)
7546 int regno = REGNO (x);
7547 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7548 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7551 for (j = regno; j < endregno; j++)
7552 if (reg_last_set_invalid[j]
7553 /* If this is a pseudo-register that was only set once, it is
7555 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
7556 && reg_last_set_label[j] > tick))
7559 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7566 for (i = 0; i < len; i++)
7568 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
7569 /* Don't bother with these. They shouldn't occur anyway. */
7573 /* If we haven't found a reason for it to be invalid, it is valid. */
7577 /* Get the last value assigned to X, if known. Some registers
7578 in the value may be replaced with (clobber (const_int 0)) if their value
7579 is known longer known reliably. */
7588 /* If this is a non-paradoxical SUBREG, get the value of its operand and
7589 then convert it to the desired mode. If this is a paradoxical SUBREG,
7590 we cannot predict what values the "extra" bits might have. */
7591 if (GET_CODE (x) == SUBREG
7592 && subreg_lowpart_p (x)
7593 && (GET_MODE_SIZE (GET_MODE (x))
7594 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7595 && (value = get_last_value (SUBREG_REG (x))) != 0)
7596 return gen_lowpart_for_combine (GET_MODE (x), value);
7598 if (GET_CODE (x) != REG)
7602 value = reg_last_set_value[regno];
7604 /* If we don't have a value, it isn't for this basic block, or if it was
7605 set in a later insn that the ones we are processing, return 0. */
7608 || (reg_n_sets[regno] != 1
7609 && (reg_last_set_label[regno] != label_tick
7610 || INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)))
7613 /* If the value has all its register valid, return it. */
7614 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
7617 /* Otherwise, make a copy and replace any invalid register with
7618 (clobber (const_int 0)). If that fails for some reason, return 0. */
7620 value = copy_rtx (value);
7621 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
7627 /* Return nonzero if expression X refers to a REG or to memory
7628 that is set in an instruction more recent than FROM_CUID. */
7631 use_crosses_set_p (x, from_cuid)
7637 register enum rtx_code code = GET_CODE (x);
7641 register int regno = REGNO (x);
7642 #ifdef PUSH_ROUNDING
7643 /* Don't allow uses of the stack pointer to be moved,
7644 because we don't know whether the move crosses a push insn. */
7645 if (regno == STACK_POINTER_REGNUM)
7648 return (reg_last_set[regno]
7649 && INSN_CUID (reg_last_set[regno]) > from_cuid);
7652 if (code == MEM && mem_last_set > from_cuid)
7655 fmt = GET_RTX_FORMAT (code);
7657 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7662 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7663 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
7666 else if (fmt[i] == 'e'
7667 && use_crosses_set_p (XEXP (x, i), from_cuid))
7673 /* Define three variables used for communication between the following
7676 static int reg_dead_regno, reg_dead_endregno;
7677 static int reg_dead_flag;
7679 /* Function called via note_stores from reg_dead_at_p.
7681 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7682 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7685 reg_dead_at_p_1 (dest, x)
7689 int regno, endregno;
7691 if (GET_CODE (dest) != REG)
7694 regno = REGNO (dest);
7695 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7696 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
7698 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
7699 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
7702 /* Return non-zero if REG is known to be dead at INSN.
7704 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7705 referencing REG, it is dead. If we hit a SET referencing REG, it is
7706 live. Otherwise, see if it is live or dead at the start of the basic
7710 reg_dead_at_p (reg, insn)
7716 /* Set variables for reg_dead_at_p_1. */
7717 reg_dead_regno = REGNO (reg);
7718 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
7719 ? HARD_REGNO_NREGS (reg_dead_regno,
7725 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7726 beginning of function. */
7727 for (; insn && GET_CODE (insn) != CODE_LABEL;
7728 insn = prev_nonnote_insn (insn))
7730 note_stores (PATTERN (insn), reg_dead_at_p_1);
7732 return reg_dead_flag == 1 ? 1 : 0;
7734 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
7738 /* Get the basic block number that we were in. */
7743 for (block = 0; block < n_basic_blocks; block++)
7744 if (insn == basic_block_head[block])
7747 if (block == n_basic_blocks)
7751 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
7752 if (basic_block_live_at_start[block][i / HOST_BITS_PER_INT]
7753 & (1 << (i % HOST_BITS_PER_INT)))
7759 /* Remove register number REGNO from the dead registers list of INSN.
7761 Return the note used to record the death, if there was one. */
7764 remove_death (regno, insn)
7768 register rtx note = find_regno_note (insn, REG_DEAD, regno);
7771 remove_note (insn, note);
7776 /* For each register (hardware or pseudo) used within expression X, if its
7777 death is in an instruction with cuid between FROM_CUID (inclusive) and
7778 TO_INSN (exclusive), put a REG_DEAD note for that register in the
7779 list headed by PNOTES.
7781 This is done when X is being merged by combination into TO_INSN. These
7782 notes will then be distributed as needed. */
7785 move_deaths (x, from_cuid, to_insn, pnotes)
7792 register int len, i;
7793 register enum rtx_code code = GET_CODE (x);
7797 register int regno = REGNO (x);
7798 register rtx where_dead = reg_last_death[regno];
7800 if (where_dead && INSN_CUID (where_dead) >= from_cuid
7801 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
7803 rtx note = remove_death (regno, reg_last_death[regno]);
7805 /* It is possible for the call above to return 0. This can occur
7806 when reg_last_death points to I2 or I1 that we combined with.
7807 In that case make a new note. */
7811 XEXP (note, 1) = *pnotes;
7815 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
7821 else if (GET_CODE (x) == SET)
7823 rtx dest = SET_DEST (x);
7825 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
7827 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
7828 that accesses one word of a multi-word item, some
7829 piece of everything register in the expression is used by
7830 this insn, so remove any old death. */
7832 if (GET_CODE (dest) == ZERO_EXTRACT
7833 || GET_CODE (dest) == STRICT_LOW_PART
7834 || (GET_CODE (dest) == SUBREG
7835 && (((GET_MODE_SIZE (GET_MODE (dest))
7836 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
7837 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
7838 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
7840 move_deaths (dest, from_cuid, to_insn, pnotes);
7844 /* If this is some other SUBREG, we know it replaces the entire
7845 value, so use that as the destination. */
7846 if (GET_CODE (dest) == SUBREG)
7847 dest = SUBREG_REG (dest);
7849 /* If this is a MEM, adjust deaths of anything used in the address.
7850 For a REG (the only other possibility), the entire value is
7851 being replaced so the old value is not used in this insn. */
7853 if (GET_CODE (dest) == MEM)
7854 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
7858 else if (GET_CODE (x) == CLOBBER)
7861 len = GET_RTX_LENGTH (code);
7862 fmt = GET_RTX_FORMAT (code);
7864 for (i = 0; i < len; i++)
7869 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7870 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
7872 else if (fmt[i] == 'e')
7873 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
7877 /* Return 1 if X is the target of a bit-field assignment in BODY, the
7878 pattern of an insn. X must be a REG. */
7881 reg_bitfield_target_p (x, body)
7887 if (GET_CODE (body) == SET)
7889 rtx dest = SET_DEST (body);
7891 int regno, tregno, endregno, endtregno;
7893 if (GET_CODE (dest) == ZERO_EXTRACT)
7894 target = XEXP (dest, 0);
7895 else if (GET_CODE (dest) == STRICT_LOW_PART)
7896 target = SUBREG_REG (XEXP (dest, 0));
7900 if (GET_CODE (target) == SUBREG)
7901 target = SUBREG_REG (target);
7903 if (GET_CODE (target) != REG)
7906 tregno = REGNO (target), regno = REGNO (x);
7907 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
7910 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
7911 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
7913 return endregno > tregno && regno < endtregno;
7916 else if (GET_CODE (body) == PARALLEL)
7917 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
7918 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
7924 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7925 as appropriate. I3 and I2 are the insns resulting from the combination
7926 insns including FROM (I2 may be zero).
7928 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7929 not need REG_DEAD notes because they are being substituted for. This
7930 saves searching in the most common cases.
7932 Each note in the list is either ignored or placed on some insns, depending
7933 on the type of note. */
7936 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
7940 rtx elim_i2, elim_i1;
7942 rtx note, next_note;
7945 for (note = notes; note; note = next_note)
7947 rtx place = 0, place2 = 0;
7949 /* If this NOTE references a pseudo register, ensure it references
7950 the latest copy of that register. */
7951 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
7952 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
7953 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
7955 next_note = XEXP (note, 1);
7956 switch (REG_NOTE_KIND (note))
7959 /* If this register is set or clobbered in I3, put the note there
7960 unless there is one already. */
7961 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
7963 if (! (GET_CODE (XEXP (note, 0)) == REG
7964 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
7965 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
7968 /* Otherwise, if this register is used by I3, then this register
7969 now dies here, so we must put a REG_DEAD note here unless there
7971 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
7972 && ! (GET_CODE (XEXP (note, 0)) == REG
7973 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
7974 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
7976 PUT_REG_NOTE_KIND (note, REG_DEAD);
7984 /* These notes say something about results of an insn. We can
7985 only support them if they used to be on I3 in which case they
7986 remain on I3. Otherwise they are ignored. */
7987 if (from_insn == i3)
7992 case REG_NO_CONFLICT:
7994 /* These notes say something about how a register is used. They must
7995 be present on any use of the register in I2 or I3. */
7996 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
7999 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
8009 /* It is too much trouble to try to see if this note is still
8010 correct in all situations. It is better to simply delete it. */
8014 /* If the insn previously containing this note still exists,
8015 put it back where it was. Otherwise move it to the previous
8016 insn. Adjust the corresponding REG_LIBCALL note. */
8017 if (GET_CODE (from_insn) != NOTE)
8021 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, 0);
8022 place = prev_real_insn (from_insn);
8024 XEXP (tem, 0) = place;
8029 /* This is handled similarly to REG_RETVAL. */
8030 if (GET_CODE (from_insn) != NOTE)
8034 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, 0);
8035 place = next_real_insn (from_insn);
8037 XEXP (tem, 0) = place;
8042 /* If the register is used as an input in I3, it dies there.
8043 Similarly for I2, if it is non-zero and adjacent to I3.
8045 If the register is not used as an input in either I3 or I2
8046 and it is not one of the registers we were supposed to eliminate,
8047 there are two possibilities. We might have a non-adjacent I2
8048 or we might have somehow eliminated an additional register
8049 from a computation. For example, we might have had A & B where
8050 we discover that B will always be zero. In this case we will
8051 eliminate the reference to A.
8053 In both cases, we must search to see if we can find a previous
8054 use of A and put the death note there. */
8056 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
8058 else if (i2 != 0 && next_nonnote_insn (i2) == i3
8059 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
8062 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
8066 for (tem = prev_nonnote_insn (i3);
8067 tem && (GET_CODE (tem) == INSN
8068 || GET_CODE (tem) == CALL_INSN);
8069 tem = prev_nonnote_insn (tem))
8071 /* If the register is being set at TEM, see if that is all
8072 TEM is doing. If so, delete TEM. Otherwise, make this
8073 into a REG_UNUSED note instead. */
8074 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
8076 rtx set = single_set (tem);
8078 /* Verify that it was the set, and not a clobber that
8079 modified the register. */
8081 if (set != 0 && ! side_effects_p (SET_SRC (set))
8082 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
8084 /* Move the notes and links of TEM elsewhere.
8085 This might delete other dead insns recursively.
8086 First set the pattern to something that won't use
8089 PATTERN (tem) = pc_rtx;
8091 distribute_notes (REG_NOTES (tem), tem, tem, 0, 0, 0);
8092 distribute_links (LOG_LINKS (tem));
8094 PUT_CODE (tem, NOTE);
8095 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
8096 NOTE_SOURCE_FILE (tem) = 0;
8100 PUT_REG_NOTE_KIND (note, REG_UNUSED);
8102 /* If there isn't already a REG_UNUSED note, put one
8104 if (! find_regno_note (tem, REG_UNUSED,
8105 REGNO (XEXP (note, 0))))
8110 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
8117 /* If the register is set or already dead at PLACE, we needn't do
8118 anything with this note if it is still a REG_DEAD note.
8120 Note that we cannot use just `dead_or_set_p' here since we can
8121 convert an assignment to a register into a bit-field assignment.
8122 Therefore, we must also omit the note if the register is the
8123 target of a bitfield assignment. */
8125 if (place && REG_NOTE_KIND (note) == REG_DEAD)
8127 int regno = REGNO (XEXP (note, 0));
8129 if (dead_or_set_p (place, XEXP (note, 0))
8130 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
8132 /* Unless the register previously died in PLACE, clear
8133 reg_last_death. [I no longer understand why this is
8135 if (reg_last_death[regno] != place)
8136 reg_last_death[regno] = 0;
8140 reg_last_death[regno] = place;
8142 /* If this is a death note for a hard reg that is occupying
8143 multiple registers, ensure that we are still using all
8144 parts of the object. If we find a piece of the object
8145 that is unused, we must add a USE for that piece before
8146 PLACE and put the appropriate REG_DEAD note on it.
8148 An alternative would be to put a REG_UNUSED for the pieces
8149 on the insn that set the register, but that can't be done if
8150 it is not in the same block. It is simpler, though less
8151 efficient, to add the USE insns. */
8153 if (place && regno < FIRST_PSEUDO_REGISTER
8154 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
8157 = regno + HARD_REGNO_NREGS (regno,
8158 GET_MODE (XEXP (note, 0)));
8162 for (i = regno; i < endregno; i++)
8163 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
8165 rtx piece = gen_rtx (REG, word_mode, i);
8168 /* See if we already placed a USE note for this
8169 register in front of PLACE. */
8171 GET_CODE (PREV_INSN (p)) == INSN
8172 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
8174 if (rtx_equal_p (piece,
8175 XEXP (PATTERN (PREV_INSN (p)), 0)))
8184 = emit_insn_before (gen_rtx (USE, VOIDmode,
8187 REG_NOTES (use_insn)
8188 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
8189 REG_NOTES (use_insn));
8197 /* Put only REG_DEAD notes for pieces that are
8198 still used and that are not already dead or set. */
8200 for (i = regno; i < endregno; i++)
8202 rtx piece = gen_rtx (REG, word_mode, i);
8204 if (reg_referenced_p (piece, PATTERN (place))
8205 && ! dead_or_set_p (place, piece)
8206 && ! reg_bitfield_target_p (piece,
8208 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
8220 /* Any other notes should not be present at this point in the
8227 XEXP (note, 1) = REG_NOTES (place);
8228 REG_NOTES (place) = note;
8232 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
8233 XEXP (note, 0), REG_NOTES (place2));
8237 /* Similarly to above, distribute the LOG_LINKS that used to be present on
8238 I3, I2, and I1 to new locations. This is also called in one case to
8239 add a link pointing at I3 when I3's destination is changed. */
8242 distribute_links (links)
8245 rtx link, next_link;
8247 for (link = links; link; link = next_link)
8253 next_link = XEXP (link, 1);
8255 /* If the insn that this link points to is a NOTE or isn't a single
8256 set, ignore it. In the latter case, it isn't clear what we
8257 can do other than ignore the link, since we can't tell which
8258 register it was for. Such links wouldn't be used by combine
8261 It is not possible for the destination of the target of the link to
8262 have been changed by combine. The only potential of this is if we
8263 replace I3, I2, and I1 by I3 and I2. But in that case the
8264 destination of I2 also remains unchanged. */
8266 if (GET_CODE (XEXP (link, 0)) == NOTE
8267 || (set = single_set (XEXP (link, 0))) == 0)
8270 reg = SET_DEST (set);
8271 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
8272 || GET_CODE (reg) == SIGN_EXTRACT
8273 || GET_CODE (reg) == STRICT_LOW_PART)
8274 reg = XEXP (reg, 0);
8276 /* A LOG_LINK is defined as being placed on the first insn that uses
8277 a register and points to the insn that sets the register. Start
8278 searching at the next insn after the target of the link and stop
8279 when we reach a set of the register or the end of the basic block.
8281 Note that this correctly handles the link that used to point from
8282 I3 to I2. Also note that not much searching is typically done here
8283 since most links don't point very far away. */
8285 for (insn = NEXT_INSN (XEXP (link, 0));
8286 (insn && GET_CODE (insn) != CODE_LABEL
8287 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
8288 insn = NEXT_INSN (insn))
8289 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8290 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8292 if (reg_referenced_p (reg, PATTERN (insn)))
8297 /* If we found a place to put the link, place it there unless there
8298 is already a link to the same insn as LINK at that point. */
8304 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
8305 if (XEXP (link2, 0) == XEXP (link, 0))
8310 XEXP (link, 1) = LOG_LINKS (place);
8311 LOG_LINKS (place) = link;
8318 dump_combine_stats (file)
8323 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8324 combine_attempts, combine_merges, combine_extras, combine_successes);
8328 dump_combine_total_stats (file)
8333 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8334 total_attempts, total_merges, total_extras, total_successes);
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