1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
97 #ifndef ACCUMULATE_OUTGOING_ARGS
98 #define ACCUMULATE_OUTGOING_ARGS 0
101 /* Supply a default definition for PUSH_ARGS. */
104 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
110 /* It is not safe to use ordinary gen_lowpart in combine.
111 Use gen_lowpart_for_combine instead. See comments there. */
112 #define gen_lowpart dont_use_gen_lowpart_you_dummy
114 /* Number of attempts to combine instructions in this function. */
116 static int combine_attempts;
118 /* Number of attempts that got as far as substitution in this function. */
120 static int combine_merges;
122 /* Number of instructions combined with added SETs in this function. */
124 static int combine_extras;
126 /* Number of instructions combined in this function. */
128 static int combine_successes;
130 /* Totals over entire compilation. */
132 static int total_attempts, total_merges, total_extras, total_successes;
134 /* Define a default value for REVERSIBLE_CC_MODE.
135 We can never assume that a condition code mode is safe to reverse unless
136 the md tells us so. */
137 #ifndef REVERSIBLE_CC_MODE
138 #define REVERSIBLE_CC_MODE(MODE) 0
141 /* Vector mapping INSN_UIDs to cuids.
142 The cuids are like uids but increase monotonically always.
143 Combine always uses cuids so that it can compare them.
144 But actually renumbering the uids, which we used to do,
145 proves to be a bad idea because it makes it hard to compare
146 the dumps produced by earlier passes with those from later passes. */
148 static int *uid_cuid;
149 static int max_uid_cuid;
151 /* Get the cuid of an insn. */
153 #define INSN_CUID(INSN) \
154 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
156 /* Maximum register number, which is the size of the tables below. */
158 static unsigned int combine_max_regno;
160 /* Record last point of death of (hard or pseudo) register n. */
162 static rtx *reg_last_death;
164 /* Record last point of modification of (hard or pseudo) register n. */
166 static rtx *reg_last_set;
168 /* Record the cuid of the last insn that invalidated memory
169 (anything that writes memory, and subroutine calls, but not pushes). */
171 static int mem_last_set;
173 /* Record the cuid of the last CALL_INSN
174 so we can tell whether a potential combination crosses any calls. */
176 static int last_call_cuid;
178 /* When `subst' is called, this is the insn that is being modified
179 (by combining in a previous insn). The PATTERN of this insn
180 is still the old pattern partially modified and it should not be
181 looked at, but this may be used to examine the successors of the insn
182 to judge whether a simplification is valid. */
184 static rtx subst_insn;
186 /* This is an insn that belongs before subst_insn, but is not currently
187 on the insn chain. */
189 static rtx subst_prev_insn;
191 /* This is the lowest CUID that `subst' is currently dealing with.
192 get_last_value will not return a value if the register was set at or
193 after this CUID. If not for this mechanism, we could get confused if
194 I2 or I1 in try_combine were an insn that used the old value of a register
195 to obtain a new value. In that case, we might erroneously get the
196 new value of the register when we wanted the old one. */
198 static int subst_low_cuid;
200 /* This contains any hard registers that are used in newpat; reg_dead_at_p
201 must consider all these registers to be always live. */
203 static HARD_REG_SET newpat_used_regs;
205 /* This is an insn to which a LOG_LINKS entry has been added. If this
206 insn is the earlier than I2 or I3, combine should rescan starting at
209 static rtx added_links_insn;
211 /* Basic block number of the block in which we are performing combines. */
212 static int this_basic_block;
214 /* A bitmap indicating which blocks had registers go dead at entry.
215 After combine, we'll need to re-do global life analysis with
216 those blocks as starting points. */
217 static sbitmap refresh_blocks;
218 static int need_refresh;
220 /* The next group of arrays allows the recording of the last value assigned
221 to (hard or pseudo) register n. We use this information to see if a
222 operation being processed is redundant given a prior operation performed
223 on the register. For example, an `and' with a constant is redundant if
224 all the zero bits are already known to be turned off.
226 We use an approach similar to that used by cse, but change it in the
229 (1) We do not want to reinitialize at each label.
230 (2) It is useful, but not critical, to know the actual value assigned
231 to a register. Often just its form is helpful.
233 Therefore, we maintain the following arrays:
235 reg_last_set_value the last value assigned
236 reg_last_set_label records the value of label_tick when the
237 register was assigned
238 reg_last_set_table_tick records the value of label_tick when a
239 value using the register is assigned
240 reg_last_set_invalid set to non-zero when it is not valid
241 to use the value of this register in some
244 To understand the usage of these tables, it is important to understand
245 the distinction between the value in reg_last_set_value being valid
246 and the register being validly contained in some other expression in the
249 Entry I in reg_last_set_value is valid if it is non-zero, and either
250 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
252 Register I may validly appear in any expression returned for the value
253 of another register if reg_n_sets[i] is 1. It may also appear in the
254 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
255 reg_last_set_invalid[j] is zero.
257 If an expression is found in the table containing a register which may
258 not validly appear in an expression, the register is replaced by
259 something that won't match, (clobber (const_int 0)).
261 reg_last_set_invalid[i] is set non-zero when register I is being assigned
262 to and reg_last_set_table_tick[i] == label_tick. */
264 /* Record last value assigned to (hard or pseudo) register n. */
266 static rtx *reg_last_set_value;
268 /* Record the value of label_tick when the value for register n is placed in
269 reg_last_set_value[n]. */
271 static int *reg_last_set_label;
273 /* Record the value of label_tick when an expression involving register n
274 is placed in reg_last_set_value. */
276 static int *reg_last_set_table_tick;
278 /* Set non-zero if references to register n in expressions should not be
281 static char *reg_last_set_invalid;
283 /* Incremented for each label. */
285 static int label_tick;
287 /* Some registers that are set more than once and used in more than one
288 basic block are nevertheless always set in similar ways. For example,
289 a QImode register may be loaded from memory in two places on a machine
290 where byte loads zero extend.
292 We record in the following array what we know about the nonzero
293 bits of a register, specifically which bits are known to be zero.
295 If an entry is zero, it means that we don't know anything special. */
297 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
299 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
300 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
302 static enum machine_mode nonzero_bits_mode;
304 /* Nonzero if we know that a register has some leading bits that are always
305 equal to the sign bit. */
307 static unsigned char *reg_sign_bit_copies;
309 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
310 It is zero while computing them and after combine has completed. This
311 former test prevents propagating values based on previously set values,
312 which can be incorrect if a variable is modified in a loop. */
314 static int nonzero_sign_valid;
316 /* These arrays are maintained in parallel with reg_last_set_value
317 and are used to store the mode in which the register was last set,
318 the bits that were known to be zero when it was last set, and the
319 number of sign bits copies it was known to have when it was last set. */
321 static enum machine_mode *reg_last_set_mode;
322 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
323 static char *reg_last_set_sign_bit_copies;
325 /* Record one modification to rtl structure
326 to be undone by storing old_contents into *where.
327 is_int is 1 if the contents are an int. */
333 union {rtx r; int i;} old_contents;
334 union {rtx *r; int *i;} where;
337 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
338 num_undo says how many are currently recorded.
340 storage is nonzero if we must undo the allocation of new storage.
341 The value of storage is what to pass to obfree.
343 other_insn is nonzero if we have modified some other insn in the process
344 of working on subst_insn. It must be verified too.
346 previous_undos is the value of undobuf.undos when we started processing
347 this substitution. This will prevent gen_rtx_combine from re-used a piece
348 from the previous expression. Doing so can produce circular rtl
356 struct undo *previous_undos;
360 static struct undobuf undobuf;
362 /* Number of times the pseudo being substituted for
363 was found and replaced. */
365 static int n_occurrences;
367 static void do_SUBST PARAMS ((rtx *, rtx));
368 static void do_SUBST_INT PARAMS ((int *, int));
369 static void init_reg_last_arrays PARAMS ((void));
370 static void setup_incoming_promotions PARAMS ((void));
371 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
372 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
373 static int sets_function_arg_p PARAMS ((rtx));
374 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
375 static int contains_muldiv PARAMS ((rtx));
376 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
377 static void undo_all PARAMS ((void));
378 static void undo_commit PARAMS ((void));
379 static rtx *find_split_point PARAMS ((rtx *, rtx));
380 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
381 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
382 static rtx simplify_if_then_else PARAMS ((rtx));
383 static rtx simplify_set PARAMS ((rtx));
384 static rtx simplify_logical PARAMS ((rtx, int));
385 static rtx expand_compound_operation PARAMS ((rtx));
386 static rtx expand_field_assignment PARAMS ((rtx));
387 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
388 rtx, unsigned HOST_WIDE_INT, int,
390 static rtx extract_left_shift PARAMS ((rtx, int));
391 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
392 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
393 unsigned HOST_WIDE_INT *));
394 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
395 unsigned HOST_WIDE_INT, rtx, int));
396 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
397 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
398 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
399 static rtx make_field_assignment PARAMS ((rtx));
400 static rtx apply_distributive_law PARAMS ((rtx));
401 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
402 unsigned HOST_WIDE_INT));
403 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
404 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
405 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
406 enum rtx_code, HOST_WIDE_INT,
407 enum machine_mode, int *));
408 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
410 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
411 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
412 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
414 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
416 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
417 enum machine_mode, rtx));
418 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
419 static int reversible_comparison_p PARAMS ((rtx));
420 static void update_table_tick PARAMS ((rtx));
421 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
422 static void check_promoted_subreg PARAMS ((rtx, rtx));
423 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
424 static void record_dead_and_set_regs PARAMS ((rtx));
425 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
426 static rtx get_last_value PARAMS ((rtx));
427 static int use_crosses_set_p PARAMS ((rtx, int));
428 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
429 static int reg_dead_at_p PARAMS ((rtx, rtx));
430 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
431 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
432 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
433 static void distribute_links PARAMS ((rtx));
434 static void mark_used_regs_combine PARAMS ((rtx));
435 static int insn_cuid PARAMS ((rtx));
436 static void record_promoted_value PARAMS ((rtx, rtx));
438 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
439 insn. The substitution can be undone by undo_all. If INTO is already
440 set to NEWVAL, do not record this change. Because computing NEWVAL might
441 also call SUBST, we have to compute it before we put anything into
445 do_SUBST (into, newval)
451 if (oldval == newval)
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
508 register rtx insn, next;
513 register rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in persuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, XEXP (links, 0),
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
745 compute_bb_for_insn (get_max_uid ());
746 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
751 sbitmap_free (refresh_blocks);
752 free (reg_nonzero_bits);
753 free (reg_sign_bit_copies);
754 free (reg_last_death);
756 free (reg_last_set_value);
757 free (reg_last_set_table_tick);
758 free (reg_last_set_label);
759 free (reg_last_set_invalid);
760 free (reg_last_set_mode);
761 free (reg_last_set_nonzero_bits);
762 free (reg_last_set_sign_bit_copies);
766 struct undo *undo, *next;
767 for (undo = undobuf.frees; undo; undo = next)
775 total_attempts += combine_attempts;
776 total_merges += combine_merges;
777 total_extras += combine_extras;
778 total_successes += combine_successes;
780 nonzero_sign_valid = 0;
782 /* Make recognizer allow volatile MEMs again. */
785 return new_direct_jump_p;
788 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
791 init_reg_last_arrays ()
793 unsigned int nregs = combine_max_regno;
795 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
796 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
797 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
798 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
799 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
800 bzero (reg_last_set_invalid, nregs * sizeof (char));
801 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
802 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
803 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
806 /* Set up any promoted values for incoming argument registers. */
809 setup_incoming_promotions ()
811 #ifdef PROMOTE_FUNCTION_ARGS
814 enum machine_mode mode;
816 rtx first = get_insns ();
818 #ifndef OUTGOING_REGNO
819 #define OUTGOING_REGNO(N) N
821 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
822 /* Check whether this register can hold an incoming pointer
823 argument. FUNCTION_ARG_REGNO_P tests outgoing register
824 numbers, so translate if necessary due to register windows. */
825 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
826 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
829 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
832 gen_rtx_CLOBBER (mode, const0_rtx)));
837 /* Called via note_stores. If X is a pseudo that is narrower than
838 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
840 If we are setting only a portion of X and we can't figure out what
841 portion, assume all bits will be used since we don't know what will
844 Similarly, set how many bits of X are known to be copies of the sign bit
845 at all locations in the function. This is the smallest number implied
849 set_nonzero_bits_and_sign_copies (x, set, data)
852 void *data ATTRIBUTE_UNUSED;
856 if (GET_CODE (x) == REG
857 && REGNO (x) >= FIRST_PSEUDO_REGISTER
858 /* If this register is undefined at the start of the file, we can't
859 say what its contents were. */
860 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
861 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
863 if (set == 0 || GET_CODE (set) == CLOBBER)
865 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
866 reg_sign_bit_copies[REGNO (x)] = 1;
870 /* If this is a complex assignment, see if we can convert it into a
871 simple assignment. */
872 set = expand_field_assignment (set);
874 /* If this is a simple assignment, or we have a paradoxical SUBREG,
875 set what we know about X. */
877 if (SET_DEST (set) == x
878 || (GET_CODE (SET_DEST (set)) == SUBREG
879 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
880 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
881 && SUBREG_REG (SET_DEST (set)) == x))
883 rtx src = SET_SRC (set);
885 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
886 /* If X is narrower than a word and SRC is a non-negative
887 constant that would appear negative in the mode of X,
888 sign-extend it for use in reg_nonzero_bits because some
889 machines (maybe most) will actually do the sign-extension
890 and this is the conservative approach.
892 ??? For 2.5, try to tighten up the MD files in this regard
893 instead of this kludge. */
895 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
896 && GET_CODE (src) == CONST_INT
898 && 0 != (INTVAL (src)
900 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
901 src = GEN_INT (INTVAL (src)
902 | ((HOST_WIDE_INT) (-1)
903 << GET_MODE_BITSIZE (GET_MODE (x))));
906 reg_nonzero_bits[REGNO (x)]
907 |= nonzero_bits (src, nonzero_bits_mode);
908 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
909 if (reg_sign_bit_copies[REGNO (x)] == 0
910 || reg_sign_bit_copies[REGNO (x)] > num)
911 reg_sign_bit_copies[REGNO (x)] = num;
915 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
916 reg_sign_bit_copies[REGNO (x)] = 1;
921 /* See if INSN can be combined into I3. PRED and SUCC are optionally
922 insns that were previously combined into I3 or that will be combined
923 into the merger of INSN and I3.
925 Return 0 if the combination is not allowed for any reason.
927 If the combination is allowed, *PDEST will be set to the single
928 destination of INSN and *PSRC to the single source, and this function
932 can_combine_p (insn, i3, pred, succ, pdest, psrc)
935 rtx pred ATTRIBUTE_UNUSED;
940 rtx set = 0, src, dest;
945 int all_adjacent = (succ ? (next_active_insn (insn) == succ
946 && next_active_insn (succ) == i3)
947 : next_active_insn (insn) == i3);
949 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
950 or a PARALLEL consisting of such a SET and CLOBBERs.
952 If INSN has CLOBBER parallel parts, ignore them for our processing.
953 By definition, these happen during the execution of the insn. When it
954 is merged with another insn, all bets are off. If they are, in fact,
955 needed and aren't also supplied in I3, they may be added by
956 recog_for_combine. Otherwise, it won't match.
958 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
961 Get the source and destination of INSN. If more than one, can't
964 if (GET_CODE (PATTERN (insn)) == SET)
965 set = PATTERN (insn);
966 else if (GET_CODE (PATTERN (insn)) == PARALLEL
967 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
969 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
971 rtx elt = XVECEXP (PATTERN (insn), 0, i);
973 switch (GET_CODE (elt))
975 /* This is important to combine floating point insns
978 /* Combining an isolated USE doesn't make sense.
979 We depend here on combinable_i3_pat to reject them. */
980 /* The code below this loop only verifies that the inputs of
981 the SET in INSN do not change. We call reg_set_between_p
982 to verify that the REG in the USE does not change betweeen
984 If the USE in INSN was for a pseudo register, the matching
985 insn pattern will likely match any register; combining this
986 with any other USE would only be safe if we knew that the
987 used registers have identical values, or if there was
988 something to tell them apart, e.g. different modes. For
989 now, we forgo such compilcated tests and simply disallow
990 combining of USES of pseudo registers with any other USE. */
991 if (GET_CODE (XEXP (elt, 0)) == REG
992 && GET_CODE (PATTERN (i3)) == PARALLEL)
994 rtx i3pat = PATTERN (i3);
995 int i = XVECLEN (i3pat, 0) - 1;
996 unsigned int regno = REGNO (XEXP (elt, 0));
1000 rtx i3elt = XVECEXP (i3pat, 0, i);
1002 if (GET_CODE (i3elt) == USE
1003 && GET_CODE (XEXP (i3elt, 0)) == REG
1004 && (REGNO (XEXP (i3elt, 0)) == regno
1005 ? reg_set_between_p (XEXP (elt, 0),
1006 PREV_INSN (insn), i3)
1007 : regno >= FIRST_PSEUDO_REGISTER))
1014 /* We can ignore CLOBBERs. */
1019 /* Ignore SETs whose result isn't used but not those that
1020 have side-effects. */
1021 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1022 && ! side_effects_p (elt))
1025 /* If we have already found a SET, this is a second one and
1026 so we cannot combine with this insn. */
1034 /* Anything else means we can't combine. */
1040 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1041 so don't do anything with it. */
1042 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1051 set = expand_field_assignment (set);
1052 src = SET_SRC (set), dest = SET_DEST (set);
1054 /* Don't eliminate a store in the stack pointer. */
1055 if (dest == stack_pointer_rtx
1056 /* If we couldn't eliminate a field assignment, we can't combine. */
1057 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1058 /* Don't combine with an insn that sets a register to itself if it has
1059 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1060 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1061 /* Can't merge a function call. */
1062 || GET_CODE (src) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3) == CALL_INSN
1065 && (find_reg_fusage (i3, USE, dest)
1066 || (GET_CODE (dest) == REG
1067 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1068 && global_regs[REGNO (dest)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3, dest)
1071 || (succ && FIND_REG_INC_NOTE (succ, dest))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ && ! all_adjacent
1082 && reg_used_between_p (dest, succ, i3))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src) != MEM
1094 || ! find_reg_note (insn, REG_EQUIV, src))
1095 && use_crosses_set_p (src, INSN_CUID (insn)))
1096 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1097 || GET_CODE (src) == UNSPEC_VOLATILE))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1101 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest) == REG)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 This is the same test done in can_combine except that we don't test
1123 if SRC is a CALL operation to permit a hard register with
1124 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1139 || (SMALL_REGISTER_CLASSES
1140 && ((! all_adjacent && ! REG_USERVAR_P (src))
1141 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1142 && ! REG_USERVAR_P (src))))))))
1145 else if (GET_CODE (dest) != CC0)
1148 /* Don't substitute for a register intended as a clobberable operand.
1149 Similarly, don't substitute an expression containing a register that
1150 will be clobbered in I3. */
1151 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1152 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1153 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1154 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1156 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1159 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1160 or not), reject, unless nothing volatile comes between it and I3 */
1162 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1164 /* Make sure succ doesn't contain a volatile reference. */
1165 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1168 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1169 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1173 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1174 to be an explicit register variable, and was chosen for a reason. */
1176 if (GET_CODE (src) == ASM_OPERANDS
1177 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1180 /* If there are any volatile insns between INSN and I3, reject, because
1181 they might affect machine state. */
1183 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1184 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1187 /* If INSN or I2 contains an autoincrement or autodecrement,
1188 make sure that register is not used between there and I3,
1189 and not already used in I3 either.
1190 Also insist that I3 not be a jump; if it were one
1191 and the incremented register were spilled, we would lose. */
1194 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1195 if (REG_NOTE_KIND (link) == REG_INC
1196 && (GET_CODE (i3) == JUMP_INSN
1197 || reg_used_between_p (XEXP (link, 0), insn, i3)
1198 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1203 /* Don't combine an insn that follows a CC0-setting insn.
1204 An insn that uses CC0 must not be separated from the one that sets it.
1205 We do, however, allow I2 to follow a CC0-setting insn if that insn
1206 is passed as I1; in that case it will be deleted also.
1207 We also allow combining in this case if all the insns are adjacent
1208 because that would leave the two CC0 insns adjacent as well.
1209 It would be more logical to test whether CC0 occurs inside I1 or I2,
1210 but that would be much slower, and this ought to be equivalent. */
1212 p = prev_nonnote_insn (insn);
1213 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1218 /* If we get here, we have passed all the tests and the combination is
1227 /* Check if PAT is an insn - or a part of it - used to set up an
1228 argument for a function in a hard register. */
1231 sets_function_arg_p (pat)
1237 switch (GET_CODE (pat))
1240 return sets_function_arg_p (PATTERN (pat));
1243 for (i = XVECLEN (pat, 0); --i >= 0;)
1244 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1250 inner_dest = SET_DEST (pat);
1251 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1252 || GET_CODE (inner_dest) == SUBREG
1253 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1254 inner_dest = XEXP (inner_dest, 0);
1256 return (GET_CODE (inner_dest) == REG
1257 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1258 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1267 /* LOC is the location within I3 that contains its pattern or the component
1268 of a PARALLEL of the pattern. We validate that it is valid for combining.
1270 One problem is if I3 modifies its output, as opposed to replacing it
1271 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1272 so would produce an insn that is not equivalent to the original insns.
1276 (set (reg:DI 101) (reg:DI 100))
1277 (set (subreg:SI (reg:DI 101) 0) <foo>)
1279 This is NOT equivalent to:
1281 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1282 (set (reg:DI 101) (reg:DI 100))])
1284 Not only does this modify 100 (in which case it might still be valid
1285 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1287 We can also run into a problem if I2 sets a register that I1
1288 uses and I1 gets directly substituted into I3 (not via I2). In that
1289 case, we would be getting the wrong value of I2DEST into I3, so we
1290 must reject the combination. This case occurs when I2 and I1 both
1291 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1292 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1293 of a SET must prevent combination from occurring.
1295 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1296 if the destination of a SET is a hard register that isn't a user
1299 Before doing the above check, we first try to expand a field assignment
1300 into a set of logical operations.
1302 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1303 we place a register that is both set and used within I3. If more than one
1304 such register is detected, we fail.
1306 Return 1 if the combination is valid, zero otherwise. */
1309 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1315 rtx *pi3dest_killed;
1319 if (GET_CODE (x) == SET)
1321 rtx set = expand_field_assignment (x);
1322 rtx dest = SET_DEST (set);
1323 rtx src = SET_SRC (set);
1324 rtx inner_dest = dest;
1327 rtx inner_src = src;
1332 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1333 || GET_CODE (inner_dest) == SUBREG
1334 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1335 inner_dest = XEXP (inner_dest, 0);
1337 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1340 while (GET_CODE (inner_src) == STRICT_LOW_PART
1341 || GET_CODE (inner_src) == SUBREG
1342 || GET_CODE (inner_src) == ZERO_EXTRACT)
1343 inner_src = XEXP (inner_src, 0);
1345 /* If it is better that two different modes keep two different pseudos,
1346 avoid combining them. This avoids producing the following pattern
1348 (set (subreg:SI (reg/v:QI 21) 0)
1349 (lshiftrt:SI (reg/v:SI 20)
1351 If that were made, reload could not handle the pair of
1352 reg 20/21, since it would try to get any GENERAL_REGS
1353 but some of them don't handle QImode. */
1355 if (rtx_equal_p (inner_src, i2dest)
1356 && GET_CODE (inner_dest) == REG
1357 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1361 /* Check for the case where I3 modifies its output, as
1363 if ((inner_dest != dest
1364 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1365 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1367 /* This is the same test done in can_combine_p except that we
1368 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1369 CALL operation. Moreover, we can't test all_adjacent; we don't
1370 have to, since this instruction will stay in place, thus we are
1371 not considering increasing the lifetime of INNER_DEST.
1373 Also, if this insn sets a function argument, combining it with
1374 something that might need a spill could clobber a previous
1375 function argument; the all_adjacent test in can_combine_p also
1376 checks this; here, we do a more specific test for this case. */
1378 || (GET_CODE (inner_dest) == REG
1379 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1380 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1381 GET_MODE (inner_dest))
1382 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1383 && ! REG_USERVAR_P (inner_dest)
1384 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1385 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1387 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1388 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1391 /* If DEST is used in I3, it is being killed in this insn,
1392 so record that for later.
1393 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1394 STACK_POINTER_REGNUM, since these are always considered to be
1395 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1396 if (pi3dest_killed && GET_CODE (dest) == REG
1397 && reg_referenced_p (dest, PATTERN (i3))
1398 && REGNO (dest) != FRAME_POINTER_REGNUM
1399 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1400 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1402 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1403 && (REGNO (dest) != ARG_POINTER_REGNUM
1404 || ! fixed_regs [REGNO (dest)])
1406 && REGNO (dest) != STACK_POINTER_REGNUM)
1408 if (*pi3dest_killed)
1411 *pi3dest_killed = dest;
1415 else if (GET_CODE (x) == PARALLEL)
1419 for (i = 0; i < XVECLEN (x, 0); i++)
1420 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1421 i1_not_in_src, pi3dest_killed))
1428 /* Return 1 if X is an arithmetic expression that contains a multiplication
1429 and division. We don't count multiplications by powers of two here. */
1435 switch (GET_CODE (x))
1437 case MOD: case DIV: case UMOD: case UDIV:
1441 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1442 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1444 switch (GET_RTX_CLASS (GET_CODE (x)))
1446 case 'c': case '<': case '2':
1447 return contains_muldiv (XEXP (x, 0))
1448 || contains_muldiv (XEXP (x, 1));
1451 return contains_muldiv (XEXP (x, 0));
1459 /* Try to combine the insns I1 and I2 into I3.
1460 Here I1 and I2 appear earlier than I3.
1461 I1 can be zero; then we combine just I2 into I3.
1463 It we are combining three insns and the resulting insn is not recognized,
1464 try splitting it into two insns. If that happens, I2 and I3 are retained
1465 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1468 Return 0 if the combination does not work. Then nothing is changed.
1469 If we did the combination, return the insn at which combine should
1472 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1473 new direct jump instruction. */
1476 try_combine (i3, i2, i1, new_direct_jump_p)
1477 register rtx i3, i2, i1;
1478 register int *new_direct_jump_p;
1480 /* New patterns for I3 and I2, respectively. */
1481 rtx newpat, newi2pat = 0;
1482 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1483 int added_sets_1, added_sets_2;
1484 /* Total number of SETs to put into I3. */
1486 /* Nonzero is I2's body now appears in I3. */
1488 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1489 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1490 /* Contains I3 if the destination of I3 is used in its source, which means
1491 that the old life of I3 is being killed. If that usage is placed into
1492 I2 and not in I3, a REG_DEAD note must be made. */
1493 rtx i3dest_killed = 0;
1494 /* SET_DEST and SET_SRC of I2 and I1. */
1495 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1496 /* PATTERN (I2), or a copy of it in certain cases. */
1498 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1499 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1500 int i1_feeds_i3 = 0;
1501 /* Notes that must be added to REG_NOTES in I3 and I2. */
1502 rtx new_i3_notes, new_i2_notes;
1503 /* Notes that we substituted I3 into I2 instead of the normal case. */
1504 int i3_subst_into_i2 = 0;
1505 /* Notes that I1, I2 or I3 is a MULT operation. */
1513 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1514 This can occur when flow deletes an insn that it has merged into an
1515 auto-increment address. We also can't do anything if I3 has a
1516 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1519 if (! INSN_P (i3) || ! INSN_P (i2) || (i1 && ! INSN_P (i1))
1521 /* ??? This gives worse code, and appears to be unnecessary, since no
1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1523 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1529 undobuf.other_insn = 0;
1531 /* Save the current high-water-mark so we can free storage if we didn't
1532 accept this combination. */
1533 undobuf.storage = (char *) oballoc (0);
1535 /* Reset the hard register usage information. */
1536 CLEAR_HARD_REG_SET (newpat_used_regs);
1538 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1539 code below, set I1 to be the earlier of the two insns. */
1540 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1541 temp = i1, i1 = i2, i2 = temp;
1543 added_links_insn = 0;
1545 /* First check for one important special-case that the code below will
1546 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1547 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1548 we may be able to replace that destination with the destination of I3.
1549 This occurs in the common code where we compute both a quotient and
1550 remainder into a structure, in which case we want to do the computation
1551 directly into the structure to avoid register-register copies.
1553 We make very conservative checks below and only try to handle the
1554 most common cases of this. For example, we only handle the case
1555 where I2 and I3 are adjacent to avoid making difficult register
1558 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1560 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1561 && (! SMALL_REGISTER_CLASSES
1562 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1563 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1564 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1565 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1566 && GET_CODE (PATTERN (i2)) == PARALLEL
1567 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1568 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1569 below would need to check what is inside (and reg_overlap_mentioned_p
1570 doesn't support those codes anyway). Don't allow those destinations;
1571 the resulting insn isn't likely to be recognized anyway. */
1572 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1573 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1574 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1575 SET_DEST (PATTERN (i3)))
1576 && next_real_insn (i2) == i3)
1578 rtx p2 = PATTERN (i2);
1580 /* Make sure that the destination of I3,
1581 which we are going to substitute into one output of I2,
1582 is not used within another output of I2. We must avoid making this:
1583 (parallel [(set (mem (reg 69)) ...)
1584 (set (reg 69) ...)])
1585 which is not well-defined as to order of actions.
1586 (Besides, reload can't handle output reloads for this.)
1588 The problem can also happen if the dest of I3 is a memory ref,
1589 if another dest in I2 is an indirect memory ref. */
1590 for (i = 0; i < XVECLEN (p2, 0); i++)
1591 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1592 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1593 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1594 SET_DEST (XVECEXP (p2, 0, i))))
1597 if (i == XVECLEN (p2, 0))
1598 for (i = 0; i < XVECLEN (p2, 0); i++)
1599 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1600 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1601 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1606 subst_low_cuid = INSN_CUID (i2);
1608 added_sets_2 = added_sets_1 = 0;
1609 i2dest = SET_SRC (PATTERN (i3));
1611 /* Replace the dest in I2 with our dest and make the resulting
1612 insn the new pattern for I3. Then skip to where we
1613 validate the pattern. Everything was set up above. */
1614 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1615 SET_DEST (PATTERN (i3)));
1618 i3_subst_into_i2 = 1;
1619 goto validate_replacement;
1623 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1624 one of those words to another constant, merge them by making a new
1627 && (temp = single_set (i2)) != 0
1628 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1629 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1630 && GET_CODE (SET_DEST (temp)) == REG
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1633 && GET_CODE (PATTERN (i3)) == SET
1634 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1635 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1636 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1637 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1638 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1640 HOST_WIDE_INT lo, hi;
1642 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1643 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1646 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1647 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1650 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1651 lo = INTVAL (SET_SRC (PATTERN (i3)));
1653 hi = INTVAL (SET_SRC (PATTERN (i3)));
1657 subst_low_cuid = INSN_CUID (i2);
1658 added_sets_2 = added_sets_1 = 0;
1659 i2dest = SET_DEST (temp);
1661 SUBST (SET_SRC (temp),
1662 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1664 newpat = PATTERN (i2);
1665 i3_subst_into_i2 = 1;
1666 goto validate_replacement;
1670 /* If we have no I1 and I2 looks like:
1671 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1673 make up a dummy I1 that is
1676 (set (reg:CC X) (compare:CC Y (const_int 0)))
1678 (We can ignore any trailing CLOBBERs.)
1680 This undoes a previous combination and allows us to match a branch-and-
1683 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1684 && XVECLEN (PATTERN (i2), 0) >= 2
1685 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1686 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1688 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1689 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1691 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1692 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1693 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1695 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1696 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1701 /* We make I1 with the same INSN_UID as I2. This gives it
1702 the same INSN_CUID for value tracking. Our fake I1 will
1703 never appear in the insn stream so giving it the same INSN_UID
1704 as I2 will not cause a problem. */
1706 subst_prev_insn = i1
1707 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1708 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1711 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1712 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1713 SET_DEST (PATTERN (i1)));
1718 /* Verify that I2 and I1 are valid for combining. */
1719 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1720 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1726 /* Record whether I2DEST is used in I2SRC and similarly for the other
1727 cases. Knowing this will help in register status updating below. */
1728 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1729 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1730 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1732 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1734 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1736 /* Ensure that I3's pattern can be the destination of combines. */
1737 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1738 i1 && i2dest_in_i1src && i1_feeds_i3,
1745 /* See if any of the insns is a MULT operation. Unless one is, we will
1746 reject a combination that is, since it must be slower. Be conservative
1748 if (GET_CODE (i2src) == MULT
1749 || (i1 != 0 && GET_CODE (i1src) == MULT)
1750 || (GET_CODE (PATTERN (i3)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1754 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1755 We used to do this EXCEPT in one case: I3 has a post-inc in an
1756 output operand. However, that exception can give rise to insns like
1758 which is a famous insn on the PDP-11 where the value of r3 used as the
1759 source was model-dependent. Avoid this sort of thing. */
1762 if (!(GET_CODE (PATTERN (i3)) == SET
1763 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1764 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1765 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1766 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1767 /* It's not the exception. */
1770 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1771 if (REG_NOTE_KIND (link) == REG_INC
1772 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1774 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1781 /* See if the SETs in I1 or I2 need to be kept around in the merged
1782 instruction: whenever the value set there is still needed past I3.
1783 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1785 For the SET in I1, we have two cases: If I1 and I2 independently
1786 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1787 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1788 in I1 needs to be kept around unless I1DEST dies or is set in either
1789 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1790 I1DEST. If so, we know I1 feeds into I2. */
1792 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1795 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1796 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1798 /* If the set in I2 needs to be kept around, we must make a copy of
1799 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1800 PATTERN (I2), we are only substituting for the original I1DEST, not into
1801 an already-substituted copy. This also prevents making self-referential
1802 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1805 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1806 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1810 i2pat = copy_rtx (i2pat);
1814 /* Substitute in the latest insn for the regs set by the earlier ones. */
1816 maxreg = max_reg_num ();
1820 /* It is possible that the source of I2 or I1 may be performing an
1821 unneeded operation, such as a ZERO_EXTEND of something that is known
1822 to have the high part zero. Handle that case by letting subst look at
1823 the innermost one of them.
1825 Another way to do this would be to have a function that tries to
1826 simplify a single insn instead of merging two or more insns. We don't
1827 do this because of the potential of infinite loops and because
1828 of the potential extra memory required. However, doing it the way
1829 we are is a bit of a kludge and doesn't catch all cases.
1831 But only do this if -fexpensive-optimizations since it slows things down
1832 and doesn't usually win. */
1834 if (flag_expensive_optimizations)
1836 /* Pass pc_rtx so no substitutions are done, just simplifications.
1837 The cases that we are interested in here do not involve the few
1838 cases were is_replaced is checked. */
1841 subst_low_cuid = INSN_CUID (i1);
1842 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1846 subst_low_cuid = INSN_CUID (i2);
1847 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1850 undobuf.previous_undos = undobuf.undos;
1854 /* Many machines that don't use CC0 have insns that can both perform an
1855 arithmetic operation and set the condition code. These operations will
1856 be represented as a PARALLEL with the first element of the vector
1857 being a COMPARE of an arithmetic operation with the constant zero.
1858 The second element of the vector will set some pseudo to the result
1859 of the same arithmetic operation. If we simplify the COMPARE, we won't
1860 match such a pattern and so will generate an extra insn. Here we test
1861 for this case, where both the comparison and the operation result are
1862 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1863 I2SRC. Later we will make the PARALLEL that contains I2. */
1865 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1866 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1867 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1868 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1870 #ifdef EXTRA_CC_MODES
1872 enum machine_mode compare_mode;
1875 newpat = PATTERN (i3);
1876 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1880 #ifdef EXTRA_CC_MODES
1881 /* See if a COMPARE with the operand we substituted in should be done
1882 with the mode that is currently being used. If not, do the same
1883 processing we do in `subst' for a SET; namely, if the destination
1884 is used only once, try to replace it with a register of the proper
1885 mode and also replace the COMPARE. */
1886 if (undobuf.other_insn == 0
1887 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1888 &undobuf.other_insn))
1889 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1891 != GET_MODE (SET_DEST (newpat))))
1893 unsigned int regno = REGNO (SET_DEST (newpat));
1894 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1896 if (regno < FIRST_PSEUDO_REGISTER
1897 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1898 && ! REG_USERVAR_P (SET_DEST (newpat))))
1900 if (regno >= FIRST_PSEUDO_REGISTER)
1901 SUBST (regno_reg_rtx[regno], new_dest);
1903 SUBST (SET_DEST (newpat), new_dest);
1904 SUBST (XEXP (*cc_use, 0), new_dest);
1905 SUBST (SET_SRC (newpat),
1906 gen_rtx_combine (COMPARE, compare_mode,
1907 i2src, const0_rtx));
1910 undobuf.other_insn = 0;
1917 n_occurrences = 0; /* `subst' counts here */
1919 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1920 need to make a unique copy of I2SRC each time we substitute it
1921 to avoid self-referential rtl. */
1923 subst_low_cuid = INSN_CUID (i2);
1924 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1925 ! i1_feeds_i3 && i1dest_in_i1src);
1926 undobuf.previous_undos = undobuf.undos;
1928 /* Record whether i2's body now appears within i3's body. */
1929 i2_is_used = n_occurrences;
1932 /* If we already got a failure, don't try to do more. Otherwise,
1933 try to substitute in I1 if we have it. */
1935 if (i1 && GET_CODE (newpat) != CLOBBER)
1937 /* Before we can do this substitution, we must redo the test done
1938 above (see detailed comments there) that ensures that I1DEST
1939 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1941 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1949 subst_low_cuid = INSN_CUID (i1);
1950 newpat = subst (newpat, i1dest, i1src, 0, 0);
1951 undobuf.previous_undos = undobuf.undos;
1954 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1955 to count all the ways that I2SRC and I1SRC can be used. */
1956 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1957 && i2_is_used + added_sets_2 > 1)
1958 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1959 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1961 /* Fail if we tried to make a new register (we used to abort, but there's
1962 really no reason to). */
1963 || max_reg_num () != maxreg
1964 /* Fail if we couldn't do something and have a CLOBBER. */
1965 || GET_CODE (newpat) == CLOBBER
1966 /* Fail if this new pattern is a MULT and we didn't have one before
1967 at the outer level. */
1968 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1975 /* If the actions of the earlier insns must be kept
1976 in addition to substituting them into the latest one,
1977 we must make a new PARALLEL for the latest insn
1978 to hold additional the SETs. */
1980 if (added_sets_1 || added_sets_2)
1984 if (GET_CODE (newpat) == PARALLEL)
1986 rtvec old = XVEC (newpat, 0);
1987 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1988 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1989 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1990 sizeof (old->elem[0]) * old->num_elem);
1995 total_sets = 1 + added_sets_1 + added_sets_2;
1996 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1997 XVECEXP (newpat, 0, 0) = old;
2001 XVECEXP (newpat, 0, --total_sets)
2002 = (GET_CODE (PATTERN (i1)) == PARALLEL
2003 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2007 /* If there is no I1, use I2's body as is. We used to also not do
2008 the subst call below if I2 was substituted into I3,
2009 but that could lose a simplification. */
2011 XVECEXP (newpat, 0, --total_sets) = i2pat;
2013 /* See comment where i2pat is assigned. */
2014 XVECEXP (newpat, 0, --total_sets)
2015 = subst (i2pat, i1dest, i1src, 0, 0);
2019 /* We come here when we are replacing a destination in I2 with the
2020 destination of I3. */
2021 validate_replacement:
2023 /* Note which hard regs this insn has as inputs. */
2024 mark_used_regs_combine (newpat);
2026 /* Is the result of combination a valid instruction? */
2027 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2029 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2030 the second SET's destination is a register that is unused. In that case,
2031 we just need the first SET. This can occur when simplifying a divmod
2032 insn. We *must* test for this case here because the code below that
2033 splits two independent SETs doesn't handle this case correctly when it
2034 updates the register status. Also check the case where the first
2035 SET's destination is unused. That would not cause incorrect code, but
2036 does cause an unneeded insn to remain. */
2038 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2039 && XVECLEN (newpat, 0) == 2
2040 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2041 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2042 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2043 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2044 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2045 && asm_noperands (newpat) < 0)
2047 newpat = XVECEXP (newpat, 0, 0);
2048 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2051 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2056 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2058 && asm_noperands (newpat) < 0)
2060 newpat = XVECEXP (newpat, 0, 1);
2061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2064 /* If we were combining three insns and the result is a simple SET
2065 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2066 insns. There are two ways to do this. It can be split using a
2067 machine-specific method (like when you have an addition of a large
2068 constant) or by combine in the function find_split_point. */
2070 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2071 && asm_noperands (newpat) < 0)
2073 rtx m_split, *split;
2074 rtx ni2dest = i2dest;
2076 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2077 use I2DEST as a scratch register will help. In the latter case,
2078 convert I2DEST to the mode of the source of NEWPAT if we can. */
2080 m_split = split_insns (newpat, i3);
2082 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2083 inputs of NEWPAT. */
2085 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2086 possible to try that as a scratch reg. This would require adding
2087 more code to make it work though. */
2089 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2091 /* If I2DEST is a hard register or the only use of a pseudo,
2092 we can change its mode. */
2093 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2094 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2095 && GET_CODE (i2dest) == REG
2096 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2097 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2098 && ! REG_USERVAR_P (i2dest))))
2099 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2102 m_split = split_insns (gen_rtx_PARALLEL
2104 gen_rtvec (2, newpat,
2105 gen_rtx_CLOBBER (VOIDmode,
2110 if (m_split && GET_CODE (m_split) == SEQUENCE
2111 && XVECLEN (m_split, 0) == 2
2112 && (next_real_insn (i2) == i3
2113 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2117 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2118 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2120 i3set = single_set (XVECEXP (m_split, 0, 1));
2121 i2set = single_set (XVECEXP (m_split, 0, 0));
2123 /* In case we changed the mode of I2DEST, replace it in the
2124 pseudo-register table here. We can't do it above in case this
2125 code doesn't get executed and we do a split the other way. */
2127 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2128 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2130 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2132 /* If I2 or I3 has multiple SETs, we won't know how to track
2133 register status, so don't use these insns. If I2's destination
2134 is used between I2 and I3, we also can't use these insns. */
2136 if (i2_code_number >= 0 && i2set && i3set
2137 && (next_real_insn (i2) == i3
2138 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2139 insn_code_number = recog_for_combine (&newi3pat, i3,
2141 if (insn_code_number >= 0)
2144 /* It is possible that both insns now set the destination of I3.
2145 If so, we must show an extra use of it. */
2147 if (insn_code_number >= 0)
2149 rtx new_i3_dest = SET_DEST (i3set);
2150 rtx new_i2_dest = SET_DEST (i2set);
2152 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2153 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2154 || GET_CODE (new_i3_dest) == SUBREG)
2155 new_i3_dest = XEXP (new_i3_dest, 0);
2157 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2158 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2159 || GET_CODE (new_i2_dest) == SUBREG)
2160 new_i2_dest = XEXP (new_i2_dest, 0);
2162 if (GET_CODE (new_i3_dest) == REG
2163 && GET_CODE (new_i2_dest) == REG
2164 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2165 REG_N_SETS (REGNO (new_i2_dest))++;
2169 /* If we can split it and use I2DEST, go ahead and see if that
2170 helps things be recognized. Verify that none of the registers
2171 are set between I2 and I3. */
2172 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2174 && GET_CODE (i2dest) == REG
2176 /* We need I2DEST in the proper mode. If it is a hard register
2177 or the only use of a pseudo, we can change its mode. */
2178 && (GET_MODE (*split) == GET_MODE (i2dest)
2179 || GET_MODE (*split) == VOIDmode
2180 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2181 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2182 && ! REG_USERVAR_P (i2dest)))
2183 && (next_real_insn (i2) == i3
2184 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2185 /* We can't overwrite I2DEST if its value is still used by
2187 && ! reg_referenced_p (i2dest, newpat))
2189 rtx newdest = i2dest;
2190 enum rtx_code split_code = GET_CODE (*split);
2191 enum machine_mode split_mode = GET_MODE (*split);
2193 /* Get NEWDEST as a register in the proper mode. We have already
2194 validated that we can do this. */
2195 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2197 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2199 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2200 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2203 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2204 an ASHIFT. This can occur if it was inside a PLUS and hence
2205 appeared to be a memory address. This is a kludge. */
2206 if (split_code == MULT
2207 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2208 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2210 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2211 XEXP (*split, 0), GEN_INT (i)));
2212 /* Update split_code because we may not have a multiply
2214 split_code = GET_CODE (*split);
2217 #ifdef INSN_SCHEDULING
2218 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2219 be written as a ZERO_EXTEND. */
2220 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2221 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2225 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2226 SUBST (*split, newdest);
2227 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2229 /* If the split point was a MULT and we didn't have one before,
2230 don't use one now. */
2231 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2232 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2236 /* Check for a case where we loaded from memory in a narrow mode and
2237 then sign extended it, but we need both registers. In that case,
2238 we have a PARALLEL with both loads from the same memory location.
2239 We can split this into a load from memory followed by a register-register
2240 copy. This saves at least one insn, more if register allocation can
2243 We cannot do this if the destination of the second assignment is
2244 a register that we have already assumed is zero-extended. Similarly
2245 for a SUBREG of such a register. */
2247 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2248 && GET_CODE (newpat) == PARALLEL
2249 && XVECLEN (newpat, 0) == 2
2250 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2251 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2252 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2253 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2254 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2255 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2257 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2258 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2259 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2260 (GET_CODE (temp) == REG
2261 && reg_nonzero_bits[REGNO (temp)] != 0
2262 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2263 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2264 && (reg_nonzero_bits[REGNO (temp)]
2265 != GET_MODE_MASK (word_mode))))
2266 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2267 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2268 (GET_CODE (temp) == REG
2269 && reg_nonzero_bits[REGNO (temp)] != 0
2270 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2271 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2272 && (reg_nonzero_bits[REGNO (temp)]
2273 != GET_MODE_MASK (word_mode)))))
2274 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2275 SET_SRC (XVECEXP (newpat, 0, 1)))
2276 && ! find_reg_note (i3, REG_UNUSED,
2277 SET_DEST (XVECEXP (newpat, 0, 0))))
2281 newi2pat = XVECEXP (newpat, 0, 0);
2282 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2283 newpat = XVECEXP (newpat, 0, 1);
2284 SUBST (SET_SRC (newpat),
2285 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2286 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2288 if (i2_code_number >= 0)
2289 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2291 if (insn_code_number >= 0)
2296 /* If we will be able to accept this, we have made a change to the
2297 destination of I3. This can invalidate a LOG_LINKS pointing
2298 to I3. No other part of combine.c makes such a transformation.
2300 The new I3 will have a destination that was previously the
2301 destination of I1 or I2 and which was used in i2 or I3. Call
2302 distribute_links to make a LOG_LINK from the next use of
2303 that destination. */
2305 PATTERN (i3) = newpat;
2306 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2308 /* I3 now uses what used to be its destination and which is
2309 now I2's destination. That means we need a LOG_LINK from
2310 I3 to I2. But we used to have one, so we still will.
2312 However, some later insn might be using I2's dest and have
2313 a LOG_LINK pointing at I3. We must remove this link.
2314 The simplest way to remove the link is to point it at I1,
2315 which we know will be a NOTE. */
2317 for (insn = NEXT_INSN (i3);
2318 insn && (this_basic_block == n_basic_blocks - 1
2319 || insn != BLOCK_HEAD (this_basic_block + 1));
2320 insn = NEXT_INSN (insn))
2322 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2324 for (link = LOG_LINKS (insn); link;
2325 link = XEXP (link, 1))
2326 if (XEXP (link, 0) == i3)
2327 XEXP (link, 0) = i1;
2335 /* Similarly, check for a case where we have a PARALLEL of two independent
2336 SETs but we started with three insns. In this case, we can do the sets
2337 as two separate insns. This case occurs when some SET allows two
2338 other insns to combine, but the destination of that SET is still live. */
2340 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2341 && GET_CODE (newpat) == PARALLEL
2342 && XVECLEN (newpat, 0) == 2
2343 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2344 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2345 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2346 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2347 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2348 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2349 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2351 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2352 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2353 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2354 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2355 XVECEXP (newpat, 0, 0))
2356 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2357 XVECEXP (newpat, 0, 1))
2358 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2359 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2361 /* Normally, it doesn't matter which of the two is done first,
2362 but it does if one references cc0. In that case, it has to
2365 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2367 newi2pat = XVECEXP (newpat, 0, 0);
2368 newpat = XVECEXP (newpat, 0, 1);
2373 newi2pat = XVECEXP (newpat, 0, 1);
2374 newpat = XVECEXP (newpat, 0, 0);
2377 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2379 if (i2_code_number >= 0)
2380 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2383 /* If it still isn't recognized, fail and change things back the way they
2385 if ((insn_code_number < 0
2386 /* Is the result a reasonable ASM_OPERANDS? */
2387 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2393 /* If we had to change another insn, make sure it is valid also. */
2394 if (undobuf.other_insn)
2396 rtx other_pat = PATTERN (undobuf.other_insn);
2397 rtx new_other_notes;
2400 CLEAR_HARD_REG_SET (newpat_used_regs);
2402 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2405 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2411 PATTERN (undobuf.other_insn) = other_pat;
2413 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2414 are still valid. Then add any non-duplicate notes added by
2415 recog_for_combine. */
2416 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2418 next = XEXP (note, 1);
2420 if (REG_NOTE_KIND (note) == REG_UNUSED
2421 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2423 if (GET_CODE (XEXP (note, 0)) == REG)
2424 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2426 remove_note (undobuf.other_insn, note);
2430 for (note = new_other_notes; note; note = XEXP (note, 1))
2431 if (GET_CODE (XEXP (note, 0)) == REG)
2432 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2434 distribute_notes (new_other_notes, undobuf.other_insn,
2435 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2438 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2439 they are adjacent to each other or not. */
2441 rtx p = prev_nonnote_insn (i3);
2442 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2443 && sets_cc0_p (newi2pat))
2451 /* We now know that we can do this combination. Merge the insns and
2452 update the status of registers and LOG_LINKS. */
2455 rtx i3notes, i2notes, i1notes = 0;
2456 rtx i3links, i2links, i1links = 0;
2459 /* Compute which registers we expect to eliminate. newi2pat may be setting
2460 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2461 same as i3dest, in which case newi2pat may be setting i1dest. */
2462 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2463 || i2dest_in_i2src || i2dest_in_i1src
2465 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2466 || (newi2pat && reg_set_p (i1dest, newi2pat))
2469 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2471 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2472 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2474 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2476 /* Ensure that we do not have something that should not be shared but
2477 occurs multiple times in the new insns. Check this by first
2478 resetting all the `used' flags and then copying anything is shared. */
2480 reset_used_flags (i3notes);
2481 reset_used_flags (i2notes);
2482 reset_used_flags (i1notes);
2483 reset_used_flags (newpat);
2484 reset_used_flags (newi2pat);
2485 if (undobuf.other_insn)
2486 reset_used_flags (PATTERN (undobuf.other_insn));
2488 i3notes = copy_rtx_if_shared (i3notes);
2489 i2notes = copy_rtx_if_shared (i2notes);
2490 i1notes = copy_rtx_if_shared (i1notes);
2491 newpat = copy_rtx_if_shared (newpat);
2492 newi2pat = copy_rtx_if_shared (newi2pat);
2493 if (undobuf.other_insn)
2494 reset_used_flags (PATTERN (undobuf.other_insn));
2496 INSN_CODE (i3) = insn_code_number;
2497 PATTERN (i3) = newpat;
2498 if (undobuf.other_insn)
2499 INSN_CODE (undobuf.other_insn) = other_code_number;
2501 /* We had one special case above where I2 had more than one set and
2502 we replaced a destination of one of those sets with the destination
2503 of I3. In that case, we have to update LOG_LINKS of insns later
2504 in this basic block. Note that this (expensive) case is rare.
2506 Also, in this case, we must pretend that all REG_NOTEs for I2
2507 actually came from I3, so that REG_UNUSED notes from I2 will be
2508 properly handled. */
2510 if (i3_subst_into_i2 && GET_CODE (PATTERN (i2)) == PARALLEL)
2512 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2514 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2515 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2516 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2517 && ! find_reg_note (i2, REG_UNUSED,
2518 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2519 for (temp = NEXT_INSN (i2);
2520 temp && (this_basic_block == n_basic_blocks - 1
2521 || BLOCK_HEAD (this_basic_block) != temp);
2522 temp = NEXT_INSN (temp))
2523 if (temp != i3 && INSN_P (temp))
2524 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2525 if (XEXP (link, 0) == i2)
2526 XEXP (link, 0) = i3;
2532 while (XEXP (link, 1))
2533 link = XEXP (link, 1);
2534 XEXP (link, 1) = i2notes;
2548 INSN_CODE (i2) = i2_code_number;
2549 PATTERN (i2) = newi2pat;
2553 PUT_CODE (i2, NOTE);
2554 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2555 NOTE_SOURCE_FILE (i2) = 0;
2562 PUT_CODE (i1, NOTE);
2563 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2564 NOTE_SOURCE_FILE (i1) = 0;
2567 /* Get death notes for everything that is now used in either I3 or
2568 I2 and used to die in a previous insn. If we built two new
2569 patterns, move from I1 to I2 then I2 to I3 so that we get the
2570 proper movement on registers that I2 modifies. */
2574 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2575 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2578 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2581 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2583 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2586 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2589 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2592 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2595 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2596 know these are REG_UNUSED and want them to go to the desired insn,
2597 so we always pass it as i3. We have not counted the notes in
2598 reg_n_deaths yet, so we need to do so now. */
2600 if (newi2pat && new_i2_notes)
2602 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2603 if (GET_CODE (XEXP (temp, 0)) == REG)
2604 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2606 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2611 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2612 if (GET_CODE (XEXP (temp, 0)) == REG)
2613 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2615 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2618 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2619 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2620 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2621 in that case, it might delete I2. Similarly for I2 and I1.
2622 Show an additional death due to the REG_DEAD note we make here. If
2623 we discard it in distribute_notes, we will decrement it again. */
2627 if (GET_CODE (i3dest_killed) == REG)
2628 REG_N_DEATHS (REGNO (i3dest_killed))++;
2630 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2631 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2633 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2635 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2637 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2641 if (i2dest_in_i2src)
2643 if (GET_CODE (i2dest) == REG)
2644 REG_N_DEATHS (REGNO (i2dest))++;
2646 if (newi2pat && reg_set_p (i2dest, newi2pat))
2647 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2648 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2650 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2651 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2652 NULL_RTX, NULL_RTX);
2655 if (i1dest_in_i1src)
2657 if (GET_CODE (i1dest) == REG)
2658 REG_N_DEATHS (REGNO (i1dest))++;
2660 if (newi2pat && reg_set_p (i1dest, newi2pat))
2661 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2662 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2664 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2665 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2666 NULL_RTX, NULL_RTX);
2669 distribute_links (i3links);
2670 distribute_links (i2links);
2671 distribute_links (i1links);
2673 if (GET_CODE (i2dest) == REG)
2676 rtx i2_insn = 0, i2_val = 0, set;
2678 /* The insn that used to set this register doesn't exist, and
2679 this life of the register may not exist either. See if one of
2680 I3's links points to an insn that sets I2DEST. If it does,
2681 that is now the last known value for I2DEST. If we don't update
2682 this and I2 set the register to a value that depended on its old
2683 contents, we will get confused. If this insn is used, thing
2684 will be set correctly in combine_instructions. */
2686 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2687 if ((set = single_set (XEXP (link, 0))) != 0
2688 && rtx_equal_p (i2dest, SET_DEST (set)))
2689 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2691 record_value_for_reg (i2dest, i2_insn, i2_val);
2693 /* If the reg formerly set in I2 died only once and that was in I3,
2694 zero its use count so it won't make `reload' do any work. */
2696 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2697 && ! i2dest_in_i2src)
2699 regno = REGNO (i2dest);
2700 REG_N_SETS (regno)--;
2704 if (i1 && GET_CODE (i1dest) == REG)
2707 rtx i1_insn = 0, i1_val = 0, set;
2709 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2710 if ((set = single_set (XEXP (link, 0))) != 0
2711 && rtx_equal_p (i1dest, SET_DEST (set)))
2712 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2714 record_value_for_reg (i1dest, i1_insn, i1_val);
2716 regno = REGNO (i1dest);
2717 if (! added_sets_1 && ! i1dest_in_i1src)
2718 REG_N_SETS (regno)--;
2721 /* Update reg_nonzero_bits et al for any changes that may have been made
2722 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2723 important. Because newi2pat can affect nonzero_bits of newpat */
2725 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2726 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2728 /* Set new_direct_jump_p if a new return or simple jump instruction
2731 If I3 is now an unconditional jump, ensure that it has a
2732 BARRIER following it since it may have initially been a
2733 conditional jump. It may also be the last nonnote insn. */
2735 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2737 *new_direct_jump_p = 1;
2739 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2740 || GET_CODE (temp) != BARRIER)
2741 emit_barrier_after (i3);
2745 combine_successes++;
2748 /* Clear this here, so that subsequent get_last_value calls are not
2750 subst_prev_insn = NULL_RTX;
2752 if (added_links_insn
2753 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2754 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2755 return added_links_insn;
2757 return newi2pat ? i2 : i3;
2760 /* Undo all the modifications recorded in undobuf. */
2765 struct undo *undo, *next;
2767 for (undo = undobuf.undos; undo; undo = next)
2771 *undo->where.i = undo->old_contents.i;
2773 *undo->where.r = undo->old_contents.r;
2775 undo->next = undobuf.frees;
2776 undobuf.frees = undo;
2779 obfree (undobuf.storage);
2780 undobuf.undos = undobuf.previous_undos = 0;
2782 /* Clear this here, so that subsequent get_last_value calls are not
2784 subst_prev_insn = NULL_RTX;
2787 /* We've committed to accepting the changes we made. Move all
2788 of the undos to the free list. */
2793 struct undo *undo, *next;
2795 for (undo = undobuf.undos; undo; undo = next)
2798 undo->next = undobuf.frees;
2799 undobuf.frees = undo;
2801 undobuf.undos = undobuf.previous_undos = 0;
2805 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2806 where we have an arithmetic expression and return that point. LOC will
2809 try_combine will call this function to see if an insn can be split into
2813 find_split_point (loc, insn)
2818 enum rtx_code code = GET_CODE (x);
2820 unsigned HOST_WIDE_INT len = 0;
2821 HOST_WIDE_INT pos = 0;
2823 rtx inner = NULL_RTX;
2825 /* First special-case some codes. */
2829 #ifdef INSN_SCHEDULING
2830 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2832 if (GET_CODE (SUBREG_REG (x)) == MEM)
2835 return find_split_point (&SUBREG_REG (x), insn);
2839 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2840 using LO_SUM and HIGH. */
2841 if (GET_CODE (XEXP (x, 0)) == CONST
2842 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2845 gen_rtx_combine (LO_SUM, Pmode,
2846 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2848 return &XEXP (XEXP (x, 0), 0);
2852 /* If we have a PLUS whose second operand is a constant and the
2853 address is not valid, perhaps will can split it up using
2854 the machine-specific way to split large constants. We use
2855 the first pseudo-reg (one of the virtual regs) as a placeholder;
2856 it will not remain in the result. */
2857 if (GET_CODE (XEXP (x, 0)) == PLUS
2858 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2859 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2861 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2862 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2865 /* This should have produced two insns, each of which sets our
2866 placeholder. If the source of the second is a valid address,
2867 we can make put both sources together and make a split point
2870 if (seq && XVECLEN (seq, 0) == 2
2871 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2872 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2873 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2874 && ! reg_mentioned_p (reg,
2875 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2876 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2877 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2878 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2879 && memory_address_p (GET_MODE (x),
2880 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2882 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2883 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2885 /* Replace the placeholder in SRC2 with SRC1. If we can
2886 find where in SRC2 it was placed, that can become our
2887 split point and we can replace this address with SRC2.
2888 Just try two obvious places. */
2890 src2 = replace_rtx (src2, reg, src1);
2892 if (XEXP (src2, 0) == src1)
2893 split = &XEXP (src2, 0);
2894 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2895 && XEXP (XEXP (src2, 0), 0) == src1)
2896 split = &XEXP (XEXP (src2, 0), 0);
2900 SUBST (XEXP (x, 0), src2);
2905 /* If that didn't work, perhaps the first operand is complex and
2906 needs to be computed separately, so make a split point there.
2907 This will occur on machines that just support REG + CONST
2908 and have a constant moved through some previous computation. */
2910 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2911 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2912 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2914 return &XEXP (XEXP (x, 0), 0);
2920 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2921 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2922 we need to put the operand into a register. So split at that
2925 if (SET_DEST (x) == cc0_rtx
2926 && GET_CODE (SET_SRC (x)) != COMPARE
2927 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2928 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2929 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2930 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2931 return &SET_SRC (x);
2934 /* See if we can split SET_SRC as it stands. */
2935 split = find_split_point (&SET_SRC (x), insn);
2936 if (split && split != &SET_SRC (x))
2939 /* See if we can split SET_DEST as it stands. */
2940 split = find_split_point (&SET_DEST (x), insn);
2941 if (split && split != &SET_DEST (x))
2944 /* See if this is a bitfield assignment with everything constant. If
2945 so, this is an IOR of an AND, so split it into that. */
2946 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2947 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2948 <= HOST_BITS_PER_WIDE_INT)
2949 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2950 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2951 && GET_CODE (SET_SRC (x)) == CONST_INT
2952 && ((INTVAL (XEXP (SET_DEST (x), 1))
2953 + INTVAL (XEXP (SET_DEST (x), 2)))
2954 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2955 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2957 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2958 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2959 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2960 rtx dest = XEXP (SET_DEST (x), 0);
2961 enum machine_mode mode = GET_MODE (dest);
2962 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2964 if (BITS_BIG_ENDIAN)
2965 pos = GET_MODE_BITSIZE (mode) - len - pos;
2969 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2972 gen_binary (IOR, mode,
2973 gen_binary (AND, mode, dest,
2974 GEN_INT (~(mask << pos)
2975 & GET_MODE_MASK (mode))),
2976 GEN_INT (src << pos)));
2978 SUBST (SET_DEST (x), dest);
2980 split = find_split_point (&SET_SRC (x), insn);
2981 if (split && split != &SET_SRC (x))
2985 /* Otherwise, see if this is an operation that we can split into two.
2986 If so, try to split that. */
2987 code = GET_CODE (SET_SRC (x));
2992 /* If we are AND'ing with a large constant that is only a single
2993 bit and the result is only being used in a context where we
2994 need to know if it is zero or non-zero, replace it with a bit
2995 extraction. This will avoid the large constant, which might
2996 have taken more than one insn to make. If the constant were
2997 not a valid argument to the AND but took only one insn to make,
2998 this is no worse, but if it took more than one insn, it will
3001 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3002 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3003 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3004 && GET_CODE (SET_DEST (x)) == REG
3005 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3006 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3007 && XEXP (*split, 0) == SET_DEST (x)
3008 && XEXP (*split, 1) == const0_rtx)
3010 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3011 XEXP (SET_SRC (x), 0),
3012 pos, NULL_RTX, 1, 1, 0, 0);
3013 if (extraction != 0)
3015 SUBST (SET_SRC (x), extraction);
3016 return find_split_point (loc, insn);
3022 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3023 is known to be on, this can be converted into a NEG of a shift. */
3024 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3025 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3026 && 1 <= (pos = exact_log2
3027 (nonzero_bits (XEXP (SET_SRC (x), 0),
3028 GET_MODE (XEXP (SET_SRC (x), 0))))))
3030 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3033 gen_rtx_combine (NEG, mode,
3034 gen_rtx_combine (LSHIFTRT, mode,
3035 XEXP (SET_SRC (x), 0),
3038 split = find_split_point (&SET_SRC (x), insn);
3039 if (split && split != &SET_SRC (x))
3045 inner = XEXP (SET_SRC (x), 0);
3047 /* We can't optimize if either mode is a partial integer
3048 mode as we don't know how many bits are significant
3050 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3051 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3055 len = GET_MODE_BITSIZE (GET_MODE (inner));
3061 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3062 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3064 inner = XEXP (SET_SRC (x), 0);
3065 len = INTVAL (XEXP (SET_SRC (x), 1));
3066 pos = INTVAL (XEXP (SET_SRC (x), 2));
3068 if (BITS_BIG_ENDIAN)
3069 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3070 unsignedp = (code == ZERO_EXTRACT);
3078 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3080 enum machine_mode mode = GET_MODE (SET_SRC (x));
3082 /* For unsigned, we have a choice of a shift followed by an
3083 AND or two shifts. Use two shifts for field sizes where the
3084 constant might be too large. We assume here that we can
3085 always at least get 8-bit constants in an AND insn, which is
3086 true for every current RISC. */
3088 if (unsignedp && len <= 8)
3093 gen_rtx_combine (LSHIFTRT, mode,
3094 gen_lowpart_for_combine (mode, inner),
3096 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3098 split = find_split_point (&SET_SRC (x), insn);
3099 if (split && split != &SET_SRC (x))
3106 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3107 gen_rtx_combine (ASHIFT, mode,
3108 gen_lowpart_for_combine (mode, inner),
3109 GEN_INT (GET_MODE_BITSIZE (mode)
3111 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3113 split = find_split_point (&SET_SRC (x), insn);
3114 if (split && split != &SET_SRC (x))
3119 /* See if this is a simple operation with a constant as the second
3120 operand. It might be that this constant is out of range and hence
3121 could be used as a split point. */
3122 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3123 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3124 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3125 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3126 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3127 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3128 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3130 return &XEXP (SET_SRC (x), 1);
3132 /* Finally, see if this is a simple operation with its first operand
3133 not in a register. The operation might require this operand in a
3134 register, so return it as a split point. We can always do this
3135 because if the first operand were another operation, we would have
3136 already found it as a split point. */
3137 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3138 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3139 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3140 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3141 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3142 return &XEXP (SET_SRC (x), 0);
3148 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3149 it is better to write this as (not (ior A B)) so we can split it.
3150 Similarly for IOR. */
3151 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3154 gen_rtx_combine (NOT, GET_MODE (x),
3155 gen_rtx_combine (code == IOR ? AND : IOR,
3157 XEXP (XEXP (x, 0), 0),
3158 XEXP (XEXP (x, 1), 0))));
3159 return find_split_point (loc, insn);
3162 /* Many RISC machines have a large set of logical insns. If the
3163 second operand is a NOT, put it first so we will try to split the
3164 other operand first. */
3165 if (GET_CODE (XEXP (x, 1)) == NOT)
3167 rtx tem = XEXP (x, 0);
3168 SUBST (XEXP (x, 0), XEXP (x, 1));
3169 SUBST (XEXP (x, 1), tem);
3177 /* Otherwise, select our actions depending on our rtx class. */
3178 switch (GET_RTX_CLASS (code))
3180 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3182 split = find_split_point (&XEXP (x, 2), insn);
3185 /* ... fall through ... */
3189 split = find_split_point (&XEXP (x, 1), insn);
3192 /* ... fall through ... */
3194 /* Some machines have (and (shift ...) ...) insns. If X is not
3195 an AND, but XEXP (X, 0) is, use it as our split point. */
3196 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3197 return &XEXP (x, 0);
3199 split = find_split_point (&XEXP (x, 0), insn);
3205 /* Otherwise, we don't have a split point. */
3209 /* Throughout X, replace FROM with TO, and return the result.
3210 The result is TO if X is FROM;
3211 otherwise the result is X, but its contents may have been modified.
3212 If they were modified, a record was made in undobuf so that
3213 undo_all will (among other things) return X to its original state.
3215 If the number of changes necessary is too much to record to undo,
3216 the excess changes are not made, so the result is invalid.
3217 The changes already made can still be undone.
3218 undobuf.num_undo is incremented for such changes, so by testing that
3219 the caller can tell whether the result is valid.
3221 `n_occurrences' is incremented each time FROM is replaced.
3223 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3225 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3226 by copying if `n_occurrences' is non-zero. */
3229 subst (x, from, to, in_dest, unique_copy)
3230 register rtx x, from, to;
3234 register enum rtx_code code = GET_CODE (x);
3235 enum machine_mode op0_mode = VOIDmode;
3236 register const char *fmt;
3237 register int len, i;
3240 /* Two expressions are equal if they are identical copies of a shared
3241 RTX or if they are both registers with the same register number
3244 #define COMBINE_RTX_EQUAL_P(X,Y) \
3246 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3247 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3249 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3252 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3255 /* If X and FROM are the same register but different modes, they will
3256 not have been seen as equal above. However, flow.c will make a
3257 LOG_LINKS entry for that case. If we do nothing, we will try to
3258 rerecognize our original insn and, when it succeeds, we will
3259 delete the feeding insn, which is incorrect.
3261 So force this insn not to match in this (rare) case. */
3262 if (! in_dest && code == REG && GET_CODE (from) == REG
3263 && REGNO (x) == REGNO (from))
3264 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3266 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3267 of which may contain things that can be combined. */
3268 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3271 /* It is possible to have a subexpression appear twice in the insn.
3272 Suppose that FROM is a register that appears within TO.
3273 Then, after that subexpression has been scanned once by `subst',
3274 the second time it is scanned, TO may be found. If we were
3275 to scan TO here, we would find FROM within it and create a
3276 self-referent rtl structure which is completely wrong. */
3277 if (COMBINE_RTX_EQUAL_P (x, to))
3280 /* Parallel asm_operands need special attention because all of the
3281 inputs are shared across the arms. Furthermore, unsharing the
3282 rtl results in recognition failures. Failure to handle this case
3283 specially can result in circular rtl.
3285 Solve this by doing a normal pass across the first entry of the
3286 parallel, and only processing the SET_DESTs of the subsequent
3289 if (code == PARALLEL
3290 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3291 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3293 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3295 /* If this substitution failed, this whole thing fails. */
3296 if (GET_CODE (new) == CLOBBER
3297 && XEXP (new, 0) == const0_rtx)
3300 SUBST (XVECEXP (x, 0, 0), new);
3302 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3304 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3306 if (GET_CODE (dest) != REG
3307 && GET_CODE (dest) != CC0
3308 && GET_CODE (dest) != PC)
3310 new = subst (dest, from, to, 0, unique_copy);
3312 /* If this substitution failed, this whole thing fails. */
3313 if (GET_CODE (new) == CLOBBER
3314 && XEXP (new, 0) == const0_rtx)
3317 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3323 len = GET_RTX_LENGTH (code);
3324 fmt = GET_RTX_FORMAT (code);
3326 /* We don't need to process a SET_DEST that is a register, CC0,
3327 or PC, so set up to skip this common case. All other cases
3328 where we want to suppress replacing something inside a
3329 SET_SRC are handled via the IN_DEST operand. */
3331 && (GET_CODE (SET_DEST (x)) == REG
3332 || GET_CODE (SET_DEST (x)) == CC0
3333 || GET_CODE (SET_DEST (x)) == PC))
3336 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3339 op0_mode = GET_MODE (XEXP (x, 0));
3341 for (i = 0; i < len; i++)
3346 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3348 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3350 new = (unique_copy && n_occurrences
3351 ? copy_rtx (to) : to);
3356 new = subst (XVECEXP (x, i, j), from, to, 0,
3359 /* If this substitution failed, this whole thing
3361 if (GET_CODE (new) == CLOBBER
3362 && XEXP (new, 0) == const0_rtx)
3366 SUBST (XVECEXP (x, i, j), new);
3369 else if (fmt[i] == 'e')
3371 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3373 /* In general, don't install a subreg involving two
3374 modes not tieable. It can worsen register
3375 allocation, and can even make invalid reload
3376 insns, since the reg inside may need to be copied
3377 from in the outside mode, and that may be invalid
3378 if it is an fp reg copied in integer mode.
3380 We allow two exceptions to this: It is valid if
3381 it is inside another SUBREG and the mode of that
3382 SUBREG and the mode of the inside of TO is
3383 tieable and it is valid if X is a SET that copies
3386 if (GET_CODE (to) == SUBREG
3387 && ! MODES_TIEABLE_P (GET_MODE (to),
3388 GET_MODE (SUBREG_REG (to)))
3389 && ! (code == SUBREG
3390 && MODES_TIEABLE_P (GET_MODE (x),
3391 GET_MODE (SUBREG_REG (to))))
3393 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3396 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3398 #ifdef CLASS_CANNOT_CHANGE_MODE
3400 && GET_CODE (to) == REG
3401 && REGNO (to) < FIRST_PSEUDO_REGISTER
3402 && (TEST_HARD_REG_BIT
3403 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3405 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3407 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3410 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3414 /* If we are in a SET_DEST, suppress most cases unless we
3415 have gone inside a MEM, in which case we want to
3416 simplify the address. We assume here that things that
3417 are actually part of the destination have their inner
3418 parts in the first expression. This is true for SUBREG,
3419 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3420 things aside from REG and MEM that should appear in a
3422 new = subst (XEXP (x, i), from, to,
3424 && (code == SUBREG || code == STRICT_LOW_PART
3425 || code == ZERO_EXTRACT))
3427 && i == 0), unique_copy);
3429 /* If we found that we will have to reject this combination,
3430 indicate that by returning the CLOBBER ourselves, rather than
3431 an expression containing it. This will speed things up as
3432 well as prevent accidents where two CLOBBERs are considered
3433 to be equal, thus producing an incorrect simplification. */
3435 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3438 SUBST (XEXP (x, i), new);
3443 /* Try to simplify X. If the simplification changed the code, it is likely
3444 that further simplification will help, so loop, but limit the number
3445 of repetitions that will be performed. */
3447 for (i = 0; i < 4; i++)
3449 /* If X is sufficiently simple, don't bother trying to do anything
3451 if (code != CONST_INT && code != REG && code != CLOBBER)
3452 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3454 if (GET_CODE (x) == code)
3457 code = GET_CODE (x);
3459 /* We no longer know the original mode of operand 0 since we
3460 have changed the form of X) */
3461 op0_mode = VOIDmode;
3467 /* Simplify X, a piece of RTL. We just operate on the expression at the
3468 outer level; call `subst' to simplify recursively. Return the new
3471 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3472 will be the iteration even if an expression with a code different from
3473 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3476 combine_simplify_rtx (x, op0_mode, last, in_dest)
3478 enum machine_mode op0_mode;
3482 enum rtx_code code = GET_CODE (x);
3483 enum machine_mode mode = GET_MODE (x);
3487 /* If this is a commutative operation, put a constant last and a complex
3488 expression first. We don't need to do this for comparisons here. */
3489 if (GET_RTX_CLASS (code) == 'c'
3490 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3491 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3492 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3493 || (GET_CODE (XEXP (x, 0)) == SUBREG
3494 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3495 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3498 SUBST (XEXP (x, 0), XEXP (x, 1));
3499 SUBST (XEXP (x, 1), temp);
3502 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3503 sign extension of a PLUS with a constant, reverse the order of the sign
3504 extension and the addition. Note that this not the same as the original
3505 code, but overflow is undefined for signed values. Also note that the
3506 PLUS will have been partially moved "inside" the sign-extension, so that
3507 the first operand of X will really look like:
3508 (ashiftrt (plus (ashift A C4) C5) C4).
3510 (plus (ashiftrt (ashift A C4) C2) C4)
3511 and replace the first operand of X with that expression. Later parts
3512 of this function may simplify the expression further.
3514 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3515 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3516 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3518 We do this to simplify address expressions. */
3520 if ((code == PLUS || code == MINUS || code == MULT)
3521 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3522 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3523 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3524 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3525 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3526 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3527 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3528 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3529 XEXP (XEXP (XEXP (x, 0), 0), 1),
3530 XEXP (XEXP (x, 0), 1))) != 0)
3533 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3534 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3535 INTVAL (XEXP (XEXP (x, 0), 1)));
3537 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3538 INTVAL (XEXP (XEXP (x, 0), 1)));
3540 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3543 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3544 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3545 things. Check for cases where both arms are testing the same
3548 Don't do anything if all operands are very simple. */
3550 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3551 || GET_RTX_CLASS (code) == '<')
3552 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3553 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3554 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3556 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3557 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3558 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3560 || (GET_RTX_CLASS (code) == '1'
3561 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3562 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3563 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3566 rtx cond, true, false;
3568 cond = if_then_else_cond (x, &true, &false);
3570 /* If everything is a comparison, what we have is highly unlikely
3571 to be simpler, so don't use it. */
3572 && ! (GET_RTX_CLASS (code) == '<'
3573 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3574 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3576 rtx cop1 = const0_rtx;
3577 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3579 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3582 /* Simplify the alternative arms; this may collapse the true and
3583 false arms to store-flag values. */
3584 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3585 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3587 /* If true and false are not general_operands, an if_then_else
3588 is unlikely to be simpler. */
3589 if (general_operand (true, VOIDmode)
3590 && general_operand (false, VOIDmode))
3592 /* Restarting if we generate a store-flag expression will cause
3593 us to loop. Just drop through in this case. */
3595 /* If the result values are STORE_FLAG_VALUE and zero, we can
3596 just make the comparison operation. */
3597 if (true == const_true_rtx && false == const0_rtx)
3598 x = gen_binary (cond_code, mode, cond, cop1);
3599 else if (true == const0_rtx && false == const_true_rtx)
3600 x = gen_binary (reverse_condition (cond_code),
3603 /* Likewise, we can make the negate of a comparison operation
3604 if the result values are - STORE_FLAG_VALUE and zero. */
3605 else if (GET_CODE (true) == CONST_INT
3606 && INTVAL (true) == - STORE_FLAG_VALUE
3607 && false == const0_rtx)
3608 x = gen_unary (NEG, mode, mode,
3609 gen_binary (cond_code, mode, cond, cop1));
3610 else if (GET_CODE (false) == CONST_INT
3611 && INTVAL (false) == - STORE_FLAG_VALUE
3612 && true == const0_rtx)
3613 x = gen_unary (NEG, mode, mode,
3614 gen_binary (reverse_condition (cond_code),
3617 return gen_rtx_IF_THEN_ELSE (mode,
3618 gen_binary (cond_code, VOIDmode,
3622 code = GET_CODE (x);
3623 op0_mode = VOIDmode;
3628 /* Try to fold this expression in case we have constants that weren't
3631 switch (GET_RTX_CLASS (code))
3634 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3638 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3639 if (cmp_mode == VOIDmode)
3640 cmp_mode = GET_MODE (XEXP (x, 1));
3641 temp = simplify_relational_operation (code, cmp_mode,
3642 XEXP (x, 0), XEXP (x, 1));
3644 #ifdef FLOAT_STORE_FLAG_VALUE
3645 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3647 if (temp == const0_rtx)
3648 temp = CONST0_RTX (mode);
3650 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3656 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3660 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3661 XEXP (x, 1), XEXP (x, 2));
3666 x = temp, code = GET_CODE (temp);
3668 /* First see if we can apply the inverse distributive law. */
3669 if (code == PLUS || code == MINUS
3670 || code == AND || code == IOR || code == XOR)
3672 x = apply_distributive_law (x);
3673 code = GET_CODE (x);
3676 /* If CODE is an associative operation not otherwise handled, see if we
3677 can associate some operands. This can win if they are constants or
3678 if they are logically related (i.e. (a & b) & a. */
3679 if ((code == PLUS || code == MINUS
3680 || code == MULT || code == AND || code == IOR || code == XOR
3681 || code == DIV || code == UDIV
3682 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3683 && INTEGRAL_MODE_P (mode))
3685 if (GET_CODE (XEXP (x, 0)) == code)
3687 rtx other = XEXP (XEXP (x, 0), 0);
3688 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3689 rtx inner_op1 = XEXP (x, 1);
3692 /* Make sure we pass the constant operand if any as the second
3693 one if this is a commutative operation. */
3694 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3696 rtx tem = inner_op0;
3697 inner_op0 = inner_op1;
3700 inner = simplify_binary_operation (code == MINUS ? PLUS
3701 : code == DIV ? MULT
3702 : code == UDIV ? MULT
3704 mode, inner_op0, inner_op1);
3706 /* For commutative operations, try the other pair if that one
3708 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3710 other = XEXP (XEXP (x, 0), 1);
3711 inner = simplify_binary_operation (code, mode,
3712 XEXP (XEXP (x, 0), 0),
3717 return gen_binary (code, mode, other, inner);
3721 /* A little bit of algebraic simplification here. */
3725 /* Ensure that our address has any ASHIFTs converted to MULT in case
3726 address-recognizing predicates are called later. */
3727 temp = make_compound_operation (XEXP (x, 0), MEM);
3728 SUBST (XEXP (x, 0), temp);
3732 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3733 is paradoxical. If we can't do that safely, then it becomes
3734 something nonsensical so that this combination won't take place. */
3736 if (GET_CODE (SUBREG_REG (x)) == MEM
3737 && (GET_MODE_SIZE (mode)
3738 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3740 rtx inner = SUBREG_REG (x);
3741 int endian_offset = 0;
3742 /* Don't change the mode of the MEM
3743 if that would change the meaning of the address. */
3744 if (MEM_VOLATILE_P (SUBREG_REG (x))
3745 || mode_dependent_address_p (XEXP (inner, 0)))
3746 return gen_rtx_CLOBBER (mode, const0_rtx);
3748 if (BYTES_BIG_ENDIAN)
3750 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3751 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3752 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3753 endian_offset -= (UNITS_PER_WORD
3754 - GET_MODE_SIZE (GET_MODE (inner)));
3756 /* Note if the plus_constant doesn't make a valid address
3757 then this combination won't be accepted. */
3758 x = gen_rtx_MEM (mode,
3759 plus_constant (XEXP (inner, 0),
3760 (SUBREG_WORD (x) * UNITS_PER_WORD
3762 MEM_COPY_ATTRIBUTES (x, inner);
3766 /* If we are in a SET_DEST, these other cases can't apply. */
3770 /* Changing mode twice with SUBREG => just change it once,
3771 or not at all if changing back to starting mode. */
3772 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3774 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3775 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3776 return SUBREG_REG (SUBREG_REG (x));
3778 SUBST_INT (SUBREG_WORD (x),
3779 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3780 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3783 /* SUBREG of a hard register => just change the register number
3784 and/or mode. If the hard register is not valid in that mode,
3785 suppress this combination. If the hard register is the stack,
3786 frame, or argument pointer, leave this as a SUBREG. */
3788 if (GET_CODE (SUBREG_REG (x)) == REG
3789 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3790 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3791 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3792 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3794 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3795 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3797 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3799 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3801 return gen_rtx_REG (mode,
3802 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3804 return gen_rtx_CLOBBER (mode, const0_rtx);
3807 /* For a constant, try to pick up the part we want. Handle a full
3808 word and low-order part. Only do this if we are narrowing
3809 the constant; if it is being widened, we have no idea what
3810 the extra bits will have been set to. */
3812 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3813 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3814 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3815 && GET_MODE_CLASS (mode) == MODE_INT)
3817 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3823 /* If we want a subreg of a constant, at offset 0,
3824 take the low bits. On a little-endian machine, that's
3825 always valid. On a big-endian machine, it's valid
3826 only if the constant's mode fits in one word. Note that we
3827 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3828 if (CONSTANT_P (SUBREG_REG (x))
3829 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3830 || ! WORDS_BIG_ENDIAN)
3831 ? SUBREG_WORD (x) == 0
3833 == ((GET_MODE_SIZE (op0_mode)
3834 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3836 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3837 && (! WORDS_BIG_ENDIAN
3838 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3839 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3841 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3842 since we are saying that the high bits don't matter. */
3843 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3844 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3846 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3847 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3848 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3849 return SUBREG_REG (x);
3852 /* Note that we cannot do any narrowing for non-constants since
3853 we might have been counting on using the fact that some bits were
3854 zero. We now do this in the SET. */
3859 /* (not (plus X -1)) can become (neg X). */
3860 if (GET_CODE (XEXP (x, 0)) == PLUS
3861 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3862 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3864 /* Similarly, (not (neg X)) is (plus X -1). */
3865 if (GET_CODE (XEXP (x, 0)) == NEG)
3866 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3869 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3870 if (GET_CODE (XEXP (x, 0)) == XOR
3871 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3872 && (temp = simplify_unary_operation (NOT, mode,
3873 XEXP (XEXP (x, 0), 1),
3875 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3877 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3878 other than 1, but that is not valid. We could do a similar
3879 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3880 but this doesn't seem common enough to bother with. */
3881 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3882 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3883 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3884 XEXP (XEXP (x, 0), 1));
3886 if (GET_CODE (XEXP (x, 0)) == SUBREG
3887 && subreg_lowpart_p (XEXP (x, 0))
3888 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3889 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3890 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3891 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3893 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3895 x = gen_rtx_ROTATE (inner_mode,
3896 gen_unary (NOT, inner_mode, inner_mode,
3898 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3899 return gen_lowpart_for_combine (mode, x);
3902 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3903 reversing the comparison code if valid. */
3904 if (STORE_FLAG_VALUE == -1
3905 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3906 && reversible_comparison_p (XEXP (x, 0)))
3907 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3908 mode, XEXP (XEXP (x, 0), 0),
3909 XEXP (XEXP (x, 0), 1));
3911 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3912 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3913 perform the above simplification. */
3915 if (STORE_FLAG_VALUE == -1
3916 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3917 && XEXP (x, 1) == const1_rtx
3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3919 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3920 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3922 /* Apply De Morgan's laws to reduce number of patterns for machines
3923 with negating logical insns (and-not, nand, etc.). If result has
3924 only one NOT, put it first, since that is how the patterns are
3927 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3929 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3931 if (GET_CODE (in1) == NOT)
3932 in1 = XEXP (in1, 0);
3934 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3936 if (GET_CODE (in2) == NOT)
3937 in2 = XEXP (in2, 0);
3938 else if (GET_CODE (in2) == CONST_INT
3939 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3940 in2 = GEN_INT (GET_MODE_MASK (mode) & ~INTVAL (in2));
3942 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3944 if (GET_CODE (in2) == NOT)
3947 in2 = in1; in1 = tem;
3950 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3956 /* (neg (plus X 1)) can become (not X). */
3957 if (GET_CODE (XEXP (x, 0)) == PLUS
3958 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3959 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3961 /* Similarly, (neg (not X)) is (plus X 1). */
3962 if (GET_CODE (XEXP (x, 0)) == NOT)
3963 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3965 /* (neg (minus X Y)) can become (minus Y X). */
3966 if (GET_CODE (XEXP (x, 0)) == MINUS
3967 && (! FLOAT_MODE_P (mode)
3968 /* x-y != -(y-x) with IEEE floating point. */
3969 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3971 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3972 XEXP (XEXP (x, 0), 0));
3974 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3975 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3976 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3977 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3979 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3980 if we can then eliminate the NEG (e.g.,
3981 if the operand is a constant). */
3983 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3985 temp = simplify_unary_operation (NEG, mode,
3986 XEXP (XEXP (x, 0), 0), mode);
3989 SUBST (XEXP (XEXP (x, 0), 0), temp);
3994 temp = expand_compound_operation (XEXP (x, 0));
3996 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3997 replaced by (lshiftrt X C). This will convert
3998 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4000 if (GET_CODE (temp) == ASHIFTRT
4001 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4002 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4003 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4004 INTVAL (XEXP (temp, 1)));
4006 /* If X has only a single bit that might be nonzero, say, bit I, convert
4007 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4008 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4009 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4010 or a SUBREG of one since we'd be making the expression more
4011 complex if it was just a register. */
4013 if (GET_CODE (temp) != REG
4014 && ! (GET_CODE (temp) == SUBREG
4015 && GET_CODE (SUBREG_REG (temp)) == REG)
4016 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4018 rtx temp1 = simplify_shift_const
4019 (NULL_RTX, ASHIFTRT, mode,
4020 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4021 GET_MODE_BITSIZE (mode) - 1 - i),
4022 GET_MODE_BITSIZE (mode) - 1 - i);
4024 /* If all we did was surround TEMP with the two shifts, we
4025 haven't improved anything, so don't use it. Otherwise,
4026 we are better off with TEMP1. */
4027 if (GET_CODE (temp1) != ASHIFTRT
4028 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4029 || XEXP (XEXP (temp1, 0), 0) != temp)
4035 /* We can't handle truncation to a partial integer mode here
4036 because we don't know the real bitsize of the partial
4038 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4041 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4042 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4043 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4045 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4046 GET_MODE_MASK (mode), NULL_RTX, 0));
4048 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4049 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4050 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4051 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4052 return XEXP (XEXP (x, 0), 0);
4054 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4055 (OP:SI foo:SI) if OP is NEG or ABS. */
4056 if ((GET_CODE (XEXP (x, 0)) == ABS
4057 || GET_CODE (XEXP (x, 0)) == NEG)
4058 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4059 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4060 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4061 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4062 XEXP (XEXP (XEXP (x, 0), 0), 0));
4064 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4066 if (GET_CODE (XEXP (x, 0)) == SUBREG
4067 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4068 && subreg_lowpart_p (XEXP (x, 0)))
4069 return SUBREG_REG (XEXP (x, 0));
4071 /* If we know that the value is already truncated, we can
4072 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4073 is nonzero for the corresponding modes. But don't do this
4074 for an (LSHIFTRT (MULT ...)) since this will cause problems
4075 with the umulXi3_highpart patterns. */
4076 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4077 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4078 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4079 >= GET_MODE_BITSIZE (mode) + 1
4080 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4081 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4082 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4084 /* A truncate of a comparison can be replaced with a subreg if
4085 STORE_FLAG_VALUE permits. This is like the previous test,
4086 but it works even if the comparison is done in a mode larger
4087 than HOST_BITS_PER_WIDE_INT. */
4088 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4089 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4090 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4091 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4093 /* Similarly, a truncate of a register whose value is a
4094 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4096 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4097 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4098 && (temp = get_last_value (XEXP (x, 0)))
4099 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4100 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4104 case FLOAT_TRUNCATE:
4105 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4106 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4107 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4108 return XEXP (XEXP (x, 0), 0);
4110 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4111 (OP:SF foo:SF) if OP is NEG or ABS. */
4112 if ((GET_CODE (XEXP (x, 0)) == ABS
4113 || GET_CODE (XEXP (x, 0)) == NEG)
4114 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4115 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4116 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4117 XEXP (XEXP (XEXP (x, 0), 0), 0));
4119 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4120 is (float_truncate:SF x). */
4121 if (GET_CODE (XEXP (x, 0)) == SUBREG
4122 && subreg_lowpart_p (XEXP (x, 0))
4123 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4124 return SUBREG_REG (XEXP (x, 0));
4129 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4130 using cc0, in which case we want to leave it as a COMPARE
4131 so we can distinguish it from a register-register-copy. */
4132 if (XEXP (x, 1) == const0_rtx)
4135 /* In IEEE floating point, x-0 is not the same as x. */
4136 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4137 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4139 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4145 /* (const (const X)) can become (const X). Do it this way rather than
4146 returning the inner CONST since CONST can be shared with a
4148 if (GET_CODE (XEXP (x, 0)) == CONST)
4149 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4154 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4155 can add in an offset. find_split_point will split this address up
4156 again if it doesn't match. */
4157 if (GET_CODE (XEXP (x, 0)) == HIGH
4158 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4164 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4165 outermost. That's because that's the way indexed addresses are
4166 supposed to appear. This code used to check many more cases, but
4167 they are now checked elsewhere. */
4168 if (GET_CODE (XEXP (x, 0)) == PLUS
4169 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4170 return gen_binary (PLUS, mode,
4171 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4173 XEXP (XEXP (x, 0), 1));
4175 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4176 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4177 bit-field and can be replaced by either a sign_extend or a
4178 sign_extract. The `and' may be a zero_extend and the two
4179 <c>, -<c> constants may be reversed. */
4180 if (GET_CODE (XEXP (x, 0)) == XOR
4181 && GET_CODE (XEXP (x, 1)) == CONST_INT
4182 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4183 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4184 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4185 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4186 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4187 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4188 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4189 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4190 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4191 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4192 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4193 == (unsigned int) i + 1))))
4194 return simplify_shift_const
4195 (NULL_RTX, ASHIFTRT, mode,
4196 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4197 XEXP (XEXP (XEXP (x, 0), 0), 0),
4198 GET_MODE_BITSIZE (mode) - (i + 1)),
4199 GET_MODE_BITSIZE (mode) - (i + 1));
4201 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4202 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4203 is 1. This produces better code than the alternative immediately
4205 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4206 && reversible_comparison_p (XEXP (x, 0))
4207 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4208 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4210 gen_unary (NEG, mode, mode,
4211 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4212 mode, XEXP (XEXP (x, 0), 0),
4213 XEXP (XEXP (x, 0), 1)));
4215 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4216 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4217 the bitsize of the mode - 1. This allows simplification of
4218 "a = (b & 8) == 0;" */
4219 if (XEXP (x, 1) == constm1_rtx
4220 && GET_CODE (XEXP (x, 0)) != REG
4221 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4222 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4223 && nonzero_bits (XEXP (x, 0), mode) == 1)
4224 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4225 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4226 gen_rtx_combine (XOR, mode,
4227 XEXP (x, 0), const1_rtx),
4228 GET_MODE_BITSIZE (mode) - 1),
4229 GET_MODE_BITSIZE (mode) - 1);
4231 /* If we are adding two things that have no bits in common, convert
4232 the addition into an IOR. This will often be further simplified,
4233 for example in cases like ((a & 1) + (a & 2)), which can
4236 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4237 && (nonzero_bits (XEXP (x, 0), mode)
4238 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4240 /* Try to simplify the expression further. */
4241 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4242 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4244 /* If we could, great. If not, do not go ahead with the IOR
4245 replacement, since PLUS appears in many special purpose
4246 address arithmetic instructions. */
4247 if (GET_CODE (temp) != CLOBBER && temp != tor)
4253 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4254 by reversing the comparison code if valid. */
4255 if (STORE_FLAG_VALUE == 1
4256 && XEXP (x, 0) == const1_rtx
4257 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4258 && reversible_comparison_p (XEXP (x, 1)))
4259 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), mode,
4260 XEXP (XEXP (x, 1), 0),
4261 XEXP (XEXP (x, 1), 1));
4263 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4264 (and <foo> (const_int pow2-1)) */
4265 if (GET_CODE (XEXP (x, 1)) == AND
4266 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4267 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4268 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4269 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4270 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4272 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4274 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4275 return gen_binary (MINUS, mode,
4276 gen_binary (MINUS, mode, XEXP (x, 0),
4277 XEXP (XEXP (x, 1), 0)),
4278 XEXP (XEXP (x, 1), 1));
4282 /* If we have (mult (plus A B) C), apply the distributive law and then
4283 the inverse distributive law to see if things simplify. This
4284 occurs mostly in addresses, often when unrolling loops. */
4286 if (GET_CODE (XEXP (x, 0)) == PLUS)
4288 x = apply_distributive_law
4289 (gen_binary (PLUS, mode,
4290 gen_binary (MULT, mode,
4291 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4292 gen_binary (MULT, mode,
4293 XEXP (XEXP (x, 0), 1),
4294 copy_rtx (XEXP (x, 1)))));
4296 if (GET_CODE (x) != MULT)
4302 /* If this is a divide by a power of two, treat it as a shift if
4303 its first operand is a shift. */
4304 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4305 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4306 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4307 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4308 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4309 || GET_CODE (XEXP (x, 0)) == ROTATE
4310 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4311 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4315 case GT: case GTU: case GE: case GEU:
4316 case LT: case LTU: case LE: case LEU:
4317 /* If the first operand is a condition code, we can't do anything
4319 if (GET_CODE (XEXP (x, 0)) == COMPARE
4320 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4322 && XEXP (x, 0) != cc0_rtx
4326 rtx op0 = XEXP (x, 0);
4327 rtx op1 = XEXP (x, 1);
4328 enum rtx_code new_code;
4330 if (GET_CODE (op0) == COMPARE)
4331 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4333 /* Simplify our comparison, if possible. */
4334 new_code = simplify_comparison (code, &op0, &op1);
4336 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4337 if only the low-order bit is possibly nonzero in X (such as when
4338 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4339 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4340 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4343 Remove any ZERO_EXTRACT we made when thinking this was a
4344 comparison. It may now be simpler to use, e.g., an AND. If a
4345 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4346 the call to make_compound_operation in the SET case. */
4348 if (STORE_FLAG_VALUE == 1
4349 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4350 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4351 return gen_lowpart_for_combine (mode,
4352 expand_compound_operation (op0));
4354 else if (STORE_FLAG_VALUE == 1
4355 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4356 && op1 == const0_rtx
4357 && (num_sign_bit_copies (op0, mode)
4358 == GET_MODE_BITSIZE (mode)))
4360 op0 = expand_compound_operation (op0);
4361 return gen_unary (NEG, mode, mode,
4362 gen_lowpart_for_combine (mode, op0));
4365 else if (STORE_FLAG_VALUE == 1
4366 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4367 && op1 == const0_rtx
4368 && nonzero_bits (op0, mode) == 1)
4370 op0 = expand_compound_operation (op0);
4371 return gen_binary (XOR, mode,
4372 gen_lowpart_for_combine (mode, op0),
4376 else if (STORE_FLAG_VALUE == 1
4377 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4378 && op1 == const0_rtx
4379 && (num_sign_bit_copies (op0, mode)
4380 == GET_MODE_BITSIZE (mode)))
4382 op0 = expand_compound_operation (op0);
4383 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4386 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4388 if (STORE_FLAG_VALUE == -1
4389 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4390 && op1 == const0_rtx
4391 && (num_sign_bit_copies (op0, mode)
4392 == GET_MODE_BITSIZE (mode)))
4393 return gen_lowpart_for_combine (mode,
4394 expand_compound_operation (op0));
4396 else if (STORE_FLAG_VALUE == -1
4397 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4398 && op1 == const0_rtx
4399 && nonzero_bits (op0, mode) == 1)
4401 op0 = expand_compound_operation (op0);
4402 return gen_unary (NEG, mode, mode,
4403 gen_lowpart_for_combine (mode, op0));
4406 else if (STORE_FLAG_VALUE == -1
4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4408 && op1 == const0_rtx
4409 && (num_sign_bit_copies (op0, mode)
4410 == GET_MODE_BITSIZE (mode)))
4412 op0 = expand_compound_operation (op0);
4413 return gen_unary (NOT, mode, mode,
4414 gen_lowpart_for_combine (mode, op0));
4417 /* If X is 0/1, (eq X 0) is X-1. */
4418 else if (STORE_FLAG_VALUE == -1
4419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4420 && op1 == const0_rtx
4421 && nonzero_bits (op0, mode) == 1)
4423 op0 = expand_compound_operation (op0);
4424 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4427 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4428 one bit that might be nonzero, we can convert (ne x 0) to
4429 (ashift x c) where C puts the bit in the sign bit. Remove any
4430 AND with STORE_FLAG_VALUE when we are done, since we are only
4431 going to test the sign bit. */
4432 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4433 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4434 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4435 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4436 && op1 == const0_rtx
4437 && mode == GET_MODE (op0)
4438 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4440 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4441 expand_compound_operation (op0),
4442 GET_MODE_BITSIZE (mode) - 1 - i);
4443 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4449 /* If the code changed, return a whole new comparison. */
4450 if (new_code != code)
4451 return gen_rtx_combine (new_code, mode, op0, op1);
4453 /* Otherwise, keep this operation, but maybe change its operands.
4454 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4455 SUBST (XEXP (x, 0), op0);
4456 SUBST (XEXP (x, 1), op1);
4461 return simplify_if_then_else (x);
4467 /* If we are processing SET_DEST, we are done. */
4471 return expand_compound_operation (x);
4474 return simplify_set (x);
4479 return simplify_logical (x, last);
4482 /* (abs (neg <foo>)) -> (abs <foo>) */
4483 if (GET_CODE (XEXP (x, 0)) == NEG)
4484 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4486 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4488 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4491 /* If operand is something known to be positive, ignore the ABS. */
4492 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4493 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4494 <= HOST_BITS_PER_WIDE_INT)
4495 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4496 & ((HOST_WIDE_INT) 1
4497 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4501 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4502 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4503 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4508 /* (ffs (*_extend <X>)) = (ffs <X>) */
4509 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4510 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4511 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4515 /* (float (sign_extend <X>)) = (float <X>). */
4516 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4517 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4525 /* If this is a shift by a constant amount, simplify it. */
4526 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4527 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4528 INTVAL (XEXP (x, 1)));
4530 #ifdef SHIFT_COUNT_TRUNCATED
4531 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4533 force_to_mode (XEXP (x, 1), GET_MODE (x),
4535 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4544 rtx op0 = XEXP (x, 0);
4545 rtx op1 = XEXP (x, 1);
4548 if (GET_CODE (op1) != PARALLEL)
4550 len = XVECLEN (op1, 0);
4552 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4553 && GET_CODE (op0) == VEC_CONCAT)
4555 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4557 /* Try to find the element in the VEC_CONCAT. */
4560 if (GET_MODE (op0) == GET_MODE (x))
4562 if (GET_CODE (op0) == VEC_CONCAT)
4564 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4565 if (op0_size < offset)
4566 op0 = XEXP (op0, 0);
4570 op0 = XEXP (op0, 1);
4588 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4591 simplify_if_then_else (x)
4594 enum machine_mode mode = GET_MODE (x);
4595 rtx cond = XEXP (x, 0);
4596 rtx true = XEXP (x, 1);
4597 rtx false = XEXP (x, 2);
4598 enum rtx_code true_code = GET_CODE (cond);
4599 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4603 /* Simplify storing of the truth value. */
4604 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4605 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4607 /* Also when the truth value has to be reversed. */
4608 if (comparison_p && reversible_comparison_p (cond)
4609 && true == const0_rtx && false == const_true_rtx)
4610 return gen_binary (reverse_condition (true_code),
4611 mode, XEXP (cond, 0), XEXP (cond, 1));
4613 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4614 in it is being compared against certain values. Get the true and false
4615 comparisons and see if that says anything about the value of each arm. */
4617 if (comparison_p && reversible_comparison_p (cond)
4618 && GET_CODE (XEXP (cond, 0)) == REG)
4621 rtx from = XEXP (cond, 0);
4622 enum rtx_code false_code = reverse_condition (true_code);
4623 rtx true_val = XEXP (cond, 1);
4624 rtx false_val = true_val;
4627 /* If FALSE_CODE is EQ, swap the codes and arms. */
4629 if (false_code == EQ)
4631 swapped = 1, true_code = EQ, false_code = NE;
4632 temp = true, true = false, false = temp;
4635 /* If we are comparing against zero and the expression being tested has
4636 only a single bit that might be nonzero, that is its value when it is
4637 not equal to zero. Similarly if it is known to be -1 or 0. */
4639 if (true_code == EQ && true_val == const0_rtx
4640 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4641 false_code = EQ, false_val = GEN_INT (nzb);
4642 else if (true_code == EQ && true_val == const0_rtx
4643 && (num_sign_bit_copies (from, GET_MODE (from))
4644 == GET_MODE_BITSIZE (GET_MODE (from))))
4645 false_code = EQ, false_val = constm1_rtx;
4647 /* Now simplify an arm if we know the value of the register in the
4648 branch and it is used in the arm. Be careful due to the potential
4649 of locally-shared RTL. */
4651 if (reg_mentioned_p (from, true))
4652 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4653 pc_rtx, pc_rtx, 0, 0);
4654 if (reg_mentioned_p (from, false))
4655 false = subst (known_cond (copy_rtx (false), false_code,
4657 pc_rtx, pc_rtx, 0, 0);
4659 SUBST (XEXP (x, 1), swapped ? false : true);
4660 SUBST (XEXP (x, 2), swapped ? true : false);
4662 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4665 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4666 reversed, do so to avoid needing two sets of patterns for
4667 subtract-and-branch insns. Similarly if we have a constant in the true
4668 arm, the false arm is the same as the first operand of the comparison, or
4669 the false arm is more complicated than the true arm. */
4671 if (comparison_p && reversible_comparison_p (cond)
4673 || (CONSTANT_P (true)
4674 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4675 || true == const0_rtx
4676 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4677 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4678 || (GET_CODE (true) == SUBREG
4679 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4680 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4681 || reg_mentioned_p (true, false)
4682 || rtx_equal_p (false, XEXP (cond, 0))))
4684 true_code = reverse_condition (true_code);
4686 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4689 SUBST (XEXP (x, 1), false);
4690 SUBST (XEXP (x, 2), true);
4692 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4694 /* It is possible that the conditional has been simplified out. */
4695 true_code = GET_CODE (cond);
4696 comparison_p = GET_RTX_CLASS (true_code) == '<';
4699 /* If the two arms are identical, we don't need the comparison. */
4701 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4704 /* Convert a == b ? b : a to "a". */
4705 if (true_code == EQ && ! side_effects_p (cond)
4706 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4707 && rtx_equal_p (XEXP (cond, 0), false)
4708 && rtx_equal_p (XEXP (cond, 1), true))
4710 else if (true_code == NE && ! side_effects_p (cond)
4711 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4712 && rtx_equal_p (XEXP (cond, 0), true)
4713 && rtx_equal_p (XEXP (cond, 1), false))
4716 /* Look for cases where we have (abs x) or (neg (abs X)). */
4718 if (GET_MODE_CLASS (mode) == MODE_INT
4719 && GET_CODE (false) == NEG
4720 && rtx_equal_p (true, XEXP (false, 0))
4722 && rtx_equal_p (true, XEXP (cond, 0))
4723 && ! side_effects_p (true))
4728 return gen_unary (ABS, mode, mode, true);
4731 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4736 /* Look for MIN or MAX. */
4738 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4740 && rtx_equal_p (XEXP (cond, 0), true)
4741 && rtx_equal_p (XEXP (cond, 1), false)
4742 && ! side_effects_p (cond))
4747 return gen_binary (SMAX, mode, true, false);
4750 return gen_binary (SMIN, mode, true, false);
4753 return gen_binary (UMAX, mode, true, false);
4756 return gen_binary (UMIN, mode, true, false);
4761 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4762 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4763 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4764 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4765 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4766 neither 1 or -1, but it isn't worth checking for. */
4768 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4769 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4771 rtx t = make_compound_operation (true, SET);
4772 rtx f = make_compound_operation (false, SET);
4773 rtx cond_op0 = XEXP (cond, 0);
4774 rtx cond_op1 = XEXP (cond, 1);
4775 enum rtx_code op = NIL, extend_op = NIL;
4776 enum machine_mode m = mode;
4777 rtx z = 0, c1 = NULL_RTX;
4779 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4780 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4781 || GET_CODE (t) == ASHIFT
4782 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4783 && rtx_equal_p (XEXP (t, 0), f))
4784 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4786 /* If an identity-zero op is commutative, check whether there
4787 would be a match if we swapped the operands. */
4788 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4789 || GET_CODE (t) == XOR)
4790 && rtx_equal_p (XEXP (t, 1), f))
4791 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4792 else if (GET_CODE (t) == SIGN_EXTEND
4793 && (GET_CODE (XEXP (t, 0)) == PLUS
4794 || GET_CODE (XEXP (t, 0)) == MINUS
4795 || GET_CODE (XEXP (t, 0)) == IOR
4796 || GET_CODE (XEXP (t, 0)) == XOR
4797 || GET_CODE (XEXP (t, 0)) == ASHIFT
4798 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4799 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4800 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4801 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4802 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4803 && (num_sign_bit_copies (f, GET_MODE (f))
4804 > (GET_MODE_BITSIZE (mode)
4805 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4807 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4808 extend_op = SIGN_EXTEND;
4809 m = GET_MODE (XEXP (t, 0));
4811 else if (GET_CODE (t) == SIGN_EXTEND
4812 && (GET_CODE (XEXP (t, 0)) == PLUS
4813 || GET_CODE (XEXP (t, 0)) == IOR
4814 || GET_CODE (XEXP (t, 0)) == XOR)
4815 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4816 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4817 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4818 && (num_sign_bit_copies (f, GET_MODE (f))
4819 > (GET_MODE_BITSIZE (mode)
4820 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4822 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4823 extend_op = SIGN_EXTEND;
4824 m = GET_MODE (XEXP (t, 0));
4826 else if (GET_CODE (t) == ZERO_EXTEND
4827 && (GET_CODE (XEXP (t, 0)) == PLUS
4828 || GET_CODE (XEXP (t, 0)) == MINUS
4829 || GET_CODE (XEXP (t, 0)) == IOR
4830 || GET_CODE (XEXP (t, 0)) == XOR
4831 || GET_CODE (XEXP (t, 0)) == ASHIFT
4832 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4833 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4834 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4835 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4836 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4837 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4838 && ((nonzero_bits (f, GET_MODE (f))
4839 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4842 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4843 extend_op = ZERO_EXTEND;
4844 m = GET_MODE (XEXP (t, 0));
4846 else if (GET_CODE (t) == ZERO_EXTEND
4847 && (GET_CODE (XEXP (t, 0)) == PLUS
4848 || GET_CODE (XEXP (t, 0)) == IOR
4849 || GET_CODE (XEXP (t, 0)) == XOR)
4850 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4851 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4852 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4853 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4854 && ((nonzero_bits (f, GET_MODE (f))
4855 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4858 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4859 extend_op = ZERO_EXTEND;
4860 m = GET_MODE (XEXP (t, 0));
4865 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4866 pc_rtx, pc_rtx, 0, 0);
4867 temp = gen_binary (MULT, m, temp,
4868 gen_binary (MULT, m, c1, const_true_rtx));
4869 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4870 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4872 if (extend_op != NIL)
4873 temp = gen_unary (extend_op, mode, m, temp);
4879 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4880 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4881 negation of a single bit, we can convert this operation to a shift. We
4882 can actually do this more generally, but it doesn't seem worth it. */
4884 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4885 && false == const0_rtx && GET_CODE (true) == CONST_INT
4886 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4887 && (i = exact_log2 (INTVAL (true))) >= 0)
4888 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4889 == GET_MODE_BITSIZE (mode))
4890 && (i = exact_log2 (-INTVAL (true))) >= 0)))
4892 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4893 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4898 /* Simplify X, a SET expression. Return the new expression. */
4904 rtx src = SET_SRC (x);
4905 rtx dest = SET_DEST (x);
4906 enum machine_mode mode
4907 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4911 /* (set (pc) (return)) gets written as (return). */
4912 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4915 /* Now that we know for sure which bits of SRC we are using, see if we can
4916 simplify the expression for the object knowing that we only need the
4919 if (GET_MODE_CLASS (mode) == MODE_INT)
4921 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4922 SUBST (SET_SRC (x), src);
4925 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4926 the comparison result and try to simplify it unless we already have used
4927 undobuf.other_insn. */
4928 if ((GET_CODE (src) == COMPARE
4933 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4934 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4935 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4936 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4938 enum rtx_code old_code = GET_CODE (*cc_use);
4939 enum rtx_code new_code;
4941 int other_changed = 0;
4942 enum machine_mode compare_mode = GET_MODE (dest);
4944 if (GET_CODE (src) == COMPARE)
4945 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4947 op0 = src, op1 = const0_rtx;
4949 /* Simplify our comparison, if possible. */
4950 new_code = simplify_comparison (old_code, &op0, &op1);
4952 #ifdef EXTRA_CC_MODES
4953 /* If this machine has CC modes other than CCmode, check to see if we
4954 need to use a different CC mode here. */
4955 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4956 #endif /* EXTRA_CC_MODES */
4958 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4959 /* If the mode changed, we have to change SET_DEST, the mode in the
4960 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4961 a hard register, just build new versions with the proper mode. If it
4962 is a pseudo, we lose unless it is only time we set the pseudo, in
4963 which case we can safely change its mode. */
4964 if (compare_mode != GET_MODE (dest))
4966 unsigned int regno = REGNO (dest);
4967 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4969 if (regno < FIRST_PSEUDO_REGISTER
4970 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4972 if (regno >= FIRST_PSEUDO_REGISTER)
4973 SUBST (regno_reg_rtx[regno], new_dest);
4975 SUBST (SET_DEST (x), new_dest);
4976 SUBST (XEXP (*cc_use, 0), new_dest);
4984 /* If the code changed, we have to build a new comparison in
4985 undobuf.other_insn. */
4986 if (new_code != old_code)
4988 unsigned HOST_WIDE_INT mask;
4990 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4993 /* If the only change we made was to change an EQ into an NE or
4994 vice versa, OP0 has only one bit that might be nonzero, and OP1
4995 is zero, check if changing the user of the condition code will
4996 produce a valid insn. If it won't, we can keep the original code
4997 in that insn by surrounding our operation with an XOR. */
4999 if (((old_code == NE && new_code == EQ)
5000 || (old_code == EQ && new_code == NE))
5001 && ! other_changed && op1 == const0_rtx
5002 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5003 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5005 rtx pat = PATTERN (other_insn), note = 0;
5007 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5008 && ! check_asm_operands (pat)))
5010 PUT_CODE (*cc_use, old_code);
5013 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5021 undobuf.other_insn = other_insn;
5024 /* If we are now comparing against zero, change our source if
5025 needed. If we do not use cc0, we always have a COMPARE. */
5026 if (op1 == const0_rtx && dest == cc0_rtx)
5028 SUBST (SET_SRC (x), op0);
5034 /* Otherwise, if we didn't previously have a COMPARE in the
5035 correct mode, we need one. */
5036 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5039 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5044 /* Otherwise, update the COMPARE if needed. */
5045 SUBST (XEXP (src, 0), op0);
5046 SUBST (XEXP (src, 1), op1);
5051 /* Get SET_SRC in a form where we have placed back any
5052 compound expressions. Then do the checks below. */
5053 src = make_compound_operation (src, SET);
5054 SUBST (SET_SRC (x), src);
5057 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5058 and X being a REG or (subreg (reg)), we may be able to convert this to
5059 (set (subreg:m2 x) (op)).
5061 We can always do this if M1 is narrower than M2 because that means that
5062 we only care about the low bits of the result.
5064 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5065 perform a narrower operation than requested since the high-order bits will
5066 be undefined. On machine where it is defined, this transformation is safe
5067 as long as M1 and M2 have the same number of words. */
5069 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5070 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5071 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5073 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5074 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5075 #ifndef WORD_REGISTER_OPERATIONS
5076 && (GET_MODE_SIZE (GET_MODE (src))
5077 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5079 #ifdef CLASS_CANNOT_CHANGE_MODE
5080 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5081 && (TEST_HARD_REG_BIT
5082 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5084 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5085 GET_MODE (SUBREG_REG (src))))
5087 && (GET_CODE (dest) == REG
5088 || (GET_CODE (dest) == SUBREG
5089 && GET_CODE (SUBREG_REG (dest)) == REG)))
5091 SUBST (SET_DEST (x),
5092 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5094 SUBST (SET_SRC (x), SUBREG_REG (src));
5096 src = SET_SRC (x), dest = SET_DEST (x);
5099 #ifdef LOAD_EXTEND_OP
5100 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5101 would require a paradoxical subreg. Replace the subreg with a
5102 zero_extend to avoid the reload that would otherwise be required. */
5104 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5105 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5106 && SUBREG_WORD (src) == 0
5107 && (GET_MODE_SIZE (GET_MODE (src))
5108 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5109 && GET_CODE (SUBREG_REG (src)) == MEM)
5112 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5113 GET_MODE (src), XEXP (src, 0)));
5119 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5120 are comparing an item known to be 0 or -1 against 0, use a logical
5121 operation instead. Check for one of the arms being an IOR of the other
5122 arm with some value. We compute three terms to be IOR'ed together. In
5123 practice, at most two will be nonzero. Then we do the IOR's. */
5125 if (GET_CODE (dest) != PC
5126 && GET_CODE (src) == IF_THEN_ELSE
5127 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5128 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5129 && XEXP (XEXP (src, 0), 1) == const0_rtx
5130 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5131 #ifdef HAVE_conditional_move
5132 && ! can_conditionally_move_p (GET_MODE (src))
5134 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5135 GET_MODE (XEXP (XEXP (src, 0), 0)))
5136 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5137 && ! side_effects_p (src))
5139 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5140 ? XEXP (src, 1) : XEXP (src, 2));
5141 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5142 ? XEXP (src, 2) : XEXP (src, 1));
5143 rtx term1 = const0_rtx, term2, term3;
5145 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5146 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5147 else if (GET_CODE (true) == IOR
5148 && rtx_equal_p (XEXP (true, 1), false))
5149 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5150 else if (GET_CODE (false) == IOR
5151 && rtx_equal_p (XEXP (false, 0), true))
5152 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5153 else if (GET_CODE (false) == IOR
5154 && rtx_equal_p (XEXP (false, 1), true))
5155 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5157 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5158 term3 = gen_binary (AND, GET_MODE (src),
5159 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5160 XEXP (XEXP (src, 0), 0)),
5164 gen_binary (IOR, GET_MODE (src),
5165 gen_binary (IOR, GET_MODE (src), term1, term2),
5171 #ifdef HAVE_conditional_arithmetic
5172 /* If we have conditional arithmetic and the operand of a SET is
5173 a conditional expression, replace this with an IF_THEN_ELSE.
5174 We can either have a conditional expression or a MULT of that expression
5176 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5177 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5178 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5179 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5180 || (GET_CODE (XEXP (src, 0)) == MULT
5181 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5182 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5184 rtx cond = XEXP (src, 0);
5185 rtx true_val = const1_rtx;
5186 rtx false_arm, true_arm;
5188 if (GET_CODE (cond) == MULT)
5190 true_val = XEXP (cond, 1);
5191 cond = XEXP (cond, 0);
5194 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5196 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5197 GET_MODE (XEXP (src, 0)), true_val);
5198 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5199 GET_MODE (XEXP (src, 0)), const0_rtx);
5203 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5204 true_val, XEXP (src, 1));
5205 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5206 const0_rtx, XEXP (src, 1));
5209 /* Canonicalize if true_arm is the simpler one. */
5210 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5211 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5212 && reversible_comparison_p (cond))
5214 rtx temp = true_arm;
5216 true_arm = false_arm;
5219 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5220 GET_MODE (cond), XEXP (cond, 0),
5224 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5225 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5228 true_arm, false_arm);
5229 SUBST (SET_SRC (x), src);
5233 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5234 whole thing fail. */
5235 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5237 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5240 /* Convert this into a field assignment operation, if possible. */
5241 return make_field_assignment (x);
5244 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5245 result. LAST is nonzero if this is the last retry. */
5248 simplify_logical (x, last)
5252 enum machine_mode mode = GET_MODE (x);
5253 rtx op0 = XEXP (x, 0);
5254 rtx op1 = XEXP (x, 1);
5256 switch (GET_CODE (x))
5259 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5260 insn (and may simplify more). */
5261 if (GET_CODE (op0) == XOR
5262 && rtx_equal_p (XEXP (op0, 0), op1)
5263 && ! side_effects_p (op1))
5264 x = gen_binary (AND, mode,
5265 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5267 if (GET_CODE (op0) == XOR
5268 && rtx_equal_p (XEXP (op0, 1), op1)
5269 && ! side_effects_p (op1))
5270 x = gen_binary (AND, mode,
5271 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5273 /* Similarly for (~(A ^ B)) & A. */
5274 if (GET_CODE (op0) == NOT
5275 && GET_CODE (XEXP (op0, 0)) == XOR
5276 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5277 && ! side_effects_p (op1))
5278 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5280 if (GET_CODE (op0) == NOT
5281 && GET_CODE (XEXP (op0, 0)) == XOR
5282 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5283 && ! side_effects_p (op1))
5284 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5286 /* We can call simplify_and_const_int only if we don't lose
5287 any (sign) bits when converting INTVAL (op1) to
5288 "unsigned HOST_WIDE_INT". */
5289 if (GET_CODE (op1) == CONST_INT
5290 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5291 || INTVAL (op1) > 0))
5293 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5295 /* If we have (ior (and (X C1) C2)) and the next restart would be
5296 the last, simplify this by making C1 as small as possible
5299 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5300 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5301 && GET_CODE (op1) == CONST_INT)
5302 return gen_binary (IOR, mode,
5303 gen_binary (AND, mode, XEXP (op0, 0),
5304 GEN_INT (INTVAL (XEXP (op0, 1))
5305 & ~INTVAL (op1))), op1);
5307 if (GET_CODE (x) != AND)
5310 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5311 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5312 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5315 /* Convert (A | B) & A to A. */
5316 if (GET_CODE (op0) == IOR
5317 && (rtx_equal_p (XEXP (op0, 0), op1)
5318 || rtx_equal_p (XEXP (op0, 1), op1))
5319 && ! side_effects_p (XEXP (op0, 0))
5320 && ! side_effects_p (XEXP (op0, 1)))
5323 /* In the following group of tests (and those in case IOR below),
5324 we start with some combination of logical operations and apply
5325 the distributive law followed by the inverse distributive law.
5326 Most of the time, this results in no change. However, if some of
5327 the operands are the same or inverses of each other, simplifications
5330 For example, (and (ior A B) (not B)) can occur as the result of
5331 expanding a bit field assignment. When we apply the distributive
5332 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5333 which then simplifies to (and (A (not B))).
5335 If we have (and (ior A B) C), apply the distributive law and then
5336 the inverse distributive law to see if things simplify. */
5338 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5340 x = apply_distributive_law
5341 (gen_binary (GET_CODE (op0), mode,
5342 gen_binary (AND, mode, XEXP (op0, 0), op1),
5343 gen_binary (AND, mode, XEXP (op0, 1),
5345 if (GET_CODE (x) != AND)
5349 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5350 return apply_distributive_law
5351 (gen_binary (GET_CODE (op1), mode,
5352 gen_binary (AND, mode, XEXP (op1, 0), op0),
5353 gen_binary (AND, mode, XEXP (op1, 1),
5356 /* Similarly, taking advantage of the fact that
5357 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5359 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5360 return apply_distributive_law
5361 (gen_binary (XOR, mode,
5362 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5363 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5366 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5367 return apply_distributive_law
5368 (gen_binary (XOR, mode,
5369 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5370 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5374 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5375 if (GET_CODE (op1) == CONST_INT
5376 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5377 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5380 /* Convert (A & B) | A to A. */
5381 if (GET_CODE (op0) == AND
5382 && (rtx_equal_p (XEXP (op0, 0), op1)
5383 || rtx_equal_p (XEXP (op0, 1), op1))
5384 && ! side_effects_p (XEXP (op0, 0))
5385 && ! side_effects_p (XEXP (op0, 1)))
5388 /* If we have (ior (and A B) C), apply the distributive law and then
5389 the inverse distributive law to see if things simplify. */
5391 if (GET_CODE (op0) == AND)
5393 x = apply_distributive_law
5394 (gen_binary (AND, mode,
5395 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5396 gen_binary (IOR, mode, XEXP (op0, 1),
5399 if (GET_CODE (x) != IOR)
5403 if (GET_CODE (op1) == AND)
5405 x = apply_distributive_law
5406 (gen_binary (AND, mode,
5407 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5408 gen_binary (IOR, mode, XEXP (op1, 1),
5411 if (GET_CODE (x) != IOR)
5415 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5416 mode size to (rotate A CX). */
5418 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5419 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5420 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5421 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5422 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5423 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5424 == GET_MODE_BITSIZE (mode)))
5425 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5426 (GET_CODE (op0) == ASHIFT
5427 ? XEXP (op0, 1) : XEXP (op1, 1)));
5429 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5430 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5431 does not affect any of the bits in OP1, it can really be done
5432 as a PLUS and we can associate. We do this by seeing if OP1
5433 can be safely shifted left C bits. */
5434 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5435 && GET_CODE (XEXP (op0, 0)) == PLUS
5436 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5437 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5438 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5440 int count = INTVAL (XEXP (op0, 1));
5441 HOST_WIDE_INT mask = INTVAL (op1) << count;
5443 if (mask >> count == INTVAL (op1)
5444 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5446 SUBST (XEXP (XEXP (op0, 0), 1),
5447 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5454 /* If we are XORing two things that have no bits in common,
5455 convert them into an IOR. This helps to detect rotation encoded
5456 using those methods and possibly other simplifications. */
5458 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5459 && (nonzero_bits (op0, mode)
5460 & nonzero_bits (op1, mode)) == 0)
5461 return (gen_binary (IOR, mode, op0, op1));
5463 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5464 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5467 int num_negated = 0;
5469 if (GET_CODE (op0) == NOT)
5470 num_negated++, op0 = XEXP (op0, 0);
5471 if (GET_CODE (op1) == NOT)
5472 num_negated++, op1 = XEXP (op1, 0);
5474 if (num_negated == 2)
5476 SUBST (XEXP (x, 0), op0);
5477 SUBST (XEXP (x, 1), op1);
5479 else if (num_negated == 1)
5480 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5483 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5484 correspond to a machine insn or result in further simplifications
5485 if B is a constant. */
5487 if (GET_CODE (op0) == AND
5488 && rtx_equal_p (XEXP (op0, 1), op1)
5489 && ! side_effects_p (op1))
5490 return gen_binary (AND, mode,
5491 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5494 else if (GET_CODE (op0) == AND
5495 && rtx_equal_p (XEXP (op0, 0), op1)
5496 && ! side_effects_p (op1))
5497 return gen_binary (AND, mode,
5498 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5501 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5502 comparison if STORE_FLAG_VALUE is 1. */
5503 if (STORE_FLAG_VALUE == 1
5504 && op1 == const1_rtx
5505 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5506 && reversible_comparison_p (op0))
5507 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5508 mode, XEXP (op0, 0), XEXP (op0, 1));
5510 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5511 is (lt foo (const_int 0)), so we can perform the above
5512 simplification if STORE_FLAG_VALUE is 1. */
5514 if (STORE_FLAG_VALUE == 1
5515 && op1 == const1_rtx
5516 && GET_CODE (op0) == LSHIFTRT
5517 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5518 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5519 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5521 /* (xor (comparison foo bar) (const_int sign-bit))
5522 when STORE_FLAG_VALUE is the sign bit. */
5523 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5524 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5525 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5526 && op1 == const_true_rtx
5527 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5528 && reversible_comparison_p (op0))
5529 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5530 mode, XEXP (op0, 0), XEXP (op0, 1));
5541 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5542 operations" because they can be replaced with two more basic operations.
5543 ZERO_EXTEND is also considered "compound" because it can be replaced with
5544 an AND operation, which is simpler, though only one operation.
5546 The function expand_compound_operation is called with an rtx expression
5547 and will convert it to the appropriate shifts and AND operations,
5548 simplifying at each stage.
5550 The function make_compound_operation is called to convert an expression
5551 consisting of shifts and ANDs into the equivalent compound expression.
5552 It is the inverse of this function, loosely speaking. */
5555 expand_compound_operation (x)
5558 unsigned HOST_WIDE_INT pos = 0, len;
5560 unsigned int modewidth;
5563 switch (GET_CODE (x))
5568 /* We can't necessarily use a const_int for a multiword mode;
5569 it depends on implicitly extending the value.
5570 Since we don't know the right way to extend it,
5571 we can't tell whether the implicit way is right.
5573 Even for a mode that is no wider than a const_int,
5574 we can't win, because we need to sign extend one of its bits through
5575 the rest of it, and we don't know which bit. */
5576 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5579 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5580 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5581 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5582 reloaded. If not for that, MEM's would very rarely be safe.
5584 Reject MODEs bigger than a word, because we might not be able
5585 to reference a two-register group starting with an arbitrary register
5586 (and currently gen_lowpart might crash for a SUBREG). */
5588 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5591 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5592 /* If the inner object has VOIDmode (the only way this can happen
5593 is if it is a ASM_OPERANDS), we can't do anything since we don't
5594 know how much masking to do. */
5603 /* If the operand is a CLOBBER, just return it. */
5604 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5607 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5608 || GET_CODE (XEXP (x, 2)) != CONST_INT
5609 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5612 len = INTVAL (XEXP (x, 1));
5613 pos = INTVAL (XEXP (x, 2));
5615 /* If this goes outside the object being extracted, replace the object
5616 with a (use (mem ...)) construct that only combine understands
5617 and is used only for this purpose. */
5618 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5619 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5621 if (BITS_BIG_ENDIAN)
5622 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5629 /* Convert sign extension to zero extension, if we know that the high
5630 bit is not set, as this is easier to optimize. It will be converted
5631 back to cheaper alternative in make_extraction. */
5632 if (GET_CODE (x) == SIGN_EXTEND
5633 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5634 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5635 & ~(((unsigned HOST_WIDE_INT)
5636 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5640 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5641 return expand_compound_operation (temp);
5644 /* We can optimize some special cases of ZERO_EXTEND. */
5645 if (GET_CODE (x) == ZERO_EXTEND)
5647 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5648 know that the last value didn't have any inappropriate bits
5650 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5651 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5652 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5653 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5654 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5655 return XEXP (XEXP (x, 0), 0);
5657 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5658 if (GET_CODE (XEXP (x, 0)) == SUBREG
5659 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5660 && subreg_lowpart_p (XEXP (x, 0))
5661 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5662 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5663 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5664 return SUBREG_REG (XEXP (x, 0));
5666 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5667 is a comparison and STORE_FLAG_VALUE permits. This is like
5668 the first case, but it works even when GET_MODE (x) is larger
5669 than HOST_WIDE_INT. */
5670 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5671 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5672 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5673 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5674 <= HOST_BITS_PER_WIDE_INT)
5675 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5676 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5677 return XEXP (XEXP (x, 0), 0);
5679 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5680 if (GET_CODE (XEXP (x, 0)) == SUBREG
5681 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5682 && subreg_lowpart_p (XEXP (x, 0))
5683 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5684 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5685 <= HOST_BITS_PER_WIDE_INT)
5686 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5687 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5688 return SUBREG_REG (XEXP (x, 0));
5692 /* If we reach here, we want to return a pair of shifts. The inner
5693 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5694 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5695 logical depending on the value of UNSIGNEDP.
5697 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5698 converted into an AND of a shift.
5700 We must check for the case where the left shift would have a negative
5701 count. This can happen in a case like (x >> 31) & 255 on machines
5702 that can't shift by a constant. On those machines, we would first
5703 combine the shift with the AND to produce a variable-position
5704 extraction. Then the constant of 31 would be substituted in to produce
5705 a such a position. */
5707 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5708 if (modewidth + len >= pos)
5709 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5711 simplify_shift_const (NULL_RTX, ASHIFT,
5714 modewidth - pos - len),
5717 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5718 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5719 simplify_shift_const (NULL_RTX, LSHIFTRT,
5722 ((HOST_WIDE_INT) 1 << len) - 1);
5724 /* Any other cases we can't handle. */
5727 /* If we couldn't do this for some reason, return the original
5729 if (GET_CODE (tem) == CLOBBER)
5735 /* X is a SET which contains an assignment of one object into
5736 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5737 or certain SUBREGS). If possible, convert it into a series of
5740 We half-heartedly support variable positions, but do not at all
5741 support variable lengths. */
5744 expand_field_assignment (x)
5748 rtx pos; /* Always counts from low bit. */
5751 enum machine_mode compute_mode;
5753 /* Loop until we find something we can't simplify. */
5756 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5757 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5759 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5760 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5761 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5763 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5764 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5766 inner = XEXP (SET_DEST (x), 0);
5767 len = INTVAL (XEXP (SET_DEST (x), 1));
5768 pos = XEXP (SET_DEST (x), 2);
5770 /* If the position is constant and spans the width of INNER,
5771 surround INNER with a USE to indicate this. */
5772 if (GET_CODE (pos) == CONST_INT
5773 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5774 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5776 if (BITS_BIG_ENDIAN)
5778 if (GET_CODE (pos) == CONST_INT)
5779 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5781 else if (GET_CODE (pos) == MINUS
5782 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5783 && (INTVAL (XEXP (pos, 1))
5784 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5785 /* If position is ADJUST - X, new position is X. */
5786 pos = XEXP (pos, 0);
5788 pos = gen_binary (MINUS, GET_MODE (pos),
5789 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5795 /* A SUBREG between two modes that occupy the same numbers of words
5796 can be done by moving the SUBREG to the source. */
5797 else if (GET_CODE (SET_DEST (x)) == SUBREG
5798 /* We need SUBREGs to compute nonzero_bits properly. */
5799 && nonzero_sign_valid
5800 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5801 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5802 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5803 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5805 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5806 gen_lowpart_for_combine
5807 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5814 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5815 inner = SUBREG_REG (inner);
5817 compute_mode = GET_MODE (inner);
5819 /* Don't attempt bitwise arithmetic on non-integral modes. */
5820 if (! INTEGRAL_MODE_P (compute_mode))
5822 enum machine_mode imode;
5824 /* Something is probably seriously wrong if this matches. */
5825 if (! FLOAT_MODE_P (compute_mode))
5828 /* Try to find an integral mode to pun with. */
5829 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5830 if (imode == BLKmode)
5833 compute_mode = imode;
5834 inner = gen_lowpart_for_combine (imode, inner);
5837 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5838 if (len < HOST_BITS_PER_WIDE_INT)
5839 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5843 /* Now compute the equivalent expression. Make a copy of INNER
5844 for the SET_DEST in case it is a MEM into which we will substitute;
5845 we don't want shared RTL in that case. */
5847 (VOIDmode, copy_rtx (inner),
5848 gen_binary (IOR, compute_mode,
5849 gen_binary (AND, compute_mode,
5850 gen_unary (NOT, compute_mode,
5856 gen_binary (ASHIFT, compute_mode,
5857 gen_binary (AND, compute_mode,
5858 gen_lowpart_for_combine
5859 (compute_mode, SET_SRC (x)),
5867 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5868 it is an RTX that represents a variable starting position; otherwise,
5869 POS is the (constant) starting bit position (counted from the LSB).
5871 INNER may be a USE. This will occur when we started with a bitfield
5872 that went outside the boundary of the object in memory, which is
5873 allowed on most machines. To isolate this case, we produce a USE
5874 whose mode is wide enough and surround the MEM with it. The only
5875 code that understands the USE is this routine. If it is not removed,
5876 it will cause the resulting insn not to match.
5878 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5881 IN_DEST is non-zero if this is a reference in the destination of a
5882 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5883 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5886 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5887 ZERO_EXTRACT should be built even for bits starting at bit 0.
5889 MODE is the desired mode of the result (if IN_DEST == 0).
5891 The result is an RTX for the extraction or NULL_RTX if the target
5895 make_extraction (mode, inner, pos, pos_rtx, len,
5896 unsignedp, in_dest, in_compare)
5897 enum machine_mode mode;
5901 unsigned HOST_WIDE_INT len;
5903 int in_dest, in_compare;
5905 /* This mode describes the size of the storage area
5906 to fetch the overall value from. Within that, we
5907 ignore the POS lowest bits, etc. */
5908 enum machine_mode is_mode = GET_MODE (inner);
5909 enum machine_mode inner_mode;
5910 enum machine_mode wanted_inner_mode = byte_mode;
5911 enum machine_mode wanted_inner_reg_mode = word_mode;
5912 enum machine_mode pos_mode = word_mode;
5913 enum machine_mode extraction_mode = word_mode;
5914 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5917 rtx orig_pos_rtx = pos_rtx;
5918 HOST_WIDE_INT orig_pos;
5920 /* Get some information about INNER and get the innermost object. */
5921 if (GET_CODE (inner) == USE)
5922 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5923 /* We don't need to adjust the position because we set up the USE
5924 to pretend that it was a full-word object. */
5925 spans_byte = 1, inner = XEXP (inner, 0);
5926 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5928 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5929 consider just the QI as the memory to extract from.
5930 The subreg adds or removes high bits; its mode is
5931 irrelevant to the meaning of this extraction,
5932 since POS and LEN count from the lsb. */
5933 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5934 is_mode = GET_MODE (SUBREG_REG (inner));
5935 inner = SUBREG_REG (inner);
5938 inner_mode = GET_MODE (inner);
5940 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5941 pos = INTVAL (pos_rtx), pos_rtx = 0;
5943 /* See if this can be done without an extraction. We never can if the
5944 width of the field is not the same as that of some integer mode. For
5945 registers, we can only avoid the extraction if the position is at the
5946 low-order bit and this is either not in the destination or we have the
5947 appropriate STRICT_LOW_PART operation available.
5949 For MEM, we can avoid an extract if the field starts on an appropriate
5950 boundary and we can change the mode of the memory reference. However,
5951 we cannot directly access the MEM if we have a USE and the underlying
5952 MEM is not TMODE. This combination means that MEM was being used in a
5953 context where bits outside its mode were being referenced; that is only
5954 valid in bit-field insns. */
5956 if (tmode != BLKmode
5957 && ! (spans_byte && inner_mode != tmode)
5958 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5959 && GET_CODE (inner) != MEM
5961 || (GET_CODE (inner) == REG
5962 && (movstrict_optab->handlers[(int) tmode].insn_code
5963 != CODE_FOR_nothing))))
5964 || (GET_CODE (inner) == MEM && pos_rtx == 0
5966 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5967 : BITS_PER_UNIT)) == 0
5968 /* We can't do this if we are widening INNER_MODE (it
5969 may not be aligned, for one thing). */
5970 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5971 && (inner_mode == tmode
5972 || (! mode_dependent_address_p (XEXP (inner, 0))
5973 && ! MEM_VOLATILE_P (inner))))))
5975 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5976 field. If the original and current mode are the same, we need not
5977 adjust the offset. Otherwise, we do if bytes big endian.
5979 If INNER is not a MEM, get a piece consisting of just the field
5980 of interest (in this case POS % BITS_PER_WORD must be 0). */
5982 if (GET_CODE (inner) == MEM)
5985 /* POS counts from lsb, but make OFFSET count in memory order. */
5986 if (BYTES_BIG_ENDIAN)
5987 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5989 offset = pos / BITS_PER_UNIT;
5991 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5992 MEM_COPY_ATTRIBUTES (new, inner);
5994 else if (GET_CODE (inner) == REG)
5996 /* We can't call gen_lowpart_for_combine here since we always want
5997 a SUBREG and it would sometimes return a new hard register. */
5998 if (tmode != inner_mode)
5999 new = gen_rtx_SUBREG (tmode, inner,
6001 && (GET_MODE_SIZE (inner_mode)
6003 ? (((GET_MODE_SIZE (inner_mode)
6004 - GET_MODE_SIZE (tmode))
6006 - pos / BITS_PER_WORD)
6007 : pos / BITS_PER_WORD));
6012 new = force_to_mode (inner, tmode,
6013 len >= HOST_BITS_PER_WIDE_INT
6014 ? ~(HOST_WIDE_INT) 0
6015 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6018 /* If this extraction is going into the destination of a SET,
6019 make a STRICT_LOW_PART unless we made a MEM. */
6022 return (GET_CODE (new) == MEM ? new
6023 : (GET_CODE (new) != SUBREG
6024 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6025 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
6030 /* If we know that no extraneous bits are set, and that the high
6031 bit is not set, convert the extraction to the cheaper of
6032 sign and zero extension, that are equivalent in these cases. */
6033 if (flag_expensive_optimizations
6034 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6035 && ((nonzero_bits (new, tmode)
6036 & ~(((unsigned HOST_WIDE_INT)
6037 GET_MODE_MASK (tmode))
6041 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6042 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6044 /* Prefer ZERO_EXTENSION, since it gives more information to
6046 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6051 /* Otherwise, sign- or zero-extend unless we already are in the
6054 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6058 /* Unless this is a COMPARE or we have a funny memory reference,
6059 don't do anything with zero-extending field extracts starting at
6060 the low-order bit since they are simple AND operations. */
6061 if (pos_rtx == 0 && pos == 0 && ! in_dest
6062 && ! in_compare && ! spans_byte && unsignedp)
6065 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6066 we would be spanning bytes or if the position is not a constant and the
6067 length is not 1. In all other cases, we would only be going outside
6068 our object in cases when an original shift would have been
6070 if (! spans_byte && GET_CODE (inner) == MEM
6071 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6072 || (pos_rtx != 0 && len != 1)))
6075 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6076 and the mode for the result. */
6080 wanted_inner_reg_mode
6081 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6082 if (wanted_inner_reg_mode == VOIDmode)
6083 wanted_inner_reg_mode = word_mode;
6085 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6086 if (pos_mode == VOIDmode)
6087 pos_mode = word_mode;
6089 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6090 if (extraction_mode == VOIDmode)
6091 extraction_mode = word_mode;
6096 if (! in_dest && unsignedp)
6098 wanted_inner_reg_mode
6099 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6100 if (wanted_inner_reg_mode == VOIDmode)
6101 wanted_inner_reg_mode = word_mode;
6103 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6104 if (pos_mode == VOIDmode)
6105 pos_mode = word_mode;
6107 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6108 if (extraction_mode == VOIDmode)
6109 extraction_mode = word_mode;
6114 if (! in_dest && ! unsignedp)
6116 wanted_inner_reg_mode
6117 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6118 if (wanted_inner_reg_mode == VOIDmode)
6119 wanted_inner_reg_mode = word_mode;
6121 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6122 if (pos_mode == VOIDmode)
6123 pos_mode = word_mode;
6125 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6126 if (extraction_mode == VOIDmode)
6127 extraction_mode = word_mode;
6131 /* Never narrow an object, since that might not be safe. */
6133 if (mode != VOIDmode
6134 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6135 extraction_mode = mode;
6137 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6138 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6139 pos_mode = GET_MODE (pos_rtx);
6141 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6142 if we have to change the mode of memory and cannot, the desired mode is
6144 if (GET_CODE (inner) != MEM)
6145 wanted_inner_mode = wanted_inner_reg_mode;
6146 else if (inner_mode != wanted_inner_mode
6147 && (mode_dependent_address_p (XEXP (inner, 0))
6148 || MEM_VOLATILE_P (inner)))
6149 wanted_inner_mode = extraction_mode;
6153 if (BITS_BIG_ENDIAN)
6155 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6156 BITS_BIG_ENDIAN style. If position is constant, compute new
6157 position. Otherwise, build subtraction.
6158 Note that POS is relative to the mode of the original argument.
6159 If it's a MEM we need to recompute POS relative to that.
6160 However, if we're extracting from (or inserting into) a register,
6161 we want to recompute POS relative to wanted_inner_mode. */
6162 int width = (GET_CODE (inner) == MEM
6163 ? GET_MODE_BITSIZE (is_mode)
6164 : GET_MODE_BITSIZE (wanted_inner_mode));
6167 pos = width - len - pos;
6170 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6171 GEN_INT (width - len), pos_rtx);
6172 /* POS may be less than 0 now, but we check for that below.
6173 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6176 /* If INNER has a wider mode, make it smaller. If this is a constant
6177 extract, try to adjust the byte to point to the byte containing
6179 if (wanted_inner_mode != VOIDmode
6180 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6181 && ((GET_CODE (inner) == MEM
6182 && (inner_mode == wanted_inner_mode
6183 || (! mode_dependent_address_p (XEXP (inner, 0))
6184 && ! MEM_VOLATILE_P (inner))))))
6188 /* The computations below will be correct if the machine is big
6189 endian in both bits and bytes or little endian in bits and bytes.
6190 If it is mixed, we must adjust. */
6192 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6193 adjust OFFSET to compensate. */
6194 if (BYTES_BIG_ENDIAN
6196 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6197 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6199 /* If this is a constant position, we can move to the desired byte. */
6202 offset += pos / BITS_PER_UNIT;
6203 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6206 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6208 && is_mode != wanted_inner_mode)
6209 offset = (GET_MODE_SIZE (is_mode)
6210 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6212 if (offset != 0 || inner_mode != wanted_inner_mode)
6214 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6215 plus_constant (XEXP (inner, 0), offset));
6217 MEM_COPY_ATTRIBUTES (newmem, inner);
6222 /* If INNER is not memory, we can always get it into the proper mode. If we
6223 are changing its mode, POS must be a constant and smaller than the size
6225 else if (GET_CODE (inner) != MEM)
6227 if (GET_MODE (inner) != wanted_inner_mode
6229 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6232 inner = force_to_mode (inner, wanted_inner_mode,
6234 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6235 ? ~(HOST_WIDE_INT) 0
6236 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6241 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6242 have to zero extend. Otherwise, we can just use a SUBREG. */
6244 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6246 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6248 /* If we know that no extraneous bits are set, and that the high
6249 bit is not set, convert extraction to cheaper one - eighter
6250 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6252 if (flag_expensive_optimizations
6253 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6254 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6255 & ~(((unsigned HOST_WIDE_INT)
6256 GET_MODE_MASK (GET_MODE (pos_rtx)))
6260 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6262 /* Prefer ZERO_EXTENSION, since it gives more information to
6264 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6269 else if (pos_rtx != 0
6270 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6271 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6273 /* Make POS_RTX unless we already have it and it is correct. If we don't
6274 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6276 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6277 pos_rtx = orig_pos_rtx;
6279 else if (pos_rtx == 0)
6280 pos_rtx = GEN_INT (pos);
6282 /* Make the required operation. See if we can use existing rtx. */
6283 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6284 extraction_mode, inner, GEN_INT (len), pos_rtx);
6286 new = gen_lowpart_for_combine (mode, new);
6291 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6292 with any other operations in X. Return X without that shift if so. */
6295 extract_left_shift (x, count)
6299 enum rtx_code code = GET_CODE (x);
6300 enum machine_mode mode = GET_MODE (x);
6306 /* This is the shift itself. If it is wide enough, we will return
6307 either the value being shifted if the shift count is equal to
6308 COUNT or a shift for the difference. */
6309 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6310 && INTVAL (XEXP (x, 1)) >= count)
6311 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6312 INTVAL (XEXP (x, 1)) - count);
6316 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6317 return gen_unary (code, mode, mode, tem);
6321 case PLUS: case IOR: case XOR: case AND:
6322 /* If we can safely shift this constant and we find the inner shift,
6323 make a new operation. */
6324 if (GET_CODE (XEXP (x,1)) == CONST_INT
6325 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6326 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6327 return gen_binary (code, mode, tem,
6328 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6339 /* Look at the expression rooted at X. Look for expressions
6340 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6341 Form these expressions.
6343 Return the new rtx, usually just X.
6345 Also, for machines like the Vax that don't have logical shift insns,
6346 try to convert logical to arithmetic shift operations in cases where
6347 they are equivalent. This undoes the canonicalizations to logical
6348 shifts done elsewhere.
6350 We try, as much as possible, to re-use rtl expressions to save memory.
6352 IN_CODE says what kind of expression we are processing. Normally, it is
6353 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6354 being kludges), it is MEM. When processing the arguments of a comparison
6355 or a COMPARE against zero, it is COMPARE. */
6358 make_compound_operation (x, in_code)
6360 enum rtx_code in_code;
6362 enum rtx_code code = GET_CODE (x);
6363 enum machine_mode mode = GET_MODE (x);
6364 int mode_width = GET_MODE_BITSIZE (mode);
6366 enum rtx_code next_code;
6372 /* Select the code to be used in recursive calls. Once we are inside an
6373 address, we stay there. If we have a comparison, set to COMPARE,
6374 but once inside, go back to our default of SET. */
6376 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6377 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6378 && XEXP (x, 1) == const0_rtx) ? COMPARE
6379 : in_code == COMPARE ? SET : in_code);
6381 /* Process depending on the code of this operation. If NEW is set
6382 non-zero, it will be returned. */
6387 /* Convert shifts by constants into multiplications if inside
6389 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6390 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6391 && INTVAL (XEXP (x, 1)) >= 0)
6393 new = make_compound_operation (XEXP (x, 0), next_code);
6394 new = gen_rtx_combine (MULT, mode, new,
6395 GEN_INT ((HOST_WIDE_INT) 1
6396 << INTVAL (XEXP (x, 1))));
6401 /* If the second operand is not a constant, we can't do anything
6403 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6406 /* If the constant is a power of two minus one and the first operand
6407 is a logical right shift, make an extraction. */
6408 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6409 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6411 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6412 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6413 0, in_code == COMPARE);
6416 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6417 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6418 && subreg_lowpart_p (XEXP (x, 0))
6419 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6420 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6422 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6424 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6425 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6426 0, in_code == COMPARE);
6428 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6429 else if ((GET_CODE (XEXP (x, 0)) == XOR
6430 || GET_CODE (XEXP (x, 0)) == IOR)
6431 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6432 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6433 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6435 /* Apply the distributive law, and then try to make extractions. */
6436 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6437 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6439 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6441 new = make_compound_operation (new, in_code);
6444 /* If we are have (and (rotate X C) M) and C is larger than the number
6445 of bits in M, this is an extraction. */
6447 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6448 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6449 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6450 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6452 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6453 new = make_extraction (mode, new,
6454 (GET_MODE_BITSIZE (mode)
6455 - INTVAL (XEXP (XEXP (x, 0), 1))),
6456 NULL_RTX, i, 1, 0, in_code == COMPARE);
6459 /* On machines without logical shifts, if the operand of the AND is
6460 a logical shift and our mask turns off all the propagated sign
6461 bits, we can replace the logical shift with an arithmetic shift. */
6462 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6463 && (lshr_optab->handlers[(int) mode].insn_code
6464 == CODE_FOR_nothing)
6465 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6466 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6467 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6468 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6469 && mode_width <= HOST_BITS_PER_WIDE_INT)
6471 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6473 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6474 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6476 gen_rtx_combine (ASHIFTRT, mode,
6477 make_compound_operation (XEXP (XEXP (x, 0), 0),
6479 XEXP (XEXP (x, 0), 1)));
6482 /* If the constant is one less than a power of two, this might be
6483 representable by an extraction even if no shift is present.
6484 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6485 we are in a COMPARE. */
6486 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6487 new = make_extraction (mode,
6488 make_compound_operation (XEXP (x, 0),
6490 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6492 /* If we are in a comparison and this is an AND with a power of two,
6493 convert this into the appropriate bit extract. */
6494 else if (in_code == COMPARE
6495 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6496 new = make_extraction (mode,
6497 make_compound_operation (XEXP (x, 0),
6499 i, NULL_RTX, 1, 1, 0, 1);
6504 /* If the sign bit is known to be zero, replace this with an
6505 arithmetic shift. */
6506 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6507 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6508 && mode_width <= HOST_BITS_PER_WIDE_INT
6509 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6511 new = gen_rtx_combine (ASHIFTRT, mode,
6512 make_compound_operation (XEXP (x, 0),
6518 /* ... fall through ... */
6524 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6525 this is a SIGN_EXTRACT. */
6526 if (GET_CODE (rhs) == CONST_INT
6527 && GET_CODE (lhs) == ASHIFT
6528 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6529 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6531 new = make_compound_operation (XEXP (lhs, 0), next_code);
6532 new = make_extraction (mode, new,
6533 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6534 NULL_RTX, mode_width - INTVAL (rhs),
6535 code == LSHIFTRT, 0, in_code == COMPARE);
6539 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6540 If so, try to merge the shifts into a SIGN_EXTEND. We could
6541 also do this for some cases of SIGN_EXTRACT, but it doesn't
6542 seem worth the effort; the case checked for occurs on Alpha. */
6544 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6545 && ! (GET_CODE (lhs) == SUBREG
6546 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6547 && GET_CODE (rhs) == CONST_INT
6548 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6549 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6550 new = make_extraction (mode, make_compound_operation (new, next_code),
6551 0, NULL_RTX, mode_width - INTVAL (rhs),
6552 code == LSHIFTRT, 0, in_code == COMPARE);
6557 /* Call ourselves recursively on the inner expression. If we are
6558 narrowing the object and it has a different RTL code from
6559 what it originally did, do this SUBREG as a force_to_mode. */
6561 tem = make_compound_operation (SUBREG_REG (x), in_code);
6562 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6563 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6564 && subreg_lowpart_p (x))
6566 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6569 /* If we have something other than a SUBREG, we might have
6570 done an expansion, so rerun outselves. */
6571 if (GET_CODE (newer) != SUBREG)
6572 newer = make_compound_operation (newer, in_code);
6577 /* If this is a paradoxical subreg, and the new code is a sign or
6578 zero extension, omit the subreg and widen the extension. If it
6579 is a regular subreg, we can still get rid of the subreg by not
6580 widening so much, or in fact removing the extension entirely. */
6581 if ((GET_CODE (tem) == SIGN_EXTEND
6582 || GET_CODE (tem) == ZERO_EXTEND)
6583 && subreg_lowpart_p (x))
6585 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6586 || (GET_MODE_SIZE (mode) >
6587 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6588 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6590 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6601 x = gen_lowpart_for_combine (mode, new);
6602 code = GET_CODE (x);
6605 /* Now recursively process each operand of this operation. */
6606 fmt = GET_RTX_FORMAT (code);
6607 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6610 new = make_compound_operation (XEXP (x, i), next_code);
6611 SUBST (XEXP (x, i), new);
6617 /* Given M see if it is a value that would select a field of bits
6618 within an item, but not the entire word. Return -1 if not.
6619 Otherwise, return the starting position of the field, where 0 is the
6622 *PLEN is set to the length of the field. */
6625 get_pos_from_mask (m, plen)
6626 unsigned HOST_WIDE_INT m;
6627 unsigned HOST_WIDE_INT *plen;
6629 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6630 int pos = exact_log2 (m & -m);
6636 /* Now shift off the low-order zero bits and see if we have a power of
6638 len = exact_log2 ((m >> pos) + 1);
6647 /* See if X can be simplified knowing that we will only refer to it in
6648 MODE and will only refer to those bits that are nonzero in MASK.
6649 If other bits are being computed or if masking operations are done
6650 that select a superset of the bits in MASK, they can sometimes be
6653 Return a possibly simplified expression, but always convert X to
6654 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6656 Also, if REG is non-zero and X is a register equal in value to REG,
6659 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6660 are all off in X. This is used when X will be complemented, by either
6661 NOT, NEG, or XOR. */
6664 force_to_mode (x, mode, mask, reg, just_select)
6666 enum machine_mode mode;
6667 unsigned HOST_WIDE_INT mask;
6671 enum rtx_code code = GET_CODE (x);
6672 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6673 enum machine_mode op_mode;
6674 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6677 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6678 code below will do the wrong thing since the mode of such an
6679 expression is VOIDmode.
6681 Also do nothing if X is a CLOBBER; this can happen if X was
6682 the return value from a call to gen_lowpart_for_combine. */
6683 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6686 /* We want to perform the operation is its present mode unless we know
6687 that the operation is valid in MODE, in which case we do the operation
6689 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6690 && code_to_optab[(int) code] != 0
6691 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6692 != CODE_FOR_nothing))
6693 ? mode : GET_MODE (x));
6695 /* It is not valid to do a right-shift in a narrower mode
6696 than the one it came in with. */
6697 if ((code == LSHIFTRT || code == ASHIFTRT)
6698 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6699 op_mode = GET_MODE (x);
6701 /* Truncate MASK to fit OP_MODE. */
6703 mask &= GET_MODE_MASK (op_mode);
6705 /* When we have an arithmetic operation, or a shift whose count we
6706 do not know, we need to assume that all bit the up to the highest-order
6707 bit in MASK will be needed. This is how we form such a mask. */
6709 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6710 ? GET_MODE_MASK (op_mode)
6711 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6714 fuller_mask = ~(HOST_WIDE_INT) 0;
6716 /* Determine what bits of X are guaranteed to be (non)zero. */
6717 nonzero = nonzero_bits (x, mode);
6719 /* If none of the bits in X are needed, return a zero. */
6720 if (! just_select && (nonzero & mask) == 0)
6723 /* If X is a CONST_INT, return a new one. Do this here since the
6724 test below will fail. */
6725 if (GET_CODE (x) == CONST_INT)
6727 HOST_WIDE_INT cval = INTVAL (x) & mask;
6728 int width = GET_MODE_BITSIZE (mode);
6730 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6731 number, sign extend it. */
6732 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6733 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6734 cval |= (HOST_WIDE_INT) -1 << width;
6736 return GEN_INT (cval);
6739 /* If X is narrower than MODE and we want all the bits in X's mode, just
6740 get X in the proper mode. */
6741 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6742 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6743 return gen_lowpart_for_combine (mode, x);
6745 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6746 MASK are already known to be zero in X, we need not do anything. */
6747 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6753 /* If X is a (clobber (const_int)), return it since we know we are
6754 generating something that won't match. */
6758 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6759 spanned the boundary of the MEM. If we are now masking so it is
6760 within that boundary, we don't need the USE any more. */
6761 if (! BITS_BIG_ENDIAN
6762 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6763 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6770 x = expand_compound_operation (x);
6771 if (GET_CODE (x) != code)
6772 return force_to_mode (x, mode, mask, reg, next_select);
6776 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6777 || rtx_equal_p (reg, get_last_value (x))))
6782 if (subreg_lowpart_p (x)
6783 /* We can ignore the effect of this SUBREG if it narrows the mode or
6784 if the constant masks to zero all the bits the mode doesn't
6786 && ((GET_MODE_SIZE (GET_MODE (x))
6787 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6789 & GET_MODE_MASK (GET_MODE (x))
6790 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6791 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6795 /* If this is an AND with a constant, convert it into an AND
6796 whose constant is the AND of that constant with MASK. If it
6797 remains an AND of MASK, delete it since it is redundant. */
6799 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6801 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6802 mask & INTVAL (XEXP (x, 1)));
6804 /* If X is still an AND, see if it is an AND with a mask that
6805 is just some low-order bits. If so, and it is MASK, we don't
6808 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6809 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6812 /* If it remains an AND, try making another AND with the bits
6813 in the mode mask that aren't in MASK turned on. If the
6814 constant in the AND is wide enough, this might make a
6815 cheaper constant. */
6817 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6818 && GET_MODE_MASK (GET_MODE (x)) != mask
6819 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6821 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6822 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6823 int width = GET_MODE_BITSIZE (GET_MODE (x));
6826 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6827 number, sign extend it. */
6828 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6829 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6830 cval |= (HOST_WIDE_INT) -1 << width;
6832 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6833 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6843 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6844 low-order bits (as in an alignment operation) and FOO is already
6845 aligned to that boundary, mask C1 to that boundary as well.
6846 This may eliminate that PLUS and, later, the AND. */
6849 unsigned int width = GET_MODE_BITSIZE (mode);
6850 unsigned HOST_WIDE_INT smask = mask;
6852 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6853 number, sign extend it. */
6855 if (width < HOST_BITS_PER_WIDE_INT
6856 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6857 smask |= (HOST_WIDE_INT) -1 << width;
6859 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6860 && exact_log2 (- smask) >= 0)
6864 && (XEXP (x, 0) == stack_pointer_rtx
6865 || XEXP (x, 0) == frame_pointer_rtx))
6867 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6868 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6870 sp_mask &= ~(sp_alignment - 1);
6871 if ((sp_mask & ~smask) == 0
6872 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6873 return force_to_mode (plus_constant (XEXP (x, 0),
6874 ((INTVAL (XEXP (x, 1)) -
6875 STACK_BIAS) & smask)
6877 mode, smask, reg, next_select);
6880 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6881 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6882 return force_to_mode (plus_constant (XEXP (x, 0),
6883 (INTVAL (XEXP (x, 1))
6885 mode, smask, reg, next_select);
6889 /* ... fall through ... */
6892 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6893 most significant bit in MASK since carries from those bits will
6894 affect the bits we are interested in. */
6899 /* If X is (minus C Y) where C's least set bit is larger than any bit
6900 in the mask, then we may replace with (neg Y). */
6901 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6902 && (INTVAL (XEXP (x, 0)) & -INTVAL (XEXP (x, 0))) > mask)
6904 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6905 return force_to_mode (x, mode, mask, reg, next_select);
6908 /* Similarly, if C contains every bit in the mask, then we may
6909 replace with (not Y). */
6910 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6911 && (INTVAL (XEXP (x, 0)) | mask) == INTVAL (XEXP (x, 0)))
6913 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6914 return force_to_mode (x, mode, mask, reg, next_select);
6922 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6923 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6924 operation which may be a bitfield extraction. Ensure that the
6925 constant we form is not wider than the mode of X. */
6927 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6928 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6929 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6930 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6931 && GET_CODE (XEXP (x, 1)) == CONST_INT
6932 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6933 + floor_log2 (INTVAL (XEXP (x, 1))))
6934 < GET_MODE_BITSIZE (GET_MODE (x)))
6935 && (INTVAL (XEXP (x, 1))
6936 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6938 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6939 << INTVAL (XEXP (XEXP (x, 0), 1)));
6940 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6941 XEXP (XEXP (x, 0), 0), temp);
6942 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6943 XEXP (XEXP (x, 0), 1));
6944 return force_to_mode (x, mode, mask, reg, next_select);
6948 /* For most binary operations, just propagate into the operation and
6949 change the mode if we have an operation of that mode. */
6951 op0 = gen_lowpart_for_combine (op_mode,
6952 force_to_mode (XEXP (x, 0), mode, mask,
6954 op1 = gen_lowpart_for_combine (op_mode,
6955 force_to_mode (XEXP (x, 1), mode, mask,
6958 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6959 MASK since OP1 might have been sign-extended but we never want
6960 to turn on extra bits, since combine might have previously relied
6961 on them being off. */
6962 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6963 && (INTVAL (op1) & mask) != 0)
6964 op1 = GEN_INT (INTVAL (op1) & mask);
6966 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6967 x = gen_binary (code, op_mode, op0, op1);
6971 /* For left shifts, do the same, but just for the first operand.
6972 However, we cannot do anything with shifts where we cannot
6973 guarantee that the counts are smaller than the size of the mode
6974 because such a count will have a different meaning in a
6977 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6978 && INTVAL (XEXP (x, 1)) >= 0
6979 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6980 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6981 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6982 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6985 /* If the shift count is a constant and we can do arithmetic in
6986 the mode of the shift, refine which bits we need. Otherwise, use the
6987 conservative form of the mask. */
6988 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6989 && INTVAL (XEXP (x, 1)) >= 0
6990 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6991 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6992 mask >>= INTVAL (XEXP (x, 1));
6996 op0 = gen_lowpart_for_combine (op_mode,
6997 force_to_mode (XEXP (x, 0), op_mode,
6998 mask, reg, next_select));
7000 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7001 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7005 /* Here we can only do something if the shift count is a constant,
7006 this shift constant is valid for the host, and we can do arithmetic
7009 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7010 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7011 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7013 rtx inner = XEXP (x, 0);
7014 unsigned HOST_WIDE_INT inner_mask;
7016 /* Select the mask of the bits we need for the shift operand. */
7017 inner_mask = mask << INTVAL (XEXP (x, 1));
7019 /* We can only change the mode of the shift if we can do arithmetic
7020 in the mode of the shift and INNER_MASK is no wider than the
7021 width of OP_MODE. */
7022 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7023 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7024 op_mode = GET_MODE (x);
7026 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7028 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7029 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7032 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7033 shift and AND produces only copies of the sign bit (C2 is one less
7034 than a power of two), we can do this with just a shift. */
7036 if (GET_CODE (x) == LSHIFTRT
7037 && GET_CODE (XEXP (x, 1)) == CONST_INT
7038 /* The shift puts one of the sign bit copies in the least significant
7040 && ((INTVAL (XEXP (x, 1))
7041 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7042 >= GET_MODE_BITSIZE (GET_MODE (x)))
7043 && exact_log2 (mask + 1) >= 0
7044 /* Number of bits left after the shift must be more than the mask
7046 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7047 <= GET_MODE_BITSIZE (GET_MODE (x)))
7048 /* Must be more sign bit copies than the mask needs. */
7049 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7050 >= exact_log2 (mask + 1)))
7051 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7052 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7053 - exact_log2 (mask + 1)));
7058 /* If we are just looking for the sign bit, we don't need this shift at
7059 all, even if it has a variable count. */
7060 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7061 && (mask == ((unsigned HOST_WIDE_INT) 1
7062 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7063 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7065 /* If this is a shift by a constant, get a mask that contains those bits
7066 that are not copies of the sign bit. We then have two cases: If
7067 MASK only includes those bits, this can be a logical shift, which may
7068 allow simplifications. If MASK is a single-bit field not within
7069 those bits, we are requesting a copy of the sign bit and hence can
7070 shift the sign bit to the appropriate location. */
7072 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7073 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7077 /* If the considered data is wider then HOST_WIDE_INT, we can't
7078 represent a mask for all its bits in a single scalar.
7079 But we only care about the lower bits, so calculate these. */
7081 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7083 nonzero = ~(HOST_WIDE_INT) 0;
7085 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7086 is the number of bits a full-width mask would have set.
7087 We need only shift if these are fewer than nonzero can
7088 hold. If not, we must keep all bits set in nonzero. */
7090 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7091 < HOST_BITS_PER_WIDE_INT)
7092 nonzero >>= INTVAL (XEXP (x, 1))
7093 + HOST_BITS_PER_WIDE_INT
7094 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7098 nonzero = GET_MODE_MASK (GET_MODE (x));
7099 nonzero >>= INTVAL (XEXP (x, 1));
7102 if ((mask & ~nonzero) == 0
7103 || (i = exact_log2 (mask)) >= 0)
7105 x = simplify_shift_const
7106 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7107 i < 0 ? INTVAL (XEXP (x, 1))
7108 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7110 if (GET_CODE (x) != ASHIFTRT)
7111 return force_to_mode (x, mode, mask, reg, next_select);
7115 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7116 even if the shift count isn't a constant. */
7118 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7122 /* If this is a zero- or sign-extension operation that just affects bits
7123 we don't care about, remove it. Be sure the call above returned
7124 something that is still a shift. */
7126 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7127 && GET_CODE (XEXP (x, 1)) == CONST_INT
7128 && INTVAL (XEXP (x, 1)) >= 0
7129 && (INTVAL (XEXP (x, 1))
7130 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7131 && GET_CODE (XEXP (x, 0)) == ASHIFT
7132 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7133 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7134 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7141 /* If the shift count is constant and we can do computations
7142 in the mode of X, compute where the bits we care about are.
7143 Otherwise, we can't do anything. Don't change the mode of
7144 the shift or propagate MODE into the shift, though. */
7145 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7146 && INTVAL (XEXP (x, 1)) >= 0)
7148 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7149 GET_MODE (x), GEN_INT (mask),
7151 if (temp && GET_CODE(temp) == CONST_INT)
7153 force_to_mode (XEXP (x, 0), GET_MODE (x),
7154 INTVAL (temp), reg, next_select));
7159 /* If we just want the low-order bit, the NEG isn't needed since it
7160 won't change the low-order bit. */
7162 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7164 /* We need any bits less significant than the most significant bit in
7165 MASK since carries from those bits will affect the bits we are
7171 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7172 same as the XOR case above. Ensure that the constant we form is not
7173 wider than the mode of X. */
7175 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7176 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7177 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7178 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7179 < GET_MODE_BITSIZE (GET_MODE (x)))
7180 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7182 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7183 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7184 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7186 return force_to_mode (x, mode, mask, reg, next_select);
7189 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7190 use the full mask inside the NOT. */
7194 op0 = gen_lowpart_for_combine (op_mode,
7195 force_to_mode (XEXP (x, 0), mode, mask,
7197 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7198 x = gen_unary (code, op_mode, op_mode, op0);
7202 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7203 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7204 which is equal to STORE_FLAG_VALUE. */
7205 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7206 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7207 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7208 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7213 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7214 written in a narrower mode. We play it safe and do not do so. */
7217 gen_lowpart_for_combine (GET_MODE (x),
7218 force_to_mode (XEXP (x, 1), mode,
7219 mask, reg, next_select)));
7221 gen_lowpart_for_combine (GET_MODE (x),
7222 force_to_mode (XEXP (x, 2), mode,
7223 mask, reg,next_select)));
7230 /* Ensure we return a value of the proper mode. */
7231 return gen_lowpart_for_combine (mode, x);
7234 /* Return nonzero if X is an expression that has one of two values depending on
7235 whether some other value is zero or nonzero. In that case, we return the
7236 value that is being tested, *PTRUE is set to the value if the rtx being
7237 returned has a nonzero value, and *PFALSE is set to the other alternative.
7239 If we return zero, we set *PTRUE and *PFALSE to X. */
7242 if_then_else_cond (x, ptrue, pfalse)
7244 rtx *ptrue, *pfalse;
7246 enum machine_mode mode = GET_MODE (x);
7247 enum rtx_code code = GET_CODE (x);
7248 rtx cond0, cond1, true0, true1, false0, false1;
7249 unsigned HOST_WIDE_INT nz;
7251 /* If we are comparing a value against zero, we are done. */
7252 if ((code == NE || code == EQ)
7253 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7255 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7256 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7260 /* If this is a unary operation whose operand has one of two values, apply
7261 our opcode to compute those values. */
7262 else if (GET_RTX_CLASS (code) == '1'
7263 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7265 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7266 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7270 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7271 make can't possibly match and would suppress other optimizations. */
7272 else if (code == COMPARE)
7275 /* If this is a binary operation, see if either side has only one of two
7276 values. If either one does or if both do and they are conditional on
7277 the same value, compute the new true and false values. */
7278 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7279 || GET_RTX_CLASS (code) == '<')
7281 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7282 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7284 if ((cond0 != 0 || cond1 != 0)
7285 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7287 /* If if_then_else_cond returned zero, then true/false are the
7288 same rtl. We must copy one of them to prevent invalid rtl
7291 true0 = copy_rtx (true0);
7292 else if (cond1 == 0)
7293 true1 = copy_rtx (true1);
7295 *ptrue = gen_binary (code, mode, true0, true1);
7296 *pfalse = gen_binary (code, mode, false0, false1);
7297 return cond0 ? cond0 : cond1;
7300 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7301 operands is zero when the other is non-zero, and vice-versa,
7302 and STORE_FLAG_VALUE is 1 or -1. */
7304 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7305 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7307 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7309 rtx op0 = XEXP (XEXP (x, 0), 1);
7310 rtx op1 = XEXP (XEXP (x, 1), 1);
7312 cond0 = XEXP (XEXP (x, 0), 0);
7313 cond1 = XEXP (XEXP (x, 1), 0);
7315 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7316 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7317 && reversible_comparison_p (cond1)
7318 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7319 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7320 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7321 || ((swap_condition (GET_CODE (cond0))
7322 == reverse_condition (GET_CODE (cond1)))
7323 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7324 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7325 && ! side_effects_p (x))
7327 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7328 *pfalse = gen_binary (MULT, mode,
7330 ? gen_unary (NEG, mode, mode, op1) : op1),
7336 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7338 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7339 && (code == MULT || code == AND || code == UMIN)
7340 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7342 cond0 = XEXP (XEXP (x, 0), 0);
7343 cond1 = XEXP (XEXP (x, 1), 0);
7345 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7346 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7347 && reversible_comparison_p (cond1)
7348 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7349 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7350 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7351 || ((swap_condition (GET_CODE (cond0))
7352 == reverse_condition (GET_CODE (cond1)))
7353 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7354 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7355 && ! side_effects_p (x))
7357 *ptrue = *pfalse = const0_rtx;
7363 else if (code == IF_THEN_ELSE)
7365 /* If we have IF_THEN_ELSE already, extract the condition and
7366 canonicalize it if it is NE or EQ. */
7367 cond0 = XEXP (x, 0);
7368 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7369 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7370 return XEXP (cond0, 0);
7371 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7373 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7374 return XEXP (cond0, 0);
7380 /* If X is a normal SUBREG with both inner and outer modes integral,
7381 we can narrow both the true and false values of the inner expression,
7382 if there is a condition. */
7383 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7384 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7385 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7386 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7389 if ((GET_CODE (SUBREG_REG (x)) == REG
7390 || GET_CODE (SUBREG_REG (x)) == MEM
7391 || CONSTANT_P (SUBREG_REG (x)))
7392 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7393 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7395 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7396 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7398 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7400 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7405 /* If X is a constant, this isn't special and will cause confusions
7406 if we treat it as such. Likewise if it is equivalent to a constant. */
7407 else if (CONSTANT_P (x)
7408 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7411 /* If X is known to be either 0 or -1, those are the true and
7412 false values when testing X. */
7413 else if (x == constm1_rtx || x == const0_rtx
7414 || (mode != VOIDmode
7415 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7417 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7421 /* Likewise for 0 or a single bit. */
7422 else if (mode != VOIDmode
7423 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7424 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7426 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7430 /* Otherwise fail; show no condition with true and false values the same. */
7431 *ptrue = *pfalse = x;
7435 /* Return the value of expression X given the fact that condition COND
7436 is known to be true when applied to REG as its first operand and VAL
7437 as its second. X is known to not be shared and so can be modified in
7440 We only handle the simplest cases, and specifically those cases that
7441 arise with IF_THEN_ELSE expressions. */
7444 known_cond (x, cond, reg, val)
7449 enum rtx_code code = GET_CODE (x);
7454 if (side_effects_p (x))
7457 if (cond == EQ && rtx_equal_p (x, reg))
7460 /* If X is (abs REG) and we know something about REG's relationship
7461 with zero, we may be able to simplify this. */
7463 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7466 case GE: case GT: case EQ:
7469 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7475 /* The only other cases we handle are MIN, MAX, and comparisons if the
7476 operands are the same as REG and VAL. */
7478 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7480 if (rtx_equal_p (XEXP (x, 0), val))
7481 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7483 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7485 if (GET_RTX_CLASS (code) == '<')
7487 if (comparison_dominates_p (cond, code))
7488 return const_true_rtx;
7490 code = reverse_condition (code);
7492 && comparison_dominates_p (cond, code))
7497 else if (code == SMAX || code == SMIN
7498 || code == UMIN || code == UMAX)
7500 int unsignedp = (code == UMIN || code == UMAX);
7502 if (code == SMAX || code == UMAX)
7503 cond = reverse_condition (cond);
7508 return unsignedp ? x : XEXP (x, 1);
7510 return unsignedp ? x : XEXP (x, 0);
7512 return unsignedp ? XEXP (x, 1) : x;
7514 return unsignedp ? XEXP (x, 0) : x;
7522 fmt = GET_RTX_FORMAT (code);
7523 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7526 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7527 else if (fmt[i] == 'E')
7528 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7529 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7536 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7537 assignment as a field assignment. */
7540 rtx_equal_for_field_assignment_p (x, y)
7544 if (x == y || rtx_equal_p (x, y))
7547 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7550 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7551 Note that all SUBREGs of MEM are paradoxical; otherwise they
7552 would have been rewritten. */
7553 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7554 && GET_CODE (SUBREG_REG (y)) == MEM
7555 && rtx_equal_p (SUBREG_REG (y),
7556 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7559 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7560 && GET_CODE (SUBREG_REG (x)) == MEM
7561 && rtx_equal_p (SUBREG_REG (x),
7562 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7565 /* We used to see if get_last_value of X and Y were the same but that's
7566 not correct. In one direction, we'll cause the assignment to have
7567 the wrong destination and in the case, we'll import a register into this
7568 insn that might have already have been dead. So fail if none of the
7569 above cases are true. */
7573 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7574 Return that assignment if so.
7576 We only handle the most common cases. */
7579 make_field_assignment (x)
7582 rtx dest = SET_DEST (x);
7583 rtx src = SET_SRC (x);
7588 unsigned HOST_WIDE_INT len;
7590 enum machine_mode mode;
7592 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7593 a clear of a one-bit field. We will have changed it to
7594 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7597 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7598 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7599 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7600 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7602 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7605 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7609 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7610 && subreg_lowpart_p (XEXP (src, 0))
7611 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7612 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7613 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7614 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7615 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7617 assign = make_extraction (VOIDmode, dest, 0,
7618 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7621 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7625 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7627 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7628 && XEXP (XEXP (src, 0), 0) == const1_rtx
7629 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7631 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7634 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7638 /* The other case we handle is assignments into a constant-position
7639 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7640 a mask that has all one bits except for a group of zero bits and
7641 OTHER is known to have zeros where C1 has ones, this is such an
7642 assignment. Compute the position and length from C1. Shift OTHER
7643 to the appropriate position, force it to the required mode, and
7644 make the extraction. Check for the AND in both operands. */
7646 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7649 rhs = expand_compound_operation (XEXP (src, 0));
7650 lhs = expand_compound_operation (XEXP (src, 1));
7652 if (GET_CODE (rhs) == AND
7653 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7654 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7655 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7656 else if (GET_CODE (lhs) == AND
7657 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7658 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7659 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7663 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7664 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7665 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7666 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7669 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7673 /* The mode to use for the source is the mode of the assignment, or of
7674 what is inside a possible STRICT_LOW_PART. */
7675 mode = (GET_CODE (assign) == STRICT_LOW_PART
7676 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7678 /* Shift OTHER right POS places and make it the source, restricting it
7679 to the proper length and mode. */
7681 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7682 GET_MODE (src), other, pos),
7684 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7685 ? ~(HOST_WIDE_INT) 0
7686 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7689 return gen_rtx_combine (SET, VOIDmode, assign, src);
7692 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7696 apply_distributive_law (x)
7699 enum rtx_code code = GET_CODE (x);
7700 rtx lhs, rhs, other;
7702 enum rtx_code inner_code;
7704 /* Distributivity is not true for floating point.
7705 It can change the value. So don't do it.
7706 -- rms and moshier@world.std.com. */
7707 if (FLOAT_MODE_P (GET_MODE (x)))
7710 /* The outer operation can only be one of the following: */
7711 if (code != IOR && code != AND && code != XOR
7712 && code != PLUS && code != MINUS)
7715 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7717 /* If either operand is a primitive we can't do anything, so get out
7719 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7720 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7723 lhs = expand_compound_operation (lhs);
7724 rhs = expand_compound_operation (rhs);
7725 inner_code = GET_CODE (lhs);
7726 if (inner_code != GET_CODE (rhs))
7729 /* See if the inner and outer operations distribute. */
7736 /* These all distribute except over PLUS. */
7737 if (code == PLUS || code == MINUS)
7742 if (code != PLUS && code != MINUS)
7747 /* This is also a multiply, so it distributes over everything. */
7751 /* Non-paradoxical SUBREGs distributes over all operations, provided
7752 the inner modes and word numbers are the same, this is an extraction
7753 of a low-order part, we don't convert an fp operation to int or
7754 vice versa, and we would not be converting a single-word
7755 operation into a multi-word operation. The latter test is not
7756 required, but it prevents generating unneeded multi-word operations.
7757 Some of the previous tests are redundant given the latter test, but
7758 are retained because they are required for correctness.
7760 We produce the result slightly differently in this case. */
7762 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7763 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7764 || ! subreg_lowpart_p (lhs)
7765 || (GET_MODE_CLASS (GET_MODE (lhs))
7766 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7767 || (GET_MODE_SIZE (GET_MODE (lhs))
7768 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7769 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7772 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7773 SUBREG_REG (lhs), SUBREG_REG (rhs));
7774 return gen_lowpart_for_combine (GET_MODE (x), tem);
7780 /* Set LHS and RHS to the inner operands (A and B in the example
7781 above) and set OTHER to the common operand (C in the example).
7782 These is only one way to do this unless the inner operation is
7784 if (GET_RTX_CLASS (inner_code) == 'c'
7785 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7786 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7787 else if (GET_RTX_CLASS (inner_code) == 'c'
7788 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7789 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7790 else if (GET_RTX_CLASS (inner_code) == 'c'
7791 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7792 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7793 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7794 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7798 /* Form the new inner operation, seeing if it simplifies first. */
7799 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7801 /* There is one exception to the general way of distributing:
7802 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7803 if (code == XOR && inner_code == IOR)
7806 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7809 /* We may be able to continuing distributing the result, so call
7810 ourselves recursively on the inner operation before forming the
7811 outer operation, which we return. */
7812 return gen_binary (inner_code, GET_MODE (x),
7813 apply_distributive_law (tem), other);
7816 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7819 Return an equivalent form, if different from X. Otherwise, return X. If
7820 X is zero, we are to always construct the equivalent form. */
7823 simplify_and_const_int (x, mode, varop, constop)
7825 enum machine_mode mode;
7827 unsigned HOST_WIDE_INT constop;
7829 unsigned HOST_WIDE_INT nonzero;
7832 /* Simplify VAROP knowing that we will be only looking at some of the
7834 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7836 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7837 CONST_INT, we are done. */
7838 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7841 /* See what bits may be nonzero in VAROP. Unlike the general case of
7842 a call to nonzero_bits, here we don't care about bits outside
7845 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7846 nonzero = trunc_int_for_mode (nonzero, mode);
7848 /* Turn off all bits in the constant that are known to already be zero.
7849 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7850 which is tested below. */
7854 /* If we don't have any bits left, return zero. */
7858 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7859 a power of two, we can replace this with a ASHIFT. */
7860 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7861 && (i = exact_log2 (constop)) >= 0)
7862 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7864 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7865 or XOR, then try to apply the distributive law. This may eliminate
7866 operations if either branch can be simplified because of the AND.
7867 It may also make some cases more complex, but those cases probably
7868 won't match a pattern either with or without this. */
7870 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7872 gen_lowpart_for_combine
7874 apply_distributive_law
7875 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7876 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7877 XEXP (varop, 0), constop),
7878 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7879 XEXP (varop, 1), constop))));
7881 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7882 if we already had one (just check for the simplest cases). */
7883 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7884 && GET_MODE (XEXP (x, 0)) == mode
7885 && SUBREG_REG (XEXP (x, 0)) == varop)
7886 varop = XEXP (x, 0);
7888 varop = gen_lowpart_for_combine (mode, varop);
7890 /* If we can't make the SUBREG, try to return what we were given. */
7891 if (GET_CODE (varop) == CLOBBER)
7892 return x ? x : varop;
7894 /* If we are only masking insignificant bits, return VAROP. */
7895 if (constop == nonzero)
7898 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7899 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7900 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7904 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7905 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7906 SUBST (XEXP (x, 1), GEN_INT (constop));
7908 SUBST (XEXP (x, 0), varop);
7914 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7915 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7916 is less useful. We can't allow both, because that results in exponential
7917 run time recursion. There is a nullstone testcase that triggered
7918 this. This macro avoids accidental uses of num_sign_bit_copies. */
7919 #define num_sign_bit_copies()
7921 /* Given an expression, X, compute which bits in X can be non-zero.
7922 We don't care about bits outside of those defined in MODE.
7924 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7925 a shift, AND, or zero_extract, we can do better. */
7927 static unsigned HOST_WIDE_INT
7928 nonzero_bits (x, mode)
7930 enum machine_mode mode;
7932 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7933 unsigned HOST_WIDE_INT inner_nz;
7935 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7938 /* For floating-point values, assume all bits are needed. */
7939 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7942 /* If X is wider than MODE, use its mode instead. */
7943 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7945 mode = GET_MODE (x);
7946 nonzero = GET_MODE_MASK (mode);
7947 mode_width = GET_MODE_BITSIZE (mode);
7950 if (mode_width > HOST_BITS_PER_WIDE_INT)
7951 /* Our only callers in this case look for single bit values. So
7952 just return the mode mask. Those tests will then be false. */
7955 #ifndef WORD_REGISTER_OPERATIONS
7956 /* If MODE is wider than X, but both are a single word for both the host
7957 and target machines, we can compute this from which bits of the
7958 object might be nonzero in its own mode, taking into account the fact
7959 that on many CISC machines, accessing an object in a wider mode
7960 causes the high-order bits to become undefined. So they are
7961 not known to be zero. */
7963 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7964 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7965 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7966 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7968 nonzero &= nonzero_bits (x, GET_MODE (x));
7969 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7974 code = GET_CODE (x);
7978 #ifdef POINTERS_EXTEND_UNSIGNED
7979 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7980 all the bits above ptr_mode are known to be zero. */
7981 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7982 && REGNO_POINTER_FLAG (REGNO (x)))
7983 nonzero &= GET_MODE_MASK (ptr_mode);
7986 #ifdef STACK_BOUNDARY
7987 /* If this is the stack pointer, we may know something about its
7988 alignment. If PUSH_ROUNDING is defined, it is possible for the
7989 stack to be momentarily aligned only to that amount, so we pick
7990 the least alignment. */
7992 /* We can't check for arg_pointer_rtx here, because it is not
7993 guaranteed to have as much alignment as the stack pointer.
7994 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7995 alignment but the argument pointer has only 64 bit alignment. */
7997 if ((x == frame_pointer_rtx
7998 || x == stack_pointer_rtx
7999 || x == hard_frame_pointer_rtx
8000 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
8001 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
8007 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8009 #ifdef PUSH_ROUNDING
8010 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
8011 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
8014 /* We must return here, otherwise we may get a worse result from
8015 one of the choices below. There is nothing useful below as
8016 far as the stack pointer is concerned. */
8017 return nonzero &= ~(sp_alignment - 1);
8021 /* If X is a register whose nonzero bits value is current, use it.
8022 Otherwise, if X is a register whose value we can find, use that
8023 value. Otherwise, use the previously-computed global nonzero bits
8024 for this register. */
8026 if (reg_last_set_value[REGNO (x)] != 0
8027 && reg_last_set_mode[REGNO (x)] == mode
8028 && (reg_last_set_label[REGNO (x)] == label_tick
8029 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8030 && REG_N_SETS (REGNO (x)) == 1
8031 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8033 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8034 return reg_last_set_nonzero_bits[REGNO (x)];
8036 tem = get_last_value (x);
8040 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8041 /* If X is narrower than MODE and TEM is a non-negative
8042 constant that would appear negative in the mode of X,
8043 sign-extend it for use in reg_nonzero_bits because some
8044 machines (maybe most) will actually do the sign-extension
8045 and this is the conservative approach.
8047 ??? For 2.5, try to tighten up the MD files in this regard
8048 instead of this kludge. */
8050 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8051 && GET_CODE (tem) == CONST_INT
8053 && 0 != (INTVAL (tem)
8054 & ((HOST_WIDE_INT) 1
8055 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8056 tem = GEN_INT (INTVAL (tem)
8057 | ((HOST_WIDE_INT) (-1)
8058 << GET_MODE_BITSIZE (GET_MODE (x))));
8060 return nonzero_bits (tem, mode);
8062 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8063 return reg_nonzero_bits[REGNO (x)] & nonzero;
8068 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8069 /* If X is negative in MODE, sign-extend the value. */
8070 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8071 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8072 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8078 #ifdef LOAD_EXTEND_OP
8079 /* In many, if not most, RISC machines, reading a byte from memory
8080 zeros the rest of the register. Noticing that fact saves a lot
8081 of extra zero-extends. */
8082 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8083 nonzero &= GET_MODE_MASK (GET_MODE (x));
8093 /* If this produces an integer result, we know which bits are set.
8094 Code here used to clear bits outside the mode of X, but that is
8097 if (GET_MODE_CLASS (mode) == MODE_INT
8098 && mode_width <= HOST_BITS_PER_WIDE_INT)
8099 nonzero = STORE_FLAG_VALUE;
8104 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8105 and num_sign_bit_copies. */
8106 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8107 == GET_MODE_BITSIZE (GET_MODE (x)))
8111 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8112 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8117 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8118 and num_sign_bit_copies. */
8119 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8120 == GET_MODE_BITSIZE (GET_MODE (x)))
8126 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8130 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8131 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8132 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8136 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8137 Otherwise, show all the bits in the outer mode but not the inner
8139 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8140 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8142 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8144 & (((HOST_WIDE_INT) 1
8145 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8146 inner_nz |= (GET_MODE_MASK (mode)
8147 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8150 nonzero &= inner_nz;
8154 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8155 & nonzero_bits (XEXP (x, 1), mode));
8159 case UMIN: case UMAX: case SMIN: case SMAX:
8160 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8161 | nonzero_bits (XEXP (x, 1), mode));
8164 case PLUS: case MINUS:
8166 case DIV: case UDIV:
8167 case MOD: case UMOD:
8168 /* We can apply the rules of arithmetic to compute the number of
8169 high- and low-order zero bits of these operations. We start by
8170 computing the width (position of the highest-order non-zero bit)
8171 and the number of low-order zero bits for each value. */
8173 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8174 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8175 int width0 = floor_log2 (nz0) + 1;
8176 int width1 = floor_log2 (nz1) + 1;
8177 int low0 = floor_log2 (nz0 & -nz0);
8178 int low1 = floor_log2 (nz1 & -nz1);
8179 HOST_WIDE_INT op0_maybe_minusp
8180 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8181 HOST_WIDE_INT op1_maybe_minusp
8182 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8183 unsigned int result_width = mode_width;
8191 && (XEXP (x, 0) == stack_pointer_rtx
8192 || XEXP (x, 0) == frame_pointer_rtx)
8193 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8195 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8197 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8198 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8199 width0 = floor_log2 (nz0) + 1;
8200 width1 = floor_log2 (nz1) + 1;
8201 low0 = floor_log2 (nz0 & -nz0);
8202 low1 = floor_log2 (nz1 & -nz1);
8205 result_width = MAX (width0, width1) + 1;
8206 result_low = MIN (low0, low1);
8209 result_low = MIN (low0, low1);
8212 result_width = width0 + width1;
8213 result_low = low0 + low1;
8216 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8217 result_width = width0;
8220 result_width = width0;
8223 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8224 result_width = MIN (width0, width1);
8225 result_low = MIN (low0, low1);
8228 result_width = MIN (width0, width1);
8229 result_low = MIN (low0, low1);
8235 if (result_width < mode_width)
8236 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8239 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8244 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8245 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8246 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8250 /* If this is a SUBREG formed for a promoted variable that has
8251 been zero-extended, we know that at least the high-order bits
8252 are zero, though others might be too. */
8254 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8255 nonzero = (GET_MODE_MASK (GET_MODE (x))
8256 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8258 /* If the inner mode is a single word for both the host and target
8259 machines, we can compute this from which bits of the inner
8260 object might be nonzero. */
8261 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8262 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8263 <= HOST_BITS_PER_WIDE_INT))
8265 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8267 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8268 /* If this is a typical RISC machine, we only have to worry
8269 about the way loads are extended. */
8270 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8272 & (((unsigned HOST_WIDE_INT) 1
8273 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8275 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8278 /* On many CISC machines, accessing an object in a wider mode
8279 causes the high-order bits to become undefined. So they are
8280 not known to be zero. */
8281 if (GET_MODE_SIZE (GET_MODE (x))
8282 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8283 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8284 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8293 /* The nonzero bits are in two classes: any bits within MODE
8294 that aren't in GET_MODE (x) are always significant. The rest of the
8295 nonzero bits are those that are significant in the operand of
8296 the shift when shifted the appropriate number of bits. This
8297 shows that high-order bits are cleared by the right shift and
8298 low-order bits by left shifts. */
8299 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8300 && INTVAL (XEXP (x, 1)) >= 0
8301 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8303 enum machine_mode inner_mode = GET_MODE (x);
8304 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8305 int count = INTVAL (XEXP (x, 1));
8306 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8307 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8308 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8309 unsigned HOST_WIDE_INT outer = 0;
8311 if (mode_width > width)
8312 outer = (op_nonzero & nonzero & ~mode_mask);
8314 if (code == LSHIFTRT)
8316 else if (code == ASHIFTRT)
8320 /* If the sign bit may have been nonzero before the shift, we
8321 need to mark all the places it could have been copied to
8322 by the shift as possibly nonzero. */
8323 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8324 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8326 else if (code == ASHIFT)
8329 inner = ((inner << (count % width)
8330 | (inner >> (width - (count % width)))) & mode_mask);
8332 nonzero &= (outer | inner);
8337 /* This is at most the number of bits in the mode. */
8338 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8342 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8343 | nonzero_bits (XEXP (x, 2), mode));
8353 /* See the macro definition above. */
8354 #undef num_sign_bit_copies
8356 /* Return the number of bits at the high-order end of X that are known to
8357 be equal to the sign bit. X will be used in mode MODE; if MODE is
8358 VOIDmode, X will be used in its own mode. The returned value will always
8359 be between 1 and the number of bits in MODE. */
8362 num_sign_bit_copies (x, mode)
8364 enum machine_mode mode;
8366 enum rtx_code code = GET_CODE (x);
8367 unsigned int bitwidth;
8368 int num0, num1, result;
8369 unsigned HOST_WIDE_INT nonzero;
8372 /* If we weren't given a mode, use the mode of X. If the mode is still
8373 VOIDmode, we don't know anything. Likewise if one of the modes is
8376 if (mode == VOIDmode)
8377 mode = GET_MODE (x);
8379 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8382 bitwidth = GET_MODE_BITSIZE (mode);
8384 /* For a smaller object, just ignore the high bits. */
8385 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8387 num0 = num_sign_bit_copies (x, GET_MODE (x));
8389 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8392 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8394 #ifndef WORD_REGISTER_OPERATIONS
8395 /* If this machine does not do all register operations on the entire
8396 register and MODE is wider than the mode of X, we can say nothing
8397 at all about the high-order bits. */
8400 /* Likewise on machines that do, if the mode of the object is smaller
8401 than a word and loads of that size don't sign extend, we can say
8402 nothing about the high order bits. */
8403 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8404 #ifdef LOAD_EXTEND_OP
8405 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8416 #ifdef POINTERS_EXTEND_UNSIGNED
8417 /* If pointers extend signed and this is a pointer in Pmode, say that
8418 all the bits above ptr_mode are known to be sign bit copies. */
8419 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8420 && REGNO_POINTER_FLAG (REGNO (x)))
8421 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8424 if (reg_last_set_value[REGNO (x)] != 0
8425 && reg_last_set_mode[REGNO (x)] == mode
8426 && (reg_last_set_label[REGNO (x)] == label_tick
8427 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8428 && REG_N_SETS (REGNO (x)) == 1
8429 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8431 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8432 return reg_last_set_sign_bit_copies[REGNO (x)];
8434 tem = get_last_value (x);
8436 return num_sign_bit_copies (tem, mode);
8438 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8439 return reg_sign_bit_copies[REGNO (x)];
8443 #ifdef LOAD_EXTEND_OP
8444 /* Some RISC machines sign-extend all loads of smaller than a word. */
8445 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8446 return MAX (1, ((int) bitwidth
8447 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8452 /* If the constant is negative, take its 1's complement and remask.
8453 Then see how many zero bits we have. */
8454 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8455 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8456 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8457 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8459 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8462 /* If this is a SUBREG for a promoted object that is sign-extended
8463 and we are looking at it in a wider mode, we know that at least the
8464 high-order bits are known to be sign bit copies. */
8466 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8468 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8469 return MAX ((int) bitwidth
8470 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8474 /* For a smaller object, just ignore the high bits. */
8475 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8477 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8478 return MAX (1, (num0
8479 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8483 #ifdef WORD_REGISTER_OPERATIONS
8484 #ifdef LOAD_EXTEND_OP
8485 /* For paradoxical SUBREGs on machines where all register operations
8486 affect the entire register, just look inside. Note that we are
8487 passing MODE to the recursive call, so the number of sign bit copies
8488 will remain relative to that mode, not the inner mode. */
8490 /* This works only if loads sign extend. Otherwise, if we get a
8491 reload for the inner part, it may be loaded from the stack, and
8492 then we lose all sign bit copies that existed before the store
8495 if ((GET_MODE_SIZE (GET_MODE (x))
8496 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8497 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8498 return num_sign_bit_copies (SUBREG_REG (x), mode);
8504 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8505 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8509 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8510 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8513 /* For a smaller object, just ignore the high bits. */
8514 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8515 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8519 return num_sign_bit_copies (XEXP (x, 0), mode);
8521 case ROTATE: case ROTATERT:
8522 /* If we are rotating left by a number of bits less than the number
8523 of sign bit copies, we can just subtract that amount from the
8525 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8526 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8528 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8529 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8530 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8535 /* In general, this subtracts one sign bit copy. But if the value
8536 is known to be positive, the number of sign bit copies is the
8537 same as that of the input. Finally, if the input has just one bit
8538 that might be nonzero, all the bits are copies of the sign bit. */
8539 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8540 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8541 return num0 > 1 ? num0 - 1 : 1;
8543 nonzero = nonzero_bits (XEXP (x, 0), mode);
8548 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8553 case IOR: case AND: case XOR:
8554 case SMIN: case SMAX: case UMIN: case UMAX:
8555 /* Logical operations will preserve the number of sign-bit copies.
8556 MIN and MAX operations always return one of the operands. */
8557 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8558 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8559 return MIN (num0, num1);
8561 case PLUS: case MINUS:
8562 /* For addition and subtraction, we can have a 1-bit carry. However,
8563 if we are subtracting 1 from a positive number, there will not
8564 be such a carry. Furthermore, if the positive number is known to
8565 be 0 or 1, we know the result is either -1 or 0. */
8567 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8568 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8570 nonzero = nonzero_bits (XEXP (x, 0), mode);
8571 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8572 return (nonzero == 1 || nonzero == 0 ? bitwidth
8573 : bitwidth - floor_log2 (nonzero) - 1);
8576 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8577 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8578 return MAX (1, MIN (num0, num1) - 1);
8581 /* The number of bits of the product is the sum of the number of
8582 bits of both terms. However, unless one of the terms if known
8583 to be positive, we must allow for an additional bit since negating
8584 a negative number can remove one sign bit copy. */
8586 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8587 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8589 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8591 && (bitwidth > HOST_BITS_PER_WIDE_INT
8592 || (((nonzero_bits (XEXP (x, 0), mode)
8593 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8594 && ((nonzero_bits (XEXP (x, 1), mode)
8595 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8598 return MAX (1, result);
8601 /* The result must be <= the first operand. If the first operand
8602 has the high bit set, we know nothing about the number of sign
8604 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8606 else if ((nonzero_bits (XEXP (x, 0), mode)
8607 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8610 return num_sign_bit_copies (XEXP (x, 0), mode);
8613 /* The result must be <= the scond operand. */
8614 return num_sign_bit_copies (XEXP (x, 1), mode);
8617 /* Similar to unsigned division, except that we have to worry about
8618 the case where the divisor is negative, in which case we have
8620 result = num_sign_bit_copies (XEXP (x, 0), mode);
8622 && (bitwidth > HOST_BITS_PER_WIDE_INT
8623 || (nonzero_bits (XEXP (x, 1), mode)
8624 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8630 result = num_sign_bit_copies (XEXP (x, 1), mode);
8632 && (bitwidth > HOST_BITS_PER_WIDE_INT
8633 || (nonzero_bits (XEXP (x, 1), mode)
8634 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8640 /* Shifts by a constant add to the number of bits equal to the
8642 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8643 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8644 && INTVAL (XEXP (x, 1)) > 0)
8645 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8650 /* Left shifts destroy copies. */
8651 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8652 || INTVAL (XEXP (x, 1)) < 0
8653 || INTVAL (XEXP (x, 1)) >= bitwidth)
8656 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8657 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8660 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8661 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8662 return MIN (num0, num1);
8664 case EQ: case NE: case GE: case GT: case LE: case LT:
8665 case GEU: case GTU: case LEU: case LTU:
8666 if (STORE_FLAG_VALUE == -1)
8674 /* If we haven't been able to figure it out by one of the above rules,
8675 see if some of the high-order bits are known to be zero. If so,
8676 count those bits and return one less than that amount. If we can't
8677 safely compute the mask for this mode, always return BITWIDTH. */
8679 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8682 nonzero = nonzero_bits (x, mode);
8683 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8684 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8687 /* Return the number of "extended" bits there are in X, when interpreted
8688 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8689 unsigned quantities, this is the number of high-order zero bits.
8690 For signed quantities, this is the number of copies of the sign bit
8691 minus 1. In both case, this function returns the number of "spare"
8692 bits. For example, if two quantities for which this function returns
8693 at least 1 are added, the addition is known not to overflow.
8695 This function will always return 0 unless called during combine, which
8696 implies that it must be called from a define_split. */
8699 extended_count (x, mode, unsignedp)
8701 enum machine_mode mode;
8704 if (nonzero_sign_valid == 0)
8708 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8709 ? (GET_MODE_BITSIZE (mode) - 1
8710 - floor_log2 (nonzero_bits (x, mode)))
8712 : num_sign_bit_copies (x, mode) - 1);
8715 /* This function is called from `simplify_shift_const' to merge two
8716 outer operations. Specifically, we have already found that we need
8717 to perform operation *POP0 with constant *PCONST0 at the outermost
8718 position. We would now like to also perform OP1 with constant CONST1
8719 (with *POP0 being done last).
8721 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8722 the resulting operation. *PCOMP_P is set to 1 if we would need to
8723 complement the innermost operand, otherwise it is unchanged.
8725 MODE is the mode in which the operation will be done. No bits outside
8726 the width of this mode matter. It is assumed that the width of this mode
8727 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8729 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8730 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8731 result is simply *PCONST0.
8733 If the resulting operation cannot be expressed as one operation, we
8734 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8737 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8738 enum rtx_code *pop0;
8739 HOST_WIDE_INT *pconst0;
8741 HOST_WIDE_INT const1;
8742 enum machine_mode mode;
8745 enum rtx_code op0 = *pop0;
8746 HOST_WIDE_INT const0 = *pconst0;
8748 const0 &= GET_MODE_MASK (mode);
8749 const1 &= GET_MODE_MASK (mode);
8751 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8755 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8758 if (op1 == NIL || op0 == SET)
8761 else if (op0 == NIL)
8762 op0 = op1, const0 = const1;
8764 else if (op0 == op1)
8788 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8789 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8792 /* If the two constants aren't the same, we can't do anything. The
8793 remaining six cases can all be done. */
8794 else if (const0 != const1)
8802 /* (a & b) | b == b */
8804 else /* op1 == XOR */
8805 /* (a ^ b) | b == a | b */
8811 /* (a & b) ^ b == (~a) & b */
8812 op0 = AND, *pcomp_p = 1;
8813 else /* op1 == IOR */
8814 /* (a | b) ^ b == a & ~b */
8815 op0 = AND, *pconst0 = ~const0;
8820 /* (a | b) & b == b */
8822 else /* op1 == XOR */
8823 /* (a ^ b) & b) == (~a) & b */
8830 /* Check for NO-OP cases. */
8831 const0 &= GET_MODE_MASK (mode);
8833 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8835 else if (const0 == 0 && op0 == AND)
8837 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8841 /* ??? Slightly redundant with the above mask, but not entirely.
8842 Moving this above means we'd have to sign-extend the mode mask
8843 for the final test. */
8844 const0 = trunc_int_for_mode (const0, mode);
8852 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8853 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8854 that we started with.
8856 The shift is normally computed in the widest mode we find in VAROP, as
8857 long as it isn't a different number of words than RESULT_MODE. Exceptions
8858 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8861 simplify_shift_const (x, code, result_mode, varop, input_count)
8864 enum machine_mode result_mode;
8868 enum rtx_code orig_code = code;
8869 int orig_count = input_count;
8872 enum machine_mode mode = result_mode;
8873 enum machine_mode shift_mode, tmode;
8874 unsigned int mode_words
8875 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8876 /* We form (outer_op (code varop count) (outer_const)). */
8877 enum rtx_code outer_op = NIL;
8878 HOST_WIDE_INT outer_const = 0;
8880 int complement_p = 0;
8883 /* If we were given an invalid count, don't do anything except exactly
8884 what was requested. */
8886 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8891 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8894 count = input_count;
8896 /* Make sure and truncate the "natural" shift on the way in. We don't
8897 want to do this inside the loop as it makes it more difficult to
8899 #ifdef SHIFT_COUNT_TRUNCATED
8900 if (SHIFT_COUNT_TRUNCATED)
8901 count %= GET_MODE_BITSIZE (mode);
8904 /* Unless one of the branches of the `if' in this loop does a `continue',
8905 we will `break' the loop after the `if'. */
8909 /* If we have an operand of (clobber (const_int 0)), just return that
8911 if (GET_CODE (varop) == CLOBBER)
8914 /* If we discovered we had to complement VAROP, leave. Making a NOT
8915 here would cause an infinite loop. */
8919 /* Convert ROTATERT to ROTATE. */
8920 if (code == ROTATERT)
8921 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8923 /* We need to determine what mode we will do the shift in. If the
8924 shift is a right shift or a ROTATE, we must always do it in the mode
8925 it was originally done in. Otherwise, we can do it in MODE, the
8926 widest mode encountered. */
8928 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8929 ? result_mode : mode);
8931 /* Handle cases where the count is greater than the size of the mode
8932 minus 1. For ASHIFT, use the size minus one as the count (this can
8933 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8934 take the count modulo the size. For other shifts, the result is
8937 Since these shifts are being produced by the compiler by combining
8938 multiple operations, each of which are defined, we know what the
8939 result is supposed to be. */
8941 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8943 if (code == ASHIFTRT)
8944 count = GET_MODE_BITSIZE (shift_mode) - 1;
8945 else if (code == ROTATE || code == ROTATERT)
8946 count %= GET_MODE_BITSIZE (shift_mode);
8949 /* We can't simply return zero because there may be an
8957 /* An arithmetic right shift of a quantity known to be -1 or 0
8959 if (code == ASHIFTRT
8960 && (num_sign_bit_copies (varop, shift_mode)
8961 == GET_MODE_BITSIZE (shift_mode)))
8967 /* If we are doing an arithmetic right shift and discarding all but
8968 the sign bit copies, this is equivalent to doing a shift by the
8969 bitsize minus one. Convert it into that shift because it will often
8970 allow other simplifications. */
8972 if (code == ASHIFTRT
8973 && (count + num_sign_bit_copies (varop, shift_mode)
8974 >= GET_MODE_BITSIZE (shift_mode)))
8975 count = GET_MODE_BITSIZE (shift_mode) - 1;
8977 /* We simplify the tests below and elsewhere by converting
8978 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8979 `make_compound_operation' will convert it to a ASHIFTRT for
8980 those machines (such as Vax) that don't have a LSHIFTRT. */
8981 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8983 && ((nonzero_bits (varop, shift_mode)
8984 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8988 switch (GET_CODE (varop))
8994 new = expand_compound_operation (varop);
9003 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9004 minus the width of a smaller mode, we can do this with a
9005 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9006 if ((code == ASHIFTRT || code == LSHIFTRT)
9007 && ! mode_dependent_address_p (XEXP (varop, 0))
9008 && ! MEM_VOLATILE_P (varop)
9009 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9010 MODE_INT, 1)) != BLKmode)
9012 if (BYTES_BIG_ENDIAN)
9013 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
9015 new = gen_rtx_MEM (tmode,
9016 plus_constant (XEXP (varop, 0),
9017 count / BITS_PER_UNIT));
9019 MEM_COPY_ATTRIBUTES (new, varop);
9020 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9021 : ZERO_EXTEND, mode, new);
9028 /* Similar to the case above, except that we can only do this if
9029 the resulting mode is the same as that of the underlying
9030 MEM and adjust the address depending on the *bits* endianness
9031 because of the way that bit-field extract insns are defined. */
9032 if ((code == ASHIFTRT || code == LSHIFTRT)
9033 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9034 MODE_INT, 1)) != BLKmode
9035 && tmode == GET_MODE (XEXP (varop, 0)))
9037 if (BITS_BIG_ENDIAN)
9038 new = XEXP (varop, 0);
9041 new = copy_rtx (XEXP (varop, 0));
9042 SUBST (XEXP (new, 0),
9043 plus_constant (XEXP (new, 0),
9044 count / BITS_PER_UNIT));
9047 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9048 : ZERO_EXTEND, mode, new);
9055 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9056 the same number of words as what we've seen so far. Then store
9057 the widest mode in MODE. */
9058 if (subreg_lowpart_p (varop)
9059 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9060 > GET_MODE_SIZE (GET_MODE (varop)))
9061 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9062 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9065 varop = SUBREG_REG (varop);
9066 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9067 mode = GET_MODE (varop);
9073 /* Some machines use MULT instead of ASHIFT because MULT
9074 is cheaper. But it is still better on those machines to
9075 merge two shifts into one. */
9076 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9077 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9080 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9081 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9087 /* Similar, for when divides are cheaper. */
9088 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9089 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9092 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9093 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9099 /* If we are extracting just the sign bit of an arithmetic right
9100 shift, that shift is not needed. */
9101 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9103 varop = XEXP (varop, 0);
9107 /* ... fall through ... */
9112 /* Here we have two nested shifts. The result is usually the
9113 AND of a new shift with a mask. We compute the result below. */
9114 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9115 && INTVAL (XEXP (varop, 1)) >= 0
9116 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9117 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9118 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9120 enum rtx_code first_code = GET_CODE (varop);
9121 unsigned int first_count = INTVAL (XEXP (varop, 1));
9122 unsigned HOST_WIDE_INT mask;
9125 /* We have one common special case. We can't do any merging if
9126 the inner code is an ASHIFTRT of a smaller mode. However, if
9127 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9128 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9129 we can convert it to
9130 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9131 This simplifies certain SIGN_EXTEND operations. */
9132 if (code == ASHIFT && first_code == ASHIFTRT
9133 && (GET_MODE_BITSIZE (result_mode)
9134 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9136 /* C3 has the low-order C1 bits zero. */
9138 mask = (GET_MODE_MASK (mode)
9139 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9141 varop = simplify_and_const_int (NULL_RTX, result_mode,
9142 XEXP (varop, 0), mask);
9143 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9145 count = first_count;
9150 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9151 than C1 high-order bits equal to the sign bit, we can convert
9152 this to either an ASHIFT or a ASHIFTRT depending on the
9155 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9157 if (code == ASHIFTRT && first_code == ASHIFT
9158 && GET_MODE (varop) == shift_mode
9159 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9162 varop = XEXP (varop, 0);
9164 signed_count = count - first_count;
9165 if (signed_count < 0)
9166 count = -signed_count, code = ASHIFT;
9168 count = signed_count;
9173 /* There are some cases we can't do. If CODE is ASHIFTRT,
9174 we can only do this if FIRST_CODE is also ASHIFTRT.
9176 We can't do the case when CODE is ROTATE and FIRST_CODE is
9179 If the mode of this shift is not the mode of the outer shift,
9180 we can't do this if either shift is a right shift or ROTATE.
9182 Finally, we can't do any of these if the mode is too wide
9183 unless the codes are the same.
9185 Handle the case where the shift codes are the same
9188 if (code == first_code)
9190 if (GET_MODE (varop) != result_mode
9191 && (code == ASHIFTRT || code == LSHIFTRT
9195 count += first_count;
9196 varop = XEXP (varop, 0);
9200 if (code == ASHIFTRT
9201 || (code == ROTATE && first_code == ASHIFTRT)
9202 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9203 || (GET_MODE (varop) != result_mode
9204 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9205 || first_code == ROTATE
9206 || code == ROTATE)))
9209 /* To compute the mask to apply after the shift, shift the
9210 nonzero bits of the inner shift the same way the
9211 outer shift will. */
9213 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9216 = simplify_binary_operation (code, result_mode, mask_rtx,
9219 /* Give up if we can't compute an outer operation to use. */
9221 || GET_CODE (mask_rtx) != CONST_INT
9222 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9224 result_mode, &complement_p))
9227 /* If the shifts are in the same direction, we add the
9228 counts. Otherwise, we subtract them. */
9229 signed_count = count;
9230 if ((code == ASHIFTRT || code == LSHIFTRT)
9231 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9232 signed_count += first_count;
9234 signed_count -= first_count;
9236 /* If COUNT is positive, the new shift is usually CODE,
9237 except for the two exceptions below, in which case it is
9238 FIRST_CODE. If the count is negative, FIRST_CODE should
9240 if (signed_count > 0
9241 && ((first_code == ROTATE && code == ASHIFT)
9242 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9243 code = first_code, count = signed_count;
9244 else if (signed_count < 0)
9245 code = first_code, count = -signed_count;
9247 count = signed_count;
9249 varop = XEXP (varop, 0);
9253 /* If we have (A << B << C) for any shift, we can convert this to
9254 (A << C << B). This wins if A is a constant. Only try this if
9255 B is not a constant. */
9257 else if (GET_CODE (varop) == code
9258 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9260 = simplify_binary_operation (code, mode,
9264 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9271 /* Make this fit the case below. */
9272 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9273 GEN_INT (GET_MODE_MASK (mode)));
9279 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9280 with C the size of VAROP - 1 and the shift is logical if
9281 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9282 we have an (le X 0) operation. If we have an arithmetic shift
9283 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9284 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9286 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9287 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9288 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9289 && (code == LSHIFTRT || code == ASHIFTRT)
9290 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9291 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9294 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9297 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9298 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9303 /* If we have (shift (logical)), move the logical to the outside
9304 to allow it to possibly combine with another logical and the
9305 shift to combine with another shift. This also canonicalizes to
9306 what a ZERO_EXTRACT looks like. Also, some machines have
9307 (and (shift)) insns. */
9309 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9310 && (new = simplify_binary_operation (code, result_mode,
9312 GEN_INT (count))) != 0
9313 && GET_CODE (new) == CONST_INT
9314 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9315 INTVAL (new), result_mode, &complement_p))
9317 varop = XEXP (varop, 0);
9321 /* If we can't do that, try to simplify the shift in each arm of the
9322 logical expression, make a new logical expression, and apply
9323 the inverse distributive law. */
9325 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9326 XEXP (varop, 0), count);
9327 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9328 XEXP (varop, 1), count);
9330 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9331 varop = apply_distributive_law (varop);
9338 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9339 says that the sign bit can be tested, FOO has mode MODE, C is
9340 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9341 that may be nonzero. */
9342 if (code == LSHIFTRT
9343 && XEXP (varop, 1) == const0_rtx
9344 && GET_MODE (XEXP (varop, 0)) == result_mode
9345 && count == GET_MODE_BITSIZE (result_mode) - 1
9346 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9347 && ((STORE_FLAG_VALUE
9348 & ((HOST_WIDE_INT) 1
9349 < (GET_MODE_BITSIZE (result_mode) - 1))))
9350 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9351 && merge_outer_ops (&outer_op, &outer_const, XOR,
9352 (HOST_WIDE_INT) 1, result_mode,
9355 varop = XEXP (varop, 0);
9362 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9363 than the number of bits in the mode is equivalent to A. */
9364 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9365 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9367 varop = XEXP (varop, 0);
9372 /* NEG commutes with ASHIFT since it is multiplication. Move the
9373 NEG outside to allow shifts to combine. */
9375 && merge_outer_ops (&outer_op, &outer_const, NEG,
9376 (HOST_WIDE_INT) 0, result_mode,
9379 varop = XEXP (varop, 0);
9385 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9386 is one less than the number of bits in the mode is
9387 equivalent to (xor A 1). */
9388 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9389 && XEXP (varop, 1) == constm1_rtx
9390 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9391 && merge_outer_ops (&outer_op, &outer_const, XOR,
9392 (HOST_WIDE_INT) 1, result_mode,
9396 varop = XEXP (varop, 0);
9400 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9401 that might be nonzero in BAR are those being shifted out and those
9402 bits are known zero in FOO, we can replace the PLUS with FOO.
9403 Similarly in the other operand order. This code occurs when
9404 we are computing the size of a variable-size array. */
9406 if ((code == ASHIFTRT || code == LSHIFTRT)
9407 && count < HOST_BITS_PER_WIDE_INT
9408 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9409 && (nonzero_bits (XEXP (varop, 1), result_mode)
9410 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9412 varop = XEXP (varop, 0);
9415 else if ((code == ASHIFTRT || code == LSHIFTRT)
9416 && count < HOST_BITS_PER_WIDE_INT
9417 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9418 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9420 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9421 & nonzero_bits (XEXP (varop, 1),
9424 varop = XEXP (varop, 1);
9428 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9430 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9431 && (new = simplify_binary_operation (ASHIFT, result_mode,
9433 GEN_INT (count))) != 0
9434 && GET_CODE (new) == CONST_INT
9435 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9436 INTVAL (new), result_mode, &complement_p))
9438 varop = XEXP (varop, 0);
9444 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9445 with C the size of VAROP - 1 and the shift is logical if
9446 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9447 we have a (gt X 0) operation. If the shift is arithmetic with
9448 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9449 we have a (neg (gt X 0)) operation. */
9451 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9452 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9453 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9454 && (code == LSHIFTRT || code == ASHIFTRT)
9455 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9456 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9457 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9460 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9463 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9464 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9471 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9472 if the truncate does not affect the value. */
9473 if (code == LSHIFTRT
9474 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9475 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9476 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9477 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9478 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9480 rtx varop_inner = XEXP (varop, 0);
9483 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9484 XEXP (varop_inner, 0),
9486 + INTVAL (XEXP (varop_inner, 1))));
9487 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9501 /* We need to determine what mode to do the shift in. If the shift is
9502 a right shift or ROTATE, we must always do it in the mode it was
9503 originally done in. Otherwise, we can do it in MODE, the widest mode
9504 encountered. The code we care about is that of the shift that will
9505 actually be done, not the shift that was originally requested. */
9507 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9508 ? result_mode : mode);
9510 /* We have now finished analyzing the shift. The result should be
9511 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9512 OUTER_OP is non-NIL, it is an operation that needs to be applied
9513 to the result of the shift. OUTER_CONST is the relevant constant,
9514 but we must turn off all bits turned off in the shift.
9516 If we were passed a value for X, see if we can use any pieces of
9517 it. If not, make new rtx. */
9519 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9520 && GET_CODE (XEXP (x, 1)) == CONST_INT
9521 && INTVAL (XEXP (x, 1)) == count)
9522 const_rtx = XEXP (x, 1);
9524 const_rtx = GEN_INT (count);
9526 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9527 && GET_MODE (XEXP (x, 0)) == shift_mode
9528 && SUBREG_REG (XEXP (x, 0)) == varop)
9529 varop = XEXP (x, 0);
9530 else if (GET_MODE (varop) != shift_mode)
9531 varop = gen_lowpart_for_combine (shift_mode, varop);
9533 /* If we can't make the SUBREG, try to return what we were given. */
9534 if (GET_CODE (varop) == CLOBBER)
9535 return x ? x : varop;
9537 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9542 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9543 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9545 SUBST (XEXP (x, 0), varop);
9546 SUBST (XEXP (x, 1), const_rtx);
9549 /* If we have an outer operation and we just made a shift, it is
9550 possible that we could have simplified the shift were it not
9551 for the outer operation. So try to do the simplification
9554 if (outer_op != NIL && GET_CODE (x) == code
9555 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9556 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9557 INTVAL (XEXP (x, 1)));
9559 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9560 turn off all the bits that the shift would have turned off. */
9561 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9562 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9563 GET_MODE_MASK (result_mode) >> orig_count);
9565 /* Do the remainder of the processing in RESULT_MODE. */
9566 x = gen_lowpart_for_combine (result_mode, x);
9568 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9571 x = gen_unary (NOT, result_mode, result_mode, x);
9573 if (outer_op != NIL)
9575 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9576 outer_const = trunc_int_for_mode (outer_const, result_mode);
9578 if (outer_op == AND)
9579 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9580 else if (outer_op == SET)
9581 /* This means that we have determined that the result is
9582 equivalent to a constant. This should be rare. */
9583 x = GEN_INT (outer_const);
9584 else if (GET_RTX_CLASS (outer_op) == '1')
9585 x = gen_unary (outer_op, result_mode, result_mode, x);
9587 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9593 /* Like recog, but we receive the address of a pointer to a new pattern.
9594 We try to match the rtx that the pointer points to.
9595 If that fails, we may try to modify or replace the pattern,
9596 storing the replacement into the same pointer object.
9598 Modifications include deletion or addition of CLOBBERs.
9600 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9601 the CLOBBERs are placed.
9603 The value is the final insn code from the pattern ultimately matched,
9607 recog_for_combine (pnewpat, insn, pnotes)
9612 register rtx pat = *pnewpat;
9613 int insn_code_number;
9614 int num_clobbers_to_add = 0;
9619 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9620 we use to indicate that something didn't match. If we find such a
9621 thing, force rejection. */
9622 if (GET_CODE (pat) == PARALLEL)
9623 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9624 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9625 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9628 /* Remove the old notes prior to trying to recognize the new pattern. */
9629 old_notes = REG_NOTES (insn);
9630 REG_NOTES (insn) = 0;
9632 /* Is the result of combination a valid instruction? */
9633 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9635 /* If it isn't, there is the possibility that we previously had an insn
9636 that clobbered some register as a side effect, but the combined
9637 insn doesn't need to do that. So try once more without the clobbers
9638 unless this represents an ASM insn. */
9640 if (insn_code_number < 0 && ! check_asm_operands (pat)
9641 && GET_CODE (pat) == PARALLEL)
9645 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9646 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9649 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9653 SUBST_INT (XVECLEN (pat, 0), pos);
9656 pat = XVECEXP (pat, 0, 0);
9658 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9661 REG_NOTES (insn) = old_notes;
9663 /* If we had any clobbers to add, make a new pattern than contains
9664 them. Then check to make sure that all of them are dead. */
9665 if (num_clobbers_to_add)
9667 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9668 gen_rtvec (GET_CODE (pat) == PARALLEL
9670 + num_clobbers_to_add)
9671 : num_clobbers_to_add + 1));
9673 if (GET_CODE (pat) == PARALLEL)
9674 for (i = 0; i < XVECLEN (pat, 0); i++)
9675 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9677 XVECEXP (newpat, 0, 0) = pat;
9679 add_clobbers (newpat, insn_code_number);
9681 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9682 i < XVECLEN (newpat, 0); i++)
9684 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9685 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9687 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9688 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9696 return insn_code_number;
9699 /* Like gen_lowpart but for use by combine. In combine it is not possible
9700 to create any new pseudoregs. However, it is safe to create
9701 invalid memory addresses, because combine will try to recognize
9702 them and all they will do is make the combine attempt fail.
9704 If for some reason this cannot do its job, an rtx
9705 (clobber (const_int 0)) is returned.
9706 An insn containing that will not be recognized. */
9711 gen_lowpart_for_combine (mode, x)
9712 enum machine_mode mode;
9717 if (GET_MODE (x) == mode)
9720 /* We can only support MODE being wider than a word if X is a
9721 constant integer or has a mode the same size. */
9723 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9724 && ! ((GET_MODE (x) == VOIDmode
9725 && (GET_CODE (x) == CONST_INT
9726 || GET_CODE (x) == CONST_DOUBLE))
9727 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9728 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9730 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9731 won't know what to do. So we will strip off the SUBREG here and
9732 process normally. */
9733 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9736 if (GET_MODE (x) == mode)
9740 result = gen_lowpart_common (mode, x);
9741 #ifdef CLASS_CANNOT_CHANGE_MODE
9743 && GET_CODE (result) == SUBREG
9744 && GET_CODE (SUBREG_REG (result)) == REG
9745 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9746 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9747 GET_MODE (SUBREG_REG (result))))
9748 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9754 if (GET_CODE (x) == MEM)
9756 register int offset = 0;
9759 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9761 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9762 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9764 /* If we want to refer to something bigger than the original memref,
9765 generate a perverse subreg instead. That will force a reload
9766 of the original memref X. */
9767 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9768 return gen_rtx_SUBREG (mode, x, 0);
9770 if (WORDS_BIG_ENDIAN)
9771 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9772 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9774 if (BYTES_BIG_ENDIAN)
9776 /* Adjust the address so that the address-after-the-data is
9778 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9779 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9781 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9782 MEM_COPY_ATTRIBUTES (new, x);
9786 /* If X is a comparison operator, rewrite it in a new mode. This
9787 probably won't match, but may allow further simplifications. */
9788 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9789 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9791 /* If we couldn't simplify X any other way, just enclose it in a
9792 SUBREG. Normally, this SUBREG won't match, but some patterns may
9793 include an explicit SUBREG or we may simplify it further in combine. */
9798 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9799 word = ((GET_MODE_SIZE (GET_MODE (x))
9800 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9802 return gen_rtx_SUBREG (mode, x, word);
9806 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9807 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9809 If the identical expression was previously in the insn (in the undobuf),
9810 it will be returned. Only if it is not found will a new expression
9815 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9817 #ifndef ANSI_PROTOTYPES
9819 enum machine_mode mode;
9831 #ifndef ANSI_PROTOTYPES
9832 code = va_arg (p, enum rtx_code);
9833 mode = va_arg (p, enum machine_mode);
9836 n_args = GET_RTX_LENGTH (code);
9837 fmt = GET_RTX_FORMAT (code);
9839 if (n_args == 0 || n_args > 3)
9842 /* Get each arg and verify that it is supposed to be an expression. */
9843 for (j = 0; j < n_args; j++)
9848 args[j] = va_arg (p, rtx);
9853 /* See if this is in undobuf. Be sure we don't use objects that came
9854 from another insn; this could produce circular rtl structures. */
9856 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9858 && GET_CODE (undo->old_contents.r) == code
9859 && GET_MODE (undo->old_contents.r) == mode)
9861 for (j = 0; j < n_args; j++)
9862 if (XEXP (undo->old_contents.r, j) != args[j])
9866 return undo->old_contents.r;
9869 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9870 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9871 rt = rtx_alloc (code);
9872 PUT_MODE (rt, mode);
9873 XEXP (rt, 0) = args[0];
9876 XEXP (rt, 1) = args[1];
9878 XEXP (rt, 2) = args[2];
9883 /* These routines make binary and unary operations by first seeing if they
9884 fold; if not, a new expression is allocated. */
9887 gen_binary (code, mode, op0, op1)
9889 enum machine_mode mode;
9895 if (GET_RTX_CLASS (code) == 'c'
9896 && (GET_CODE (op0) == CONST_INT
9897 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9898 tem = op0, op0 = op1, op1 = tem;
9900 if (GET_RTX_CLASS (code) == '<')
9902 enum machine_mode op_mode = GET_MODE (op0);
9904 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9905 just (REL_OP X Y). */
9906 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9908 op1 = XEXP (op0, 1);
9909 op0 = XEXP (op0, 0);
9910 op_mode = GET_MODE (op0);
9913 if (op_mode == VOIDmode)
9914 op_mode = GET_MODE (op1);
9915 result = simplify_relational_operation (code, op_mode, op0, op1);
9918 result = simplify_binary_operation (code, mode, op0, op1);
9923 /* Put complex operands first and constants second. */
9924 if (GET_RTX_CLASS (code) == 'c'
9925 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9926 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9927 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9928 || (GET_CODE (op0) == SUBREG
9929 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9930 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9931 return gen_rtx_combine (code, mode, op1, op0);
9933 /* If we are turning off bits already known off in OP0, we need not do
9935 else if (code == AND && GET_CODE (op1) == CONST_INT
9936 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9937 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9940 return gen_rtx_combine (code, mode, op0, op1);
9944 gen_unary (code, mode, op0_mode, op0)
9946 enum machine_mode mode, op0_mode;
9949 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9954 return gen_rtx_combine (code, mode, op0);
9957 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9958 comparison code that will be tested.
9960 The result is a possibly different comparison code to use. *POP0 and
9961 *POP1 may be updated.
9963 It is possible that we might detect that a comparison is either always
9964 true or always false. However, we do not perform general constant
9965 folding in combine, so this knowledge isn't useful. Such tautologies
9966 should have been detected earlier. Hence we ignore all such cases. */
9968 static enum rtx_code
9969 simplify_comparison (code, pop0, pop1)
9978 enum machine_mode mode, tmode;
9980 /* Try a few ways of applying the same transformation to both operands. */
9983 #ifndef WORD_REGISTER_OPERATIONS
9984 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9985 so check specially. */
9986 if (code != GTU && code != GEU && code != LTU && code != LEU
9987 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9988 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9989 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9990 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9991 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9992 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9993 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9994 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9995 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9996 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9997 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9998 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9999 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10000 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10001 && (INTVAL (XEXP (op0, 1))
10002 == (GET_MODE_BITSIZE (GET_MODE (op0))
10003 - (GET_MODE_BITSIZE
10004 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10006 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10007 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10011 /* If both operands are the same constant shift, see if we can ignore the
10012 shift. We can if the shift is a rotate or if the bits shifted out of
10013 this shift are known to be zero for both inputs and if the type of
10014 comparison is compatible with the shift. */
10015 if (GET_CODE (op0) == GET_CODE (op1)
10016 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10017 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10018 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10019 && (code != GT && code != LT && code != GE && code != LE))
10020 || (GET_CODE (op0) == ASHIFTRT
10021 && (code != GTU && code != LTU
10022 && code != GEU && code != GEU)))
10023 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10024 && INTVAL (XEXP (op0, 1)) >= 0
10025 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10026 && XEXP (op0, 1) == XEXP (op1, 1))
10028 enum machine_mode mode = GET_MODE (op0);
10029 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10030 int shift_count = INTVAL (XEXP (op0, 1));
10032 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10033 mask &= (mask >> shift_count) << shift_count;
10034 else if (GET_CODE (op0) == ASHIFT)
10035 mask = (mask & (mask << shift_count)) >> shift_count;
10037 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10038 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10039 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10044 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10045 SUBREGs are of the same mode, and, in both cases, the AND would
10046 be redundant if the comparison was done in the narrower mode,
10047 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10048 and the operand's possibly nonzero bits are 0xffffff01; in that case
10049 if we only care about QImode, we don't need the AND). This case
10050 occurs if the output mode of an scc insn is not SImode and
10051 STORE_FLAG_VALUE == 1 (e.g., the 386).
10053 Similarly, check for a case where the AND's are ZERO_EXTEND
10054 operations from some narrower mode even though a SUBREG is not
10057 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10058 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10059 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10061 rtx inner_op0 = XEXP (op0, 0);
10062 rtx inner_op1 = XEXP (op1, 0);
10063 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10064 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10067 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10068 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10069 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10070 && (GET_MODE (SUBREG_REG (inner_op0))
10071 == GET_MODE (SUBREG_REG (inner_op1)))
10072 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10073 <= HOST_BITS_PER_WIDE_INT)
10074 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10075 GET_MODE (SUBREG_REG (inner_op0)))))
10076 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10077 GET_MODE (SUBREG_REG (inner_op1))))))
10079 op0 = SUBREG_REG (inner_op0);
10080 op1 = SUBREG_REG (inner_op1);
10082 /* The resulting comparison is always unsigned since we masked
10083 off the original sign bit. */
10084 code = unsigned_condition (code);
10090 for (tmode = GET_CLASS_NARROWEST_MODE
10091 (GET_MODE_CLASS (GET_MODE (op0)));
10092 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10093 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10095 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10096 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10097 code = unsigned_condition (code);
10106 /* If both operands are NOT, we can strip off the outer operation
10107 and adjust the comparison code for swapped operands; similarly for
10108 NEG, except that this must be an equality comparison. */
10109 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10110 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10111 && (code == EQ || code == NE)))
10112 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10118 /* If the first operand is a constant, swap the operands and adjust the
10119 comparison code appropriately, but don't do this if the second operand
10120 is already a constant integer. */
10121 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10123 tem = op0, op0 = op1, op1 = tem;
10124 code = swap_condition (code);
10127 /* We now enter a loop during which we will try to simplify the comparison.
10128 For the most part, we only are concerned with comparisons with zero,
10129 but some things may really be comparisons with zero but not start
10130 out looking that way. */
10132 while (GET_CODE (op1) == CONST_INT)
10134 enum machine_mode mode = GET_MODE (op0);
10135 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10136 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10137 int equality_comparison_p;
10138 int sign_bit_comparison_p;
10139 int unsigned_comparison_p;
10140 HOST_WIDE_INT const_op;
10142 /* We only want to handle integral modes. This catches VOIDmode,
10143 CCmode, and the floating-point modes. An exception is that we
10144 can handle VOIDmode if OP0 is a COMPARE or a comparison
10147 if (GET_MODE_CLASS (mode) != MODE_INT
10148 && ! (mode == VOIDmode
10149 && (GET_CODE (op0) == COMPARE
10150 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10153 /* Get the constant we are comparing against and turn off all bits
10154 not on in our mode. */
10155 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10157 /* If we are comparing against a constant power of two and the value
10158 being compared can only have that single bit nonzero (e.g., it was
10159 `and'ed with that bit), we can replace this with a comparison
10162 && (code == EQ || code == NE || code == GE || code == GEU
10163 || code == LT || code == LTU)
10164 && mode_width <= HOST_BITS_PER_WIDE_INT
10165 && exact_log2 (const_op) >= 0
10166 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10168 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10169 op1 = const0_rtx, const_op = 0;
10172 /* Similarly, if we are comparing a value known to be either -1 or
10173 0 with -1, change it to the opposite comparison against zero. */
10176 && (code == EQ || code == NE || code == GT || code == LE
10177 || code == GEU || code == LTU)
10178 && num_sign_bit_copies (op0, mode) == mode_width)
10180 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10181 op1 = const0_rtx, const_op = 0;
10184 /* Do some canonicalizations based on the comparison code. We prefer
10185 comparisons against zero and then prefer equality comparisons.
10186 If we can reduce the size of a constant, we will do that too. */
10191 /* < C is equivalent to <= (C - 1) */
10195 op1 = GEN_INT (const_op);
10197 /* ... fall through to LE case below. */
10203 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10207 op1 = GEN_INT (const_op);
10211 /* If we are doing a <= 0 comparison on a value known to have
10212 a zero sign bit, we can replace this with == 0. */
10213 else if (const_op == 0
10214 && mode_width <= HOST_BITS_PER_WIDE_INT
10215 && (nonzero_bits (op0, mode)
10216 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10221 /* >= C is equivalent to > (C - 1). */
10225 op1 = GEN_INT (const_op);
10227 /* ... fall through to GT below. */
10233 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10237 op1 = GEN_INT (const_op);
10241 /* If we are doing a > 0 comparison on a value known to have
10242 a zero sign bit, we can replace this with != 0. */
10243 else if (const_op == 0
10244 && mode_width <= HOST_BITS_PER_WIDE_INT
10245 && (nonzero_bits (op0, mode)
10246 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10251 /* < C is equivalent to <= (C - 1). */
10255 op1 = GEN_INT (const_op);
10257 /* ... fall through ... */
10260 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10261 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10262 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10264 const_op = 0, op1 = const0_rtx;
10272 /* unsigned <= 0 is equivalent to == 0 */
10276 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10277 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10278 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10280 const_op = 0, op1 = const0_rtx;
10286 /* >= C is equivalent to < (C - 1). */
10290 op1 = GEN_INT (const_op);
10292 /* ... fall through ... */
10295 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10296 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10297 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10299 const_op = 0, op1 = const0_rtx;
10307 /* unsigned > 0 is equivalent to != 0 */
10311 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10312 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10313 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10315 const_op = 0, op1 = const0_rtx;
10324 /* Compute some predicates to simplify code below. */
10326 equality_comparison_p = (code == EQ || code == NE);
10327 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10328 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10331 /* If this is a sign bit comparison and we can do arithmetic in
10332 MODE, say that we will only be needing the sign bit of OP0. */
10333 if (sign_bit_comparison_p
10334 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10335 op0 = force_to_mode (op0, mode,
10337 << (GET_MODE_BITSIZE (mode) - 1)),
10340 /* Now try cases based on the opcode of OP0. If none of the cases
10341 does a "continue", we exit this loop immediately after the
10344 switch (GET_CODE (op0))
10347 /* If we are extracting a single bit from a variable position in
10348 a constant that has only a single bit set and are comparing it
10349 with zero, we can convert this into an equality comparison
10350 between the position and the location of the single bit. */
10352 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10353 && XEXP (op0, 1) == const1_rtx
10354 && equality_comparison_p && const_op == 0
10355 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10357 if (BITS_BIG_ENDIAN)
10360 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10361 if (mode == VOIDmode)
10363 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10365 i = BITS_PER_WORD - 1 - i;
10369 op0 = XEXP (op0, 2);
10373 /* Result is nonzero iff shift count is equal to I. */
10374 code = reverse_condition (code);
10378 /* ... fall through ... */
10381 tem = expand_compound_operation (op0);
10390 /* If testing for equality, we can take the NOT of the constant. */
10391 if (equality_comparison_p
10392 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10394 op0 = XEXP (op0, 0);
10399 /* If just looking at the sign bit, reverse the sense of the
10401 if (sign_bit_comparison_p)
10403 op0 = XEXP (op0, 0);
10404 code = (code == GE ? LT : GE);
10410 /* If testing for equality, we can take the NEG of the constant. */
10411 if (equality_comparison_p
10412 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10414 op0 = XEXP (op0, 0);
10419 /* The remaining cases only apply to comparisons with zero. */
10423 /* When X is ABS or is known positive,
10424 (neg X) is < 0 if and only if X != 0. */
10426 if (sign_bit_comparison_p
10427 && (GET_CODE (XEXP (op0, 0)) == ABS
10428 || (mode_width <= HOST_BITS_PER_WIDE_INT
10429 && (nonzero_bits (XEXP (op0, 0), mode)
10430 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10432 op0 = XEXP (op0, 0);
10433 code = (code == LT ? NE : EQ);
10437 /* If we have NEG of something whose two high-order bits are the
10438 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10439 if (num_sign_bit_copies (op0, mode) >= 2)
10441 op0 = XEXP (op0, 0);
10442 code = swap_condition (code);
10448 /* If we are testing equality and our count is a constant, we
10449 can perform the inverse operation on our RHS. */
10450 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10451 && (tem = simplify_binary_operation (ROTATERT, mode,
10452 op1, XEXP (op0, 1))) != 0)
10454 op0 = XEXP (op0, 0);
10459 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10460 a particular bit. Convert it to an AND of a constant of that
10461 bit. This will be converted into a ZERO_EXTRACT. */
10462 if (const_op == 0 && sign_bit_comparison_p
10463 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10464 && mode_width <= HOST_BITS_PER_WIDE_INT)
10466 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10469 - INTVAL (XEXP (op0, 1)))));
10470 code = (code == LT ? NE : EQ);
10474 /* Fall through. */
10477 /* ABS is ignorable inside an equality comparison with zero. */
10478 if (const_op == 0 && equality_comparison_p)
10480 op0 = XEXP (op0, 0);
10486 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10487 to (compare FOO CONST) if CONST fits in FOO's mode and we
10488 are either testing inequality or have an unsigned comparison
10489 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10490 if (! unsigned_comparison_p
10491 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10492 <= HOST_BITS_PER_WIDE_INT)
10493 && ((unsigned HOST_WIDE_INT) const_op
10494 < (((unsigned HOST_WIDE_INT) 1
10495 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10497 op0 = XEXP (op0, 0);
10503 /* Check for the case where we are comparing A - C1 with C2,
10504 both constants are smaller than 1/2 the maximum positive
10505 value in MODE, and the comparison is equality or unsigned.
10506 In that case, if A is either zero-extended to MODE or has
10507 sufficient sign bits so that the high-order bit in MODE
10508 is a copy of the sign in the inner mode, we can prove that it is
10509 safe to do the operation in the wider mode. This simplifies
10510 many range checks. */
10512 if (mode_width <= HOST_BITS_PER_WIDE_INT
10513 && subreg_lowpart_p (op0)
10514 && GET_CODE (SUBREG_REG (op0)) == PLUS
10515 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10516 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10517 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10518 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10519 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10520 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10521 GET_MODE (SUBREG_REG (op0)))
10522 & ~GET_MODE_MASK (mode))
10523 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10524 GET_MODE (SUBREG_REG (op0)))
10525 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10526 - GET_MODE_BITSIZE (mode)))))
10528 op0 = SUBREG_REG (op0);
10532 /* If the inner mode is narrower and we are extracting the low part,
10533 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10534 if (subreg_lowpart_p (op0)
10535 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10536 /* Fall through */ ;
10540 /* ... fall through ... */
10543 if ((unsigned_comparison_p || equality_comparison_p)
10544 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10545 <= HOST_BITS_PER_WIDE_INT)
10546 && ((unsigned HOST_WIDE_INT) const_op
10547 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10549 op0 = XEXP (op0, 0);
10555 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10556 this for equality comparisons due to pathological cases involving
10558 if (equality_comparison_p
10559 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10560 op1, XEXP (op0, 1))))
10562 op0 = XEXP (op0, 0);
10567 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10568 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10569 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10571 op0 = XEXP (XEXP (op0, 0), 0);
10572 code = (code == LT ? EQ : NE);
10578 /* We used to optimize signed comparisons against zero, but that
10579 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10580 arrive here as equality comparisons, or (GEU, LTU) are
10581 optimized away. No need to special-case them. */
10583 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10584 (eq B (minus A C)), whichever simplifies. We can only do
10585 this for equality comparisons due to pathological cases involving
10587 if (equality_comparison_p
10588 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10589 XEXP (op0, 1), op1)))
10591 op0 = XEXP (op0, 0);
10596 if (equality_comparison_p
10597 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10598 XEXP (op0, 0), op1)))
10600 op0 = XEXP (op0, 1);
10605 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10606 of bits in X minus 1, is one iff X > 0. */
10607 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10608 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10609 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10610 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10612 op0 = XEXP (op0, 1);
10613 code = (code == GE ? LE : GT);
10619 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10620 if C is zero or B is a constant. */
10621 if (equality_comparison_p
10622 && 0 != (tem = simplify_binary_operation (XOR, mode,
10623 XEXP (op0, 1), op1)))
10625 op0 = XEXP (op0, 0);
10632 case LT: case LTU: case LE: case LEU:
10633 case GT: case GTU: case GE: case GEU:
10634 /* We can't do anything if OP0 is a condition code value, rather
10635 than an actual data value. */
10638 || XEXP (op0, 0) == cc0_rtx
10640 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10643 /* Get the two operands being compared. */
10644 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10645 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10647 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10649 /* Check for the cases where we simply want the result of the
10650 earlier test or the opposite of that result. */
10652 || (code == EQ && reversible_comparison_p (op0))
10653 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10654 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10655 && (STORE_FLAG_VALUE
10656 & (((HOST_WIDE_INT) 1
10657 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10659 || (code == GE && reversible_comparison_p (op0)))))
10661 code = (code == LT || code == NE
10662 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10663 op0 = tem, op1 = tem1;
10669 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10671 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10672 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10673 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10675 op0 = XEXP (op0, 1);
10676 code = (code == GE ? GT : LE);
10682 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10683 will be converted to a ZERO_EXTRACT later. */
10684 if (const_op == 0 && equality_comparison_p
10685 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10686 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10688 op0 = simplify_and_const_int
10689 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10691 XEXP (XEXP (op0, 0), 1)),
10692 (HOST_WIDE_INT) 1);
10696 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10697 zero and X is a comparison and C1 and C2 describe only bits set
10698 in STORE_FLAG_VALUE, we can compare with X. */
10699 if (const_op == 0 && equality_comparison_p
10700 && mode_width <= HOST_BITS_PER_WIDE_INT
10701 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10702 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10703 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10704 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10705 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10707 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10708 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10709 if ((~STORE_FLAG_VALUE & mask) == 0
10710 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10711 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10712 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10714 op0 = XEXP (XEXP (op0, 0), 0);
10719 /* If we are doing an equality comparison of an AND of a bit equal
10720 to the sign bit, replace this with a LT or GE comparison of
10721 the underlying value. */
10722 if (equality_comparison_p
10724 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10725 && mode_width <= HOST_BITS_PER_WIDE_INT
10726 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10727 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10729 op0 = XEXP (op0, 0);
10730 code = (code == EQ ? GE : LT);
10734 /* If this AND operation is really a ZERO_EXTEND from a narrower
10735 mode, the constant fits within that mode, and this is either an
10736 equality or unsigned comparison, try to do this comparison in
10737 the narrower mode. */
10738 if ((equality_comparison_p || unsigned_comparison_p)
10739 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10740 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10741 & GET_MODE_MASK (mode))
10743 && const_op >> i == 0
10744 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10746 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10750 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10751 in both M1 and M2 and the SUBREG is either paradoxical or
10752 represents the low part, permute the SUBREG and the AND and
10754 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10756 #ifdef WORD_REGISTER_OPERATIONS
10758 > (GET_MODE_BITSIZE
10759 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10760 && mode_width <= BITS_PER_WORD)
10763 <= (GET_MODE_BITSIZE
10764 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10765 && subreg_lowpart_p (XEXP (op0, 0))))
10766 #ifndef WORD_REGISTER_OPERATIONS
10767 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10768 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10769 As originally written the upper bits have a defined value
10770 due to the AND operation. However, if we commute the AND
10771 inside the SUBREG then they no longer have defined values
10772 and the meaning of the code has been changed. */
10773 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10774 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10776 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10777 && mode_width <= HOST_BITS_PER_WIDE_INT
10778 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10779 <= HOST_BITS_PER_WIDE_INT)
10780 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10781 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10782 & INTVAL (XEXP (op0, 1)))
10783 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10784 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10785 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10789 = gen_lowpart_for_combine
10791 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10792 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10799 /* If we have (compare (ashift FOO N) (const_int C)) and
10800 the high order N bits of FOO (N+1 if an inequality comparison)
10801 are known to be zero, we can do this by comparing FOO with C
10802 shifted right N bits so long as the low-order N bits of C are
10804 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10805 && INTVAL (XEXP (op0, 1)) >= 0
10806 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10807 < HOST_BITS_PER_WIDE_INT)
10809 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10810 && mode_width <= HOST_BITS_PER_WIDE_INT
10811 && (nonzero_bits (XEXP (op0, 0), mode)
10812 & ~(mask >> (INTVAL (XEXP (op0, 1))
10813 + ! equality_comparison_p))) == 0)
10815 /* We must perform a logical shift, not an arithmetic one,
10816 as we want the top N bits of C to be zero. */
10817 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10819 temp >>= INTVAL (XEXP (op0, 1));
10820 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10821 op0 = XEXP (op0, 0);
10825 /* If we are doing a sign bit comparison, it means we are testing
10826 a particular bit. Convert it to the appropriate AND. */
10827 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10828 && mode_width <= HOST_BITS_PER_WIDE_INT)
10830 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10833 - INTVAL (XEXP (op0, 1)))));
10834 code = (code == LT ? NE : EQ);
10838 /* If this an equality comparison with zero and we are shifting
10839 the low bit to the sign bit, we can convert this to an AND of the
10841 if (const_op == 0 && equality_comparison_p
10842 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10843 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10845 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10846 (HOST_WIDE_INT) 1);
10852 /* If this is an equality comparison with zero, we can do this
10853 as a logical shift, which might be much simpler. */
10854 if (equality_comparison_p && const_op == 0
10855 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10857 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10859 INTVAL (XEXP (op0, 1)));
10863 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10864 do the comparison in a narrower mode. */
10865 if (! unsigned_comparison_p
10866 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10867 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10868 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10869 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10870 MODE_INT, 1)) != BLKmode
10871 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10872 || ((unsigned HOST_WIDE_INT) -const_op
10873 <= GET_MODE_MASK (tmode))))
10875 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10879 /* Likewise if OP0 is a PLUS of a sign extension with a
10880 constant, which is usually represented with the PLUS
10881 between the shifts. */
10882 if (! unsigned_comparison_p
10883 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10884 && GET_CODE (XEXP (op0, 0)) == PLUS
10885 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10886 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10887 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10888 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10889 MODE_INT, 1)) != BLKmode
10890 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10891 || ((unsigned HOST_WIDE_INT) -const_op
10892 <= GET_MODE_MASK (tmode))))
10894 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10895 rtx add_const = XEXP (XEXP (op0, 0), 1);
10896 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10899 op0 = gen_binary (PLUS, tmode,
10900 gen_lowpart_for_combine (tmode, inner),
10905 /* ... fall through ... */
10907 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10908 the low order N bits of FOO are known to be zero, we can do this
10909 by comparing FOO with C shifted left N bits so long as no
10910 overflow occurs. */
10911 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10912 && INTVAL (XEXP (op0, 1)) >= 0
10913 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10914 && mode_width <= HOST_BITS_PER_WIDE_INT
10915 && (nonzero_bits (XEXP (op0, 0), mode)
10916 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10918 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10921 const_op <<= INTVAL (XEXP (op0, 1));
10922 op1 = GEN_INT (const_op);
10923 op0 = XEXP (op0, 0);
10927 /* If we are using this shift to extract just the sign bit, we
10928 can replace this with an LT or GE comparison. */
10930 && (equality_comparison_p || sign_bit_comparison_p)
10931 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10932 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10934 op0 = XEXP (op0, 0);
10935 code = (code == NE || code == GT ? LT : GE);
10947 /* Now make any compound operations involved in this comparison. Then,
10948 check for an outmost SUBREG on OP0 that is not doing anything or is
10949 paradoxical. The latter case can only occur when it is known that the
10950 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10951 We can never remove a SUBREG for a non-equality comparison because the
10952 sign bit is in a different place in the underlying object. */
10954 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10955 op1 = make_compound_operation (op1, SET);
10957 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10958 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10959 && (code == NE || code == EQ)
10960 && ((GET_MODE_SIZE (GET_MODE (op0))
10961 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10963 op0 = SUBREG_REG (op0);
10964 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10967 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10968 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10969 && (code == NE || code == EQ)
10970 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10971 <= HOST_BITS_PER_WIDE_INT)
10972 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10973 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10974 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10976 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10977 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10978 op0 = SUBREG_REG (op0), op1 = tem;
10980 /* We now do the opposite procedure: Some machines don't have compare
10981 insns in all modes. If OP0's mode is an integer mode smaller than a
10982 word and we can't do a compare in that mode, see if there is a larger
10983 mode for which we can do the compare. There are a number of cases in
10984 which we can use the wider mode. */
10986 mode = GET_MODE (op0);
10987 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10988 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10989 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10990 for (tmode = GET_MODE_WIDER_MODE (mode);
10992 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10993 tmode = GET_MODE_WIDER_MODE (tmode))
10994 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10996 /* If the only nonzero bits in OP0 and OP1 are those in the
10997 narrower mode and this is an equality or unsigned comparison,
10998 we can use the wider mode. Similarly for sign-extended
10999 values, in which case it is true for all comparisons. */
11000 if (((code == EQ || code == NE
11001 || code == GEU || code == GTU || code == LEU || code == LTU)
11002 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
11003 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
11004 || ((num_sign_bit_copies (op0, tmode)
11005 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11006 && (num_sign_bit_copies (op1, tmode)
11007 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11009 /* If OP0 is an AND and we don't have an AND in MODE either,
11010 make a new AND in the proper mode. */
11011 if (GET_CODE (op0) == AND
11012 && (add_optab->handlers[(int) mode].insn_code
11013 == CODE_FOR_nothing))
11014 op0 = gen_binary (AND, tmode,
11015 gen_lowpart_for_combine (tmode,
11017 gen_lowpart_for_combine (tmode,
11020 op0 = gen_lowpart_for_combine (tmode, op0);
11021 op1 = gen_lowpart_for_combine (tmode, op1);
11025 /* If this is a test for negative, we can make an explicit
11026 test of the sign bit. */
11028 if (op1 == const0_rtx && (code == LT || code == GE)
11029 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11031 op0 = gen_binary (AND, tmode,
11032 gen_lowpart_for_combine (tmode, op0),
11033 GEN_INT ((HOST_WIDE_INT) 1
11034 << (GET_MODE_BITSIZE (mode) - 1)));
11035 code = (code == LT) ? NE : EQ;
11040 #ifdef CANONICALIZE_COMPARISON
11041 /* If this machine only supports a subset of valid comparisons, see if we
11042 can convert an unsupported one into a supported one. */
11043 CANONICALIZE_COMPARISON (code, op0, op1);
11052 /* Return 1 if we know that X, a comparison operation, is not operating
11053 on a floating-point value or is EQ or NE, meaning that we can safely
11057 reversible_comparison_p (x)
11060 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
11062 || GET_CODE (x) == NE || GET_CODE (x) == EQ
11063 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
11066 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
11069 case MODE_PARTIAL_INT:
11070 case MODE_COMPLEX_INT:
11074 /* If the mode of the condition codes tells us that this is safe,
11075 we need look no further. */
11076 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
11079 /* Otherwise try and find where the condition codes were last set and
11081 x = get_last_value (XEXP (x, 0));
11082 return (x && GET_CODE (x) == COMPARE
11083 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
11090 /* Utility function for following routine. Called when X is part of a value
11091 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11092 for each register mentioned. Similar to mention_regs in cse.c */
11095 update_table_tick (x)
11098 register enum rtx_code code = GET_CODE (x);
11099 register const char *fmt = GET_RTX_FORMAT (code);
11104 unsigned int regno = REGNO (x);
11105 unsigned int endregno
11106 = regno + (regno < FIRST_PSEUDO_REGISTER
11107 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11110 for (r = regno; r < endregno; r++)
11111 reg_last_set_table_tick[r] = label_tick;
11116 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11117 /* Note that we can't have an "E" in values stored; see
11118 get_last_value_validate. */
11120 update_table_tick (XEXP (x, i));
11123 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11124 are saying that the register is clobbered and we no longer know its
11125 value. If INSN is zero, don't update reg_last_set; this is only permitted
11126 with VALUE also zero and is used to invalidate the register. */
11129 record_value_for_reg (reg, insn, value)
11134 unsigned int regno = REGNO (reg);
11135 unsigned int endregno
11136 = regno + (regno < FIRST_PSEUDO_REGISTER
11137 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11140 /* If VALUE contains REG and we have a previous value for REG, substitute
11141 the previous value. */
11142 if (value && insn && reg_overlap_mentioned_p (reg, value))
11146 /* Set things up so get_last_value is allowed to see anything set up to
11148 subst_low_cuid = INSN_CUID (insn);
11149 tem = get_last_value (reg);
11151 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11152 it isn't going to be useful and will take a lot of time to process,
11153 so just use the CLOBBER. */
11157 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11158 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11159 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11160 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11161 tem = XEXP (tem, 0);
11163 value = replace_rtx (copy_rtx (value), reg, tem);
11167 /* For each register modified, show we don't know its value, that
11168 we don't know about its bitwise content, that its value has been
11169 updated, and that we don't know the location of the death of the
11171 for (i = regno; i < endregno; i++)
11174 reg_last_set[i] = insn;
11176 reg_last_set_value[i] = 0;
11177 reg_last_set_mode[i] = 0;
11178 reg_last_set_nonzero_bits[i] = 0;
11179 reg_last_set_sign_bit_copies[i] = 0;
11180 reg_last_death[i] = 0;
11183 /* Mark registers that are being referenced in this value. */
11185 update_table_tick (value);
11187 /* Now update the status of each register being set.
11188 If someone is using this register in this block, set this register
11189 to invalid since we will get confused between the two lives in this
11190 basic block. This makes using this register always invalid. In cse, we
11191 scan the table to invalidate all entries using this register, but this
11192 is too much work for us. */
11194 for (i = regno; i < endregno; i++)
11196 reg_last_set_label[i] = label_tick;
11197 if (value && reg_last_set_table_tick[i] == label_tick)
11198 reg_last_set_invalid[i] = 1;
11200 reg_last_set_invalid[i] = 0;
11203 /* The value being assigned might refer to X (like in "x++;"). In that
11204 case, we must replace it with (clobber (const_int 0)) to prevent
11206 if (value && ! get_last_value_validate (&value, insn,
11207 reg_last_set_label[regno], 0))
11209 value = copy_rtx (value);
11210 if (! get_last_value_validate (&value, insn,
11211 reg_last_set_label[regno], 1))
11215 /* For the main register being modified, update the value, the mode, the
11216 nonzero bits, and the number of sign bit copies. */
11218 reg_last_set_value[regno] = value;
11222 subst_low_cuid = INSN_CUID (insn);
11223 reg_last_set_mode[regno] = GET_MODE (reg);
11224 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11225 reg_last_set_sign_bit_copies[regno]
11226 = num_sign_bit_copies (value, GET_MODE (reg));
11230 /* Called via note_stores from record_dead_and_set_regs to handle one
11231 SET or CLOBBER in an insn. DATA is the instruction in which the
11232 set is occurring. */
11235 record_dead_and_set_regs_1 (dest, setter, data)
11239 rtx record_dead_insn = (rtx) data;
11241 if (GET_CODE (dest) == SUBREG)
11242 dest = SUBREG_REG (dest);
11244 if (GET_CODE (dest) == REG)
11246 /* If we are setting the whole register, we know its value. Otherwise
11247 show that we don't know the value. We can handle SUBREG in
11249 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11250 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11251 else if (GET_CODE (setter) == SET
11252 && GET_CODE (SET_DEST (setter)) == SUBREG
11253 && SUBREG_REG (SET_DEST (setter)) == dest
11254 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11255 && subreg_lowpart_p (SET_DEST (setter)))
11256 record_value_for_reg (dest, record_dead_insn,
11257 gen_lowpart_for_combine (GET_MODE (dest),
11258 SET_SRC (setter)));
11260 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11262 else if (GET_CODE (dest) == MEM
11263 /* Ignore pushes, they clobber nothing. */
11264 && ! push_operand (dest, GET_MODE (dest)))
11265 mem_last_set = INSN_CUID (record_dead_insn);
11268 /* Update the records of when each REG was most recently set or killed
11269 for the things done by INSN. This is the last thing done in processing
11270 INSN in the combiner loop.
11272 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11273 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11274 and also the similar information mem_last_set (which insn most recently
11275 modified memory) and last_call_cuid (which insn was the most recent
11276 subroutine call). */
11279 record_dead_and_set_regs (insn)
11285 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11287 if (REG_NOTE_KIND (link) == REG_DEAD
11288 && GET_CODE (XEXP (link, 0)) == REG)
11290 unsigned int regno = REGNO (XEXP (link, 0));
11291 unsigned int endregno
11292 = regno + (regno < FIRST_PSEUDO_REGISTER
11293 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11296 for (i = regno; i < endregno; i++)
11297 reg_last_death[i] = insn;
11299 else if (REG_NOTE_KIND (link) == REG_INC)
11300 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11303 if (GET_CODE (insn) == CALL_INSN)
11305 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11306 if (call_used_regs[i])
11308 reg_last_set_value[i] = 0;
11309 reg_last_set_mode[i] = 0;
11310 reg_last_set_nonzero_bits[i] = 0;
11311 reg_last_set_sign_bit_copies[i] = 0;
11312 reg_last_death[i] = 0;
11315 last_call_cuid = mem_last_set = INSN_CUID (insn);
11318 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11321 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11322 register present in the SUBREG, so for each such SUBREG go back and
11323 adjust nonzero and sign bit information of the registers that are
11324 known to have some zero/sign bits set.
11326 This is needed because when combine blows the SUBREGs away, the
11327 information on zero/sign bits is lost and further combines can be
11328 missed because of that. */
11331 record_promoted_value (insn, subreg)
11336 unsigned int regno = REGNO (SUBREG_REG (subreg));
11337 enum machine_mode mode = GET_MODE (subreg);
11339 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11342 for (links = LOG_LINKS (insn); links;)
11344 insn = XEXP (links, 0);
11345 set = single_set (insn);
11347 if (! set || GET_CODE (SET_DEST (set)) != REG
11348 || REGNO (SET_DEST (set)) != regno
11349 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11351 links = XEXP (links, 1);
11355 if (reg_last_set[regno] == insn)
11357 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11358 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11361 if (GET_CODE (SET_SRC (set)) == REG)
11363 regno = REGNO (SET_SRC (set));
11364 links = LOG_LINKS (insn);
11371 /* Scan X for promoted SUBREGs. For each one found,
11372 note what it implies to the registers used in it. */
11375 check_promoted_subreg (insn, x)
11379 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11380 && GET_CODE (SUBREG_REG (x)) == REG)
11381 record_promoted_value (insn, x);
11384 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11387 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11391 check_promoted_subreg (insn, XEXP (x, i));
11395 if (XVEC (x, i) != 0)
11396 for (j = 0; j < XVECLEN (x, i); j++)
11397 check_promoted_subreg (insn, XVECEXP (x, i, j));
11403 /* Utility routine for the following function. Verify that all the registers
11404 mentioned in *LOC are valid when *LOC was part of a value set when
11405 label_tick == TICK. Return 0 if some are not.
11407 If REPLACE is non-zero, replace the invalid reference with
11408 (clobber (const_int 0)) and return 1. This replacement is useful because
11409 we often can get useful information about the form of a value (e.g., if
11410 it was produced by a shift that always produces -1 or 0) even though
11411 we don't know exactly what registers it was produced from. */
11414 get_last_value_validate (loc, insn, tick, replace)
11421 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11422 int len = GET_RTX_LENGTH (GET_CODE (x));
11425 if (GET_CODE (x) == REG)
11427 unsigned int regno = REGNO (x);
11428 unsigned int endregno
11429 = regno + (regno < FIRST_PSEUDO_REGISTER
11430 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11433 for (j = regno; j < endregno; j++)
11434 if (reg_last_set_invalid[j]
11435 /* If this is a pseudo-register that was only set once and not
11436 live at the beginning of the function, it is always valid. */
11437 || (! (regno >= FIRST_PSEUDO_REGISTER
11438 && REG_N_SETS (regno) == 1
11439 && (! REGNO_REG_SET_P
11440 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11441 && reg_last_set_label[j] > tick))
11444 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11450 /* If this is a memory reference, make sure that there were
11451 no stores after it that might have clobbered the value. We don't
11452 have alias info, so we assume any store invalidates it. */
11453 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11454 && INSN_CUID (insn) <= mem_last_set)
11457 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11461 for (i = 0; i < len; i++)
11463 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11464 /* Don't bother with these. They shouldn't occur anyway. */
11468 /* If we haven't found a reason for it to be invalid, it is valid. */
11472 /* Get the last value assigned to X, if known. Some registers
11473 in the value may be replaced with (clobber (const_int 0)) if their value
11474 is known longer known reliably. */
11480 unsigned int regno;
11483 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11484 then convert it to the desired mode. If this is a paradoxical SUBREG,
11485 we cannot predict what values the "extra" bits might have. */
11486 if (GET_CODE (x) == SUBREG
11487 && subreg_lowpart_p (x)
11488 && (GET_MODE_SIZE (GET_MODE (x))
11489 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11490 && (value = get_last_value (SUBREG_REG (x))) != 0)
11491 return gen_lowpart_for_combine (GET_MODE (x), value);
11493 if (GET_CODE (x) != REG)
11497 value = reg_last_set_value[regno];
11499 /* If we don't have a value, or if it isn't for this basic block and
11500 it's either a hard register, set more than once, or it's a live
11501 at the beginning of the function, return 0.
11503 Because if it's not live at the beginnning of the function then the reg
11504 is always set before being used (is never used without being set).
11505 And, if it's set only once, and it's always set before use, then all
11506 uses must have the same last value, even if it's not from this basic
11510 || (reg_last_set_label[regno] != label_tick
11511 && (regno < FIRST_PSEUDO_REGISTER
11512 || REG_N_SETS (regno) != 1
11513 || (REGNO_REG_SET_P
11514 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11517 /* If the value was set in a later insn than the ones we are processing,
11518 we can't use it even if the register was only set once. */
11519 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11522 /* If the value has all its registers valid, return it. */
11523 if (get_last_value_validate (&value, reg_last_set[regno],
11524 reg_last_set_label[regno], 0))
11527 /* Otherwise, make a copy and replace any invalid register with
11528 (clobber (const_int 0)). If that fails for some reason, return 0. */
11530 value = copy_rtx (value);
11531 if (get_last_value_validate (&value, reg_last_set[regno],
11532 reg_last_set_label[regno], 1))
11538 /* Return nonzero if expression X refers to a REG or to memory
11539 that is set in an instruction more recent than FROM_CUID. */
11542 use_crosses_set_p (x, from_cuid)
11546 register const char *fmt;
11548 register enum rtx_code code = GET_CODE (x);
11552 unsigned int regno = REGNO (x);
11553 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11554 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11556 #ifdef PUSH_ROUNDING
11557 /* Don't allow uses of the stack pointer to be moved,
11558 because we don't know whether the move crosses a push insn. */
11559 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11562 for (; regno < endreg; regno++)
11563 if (reg_last_set[regno]
11564 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11569 if (code == MEM && mem_last_set > from_cuid)
11572 fmt = GET_RTX_FORMAT (code);
11574 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11579 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11580 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11583 else if (fmt[i] == 'e'
11584 && use_crosses_set_p (XEXP (x, i), from_cuid))
11590 /* Define three variables used for communication between the following
11593 static unsigned int reg_dead_regno, reg_dead_endregno;
11594 static int reg_dead_flag;
11596 /* Function called via note_stores from reg_dead_at_p.
11598 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11599 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11602 reg_dead_at_p_1 (dest, x, data)
11605 void *data ATTRIBUTE_UNUSED;
11607 unsigned int regno, endregno;
11609 if (GET_CODE (dest) != REG)
11612 regno = REGNO (dest);
11613 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11614 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11616 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11617 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11620 /* Return non-zero if REG is known to be dead at INSN.
11622 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11623 referencing REG, it is dead. If we hit a SET referencing REG, it is
11624 live. Otherwise, see if it is live or dead at the start of the basic
11625 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11626 must be assumed to be always live. */
11629 reg_dead_at_p (reg, insn)
11636 /* Set variables for reg_dead_at_p_1. */
11637 reg_dead_regno = REGNO (reg);
11638 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11639 ? HARD_REGNO_NREGS (reg_dead_regno,
11645 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11646 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11648 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11649 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11653 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11654 beginning of function. */
11655 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11656 insn = prev_nonnote_insn (insn))
11658 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11660 return reg_dead_flag == 1 ? 1 : 0;
11662 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11666 /* Get the basic block number that we were in. */
11671 for (block = 0; block < n_basic_blocks; block++)
11672 if (insn == BLOCK_HEAD (block))
11675 if (block == n_basic_blocks)
11679 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11680 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11686 /* Note hard registers in X that are used. This code is similar to
11687 that in flow.c, but much simpler since we don't care about pseudos. */
11690 mark_used_regs_combine (x)
11693 RTX_CODE code = GET_CODE (x);
11694 unsigned int regno;
11706 case ADDR_DIFF_VEC:
11709 /* CC0 must die in the insn after it is set, so we don't need to take
11710 special note of it here. */
11716 /* If we are clobbering a MEM, mark any hard registers inside the
11717 address as used. */
11718 if (GET_CODE (XEXP (x, 0)) == MEM)
11719 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11724 /* A hard reg in a wide mode may really be multiple registers.
11725 If so, mark all of them just like the first. */
11726 if (regno < FIRST_PSEUDO_REGISTER)
11728 unsigned int endregno, r;
11730 /* None of this applies to the stack, frame or arg pointers */
11731 if (regno == STACK_POINTER_REGNUM
11732 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11733 || regno == HARD_FRAME_POINTER_REGNUM
11735 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11736 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11738 || regno == FRAME_POINTER_REGNUM)
11741 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11742 for (r = regno; r < endregno; r++)
11743 SET_HARD_REG_BIT (newpat_used_regs, r);
11749 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11751 register rtx testreg = SET_DEST (x);
11753 while (GET_CODE (testreg) == SUBREG
11754 || GET_CODE (testreg) == ZERO_EXTRACT
11755 || GET_CODE (testreg) == SIGN_EXTRACT
11756 || GET_CODE (testreg) == STRICT_LOW_PART)
11757 testreg = XEXP (testreg, 0);
11759 if (GET_CODE (testreg) == MEM)
11760 mark_used_regs_combine (XEXP (testreg, 0));
11762 mark_used_regs_combine (SET_SRC (x));
11770 /* Recursively scan the operands of this expression. */
11773 register const char *fmt = GET_RTX_FORMAT (code);
11775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11778 mark_used_regs_combine (XEXP (x, i));
11779 else if (fmt[i] == 'E')
11783 for (j = 0; j < XVECLEN (x, i); j++)
11784 mark_used_regs_combine (XVECEXP (x, i, j));
11790 /* Remove register number REGNO from the dead registers list of INSN.
11792 Return the note used to record the death, if there was one. */
11795 remove_death (regno, insn)
11796 unsigned int regno;
11799 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11803 REG_N_DEATHS (regno)--;
11804 remove_note (insn, note);
11810 /* For each register (hardware or pseudo) used within expression X, if its
11811 death is in an instruction with cuid between FROM_CUID (inclusive) and
11812 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11813 list headed by PNOTES.
11815 That said, don't move registers killed by maybe_kill_insn.
11817 This is done when X is being merged by combination into TO_INSN. These
11818 notes will then be distributed as needed. */
11821 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11823 rtx maybe_kill_insn;
11828 register const char *fmt;
11829 register int len, i;
11830 register enum rtx_code code = GET_CODE (x);
11834 unsigned int regno = REGNO (x);
11835 register rtx where_dead = reg_last_death[regno];
11836 register rtx before_dead, after_dead;
11838 /* Don't move the register if it gets killed in between from and to */
11839 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11840 && ! reg_referenced_p (x, maybe_kill_insn))
11843 /* WHERE_DEAD could be a USE insn made by combine, so first we
11844 make sure that we have insns with valid INSN_CUID values. */
11845 before_dead = where_dead;
11846 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11847 before_dead = PREV_INSN (before_dead);
11849 after_dead = where_dead;
11850 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11851 after_dead = NEXT_INSN (after_dead);
11853 if (before_dead && after_dead
11854 && INSN_CUID (before_dead) >= from_cuid
11855 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11856 || (where_dead != after_dead
11857 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11859 rtx note = remove_death (regno, where_dead);
11861 /* It is possible for the call above to return 0. This can occur
11862 when reg_last_death points to I2 or I1 that we combined with.
11863 In that case make a new note.
11865 We must also check for the case where X is a hard register
11866 and NOTE is a death note for a range of hard registers
11867 including X. In that case, we must put REG_DEAD notes for
11868 the remaining registers in place of NOTE. */
11870 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11871 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11872 > GET_MODE_SIZE (GET_MODE (x))))
11874 unsigned int deadregno = REGNO (XEXP (note, 0));
11875 unsigned int deadend
11876 = (deadregno + HARD_REGNO_NREGS (deadregno,
11877 GET_MODE (XEXP (note, 0))));
11878 unsigned int ourend
11879 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11882 for (i = deadregno; i < deadend; i++)
11883 if (i < regno || i >= ourend)
11884 REG_NOTES (where_dead)
11885 = gen_rtx_EXPR_LIST (REG_DEAD,
11886 gen_rtx_REG (reg_raw_mode[i], i),
11887 REG_NOTES (where_dead));
11890 /* If we didn't find any note, or if we found a REG_DEAD note that
11891 covers only part of the given reg, and we have a multi-reg hard
11892 register, then to be safe we must check for REG_DEAD notes
11893 for each register other than the first. They could have
11894 their own REG_DEAD notes lying around. */
11895 else if ((note == 0
11897 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11898 < GET_MODE_SIZE (GET_MODE (x)))))
11899 && regno < FIRST_PSEUDO_REGISTER
11900 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11902 unsigned int ourend
11903 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11904 unsigned int i, offset;
11908 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11912 for (i = regno + offset; i < ourend; i++)
11913 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11914 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11917 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11919 XEXP (note, 1) = *pnotes;
11923 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11925 REG_N_DEATHS (regno)++;
11931 else if (GET_CODE (x) == SET)
11933 rtx dest = SET_DEST (x);
11935 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11937 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11938 that accesses one word of a multi-word item, some
11939 piece of everything register in the expression is used by
11940 this insn, so remove any old death. */
11942 if (GET_CODE (dest) == ZERO_EXTRACT
11943 || GET_CODE (dest) == STRICT_LOW_PART
11944 || (GET_CODE (dest) == SUBREG
11945 && (((GET_MODE_SIZE (GET_MODE (dest))
11946 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11947 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11948 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11950 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11954 /* If this is some other SUBREG, we know it replaces the entire
11955 value, so use that as the destination. */
11956 if (GET_CODE (dest) == SUBREG)
11957 dest = SUBREG_REG (dest);
11959 /* If this is a MEM, adjust deaths of anything used in the address.
11960 For a REG (the only other possibility), the entire value is
11961 being replaced so the old value is not used in this insn. */
11963 if (GET_CODE (dest) == MEM)
11964 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11969 else if (GET_CODE (x) == CLOBBER)
11972 len = GET_RTX_LENGTH (code);
11973 fmt = GET_RTX_FORMAT (code);
11975 for (i = 0; i < len; i++)
11980 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11981 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11984 else if (fmt[i] == 'e')
11985 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11989 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11990 pattern of an insn. X must be a REG. */
11993 reg_bitfield_target_p (x, body)
11999 if (GET_CODE (body) == SET)
12001 rtx dest = SET_DEST (body);
12003 unsigned int regno, tregno, endregno, endtregno;
12005 if (GET_CODE (dest) == ZERO_EXTRACT)
12006 target = XEXP (dest, 0);
12007 else if (GET_CODE (dest) == STRICT_LOW_PART)
12008 target = SUBREG_REG (XEXP (dest, 0));
12012 if (GET_CODE (target) == SUBREG)
12013 target = SUBREG_REG (target);
12015 if (GET_CODE (target) != REG)
12018 tregno = REGNO (target), regno = REGNO (x);
12019 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12020 return target == x;
12022 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12023 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12025 return endregno > tregno && regno < endtregno;
12028 else if (GET_CODE (body) == PARALLEL)
12029 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12030 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12036 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12037 as appropriate. I3 and I2 are the insns resulting from the combination
12038 insns including FROM (I2 may be zero).
12040 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12041 not need REG_DEAD notes because they are being substituted for. This
12042 saves searching in the most common cases.
12044 Each note in the list is either ignored or placed on some insns, depending
12045 on the type of note. */
12048 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12052 rtx elim_i2, elim_i1;
12054 rtx note, next_note;
12057 for (note = notes; note; note = next_note)
12059 rtx place = 0, place2 = 0;
12061 /* If this NOTE references a pseudo register, ensure it references
12062 the latest copy of that register. */
12063 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12064 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12065 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12067 next_note = XEXP (note, 1);
12068 switch (REG_NOTE_KIND (note))
12071 case REG_EXEC_COUNT:
12072 /* Doesn't matter much where we put this, as long as it's somewhere.
12073 It is preferable to keep these notes on branches, which is most
12074 likely to be i3. */
12078 case REG_EH_REGION:
12079 case REG_EH_RETHROW:
12081 /* These notes must remain with the call. It should not be
12082 possible for both I2 and I3 to be a call. */
12083 if (GET_CODE (i3) == CALL_INSN)
12085 else if (i2 && GET_CODE (i2) == CALL_INSN)
12092 /* Any clobbers for i3 may still exist, and so we must process
12093 REG_UNUSED notes from that insn.
12095 Any clobbers from i2 or i1 can only exist if they were added by
12096 recog_for_combine. In that case, recog_for_combine created the
12097 necessary REG_UNUSED notes. Trying to keep any original
12098 REG_UNUSED notes from these insns can cause incorrect output
12099 if it is for the same register as the original i3 dest.
12100 In that case, we will notice that the register is set in i3,
12101 and then add a REG_UNUSED note for the destination of i3, which
12102 is wrong. However, it is possible to have REG_UNUSED notes from
12103 i2 or i1 for register which were both used and clobbered, so
12104 we keep notes from i2 or i1 if they will turn into REG_DEAD
12107 /* If this register is set or clobbered in I3, put the note there
12108 unless there is one already. */
12109 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12111 if (from_insn != i3)
12114 if (! (GET_CODE (XEXP (note, 0)) == REG
12115 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12116 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12119 /* Otherwise, if this register is used by I3, then this register
12120 now dies here, so we must put a REG_DEAD note here unless there
12122 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12123 && ! (GET_CODE (XEXP (note, 0)) == REG
12124 ? find_regno_note (i3, REG_DEAD,
12125 REGNO (XEXP (note, 0)))
12126 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12128 PUT_REG_NOTE_KIND (note, REG_DEAD);
12136 /* These notes say something about results of an insn. We can
12137 only support them if they used to be on I3 in which case they
12138 remain on I3. Otherwise they are ignored.
12140 If the note refers to an expression that is not a constant, we
12141 must also ignore the note since we cannot tell whether the
12142 equivalence is still true. It might be possible to do
12143 slightly better than this (we only have a problem if I2DEST
12144 or I1DEST is present in the expression), but it doesn't
12145 seem worth the trouble. */
12147 if (from_insn == i3
12148 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12153 case REG_NO_CONFLICT:
12154 /* These notes say something about how a register is used. They must
12155 be present on any use of the register in I2 or I3. */
12156 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12159 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12169 /* This can show up in several ways -- either directly in the
12170 pattern, or hidden off in the constant pool with (or without?)
12171 a REG_EQUAL note. */
12172 /* ??? Ignore the without-reg_equal-note problem for now. */
12173 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12174 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12175 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12176 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12180 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12181 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12182 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12183 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12194 /* These notes say something about the value of a register prior
12195 to the execution of an insn. It is too much trouble to see
12196 if the note is still correct in all situations. It is better
12197 to simply delete it. */
12201 /* If the insn previously containing this note still exists,
12202 put it back where it was. Otherwise move it to the previous
12203 insn. Adjust the corresponding REG_LIBCALL note. */
12204 if (GET_CODE (from_insn) != NOTE)
12208 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12209 place = prev_real_insn (from_insn);
12211 XEXP (tem, 0) = place;
12216 /* This is handled similarly to REG_RETVAL. */
12217 if (GET_CODE (from_insn) != NOTE)
12221 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12222 place = next_real_insn (from_insn);
12224 XEXP (tem, 0) = place;
12229 /* If the register is used as an input in I3, it dies there.
12230 Similarly for I2, if it is non-zero and adjacent to I3.
12232 If the register is not used as an input in either I3 or I2
12233 and it is not one of the registers we were supposed to eliminate,
12234 there are two possibilities. We might have a non-adjacent I2
12235 or we might have somehow eliminated an additional register
12236 from a computation. For example, we might have had A & B where
12237 we discover that B will always be zero. In this case we will
12238 eliminate the reference to A.
12240 In both cases, we must search to see if we can find a previous
12241 use of A and put the death note there. */
12244 && GET_CODE (from_insn) == CALL_INSN
12245 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12247 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12249 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12250 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12253 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12258 basic_block bb = BASIC_BLOCK (this_basic_block);
12260 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12262 if (! INSN_P (tem))
12264 if (tem == bb->head)
12269 /* If the register is being set at TEM, see if that is all
12270 TEM is doing. If so, delete TEM. Otherwise, make this
12271 into a REG_UNUSED note instead. */
12272 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12274 rtx set = single_set (tem);
12275 rtx inner_dest = 0;
12277 rtx cc0_setter = NULL_RTX;
12281 for (inner_dest = SET_DEST (set);
12282 (GET_CODE (inner_dest) == STRICT_LOW_PART
12283 || GET_CODE (inner_dest) == SUBREG
12284 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12285 inner_dest = XEXP (inner_dest, 0))
12288 /* Verify that it was the set, and not a clobber that
12289 modified the register.
12291 CC0 targets must be careful to maintain setter/user
12292 pairs. If we cannot delete the setter due to side
12293 effects, mark the user with an UNUSED note instead
12296 if (set != 0 && ! side_effects_p (SET_SRC (set))
12297 && rtx_equal_p (XEXP (note, 0), inner_dest)
12299 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12300 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12301 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12305 /* Move the notes and links of TEM elsewhere.
12306 This might delete other dead insns recursively.
12307 First set the pattern to something that won't use
12310 PATTERN (tem) = pc_rtx;
12312 distribute_notes (REG_NOTES (tem), tem, tem,
12313 NULL_RTX, NULL_RTX, NULL_RTX);
12314 distribute_links (LOG_LINKS (tem));
12316 PUT_CODE (tem, NOTE);
12317 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12318 NOTE_SOURCE_FILE (tem) = 0;
12321 /* Delete the setter too. */
12324 PATTERN (cc0_setter) = pc_rtx;
12326 distribute_notes (REG_NOTES (cc0_setter),
12327 cc0_setter, cc0_setter,
12328 NULL_RTX, NULL_RTX, NULL_RTX);
12329 distribute_links (LOG_LINKS (cc0_setter));
12331 PUT_CODE (cc0_setter, NOTE);
12332 NOTE_LINE_NUMBER (cc0_setter)
12333 = NOTE_INSN_DELETED;
12334 NOTE_SOURCE_FILE (cc0_setter) = 0;
12338 /* If the register is both set and used here, put the
12339 REG_DEAD note here, but place a REG_UNUSED note
12340 here too unless there already is one. */
12341 else if (reg_referenced_p (XEXP (note, 0),
12346 if (! find_regno_note (tem, REG_UNUSED,
12347 REGNO (XEXP (note, 0))))
12349 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12354 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12356 /* If there isn't already a REG_UNUSED note, put one
12358 if (! find_regno_note (tem, REG_UNUSED,
12359 REGNO (XEXP (note, 0))))
12364 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12365 || (GET_CODE (tem) == CALL_INSN
12366 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12370 /* If we are doing a 3->2 combination, and we have a
12371 register which formerly died in i3 and was not used
12372 by i2, which now no longer dies in i3 and is used in
12373 i2 but does not die in i2, and place is between i2
12374 and i3, then we may need to move a link from place to
12376 if (i2 && INSN_UID (place) <= max_uid_cuid
12377 && INSN_CUID (place) > INSN_CUID (i2)
12379 && INSN_CUID (from_insn) > INSN_CUID (i2)
12380 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12382 rtx links = LOG_LINKS (place);
12383 LOG_LINKS (place) = 0;
12384 distribute_links (links);
12389 if (tem == bb->head)
12393 /* We haven't found an insn for the death note and it
12394 is still a REG_DEAD note, but we have hit the beginning
12395 of the block. If the existing life info says the reg
12396 was dead, there's nothing left to do. Otherwise, we'll
12397 need to do a global life update after combine. */
12398 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12399 && REGNO_REG_SET_P (bb->global_live_at_start,
12400 REGNO (XEXP (note, 0))))
12402 SET_BIT (refresh_blocks, this_basic_block);
12407 /* If the register is set or already dead at PLACE, we needn't do
12408 anything with this note if it is still a REG_DEAD note.
12409 We can here if it is set at all, not if is it totally replace,
12410 which is what `dead_or_set_p' checks, so also check for it being
12413 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12415 unsigned int regno = REGNO (XEXP (note, 0));
12417 if (dead_or_set_p (place, XEXP (note, 0))
12418 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12420 /* Unless the register previously died in PLACE, clear
12421 reg_last_death. [I no longer understand why this is
12423 if (reg_last_death[regno] != place)
12424 reg_last_death[regno] = 0;
12428 reg_last_death[regno] = place;
12430 /* If this is a death note for a hard reg that is occupying
12431 multiple registers, ensure that we are still using all
12432 parts of the object. If we find a piece of the object
12433 that is unused, we must add a USE for that piece before
12434 PLACE and put the appropriate REG_DEAD note on it.
12436 An alternative would be to put a REG_UNUSED for the pieces
12437 on the insn that set the register, but that can't be done if
12438 it is not in the same block. It is simpler, though less
12439 efficient, to add the USE insns. */
12441 if (place && regno < FIRST_PSEUDO_REGISTER
12442 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12444 unsigned int endregno
12445 = regno + HARD_REGNO_NREGS (regno,
12446 GET_MODE (XEXP (note, 0)));
12450 for (i = regno; i < endregno; i++)
12451 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12452 && ! find_regno_fusage (place, USE, i))
12454 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12457 /* See if we already placed a USE note for this
12458 register in front of PLACE. */
12460 GET_CODE (PREV_INSN (p)) == INSN
12461 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12463 if (rtx_equal_p (piece,
12464 XEXP (PATTERN (PREV_INSN (p)), 0)))
12473 = emit_insn_before (gen_rtx_USE (VOIDmode,
12476 REG_NOTES (use_insn)
12477 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12478 REG_NOTES (use_insn));
12484 /* Check for the case where the register dying partially
12485 overlaps the register set by this insn. */
12487 for (i = regno; i < endregno; i++)
12488 if (dead_or_set_regno_p (place, i))
12496 /* Put only REG_DEAD notes for pieces that are
12497 still used and that are not already dead or set. */
12499 for (i = regno; i < endregno; i++)
12501 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12503 if ((reg_referenced_p (piece, PATTERN (place))
12504 || (GET_CODE (place) == CALL_INSN
12505 && find_reg_fusage (place, USE, piece)))
12506 && ! dead_or_set_p (place, piece)
12507 && ! reg_bitfield_target_p (piece,
12510 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12511 REG_NOTES (place));
12521 /* Any other notes should not be present at this point in the
12528 XEXP (note, 1) = REG_NOTES (place);
12529 REG_NOTES (place) = note;
12531 else if ((REG_NOTE_KIND (note) == REG_DEAD
12532 || REG_NOTE_KIND (note) == REG_UNUSED)
12533 && GET_CODE (XEXP (note, 0)) == REG)
12534 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12538 if ((REG_NOTE_KIND (note) == REG_DEAD
12539 || REG_NOTE_KIND (note) == REG_UNUSED)
12540 && GET_CODE (XEXP (note, 0)) == REG)
12541 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12543 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12544 REG_NOTE_KIND (note),
12546 REG_NOTES (place2));
12551 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12552 I3, I2, and I1 to new locations. This is also called in one case to
12553 add a link pointing at I3 when I3's destination is changed. */
12556 distribute_links (links)
12559 rtx link, next_link;
12561 for (link = links; link; link = next_link)
12567 next_link = XEXP (link, 1);
12569 /* If the insn that this link points to is a NOTE or isn't a single
12570 set, ignore it. In the latter case, it isn't clear what we
12571 can do other than ignore the link, since we can't tell which
12572 register it was for. Such links wouldn't be used by combine
12575 It is not possible for the destination of the target of the link to
12576 have been changed by combine. The only potential of this is if we
12577 replace I3, I2, and I1 by I3 and I2. But in that case the
12578 destination of I2 also remains unchanged. */
12580 if (GET_CODE (XEXP (link, 0)) == NOTE
12581 || (set = single_set (XEXP (link, 0))) == 0)
12584 reg = SET_DEST (set);
12585 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12586 || GET_CODE (reg) == SIGN_EXTRACT
12587 || GET_CODE (reg) == STRICT_LOW_PART)
12588 reg = XEXP (reg, 0);
12590 /* A LOG_LINK is defined as being placed on the first insn that uses
12591 a register and points to the insn that sets the register. Start
12592 searching at the next insn after the target of the link and stop
12593 when we reach a set of the register or the end of the basic block.
12595 Note that this correctly handles the link that used to point from
12596 I3 to I2. Also note that not much searching is typically done here
12597 since most links don't point very far away. */
12599 for (insn = NEXT_INSN (XEXP (link, 0));
12600 (insn && (this_basic_block == n_basic_blocks - 1
12601 || BLOCK_HEAD (this_basic_block + 1) != insn));
12602 insn = NEXT_INSN (insn))
12603 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12605 if (reg_referenced_p (reg, PATTERN (insn)))
12609 else if (GET_CODE (insn) == CALL_INSN
12610 && find_reg_fusage (insn, USE, reg))
12616 /* If we found a place to put the link, place it there unless there
12617 is already a link to the same insn as LINK at that point. */
12623 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12624 if (XEXP (link2, 0) == XEXP (link, 0))
12629 XEXP (link, 1) = LOG_LINKS (place);
12630 LOG_LINKS (place) = link;
12632 /* Set added_links_insn to the earliest insn we added a
12634 if (added_links_insn == 0
12635 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12636 added_links_insn = place;
12642 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12648 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12649 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12650 insn = NEXT_INSN (insn);
12652 if (INSN_UID (insn) > max_uid_cuid)
12655 return INSN_CUID (insn);
12659 dump_combine_stats (file)
12664 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12665 combine_attempts, combine_merges, combine_extras, combine_successes);
12669 dump_combine_total_stats (file)
12674 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12675 total_attempts, total_merges, total_extras, total_successes);