1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* This is the value of undobuf.num_undo when we started processing this
202 substitution. This will prevent gen_rtx_combine from re-used a piece
203 from the previous expression. Doing so can produce circular rtl
206 static int previous_num_undos;
208 /* Basic block number of the block in which we are performing combines. */
209 static int this_basic_block;
211 /* The next group of arrays allows the recording of the last value assigned
212 to (hard or pseudo) register n. We use this information to see if a
213 operation being processed is redundant given a prior operation performed
214 on the register. For example, an `and' with a constant is redundant if
215 all the zero bits are already known to be turned off.
217 We use an approach similar to that used by cse, but change it in the
220 (1) We do not want to reinitialize at each label.
221 (2) It is useful, but not critical, to know the actual value assigned
222 to a register. Often just its form is helpful.
224 Therefore, we maintain the following arrays:
226 reg_last_set_value the last value assigned
227 reg_last_set_label records the value of label_tick when the
228 register was assigned
229 reg_last_set_table_tick records the value of label_tick when a
230 value using the register is assigned
231 reg_last_set_invalid set to non-zero when it is not valid
232 to use the value of this register in some
235 To understand the usage of these tables, it is important to understand
236 the distinction between the value in reg_last_set_value being valid
237 and the register being validly contained in some other expression in the
240 Entry I in reg_last_set_value is valid if it is non-zero, and either
241 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
243 Register I may validly appear in any expression returned for the value
244 of another register if reg_n_sets[i] is 1. It may also appear in the
245 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
246 reg_last_set_invalid[j] is zero.
248 If an expression is found in the table containing a register which may
249 not validly appear in an expression, the register is replaced by
250 something that won't match, (clobber (const_int 0)).
252 reg_last_set_invalid[i] is set non-zero when register I is being assigned
253 to and reg_last_set_table_tick[i] == label_tick. */
255 /* Record last value assigned to (hard or pseudo) register n. */
257 static rtx *reg_last_set_value;
259 /* Record the value of label_tick when the value for register n is placed in
260 reg_last_set_value[n]. */
262 static int *reg_last_set_label;
264 /* Record the value of label_tick when an expression involving register n
265 is placed in reg_last_set_value. */
267 static int *reg_last_set_table_tick;
269 /* Set non-zero if references to register n in expressions should not be
272 static char *reg_last_set_invalid;
274 /* Incremented for each label. */
276 static int label_tick;
278 /* Some registers that are set more than once and used in more than one
279 basic block are nevertheless always set in similar ways. For example,
280 a QImode register may be loaded from memory in two places on a machine
281 where byte loads zero extend.
283 We record in the following array what we know about the nonzero
284 bits of a register, specifically which bits are known to be zero.
286 If an entry is zero, it means that we don't know anything special. */
288 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
290 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
291 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
293 static enum machine_mode nonzero_bits_mode;
295 /* Nonzero if we know that a register has some leading bits that are always
296 equal to the sign bit. */
298 static char *reg_sign_bit_copies;
300 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
301 It is zero while computing them and after combine has completed. This
302 former test prevents propagating values based on previously set values,
303 which can be incorrect if a variable is modified in a loop. */
305 static int nonzero_sign_valid;
307 /* These arrays are maintained in parallel with reg_last_set_value
308 and are used to store the mode in which the register was last set,
309 the bits that were known to be zero when it was last set, and the
310 number of sign bits copies it was known to have when it was last set. */
312 static enum machine_mode *reg_last_set_mode;
313 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
314 static char *reg_last_set_sign_bit_copies;
316 /* Record one modification to rtl structure
317 to be undone by storing old_contents into *where.
318 is_int is 1 if the contents are an int. */
323 union {rtx r; int i;} old_contents;
324 union {rtx *r; int *i;} where;
327 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
328 num_undo says how many are currently recorded.
330 storage is nonzero if we must undo the allocation of new storage.
331 The value of storage is what to pass to obfree.
333 other_insn is nonzero if we have modified some other insn in the process
334 of working on subst_insn. It must be verified too. */
342 struct undo undo[MAX_UNDO];
346 static struct undobuf undobuf;
348 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
349 insn. The substitution can be undone by undo_all. If INTO is already
350 set to NEWVAL, do not record this change. Because computing NEWVAL might
351 also call SUBST, we have to compute it before we put anything into
354 #define SUBST(INTO, NEWVAL) \
355 do { rtx _new = (NEWVAL); \
356 if (undobuf.num_undo < MAX_UNDO) \
358 undobuf.undo[undobuf.num_undo].is_int = 0; \
359 undobuf.undo[undobuf.num_undo].where.r = &INTO; \
360 undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \
362 if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \
363 undobuf.num_undo++; \
367 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
369 Note that substitution for the value of a CONST_INT is not safe. */
371 #define SUBST_INT(INTO, NEWVAL) \
372 do { if (undobuf.num_undo < MAX_UNDO) \
374 undobuf.undo[undobuf.num_undo].is_int = 1; \
375 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
376 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
378 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
379 undobuf.num_undo++; \
383 /* Number of times the pseudo being substituted for
384 was found and replaced. */
386 static int n_occurrences;
388 static void init_reg_last_arrays PROTO(());
389 static void setup_incoming_promotions PROTO(());
390 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
391 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
392 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
393 static rtx try_combine PROTO((rtx, rtx, rtx));
394 static void undo_all PROTO((void));
395 static rtx *find_split_point PROTO((rtx *, rtx));
396 static rtx subst PROTO((rtx, rtx, rtx, int, int));
397 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
398 static rtx simplify_if_then_else PROTO((rtx));
399 static rtx simplify_set PROTO((rtx));
400 static rtx simplify_logical PROTO((rtx, int));
401 static rtx expand_compound_operation PROTO((rtx));
402 static rtx expand_field_assignment PROTO((rtx));
403 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
405 static rtx extract_left_shift PROTO((rtx, int));
406 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
407 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
408 static rtx force_to_mode PROTO((rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, rtx, int));
410 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
411 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
412 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
413 static rtx make_field_assignment PROTO((rtx));
414 static rtx apply_distributive_law PROTO((rtx));
415 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT));
417 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
418 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
419 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
420 enum rtx_code, HOST_WIDE_INT,
421 enum machine_mode, int *));
422 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
424 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
425 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
426 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
428 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
430 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
431 enum machine_mode, rtx));
432 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
433 static int reversible_comparison_p PROTO((rtx));
434 static void update_table_tick PROTO((rtx));
435 static void record_value_for_reg PROTO((rtx, rtx, rtx));
436 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
437 static void record_dead_and_set_regs PROTO((rtx));
438 static int get_last_value_validate PROTO((rtx *, int, int));
439 static rtx get_last_value PROTO((rtx));
440 static int use_crosses_set_p PROTO((rtx, int));
441 static void reg_dead_at_p_1 PROTO((rtx, rtx));
442 static int reg_dead_at_p PROTO((rtx, rtx));
443 static void move_deaths PROTO((rtx, int, rtx, rtx *));
444 static int reg_bitfield_target_p PROTO((rtx, rtx));
445 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
446 static void distribute_links PROTO((rtx));
447 static void mark_used_regs_combine PROTO((rtx));
448 static int insn_cuid PROTO((rtx));
450 /* Main entry point for combiner. F is the first insn of the function.
451 NREGS is the first unused pseudo-reg number. */
454 combine_instructions (f, nregs)
458 register rtx insn, next, prev;
460 register rtx links, nextlinks;
462 combine_attempts = 0;
465 combine_successes = 0;
466 undobuf.num_undo = previous_num_undos = 0;
468 combine_max_regno = nregs;
471 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
472 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
474 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
475 bzero (reg_sign_bit_copies, nregs * sizeof (char));
477 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
478 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
479 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
480 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
481 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
482 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
484 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
485 reg_last_set_nonzero_bits
486 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
487 reg_last_set_sign_bit_copies
488 = (char *) alloca (nregs * sizeof (char));
490 init_reg_last_arrays ();
492 init_recog_no_volatile ();
494 /* Compute maximum uid value so uid_cuid can be allocated. */
496 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
497 if (INSN_UID (insn) > i)
500 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
503 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
505 /* Don't use reg_nonzero_bits when computing it. This can cause problems
506 when, for example, we have j <<= 1 in a loop. */
508 nonzero_sign_valid = 0;
510 /* Compute the mapping from uids to cuids.
511 Cuids are numbers assigned to insns, like uids,
512 except that cuids increase monotonically through the code.
514 Scan all SETs and see if we can deduce anything about what
515 bits are known to be zero for some registers and how many copies
516 of the sign bit are known to exist for those registers.
518 Also set any known values so that we can use it while searching
519 for what bits are known to be set. */
523 /* We need to initialize it here, because record_dead_and_set_regs may call
525 subst_prev_insn = NULL_RTX;
527 setup_incoming_promotions ();
529 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
531 uid_cuid[INSN_UID (insn)] = ++i;
535 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
537 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
538 record_dead_and_set_regs (insn);
541 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
542 if (REG_NOTE_KIND (links) == REG_INC)
543 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
547 if (GET_CODE (insn) == CODE_LABEL)
551 nonzero_sign_valid = 1;
553 /* Now scan all the insns in forward order. */
555 this_basic_block = -1;
559 init_reg_last_arrays ();
560 setup_incoming_promotions ();
562 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
566 /* If INSN starts a new basic block, update our basic block number. */
567 if (this_basic_block + 1 < n_basic_blocks
568 && basic_block_head[this_basic_block + 1] == insn)
571 if (GET_CODE (insn) == CODE_LABEL)
574 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
576 /* Try this insn with each insn it links back to. */
578 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
579 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
582 /* Try each sequence of three linked insns ending with this one. */
584 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
585 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
586 nextlinks = XEXP (nextlinks, 1))
587 if ((next = try_combine (insn, XEXP (links, 0),
588 XEXP (nextlinks, 0))) != 0)
592 /* Try to combine a jump insn that uses CC0
593 with a preceding insn that sets CC0, and maybe with its
594 logical predecessor as well.
595 This is how we make decrement-and-branch insns.
596 We need this special code because data flow connections
597 via CC0 do not get entered in LOG_LINKS. */
599 if (GET_CODE (insn) == JUMP_INSN
600 && (prev = prev_nonnote_insn (insn)) != 0
601 && GET_CODE (prev) == INSN
602 && sets_cc0_p (PATTERN (prev)))
604 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
607 for (nextlinks = LOG_LINKS (prev); nextlinks;
608 nextlinks = XEXP (nextlinks, 1))
609 if ((next = try_combine (insn, prev,
610 XEXP (nextlinks, 0))) != 0)
614 /* Do the same for an insn that explicitly references CC0. */
615 if (GET_CODE (insn) == INSN
616 && (prev = prev_nonnote_insn (insn)) != 0
617 && GET_CODE (prev) == INSN
618 && sets_cc0_p (PATTERN (prev))
619 && GET_CODE (PATTERN (insn)) == SET
620 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
622 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
625 for (nextlinks = LOG_LINKS (prev); nextlinks;
626 nextlinks = XEXP (nextlinks, 1))
627 if ((next = try_combine (insn, prev,
628 XEXP (nextlinks, 0))) != 0)
632 /* Finally, see if any of the insns that this insn links to
633 explicitly references CC0. If so, try this insn, that insn,
634 and its predecessor if it sets CC0. */
635 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
636 if (GET_CODE (XEXP (links, 0)) == INSN
637 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
638 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
639 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
640 && GET_CODE (prev) == INSN
641 && sets_cc0_p (PATTERN (prev))
642 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
646 /* Try combining an insn with two different insns whose results it
648 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 for (nextlinks = XEXP (links, 1); nextlinks;
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, XEXP (links, 0),
652 XEXP (nextlinks, 0))) != 0)
655 if (GET_CODE (insn) != NOTE)
656 record_dead_and_set_regs (insn);
663 total_attempts += combine_attempts;
664 total_merges += combine_merges;
665 total_extras += combine_extras;
666 total_successes += combine_successes;
668 nonzero_sign_valid = 0;
671 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
674 init_reg_last_arrays ()
676 int nregs = combine_max_regno;
678 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
679 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
680 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
681 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
682 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
683 bzero (reg_last_set_invalid, nregs * sizeof (char));
684 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
685 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
686 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
689 /* Set up any promoted values for incoming argument registers. */
692 setup_incoming_promotions ()
694 #ifdef PROMOTE_FUNCTION_ARGS
697 enum machine_mode mode;
699 rtx first = get_insns ();
701 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
702 if (FUNCTION_ARG_REGNO_P (regno)
703 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
704 record_value_for_reg (reg, first,
705 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
707 gen_rtx (CLOBBER, mode, const0_rtx)));
711 /* Called via note_stores. If X is a pseudo that is narrower than
712 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
714 If we are setting only a portion of X and we can't figure out what
715 portion, assume all bits will be used since we don't know what will
718 Similarly, set how many bits of X are known to be copies of the sign bit
719 at all locations in the function. This is the smallest number implied
723 set_nonzero_bits_and_sign_copies (x, set)
729 if (GET_CODE (x) == REG
730 && REGNO (x) >= FIRST_PSEUDO_REGISTER
731 /* If this register is undefined at the start of the file, we can't
732 say what its contents were. */
733 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
734 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
735 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
737 if (set == 0 || GET_CODE (set) == CLOBBER)
739 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
740 reg_sign_bit_copies[REGNO (x)] = 0;
744 /* If this is a complex assignment, see if we can convert it into a
745 simple assignment. */
746 set = expand_field_assignment (set);
748 /* If this is a simple assignment, or we have a paradoxical SUBREG,
749 set what we know about X. */
751 if (SET_DEST (set) == x
752 || (GET_CODE (SET_DEST (set)) == SUBREG
753 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
754 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
755 && SUBREG_REG (SET_DEST (set)) == x))
757 rtx src = SET_SRC (set);
759 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
760 /* If X is narrower than a word and SRC is a non-negative
761 constant that would appear negative in the mode of X,
762 sign-extend it for use in reg_nonzero_bits because some
763 machines (maybe most) will actually do the sign-extension
764 and this is the conservative approach.
766 ??? For 2.5, try to tighten up the MD files in this regard
767 instead of this kludge. */
769 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
770 && GET_CODE (src) == CONST_INT
772 && 0 != (INTVAL (src)
774 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
775 src = GEN_INT (INTVAL (src)
776 | ((HOST_WIDE_INT) (-1)
777 << GET_MODE_BITSIZE (GET_MODE (x))));
780 reg_nonzero_bits[REGNO (x)]
781 |= nonzero_bits (src, nonzero_bits_mode);
782 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
783 if (reg_sign_bit_copies[REGNO (x)] == 0
784 || reg_sign_bit_copies[REGNO (x)] > num)
785 reg_sign_bit_copies[REGNO (x)] = num;
789 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
790 reg_sign_bit_copies[REGNO (x)] = 0;
795 /* See if INSN can be combined into I3. PRED and SUCC are optionally
796 insns that were previously combined into I3 or that will be combined
797 into the merger of INSN and I3.
799 Return 0 if the combination is not allowed for any reason.
801 If the combination is allowed, *PDEST will be set to the single
802 destination of INSN and *PSRC to the single source, and this function
806 can_combine_p (insn, i3, pred, succ, pdest, psrc)
813 rtx set = 0, src, dest;
815 int all_adjacent = (succ ? (next_active_insn (insn) == succ
816 && next_active_insn (succ) == i3)
817 : next_active_insn (insn) == i3);
819 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
820 or a PARALLEL consisting of such a SET and CLOBBERs.
822 If INSN has CLOBBER parallel parts, ignore them for our processing.
823 By definition, these happen during the execution of the insn. When it
824 is merged with another insn, all bets are off. If they are, in fact,
825 needed and aren't also supplied in I3, they may be added by
826 recog_for_combine. Otherwise, it won't match.
828 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
831 Get the source and destination of INSN. If more than one, can't
834 if (GET_CODE (PATTERN (insn)) == SET)
835 set = PATTERN (insn);
836 else if (GET_CODE (PATTERN (insn)) == PARALLEL
837 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
839 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
841 rtx elt = XVECEXP (PATTERN (insn), 0, i);
843 switch (GET_CODE (elt))
845 /* We can ignore CLOBBERs. */
850 /* Ignore SETs whose result isn't used but not those that
851 have side-effects. */
852 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
853 && ! side_effects_p (elt))
856 /* If we have already found a SET, this is a second one and
857 so we cannot combine with this insn. */
865 /* Anything else means we can't combine. */
871 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
872 so don't do anything with it. */
873 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
882 set = expand_field_assignment (set);
883 src = SET_SRC (set), dest = SET_DEST (set);
885 /* Don't eliminate a store in the stack pointer. */
886 if (dest == stack_pointer_rtx
887 /* If we couldn't eliminate a field assignment, we can't combine. */
888 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
889 /* Don't combine with an insn that sets a register to itself if it has
890 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
891 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
892 /* Can't merge a function call. */
893 || GET_CODE (src) == CALL
894 /* Don't eliminate a function call argument. */
895 || (GET_CODE (i3) == CALL_INSN
896 && (find_reg_fusage (i3, USE, dest)
897 || (GET_CODE (dest) == REG
898 && REGNO (dest) < FIRST_PSEUDO_REGISTER
899 && global_regs[REGNO (dest)])))
900 /* Don't substitute into an incremented register. */
901 || FIND_REG_INC_NOTE (i3, dest)
902 || (succ && FIND_REG_INC_NOTE (succ, dest))
903 /* Don't combine the end of a libcall into anything. */
904 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
905 /* Make sure that DEST is not used after SUCC but before I3. */
906 || (succ && ! all_adjacent
907 && reg_used_between_p (dest, succ, i3))
908 /* Make sure that the value that is to be substituted for the register
909 does not use any registers whose values alter in between. However,
910 If the insns are adjacent, a use can't cross a set even though we
911 think it might (this can happen for a sequence of insns each setting
912 the same destination; reg_last_set of that register might point to
913 a NOTE). If INSN has a REG_EQUIV note, the register is always
914 equivalent to the memory so the substitution is valid even if there
915 are intervening stores. Also, don't move a volatile asm or
916 UNSPEC_VOLATILE across any other insns. */
918 && (((GET_CODE (src) != MEM
919 || ! find_reg_note (insn, REG_EQUIV, src))
920 && use_crosses_set_p (src, INSN_CUID (insn)))
921 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
922 || GET_CODE (src) == UNSPEC_VOLATILE))
923 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
924 better register allocation by not doing the combine. */
925 || find_reg_note (i3, REG_NO_CONFLICT, dest)
926 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
927 /* Don't combine across a CALL_INSN, because that would possibly
928 change whether the life span of some REGs crosses calls or not,
929 and it is a pain to update that information.
930 Exception: if source is a constant, moving it later can't hurt.
931 Accept that special case, because it helps -fforce-addr a lot. */
932 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
935 /* DEST must either be a REG or CC0. */
936 if (GET_CODE (dest) == REG)
938 /* If register alignment is being enforced for multi-word items in all
939 cases except for parameters, it is possible to have a register copy
940 insn referencing a hard register that is not allowed to contain the
941 mode being copied and which would not be valid as an operand of most
942 insns. Eliminate this problem by not combining with such an insn.
944 Also, on some machines we don't want to extend the life of a hard
947 if (GET_CODE (src) == REG
948 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
949 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
950 /* Don't extend the life of a hard register unless it is
951 user variable (if we have few registers) or it can't
952 fit into the desired register (meaning something special
954 || (REGNO (src) < FIRST_PSEUDO_REGISTER
955 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
956 #ifdef SMALL_REGISTER_CLASSES
957 || ! REG_USERVAR_P (src)
962 else if (GET_CODE (dest) != CC0)
965 /* Don't substitute for a register intended as a clobberable operand.
966 Similarly, don't substitute an expression containing a register that
967 will be clobbered in I3. */
968 if (GET_CODE (PATTERN (i3)) == PARALLEL)
969 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
970 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
971 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
973 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
976 /* If INSN contains anything volatile, or is an `asm' (whether volatile
977 or not), reject, unless nothing volatile comes between it and I3,
978 with the exception of SUCC. */
980 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
981 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
982 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
983 && p != succ && volatile_refs_p (PATTERN (p)))
986 /* If there are any volatile insns between INSN and I3, reject, because
987 they might affect machine state. */
989 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
990 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
991 && p != succ && volatile_insn_p (PATTERN (p)))
994 /* If INSN or I2 contains an autoincrement or autodecrement,
995 make sure that register is not used between there and I3,
996 and not already used in I3 either.
997 Also insist that I3 not be a jump; if it were one
998 and the incremented register were spilled, we would lose. */
1001 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1002 if (REG_NOTE_KIND (link) == REG_INC
1003 && (GET_CODE (i3) == JUMP_INSN
1004 || reg_used_between_p (XEXP (link, 0), insn, i3)
1005 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1010 /* Don't combine an insn that follows a CC0-setting insn.
1011 An insn that uses CC0 must not be separated from the one that sets it.
1012 We do, however, allow I2 to follow a CC0-setting insn if that insn
1013 is passed as I1; in that case it will be deleted also.
1014 We also allow combining in this case if all the insns are adjacent
1015 because that would leave the two CC0 insns adjacent as well.
1016 It would be more logical to test whether CC0 occurs inside I1 or I2,
1017 but that would be much slower, and this ought to be equivalent. */
1019 p = prev_nonnote_insn (insn);
1020 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1025 /* If we get here, we have passed all the tests and the combination is
1034 /* LOC is the location within I3 that contains its pattern or the component
1035 of a PARALLEL of the pattern. We validate that it is valid for combining.
1037 One problem is if I3 modifies its output, as opposed to replacing it
1038 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1039 so would produce an insn that is not equivalent to the original insns.
1043 (set (reg:DI 101) (reg:DI 100))
1044 (set (subreg:SI (reg:DI 101) 0) <foo>)
1046 This is NOT equivalent to:
1048 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1049 (set (reg:DI 101) (reg:DI 100))])
1051 Not only does this modify 100 (in which case it might still be valid
1052 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1054 We can also run into a problem if I2 sets a register that I1
1055 uses and I1 gets directly substituted into I3 (not via I2). In that
1056 case, we would be getting the wrong value of I2DEST into I3, so we
1057 must reject the combination. This case occurs when I2 and I1 both
1058 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1059 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1060 of a SET must prevent combination from occurring.
1062 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1063 if the destination of a SET is a hard register that isn't a user
1066 Before doing the above check, we first try to expand a field assignment
1067 into a set of logical operations.
1069 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1070 we place a register that is both set and used within I3. If more than one
1071 such register is detected, we fail.
1073 Return 1 if the combination is valid, zero otherwise. */
1076 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1082 rtx *pi3dest_killed;
1086 if (GET_CODE (x) == SET)
1088 rtx set = expand_field_assignment (x);
1089 rtx dest = SET_DEST (set);
1090 rtx src = SET_SRC (set);
1091 rtx inner_dest = dest, inner_src = src;
1095 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1096 || GET_CODE (inner_dest) == SUBREG
1097 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1098 inner_dest = XEXP (inner_dest, 0);
1100 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1103 while (GET_CODE (inner_src) == STRICT_LOW_PART
1104 || GET_CODE (inner_src) == SUBREG
1105 || GET_CODE (inner_src) == ZERO_EXTRACT)
1106 inner_src = XEXP (inner_src, 0);
1108 /* If it is better that two different modes keep two different pseudos,
1109 avoid combining them. This avoids producing the following pattern
1111 (set (subreg:SI (reg/v:QI 21) 0)
1112 (lshiftrt:SI (reg/v:SI 20)
1114 If that were made, reload could not handle the pair of
1115 reg 20/21, since it would try to get any GENERAL_REGS
1116 but some of them don't handle QImode. */
1118 if (rtx_equal_p (inner_src, i2dest)
1119 && GET_CODE (inner_dest) == REG
1120 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1124 /* Check for the case where I3 modifies its output, as
1126 if ((inner_dest != dest
1127 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1128 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1129 /* This is the same test done in can_combine_p except that we
1130 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1132 || (GET_CODE (inner_dest) == REG
1133 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1134 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1135 GET_MODE (inner_dest))
1136 #ifdef SMALL_REGISTER_CLASSES
1137 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest))
1140 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1143 /* If DEST is used in I3, it is being killed in this insn,
1144 so record that for later.
1145 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1146 STACK_POINTER_REGNUM, since these are always considered to be
1147 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1148 if (pi3dest_killed && GET_CODE (dest) == REG
1149 && reg_referenced_p (dest, PATTERN (i3))
1150 && REGNO (dest) != FRAME_POINTER_REGNUM
1151 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1152 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1154 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1155 && (REGNO (dest) != ARG_POINTER_REGNUM
1156 || ! fixed_regs [REGNO (dest)])
1158 && REGNO (dest) != STACK_POINTER_REGNUM)
1160 if (*pi3dest_killed)
1163 *pi3dest_killed = dest;
1167 else if (GET_CODE (x) == PARALLEL)
1171 for (i = 0; i < XVECLEN (x, 0); i++)
1172 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1173 i1_not_in_src, pi3dest_killed))
1180 /* Try to combine the insns I1 and I2 into I3.
1181 Here I1 and I2 appear earlier than I3.
1182 I1 can be zero; then we combine just I2 into I3.
1184 It we are combining three insns and the resulting insn is not recognized,
1185 try splitting it into two insns. If that happens, I2 and I3 are retained
1186 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1189 Return 0 if the combination does not work. Then nothing is changed.
1190 If we did the combination, return the insn at which combine should
1194 try_combine (i3, i2, i1)
1195 register rtx i3, i2, i1;
1197 /* New patterns for I3 and I3, respectively. */
1198 rtx newpat, newi2pat = 0;
1199 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1200 int added_sets_1, added_sets_2;
1201 /* Total number of SETs to put into I3. */
1203 /* Nonzero is I2's body now appears in I3. */
1205 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1206 int insn_code_number, i2_code_number, other_code_number;
1207 /* Contains I3 if the destination of I3 is used in its source, which means
1208 that the old life of I3 is being killed. If that usage is placed into
1209 I2 and not in I3, a REG_DEAD note must be made. */
1210 rtx i3dest_killed = 0;
1211 /* SET_DEST and SET_SRC of I2 and I1. */
1212 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1213 /* PATTERN (I2), or a copy of it in certain cases. */
1215 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1216 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1217 int i1_feeds_i3 = 0;
1218 /* Notes that must be added to REG_NOTES in I3 and I2. */
1219 rtx new_i3_notes, new_i2_notes;
1220 /* Notes that we substituted I3 into I2 instead of the normal case. */
1221 int i3_subst_into_i2 = 0;
1222 /* Notes that I1, I2 or I3 is a MULT operation. */
1224 /* Number of clobbers of SCRATCH we had to add. */
1225 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1232 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1233 This can occur when flow deletes an insn that it has merged into an
1234 auto-increment address. We also can't do anything if I3 has a
1235 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1238 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1239 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1240 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1241 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1246 undobuf.num_undo = previous_num_undos = 0;
1247 undobuf.other_insn = 0;
1249 /* Save the current high-water-mark so we can free storage if we didn't
1250 accept this combination. */
1251 undobuf.storage = (char *) oballoc (0);
1253 /* Reset the hard register usage information. */
1254 CLEAR_HARD_REG_SET (newpat_used_regs);
1256 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1257 code below, set I1 to be the earlier of the two insns. */
1258 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1259 temp = i1, i1 = i2, i2 = temp;
1261 added_links_insn = 0;
1263 /* First check for one important special-case that the code below will
1264 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1265 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1266 we may be able to replace that destination with the destination of I3.
1267 This occurs in the common code where we compute both a quotient and
1268 remainder into a structure, in which case we want to do the computation
1269 directly into the structure to avoid register-register copies.
1271 We make very conservative checks below and only try to handle the
1272 most common cases of this. For example, we only handle the case
1273 where I2 and I3 are adjacent to avoid making difficult register
1276 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1277 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1278 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1279 #ifdef SMALL_REGISTER_CLASSES
1280 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1281 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1282 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1284 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1285 && GET_CODE (PATTERN (i2)) == PARALLEL
1286 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1287 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1288 below would need to check what is inside (and reg_overlap_mentioned_p
1289 doesn't support those codes anyway). Don't allow those destinations;
1290 the resulting insn isn't likely to be recognized anyway. */
1291 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1292 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1293 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1294 SET_DEST (PATTERN (i3)))
1295 && next_real_insn (i2) == i3)
1297 rtx p2 = PATTERN (i2);
1299 /* Make sure that the destination of I3,
1300 which we are going to substitute into one output of I2,
1301 is not used within another output of I2. We must avoid making this:
1302 (parallel [(set (mem (reg 69)) ...)
1303 (set (reg 69) ...)])
1304 which is not well-defined as to order of actions.
1305 (Besides, reload can't handle output reloads for this.)
1307 The problem can also happen if the dest of I3 is a memory ref,
1308 if another dest in I2 is an indirect memory ref. */
1309 for (i = 0; i < XVECLEN (p2, 0); i++)
1310 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1311 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1312 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1313 SET_DEST (XVECEXP (p2, 0, i))))
1316 if (i == XVECLEN (p2, 0))
1317 for (i = 0; i < XVECLEN (p2, 0); i++)
1318 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1323 subst_low_cuid = INSN_CUID (i2);
1325 added_sets_2 = added_sets_1 = 0;
1326 i2dest = SET_SRC (PATTERN (i3));
1328 /* Replace the dest in I2 with our dest and make the resulting
1329 insn the new pattern for I3. Then skip to where we
1330 validate the pattern. Everything was set up above. */
1331 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1332 SET_DEST (PATTERN (i3)));
1335 i3_subst_into_i2 = 1;
1336 goto validate_replacement;
1341 /* If we have no I1 and I2 looks like:
1342 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1344 make up a dummy I1 that is
1347 (set (reg:CC X) (compare:CC Y (const_int 0)))
1349 (We can ignore any trailing CLOBBERs.)
1351 This undoes a previous combination and allows us to match a branch-and-
1354 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1355 && XVECLEN (PATTERN (i2), 0) >= 2
1356 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1357 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1359 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1360 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1361 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1362 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1363 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1364 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1366 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1367 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1372 /* We make I1 with the same INSN_UID as I2. This gives it
1373 the same INSN_CUID for value tracking. Our fake I1 will
1374 never appear in the insn stream so giving it the same INSN_UID
1375 as I2 will not cause a problem. */
1377 subst_prev_insn = i1
1378 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1379 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1381 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1382 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1383 SET_DEST (PATTERN (i1)));
1388 /* Verify that I2 and I1 are valid for combining. */
1389 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1390 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1396 /* Record whether I2DEST is used in I2SRC and similarly for the other
1397 cases. Knowing this will help in register status updating below. */
1398 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1399 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1400 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1402 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1404 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1406 /* Ensure that I3's pattern can be the destination of combines. */
1407 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1408 i1 && i2dest_in_i1src && i1_feeds_i3,
1415 /* See if any of the insns is a MULT operation. Unless one is, we will
1416 reject a combination that is, since it must be slower. Be conservative
1418 if (GET_CODE (i2src) == MULT
1419 || (i1 != 0 && GET_CODE (i1src) == MULT)
1420 || (GET_CODE (PATTERN (i3)) == SET
1421 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1424 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1425 We used to do this EXCEPT in one case: I3 has a post-inc in an
1426 output operand. However, that exception can give rise to insns like
1428 which is a famous insn on the PDP-11 where the value of r3 used as the
1429 source was model-dependent. Avoid this sort of thing. */
1432 if (!(GET_CODE (PATTERN (i3)) == SET
1433 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1434 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1435 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1436 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1437 /* It's not the exception. */
1440 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1441 if (REG_NOTE_KIND (link) == REG_INC
1442 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1444 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1451 /* See if the SETs in I1 or I2 need to be kept around in the merged
1452 instruction: whenever the value set there is still needed past I3.
1453 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1455 For the SET in I1, we have two cases: If I1 and I2 independently
1456 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1457 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1458 in I1 needs to be kept around unless I1DEST dies or is set in either
1459 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1460 I1DEST. If so, we know I1 feeds into I2. */
1462 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1465 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1466 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1468 /* If the set in I2 needs to be kept around, we must make a copy of
1469 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1470 PATTERN (I2), we are only substituting for the original I1DEST, not into
1471 an already-substituted copy. This also prevents making self-referential
1472 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1475 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1476 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1480 i2pat = copy_rtx (i2pat);
1484 /* Substitute in the latest insn for the regs set by the earlier ones. */
1486 maxreg = max_reg_num ();
1490 /* It is possible that the source of I2 or I1 may be performing an
1491 unneeded operation, such as a ZERO_EXTEND of something that is known
1492 to have the high part zero. Handle that case by letting subst look at
1493 the innermost one of them.
1495 Another way to do this would be to have a function that tries to
1496 simplify a single insn instead of merging two or more insns. We don't
1497 do this because of the potential of infinite loops and because
1498 of the potential extra memory required. However, doing it the way
1499 we are is a bit of a kludge and doesn't catch all cases.
1501 But only do this if -fexpensive-optimizations since it slows things down
1502 and doesn't usually win. */
1504 if (flag_expensive_optimizations)
1506 /* Pass pc_rtx so no substitutions are done, just simplifications.
1507 The cases that we are interested in here do not involve the few
1508 cases were is_replaced is checked. */
1511 subst_low_cuid = INSN_CUID (i1);
1512 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1516 subst_low_cuid = INSN_CUID (i2);
1517 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1520 previous_num_undos = undobuf.num_undo;
1524 /* Many machines that don't use CC0 have insns that can both perform an
1525 arithmetic operation and set the condition code. These operations will
1526 be represented as a PARALLEL with the first element of the vector
1527 being a COMPARE of an arithmetic operation with the constant zero.
1528 The second element of the vector will set some pseudo to the result
1529 of the same arithmetic operation. If we simplify the COMPARE, we won't
1530 match such a pattern and so will generate an extra insn. Here we test
1531 for this case, where both the comparison and the operation result are
1532 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1533 I2SRC. Later we will make the PARALLEL that contains I2. */
1535 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1536 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1537 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1538 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1541 enum machine_mode compare_mode;
1543 newpat = PATTERN (i3);
1544 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1548 #ifdef EXTRA_CC_MODES
1549 /* See if a COMPARE with the operand we substituted in should be done
1550 with the mode that is currently being used. If not, do the same
1551 processing we do in `subst' for a SET; namely, if the destination
1552 is used only once, try to replace it with a register of the proper
1553 mode and also replace the COMPARE. */
1554 if (undobuf.other_insn == 0
1555 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1556 &undobuf.other_insn))
1557 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1559 != GET_MODE (SET_DEST (newpat))))
1561 int regno = REGNO (SET_DEST (newpat));
1562 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1564 if (regno < FIRST_PSEUDO_REGISTER
1565 || (reg_n_sets[regno] == 1 && ! added_sets_2
1566 && ! REG_USERVAR_P (SET_DEST (newpat))))
1568 if (regno >= FIRST_PSEUDO_REGISTER)
1569 SUBST (regno_reg_rtx[regno], new_dest);
1571 SUBST (SET_DEST (newpat), new_dest);
1572 SUBST (XEXP (*cc_use, 0), new_dest);
1573 SUBST (SET_SRC (newpat),
1574 gen_rtx_combine (COMPARE, compare_mode,
1575 i2src, const0_rtx));
1578 undobuf.other_insn = 0;
1585 n_occurrences = 0; /* `subst' counts here */
1587 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1588 need to make a unique copy of I2SRC each time we substitute it
1589 to avoid self-referential rtl. */
1591 subst_low_cuid = INSN_CUID (i2);
1592 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1593 ! i1_feeds_i3 && i1dest_in_i1src);
1594 previous_num_undos = undobuf.num_undo;
1596 /* Record whether i2's body now appears within i3's body. */
1597 i2_is_used = n_occurrences;
1600 /* If we already got a failure, don't try to do more. Otherwise,
1601 try to substitute in I1 if we have it. */
1603 if (i1 && GET_CODE (newpat) != CLOBBER)
1605 /* Before we can do this substitution, we must redo the test done
1606 above (see detailed comments there) that ensures that I1DEST
1607 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1609 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1617 subst_low_cuid = INSN_CUID (i1);
1618 newpat = subst (newpat, i1dest, i1src, 0, 0);
1619 previous_num_undos = undobuf.num_undo;
1622 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1623 to count all the ways that I2SRC and I1SRC can be used. */
1624 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1625 && i2_is_used + added_sets_2 > 1)
1626 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1627 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1629 /* Fail if we tried to make a new register (we used to abort, but there's
1630 really no reason to). */
1631 || max_reg_num () != maxreg
1632 /* Fail if we couldn't do something and have a CLOBBER. */
1633 || GET_CODE (newpat) == CLOBBER
1634 /* Fail if this new pattern is a MULT and we didn't have one before
1635 at the outer level. */
1636 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1643 /* If the actions of the earlier insns must be kept
1644 in addition to substituting them into the latest one,
1645 we must make a new PARALLEL for the latest insn
1646 to hold additional the SETs. */
1648 if (added_sets_1 || added_sets_2)
1652 if (GET_CODE (newpat) == PARALLEL)
1654 rtvec old = XVEC (newpat, 0);
1655 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1656 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1657 bcopy ((char *) &old->elem[0], (char *) &XVECEXP (newpat, 0, 0),
1658 sizeof (old->elem[0]) * old->num_elem);
1663 total_sets = 1 + added_sets_1 + added_sets_2;
1664 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1665 XVECEXP (newpat, 0, 0) = old;
1669 XVECEXP (newpat, 0, --total_sets)
1670 = (GET_CODE (PATTERN (i1)) == PARALLEL
1671 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1675 /* If there is no I1, use I2's body as is. We used to also not do
1676 the subst call below if I2 was substituted into I3,
1677 but that could lose a simplification. */
1679 XVECEXP (newpat, 0, --total_sets) = i2pat;
1681 /* See comment where i2pat is assigned. */
1682 XVECEXP (newpat, 0, --total_sets)
1683 = subst (i2pat, i1dest, i1src, 0, 0);
1687 /* We come here when we are replacing a destination in I2 with the
1688 destination of I3. */
1689 validate_replacement:
1691 /* Note which hard regs this insn has as inputs. */
1692 mark_used_regs_combine (newpat);
1694 /* Is the result of combination a valid instruction? */
1696 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1698 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1699 the second SET's destination is a register that is unused. In that case,
1700 we just need the first SET. This can occur when simplifying a divmod
1701 insn. We *must* test for this case here because the code below that
1702 splits two independent SETs doesn't handle this case correctly when it
1703 updates the register status. Also check the case where the first
1704 SET's destination is unused. That would not cause incorrect code, but
1705 does cause an unneeded insn to remain. */
1707 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1708 && XVECLEN (newpat, 0) == 2
1709 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1710 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1711 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1712 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1713 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1714 && asm_noperands (newpat) < 0)
1716 newpat = XVECEXP (newpat, 0, 0);
1718 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1721 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1722 && XVECLEN (newpat, 0) == 2
1723 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1724 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1725 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1726 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1727 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1728 && asm_noperands (newpat) < 0)
1730 newpat = XVECEXP (newpat, 0, 1);
1732 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1735 /* If we were combining three insns and the result is a simple SET
1736 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1737 insns. There are two ways to do this. It can be split using a
1738 machine-specific method (like when you have an addition of a large
1739 constant) or by combine in the function find_split_point. */
1741 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1742 && asm_noperands (newpat) < 0)
1744 rtx m_split, *split;
1745 rtx ni2dest = i2dest;
1747 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1748 use I2DEST as a scratch register will help. In the latter case,
1749 convert I2DEST to the mode of the source of NEWPAT if we can. */
1751 m_split = split_insns (newpat, i3);
1753 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1754 inputs of NEWPAT. */
1756 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1757 possible to try that as a scratch reg. This would require adding
1758 more code to make it work though. */
1760 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1762 /* If I2DEST is a hard register or the only use of a pseudo,
1763 we can change its mode. */
1764 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1765 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1766 && GET_CODE (i2dest) == REG
1767 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1768 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1769 && ! REG_USERVAR_P (i2dest))))
1770 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1773 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1774 gen_rtvec (2, newpat,
1781 if (m_split && GET_CODE (m_split) == SEQUENCE
1782 && XVECLEN (m_split, 0) == 2
1783 && (next_real_insn (i2) == i3
1784 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1788 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1789 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1791 i3set = single_set (XVECEXP (m_split, 0, 1));
1792 i2set = single_set (XVECEXP (m_split, 0, 0));
1794 /* In case we changed the mode of I2DEST, replace it in the
1795 pseudo-register table here. We can't do it above in case this
1796 code doesn't get executed and we do a split the other way. */
1798 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1799 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1801 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1804 /* If I2 or I3 has multiple SETs, we won't know how to track
1805 register status, so don't use these insns. */
1807 if (i2_code_number >= 0 && i2set && i3set)
1808 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1810 if (insn_code_number >= 0)
1813 /* It is possible that both insns now set the destination of I3.
1814 If so, we must show an extra use of it. */
1816 if (insn_code_number >= 0)
1818 rtx new_i3_dest = SET_DEST (i3set);
1819 rtx new_i2_dest = SET_DEST (i2set);
1821 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1822 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1823 || GET_CODE (new_i3_dest) == SUBREG)
1824 new_i3_dest = XEXP (new_i3_dest, 0);
1826 if (GET_CODE (new_i3_dest) == REG
1827 && GET_CODE (new_i2_dest) == REG
1828 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1829 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1833 /* If we can split it and use I2DEST, go ahead and see if that
1834 helps things be recognized. Verify that none of the registers
1835 are set between I2 and I3. */
1836 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1838 && GET_CODE (i2dest) == REG
1840 /* We need I2DEST in the proper mode. If it is a hard register
1841 or the only use of a pseudo, we can change its mode. */
1842 && (GET_MODE (*split) == GET_MODE (i2dest)
1843 || GET_MODE (*split) == VOIDmode
1844 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1845 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1846 && ! REG_USERVAR_P (i2dest)))
1847 && (next_real_insn (i2) == i3
1848 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1849 /* We can't overwrite I2DEST if its value is still used by
1851 && ! reg_referenced_p (i2dest, newpat))
1853 rtx newdest = i2dest;
1854 enum rtx_code split_code = GET_CODE (*split);
1855 enum machine_mode split_mode = GET_MODE (*split);
1857 /* Get NEWDEST as a register in the proper mode. We have already
1858 validated that we can do this. */
1859 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1861 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1863 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1864 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1867 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1868 an ASHIFT. This can occur if it was inside a PLUS and hence
1869 appeared to be a memory address. This is a kludge. */
1870 if (split_code == MULT
1871 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1872 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1874 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1875 XEXP (*split, 0), GEN_INT (i)));
1876 /* Update split_code because we may not have a multiply
1878 split_code = GET_CODE (*split);
1881 #ifdef INSN_SCHEDULING
1882 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1883 be written as a ZERO_EXTEND. */
1884 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1885 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1889 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1890 SUBST (*split, newdest);
1892 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1894 /* If the split point was a MULT and we didn't have one before,
1895 don't use one now. */
1896 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1898 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1902 /* Check for a case where we loaded from memory in a narrow mode and
1903 then sign extended it, but we need both registers. In that case,
1904 we have a PARALLEL with both loads from the same memory location.
1905 We can split this into a load from memory followed by a register-register
1906 copy. This saves at least one insn, more if register allocation can
1909 We cannot do this if the destination of the second assignment is
1910 a register that we have already assumed is zero-extended. Similarly
1911 for a SUBREG of such a register. */
1913 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1914 && GET_CODE (newpat) == PARALLEL
1915 && XVECLEN (newpat, 0) == 2
1916 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1917 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1918 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1919 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1920 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1921 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1923 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1924 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1925 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1926 (GET_CODE (temp) == REG
1927 && reg_nonzero_bits[REGNO (temp)] != 0
1928 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1929 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1930 && (reg_nonzero_bits[REGNO (temp)]
1931 != GET_MODE_MASK (word_mode))))
1932 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1933 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1934 (GET_CODE (temp) == REG
1935 && reg_nonzero_bits[REGNO (temp)] != 0
1936 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1937 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1938 && (reg_nonzero_bits[REGNO (temp)]
1939 != GET_MODE_MASK (word_mode)))))
1940 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1941 SET_SRC (XVECEXP (newpat, 0, 1)))
1942 && ! find_reg_note (i3, REG_UNUSED,
1943 SET_DEST (XVECEXP (newpat, 0, 0))))
1947 newi2pat = XVECEXP (newpat, 0, 0);
1948 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1949 newpat = XVECEXP (newpat, 0, 1);
1950 SUBST (SET_SRC (newpat),
1951 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1953 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1955 if (i2_code_number >= 0)
1957 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1959 if (insn_code_number >= 0)
1964 /* If we will be able to accept this, we have made a change to the
1965 destination of I3. This can invalidate a LOG_LINKS pointing
1966 to I3. No other part of combine.c makes such a transformation.
1968 The new I3 will have a destination that was previously the
1969 destination of I1 or I2 and which was used in i2 or I3. Call
1970 distribute_links to make a LOG_LINK from the next use of
1971 that destination. */
1973 PATTERN (i3) = newpat;
1974 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1976 /* I3 now uses what used to be its destination and which is
1977 now I2's destination. That means we need a LOG_LINK from
1978 I3 to I2. But we used to have one, so we still will.
1980 However, some later insn might be using I2's dest and have
1981 a LOG_LINK pointing at I3. We must remove this link.
1982 The simplest way to remove the link is to point it at I1,
1983 which we know will be a NOTE. */
1985 for (insn = NEXT_INSN (i3);
1986 insn && (this_basic_block == n_basic_blocks - 1
1987 || insn != basic_block_head[this_basic_block + 1]);
1988 insn = NEXT_INSN (insn))
1990 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1991 && reg_referenced_p (ni2dest, PATTERN (insn)))
1993 for (link = LOG_LINKS (insn); link;
1994 link = XEXP (link, 1))
1995 if (XEXP (link, 0) == i3)
1996 XEXP (link, 0) = i1;
2004 /* Similarly, check for a case where we have a PARALLEL of two independent
2005 SETs but we started with three insns. In this case, we can do the sets
2006 as two separate insns. This case occurs when some SET allows two
2007 other insns to combine, but the destination of that SET is still live. */
2009 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2010 && GET_CODE (newpat) == PARALLEL
2011 && XVECLEN (newpat, 0) == 2
2012 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2013 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2014 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2015 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2016 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2017 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2018 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2020 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2021 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2022 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2023 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2024 XVECEXP (newpat, 0, 0))
2025 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2026 XVECEXP (newpat, 0, 1)))
2028 newi2pat = XVECEXP (newpat, 0, 1);
2029 newpat = XVECEXP (newpat, 0, 0);
2032 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2034 if (i2_code_number >= 0)
2036 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2039 /* If it still isn't recognized, fail and change things back the way they
2041 if ((insn_code_number < 0
2042 /* Is the result a reasonable ASM_OPERANDS? */
2043 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2049 /* If we had to change another insn, make sure it is valid also. */
2050 if (undobuf.other_insn)
2052 rtx other_pat = PATTERN (undobuf.other_insn);
2053 rtx new_other_notes;
2056 CLEAR_HARD_REG_SET (newpat_used_regs);
2059 = recog_for_combine (&other_pat, undobuf.other_insn,
2060 &new_other_notes, &other_scratches);
2062 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2068 PATTERN (undobuf.other_insn) = other_pat;
2070 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2071 are still valid. Then add any non-duplicate notes added by
2072 recog_for_combine. */
2073 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2075 next = XEXP (note, 1);
2077 if (REG_NOTE_KIND (note) == REG_UNUSED
2078 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2080 if (GET_CODE (XEXP (note, 0)) == REG)
2081 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2083 remove_note (undobuf.other_insn, note);
2087 for (note = new_other_notes; note; note = XEXP (note, 1))
2088 if (GET_CODE (XEXP (note, 0)) == REG)
2089 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2091 distribute_notes (new_other_notes, undobuf.other_insn,
2092 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2095 /* We now know that we can do this combination. Merge the insns and
2096 update the status of registers and LOG_LINKS. */
2099 rtx i3notes, i2notes, i1notes = 0;
2100 rtx i3links, i2links, i1links = 0;
2103 /* Compute which registers we expect to eliminate. */
2104 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2106 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2108 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2110 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2111 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2113 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2115 /* Ensure that we do not have something that should not be shared but
2116 occurs multiple times in the new insns. Check this by first
2117 resetting all the `used' flags and then copying anything is shared. */
2119 reset_used_flags (i3notes);
2120 reset_used_flags (i2notes);
2121 reset_used_flags (i1notes);
2122 reset_used_flags (newpat);
2123 reset_used_flags (newi2pat);
2124 if (undobuf.other_insn)
2125 reset_used_flags (PATTERN (undobuf.other_insn));
2127 i3notes = copy_rtx_if_shared (i3notes);
2128 i2notes = copy_rtx_if_shared (i2notes);
2129 i1notes = copy_rtx_if_shared (i1notes);
2130 newpat = copy_rtx_if_shared (newpat);
2131 newi2pat = copy_rtx_if_shared (newi2pat);
2132 if (undobuf.other_insn)
2133 reset_used_flags (PATTERN (undobuf.other_insn));
2135 INSN_CODE (i3) = insn_code_number;
2136 PATTERN (i3) = newpat;
2137 if (undobuf.other_insn)
2138 INSN_CODE (undobuf.other_insn) = other_code_number;
2140 /* We had one special case above where I2 had more than one set and
2141 we replaced a destination of one of those sets with the destination
2142 of I3. In that case, we have to update LOG_LINKS of insns later
2143 in this basic block. Note that this (expensive) case is rare.
2145 Also, in this case, we must pretend that all REG_NOTEs for I2
2146 actually came from I3, so that REG_UNUSED notes from I2 will be
2147 properly handled. */
2149 if (i3_subst_into_i2)
2151 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2152 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2153 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2154 && ! find_reg_note (i2, REG_UNUSED,
2155 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2156 for (temp = NEXT_INSN (i2);
2157 temp && (this_basic_block == n_basic_blocks - 1
2158 || basic_block_head[this_basic_block] != temp);
2159 temp = NEXT_INSN (temp))
2160 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2161 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2162 if (XEXP (link, 0) == i2)
2163 XEXP (link, 0) = i3;
2168 while (XEXP (link, 1))
2169 link = XEXP (link, 1);
2170 XEXP (link, 1) = i2notes;
2184 INSN_CODE (i2) = i2_code_number;
2185 PATTERN (i2) = newi2pat;
2189 PUT_CODE (i2, NOTE);
2190 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2191 NOTE_SOURCE_FILE (i2) = 0;
2198 PUT_CODE (i1, NOTE);
2199 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2200 NOTE_SOURCE_FILE (i1) = 0;
2203 /* Get death notes for everything that is now used in either I3 or
2204 I2 and used to die in a previous insn. */
2206 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2208 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2210 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2212 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2215 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2218 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2221 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2224 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2225 know these are REG_UNUSED and want them to go to the desired insn,
2226 so we always pass it as i3. We have not counted the notes in
2227 reg_n_deaths yet, so we need to do so now. */
2229 if (newi2pat && new_i2_notes)
2231 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2232 if (GET_CODE (XEXP (temp, 0)) == REG)
2233 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2235 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2240 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2241 if (GET_CODE (XEXP (temp, 0)) == REG)
2242 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2244 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2247 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2248 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2249 Show an additional death due to the REG_DEAD note we make here. If
2250 we discard it in distribute_notes, we will decrement it again. */
2254 if (GET_CODE (i3dest_killed) == REG)
2255 reg_n_deaths[REGNO (i3dest_killed)]++;
2257 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2259 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2260 NULL_RTX, NULL_RTX);
2263 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2264 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2265 we passed I3 in that case, it might delete I2. */
2267 if (i2dest_in_i2src)
2269 if (GET_CODE (i2dest) == REG)
2270 reg_n_deaths[REGNO (i2dest)]++;
2272 if (newi2pat && reg_set_p (i2dest, newi2pat))
2273 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2274 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2276 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2277 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2278 NULL_RTX, NULL_RTX);
2281 if (i1dest_in_i1src)
2283 if (GET_CODE (i1dest) == REG)
2284 reg_n_deaths[REGNO (i1dest)]++;
2286 if (newi2pat && reg_set_p (i1dest, newi2pat))
2287 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2288 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2290 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2291 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2292 NULL_RTX, NULL_RTX);
2295 distribute_links (i3links);
2296 distribute_links (i2links);
2297 distribute_links (i1links);
2299 if (GET_CODE (i2dest) == REG)
2302 rtx i2_insn = 0, i2_val = 0, set;
2304 /* The insn that used to set this register doesn't exist, and
2305 this life of the register may not exist either. See if one of
2306 I3's links points to an insn that sets I2DEST. If it does,
2307 that is now the last known value for I2DEST. If we don't update
2308 this and I2 set the register to a value that depended on its old
2309 contents, we will get confused. If this insn is used, thing
2310 will be set correctly in combine_instructions. */
2312 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2313 if ((set = single_set (XEXP (link, 0))) != 0
2314 && rtx_equal_p (i2dest, SET_DEST (set)))
2315 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2317 record_value_for_reg (i2dest, i2_insn, i2_val);
2319 /* If the reg formerly set in I2 died only once and that was in I3,
2320 zero its use count so it won't make `reload' do any work. */
2321 if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src)
2323 regno = REGNO (i2dest);
2324 reg_n_sets[regno]--;
2325 if (reg_n_sets[regno] == 0
2326 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2327 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2328 reg_n_refs[regno] = 0;
2332 if (i1 && GET_CODE (i1dest) == REG)
2335 rtx i1_insn = 0, i1_val = 0, set;
2337 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2338 if ((set = single_set (XEXP (link, 0))) != 0
2339 && rtx_equal_p (i1dest, SET_DEST (set)))
2340 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2342 record_value_for_reg (i1dest, i1_insn, i1_val);
2344 regno = REGNO (i1dest);
2345 if (! added_sets_1 && ! i1dest_in_i1src)
2347 reg_n_sets[regno]--;
2348 if (reg_n_sets[regno] == 0
2349 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2350 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2351 reg_n_refs[regno] = 0;
2355 /* Update reg_nonzero_bits et al for any changes that may have been made
2358 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2360 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2362 /* If we added any (clobber (scratch)), add them to the max for a
2363 block. This is a very pessimistic calculation, since we might
2364 have had them already and this might not be the worst block, but
2365 it's not worth doing any better. */
2366 max_scratch += i3_scratches + i2_scratches + other_scratches;
2368 /* If I3 is now an unconditional jump, ensure that it has a
2369 BARRIER following it since it may have initially been a
2370 conditional jump. It may also be the last nonnote insn. */
2372 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2373 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2374 || GET_CODE (temp) != BARRIER))
2375 emit_barrier_after (i3);
2378 combine_successes++;
2380 /* Clear this here, so that subsequent get_last_value calls are not
2382 subst_prev_insn = NULL_RTX;
2384 if (added_links_insn
2385 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2386 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2387 return added_links_insn;
2389 return newi2pat ? i2 : i3;
2392 /* Undo all the modifications recorded in undobuf. */
2398 if (undobuf.num_undo > MAX_UNDO)
2399 undobuf.num_undo = MAX_UNDO;
2400 for (i = undobuf.num_undo - 1; i >= 0; i--)
2402 if (undobuf.undo[i].is_int)
2403 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2405 *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r;
2409 obfree (undobuf.storage);
2410 undobuf.num_undo = 0;
2412 /* Clear this here, so that subsequent get_last_value calls are not
2414 subst_prev_insn = NULL_RTX;
2417 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2418 where we have an arithmetic expression and return that point. LOC will
2421 try_combine will call this function to see if an insn can be split into
2425 find_split_point (loc, insn)
2430 enum rtx_code code = GET_CODE (x);
2432 int len = 0, pos, unsignedp;
2435 /* First special-case some codes. */
2439 #ifdef INSN_SCHEDULING
2440 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2442 if (GET_CODE (SUBREG_REG (x)) == MEM)
2445 return find_split_point (&SUBREG_REG (x), insn);
2449 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2450 using LO_SUM and HIGH. */
2451 if (GET_CODE (XEXP (x, 0)) == CONST
2452 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2455 gen_rtx_combine (LO_SUM, Pmode,
2456 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2458 return &XEXP (XEXP (x, 0), 0);
2462 /* If we have a PLUS whose second operand is a constant and the
2463 address is not valid, perhaps will can split it up using
2464 the machine-specific way to split large constants. We use
2465 the first pseudo-reg (one of the virtual regs) as a placeholder;
2466 it will not remain in the result. */
2467 if (GET_CODE (XEXP (x, 0)) == PLUS
2468 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2469 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2471 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2472 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2475 /* This should have produced two insns, each of which sets our
2476 placeholder. If the source of the second is a valid address,
2477 we can make put both sources together and make a split point
2480 if (seq && XVECLEN (seq, 0) == 2
2481 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2482 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2483 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2484 && ! reg_mentioned_p (reg,
2485 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2486 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2487 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2488 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2489 && memory_address_p (GET_MODE (x),
2490 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2492 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2493 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2495 /* Replace the placeholder in SRC2 with SRC1. If we can
2496 find where in SRC2 it was placed, that can become our
2497 split point and we can replace this address with SRC2.
2498 Just try two obvious places. */
2500 src2 = replace_rtx (src2, reg, src1);
2502 if (XEXP (src2, 0) == src1)
2503 split = &XEXP (src2, 0);
2504 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2505 && XEXP (XEXP (src2, 0), 0) == src1)
2506 split = &XEXP (XEXP (src2, 0), 0);
2510 SUBST (XEXP (x, 0), src2);
2515 /* If that didn't work, perhaps the first operand is complex and
2516 needs to be computed separately, so make a split point there.
2517 This will occur on machines that just support REG + CONST
2518 and have a constant moved through some previous computation. */
2520 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2521 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2522 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2524 return &XEXP (XEXP (x, 0), 0);
2530 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2531 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2532 we need to put the operand into a register. So split at that
2535 if (SET_DEST (x) == cc0_rtx
2536 && GET_CODE (SET_SRC (x)) != COMPARE
2537 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2538 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2539 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2540 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2541 return &SET_SRC (x);
2544 /* See if we can split SET_SRC as it stands. */
2545 split = find_split_point (&SET_SRC (x), insn);
2546 if (split && split != &SET_SRC (x))
2549 /* See if we can split SET_DEST as it stands. */
2550 split = find_split_point (&SET_DEST (x), insn);
2551 if (split && split != &SET_DEST (x))
2554 /* See if this is a bitfield assignment with everything constant. If
2555 so, this is an IOR of an AND, so split it into that. */
2556 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2557 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2558 <= HOST_BITS_PER_WIDE_INT)
2559 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2560 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2561 && GET_CODE (SET_SRC (x)) == CONST_INT
2562 && ((INTVAL (XEXP (SET_DEST (x), 1))
2563 + INTVAL (XEXP (SET_DEST (x), 2)))
2564 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2565 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2567 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2568 int len = INTVAL (XEXP (SET_DEST (x), 1));
2569 int src = INTVAL (SET_SRC (x));
2570 rtx dest = XEXP (SET_DEST (x), 0);
2571 enum machine_mode mode = GET_MODE (dest);
2572 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2574 if (BITS_BIG_ENDIAN)
2575 pos = GET_MODE_BITSIZE (mode) - len - pos;
2579 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2582 gen_binary (IOR, mode,
2583 gen_binary (AND, mode, dest,
2584 GEN_INT (~ (mask << pos)
2585 & GET_MODE_MASK (mode))),
2586 GEN_INT (src << pos)));
2588 SUBST (SET_DEST (x), dest);
2590 split = find_split_point (&SET_SRC (x), insn);
2591 if (split && split != &SET_SRC (x))
2595 /* Otherwise, see if this is an operation that we can split into two.
2596 If so, try to split that. */
2597 code = GET_CODE (SET_SRC (x));
2602 /* If we are AND'ing with a large constant that is only a single
2603 bit and the result is only being used in a context where we
2604 need to know if it is zero or non-zero, replace it with a bit
2605 extraction. This will avoid the large constant, which might
2606 have taken more than one insn to make. If the constant were
2607 not a valid argument to the AND but took only one insn to make,
2608 this is no worse, but if it took more than one insn, it will
2611 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2612 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2613 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2614 && GET_CODE (SET_DEST (x)) == REG
2615 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2616 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2617 && XEXP (*split, 0) == SET_DEST (x)
2618 && XEXP (*split, 1) == const0_rtx)
2620 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2621 XEXP (SET_SRC (x), 0),
2622 pos, NULL_RTX, 1, 1, 0, 0);
2623 if (extraction != 0)
2625 SUBST (SET_SRC (x), extraction);
2626 return find_split_point (loc, insn);
2632 inner = XEXP (SET_SRC (x), 0);
2634 len = GET_MODE_BITSIZE (GET_MODE (inner));
2640 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2641 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2643 inner = XEXP (SET_SRC (x), 0);
2644 len = INTVAL (XEXP (SET_SRC (x), 1));
2645 pos = INTVAL (XEXP (SET_SRC (x), 2));
2647 if (BITS_BIG_ENDIAN)
2648 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2649 unsignedp = (code == ZERO_EXTRACT);
2654 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2656 enum machine_mode mode = GET_MODE (SET_SRC (x));
2658 /* For unsigned, we have a choice of a shift followed by an
2659 AND or two shifts. Use two shifts for field sizes where the
2660 constant might be too large. We assume here that we can
2661 always at least get 8-bit constants in an AND insn, which is
2662 true for every current RISC. */
2664 if (unsignedp && len <= 8)
2669 gen_rtx_combine (LSHIFTRT, mode,
2670 gen_lowpart_for_combine (mode, inner),
2672 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2674 split = find_split_point (&SET_SRC (x), insn);
2675 if (split && split != &SET_SRC (x))
2682 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2683 gen_rtx_combine (ASHIFT, mode,
2684 gen_lowpart_for_combine (mode, inner),
2685 GEN_INT (GET_MODE_BITSIZE (mode)
2687 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2689 split = find_split_point (&SET_SRC (x), insn);
2690 if (split && split != &SET_SRC (x))
2695 /* See if this is a simple operation with a constant as the second
2696 operand. It might be that this constant is out of range and hence
2697 could be used as a split point. */
2698 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2699 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2700 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2701 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2702 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2703 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2704 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2706 return &XEXP (SET_SRC (x), 1);
2708 /* Finally, see if this is a simple operation with its first operand
2709 not in a register. The operation might require this operand in a
2710 register, so return it as a split point. We can always do this
2711 because if the first operand were another operation, we would have
2712 already found it as a split point. */
2713 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2714 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2715 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2716 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2717 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2718 return &XEXP (SET_SRC (x), 0);
2724 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2725 it is better to write this as (not (ior A B)) so we can split it.
2726 Similarly for IOR. */
2727 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2730 gen_rtx_combine (NOT, GET_MODE (x),
2731 gen_rtx_combine (code == IOR ? AND : IOR,
2733 XEXP (XEXP (x, 0), 0),
2734 XEXP (XEXP (x, 1), 0))));
2735 return find_split_point (loc, insn);
2738 /* Many RISC machines have a large set of logical insns. If the
2739 second operand is a NOT, put it first so we will try to split the
2740 other operand first. */
2741 if (GET_CODE (XEXP (x, 1)) == NOT)
2743 rtx tem = XEXP (x, 0);
2744 SUBST (XEXP (x, 0), XEXP (x, 1));
2745 SUBST (XEXP (x, 1), tem);
2750 /* Otherwise, select our actions depending on our rtx class. */
2751 switch (GET_RTX_CLASS (code))
2753 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2755 split = find_split_point (&XEXP (x, 2), insn);
2758 /* ... fall through ... */
2762 split = find_split_point (&XEXP (x, 1), insn);
2765 /* ... fall through ... */
2767 /* Some machines have (and (shift ...) ...) insns. If X is not
2768 an AND, but XEXP (X, 0) is, use it as our split point. */
2769 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2770 return &XEXP (x, 0);
2772 split = find_split_point (&XEXP (x, 0), insn);
2778 /* Otherwise, we don't have a split point. */
2782 /* Throughout X, replace FROM with TO, and return the result.
2783 The result is TO if X is FROM;
2784 otherwise the result is X, but its contents may have been modified.
2785 If they were modified, a record was made in undobuf so that
2786 undo_all will (among other things) return X to its original state.
2788 If the number of changes necessary is too much to record to undo,
2789 the excess changes are not made, so the result is invalid.
2790 The changes already made can still be undone.
2791 undobuf.num_undo is incremented for such changes, so by testing that
2792 the caller can tell whether the result is valid.
2794 `n_occurrences' is incremented each time FROM is replaced.
2796 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2798 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2799 by copying if `n_occurrences' is non-zero. */
2802 subst (x, from, to, in_dest, unique_copy)
2803 register rtx x, from, to;
2807 register enum rtx_code code = GET_CODE (x);
2808 enum machine_mode op0_mode = VOIDmode;
2810 register int len, i;
2813 /* Two expressions are equal if they are identical copies of a shared
2814 RTX or if they are both registers with the same register number
2817 #define COMBINE_RTX_EQUAL_P(X,Y) \
2819 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2820 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2822 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2825 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2828 /* If X and FROM are the same register but different modes, they will
2829 not have been seen as equal above. However, flow.c will make a
2830 LOG_LINKS entry for that case. If we do nothing, we will try to
2831 rerecognize our original insn and, when it succeeds, we will
2832 delete the feeding insn, which is incorrect.
2834 So force this insn not to match in this (rare) case. */
2835 if (! in_dest && code == REG && GET_CODE (from) == REG
2836 && REGNO (x) == REGNO (from))
2837 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2839 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2840 of which may contain things that can be combined. */
2841 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2844 /* It is possible to have a subexpression appear twice in the insn.
2845 Suppose that FROM is a register that appears within TO.
2846 Then, after that subexpression has been scanned once by `subst',
2847 the second time it is scanned, TO may be found. If we were
2848 to scan TO here, we would find FROM within it and create a
2849 self-referent rtl structure which is completely wrong. */
2850 if (COMBINE_RTX_EQUAL_P (x, to))
2853 len = GET_RTX_LENGTH (code);
2854 fmt = GET_RTX_FORMAT (code);
2856 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2857 set up to skip this common case. All other cases where we want to
2858 suppress replacing something inside a SET_SRC are handled via the
2861 && (GET_CODE (SET_DEST (x)) == REG
2862 || GET_CODE (SET_DEST (x)) == CC0
2863 || GET_CODE (SET_DEST (x)) == PC))
2866 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2868 op0_mode = GET_MODE (XEXP (x, 0));
2870 for (i = 0; i < len; i++)
2875 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2877 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2879 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2884 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2886 /* If this substitution failed, this whole thing fails. */
2887 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2891 SUBST (XVECEXP (x, i, j), new);
2894 else if (fmt[i] == 'e')
2896 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2898 /* In general, don't install a subreg involving two modes not
2899 tieable. It can worsen register allocation, and can even
2900 make invalid reload insns, since the reg inside may need to
2901 be copied from in the outside mode, and that may be invalid
2902 if it is an fp reg copied in integer mode.
2904 We allow two exceptions to this: It is valid if it is inside
2905 another SUBREG and the mode of that SUBREG and the mode of
2906 the inside of TO is tieable and it is valid if X is a SET
2907 that copies FROM to CC0. */
2908 if (GET_CODE (to) == SUBREG
2909 && ! MODES_TIEABLE_P (GET_MODE (to),
2910 GET_MODE (SUBREG_REG (to)))
2911 && ! (code == SUBREG
2912 && MODES_TIEABLE_P (GET_MODE (x),
2913 GET_MODE (SUBREG_REG (to))))
2915 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2918 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2920 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2924 /* If we are in a SET_DEST, suppress most cases unless we
2925 have gone inside a MEM, in which case we want to
2926 simplify the address. We assume here that things that
2927 are actually part of the destination have their inner
2928 parts in the first expression. This is true for SUBREG,
2929 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2930 things aside from REG and MEM that should appear in a
2932 new = subst (XEXP (x, i), from, to,
2934 && (code == SUBREG || code == STRICT_LOW_PART
2935 || code == ZERO_EXTRACT))
2937 && i == 0), unique_copy);
2939 /* If we found that we will have to reject this combination,
2940 indicate that by returning the CLOBBER ourselves, rather than
2941 an expression containing it. This will speed things up as
2942 well as prevent accidents where two CLOBBERs are considered
2943 to be equal, thus producing an incorrect simplification. */
2945 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2948 SUBST (XEXP (x, i), new);
2952 /* Try to simplify X. If the simplification changed the code, it is likely
2953 that further simplification will help, so loop, but limit the number
2954 of repetitions that will be performed. */
2956 for (i = 0; i < 4; i++)
2958 /* If X is sufficiently simple, don't bother trying to do anything
2960 if (code != CONST_INT && code != REG && code != CLOBBER)
2961 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
2963 if (GET_CODE (x) == code)
2966 code = GET_CODE (x);
2968 /* We no longer know the original mode of operand 0 since we
2969 have changed the form of X) */
2970 op0_mode = VOIDmode;
2976 /* Simplify X, a piece of RTL. We just operate on the expression at the
2977 outer level; call `subst' to simplify recursively. Return the new
2980 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
2981 will be the iteration even if an expression with a code different from
2982 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
2985 simplify_rtx (x, op0_mode, last, in_dest)
2987 enum machine_mode op0_mode;
2991 enum rtx_code code = GET_CODE (x);
2992 enum machine_mode mode = GET_MODE (x);
2996 /* If this is a commutative operation, put a constant last and a complex
2997 expression first. We don't need to do this for comparisons here. */
2998 if (GET_RTX_CLASS (code) == 'c'
2999 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3000 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3001 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3002 || (GET_CODE (XEXP (x, 0)) == SUBREG
3003 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3004 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3007 SUBST (XEXP (x, 0), XEXP (x, 1));
3008 SUBST (XEXP (x, 1), temp);
3011 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3012 sign extension of a PLUS with a constant, reverse the order of the sign
3013 extension and the addition. Note that this not the same as the original
3014 code, but overflow is undefined for signed values. Also note that the
3015 PLUS will have been partially moved "inside" the sign-extension, so that
3016 the first operand of X will really look like:
3017 (ashiftrt (plus (ashift A C4) C5) C4).
3019 (plus (ashiftrt (ashift A C4) C2) C4)
3020 and replace the first operand of X with that expression. Later parts
3021 of this function may simplify the expression further.
3023 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3024 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3025 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3027 We do this to simplify address expressions. */
3029 if ((code == PLUS || code == MINUS || code == MULT)
3030 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3031 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3032 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3033 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3034 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3035 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3036 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3037 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3038 XEXP (XEXP (XEXP (x, 0), 0), 1),
3039 XEXP (XEXP (x, 0), 1))) != 0)
3042 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3043 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3044 INTVAL (XEXP (XEXP (x, 0), 1)));
3046 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3047 INTVAL (XEXP (XEXP (x, 0), 1)));
3049 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3052 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3053 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3054 things. Check for cases where both arms are testing the same
3057 Don't do anything if all operands are very simple. */
3059 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3060 || GET_RTX_CLASS (code) == '<')
3061 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3062 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3063 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3065 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3066 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3067 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3069 || (GET_RTX_CLASS (code) == '1'
3070 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3071 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3072 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3075 rtx cond, true, false;
3077 cond = if_then_else_cond (x, &true, &false);
3080 rtx cop1 = const0_rtx;
3081 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3083 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3086 /* Simplify the alternative arms; this may collapse the true and
3087 false arms to store-flag values. */
3088 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3089 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3091 /* Restarting if we generate a store-flag expression will cause
3092 us to loop. Just drop through in this case. */
3094 /* If the result values are STORE_FLAG_VALUE and zero, we can
3095 just make the comparison operation. */
3096 if (true == const_true_rtx && false == const0_rtx)
3097 x = gen_binary (cond_code, mode, cond, cop1);
3098 else if (true == const0_rtx && false == const_true_rtx)
3099 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3101 /* Likewise, we can make the negate of a comparison operation
3102 if the result values are - STORE_FLAG_VALUE and zero. */
3103 else if (GET_CODE (true) == CONST_INT
3104 && INTVAL (true) == - STORE_FLAG_VALUE
3105 && false == const0_rtx)
3106 x = gen_unary (NEG, mode, mode,
3107 gen_binary (cond_code, mode, cond, cop1));
3108 else if (GET_CODE (false) == CONST_INT
3109 && INTVAL (false) == - STORE_FLAG_VALUE
3110 && true == const0_rtx)
3111 x = gen_unary (NEG, mode, mode,
3112 gen_binary (reverse_condition (cond_code),
3115 return gen_rtx (IF_THEN_ELSE, mode,
3116 gen_binary (cond_code, VOIDmode, cond, cop1),
3119 code = GET_CODE (x);
3120 op0_mode = VOIDmode;
3124 /* Try to fold this expression in case we have constants that weren't
3127 switch (GET_RTX_CLASS (code))
3130 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3133 temp = simplify_relational_operation (code, op0_mode,
3134 XEXP (x, 0), XEXP (x, 1));
3135 #ifdef FLOAT_STORE_FLAG_VALUE
3136 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3137 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3138 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3143 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3147 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3148 XEXP (x, 1), XEXP (x, 2));
3153 x = temp, code = GET_CODE (temp);
3155 /* First see if we can apply the inverse distributive law. */
3156 if (code == PLUS || code == MINUS
3157 || code == AND || code == IOR || code == XOR)
3159 x = apply_distributive_law (x);
3160 code = GET_CODE (x);
3163 /* If CODE is an associative operation not otherwise handled, see if we
3164 can associate some operands. This can win if they are constants or
3165 if they are logically related (i.e. (a & b) & a. */
3166 if ((code == PLUS || code == MINUS
3167 || code == MULT || code == AND || code == IOR || code == XOR
3168 || code == DIV || code == UDIV
3169 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3170 && INTEGRAL_MODE_P (mode))
3172 if (GET_CODE (XEXP (x, 0)) == code)
3174 rtx other = XEXP (XEXP (x, 0), 0);
3175 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3176 rtx inner_op1 = XEXP (x, 1);
3179 /* Make sure we pass the constant operand if any as the second
3180 one if this is a commutative operation. */
3181 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3183 rtx tem = inner_op0;
3184 inner_op0 = inner_op1;
3187 inner = simplify_binary_operation (code == MINUS ? PLUS
3188 : code == DIV ? MULT
3189 : code == UDIV ? MULT
3191 mode, inner_op0, inner_op1);
3193 /* For commutative operations, try the other pair if that one
3195 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3197 other = XEXP (XEXP (x, 0), 1);
3198 inner = simplify_binary_operation (code, mode,
3199 XEXP (XEXP (x, 0), 0),
3204 return gen_binary (code, mode, other, inner);
3208 /* A little bit of algebraic simplification here. */
3212 /* Ensure that our address has any ASHIFTs converted to MULT in case
3213 address-recognizing predicates are called later. */
3214 temp = make_compound_operation (XEXP (x, 0), MEM);
3215 SUBST (XEXP (x, 0), temp);
3219 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3220 is paradoxical. If we can't do that safely, then it becomes
3221 something nonsensical so that this combination won't take place. */
3223 if (GET_CODE (SUBREG_REG (x)) == MEM
3224 && (GET_MODE_SIZE (mode)
3225 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3227 rtx inner = SUBREG_REG (x);
3228 int endian_offset = 0;
3229 /* Don't change the mode of the MEM
3230 if that would change the meaning of the address. */
3231 if (MEM_VOLATILE_P (SUBREG_REG (x))
3232 || mode_dependent_address_p (XEXP (inner, 0)))
3233 return gen_rtx (CLOBBER, mode, const0_rtx);
3235 if (BYTES_BIG_ENDIAN)
3237 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3238 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3239 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3240 endian_offset -= (UNITS_PER_WORD
3241 - GET_MODE_SIZE (GET_MODE (inner)));
3243 /* Note if the plus_constant doesn't make a valid address
3244 then this combination won't be accepted. */
3245 x = gen_rtx (MEM, mode,
3246 plus_constant (XEXP (inner, 0),
3247 (SUBREG_WORD (x) * UNITS_PER_WORD
3249 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3250 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3251 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3255 /* If we are in a SET_DEST, these other cases can't apply. */
3259 /* Changing mode twice with SUBREG => just change it once,
3260 or not at all if changing back to starting mode. */
3261 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3263 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3264 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3265 return SUBREG_REG (SUBREG_REG (x));
3267 SUBST_INT (SUBREG_WORD (x),
3268 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3269 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3272 /* SUBREG of a hard register => just change the register number
3273 and/or mode. If the hard register is not valid in that mode,
3274 suppress this combination. If the hard register is the stack,
3275 frame, or argument pointer, leave this as a SUBREG. */
3277 if (GET_CODE (SUBREG_REG (x)) == REG
3278 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3279 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3280 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3281 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3283 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3284 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3286 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3288 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3290 return gen_rtx (REG, mode,
3291 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3293 return gen_rtx (CLOBBER, mode, const0_rtx);
3296 /* For a constant, try to pick up the part we want. Handle a full
3297 word and low-order part. Only do this if we are narrowing
3298 the constant; if it is being widened, we have no idea what
3299 the extra bits will have been set to. */
3301 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3302 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3303 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3304 && GET_MODE_CLASS (mode) == MODE_INT)
3306 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3312 /* If we want a subreg of a constant, at offset 0,
3313 take the low bits. On a little-endian machine, that's
3314 always valid. On a big-endian machine, it's valid
3315 only if the constant's mode fits in one word. */
3316 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3317 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3318 && (! WORDS_BIG_ENDIAN
3319 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3320 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3322 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3323 since we are saying that the high bits don't matter. */
3324 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3325 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3326 return SUBREG_REG (x);
3328 /* Note that we cannot do any narrowing for non-constants since
3329 we might have been counting on using the fact that some bits were
3330 zero. We now do this in the SET. */
3335 /* (not (plus X -1)) can become (neg X). */
3336 if (GET_CODE (XEXP (x, 0)) == PLUS
3337 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3338 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3340 /* Similarly, (not (neg X)) is (plus X -1). */
3341 if (GET_CODE (XEXP (x, 0)) == NEG)
3342 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3345 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3346 if (GET_CODE (XEXP (x, 0)) == XOR
3347 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3348 && (temp = simplify_unary_operation (NOT, mode,
3349 XEXP (XEXP (x, 0), 1),
3351 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3353 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3354 other than 1, but that is not valid. We could do a similar
3355 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3356 but this doesn't seem common enough to bother with. */
3357 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3358 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3359 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3360 XEXP (XEXP (x, 0), 1));
3362 if (GET_CODE (XEXP (x, 0)) == SUBREG
3363 && subreg_lowpart_p (XEXP (x, 0))
3364 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3365 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3366 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3367 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3369 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3371 x = gen_rtx (ROTATE, inner_mode,
3372 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3373 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3374 return gen_lowpart_for_combine (mode, x);
3377 #if STORE_FLAG_VALUE == -1
3378 /* (not (comparison foo bar)) can be done by reversing the comparison
3380 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3381 && reversible_comparison_p (XEXP (x, 0)))
3382 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3383 mode, XEXP (XEXP (x, 0), 0),
3384 XEXP (XEXP (x, 0), 1));
3386 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3387 is (lt foo (const_int 0)), so we can perform the above
3390 if (XEXP (x, 1) == const1_rtx
3391 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3392 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3393 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3394 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3397 /* Apply De Morgan's laws to reduce number of patterns for machines
3398 with negating logical insns (and-not, nand, etc.). If result has
3399 only one NOT, put it first, since that is how the patterns are
3402 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3404 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3406 if (GET_CODE (in1) == NOT)
3407 in1 = XEXP (in1, 0);
3409 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3411 if (GET_CODE (in2) == NOT)
3412 in2 = XEXP (in2, 0);
3413 else if (GET_CODE (in2) == CONST_INT
3414 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3415 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3417 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3419 if (GET_CODE (in2) == NOT)
3422 in2 = in1; in1 = tem;
3425 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3431 /* (neg (plus X 1)) can become (not X). */
3432 if (GET_CODE (XEXP (x, 0)) == PLUS
3433 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3434 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3436 /* Similarly, (neg (not X)) is (plus X 1). */
3437 if (GET_CODE (XEXP (x, 0)) == NOT)
3438 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3440 /* (neg (minus X Y)) can become (minus Y X). */
3441 if (GET_CODE (XEXP (x, 0)) == MINUS
3442 && (! FLOAT_MODE_P (mode)
3443 /* x-y != -(y-x) with IEEE floating point. */
3444 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3446 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3447 XEXP (XEXP (x, 0), 0));
3449 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3450 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3451 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3452 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3454 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3455 if we can then eliminate the NEG (e.g.,
3456 if the operand is a constant). */
3458 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3460 temp = simplify_unary_operation (NEG, mode,
3461 XEXP (XEXP (x, 0), 0), mode);
3464 SUBST (XEXP (XEXP (x, 0), 0), temp);
3469 temp = expand_compound_operation (XEXP (x, 0));
3471 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3472 replaced by (lshiftrt X C). This will convert
3473 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3475 if (GET_CODE (temp) == ASHIFTRT
3476 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3477 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3478 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3479 INTVAL (XEXP (temp, 1)));
3481 /* If X has only a single bit that might be nonzero, say, bit I, convert
3482 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3483 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3484 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3485 or a SUBREG of one since we'd be making the expression more
3486 complex if it was just a register. */
3488 if (GET_CODE (temp) != REG
3489 && ! (GET_CODE (temp) == SUBREG
3490 && GET_CODE (SUBREG_REG (temp)) == REG)
3491 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3493 rtx temp1 = simplify_shift_const
3494 (NULL_RTX, ASHIFTRT, mode,
3495 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3496 GET_MODE_BITSIZE (mode) - 1 - i),
3497 GET_MODE_BITSIZE (mode) - 1 - i);
3499 /* If all we did was surround TEMP with the two shifts, we
3500 haven't improved anything, so don't use it. Otherwise,
3501 we are better off with TEMP1. */
3502 if (GET_CODE (temp1) != ASHIFTRT
3503 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3504 || XEXP (XEXP (temp1, 0), 0) != temp)
3510 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3512 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3513 GET_MODE_MASK (mode), NULL_RTX, 0));
3516 case FLOAT_TRUNCATE:
3517 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3518 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3519 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3520 return XEXP (XEXP (x, 0), 0);
3522 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3523 (OP:SF foo:SF) if OP is NEG or ABS. */
3524 if ((GET_CODE (XEXP (x, 0)) == ABS
3525 || GET_CODE (XEXP (x, 0)) == NEG)
3526 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3527 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3528 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3529 XEXP (XEXP (XEXP (x, 0), 0), 0));
3531 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3532 is (float_truncate:SF x). */
3533 if (GET_CODE (XEXP (x, 0)) == SUBREG
3534 && subreg_lowpart_p (XEXP (x, 0))
3535 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3536 return SUBREG_REG (XEXP (x, 0));
3541 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3542 using cc0, in which case we want to leave it as a COMPARE
3543 so we can distinguish it from a register-register-copy. */
3544 if (XEXP (x, 1) == const0_rtx)
3547 /* In IEEE floating point, x-0 is not the same as x. */
3548 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3549 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3551 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3557 /* (const (const X)) can become (const X). Do it this way rather than
3558 returning the inner CONST since CONST can be shared with a
3560 if (GET_CODE (XEXP (x, 0)) == CONST)
3561 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3566 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3567 can add in an offset. find_split_point will split this address up
3568 again if it doesn't match. */
3569 if (GET_CODE (XEXP (x, 0)) == HIGH
3570 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3576 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3577 outermost. That's because that's the way indexed addresses are
3578 supposed to appear. This code used to check many more cases, but
3579 they are now checked elsewhere. */
3580 if (GET_CODE (XEXP (x, 0)) == PLUS
3581 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3582 return gen_binary (PLUS, mode,
3583 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3585 XEXP (XEXP (x, 0), 1));
3587 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3588 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3589 bit-field and can be replaced by either a sign_extend or a
3590 sign_extract. The `and' may be a zero_extend. */
3591 if (GET_CODE (XEXP (x, 0)) == XOR
3592 && GET_CODE (XEXP (x, 1)) == CONST_INT
3593 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3594 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3595 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3596 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3597 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3598 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3599 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3600 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3601 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3604 return simplify_shift_const
3605 (NULL_RTX, ASHIFTRT, mode,
3606 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3607 XEXP (XEXP (XEXP (x, 0), 0), 0),
3608 GET_MODE_BITSIZE (mode) - (i + 1)),
3609 GET_MODE_BITSIZE (mode) - (i + 1));
3611 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3612 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3613 is 1. This produces better code than the alternative immediately
3615 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3616 && reversible_comparison_p (XEXP (x, 0))
3617 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3618 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3620 gen_unary (NEG, mode, mode,
3621 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3622 mode, XEXP (XEXP (x, 0), 0),
3623 XEXP (XEXP (x, 0), 1)));
3625 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3626 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3627 the bitsize of the mode - 1. This allows simplification of
3628 "a = (b & 8) == 0;" */
3629 if (XEXP (x, 1) == constm1_rtx
3630 && GET_CODE (XEXP (x, 0)) != REG
3631 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3633 && nonzero_bits (XEXP (x, 0), mode) == 1)
3634 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3635 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3636 gen_rtx_combine (XOR, mode,
3637 XEXP (x, 0), const1_rtx),
3638 GET_MODE_BITSIZE (mode) - 1),
3639 GET_MODE_BITSIZE (mode) - 1);
3641 /* If we are adding two things that have no bits in common, convert
3642 the addition into an IOR. This will often be further simplified,
3643 for example in cases like ((a & 1) + (a & 2)), which can
3646 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3647 && (nonzero_bits (XEXP (x, 0), mode)
3648 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3649 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3653 #if STORE_FLAG_VALUE == 1
3654 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3656 if (XEXP (x, 0) == const1_rtx
3657 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3658 && reversible_comparison_p (XEXP (x, 1)))
3659 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3660 mode, XEXP (XEXP (x, 1), 0),
3661 XEXP (XEXP (x, 1), 1));
3664 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3665 (and <foo> (const_int pow2-1)) */
3666 if (GET_CODE (XEXP (x, 1)) == AND
3667 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3668 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3669 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3670 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3671 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3673 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3675 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3676 return gen_binary (MINUS, mode,
3677 gen_binary (MINUS, mode, XEXP (x, 0),
3678 XEXP (XEXP (x, 1), 0)),
3679 XEXP (XEXP (x, 1), 1));
3683 /* If we have (mult (plus A B) C), apply the distributive law and then
3684 the inverse distributive law to see if things simplify. This
3685 occurs mostly in addresses, often when unrolling loops. */
3687 if (GET_CODE (XEXP (x, 0)) == PLUS)
3689 x = apply_distributive_law
3690 (gen_binary (PLUS, mode,
3691 gen_binary (MULT, mode,
3692 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3693 gen_binary (MULT, mode,
3694 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3696 if (GET_CODE (x) != MULT)
3702 /* If this is a divide by a power of two, treat it as a shift if
3703 its first operand is a shift. */
3704 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3705 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3706 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3707 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3708 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3709 || GET_CODE (XEXP (x, 0)) == ROTATE
3710 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3711 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3715 case GT: case GTU: case GE: case GEU:
3716 case LT: case LTU: case LE: case LEU:
3717 /* If the first operand is a condition code, we can't do anything
3719 if (GET_CODE (XEXP (x, 0)) == COMPARE
3720 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3722 && XEXP (x, 0) != cc0_rtx
3726 rtx op0 = XEXP (x, 0);
3727 rtx op1 = XEXP (x, 1);
3728 enum rtx_code new_code;
3730 if (GET_CODE (op0) == COMPARE)
3731 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3733 /* Simplify our comparison, if possible. */
3734 new_code = simplify_comparison (code, &op0, &op1);
3736 #if STORE_FLAG_VALUE == 1
3737 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3738 if only the low-order bit is possibly nonzero in X (such as when
3739 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3740 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3741 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3744 Remove any ZERO_EXTRACT we made when thinking this was a
3745 comparison. It may now be simpler to use, e.g., an AND. If a
3746 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3747 the call to make_compound_operation in the SET case. */
3749 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3750 && op1 == const0_rtx
3751 && nonzero_bits (op0, mode) == 1)
3752 return gen_lowpart_for_combine (mode,
3753 expand_compound_operation (op0));
3755 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3756 && op1 == const0_rtx
3757 && (num_sign_bit_copies (op0, mode)
3758 == GET_MODE_BITSIZE (mode)))
3760 op0 = expand_compound_operation (op0);
3761 return gen_unary (NEG, mode, mode,
3762 gen_lowpart_for_combine (mode, op0));
3765 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3766 && op1 == const0_rtx
3767 && nonzero_bits (op0, mode) == 1)
3769 op0 = expand_compound_operation (op0);
3770 return gen_binary (XOR, mode,
3771 gen_lowpart_for_combine (mode, op0),
3775 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3776 && op1 == const0_rtx
3777 && (num_sign_bit_copies (op0, mode)
3778 == GET_MODE_BITSIZE (mode)))
3780 op0 = expand_compound_operation (op0);
3781 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3785 #if STORE_FLAG_VALUE == -1
3786 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3788 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3789 && op1 == const0_rtx
3790 && (num_sign_bit_copies (op0, mode)
3791 == GET_MODE_BITSIZE (mode)))
3792 return gen_lowpart_for_combine (mode,
3793 expand_compound_operation (op0));
3795 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3796 && op1 == const0_rtx
3797 && nonzero_bits (op0, mode) == 1)
3799 op0 = expand_compound_operation (op0);
3800 return gen_unary (NEG, mode, mode,
3801 gen_lowpart_for_combine (mode, op0));
3804 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3805 && op1 == const0_rtx
3806 && (num_sign_bit_copies (op0, mode)
3807 == GET_MODE_BITSIZE (mode)))
3809 op0 = expand_compound_operation (op0);
3810 return gen_unary (NOT, mode, mode,
3811 gen_lowpart_for_combine (mode, op0));
3814 /* If X is 0/1, (eq X 0) is X-1. */
3815 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3816 && op1 == const0_rtx
3817 && nonzero_bits (op0, mode) == 1)
3819 op0 = expand_compound_operation (op0);
3820 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3824 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3825 one bit that might be nonzero, we can convert (ne x 0) to
3826 (ashift x c) where C puts the bit in the sign bit. Remove any
3827 AND with STORE_FLAG_VALUE when we are done, since we are only
3828 going to test the sign bit. */
3829 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3830 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3831 && (STORE_FLAG_VALUE
3832 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3833 && op1 == const0_rtx
3834 && mode == GET_MODE (op0)
3835 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3837 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3838 expand_compound_operation (op0),
3839 GET_MODE_BITSIZE (mode) - 1 - i);
3840 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3846 /* If the code changed, return a whole new comparison. */
3847 if (new_code != code)
3848 return gen_rtx_combine (new_code, mode, op0, op1);
3850 /* Otherwise, keep this operation, but maybe change its operands.
3851 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3852 SUBST (XEXP (x, 0), op0);
3853 SUBST (XEXP (x, 1), op1);
3858 return simplify_if_then_else (x);
3864 /* If we are processing SET_DEST, we are done. */
3868 return expand_compound_operation (x);
3871 return simplify_set (x);
3876 return simplify_logical (x, last);
3879 /* (abs (neg <foo>)) -> (abs <foo>) */
3880 if (GET_CODE (XEXP (x, 0)) == NEG)
3881 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3883 /* If operand is something known to be positive, ignore the ABS. */
3884 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3885 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3886 <= HOST_BITS_PER_WIDE_INT)
3887 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3888 & ((HOST_WIDE_INT) 1
3889 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3894 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3895 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
3896 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
3901 /* (ffs (*_extend <X>)) = (ffs <X>) */
3902 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3903 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3904 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3908 /* (float (sign_extend <X>)) = (float <X>). */
3909 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3910 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3918 /* If this is a shift by a constant amount, simplify it. */
3919 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3920 return simplify_shift_const (x, code, mode, XEXP (x, 0),
3921 INTVAL (XEXP (x, 1)));
3923 #ifdef SHIFT_COUNT_TRUNCATED
3924 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
3926 force_to_mode (XEXP (x, 1), GET_MODE (x),
3928 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
3939 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3942 simplify_if_then_else (x)
3945 enum machine_mode mode = GET_MODE (x);
3946 rtx cond = XEXP (x, 0);
3947 rtx true = XEXP (x, 1);
3948 rtx false = XEXP (x, 2);
3949 enum rtx_code true_code = GET_CODE (cond);
3950 int comparison_p = GET_RTX_CLASS (true_code) == '<';
3954 /* Simplify storing of the truth value. */
3955 if (comparison_p && true == const_true_rtx && false == const0_rtx)
3956 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
3958 /* Also when the truth value has to be reversed. */
3959 if (comparison_p && reversible_comparison_p (cond)
3960 && true == const0_rtx && false == const_true_rtx)
3961 return gen_binary (reverse_condition (true_code),
3962 mode, XEXP (cond, 0), XEXP (cond, 1));
3964 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3965 in it is being compared against certain values. Get the true and false
3966 comparisons and see if that says anything about the value of each arm. */
3968 if (comparison_p && reversible_comparison_p (cond)
3969 && GET_CODE (XEXP (cond, 0)) == REG)
3972 rtx from = XEXP (cond, 0);
3973 enum rtx_code false_code = reverse_condition (true_code);
3974 rtx true_val = XEXP (cond, 1);
3975 rtx false_val = true_val;
3978 /* If FALSE_CODE is EQ, swap the codes and arms. */
3980 if (false_code == EQ)
3982 swapped = 1, true_code = EQ, false_code = NE;
3983 temp = true, true = false, false = temp;
3986 /* If we are comparing against zero and the expression being tested has
3987 only a single bit that might be nonzero, that is its value when it is
3988 not equal to zero. Similarly if it is known to be -1 or 0. */
3990 if (true_code == EQ && true_val == const0_rtx
3991 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3992 false_code = EQ, false_val = GEN_INT (nzb);
3993 else if (true_code == EQ && true_val == const0_rtx
3994 && (num_sign_bit_copies (from, GET_MODE (from))
3995 == GET_MODE_BITSIZE (GET_MODE (from))))
3996 false_code = EQ, false_val = constm1_rtx;
3998 /* Now simplify an arm if we know the value of the register in the
3999 branch and it is used in the arm. Be careful due to the potential
4000 of locally-shared RTL. */
4002 if (reg_mentioned_p (from, true))
4003 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4004 pc_rtx, pc_rtx, 0, 0);
4005 if (reg_mentioned_p (from, false))
4006 false = subst (known_cond (copy_rtx (false), false_code,
4008 pc_rtx, pc_rtx, 0, 0);
4010 SUBST (XEXP (x, 1), swapped ? false : true);
4011 SUBST (XEXP (x, 2), swapped ? true : false);
4013 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4016 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4017 reversed, do so to avoid needing two sets of patterns for
4018 subtract-and-branch insns. Similarly if we have a constant in the true
4019 arm, the false arm is the same as the first operand of the comparison, or
4020 the false arm is more complicated than the true arm. */
4022 if (comparison_p && reversible_comparison_p (cond)
4024 || (CONSTANT_P (true)
4025 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4026 || true == const0_rtx
4027 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4028 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4029 || (GET_CODE (true) == SUBREG
4030 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4031 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4032 || reg_mentioned_p (true, false)
4033 || rtx_equal_p (false, XEXP (cond, 0))))
4035 true_code = reverse_condition (true_code);
4037 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4040 SUBST (XEXP (x, 1), false);
4041 SUBST (XEXP (x, 2), true);
4043 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4045 /* It is possible that the conditional has been simplified out. */
4046 true_code = GET_CODE (cond);
4047 comparison_p = GET_RTX_CLASS (true_code) == '<';
4050 /* If the two arms are identical, we don't need the comparison. */
4052 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4055 /* Convert a == b ? b : a to "a". */
4056 if (true_code == EQ && ! side_effects_p (cond)
4057 && rtx_equal_p (XEXP (cond, 0), false)
4058 && rtx_equal_p (XEXP (cond, 1), true))
4060 else if (true_code == NE && ! side_effects_p (cond)
4061 && rtx_equal_p (XEXP (cond, 0), true)
4062 && rtx_equal_p (XEXP (cond, 1), false))
4065 /* Look for cases where we have (abs x) or (neg (abs X)). */
4067 if (GET_MODE_CLASS (mode) == MODE_INT
4068 && GET_CODE (false) == NEG
4069 && rtx_equal_p (true, XEXP (false, 0))
4071 && rtx_equal_p (true, XEXP (cond, 0))
4072 && ! side_effects_p (true))
4077 return gen_unary (ABS, mode, mode, true);
4080 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4083 /* Look for MIN or MAX. */
4085 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4087 && rtx_equal_p (XEXP (cond, 0), true)
4088 && rtx_equal_p (XEXP (cond, 1), false)
4089 && ! side_effects_p (cond))
4094 return gen_binary (SMAX, mode, true, false);
4097 return gen_binary (SMIN, mode, true, false);
4100 return gen_binary (UMAX, mode, true, false);
4103 return gen_binary (UMIN, mode, true, false);
4106 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4108 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4109 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4110 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4111 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4112 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4113 neither of the above, but it isn't worth checking for. */
4115 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4117 rtx t = make_compound_operation (true, SET);
4118 rtx f = make_compound_operation (false, SET);
4119 rtx cond_op0 = XEXP (cond, 0);
4120 rtx cond_op1 = XEXP (cond, 1);
4121 enum rtx_code op, extend_op = NIL;
4122 enum machine_mode m = mode;
4125 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4126 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4127 || GET_CODE (t) == ASHIFT
4128 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4129 && rtx_equal_p (XEXP (t, 0), f))
4130 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4132 /* If an identity-zero op is commutative, check whether there
4133 would be a match if we swapped the operands. */
4134 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4135 || GET_CODE (t) == XOR)
4136 && rtx_equal_p (XEXP (t, 1), f))
4137 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4138 else if (GET_CODE (t) == SIGN_EXTEND
4139 && (GET_CODE (XEXP (t, 0)) == PLUS
4140 || GET_CODE (XEXP (t, 0)) == MINUS
4141 || GET_CODE (XEXP (t, 0)) == IOR
4142 || GET_CODE (XEXP (t, 0)) == XOR
4143 || GET_CODE (XEXP (t, 0)) == ASHIFT
4144 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4145 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4146 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4147 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4148 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4149 && (num_sign_bit_copies (f, GET_MODE (f))
4150 > (GET_MODE_BITSIZE (mode)
4151 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4153 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4154 extend_op = SIGN_EXTEND;
4155 m = GET_MODE (XEXP (t, 0));
4157 else if (GET_CODE (t) == SIGN_EXTEND
4158 && (GET_CODE (XEXP (t, 0)) == PLUS
4159 || GET_CODE (XEXP (t, 0)) == IOR
4160 || GET_CODE (XEXP (t, 0)) == XOR)
4161 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4162 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4163 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4164 && (num_sign_bit_copies (f, GET_MODE (f))
4165 > (GET_MODE_BITSIZE (mode)
4166 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4168 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4169 extend_op = SIGN_EXTEND;
4170 m = GET_MODE (XEXP (t, 0));
4172 else if (GET_CODE (t) == ZERO_EXTEND
4173 && (GET_CODE (XEXP (t, 0)) == PLUS
4174 || GET_CODE (XEXP (t, 0)) == MINUS
4175 || GET_CODE (XEXP (t, 0)) == IOR
4176 || GET_CODE (XEXP (t, 0)) == XOR
4177 || GET_CODE (XEXP (t, 0)) == ASHIFT
4178 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4179 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4180 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4181 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4182 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4183 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4184 && ((nonzero_bits (f, GET_MODE (f))
4185 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4188 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4189 extend_op = ZERO_EXTEND;
4190 m = GET_MODE (XEXP (t, 0));
4192 else if (GET_CODE (t) == ZERO_EXTEND
4193 && (GET_CODE (XEXP (t, 0)) == PLUS
4194 || GET_CODE (XEXP (t, 0)) == IOR
4195 || GET_CODE (XEXP (t, 0)) == XOR)
4196 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4197 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4198 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4199 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4200 && ((nonzero_bits (f, GET_MODE (f))
4201 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4204 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4205 extend_op = ZERO_EXTEND;
4206 m = GET_MODE (XEXP (t, 0));
4211 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4212 pc_rtx, pc_rtx, 0, 0);
4213 temp = gen_binary (MULT, m, temp,
4214 gen_binary (MULT, m, c1, const_true_rtx));
4215 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4216 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4218 if (extend_op != NIL)
4219 temp = gen_unary (extend_op, mode, m, temp);
4226 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4227 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4228 negation of a single bit, we can convert this operation to a shift. We
4229 can actually do this more generally, but it doesn't seem worth it. */
4231 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4232 && false == const0_rtx && GET_CODE (true) == CONST_INT
4233 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4234 && (i = exact_log2 (INTVAL (true))) >= 0)
4235 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4236 == GET_MODE_BITSIZE (mode))
4237 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4239 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4240 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4245 /* Simplify X, a SET expression. Return the new expression. */
4251 rtx src = SET_SRC (x);
4252 rtx dest = SET_DEST (x);
4253 enum machine_mode mode
4254 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4258 /* (set (pc) (return)) gets written as (return). */
4259 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4262 /* Now that we know for sure which bits of SRC we are using, see if we can
4263 simplify the expression for the object knowing that we only need the
4266 if (GET_MODE_CLASS (mode) == MODE_INT)
4267 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4269 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4270 the comparison result and try to simplify it unless we already have used
4271 undobuf.other_insn. */
4272 if ((GET_CODE (src) == COMPARE
4277 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4278 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4279 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4280 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4282 enum rtx_code old_code = GET_CODE (*cc_use);
4283 enum rtx_code new_code;
4285 int other_changed = 0;
4286 enum machine_mode compare_mode = GET_MODE (dest);
4288 if (GET_CODE (src) == COMPARE)
4289 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4291 op0 = src, op1 = const0_rtx;
4293 /* Simplify our comparison, if possible. */
4294 new_code = simplify_comparison (old_code, &op0, &op1);
4296 #ifdef EXTRA_CC_MODES
4297 /* If this machine has CC modes other than CCmode, check to see if we
4298 need to use a different CC mode here. */
4299 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4300 #endif /* EXTRA_CC_MODES */
4302 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4303 /* If the mode changed, we have to change SET_DEST, the mode in the
4304 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4305 a hard register, just build new versions with the proper mode. If it
4306 is a pseudo, we lose unless it is only time we set the pseudo, in
4307 which case we can safely change its mode. */
4308 if (compare_mode != GET_MODE (dest))
4310 int regno = REGNO (dest);
4311 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4313 if (regno < FIRST_PSEUDO_REGISTER
4314 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4316 if (regno >= FIRST_PSEUDO_REGISTER)
4317 SUBST (regno_reg_rtx[regno], new_dest);
4319 SUBST (SET_DEST (x), new_dest);
4320 SUBST (XEXP (*cc_use, 0), new_dest);
4328 /* If the code changed, we have to build a new comparison in
4329 undobuf.other_insn. */
4330 if (new_code != old_code)
4332 unsigned HOST_WIDE_INT mask;
4334 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4337 /* If the only change we made was to change an EQ into an NE or
4338 vice versa, OP0 has only one bit that might be nonzero, and OP1
4339 is zero, check if changing the user of the condition code will
4340 produce a valid insn. If it won't, we can keep the original code
4341 in that insn by surrounding our operation with an XOR. */
4343 if (((old_code == NE && new_code == EQ)
4344 || (old_code == EQ && new_code == NE))
4345 && ! other_changed && op1 == const0_rtx
4346 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4347 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4349 rtx pat = PATTERN (other_insn), note = 0;
4352 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4353 && ! check_asm_operands (pat)))
4355 PUT_CODE (*cc_use, old_code);
4358 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4366 undobuf.other_insn = other_insn;
4369 /* If we are now comparing against zero, change our source if
4370 needed. If we do not use cc0, we always have a COMPARE. */
4371 if (op1 == const0_rtx && dest == cc0_rtx)
4373 SUBST (SET_SRC (x), op0);
4379 /* Otherwise, if we didn't previously have a COMPARE in the
4380 correct mode, we need one. */
4381 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4384 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4389 /* Otherwise, update the COMPARE if needed. */
4390 SUBST (XEXP (src, 0), op0);
4391 SUBST (XEXP (src, 1), op1);
4396 /* Get SET_SRC in a form where we have placed back any
4397 compound expressions. Then do the checks below. */
4398 src = make_compound_operation (src, SET);
4399 SUBST (SET_SRC (x), src);
4402 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4403 and X being a REG or (subreg (reg)), we may be able to convert this to
4404 (set (subreg:m2 x) (op)).
4406 We can always do this if M1 is narrower than M2 because that means that
4407 we only care about the low bits of the result.
4409 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4410 perform a narrower operation that requested since the high-order bits will
4411 be undefined. On machine where it is defined, this transformation is safe
4412 as long as M1 and M2 have the same number of words. */
4414 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4415 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4416 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4418 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4419 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4420 #ifndef WORD_REGISTER_OPERATIONS
4421 && (GET_MODE_SIZE (GET_MODE (src))
4422 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4424 #ifdef CLASS_CANNOT_CHANGE_SIZE
4425 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4426 && (TEST_HARD_REG_BIT
4427 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4429 && (GET_MODE_SIZE (GET_MODE (src))
4430 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4432 && (GET_CODE (dest) == REG
4433 || (GET_CODE (dest) == SUBREG
4434 && GET_CODE (SUBREG_REG (dest)) == REG)))
4436 SUBST (SET_DEST (x),
4437 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4439 SUBST (SET_SRC (x), SUBREG_REG (src));
4441 src = SET_SRC (x), dest = SET_DEST (x);
4444 #ifdef LOAD_EXTEND_OP
4445 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4446 would require a paradoxical subreg. Replace the subreg with a
4447 zero_extend to avoid the reload that would otherwise be required. */
4449 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4450 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4451 && SUBREG_WORD (src) == 0
4452 && (GET_MODE_SIZE (GET_MODE (src))
4453 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4454 && GET_CODE (SUBREG_REG (src)) == MEM)
4457 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4458 GET_MODE (src), XEXP (src, 0)));
4464 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4465 are comparing an item known to be 0 or -1 against 0, use a logical
4466 operation instead. Check for one of the arms being an IOR of the other
4467 arm with some value. We compute three terms to be IOR'ed together. In
4468 practice, at most two will be nonzero. Then we do the IOR's. */
4470 if (GET_CODE (dest) != PC
4471 && GET_CODE (src) == IF_THEN_ELSE
4472 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4473 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4474 && XEXP (XEXP (src, 0), 1) == const0_rtx
4475 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4476 #ifdef HAVE_conditional_move
4477 && ! can_conditionally_move_p (GET_MODE (src))
4479 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4480 GET_MODE (XEXP (XEXP (src, 0), 0)))
4481 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4482 && ! side_effects_p (src))
4484 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4485 ? XEXP (src, 1) : XEXP (src, 2));
4486 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4487 ? XEXP (src, 2) : XEXP (src, 1));
4488 rtx term1 = const0_rtx, term2, term3;
4490 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4491 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4492 else if (GET_CODE (true) == IOR
4493 && rtx_equal_p (XEXP (true, 1), false))
4494 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4495 else if (GET_CODE (false) == IOR
4496 && rtx_equal_p (XEXP (false, 0), true))
4497 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4498 else if (GET_CODE (false) == IOR
4499 && rtx_equal_p (XEXP (false, 1), true))
4500 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4502 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4503 term3 = gen_binary (AND, GET_MODE (src),
4504 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4505 XEXP (XEXP (src, 0), 0)),
4509 gen_binary (IOR, GET_MODE (src),
4510 gen_binary (IOR, GET_MODE (src), term1, term2),
4516 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4517 whole thing fail. */
4518 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4520 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4523 /* Convert this into a field assignment operation, if possible. */
4524 return make_field_assignment (x);
4527 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4528 result. LAST is nonzero if this is the last retry. */
4531 simplify_logical (x, last)
4535 enum machine_mode mode = GET_MODE (x);
4536 rtx op0 = XEXP (x, 0);
4537 rtx op1 = XEXP (x, 1);
4539 switch (GET_CODE (x))
4542 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4543 insn (and may simplify more). */
4544 if (GET_CODE (op0) == XOR
4545 && rtx_equal_p (XEXP (op0, 0), op1)
4546 && ! side_effects_p (op1))
4547 x = gen_binary (AND, mode,
4548 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4550 if (GET_CODE (op0) == XOR
4551 && rtx_equal_p (XEXP (op0, 1), op1)
4552 && ! side_effects_p (op1))
4553 x = gen_binary (AND, mode,
4554 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4556 /* Similarly for (~ (A ^ B)) & A. */
4557 if (GET_CODE (op0) == NOT
4558 && GET_CODE (XEXP (op0, 0)) == XOR
4559 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4560 && ! side_effects_p (op1))
4561 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4563 if (GET_CODE (op0) == NOT
4564 && GET_CODE (XEXP (op0, 0)) == XOR
4565 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4566 && ! side_effects_p (op1))
4567 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4569 if (GET_CODE (op1) == CONST_INT)
4571 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4573 /* If we have (ior (and (X C1) C2)) and the next restart would be
4574 the last, simplify this by making C1 as small as possible
4577 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4578 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4579 && GET_CODE (op1) == CONST_INT)
4580 return gen_binary (IOR, mode,
4581 gen_binary (AND, mode, XEXP (op0, 0),
4582 GEN_INT (INTVAL (XEXP (op0, 1))
4583 & ~ INTVAL (op1))), op1);
4585 if (GET_CODE (x) != AND)
4588 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4589 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4590 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4593 /* Convert (A | B) & A to A. */
4594 if (GET_CODE (op0) == IOR
4595 && (rtx_equal_p (XEXP (op0, 0), op1)
4596 || rtx_equal_p (XEXP (op0, 1), op1))
4597 && ! side_effects_p (XEXP (op0, 0))
4598 && ! side_effects_p (XEXP (op0, 1)))
4601 /* In the following group of tests (and those in case IOR below),
4602 we start with some combination of logical operations and apply
4603 the distributive law followed by the inverse distributive law.
4604 Most of the time, this results in no change. However, if some of
4605 the operands are the same or inverses of each other, simplifications
4608 For example, (and (ior A B) (not B)) can occur as the result of
4609 expanding a bit field assignment. When we apply the distributive
4610 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4611 which then simplifies to (and (A (not B))).
4613 If we have (and (ior A B) C), apply the distributive law and then
4614 the inverse distributive law to see if things simplify. */
4616 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4618 x = apply_distributive_law
4619 (gen_binary (GET_CODE (op0), mode,
4620 gen_binary (AND, mode, XEXP (op0, 0), op1),
4621 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4622 if (GET_CODE (x) != AND)
4626 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4627 return apply_distributive_law
4628 (gen_binary (GET_CODE (op1), mode,
4629 gen_binary (AND, mode, XEXP (op1, 0), op0),
4630 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4632 /* Similarly, taking advantage of the fact that
4633 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4635 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4636 return apply_distributive_law
4637 (gen_binary (XOR, mode,
4638 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4639 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4641 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4642 return apply_distributive_law
4643 (gen_binary (XOR, mode,
4644 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4645 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4649 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4650 if (GET_CODE (op1) == CONST_INT
4651 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4652 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4655 /* Convert (A & B) | A to A. */
4656 if (GET_CODE (op0) == AND
4657 && (rtx_equal_p (XEXP (op0, 0), op1)
4658 || rtx_equal_p (XEXP (op0, 1), op1))
4659 && ! side_effects_p (XEXP (op0, 0))
4660 && ! side_effects_p (XEXP (op0, 1)))
4663 /* If we have (ior (and A B) C), apply the distributive law and then
4664 the inverse distributive law to see if things simplify. */
4666 if (GET_CODE (op0) == AND)
4668 x = apply_distributive_law
4669 (gen_binary (AND, mode,
4670 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4671 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4673 if (GET_CODE (x) != IOR)
4677 if (GET_CODE (op1) == AND)
4679 x = apply_distributive_law
4680 (gen_binary (AND, mode,
4681 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4682 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4684 if (GET_CODE (x) != IOR)
4688 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4689 mode size to (rotate A CX). */
4691 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4692 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4693 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4694 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4695 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4696 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4697 == GET_MODE_BITSIZE (mode)))
4698 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4699 (GET_CODE (op0) == ASHIFT
4700 ? XEXP (op0, 1) : XEXP (op1, 1)));
4702 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4703 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4704 does not affect any of the bits in OP1, it can really be done
4705 as a PLUS and we can associate. We do this by seeing if OP1
4706 can be safely shifted left C bits. */
4707 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4708 && GET_CODE (XEXP (op0, 0)) == PLUS
4709 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4710 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4711 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4713 int count = INTVAL (XEXP (op0, 1));
4714 HOST_WIDE_INT mask = INTVAL (op1) << count;
4716 if (mask >> count == INTVAL (op1)
4717 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4719 SUBST (XEXP (XEXP (op0, 0), 1),
4720 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4727 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4728 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4731 int num_negated = 0;
4733 if (GET_CODE (op0) == NOT)
4734 num_negated++, op0 = XEXP (op0, 0);
4735 if (GET_CODE (op1) == NOT)
4736 num_negated++, op1 = XEXP (op1, 0);
4738 if (num_negated == 2)
4740 SUBST (XEXP (x, 0), op0);
4741 SUBST (XEXP (x, 1), op1);
4743 else if (num_negated == 1)
4744 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4747 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4748 correspond to a machine insn or result in further simplifications
4749 if B is a constant. */
4751 if (GET_CODE (op0) == AND
4752 && rtx_equal_p (XEXP (op0, 1), op1)
4753 && ! side_effects_p (op1))
4754 return gen_binary (AND, mode,
4755 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4758 else if (GET_CODE (op0) == AND
4759 && rtx_equal_p (XEXP (op0, 0), op1)
4760 && ! side_effects_p (op1))
4761 return gen_binary (AND, mode,
4762 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4765 #if STORE_FLAG_VALUE == 1
4766 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4768 if (op1 == const1_rtx
4769 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4770 && reversible_comparison_p (op0))
4771 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4772 mode, XEXP (op0, 0), XEXP (op0, 1));
4774 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4775 is (lt foo (const_int 0)), so we can perform the above
4778 if (op1 == const1_rtx
4779 && GET_CODE (op0) == LSHIFTRT
4780 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4781 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4782 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4785 /* (xor (comparison foo bar) (const_int sign-bit))
4786 when STORE_FLAG_VALUE is the sign bit. */
4787 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4788 && (STORE_FLAG_VALUE
4789 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4790 && op1 == const_true_rtx
4791 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4792 && reversible_comparison_p (op0))
4793 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4794 mode, XEXP (op0, 0), XEXP (op0, 1));
4801 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4802 operations" because they can be replaced with two more basic operations.
4803 ZERO_EXTEND is also considered "compound" because it can be replaced with
4804 an AND operation, which is simpler, though only one operation.
4806 The function expand_compound_operation is called with an rtx expression
4807 and will convert it to the appropriate shifts and AND operations,
4808 simplifying at each stage.
4810 The function make_compound_operation is called to convert an expression
4811 consisting of shifts and ANDs into the equivalent compound expression.
4812 It is the inverse of this function, loosely speaking. */
4815 expand_compound_operation (x)
4823 switch (GET_CODE (x))
4828 /* We can't necessarily use a const_int for a multiword mode;
4829 it depends on implicitly extending the value.
4830 Since we don't know the right way to extend it,
4831 we can't tell whether the implicit way is right.
4833 Even for a mode that is no wider than a const_int,
4834 we can't win, because we need to sign extend one of its bits through
4835 the rest of it, and we don't know which bit. */
4836 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4839 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4840 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4841 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4842 reloaded. If not for that, MEM's would very rarely be safe.
4844 Reject MODEs bigger than a word, because we might not be able
4845 to reference a two-register group starting with an arbitrary register
4846 (and currently gen_lowpart might crash for a SUBREG). */
4848 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4851 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4852 /* If the inner object has VOIDmode (the only way this can happen
4853 is if it is a ASM_OPERANDS), we can't do anything since we don't
4854 know how much masking to do. */
4863 /* If the operand is a CLOBBER, just return it. */
4864 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4867 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4868 || GET_CODE (XEXP (x, 2)) != CONST_INT
4869 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4872 len = INTVAL (XEXP (x, 1));
4873 pos = INTVAL (XEXP (x, 2));
4875 /* If this goes outside the object being extracted, replace the object
4876 with a (use (mem ...)) construct that only combine understands
4877 and is used only for this purpose. */
4878 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4879 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4881 if (BITS_BIG_ENDIAN)
4882 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4890 /* If we reach here, we want to return a pair of shifts. The inner
4891 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4892 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4893 logical depending on the value of UNSIGNEDP.
4895 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4896 converted into an AND of a shift.
4898 We must check for the case where the left shift would have a negative
4899 count. This can happen in a case like (x >> 31) & 255 on machines
4900 that can't shift by a constant. On those machines, we would first
4901 combine the shift with the AND to produce a variable-position
4902 extraction. Then the constant of 31 would be substituted in to produce
4903 a such a position. */
4905 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4906 if (modewidth >= pos - len)
4907 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4909 simplify_shift_const (NULL_RTX, ASHIFT,
4912 modewidth - pos - len),
4915 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4916 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4917 simplify_shift_const (NULL_RTX, LSHIFTRT,
4920 ((HOST_WIDE_INT) 1 << len) - 1);
4922 /* Any other cases we can't handle. */
4926 /* If we couldn't do this for some reason, return the original
4928 if (GET_CODE (tem) == CLOBBER)
4934 /* X is a SET which contains an assignment of one object into
4935 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4936 or certain SUBREGS). If possible, convert it into a series of
4939 We half-heartedly support variable positions, but do not at all
4940 support variable lengths. */
4943 expand_field_assignment (x)
4947 rtx pos; /* Always counts from low bit. */
4950 enum machine_mode compute_mode;
4952 /* Loop until we find something we can't simplify. */
4955 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4956 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4958 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4959 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4960 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
4962 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4963 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4965 inner = XEXP (SET_DEST (x), 0);
4966 len = INTVAL (XEXP (SET_DEST (x), 1));
4967 pos = XEXP (SET_DEST (x), 2);
4969 /* If the position is constant and spans the width of INNER,
4970 surround INNER with a USE to indicate this. */
4971 if (GET_CODE (pos) == CONST_INT
4972 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4973 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4975 if (BITS_BIG_ENDIAN)
4977 if (GET_CODE (pos) == CONST_INT)
4978 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4980 else if (GET_CODE (pos) == MINUS
4981 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4982 && (INTVAL (XEXP (pos, 1))
4983 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4984 /* If position is ADJUST - X, new position is X. */
4985 pos = XEXP (pos, 0);
4987 pos = gen_binary (MINUS, GET_MODE (pos),
4988 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4994 /* A SUBREG between two modes that occupy the same numbers of words
4995 can be done by moving the SUBREG to the source. */
4996 else if (GET_CODE (SET_DEST (x)) == SUBREG
4997 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4998 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4999 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5000 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5002 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5003 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5010 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5011 inner = SUBREG_REG (inner);
5013 compute_mode = GET_MODE (inner);
5015 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5016 if (len < HOST_BITS_PER_WIDE_INT)
5017 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5021 /* Now compute the equivalent expression. Make a copy of INNER
5022 for the SET_DEST in case it is a MEM into which we will substitute;
5023 we don't want shared RTL in that case. */
5024 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5025 gen_binary (IOR, compute_mode,
5026 gen_binary (AND, compute_mode,
5027 gen_unary (NOT, compute_mode,
5033 gen_binary (ASHIFT, compute_mode,
5034 gen_binary (AND, compute_mode,
5035 gen_lowpart_for_combine
5045 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5046 it is an RTX that represents a variable starting position; otherwise,
5047 POS is the (constant) starting bit position (counted from the LSB).
5049 INNER may be a USE. This will occur when we started with a bitfield
5050 that went outside the boundary of the object in memory, which is
5051 allowed on most machines. To isolate this case, we produce a USE
5052 whose mode is wide enough and surround the MEM with it. The only
5053 code that understands the USE is this routine. If it is not removed,
5054 it will cause the resulting insn not to match.
5056 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5059 IN_DEST is non-zero if this is a reference in the destination of a
5060 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5061 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5064 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5065 ZERO_EXTRACT should be built even for bits starting at bit 0.
5067 MODE is the desired mode of the result (if IN_DEST == 0).
5069 The result is an RTX for the extraction or NULL_RTX if the target
5073 make_extraction (mode, inner, pos, pos_rtx, len,
5074 unsignedp, in_dest, in_compare)
5075 enum machine_mode mode;
5081 int in_dest, in_compare;
5083 /* This mode describes the size of the storage area
5084 to fetch the overall value from. Within that, we
5085 ignore the POS lowest bits, etc. */
5086 enum machine_mode is_mode = GET_MODE (inner);
5087 enum machine_mode inner_mode;
5088 enum machine_mode wanted_inner_mode = byte_mode;
5089 enum machine_mode wanted_inner_reg_mode = word_mode;
5090 enum machine_mode pos_mode = word_mode;
5091 enum machine_mode extraction_mode = word_mode;
5092 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5095 rtx orig_pos_rtx = pos_rtx;
5098 /* Get some information about INNER and get the innermost object. */
5099 if (GET_CODE (inner) == USE)
5100 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5101 /* We don't need to adjust the position because we set up the USE
5102 to pretend that it was a full-word object. */
5103 spans_byte = 1, inner = XEXP (inner, 0);
5104 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5106 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5107 consider just the QI as the memory to extract from.
5108 The subreg adds or removes high bits; its mode is
5109 irrelevant to the meaning of this extraction,
5110 since POS and LEN count from the lsb. */
5111 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5112 is_mode = GET_MODE (SUBREG_REG (inner));
5113 inner = SUBREG_REG (inner);
5116 inner_mode = GET_MODE (inner);
5118 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5119 pos = INTVAL (pos_rtx), pos_rtx = 0;
5121 /* See if this can be done without an extraction. We never can if the
5122 width of the field is not the same as that of some integer mode. For
5123 registers, we can only avoid the extraction if the position is at the
5124 low-order bit and this is either not in the destination or we have the
5125 appropriate STRICT_LOW_PART operation available.
5127 For MEM, we can avoid an extract if the field starts on an appropriate
5128 boundary and we can change the mode of the memory reference. However,
5129 we cannot directly access the MEM if we have a USE and the underlying
5130 MEM is not TMODE. This combination means that MEM was being used in a
5131 context where bits outside its mode were being referenced; that is only
5132 valid in bit-field insns. */
5134 if (tmode != BLKmode
5135 && ! (spans_byte && inner_mode != tmode)
5136 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5137 && GET_CODE (inner) != MEM
5139 || (GET_CODE (inner) == REG
5140 && (movstrict_optab->handlers[(int) tmode].insn_code
5141 != CODE_FOR_nothing))))
5142 || (GET_CODE (inner) == MEM && pos_rtx == 0
5144 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5145 : BITS_PER_UNIT)) == 0
5146 /* We can't do this if we are widening INNER_MODE (it
5147 may not be aligned, for one thing). */
5148 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5149 && (inner_mode == tmode
5150 || (! mode_dependent_address_p (XEXP (inner, 0))
5151 && ! MEM_VOLATILE_P (inner))))))
5153 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5154 field. If the original and current mode are the same, we need not
5155 adjust the offset. Otherwise, we do if bytes big endian.
5157 If INNER is not a MEM, get a piece consisting of just the field
5158 of interest (in this case POS % BITS_PER_WORD must be 0). */
5160 if (GET_CODE (inner) == MEM)
5163 /* POS counts from lsb, but make OFFSET count in memory order. */
5164 if (BYTES_BIG_ENDIAN)
5165 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5167 offset = pos / BITS_PER_UNIT;
5169 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5170 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5171 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5172 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5174 else if (GET_CODE (inner) == REG)
5176 /* We can't call gen_lowpart_for_combine here since we always want
5177 a SUBREG and it would sometimes return a new hard register. */
5178 if (tmode != inner_mode)
5179 new = gen_rtx (SUBREG, tmode, inner,
5181 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5182 ? (((GET_MODE_SIZE (inner_mode)
5183 - GET_MODE_SIZE (tmode))
5185 - pos / BITS_PER_WORD)
5186 : pos / BITS_PER_WORD));
5191 new = force_to_mode (inner, tmode,
5192 len >= HOST_BITS_PER_WIDE_INT
5193 ? GET_MODE_MASK (tmode)
5194 : ((HOST_WIDE_INT) 1 << len) - 1,
5197 /* If this extraction is going into the destination of a SET,
5198 make a STRICT_LOW_PART unless we made a MEM. */
5201 return (GET_CODE (new) == MEM ? new
5202 : (GET_CODE (new) != SUBREG
5203 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5204 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5206 /* Otherwise, sign- or zero-extend unless we already are in the
5209 return (mode == tmode ? new
5210 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5214 /* Unless this is a COMPARE or we have a funny memory reference,
5215 don't do anything with zero-extending field extracts starting at
5216 the low-order bit since they are simple AND operations. */
5217 if (pos_rtx == 0 && pos == 0 && ! in_dest
5218 && ! in_compare && ! spans_byte && unsignedp)
5221 /* Unless we are allowed to span bytes, reject this if we would be
5222 spanning bytes or if the position is not a constant and the length
5223 is not 1. In all other cases, we would only be going outside
5224 out object in cases when an original shift would have been
5227 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5228 || (pos_rtx != 0 && len != 1)))
5231 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5232 and the mode for the result. */
5236 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5237 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5238 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5243 if (! in_dest && unsignedp)
5245 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5246 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5247 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5252 if (! in_dest && ! unsignedp)
5254 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5255 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5256 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5260 /* Never narrow an object, since that might not be safe. */
5262 if (mode != VOIDmode
5263 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5264 extraction_mode = mode;
5266 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5267 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5268 pos_mode = GET_MODE (pos_rtx);
5270 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5271 if we have to change the mode of memory and cannot, the desired mode is
5273 if (GET_CODE (inner) != MEM)
5274 wanted_inner_mode = wanted_inner_reg_mode;
5275 else if (inner_mode != wanted_inner_mode
5276 && (mode_dependent_address_p (XEXP (inner, 0))
5277 || MEM_VOLATILE_P (inner)))
5278 wanted_inner_mode = extraction_mode;
5282 if (BITS_BIG_ENDIAN)
5284 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5285 BITS_BIG_ENDIAN style. If position is constant, compute new
5286 position. Otherwise, build subtraction.
5287 Note that POS is relative to the mode of the original argument.
5288 If it's a MEM we need to recompute POS relative to that.
5289 However, if we're extracting from (or inserting into) a register,
5290 we want to recompute POS relative to wanted_inner_mode. */
5291 int width = (GET_CODE (inner) == MEM
5292 ? GET_MODE_BITSIZE (is_mode)
5293 : GET_MODE_BITSIZE (wanted_inner_mode));
5296 pos = width - len - pos;
5299 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5300 GEN_INT (width - len), pos_rtx);
5301 /* POS may be less than 0 now, but we check for that below.
5302 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5305 /* If INNER has a wider mode, make it smaller. If this is a constant
5306 extract, try to adjust the byte to point to the byte containing
5308 if (wanted_inner_mode != VOIDmode
5309 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5310 && ((GET_CODE (inner) == MEM
5311 && (inner_mode == wanted_inner_mode
5312 || (! mode_dependent_address_p (XEXP (inner, 0))
5313 && ! MEM_VOLATILE_P (inner))))))
5317 /* The computations below will be correct if the machine is big
5318 endian in both bits and bytes or little endian in bits and bytes.
5319 If it is mixed, we must adjust. */
5321 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5322 adjust OFFSET to compensate. */
5323 if (BYTES_BIG_ENDIAN
5325 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5326 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5328 /* If this is a constant position, we can move to the desired byte. */
5331 offset += pos / BITS_PER_UNIT;
5332 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5335 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5337 && is_mode != wanted_inner_mode)
5338 offset = (GET_MODE_SIZE (is_mode)
5339 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5341 if (offset != 0 || inner_mode != wanted_inner_mode)
5343 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5344 plus_constant (XEXP (inner, 0), offset));
5345 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5346 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5347 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5352 /* If INNER is not memory, we can always get it into the proper mode. If we
5353 are changing its mode, POS must be a constant and smaller than the size
5355 else if (GET_CODE (inner) != MEM)
5357 if (GET_MODE (inner) != wanted_inner_mode
5359 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5362 inner = force_to_mode (inner, wanted_inner_mode,
5364 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5365 ? GET_MODE_MASK (wanted_inner_mode)
5366 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5370 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5371 have to zero extend. Otherwise, we can just use a SUBREG. */
5373 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5374 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5375 else if (pos_rtx != 0
5376 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5377 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5379 /* Make POS_RTX unless we already have it and it is correct. If we don't
5380 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5382 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5383 pos_rtx = orig_pos_rtx;
5385 else if (pos_rtx == 0)
5386 pos_rtx = GEN_INT (pos);
5388 /* Make the required operation. See if we can use existing rtx. */
5389 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5390 extraction_mode, inner, GEN_INT (len), pos_rtx);
5392 new = gen_lowpart_for_combine (mode, new);
5397 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5398 with any other operations in X. Return X without that shift if so. */
5401 extract_left_shift (x, count)
5405 enum rtx_code code = GET_CODE (x);
5406 enum machine_mode mode = GET_MODE (x);
5412 /* This is the shift itself. If it is wide enough, we will return
5413 either the value being shifted if the shift count is equal to
5414 COUNT or a shift for the difference. */
5415 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5416 && INTVAL (XEXP (x, 1)) >= count)
5417 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5418 INTVAL (XEXP (x, 1)) - count);
5422 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5423 return gen_unary (code, mode, mode, tem);
5427 case PLUS: case IOR: case XOR: case AND:
5428 /* If we can safely shift this constant and we find the inner shift,
5429 make a new operation. */
5430 if (GET_CODE (XEXP (x,1)) == CONST_INT
5431 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5432 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5433 return gen_binary (code, mode, tem,
5434 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5442 /* Look at the expression rooted at X. Look for expressions
5443 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5444 Form these expressions.
5446 Return the new rtx, usually just X.
5448 Also, for machines like the Vax that don't have logical shift insns,
5449 try to convert logical to arithmetic shift operations in cases where
5450 they are equivalent. This undoes the canonicalizations to logical
5451 shifts done elsewhere.
5453 We try, as much as possible, to re-use rtl expressions to save memory.
5455 IN_CODE says what kind of expression we are processing. Normally, it is
5456 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5457 being kludges), it is MEM. When processing the arguments of a comparison
5458 or a COMPARE against zero, it is COMPARE. */
5461 make_compound_operation (x, in_code)
5463 enum rtx_code in_code;
5465 enum rtx_code code = GET_CODE (x);
5466 enum machine_mode mode = GET_MODE (x);
5467 int mode_width = GET_MODE_BITSIZE (mode);
5469 enum rtx_code next_code;
5475 /* Select the code to be used in recursive calls. Once we are inside an
5476 address, we stay there. If we have a comparison, set to COMPARE,
5477 but once inside, go back to our default of SET. */
5479 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5480 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5481 && XEXP (x, 1) == const0_rtx) ? COMPARE
5482 : in_code == COMPARE ? SET : in_code);
5484 /* Process depending on the code of this operation. If NEW is set
5485 non-zero, it will be returned. */
5490 /* Convert shifts by constants into multiplications if inside
5492 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5493 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5494 && INTVAL (XEXP (x, 1)) >= 0)
5496 new = make_compound_operation (XEXP (x, 0), next_code);
5497 new = gen_rtx_combine (MULT, mode, new,
5498 GEN_INT ((HOST_WIDE_INT) 1
5499 << INTVAL (XEXP (x, 1))));
5504 /* If the second operand is not a constant, we can't do anything
5506 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5509 /* If the constant is a power of two minus one and the first operand
5510 is a logical right shift, make an extraction. */
5511 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5512 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5514 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5515 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5516 0, in_code == COMPARE);
5519 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5520 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5521 && subreg_lowpart_p (XEXP (x, 0))
5522 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5523 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5525 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5527 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5528 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5529 0, in_code == COMPARE);
5531 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5532 else if ((GET_CODE (XEXP (x, 0)) == XOR
5533 || GET_CODE (XEXP (x, 0)) == IOR)
5534 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5535 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5536 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5538 /* Apply the distributive law, and then try to make extractions. */
5539 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5540 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5542 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5544 new = make_compound_operation (new, in_code);
5547 /* If we are have (and (rotate X C) M) and C is larger than the number
5548 of bits in M, this is an extraction. */
5550 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5551 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5552 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5553 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5555 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5556 new = make_extraction (mode, new,
5557 (GET_MODE_BITSIZE (mode)
5558 - INTVAL (XEXP (XEXP (x, 0), 1))),
5559 NULL_RTX, i, 1, 0, in_code == COMPARE);
5562 /* On machines without logical shifts, if the operand of the AND is
5563 a logical shift and our mask turns off all the propagated sign
5564 bits, we can replace the logical shift with an arithmetic shift. */
5565 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5566 && (lshr_optab->handlers[(int) mode].insn_code
5567 == CODE_FOR_nothing)
5568 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5569 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5570 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5571 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5572 && mode_width <= HOST_BITS_PER_WIDE_INT)
5574 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5576 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5577 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5579 gen_rtx_combine (ASHIFTRT, mode,
5580 make_compound_operation (XEXP (XEXP (x, 0), 0),
5582 XEXP (XEXP (x, 0), 1)));
5585 /* If the constant is one less than a power of two, this might be
5586 representable by an extraction even if no shift is present.
5587 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5588 we are in a COMPARE. */
5589 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5590 new = make_extraction (mode,
5591 make_compound_operation (XEXP (x, 0),
5593 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5595 /* If we are in a comparison and this is an AND with a power of two,
5596 convert this into the appropriate bit extract. */
5597 else if (in_code == COMPARE
5598 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5599 new = make_extraction (mode,
5600 make_compound_operation (XEXP (x, 0),
5602 i, NULL_RTX, 1, 1, 0, 1);
5607 /* If the sign bit is known to be zero, replace this with an
5608 arithmetic shift. */
5609 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5610 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5611 && mode_width <= HOST_BITS_PER_WIDE_INT
5612 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5614 new = gen_rtx_combine (ASHIFTRT, mode,
5615 make_compound_operation (XEXP (x, 0),
5621 /* ... fall through ... */
5627 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5628 this is a SIGN_EXTRACT. */
5629 if (GET_CODE (rhs) == CONST_INT
5630 && GET_CODE (lhs) == ASHIFT
5631 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5632 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5634 new = make_compound_operation (XEXP (lhs, 0), next_code);
5635 new = make_extraction (mode, new,
5636 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5637 NULL_RTX, mode_width - INTVAL (rhs),
5638 code == LSHIFTRT, 0, in_code == COMPARE);
5641 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5642 If so, try to merge the shifts into a SIGN_EXTEND. We could
5643 also do this for some cases of SIGN_EXTRACT, but it doesn't
5644 seem worth the effort; the case checked for occurs on Alpha. */
5646 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5647 && ! (GET_CODE (lhs) == SUBREG
5648 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5649 && GET_CODE (rhs) == CONST_INT
5650 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5651 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5652 new = make_extraction (mode, make_compound_operation (new, next_code),
5653 0, NULL_RTX, mode_width - INTVAL (rhs),
5654 code == LSHIFTRT, 0, in_code == COMPARE);
5659 /* Call ourselves recursively on the inner expression. If we are
5660 narrowing the object and it has a different RTL code from
5661 what it originally did, do this SUBREG as a force_to_mode. */
5663 tem = make_compound_operation (SUBREG_REG (x), in_code);
5664 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5665 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5666 && subreg_lowpart_p (x))
5668 rtx newer = force_to_mode (tem, mode,
5669 GET_MODE_MASK (mode), NULL_RTX, 0);
5671 /* If we have something other than a SUBREG, we might have
5672 done an expansion, so rerun outselves. */
5673 if (GET_CODE (newer) != SUBREG)
5674 newer = make_compound_operation (newer, in_code);
5682 x = gen_lowpart_for_combine (mode, new);
5683 code = GET_CODE (x);
5686 /* Now recursively process each operand of this operation. */
5687 fmt = GET_RTX_FORMAT (code);
5688 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5691 new = make_compound_operation (XEXP (x, i), next_code);
5692 SUBST (XEXP (x, i), new);
5698 /* Given M see if it is a value that would select a field of bits
5699 within an item, but not the entire word. Return -1 if not.
5700 Otherwise, return the starting position of the field, where 0 is the
5703 *PLEN is set to the length of the field. */
5706 get_pos_from_mask (m, plen)
5707 unsigned HOST_WIDE_INT m;
5710 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5711 int pos = exact_log2 (m & - m);
5716 /* Now shift off the low-order zero bits and see if we have a power of
5718 *plen = exact_log2 ((m >> pos) + 1);
5726 /* See if X can be simplified knowing that we will only refer to it in
5727 MODE and will only refer to those bits that are nonzero in MASK.
5728 If other bits are being computed or if masking operations are done
5729 that select a superset of the bits in MASK, they can sometimes be
5732 Return a possibly simplified expression, but always convert X to
5733 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5735 Also, if REG is non-zero and X is a register equal in value to REG,
5738 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5739 are all off in X. This is used when X will be complemented, by either
5740 NOT, NEG, or XOR. */
5743 force_to_mode (x, mode, mask, reg, just_select)
5745 enum machine_mode mode;
5746 unsigned HOST_WIDE_INT mask;
5750 enum rtx_code code = GET_CODE (x);
5751 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5752 enum machine_mode op_mode;
5753 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5756 /* If this is a CALL, don't do anything. Some of the code below
5757 will do the wrong thing since the mode of a CALL is VOIDmode. */
5761 /* We want to perform the operation is its present mode unless we know
5762 that the operation is valid in MODE, in which case we do the operation
5764 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5765 && code_to_optab[(int) code] != 0
5766 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5767 != CODE_FOR_nothing))
5768 ? mode : GET_MODE (x));
5770 /* It is not valid to do a right-shift in a narrower mode
5771 than the one it came in with. */
5772 if ((code == LSHIFTRT || code == ASHIFTRT)
5773 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5774 op_mode = GET_MODE (x);
5776 /* Truncate MASK to fit OP_MODE. */
5778 mask &= GET_MODE_MASK (op_mode);
5780 /* When we have an arithmetic operation, or a shift whose count we
5781 do not know, we need to assume that all bit the up to the highest-order
5782 bit in MASK will be needed. This is how we form such a mask. */
5784 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5785 ? GET_MODE_MASK (op_mode)
5786 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5788 fuller_mask = ~ (HOST_WIDE_INT) 0;
5790 /* Determine what bits of X are guaranteed to be (non)zero. */
5791 nonzero = nonzero_bits (x, mode);
5793 /* If none of the bits in X are needed, return a zero. */
5794 if (! just_select && (nonzero & mask) == 0)
5797 /* If X is a CONST_INT, return a new one. Do this here since the
5798 test below will fail. */
5799 if (GET_CODE (x) == CONST_INT)
5801 HOST_WIDE_INT cval = INTVAL (x) & mask;
5802 int width = GET_MODE_BITSIZE (mode);
5804 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5805 number, sign extend it. */
5806 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5807 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5808 cval |= (HOST_WIDE_INT) -1 << width;
5810 return GEN_INT (cval);
5813 /* If X is narrower than MODE and we want all the bits in X's mode, just
5814 get X in the proper mode. */
5815 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5816 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
5817 return gen_lowpart_for_combine (mode, x);
5819 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5820 MASK are already known to be zero in X, we need not do anything. */
5821 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
5827 /* If X is a (clobber (const_int)), return it since we know we are
5828 generating something that won't match. */
5832 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5833 spanned the boundary of the MEM. If we are now masking so it is
5834 within that boundary, we don't need the USE any more. */
5835 if (! BITS_BIG_ENDIAN
5836 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5837 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5844 x = expand_compound_operation (x);
5845 if (GET_CODE (x) != code)
5846 return force_to_mode (x, mode, mask, reg, next_select);
5850 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5851 || rtx_equal_p (reg, get_last_value (x))))
5856 if (subreg_lowpart_p (x)
5857 /* We can ignore the effect of this SUBREG if it narrows the mode or
5858 if the constant masks to zero all the bits the mode doesn't
5860 && ((GET_MODE_SIZE (GET_MODE (x))
5861 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5863 & GET_MODE_MASK (GET_MODE (x))
5864 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
5865 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
5869 /* If this is an AND with a constant, convert it into an AND
5870 whose constant is the AND of that constant with MASK. If it
5871 remains an AND of MASK, delete it since it is redundant. */
5873 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5875 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
5876 mask & INTVAL (XEXP (x, 1)));
5878 /* If X is still an AND, see if it is an AND with a mask that
5879 is just some low-order bits. If so, and it is MASK, we don't
5882 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5883 && INTVAL (XEXP (x, 1)) == mask)
5886 /* If it remains an AND, try making another AND with the bits
5887 in the mode mask that aren't in MASK turned on. If the
5888 constant in the AND is wide enough, this might make a
5889 cheaper constant. */
5891 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5892 && GET_MODE_MASK (GET_MODE (x)) != mask
5893 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
5895 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
5896 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
5897 int width = GET_MODE_BITSIZE (GET_MODE (x));
5900 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5901 number, sign extend it. */
5902 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5903 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5904 cval |= (HOST_WIDE_INT) -1 << width;
5906 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
5907 if (rtx_cost (y, SET) < rtx_cost (x, SET))
5917 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5918 low-order bits (as in an alignment operation) and FOO is already
5919 aligned to that boundary, mask C1 to that boundary as well.
5920 This may eliminate that PLUS and, later, the AND. */
5923 int width = GET_MODE_BITSIZE (mode);
5924 unsigned HOST_WIDE_INT smask = mask;
5926 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
5927 number, sign extend it. */
5929 if (width < HOST_BITS_PER_WIDE_INT
5930 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5931 smask |= (HOST_WIDE_INT) -1 << width;
5933 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5934 && exact_log2 (- smask) >= 0
5935 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
5936 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
5937 return force_to_mode (plus_constant (XEXP (x, 0),
5938 INTVAL (XEXP (x, 1)) & mask),
5939 mode, mask, reg, next_select);
5942 /* ... fall through ... */
5946 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5947 most significant bit in MASK since carries from those bits will
5948 affect the bits we are interested in. */
5954 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5955 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5956 operation which may be a bitfield extraction. Ensure that the
5957 constant we form is not wider than the mode of X. */
5959 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5960 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5961 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5962 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5963 && GET_CODE (XEXP (x, 1)) == CONST_INT
5964 && ((INTVAL (XEXP (XEXP (x, 0), 1))
5965 + floor_log2 (INTVAL (XEXP (x, 1))))
5966 < GET_MODE_BITSIZE (GET_MODE (x)))
5967 && (INTVAL (XEXP (x, 1))
5968 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
5970 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
5971 << INTVAL (XEXP (XEXP (x, 0), 1)));
5972 temp = gen_binary (GET_CODE (x), GET_MODE (x),
5973 XEXP (XEXP (x, 0), 0), temp);
5974 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
5975 XEXP (XEXP (x, 0), 1));
5976 return force_to_mode (x, mode, mask, reg, next_select);
5980 /* For most binary operations, just propagate into the operation and
5981 change the mode if we have an operation of that mode. */
5983 op0 = gen_lowpart_for_combine (op_mode,
5984 force_to_mode (XEXP (x, 0), mode, mask,
5986 op1 = gen_lowpart_for_combine (op_mode,
5987 force_to_mode (XEXP (x, 1), mode, mask,
5990 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
5991 MASK since OP1 might have been sign-extended but we never want
5992 to turn on extra bits, since combine might have previously relied
5993 on them being off. */
5994 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
5995 && (INTVAL (op1) & mask) != 0)
5996 op1 = GEN_INT (INTVAL (op1) & mask);
5998 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
5999 x = gen_binary (code, op_mode, op0, op1);
6003 /* For left shifts, do the same, but just for the first operand.
6004 However, we cannot do anything with shifts where we cannot
6005 guarantee that the counts are smaller than the size of the mode
6006 because such a count will have a different meaning in a
6009 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6010 && INTVAL (XEXP (x, 1)) >= 0
6011 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6012 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6013 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6014 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6017 /* If the shift count is a constant and we can do arithmetic in
6018 the mode of the shift, refine which bits we need. Otherwise, use the
6019 conservative form of the mask. */
6020 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6021 && INTVAL (XEXP (x, 1)) >= 0
6022 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6023 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6024 mask >>= INTVAL (XEXP (x, 1));
6028 op0 = gen_lowpart_for_combine (op_mode,
6029 force_to_mode (XEXP (x, 0), op_mode,
6030 mask, reg, next_select));
6032 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6033 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6037 /* Here we can only do something if the shift count is a constant,
6038 this shift constant is valid for the host, and we can do arithmetic
6041 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6042 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6043 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6045 rtx inner = XEXP (x, 0);
6047 /* Select the mask of the bits we need for the shift operand. */
6048 mask <<= INTVAL (XEXP (x, 1));
6050 /* We can only change the mode of the shift if we can do arithmetic
6051 in the mode of the shift and MASK is no wider than the width of
6053 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6054 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6055 op_mode = GET_MODE (x);
6057 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6059 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6060 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6063 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6064 shift and AND produces only copies of the sign bit (C2 is one less
6065 than a power of two), we can do this with just a shift. */
6067 if (GET_CODE (x) == LSHIFTRT
6068 && GET_CODE (XEXP (x, 1)) == CONST_INT
6069 && ((INTVAL (XEXP (x, 1))
6070 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6071 >= GET_MODE_BITSIZE (GET_MODE (x)))
6072 && exact_log2 (mask + 1) >= 0
6073 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6074 >= exact_log2 (mask + 1)))
6075 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6076 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6077 - exact_log2 (mask + 1)));
6081 /* If we are just looking for the sign bit, we don't need this shift at
6082 all, even if it has a variable count. */
6083 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6084 && (mask == ((HOST_WIDE_INT) 1
6085 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6086 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6088 /* If this is a shift by a constant, get a mask that contains those bits
6089 that are not copies of the sign bit. We then have two cases: If
6090 MASK only includes those bits, this can be a logical shift, which may
6091 allow simplifications. If MASK is a single-bit field not within
6092 those bits, we are requesting a copy of the sign bit and hence can
6093 shift the sign bit to the appropriate location. */
6095 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6096 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6100 /* If the considered data is wider then HOST_WIDE_INT, we can't
6101 represent a mask for all its bits in a single scalar.
6102 But we only care about the lower bits, so calculate these. */
6104 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6106 nonzero = ~(HOST_WIDE_INT)0;
6108 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6109 is the number of bits a full-width mask would have set.
6110 We need only shift if these are fewer than nonzero can
6111 hold. If not, we must keep all bits set in nonzero. */
6113 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6114 < HOST_BITS_PER_WIDE_INT)
6115 nonzero >>= INTVAL (XEXP (x, 1))
6116 + HOST_BITS_PER_WIDE_INT
6117 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6121 nonzero = GET_MODE_MASK (GET_MODE (x));
6122 nonzero >>= INTVAL (XEXP (x, 1));
6125 if ((mask & ~ nonzero) == 0
6126 || (i = exact_log2 (mask)) >= 0)
6128 x = simplify_shift_const
6129 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6130 i < 0 ? INTVAL (XEXP (x, 1))
6131 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6133 if (GET_CODE (x) != ASHIFTRT)
6134 return force_to_mode (x, mode, mask, reg, next_select);
6138 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6139 even if the shift count isn't a constant. */
6141 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6143 /* If this is a sign-extension operation that just affects bits
6144 we don't care about, remove it. Be sure the call above returned
6145 something that is still a shift. */
6147 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6148 && GET_CODE (XEXP (x, 1)) == CONST_INT
6149 && INTVAL (XEXP (x, 1)) >= 0
6150 && (INTVAL (XEXP (x, 1))
6151 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6152 && GET_CODE (XEXP (x, 0)) == ASHIFT
6153 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6154 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6155 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6162 /* If the shift count is constant and we can do computations
6163 in the mode of X, compute where the bits we care about are.
6164 Otherwise, we can't do anything. Don't change the mode of
6165 the shift or propagate MODE into the shift, though. */
6166 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6167 && INTVAL (XEXP (x, 1)) >= 0)
6169 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6170 GET_MODE (x), GEN_INT (mask),
6172 if (temp && GET_CODE(temp) == CONST_INT)
6174 force_to_mode (XEXP (x, 0), GET_MODE (x),
6175 INTVAL (temp), reg, next_select));
6180 /* If we just want the low-order bit, the NEG isn't needed since it
6181 won't change the low-order bit. */
6183 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6185 /* We need any bits less significant than the most significant bit in
6186 MASK since carries from those bits will affect the bits we are
6192 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6193 same as the XOR case above. Ensure that the constant we form is not
6194 wider than the mode of X. */
6196 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6197 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6198 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6199 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6200 < GET_MODE_BITSIZE (GET_MODE (x)))
6201 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6203 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6204 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6205 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6207 return force_to_mode (x, mode, mask, reg, next_select);
6210 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6211 use the full mask inside the NOT. */
6215 op0 = gen_lowpart_for_combine (op_mode,
6216 force_to_mode (XEXP (x, 0), mode, mask,
6218 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6219 x = gen_unary (code, op_mode, op_mode, op0);
6223 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6224 in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not
6226 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 0) == const0_rtx
6227 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6228 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6233 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6234 written in a narrower mode. We play it safe and do not do so. */
6237 gen_lowpart_for_combine (GET_MODE (x),
6238 force_to_mode (XEXP (x, 1), mode,
6239 mask, reg, next_select)));
6241 gen_lowpart_for_combine (GET_MODE (x),
6242 force_to_mode (XEXP (x, 2), mode,
6243 mask, reg,next_select)));
6247 /* Ensure we return a value of the proper mode. */
6248 return gen_lowpart_for_combine (mode, x);
6251 /* Return nonzero if X is an expression that has one of two values depending on
6252 whether some other value is zero or nonzero. In that case, we return the
6253 value that is being tested, *PTRUE is set to the value if the rtx being
6254 returned has a nonzero value, and *PFALSE is set to the other alternative.
6256 If we return zero, we set *PTRUE and *PFALSE to X. */
6259 if_then_else_cond (x, ptrue, pfalse)
6261 rtx *ptrue, *pfalse;
6263 enum machine_mode mode = GET_MODE (x);
6264 enum rtx_code code = GET_CODE (x);
6265 int size = GET_MODE_BITSIZE (mode);
6266 rtx cond0, cond1, true0, true1, false0, false1;
6267 unsigned HOST_WIDE_INT nz;
6269 /* If this is a unary operation whose operand has one of two values, apply
6270 our opcode to compute those values. */
6271 if (GET_RTX_CLASS (code) == '1'
6272 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6274 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6275 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6279 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6280 make can't possibly match and would suppress other optimizations. */
6281 else if (code == COMPARE)
6284 /* If this is a binary operation, see if either side has only one of two
6285 values. If either one does or if both do and they are conditional on
6286 the same value, compute the new true and false values. */
6287 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6288 || GET_RTX_CLASS (code) == '<')
6290 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6291 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6293 if ((cond0 != 0 || cond1 != 0)
6294 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6296 *ptrue = gen_binary (code, mode, true0, true1);
6297 *pfalse = gen_binary (code, mode, false0, false1);
6298 return cond0 ? cond0 : cond1;
6301 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6303 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6304 operands is zero when the other is non-zero, and vice-versa. */
6306 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6308 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6310 rtx op0 = XEXP (XEXP (x, 0), 1);
6311 rtx op1 = XEXP (XEXP (x, 1), 1);
6313 cond0 = XEXP (XEXP (x, 0), 0);
6314 cond1 = XEXP (XEXP (x, 1), 0);
6316 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6317 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6318 && reversible_comparison_p (cond1)
6319 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6320 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6321 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6322 || ((swap_condition (GET_CODE (cond0))
6323 == reverse_condition (GET_CODE (cond1)))
6324 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6325 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6326 && ! side_effects_p (x))
6328 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6329 *pfalse = gen_binary (MULT, mode,
6331 ? gen_unary (NEG, mode, mode, op1) : op1),
6337 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6339 if ((code == MULT || code == AND || code == UMIN)
6340 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6342 cond0 = XEXP (XEXP (x, 0), 0);
6343 cond1 = XEXP (XEXP (x, 1), 0);
6345 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6346 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6347 && reversible_comparison_p (cond1)
6348 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6349 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6350 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6351 || ((swap_condition (GET_CODE (cond0))
6352 == reverse_condition (GET_CODE (cond1)))
6353 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6354 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6355 && ! side_effects_p (x))
6357 *ptrue = *pfalse = const0_rtx;
6364 else if (code == IF_THEN_ELSE)
6366 /* If we have IF_THEN_ELSE already, extract the condition and
6367 canonicalize it if it is NE or EQ. */
6368 cond0 = XEXP (x, 0);
6369 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6370 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6371 return XEXP (cond0, 0);
6372 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6374 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6375 return XEXP (cond0, 0);
6381 /* If X is a normal SUBREG with both inner and outer modes integral,
6382 we can narrow both the true and false values of the inner expression,
6383 if there is a condition. */
6384 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6385 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6386 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6387 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6390 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6392 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6397 /* If X is a constant, this isn't special and will cause confusions
6398 if we treat it as such. Likewise if it is equivalent to a constant. */
6399 else if (CONSTANT_P (x)
6400 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6403 /* If X is known to be either 0 or -1, those are the true and
6404 false values when testing X. */
6405 else if (num_sign_bit_copies (x, mode) == size)
6407 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6411 /* Likewise for 0 or a single bit. */
6412 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6414 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6418 /* Otherwise fail; show no condition with true and false values the same. */
6419 *ptrue = *pfalse = x;
6423 /* Return the value of expression X given the fact that condition COND
6424 is known to be true when applied to REG as its first operand and VAL
6425 as its second. X is known to not be shared and so can be modified in
6428 We only handle the simplest cases, and specifically those cases that
6429 arise with IF_THEN_ELSE expressions. */
6432 known_cond (x, cond, reg, val)
6437 enum rtx_code code = GET_CODE (x);
6442 if (side_effects_p (x))
6445 if (cond == EQ && rtx_equal_p (x, reg))
6448 /* If X is (abs REG) and we know something about REG's relationship
6449 with zero, we may be able to simplify this. */
6451 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6454 case GE: case GT: case EQ:
6457 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6461 /* The only other cases we handle are MIN, MAX, and comparisons if the
6462 operands are the same as REG and VAL. */
6464 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6466 if (rtx_equal_p (XEXP (x, 0), val))
6467 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6469 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6471 if (GET_RTX_CLASS (code) == '<')
6472 return (comparison_dominates_p (cond, code) ? const_true_rtx
6473 : (comparison_dominates_p (cond,
6474 reverse_condition (code))
6477 else if (code == SMAX || code == SMIN
6478 || code == UMIN || code == UMAX)
6480 int unsignedp = (code == UMIN || code == UMAX);
6482 if (code == SMAX || code == UMAX)
6483 cond = reverse_condition (cond);
6488 return unsignedp ? x : XEXP (x, 1);
6490 return unsignedp ? x : XEXP (x, 0);
6492 return unsignedp ? XEXP (x, 1) : x;
6494 return unsignedp ? XEXP (x, 0) : x;
6500 fmt = GET_RTX_FORMAT (code);
6501 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6504 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6505 else if (fmt[i] == 'E')
6506 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6507 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6514 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6515 assignment as a field assignment. */
6518 rtx_equal_for_field_assignment_p (x, y)
6524 if (x == y || rtx_equal_p (x, y))
6527 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6530 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6531 Note that all SUBREGs of MEM are paradoxical; otherwise they
6532 would have been rewritten. */
6533 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6534 && GET_CODE (SUBREG_REG (y)) == MEM
6535 && rtx_equal_p (SUBREG_REG (y),
6536 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6539 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6540 && GET_CODE (SUBREG_REG (x)) == MEM
6541 && rtx_equal_p (SUBREG_REG (x),
6542 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6545 last_x = get_last_value (x);
6546 last_y = get_last_value (y);
6548 return ((last_x != 0 && rtx_equal_for_field_assignment_p (last_x, y))
6549 || (last_y != 0 && rtx_equal_for_field_assignment_p (x, last_y))
6550 || (last_x != 0 && last_y != 0
6551 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6554 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6555 Return that assignment if so.
6557 We only handle the most common cases. */
6560 make_field_assignment (x)
6563 rtx dest = SET_DEST (x);
6564 rtx src = SET_SRC (x);
6570 enum machine_mode mode;
6572 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6573 a clear of a one-bit field. We will have changed it to
6574 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6577 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6578 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6579 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6580 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6582 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6585 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6589 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6590 && subreg_lowpart_p (XEXP (src, 0))
6591 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6592 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6593 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6594 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6595 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6597 assign = make_extraction (VOIDmode, dest, 0,
6598 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6601 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6605 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6607 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6608 && XEXP (XEXP (src, 0), 0) == const1_rtx
6609 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6611 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6614 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6618 /* The other case we handle is assignments into a constant-position
6619 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6620 a mask that has all one bits except for a group of zero bits and
6621 OTHER is known to have zeros where C1 has ones, this is such an
6622 assignment. Compute the position and length from C1. Shift OTHER
6623 to the appropriate position, force it to the required mode, and
6624 make the extraction. Check for the AND in both operands. */
6626 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6629 rhs = expand_compound_operation (XEXP (src, 0));
6630 lhs = expand_compound_operation (XEXP (src, 1));
6632 if (GET_CODE (rhs) == AND
6633 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6634 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6635 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6636 else if (GET_CODE (lhs) == AND
6637 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6638 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6639 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6643 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6644 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6645 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6646 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6649 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6653 /* The mode to use for the source is the mode of the assignment, or of
6654 what is inside a possible STRICT_LOW_PART. */
6655 mode = (GET_CODE (assign) == STRICT_LOW_PART
6656 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6658 /* Shift OTHER right POS places and make it the source, restricting it
6659 to the proper length and mode. */
6661 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6662 GET_MODE (src), other, pos),
6664 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6665 ? GET_MODE_MASK (mode)
6666 : ((HOST_WIDE_INT) 1 << len) - 1,
6669 return gen_rtx_combine (SET, VOIDmode, assign, src);
6672 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6676 apply_distributive_law (x)
6679 enum rtx_code code = GET_CODE (x);
6680 rtx lhs, rhs, other;
6682 enum rtx_code inner_code;
6684 /* Distributivity is not true for floating point.
6685 It can change the value. So don't do it.
6686 -- rms and moshier@world.std.com. */
6687 if (FLOAT_MODE_P (GET_MODE (x)))
6690 /* The outer operation can only be one of the following: */
6691 if (code != IOR && code != AND && code != XOR
6692 && code != PLUS && code != MINUS)
6695 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6697 /* If either operand is a primitive we can't do anything, so get out fast. */
6698 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6699 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6702 lhs = expand_compound_operation (lhs);
6703 rhs = expand_compound_operation (rhs);
6704 inner_code = GET_CODE (lhs);
6705 if (inner_code != GET_CODE (rhs))
6708 /* See if the inner and outer operations distribute. */
6715 /* These all distribute except over PLUS. */
6716 if (code == PLUS || code == MINUS)
6721 if (code != PLUS && code != MINUS)
6726 /* This is also a multiply, so it distributes over everything. */
6730 /* Non-paradoxical SUBREGs distributes over all operations, provided
6731 the inner modes and word numbers are the same, this is an extraction
6732 of a low-order part, we don't convert an fp operation to int or
6733 vice versa, and we would not be converting a single-word
6734 operation into a multi-word operation. The latter test is not
6735 required, but it prevents generating unneeded multi-word operations.
6736 Some of the previous tests are redundant given the latter test, but
6737 are retained because they are required for correctness.
6739 We produce the result slightly differently in this case. */
6741 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6742 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6743 || ! subreg_lowpart_p (lhs)
6744 || (GET_MODE_CLASS (GET_MODE (lhs))
6745 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6746 || (GET_MODE_SIZE (GET_MODE (lhs))
6747 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6748 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6751 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6752 SUBREG_REG (lhs), SUBREG_REG (rhs));
6753 return gen_lowpart_for_combine (GET_MODE (x), tem);
6759 /* Set LHS and RHS to the inner operands (A and B in the example
6760 above) and set OTHER to the common operand (C in the example).
6761 These is only one way to do this unless the inner operation is
6763 if (GET_RTX_CLASS (inner_code) == 'c'
6764 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6765 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6766 else if (GET_RTX_CLASS (inner_code) == 'c'
6767 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6768 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6769 else if (GET_RTX_CLASS (inner_code) == 'c'
6770 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6771 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6772 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6773 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6777 /* Form the new inner operation, seeing if it simplifies first. */
6778 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6780 /* There is one exception to the general way of distributing:
6781 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6782 if (code == XOR && inner_code == IOR)
6785 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
6788 /* We may be able to continuing distributing the result, so call
6789 ourselves recursively on the inner operation before forming the
6790 outer operation, which we return. */
6791 return gen_binary (inner_code, GET_MODE (x),
6792 apply_distributive_law (tem), other);
6795 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6798 Return an equivalent form, if different from X. Otherwise, return X. If
6799 X is zero, we are to always construct the equivalent form. */
6802 simplify_and_const_int (x, mode, varop, constop)
6804 enum machine_mode mode;
6806 unsigned HOST_WIDE_INT constop;
6808 unsigned HOST_WIDE_INT nonzero;
6809 int width = GET_MODE_BITSIZE (mode);
6812 /* Simplify VAROP knowing that we will be only looking at some of the
6814 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6816 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6817 CONST_INT, we are done. */
6818 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6821 /* See what bits may be nonzero in VAROP. Unlike the general case of
6822 a call to nonzero_bits, here we don't care about bits outside
6825 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6827 /* If this would be an entire word for the target, but is not for
6828 the host, then sign-extend on the host so that the number will look
6829 the same way on the host that it would on the target.
6831 For example, when building a 64 bit alpha hosted 32 bit sparc
6832 targeted compiler, then we want the 32 bit unsigned value -1 to be
6833 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
6834 The later confuses the sparc backend. */
6836 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
6837 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
6838 nonzero |= ((HOST_WIDE_INT) (-1) << width);
6840 /* Turn off all bits in the constant that are known to already be zero.
6841 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6842 which is tested below. */
6846 /* If we don't have any bits left, return zero. */
6850 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6851 a power of two, we can replace this with a ASHIFT. */
6852 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
6853 && (i = exact_log2 (constop)) >= 0)
6854 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
6856 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6857 or XOR, then try to apply the distributive law. This may eliminate
6858 operations if either branch can be simplified because of the AND.
6859 It may also make some cases more complex, but those cases probably
6860 won't match a pattern either with or without this. */
6862 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
6864 gen_lowpart_for_combine
6866 apply_distributive_law
6867 (gen_binary (GET_CODE (varop), GET_MODE (varop),
6868 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6869 XEXP (varop, 0), constop),
6870 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6871 XEXP (varop, 1), constop))));
6873 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6874 if we already had one (just check for the simplest cases). */
6875 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6876 && GET_MODE (XEXP (x, 0)) == mode
6877 && SUBREG_REG (XEXP (x, 0)) == varop)
6878 varop = XEXP (x, 0);
6880 varop = gen_lowpart_for_combine (mode, varop);
6882 /* If we can't make the SUBREG, try to return what we were given. */
6883 if (GET_CODE (varop) == CLOBBER)
6884 return x ? x : varop;
6886 /* If we are only masking insignificant bits, return VAROP. */
6887 if (constop == nonzero)
6890 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6891 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6892 x = gen_binary (AND, mode, varop, GEN_INT (constop));
6896 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6897 || INTVAL (XEXP (x, 1)) != constop)
6898 SUBST (XEXP (x, 1), GEN_INT (constop));
6900 SUBST (XEXP (x, 0), varop);
6906 /* Given an expression, X, compute which bits in X can be non-zero.
6907 We don't care about bits outside of those defined in MODE.
6909 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6910 a shift, AND, or zero_extract, we can do better. */
6912 static unsigned HOST_WIDE_INT
6913 nonzero_bits (x, mode)
6915 enum machine_mode mode;
6917 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6918 unsigned HOST_WIDE_INT inner_nz;
6920 int mode_width = GET_MODE_BITSIZE (mode);
6923 /* For floating-point values, assume all bits are needed. */
6924 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
6927 /* If X is wider than MODE, use its mode instead. */
6928 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6930 mode = GET_MODE (x);
6931 nonzero = GET_MODE_MASK (mode);
6932 mode_width = GET_MODE_BITSIZE (mode);
6935 if (mode_width > HOST_BITS_PER_WIDE_INT)
6936 /* Our only callers in this case look for single bit values. So
6937 just return the mode mask. Those tests will then be false. */
6940 #ifndef WORD_REGISTER_OPERATIONS
6941 /* If MODE is wider than X, but both are a single word for both the host
6942 and target machines, we can compute this from which bits of the
6943 object might be nonzero in its own mode, taking into account the fact
6944 that on many CISC machines, accessing an object in a wider mode
6945 causes the high-order bits to become undefined. So they are
6946 not known to be zero. */
6948 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
6949 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
6950 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6951 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
6953 nonzero &= nonzero_bits (x, GET_MODE (x));
6954 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
6959 code = GET_CODE (x);
6963 #ifdef POINTERS_EXTEND_UNSIGNED
6964 /* If pointers extend unsigned and this is a pointer in Pmode, say that
6965 all the bits above ptr_mode are known to be zero. */
6966 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
6967 && REGNO_POINTER_FLAG (REGNO (x)))
6968 nonzero &= GET_MODE_MASK (ptr_mode);
6971 #ifdef STACK_BOUNDARY
6972 /* If this is the stack pointer, we may know something about its
6973 alignment. If PUSH_ROUNDING is defined, it is possible for the
6974 stack to be momentarily aligned only to that amount, so we pick
6975 the least alignment. */
6977 if (x == stack_pointer_rtx || x == frame_pointer_rtx
6978 || x == arg_pointer_rtx || x == hard_frame_pointer_rtx
6979 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
6980 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
6982 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6984 #ifdef PUSH_ROUNDING
6985 if (REGNO (x) == STACK_POINTER_REGNUM)
6986 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6989 /* We must return here, otherwise we may get a worse result from
6990 one of the choices below. There is nothing useful below as
6991 far as the stack pointer is concerned. */
6992 return nonzero &= ~ (sp_alignment - 1);
6996 /* If X is a register whose nonzero bits value is current, use it.
6997 Otherwise, if X is a register whose value we can find, use that
6998 value. Otherwise, use the previously-computed global nonzero bits
6999 for this register. */
7001 if (reg_last_set_value[REGNO (x)] != 0
7002 && reg_last_set_mode[REGNO (x)] == mode
7003 && (reg_n_sets[REGNO (x)] == 1
7004 || reg_last_set_label[REGNO (x)] == label_tick)
7005 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7006 return reg_last_set_nonzero_bits[REGNO (x)];
7008 tem = get_last_value (x);
7012 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7013 /* If X is narrower than MODE and TEM is a non-negative
7014 constant that would appear negative in the mode of X,
7015 sign-extend it for use in reg_nonzero_bits because some
7016 machines (maybe most) will actually do the sign-extension
7017 and this is the conservative approach.
7019 ??? For 2.5, try to tighten up the MD files in this regard
7020 instead of this kludge. */
7022 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7023 && GET_CODE (tem) == CONST_INT
7025 && 0 != (INTVAL (tem)
7026 & ((HOST_WIDE_INT) 1
7027 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7028 tem = GEN_INT (INTVAL (tem)
7029 | ((HOST_WIDE_INT) (-1)
7030 << GET_MODE_BITSIZE (GET_MODE (x))));
7032 return nonzero_bits (tem, mode);
7034 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7035 return reg_nonzero_bits[REGNO (x)] & nonzero;
7040 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7041 /* If X is negative in MODE, sign-extend the value. */
7042 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7043 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7044 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7050 #ifdef LOAD_EXTEND_OP
7051 /* In many, if not most, RISC machines, reading a byte from memory
7052 zeros the rest of the register. Noticing that fact saves a lot
7053 of extra zero-extends. */
7054 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7055 nonzero &= GET_MODE_MASK (GET_MODE (x));
7065 /* If this produces an integer result, we know which bits are set.
7066 Code here used to clear bits outside the mode of X, but that is
7069 if (GET_MODE_CLASS (mode) == MODE_INT
7070 && mode_width <= HOST_BITS_PER_WIDE_INT)
7071 nonzero = STORE_FLAG_VALUE;
7075 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7076 == GET_MODE_BITSIZE (GET_MODE (x)))
7079 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7080 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7084 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7085 == GET_MODE_BITSIZE (GET_MODE (x)))
7090 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7094 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7095 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7096 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7100 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7101 Otherwise, show all the bits in the outer mode but not the inner
7103 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7104 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7106 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7109 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7110 inner_nz |= (GET_MODE_MASK (mode)
7111 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7114 nonzero &= inner_nz;
7118 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7119 & nonzero_bits (XEXP (x, 1), mode));
7123 case UMIN: case UMAX: case SMIN: case SMAX:
7124 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7125 | nonzero_bits (XEXP (x, 1), mode));
7128 case PLUS: case MINUS:
7130 case DIV: case UDIV:
7131 case MOD: case UMOD:
7132 /* We can apply the rules of arithmetic to compute the number of
7133 high- and low-order zero bits of these operations. We start by
7134 computing the width (position of the highest-order non-zero bit)
7135 and the number of low-order zero bits for each value. */
7137 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7138 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7139 int width0 = floor_log2 (nz0) + 1;
7140 int width1 = floor_log2 (nz1) + 1;
7141 int low0 = floor_log2 (nz0 & -nz0);
7142 int low1 = floor_log2 (nz1 & -nz1);
7143 HOST_WIDE_INT op0_maybe_minusp
7144 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7145 HOST_WIDE_INT op1_maybe_minusp
7146 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7147 int result_width = mode_width;
7153 result_width = MAX (width0, width1) + 1;
7154 result_low = MIN (low0, low1);
7157 result_low = MIN (low0, low1);
7160 result_width = width0 + width1;
7161 result_low = low0 + low1;
7164 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7165 result_width = width0;
7168 result_width = width0;
7171 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7172 result_width = MIN (width0, width1);
7173 result_low = MIN (low0, low1);
7176 result_width = MIN (width0, width1);
7177 result_low = MIN (low0, low1);
7181 if (result_width < mode_width)
7182 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7185 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7190 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7191 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7192 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7196 /* If this is a SUBREG formed for a promoted variable that has
7197 been zero-extended, we know that at least the high-order bits
7198 are zero, though others might be too. */
7200 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7201 nonzero = (GET_MODE_MASK (GET_MODE (x))
7202 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7204 /* If the inner mode is a single word for both the host and target
7205 machines, we can compute this from which bits of the inner
7206 object might be nonzero. */
7207 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7208 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7209 <= HOST_BITS_PER_WIDE_INT))
7211 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7213 #ifndef WORD_REGISTER_OPERATIONS
7214 /* On many CISC machines, accessing an object in a wider mode
7215 causes the high-order bits to become undefined. So they are
7216 not known to be zero. */
7217 if (GET_MODE_SIZE (GET_MODE (x))
7218 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7219 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7220 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7229 /* The nonzero bits are in two classes: any bits within MODE
7230 that aren't in GET_MODE (x) are always significant. The rest of the
7231 nonzero bits are those that are significant in the operand of
7232 the shift when shifted the appropriate number of bits. This
7233 shows that high-order bits are cleared by the right shift and
7234 low-order bits by left shifts. */
7235 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7236 && INTVAL (XEXP (x, 1)) >= 0
7237 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7239 enum machine_mode inner_mode = GET_MODE (x);
7240 int width = GET_MODE_BITSIZE (inner_mode);
7241 int count = INTVAL (XEXP (x, 1));
7242 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7243 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7244 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7245 unsigned HOST_WIDE_INT outer = 0;
7247 if (mode_width > width)
7248 outer = (op_nonzero & nonzero & ~ mode_mask);
7250 if (code == LSHIFTRT)
7252 else if (code == ASHIFTRT)
7256 /* If the sign bit may have been nonzero before the shift, we
7257 need to mark all the places it could have been copied to
7258 by the shift as possibly nonzero. */
7259 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7260 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7262 else if (code == ASHIFT)
7265 inner = ((inner << (count % width)
7266 | (inner >> (width - (count % width)))) & mode_mask);
7268 nonzero &= (outer | inner);
7273 /* This is at most the number of bits in the mode. */
7274 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7278 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7279 | nonzero_bits (XEXP (x, 2), mode));
7286 /* Return the number of bits at the high-order end of X that are known to
7287 be equal to the sign bit. X will be used in mode MODE; if MODE is
7288 VOIDmode, X will be used in its own mode. The returned value will always
7289 be between 1 and the number of bits in MODE. */
7292 num_sign_bit_copies (x, mode)
7294 enum machine_mode mode;
7296 enum rtx_code code = GET_CODE (x);
7298 int num0, num1, result;
7299 unsigned HOST_WIDE_INT nonzero;
7302 /* If we weren't given a mode, use the mode of X. If the mode is still
7303 VOIDmode, we don't know anything. Likewise if one of the modes is
7306 if (mode == VOIDmode)
7307 mode = GET_MODE (x);
7309 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7312 bitwidth = GET_MODE_BITSIZE (mode);
7314 /* For a smaller object, just ignore the high bits. */
7315 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7316 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7317 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7319 #ifndef WORD_REGISTER_OPERATIONS
7320 /* If this machine does not do all register operations on the entire
7321 register and MODE is wider than the mode of X, we can say nothing
7322 at all about the high-order bits. */
7323 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7331 #ifdef POINTERS_EXTEND_UNSIGNED
7332 /* If pointers extend signed and this is a pointer in Pmode, say that
7333 all the bits above ptr_mode are known to be sign bit copies. */
7334 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7335 && REGNO_POINTER_FLAG (REGNO (x)))
7336 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7339 if (reg_last_set_value[REGNO (x)] != 0
7340 && reg_last_set_mode[REGNO (x)] == mode
7341 && (reg_n_sets[REGNO (x)] == 1
7342 || reg_last_set_label[REGNO (x)] == label_tick)
7343 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7344 return reg_last_set_sign_bit_copies[REGNO (x)];
7346 tem = get_last_value (x);
7348 return num_sign_bit_copies (tem, mode);
7350 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7351 return reg_sign_bit_copies[REGNO (x)];
7355 #ifdef LOAD_EXTEND_OP
7356 /* Some RISC machines sign-extend all loads of smaller than a word. */
7357 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7358 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7363 /* If the constant is negative, take its 1's complement and remask.
7364 Then see how many zero bits we have. */
7365 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7366 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7367 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7368 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7370 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7373 /* If this is a SUBREG for a promoted object that is sign-extended
7374 and we are looking at it in a wider mode, we know that at least the
7375 high-order bits are known to be sign bit copies. */
7377 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7378 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7379 num_sign_bit_copies (SUBREG_REG (x), mode));
7381 /* For a smaller object, just ignore the high bits. */
7382 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7384 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7385 return MAX (1, (num0
7386 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7390 #ifdef WORD_REGISTER_OPERATIONS
7391 #ifdef LOAD_EXTEND_OP
7392 /* For paradoxical SUBREGs on machines where all register operations
7393 affect the entire register, just look inside. Note that we are
7394 passing MODE to the recursive call, so the number of sign bit copies
7395 will remain relative to that mode, not the inner mode. */
7397 /* This works only if loads sign extend. Otherwise, if we get a
7398 reload for the inner part, it may be loaded from the stack, and
7399 then we lose all sign bit copies that existed before the store
7402 if ((GET_MODE_SIZE (GET_MODE (x))
7403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7404 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7405 return num_sign_bit_copies (SUBREG_REG (x), mode);
7411 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7412 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7416 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7417 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7420 /* For a smaller object, just ignore the high bits. */
7421 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7422 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7426 return num_sign_bit_copies (XEXP (x, 0), mode);
7428 case ROTATE: case ROTATERT:
7429 /* If we are rotating left by a number of bits less than the number
7430 of sign bit copies, we can just subtract that amount from the
7432 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7433 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7435 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7436 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7437 : bitwidth - INTVAL (XEXP (x, 1))));
7442 /* In general, this subtracts one sign bit copy. But if the value
7443 is known to be positive, the number of sign bit copies is the
7444 same as that of the input. Finally, if the input has just one bit
7445 that might be nonzero, all the bits are copies of the sign bit. */
7446 nonzero = nonzero_bits (XEXP (x, 0), mode);
7450 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7452 && bitwidth <= HOST_BITS_PER_WIDE_INT
7453 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7458 case IOR: case AND: case XOR:
7459 case SMIN: case SMAX: case UMIN: case UMAX:
7460 /* Logical operations will preserve the number of sign-bit copies.
7461 MIN and MAX operations always return one of the operands. */
7462 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7463 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7464 return MIN (num0, num1);
7466 case PLUS: case MINUS:
7467 /* For addition and subtraction, we can have a 1-bit carry. However,
7468 if we are subtracting 1 from a positive number, there will not
7469 be such a carry. Furthermore, if the positive number is known to
7470 be 0 or 1, we know the result is either -1 or 0. */
7472 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7473 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7475 nonzero = nonzero_bits (XEXP (x, 0), mode);
7476 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7477 return (nonzero == 1 || nonzero == 0 ? bitwidth
7478 : bitwidth - floor_log2 (nonzero) - 1);
7481 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7482 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7483 return MAX (1, MIN (num0, num1) - 1);
7486 /* The number of bits of the product is the sum of the number of
7487 bits of both terms. However, unless one of the terms if known
7488 to be positive, we must allow for an additional bit since negating
7489 a negative number can remove one sign bit copy. */
7491 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7492 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7494 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7496 && bitwidth <= HOST_BITS_PER_WIDE_INT
7497 && ((nonzero_bits (XEXP (x, 0), mode)
7498 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7499 && ((nonzero_bits (XEXP (x, 1), mode)
7500 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7503 return MAX (1, result);
7506 /* The result must be <= the first operand. */
7507 return num_sign_bit_copies (XEXP (x, 0), mode);
7510 /* The result must be <= the scond operand. */
7511 return num_sign_bit_copies (XEXP (x, 1), mode);
7514 /* Similar to unsigned division, except that we have to worry about
7515 the case where the divisor is negative, in which case we have
7517 result = num_sign_bit_copies (XEXP (x, 0), mode);
7519 && bitwidth <= HOST_BITS_PER_WIDE_INT
7520 && (nonzero_bits (XEXP (x, 1), mode)
7521 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7527 result = num_sign_bit_copies (XEXP (x, 1), mode);
7529 && bitwidth <= HOST_BITS_PER_WIDE_INT
7530 && (nonzero_bits (XEXP (x, 1), mode)
7531 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7537 /* Shifts by a constant add to the number of bits equal to the
7539 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7540 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7541 && INTVAL (XEXP (x, 1)) > 0)
7542 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7547 /* Left shifts destroy copies. */
7548 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7549 || INTVAL (XEXP (x, 1)) < 0
7550 || INTVAL (XEXP (x, 1)) >= bitwidth)
7553 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7554 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7557 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7558 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7559 return MIN (num0, num1);
7561 #if STORE_FLAG_VALUE == -1
7562 case EQ: case NE: case GE: case GT: case LE: case LT:
7563 case GEU: case GTU: case LEU: case LTU:
7568 /* If we haven't been able to figure it out by one of the above rules,
7569 see if some of the high-order bits are known to be zero. If so,
7570 count those bits and return one less than that amount. If we can't
7571 safely compute the mask for this mode, always return BITWIDTH. */
7573 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7576 nonzero = nonzero_bits (x, mode);
7577 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7578 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7581 /* Return the number of "extended" bits there are in X, when interpreted
7582 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7583 unsigned quantities, this is the number of high-order zero bits.
7584 For signed quantities, this is the number of copies of the sign bit
7585 minus 1. In both case, this function returns the number of "spare"
7586 bits. For example, if two quantities for which this function returns
7587 at least 1 are added, the addition is known not to overflow.
7589 This function will always return 0 unless called during combine, which
7590 implies that it must be called from a define_split. */
7593 extended_count (x, mode, unsignedp)
7595 enum machine_mode mode;
7598 if (nonzero_sign_valid == 0)
7602 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7603 && (GET_MODE_BITSIZE (mode) - 1
7604 - floor_log2 (nonzero_bits (x, mode))))
7605 : num_sign_bit_copies (x, mode) - 1);
7608 /* This function is called from `simplify_shift_const' to merge two
7609 outer operations. Specifically, we have already found that we need
7610 to perform operation *POP0 with constant *PCONST0 at the outermost
7611 position. We would now like to also perform OP1 with constant CONST1
7612 (with *POP0 being done last).
7614 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7615 the resulting operation. *PCOMP_P is set to 1 if we would need to
7616 complement the innermost operand, otherwise it is unchanged.
7618 MODE is the mode in which the operation will be done. No bits outside
7619 the width of this mode matter. It is assumed that the width of this mode
7620 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7622 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7623 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7624 result is simply *PCONST0.
7626 If the resulting operation cannot be expressed as one operation, we
7627 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7630 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7631 enum rtx_code *pop0;
7632 HOST_WIDE_INT *pconst0;
7634 HOST_WIDE_INT const1;
7635 enum machine_mode mode;
7638 enum rtx_code op0 = *pop0;
7639 HOST_WIDE_INT const0 = *pconst0;
7640 int width = GET_MODE_BITSIZE (mode);
7642 const0 &= GET_MODE_MASK (mode);
7643 const1 &= GET_MODE_MASK (mode);
7645 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7649 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7652 if (op1 == NIL || op0 == SET)
7655 else if (op0 == NIL)
7656 op0 = op1, const0 = const1;
7658 else if (op0 == op1)
7680 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7681 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7684 /* If the two constants aren't the same, we can't do anything. The
7685 remaining six cases can all be done. */
7686 else if (const0 != const1)
7694 /* (a & b) | b == b */
7696 else /* op1 == XOR */
7697 /* (a ^ b) | b == a | b */
7703 /* (a & b) ^ b == (~a) & b */
7704 op0 = AND, *pcomp_p = 1;
7705 else /* op1 == IOR */
7706 /* (a | b) ^ b == a & ~b */
7707 op0 = AND, *pconst0 = ~ const0;
7712 /* (a | b) & b == b */
7714 else /* op1 == XOR */
7715 /* (a ^ b) & b) == (~a) & b */
7720 /* Check for NO-OP cases. */
7721 const0 &= GET_MODE_MASK (mode);
7723 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7725 else if (const0 == 0 && op0 == AND)
7727 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7730 /* If this would be an entire word for the target, but is not for
7731 the host, then sign-extend on the host so that the number will look
7732 the same way on the host that it would on the target.
7734 For example, when building a 64 bit alpha hosted 32 bit sparc
7735 targeted compiler, then we want the 32 bit unsigned value -1 to be
7736 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7737 The later confuses the sparc backend. */
7739 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7740 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7741 const0 |= ((HOST_WIDE_INT) (-1) << width);
7749 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7750 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7751 that we started with.
7753 The shift is normally computed in the widest mode we find in VAROP, as
7754 long as it isn't a different number of words than RESULT_MODE. Exceptions
7755 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7758 simplify_shift_const (x, code, result_mode, varop, count)
7761 enum machine_mode result_mode;
7765 enum rtx_code orig_code = code;
7766 int orig_count = count;
7767 enum machine_mode mode = result_mode;
7768 enum machine_mode shift_mode, tmode;
7770 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7771 /* We form (outer_op (code varop count) (outer_const)). */
7772 enum rtx_code outer_op = NIL;
7773 HOST_WIDE_INT outer_const = 0;
7775 int complement_p = 0;
7778 /* If we were given an invalid count, don't do anything except exactly
7779 what was requested. */
7781 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7786 return gen_rtx (code, mode, varop, GEN_INT (count));
7789 /* Unless one of the branches of the `if' in this loop does a `continue',
7790 we will `break' the loop after the `if'. */
7794 /* If we have an operand of (clobber (const_int 0)), just return that
7796 if (GET_CODE (varop) == CLOBBER)
7799 /* If we discovered we had to complement VAROP, leave. Making a NOT
7800 here would cause an infinite loop. */
7804 /* Convert ROTATERT to ROTATE. */
7805 if (code == ROTATERT)
7806 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7808 /* We need to determine what mode we will do the shift in. If the
7809 shift is a right shift or a ROTATE, we must always do it in the mode
7810 it was originally done in. Otherwise, we can do it in MODE, the
7811 widest mode encountered. */
7813 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
7814 ? result_mode : mode);
7816 /* Handle cases where the count is greater than the size of the mode
7817 minus 1. For ASHIFT, use the size minus one as the count (this can
7818 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7819 take the count modulo the size. For other shifts, the result is
7822 Since these shifts are being produced by the compiler by combining
7823 multiple operations, each of which are defined, we know what the
7824 result is supposed to be. */
7826 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7828 if (code == ASHIFTRT)
7829 count = GET_MODE_BITSIZE (shift_mode) - 1;
7830 else if (code == ROTATE || code == ROTATERT)
7831 count %= GET_MODE_BITSIZE (shift_mode);
7834 /* We can't simply return zero because there may be an
7842 /* Negative counts are invalid and should not have been made (a
7843 programmer-specified negative count should have been handled
7848 /* An arithmetic right shift of a quantity known to be -1 or 0
7850 if (code == ASHIFTRT
7851 && (num_sign_bit_copies (varop, shift_mode)
7852 == GET_MODE_BITSIZE (shift_mode)))
7858 /* If we are doing an arithmetic right shift and discarding all but
7859 the sign bit copies, this is equivalent to doing a shift by the
7860 bitsize minus one. Convert it into that shift because it will often
7861 allow other simplifications. */
7863 if (code == ASHIFTRT
7864 && (count + num_sign_bit_copies (varop, shift_mode)
7865 >= GET_MODE_BITSIZE (shift_mode)))
7866 count = GET_MODE_BITSIZE (shift_mode) - 1;
7868 /* We simplify the tests below and elsewhere by converting
7869 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7870 `make_compound_operation' will convert it to a ASHIFTRT for
7871 those machines (such as Vax) that don't have a LSHIFTRT. */
7872 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7874 && ((nonzero_bits (varop, shift_mode)
7875 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7879 switch (GET_CODE (varop))
7885 new = expand_compound_operation (varop);
7894 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7895 minus the width of a smaller mode, we can do this with a
7896 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7897 if ((code == ASHIFTRT || code == LSHIFTRT)
7898 && ! mode_dependent_address_p (XEXP (varop, 0))
7899 && ! MEM_VOLATILE_P (varop)
7900 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7901 MODE_INT, 1)) != BLKmode)
7903 if (BYTES_BIG_ENDIAN)
7904 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7906 new = gen_rtx (MEM, tmode,
7907 plus_constant (XEXP (varop, 0),
7908 count / BITS_PER_UNIT));
7909 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7910 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7911 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7912 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7913 : ZERO_EXTEND, mode, new);
7920 /* Similar to the case above, except that we can only do this if
7921 the resulting mode is the same as that of the underlying
7922 MEM and adjust the address depending on the *bits* endianness
7923 because of the way that bit-field extract insns are defined. */
7924 if ((code == ASHIFTRT || code == LSHIFTRT)
7925 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7926 MODE_INT, 1)) != BLKmode
7927 && tmode == GET_MODE (XEXP (varop, 0)))
7929 if (BITS_BIG_ENDIAN)
7930 new = XEXP (varop, 0);
7933 new = copy_rtx (XEXP (varop, 0));
7934 SUBST (XEXP (new, 0),
7935 plus_constant (XEXP (new, 0),
7936 count / BITS_PER_UNIT));
7939 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7940 : ZERO_EXTEND, mode, new);
7947 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7948 the same number of words as what we've seen so far. Then store
7949 the widest mode in MODE. */
7950 if (subreg_lowpart_p (varop)
7951 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7952 > GET_MODE_SIZE (GET_MODE (varop)))
7953 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7954 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7957 varop = SUBREG_REG (varop);
7958 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7959 mode = GET_MODE (varop);
7965 /* Some machines use MULT instead of ASHIFT because MULT
7966 is cheaper. But it is still better on those machines to
7967 merge two shifts into one. */
7968 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7969 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7971 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7972 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7978 /* Similar, for when divides are cheaper. */
7979 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7980 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7982 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7983 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7989 /* If we are extracting just the sign bit of an arithmetic right
7990 shift, that shift is not needed. */
7991 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7993 varop = XEXP (varop, 0);
7997 /* ... fall through ... */
8002 /* Here we have two nested shifts. The result is usually the
8003 AND of a new shift with a mask. We compute the result below. */
8004 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8005 && INTVAL (XEXP (varop, 1)) >= 0
8006 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8007 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8008 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8010 enum rtx_code first_code = GET_CODE (varop);
8011 int first_count = INTVAL (XEXP (varop, 1));
8012 unsigned HOST_WIDE_INT mask;
8015 /* We have one common special case. We can't do any merging if
8016 the inner code is an ASHIFTRT of a smaller mode. However, if
8017 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8018 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8019 we can convert it to
8020 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8021 This simplifies certain SIGN_EXTEND operations. */
8022 if (code == ASHIFT && first_code == ASHIFTRT
8023 && (GET_MODE_BITSIZE (result_mode)
8024 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8026 /* C3 has the low-order C1 bits zero. */
8028 mask = (GET_MODE_MASK (mode)
8029 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8031 varop = simplify_and_const_int (NULL_RTX, result_mode,
8032 XEXP (varop, 0), mask);
8033 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8035 count = first_count;
8040 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8041 than C1 high-order bits equal to the sign bit, we can convert
8042 this to either an ASHIFT or a ASHIFTRT depending on the
8045 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8047 if (code == ASHIFTRT && first_code == ASHIFT
8048 && GET_MODE (varop) == shift_mode
8049 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8052 count -= first_count;
8054 count = - count, code = ASHIFT;
8055 varop = XEXP (varop, 0);
8059 /* There are some cases we can't do. If CODE is ASHIFTRT,
8060 we can only do this if FIRST_CODE is also ASHIFTRT.
8062 We can't do the case when CODE is ROTATE and FIRST_CODE is
8065 If the mode of this shift is not the mode of the outer shift,
8066 we can't do this if either shift is a right shift or ROTATE.
8068 Finally, we can't do any of these if the mode is too wide
8069 unless the codes are the same.
8071 Handle the case where the shift codes are the same
8074 if (code == first_code)
8076 if (GET_MODE (varop) != result_mode
8077 && (code == ASHIFTRT || code == LSHIFTRT
8081 count += first_count;
8082 varop = XEXP (varop, 0);
8086 if (code == ASHIFTRT
8087 || (code == ROTATE && first_code == ASHIFTRT)
8088 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8089 || (GET_MODE (varop) != result_mode
8090 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8091 || first_code == ROTATE
8092 || code == ROTATE)))
8095 /* To compute the mask to apply after the shift, shift the
8096 nonzero bits of the inner shift the same way the
8097 outer shift will. */
8099 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8102 = simplify_binary_operation (code, result_mode, mask_rtx,
8105 /* Give up if we can't compute an outer operation to use. */
8107 || GET_CODE (mask_rtx) != CONST_INT
8108 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8110 result_mode, &complement_p))
8113 /* If the shifts are in the same direction, we add the
8114 counts. Otherwise, we subtract them. */
8115 if ((code == ASHIFTRT || code == LSHIFTRT)
8116 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8117 count += first_count;
8119 count -= first_count;
8121 /* If COUNT is positive, the new shift is usually CODE,
8122 except for the two exceptions below, in which case it is
8123 FIRST_CODE. If the count is negative, FIRST_CODE should
8126 && ((first_code == ROTATE && code == ASHIFT)
8127 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8130 code = first_code, count = - count;
8132 varop = XEXP (varop, 0);
8136 /* If we have (A << B << C) for any shift, we can convert this to
8137 (A << C << B). This wins if A is a constant. Only try this if
8138 B is not a constant. */
8140 else if (GET_CODE (varop) == code
8141 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8143 = simplify_binary_operation (code, mode,
8147 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8154 /* Make this fit the case below. */
8155 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8156 GEN_INT (GET_MODE_MASK (mode)));
8162 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8163 with C the size of VAROP - 1 and the shift is logical if
8164 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8165 we have an (le X 0) operation. If we have an arithmetic shift
8166 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8167 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8169 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8170 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8171 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8172 && (code == LSHIFTRT || code == ASHIFTRT)
8173 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8174 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8177 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8180 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8181 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8186 /* If we have (shift (logical)), move the logical to the outside
8187 to allow it to possibly combine with another logical and the
8188 shift to combine with another shift. This also canonicalizes to
8189 what a ZERO_EXTRACT looks like. Also, some machines have
8190 (and (shift)) insns. */
8192 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8193 && (new = simplify_binary_operation (code, result_mode,
8195 GEN_INT (count))) != 0
8196 && GET_CODE(new) == CONST_INT
8197 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8198 INTVAL (new), result_mode, &complement_p))
8200 varop = XEXP (varop, 0);
8204 /* If we can't do that, try to simplify the shift in each arm of the
8205 logical expression, make a new logical expression, and apply
8206 the inverse distributive law. */
8208 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8209 XEXP (varop, 0), count);
8210 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8211 XEXP (varop, 1), count);
8213 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8214 varop = apply_distributive_law (varop);
8221 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8222 says that the sign bit can be tested, FOO has mode MODE, C is
8223 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8224 that may be nonzero. */
8225 if (code == LSHIFTRT
8226 && XEXP (varop, 1) == const0_rtx
8227 && GET_MODE (XEXP (varop, 0)) == result_mode
8228 && count == GET_MODE_BITSIZE (result_mode) - 1
8229 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8230 && ((STORE_FLAG_VALUE
8231 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8232 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8233 && merge_outer_ops (&outer_op, &outer_const, XOR,
8234 (HOST_WIDE_INT) 1, result_mode,
8237 varop = XEXP (varop, 0);
8244 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8245 than the number of bits in the mode is equivalent to A. */
8246 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8247 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8249 varop = XEXP (varop, 0);
8254 /* NEG commutes with ASHIFT since it is multiplication. Move the
8255 NEG outside to allow shifts to combine. */
8257 && merge_outer_ops (&outer_op, &outer_const, NEG,
8258 (HOST_WIDE_INT) 0, result_mode,
8261 varop = XEXP (varop, 0);
8267 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8268 is one less than the number of bits in the mode is
8269 equivalent to (xor A 1). */
8270 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8271 && XEXP (varop, 1) == constm1_rtx
8272 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8273 && merge_outer_ops (&outer_op, &outer_const, XOR,
8274 (HOST_WIDE_INT) 1, result_mode,
8278 varop = XEXP (varop, 0);
8282 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8283 that might be nonzero in BAR are those being shifted out and those
8284 bits are known zero in FOO, we can replace the PLUS with FOO.
8285 Similarly in the other operand order. This code occurs when
8286 we are computing the size of a variable-size array. */
8288 if ((code == ASHIFTRT || code == LSHIFTRT)
8289 && count < HOST_BITS_PER_WIDE_INT
8290 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8291 && (nonzero_bits (XEXP (varop, 1), result_mode)
8292 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8294 varop = XEXP (varop, 0);
8297 else if ((code == ASHIFTRT || code == LSHIFTRT)
8298 && count < HOST_BITS_PER_WIDE_INT
8299 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8300 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8302 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8303 & nonzero_bits (XEXP (varop, 1),
8306 varop = XEXP (varop, 1);
8310 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8312 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8313 && (new = simplify_binary_operation (ASHIFT, result_mode,
8315 GEN_INT (count))) != 0
8316 && GET_CODE(new) == CONST_INT
8317 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8318 INTVAL (new), result_mode, &complement_p))
8320 varop = XEXP (varop, 0);
8326 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8327 with C the size of VAROP - 1 and the shift is logical if
8328 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8329 we have a (gt X 0) operation. If the shift is arithmetic with
8330 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8331 we have a (neg (gt X 0)) operation. */
8333 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8334 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8335 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8336 && (code == LSHIFTRT || code == ASHIFTRT)
8337 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8338 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8339 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8342 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8345 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8346 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8356 /* We need to determine what mode to do the shift in. If the shift is
8357 a right shift or ROTATE, we must always do it in the mode it was
8358 originally done in. Otherwise, we can do it in MODE, the widest mode
8359 encountered. The code we care about is that of the shift that will
8360 actually be done, not the shift that was originally requested. */
8362 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8363 ? result_mode : mode);
8365 /* We have now finished analyzing the shift. The result should be
8366 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8367 OUTER_OP is non-NIL, it is an operation that needs to be applied
8368 to the result of the shift. OUTER_CONST is the relevant constant,
8369 but we must turn off all bits turned off in the shift.
8371 If we were passed a value for X, see if we can use any pieces of
8372 it. If not, make new rtx. */
8374 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8375 && GET_CODE (XEXP (x, 1)) == CONST_INT
8376 && INTVAL (XEXP (x, 1)) == count)
8377 const_rtx = XEXP (x, 1);
8379 const_rtx = GEN_INT (count);
8381 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8382 && GET_MODE (XEXP (x, 0)) == shift_mode
8383 && SUBREG_REG (XEXP (x, 0)) == varop)
8384 varop = XEXP (x, 0);
8385 else if (GET_MODE (varop) != shift_mode)
8386 varop = gen_lowpart_for_combine (shift_mode, varop);
8388 /* If we can't make the SUBREG, try to return what we were given. */
8389 if (GET_CODE (varop) == CLOBBER)
8390 return x ? x : varop;
8392 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8397 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8398 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8400 SUBST (XEXP (x, 0), varop);
8401 SUBST (XEXP (x, 1), const_rtx);
8404 /* If we have an outer operation and we just made a shift, it is
8405 possible that we could have simplified the shift were it not
8406 for the outer operation. So try to do the simplification
8409 if (outer_op != NIL && GET_CODE (x) == code
8410 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8411 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8412 INTVAL (XEXP (x, 1)));
8414 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8415 turn off all the bits that the shift would have turned off. */
8416 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8417 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8418 GET_MODE_MASK (result_mode) >> orig_count);
8420 /* Do the remainder of the processing in RESULT_MODE. */
8421 x = gen_lowpart_for_combine (result_mode, x);
8423 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8426 x = gen_unary (NOT, result_mode, result_mode, x);
8428 if (outer_op != NIL)
8430 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8432 int width = GET_MODE_BITSIZE (result_mode);
8434 outer_const &= GET_MODE_MASK (result_mode);
8436 /* If this would be an entire word for the target, but is not for
8437 the host, then sign-extend on the host so that the number will
8438 look the same way on the host that it would on the target.
8440 For example, when building a 64 bit alpha hosted 32 bit sparc
8441 targeted compiler, then we want the 32 bit unsigned value -1 to be
8442 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8443 The later confuses the sparc backend. */
8445 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8446 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8447 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8450 if (outer_op == AND)
8451 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8452 else if (outer_op == SET)
8453 /* This means that we have determined that the result is
8454 equivalent to a constant. This should be rare. */
8455 x = GEN_INT (outer_const);
8456 else if (GET_RTX_CLASS (outer_op) == '1')
8457 x = gen_unary (outer_op, result_mode, result_mode, x);
8459 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8465 /* Like recog, but we receive the address of a pointer to a new pattern.
8466 We try to match the rtx that the pointer points to.
8467 If that fails, we may try to modify or replace the pattern,
8468 storing the replacement into the same pointer object.
8470 Modifications include deletion or addition of CLOBBERs.
8472 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8473 the CLOBBERs are placed.
8475 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8478 The value is the final insn code from the pattern ultimately matched,
8482 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8486 int *padded_scratches;
8488 register rtx pat = *pnewpat;
8489 int insn_code_number;
8490 int num_clobbers_to_add = 0;
8494 *padded_scratches = 0;
8496 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8497 we use to indicate that something didn't match. If we find such a
8498 thing, force rejection. */
8499 if (GET_CODE (pat) == PARALLEL)
8500 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8501 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8502 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8505 /* Is the result of combination a valid instruction? */
8506 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8508 /* If it isn't, there is the possibility that we previously had an insn
8509 that clobbered some register as a side effect, but the combined
8510 insn doesn't need to do that. So try once more without the clobbers
8511 unless this represents an ASM insn. */
8513 if (insn_code_number < 0 && ! check_asm_operands (pat)
8514 && GET_CODE (pat) == PARALLEL)
8518 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8519 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8522 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8526 SUBST_INT (XVECLEN (pat, 0), pos);
8529 pat = XVECEXP (pat, 0, 0);
8531 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8534 /* If we had any clobbers to add, make a new pattern than contains
8535 them. Then check to make sure that all of them are dead. */
8536 if (num_clobbers_to_add)
8538 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8539 gen_rtvec (GET_CODE (pat) == PARALLEL
8540 ? XVECLEN (pat, 0) + num_clobbers_to_add
8541 : num_clobbers_to_add + 1));
8543 if (GET_CODE (pat) == PARALLEL)
8544 for (i = 0; i < XVECLEN (pat, 0); i++)
8545 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8547 XVECEXP (newpat, 0, 0) = pat;
8549 add_clobbers (newpat, insn_code_number);
8551 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8552 i < XVECLEN (newpat, 0); i++)
8554 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8555 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8557 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8558 (*padded_scratches)++;
8559 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8560 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8568 return insn_code_number;
8571 /* Like gen_lowpart but for use by combine. In combine it is not possible
8572 to create any new pseudoregs. However, it is safe to create
8573 invalid memory addresses, because combine will try to recognize
8574 them and all they will do is make the combine attempt fail.
8576 If for some reason this cannot do its job, an rtx
8577 (clobber (const_int 0)) is returned.
8578 An insn containing that will not be recognized. */
8583 gen_lowpart_for_combine (mode, x)
8584 enum machine_mode mode;
8589 if (GET_MODE (x) == mode)
8592 /* We can only support MODE being wider than a word if X is a
8593 constant integer or has a mode the same size. */
8595 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8596 && ! ((GET_MODE (x) == VOIDmode
8597 && (GET_CODE (x) == CONST_INT
8598 || GET_CODE (x) == CONST_DOUBLE))
8599 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8600 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8602 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8603 won't know what to do. So we will strip off the SUBREG here and
8604 process normally. */
8605 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8608 if (GET_MODE (x) == mode)
8612 result = gen_lowpart_common (mode, x);
8614 && GET_CODE (result) == SUBREG
8615 && GET_CODE (SUBREG_REG (result)) == REG
8616 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8617 && (GET_MODE_SIZE (GET_MODE (result))
8618 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8619 reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
8624 if (GET_CODE (x) == MEM)
8626 register int offset = 0;
8629 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8631 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8632 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8634 /* If we want to refer to something bigger than the original memref,
8635 generate a perverse subreg instead. That will force a reload
8636 of the original memref X. */
8637 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8638 return gen_rtx (SUBREG, mode, x, 0);
8640 if (WORDS_BIG_ENDIAN)
8641 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8642 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8643 if (BYTES_BIG_ENDIAN)
8645 /* Adjust the address so that the address-after-the-data is
8647 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8648 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8650 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8651 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8652 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8653 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8657 /* If X is a comparison operator, rewrite it in a new mode. This
8658 probably won't match, but may allow further simplifications. */
8659 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8660 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8662 /* If we couldn't simplify X any other way, just enclose it in a
8663 SUBREG. Normally, this SUBREG won't match, but some patterns may
8664 include an explicit SUBREG or we may simplify it further in combine. */
8669 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8670 word = ((GET_MODE_SIZE (GET_MODE (x))
8671 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8673 return gen_rtx (SUBREG, mode, x, word);
8677 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8678 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8680 If the identical expression was previously in the insn (in the undobuf),
8681 it will be returned. Only if it is not found will a new expression
8686 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8690 enum machine_mode mode;
8702 code = va_arg (p, enum rtx_code);
8703 mode = va_arg (p, enum machine_mode);
8706 n_args = GET_RTX_LENGTH (code);
8707 fmt = GET_RTX_FORMAT (code);
8709 if (n_args == 0 || n_args > 3)
8712 /* Get each arg and verify that it is supposed to be an expression. */
8713 for (j = 0; j < n_args; j++)
8718 args[j] = va_arg (p, rtx);
8721 /* See if this is in undobuf. Be sure we don't use objects that came
8722 from another insn; this could produce circular rtl structures. */
8724 for (i = previous_num_undos; i < undobuf.num_undo; i++)
8725 if (!undobuf.undo[i].is_int
8726 && GET_CODE (undobuf.undo[i].old_contents.r) == code
8727 && GET_MODE (undobuf.undo[i].old_contents.r) == mode)
8729 for (j = 0; j < n_args; j++)
8730 if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j])
8734 return undobuf.undo[i].old_contents.r;
8737 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8738 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8739 rt = rtx_alloc (code);
8740 PUT_MODE (rt, mode);
8741 XEXP (rt, 0) = args[0];
8744 XEXP (rt, 1) = args[1];
8746 XEXP (rt, 2) = args[2];
8751 /* These routines make binary and unary operations by first seeing if they
8752 fold; if not, a new expression is allocated. */
8755 gen_binary (code, mode, op0, op1)
8757 enum machine_mode mode;
8763 if (GET_RTX_CLASS (code) == 'c'
8764 && (GET_CODE (op0) == CONST_INT
8765 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8766 tem = op0, op0 = op1, op1 = tem;
8768 if (GET_RTX_CLASS (code) == '<')
8770 enum machine_mode op_mode = GET_MODE (op0);
8772 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8773 just (REL_OP X Y). */
8774 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8776 op1 = XEXP (op0, 1);
8777 op0 = XEXP (op0, 0);
8778 op_mode = GET_MODE (op0);
8781 if (op_mode == VOIDmode)
8782 op_mode = GET_MODE (op1);
8783 result = simplify_relational_operation (code, op_mode, op0, op1);
8786 result = simplify_binary_operation (code, mode, op0, op1);
8791 /* Put complex operands first and constants second. */
8792 if (GET_RTX_CLASS (code) == 'c'
8793 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8794 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8795 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8796 || (GET_CODE (op0) == SUBREG
8797 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8798 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8799 return gen_rtx_combine (code, mode, op1, op0);
8801 return gen_rtx_combine (code, mode, op0, op1);
8805 gen_unary (code, mode, op0_mode, op0)
8807 enum machine_mode mode, op0_mode;
8810 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
8815 return gen_rtx_combine (code, mode, op0);
8818 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8819 comparison code that will be tested.
8821 The result is a possibly different comparison code to use. *POP0 and
8822 *POP1 may be updated.
8824 It is possible that we might detect that a comparison is either always
8825 true or always false. However, we do not perform general constant
8826 folding in combine, so this knowledge isn't useful. Such tautologies
8827 should have been detected earlier. Hence we ignore all such cases. */
8829 static enum rtx_code
8830 simplify_comparison (code, pop0, pop1)
8839 enum machine_mode mode, tmode;
8841 /* Try a few ways of applying the same transformation to both operands. */
8844 #ifndef WORD_REGISTER_OPERATIONS
8845 /* The test below this one won't handle SIGN_EXTENDs on these machines,
8846 so check specially. */
8847 if (code != GTU && code != GEU && code != LTU && code != LEU
8848 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
8849 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8850 && GET_CODE (XEXP (op1, 0)) == ASHIFT
8851 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
8852 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
8853 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
8854 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
8855 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8856 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8857 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8858 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
8859 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
8860 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
8861 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
8862 && (INTVAL (XEXP (op0, 1))
8863 == (GET_MODE_BITSIZE (GET_MODE (op0))
8865 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
8867 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
8868 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
8872 /* If both operands are the same constant shift, see if we can ignore the
8873 shift. We can if the shift is a rotate or if the bits shifted out of
8874 this shift are known to be zero for both inputs and if the type of
8875 comparison is compatible with the shift. */
8876 if (GET_CODE (op0) == GET_CODE (op1)
8877 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8878 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8879 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
8880 && (code != GT && code != LT && code != GE && code != LE))
8881 || (GET_CODE (op0) == ASHIFTRT
8882 && (code != GTU && code != LTU
8883 && code != GEU && code != GEU)))
8884 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8885 && INTVAL (XEXP (op0, 1)) >= 0
8886 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8887 && XEXP (op0, 1) == XEXP (op1, 1))
8889 enum machine_mode mode = GET_MODE (op0);
8890 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8891 int shift_count = INTVAL (XEXP (op0, 1));
8893 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8894 mask &= (mask >> shift_count) << shift_count;
8895 else if (GET_CODE (op0) == ASHIFT)
8896 mask = (mask & (mask << shift_count)) >> shift_count;
8898 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8899 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8900 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8905 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8906 SUBREGs are of the same mode, and, in both cases, the AND would
8907 be redundant if the comparison was done in the narrower mode,
8908 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8909 and the operand's possibly nonzero bits are 0xffffff01; in that case
8910 if we only care about QImode, we don't need the AND). This case
8911 occurs if the output mode of an scc insn is not SImode and
8912 STORE_FLAG_VALUE == 1 (e.g., the 386).
8914 Similarly, check for a case where the AND's are ZERO_EXTEND
8915 operations from some narrower mode even though a SUBREG is not
8918 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8919 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8920 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
8922 rtx inner_op0 = XEXP (op0, 0);
8923 rtx inner_op1 = XEXP (op1, 0);
8924 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
8925 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
8928 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
8929 && (GET_MODE_SIZE (GET_MODE (inner_op0))
8930 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
8931 && (GET_MODE (SUBREG_REG (inner_op0))
8932 == GET_MODE (SUBREG_REG (inner_op1)))
8933 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8934 <= HOST_BITS_PER_WIDE_INT)
8935 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
8936 GET_MODE (SUBREG_REG (op0)))))
8937 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
8938 GET_MODE (SUBREG_REG (inner_op1))))))
8940 op0 = SUBREG_REG (inner_op0);
8941 op1 = SUBREG_REG (inner_op1);
8943 /* The resulting comparison is always unsigned since we masked
8944 off the original sign bit. */
8945 code = unsigned_condition (code);
8951 for (tmode = GET_CLASS_NARROWEST_MODE
8952 (GET_MODE_CLASS (GET_MODE (op0)));
8953 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
8954 if (c0 == GET_MODE_MASK (tmode))
8956 op0 = gen_lowpart_for_combine (tmode, inner_op0);
8957 op1 = gen_lowpart_for_combine (tmode, inner_op1);
8958 code = unsigned_condition (code);
8967 /* If both operands are NOT, we can strip off the outer operation
8968 and adjust the comparison code for swapped operands; similarly for
8969 NEG, except that this must be an equality comparison. */
8970 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
8971 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
8972 && (code == EQ || code == NE)))
8973 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
8979 /* If the first operand is a constant, swap the operands and adjust the
8980 comparison code appropriately. */
8981 if (CONSTANT_P (op0))
8983 tem = op0, op0 = op1, op1 = tem;
8984 code = swap_condition (code);
8987 /* We now enter a loop during which we will try to simplify the comparison.
8988 For the most part, we only are concerned with comparisons with zero,
8989 but some things may really be comparisons with zero but not start
8990 out looking that way. */
8992 while (GET_CODE (op1) == CONST_INT)
8994 enum machine_mode mode = GET_MODE (op0);
8995 int mode_width = GET_MODE_BITSIZE (mode);
8996 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8997 int equality_comparison_p;
8998 int sign_bit_comparison_p;
8999 int unsigned_comparison_p;
9000 HOST_WIDE_INT const_op;
9002 /* We only want to handle integral modes. This catches VOIDmode,
9003 CCmode, and the floating-point modes. An exception is that we
9004 can handle VOIDmode if OP0 is a COMPARE or a comparison
9007 if (GET_MODE_CLASS (mode) != MODE_INT
9008 && ! (mode == VOIDmode
9009 && (GET_CODE (op0) == COMPARE
9010 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9013 /* Get the constant we are comparing against and turn off all bits
9014 not on in our mode. */
9015 const_op = INTVAL (op1);
9016 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9019 /* If we are comparing against a constant power of two and the value
9020 being compared can only have that single bit nonzero (e.g., it was
9021 `and'ed with that bit), we can replace this with a comparison
9024 && (code == EQ || code == NE || code == GE || code == GEU
9025 || code == LT || code == LTU)
9026 && mode_width <= HOST_BITS_PER_WIDE_INT
9027 && exact_log2 (const_op) >= 0
9028 && nonzero_bits (op0, mode) == const_op)
9030 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9031 op1 = const0_rtx, const_op = 0;
9034 /* Similarly, if we are comparing a value known to be either -1 or
9035 0 with -1, change it to the opposite comparison against zero. */
9038 && (code == EQ || code == NE || code == GT || code == LE
9039 || code == GEU || code == LTU)
9040 && num_sign_bit_copies (op0, mode) == mode_width)
9042 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9043 op1 = const0_rtx, const_op = 0;
9046 /* Do some canonicalizations based on the comparison code. We prefer
9047 comparisons against zero and then prefer equality comparisons.
9048 If we can reduce the size of a constant, we will do that too. */
9053 /* < C is equivalent to <= (C - 1) */
9057 op1 = GEN_INT (const_op);
9059 /* ... fall through to LE case below. */
9065 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9069 op1 = GEN_INT (const_op);
9073 /* If we are doing a <= 0 comparison on a value known to have
9074 a zero sign bit, we can replace this with == 0. */
9075 else if (const_op == 0
9076 && mode_width <= HOST_BITS_PER_WIDE_INT
9077 && (nonzero_bits (op0, mode)
9078 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9083 /* >= C is equivalent to > (C - 1). */
9087 op1 = GEN_INT (const_op);
9089 /* ... fall through to GT below. */
9095 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9099 op1 = GEN_INT (const_op);
9103 /* If we are doing a > 0 comparison on a value known to have
9104 a zero sign bit, we can replace this with != 0. */
9105 else if (const_op == 0
9106 && mode_width <= HOST_BITS_PER_WIDE_INT
9107 && (nonzero_bits (op0, mode)
9108 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9113 /* < C is equivalent to <= (C - 1). */
9117 op1 = GEN_INT (const_op);
9119 /* ... fall through ... */
9122 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9123 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9125 const_op = 0, op1 = const0_rtx;
9133 /* unsigned <= 0 is equivalent to == 0 */
9137 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9138 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9140 const_op = 0, op1 = const0_rtx;
9146 /* >= C is equivalent to < (C - 1). */
9150 op1 = GEN_INT (const_op);
9152 /* ... fall through ... */
9155 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9156 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9158 const_op = 0, op1 = const0_rtx;
9166 /* unsigned > 0 is equivalent to != 0 */
9170 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9171 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9173 const_op = 0, op1 = const0_rtx;
9179 /* Compute some predicates to simplify code below. */
9181 equality_comparison_p = (code == EQ || code == NE);
9182 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9183 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9186 /* If this is a sign bit comparison and we can do arithmetic in
9187 MODE, say that we will only be needing the sign bit of OP0. */
9188 if (sign_bit_comparison_p
9189 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9190 op0 = force_to_mode (op0, mode,
9192 << (GET_MODE_BITSIZE (mode) - 1)),
9195 /* Now try cases based on the opcode of OP0. If none of the cases
9196 does a "continue", we exit this loop immediately after the
9199 switch (GET_CODE (op0))
9202 /* If we are extracting a single bit from a variable position in
9203 a constant that has only a single bit set and are comparing it
9204 with zero, we can convert this into an equality comparison
9205 between the position and the location of the single bit. */
9207 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9208 && XEXP (op0, 1) == const1_rtx
9209 && equality_comparison_p && const_op == 0
9210 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9212 if (BITS_BIG_ENDIAN)
9214 i = (GET_MODE_BITSIZE
9215 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9217 i = BITS_PER_WORD - 1 - i;
9220 op0 = XEXP (op0, 2);
9224 /* Result is nonzero iff shift count is equal to I. */
9225 code = reverse_condition (code);
9229 /* ... fall through ... */
9232 tem = expand_compound_operation (op0);
9241 /* If testing for equality, we can take the NOT of the constant. */
9242 if (equality_comparison_p
9243 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9245 op0 = XEXP (op0, 0);
9250 /* If just looking at the sign bit, reverse the sense of the
9252 if (sign_bit_comparison_p)
9254 op0 = XEXP (op0, 0);
9255 code = (code == GE ? LT : GE);
9261 /* If testing for equality, we can take the NEG of the constant. */
9262 if (equality_comparison_p
9263 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9265 op0 = XEXP (op0, 0);
9270 /* The remaining cases only apply to comparisons with zero. */
9274 /* When X is ABS or is known positive,
9275 (neg X) is < 0 if and only if X != 0. */
9277 if (sign_bit_comparison_p
9278 && (GET_CODE (XEXP (op0, 0)) == ABS
9279 || (mode_width <= HOST_BITS_PER_WIDE_INT
9280 && (nonzero_bits (XEXP (op0, 0), mode)
9281 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9283 op0 = XEXP (op0, 0);
9284 code = (code == LT ? NE : EQ);
9288 /* If we have NEG of something whose two high-order bits are the
9289 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9290 if (num_sign_bit_copies (op0, mode) >= 2)
9292 op0 = XEXP (op0, 0);
9293 code = swap_condition (code);
9299 /* If we are testing equality and our count is a constant, we
9300 can perform the inverse operation on our RHS. */
9301 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9302 && (tem = simplify_binary_operation (ROTATERT, mode,
9303 op1, XEXP (op0, 1))) != 0)
9305 op0 = XEXP (op0, 0);
9310 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9311 a particular bit. Convert it to an AND of a constant of that
9312 bit. This will be converted into a ZERO_EXTRACT. */
9313 if (const_op == 0 && sign_bit_comparison_p
9314 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9315 && mode_width <= HOST_BITS_PER_WIDE_INT)
9317 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9320 - INTVAL (XEXP (op0, 1)))));
9321 code = (code == LT ? NE : EQ);
9325 /* ... fall through ... */
9328 /* ABS is ignorable inside an equality comparison with zero. */
9329 if (const_op == 0 && equality_comparison_p)
9331 op0 = XEXP (op0, 0);
9338 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9339 to (compare FOO CONST) if CONST fits in FOO's mode and we
9340 are either testing inequality or have an unsigned comparison
9341 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9342 if (! unsigned_comparison_p
9343 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9344 <= HOST_BITS_PER_WIDE_INT)
9345 && ((unsigned HOST_WIDE_INT) const_op
9346 < (((HOST_WIDE_INT) 1
9347 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9349 op0 = XEXP (op0, 0);
9355 /* Check for the case where we are comparing A - C1 with C2,
9356 both constants are smaller than 1/2 the maximum positive
9357 value in MODE, and the comparison is equality or unsigned.
9358 In that case, if A is either zero-extended to MODE or has
9359 sufficient sign bits so that the high-order bit in MODE
9360 is a copy of the sign in the inner mode, we can prove that it is
9361 safe to do the operation in the wider mode. This simplifies
9362 many range checks. */
9364 if (mode_width <= HOST_BITS_PER_WIDE_INT
9365 && subreg_lowpart_p (op0)
9366 && GET_CODE (SUBREG_REG (op0)) == PLUS
9367 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9368 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9369 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9370 < GET_MODE_MASK (mode) / 2)
9371 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9372 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9373 GET_MODE (SUBREG_REG (op0)))
9374 & ~ GET_MODE_MASK (mode))
9375 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9376 GET_MODE (SUBREG_REG (op0)))
9377 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9378 - GET_MODE_BITSIZE (mode)))))
9380 op0 = SUBREG_REG (op0);
9384 /* If the inner mode is narrower and we are extracting the low part,
9385 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9386 if (subreg_lowpart_p (op0)
9387 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9388 /* Fall through */ ;
9392 /* ... fall through ... */
9395 if ((unsigned_comparison_p || equality_comparison_p)
9396 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9397 <= HOST_BITS_PER_WIDE_INT)
9398 && ((unsigned HOST_WIDE_INT) const_op
9399 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9401 op0 = XEXP (op0, 0);
9407 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9408 this for equality comparisons due to pathological cases involving
9410 if (equality_comparison_p
9411 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9412 op1, XEXP (op0, 1))))
9414 op0 = XEXP (op0, 0);
9419 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9420 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9421 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9423 op0 = XEXP (XEXP (op0, 0), 0);
9424 code = (code == LT ? EQ : NE);
9430 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9431 (eq B (minus A C)), whichever simplifies. We can only do
9432 this for equality comparisons due to pathological cases involving
9434 if (equality_comparison_p
9435 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9436 XEXP (op0, 1), op1)))
9438 op0 = XEXP (op0, 0);
9443 if (equality_comparison_p
9444 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9445 XEXP (op0, 0), op1)))
9447 op0 = XEXP (op0, 1);
9452 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9453 of bits in X minus 1, is one iff X > 0. */
9454 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9455 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9456 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9457 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9459 op0 = XEXP (op0, 1);
9460 code = (code == GE ? LE : GT);
9466 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9467 if C is zero or B is a constant. */
9468 if (equality_comparison_p
9469 && 0 != (tem = simplify_binary_operation (XOR, mode,
9470 XEXP (op0, 1), op1)))
9472 op0 = XEXP (op0, 0);
9479 case LT: case LTU: case LE: case LEU:
9480 case GT: case GTU: case GE: case GEU:
9481 /* We can't do anything if OP0 is a condition code value, rather
9482 than an actual data value. */
9485 || XEXP (op0, 0) == cc0_rtx
9487 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9490 /* Get the two operands being compared. */
9491 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9492 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9494 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9496 /* Check for the cases where we simply want the result of the
9497 earlier test or the opposite of that result. */
9499 || (code == EQ && reversible_comparison_p (op0))
9500 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9501 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9502 && (STORE_FLAG_VALUE
9503 & (((HOST_WIDE_INT) 1
9504 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9506 || (code == GE && reversible_comparison_p (op0)))))
9508 code = (code == LT || code == NE
9509 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9510 op0 = tem, op1 = tem1;
9516 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9518 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9519 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9520 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9522 op0 = XEXP (op0, 1);
9523 code = (code == GE ? GT : LE);
9529 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9530 will be converted to a ZERO_EXTRACT later. */
9531 if (const_op == 0 && equality_comparison_p
9532 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9533 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9535 op0 = simplify_and_const_int
9536 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9538 XEXP (XEXP (op0, 0), 1)),
9543 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9544 zero and X is a comparison and C1 and C2 describe only bits set
9545 in STORE_FLAG_VALUE, we can compare with X. */
9546 if (const_op == 0 && equality_comparison_p
9547 && mode_width <= HOST_BITS_PER_WIDE_INT
9548 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9549 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9550 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9551 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9552 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9554 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9555 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9556 if ((~ STORE_FLAG_VALUE & mask) == 0
9557 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9558 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9559 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9561 op0 = XEXP (XEXP (op0, 0), 0);
9566 /* If we are doing an equality comparison of an AND of a bit equal
9567 to the sign bit, replace this with a LT or GE comparison of
9568 the underlying value. */
9569 if (equality_comparison_p
9571 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9572 && mode_width <= HOST_BITS_PER_WIDE_INT
9573 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9574 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9576 op0 = XEXP (op0, 0);
9577 code = (code == EQ ? GE : LT);
9581 /* If this AND operation is really a ZERO_EXTEND from a narrower
9582 mode, the constant fits within that mode, and this is either an
9583 equality or unsigned comparison, try to do this comparison in
9584 the narrower mode. */
9585 if ((equality_comparison_p || unsigned_comparison_p)
9586 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9587 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9588 & GET_MODE_MASK (mode))
9590 && const_op >> i == 0
9591 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9593 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9599 /* If we have (compare (ashift FOO N) (const_int C)) and
9600 the high order N bits of FOO (N+1 if an inequality comparison)
9601 are known to be zero, we can do this by comparing FOO with C
9602 shifted right N bits so long as the low-order N bits of C are
9604 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9605 && INTVAL (XEXP (op0, 1)) >= 0
9606 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9607 < HOST_BITS_PER_WIDE_INT)
9609 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9610 && mode_width <= HOST_BITS_PER_WIDE_INT
9611 && (nonzero_bits (XEXP (op0, 0), mode)
9612 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9613 + ! equality_comparison_p))) == 0)
9615 const_op >>= INTVAL (XEXP (op0, 1));
9616 op1 = GEN_INT (const_op);
9617 op0 = XEXP (op0, 0);
9621 /* If we are doing a sign bit comparison, it means we are testing
9622 a particular bit. Convert it to the appropriate AND. */
9623 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9624 && mode_width <= HOST_BITS_PER_WIDE_INT)
9626 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9629 - INTVAL (XEXP (op0, 1)))));
9630 code = (code == LT ? NE : EQ);
9634 /* If this an equality comparison with zero and we are shifting
9635 the low bit to the sign bit, we can convert this to an AND of the
9637 if (const_op == 0 && equality_comparison_p
9638 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9639 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9641 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9648 /* If this is an equality comparison with zero, we can do this
9649 as a logical shift, which might be much simpler. */
9650 if (equality_comparison_p && const_op == 0
9651 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9653 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9655 INTVAL (XEXP (op0, 1)));
9659 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9660 do the comparison in a narrower mode. */
9661 if (! unsigned_comparison_p
9662 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9663 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9664 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9665 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9666 MODE_INT, 1)) != BLKmode
9667 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9668 || ((unsigned HOST_WIDE_INT) - const_op
9669 <= GET_MODE_MASK (tmode))))
9671 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9675 /* ... fall through ... */
9677 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9678 the low order N bits of FOO are known to be zero, we can do this
9679 by comparing FOO with C shifted left N bits so long as no
9681 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9682 && INTVAL (XEXP (op0, 1)) >= 0
9683 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9684 && mode_width <= HOST_BITS_PER_WIDE_INT
9685 && (nonzero_bits (XEXP (op0, 0), mode)
9686 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9688 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9691 const_op <<= INTVAL (XEXP (op0, 1));
9692 op1 = GEN_INT (const_op);
9693 op0 = XEXP (op0, 0);
9697 /* If we are using this shift to extract just the sign bit, we
9698 can replace this with an LT or GE comparison. */
9700 && (equality_comparison_p || sign_bit_comparison_p)
9701 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9702 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9704 op0 = XEXP (op0, 0);
9705 code = (code == NE || code == GT ? LT : GE);
9714 /* Now make any compound operations involved in this comparison. Then,
9715 check for an outmost SUBREG on OP0 that isn't doing anything or is
9716 paradoxical. The latter case can only occur when it is known that the
9717 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9718 We can never remove a SUBREG for a non-equality comparison because the
9719 sign bit is in a different place in the underlying object. */
9721 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9722 op1 = make_compound_operation (op1, SET);
9724 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9725 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9726 && (code == NE || code == EQ)
9727 && ((GET_MODE_SIZE (GET_MODE (op0))
9728 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9730 op0 = SUBREG_REG (op0);
9731 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9734 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9735 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9736 && (code == NE || code == EQ)
9737 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9738 <= HOST_BITS_PER_WIDE_INT)
9739 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9740 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9741 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9743 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9744 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9745 op0 = SUBREG_REG (op0), op1 = tem;
9747 /* We now do the opposite procedure: Some machines don't have compare
9748 insns in all modes. If OP0's mode is an integer mode smaller than a
9749 word and we can't do a compare in that mode, see if there is a larger
9750 mode for which we can do the compare. There are a number of cases in
9751 which we can use the wider mode. */
9753 mode = GET_MODE (op0);
9754 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9755 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9756 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9757 for (tmode = GET_MODE_WIDER_MODE (mode);
9759 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9760 tmode = GET_MODE_WIDER_MODE (tmode))
9761 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9763 /* If the only nonzero bits in OP0 and OP1 are those in the
9764 narrower mode and this is an equality or unsigned comparison,
9765 we can use the wider mode. Similarly for sign-extended
9766 values, in which case it is true for all comparisons. */
9767 if (((code == EQ || code == NE
9768 || code == GEU || code == GTU || code == LEU || code == LTU)
9769 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9770 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9771 || ((num_sign_bit_copies (op0, tmode)
9772 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9773 && (num_sign_bit_copies (op1, tmode)
9774 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9776 op0 = gen_lowpart_for_combine (tmode, op0);
9777 op1 = gen_lowpart_for_combine (tmode, op1);
9781 /* If this is a test for negative, we can make an explicit
9782 test of the sign bit. */
9784 if (op1 == const0_rtx && (code == LT || code == GE)
9785 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9787 op0 = gen_binary (AND, tmode,
9788 gen_lowpart_for_combine (tmode, op0),
9789 GEN_INT ((HOST_WIDE_INT) 1
9790 << (GET_MODE_BITSIZE (mode) - 1)));
9791 code = (code == LT) ? NE : EQ;
9796 #ifdef CANONICALIZE_COMPARISON
9797 /* If this machine only supports a subset of valid comparisons, see if we
9798 can convert an unsupported one into a supported one. */
9799 CANONICALIZE_COMPARISON (code, op0, op1);
9808 /* Return 1 if we know that X, a comparison operation, is not operating
9809 on a floating-point value or is EQ or NE, meaning that we can safely
9813 reversible_comparison_p (x)
9816 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9818 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9821 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9824 case MODE_PARTIAL_INT:
9825 case MODE_COMPLEX_INT:
9829 /* If the mode of the condition codes tells us that this is safe,
9830 we need look no further. */
9831 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
9834 /* Otherwise try and find where the condition codes were last set and
9836 x = get_last_value (XEXP (x, 0));
9837 return (x && GET_CODE (x) == COMPARE
9838 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
9844 /* Utility function for following routine. Called when X is part of a value
9845 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9846 for each register mentioned. Similar to mention_regs in cse.c */
9849 update_table_tick (x)
9852 register enum rtx_code code = GET_CODE (x);
9853 register char *fmt = GET_RTX_FORMAT (code);
9858 int regno = REGNO (x);
9859 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9860 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9862 for (i = regno; i < endregno; i++)
9863 reg_last_set_table_tick[i] = label_tick;
9868 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9869 /* Note that we can't have an "E" in values stored; see
9870 get_last_value_validate. */
9872 update_table_tick (XEXP (x, i));
9875 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9876 are saying that the register is clobbered and we no longer know its
9877 value. If INSN is zero, don't update reg_last_set; this is only permitted
9878 with VALUE also zero and is used to invalidate the register. */
9881 record_value_for_reg (reg, insn, value)
9886 int regno = REGNO (reg);
9887 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9888 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
9891 /* If VALUE contains REG and we have a previous value for REG, substitute
9892 the previous value. */
9893 if (value && insn && reg_overlap_mentioned_p (reg, value))
9897 /* Set things up so get_last_value is allowed to see anything set up to
9899 subst_low_cuid = INSN_CUID (insn);
9900 tem = get_last_value (reg);
9903 value = replace_rtx (copy_rtx (value), reg, tem);
9906 /* For each register modified, show we don't know its value, that
9907 we don't know about its bitwise content, that its value has been
9908 updated, and that we don't know the location of the death of the
9910 for (i = regno; i < endregno; i ++)
9913 reg_last_set[i] = insn;
9914 reg_last_set_value[i] = 0;
9915 reg_last_set_mode[i] = 0;
9916 reg_last_set_nonzero_bits[i] = 0;
9917 reg_last_set_sign_bit_copies[i] = 0;
9918 reg_last_death[i] = 0;
9921 /* Mark registers that are being referenced in this value. */
9923 update_table_tick (value);
9925 /* Now update the status of each register being set.
9926 If someone is using this register in this block, set this register
9927 to invalid since we will get confused between the two lives in this
9928 basic block. This makes using this register always invalid. In cse, we
9929 scan the table to invalidate all entries using this register, but this
9930 is too much work for us. */
9932 for (i = regno; i < endregno; i++)
9934 reg_last_set_label[i] = label_tick;
9935 if (value && reg_last_set_table_tick[i] == label_tick)
9936 reg_last_set_invalid[i] = 1;
9938 reg_last_set_invalid[i] = 0;
9941 /* The value being assigned might refer to X (like in "x++;"). In that
9942 case, we must replace it with (clobber (const_int 0)) to prevent
9944 if (value && ! get_last_value_validate (&value,
9945 reg_last_set_label[regno], 0))
9947 value = copy_rtx (value);
9948 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9952 /* For the main register being modified, update the value, the mode, the
9953 nonzero bits, and the number of sign bit copies. */
9955 reg_last_set_value[regno] = value;
9959 subst_low_cuid = INSN_CUID (insn);
9960 reg_last_set_mode[regno] = GET_MODE (reg);
9961 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
9962 reg_last_set_sign_bit_copies[regno]
9963 = num_sign_bit_copies (value, GET_MODE (reg));
9967 /* Used for communication between the following two routines. */
9968 static rtx record_dead_insn;
9970 /* Called via note_stores from record_dead_and_set_regs to handle one
9971 SET or CLOBBER in an insn. */
9974 record_dead_and_set_regs_1 (dest, setter)
9977 if (GET_CODE (dest) == SUBREG)
9978 dest = SUBREG_REG (dest);
9980 if (GET_CODE (dest) == REG)
9982 /* If we are setting the whole register, we know its value. Otherwise
9983 show that we don't know the value. We can handle SUBREG in
9985 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
9986 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
9987 else if (GET_CODE (setter) == SET
9988 && GET_CODE (SET_DEST (setter)) == SUBREG
9989 && SUBREG_REG (SET_DEST (setter)) == dest
9990 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
9991 && subreg_lowpart_p (SET_DEST (setter)))
9992 record_value_for_reg (dest, record_dead_insn,
9993 gen_lowpart_for_combine (GET_MODE (dest),
9996 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
9998 else if (GET_CODE (dest) == MEM
9999 /* Ignore pushes, they clobber nothing. */
10000 && ! push_operand (dest, GET_MODE (dest)))
10001 mem_last_set = INSN_CUID (record_dead_insn);
10004 /* Update the records of when each REG was most recently set or killed
10005 for the things done by INSN. This is the last thing done in processing
10006 INSN in the combiner loop.
10008 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10009 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10010 and also the similar information mem_last_set (which insn most recently
10011 modified memory) and last_call_cuid (which insn was the most recent
10012 subroutine call). */
10015 record_dead_and_set_regs (insn)
10021 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10023 if (REG_NOTE_KIND (link) == REG_DEAD
10024 && GET_CODE (XEXP (link, 0)) == REG)
10026 int regno = REGNO (XEXP (link, 0));
10028 = regno + (regno < FIRST_PSEUDO_REGISTER
10029 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10032 for (i = regno; i < endregno; i++)
10033 reg_last_death[i] = insn;
10035 else if (REG_NOTE_KIND (link) == REG_INC)
10036 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10039 if (GET_CODE (insn) == CALL_INSN)
10041 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10042 if (call_used_regs[i])
10044 reg_last_set_value[i] = 0;
10045 reg_last_set_mode[i] = 0;
10046 reg_last_set_nonzero_bits[i] = 0;
10047 reg_last_set_sign_bit_copies[i] = 0;
10048 reg_last_death[i] = 0;
10051 last_call_cuid = mem_last_set = INSN_CUID (insn);
10054 record_dead_insn = insn;
10055 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10058 /* Utility routine for the following function. Verify that all the registers
10059 mentioned in *LOC are valid when *LOC was part of a value set when
10060 label_tick == TICK. Return 0 if some are not.
10062 If REPLACE is non-zero, replace the invalid reference with
10063 (clobber (const_int 0)) and return 1. This replacement is useful because
10064 we often can get useful information about the form of a value (e.g., if
10065 it was produced by a shift that always produces -1 or 0) even though
10066 we don't know exactly what registers it was produced from. */
10069 get_last_value_validate (loc, tick, replace)
10075 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10076 int len = GET_RTX_LENGTH (GET_CODE (x));
10079 if (GET_CODE (x) == REG)
10081 int regno = REGNO (x);
10082 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10083 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10086 for (j = regno; j < endregno; j++)
10087 if (reg_last_set_invalid[j]
10088 /* If this is a pseudo-register that was only set once, it is
10090 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10091 && reg_last_set_label[j] > tick))
10094 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10101 for (i = 0; i < len; i++)
10103 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10104 /* Don't bother with these. They shouldn't occur anyway. */
10108 /* If we haven't found a reason for it to be invalid, it is valid. */
10112 /* Get the last value assigned to X, if known. Some registers
10113 in the value may be replaced with (clobber (const_int 0)) if their value
10114 is known longer known reliably. */
10123 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10124 then convert it to the desired mode. If this is a paradoxical SUBREG,
10125 we cannot predict what values the "extra" bits might have. */
10126 if (GET_CODE (x) == SUBREG
10127 && subreg_lowpart_p (x)
10128 && (GET_MODE_SIZE (GET_MODE (x))
10129 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10130 && (value = get_last_value (SUBREG_REG (x))) != 0)
10131 return gen_lowpart_for_combine (GET_MODE (x), value);
10133 if (GET_CODE (x) != REG)
10137 value = reg_last_set_value[regno];
10139 /* If we don't have a value or if it isn't for this basic block, return 0. */
10142 || (reg_n_sets[regno] != 1
10143 && reg_last_set_label[regno] != label_tick))
10146 /* If the value was set in a later insn than the ones we are processing,
10147 we can't use it even if the register was only set once, but make a quick
10148 check to see if the previous insn set it to something. This is commonly
10149 the case when the same pseudo is used by repeated insns.
10151 This does not work if there exists an instruction which is temporarily
10152 not on the insn chain. */
10154 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10158 /* We can not do anything useful in this case, because there is
10159 an instruction which is not on the insn chain. */
10160 if (subst_prev_insn)
10163 /* Skip over USE insns. They are not useful here, and they may have
10164 been made by combine, in which case they do not have a INSN_CUID
10165 value. We can't use prev_real_insn, because that would incorrectly
10166 take us backwards across labels. Skip over BARRIERs also, since
10167 they could have been made by combine. If we see one, we must be
10168 optimizing dead code, so it doesn't matter what we do. */
10169 for (insn = prev_nonnote_insn (subst_insn);
10170 insn && ((GET_CODE (insn) == INSN
10171 && GET_CODE (PATTERN (insn)) == USE)
10172 || GET_CODE (insn) == BARRIER
10173 || INSN_CUID (insn) >= subst_low_cuid);
10174 insn = prev_nonnote_insn (insn))
10178 && (set = single_set (insn)) != 0
10179 && rtx_equal_p (SET_DEST (set), x))
10181 value = SET_SRC (set);
10183 /* Make sure that VALUE doesn't reference X. Replace any
10184 explicit references with a CLOBBER. If there are any remaining
10185 references (rare), don't use the value. */
10187 if (reg_mentioned_p (x, value))
10188 value = replace_rtx (copy_rtx (value), x,
10189 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10191 if (reg_overlap_mentioned_p (x, value))
10198 /* If the value has all its registers valid, return it. */
10199 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10202 /* Otherwise, make a copy and replace any invalid register with
10203 (clobber (const_int 0)). If that fails for some reason, return 0. */
10205 value = copy_rtx (value);
10206 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10212 /* Return nonzero if expression X refers to a REG or to memory
10213 that is set in an instruction more recent than FROM_CUID. */
10216 use_crosses_set_p (x, from_cuid)
10220 register char *fmt;
10222 register enum rtx_code code = GET_CODE (x);
10226 register int regno = REGNO (x);
10227 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10228 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10230 #ifdef PUSH_ROUNDING
10231 /* Don't allow uses of the stack pointer to be moved,
10232 because we don't know whether the move crosses a push insn. */
10233 if (regno == STACK_POINTER_REGNUM)
10236 for (;regno < endreg; regno++)
10237 if (reg_last_set[regno]
10238 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10243 if (code == MEM && mem_last_set > from_cuid)
10246 fmt = GET_RTX_FORMAT (code);
10248 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10253 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10254 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10257 else if (fmt[i] == 'e'
10258 && use_crosses_set_p (XEXP (x, i), from_cuid))
10264 /* Define three variables used for communication between the following
10267 static int reg_dead_regno, reg_dead_endregno;
10268 static int reg_dead_flag;
10270 /* Function called via note_stores from reg_dead_at_p.
10272 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10273 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10276 reg_dead_at_p_1 (dest, x)
10280 int regno, endregno;
10282 if (GET_CODE (dest) != REG)
10285 regno = REGNO (dest);
10286 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10287 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10289 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10290 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10293 /* Return non-zero if REG is known to be dead at INSN.
10295 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10296 referencing REG, it is dead. If we hit a SET referencing REG, it is
10297 live. Otherwise, see if it is live or dead at the start of the basic
10298 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10299 must be assumed to be always live. */
10302 reg_dead_at_p (reg, insn)
10308 /* Set variables for reg_dead_at_p_1. */
10309 reg_dead_regno = REGNO (reg);
10310 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10311 ? HARD_REGNO_NREGS (reg_dead_regno,
10317 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10318 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10320 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10321 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10325 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10326 beginning of function. */
10327 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10328 insn = prev_nonnote_insn (insn))
10330 note_stores (PATTERN (insn), reg_dead_at_p_1);
10332 return reg_dead_flag == 1 ? 1 : 0;
10334 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10338 /* Get the basic block number that we were in. */
10343 for (block = 0; block < n_basic_blocks; block++)
10344 if (insn == basic_block_head[block])
10347 if (block == n_basic_blocks)
10351 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10352 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10353 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
10359 /* Note hard registers in X that are used. This code is similar to
10360 that in flow.c, but much simpler since we don't care about pseudos. */
10363 mark_used_regs_combine (x)
10366 register RTX_CODE code = GET_CODE (x);
10367 register int regno;
10379 case ADDR_DIFF_VEC:
10382 /* CC0 must die in the insn after it is set, so we don't need to take
10383 special note of it here. */
10389 /* If we are clobbering a MEM, mark any hard registers inside the
10390 address as used. */
10391 if (GET_CODE (XEXP (x, 0)) == MEM)
10392 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10397 /* A hard reg in a wide mode may really be multiple registers.
10398 If so, mark all of them just like the first. */
10399 if (regno < FIRST_PSEUDO_REGISTER)
10401 /* None of this applies to the stack, frame or arg pointers */
10402 if (regno == STACK_POINTER_REGNUM
10403 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10404 || regno == HARD_FRAME_POINTER_REGNUM
10406 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10407 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10409 || regno == FRAME_POINTER_REGNUM)
10412 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10414 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10420 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10422 register rtx testreg = SET_DEST (x);
10424 while (GET_CODE (testreg) == SUBREG
10425 || GET_CODE (testreg) == ZERO_EXTRACT
10426 || GET_CODE (testreg) == SIGN_EXTRACT
10427 || GET_CODE (testreg) == STRICT_LOW_PART)
10428 testreg = XEXP (testreg, 0);
10430 if (GET_CODE (testreg) == MEM)
10431 mark_used_regs_combine (XEXP (testreg, 0));
10433 mark_used_regs_combine (SET_SRC (x));
10438 /* Recursively scan the operands of this expression. */
10441 register char *fmt = GET_RTX_FORMAT (code);
10443 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10446 mark_used_regs_combine (XEXP (x, i));
10447 else if (fmt[i] == 'E')
10451 for (j = 0; j < XVECLEN (x, i); j++)
10452 mark_used_regs_combine (XVECEXP (x, i, j));
10459 /* Remove register number REGNO from the dead registers list of INSN.
10461 Return the note used to record the death, if there was one. */
10464 remove_death (regno, insn)
10468 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10472 reg_n_deaths[regno]--;
10473 remove_note (insn, note);
10479 /* For each register (hardware or pseudo) used within expression X, if its
10480 death is in an instruction with cuid between FROM_CUID (inclusive) and
10481 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10482 list headed by PNOTES.
10484 This is done when X is being merged by combination into TO_INSN. These
10485 notes will then be distributed as needed. */
10488 move_deaths (x, from_cuid, to_insn, pnotes)
10494 register char *fmt;
10495 register int len, i;
10496 register enum rtx_code code = GET_CODE (x);
10500 register int regno = REGNO (x);
10501 register rtx where_dead = reg_last_death[regno];
10502 register rtx before_dead, after_dead;
10504 /* WHERE_DEAD could be a USE insn made by combine, so first we
10505 make sure that we have insns with valid INSN_CUID values. */
10506 before_dead = where_dead;
10507 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10508 before_dead = PREV_INSN (before_dead);
10509 after_dead = where_dead;
10510 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10511 after_dead = NEXT_INSN (after_dead);
10513 if (before_dead && after_dead
10514 && INSN_CUID (before_dead) >= from_cuid
10515 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10516 || (where_dead != after_dead
10517 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10519 rtx note = remove_death (regno, where_dead);
10521 /* It is possible for the call above to return 0. This can occur
10522 when reg_last_death points to I2 or I1 that we combined with.
10523 In that case make a new note.
10525 We must also check for the case where X is a hard register
10526 and NOTE is a death note for a range of hard registers
10527 including X. In that case, we must put REG_DEAD notes for
10528 the remaining registers in place of NOTE. */
10530 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10531 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10532 != GET_MODE_SIZE (GET_MODE (x))))
10534 int deadregno = REGNO (XEXP (note, 0));
10536 = (deadregno + HARD_REGNO_NREGS (deadregno,
10537 GET_MODE (XEXP (note, 0))));
10538 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10541 for (i = deadregno; i < deadend; i++)
10542 if (i < regno || i >= ourend)
10543 REG_NOTES (where_dead)
10544 = gen_rtx (EXPR_LIST, REG_DEAD,
10545 gen_rtx (REG, reg_raw_mode[i], i),
10546 REG_NOTES (where_dead));
10548 /* If we didn't find any note, and we have a multi-reg hard
10549 register, then to be safe we must check for REG_DEAD notes
10550 for each register other than the first. They could have
10551 their own REG_DEAD notes lying around. */
10552 else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
10553 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10555 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10559 for (i = regno + 1; i < ourend; i++)
10560 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10561 from_cuid, to_insn, &oldnotes);
10564 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10566 XEXP (note, 1) = *pnotes;
10570 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10572 reg_n_deaths[regno]++;
10578 else if (GET_CODE (x) == SET)
10580 rtx dest = SET_DEST (x);
10582 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
10584 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10585 that accesses one word of a multi-word item, some
10586 piece of everything register in the expression is used by
10587 this insn, so remove any old death. */
10589 if (GET_CODE (dest) == ZERO_EXTRACT
10590 || GET_CODE (dest) == STRICT_LOW_PART
10591 || (GET_CODE (dest) == SUBREG
10592 && (((GET_MODE_SIZE (GET_MODE (dest))
10593 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10594 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10595 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10597 move_deaths (dest, from_cuid, to_insn, pnotes);
10601 /* If this is some other SUBREG, we know it replaces the entire
10602 value, so use that as the destination. */
10603 if (GET_CODE (dest) == SUBREG)
10604 dest = SUBREG_REG (dest);
10606 /* If this is a MEM, adjust deaths of anything used in the address.
10607 For a REG (the only other possibility), the entire value is
10608 being replaced so the old value is not used in this insn. */
10610 if (GET_CODE (dest) == MEM)
10611 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
10615 else if (GET_CODE (x) == CLOBBER)
10618 len = GET_RTX_LENGTH (code);
10619 fmt = GET_RTX_FORMAT (code);
10621 for (i = 0; i < len; i++)
10626 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10627 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
10629 else if (fmt[i] == 'e')
10630 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
10634 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10635 pattern of an insn. X must be a REG. */
10638 reg_bitfield_target_p (x, body)
10644 if (GET_CODE (body) == SET)
10646 rtx dest = SET_DEST (body);
10648 int regno, tregno, endregno, endtregno;
10650 if (GET_CODE (dest) == ZERO_EXTRACT)
10651 target = XEXP (dest, 0);
10652 else if (GET_CODE (dest) == STRICT_LOW_PART)
10653 target = SUBREG_REG (XEXP (dest, 0));
10657 if (GET_CODE (target) == SUBREG)
10658 target = SUBREG_REG (target);
10660 if (GET_CODE (target) != REG)
10663 tregno = REGNO (target), regno = REGNO (x);
10664 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10665 return target == x;
10667 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10668 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10670 return endregno > tregno && regno < endtregno;
10673 else if (GET_CODE (body) == PARALLEL)
10674 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10675 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10681 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10682 as appropriate. I3 and I2 are the insns resulting from the combination
10683 insns including FROM (I2 may be zero).
10685 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10686 not need REG_DEAD notes because they are being substituted for. This
10687 saves searching in the most common cases.
10689 Each note in the list is either ignored or placed on some insns, depending
10690 on the type of note. */
10693 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10697 rtx elim_i2, elim_i1;
10699 rtx note, next_note;
10702 for (note = notes; note; note = next_note)
10704 rtx place = 0, place2 = 0;
10706 /* If this NOTE references a pseudo register, ensure it references
10707 the latest copy of that register. */
10708 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10709 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10710 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10712 next_note = XEXP (note, 1);
10713 switch (REG_NOTE_KIND (note))
10716 /* Any clobbers for i3 may still exist, and so we must process
10717 REG_UNUSED notes from that insn.
10719 Any clobbers from i2 or i1 can only exist if they were added by
10720 recog_for_combine. In that case, recog_for_combine created the
10721 necessary REG_UNUSED notes. Trying to keep any original
10722 REG_UNUSED notes from these insns can cause incorrect output
10723 if it is for the same register as the original i3 dest.
10724 In that case, we will notice that the register is set in i3,
10725 and then add a REG_UNUSED note for the destination of i3, which
10726 is wrong. However, it is possible to have REG_UNUSED notes from
10727 i2 or i1 for register which were both used and clobbered, so
10728 we keep notes from i2 or i1 if they will turn into REG_DEAD
10731 /* If this register is set or clobbered in I3, put the note there
10732 unless there is one already. */
10733 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10735 if (from_insn != i3)
10738 if (! (GET_CODE (XEXP (note, 0)) == REG
10739 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
10740 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
10743 /* Otherwise, if this register is used by I3, then this register
10744 now dies here, so we must put a REG_DEAD note here unless there
10746 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
10747 && ! (GET_CODE (XEXP (note, 0)) == REG
10748 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
10749 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
10751 PUT_REG_NOTE_KIND (note, REG_DEAD);
10759 /* These notes say something about results of an insn. We can
10760 only support them if they used to be on I3 in which case they
10761 remain on I3. Otherwise they are ignored.
10763 If the note refers to an expression that is not a constant, we
10764 must also ignore the note since we cannot tell whether the
10765 equivalence is still true. It might be possible to do
10766 slightly better than this (we only have a problem if I2DEST
10767 or I1DEST is present in the expression), but it doesn't
10768 seem worth the trouble. */
10770 if (from_insn == i3
10771 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10776 case REG_NO_CONFLICT:
10778 /* These notes say something about how a register is used. They must
10779 be present on any use of the register in I2 or I3. */
10780 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10783 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10793 /* It is too much trouble to try to see if this note is still
10794 correct in all situations. It is better to simply delete it. */
10798 /* If the insn previously containing this note still exists,
10799 put it back where it was. Otherwise move it to the previous
10800 insn. Adjust the corresponding REG_LIBCALL note. */
10801 if (GET_CODE (from_insn) != NOTE)
10805 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10806 place = prev_real_insn (from_insn);
10808 XEXP (tem, 0) = place;
10813 /* This is handled similarly to REG_RETVAL. */
10814 if (GET_CODE (from_insn) != NOTE)
10818 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
10819 place = next_real_insn (from_insn);
10821 XEXP (tem, 0) = place;
10826 /* If the register is used as an input in I3, it dies there.
10827 Similarly for I2, if it is non-zero and adjacent to I3.
10829 If the register is not used as an input in either I3 or I2
10830 and it is not one of the registers we were supposed to eliminate,
10831 there are two possibilities. We might have a non-adjacent I2
10832 or we might have somehow eliminated an additional register
10833 from a computation. For example, we might have had A & B where
10834 we discover that B will always be zero. In this case we will
10835 eliminate the reference to A.
10837 In both cases, we must search to see if we can find a previous
10838 use of A and put the death note there. */
10841 && GET_CODE (from_insn) == CALL_INSN
10842 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
10844 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
10846 else if (i2 != 0 && next_nonnote_insn (i2) == i3
10847 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10850 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
10853 /* If the register is used in both I2 and I3 and it dies in I3,
10854 we might have added another reference to it. If reg_n_refs
10855 was 2, bump it to 3. This has to be correct since the
10856 register must have been set somewhere. The reason this is
10857 done is because local-alloc.c treats 2 references as a
10860 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
10861 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
10862 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10863 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
10867 for (tem = prev_nonnote_insn (i3);
10869 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
10870 tem = prev_nonnote_insn (tem))
10872 /* If the register is being set at TEM, see if that is all
10873 TEM is doing. If so, delete TEM. Otherwise, make this
10874 into a REG_UNUSED note instead. */
10875 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
10877 rtx set = single_set (tem);
10879 /* Verify that it was the set, and not a clobber that
10880 modified the register. */
10882 if (set != 0 && ! side_effects_p (SET_SRC (set))
10883 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
10884 || (GET_CODE (SET_DEST (set)) == SUBREG
10885 && rtx_equal_p (XEXP (note, 0),
10886 XEXP (SET_DEST (set), 0)))))
10888 /* Move the notes and links of TEM elsewhere.
10889 This might delete other dead insns recursively.
10890 First set the pattern to something that won't use
10893 PATTERN (tem) = pc_rtx;
10895 distribute_notes (REG_NOTES (tem), tem, tem,
10896 NULL_RTX, NULL_RTX, NULL_RTX);
10897 distribute_links (LOG_LINKS (tem));
10899 PUT_CODE (tem, NOTE);
10900 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
10901 NOTE_SOURCE_FILE (tem) = 0;
10905 PUT_REG_NOTE_KIND (note, REG_UNUSED);
10907 /* If there isn't already a REG_UNUSED note, put one
10909 if (! find_regno_note (tem, REG_UNUSED,
10910 REGNO (XEXP (note, 0))))
10915 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
10916 || (GET_CODE (tem) == CALL_INSN
10917 && find_reg_fusage (tem, USE, XEXP (note, 0))))
10921 /* If we are doing a 3->2 combination, and we have a
10922 register which formerly died in i3 and was not used
10923 by i2, which now no longer dies in i3 and is used in
10924 i2 but does not die in i2, and place is between i2
10925 and i3, then we may need to move a link from place to
10927 if (i2 && INSN_UID (place) <= max_uid_cuid
10928 && INSN_CUID (place) > INSN_CUID (i2)
10929 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
10930 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10932 rtx links = LOG_LINKS (place);
10933 LOG_LINKS (place) = 0;
10934 distribute_links (links);
10940 /* If we haven't found an insn for the death note and it
10941 is still a REG_DEAD note, but we have hit a CODE_LABEL,
10942 insert a USE insn for the register at that label and
10943 put the death node there. This prevents problems with
10944 call-state tracking in caller-save.c. */
10945 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
10948 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
10951 /* If this insn was emitted between blocks, then update
10952 basic_block_head of the current block to include it. */
10953 if (basic_block_end[this_basic_block - 1] == tem)
10954 basic_block_head[this_basic_block] = place;
10958 /* If the register is set or already dead at PLACE, we needn't do
10959 anything with this note if it is still a REG_DEAD note.
10961 Note that we cannot use just `dead_or_set_p' here since we can
10962 convert an assignment to a register into a bit-field assignment.
10963 Therefore, we must also omit the note if the register is the
10964 target of a bitfield assignment. */
10966 if (place && REG_NOTE_KIND (note) == REG_DEAD)
10968 int regno = REGNO (XEXP (note, 0));
10970 if (dead_or_set_p (place, XEXP (note, 0))
10971 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
10973 /* Unless the register previously died in PLACE, clear
10974 reg_last_death. [I no longer understand why this is
10976 if (reg_last_death[regno] != place)
10977 reg_last_death[regno] = 0;
10981 reg_last_death[regno] = place;
10983 /* If this is a death note for a hard reg that is occupying
10984 multiple registers, ensure that we are still using all
10985 parts of the object. If we find a piece of the object
10986 that is unused, we must add a USE for that piece before
10987 PLACE and put the appropriate REG_DEAD note on it.
10989 An alternative would be to put a REG_UNUSED for the pieces
10990 on the insn that set the register, but that can't be done if
10991 it is not in the same block. It is simpler, though less
10992 efficient, to add the USE insns. */
10994 if (place && regno < FIRST_PSEUDO_REGISTER
10995 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
10998 = regno + HARD_REGNO_NREGS (regno,
10999 GET_MODE (XEXP (note, 0)));
11003 for (i = regno; i < endregno; i++)
11004 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11005 && ! find_regno_fusage (place, USE, i))
11007 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11010 /* See if we already placed a USE note for this
11011 register in front of PLACE. */
11013 GET_CODE (PREV_INSN (p)) == INSN
11014 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11016 if (rtx_equal_p (piece,
11017 XEXP (PATTERN (PREV_INSN (p)), 0)))
11026 = emit_insn_before (gen_rtx (USE, VOIDmode,
11029 REG_NOTES (use_insn)
11030 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11031 REG_NOTES (use_insn));
11037 /* Check for the case where the register dying partially
11038 overlaps the register set by this insn. */
11040 for (i = regno; i < endregno; i++)
11041 if (dead_or_set_regno_p (place, i))
11049 /* Put only REG_DEAD notes for pieces that are
11050 still used and that are not already dead or set. */
11052 for (i = regno; i < endregno; i++)
11054 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11056 if ((reg_referenced_p (piece, PATTERN (place))
11057 || (GET_CODE (place) == CALL_INSN
11058 && find_reg_fusage (place, USE, piece)))
11059 && ! dead_or_set_p (place, piece)
11060 && ! reg_bitfield_target_p (piece,
11062 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11064 REG_NOTES (place));
11074 /* Any other notes should not be present at this point in the
11081 XEXP (note, 1) = REG_NOTES (place);
11082 REG_NOTES (place) = note;
11084 else if ((REG_NOTE_KIND (note) == REG_DEAD
11085 || REG_NOTE_KIND (note) == REG_UNUSED)
11086 && GET_CODE (XEXP (note, 0)) == REG)
11087 reg_n_deaths[REGNO (XEXP (note, 0))]--;
11091 if ((REG_NOTE_KIND (note) == REG_DEAD
11092 || REG_NOTE_KIND (note) == REG_UNUSED)
11093 && GET_CODE (XEXP (note, 0)) == REG)
11094 reg_n_deaths[REGNO (XEXP (note, 0))]++;
11096 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11097 XEXP (note, 0), REG_NOTES (place2));
11102 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11103 I3, I2, and I1 to new locations. This is also called in one case to
11104 add a link pointing at I3 when I3's destination is changed. */
11107 distribute_links (links)
11110 rtx link, next_link;
11112 for (link = links; link; link = next_link)
11118 next_link = XEXP (link, 1);
11120 /* If the insn that this link points to is a NOTE or isn't a single
11121 set, ignore it. In the latter case, it isn't clear what we
11122 can do other than ignore the link, since we can't tell which
11123 register it was for. Such links wouldn't be used by combine
11126 It is not possible for the destination of the target of the link to
11127 have been changed by combine. The only potential of this is if we
11128 replace I3, I2, and I1 by I3 and I2. But in that case the
11129 destination of I2 also remains unchanged. */
11131 if (GET_CODE (XEXP (link, 0)) == NOTE
11132 || (set = single_set (XEXP (link, 0))) == 0)
11135 reg = SET_DEST (set);
11136 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11137 || GET_CODE (reg) == SIGN_EXTRACT
11138 || GET_CODE (reg) == STRICT_LOW_PART)
11139 reg = XEXP (reg, 0);
11141 /* A LOG_LINK is defined as being placed on the first insn that uses
11142 a register and points to the insn that sets the register. Start
11143 searching at the next insn after the target of the link and stop
11144 when we reach a set of the register or the end of the basic block.
11146 Note that this correctly handles the link that used to point from
11147 I3 to I2. Also note that not much searching is typically done here
11148 since most links don't point very far away. */
11150 for (insn = NEXT_INSN (XEXP (link, 0));
11151 (insn && (this_basic_block == n_basic_blocks - 1
11152 || basic_block_head[this_basic_block + 1] != insn));
11153 insn = NEXT_INSN (insn))
11154 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11155 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11157 if (reg_referenced_p (reg, PATTERN (insn)))
11161 else if (GET_CODE (insn) == CALL_INSN
11162 && find_reg_fusage (insn, USE, reg))
11168 /* If we found a place to put the link, place it there unless there
11169 is already a link to the same insn as LINK at that point. */
11175 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11176 if (XEXP (link2, 0) == XEXP (link, 0))
11181 XEXP (link, 1) = LOG_LINKS (place);
11182 LOG_LINKS (place) = link;
11184 /* Set added_links_insn to the earliest insn we added a
11186 if (added_links_insn == 0
11187 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11188 added_links_insn = place;
11194 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11200 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11201 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11202 insn = NEXT_INSN (insn);
11204 if (INSN_UID (insn) > max_uid_cuid)
11207 return INSN_CUID (insn);
11211 dump_combine_stats (file)
11216 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11217 combine_attempts, combine_merges, combine_extras, combine_successes);
11221 dump_combine_total_stats (file)
11226 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11227 total_attempts, total_merges, total_extras, total_successes);
OSDN Git Service
