1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (last_basic_block);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
616 init_reg_last_arrays ();
617 setup_incoming_promotions ();
619 FOR_EACH_BB (this_basic_block)
621 for (insn = this_basic_block->head;
622 insn != NEXT_INSN (this_basic_block->end);
623 insn = next ? next : NEXT_INSN (insn))
627 if (GET_CODE (insn) == CODE_LABEL)
630 else if (INSN_P (insn))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn, PATTERN (insn));
636 /* Try this insn with each insn it links back to. */
638 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
639 if ((next = try_combine (insn, XEXP (links, 0),
640 NULL_RTX, &new_direct_jump_p)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 rtx link = XEXP (links, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in pursuing this chain any further. */
651 if (GET_CODE (link) == NOTE)
654 for (nextlinks = LOG_LINKS (link);
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, link,
659 &new_direct_jump_p)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn) == JUMP_INSN
672 && (prev = prev_nonnote_insn (insn)) != 0
673 && GET_CODE (prev) == INSN
674 && sets_cc0_p (PATTERN (prev)))
676 if ((next = try_combine (insn, prev,
677 NULL_RTX, &new_direct_jump_p)) != 0)
680 for (nextlinks = LOG_LINKS (prev); nextlinks;
681 nextlinks = XEXP (nextlinks, 1))
682 if ((next = try_combine (insn, prev,
684 &new_direct_jump_p)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn) == INSN
690 && (prev = prev_nonnote_insn (insn)) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && GET_CODE (PATTERN (insn)) == SET
694 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
696 if ((next = try_combine (insn, prev,
697 NULL_RTX, &new_direct_jump_p)) != 0)
700 for (nextlinks = LOG_LINKS (prev); nextlinks;
701 nextlinks = XEXP (nextlinks, 1))
702 if ((next = try_combine (insn, prev,
704 &new_direct_jump_p)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
712 if (GET_CODE (XEXP (links, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
714 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
715 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
716 && GET_CODE (prev) == INSN
717 && sets_cc0_p (PATTERN (prev))
718 && (next = try_combine (insn, XEXP (links, 0),
719 prev, &new_direct_jump_p)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
726 for (nextlinks = XEXP (links, 1); nextlinks;
727 nextlinks = XEXP (nextlinks, 1))
728 if ((next = try_combine (insn, XEXP (links, 0),
730 &new_direct_jump_p)) != 0)
733 if (GET_CODE (insn) != NOTE)
734 record_dead_and_set_regs (insn);
743 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
744 BASIC_BLOCK (i)->flags |= BB_DIRTY);
745 new_direct_jump_p |= purge_all_dead_edges (0);
746 delete_noop_moves (f);
748 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
749 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
750 | PROP_KILL_DEAD_CODE);
753 sbitmap_free (refresh_blocks);
754 free (reg_nonzero_bits);
755 free (reg_sign_bit_copies);
756 free (reg_last_death);
758 free (reg_last_set_value);
759 free (reg_last_set_table_tick);
760 free (reg_last_set_label);
761 free (reg_last_set_invalid);
762 free (reg_last_set_mode);
763 free (reg_last_set_nonzero_bits);
764 free (reg_last_set_sign_bit_copies);
768 struct undo *undo, *next;
769 for (undo = undobuf.frees; undo; undo = next)
777 total_attempts += combine_attempts;
778 total_merges += combine_merges;
779 total_extras += combine_extras;
780 total_successes += combine_successes;
782 nonzero_sign_valid = 0;
784 /* Make recognizer allow volatile MEMs again. */
787 return new_direct_jump_p;
790 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
793 init_reg_last_arrays ()
795 unsigned int nregs = combine_max_regno;
797 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
800 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
801 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
802 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
803 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
804 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
805 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
808 /* Set up any promoted values for incoming argument registers. */
811 setup_incoming_promotions ()
813 #ifdef PROMOTE_FUNCTION_ARGS
816 enum machine_mode mode;
818 rtx first = get_insns ();
820 #ifndef OUTGOING_REGNO
821 #define OUTGOING_REGNO(N) N
823 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
824 /* Check whether this register can hold an incoming pointer
825 argument. FUNCTION_ARG_REGNO_P tests outgoing register
826 numbers, so translate if necessary due to register windows. */
827 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
828 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
831 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
834 gen_rtx_CLOBBER (mode, const0_rtx)));
839 /* Called via note_stores. If X is a pseudo that is narrower than
840 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
842 If we are setting only a portion of X and we can't figure out what
843 portion, assume all bits will be used since we don't know what will
846 Similarly, set how many bits of X are known to be copies of the sign bit
847 at all locations in the function. This is the smallest number implied
851 set_nonzero_bits_and_sign_copies (x, set, data)
854 void *data ATTRIBUTE_UNUSED;
858 if (GET_CODE (x) == REG
859 && REGNO (x) >= FIRST_PSEUDO_REGISTER
860 /* If this register is undefined at the start of the file, we can't
861 say what its contents were. */
862 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
863 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
865 if (set == 0 || GET_CODE (set) == CLOBBER)
867 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
868 reg_sign_bit_copies[REGNO (x)] = 1;
872 /* If this is a complex assignment, see if we can convert it into a
873 simple assignment. */
874 set = expand_field_assignment (set);
876 /* If this is a simple assignment, or we have a paradoxical SUBREG,
877 set what we know about X. */
879 if (SET_DEST (set) == x
880 || (GET_CODE (SET_DEST (set)) == SUBREG
881 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
882 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
883 && SUBREG_REG (SET_DEST (set)) == x))
885 rtx src = SET_SRC (set);
887 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
888 /* If X is narrower than a word and SRC is a non-negative
889 constant that would appear negative in the mode of X,
890 sign-extend it for use in reg_nonzero_bits because some
891 machines (maybe most) will actually do the sign-extension
892 and this is the conservative approach.
894 ??? For 2.5, try to tighten up the MD files in this regard
895 instead of this kludge. */
897 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
898 && GET_CODE (src) == CONST_INT
900 && 0 != (INTVAL (src)
902 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
903 src = GEN_INT (INTVAL (src)
904 | ((HOST_WIDE_INT) (-1)
905 << GET_MODE_BITSIZE (GET_MODE (x))));
908 /* Don't call nonzero_bits if it cannot change anything. */
909 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
910 reg_nonzero_bits[REGNO (x)]
911 |= nonzero_bits (src, nonzero_bits_mode);
912 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
913 if (reg_sign_bit_copies[REGNO (x)] == 0
914 || reg_sign_bit_copies[REGNO (x)] > num)
915 reg_sign_bit_copies[REGNO (x)] = num;
919 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
920 reg_sign_bit_copies[REGNO (x)] = 1;
925 /* See if INSN can be combined into I3. PRED and SUCC are optionally
926 insns that were previously combined into I3 or that will be combined
927 into the merger of INSN and I3.
929 Return 0 if the combination is not allowed for any reason.
931 If the combination is allowed, *PDEST will be set to the single
932 destination of INSN and *PSRC to the single source, and this function
936 can_combine_p (insn, i3, pred, succ, pdest, psrc)
939 rtx pred ATTRIBUTE_UNUSED;
944 rtx set = 0, src, dest;
949 int all_adjacent = (succ ? (next_active_insn (insn) == succ
950 && next_active_insn (succ) == i3)
951 : next_active_insn (insn) == i3);
953 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
954 or a PARALLEL consisting of such a SET and CLOBBERs.
956 If INSN has CLOBBER parallel parts, ignore them for our processing.
957 By definition, these happen during the execution of the insn. When it
958 is merged with another insn, all bets are off. If they are, in fact,
959 needed and aren't also supplied in I3, they may be added by
960 recog_for_combine. Otherwise, it won't match.
962 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
965 Get the source and destination of INSN. If more than one, can't
968 if (GET_CODE (PATTERN (insn)) == SET)
969 set = PATTERN (insn);
970 else if (GET_CODE (PATTERN (insn)) == PARALLEL
971 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
973 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
975 rtx elt = XVECEXP (PATTERN (insn), 0, i);
977 switch (GET_CODE (elt))
979 /* This is important to combine floating point insns
982 /* Combining an isolated USE doesn't make sense.
983 We depend here on combinable_i3pat to reject them. */
984 /* The code below this loop only verifies that the inputs of
985 the SET in INSN do not change. We call reg_set_between_p
986 to verify that the REG in the USE does not change between
988 If the USE in INSN was for a pseudo register, the matching
989 insn pattern will likely match any register; combining this
990 with any other USE would only be safe if we knew that the
991 used registers have identical values, or if there was
992 something to tell them apart, e.g. different modes. For
993 now, we forgo such complicated tests and simply disallow
994 combining of USES of pseudo registers with any other USE. */
995 if (GET_CODE (XEXP (elt, 0)) == REG
996 && GET_CODE (PATTERN (i3)) == PARALLEL)
998 rtx i3pat = PATTERN (i3);
999 int i = XVECLEN (i3pat, 0) - 1;
1000 unsigned int regno = REGNO (XEXP (elt, 0));
1004 rtx i3elt = XVECEXP (i3pat, 0, i);
1006 if (GET_CODE (i3elt) == USE
1007 && GET_CODE (XEXP (i3elt, 0)) == REG
1008 && (REGNO (XEXP (i3elt, 0)) == regno
1009 ? reg_set_between_p (XEXP (elt, 0),
1010 PREV_INSN (insn), i3)
1011 : regno >= FIRST_PSEUDO_REGISTER))
1018 /* We can ignore CLOBBERs. */
1023 /* Ignore SETs whose result isn't used but not those that
1024 have side-effects. */
1025 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1026 && ! side_effects_p (elt))
1029 /* If we have already found a SET, this is a second one and
1030 so we cannot combine with this insn. */
1038 /* Anything else means we can't combine. */
1044 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1045 so don't do anything with it. */
1046 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1055 set = expand_field_assignment (set);
1056 src = SET_SRC (set), dest = SET_DEST (set);
1058 /* Don't eliminate a store in the stack pointer. */
1059 if (dest == stack_pointer_rtx
1060 /* If we couldn't eliminate a field assignment, we can't combine. */
1061 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1062 /* Don't combine with an insn that sets a register to itself if it has
1063 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1064 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1065 /* Can't merge an ASM_OPERANDS. */
1066 || GET_CODE (src) == ASM_OPERANDS
1067 /* Can't merge a function call. */
1068 || GET_CODE (src) == CALL
1069 /* Don't eliminate a function call argument. */
1070 || (GET_CODE (i3) == CALL_INSN
1071 && (find_reg_fusage (i3, USE, dest)
1072 || (GET_CODE (dest) == REG
1073 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1074 && global_regs[REGNO (dest)])))
1075 /* Don't substitute into an incremented register. */
1076 || FIND_REG_INC_NOTE (i3, dest)
1077 || (succ && FIND_REG_INC_NOTE (succ, dest))
1079 /* Don't combine the end of a libcall into anything. */
1080 /* ??? This gives worse code, and appears to be unnecessary, since no
1081 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1082 use REG_RETVAL notes for noconflict blocks, but other code here
1083 makes sure that those insns don't disappear. */
1084 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1086 /* Make sure that DEST is not used after SUCC but before I3. */
1087 || (succ && ! all_adjacent
1088 && reg_used_between_p (dest, succ, i3))
1089 /* Make sure that the value that is to be substituted for the register
1090 does not use any registers whose values alter in between. However,
1091 If the insns are adjacent, a use can't cross a set even though we
1092 think it might (this can happen for a sequence of insns each setting
1093 the same destination; reg_last_set of that register might point to
1094 a NOTE). If INSN has a REG_EQUIV note, the register is always
1095 equivalent to the memory so the substitution is valid even if there
1096 are intervening stores. Also, don't move a volatile asm or
1097 UNSPEC_VOLATILE across any other insns. */
1099 && (((GET_CODE (src) != MEM
1100 || ! find_reg_note (insn, REG_EQUIV, src))
1101 && use_crosses_set_p (src, INSN_CUID (insn)))
1102 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1103 || GET_CODE (src) == UNSPEC_VOLATILE))
1104 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1105 better register allocation by not doing the combine. */
1106 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1107 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1108 /* Don't combine across a CALL_INSN, because that would possibly
1109 change whether the life span of some REGs crosses calls or not,
1110 and it is a pain to update that information.
1111 Exception: if source is a constant, moving it later can't hurt.
1112 Accept that special case, because it helps -fforce-addr a lot. */
1113 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1116 /* DEST must either be a REG or CC0. */
1117 if (GET_CODE (dest) == REG)
1119 /* If register alignment is being enforced for multi-word items in all
1120 cases except for parameters, it is possible to have a register copy
1121 insn referencing a hard register that is not allowed to contain the
1122 mode being copied and which would not be valid as an operand of most
1123 insns. Eliminate this problem by not combining with such an insn.
1125 Also, on some machines we don't want to extend the life of a hard
1128 if (GET_CODE (src) == REG
1129 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1130 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1131 /* Don't extend the life of a hard register unless it is
1132 user variable (if we have few registers) or it can't
1133 fit into the desired register (meaning something special
1135 Also avoid substituting a return register into I3, because
1136 reload can't handle a conflict with constraints of other
1138 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1139 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1142 else if (GET_CODE (dest) != CC0)
1145 /* Don't substitute for a register intended as a clobberable operand.
1146 Similarly, don't substitute an expression containing a register that
1147 will be clobbered in I3. */
1148 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1149 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1150 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1151 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1153 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1156 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1157 or not), reject, unless nothing volatile comes between it and I3 */
1159 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1161 /* Make sure succ doesn't contain a volatile reference. */
1162 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1165 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1166 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1170 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1171 to be an explicit register variable, and was chosen for a reason. */
1173 if (GET_CODE (src) == ASM_OPERANDS
1174 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1177 /* If there are any volatile insns between INSN and I3, reject, because
1178 they might affect machine state. */
1180 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1181 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1184 /* If INSN or I2 contains an autoincrement or autodecrement,
1185 make sure that register is not used between there and I3,
1186 and not already used in I3 either.
1187 Also insist that I3 not be a jump; if it were one
1188 and the incremented register were spilled, we would lose. */
1191 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1192 if (REG_NOTE_KIND (link) == REG_INC
1193 && (GET_CODE (i3) == JUMP_INSN
1194 || reg_used_between_p (XEXP (link, 0), insn, i3)
1195 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1200 /* Don't combine an insn that follows a CC0-setting insn.
1201 An insn that uses CC0 must not be separated from the one that sets it.
1202 We do, however, allow I2 to follow a CC0-setting insn if that insn
1203 is passed as I1; in that case it will be deleted also.
1204 We also allow combining in this case if all the insns are adjacent
1205 because that would leave the two CC0 insns adjacent as well.
1206 It would be more logical to test whether CC0 occurs inside I1 or I2,
1207 but that would be much slower, and this ought to be equivalent. */
1209 p = prev_nonnote_insn (insn);
1210 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1215 /* If we get here, we have passed all the tests and the combination is
1224 /* Check if PAT is an insn - or a part of it - used to set up an
1225 argument for a function in a hard register. */
1228 sets_function_arg_p (pat)
1234 switch (GET_CODE (pat))
1237 return sets_function_arg_p (PATTERN (pat));
1240 for (i = XVECLEN (pat, 0); --i >= 0;)
1241 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1247 inner_dest = SET_DEST (pat);
1248 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1249 || GET_CODE (inner_dest) == SUBREG
1250 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1251 inner_dest = XEXP (inner_dest, 0);
1253 return (GET_CODE (inner_dest) == REG
1254 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1255 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1264 /* LOC is the location within I3 that contains its pattern or the component
1265 of a PARALLEL of the pattern. We validate that it is valid for combining.
1267 One problem is if I3 modifies its output, as opposed to replacing it
1268 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1269 so would produce an insn that is not equivalent to the original insns.
1273 (set (reg:DI 101) (reg:DI 100))
1274 (set (subreg:SI (reg:DI 101) 0) <foo>)
1276 This is NOT equivalent to:
1278 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1279 (set (reg:DI 101) (reg:DI 100))])
1281 Not only does this modify 100 (in which case it might still be valid
1282 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1284 We can also run into a problem if I2 sets a register that I1
1285 uses and I1 gets directly substituted into I3 (not via I2). In that
1286 case, we would be getting the wrong value of I2DEST into I3, so we
1287 must reject the combination. This case occurs when I2 and I1 both
1288 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1289 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1290 of a SET must prevent combination from occurring.
1292 Before doing the above check, we first try to expand a field assignment
1293 into a set of logical operations.
1295 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1296 we place a register that is both set and used within I3. If more than one
1297 such register is detected, we fail.
1299 Return 1 if the combination is valid, zero otherwise. */
1302 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1308 rtx *pi3dest_killed;
1312 if (GET_CODE (x) == SET)
1314 rtx set = expand_field_assignment (x);
1315 rtx dest = SET_DEST (set);
1316 rtx src = SET_SRC (set);
1317 rtx inner_dest = dest;
1320 rtx inner_src = src;
1325 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1326 || GET_CODE (inner_dest) == SUBREG
1327 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1328 inner_dest = XEXP (inner_dest, 0);
1330 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1333 while (GET_CODE (inner_src) == STRICT_LOW_PART
1334 || GET_CODE (inner_src) == SUBREG
1335 || GET_CODE (inner_src) == ZERO_EXTRACT)
1336 inner_src = XEXP (inner_src, 0);
1338 /* If it is better that two different modes keep two different pseudos,
1339 avoid combining them. This avoids producing the following pattern
1341 (set (subreg:SI (reg/v:QI 21) 0)
1342 (lshiftrt:SI (reg/v:SI 20)
1344 If that were made, reload could not handle the pair of
1345 reg 20/21, since it would try to get any GENERAL_REGS
1346 but some of them don't handle QImode. */
1348 if (rtx_equal_p (inner_src, i2dest)
1349 && GET_CODE (inner_dest) == REG
1350 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1354 /* Check for the case where I3 modifies its output, as
1356 if ((inner_dest != dest
1357 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1358 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1360 /* This is the same test done in can_combine_p except we can't test
1361 all_adjacent; we don't have to, since this instruction will stay
1362 in place, thus we are not considering increasing the lifetime of
1365 Also, if this insn sets a function argument, combining it with
1366 something that might need a spill could clobber a previous
1367 function argument; the all_adjacent test in can_combine_p also
1368 checks this; here, we do a more specific test for this case. */
1370 || (GET_CODE (inner_dest) == REG
1371 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1372 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1373 GET_MODE (inner_dest))))
1374 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1377 /* If DEST is used in I3, it is being killed in this insn,
1378 so record that for later.
1379 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1380 STACK_POINTER_REGNUM, since these are always considered to be
1381 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1382 if (pi3dest_killed && GET_CODE (dest) == REG
1383 && reg_referenced_p (dest, PATTERN (i3))
1384 && REGNO (dest) != FRAME_POINTER_REGNUM
1385 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1386 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1388 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1389 && (REGNO (dest) != ARG_POINTER_REGNUM
1390 || ! fixed_regs [REGNO (dest)])
1392 && REGNO (dest) != STACK_POINTER_REGNUM)
1394 if (*pi3dest_killed)
1397 *pi3dest_killed = dest;
1401 else if (GET_CODE (x) == PARALLEL)
1405 for (i = 0; i < XVECLEN (x, 0); i++)
1406 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1407 i1_not_in_src, pi3dest_killed))
1414 /* Return 1 if X is an arithmetic expression that contains a multiplication
1415 and division. We don't count multiplications by powers of two here. */
1421 switch (GET_CODE (x))
1423 case MOD: case DIV: case UMOD: case UDIV:
1427 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1428 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1430 switch (GET_RTX_CLASS (GET_CODE (x)))
1432 case 'c': case '<': case '2':
1433 return contains_muldiv (XEXP (x, 0))
1434 || contains_muldiv (XEXP (x, 1));
1437 return contains_muldiv (XEXP (x, 0));
1445 /* Determine whether INSN can be used in a combination. Return nonzero if
1446 not. This is used in try_combine to detect early some cases where we
1447 can't perform combinations. */
1450 cant_combine_insn_p (insn)
1456 /* If this isn't really an insn, we can't do anything.
1457 This can occur when flow deletes an insn that it has merged into an
1458 auto-increment address. */
1459 if (! INSN_P (insn))
1462 /* Never combine loads and stores involving hard regs. The register
1463 allocator can usually handle such reg-reg moves by tying. If we allow
1464 the combiner to make substitutions of hard regs, we risk aborting in
1465 reload on machines that have SMALL_REGISTER_CLASSES.
1466 As an exception, we allow combinations involving fixed regs; these are
1467 not available to the register allocator so there's no risk involved. */
1469 set = single_set (insn);
1472 src = SET_SRC (set);
1473 dest = SET_DEST (set);
1474 if (GET_CODE (src) == SUBREG)
1475 src = SUBREG_REG (src);
1476 if (GET_CODE (dest) == SUBREG)
1477 dest = SUBREG_REG (dest);
1478 if (REG_P (src) && REG_P (dest)
1479 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1480 && ! fixed_regs[REGNO (src)])
1481 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1482 && ! fixed_regs[REGNO (dest)])))
1488 /* Try to combine the insns I1 and I2 into I3.
1489 Here I1 and I2 appear earlier than I3.
1490 I1 can be zero; then we combine just I2 into I3.
1492 If we are combining three insns and the resulting insn is not recognized,
1493 try splitting it into two insns. If that happens, I2 and I3 are retained
1494 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1497 Return 0 if the combination does not work. Then nothing is changed.
1498 If we did the combination, return the insn at which combine should
1501 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1502 new direct jump instruction. */
1505 try_combine (i3, i2, i1, new_direct_jump_p)
1507 int *new_direct_jump_p;
1509 /* New patterns for I3 and I2, respectively. */
1510 rtx newpat, newi2pat = 0;
1511 int substed_i2 = 0, substed_i1 = 0;
1512 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1513 int added_sets_1, added_sets_2;
1514 /* Total number of SETs to put into I3. */
1516 /* Nonzero is I2's body now appears in I3. */
1518 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1519 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1520 /* Contains I3 if the destination of I3 is used in its source, which means
1521 that the old life of I3 is being killed. If that usage is placed into
1522 I2 and not in I3, a REG_DEAD note must be made. */
1523 rtx i3dest_killed = 0;
1524 /* SET_DEST and SET_SRC of I2 and I1. */
1525 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1526 /* PATTERN (I2), or a copy of it in certain cases. */
1528 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1529 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1530 int i1_feeds_i3 = 0;
1531 /* Notes that must be added to REG_NOTES in I3 and I2. */
1532 rtx new_i3_notes, new_i2_notes;
1533 /* Notes that we substituted I3 into I2 instead of the normal case. */
1534 int i3_subst_into_i2 = 0;
1535 /* Notes that I1, I2 or I3 is a MULT operation. */
1543 /* Exit early if one of the insns involved can't be used for
1545 if (cant_combine_insn_p (i3)
1546 || cant_combine_insn_p (i2)
1547 || (i1 && cant_combine_insn_p (i1))
1548 /* We also can't do anything if I3 has a
1549 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1552 /* ??? This gives worse code, and appears to be unnecessary, since no
1553 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1554 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1560 undobuf.other_insn = 0;
1562 /* Reset the hard register usage information. */
1563 CLEAR_HARD_REG_SET (newpat_used_regs);
1565 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1566 code below, set I1 to be the earlier of the two insns. */
1567 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1568 temp = i1, i1 = i2, i2 = temp;
1570 added_links_insn = 0;
1572 /* First check for one important special-case that the code below will
1573 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1574 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1575 we may be able to replace that destination with the destination of I3.
1576 This occurs in the common code where we compute both a quotient and
1577 remainder into a structure, in which case we want to do the computation
1578 directly into the structure to avoid register-register copies.
1580 Note that this case handles both multiple sets in I2 and also
1581 cases where I2 has a number of CLOBBER or PARALLELs.
1583 We make very conservative checks below and only try to handle the
1584 most common cases of this. For example, we only handle the case
1585 where I2 and I3 are adjacent to avoid making difficult register
1588 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1589 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1590 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1591 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1592 && GET_CODE (PATTERN (i2)) == PARALLEL
1593 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1594 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1595 below would need to check what is inside (and reg_overlap_mentioned_p
1596 doesn't support those codes anyway). Don't allow those destinations;
1597 the resulting insn isn't likely to be recognized anyway. */
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1599 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1600 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1601 SET_DEST (PATTERN (i3)))
1602 && next_real_insn (i2) == i3)
1604 rtx p2 = PATTERN (i2);
1606 /* Make sure that the destination of I3,
1607 which we are going to substitute into one output of I2,
1608 is not used within another output of I2. We must avoid making this:
1609 (parallel [(set (mem (reg 69)) ...)
1610 (set (reg 69) ...)])
1611 which is not well-defined as to order of actions.
1612 (Besides, reload can't handle output reloads for this.)
1614 The problem can also happen if the dest of I3 is a memory ref,
1615 if another dest in I2 is an indirect memory ref. */
1616 for (i = 0; i < XVECLEN (p2, 0); i++)
1617 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1618 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1619 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1620 SET_DEST (XVECEXP (p2, 0, i))))
1623 if (i == XVECLEN (p2, 0))
1624 for (i = 0; i < XVECLEN (p2, 0); i++)
1625 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1626 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1627 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1632 subst_low_cuid = INSN_CUID (i2);
1634 added_sets_2 = added_sets_1 = 0;
1635 i2dest = SET_SRC (PATTERN (i3));
1637 /* Replace the dest in I2 with our dest and make the resulting
1638 insn the new pattern for I3. Then skip to where we
1639 validate the pattern. Everything was set up above. */
1640 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1641 SET_DEST (PATTERN (i3)));
1644 i3_subst_into_i2 = 1;
1645 goto validate_replacement;
1649 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1650 one of those words to another constant, merge them by making a new
1653 && (temp = single_set (i2)) != 0
1654 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1655 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1656 && GET_CODE (SET_DEST (temp)) == REG
1657 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1658 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1659 && GET_CODE (PATTERN (i3)) == SET
1660 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1661 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1662 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1663 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1664 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1666 HOST_WIDE_INT lo, hi;
1668 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1669 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1672 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1673 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1676 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1678 /* We don't handle the case of the target word being wider
1679 than a host wide int. */
1680 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1683 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1684 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1685 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1687 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1688 hi = INTVAL (SET_SRC (PATTERN (i3)));
1689 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1691 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1692 >> (HOST_BITS_PER_WIDE_INT - 1));
1694 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1695 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1696 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1697 (INTVAL (SET_SRC (PATTERN (i3)))));
1699 hi = lo < 0 ? -1 : 0;
1702 /* We don't handle the case of the higher word not fitting
1703 entirely in either hi or lo. */
1708 subst_low_cuid = INSN_CUID (i2);
1709 added_sets_2 = added_sets_1 = 0;
1710 i2dest = SET_DEST (temp);
1712 SUBST (SET_SRC (temp),
1713 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1715 newpat = PATTERN (i2);
1716 goto validate_replacement;
1720 /* If we have no I1 and I2 looks like:
1721 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1723 make up a dummy I1 that is
1726 (set (reg:CC X) (compare:CC Y (const_int 0)))
1728 (We can ignore any trailing CLOBBERs.)
1730 This undoes a previous combination and allows us to match a branch-and-
1733 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1734 && XVECLEN (PATTERN (i2), 0) >= 2
1735 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1736 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1738 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1739 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1740 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1741 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1742 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1743 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1745 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1746 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1751 /* We make I1 with the same INSN_UID as I2. This gives it
1752 the same INSN_CUID for value tracking. Our fake I1 will
1753 never appear in the insn stream so giving it the same INSN_UID
1754 as I2 will not cause a problem. */
1756 subst_prev_insn = i1
1757 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1758 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1759 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1762 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1763 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1764 SET_DEST (PATTERN (i1)));
1769 /* Verify that I2 and I1 are valid for combining. */
1770 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1771 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1777 /* Record whether I2DEST is used in I2SRC and similarly for the other
1778 cases. Knowing this will help in register status updating below. */
1779 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1780 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1781 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1783 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1785 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1787 /* Ensure that I3's pattern can be the destination of combines. */
1788 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1789 i1 && i2dest_in_i1src && i1_feeds_i3,
1796 /* See if any of the insns is a MULT operation. Unless one is, we will
1797 reject a combination that is, since it must be slower. Be conservative
1799 if (GET_CODE (i2src) == MULT
1800 || (i1 != 0 && GET_CODE (i1src) == MULT)
1801 || (GET_CODE (PATTERN (i3)) == SET
1802 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1805 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1806 We used to do this EXCEPT in one case: I3 has a post-inc in an
1807 output operand. However, that exception can give rise to insns like
1809 which is a famous insn on the PDP-11 where the value of r3 used as the
1810 source was model-dependent. Avoid this sort of thing. */
1813 if (!(GET_CODE (PATTERN (i3)) == SET
1814 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1815 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1816 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1817 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1818 /* It's not the exception. */
1821 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1822 if (REG_NOTE_KIND (link) == REG_INC
1823 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1825 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1832 /* See if the SETs in I1 or I2 need to be kept around in the merged
1833 instruction: whenever the value set there is still needed past I3.
1834 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1836 For the SET in I1, we have two cases: If I1 and I2 independently
1837 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1838 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1839 in I1 needs to be kept around unless I1DEST dies or is set in either
1840 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1841 I1DEST. If so, we know I1 feeds into I2. */
1843 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1846 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1847 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1849 /* If the set in I2 needs to be kept around, we must make a copy of
1850 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1851 PATTERN (I2), we are only substituting for the original I1DEST, not into
1852 an already-substituted copy. This also prevents making self-referential
1853 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1856 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1857 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1861 i2pat = copy_rtx (i2pat);
1865 /* Substitute in the latest insn for the regs set by the earlier ones. */
1867 maxreg = max_reg_num ();
1871 /* It is possible that the source of I2 or I1 may be performing an
1872 unneeded operation, such as a ZERO_EXTEND of something that is known
1873 to have the high part zero. Handle that case by letting subst look at
1874 the innermost one of them.
1876 Another way to do this would be to have a function that tries to
1877 simplify a single insn instead of merging two or more insns. We don't
1878 do this because of the potential of infinite loops and because
1879 of the potential extra memory required. However, doing it the way
1880 we are is a bit of a kludge and doesn't catch all cases.
1882 But only do this if -fexpensive-optimizations since it slows things down
1883 and doesn't usually win. */
1885 if (flag_expensive_optimizations)
1887 /* Pass pc_rtx so no substitutions are done, just simplifications.
1888 The cases that we are interested in here do not involve the few
1889 cases were is_replaced is checked. */
1892 subst_low_cuid = INSN_CUID (i1);
1893 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1897 subst_low_cuid = INSN_CUID (i2);
1898 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1903 /* Many machines that don't use CC0 have insns that can both perform an
1904 arithmetic operation and set the condition code. These operations will
1905 be represented as a PARALLEL with the first element of the vector
1906 being a COMPARE of an arithmetic operation with the constant zero.
1907 The second element of the vector will set some pseudo to the result
1908 of the same arithmetic operation. If we simplify the COMPARE, we won't
1909 match such a pattern and so will generate an extra insn. Here we test
1910 for this case, where both the comparison and the operation result are
1911 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1912 I2SRC. Later we will make the PARALLEL that contains I2. */
1914 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1915 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1916 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1917 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1919 #ifdef EXTRA_CC_MODES
1921 enum machine_mode compare_mode;
1924 newpat = PATTERN (i3);
1925 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1929 #ifdef EXTRA_CC_MODES
1930 /* See if a COMPARE with the operand we substituted in should be done
1931 with the mode that is currently being used. If not, do the same
1932 processing we do in `subst' for a SET; namely, if the destination
1933 is used only once, try to replace it with a register of the proper
1934 mode and also replace the COMPARE. */
1935 if (undobuf.other_insn == 0
1936 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1937 &undobuf.other_insn))
1938 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1940 != GET_MODE (SET_DEST (newpat))))
1942 unsigned int regno = REGNO (SET_DEST (newpat));
1943 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1945 if (regno < FIRST_PSEUDO_REGISTER
1946 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1947 && ! REG_USERVAR_P (SET_DEST (newpat))))
1949 if (regno >= FIRST_PSEUDO_REGISTER)
1950 SUBST (regno_reg_rtx[regno], new_dest);
1952 SUBST (SET_DEST (newpat), new_dest);
1953 SUBST (XEXP (*cc_use, 0), new_dest);
1954 SUBST (SET_SRC (newpat),
1955 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1958 undobuf.other_insn = 0;
1965 n_occurrences = 0; /* `subst' counts here */
1967 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1968 need to make a unique copy of I2SRC each time we substitute it
1969 to avoid self-referential rtl. */
1971 subst_low_cuid = INSN_CUID (i2);
1972 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1973 ! i1_feeds_i3 && i1dest_in_i1src);
1976 /* Record whether i2's body now appears within i3's body. */
1977 i2_is_used = n_occurrences;
1980 /* If we already got a failure, don't try to do more. Otherwise,
1981 try to substitute in I1 if we have it. */
1983 if (i1 && GET_CODE (newpat) != CLOBBER)
1985 /* Before we can do this substitution, we must redo the test done
1986 above (see detailed comments there) that ensures that I1DEST
1987 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1989 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1997 subst_low_cuid = INSN_CUID (i1);
1998 newpat = subst (newpat, i1dest, i1src, 0, 0);
2002 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2003 to count all the ways that I2SRC and I1SRC can be used. */
2004 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2005 && i2_is_used + added_sets_2 > 1)
2006 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2007 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2009 /* Fail if we tried to make a new register (we used to abort, but there's
2010 really no reason to). */
2011 || max_reg_num () != maxreg
2012 /* Fail if we couldn't do something and have a CLOBBER. */
2013 || GET_CODE (newpat) == CLOBBER
2014 /* Fail if this new pattern is a MULT and we didn't have one before
2015 at the outer level. */
2016 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2023 /* If the actions of the earlier insns must be kept
2024 in addition to substituting them into the latest one,
2025 we must make a new PARALLEL for the latest insn
2026 to hold additional the SETs. */
2028 if (added_sets_1 || added_sets_2)
2032 if (GET_CODE (newpat) == PARALLEL)
2034 rtvec old = XVEC (newpat, 0);
2035 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2036 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2037 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2038 sizeof (old->elem[0]) * old->num_elem);
2043 total_sets = 1 + added_sets_1 + added_sets_2;
2044 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2045 XVECEXP (newpat, 0, 0) = old;
2049 XVECEXP (newpat, 0, --total_sets)
2050 = (GET_CODE (PATTERN (i1)) == PARALLEL
2051 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2055 /* If there is no I1, use I2's body as is. We used to also not do
2056 the subst call below if I2 was substituted into I3,
2057 but that could lose a simplification. */
2059 XVECEXP (newpat, 0, --total_sets) = i2pat;
2061 /* See comment where i2pat is assigned. */
2062 XVECEXP (newpat, 0, --total_sets)
2063 = subst (i2pat, i1dest, i1src, 0, 0);
2067 /* We come here when we are replacing a destination in I2 with the
2068 destination of I3. */
2069 validate_replacement:
2071 /* Note which hard regs this insn has as inputs. */
2072 mark_used_regs_combine (newpat);
2074 /* Is the result of combination a valid instruction? */
2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2078 the second SET's destination is a register that is unused. In that case,
2079 we just need the first SET. This can occur when simplifying a divmod
2080 insn. We *must* test for this case here because the code below that
2081 splits two independent SETs doesn't handle this case correctly when it
2082 updates the register status. Also check the case where the first
2083 SET's destination is unused. That would not cause incorrect code, but
2084 does cause an unneeded insn to remain. */
2086 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2087 && XVECLEN (newpat, 0) == 2
2088 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2089 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2090 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2091 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2092 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2093 && asm_noperands (newpat) < 0)
2095 newpat = XVECEXP (newpat, 0, 0);
2096 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2099 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2100 && XVECLEN (newpat, 0) == 2
2101 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2102 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2104 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2105 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2106 && asm_noperands (newpat) < 0)
2108 newpat = XVECEXP (newpat, 0, 1);
2109 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2112 /* If we were combining three insns and the result is a simple SET
2113 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2114 insns. There are two ways to do this. It can be split using a
2115 machine-specific method (like when you have an addition of a large
2116 constant) or by combine in the function find_split_point. */
2118 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2119 && asm_noperands (newpat) < 0)
2121 rtx m_split, *split;
2122 rtx ni2dest = i2dest;
2124 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2125 use I2DEST as a scratch register will help. In the latter case,
2126 convert I2DEST to the mode of the source of NEWPAT if we can. */
2128 m_split = split_insns (newpat, i3);
2130 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2131 inputs of NEWPAT. */
2133 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2134 possible to try that as a scratch reg. This would require adding
2135 more code to make it work though. */
2137 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2139 /* If I2DEST is a hard register or the only use of a pseudo,
2140 we can change its mode. */
2141 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2142 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2143 && GET_CODE (i2dest) == REG
2144 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2145 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2146 && ! REG_USERVAR_P (i2dest))))
2147 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2150 m_split = split_insns (gen_rtx_PARALLEL
2152 gen_rtvec (2, newpat,
2153 gen_rtx_CLOBBER (VOIDmode,
2156 /* If the split with the mode-changed register didn't work, try
2157 the original register. */
2158 if (! m_split && ni2dest != i2dest)
2161 m_split = split_insns (gen_rtx_PARALLEL
2163 gen_rtvec (2, newpat,
2164 gen_rtx_CLOBBER (VOIDmode,
2170 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2172 m_split = PATTERN (m_split);
2173 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2174 if (insn_code_number >= 0)
2177 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2178 && (next_real_insn (i2) == i3
2179 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2182 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2183 newi2pat = PATTERN (m_split);
2185 i3set = single_set (NEXT_INSN (m_split));
2186 i2set = single_set (m_split);
2188 /* In case we changed the mode of I2DEST, replace it in the
2189 pseudo-register table here. We can't do it above in case this
2190 code doesn't get executed and we do a split the other way. */
2192 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2193 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2195 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2197 /* If I2 or I3 has multiple SETs, we won't know how to track
2198 register status, so don't use these insns. If I2's destination
2199 is used between I2 and I3, we also can't use these insns. */
2201 if (i2_code_number >= 0 && i2set && i3set
2202 && (next_real_insn (i2) == i3
2203 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2204 insn_code_number = recog_for_combine (&newi3pat, i3,
2206 if (insn_code_number >= 0)
2209 /* It is possible that both insns now set the destination of I3.
2210 If so, we must show an extra use of it. */
2212 if (insn_code_number >= 0)
2214 rtx new_i3_dest = SET_DEST (i3set);
2215 rtx new_i2_dest = SET_DEST (i2set);
2217 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2218 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2219 || GET_CODE (new_i3_dest) == SUBREG)
2220 new_i3_dest = XEXP (new_i3_dest, 0);
2222 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2223 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2224 || GET_CODE (new_i2_dest) == SUBREG)
2225 new_i2_dest = XEXP (new_i2_dest, 0);
2227 if (GET_CODE (new_i3_dest) == REG
2228 && GET_CODE (new_i2_dest) == REG
2229 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2230 REG_N_SETS (REGNO (new_i2_dest))++;
2234 /* If we can split it and use I2DEST, go ahead and see if that
2235 helps things be recognized. Verify that none of the registers
2236 are set between I2 and I3. */
2237 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2239 && GET_CODE (i2dest) == REG
2241 /* We need I2DEST in the proper mode. If it is a hard register
2242 or the only use of a pseudo, we can change its mode. */
2243 && (GET_MODE (*split) == GET_MODE (i2dest)
2244 || GET_MODE (*split) == VOIDmode
2245 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2246 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2247 && ! REG_USERVAR_P (i2dest)))
2248 && (next_real_insn (i2) == i3
2249 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2250 /* We can't overwrite I2DEST if its value is still used by
2252 && ! reg_referenced_p (i2dest, newpat))
2254 rtx newdest = i2dest;
2255 enum rtx_code split_code = GET_CODE (*split);
2256 enum machine_mode split_mode = GET_MODE (*split);
2258 /* Get NEWDEST as a register in the proper mode. We have already
2259 validated that we can do this. */
2260 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2262 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2264 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2265 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2268 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2269 an ASHIFT. This can occur if it was inside a PLUS and hence
2270 appeared to be a memory address. This is a kludge. */
2271 if (split_code == MULT
2272 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2273 && INTVAL (XEXP (*split, 1)) > 0
2274 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2276 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2277 XEXP (*split, 0), GEN_INT (i)));
2278 /* Update split_code because we may not have a multiply
2280 split_code = GET_CODE (*split);
2283 #ifdef INSN_SCHEDULING
2284 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2285 be written as a ZERO_EXTEND. */
2286 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2287 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2288 SUBREG_REG (*split)));
2291 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2292 SUBST (*split, newdest);
2293 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2295 /* If the split point was a MULT and we didn't have one before,
2296 don't use one now. */
2297 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2298 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2302 /* Check for a case where we loaded from memory in a narrow mode and
2303 then sign extended it, but we need both registers. In that case,
2304 we have a PARALLEL with both loads from the same memory location.
2305 We can split this into a load from memory followed by a register-register
2306 copy. This saves at least one insn, more if register allocation can
2309 We cannot do this if the destination of the second assignment is
2310 a register that we have already assumed is zero-extended. Similarly
2311 for a SUBREG of such a register. */
2313 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2314 && GET_CODE (newpat) == PARALLEL
2315 && XVECLEN (newpat, 0) == 2
2316 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2317 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2318 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2319 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2320 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2321 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2323 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2324 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2325 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2326 (GET_CODE (temp) == REG
2327 && reg_nonzero_bits[REGNO (temp)] != 0
2328 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2329 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2330 && (reg_nonzero_bits[REGNO (temp)]
2331 != GET_MODE_MASK (word_mode))))
2332 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2333 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2334 (GET_CODE (temp) == REG
2335 && reg_nonzero_bits[REGNO (temp)] != 0
2336 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2337 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2338 && (reg_nonzero_bits[REGNO (temp)]
2339 != GET_MODE_MASK (word_mode)))))
2340 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2341 SET_SRC (XVECEXP (newpat, 0, 1)))
2342 && ! find_reg_note (i3, REG_UNUSED,
2343 SET_DEST (XVECEXP (newpat, 0, 0))))
2347 newi2pat = XVECEXP (newpat, 0, 0);
2348 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2349 newpat = XVECEXP (newpat, 0, 1);
2350 SUBST (SET_SRC (newpat),
2351 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2352 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2354 if (i2_code_number >= 0)
2355 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2357 if (insn_code_number >= 0)
2362 /* If we will be able to accept this, we have made a change to the
2363 destination of I3. This can invalidate a LOG_LINKS pointing
2364 to I3. No other part of combine.c makes such a transformation.
2366 The new I3 will have a destination that was previously the
2367 destination of I1 or I2 and which was used in i2 or I3. Call
2368 distribute_links to make a LOG_LINK from the next use of
2369 that destination. */
2371 PATTERN (i3) = newpat;
2372 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2374 /* I3 now uses what used to be its destination and which is
2375 now I2's destination. That means we need a LOG_LINK from
2376 I3 to I2. But we used to have one, so we still will.
2378 However, some later insn might be using I2's dest and have
2379 a LOG_LINK pointing at I3. We must remove this link.
2380 The simplest way to remove the link is to point it at I1,
2381 which we know will be a NOTE. */
2383 for (insn = NEXT_INSN (i3);
2384 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2385 || insn != this_basic_block->next_bb->head);
2386 insn = NEXT_INSN (insn))
2388 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2390 for (link = LOG_LINKS (insn); link;
2391 link = XEXP (link, 1))
2392 if (XEXP (link, 0) == i3)
2393 XEXP (link, 0) = i1;
2401 /* Similarly, check for a case where we have a PARALLEL of two independent
2402 SETs but we started with three insns. In this case, we can do the sets
2403 as two separate insns. This case occurs when some SET allows two
2404 other insns to combine, but the destination of that SET is still live. */
2406 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2407 && GET_CODE (newpat) == PARALLEL
2408 && XVECLEN (newpat, 0) == 2
2409 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2411 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2412 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2413 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2414 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2415 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2417 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2419 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2420 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2421 XVECEXP (newpat, 0, 0))
2422 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2423 XVECEXP (newpat, 0, 1))
2424 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2425 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2427 /* Normally, it doesn't matter which of the two is done first,
2428 but it does if one references cc0. In that case, it has to
2431 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2433 newi2pat = XVECEXP (newpat, 0, 0);
2434 newpat = XVECEXP (newpat, 0, 1);
2439 newi2pat = XVECEXP (newpat, 0, 1);
2440 newpat = XVECEXP (newpat, 0, 0);
2443 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2445 if (i2_code_number >= 0)
2446 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2449 /* If it still isn't recognized, fail and change things back the way they
2451 if ((insn_code_number < 0
2452 /* Is the result a reasonable ASM_OPERANDS? */
2453 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2459 /* If we had to change another insn, make sure it is valid also. */
2460 if (undobuf.other_insn)
2462 rtx other_pat = PATTERN (undobuf.other_insn);
2463 rtx new_other_notes;
2466 CLEAR_HARD_REG_SET (newpat_used_regs);
2468 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2471 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2477 PATTERN (undobuf.other_insn) = other_pat;
2479 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2480 are still valid. Then add any non-duplicate notes added by
2481 recog_for_combine. */
2482 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2484 next = XEXP (note, 1);
2486 if (REG_NOTE_KIND (note) == REG_UNUSED
2487 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2489 if (GET_CODE (XEXP (note, 0)) == REG)
2490 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2492 remove_note (undobuf.other_insn, note);
2496 for (note = new_other_notes; note; note = XEXP (note, 1))
2497 if (GET_CODE (XEXP (note, 0)) == REG)
2498 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2500 distribute_notes (new_other_notes, undobuf.other_insn,
2501 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2504 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2505 they are adjacent to each other or not. */
2507 rtx p = prev_nonnote_insn (i3);
2508 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2509 && sets_cc0_p (newi2pat))
2517 /* We now know that we can do this combination. Merge the insns and
2518 update the status of registers and LOG_LINKS. */
2521 rtx i3notes, i2notes, i1notes = 0;
2522 rtx i3links, i2links, i1links = 0;
2525 /* Compute which registers we expect to eliminate. newi2pat may be setting
2526 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2527 same as i3dest, in which case newi2pat may be setting i1dest. */
2528 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2529 || i2dest_in_i2src || i2dest_in_i1src
2531 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2532 || (newi2pat && reg_set_p (i1dest, newi2pat))
2535 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2537 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2538 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2540 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2542 /* Ensure that we do not have something that should not be shared but
2543 occurs multiple times in the new insns. Check this by first
2544 resetting all the `used' flags and then copying anything is shared. */
2546 reset_used_flags (i3notes);
2547 reset_used_flags (i2notes);
2548 reset_used_flags (i1notes);
2549 reset_used_flags (newpat);
2550 reset_used_flags (newi2pat);
2551 if (undobuf.other_insn)
2552 reset_used_flags (PATTERN (undobuf.other_insn));
2554 i3notes = copy_rtx_if_shared (i3notes);
2555 i2notes = copy_rtx_if_shared (i2notes);
2556 i1notes = copy_rtx_if_shared (i1notes);
2557 newpat = copy_rtx_if_shared (newpat);
2558 newi2pat = copy_rtx_if_shared (newi2pat);
2559 if (undobuf.other_insn)
2560 reset_used_flags (PATTERN (undobuf.other_insn));
2562 INSN_CODE (i3) = insn_code_number;
2563 PATTERN (i3) = newpat;
2565 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2567 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2569 reset_used_flags (call_usage);
2570 call_usage = copy_rtx (call_usage);
2573 replace_rtx (call_usage, i2dest, i2src);
2576 replace_rtx (call_usage, i1dest, i1src);
2578 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2581 if (undobuf.other_insn)
2582 INSN_CODE (undobuf.other_insn) = other_code_number;
2584 /* We had one special case above where I2 had more than one set and
2585 we replaced a destination of one of those sets with the destination
2586 of I3. In that case, we have to update LOG_LINKS of insns later
2587 in this basic block. Note that this (expensive) case is rare.
2589 Also, in this case, we must pretend that all REG_NOTEs for I2
2590 actually came from I3, so that REG_UNUSED notes from I2 will be
2591 properly handled. */
2593 if (i3_subst_into_i2)
2595 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2596 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2597 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2598 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2599 && ! find_reg_note (i2, REG_UNUSED,
2600 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2601 for (temp = NEXT_INSN (i2);
2602 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2603 || this_basic_block->head != temp);
2604 temp = NEXT_INSN (temp))
2605 if (temp != i3 && INSN_P (temp))
2606 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2607 if (XEXP (link, 0) == i2)
2608 XEXP (link, 0) = i3;
2613 while (XEXP (link, 1))
2614 link = XEXP (link, 1);
2615 XEXP (link, 1) = i2notes;
2629 INSN_CODE (i2) = i2_code_number;
2630 PATTERN (i2) = newi2pat;
2634 PUT_CODE (i2, NOTE);
2635 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2636 NOTE_SOURCE_FILE (i2) = 0;
2643 PUT_CODE (i1, NOTE);
2644 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2645 NOTE_SOURCE_FILE (i1) = 0;
2648 /* Get death notes for everything that is now used in either I3 or
2649 I2 and used to die in a previous insn. If we built two new
2650 patterns, move from I1 to I2 then I2 to I3 so that we get the
2651 proper movement on registers that I2 modifies. */
2655 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2656 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2659 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2662 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2664 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2667 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2670 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2673 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2676 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2677 know these are REG_UNUSED and want them to go to the desired insn,
2678 so we always pass it as i3. We have not counted the notes in
2679 reg_n_deaths yet, so we need to do so now. */
2681 if (newi2pat && new_i2_notes)
2683 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2684 if (GET_CODE (XEXP (temp, 0)) == REG)
2685 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2687 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2692 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2693 if (GET_CODE (XEXP (temp, 0)) == REG)
2694 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2696 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2699 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2700 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2701 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2702 in that case, it might delete I2. Similarly for I2 and I1.
2703 Show an additional death due to the REG_DEAD note we make here. If
2704 we discard it in distribute_notes, we will decrement it again. */
2708 if (GET_CODE (i3dest_killed) == REG)
2709 REG_N_DEATHS (REGNO (i3dest_killed))++;
2711 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2712 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2714 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2716 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2718 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2722 if (i2dest_in_i2src)
2724 if (GET_CODE (i2dest) == REG)
2725 REG_N_DEATHS (REGNO (i2dest))++;
2727 if (newi2pat && reg_set_p (i2dest, newi2pat))
2728 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2729 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2731 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2732 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2733 NULL_RTX, NULL_RTX);
2736 if (i1dest_in_i1src)
2738 if (GET_CODE (i1dest) == REG)
2739 REG_N_DEATHS (REGNO (i1dest))++;
2741 if (newi2pat && reg_set_p (i1dest, newi2pat))
2742 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2743 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2745 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2746 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2747 NULL_RTX, NULL_RTX);
2750 distribute_links (i3links);
2751 distribute_links (i2links);
2752 distribute_links (i1links);
2754 if (GET_CODE (i2dest) == REG)
2757 rtx i2_insn = 0, i2_val = 0, set;
2759 /* The insn that used to set this register doesn't exist, and
2760 this life of the register may not exist either. See if one of
2761 I3's links points to an insn that sets I2DEST. If it does,
2762 that is now the last known value for I2DEST. If we don't update
2763 this and I2 set the register to a value that depended on its old
2764 contents, we will get confused. If this insn is used, thing
2765 will be set correctly in combine_instructions. */
2767 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2768 if ((set = single_set (XEXP (link, 0))) != 0
2769 && rtx_equal_p (i2dest, SET_DEST (set)))
2770 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2772 record_value_for_reg (i2dest, i2_insn, i2_val);
2774 /* If the reg formerly set in I2 died only once and that was in I3,
2775 zero its use count so it won't make `reload' do any work. */
2777 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2778 && ! i2dest_in_i2src)
2780 regno = REGNO (i2dest);
2781 REG_N_SETS (regno)--;
2785 if (i1 && GET_CODE (i1dest) == REG)
2788 rtx i1_insn = 0, i1_val = 0, set;
2790 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2791 if ((set = single_set (XEXP (link, 0))) != 0
2792 && rtx_equal_p (i1dest, SET_DEST (set)))
2793 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2795 record_value_for_reg (i1dest, i1_insn, i1_val);
2797 regno = REGNO (i1dest);
2798 if (! added_sets_1 && ! i1dest_in_i1src)
2799 REG_N_SETS (regno)--;
2802 /* Update reg_nonzero_bits et al for any changes that may have been made
2803 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2804 important. Because newi2pat can affect nonzero_bits of newpat */
2806 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2807 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2809 /* Set new_direct_jump_p if a new return or simple jump instruction
2812 If I3 is now an unconditional jump, ensure that it has a
2813 BARRIER following it since it may have initially been a
2814 conditional jump. It may also be the last nonnote insn. */
2816 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2818 *new_direct_jump_p = 1;
2820 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2821 || GET_CODE (temp) != BARRIER)
2822 emit_barrier_after (i3);
2824 /* An NOOP jump does not need barrier, but it does need cleaning up
2826 if (GET_CODE (newpat) == SET
2827 && SET_SRC (newpat) == pc_rtx
2828 && SET_DEST (newpat) == pc_rtx)
2829 *new_direct_jump_p = 1;
2832 combine_successes++;
2835 /* Clear this here, so that subsequent get_last_value calls are not
2837 subst_prev_insn = NULL_RTX;
2839 if (added_links_insn
2840 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2841 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2842 return added_links_insn;
2844 return newi2pat ? i2 : i3;
2847 /* Undo all the modifications recorded in undobuf. */
2852 struct undo *undo, *next;
2854 for (undo = undobuf.undos; undo; undo = next)
2858 *undo->where.i = undo->old_contents.i;
2860 *undo->where.r = undo->old_contents.r;
2862 undo->next = undobuf.frees;
2863 undobuf.frees = undo;
2868 /* Clear this here, so that subsequent get_last_value calls are not
2870 subst_prev_insn = NULL_RTX;
2873 /* We've committed to accepting the changes we made. Move all
2874 of the undos to the free list. */
2879 struct undo *undo, *next;
2881 for (undo = undobuf.undos; undo; undo = next)
2884 undo->next = undobuf.frees;
2885 undobuf.frees = undo;
2891 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2892 where we have an arithmetic expression and return that point. LOC will
2895 try_combine will call this function to see if an insn can be split into
2899 find_split_point (loc, insn)
2904 enum rtx_code code = GET_CODE (x);
2906 unsigned HOST_WIDE_INT len = 0;
2907 HOST_WIDE_INT pos = 0;
2909 rtx inner = NULL_RTX;
2911 /* First special-case some codes. */
2915 #ifdef INSN_SCHEDULING
2916 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2918 if (GET_CODE (SUBREG_REG (x)) == MEM)
2921 return find_split_point (&SUBREG_REG (x), insn);
2925 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2926 using LO_SUM and HIGH. */
2927 if (GET_CODE (XEXP (x, 0)) == CONST
2928 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2931 gen_rtx_LO_SUM (Pmode,
2932 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2934 return &XEXP (XEXP (x, 0), 0);
2938 /* If we have a PLUS whose second operand is a constant and the
2939 address is not valid, perhaps will can split it up using
2940 the machine-specific way to split large constants. We use
2941 the first pseudo-reg (one of the virtual regs) as a placeholder;
2942 it will not remain in the result. */
2943 if (GET_CODE (XEXP (x, 0)) == PLUS
2944 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2945 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2947 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2948 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2951 /* This should have produced two insns, each of which sets our
2952 placeholder. If the source of the second is a valid address,
2953 we can make put both sources together and make a split point
2957 && NEXT_INSN (seq) != NULL_RTX
2958 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2959 && GET_CODE (seq) == INSN
2960 && GET_CODE (PATTERN (seq)) == SET
2961 && SET_DEST (PATTERN (seq)) == reg
2962 && ! reg_mentioned_p (reg,
2963 SET_SRC (PATTERN (seq)))
2964 && GET_CODE (NEXT_INSN (seq)) == INSN
2965 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2966 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2967 && memory_address_p (GET_MODE (x),
2968 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2970 rtx src1 = SET_SRC (PATTERN (seq));
2971 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2973 /* Replace the placeholder in SRC2 with SRC1. If we can
2974 find where in SRC2 it was placed, that can become our
2975 split point and we can replace this address with SRC2.
2976 Just try two obvious places. */
2978 src2 = replace_rtx (src2, reg, src1);
2980 if (XEXP (src2, 0) == src1)
2981 split = &XEXP (src2, 0);
2982 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2983 && XEXP (XEXP (src2, 0), 0) == src1)
2984 split = &XEXP (XEXP (src2, 0), 0);
2988 SUBST (XEXP (x, 0), src2);
2993 /* If that didn't work, perhaps the first operand is complex and
2994 needs to be computed separately, so make a split point there.
2995 This will occur on machines that just support REG + CONST
2996 and have a constant moved through some previous computation. */
2998 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2999 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3000 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3002 return &XEXP (XEXP (x, 0), 0);
3008 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3009 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3010 we need to put the operand into a register. So split at that
3013 if (SET_DEST (x) == cc0_rtx
3014 && GET_CODE (SET_SRC (x)) != COMPARE
3015 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3016 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3017 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3018 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3019 return &SET_SRC (x);
3022 /* See if we can split SET_SRC as it stands. */
3023 split = find_split_point (&SET_SRC (x), insn);
3024 if (split && split != &SET_SRC (x))
3027 /* See if we can split SET_DEST as it stands. */
3028 split = find_split_point (&SET_DEST (x), insn);
3029 if (split && split != &SET_DEST (x))
3032 /* See if this is a bitfield assignment with everything constant. If
3033 so, this is an IOR of an AND, so split it into that. */
3034 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3035 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3036 <= HOST_BITS_PER_WIDE_INT)
3037 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3038 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3039 && GET_CODE (SET_SRC (x)) == CONST_INT
3040 && ((INTVAL (XEXP (SET_DEST (x), 1))
3041 + INTVAL (XEXP (SET_DEST (x), 2)))
3042 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3043 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3045 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3046 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3047 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3048 rtx dest = XEXP (SET_DEST (x), 0);
3049 enum machine_mode mode = GET_MODE (dest);
3050 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3052 if (BITS_BIG_ENDIAN)
3053 pos = GET_MODE_BITSIZE (mode) - len - pos;
3057 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3060 gen_binary (IOR, mode,
3061 gen_binary (AND, mode, dest,
3062 gen_int_mode (~(mask << pos),
3064 GEN_INT (src << pos)));
3066 SUBST (SET_DEST (x), dest);
3068 split = find_split_point (&SET_SRC (x), insn);
3069 if (split && split != &SET_SRC (x))
3073 /* Otherwise, see if this is an operation that we can split into two.
3074 If so, try to split that. */
3075 code = GET_CODE (SET_SRC (x));
3080 /* If we are AND'ing with a large constant that is only a single
3081 bit and the result is only being used in a context where we
3082 need to know if it is zero or non-zero, replace it with a bit
3083 extraction. This will avoid the large constant, which might
3084 have taken more than one insn to make. If the constant were
3085 not a valid argument to the AND but took only one insn to make,
3086 this is no worse, but if it took more than one insn, it will
3089 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3090 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3091 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3092 && GET_CODE (SET_DEST (x)) == REG
3093 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3094 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3095 && XEXP (*split, 0) == SET_DEST (x)
3096 && XEXP (*split, 1) == const0_rtx)
3098 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3099 XEXP (SET_SRC (x), 0),
3100 pos, NULL_RTX, 1, 1, 0, 0);
3101 if (extraction != 0)
3103 SUBST (SET_SRC (x), extraction);
3104 return find_split_point (loc, insn);
3110 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3111 is known to be on, this can be converted into a NEG of a shift. */
3112 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3113 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3114 && 1 <= (pos = exact_log2
3115 (nonzero_bits (XEXP (SET_SRC (x), 0),
3116 GET_MODE (XEXP (SET_SRC (x), 0))))))
3118 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3122 gen_rtx_LSHIFTRT (mode,
3123 XEXP (SET_SRC (x), 0),
3126 split = find_split_point (&SET_SRC (x), insn);
3127 if (split && split != &SET_SRC (x))
3133 inner = XEXP (SET_SRC (x), 0);
3135 /* We can't optimize if either mode is a partial integer
3136 mode as we don't know how many bits are significant
3138 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3139 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3143 len = GET_MODE_BITSIZE (GET_MODE (inner));
3149 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3150 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3152 inner = XEXP (SET_SRC (x), 0);
3153 len = INTVAL (XEXP (SET_SRC (x), 1));
3154 pos = INTVAL (XEXP (SET_SRC (x), 2));
3156 if (BITS_BIG_ENDIAN)
3157 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3158 unsignedp = (code == ZERO_EXTRACT);
3166 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3168 enum machine_mode mode = GET_MODE (SET_SRC (x));
3170 /* For unsigned, we have a choice of a shift followed by an
3171 AND or two shifts. Use two shifts for field sizes where the
3172 constant might be too large. We assume here that we can
3173 always at least get 8-bit constants in an AND insn, which is
3174 true for every current RISC. */
3176 if (unsignedp && len <= 8)
3181 (mode, gen_lowpart_for_combine (mode, inner),
3183 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3185 split = find_split_point (&SET_SRC (x), insn);
3186 if (split && split != &SET_SRC (x))
3193 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3194 gen_rtx_ASHIFT (mode,
3195 gen_lowpart_for_combine (mode, inner),
3196 GEN_INT (GET_MODE_BITSIZE (mode)
3198 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3200 split = find_split_point (&SET_SRC (x), insn);
3201 if (split && split != &SET_SRC (x))
3206 /* See if this is a simple operation with a constant as the second
3207 operand. It might be that this constant is out of range and hence
3208 could be used as a split point. */
3209 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3210 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3211 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3212 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3213 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3214 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3215 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3217 return &XEXP (SET_SRC (x), 1);
3219 /* Finally, see if this is a simple operation with its first operand
3220 not in a register. The operation might require this operand in a
3221 register, so return it as a split point. We can always do this
3222 because if the first operand were another operation, we would have
3223 already found it as a split point. */
3224 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3225 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3226 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3227 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3228 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3229 return &XEXP (SET_SRC (x), 0);
3235 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3236 it is better to write this as (not (ior A B)) so we can split it.
3237 Similarly for IOR. */
3238 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3241 gen_rtx_NOT (GET_MODE (x),
3242 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3244 XEXP (XEXP (x, 0), 0),
3245 XEXP (XEXP (x, 1), 0))));
3246 return find_split_point (loc, insn);
3249 /* Many RISC machines have a large set of logical insns. If the
3250 second operand is a NOT, put it first so we will try to split the
3251 other operand first. */
3252 if (GET_CODE (XEXP (x, 1)) == NOT)
3254 rtx tem = XEXP (x, 0);
3255 SUBST (XEXP (x, 0), XEXP (x, 1));
3256 SUBST (XEXP (x, 1), tem);
3264 /* Otherwise, select our actions depending on our rtx class. */
3265 switch (GET_RTX_CLASS (code))
3267 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3269 split = find_split_point (&XEXP (x, 2), insn);
3272 /* ... fall through ... */
3276 split = find_split_point (&XEXP (x, 1), insn);
3279 /* ... fall through ... */
3281 /* Some machines have (and (shift ...) ...) insns. If X is not
3282 an AND, but XEXP (X, 0) is, use it as our split point. */
3283 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3284 return &XEXP (x, 0);
3286 split = find_split_point (&XEXP (x, 0), insn);
3292 /* Otherwise, we don't have a split point. */
3296 /* Throughout X, replace FROM with TO, and return the result.
3297 The result is TO if X is FROM;
3298 otherwise the result is X, but its contents may have been modified.
3299 If they were modified, a record was made in undobuf so that
3300 undo_all will (among other things) return X to its original state.
3302 If the number of changes necessary is too much to record to undo,
3303 the excess changes are not made, so the result is invalid.
3304 The changes already made can still be undone.
3305 undobuf.num_undo is incremented for such changes, so by testing that
3306 the caller can tell whether the result is valid.
3308 `n_occurrences' is incremented each time FROM is replaced.
3310 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3312 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3313 by copying if `n_occurrences' is non-zero. */
3316 subst (x, from, to, in_dest, unique_copy)
3321 enum rtx_code code = GET_CODE (x);
3322 enum machine_mode op0_mode = VOIDmode;
3327 /* Two expressions are equal if they are identical copies of a shared
3328 RTX or if they are both registers with the same register number
3331 #define COMBINE_RTX_EQUAL_P(X,Y) \
3333 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3334 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3336 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3339 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3342 /* If X and FROM are the same register but different modes, they will
3343 not have been seen as equal above. However, flow.c will make a
3344 LOG_LINKS entry for that case. If we do nothing, we will try to
3345 rerecognize our original insn and, when it succeeds, we will
3346 delete the feeding insn, which is incorrect.
3348 So force this insn not to match in this (rare) case. */
3349 if (! in_dest && code == REG && GET_CODE (from) == REG
3350 && REGNO (x) == REGNO (from))
3351 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3353 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3354 of which may contain things that can be combined. */
3355 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3358 /* It is possible to have a subexpression appear twice in the insn.
3359 Suppose that FROM is a register that appears within TO.
3360 Then, after that subexpression has been scanned once by `subst',
3361 the second time it is scanned, TO may be found. If we were
3362 to scan TO here, we would find FROM within it and create a
3363 self-referent rtl structure which is completely wrong. */
3364 if (COMBINE_RTX_EQUAL_P (x, to))
3367 /* Parallel asm_operands need special attention because all of the
3368 inputs are shared across the arms. Furthermore, unsharing the
3369 rtl results in recognition failures. Failure to handle this case
3370 specially can result in circular rtl.
3372 Solve this by doing a normal pass across the first entry of the
3373 parallel, and only processing the SET_DESTs of the subsequent
3376 if (code == PARALLEL
3377 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3378 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3380 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3382 /* If this substitution failed, this whole thing fails. */
3383 if (GET_CODE (new) == CLOBBER
3384 && XEXP (new, 0) == const0_rtx)
3387 SUBST (XVECEXP (x, 0, 0), new);
3389 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3391 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3393 if (GET_CODE (dest) != REG
3394 && GET_CODE (dest) != CC0
3395 && GET_CODE (dest) != PC)
3397 new = subst (dest, from, to, 0, unique_copy);
3399 /* If this substitution failed, this whole thing fails. */
3400 if (GET_CODE (new) == CLOBBER
3401 && XEXP (new, 0) == const0_rtx)
3404 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3410 len = GET_RTX_LENGTH (code);
3411 fmt = GET_RTX_FORMAT (code);
3413 /* We don't need to process a SET_DEST that is a register, CC0,
3414 or PC, so set up to skip this common case. All other cases
3415 where we want to suppress replacing something inside a
3416 SET_SRC are handled via the IN_DEST operand. */
3418 && (GET_CODE (SET_DEST (x)) == REG
3419 || GET_CODE (SET_DEST (x)) == CC0
3420 || GET_CODE (SET_DEST (x)) == PC))
3423 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3426 op0_mode = GET_MODE (XEXP (x, 0));
3428 for (i = 0; i < len; i++)
3433 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3435 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3437 new = (unique_copy && n_occurrences
3438 ? copy_rtx (to) : to);
3443 new = subst (XVECEXP (x, i, j), from, to, 0,
3446 /* If this substitution failed, this whole thing
3448 if (GET_CODE (new) == CLOBBER
3449 && XEXP (new, 0) == const0_rtx)
3453 SUBST (XVECEXP (x, i, j), new);
3456 else if (fmt[i] == 'e')
3458 /* If this is a register being set, ignore it. */
3461 && (code == SUBREG || code == STRICT_LOW_PART
3462 || code == ZERO_EXTRACT)
3464 && GET_CODE (new) == REG)
3467 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3469 /* In general, don't install a subreg involving two
3470 modes not tieable. It can worsen register
3471 allocation, and can even make invalid reload
3472 insns, since the reg inside may need to be copied
3473 from in the outside mode, and that may be invalid
3474 if it is an fp reg copied in integer mode.
3476 We allow two exceptions to this: It is valid if
3477 it is inside another SUBREG and the mode of that
3478 SUBREG and the mode of the inside of TO is
3479 tieable and it is valid if X is a SET that copies
3482 if (GET_CODE (to) == SUBREG
3483 && ! MODES_TIEABLE_P (GET_MODE (to),
3484 GET_MODE (SUBREG_REG (to)))
3485 && ! (code == SUBREG
3486 && MODES_TIEABLE_P (GET_MODE (x),
3487 GET_MODE (SUBREG_REG (to))))
3489 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3492 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3494 #ifdef CLASS_CANNOT_CHANGE_MODE
3496 && GET_CODE (to) == REG
3497 && REGNO (to) < FIRST_PSEUDO_REGISTER
3498 && (TEST_HARD_REG_BIT
3499 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3501 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3503 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3506 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3510 /* If we are in a SET_DEST, suppress most cases unless we
3511 have gone inside a MEM, in which case we want to
3512 simplify the address. We assume here that things that
3513 are actually part of the destination have their inner
3514 parts in the first expression. This is true for SUBREG,
3515 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3516 things aside from REG and MEM that should appear in a
3518 new = subst (XEXP (x, i), from, to,
3520 && (code == SUBREG || code == STRICT_LOW_PART
3521 || code == ZERO_EXTRACT))
3523 && i == 0), unique_copy);
3525 /* If we found that we will have to reject this combination,
3526 indicate that by returning the CLOBBER ourselves, rather than
3527 an expression containing it. This will speed things up as
3528 well as prevent accidents where two CLOBBERs are considered
3529 to be equal, thus producing an incorrect simplification. */
3531 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3534 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3536 enum machine_mode mode = GET_MODE (x);
3538 x = simplify_subreg (GET_MODE (x), new,
3539 GET_MODE (SUBREG_REG (x)),
3542 x = gen_rtx_CLOBBER (mode, const0_rtx);
3544 else if (GET_CODE (new) == CONST_INT
3545 && GET_CODE (x) == ZERO_EXTEND)
3547 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3548 new, GET_MODE (XEXP (x, 0)));
3553 SUBST (XEXP (x, i), new);
3558 /* Try to simplify X. If the simplification changed the code, it is likely
3559 that further simplification will help, so loop, but limit the number
3560 of repetitions that will be performed. */
3562 for (i = 0; i < 4; i++)
3564 /* If X is sufficiently simple, don't bother trying to do anything
3566 if (code != CONST_INT && code != REG && code != CLOBBER)
3567 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3569 if (GET_CODE (x) == code)
3572 code = GET_CODE (x);
3574 /* We no longer know the original mode of operand 0 since we
3575 have changed the form of X) */
3576 op0_mode = VOIDmode;
3582 /* Simplify X, a piece of RTL. We just operate on the expression at the
3583 outer level; call `subst' to simplify recursively. Return the new
3586 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3587 will be the iteration even if an expression with a code different from
3588 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3591 combine_simplify_rtx (x, op0_mode, last, in_dest)
3593 enum machine_mode op0_mode;
3597 enum rtx_code code = GET_CODE (x);
3598 enum machine_mode mode = GET_MODE (x);
3603 /* If this is a commutative operation, put a constant last and a complex
3604 expression first. We don't need to do this for comparisons here. */
3605 if (GET_RTX_CLASS (code) == 'c'
3606 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3609 SUBST (XEXP (x, 0), XEXP (x, 1));
3610 SUBST (XEXP (x, 1), temp);
3613 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3614 sign extension of a PLUS with a constant, reverse the order of the sign
3615 extension and the addition. Note that this not the same as the original
3616 code, but overflow is undefined for signed values. Also note that the
3617 PLUS will have been partially moved "inside" the sign-extension, so that
3618 the first operand of X will really look like:
3619 (ashiftrt (plus (ashift A C4) C5) C4).
3621 (plus (ashiftrt (ashift A C4) C2) C4)
3622 and replace the first operand of X with that expression. Later parts
3623 of this function may simplify the expression further.
3625 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3626 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3627 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3629 We do this to simplify address expressions. */
3631 if ((code == PLUS || code == MINUS || code == MULT)
3632 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3633 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3634 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3635 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3636 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3637 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3638 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3639 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3640 XEXP (XEXP (XEXP (x, 0), 0), 1),
3641 XEXP (XEXP (x, 0), 1))) != 0)
3644 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3645 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3646 INTVAL (XEXP (XEXP (x, 0), 1)));
3648 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3649 INTVAL (XEXP (XEXP (x, 0), 1)));
3651 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3654 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3655 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3656 things. Check for cases where both arms are testing the same
3659 Don't do anything if all operands are very simple. */
3661 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3662 || GET_RTX_CLASS (code) == '<')
3663 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3664 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3665 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3667 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3668 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3669 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3671 || (GET_RTX_CLASS (code) == '1'
3672 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3673 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3674 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3677 rtx cond, true_rtx, false_rtx;
3679 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3681 /* If everything is a comparison, what we have is highly unlikely
3682 to be simpler, so don't use it. */
3683 && ! (GET_RTX_CLASS (code) == '<'
3684 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3685 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3687 rtx cop1 = const0_rtx;
3688 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3690 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3693 /* Simplify the alternative arms; this may collapse the true and
3694 false arms to store-flag values. */
3695 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3696 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3698 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3699 is unlikely to be simpler. */
3700 if (general_operand (true_rtx, VOIDmode)
3701 && general_operand (false_rtx, VOIDmode))
3703 /* Restarting if we generate a store-flag expression will cause
3704 us to loop. Just drop through in this case. */
3706 /* If the result values are STORE_FLAG_VALUE and zero, we can
3707 just make the comparison operation. */
3708 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3709 x = gen_binary (cond_code, mode, cond, cop1);
3710 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3711 && reverse_condition (cond_code) != UNKNOWN)
3712 x = gen_binary (reverse_condition (cond_code),
3715 /* Likewise, we can make the negate of a comparison operation
3716 if the result values are - STORE_FLAG_VALUE and zero. */
3717 else if (GET_CODE (true_rtx) == CONST_INT
3718 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3719 && false_rtx == const0_rtx)
3720 x = simplify_gen_unary (NEG, mode,
3721 gen_binary (cond_code, mode, cond,
3724 else if (GET_CODE (false_rtx) == CONST_INT
3725 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3726 && true_rtx == const0_rtx)
3727 x = simplify_gen_unary (NEG, mode,
3728 gen_binary (reverse_condition
3733 return gen_rtx_IF_THEN_ELSE (mode,
3734 gen_binary (cond_code, VOIDmode,
3736 true_rtx, false_rtx);
3738 code = GET_CODE (x);
3739 op0_mode = VOIDmode;
3744 /* Try to fold this expression in case we have constants that weren't
3747 switch (GET_RTX_CLASS (code))
3750 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3754 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3755 if (cmp_mode == VOIDmode)
3757 cmp_mode = GET_MODE (XEXP (x, 1));
3758 if (cmp_mode == VOIDmode)
3759 cmp_mode = op0_mode;
3761 temp = simplify_relational_operation (code, cmp_mode,
3762 XEXP (x, 0), XEXP (x, 1));
3764 #ifdef FLOAT_STORE_FLAG_VALUE
3765 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3767 if (temp == const0_rtx)
3768 temp = CONST0_RTX (mode);
3770 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3777 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3781 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3782 XEXP (x, 1), XEXP (x, 2));
3789 code = GET_CODE (temp);
3790 op0_mode = VOIDmode;
3791 mode = GET_MODE (temp);
3794 /* First see if we can apply the inverse distributive law. */
3795 if (code == PLUS || code == MINUS
3796 || code == AND || code == IOR || code == XOR)
3798 x = apply_distributive_law (x);
3799 code = GET_CODE (x);
3800 op0_mode = VOIDmode;
3803 /* If CODE is an associative operation not otherwise handled, see if we
3804 can associate some operands. This can win if they are constants or
3805 if they are logically related (i.e. (a & b) & a). */
3806 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3807 || code == AND || code == IOR || code == XOR
3808 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3809 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3810 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3812 if (GET_CODE (XEXP (x, 0)) == code)
3814 rtx other = XEXP (XEXP (x, 0), 0);
3815 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3816 rtx inner_op1 = XEXP (x, 1);
3819 /* Make sure we pass the constant operand if any as the second
3820 one if this is a commutative operation. */
3821 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3823 rtx tem = inner_op0;
3824 inner_op0 = inner_op1;
3827 inner = simplify_binary_operation (code == MINUS ? PLUS
3828 : code == DIV ? MULT
3830 mode, inner_op0, inner_op1);
3832 /* For commutative operations, try the other pair if that one
3834 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3836 other = XEXP (XEXP (x, 0), 1);
3837 inner = simplify_binary_operation (code, mode,
3838 XEXP (XEXP (x, 0), 0),
3843 return gen_binary (code, mode, other, inner);
3847 /* A little bit of algebraic simplification here. */
3851 /* Ensure that our address has any ASHIFTs converted to MULT in case
3852 address-recognizing predicates are called later. */
3853 temp = make_compound_operation (XEXP (x, 0), MEM);
3854 SUBST (XEXP (x, 0), temp);
3858 if (op0_mode == VOIDmode)
3859 op0_mode = GET_MODE (SUBREG_REG (x));
3861 /* simplify_subreg can't use gen_lowpart_for_combine. */
3862 if (CONSTANT_P (SUBREG_REG (x))
3863 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3864 /* Don't call gen_lowpart_for_combine if the inner mode
3865 is VOIDmode and we cannot simplify it, as SUBREG without
3866 inner mode is invalid. */
3867 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3868 || gen_lowpart_common (mode, SUBREG_REG (x))))
3869 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3871 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3875 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3881 /* Don't change the mode of the MEM if that would change the meaning
3883 if (GET_CODE (SUBREG_REG (x)) == MEM
3884 && (MEM_VOLATILE_P (SUBREG_REG (x))
3885 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3886 return gen_rtx_CLOBBER (mode, const0_rtx);
3888 /* Note that we cannot do any narrowing for non-constants since
3889 we might have been counting on using the fact that some bits were
3890 zero. We now do this in the SET. */
3895 /* (not (plus X -1)) can become (neg X). */
3896 if (GET_CODE (XEXP (x, 0)) == PLUS
3897 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3898 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3900 /* Similarly, (not (neg X)) is (plus X -1). */
3901 if (GET_CODE (XEXP (x, 0)) == NEG)
3902 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3904 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3905 if (GET_CODE (XEXP (x, 0)) == XOR
3906 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3907 && (temp = simplify_unary_operation (NOT, mode,
3908 XEXP (XEXP (x, 0), 1),
3910 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3912 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3913 other than 1, but that is not valid. We could do a similar
3914 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3915 but this doesn't seem common enough to bother with. */
3916 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3917 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3918 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3920 XEXP (XEXP (x, 0), 1));
3922 if (GET_CODE (XEXP (x, 0)) == SUBREG
3923 && subreg_lowpart_p (XEXP (x, 0))
3924 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3925 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3926 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3927 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3929 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3931 x = gen_rtx_ROTATE (inner_mode,
3932 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3934 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3935 return gen_lowpart_for_combine (mode, x);
3938 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3939 reversing the comparison code if valid. */
3940 if (STORE_FLAG_VALUE == -1
3941 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3942 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3943 XEXP (XEXP (x, 0), 1))))
3946 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3947 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3948 perform the above simplification. */
3950 if (STORE_FLAG_VALUE == -1
3951 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3952 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3953 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3954 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3956 /* Apply De Morgan's laws to reduce number of patterns for machines
3957 with negating logical insns (and-not, nand, etc.). If result has
3958 only one NOT, put it first, since that is how the patterns are
3961 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3963 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3964 enum machine_mode op_mode;
3966 op_mode = GET_MODE (in1);
3967 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3969 op_mode = GET_MODE (in2);
3970 if (op_mode == VOIDmode)
3972 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3974 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3977 in2 = in1; in1 = tem;
3980 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3986 /* (neg (plus X 1)) can become (not X). */
3987 if (GET_CODE (XEXP (x, 0)) == PLUS
3988 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3989 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3991 /* Similarly, (neg (not X)) is (plus X 1). */
3992 if (GET_CODE (XEXP (x, 0)) == NOT)
3993 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3995 /* (neg (minus X Y)) can become (minus Y X). This transformation
3996 isn't safe for modes with signed zeros, since if X and Y are
3997 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3998 mode is towards +infinity (or -infinity) then the two expressions
3999 will be rounded differently. */
4000 if (GET_CODE (XEXP (x, 0)) == MINUS
4001 && !HONOR_SIGNED_ZEROS (mode)
4002 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4003 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4004 XEXP (XEXP (x, 0), 0));
4006 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4007 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4008 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4009 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4011 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4012 if we can then eliminate the NEG (e.g.,
4013 if the operand is a constant). */
4015 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4017 temp = simplify_unary_operation (NEG, mode,
4018 XEXP (XEXP (x, 0), 0), mode);
4020 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4023 temp = expand_compound_operation (XEXP (x, 0));
4025 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4026 replaced by (lshiftrt X C). This will convert
4027 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4029 if (GET_CODE (temp) == ASHIFTRT
4030 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4031 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4032 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4033 INTVAL (XEXP (temp, 1)));
4035 /* If X has only a single bit that might be nonzero, say, bit I, convert
4036 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4037 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4038 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4039 or a SUBREG of one since we'd be making the expression more
4040 complex if it was just a register. */
4042 if (GET_CODE (temp) != REG
4043 && ! (GET_CODE (temp) == SUBREG
4044 && GET_CODE (SUBREG_REG (temp)) == REG)
4045 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4047 rtx temp1 = simplify_shift_const
4048 (NULL_RTX, ASHIFTRT, mode,
4049 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4050 GET_MODE_BITSIZE (mode) - 1 - i),
4051 GET_MODE_BITSIZE (mode) - 1 - i);
4053 /* If all we did was surround TEMP with the two shifts, we
4054 haven't improved anything, so don't use it. Otherwise,
4055 we are better off with TEMP1. */
4056 if (GET_CODE (temp1) != ASHIFTRT
4057 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4058 || XEXP (XEXP (temp1, 0), 0) != temp)
4064 /* We can't handle truncation to a partial integer mode here
4065 because we don't know the real bitsize of the partial
4067 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4070 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4071 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4072 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4074 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4075 GET_MODE_MASK (mode), NULL_RTX, 0));
4077 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4078 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4079 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4080 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4081 return XEXP (XEXP (x, 0), 0);
4083 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4084 (OP:SI foo:SI) if OP is NEG or ABS. */
4085 if ((GET_CODE (XEXP (x, 0)) == ABS
4086 || GET_CODE (XEXP (x, 0)) == NEG)
4087 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4088 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4089 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4090 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4091 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4093 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4095 if (GET_CODE (XEXP (x, 0)) == SUBREG
4096 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4097 && subreg_lowpart_p (XEXP (x, 0)))
4098 return SUBREG_REG (XEXP (x, 0));
4100 /* If we know that the value is already truncated, we can
4101 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4102 is nonzero for the corresponding modes. But don't do this
4103 for an (LSHIFTRT (MULT ...)) since this will cause problems
4104 with the umulXi3_highpart patterns. */
4105 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4106 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4107 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4108 >= GET_MODE_BITSIZE (mode) + 1
4109 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4110 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4111 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4113 /* A truncate of a comparison can be replaced with a subreg if
4114 STORE_FLAG_VALUE permits. This is like the previous test,
4115 but it works even if the comparison is done in a mode larger
4116 than HOST_BITS_PER_WIDE_INT. */
4117 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4118 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4119 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4120 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4122 /* Similarly, a truncate of a register whose value is a
4123 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4125 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4126 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4127 && (temp = get_last_value (XEXP (x, 0)))
4128 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4129 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4133 case FLOAT_TRUNCATE:
4134 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4135 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4136 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4137 return XEXP (XEXP (x, 0), 0);
4139 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4140 (OP:SF foo:SF) if OP is NEG or ABS. */
4141 if ((GET_CODE (XEXP (x, 0)) == ABS
4142 || GET_CODE (XEXP (x, 0)) == NEG)
4143 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4144 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4145 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4146 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4148 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4149 is (float_truncate:SF x). */
4150 if (GET_CODE (XEXP (x, 0)) == SUBREG
4151 && subreg_lowpart_p (XEXP (x, 0))
4152 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4153 return SUBREG_REG (XEXP (x, 0));
4158 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4159 using cc0, in which case we want to leave it as a COMPARE
4160 so we can distinguish it from a register-register-copy. */
4161 if (XEXP (x, 1) == const0_rtx)
4164 /* x - 0 is the same as x unless x's mode has signed zeros and
4165 allows rounding towards -infinity. Under those conditions,
4167 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4168 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4169 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4175 /* (const (const X)) can become (const X). Do it this way rather than
4176 returning the inner CONST since CONST can be shared with a
4178 if (GET_CODE (XEXP (x, 0)) == CONST)
4179 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4184 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4185 can add in an offset. find_split_point will split this address up
4186 again if it doesn't match. */
4187 if (GET_CODE (XEXP (x, 0)) == HIGH
4188 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4194 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4195 outermost. That's because that's the way indexed addresses are
4196 supposed to appear. This code used to check many more cases, but
4197 they are now checked elsewhere. */
4198 if (GET_CODE (XEXP (x, 0)) == PLUS
4199 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4200 return gen_binary (PLUS, mode,
4201 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4203 XEXP (XEXP (x, 0), 1));
4205 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4206 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4207 bit-field and can be replaced by either a sign_extend or a
4208 sign_extract. The `and' may be a zero_extend and the two
4209 <c>, -<c> constants may be reversed. */
4210 if (GET_CODE (XEXP (x, 0)) == XOR
4211 && GET_CODE (XEXP (x, 1)) == CONST_INT
4212 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4213 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4214 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4215 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4216 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4217 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4218 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4219 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4220 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4221 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4222 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4223 == (unsigned int) i + 1))))
4224 return simplify_shift_const
4225 (NULL_RTX, ASHIFTRT, mode,
4226 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4227 XEXP (XEXP (XEXP (x, 0), 0), 0),
4228 GET_MODE_BITSIZE (mode) - (i + 1)),
4229 GET_MODE_BITSIZE (mode) - (i + 1));
4231 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4232 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4233 is 1. This produces better code than the alternative immediately
4235 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4236 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4237 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4238 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4239 XEXP (XEXP (x, 0), 0),
4240 XEXP (XEXP (x, 0), 1))))
4242 simplify_gen_unary (NEG, mode, reversed, mode);
4244 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4245 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4246 the bitsize of the mode - 1. This allows simplification of
4247 "a = (b & 8) == 0;" */
4248 if (XEXP (x, 1) == constm1_rtx
4249 && GET_CODE (XEXP (x, 0)) != REG
4250 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4251 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4252 && nonzero_bits (XEXP (x, 0), mode) == 1)
4253 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4254 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4255 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4256 GET_MODE_BITSIZE (mode) - 1),
4257 GET_MODE_BITSIZE (mode) - 1);
4259 /* If we are adding two things that have no bits in common, convert
4260 the addition into an IOR. This will often be further simplified,
4261 for example in cases like ((a & 1) + (a & 2)), which can
4264 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4265 && (nonzero_bits (XEXP (x, 0), mode)
4266 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4268 /* Try to simplify the expression further. */
4269 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4270 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4272 /* If we could, great. If not, do not go ahead with the IOR
4273 replacement, since PLUS appears in many special purpose
4274 address arithmetic instructions. */
4275 if (GET_CODE (temp) != CLOBBER && temp != tor)
4281 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4282 by reversing the comparison code if valid. */
4283 if (STORE_FLAG_VALUE == 1
4284 && XEXP (x, 0) == const1_rtx
4285 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4286 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4287 XEXP (XEXP (x, 1), 0),
4288 XEXP (XEXP (x, 1), 1))))
4291 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4292 (and <foo> (const_int pow2-1)) */
4293 if (GET_CODE (XEXP (x, 1)) == AND
4294 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4295 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4296 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4297 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4298 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4300 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4302 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4303 return gen_binary (MINUS, mode,
4304 gen_binary (MINUS, mode, XEXP (x, 0),
4305 XEXP (XEXP (x, 1), 0)),
4306 XEXP (XEXP (x, 1), 1));
4310 /* If we have (mult (plus A B) C), apply the distributive law and then
4311 the inverse distributive law to see if things simplify. This
4312 occurs mostly in addresses, often when unrolling loops. */
4314 if (GET_CODE (XEXP (x, 0)) == PLUS)
4316 x = apply_distributive_law
4317 (gen_binary (PLUS, mode,
4318 gen_binary (MULT, mode,
4319 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4320 gen_binary (MULT, mode,
4321 XEXP (XEXP (x, 0), 1),
4322 copy_rtx (XEXP (x, 1)))));
4324 if (GET_CODE (x) != MULT)
4327 /* Try simplify a*(b/c) as (a*b)/c. */
4328 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4329 && GET_CODE (XEXP (x, 0)) == DIV)
4331 rtx tem = simplify_binary_operation (MULT, mode,
4332 XEXP (XEXP (x, 0), 0),
4335 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4340 /* If this is a divide by a power of two, treat it as a shift if
4341 its first operand is a shift. */
4342 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4343 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4344 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4345 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4346 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4347 || GET_CODE (XEXP (x, 0)) == ROTATE
4348 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4349 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4353 case GT: case GTU: case GE: case GEU:
4354 case LT: case LTU: case LE: case LEU:
4355 case UNEQ: case LTGT:
4356 case UNGT: case UNGE:
4357 case UNLT: case UNLE:
4358 case UNORDERED: case ORDERED:
4359 /* If the first operand is a condition code, we can't do anything
4361 if (GET_CODE (XEXP (x, 0)) == COMPARE
4362 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4364 && XEXP (x, 0) != cc0_rtx
4368 rtx op0 = XEXP (x, 0);
4369 rtx op1 = XEXP (x, 1);
4370 enum rtx_code new_code;
4372 if (GET_CODE (op0) == COMPARE)
4373 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4375 /* Simplify our comparison, if possible. */
4376 new_code = simplify_comparison (code, &op0, &op1);
4378 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4379 if only the low-order bit is possibly nonzero in X (such as when
4380 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4381 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4382 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4385 Remove any ZERO_EXTRACT we made when thinking this was a
4386 comparison. It may now be simpler to use, e.g., an AND. If a
4387 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4388 the call to make_compound_operation in the SET case. */
4390 if (STORE_FLAG_VALUE == 1
4391 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4392 && op1 == const0_rtx
4393 && mode == GET_MODE (op0)
4394 && nonzero_bits (op0, mode) == 1)
4395 return gen_lowpart_for_combine (mode,
4396 expand_compound_operation (op0));
4398 else if (STORE_FLAG_VALUE == 1
4399 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4400 && op1 == const0_rtx
4401 && mode == GET_MODE (op0)
4402 && (num_sign_bit_copies (op0, mode)
4403 == GET_MODE_BITSIZE (mode)))
4405 op0 = expand_compound_operation (op0);
4406 return simplify_gen_unary (NEG, mode,
4407 gen_lowpart_for_combine (mode, op0),
4411 else if (STORE_FLAG_VALUE == 1
4412 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4413 && op1 == const0_rtx
4414 && mode == GET_MODE (op0)
4415 && nonzero_bits (op0, mode) == 1)
4417 op0 = expand_compound_operation (op0);
4418 return gen_binary (XOR, mode,
4419 gen_lowpart_for_combine (mode, op0),
4423 else if (STORE_FLAG_VALUE == 1
4424 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4425 && op1 == const0_rtx
4426 && mode == GET_MODE (op0)
4427 && (num_sign_bit_copies (op0, mode)
4428 == GET_MODE_BITSIZE (mode)))
4430 op0 = expand_compound_operation (op0);
4431 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4434 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4436 if (STORE_FLAG_VALUE == -1
4437 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4438 && op1 == const0_rtx
4439 && (num_sign_bit_copies (op0, mode)
4440 == GET_MODE_BITSIZE (mode)))
4441 return gen_lowpart_for_combine (mode,
4442 expand_compound_operation (op0));
4444 else if (STORE_FLAG_VALUE == -1
4445 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4446 && op1 == const0_rtx
4447 && mode == GET_MODE (op0)
4448 && nonzero_bits (op0, mode) == 1)
4450 op0 = expand_compound_operation (op0);
4451 return simplify_gen_unary (NEG, mode,
4452 gen_lowpart_for_combine (mode, op0),
4456 else if (STORE_FLAG_VALUE == -1
4457 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4458 && op1 == const0_rtx
4459 && mode == GET_MODE (op0)
4460 && (num_sign_bit_copies (op0, mode)
4461 == GET_MODE_BITSIZE (mode)))
4463 op0 = expand_compound_operation (op0);
4464 return simplify_gen_unary (NOT, mode,
4465 gen_lowpart_for_combine (mode, op0),
4469 /* If X is 0/1, (eq X 0) is X-1. */
4470 else if (STORE_FLAG_VALUE == -1
4471 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4472 && op1 == const0_rtx
4473 && mode == GET_MODE (op0)
4474 && nonzero_bits (op0, mode) == 1)
4476 op0 = expand_compound_operation (op0);
4477 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4480 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4481 one bit that might be nonzero, we can convert (ne x 0) to
4482 (ashift x c) where C puts the bit in the sign bit. Remove any
4483 AND with STORE_FLAG_VALUE when we are done, since we are only
4484 going to test the sign bit. */
4485 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4486 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4487 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4488 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4489 && op1 == const0_rtx
4490 && mode == GET_MODE (op0)
4491 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4493 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4494 expand_compound_operation (op0),
4495 GET_MODE_BITSIZE (mode) - 1 - i);
4496 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4502 /* If the code changed, return a whole new comparison. */
4503 if (new_code != code)
4504 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4506 /* Otherwise, keep this operation, but maybe change its operands.
4507 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4508 SUBST (XEXP (x, 0), op0);
4509 SUBST (XEXP (x, 1), op1);
4514 return simplify_if_then_else (x);
4520 /* If we are processing SET_DEST, we are done. */
4524 return expand_compound_operation (x);
4527 return simplify_set (x);
4532 return simplify_logical (x, last);
4535 /* (abs (neg <foo>)) -> (abs <foo>) */
4536 if (GET_CODE (XEXP (x, 0)) == NEG)
4537 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4539 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4541 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4544 /* If operand is something known to be positive, ignore the ABS. */
4545 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4546 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4547 <= HOST_BITS_PER_WIDE_INT)
4548 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4549 & ((HOST_WIDE_INT) 1
4550 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4554 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4555 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4556 return gen_rtx_NEG (mode, XEXP (x, 0));
4561 /* (ffs (*_extend <X>)) = (ffs <X>) */
4562 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4563 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4564 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4568 /* (float (sign_extend <X>)) = (float <X>). */
4569 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4570 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4578 /* If this is a shift by a constant amount, simplify it. */
4579 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4580 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4581 INTVAL (XEXP (x, 1)));
4583 #ifdef SHIFT_COUNT_TRUNCATED
4584 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4586 force_to_mode (XEXP (x, 1), GET_MODE (x),
4588 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4597 rtx op0 = XEXP (x, 0);
4598 rtx op1 = XEXP (x, 1);
4601 if (GET_CODE (op1) != PARALLEL)
4603 len = XVECLEN (op1, 0);
4605 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4606 && GET_CODE (op0) == VEC_CONCAT)
4608 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4610 /* Try to find the element in the VEC_CONCAT. */
4613 if (GET_MODE (op0) == GET_MODE (x))
4615 if (GET_CODE (op0) == VEC_CONCAT)
4617 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4618 if (op0_size < offset)
4619 op0 = XEXP (op0, 0);
4623 op0 = XEXP (op0, 1);
4641 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4644 simplify_if_then_else (x)
4647 enum machine_mode mode = GET_MODE (x);
4648 rtx cond = XEXP (x, 0);
4649 rtx true_rtx = XEXP (x, 1);
4650 rtx false_rtx = XEXP (x, 2);
4651 enum rtx_code true_code = GET_CODE (cond);
4652 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4655 enum rtx_code false_code;
4658 /* Simplify storing of the truth value. */
4659 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4660 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4662 /* Also when the truth value has to be reversed. */
4664 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4665 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4669 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4670 in it is being compared against certain values. Get the true and false
4671 comparisons and see if that says anything about the value of each arm. */
4674 && ((false_code = combine_reversed_comparison_code (cond))
4676 && GET_CODE (XEXP (cond, 0)) == REG)
4679 rtx from = XEXP (cond, 0);
4680 rtx true_val = XEXP (cond, 1);
4681 rtx false_val = true_val;
4684 /* If FALSE_CODE is EQ, swap the codes and arms. */
4686 if (false_code == EQ)
4688 swapped = 1, true_code = EQ, false_code = NE;
4689 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4692 /* If we are comparing against zero and the expression being tested has
4693 only a single bit that might be nonzero, that is its value when it is
4694 not equal to zero. Similarly if it is known to be -1 or 0. */
4696 if (true_code == EQ && true_val == const0_rtx
4697 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4698 false_code = EQ, false_val = GEN_INT (nzb);
4699 else if (true_code == EQ && true_val == const0_rtx
4700 && (num_sign_bit_copies (from, GET_MODE (from))
4701 == GET_MODE_BITSIZE (GET_MODE (from))))
4702 false_code = EQ, false_val = constm1_rtx;
4704 /* Now simplify an arm if we know the value of the register in the
4705 branch and it is used in the arm. Be careful due to the potential
4706 of locally-shared RTL. */
4708 if (reg_mentioned_p (from, true_rtx))
4709 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4711 pc_rtx, pc_rtx, 0, 0);
4712 if (reg_mentioned_p (from, false_rtx))
4713 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4715 pc_rtx, pc_rtx, 0, 0);
4717 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4718 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4720 true_rtx = XEXP (x, 1);
4721 false_rtx = XEXP (x, 2);
4722 true_code = GET_CODE (cond);
4725 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4726 reversed, do so to avoid needing two sets of patterns for
4727 subtract-and-branch insns. Similarly if we have a constant in the true
4728 arm, the false arm is the same as the first operand of the comparison, or
4729 the false arm is more complicated than the true arm. */
4732 && combine_reversed_comparison_code (cond) != UNKNOWN
4733 && (true_rtx == pc_rtx
4734 || (CONSTANT_P (true_rtx)
4735 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4736 || true_rtx == const0_rtx
4737 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4738 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4739 || (GET_CODE (true_rtx) == SUBREG
4740 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4741 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4742 || reg_mentioned_p (true_rtx, false_rtx)
4743 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4745 true_code = reversed_comparison_code (cond, NULL);
4747 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4750 SUBST (XEXP (x, 1), false_rtx);
4751 SUBST (XEXP (x, 2), true_rtx);
4753 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4756 /* It is possible that the conditional has been simplified out. */
4757 true_code = GET_CODE (cond);
4758 comparison_p = GET_RTX_CLASS (true_code) == '<';
4761 /* If the two arms are identical, we don't need the comparison. */
4763 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4766 /* Convert a == b ? b : a to "a". */
4767 if (true_code == EQ && ! side_effects_p (cond)
4768 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4769 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4770 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4772 else if (true_code == NE && ! side_effects_p (cond)
4773 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4774 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4775 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4778 /* Look for cases where we have (abs x) or (neg (abs X)). */
4780 if (GET_MODE_CLASS (mode) == MODE_INT
4781 && GET_CODE (false_rtx) == NEG
4782 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4784 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4785 && ! side_effects_p (true_rtx))
4790 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4794 simplify_gen_unary (NEG, mode,
4795 simplify_gen_unary (ABS, mode, true_rtx, mode),
4801 /* Look for MIN or MAX. */
4803 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4805 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4806 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4807 && ! side_effects_p (cond))
4812 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4815 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4818 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4821 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4826 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4827 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4828 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4829 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4830 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4831 neither 1 or -1, but it isn't worth checking for. */
4833 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4834 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4836 rtx t = make_compound_operation (true_rtx, SET);
4837 rtx f = make_compound_operation (false_rtx, SET);
4838 rtx cond_op0 = XEXP (cond, 0);
4839 rtx cond_op1 = XEXP (cond, 1);
4840 enum rtx_code op = NIL, extend_op = NIL;
4841 enum machine_mode m = mode;
4842 rtx z = 0, c1 = NULL_RTX;
4844 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4845 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4846 || GET_CODE (t) == ASHIFT
4847 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4848 && rtx_equal_p (XEXP (t, 0), f))
4849 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4851 /* If an identity-zero op is commutative, check whether there
4852 would be a match if we swapped the operands. */
4853 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4854 || GET_CODE (t) == XOR)
4855 && rtx_equal_p (XEXP (t, 1), f))
4856 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4857 else if (GET_CODE (t) == SIGN_EXTEND
4858 && (GET_CODE (XEXP (t, 0)) == PLUS
4859 || GET_CODE (XEXP (t, 0)) == MINUS
4860 || GET_CODE (XEXP (t, 0)) == IOR
4861 || GET_CODE (XEXP (t, 0)) == XOR
4862 || GET_CODE (XEXP (t, 0)) == ASHIFT
4863 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4864 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4865 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4866 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4867 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4868 && (num_sign_bit_copies (f, GET_MODE (f))
4869 > (GET_MODE_BITSIZE (mode)
4870 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4872 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4873 extend_op = SIGN_EXTEND;
4874 m = GET_MODE (XEXP (t, 0));
4876 else if (GET_CODE (t) == SIGN_EXTEND
4877 && (GET_CODE (XEXP (t, 0)) == PLUS
4878 || GET_CODE (XEXP (t, 0)) == IOR
4879 || GET_CODE (XEXP (t, 0)) == XOR)
4880 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4881 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4882 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4883 && (num_sign_bit_copies (f, GET_MODE (f))
4884 > (GET_MODE_BITSIZE (mode)
4885 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4887 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4888 extend_op = SIGN_EXTEND;
4889 m = GET_MODE (XEXP (t, 0));
4891 else if (GET_CODE (t) == ZERO_EXTEND
4892 && (GET_CODE (XEXP (t, 0)) == PLUS
4893 || GET_CODE (XEXP (t, 0)) == MINUS
4894 || GET_CODE (XEXP (t, 0)) == IOR
4895 || GET_CODE (XEXP (t, 0)) == XOR
4896 || GET_CODE (XEXP (t, 0)) == ASHIFT
4897 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4898 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4899 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4900 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4901 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4902 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4903 && ((nonzero_bits (f, GET_MODE (f))
4904 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4907 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4908 extend_op = ZERO_EXTEND;
4909 m = GET_MODE (XEXP (t, 0));
4911 else if (GET_CODE (t) == ZERO_EXTEND
4912 && (GET_CODE (XEXP (t, 0)) == PLUS
4913 || GET_CODE (XEXP (t, 0)) == IOR
4914 || GET_CODE (XEXP (t, 0)) == XOR)
4915 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4916 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4917 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4918 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4919 && ((nonzero_bits (f, GET_MODE (f))
4920 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4923 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4924 extend_op = ZERO_EXTEND;
4925 m = GET_MODE (XEXP (t, 0));
4930 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4931 pc_rtx, pc_rtx, 0, 0);
4932 temp = gen_binary (MULT, m, temp,
4933 gen_binary (MULT, m, c1, const_true_rtx));
4934 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4935 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4937 if (extend_op != NIL)
4938 temp = simplify_gen_unary (extend_op, mode, temp, m);
4944 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4945 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4946 negation of a single bit, we can convert this operation to a shift. We
4947 can actually do this more generally, but it doesn't seem worth it. */
4949 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4950 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4951 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4952 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4953 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4954 == GET_MODE_BITSIZE (mode))
4955 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4957 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4958 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4963 /* Simplify X, a SET expression. Return the new expression. */
4969 rtx src = SET_SRC (x);
4970 rtx dest = SET_DEST (x);
4971 enum machine_mode mode
4972 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4976 /* (set (pc) (return)) gets written as (return). */
4977 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4980 /* Now that we know for sure which bits of SRC we are using, see if we can
4981 simplify the expression for the object knowing that we only need the
4984 if (GET_MODE_CLASS (mode) == MODE_INT)
4986 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4987 SUBST (SET_SRC (x), src);
4990 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4991 the comparison result and try to simplify it unless we already have used
4992 undobuf.other_insn. */
4993 if ((GET_CODE (src) == COMPARE
4998 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4999 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5000 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5001 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5003 enum rtx_code old_code = GET_CODE (*cc_use);
5004 enum rtx_code new_code;
5006 int other_changed = 0;
5007 enum machine_mode compare_mode = GET_MODE (dest);
5009 if (GET_CODE (src) == COMPARE)
5010 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5012 op0 = src, op1 = const0_rtx;
5014 /* Simplify our comparison, if possible. */
5015 new_code = simplify_comparison (old_code, &op0, &op1);
5017 #ifdef EXTRA_CC_MODES
5018 /* If this machine has CC modes other than CCmode, check to see if we
5019 need to use a different CC mode here. */
5020 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5021 #endif /* EXTRA_CC_MODES */
5023 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5024 /* If the mode changed, we have to change SET_DEST, the mode in the
5025 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5026 a hard register, just build new versions with the proper mode. If it
5027 is a pseudo, we lose unless it is only time we set the pseudo, in
5028 which case we can safely change its mode. */
5029 if (compare_mode != GET_MODE (dest))
5031 unsigned int regno = REGNO (dest);
5032 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5034 if (regno < FIRST_PSEUDO_REGISTER
5035 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5037 if (regno >= FIRST_PSEUDO_REGISTER)
5038 SUBST (regno_reg_rtx[regno], new_dest);
5040 SUBST (SET_DEST (x), new_dest);
5041 SUBST (XEXP (*cc_use, 0), new_dest);
5049 /* If the code changed, we have to build a new comparison in
5050 undobuf.other_insn. */
5051 if (new_code != old_code)
5053 unsigned HOST_WIDE_INT mask;
5055 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5058 /* If the only change we made was to change an EQ into an NE or
5059 vice versa, OP0 has only one bit that might be nonzero, and OP1
5060 is zero, check if changing the user of the condition code will
5061 produce a valid insn. If it won't, we can keep the original code
5062 in that insn by surrounding our operation with an XOR. */
5064 if (((old_code == NE && new_code == EQ)
5065 || (old_code == EQ && new_code == NE))
5066 && ! other_changed && op1 == const0_rtx
5067 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5068 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5070 rtx pat = PATTERN (other_insn), note = 0;
5072 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5073 && ! check_asm_operands (pat)))
5075 PUT_CODE (*cc_use, old_code);
5078 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5086 undobuf.other_insn = other_insn;
5089 /* If we are now comparing against zero, change our source if
5090 needed. If we do not use cc0, we always have a COMPARE. */
5091 if (op1 == const0_rtx && dest == cc0_rtx)
5093 SUBST (SET_SRC (x), op0);
5099 /* Otherwise, if we didn't previously have a COMPARE in the
5100 correct mode, we need one. */
5101 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5103 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5108 /* Otherwise, update the COMPARE if needed. */
5109 SUBST (XEXP (src, 0), op0);
5110 SUBST (XEXP (src, 1), op1);
5115 /* Get SET_SRC in a form where we have placed back any
5116 compound expressions. Then do the checks below. */
5117 src = make_compound_operation (src, SET);
5118 SUBST (SET_SRC (x), src);
5121 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5122 and X being a REG or (subreg (reg)), we may be able to convert this to
5123 (set (subreg:m2 x) (op)).
5125 We can always do this if M1 is narrower than M2 because that means that
5126 we only care about the low bits of the result.
5128 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5129 perform a narrower operation than requested since the high-order bits will
5130 be undefined. On machine where it is defined, this transformation is safe
5131 as long as M1 and M2 have the same number of words. */
5133 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5134 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5135 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5137 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5138 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5139 #ifndef WORD_REGISTER_OPERATIONS
5140 && (GET_MODE_SIZE (GET_MODE (src))
5141 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5143 #ifdef CLASS_CANNOT_CHANGE_MODE
5144 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5145 && (TEST_HARD_REG_BIT
5146 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5148 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5149 GET_MODE (SUBREG_REG (src))))
5151 && (GET_CODE (dest) == REG
5152 || (GET_CODE (dest) == SUBREG
5153 && GET_CODE (SUBREG_REG (dest)) == REG)))
5155 SUBST (SET_DEST (x),
5156 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5158 SUBST (SET_SRC (x), SUBREG_REG (src));
5160 src = SET_SRC (x), dest = SET_DEST (x);
5164 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5167 && GET_CODE (src) == SUBREG
5168 && subreg_lowpart_p (src)
5169 && (GET_MODE_BITSIZE (GET_MODE (src))
5170 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5172 rtx inner = SUBREG_REG (src);
5173 enum machine_mode inner_mode = GET_MODE (inner);
5175 /* Here we make sure that we don't have a sign bit on. */
5176 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5177 && (nonzero_bits (inner, inner_mode)
5178 < ((unsigned HOST_WIDE_INT) 1
5179 << (GET_MODE_BITSIZE (inner_mode) - 1))))
5181 SUBST (SET_SRC (x), inner);
5187 #ifdef LOAD_EXTEND_OP
5188 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5189 would require a paradoxical subreg. Replace the subreg with a
5190 zero_extend to avoid the reload that would otherwise be required. */
5192 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5193 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5194 && SUBREG_BYTE (src) == 0
5195 && (GET_MODE_SIZE (GET_MODE (src))
5196 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5197 && GET_CODE (SUBREG_REG (src)) == MEM)
5200 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5201 GET_MODE (src), SUBREG_REG (src)));
5207 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5208 are comparing an item known to be 0 or -1 against 0, use a logical
5209 operation instead. Check for one of the arms being an IOR of the other
5210 arm with some value. We compute three terms to be IOR'ed together. In
5211 practice, at most two will be nonzero. Then we do the IOR's. */
5213 if (GET_CODE (dest) != PC
5214 && GET_CODE (src) == IF_THEN_ELSE
5215 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5216 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5217 && XEXP (XEXP (src, 0), 1) == const0_rtx
5218 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5219 #ifdef HAVE_conditional_move
5220 && ! can_conditionally_move_p (GET_MODE (src))
5222 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5223 GET_MODE (XEXP (XEXP (src, 0), 0)))
5224 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5225 && ! side_effects_p (src))
5227 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5228 ? XEXP (src, 1) : XEXP (src, 2));
5229 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5230 ? XEXP (src, 2) : XEXP (src, 1));
5231 rtx term1 = const0_rtx, term2, term3;
5233 if (GET_CODE (true_rtx) == IOR
5234 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5235 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5236 else if (GET_CODE (true_rtx) == IOR
5237 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5238 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5239 else if (GET_CODE (false_rtx) == IOR
5240 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5241 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5242 else if (GET_CODE (false_rtx) == IOR
5243 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5244 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5246 term2 = gen_binary (AND, GET_MODE (src),
5247 XEXP (XEXP (src, 0), 0), true_rtx);
5248 term3 = gen_binary (AND, GET_MODE (src),
5249 simplify_gen_unary (NOT, GET_MODE (src),
5250 XEXP (XEXP (src, 0), 0),
5255 gen_binary (IOR, GET_MODE (src),
5256 gen_binary (IOR, GET_MODE (src), term1, term2),
5262 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5263 whole thing fail. */
5264 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5266 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5269 /* Convert this into a field assignment operation, if possible. */
5270 return make_field_assignment (x);
5273 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5274 result. LAST is nonzero if this is the last retry. */
5277 simplify_logical (x, last)
5281 enum machine_mode mode = GET_MODE (x);
5282 rtx op0 = XEXP (x, 0);
5283 rtx op1 = XEXP (x, 1);
5286 switch (GET_CODE (x))
5289 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5290 insn (and may simplify more). */
5291 if (GET_CODE (op0) == XOR
5292 && rtx_equal_p (XEXP (op0, 0), op1)
5293 && ! side_effects_p (op1))
5294 x = gen_binary (AND, mode,
5295 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5298 if (GET_CODE (op0) == XOR
5299 && rtx_equal_p (XEXP (op0, 1), op1)
5300 && ! side_effects_p (op1))
5301 x = gen_binary (AND, mode,
5302 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5305 /* Similarly for (~(A ^ B)) & A. */
5306 if (GET_CODE (op0) == NOT
5307 && GET_CODE (XEXP (op0, 0)) == XOR
5308 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5309 && ! side_effects_p (op1))
5310 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5312 if (GET_CODE (op0) == NOT
5313 && GET_CODE (XEXP (op0, 0)) == XOR
5314 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5315 && ! side_effects_p (op1))
5316 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5318 /* We can call simplify_and_const_int only if we don't lose
5319 any (sign) bits when converting INTVAL (op1) to
5320 "unsigned HOST_WIDE_INT". */
5321 if (GET_CODE (op1) == CONST_INT
5322 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5323 || INTVAL (op1) > 0))
5325 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5327 /* If we have (ior (and (X C1) C2)) and the next restart would be
5328 the last, simplify this by making C1 as small as possible
5331 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5332 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5333 && GET_CODE (op1) == CONST_INT)
5334 return gen_binary (IOR, mode,
5335 gen_binary (AND, mode, XEXP (op0, 0),
5336 GEN_INT (INTVAL (XEXP (op0, 1))
5337 & ~INTVAL (op1))), op1);
5339 if (GET_CODE (x) != AND)
5342 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5343 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5344 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5347 /* Convert (A | B) & A to A. */
5348 if (GET_CODE (op0) == IOR
5349 && (rtx_equal_p (XEXP (op0, 0), op1)
5350 || rtx_equal_p (XEXP (op0, 1), op1))
5351 && ! side_effects_p (XEXP (op0, 0))
5352 && ! side_effects_p (XEXP (op0, 1)))
5355 /* In the following group of tests (and those in case IOR below),
5356 we start with some combination of logical operations and apply
5357 the distributive law followed by the inverse distributive law.
5358 Most of the time, this results in no change. However, if some of
5359 the operands are the same or inverses of each other, simplifications
5362 For example, (and (ior A B) (not B)) can occur as the result of
5363 expanding a bit field assignment. When we apply the distributive
5364 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5365 which then simplifies to (and (A (not B))).
5367 If we have (and (ior A B) C), apply the distributive law and then
5368 the inverse distributive law to see if things simplify. */
5370 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5372 x = apply_distributive_law
5373 (gen_binary (GET_CODE (op0), mode,
5374 gen_binary (AND, mode, XEXP (op0, 0), op1),
5375 gen_binary (AND, mode, XEXP (op0, 1),
5377 if (GET_CODE (x) != AND)
5381 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5382 return apply_distributive_law
5383 (gen_binary (GET_CODE (op1), mode,
5384 gen_binary (AND, mode, XEXP (op1, 0), op0),
5385 gen_binary (AND, mode, XEXP (op1, 1),
5388 /* Similarly, taking advantage of the fact that
5389 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5391 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5392 return apply_distributive_law
5393 (gen_binary (XOR, mode,
5394 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5395 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5398 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5399 return apply_distributive_law
5400 (gen_binary (XOR, mode,
5401 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5402 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5406 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5407 if (GET_CODE (op1) == CONST_INT
5408 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5409 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5412 /* Convert (A & B) | A to A. */
5413 if (GET_CODE (op0) == AND
5414 && (rtx_equal_p (XEXP (op0, 0), op1)
5415 || rtx_equal_p (XEXP (op0, 1), op1))
5416 && ! side_effects_p (XEXP (op0, 0))
5417 && ! side_effects_p (XEXP (op0, 1)))
5420 /* If we have (ior (and A B) C), apply the distributive law and then
5421 the inverse distributive law to see if things simplify. */
5423 if (GET_CODE (op0) == AND)
5425 x = apply_distributive_law
5426 (gen_binary (AND, mode,
5427 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5428 gen_binary (IOR, mode, XEXP (op0, 1),
5431 if (GET_CODE (x) != IOR)
5435 if (GET_CODE (op1) == AND)
5437 x = apply_distributive_law
5438 (gen_binary (AND, mode,
5439 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5440 gen_binary (IOR, mode, XEXP (op1, 1),
5443 if (GET_CODE (x) != IOR)
5447 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5448 mode size to (rotate A CX). */
5450 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5451 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5452 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5453 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5454 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5455 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5456 == GET_MODE_BITSIZE (mode)))
5457 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5458 (GET_CODE (op0) == ASHIFT
5459 ? XEXP (op0, 1) : XEXP (op1, 1)));
5461 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5462 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5463 does not affect any of the bits in OP1, it can really be done
5464 as a PLUS and we can associate. We do this by seeing if OP1
5465 can be safely shifted left C bits. */
5466 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5467 && GET_CODE (XEXP (op0, 0)) == PLUS
5468 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5469 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5470 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5472 int count = INTVAL (XEXP (op0, 1));
5473 HOST_WIDE_INT mask = INTVAL (op1) << count;
5475 if (mask >> count == INTVAL (op1)
5476 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5478 SUBST (XEXP (XEXP (op0, 0), 1),
5479 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5486 /* If we are XORing two things that have no bits in common,
5487 convert them into an IOR. This helps to detect rotation encoded
5488 using those methods and possibly other simplifications. */
5490 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5491 && (nonzero_bits (op0, mode)
5492 & nonzero_bits (op1, mode)) == 0)
5493 return (gen_binary (IOR, mode, op0, op1));
5495 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5496 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5499 int num_negated = 0;
5501 if (GET_CODE (op0) == NOT)
5502 num_negated++, op0 = XEXP (op0, 0);
5503 if (GET_CODE (op1) == NOT)
5504 num_negated++, op1 = XEXP (op1, 0);
5506 if (num_negated == 2)
5508 SUBST (XEXP (x, 0), op0);
5509 SUBST (XEXP (x, 1), op1);
5511 else if (num_negated == 1)
5513 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5517 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5518 correspond to a machine insn or result in further simplifications
5519 if B is a constant. */
5521 if (GET_CODE (op0) == AND
5522 && rtx_equal_p (XEXP (op0, 1), op1)
5523 && ! side_effects_p (op1))
5524 return gen_binary (AND, mode,
5525 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5528 else if (GET_CODE (op0) == AND
5529 && rtx_equal_p (XEXP (op0, 0), op1)
5530 && ! side_effects_p (op1))
5531 return gen_binary (AND, mode,
5532 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5535 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5536 comparison if STORE_FLAG_VALUE is 1. */
5537 if (STORE_FLAG_VALUE == 1
5538 && op1 == const1_rtx
5539 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5540 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5544 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5545 is (lt foo (const_int 0)), so we can perform the above
5546 simplification if STORE_FLAG_VALUE is 1. */
5548 if (STORE_FLAG_VALUE == 1
5549 && op1 == const1_rtx
5550 && GET_CODE (op0) == LSHIFTRT
5551 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5552 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5553 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5555 /* (xor (comparison foo bar) (const_int sign-bit))
5556 when STORE_FLAG_VALUE is the sign bit. */
5557 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5558 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5559 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5560 && op1 == const_true_rtx
5561 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5562 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5575 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5576 operations" because they can be replaced with two more basic operations.
5577 ZERO_EXTEND is also considered "compound" because it can be replaced with
5578 an AND operation, which is simpler, though only one operation.
5580 The function expand_compound_operation is called with an rtx expression
5581 and will convert it to the appropriate shifts and AND operations,
5582 simplifying at each stage.
5584 The function make_compound_operation is called to convert an expression
5585 consisting of shifts and ANDs into the equivalent compound expression.
5586 It is the inverse of this function, loosely speaking. */
5589 expand_compound_operation (x)
5592 unsigned HOST_WIDE_INT pos = 0, len;
5594 unsigned int modewidth;
5597 switch (GET_CODE (x))
5602 /* We can't necessarily use a const_int for a multiword mode;
5603 it depends on implicitly extending the value.
5604 Since we don't know the right way to extend it,
5605 we can't tell whether the implicit way is right.
5607 Even for a mode that is no wider than a const_int,
5608 we can't win, because we need to sign extend one of its bits through
5609 the rest of it, and we don't know which bit. */
5610 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5613 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5614 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5615 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5616 reloaded. If not for that, MEM's would very rarely be safe.
5618 Reject MODEs bigger than a word, because we might not be able
5619 to reference a two-register group starting with an arbitrary register
5620 (and currently gen_lowpart might crash for a SUBREG). */
5622 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5625 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5626 /* If the inner object has VOIDmode (the only way this can happen
5627 is if it is an ASM_OPERANDS), we can't do anything since we don't
5628 know how much masking to do. */
5637 /* If the operand is a CLOBBER, just return it. */
5638 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5641 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5642 || GET_CODE (XEXP (x, 2)) != CONST_INT
5643 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5646 len = INTVAL (XEXP (x, 1));
5647 pos = INTVAL (XEXP (x, 2));
5649 /* If this goes outside the object being extracted, replace the object
5650 with a (use (mem ...)) construct that only combine understands
5651 and is used only for this purpose. */
5652 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5653 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5655 if (BITS_BIG_ENDIAN)
5656 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5663 /* Convert sign extension to zero extension, if we know that the high
5664 bit is not set, as this is easier to optimize. It will be converted
5665 back to cheaper alternative in make_extraction. */
5666 if (GET_CODE (x) == SIGN_EXTEND
5667 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5668 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5669 & ~(((unsigned HOST_WIDE_INT)
5670 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5674 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5675 return expand_compound_operation (temp);
5678 /* We can optimize some special cases of ZERO_EXTEND. */
5679 if (GET_CODE (x) == ZERO_EXTEND)
5681 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5682 know that the last value didn't have any inappropriate bits
5684 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5685 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5686 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5687 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5688 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5689 return XEXP (XEXP (x, 0), 0);
5691 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5692 if (GET_CODE (XEXP (x, 0)) == SUBREG
5693 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5694 && subreg_lowpart_p (XEXP (x, 0))
5695 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5696 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5697 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5698 return SUBREG_REG (XEXP (x, 0));
5700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5701 is a comparison and STORE_FLAG_VALUE permits. This is like
5702 the first case, but it works even when GET_MODE (x) is larger
5703 than HOST_WIDE_INT. */
5704 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5705 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5706 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5707 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5708 <= HOST_BITS_PER_WIDE_INT)
5709 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5710 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5711 return XEXP (XEXP (x, 0), 0);
5713 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5714 if (GET_CODE (XEXP (x, 0)) == SUBREG
5715 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5716 && subreg_lowpart_p (XEXP (x, 0))
5717 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5719 <= HOST_BITS_PER_WIDE_INT)
5720 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5722 return SUBREG_REG (XEXP (x, 0));
5726 /* If we reach here, we want to return a pair of shifts. The inner
5727 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5728 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5729 logical depending on the value of UNSIGNEDP.
5731 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5732 converted into an AND of a shift.
5734 We must check for the case where the left shift would have a negative
5735 count. This can happen in a case like (x >> 31) & 255 on machines
5736 that can't shift by a constant. On those machines, we would first
5737 combine the shift with the AND to produce a variable-position
5738 extraction. Then the constant of 31 would be substituted in to produce
5739 a such a position. */
5741 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5742 if (modewidth + len >= pos)
5743 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5745 simplify_shift_const (NULL_RTX, ASHIFT,
5748 modewidth - pos - len),
5751 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5752 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5753 simplify_shift_const (NULL_RTX, LSHIFTRT,
5756 ((HOST_WIDE_INT) 1 << len) - 1);
5758 /* Any other cases we can't handle. */
5761 /* If we couldn't do this for some reason, return the original
5763 if (GET_CODE (tem) == CLOBBER)
5769 /* X is a SET which contains an assignment of one object into
5770 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5771 or certain SUBREGS). If possible, convert it into a series of
5774 We half-heartedly support variable positions, but do not at all
5775 support variable lengths. */
5778 expand_field_assignment (x)
5782 rtx pos; /* Always counts from low bit. */
5785 enum machine_mode compute_mode;
5787 /* Loop until we find something we can't simplify. */
5790 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5791 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5793 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5794 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5795 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5797 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5798 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5800 inner = XEXP (SET_DEST (x), 0);
5801 len = INTVAL (XEXP (SET_DEST (x), 1));
5802 pos = XEXP (SET_DEST (x), 2);
5804 /* If the position is constant and spans the width of INNER,
5805 surround INNER with a USE to indicate this. */
5806 if (GET_CODE (pos) == CONST_INT
5807 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5808 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5810 if (BITS_BIG_ENDIAN)
5812 if (GET_CODE (pos) == CONST_INT)
5813 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5815 else if (GET_CODE (pos) == MINUS
5816 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5817 && (INTVAL (XEXP (pos, 1))
5818 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5819 /* If position is ADJUST - X, new position is X. */
5820 pos = XEXP (pos, 0);
5822 pos = gen_binary (MINUS, GET_MODE (pos),
5823 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5829 /* A SUBREG between two modes that occupy the same numbers of words
5830 can be done by moving the SUBREG to the source. */
5831 else if (GET_CODE (SET_DEST (x)) == SUBREG
5832 /* We need SUBREGs to compute nonzero_bits properly. */
5833 && nonzero_sign_valid
5834 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5835 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5836 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5837 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5839 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5840 gen_lowpart_for_combine
5841 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5848 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5849 inner = SUBREG_REG (inner);
5851 compute_mode = GET_MODE (inner);
5853 /* Don't attempt bitwise arithmetic on non-integral modes. */
5854 if (! INTEGRAL_MODE_P (compute_mode))
5856 enum machine_mode imode;
5858 /* Something is probably seriously wrong if this matches. */
5859 if (! FLOAT_MODE_P (compute_mode))
5862 /* Try to find an integral mode to pun with. */
5863 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5864 if (imode == BLKmode)
5867 compute_mode = imode;
5868 inner = gen_lowpart_for_combine (imode, inner);
5871 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5872 if (len < HOST_BITS_PER_WIDE_INT)
5873 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5877 /* Now compute the equivalent expression. Make a copy of INNER
5878 for the SET_DEST in case it is a MEM into which we will substitute;
5879 we don't want shared RTL in that case. */
5881 (VOIDmode, copy_rtx (inner),
5882 gen_binary (IOR, compute_mode,
5883 gen_binary (AND, compute_mode,
5884 simplify_gen_unary (NOT, compute_mode,
5890 gen_binary (ASHIFT, compute_mode,
5891 gen_binary (AND, compute_mode,
5892 gen_lowpart_for_combine
5893 (compute_mode, SET_SRC (x)),
5901 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5902 it is an RTX that represents a variable starting position; otherwise,
5903 POS is the (constant) starting bit position (counted from the LSB).
5905 INNER may be a USE. This will occur when we started with a bitfield
5906 that went outside the boundary of the object in memory, which is
5907 allowed on most machines. To isolate this case, we produce a USE
5908 whose mode is wide enough and surround the MEM with it. The only
5909 code that understands the USE is this routine. If it is not removed,
5910 it will cause the resulting insn not to match.
5912 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5915 IN_DEST is non-zero if this is a reference in the destination of a
5916 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5917 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5920 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5921 ZERO_EXTRACT should be built even for bits starting at bit 0.
5923 MODE is the desired mode of the result (if IN_DEST == 0).
5925 The result is an RTX for the extraction or NULL_RTX if the target
5929 make_extraction (mode, inner, pos, pos_rtx, len,
5930 unsignedp, in_dest, in_compare)
5931 enum machine_mode mode;
5935 unsigned HOST_WIDE_INT len;
5937 int in_dest, in_compare;
5939 /* This mode describes the size of the storage area
5940 to fetch the overall value from. Within that, we
5941 ignore the POS lowest bits, etc. */
5942 enum machine_mode is_mode = GET_MODE (inner);
5943 enum machine_mode inner_mode;
5944 enum machine_mode wanted_inner_mode = byte_mode;
5945 enum machine_mode wanted_inner_reg_mode = word_mode;
5946 enum machine_mode pos_mode = word_mode;
5947 enum machine_mode extraction_mode = word_mode;
5948 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5951 rtx orig_pos_rtx = pos_rtx;
5952 HOST_WIDE_INT orig_pos;
5954 /* Get some information about INNER and get the innermost object. */
5955 if (GET_CODE (inner) == USE)
5956 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5957 /* We don't need to adjust the position because we set up the USE
5958 to pretend that it was a full-word object. */
5959 spans_byte = 1, inner = XEXP (inner, 0);
5960 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5962 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5963 consider just the QI as the memory to extract from.
5964 The subreg adds or removes high bits; its mode is
5965 irrelevant to the meaning of this extraction,
5966 since POS and LEN count from the lsb. */
5967 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5968 is_mode = GET_MODE (SUBREG_REG (inner));
5969 inner = SUBREG_REG (inner);
5972 inner_mode = GET_MODE (inner);
5974 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5975 pos = INTVAL (pos_rtx), pos_rtx = 0;
5977 /* See if this can be done without an extraction. We never can if the
5978 width of the field is not the same as that of some integer mode. For
5979 registers, we can only avoid the extraction if the position is at the
5980 low-order bit and this is either not in the destination or we have the
5981 appropriate STRICT_LOW_PART operation available.
5983 For MEM, we can avoid an extract if the field starts on an appropriate
5984 boundary and we can change the mode of the memory reference. However,
5985 we cannot directly access the MEM if we have a USE and the underlying
5986 MEM is not TMODE. This combination means that MEM was being used in a
5987 context where bits outside its mode were being referenced; that is only
5988 valid in bit-field insns. */
5990 if (tmode != BLKmode
5991 && ! (spans_byte && inner_mode != tmode)
5992 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5993 && GET_CODE (inner) != MEM
5995 || (GET_CODE (inner) == REG
5996 && have_insn_for (STRICT_LOW_PART, tmode))))
5997 || (GET_CODE (inner) == MEM && pos_rtx == 0
5999 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6000 : BITS_PER_UNIT)) == 0
6001 /* We can't do this if we are widening INNER_MODE (it
6002 may not be aligned, for one thing). */
6003 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6004 && (inner_mode == tmode
6005 || (! mode_dependent_address_p (XEXP (inner, 0))
6006 && ! MEM_VOLATILE_P (inner))))))
6008 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6009 field. If the original and current mode are the same, we need not
6010 adjust the offset. Otherwise, we do if bytes big endian.
6012 If INNER is not a MEM, get a piece consisting of just the field
6013 of interest (in this case POS % BITS_PER_WORD must be 0). */
6015 if (GET_CODE (inner) == MEM)
6017 HOST_WIDE_INT offset;
6019 /* POS counts from lsb, but make OFFSET count in memory order. */
6020 if (BYTES_BIG_ENDIAN)
6021 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6023 offset = pos / BITS_PER_UNIT;
6025 new = adjust_address_nv (inner, tmode, offset);
6027 else if (GET_CODE (inner) == REG)
6029 /* We can't call gen_lowpart_for_combine here since we always want
6030 a SUBREG and it would sometimes return a new hard register. */
6031 if (tmode != inner_mode)
6033 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6035 if (WORDS_BIG_ENDIAN
6036 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6037 final_word = ((GET_MODE_SIZE (inner_mode)
6038 - GET_MODE_SIZE (tmode))
6039 / UNITS_PER_WORD) - final_word;
6041 final_word *= UNITS_PER_WORD;
6042 if (BYTES_BIG_ENDIAN &&
6043 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6044 final_word += (GET_MODE_SIZE (inner_mode)
6045 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6047 new = gen_rtx_SUBREG (tmode, inner, final_word);
6053 new = force_to_mode (inner, tmode,
6054 len >= HOST_BITS_PER_WIDE_INT
6055 ? ~(unsigned HOST_WIDE_INT) 0
6056 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6059 /* If this extraction is going into the destination of a SET,
6060 make a STRICT_LOW_PART unless we made a MEM. */
6063 return (GET_CODE (new) == MEM ? new
6064 : (GET_CODE (new) != SUBREG
6065 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6066 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6071 if (GET_CODE (new) == CONST_INT)
6072 return gen_int_mode (INTVAL (new), mode);
6074 /* If we know that no extraneous bits are set, and that the high
6075 bit is not set, convert the extraction to the cheaper of
6076 sign and zero extension, that are equivalent in these cases. */
6077 if (flag_expensive_optimizations
6078 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6079 && ((nonzero_bits (new, tmode)
6080 & ~(((unsigned HOST_WIDE_INT)
6081 GET_MODE_MASK (tmode))
6085 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6086 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6088 /* Prefer ZERO_EXTENSION, since it gives more information to
6090 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6095 /* Otherwise, sign- or zero-extend unless we already are in the
6098 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6102 /* Unless this is a COMPARE or we have a funny memory reference,
6103 don't do anything with zero-extending field extracts starting at
6104 the low-order bit since they are simple AND operations. */
6105 if (pos_rtx == 0 && pos == 0 && ! in_dest
6106 && ! in_compare && ! spans_byte && unsignedp)
6109 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6110 we would be spanning bytes or if the position is not a constant and the
6111 length is not 1. In all other cases, we would only be going outside
6112 our object in cases when an original shift would have been
6114 if (! spans_byte && GET_CODE (inner) == MEM
6115 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6116 || (pos_rtx != 0 && len != 1)))
6119 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6120 and the mode for the result. */
6121 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6123 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6124 pos_mode = mode_for_extraction (EP_insv, 2);
6125 extraction_mode = mode_for_extraction (EP_insv, 3);
6128 if (! in_dest && unsignedp
6129 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6131 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6132 pos_mode = mode_for_extraction (EP_extzv, 3);
6133 extraction_mode = mode_for_extraction (EP_extzv, 0);
6136 if (! in_dest && ! unsignedp
6137 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6139 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6140 pos_mode = mode_for_extraction (EP_extv, 3);
6141 extraction_mode = mode_for_extraction (EP_extv, 0);
6144 /* Never narrow an object, since that might not be safe. */
6146 if (mode != VOIDmode
6147 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6148 extraction_mode = mode;
6150 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6151 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6152 pos_mode = GET_MODE (pos_rtx);
6154 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6155 if we have to change the mode of memory and cannot, the desired mode is
6157 if (GET_CODE (inner) != MEM)
6158 wanted_inner_mode = wanted_inner_reg_mode;
6159 else if (inner_mode != wanted_inner_mode
6160 && (mode_dependent_address_p (XEXP (inner, 0))
6161 || MEM_VOLATILE_P (inner)))
6162 wanted_inner_mode = extraction_mode;
6166 if (BITS_BIG_ENDIAN)
6168 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6169 BITS_BIG_ENDIAN style. If position is constant, compute new
6170 position. Otherwise, build subtraction.
6171 Note that POS is relative to the mode of the original argument.
6172 If it's a MEM we need to recompute POS relative to that.
6173 However, if we're extracting from (or inserting into) a register,
6174 we want to recompute POS relative to wanted_inner_mode. */
6175 int width = (GET_CODE (inner) == MEM
6176 ? GET_MODE_BITSIZE (is_mode)
6177 : GET_MODE_BITSIZE (wanted_inner_mode));
6180 pos = width - len - pos;
6183 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6184 /* POS may be less than 0 now, but we check for that below.
6185 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6188 /* If INNER has a wider mode, make it smaller. If this is a constant
6189 extract, try to adjust the byte to point to the byte containing
6191 if (wanted_inner_mode != VOIDmode
6192 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6193 && ((GET_CODE (inner) == MEM
6194 && (inner_mode == wanted_inner_mode
6195 || (! mode_dependent_address_p (XEXP (inner, 0))
6196 && ! MEM_VOLATILE_P (inner))))))
6200 /* The computations below will be correct if the machine is big
6201 endian in both bits and bytes or little endian in bits and bytes.
6202 If it is mixed, we must adjust. */
6204 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6205 adjust OFFSET to compensate. */
6206 if (BYTES_BIG_ENDIAN
6208 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6209 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6211 /* If this is a constant position, we can move to the desired byte. */
6214 offset += pos / BITS_PER_UNIT;
6215 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6218 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6220 && is_mode != wanted_inner_mode)
6221 offset = (GET_MODE_SIZE (is_mode)
6222 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6224 if (offset != 0 || inner_mode != wanted_inner_mode)
6225 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6228 /* If INNER is not memory, we can always get it into the proper mode. If we
6229 are changing its mode, POS must be a constant and smaller than the size
6231 else if (GET_CODE (inner) != MEM)
6233 if (GET_MODE (inner) != wanted_inner_mode
6235 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6238 inner = force_to_mode (inner, wanted_inner_mode,
6240 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6241 ? ~(unsigned HOST_WIDE_INT) 0
6242 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6247 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6248 have to zero extend. Otherwise, we can just use a SUBREG. */
6250 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6252 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6254 /* If we know that no extraneous bits are set, and that the high
6255 bit is not set, convert extraction to cheaper one - either
6256 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6258 if (flag_expensive_optimizations
6259 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6260 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6261 & ~(((unsigned HOST_WIDE_INT)
6262 GET_MODE_MASK (GET_MODE (pos_rtx)))
6266 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6268 /* Prefer ZERO_EXTENSION, since it gives more information to
6270 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6275 else if (pos_rtx != 0
6276 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6277 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6279 /* Make POS_RTX unless we already have it and it is correct. If we don't
6280 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6282 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6283 pos_rtx = orig_pos_rtx;
6285 else if (pos_rtx == 0)
6286 pos_rtx = GEN_INT (pos);
6288 /* Make the required operation. See if we can use existing rtx. */
6289 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6290 extraction_mode, inner, GEN_INT (len), pos_rtx);
6292 new = gen_lowpart_for_combine (mode, new);
6297 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6298 with any other operations in X. Return X without that shift if so. */
6301 extract_left_shift (x, count)
6305 enum rtx_code code = GET_CODE (x);
6306 enum machine_mode mode = GET_MODE (x);
6312 /* This is the shift itself. If it is wide enough, we will return
6313 either the value being shifted if the shift count is equal to
6314 COUNT or a shift for the difference. */
6315 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6316 && INTVAL (XEXP (x, 1)) >= count)
6317 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6318 INTVAL (XEXP (x, 1)) - count);
6322 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6323 return simplify_gen_unary (code, mode, tem, mode);
6327 case PLUS: case IOR: case XOR: case AND:
6328 /* If we can safely shift this constant and we find the inner shift,
6329 make a new operation. */
6330 if (GET_CODE (XEXP (x,1)) == CONST_INT
6331 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6332 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6333 return gen_binary (code, mode, tem,
6334 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6345 /* Look at the expression rooted at X. Look for expressions
6346 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6347 Form these expressions.
6349 Return the new rtx, usually just X.
6351 Also, for machines like the VAX that don't have logical shift insns,
6352 try to convert logical to arithmetic shift operations in cases where
6353 they are equivalent. This undoes the canonicalizations to logical
6354 shifts done elsewhere.
6356 We try, as much as possible, to re-use rtl expressions to save memory.
6358 IN_CODE says what kind of expression we are processing. Normally, it is
6359 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6360 being kludges), it is MEM. When processing the arguments of a comparison
6361 or a COMPARE against zero, it is COMPARE. */
6364 make_compound_operation (x, in_code)
6366 enum rtx_code in_code;
6368 enum rtx_code code = GET_CODE (x);
6369 enum machine_mode mode = GET_MODE (x);
6370 int mode_width = GET_MODE_BITSIZE (mode);
6372 enum rtx_code next_code;
6378 /* Select the code to be used in recursive calls. Once we are inside an
6379 address, we stay there. If we have a comparison, set to COMPARE,
6380 but once inside, go back to our default of SET. */
6382 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6383 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6384 && XEXP (x, 1) == const0_rtx) ? COMPARE
6385 : in_code == COMPARE ? SET : in_code);
6387 /* Process depending on the code of this operation. If NEW is set
6388 non-zero, it will be returned. */
6393 /* Convert shifts by constants into multiplications if inside
6395 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6396 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6397 && INTVAL (XEXP (x, 1)) >= 0)
6399 new = make_compound_operation (XEXP (x, 0), next_code);
6400 new = gen_rtx_MULT (mode, new,
6401 GEN_INT ((HOST_WIDE_INT) 1
6402 << INTVAL (XEXP (x, 1))));
6407 /* If the second operand is not a constant, we can't do anything
6409 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6412 /* If the constant is a power of two minus one and the first operand
6413 is a logical right shift, make an extraction. */
6414 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6415 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6417 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6418 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6419 0, in_code == COMPARE);
6422 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6423 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6424 && subreg_lowpart_p (XEXP (x, 0))
6425 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6426 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6428 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6430 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6431 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6432 0, in_code == COMPARE);
6434 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6435 else if ((GET_CODE (XEXP (x, 0)) == XOR
6436 || GET_CODE (XEXP (x, 0)) == IOR)
6437 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6438 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6439 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6441 /* Apply the distributive law, and then try to make extractions. */
6442 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6443 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6445 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6447 new = make_compound_operation (new, in_code);
6450 /* If we are have (and (rotate X C) M) and C is larger than the number
6451 of bits in M, this is an extraction. */
6453 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6454 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6455 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6456 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6458 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6459 new = make_extraction (mode, new,
6460 (GET_MODE_BITSIZE (mode)
6461 - INTVAL (XEXP (XEXP (x, 0), 1))),
6462 NULL_RTX, i, 1, 0, in_code == COMPARE);
6465 /* On machines without logical shifts, if the operand of the AND is
6466 a logical shift and our mask turns off all the propagated sign
6467 bits, we can replace the logical shift with an arithmetic shift. */
6468 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6469 && !have_insn_for (LSHIFTRT, mode)
6470 && have_insn_for (ASHIFTRT, mode)
6471 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6472 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6473 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6474 && mode_width <= HOST_BITS_PER_WIDE_INT)
6476 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6478 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6479 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6481 gen_rtx_ASHIFTRT (mode,
6482 make_compound_operation
6483 (XEXP (XEXP (x, 0), 0), next_code),
6484 XEXP (XEXP (x, 0), 1)));
6487 /* If the constant is one less than a power of two, this might be
6488 representable by an extraction even if no shift is present.
6489 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6490 we are in a COMPARE. */
6491 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6492 new = make_extraction (mode,
6493 make_compound_operation (XEXP (x, 0),
6495 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6497 /* If we are in a comparison and this is an AND with a power of two,
6498 convert this into the appropriate bit extract. */
6499 else if (in_code == COMPARE
6500 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6501 new = make_extraction (mode,
6502 make_compound_operation (XEXP (x, 0),
6504 i, NULL_RTX, 1, 1, 0, 1);
6509 /* If the sign bit is known to be zero, replace this with an
6510 arithmetic shift. */
6511 if (have_insn_for (ASHIFTRT, mode)
6512 && ! have_insn_for (LSHIFTRT, mode)
6513 && mode_width <= HOST_BITS_PER_WIDE_INT
6514 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6516 new = gen_rtx_ASHIFTRT (mode,
6517 make_compound_operation (XEXP (x, 0),
6523 /* ... fall through ... */
6529 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6530 this is a SIGN_EXTRACT. */
6531 if (GET_CODE (rhs) == CONST_INT
6532 && GET_CODE (lhs) == ASHIFT
6533 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6534 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6536 new = make_compound_operation (XEXP (lhs, 0), next_code);
6537 new = make_extraction (mode, new,
6538 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6539 NULL_RTX, mode_width - INTVAL (rhs),
6540 code == LSHIFTRT, 0, in_code == COMPARE);
6544 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6545 If so, try to merge the shifts into a SIGN_EXTEND. We could
6546 also do this for some cases of SIGN_EXTRACT, but it doesn't
6547 seem worth the effort; the case checked for occurs on Alpha. */
6549 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6550 && ! (GET_CODE (lhs) == SUBREG
6551 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6552 && GET_CODE (rhs) == CONST_INT
6553 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6554 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6555 new = make_extraction (mode, make_compound_operation (new, next_code),
6556 0, NULL_RTX, mode_width - INTVAL (rhs),
6557 code == LSHIFTRT, 0, in_code == COMPARE);
6562 /* Call ourselves recursively on the inner expression. If we are
6563 narrowing the object and it has a different RTL code from
6564 what it originally did, do this SUBREG as a force_to_mode. */
6566 tem = make_compound_operation (SUBREG_REG (x), in_code);
6567 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6568 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6569 && subreg_lowpart_p (x))
6571 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6574 /* If we have something other than a SUBREG, we might have
6575 done an expansion, so rerun ourselves. */
6576 if (GET_CODE (newer) != SUBREG)
6577 newer = make_compound_operation (newer, in_code);
6582 /* If this is a paradoxical subreg, and the new code is a sign or
6583 zero extension, omit the subreg and widen the extension. If it
6584 is a regular subreg, we can still get rid of the subreg by not
6585 widening so much, or in fact removing the extension entirely. */
6586 if ((GET_CODE (tem) == SIGN_EXTEND
6587 || GET_CODE (tem) == ZERO_EXTEND)
6588 && subreg_lowpart_p (x))
6590 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6591 || (GET_MODE_SIZE (mode) >
6592 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6593 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6595 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6606 x = gen_lowpart_for_combine (mode, new);
6607 code = GET_CODE (x);
6610 /* Now recursively process each operand of this operation. */
6611 fmt = GET_RTX_FORMAT (code);
6612 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6615 new = make_compound_operation (XEXP (x, i), next_code);
6616 SUBST (XEXP (x, i), new);
6622 /* Given M see if it is a value that would select a field of bits
6623 within an item, but not the entire word. Return -1 if not.
6624 Otherwise, return the starting position of the field, where 0 is the
6627 *PLEN is set to the length of the field. */
6630 get_pos_from_mask (m, plen)
6631 unsigned HOST_WIDE_INT m;
6632 unsigned HOST_WIDE_INT *plen;
6634 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6635 int pos = exact_log2 (m & -m);
6641 /* Now shift off the low-order zero bits and see if we have a power of
6643 len = exact_log2 ((m >> pos) + 1);
6652 /* See if X can be simplified knowing that we will only refer to it in
6653 MODE and will only refer to those bits that are nonzero in MASK.
6654 If other bits are being computed or if masking operations are done
6655 that select a superset of the bits in MASK, they can sometimes be
6658 Return a possibly simplified expression, but always convert X to
6659 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6661 Also, if REG is non-zero and X is a register equal in value to REG,
6664 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6665 are all off in X. This is used when X will be complemented, by either
6666 NOT, NEG, or XOR. */
6669 force_to_mode (x, mode, mask, reg, just_select)
6671 enum machine_mode mode;
6672 unsigned HOST_WIDE_INT mask;
6676 enum rtx_code code = GET_CODE (x);
6677 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6678 enum machine_mode op_mode;
6679 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6682 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6683 code below will do the wrong thing since the mode of such an
6684 expression is VOIDmode.
6686 Also do nothing if X is a CLOBBER; this can happen if X was
6687 the return value from a call to gen_lowpart_for_combine. */
6688 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6691 /* We want to perform the operation is its present mode unless we know
6692 that the operation is valid in MODE, in which case we do the operation
6694 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6695 && have_insn_for (code, mode))
6696 ? mode : GET_MODE (x));
6698 /* It is not valid to do a right-shift in a narrower mode
6699 than the one it came in with. */
6700 if ((code == LSHIFTRT || code == ASHIFTRT)
6701 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6702 op_mode = GET_MODE (x);
6704 /* Truncate MASK to fit OP_MODE. */
6706 mask &= GET_MODE_MASK (op_mode);
6708 /* When we have an arithmetic operation, or a shift whose count we
6709 do not know, we need to assume that all bit the up to the highest-order
6710 bit in MASK will be needed. This is how we form such a mask. */
6712 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6713 ? GET_MODE_MASK (op_mode)
6714 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6717 fuller_mask = ~(HOST_WIDE_INT) 0;
6719 /* Determine what bits of X are guaranteed to be (non)zero. */
6720 nonzero = nonzero_bits (x, mode);
6722 /* If none of the bits in X are needed, return a zero. */
6723 if (! just_select && (nonzero & mask) == 0)
6726 /* If X is a CONST_INT, return a new one. Do this here since the
6727 test below will fail. */
6728 if (GET_CODE (x) == CONST_INT)
6729 return gen_int_mode (INTVAL (x) & mask, mode);
6731 /* If X is narrower than MODE and we want all the bits in X's mode, just
6732 get X in the proper mode. */
6733 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6734 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6735 return gen_lowpart_for_combine (mode, x);
6737 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6738 MASK are already known to be zero in X, we need not do anything. */
6739 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6745 /* If X is a (clobber (const_int)), return it since we know we are
6746 generating something that won't match. */
6750 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6751 spanned the boundary of the MEM. If we are now masking so it is
6752 within that boundary, we don't need the USE any more. */
6753 if (! BITS_BIG_ENDIAN
6754 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6755 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6762 x = expand_compound_operation (x);
6763 if (GET_CODE (x) != code)
6764 return force_to_mode (x, mode, mask, reg, next_select);
6768 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6769 || rtx_equal_p (reg, get_last_value (x))))
6774 if (subreg_lowpart_p (x)
6775 /* We can ignore the effect of this SUBREG if it narrows the mode or
6776 if the constant masks to zero all the bits the mode doesn't
6778 && ((GET_MODE_SIZE (GET_MODE (x))
6779 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6781 & GET_MODE_MASK (GET_MODE (x))
6782 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6783 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6787 /* If this is an AND with a constant, convert it into an AND
6788 whose constant is the AND of that constant with MASK. If it
6789 remains an AND of MASK, delete it since it is redundant. */
6791 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6793 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6794 mask & INTVAL (XEXP (x, 1)));
6796 /* If X is still an AND, see if it is an AND with a mask that
6797 is just some low-order bits. If so, and it is MASK, we don't
6800 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6801 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6802 == (HOST_WIDE_INT) mask))
6805 /* If it remains an AND, try making another AND with the bits
6806 in the mode mask that aren't in MASK turned on. If the
6807 constant in the AND is wide enough, this might make a
6808 cheaper constant. */
6810 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6811 && GET_MODE_MASK (GET_MODE (x)) != mask
6812 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6814 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6815 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6816 int width = GET_MODE_BITSIZE (GET_MODE (x));
6819 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6820 number, sign extend it. */
6821 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6822 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6823 cval |= (HOST_WIDE_INT) -1 << width;
6825 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6826 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6836 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6837 low-order bits (as in an alignment operation) and FOO is already
6838 aligned to that boundary, mask C1 to that boundary as well.
6839 This may eliminate that PLUS and, later, the AND. */
6842 unsigned int width = GET_MODE_BITSIZE (mode);
6843 unsigned HOST_WIDE_INT smask = mask;
6845 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6846 number, sign extend it. */
6848 if (width < HOST_BITS_PER_WIDE_INT
6849 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6850 smask |= (HOST_WIDE_INT) -1 << width;
6852 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6853 && exact_log2 (- smask) >= 0
6854 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6855 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6856 return force_to_mode (plus_constant (XEXP (x, 0),
6857 (INTVAL (XEXP (x, 1)) & smask)),
6858 mode, smask, reg, next_select);
6861 /* ... fall through ... */
6864 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6865 most significant bit in MASK since carries from those bits will
6866 affect the bits we are interested in. */
6871 /* If X is (minus C Y) where C's least set bit is larger than any bit
6872 in the mask, then we may replace with (neg Y). */
6873 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6874 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6875 & -INTVAL (XEXP (x, 0))))
6878 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6880 return force_to_mode (x, mode, mask, reg, next_select);
6883 /* Similarly, if C contains every bit in the mask, then we may
6884 replace with (not Y). */
6885 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6886 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6887 == INTVAL (XEXP (x, 0))))
6889 x = simplify_gen_unary (NOT, GET_MODE (x),
6890 XEXP (x, 1), GET_MODE (x));
6891 return force_to_mode (x, mode, mask, reg, next_select);
6899 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6900 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6901 operation which may be a bitfield extraction. Ensure that the
6902 constant we form is not wider than the mode of X. */
6904 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6905 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6906 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6907 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6908 && GET_CODE (XEXP (x, 1)) == CONST_INT
6909 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6910 + floor_log2 (INTVAL (XEXP (x, 1))))
6911 < GET_MODE_BITSIZE (GET_MODE (x)))
6912 && (INTVAL (XEXP (x, 1))
6913 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6915 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6916 << INTVAL (XEXP (XEXP (x, 0), 1)));
6917 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6918 XEXP (XEXP (x, 0), 0), temp);
6919 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6920 XEXP (XEXP (x, 0), 1));
6921 return force_to_mode (x, mode, mask, reg, next_select);
6925 /* For most binary operations, just propagate into the operation and
6926 change the mode if we have an operation of that mode. */
6928 op0 = gen_lowpart_for_combine (op_mode,
6929 force_to_mode (XEXP (x, 0), mode, mask,
6931 op1 = gen_lowpart_for_combine (op_mode,
6932 force_to_mode (XEXP (x, 1), mode, mask,
6935 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6936 x = gen_binary (code, op_mode, op0, op1);
6940 /* For left shifts, do the same, but just for the first operand.
6941 However, we cannot do anything with shifts where we cannot
6942 guarantee that the counts are smaller than the size of the mode
6943 because such a count will have a different meaning in a
6946 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6947 && INTVAL (XEXP (x, 1)) >= 0
6948 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6949 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6950 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6951 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6954 /* If the shift count is a constant and we can do arithmetic in
6955 the mode of the shift, refine which bits we need. Otherwise, use the
6956 conservative form of the mask. */
6957 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6958 && INTVAL (XEXP (x, 1)) >= 0
6959 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6960 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6961 mask >>= INTVAL (XEXP (x, 1));
6965 op0 = gen_lowpart_for_combine (op_mode,
6966 force_to_mode (XEXP (x, 0), op_mode,
6967 mask, reg, next_select));
6969 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6970 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6974 /* Here we can only do something if the shift count is a constant,
6975 this shift constant is valid for the host, and we can do arithmetic
6978 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6979 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6980 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6982 rtx inner = XEXP (x, 0);
6983 unsigned HOST_WIDE_INT inner_mask;
6985 /* Select the mask of the bits we need for the shift operand. */
6986 inner_mask = mask << INTVAL (XEXP (x, 1));
6988 /* We can only change the mode of the shift if we can do arithmetic
6989 in the mode of the shift and INNER_MASK is no wider than the
6990 width of OP_MODE. */
6991 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6992 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6993 op_mode = GET_MODE (x);
6995 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6997 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6998 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7001 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7002 shift and AND produces only copies of the sign bit (C2 is one less
7003 than a power of two), we can do this with just a shift. */
7005 if (GET_CODE (x) == LSHIFTRT
7006 && GET_CODE (XEXP (x, 1)) == CONST_INT
7007 /* The shift puts one of the sign bit copies in the least significant
7009 && ((INTVAL (XEXP (x, 1))
7010 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7011 >= GET_MODE_BITSIZE (GET_MODE (x)))
7012 && exact_log2 (mask + 1) >= 0
7013 /* Number of bits left after the shift must be more than the mask
7015 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7016 <= GET_MODE_BITSIZE (GET_MODE (x)))
7017 /* Must be more sign bit copies than the mask needs. */
7018 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7019 >= exact_log2 (mask + 1)))
7020 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7021 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7022 - exact_log2 (mask + 1)));
7027 /* If we are just looking for the sign bit, we don't need this shift at
7028 all, even if it has a variable count. */
7029 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7030 && (mask == ((unsigned HOST_WIDE_INT) 1
7031 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7032 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7034 /* If this is a shift by a constant, get a mask that contains those bits
7035 that are not copies of the sign bit. We then have two cases: If
7036 MASK only includes those bits, this can be a logical shift, which may
7037 allow simplifications. If MASK is a single-bit field not within
7038 those bits, we are requesting a copy of the sign bit and hence can
7039 shift the sign bit to the appropriate location. */
7041 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7042 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7046 /* If the considered data is wider than HOST_WIDE_INT, we can't
7047 represent a mask for all its bits in a single scalar.
7048 But we only care about the lower bits, so calculate these. */
7050 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7052 nonzero = ~(HOST_WIDE_INT) 0;
7054 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7055 is the number of bits a full-width mask would have set.
7056 We need only shift if these are fewer than nonzero can
7057 hold. If not, we must keep all bits set in nonzero. */
7059 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7060 < HOST_BITS_PER_WIDE_INT)
7061 nonzero >>= INTVAL (XEXP (x, 1))
7062 + HOST_BITS_PER_WIDE_INT
7063 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7067 nonzero = GET_MODE_MASK (GET_MODE (x));
7068 nonzero >>= INTVAL (XEXP (x, 1));
7071 if ((mask & ~nonzero) == 0
7072 || (i = exact_log2 (mask)) >= 0)
7074 x = simplify_shift_const
7075 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7076 i < 0 ? INTVAL (XEXP (x, 1))
7077 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7079 if (GET_CODE (x) != ASHIFTRT)
7080 return force_to_mode (x, mode, mask, reg, next_select);
7084 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7085 even if the shift count isn't a constant. */
7087 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7091 /* If this is a zero- or sign-extension operation that just affects bits
7092 we don't care about, remove it. Be sure the call above returned
7093 something that is still a shift. */
7095 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7096 && GET_CODE (XEXP (x, 1)) == CONST_INT
7097 && INTVAL (XEXP (x, 1)) >= 0
7098 && (INTVAL (XEXP (x, 1))
7099 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7100 && GET_CODE (XEXP (x, 0)) == ASHIFT
7101 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7102 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7103 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7110 /* If the shift count is constant and we can do computations
7111 in the mode of X, compute where the bits we care about are.
7112 Otherwise, we can't do anything. Don't change the mode of
7113 the shift or propagate MODE into the shift, though. */
7114 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7115 && INTVAL (XEXP (x, 1)) >= 0)
7117 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7118 GET_MODE (x), GEN_INT (mask),
7120 if (temp && GET_CODE(temp) == CONST_INT)
7122 force_to_mode (XEXP (x, 0), GET_MODE (x),
7123 INTVAL (temp), reg, next_select));
7128 /* If we just want the low-order bit, the NEG isn't needed since it
7129 won't change the low-order bit. */
7131 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7133 /* We need any bits less significant than the most significant bit in
7134 MASK since carries from those bits will affect the bits we are
7140 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7141 same as the XOR case above. Ensure that the constant we form is not
7142 wider than the mode of X. */
7144 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7145 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7146 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7147 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7148 < GET_MODE_BITSIZE (GET_MODE (x)))
7149 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7151 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7152 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7153 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7155 return force_to_mode (x, mode, mask, reg, next_select);
7158 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7159 use the full mask inside the NOT. */
7163 op0 = gen_lowpart_for_combine (op_mode,
7164 force_to_mode (XEXP (x, 0), mode, mask,
7166 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7167 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7171 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7172 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7173 which is equal to STORE_FLAG_VALUE. */
7174 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7175 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7176 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7177 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7182 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7183 written in a narrower mode. We play it safe and do not do so. */
7186 gen_lowpart_for_combine (GET_MODE (x),
7187 force_to_mode (XEXP (x, 1), mode,
7188 mask, reg, next_select)));
7190 gen_lowpart_for_combine (GET_MODE (x),
7191 force_to_mode (XEXP (x, 2), mode,
7192 mask, reg,next_select)));
7199 /* Ensure we return a value of the proper mode. */
7200 return gen_lowpart_for_combine (mode, x);
7203 /* Return nonzero if X is an expression that has one of two values depending on
7204 whether some other value is zero or nonzero. In that case, we return the
7205 value that is being tested, *PTRUE is set to the value if the rtx being
7206 returned has a nonzero value, and *PFALSE is set to the other alternative.
7208 If we return zero, we set *PTRUE and *PFALSE to X. */
7211 if_then_else_cond (x, ptrue, pfalse)
7213 rtx *ptrue, *pfalse;
7215 enum machine_mode mode = GET_MODE (x);
7216 enum rtx_code code = GET_CODE (x);
7217 rtx cond0, cond1, true0, true1, false0, false1;
7218 unsigned HOST_WIDE_INT nz;
7220 /* If we are comparing a value against zero, we are done. */
7221 if ((code == NE || code == EQ)
7222 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7224 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7225 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7229 /* If this is a unary operation whose operand has one of two values, apply
7230 our opcode to compute those values. */
7231 else if (GET_RTX_CLASS (code) == '1'
7232 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7234 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7235 *pfalse = simplify_gen_unary (code, mode, false0,
7236 GET_MODE (XEXP (x, 0)));
7240 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7241 make can't possibly match and would suppress other optimizations. */
7242 else if (code == COMPARE)
7245 /* If this is a binary operation, see if either side has only one of two
7246 values. If either one does or if both do and they are conditional on
7247 the same value, compute the new true and false values. */
7248 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7249 || GET_RTX_CLASS (code) == '<')
7251 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7252 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7254 if ((cond0 != 0 || cond1 != 0)
7255 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7257 /* If if_then_else_cond returned zero, then true/false are the
7258 same rtl. We must copy one of them to prevent invalid rtl
7261 true0 = copy_rtx (true0);
7262 else if (cond1 == 0)
7263 true1 = copy_rtx (true1);
7265 *ptrue = gen_binary (code, mode, true0, true1);
7266 *pfalse = gen_binary (code, mode, false0, false1);
7267 return cond0 ? cond0 : cond1;
7270 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7271 operands is zero when the other is non-zero, and vice-versa,
7272 and STORE_FLAG_VALUE is 1 or -1. */
7274 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7275 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7277 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7279 rtx op0 = XEXP (XEXP (x, 0), 1);
7280 rtx op1 = XEXP (XEXP (x, 1), 1);
7282 cond0 = XEXP (XEXP (x, 0), 0);
7283 cond1 = XEXP (XEXP (x, 1), 0);
7285 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7286 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7287 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7288 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7289 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7290 || ((swap_condition (GET_CODE (cond0))
7291 == combine_reversed_comparison_code (cond1))
7292 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7293 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7294 && ! side_effects_p (x))
7296 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7297 *pfalse = gen_binary (MULT, mode,
7299 ? simplify_gen_unary (NEG, mode, op1,
7307 /* Similarly for MULT, AND and UMIN, except that for these the result
7309 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7310 && (code == MULT || code == AND || code == UMIN)
7311 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7313 cond0 = XEXP (XEXP (x, 0), 0);
7314 cond1 = XEXP (XEXP (x, 1), 0);
7316 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7317 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7318 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7319 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7320 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7321 || ((swap_condition (GET_CODE (cond0))
7322 == combine_reversed_comparison_code (cond1))
7323 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7324 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7325 && ! side_effects_p (x))
7327 *ptrue = *pfalse = const0_rtx;
7333 else if (code == IF_THEN_ELSE)
7335 /* If we have IF_THEN_ELSE already, extract the condition and
7336 canonicalize it if it is NE or EQ. */
7337 cond0 = XEXP (x, 0);
7338 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7339 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7340 return XEXP (cond0, 0);
7341 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7343 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7344 return XEXP (cond0, 0);
7350 /* If X is a SUBREG, we can narrow both the true and false values
7351 if the inner expression, if there is a condition. */
7352 else if (code == SUBREG
7353 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7356 *ptrue = simplify_gen_subreg (mode, true0,
7357 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7358 *pfalse = simplify_gen_subreg (mode, false0,
7359 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7364 /* If X is a constant, this isn't special and will cause confusions
7365 if we treat it as such. Likewise if it is equivalent to a constant. */
7366 else if (CONSTANT_P (x)
7367 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7370 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7371 will be least confusing to the rest of the compiler. */
7372 else if (mode == BImode)
7374 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7378 /* If X is known to be either 0 or -1, those are the true and
7379 false values when testing X. */
7380 else if (x == constm1_rtx || x == const0_rtx
7381 || (mode != VOIDmode
7382 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7384 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7388 /* Likewise for 0 or a single bit. */
7389 else if (mode != VOIDmode
7390 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7391 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7393 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7397 /* Otherwise fail; show no condition with true and false values the same. */
7398 *ptrue = *pfalse = x;
7402 /* Return the value of expression X given the fact that condition COND
7403 is known to be true when applied to REG as its first operand and VAL
7404 as its second. X is known to not be shared and so can be modified in
7407 We only handle the simplest cases, and specifically those cases that
7408 arise with IF_THEN_ELSE expressions. */
7411 known_cond (x, cond, reg, val)
7416 enum rtx_code code = GET_CODE (x);
7421 if (side_effects_p (x))
7424 /* If either operand of the condition is a floating point value,
7425 then we have to avoid collapsing an EQ comparison. */
7427 && rtx_equal_p (x, reg)
7428 && ! FLOAT_MODE_P (GET_MODE (x))
7429 && ! FLOAT_MODE_P (GET_MODE (val)))
7432 if (cond == UNEQ && rtx_equal_p (x, reg))
7435 /* If X is (abs REG) and we know something about REG's relationship
7436 with zero, we may be able to simplify this. */
7438 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7441 case GE: case GT: case EQ:
7444 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7446 GET_MODE (XEXP (x, 0)));
7451 /* The only other cases we handle are MIN, MAX, and comparisons if the
7452 operands are the same as REG and VAL. */
7454 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7456 if (rtx_equal_p (XEXP (x, 0), val))
7457 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7459 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7461 if (GET_RTX_CLASS (code) == '<')
7463 if (comparison_dominates_p (cond, code))
7464 return const_true_rtx;
7466 code = combine_reversed_comparison_code (x);
7468 && comparison_dominates_p (cond, code))
7473 else if (code == SMAX || code == SMIN
7474 || code == UMIN || code == UMAX)
7476 int unsignedp = (code == UMIN || code == UMAX);
7478 /* Do not reverse the condition when it is NE or EQ.
7479 This is because we cannot conclude anything about
7480 the value of 'SMAX (x, y)' when x is not equal to y,
7481 but we can when x equals y. */
7482 if ((code == SMAX || code == UMAX)
7483 && ! (cond == EQ || cond == NE))
7484 cond = reverse_condition (cond);
7489 return unsignedp ? x : XEXP (x, 1);
7491 return unsignedp ? x : XEXP (x, 0);
7493 return unsignedp ? XEXP (x, 1) : x;
7495 return unsignedp ? XEXP (x, 0) : x;
7502 else if (code == SUBREG)
7504 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7505 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7507 if (SUBREG_REG (x) != r)
7509 /* We must simplify subreg here, before we lose track of the
7510 original inner_mode. */
7511 new = simplify_subreg (GET_MODE (x), r,
7512 inner_mode, SUBREG_BYTE (x));
7516 SUBST (SUBREG_REG (x), r);
7521 /* We don't have to handle SIGN_EXTEND here, because even in the
7522 case of replacing something with a modeless CONST_INT, a
7523 CONST_INT is already (supposed to be) a valid sign extension for
7524 its narrower mode, which implies it's already properly
7525 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7526 story is different. */
7527 else if (code == ZERO_EXTEND)
7529 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7530 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7532 if (XEXP (x, 0) != r)
7534 /* We must simplify the zero_extend here, before we lose
7535 track of the original inner_mode. */
7536 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7541 SUBST (XEXP (x, 0), r);
7547 fmt = GET_RTX_FORMAT (code);
7548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7551 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7552 else if (fmt[i] == 'E')
7553 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7554 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7561 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7562 assignment as a field assignment. */
7565 rtx_equal_for_field_assignment_p (x, y)
7569 if (x == y || rtx_equal_p (x, y))
7572 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7575 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7576 Note that all SUBREGs of MEM are paradoxical; otherwise they
7577 would have been rewritten. */
7578 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7579 && GET_CODE (SUBREG_REG (y)) == MEM
7580 && rtx_equal_p (SUBREG_REG (y),
7581 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7584 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7585 && GET_CODE (SUBREG_REG (x)) == MEM
7586 && rtx_equal_p (SUBREG_REG (x),
7587 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7590 /* We used to see if get_last_value of X and Y were the same but that's
7591 not correct. In one direction, we'll cause the assignment to have
7592 the wrong destination and in the case, we'll import a register into this
7593 insn that might have already have been dead. So fail if none of the
7594 above cases are true. */
7598 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7599 Return that assignment if so.
7601 We only handle the most common cases. */
7604 make_field_assignment (x)
7607 rtx dest = SET_DEST (x);
7608 rtx src = SET_SRC (x);
7613 unsigned HOST_WIDE_INT len;
7615 enum machine_mode mode;
7617 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7618 a clear of a one-bit field. We will have changed it to
7619 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7622 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7623 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7624 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7625 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7627 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7630 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7634 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7635 && subreg_lowpart_p (XEXP (src, 0))
7636 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7637 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7638 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7639 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7640 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7642 assign = make_extraction (VOIDmode, dest, 0,
7643 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7646 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7650 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7652 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7653 && XEXP (XEXP (src, 0), 0) == const1_rtx
7654 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7656 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7659 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7663 /* The other case we handle is assignments into a constant-position
7664 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7665 a mask that has all one bits except for a group of zero bits and
7666 OTHER is known to have zeros where C1 has ones, this is such an
7667 assignment. Compute the position and length from C1. Shift OTHER
7668 to the appropriate position, force it to the required mode, and
7669 make the extraction. Check for the AND in both operands. */
7671 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7674 rhs = expand_compound_operation (XEXP (src, 0));
7675 lhs = expand_compound_operation (XEXP (src, 1));
7677 if (GET_CODE (rhs) == AND
7678 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7679 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7680 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7681 else if (GET_CODE (lhs) == AND
7682 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7683 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7684 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7688 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7689 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7690 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7691 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7694 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7698 /* The mode to use for the source is the mode of the assignment, or of
7699 what is inside a possible STRICT_LOW_PART. */
7700 mode = (GET_CODE (assign) == STRICT_LOW_PART
7701 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7703 /* Shift OTHER right POS places and make it the source, restricting it
7704 to the proper length and mode. */
7706 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7707 GET_MODE (src), other, pos),
7709 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7710 ? ~(unsigned HOST_WIDE_INT) 0
7711 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7714 return gen_rtx_SET (VOIDmode, assign, src);
7717 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7721 apply_distributive_law (x)
7724 enum rtx_code code = GET_CODE (x);
7725 rtx lhs, rhs, other;
7727 enum rtx_code inner_code;
7729 /* Distributivity is not true for floating point.
7730 It can change the value. So don't do it.
7731 -- rms and moshier@world.std.com. */
7732 if (FLOAT_MODE_P (GET_MODE (x)))
7735 /* The outer operation can only be one of the following: */
7736 if (code != IOR && code != AND && code != XOR
7737 && code != PLUS && code != MINUS)
7740 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7742 /* If either operand is a primitive we can't do anything, so get out
7744 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7745 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7748 lhs = expand_compound_operation (lhs);
7749 rhs = expand_compound_operation (rhs);
7750 inner_code = GET_CODE (lhs);
7751 if (inner_code != GET_CODE (rhs))
7754 /* See if the inner and outer operations distribute. */
7761 /* These all distribute except over PLUS. */
7762 if (code == PLUS || code == MINUS)
7767 if (code != PLUS && code != MINUS)
7772 /* This is also a multiply, so it distributes over everything. */
7776 /* Non-paradoxical SUBREGs distributes over all operations, provided
7777 the inner modes and byte offsets are the same, this is an extraction
7778 of a low-order part, we don't convert an fp operation to int or
7779 vice versa, and we would not be converting a single-word
7780 operation into a multi-word operation. The latter test is not
7781 required, but it prevents generating unneeded multi-word operations.
7782 Some of the previous tests are redundant given the latter test, but
7783 are retained because they are required for correctness.
7785 We produce the result slightly differently in this case. */
7787 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7788 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7789 || ! subreg_lowpart_p (lhs)
7790 || (GET_MODE_CLASS (GET_MODE (lhs))
7791 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7792 || (GET_MODE_SIZE (GET_MODE (lhs))
7793 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7794 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7797 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7798 SUBREG_REG (lhs), SUBREG_REG (rhs));
7799 return gen_lowpart_for_combine (GET_MODE (x), tem);
7805 /* Set LHS and RHS to the inner operands (A and B in the example
7806 above) and set OTHER to the common operand (C in the example).
7807 These is only one way to do this unless the inner operation is
7809 if (GET_RTX_CLASS (inner_code) == 'c'
7810 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7811 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7812 else if (GET_RTX_CLASS (inner_code) == 'c'
7813 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7814 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7815 else if (GET_RTX_CLASS (inner_code) == 'c'
7816 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7817 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7818 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7819 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7823 /* Form the new inner operation, seeing if it simplifies first. */
7824 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7826 /* There is one exception to the general way of distributing:
7827 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7828 if (code == XOR && inner_code == IOR)
7831 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7834 /* We may be able to continuing distributing the result, so call
7835 ourselves recursively on the inner operation before forming the
7836 outer operation, which we return. */
7837 return gen_binary (inner_code, GET_MODE (x),
7838 apply_distributive_law (tem), other);
7841 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7844 Return an equivalent form, if different from X. Otherwise, return X. If
7845 X is zero, we are to always construct the equivalent form. */
7848 simplify_and_const_int (x, mode, varop, constop)
7850 enum machine_mode mode;
7852 unsigned HOST_WIDE_INT constop;
7854 unsigned HOST_WIDE_INT nonzero;
7857 /* Simplify VAROP knowing that we will be only looking at some of the
7860 Note by passing in CONSTOP, we guarantee that the bits not set in
7861 CONSTOP are not significant and will never be examined. We must
7862 ensure that is the case by explicitly masking out those bits
7863 before returning. */
7864 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7866 /* If VAROP is a CLOBBER, we will fail so return it. */
7867 if (GET_CODE (varop) == CLOBBER)
7870 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7871 to VAROP and return the new constant. */
7872 if (GET_CODE (varop) == CONST_INT)
7873 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7875 /* See what bits may be nonzero in VAROP. Unlike the general case of
7876 a call to nonzero_bits, here we don't care about bits outside
7879 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7881 /* Turn off all bits in the constant that are known to already be zero.
7882 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7883 which is tested below. */
7887 /* If we don't have any bits left, return zero. */
7891 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7892 a power of two, we can replace this with an ASHIFT. */
7893 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7894 && (i = exact_log2 (constop)) >= 0)
7895 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7897 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7898 or XOR, then try to apply the distributive law. This may eliminate
7899 operations if either branch can be simplified because of the AND.
7900 It may also make some cases more complex, but those cases probably
7901 won't match a pattern either with or without this. */
7903 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7905 gen_lowpart_for_combine
7907 apply_distributive_law
7908 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7909 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7910 XEXP (varop, 0), constop),
7911 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7912 XEXP (varop, 1), constop))));
7914 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7915 the AND and see if one of the operands simplifies to zero. If so, we
7916 may eliminate it. */
7918 if (GET_CODE (varop) == PLUS
7919 && exact_log2 (constop + 1) >= 0)
7923 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7924 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7925 if (o0 == const0_rtx)
7927 if (o1 == const0_rtx)
7931 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7932 if we already had one (just check for the simplest cases). */
7933 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7934 && GET_MODE (XEXP (x, 0)) == mode
7935 && SUBREG_REG (XEXP (x, 0)) == varop)
7936 varop = XEXP (x, 0);
7938 varop = gen_lowpart_for_combine (mode, varop);
7940 /* If we can't make the SUBREG, try to return what we were given. */
7941 if (GET_CODE (varop) == CLOBBER)
7942 return x ? x : varop;
7944 /* If we are only masking insignificant bits, return VAROP. */
7945 if (constop == nonzero)
7949 /* Otherwise, return an AND. */
7950 constop = trunc_int_for_mode (constop, mode);
7951 /* See how much, if any, of X we can use. */
7952 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7953 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7957 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7958 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7959 SUBST (XEXP (x, 1), GEN_INT (constop));
7961 SUBST (XEXP (x, 0), varop);
7968 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7969 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7970 is less useful. We can't allow both, because that results in exponential
7971 run time recursion. There is a nullstone testcase that triggered
7972 this. This macro avoids accidental uses of num_sign_bit_copies. */
7973 #define num_sign_bit_copies()
7975 /* Given an expression, X, compute which bits in X can be non-zero.
7976 We don't care about bits outside of those defined in MODE.
7978 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7979 a shift, AND, or zero_extract, we can do better. */
7981 static unsigned HOST_WIDE_INT
7982 nonzero_bits (x, mode)
7984 enum machine_mode mode;
7986 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7987 unsigned HOST_WIDE_INT inner_nz;
7989 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7992 /* For floating-point values, assume all bits are needed. */
7993 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7996 /* If X is wider than MODE, use its mode instead. */
7997 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7999 mode = GET_MODE (x);
8000 nonzero = GET_MODE_MASK (mode);
8001 mode_width = GET_MODE_BITSIZE (mode);
8004 if (mode_width > HOST_BITS_PER_WIDE_INT)
8005 /* Our only callers in this case look for single bit values. So
8006 just return the mode mask. Those tests will then be false. */
8009 #ifndef WORD_REGISTER_OPERATIONS
8010 /* If MODE is wider than X, but both are a single word for both the host
8011 and target machines, we can compute this from which bits of the
8012 object might be nonzero in its own mode, taking into account the fact
8013 that on many CISC machines, accessing an object in a wider mode
8014 causes the high-order bits to become undefined. So they are
8015 not known to be zero. */
8017 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8018 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8019 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8020 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8022 nonzero &= nonzero_bits (x, GET_MODE (x));
8023 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8028 code = GET_CODE (x);
8032 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8033 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8034 all the bits above ptr_mode are known to be zero. */
8035 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8037 nonzero &= GET_MODE_MASK (ptr_mode);
8040 /* Include declared information about alignment of pointers. */
8041 /* ??? We don't properly preserve REG_POINTER changes across
8042 pointer-to-integer casts, so we can't trust it except for
8043 things that we know must be pointers. See execute/960116-1.c. */
8044 if ((x == stack_pointer_rtx
8045 || x == frame_pointer_rtx
8046 || x == arg_pointer_rtx)
8047 && REGNO_POINTER_ALIGN (REGNO (x)))
8049 unsigned HOST_WIDE_INT alignment
8050 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8052 #ifdef PUSH_ROUNDING
8053 /* If PUSH_ROUNDING is defined, it is possible for the
8054 stack to be momentarily aligned only to that amount,
8055 so we pick the least alignment. */
8056 if (x == stack_pointer_rtx && PUSH_ARGS)
8057 alignment = MIN (PUSH_ROUNDING (1), alignment);
8060 nonzero &= ~(alignment - 1);
8063 /* If X is a register whose nonzero bits value is current, use it.
8064 Otherwise, if X is a register whose value we can find, use that
8065 value. Otherwise, use the previously-computed global nonzero bits
8066 for this register. */
8068 if (reg_last_set_value[REGNO (x)] != 0
8069 && (reg_last_set_mode[REGNO (x)] == mode
8070 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8071 && GET_MODE_CLASS (mode) == MODE_INT))
8072 && (reg_last_set_label[REGNO (x)] == label_tick
8073 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8074 && REG_N_SETS (REGNO (x)) == 1
8075 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8077 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8078 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8080 tem = get_last_value (x);
8084 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8085 /* If X is narrower than MODE and TEM is a non-negative
8086 constant that would appear negative in the mode of X,
8087 sign-extend it for use in reg_nonzero_bits because some
8088 machines (maybe most) will actually do the sign-extension
8089 and this is the conservative approach.
8091 ??? For 2.5, try to tighten up the MD files in this regard
8092 instead of this kludge. */
8094 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8095 && GET_CODE (tem) == CONST_INT
8097 && 0 != (INTVAL (tem)
8098 & ((HOST_WIDE_INT) 1
8099 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8100 tem = GEN_INT (INTVAL (tem)
8101 | ((HOST_WIDE_INT) (-1)
8102 << GET_MODE_BITSIZE (GET_MODE (x))));
8104 return nonzero_bits (tem, mode) & nonzero;
8106 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8108 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8110 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8111 /* We don't know anything about the upper bits. */
8112 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8113 return nonzero & mask;
8119 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8120 /* If X is negative in MODE, sign-extend the value. */
8121 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8122 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8123 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8129 #ifdef LOAD_EXTEND_OP
8130 /* In many, if not most, RISC machines, reading a byte from memory
8131 zeros the rest of the register. Noticing that fact saves a lot
8132 of extra zero-extends. */
8133 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8134 nonzero &= GET_MODE_MASK (GET_MODE (x));
8139 case UNEQ: case LTGT:
8140 case GT: case GTU: case UNGT:
8141 case LT: case LTU: case UNLT:
8142 case GE: case GEU: case UNGE:
8143 case LE: case LEU: case UNLE:
8144 case UNORDERED: case ORDERED:
8146 /* If this produces an integer result, we know which bits are set.
8147 Code here used to clear bits outside the mode of X, but that is
8150 if (GET_MODE_CLASS (mode) == MODE_INT
8151 && mode_width <= HOST_BITS_PER_WIDE_INT)
8152 nonzero = STORE_FLAG_VALUE;
8157 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8158 and num_sign_bit_copies. */
8159 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8160 == GET_MODE_BITSIZE (GET_MODE (x)))
8164 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8165 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8170 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8171 and num_sign_bit_copies. */
8172 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8173 == GET_MODE_BITSIZE (GET_MODE (x)))
8179 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8183 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8184 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8185 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8189 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8190 Otherwise, show all the bits in the outer mode but not the inner
8192 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8193 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8195 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8197 & (((HOST_WIDE_INT) 1
8198 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8199 inner_nz |= (GET_MODE_MASK (mode)
8200 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8203 nonzero &= inner_nz;
8207 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8208 & nonzero_bits (XEXP (x, 1), mode));
8212 case UMIN: case UMAX: case SMIN: case SMAX:
8214 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8216 /* Don't call nonzero_bits for the second time if it cannot change
8218 if ((nonzero & nonzero0) != nonzero)
8219 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8223 case PLUS: case MINUS:
8225 case DIV: case UDIV:
8226 case MOD: case UMOD:
8227 /* We can apply the rules of arithmetic to compute the number of
8228 high- and low-order zero bits of these operations. We start by
8229 computing the width (position of the highest-order non-zero bit)
8230 and the number of low-order zero bits for each value. */
8232 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8233 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8234 int width0 = floor_log2 (nz0) + 1;
8235 int width1 = floor_log2 (nz1) + 1;
8236 int low0 = floor_log2 (nz0 & -nz0);
8237 int low1 = floor_log2 (nz1 & -nz1);
8238 HOST_WIDE_INT op0_maybe_minusp
8239 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8240 HOST_WIDE_INT op1_maybe_minusp
8241 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8242 unsigned int result_width = mode_width;
8248 result_width = MAX (width0, width1) + 1;
8249 result_low = MIN (low0, low1);
8252 result_low = MIN (low0, low1);
8255 result_width = width0 + width1;
8256 result_low = low0 + low1;
8261 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8262 result_width = width0;
8267 result_width = width0;
8272 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8273 result_width = MIN (width0, width1);
8274 result_low = MIN (low0, low1);
8279 result_width = MIN (width0, width1);
8280 result_low = MIN (low0, low1);
8286 if (result_width < mode_width)
8287 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8290 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8292 #ifdef POINTERS_EXTEND_UNSIGNED
8293 /* If pointers extend unsigned and this is an addition or subtraction
8294 to a pointer in Pmode, all the bits above ptr_mode are known to be
8296 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8297 && (code == PLUS || code == MINUS)
8298 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8299 nonzero &= GET_MODE_MASK (ptr_mode);
8305 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8306 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8307 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8311 /* If this is a SUBREG formed for a promoted variable that has
8312 been zero-extended, we know that at least the high-order bits
8313 are zero, though others might be too. */
8315 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8316 nonzero = (GET_MODE_MASK (GET_MODE (x))
8317 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8319 /* If the inner mode is a single word for both the host and target
8320 machines, we can compute this from which bits of the inner
8321 object might be nonzero. */
8322 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8323 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8324 <= HOST_BITS_PER_WIDE_INT))
8326 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8328 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8329 /* If this is a typical RISC machine, we only have to worry
8330 about the way loads are extended. */
8331 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8333 & (((unsigned HOST_WIDE_INT) 1
8334 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8336 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8339 /* On many CISC machines, accessing an object in a wider mode
8340 causes the high-order bits to become undefined. So they are
8341 not known to be zero. */
8342 if (GET_MODE_SIZE (GET_MODE (x))
8343 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8344 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8345 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8354 /* The nonzero bits are in two classes: any bits within MODE
8355 that aren't in GET_MODE (x) are always significant. The rest of the
8356 nonzero bits are those that are significant in the operand of
8357 the shift when shifted the appropriate number of bits. This
8358 shows that high-order bits are cleared by the right shift and
8359 low-order bits by left shifts. */
8360 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8361 && INTVAL (XEXP (x, 1)) >= 0
8362 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8364 enum machine_mode inner_mode = GET_MODE (x);
8365 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8366 int count = INTVAL (XEXP (x, 1));
8367 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8368 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8369 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8370 unsigned HOST_WIDE_INT outer = 0;
8372 if (mode_width > width)
8373 outer = (op_nonzero & nonzero & ~mode_mask);
8375 if (code == LSHIFTRT)
8377 else if (code == ASHIFTRT)
8381 /* If the sign bit may have been nonzero before the shift, we
8382 need to mark all the places it could have been copied to
8383 by the shift as possibly nonzero. */
8384 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8385 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8387 else if (code == ASHIFT)
8390 inner = ((inner << (count % width)
8391 | (inner >> (width - (count % width)))) & mode_mask);
8393 nonzero &= (outer | inner);
8398 /* This is at most the number of bits in the mode. */
8399 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8403 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8404 | nonzero_bits (XEXP (x, 2), mode));
8414 /* See the macro definition above. */
8415 #undef num_sign_bit_copies
8417 /* Return the number of bits at the high-order end of X that are known to
8418 be equal to the sign bit. X will be used in mode MODE; if MODE is
8419 VOIDmode, X will be used in its own mode. The returned value will always
8420 be between 1 and the number of bits in MODE. */
8423 num_sign_bit_copies (x, mode)
8425 enum machine_mode mode;
8427 enum rtx_code code = GET_CODE (x);
8428 unsigned int bitwidth;
8429 int num0, num1, result;
8430 unsigned HOST_WIDE_INT nonzero;
8433 /* If we weren't given a mode, use the mode of X. If the mode is still
8434 VOIDmode, we don't know anything. Likewise if one of the modes is
8437 if (mode == VOIDmode)
8438 mode = GET_MODE (x);
8440 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8443 bitwidth = GET_MODE_BITSIZE (mode);
8445 /* For a smaller object, just ignore the high bits. */
8446 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8448 num0 = num_sign_bit_copies (x, GET_MODE (x));
8450 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8453 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8455 #ifndef WORD_REGISTER_OPERATIONS
8456 /* If this machine does not do all register operations on the entire
8457 register and MODE is wider than the mode of X, we can say nothing
8458 at all about the high-order bits. */
8461 /* Likewise on machines that do, if the mode of the object is smaller
8462 than a word and loads of that size don't sign extend, we can say
8463 nothing about the high order bits. */
8464 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8465 #ifdef LOAD_EXTEND_OP
8466 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8477 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8478 /* If pointers extend signed and this is a pointer in Pmode, say that
8479 all the bits above ptr_mode are known to be sign bit copies. */
8480 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8482 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8485 if (reg_last_set_value[REGNO (x)] != 0
8486 && reg_last_set_mode[REGNO (x)] == mode
8487 && (reg_last_set_label[REGNO (x)] == label_tick
8488 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8489 && REG_N_SETS (REGNO (x)) == 1
8490 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8492 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8493 return reg_last_set_sign_bit_copies[REGNO (x)];
8495 tem = get_last_value (x);
8497 return num_sign_bit_copies (tem, mode);
8499 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8500 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8501 return reg_sign_bit_copies[REGNO (x)];
8505 #ifdef LOAD_EXTEND_OP
8506 /* Some RISC machines sign-extend all loads of smaller than a word. */
8507 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8508 return MAX (1, ((int) bitwidth
8509 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8514 /* If the constant is negative, take its 1's complement and remask.
8515 Then see how many zero bits we have. */
8516 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8517 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8518 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8519 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8521 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8524 /* If this is a SUBREG for a promoted object that is sign-extended
8525 and we are looking at it in a wider mode, we know that at least the
8526 high-order bits are known to be sign bit copies. */
8528 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8530 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8531 return MAX ((int) bitwidth
8532 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8536 /* For a smaller object, just ignore the high bits. */
8537 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8539 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8540 return MAX (1, (num0
8541 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8545 #ifdef WORD_REGISTER_OPERATIONS
8546 #ifdef LOAD_EXTEND_OP
8547 /* For paradoxical SUBREGs on machines where all register operations
8548 affect the entire register, just look inside. Note that we are
8549 passing MODE to the recursive call, so the number of sign bit copies
8550 will remain relative to that mode, not the inner mode. */
8552 /* This works only if loads sign extend. Otherwise, if we get a
8553 reload for the inner part, it may be loaded from the stack, and
8554 then we lose all sign bit copies that existed before the store
8557 if ((GET_MODE_SIZE (GET_MODE (x))
8558 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8559 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8560 return num_sign_bit_copies (SUBREG_REG (x), mode);
8566 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8567 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8571 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8572 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8575 /* For a smaller object, just ignore the high bits. */
8576 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8577 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8581 return num_sign_bit_copies (XEXP (x, 0), mode);
8583 case ROTATE: case ROTATERT:
8584 /* If we are rotating left by a number of bits less than the number
8585 of sign bit copies, we can just subtract that amount from the
8587 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8588 && INTVAL (XEXP (x, 1)) >= 0
8589 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8591 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8592 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8593 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8598 /* In general, this subtracts one sign bit copy. But if the value
8599 is known to be positive, the number of sign bit copies is the
8600 same as that of the input. Finally, if the input has just one bit
8601 that might be nonzero, all the bits are copies of the sign bit. */
8602 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8603 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8604 return num0 > 1 ? num0 - 1 : 1;
8606 nonzero = nonzero_bits (XEXP (x, 0), mode);
8611 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8616 case IOR: case AND: case XOR:
8617 case SMIN: case SMAX: case UMIN: case UMAX:
8618 /* Logical operations will preserve the number of sign-bit copies.
8619 MIN and MAX operations always return one of the operands. */
8620 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8621 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8622 return MIN (num0, num1);
8624 case PLUS: case MINUS:
8625 /* For addition and subtraction, we can have a 1-bit carry. However,
8626 if we are subtracting 1 from a positive number, there will not
8627 be such a carry. Furthermore, if the positive number is known to
8628 be 0 or 1, we know the result is either -1 or 0. */
8630 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8631 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8633 nonzero = nonzero_bits (XEXP (x, 0), mode);
8634 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8635 return (nonzero == 1 || nonzero == 0 ? bitwidth
8636 : bitwidth - floor_log2 (nonzero) - 1);
8639 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8640 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8641 result = MAX (1, MIN (num0, num1) - 1);
8643 #ifdef POINTERS_EXTEND_UNSIGNED
8644 /* If pointers extend signed and this is an addition or subtraction
8645 to a pointer in Pmode, all the bits above ptr_mode are known to be
8647 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8648 && (code == PLUS || code == MINUS)
8649 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8650 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8651 - GET_MODE_BITSIZE (ptr_mode) + 1),
8657 /* The number of bits of the product is the sum of the number of
8658 bits of both terms. However, unless one of the terms if known
8659 to be positive, we must allow for an additional bit since negating
8660 a negative number can remove one sign bit copy. */
8662 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8663 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8665 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8667 && (bitwidth > HOST_BITS_PER_WIDE_INT
8668 || (((nonzero_bits (XEXP (x, 0), mode)
8669 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8670 && ((nonzero_bits (XEXP (x, 1), mode)
8671 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8674 return MAX (1, result);
8677 /* The result must be <= the first operand. If the first operand
8678 has the high bit set, we know nothing about the number of sign
8680 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8682 else if ((nonzero_bits (XEXP (x, 0), mode)
8683 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8686 return num_sign_bit_copies (XEXP (x, 0), mode);
8689 /* The result must be <= the second operand. */
8690 return num_sign_bit_copies (XEXP (x, 1), mode);
8693 /* Similar to unsigned division, except that we have to worry about
8694 the case where the divisor is negative, in which case we have
8696 result = num_sign_bit_copies (XEXP (x, 0), mode);
8698 && (bitwidth > HOST_BITS_PER_WIDE_INT
8699 || (nonzero_bits (XEXP (x, 1), mode)
8700 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8706 result = num_sign_bit_copies (XEXP (x, 1), mode);
8708 && (bitwidth > HOST_BITS_PER_WIDE_INT
8709 || (nonzero_bits (XEXP (x, 1), mode)
8710 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8716 /* Shifts by a constant add to the number of bits equal to the
8718 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8719 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8720 && INTVAL (XEXP (x, 1)) > 0)
8721 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8726 /* Left shifts destroy copies. */
8727 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8728 || INTVAL (XEXP (x, 1)) < 0
8729 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8732 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8733 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8736 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8737 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8738 return MIN (num0, num1);
8740 case EQ: case NE: case GE: case GT: case LE: case LT:
8741 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8742 case GEU: case GTU: case LEU: case LTU:
8743 case UNORDERED: case ORDERED:
8744 /* If the constant is negative, take its 1's complement and remask.
8745 Then see how many zero bits we have. */
8746 nonzero = STORE_FLAG_VALUE;
8747 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8748 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8749 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8751 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8758 /* If we haven't been able to figure it out by one of the above rules,
8759 see if some of the high-order bits are known to be zero. If so,
8760 count those bits and return one less than that amount. If we can't
8761 safely compute the mask for this mode, always return BITWIDTH. */
8763 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8766 nonzero = nonzero_bits (x, mode);
8767 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8768 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8771 /* Return the number of "extended" bits there are in X, when interpreted
8772 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8773 unsigned quantities, this is the number of high-order zero bits.
8774 For signed quantities, this is the number of copies of the sign bit
8775 minus 1. In both case, this function returns the number of "spare"
8776 bits. For example, if two quantities for which this function returns
8777 at least 1 are added, the addition is known not to overflow.
8779 This function will always return 0 unless called during combine, which
8780 implies that it must be called from a define_split. */
8783 extended_count (x, mode, unsignedp)
8785 enum machine_mode mode;
8788 if (nonzero_sign_valid == 0)
8792 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8793 ? (GET_MODE_BITSIZE (mode) - 1
8794 - floor_log2 (nonzero_bits (x, mode)))
8796 : num_sign_bit_copies (x, mode) - 1);
8799 /* This function is called from `simplify_shift_const' to merge two
8800 outer operations. Specifically, we have already found that we need
8801 to perform operation *POP0 with constant *PCONST0 at the outermost
8802 position. We would now like to also perform OP1 with constant CONST1
8803 (with *POP0 being done last).
8805 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8806 the resulting operation. *PCOMP_P is set to 1 if we would need to
8807 complement the innermost operand, otherwise it is unchanged.
8809 MODE is the mode in which the operation will be done. No bits outside
8810 the width of this mode matter. It is assumed that the width of this mode
8811 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8813 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8814 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8815 result is simply *PCONST0.
8817 If the resulting operation cannot be expressed as one operation, we
8818 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8821 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8822 enum rtx_code *pop0;
8823 HOST_WIDE_INT *pconst0;
8825 HOST_WIDE_INT const1;
8826 enum machine_mode mode;
8829 enum rtx_code op0 = *pop0;
8830 HOST_WIDE_INT const0 = *pconst0;
8832 const0 &= GET_MODE_MASK (mode);
8833 const1 &= GET_MODE_MASK (mode);
8835 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8839 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8842 if (op1 == NIL || op0 == SET)
8845 else if (op0 == NIL)
8846 op0 = op1, const0 = const1;
8848 else if (op0 == op1)
8872 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8873 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8876 /* If the two constants aren't the same, we can't do anything. The
8877 remaining six cases can all be done. */
8878 else if (const0 != const1)
8886 /* (a & b) | b == b */
8888 else /* op1 == XOR */
8889 /* (a ^ b) | b == a | b */
8895 /* (a & b) ^ b == (~a) & b */
8896 op0 = AND, *pcomp_p = 1;
8897 else /* op1 == IOR */
8898 /* (a | b) ^ b == a & ~b */
8899 op0 = AND, *pconst0 = ~const0;
8904 /* (a | b) & b == b */
8906 else /* op1 == XOR */
8907 /* (a ^ b) & b) == (~a) & b */
8914 /* Check for NO-OP cases. */
8915 const0 &= GET_MODE_MASK (mode);
8917 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8919 else if (const0 == 0 && op0 == AND)
8921 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8925 /* ??? Slightly redundant with the above mask, but not entirely.
8926 Moving this above means we'd have to sign-extend the mode mask
8927 for the final test. */
8928 const0 = trunc_int_for_mode (const0, mode);
8936 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8937 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8938 that we started with.
8940 The shift is normally computed in the widest mode we find in VAROP, as
8941 long as it isn't a different number of words than RESULT_MODE. Exceptions
8942 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8945 simplify_shift_const (x, code, result_mode, varop, orig_count)
8948 enum machine_mode result_mode;
8952 enum rtx_code orig_code = code;
8955 enum machine_mode mode = result_mode;
8956 enum machine_mode shift_mode, tmode;
8957 unsigned int mode_words
8958 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8959 /* We form (outer_op (code varop count) (outer_const)). */
8960 enum rtx_code outer_op = NIL;
8961 HOST_WIDE_INT outer_const = 0;
8963 int complement_p = 0;
8966 /* Make sure and truncate the "natural" shift on the way in. We don't
8967 want to do this inside the loop as it makes it more difficult to
8969 #ifdef SHIFT_COUNT_TRUNCATED
8970 if (SHIFT_COUNT_TRUNCATED)
8971 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8974 /* If we were given an invalid count, don't do anything except exactly
8975 what was requested. */
8977 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8982 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8987 /* Unless one of the branches of the `if' in this loop does a `continue',
8988 we will `break' the loop after the `if'. */
8992 /* If we have an operand of (clobber (const_int 0)), just return that
8994 if (GET_CODE (varop) == CLOBBER)
8997 /* If we discovered we had to complement VAROP, leave. Making a NOT
8998 here would cause an infinite loop. */
9002 /* Convert ROTATERT to ROTATE. */
9003 if (code == ROTATERT)
9004 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
9006 /* We need to determine what mode we will do the shift in. If the
9007 shift is a right shift or a ROTATE, we must always do it in the mode
9008 it was originally done in. Otherwise, we can do it in MODE, the
9009 widest mode encountered. */
9011 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9012 ? result_mode : mode);
9014 /* Handle cases where the count is greater than the size of the mode
9015 minus 1. For ASHIFT, use the size minus one as the count (this can
9016 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9017 take the count modulo the size. For other shifts, the result is
9020 Since these shifts are being produced by the compiler by combining
9021 multiple operations, each of which are defined, we know what the
9022 result is supposed to be. */
9024 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9026 if (code == ASHIFTRT)
9027 count = GET_MODE_BITSIZE (shift_mode) - 1;
9028 else if (code == ROTATE || code == ROTATERT)
9029 count %= GET_MODE_BITSIZE (shift_mode);
9032 /* We can't simply return zero because there may be an
9040 /* An arithmetic right shift of a quantity known to be -1 or 0
9042 if (code == ASHIFTRT
9043 && (num_sign_bit_copies (varop, shift_mode)
9044 == GET_MODE_BITSIZE (shift_mode)))
9050 /* If we are doing an arithmetic right shift and discarding all but
9051 the sign bit copies, this is equivalent to doing a shift by the
9052 bitsize minus one. Convert it into that shift because it will often
9053 allow other simplifications. */
9055 if (code == ASHIFTRT
9056 && (count + num_sign_bit_copies (varop, shift_mode)
9057 >= GET_MODE_BITSIZE (shift_mode)))
9058 count = GET_MODE_BITSIZE (shift_mode) - 1;
9060 /* We simplify the tests below and elsewhere by converting
9061 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9062 `make_compound_operation' will convert it to an ASHIFTRT for
9063 those machines (such as VAX) that don't have an LSHIFTRT. */
9064 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9066 && ((nonzero_bits (varop, shift_mode)
9067 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9071 switch (GET_CODE (varop))
9077 new = expand_compound_operation (varop);
9086 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9087 minus the width of a smaller mode, we can do this with a
9088 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9089 if ((code == ASHIFTRT || code == LSHIFTRT)
9090 && ! mode_dependent_address_p (XEXP (varop, 0))
9091 && ! MEM_VOLATILE_P (varop)
9092 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9093 MODE_INT, 1)) != BLKmode)
9095 new = adjust_address_nv (varop, tmode,
9096 BYTES_BIG_ENDIAN ? 0
9097 : count / BITS_PER_UNIT);
9099 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9100 : ZERO_EXTEND, mode, new);
9107 /* Similar to the case above, except that we can only do this if
9108 the resulting mode is the same as that of the underlying
9109 MEM and adjust the address depending on the *bits* endianness
9110 because of the way that bit-field extract insns are defined. */
9111 if ((code == ASHIFTRT || code == LSHIFTRT)
9112 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9113 MODE_INT, 1)) != BLKmode
9114 && tmode == GET_MODE (XEXP (varop, 0)))
9116 if (BITS_BIG_ENDIAN)
9117 new = XEXP (varop, 0);
9120 new = copy_rtx (XEXP (varop, 0));
9121 SUBST (XEXP (new, 0),
9122 plus_constant (XEXP (new, 0),
9123 count / BITS_PER_UNIT));
9126 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9127 : ZERO_EXTEND, mode, new);
9134 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9135 the same number of words as what we've seen so far. Then store
9136 the widest mode in MODE. */
9137 if (subreg_lowpart_p (varop)
9138 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9139 > GET_MODE_SIZE (GET_MODE (varop)))
9140 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9141 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9144 varop = SUBREG_REG (varop);
9145 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9146 mode = GET_MODE (varop);
9152 /* Some machines use MULT instead of ASHIFT because MULT
9153 is cheaper. But it is still better on those machines to
9154 merge two shifts into one. */
9155 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9156 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9159 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9160 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9166 /* Similar, for when divides are cheaper. */
9167 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9168 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9171 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9172 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9178 /* If we are extracting just the sign bit of an arithmetic
9179 right shift, that shift is not needed. However, the sign
9180 bit of a wider mode may be different from what would be
9181 interpreted as the sign bit in a narrower mode, so, if
9182 the result is narrower, don't discard the shift. */
9183 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9184 && (GET_MODE_BITSIZE (result_mode)
9185 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9187 varop = XEXP (varop, 0);
9191 /* ... fall through ... */
9196 /* Here we have two nested shifts. The result is usually the
9197 AND of a new shift with a mask. We compute the result below. */
9198 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9199 && INTVAL (XEXP (varop, 1)) >= 0
9200 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9201 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9202 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9204 enum rtx_code first_code = GET_CODE (varop);
9205 unsigned int first_count = INTVAL (XEXP (varop, 1));
9206 unsigned HOST_WIDE_INT mask;
9209 /* We have one common special case. We can't do any merging if
9210 the inner code is an ASHIFTRT of a smaller mode. However, if
9211 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9212 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9213 we can convert it to
9214 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9215 This simplifies certain SIGN_EXTEND operations. */
9216 if (code == ASHIFT && first_code == ASHIFTRT
9217 && (GET_MODE_BITSIZE (result_mode)
9218 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9220 /* C3 has the low-order C1 bits zero. */
9222 mask = (GET_MODE_MASK (mode)
9223 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9225 varop = simplify_and_const_int (NULL_RTX, result_mode,
9226 XEXP (varop, 0), mask);
9227 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9229 count = first_count;
9234 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9235 than C1 high-order bits equal to the sign bit, we can convert
9236 this to either an ASHIFT or an ASHIFTRT depending on the
9239 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9241 if (code == ASHIFTRT && first_code == ASHIFT
9242 && GET_MODE (varop) == shift_mode
9243 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9246 varop = XEXP (varop, 0);
9248 signed_count = count - first_count;
9249 if (signed_count < 0)
9250 count = -signed_count, code = ASHIFT;
9252 count = signed_count;
9257 /* There are some cases we can't do. If CODE is ASHIFTRT,
9258 we can only do this if FIRST_CODE is also ASHIFTRT.
9260 We can't do the case when CODE is ROTATE and FIRST_CODE is
9263 If the mode of this shift is not the mode of the outer shift,
9264 we can't do this if either shift is a right shift or ROTATE.
9266 Finally, we can't do any of these if the mode is too wide
9267 unless the codes are the same.
9269 Handle the case where the shift codes are the same
9272 if (code == first_code)
9274 if (GET_MODE (varop) != result_mode
9275 && (code == ASHIFTRT || code == LSHIFTRT
9279 count += first_count;
9280 varop = XEXP (varop, 0);
9284 if (code == ASHIFTRT
9285 || (code == ROTATE && first_code == ASHIFTRT)
9286 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9287 || (GET_MODE (varop) != result_mode
9288 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9289 || first_code == ROTATE
9290 || code == ROTATE)))
9293 /* To compute the mask to apply after the shift, shift the
9294 nonzero bits of the inner shift the same way the
9295 outer shift will. */
9297 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9300 = simplify_binary_operation (code, result_mode, mask_rtx,
9303 /* Give up if we can't compute an outer operation to use. */
9305 || GET_CODE (mask_rtx) != CONST_INT
9306 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9308 result_mode, &complement_p))
9311 /* If the shifts are in the same direction, we add the
9312 counts. Otherwise, we subtract them. */
9313 signed_count = count;
9314 if ((code == ASHIFTRT || code == LSHIFTRT)
9315 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9316 signed_count += first_count;
9318 signed_count -= first_count;
9320 /* If COUNT is positive, the new shift is usually CODE,
9321 except for the two exceptions below, in which case it is
9322 FIRST_CODE. If the count is negative, FIRST_CODE should
9324 if (signed_count > 0
9325 && ((first_code == ROTATE && code == ASHIFT)
9326 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9327 code = first_code, count = signed_count;
9328 else if (signed_count < 0)
9329 code = first_code, count = -signed_count;
9331 count = signed_count;
9333 varop = XEXP (varop, 0);
9337 /* If we have (A << B << C) for any shift, we can convert this to
9338 (A << C << B). This wins if A is a constant. Only try this if
9339 B is not a constant. */
9341 else if (GET_CODE (varop) == code
9342 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9344 = simplify_binary_operation (code, mode,
9348 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9355 /* Make this fit the case below. */
9356 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9357 GEN_INT (GET_MODE_MASK (mode)));
9363 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9364 with C the size of VAROP - 1 and the shift is logical if
9365 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9366 we have an (le X 0) operation. If we have an arithmetic shift
9367 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9368 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9370 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9371 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9372 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9373 && (code == LSHIFTRT || code == ASHIFTRT)
9374 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9375 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9378 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9381 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9382 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9387 /* If we have (shift (logical)), move the logical to the outside
9388 to allow it to possibly combine with another logical and the
9389 shift to combine with another shift. This also canonicalizes to
9390 what a ZERO_EXTRACT looks like. Also, some machines have
9391 (and (shift)) insns. */
9393 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9394 && (new = simplify_binary_operation (code, result_mode,
9396 GEN_INT (count))) != 0
9397 && GET_CODE (new) == CONST_INT
9398 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9399 INTVAL (new), result_mode, &complement_p))
9401 varop = XEXP (varop, 0);
9405 /* If we can't do that, try to simplify the shift in each arm of the
9406 logical expression, make a new logical expression, and apply
9407 the inverse distributive law. */
9409 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9410 XEXP (varop, 0), count);
9411 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9412 XEXP (varop, 1), count);
9414 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9415 varop = apply_distributive_law (varop);
9422 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9423 says that the sign bit can be tested, FOO has mode MODE, C is
9424 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9425 that may be nonzero. */
9426 if (code == LSHIFTRT
9427 && XEXP (varop, 1) == const0_rtx
9428 && GET_MODE (XEXP (varop, 0)) == result_mode
9429 && count == GET_MODE_BITSIZE (result_mode) - 1
9430 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9431 && ((STORE_FLAG_VALUE
9432 & ((HOST_WIDE_INT) 1
9433 < (GET_MODE_BITSIZE (result_mode) - 1))))
9434 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9435 && merge_outer_ops (&outer_op, &outer_const, XOR,
9436 (HOST_WIDE_INT) 1, result_mode,
9439 varop = XEXP (varop, 0);
9446 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9447 than the number of bits in the mode is equivalent to A. */
9448 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9449 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9451 varop = XEXP (varop, 0);
9456 /* NEG commutes with ASHIFT since it is multiplication. Move the
9457 NEG outside to allow shifts to combine. */
9459 && merge_outer_ops (&outer_op, &outer_const, NEG,
9460 (HOST_WIDE_INT) 0, result_mode,
9463 varop = XEXP (varop, 0);
9469 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9470 is one less than the number of bits in the mode is
9471 equivalent to (xor A 1). */
9472 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9473 && XEXP (varop, 1) == constm1_rtx
9474 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9475 && merge_outer_ops (&outer_op, &outer_const, XOR,
9476 (HOST_WIDE_INT) 1, result_mode,
9480 varop = XEXP (varop, 0);
9484 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9485 that might be nonzero in BAR are those being shifted out and those
9486 bits are known zero in FOO, we can replace the PLUS with FOO.
9487 Similarly in the other operand order. This code occurs when
9488 we are computing the size of a variable-size array. */
9490 if ((code == ASHIFTRT || code == LSHIFTRT)
9491 && count < HOST_BITS_PER_WIDE_INT
9492 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9493 && (nonzero_bits (XEXP (varop, 1), result_mode)
9494 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9496 varop = XEXP (varop, 0);
9499 else if ((code == ASHIFTRT || code == LSHIFTRT)
9500 && count < HOST_BITS_PER_WIDE_INT
9501 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9502 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9504 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9505 & nonzero_bits (XEXP (varop, 1),
9508 varop = XEXP (varop, 1);
9512 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9514 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9515 && (new = simplify_binary_operation (ASHIFT, result_mode,
9517 GEN_INT (count))) != 0
9518 && GET_CODE (new) == CONST_INT
9519 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9520 INTVAL (new), result_mode, &complement_p))
9522 varop = XEXP (varop, 0);
9528 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9529 with C the size of VAROP - 1 and the shift is logical if
9530 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9531 we have a (gt X 0) operation. If the shift is arithmetic with
9532 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9533 we have a (neg (gt X 0)) operation. */
9535 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9536 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9537 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9538 && (code == LSHIFTRT || code == ASHIFTRT)
9539 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9540 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9541 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9544 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9547 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9548 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9555 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9556 if the truncate does not affect the value. */
9557 if (code == LSHIFTRT
9558 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9559 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9560 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9561 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9562 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9564 rtx varop_inner = XEXP (varop, 0);
9567 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9568 XEXP (varop_inner, 0),
9570 (count + INTVAL (XEXP (varop_inner, 1))));
9571 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9584 /* We need to determine what mode to do the shift in. If the shift is
9585 a right shift or ROTATE, we must always do it in the mode it was
9586 originally done in. Otherwise, we can do it in MODE, the widest mode
9587 encountered. The code we care about is that of the shift that will
9588 actually be done, not the shift that was originally requested. */
9590 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9591 ? result_mode : mode);
9593 /* We have now finished analyzing the shift. The result should be
9594 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9595 OUTER_OP is non-NIL, it is an operation that needs to be applied
9596 to the result of the shift. OUTER_CONST is the relevant constant,
9597 but we must turn off all bits turned off in the shift.
9599 If we were passed a value for X, see if we can use any pieces of
9600 it. If not, make new rtx. */
9602 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9603 && GET_CODE (XEXP (x, 1)) == CONST_INT
9604 && INTVAL (XEXP (x, 1)) == count)
9605 const_rtx = XEXP (x, 1);
9607 const_rtx = GEN_INT (count);
9609 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9610 && GET_MODE (XEXP (x, 0)) == shift_mode
9611 && SUBREG_REG (XEXP (x, 0)) == varop)
9612 varop = XEXP (x, 0);
9613 else if (GET_MODE (varop) != shift_mode)
9614 varop = gen_lowpart_for_combine (shift_mode, varop);
9616 /* If we can't make the SUBREG, try to return what we were given. */
9617 if (GET_CODE (varop) == CLOBBER)
9618 return x ? x : varop;
9620 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9624 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9626 /* If we have an outer operation and we just made a shift, it is
9627 possible that we could have simplified the shift were it not
9628 for the outer operation. So try to do the simplification
9631 if (outer_op != NIL && GET_CODE (x) == code
9632 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9633 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9634 INTVAL (XEXP (x, 1)));
9636 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9637 turn off all the bits that the shift would have turned off. */
9638 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9639 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9640 GET_MODE_MASK (result_mode) >> orig_count);
9642 /* Do the remainder of the processing in RESULT_MODE. */
9643 x = gen_lowpart_for_combine (result_mode, x);
9645 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9648 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9650 if (outer_op != NIL)
9652 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9653 outer_const = trunc_int_for_mode (outer_const, result_mode);
9655 if (outer_op == AND)
9656 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9657 else if (outer_op == SET)
9658 /* This means that we have determined that the result is
9659 equivalent to a constant. This should be rare. */
9660 x = GEN_INT (outer_const);
9661 else if (GET_RTX_CLASS (outer_op) == '1')
9662 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9664 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9670 /* Like recog, but we receive the address of a pointer to a new pattern.
9671 We try to match the rtx that the pointer points to.
9672 If that fails, we may try to modify or replace the pattern,
9673 storing the replacement into the same pointer object.
9675 Modifications include deletion or addition of CLOBBERs.
9677 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9678 the CLOBBERs are placed.
9680 The value is the final insn code from the pattern ultimately matched,
9684 recog_for_combine (pnewpat, insn, pnotes)
9690 int insn_code_number;
9691 int num_clobbers_to_add = 0;
9696 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9697 we use to indicate that something didn't match. If we find such a
9698 thing, force rejection. */
9699 if (GET_CODE (pat) == PARALLEL)
9700 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9701 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9702 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9705 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9706 instruction for pattern recognition. */
9707 dummy_insn = shallow_copy_rtx (insn);
9708 PATTERN (dummy_insn) = pat;
9709 REG_NOTES (dummy_insn) = 0;
9711 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9713 /* If it isn't, there is the possibility that we previously had an insn
9714 that clobbered some register as a side effect, but the combined
9715 insn doesn't need to do that. So try once more without the clobbers
9716 unless this represents an ASM insn. */
9718 if (insn_code_number < 0 && ! check_asm_operands (pat)
9719 && GET_CODE (pat) == PARALLEL)
9723 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9724 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9727 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9731 SUBST_INT (XVECLEN (pat, 0), pos);
9734 pat = XVECEXP (pat, 0, 0);
9736 PATTERN (dummy_insn) = pat;
9737 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9740 /* Recognize all noop sets, these will be killed by followup pass. */
9741 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9742 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9744 /* If we had any clobbers to add, make a new pattern than contains
9745 them. Then check to make sure that all of them are dead. */
9746 if (num_clobbers_to_add)
9748 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9749 rtvec_alloc (GET_CODE (pat) == PARALLEL
9751 + num_clobbers_to_add)
9752 : num_clobbers_to_add + 1));
9754 if (GET_CODE (pat) == PARALLEL)
9755 for (i = 0; i < XVECLEN (pat, 0); i++)
9756 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9758 XVECEXP (newpat, 0, 0) = pat;
9760 add_clobbers (newpat, insn_code_number);
9762 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9763 i < XVECLEN (newpat, 0); i++)
9765 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9766 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9768 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9769 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9777 return insn_code_number;
9780 /* Like gen_lowpart but for use by combine. In combine it is not possible
9781 to create any new pseudoregs. However, it is safe to create
9782 invalid memory addresses, because combine will try to recognize
9783 them and all they will do is make the combine attempt fail.
9785 If for some reason this cannot do its job, an rtx
9786 (clobber (const_int 0)) is returned.
9787 An insn containing that will not be recognized. */
9792 gen_lowpart_for_combine (mode, x)
9793 enum machine_mode mode;
9798 if (GET_MODE (x) == mode)
9801 /* We can only support MODE being wider than a word if X is a
9802 constant integer or has a mode the same size. */
9804 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9805 && ! ((GET_MODE (x) == VOIDmode
9806 && (GET_CODE (x) == CONST_INT
9807 || GET_CODE (x) == CONST_DOUBLE))
9808 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9809 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9811 /* simplify_gen_subreg does not know how to handle the case where we try
9812 to convert an integer constant to a vector.
9813 ??? We could try to teach it to generate CONST_VECTORs. */
9814 if (GET_MODE (x) == VOIDmode && VECTOR_MODE_P (mode))
9815 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9817 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9818 won't know what to do. So we will strip off the SUBREG here and
9819 process normally. */
9820 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9823 if (GET_MODE (x) == mode)
9827 result = gen_lowpart_common (mode, x);
9828 #ifdef CLASS_CANNOT_CHANGE_MODE
9830 && GET_CODE (result) == SUBREG
9831 && GET_CODE (SUBREG_REG (result)) == REG
9832 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9833 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9834 GET_MODE (SUBREG_REG (result))))
9835 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9841 if (GET_CODE (x) == MEM)
9845 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9847 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9848 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9850 /* If we want to refer to something bigger than the original memref,
9851 generate a perverse subreg instead. That will force a reload
9852 of the original memref X. */
9853 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9854 return gen_rtx_SUBREG (mode, x, 0);
9856 if (WORDS_BIG_ENDIAN)
9857 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9858 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9860 if (BYTES_BIG_ENDIAN)
9862 /* Adjust the address so that the address-after-the-data is
9864 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9865 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9868 return adjust_address_nv (x, mode, offset);
9871 /* If X is a comparison operator, rewrite it in a new mode. This
9872 probably won't match, but may allow further simplifications. */
9873 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9874 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9876 /* If we couldn't simplify X any other way, just enclose it in a
9877 SUBREG. Normally, this SUBREG won't match, but some patterns may
9878 include an explicit SUBREG or we may simplify it further in combine. */
9884 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9885 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9888 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9892 /* These routines make binary and unary operations by first seeing if they
9893 fold; if not, a new expression is allocated. */
9896 gen_binary (code, mode, op0, op1)
9898 enum machine_mode mode;
9904 if (GET_RTX_CLASS (code) == 'c'
9905 && swap_commutative_operands_p (op0, op1))
9906 tem = op0, op0 = op1, op1 = tem;
9908 if (GET_RTX_CLASS (code) == '<')
9910 enum machine_mode op_mode = GET_MODE (op0);
9912 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9913 just (REL_OP X Y). */
9914 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9916 op1 = XEXP (op0, 1);
9917 op0 = XEXP (op0, 0);
9918 op_mode = GET_MODE (op0);
9921 if (op_mode == VOIDmode)
9922 op_mode = GET_MODE (op1);
9923 result = simplify_relational_operation (code, op_mode, op0, op1);
9926 result = simplify_binary_operation (code, mode, op0, op1);
9931 /* Put complex operands first and constants second. */
9932 if (GET_RTX_CLASS (code) == 'c'
9933 && swap_commutative_operands_p (op0, op1))
9934 return gen_rtx_fmt_ee (code, mode, op1, op0);
9936 /* If we are turning off bits already known off in OP0, we need not do
9938 else if (code == AND && GET_CODE (op1) == CONST_INT
9939 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9940 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9943 return gen_rtx_fmt_ee (code, mode, op0, op1);
9946 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9947 comparison code that will be tested.
9949 The result is a possibly different comparison code to use. *POP0 and
9950 *POP1 may be updated.
9952 It is possible that we might detect that a comparison is either always
9953 true or always false. However, we do not perform general constant
9954 folding in combine, so this knowledge isn't useful. Such tautologies
9955 should have been detected earlier. Hence we ignore all such cases. */
9957 static enum rtx_code
9958 simplify_comparison (code, pop0, pop1)
9967 enum machine_mode mode, tmode;
9969 /* Try a few ways of applying the same transformation to both operands. */
9972 #ifndef WORD_REGISTER_OPERATIONS
9973 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9974 so check specially. */
9975 if (code != GTU && code != GEU && code != LTU && code != LEU
9976 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9977 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9978 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9979 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9980 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9981 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9982 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9983 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9984 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9985 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9986 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9987 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9988 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9989 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9990 && (INTVAL (XEXP (op0, 1))
9991 == (GET_MODE_BITSIZE (GET_MODE (op0))
9993 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9995 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9996 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10000 /* If both operands are the same constant shift, see if we can ignore the
10001 shift. We can if the shift is a rotate or if the bits shifted out of
10002 this shift are known to be zero for both inputs and if the type of
10003 comparison is compatible with the shift. */
10004 if (GET_CODE (op0) == GET_CODE (op1)
10005 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10006 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10007 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10008 && (code != GT && code != LT && code != GE && code != LE))
10009 || (GET_CODE (op0) == ASHIFTRT
10010 && (code != GTU && code != LTU
10011 && code != GEU && code != LEU)))
10012 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10013 && INTVAL (XEXP (op0, 1)) >= 0
10014 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10015 && XEXP (op0, 1) == XEXP (op1, 1))
10017 enum machine_mode mode = GET_MODE (op0);
10018 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10019 int shift_count = INTVAL (XEXP (op0, 1));
10021 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10022 mask &= (mask >> shift_count) << shift_count;
10023 else if (GET_CODE (op0) == ASHIFT)
10024 mask = (mask & (mask << shift_count)) >> shift_count;
10026 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10027 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10028 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10033 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10034 SUBREGs are of the same mode, and, in both cases, the AND would
10035 be redundant if the comparison was done in the narrower mode,
10036 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10037 and the operand's possibly nonzero bits are 0xffffff01; in that case
10038 if we only care about QImode, we don't need the AND). This case
10039 occurs if the output mode of an scc insn is not SImode and
10040 STORE_FLAG_VALUE == 1 (e.g., the 386).
10042 Similarly, check for a case where the AND's are ZERO_EXTEND
10043 operations from some narrower mode even though a SUBREG is not
10046 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10047 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10048 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10050 rtx inner_op0 = XEXP (op0, 0);
10051 rtx inner_op1 = XEXP (op1, 0);
10052 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10053 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10056 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10057 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10058 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10059 && (GET_MODE (SUBREG_REG (inner_op0))
10060 == GET_MODE (SUBREG_REG (inner_op1)))
10061 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10062 <= HOST_BITS_PER_WIDE_INT)
10063 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10064 GET_MODE (SUBREG_REG (inner_op0)))))
10065 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10066 GET_MODE (SUBREG_REG (inner_op1))))))
10068 op0 = SUBREG_REG (inner_op0);
10069 op1 = SUBREG_REG (inner_op1);
10071 /* The resulting comparison is always unsigned since we masked
10072 off the original sign bit. */
10073 code = unsigned_condition (code);
10079 for (tmode = GET_CLASS_NARROWEST_MODE
10080 (GET_MODE_CLASS (GET_MODE (op0)));
10081 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10082 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10084 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10085 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10086 code = unsigned_condition (code);
10095 /* If both operands are NOT, we can strip off the outer operation
10096 and adjust the comparison code for swapped operands; similarly for
10097 NEG, except that this must be an equality comparison. */
10098 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10099 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10100 && (code == EQ || code == NE)))
10101 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10107 /* If the first operand is a constant, swap the operands and adjust the
10108 comparison code appropriately, but don't do this if the second operand
10109 is already a constant integer. */
10110 if (swap_commutative_operands_p (op0, op1))
10112 tem = op0, op0 = op1, op1 = tem;
10113 code = swap_condition (code);
10116 /* We now enter a loop during which we will try to simplify the comparison.
10117 For the most part, we only are concerned with comparisons with zero,
10118 but some things may really be comparisons with zero but not start
10119 out looking that way. */
10121 while (GET_CODE (op1) == CONST_INT)
10123 enum machine_mode mode = GET_MODE (op0);
10124 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10125 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10126 int equality_comparison_p;
10127 int sign_bit_comparison_p;
10128 int unsigned_comparison_p;
10129 HOST_WIDE_INT const_op;
10131 /* We only want to handle integral modes. This catches VOIDmode,
10132 CCmode, and the floating-point modes. An exception is that we
10133 can handle VOIDmode if OP0 is a COMPARE or a comparison
10136 if (GET_MODE_CLASS (mode) != MODE_INT
10137 && ! (mode == VOIDmode
10138 && (GET_CODE (op0) == COMPARE
10139 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10142 /* Get the constant we are comparing against and turn off all bits
10143 not on in our mode. */
10144 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10145 op1 = GEN_INT (const_op);
10147 /* If we are comparing against a constant power of two and the value
10148 being compared can only have that single bit nonzero (e.g., it was
10149 `and'ed with that bit), we can replace this with a comparison
10152 && (code == EQ || code == NE || code == GE || code == GEU
10153 || code == LT || code == LTU)
10154 && mode_width <= HOST_BITS_PER_WIDE_INT
10155 && exact_log2 (const_op) >= 0
10156 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10158 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10159 op1 = const0_rtx, const_op = 0;
10162 /* Similarly, if we are comparing a value known to be either -1 or
10163 0 with -1, change it to the opposite comparison against zero. */
10166 && (code == EQ || code == NE || code == GT || code == LE
10167 || code == GEU || code == LTU)
10168 && num_sign_bit_copies (op0, mode) == mode_width)
10170 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10171 op1 = const0_rtx, const_op = 0;
10174 /* Do some canonicalizations based on the comparison code. We prefer
10175 comparisons against zero and then prefer equality comparisons.
10176 If we can reduce the size of a constant, we will do that too. */
10181 /* < C is equivalent to <= (C - 1) */
10185 op1 = GEN_INT (const_op);
10187 /* ... fall through to LE case below. */
10193 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10197 op1 = GEN_INT (const_op);
10201 /* If we are doing a <= 0 comparison on a value known to have
10202 a zero sign bit, we can replace this with == 0. */
10203 else if (const_op == 0
10204 && mode_width <= HOST_BITS_PER_WIDE_INT
10205 && (nonzero_bits (op0, mode)
10206 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10211 /* >= C is equivalent to > (C - 1). */
10215 op1 = GEN_INT (const_op);
10217 /* ... fall through to GT below. */
10223 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10227 op1 = GEN_INT (const_op);
10231 /* If we are doing a > 0 comparison on a value known to have
10232 a zero sign bit, we can replace this with != 0. */
10233 else if (const_op == 0
10234 && mode_width <= HOST_BITS_PER_WIDE_INT
10235 && (nonzero_bits (op0, mode)
10236 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10241 /* < C is equivalent to <= (C - 1). */
10245 op1 = GEN_INT (const_op);
10247 /* ... fall through ... */
10250 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10251 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10252 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10254 const_op = 0, op1 = const0_rtx;
10262 /* unsigned <= 0 is equivalent to == 0 */
10266 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10267 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10268 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10270 const_op = 0, op1 = const0_rtx;
10276 /* >= C is equivalent to < (C - 1). */
10280 op1 = GEN_INT (const_op);
10282 /* ... fall through ... */
10285 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10286 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10287 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10289 const_op = 0, op1 = const0_rtx;
10297 /* unsigned > 0 is equivalent to != 0 */
10301 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10302 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10303 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10305 const_op = 0, op1 = const0_rtx;
10314 /* Compute some predicates to simplify code below. */
10316 equality_comparison_p = (code == EQ || code == NE);
10317 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10318 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10321 /* If this is a sign bit comparison and we can do arithmetic in
10322 MODE, say that we will only be needing the sign bit of OP0. */
10323 if (sign_bit_comparison_p
10324 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10325 op0 = force_to_mode (op0, mode,
10327 << (GET_MODE_BITSIZE (mode) - 1)),
10330 /* Now try cases based on the opcode of OP0. If none of the cases
10331 does a "continue", we exit this loop immediately after the
10334 switch (GET_CODE (op0))
10337 /* If we are extracting a single bit from a variable position in
10338 a constant that has only a single bit set and are comparing it
10339 with zero, we can convert this into an equality comparison
10340 between the position and the location of the single bit. */
10342 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10343 && XEXP (op0, 1) == const1_rtx
10344 && equality_comparison_p && const_op == 0
10345 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10347 if (BITS_BIG_ENDIAN)
10349 enum machine_mode new_mode
10350 = mode_for_extraction (EP_extzv, 1);
10351 if (new_mode == MAX_MACHINE_MODE)
10352 i = BITS_PER_WORD - 1 - i;
10356 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10360 op0 = XEXP (op0, 2);
10364 /* Result is nonzero iff shift count is equal to I. */
10365 code = reverse_condition (code);
10369 /* ... fall through ... */
10372 tem = expand_compound_operation (op0);
10381 /* If testing for equality, we can take the NOT of the constant. */
10382 if (equality_comparison_p
10383 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10385 op0 = XEXP (op0, 0);
10390 /* If just looking at the sign bit, reverse the sense of the
10392 if (sign_bit_comparison_p)
10394 op0 = XEXP (op0, 0);
10395 code = (code == GE ? LT : GE);
10401 /* If testing for equality, we can take the NEG of the constant. */
10402 if (equality_comparison_p
10403 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10405 op0 = XEXP (op0, 0);
10410 /* The remaining cases only apply to comparisons with zero. */
10414 /* When X is ABS or is known positive,
10415 (neg X) is < 0 if and only if X != 0. */
10417 if (sign_bit_comparison_p
10418 && (GET_CODE (XEXP (op0, 0)) == ABS
10419 || (mode_width <= HOST_BITS_PER_WIDE_INT
10420 && (nonzero_bits (XEXP (op0, 0), mode)
10421 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10423 op0 = XEXP (op0, 0);
10424 code = (code == LT ? NE : EQ);
10428 /* If we have NEG of something whose two high-order bits are the
10429 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10430 if (num_sign_bit_copies (op0, mode) >= 2)
10432 op0 = XEXP (op0, 0);
10433 code = swap_condition (code);
10439 /* If we are testing equality and our count is a constant, we
10440 can perform the inverse operation on our RHS. */
10441 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10442 && (tem = simplify_binary_operation (ROTATERT, mode,
10443 op1, XEXP (op0, 1))) != 0)
10445 op0 = XEXP (op0, 0);
10450 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10451 a particular bit. Convert it to an AND of a constant of that
10452 bit. This will be converted into a ZERO_EXTRACT. */
10453 if (const_op == 0 && sign_bit_comparison_p
10454 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10455 && mode_width <= HOST_BITS_PER_WIDE_INT)
10457 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10460 - INTVAL (XEXP (op0, 1)))));
10461 code = (code == LT ? NE : EQ);
10465 /* Fall through. */
10468 /* ABS is ignorable inside an equality comparison with zero. */
10469 if (const_op == 0 && equality_comparison_p)
10471 op0 = XEXP (op0, 0);
10477 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10478 to (compare FOO CONST) if CONST fits in FOO's mode and we
10479 are either testing inequality or have an unsigned comparison
10480 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10481 if (! unsigned_comparison_p
10482 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10483 <= HOST_BITS_PER_WIDE_INT)
10484 && ((unsigned HOST_WIDE_INT) const_op
10485 < (((unsigned HOST_WIDE_INT) 1
10486 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10488 op0 = XEXP (op0, 0);
10494 /* Check for the case where we are comparing A - C1 with C2,
10495 both constants are smaller than 1/2 the maximum positive
10496 value in MODE, and the comparison is equality or unsigned.
10497 In that case, if A is either zero-extended to MODE or has
10498 sufficient sign bits so that the high-order bit in MODE
10499 is a copy of the sign in the inner mode, we can prove that it is
10500 safe to do the operation in the wider mode. This simplifies
10501 many range checks. */
10503 if (mode_width <= HOST_BITS_PER_WIDE_INT
10504 && subreg_lowpart_p (op0)
10505 && GET_CODE (SUBREG_REG (op0)) == PLUS
10506 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10507 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10508 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10509 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10510 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10511 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10512 GET_MODE (SUBREG_REG (op0)))
10513 & ~GET_MODE_MASK (mode))
10514 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10515 GET_MODE (SUBREG_REG (op0)))
10516 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10517 - GET_MODE_BITSIZE (mode)))))
10519 op0 = SUBREG_REG (op0);
10523 /* If the inner mode is narrower and we are extracting the low part,
10524 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10525 if (subreg_lowpart_p (op0)
10526 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10527 /* Fall through */ ;
10531 /* ... fall through ... */
10534 if ((unsigned_comparison_p || equality_comparison_p)
10535 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10536 <= HOST_BITS_PER_WIDE_INT)
10537 && ((unsigned HOST_WIDE_INT) const_op
10538 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10540 op0 = XEXP (op0, 0);
10546 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10547 this for equality comparisons due to pathological cases involving
10549 if (equality_comparison_p
10550 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10551 op1, XEXP (op0, 1))))
10553 op0 = XEXP (op0, 0);
10558 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10559 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10560 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10562 op0 = XEXP (XEXP (op0, 0), 0);
10563 code = (code == LT ? EQ : NE);
10569 /* We used to optimize signed comparisons against zero, but that
10570 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10571 arrive here as equality comparisons, or (GEU, LTU) are
10572 optimized away. No need to special-case them. */
10574 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10575 (eq B (minus A C)), whichever simplifies. We can only do
10576 this for equality comparisons due to pathological cases involving
10578 if (equality_comparison_p
10579 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10580 XEXP (op0, 1), op1)))
10582 op0 = XEXP (op0, 0);
10587 if (equality_comparison_p
10588 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10589 XEXP (op0, 0), op1)))
10591 op0 = XEXP (op0, 1);
10596 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10597 of bits in X minus 1, is one iff X > 0. */
10598 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10599 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10600 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10601 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10603 op0 = XEXP (op0, 1);
10604 code = (code == GE ? LE : GT);
10610 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10611 if C is zero or B is a constant. */
10612 if (equality_comparison_p
10613 && 0 != (tem = simplify_binary_operation (XOR, mode,
10614 XEXP (op0, 1), op1)))
10616 op0 = XEXP (op0, 0);
10623 case UNEQ: case LTGT:
10624 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10625 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10626 case UNORDERED: case ORDERED:
10627 /* We can't do anything if OP0 is a condition code value, rather
10628 than an actual data value. */
10631 || XEXP (op0, 0) == cc0_rtx
10633 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10636 /* Get the two operands being compared. */
10637 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10638 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10640 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10642 /* Check for the cases where we simply want the result of the
10643 earlier test or the opposite of that result. */
10644 if (code == NE || code == EQ
10645 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10646 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10647 && (STORE_FLAG_VALUE
10648 & (((HOST_WIDE_INT) 1
10649 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10650 && (code == LT || code == GE)))
10652 enum rtx_code new_code;
10653 if (code == LT || code == NE)
10654 new_code = GET_CODE (op0);
10656 new_code = combine_reversed_comparison_code (op0);
10658 if (new_code != UNKNOWN)
10669 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10671 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10672 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10673 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10675 op0 = XEXP (op0, 1);
10676 code = (code == GE ? GT : LE);
10682 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10683 will be converted to a ZERO_EXTRACT later. */
10684 if (const_op == 0 && equality_comparison_p
10685 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10686 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10688 op0 = simplify_and_const_int
10689 (op0, mode, gen_rtx_LSHIFTRT (mode,
10691 XEXP (XEXP (op0, 0), 1)),
10692 (HOST_WIDE_INT) 1);
10696 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10697 zero and X is a comparison and C1 and C2 describe only bits set
10698 in STORE_FLAG_VALUE, we can compare with X. */
10699 if (const_op == 0 && equality_comparison_p
10700 && mode_width <= HOST_BITS_PER_WIDE_INT
10701 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10702 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10703 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10704 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10705 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10707 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10708 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10709 if ((~STORE_FLAG_VALUE & mask) == 0
10710 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10711 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10712 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10714 op0 = XEXP (XEXP (op0, 0), 0);
10719 /* If we are doing an equality comparison of an AND of a bit equal
10720 to the sign bit, replace this with a LT or GE comparison of
10721 the underlying value. */
10722 if (equality_comparison_p
10724 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10725 && mode_width <= HOST_BITS_PER_WIDE_INT
10726 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10727 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10729 op0 = XEXP (op0, 0);
10730 code = (code == EQ ? GE : LT);
10734 /* If this AND operation is really a ZERO_EXTEND from a narrower
10735 mode, the constant fits within that mode, and this is either an
10736 equality or unsigned comparison, try to do this comparison in
10737 the narrower mode. */
10738 if ((equality_comparison_p || unsigned_comparison_p)
10739 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10740 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10741 & GET_MODE_MASK (mode))
10743 && const_op >> i == 0
10744 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10746 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10750 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10751 in both M1 and M2 and the SUBREG is either paradoxical or
10752 represents the low part, permute the SUBREG and the AND and
10754 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10756 #ifdef WORD_REGISTER_OPERATIONS
10758 > (GET_MODE_BITSIZE
10759 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10760 && mode_width <= BITS_PER_WORD)
10763 <= (GET_MODE_BITSIZE
10764 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10765 && subreg_lowpart_p (XEXP (op0, 0))))
10766 #ifndef WORD_REGISTER_OPERATIONS
10767 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10768 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10769 As originally written the upper bits have a defined value
10770 due to the AND operation. However, if we commute the AND
10771 inside the SUBREG then they no longer have defined values
10772 and the meaning of the code has been changed. */
10773 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10774 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10776 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10777 && mode_width <= HOST_BITS_PER_WIDE_INT
10778 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10779 <= HOST_BITS_PER_WIDE_INT)
10780 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10781 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10782 & INTVAL (XEXP (op0, 1)))
10783 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10784 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10785 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10789 = gen_lowpart_for_combine
10791 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10792 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10796 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10797 (eq (and (lshiftrt X) 1) 0). */
10798 if (const_op == 0 && equality_comparison_p
10799 && XEXP (op0, 1) == const1_rtx
10800 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10801 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10803 op0 = simplify_and_const_int
10805 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10806 XEXP (XEXP (op0, 0), 1)),
10807 (HOST_WIDE_INT) 1);
10808 code = (code == NE ? EQ : NE);
10814 /* If we have (compare (ashift FOO N) (const_int C)) and
10815 the high order N bits of FOO (N+1 if an inequality comparison)
10816 are known to be zero, we can do this by comparing FOO with C
10817 shifted right N bits so long as the low-order N bits of C are
10819 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10820 && INTVAL (XEXP (op0, 1)) >= 0
10821 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10822 < HOST_BITS_PER_WIDE_INT)
10824 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10825 && mode_width <= HOST_BITS_PER_WIDE_INT
10826 && (nonzero_bits (XEXP (op0, 0), mode)
10827 & ~(mask >> (INTVAL (XEXP (op0, 1))
10828 + ! equality_comparison_p))) == 0)
10830 /* We must perform a logical shift, not an arithmetic one,
10831 as we want the top N bits of C to be zero. */
10832 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10834 temp >>= INTVAL (XEXP (op0, 1));
10835 op1 = gen_int_mode (temp, mode);
10836 op0 = XEXP (op0, 0);
10840 /* If we are doing a sign bit comparison, it means we are testing
10841 a particular bit. Convert it to the appropriate AND. */
10842 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10843 && mode_width <= HOST_BITS_PER_WIDE_INT)
10845 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10848 - INTVAL (XEXP (op0, 1)))));
10849 code = (code == LT ? NE : EQ);
10853 /* If this an equality comparison with zero and we are shifting
10854 the low bit to the sign bit, we can convert this to an AND of the
10856 if (const_op == 0 && equality_comparison_p
10857 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10858 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10860 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10861 (HOST_WIDE_INT) 1);
10867 /* If this is an equality comparison with zero, we can do this
10868 as a logical shift, which might be much simpler. */
10869 if (equality_comparison_p && const_op == 0
10870 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10872 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10874 INTVAL (XEXP (op0, 1)));
10878 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10879 do the comparison in a narrower mode. */
10880 if (! unsigned_comparison_p
10881 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10882 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10883 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10884 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10885 MODE_INT, 1)) != BLKmode
10886 && (((unsigned HOST_WIDE_INT) const_op
10887 + (GET_MODE_MASK (tmode) >> 1) + 1)
10888 <= GET_MODE_MASK (tmode)))
10890 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10894 /* Likewise if OP0 is a PLUS of a sign extension with a
10895 constant, which is usually represented with the PLUS
10896 between the shifts. */
10897 if (! unsigned_comparison_p
10898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && GET_CODE (XEXP (op0, 0)) == PLUS
10900 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10901 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10902 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10903 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10904 MODE_INT, 1)) != BLKmode
10905 && (((unsigned HOST_WIDE_INT) const_op
10906 + (GET_MODE_MASK (tmode) >> 1) + 1)
10907 <= GET_MODE_MASK (tmode)))
10909 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10910 rtx add_const = XEXP (XEXP (op0, 0), 1);
10911 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10914 op0 = gen_binary (PLUS, tmode,
10915 gen_lowpart_for_combine (tmode, inner),
10920 /* ... fall through ... */
10922 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10923 the low order N bits of FOO are known to be zero, we can do this
10924 by comparing FOO with C shifted left N bits so long as no
10925 overflow occurs. */
10926 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10927 && INTVAL (XEXP (op0, 1)) >= 0
10928 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10929 && mode_width <= HOST_BITS_PER_WIDE_INT
10930 && (nonzero_bits (XEXP (op0, 0), mode)
10931 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10932 && (((unsigned HOST_WIDE_INT) const_op
10933 + (GET_CODE (op0) != LSHIFTRT
10934 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10937 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10939 /* If the shift was logical, then we must make the condition
10941 if (GET_CODE (op0) == LSHIFTRT)
10942 code = unsigned_condition (code);
10944 const_op <<= INTVAL (XEXP (op0, 1));
10945 op1 = GEN_INT (const_op);
10946 op0 = XEXP (op0, 0);
10950 /* If we are using this shift to extract just the sign bit, we
10951 can replace this with an LT or GE comparison. */
10953 && (equality_comparison_p || sign_bit_comparison_p)
10954 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10955 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10957 op0 = XEXP (op0, 0);
10958 code = (code == NE || code == GT ? LT : GE);
10970 /* Now make any compound operations involved in this comparison. Then,
10971 check for an outmost SUBREG on OP0 that is not doing anything or is
10972 paradoxical. The latter transformation must only be performed when
10973 it is known that the "extra" bits will be the same in op0 and op1 or
10974 that they don't matter. There are three cases to consider:
10976 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10977 care bits and we can assume they have any convenient value. So
10978 making the transformation is safe.
10980 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10981 In this case the upper bits of op0 are undefined. We should not make
10982 the simplification in that case as we do not know the contents of
10985 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10986 NIL. In that case we know those bits are zeros or ones. We must
10987 also be sure that they are the same as the upper bits of op1.
10989 We can never remove a SUBREG for a non-equality comparison because
10990 the sign bit is in a different place in the underlying object. */
10992 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10993 op1 = make_compound_operation (op1, SET);
10995 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10996 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
10998 && GET_CODE (SUBREG_REG (op0)) == REG
10999 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11000 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11001 && (code == NE || code == EQ))
11003 if (GET_MODE_SIZE (GET_MODE (op0))
11004 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11006 op0 = SUBREG_REG (op0);
11007 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11009 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11010 <= HOST_BITS_PER_WIDE_INT)
11011 && (nonzero_bits (SUBREG_REG (op0),
11012 GET_MODE (SUBREG_REG (op0)))
11013 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11015 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11017 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11018 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11019 op0 = SUBREG_REG (op0), op1 = tem;
11023 /* We now do the opposite procedure: Some machines don't have compare
11024 insns in all modes. If OP0's mode is an integer mode smaller than a
11025 word and we can't do a compare in that mode, see if there is a larger
11026 mode for which we can do the compare. There are a number of cases in
11027 which we can use the wider mode. */
11029 mode = GET_MODE (op0);
11030 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11031 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11032 && ! have_insn_for (COMPARE, mode))
11033 for (tmode = GET_MODE_WIDER_MODE (mode);
11035 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11036 tmode = GET_MODE_WIDER_MODE (tmode))
11037 if (have_insn_for (COMPARE, tmode))
11041 /* If the only nonzero bits in OP0 and OP1 are those in the
11042 narrower mode and this is an equality or unsigned comparison,
11043 we can use the wider mode. Similarly for sign-extended
11044 values, in which case it is true for all comparisons. */
11045 zero_extended = ((code == EQ || code == NE
11046 || code == GEU || code == GTU
11047 || code == LEU || code == LTU)
11048 && (nonzero_bits (op0, tmode)
11049 & ~GET_MODE_MASK (mode)) == 0
11050 && ((GET_CODE (op1) == CONST_INT
11051 || (nonzero_bits (op1, tmode)
11052 & ~GET_MODE_MASK (mode)) == 0)));
11055 || ((num_sign_bit_copies (op0, tmode)
11056 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11057 && (num_sign_bit_copies (op1, tmode)
11058 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11060 /* If OP0 is an AND and we don't have an AND in MODE either,
11061 make a new AND in the proper mode. */
11062 if (GET_CODE (op0) == AND
11063 && !have_insn_for (AND, mode))
11064 op0 = gen_binary (AND, tmode,
11065 gen_lowpart_for_combine (tmode,
11067 gen_lowpart_for_combine (tmode,
11070 op0 = gen_lowpart_for_combine (tmode, op0);
11071 if (zero_extended && GET_CODE (op1) == CONST_INT)
11072 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11073 op1 = gen_lowpart_for_combine (tmode, op1);
11077 /* If this is a test for negative, we can make an explicit
11078 test of the sign bit. */
11080 if (op1 == const0_rtx && (code == LT || code == GE)
11081 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11083 op0 = gen_binary (AND, tmode,
11084 gen_lowpart_for_combine (tmode, op0),
11085 GEN_INT ((HOST_WIDE_INT) 1
11086 << (GET_MODE_BITSIZE (mode) - 1)));
11087 code = (code == LT) ? NE : EQ;
11092 #ifdef CANONICALIZE_COMPARISON
11093 /* If this machine only supports a subset of valid comparisons, see if we
11094 can convert an unsupported one into a supported one. */
11095 CANONICALIZE_COMPARISON (code, op0, op1);
11104 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11105 searching backward. */
11106 static enum rtx_code
11107 combine_reversed_comparison_code (exp)
11110 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11113 if (code1 != UNKNOWN
11114 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11116 /* Otherwise try and find where the condition codes were last set and
11118 x = get_last_value (XEXP (exp, 0));
11119 if (!x || GET_CODE (x) != COMPARE)
11121 return reversed_comparison_code_parts (GET_CODE (exp),
11122 XEXP (x, 0), XEXP (x, 1), NULL);
11124 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11125 Return NULL_RTX in case we fail to do the reversal. */
11127 reversed_comparison (exp, mode, op0, op1)
11129 enum machine_mode mode;
11131 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11132 if (reversed_code == UNKNOWN)
11135 return gen_binary (reversed_code, mode, op0, op1);
11138 /* Utility function for following routine. Called when X is part of a value
11139 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11140 for each register mentioned. Similar to mention_regs in cse.c */
11143 update_table_tick (x)
11146 enum rtx_code code = GET_CODE (x);
11147 const char *fmt = GET_RTX_FORMAT (code);
11152 unsigned int regno = REGNO (x);
11153 unsigned int endregno
11154 = regno + (regno < FIRST_PSEUDO_REGISTER
11155 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11158 for (r = regno; r < endregno; r++)
11159 reg_last_set_table_tick[r] = label_tick;
11164 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11165 /* Note that we can't have an "E" in values stored; see
11166 get_last_value_validate. */
11168 update_table_tick (XEXP (x, i));
11171 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11172 are saying that the register is clobbered and we no longer know its
11173 value. If INSN is zero, don't update reg_last_set; this is only permitted
11174 with VALUE also zero and is used to invalidate the register. */
11177 record_value_for_reg (reg, insn, value)
11182 unsigned int regno = REGNO (reg);
11183 unsigned int endregno
11184 = regno + (regno < FIRST_PSEUDO_REGISTER
11185 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11188 /* If VALUE contains REG and we have a previous value for REG, substitute
11189 the previous value. */
11190 if (value && insn && reg_overlap_mentioned_p (reg, value))
11194 /* Set things up so get_last_value is allowed to see anything set up to
11196 subst_low_cuid = INSN_CUID (insn);
11197 tem = get_last_value (reg);
11199 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11200 it isn't going to be useful and will take a lot of time to process,
11201 so just use the CLOBBER. */
11205 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11206 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11207 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11208 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11209 tem = XEXP (tem, 0);
11211 value = replace_rtx (copy_rtx (value), reg, tem);
11215 /* For each register modified, show we don't know its value, that
11216 we don't know about its bitwise content, that its value has been
11217 updated, and that we don't know the location of the death of the
11219 for (i = regno; i < endregno; i++)
11222 reg_last_set[i] = insn;
11224 reg_last_set_value[i] = 0;
11225 reg_last_set_mode[i] = 0;
11226 reg_last_set_nonzero_bits[i] = 0;
11227 reg_last_set_sign_bit_copies[i] = 0;
11228 reg_last_death[i] = 0;
11231 /* Mark registers that are being referenced in this value. */
11233 update_table_tick (value);
11235 /* Now update the status of each register being set.
11236 If someone is using this register in this block, set this register
11237 to invalid since we will get confused between the two lives in this
11238 basic block. This makes using this register always invalid. In cse, we
11239 scan the table to invalidate all entries using this register, but this
11240 is too much work for us. */
11242 for (i = regno; i < endregno; i++)
11244 reg_last_set_label[i] = label_tick;
11245 if (value && reg_last_set_table_tick[i] == label_tick)
11246 reg_last_set_invalid[i] = 1;
11248 reg_last_set_invalid[i] = 0;
11251 /* The value being assigned might refer to X (like in "x++;"). In that
11252 case, we must replace it with (clobber (const_int 0)) to prevent
11254 if (value && ! get_last_value_validate (&value, insn,
11255 reg_last_set_label[regno], 0))
11257 value = copy_rtx (value);
11258 if (! get_last_value_validate (&value, insn,
11259 reg_last_set_label[regno], 1))
11263 /* For the main register being modified, update the value, the mode, the
11264 nonzero bits, and the number of sign bit copies. */
11266 reg_last_set_value[regno] = value;
11270 enum machine_mode mode = GET_MODE (reg);
11271 subst_low_cuid = INSN_CUID (insn);
11272 reg_last_set_mode[regno] = mode;
11273 if (GET_MODE_CLASS (mode) == MODE_INT
11274 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11275 mode = nonzero_bits_mode;
11276 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11277 reg_last_set_sign_bit_copies[regno]
11278 = num_sign_bit_copies (value, GET_MODE (reg));
11282 /* Called via note_stores from record_dead_and_set_regs to handle one
11283 SET or CLOBBER in an insn. DATA is the instruction in which the
11284 set is occurring. */
11287 record_dead_and_set_regs_1 (dest, setter, data)
11291 rtx record_dead_insn = (rtx) data;
11293 if (GET_CODE (dest) == SUBREG)
11294 dest = SUBREG_REG (dest);
11296 if (GET_CODE (dest) == REG)
11298 /* If we are setting the whole register, we know its value. Otherwise
11299 show that we don't know the value. We can handle SUBREG in
11301 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11302 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11303 else if (GET_CODE (setter) == SET
11304 && GET_CODE (SET_DEST (setter)) == SUBREG
11305 && SUBREG_REG (SET_DEST (setter)) == dest
11306 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11307 && subreg_lowpart_p (SET_DEST (setter)))
11308 record_value_for_reg (dest, record_dead_insn,
11309 gen_lowpart_for_combine (GET_MODE (dest),
11310 SET_SRC (setter)));
11312 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11314 else if (GET_CODE (dest) == MEM
11315 /* Ignore pushes, they clobber nothing. */
11316 && ! push_operand (dest, GET_MODE (dest)))
11317 mem_last_set = INSN_CUID (record_dead_insn);
11320 /* Update the records of when each REG was most recently set or killed
11321 for the things done by INSN. This is the last thing done in processing
11322 INSN in the combiner loop.
11324 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11325 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11326 and also the similar information mem_last_set (which insn most recently
11327 modified memory) and last_call_cuid (which insn was the most recent
11328 subroutine call). */
11331 record_dead_and_set_regs (insn)
11337 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11339 if (REG_NOTE_KIND (link) == REG_DEAD
11340 && GET_CODE (XEXP (link, 0)) == REG)
11342 unsigned int regno = REGNO (XEXP (link, 0));
11343 unsigned int endregno
11344 = regno + (regno < FIRST_PSEUDO_REGISTER
11345 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11348 for (i = regno; i < endregno; i++)
11349 reg_last_death[i] = insn;
11351 else if (REG_NOTE_KIND (link) == REG_INC)
11352 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11355 if (GET_CODE (insn) == CALL_INSN)
11357 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11358 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11360 reg_last_set_value[i] = 0;
11361 reg_last_set_mode[i] = 0;
11362 reg_last_set_nonzero_bits[i] = 0;
11363 reg_last_set_sign_bit_copies[i] = 0;
11364 reg_last_death[i] = 0;
11367 last_call_cuid = mem_last_set = INSN_CUID (insn);
11369 /* Don't bother recording what this insn does. It might set the
11370 return value register, but we can't combine into a call
11371 pattern anyway, so there's no point trying (and it may cause
11372 a crash, if e.g. we wind up asking for last_set_value of a
11373 SUBREG of the return value register). */
11377 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11380 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11381 register present in the SUBREG, so for each such SUBREG go back and
11382 adjust nonzero and sign bit information of the registers that are
11383 known to have some zero/sign bits set.
11385 This is needed because when combine blows the SUBREGs away, the
11386 information on zero/sign bits is lost and further combines can be
11387 missed because of that. */
11390 record_promoted_value (insn, subreg)
11395 unsigned int regno = REGNO (SUBREG_REG (subreg));
11396 enum machine_mode mode = GET_MODE (subreg);
11398 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11401 for (links = LOG_LINKS (insn); links;)
11403 insn = XEXP (links, 0);
11404 set = single_set (insn);
11406 if (! set || GET_CODE (SET_DEST (set)) != REG
11407 || REGNO (SET_DEST (set)) != regno
11408 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11410 links = XEXP (links, 1);
11414 if (reg_last_set[regno] == insn)
11416 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11417 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11420 if (GET_CODE (SET_SRC (set)) == REG)
11422 regno = REGNO (SET_SRC (set));
11423 links = LOG_LINKS (insn);
11430 /* Scan X for promoted SUBREGs. For each one found,
11431 note what it implies to the registers used in it. */
11434 check_promoted_subreg (insn, x)
11438 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11439 && GET_CODE (SUBREG_REG (x)) == REG)
11440 record_promoted_value (insn, x);
11443 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11446 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11450 check_promoted_subreg (insn, XEXP (x, i));
11454 if (XVEC (x, i) != 0)
11455 for (j = 0; j < XVECLEN (x, i); j++)
11456 check_promoted_subreg (insn, XVECEXP (x, i, j));
11462 /* Utility routine for the following function. Verify that all the registers
11463 mentioned in *LOC are valid when *LOC was part of a value set when
11464 label_tick == TICK. Return 0 if some are not.
11466 If REPLACE is non-zero, replace the invalid reference with
11467 (clobber (const_int 0)) and return 1. This replacement is useful because
11468 we often can get useful information about the form of a value (e.g., if
11469 it was produced by a shift that always produces -1 or 0) even though
11470 we don't know exactly what registers it was produced from. */
11473 get_last_value_validate (loc, insn, tick, replace)
11480 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11481 int len = GET_RTX_LENGTH (GET_CODE (x));
11484 if (GET_CODE (x) == REG)
11486 unsigned int regno = REGNO (x);
11487 unsigned int endregno
11488 = regno + (regno < FIRST_PSEUDO_REGISTER
11489 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11492 for (j = regno; j < endregno; j++)
11493 if (reg_last_set_invalid[j]
11494 /* If this is a pseudo-register that was only set once and not
11495 live at the beginning of the function, it is always valid. */
11496 || (! (regno >= FIRST_PSEUDO_REGISTER
11497 && REG_N_SETS (regno) == 1
11498 && (! REGNO_REG_SET_P
11499 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11500 && reg_last_set_label[j] > tick))
11503 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11509 /* If this is a memory reference, make sure that there were
11510 no stores after it that might have clobbered the value. We don't
11511 have alias info, so we assume any store invalidates it. */
11512 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11513 && INSN_CUID (insn) <= mem_last_set)
11516 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11520 for (i = 0; i < len; i++)
11522 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11523 /* Don't bother with these. They shouldn't occur anyway. */
11527 /* If we haven't found a reason for it to be invalid, it is valid. */
11531 /* Get the last value assigned to X, if known. Some registers
11532 in the value may be replaced with (clobber (const_int 0)) if their value
11533 is known longer known reliably. */
11539 unsigned int regno;
11542 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11543 then convert it to the desired mode. If this is a paradoxical SUBREG,
11544 we cannot predict what values the "extra" bits might have. */
11545 if (GET_CODE (x) == SUBREG
11546 && subreg_lowpart_p (x)
11547 && (GET_MODE_SIZE (GET_MODE (x))
11548 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11549 && (value = get_last_value (SUBREG_REG (x))) != 0)
11550 return gen_lowpart_for_combine (GET_MODE (x), value);
11552 if (GET_CODE (x) != REG)
11556 value = reg_last_set_value[regno];
11558 /* If we don't have a value, or if it isn't for this basic block and
11559 it's either a hard register, set more than once, or it's a live
11560 at the beginning of the function, return 0.
11562 Because if it's not live at the beginning of the function then the reg
11563 is always set before being used (is never used without being set).
11564 And, if it's set only once, and it's always set before use, then all
11565 uses must have the same last value, even if it's not from this basic
11569 || (reg_last_set_label[regno] != label_tick
11570 && (regno < FIRST_PSEUDO_REGISTER
11571 || REG_N_SETS (regno) != 1
11572 || (REGNO_REG_SET_P
11573 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11576 /* If the value was set in a later insn than the ones we are processing,
11577 we can't use it even if the register was only set once. */
11578 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11581 /* If the value has all its registers valid, return it. */
11582 if (get_last_value_validate (&value, reg_last_set[regno],
11583 reg_last_set_label[regno], 0))
11586 /* Otherwise, make a copy and replace any invalid register with
11587 (clobber (const_int 0)). If that fails for some reason, return 0. */
11589 value = copy_rtx (value);
11590 if (get_last_value_validate (&value, reg_last_set[regno],
11591 reg_last_set_label[regno], 1))
11597 /* Return nonzero if expression X refers to a REG or to memory
11598 that is set in an instruction more recent than FROM_CUID. */
11601 use_crosses_set_p (x, from_cuid)
11607 enum rtx_code code = GET_CODE (x);
11611 unsigned int regno = REGNO (x);
11612 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11613 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11615 #ifdef PUSH_ROUNDING
11616 /* Don't allow uses of the stack pointer to be moved,
11617 because we don't know whether the move crosses a push insn. */
11618 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11621 for (; regno < endreg; regno++)
11622 if (reg_last_set[regno]
11623 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11628 if (code == MEM && mem_last_set > from_cuid)
11631 fmt = GET_RTX_FORMAT (code);
11633 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11638 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11639 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11642 else if (fmt[i] == 'e'
11643 && use_crosses_set_p (XEXP (x, i), from_cuid))
11649 /* Define three variables used for communication between the following
11652 static unsigned int reg_dead_regno, reg_dead_endregno;
11653 static int reg_dead_flag;
11655 /* Function called via note_stores from reg_dead_at_p.
11657 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11658 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11661 reg_dead_at_p_1 (dest, x, data)
11664 void *data ATTRIBUTE_UNUSED;
11666 unsigned int regno, endregno;
11668 if (GET_CODE (dest) != REG)
11671 regno = REGNO (dest);
11672 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11673 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11675 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11676 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11679 /* Return non-zero if REG is known to be dead at INSN.
11681 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11682 referencing REG, it is dead. If we hit a SET referencing REG, it is
11683 live. Otherwise, see if it is live or dead at the start of the basic
11684 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11685 must be assumed to be always live. */
11688 reg_dead_at_p (reg, insn)
11695 /* Set variables for reg_dead_at_p_1. */
11696 reg_dead_regno = REGNO (reg);
11697 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11698 ? HARD_REGNO_NREGS (reg_dead_regno,
11704 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11705 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11707 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11708 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11712 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11713 beginning of function. */
11714 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11715 insn = prev_nonnote_insn (insn))
11717 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11719 return reg_dead_flag == 1 ? 1 : 0;
11721 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11725 /* Get the basic block that we were in. */
11727 block = ENTRY_BLOCK_PTR->next_bb;
11730 FOR_EACH_BB (block)
11731 if (insn == block->head)
11734 if (block == EXIT_BLOCK_PTR)
11738 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11739 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11745 /* Note hard registers in X that are used. This code is similar to
11746 that in flow.c, but much simpler since we don't care about pseudos. */
11749 mark_used_regs_combine (x)
11752 RTX_CODE code = GET_CODE (x);
11753 unsigned int regno;
11766 case ADDR_DIFF_VEC:
11769 /* CC0 must die in the insn after it is set, so we don't need to take
11770 special note of it here. */
11776 /* If we are clobbering a MEM, mark any hard registers inside the
11777 address as used. */
11778 if (GET_CODE (XEXP (x, 0)) == MEM)
11779 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11784 /* A hard reg in a wide mode may really be multiple registers.
11785 If so, mark all of them just like the first. */
11786 if (regno < FIRST_PSEUDO_REGISTER)
11788 unsigned int endregno, r;
11790 /* None of this applies to the stack, frame or arg pointers */
11791 if (regno == STACK_POINTER_REGNUM
11792 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11793 || regno == HARD_FRAME_POINTER_REGNUM
11795 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11796 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11798 || regno == FRAME_POINTER_REGNUM)
11801 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11802 for (r = regno; r < endregno; r++)
11803 SET_HARD_REG_BIT (newpat_used_regs, r);
11809 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11811 rtx testreg = SET_DEST (x);
11813 while (GET_CODE (testreg) == SUBREG
11814 || GET_CODE (testreg) == ZERO_EXTRACT
11815 || GET_CODE (testreg) == SIGN_EXTRACT
11816 || GET_CODE (testreg) == STRICT_LOW_PART)
11817 testreg = XEXP (testreg, 0);
11819 if (GET_CODE (testreg) == MEM)
11820 mark_used_regs_combine (XEXP (testreg, 0));
11822 mark_used_regs_combine (SET_SRC (x));
11830 /* Recursively scan the operands of this expression. */
11833 const char *fmt = GET_RTX_FORMAT (code);
11835 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11838 mark_used_regs_combine (XEXP (x, i));
11839 else if (fmt[i] == 'E')
11843 for (j = 0; j < XVECLEN (x, i); j++)
11844 mark_used_regs_combine (XVECEXP (x, i, j));
11850 /* Remove register number REGNO from the dead registers list of INSN.
11852 Return the note used to record the death, if there was one. */
11855 remove_death (regno, insn)
11856 unsigned int regno;
11859 rtx note = find_regno_note (insn, REG_DEAD, regno);
11863 REG_N_DEATHS (regno)--;
11864 remove_note (insn, note);
11870 /* For each register (hardware or pseudo) used within expression X, if its
11871 death is in an instruction with cuid between FROM_CUID (inclusive) and
11872 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11873 list headed by PNOTES.
11875 That said, don't move registers killed by maybe_kill_insn.
11877 This is done when X is being merged by combination into TO_INSN. These
11878 notes will then be distributed as needed. */
11881 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11883 rtx maybe_kill_insn;
11890 enum rtx_code code = GET_CODE (x);
11894 unsigned int regno = REGNO (x);
11895 rtx where_dead = reg_last_death[regno];
11896 rtx before_dead, after_dead;
11898 /* Don't move the register if it gets killed in between from and to */
11899 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11900 && ! reg_referenced_p (x, maybe_kill_insn))
11903 /* WHERE_DEAD could be a USE insn made by combine, so first we
11904 make sure that we have insns with valid INSN_CUID values. */
11905 before_dead = where_dead;
11906 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11907 before_dead = PREV_INSN (before_dead);
11909 after_dead = where_dead;
11910 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11911 after_dead = NEXT_INSN (after_dead);
11913 if (before_dead && after_dead
11914 && INSN_CUID (before_dead) >= from_cuid
11915 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11916 || (where_dead != after_dead
11917 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11919 rtx note = remove_death (regno, where_dead);
11921 /* It is possible for the call above to return 0. This can occur
11922 when reg_last_death points to I2 or I1 that we combined with.
11923 In that case make a new note.
11925 We must also check for the case where X is a hard register
11926 and NOTE is a death note for a range of hard registers
11927 including X. In that case, we must put REG_DEAD notes for
11928 the remaining registers in place of NOTE. */
11930 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11931 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11932 > GET_MODE_SIZE (GET_MODE (x))))
11934 unsigned int deadregno = REGNO (XEXP (note, 0));
11935 unsigned int deadend
11936 = (deadregno + HARD_REGNO_NREGS (deadregno,
11937 GET_MODE (XEXP (note, 0))));
11938 unsigned int ourend
11939 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11942 for (i = deadregno; i < deadend; i++)
11943 if (i < regno || i >= ourend)
11944 REG_NOTES (where_dead)
11945 = gen_rtx_EXPR_LIST (REG_DEAD,
11947 REG_NOTES (where_dead));
11950 /* If we didn't find any note, or if we found a REG_DEAD note that
11951 covers only part of the given reg, and we have a multi-reg hard
11952 register, then to be safe we must check for REG_DEAD notes
11953 for each register other than the first. They could have
11954 their own REG_DEAD notes lying around. */
11955 else if ((note == 0
11957 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11958 < GET_MODE_SIZE (GET_MODE (x)))))
11959 && regno < FIRST_PSEUDO_REGISTER
11960 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11962 unsigned int ourend
11963 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11964 unsigned int i, offset;
11968 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11972 for (i = regno + offset; i < ourend; i++)
11973 move_deaths (regno_reg_rtx[i],
11974 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11977 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11979 XEXP (note, 1) = *pnotes;
11983 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11985 REG_N_DEATHS (regno)++;
11991 else if (GET_CODE (x) == SET)
11993 rtx dest = SET_DEST (x);
11995 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11997 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11998 that accesses one word of a multi-word item, some
11999 piece of everything register in the expression is used by
12000 this insn, so remove any old death. */
12001 /* ??? So why do we test for equality of the sizes? */
12003 if (GET_CODE (dest) == ZERO_EXTRACT
12004 || GET_CODE (dest) == STRICT_LOW_PART
12005 || (GET_CODE (dest) == SUBREG
12006 && (((GET_MODE_SIZE (GET_MODE (dest))
12007 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12008 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12009 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12011 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12015 /* If this is some other SUBREG, we know it replaces the entire
12016 value, so use that as the destination. */
12017 if (GET_CODE (dest) == SUBREG)
12018 dest = SUBREG_REG (dest);
12020 /* If this is a MEM, adjust deaths of anything used in the address.
12021 For a REG (the only other possibility), the entire value is
12022 being replaced so the old value is not used in this insn. */
12024 if (GET_CODE (dest) == MEM)
12025 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12030 else if (GET_CODE (x) == CLOBBER)
12033 len = GET_RTX_LENGTH (code);
12034 fmt = GET_RTX_FORMAT (code);
12036 for (i = 0; i < len; i++)
12041 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12042 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12045 else if (fmt[i] == 'e')
12046 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12050 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12051 pattern of an insn. X must be a REG. */
12054 reg_bitfield_target_p (x, body)
12060 if (GET_CODE (body) == SET)
12062 rtx dest = SET_DEST (body);
12064 unsigned int regno, tregno, endregno, endtregno;
12066 if (GET_CODE (dest) == ZERO_EXTRACT)
12067 target = XEXP (dest, 0);
12068 else if (GET_CODE (dest) == STRICT_LOW_PART)
12069 target = SUBREG_REG (XEXP (dest, 0));
12073 if (GET_CODE (target) == SUBREG)
12074 target = SUBREG_REG (target);
12076 if (GET_CODE (target) != REG)
12079 tregno = REGNO (target), regno = REGNO (x);
12080 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12081 return target == x;
12083 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12084 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12086 return endregno > tregno && regno < endtregno;
12089 else if (GET_CODE (body) == PARALLEL)
12090 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12091 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12097 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12098 as appropriate. I3 and I2 are the insns resulting from the combination
12099 insns including FROM (I2 may be zero).
12101 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12102 not need REG_DEAD notes because they are being substituted for. This
12103 saves searching in the most common cases.
12105 Each note in the list is either ignored or placed on some insns, depending
12106 on the type of note. */
12109 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12113 rtx elim_i2, elim_i1;
12115 rtx note, next_note;
12118 for (note = notes; note; note = next_note)
12120 rtx place = 0, place2 = 0;
12122 /* If this NOTE references a pseudo register, ensure it references
12123 the latest copy of that register. */
12124 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12125 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12126 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12128 next_note = XEXP (note, 1);
12129 switch (REG_NOTE_KIND (note))
12133 case REG_EXEC_COUNT:
12134 /* Doesn't matter much where we put this, as long as it's somewhere.
12135 It is preferable to keep these notes on branches, which is most
12136 likely to be i3. */
12140 case REG_VTABLE_REF:
12141 /* ??? Should remain with *a particular* memory load. Given the
12142 nature of vtable data, the last insn seems relatively safe. */
12146 case REG_NON_LOCAL_GOTO:
12147 if (GET_CODE (i3) == JUMP_INSN)
12149 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12155 case REG_EH_REGION:
12156 /* These notes must remain with the call or trapping instruction. */
12157 if (GET_CODE (i3) == CALL_INSN)
12159 else if (i2 && GET_CODE (i2) == CALL_INSN)
12161 else if (flag_non_call_exceptions)
12163 if (may_trap_p (i3))
12165 else if (i2 && may_trap_p (i2))
12167 /* ??? Otherwise assume we've combined things such that we
12168 can now prove that the instructions can't trap. Drop the
12169 note in this case. */
12177 /* These notes must remain with the call. It should not be
12178 possible for both I2 and I3 to be a call. */
12179 if (GET_CODE (i3) == CALL_INSN)
12181 else if (i2 && GET_CODE (i2) == CALL_INSN)
12188 /* Any clobbers for i3 may still exist, and so we must process
12189 REG_UNUSED notes from that insn.
12191 Any clobbers from i2 or i1 can only exist if they were added by
12192 recog_for_combine. In that case, recog_for_combine created the
12193 necessary REG_UNUSED notes. Trying to keep any original
12194 REG_UNUSED notes from these insns can cause incorrect output
12195 if it is for the same register as the original i3 dest.
12196 In that case, we will notice that the register is set in i3,
12197 and then add a REG_UNUSED note for the destination of i3, which
12198 is wrong. However, it is possible to have REG_UNUSED notes from
12199 i2 or i1 for register which were both used and clobbered, so
12200 we keep notes from i2 or i1 if they will turn into REG_DEAD
12203 /* If this register is set or clobbered in I3, put the note there
12204 unless there is one already. */
12205 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12207 if (from_insn != i3)
12210 if (! (GET_CODE (XEXP (note, 0)) == REG
12211 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12212 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12215 /* Otherwise, if this register is used by I3, then this register
12216 now dies here, so we must put a REG_DEAD note here unless there
12218 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12219 && ! (GET_CODE (XEXP (note, 0)) == REG
12220 ? find_regno_note (i3, REG_DEAD,
12221 REGNO (XEXP (note, 0)))
12222 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12224 PUT_REG_NOTE_KIND (note, REG_DEAD);
12232 /* These notes say something about results of an insn. We can
12233 only support them if they used to be on I3 in which case they
12234 remain on I3. Otherwise they are ignored.
12236 If the note refers to an expression that is not a constant, we
12237 must also ignore the note since we cannot tell whether the
12238 equivalence is still true. It might be possible to do
12239 slightly better than this (we only have a problem if I2DEST
12240 or I1DEST is present in the expression), but it doesn't
12241 seem worth the trouble. */
12243 if (from_insn == i3
12244 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12249 case REG_NO_CONFLICT:
12250 /* These notes say something about how a register is used. They must
12251 be present on any use of the register in I2 or I3. */
12252 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12255 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12265 /* This can show up in several ways -- either directly in the
12266 pattern, or hidden off in the constant pool with (or without?)
12267 a REG_EQUAL note. */
12268 /* ??? Ignore the without-reg_equal-note problem for now. */
12269 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12270 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12271 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12272 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12276 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12277 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12278 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12279 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12287 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12288 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12289 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12291 if (JUMP_LABEL (place) != XEXP (note, 0))
12293 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12294 LABEL_NUSES (JUMP_LABEL (place))--;
12297 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12299 if (JUMP_LABEL (place2) != XEXP (note, 0))
12301 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12302 LABEL_NUSES (JUMP_LABEL (place2))--;
12309 /* These notes say something about the value of a register prior
12310 to the execution of an insn. It is too much trouble to see
12311 if the note is still correct in all situations. It is better
12312 to simply delete it. */
12316 /* If the insn previously containing this note still exists,
12317 put it back where it was. Otherwise move it to the previous
12318 insn. Adjust the corresponding REG_LIBCALL note. */
12319 if (GET_CODE (from_insn) != NOTE)
12323 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12324 place = prev_real_insn (from_insn);
12326 XEXP (tem, 0) = place;
12327 /* If we're deleting the last remaining instruction of a
12328 libcall sequence, don't add the notes. */
12329 else if (XEXP (note, 0) == from_insn)
12335 /* This is handled similarly to REG_RETVAL. */
12336 if (GET_CODE (from_insn) != NOTE)
12340 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12341 place = next_real_insn (from_insn);
12343 XEXP (tem, 0) = place;
12344 /* If we're deleting the last remaining instruction of a
12345 libcall sequence, don't add the notes. */
12346 else if (XEXP (note, 0) == from_insn)
12352 /* If the register is used as an input in I3, it dies there.
12353 Similarly for I2, if it is non-zero and adjacent to I3.
12355 If the register is not used as an input in either I3 or I2
12356 and it is not one of the registers we were supposed to eliminate,
12357 there are two possibilities. We might have a non-adjacent I2
12358 or we might have somehow eliminated an additional register
12359 from a computation. For example, we might have had A & B where
12360 we discover that B will always be zero. In this case we will
12361 eliminate the reference to A.
12363 In both cases, we must search to see if we can find a previous
12364 use of A and put the death note there. */
12367 && GET_CODE (from_insn) == CALL_INSN
12368 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12370 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12372 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12373 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12376 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12377 || rtx_equal_p (XEXP (note, 0), elim_i1))
12382 basic_block bb = this_basic_block;
12384 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12386 if (! INSN_P (tem))
12388 if (tem == bb->head)
12393 /* If the register is being set at TEM, see if that is all
12394 TEM is doing. If so, delete TEM. Otherwise, make this
12395 into a REG_UNUSED note instead. */
12396 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12398 rtx set = single_set (tem);
12399 rtx inner_dest = 0;
12401 rtx cc0_setter = NULL_RTX;
12405 for (inner_dest = SET_DEST (set);
12406 (GET_CODE (inner_dest) == STRICT_LOW_PART
12407 || GET_CODE (inner_dest) == SUBREG
12408 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12409 inner_dest = XEXP (inner_dest, 0))
12412 /* Verify that it was the set, and not a clobber that
12413 modified the register.
12415 CC0 targets must be careful to maintain setter/user
12416 pairs. If we cannot delete the setter due to side
12417 effects, mark the user with an UNUSED note instead
12420 if (set != 0 && ! side_effects_p (SET_SRC (set))
12421 && rtx_equal_p (XEXP (note, 0), inner_dest)
12423 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12424 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12425 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12429 /* Move the notes and links of TEM elsewhere.
12430 This might delete other dead insns recursively.
12431 First set the pattern to something that won't use
12434 PATTERN (tem) = pc_rtx;
12436 distribute_notes (REG_NOTES (tem), tem, tem,
12437 NULL_RTX, NULL_RTX, NULL_RTX);
12438 distribute_links (LOG_LINKS (tem));
12440 PUT_CODE (tem, NOTE);
12441 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12442 NOTE_SOURCE_FILE (tem) = 0;
12445 /* Delete the setter too. */
12448 PATTERN (cc0_setter) = pc_rtx;
12450 distribute_notes (REG_NOTES (cc0_setter),
12451 cc0_setter, cc0_setter,
12452 NULL_RTX, NULL_RTX, NULL_RTX);
12453 distribute_links (LOG_LINKS (cc0_setter));
12455 PUT_CODE (cc0_setter, NOTE);
12456 NOTE_LINE_NUMBER (cc0_setter)
12457 = NOTE_INSN_DELETED;
12458 NOTE_SOURCE_FILE (cc0_setter) = 0;
12462 /* If the register is both set and used here, put the
12463 REG_DEAD note here, but place a REG_UNUSED note
12464 here too unless there already is one. */
12465 else if (reg_referenced_p (XEXP (note, 0),
12470 if (! find_regno_note (tem, REG_UNUSED,
12471 REGNO (XEXP (note, 0))))
12473 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12478 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12480 /* If there isn't already a REG_UNUSED note, put one
12482 if (! find_regno_note (tem, REG_UNUSED,
12483 REGNO (XEXP (note, 0))))
12488 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12489 || (GET_CODE (tem) == CALL_INSN
12490 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12494 /* If we are doing a 3->2 combination, and we have a
12495 register which formerly died in i3 and was not used
12496 by i2, which now no longer dies in i3 and is used in
12497 i2 but does not die in i2, and place is between i2
12498 and i3, then we may need to move a link from place to
12500 if (i2 && INSN_UID (place) <= max_uid_cuid
12501 && INSN_CUID (place) > INSN_CUID (i2)
12503 && INSN_CUID (from_insn) > INSN_CUID (i2)
12504 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12506 rtx links = LOG_LINKS (place);
12507 LOG_LINKS (place) = 0;
12508 distribute_links (links);
12513 if (tem == bb->head)
12517 /* We haven't found an insn for the death note and it
12518 is still a REG_DEAD note, but we have hit the beginning
12519 of the block. If the existing life info says the reg
12520 was dead, there's nothing left to do. Otherwise, we'll
12521 need to do a global life update after combine. */
12522 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12523 && REGNO_REG_SET_P (bb->global_live_at_start,
12524 REGNO (XEXP (note, 0))))
12526 SET_BIT (refresh_blocks, this_basic_block->index);
12531 /* If the register is set or already dead at PLACE, we needn't do
12532 anything with this note if it is still a REG_DEAD note.
12533 We can here if it is set at all, not if is it totally replace,
12534 which is what `dead_or_set_p' checks, so also check for it being
12537 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12539 unsigned int regno = REGNO (XEXP (note, 0));
12541 /* Similarly, if the instruction on which we want to place
12542 the note is a noop, we'll need do a global live update
12543 after we remove them in delete_noop_moves. */
12544 if (noop_move_p (place))
12546 SET_BIT (refresh_blocks, this_basic_block->index);
12550 if (dead_or_set_p (place, XEXP (note, 0))
12551 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12553 /* Unless the register previously died in PLACE, clear
12554 reg_last_death. [I no longer understand why this is
12556 if (reg_last_death[regno] != place)
12557 reg_last_death[regno] = 0;
12561 reg_last_death[regno] = place;
12563 /* If this is a death note for a hard reg that is occupying
12564 multiple registers, ensure that we are still using all
12565 parts of the object. If we find a piece of the object
12566 that is unused, we must arrange for an appropriate REG_DEAD
12567 note to be added for it. However, we can't just emit a USE
12568 and tag the note to it, since the register might actually
12569 be dead; so we recourse, and the recursive call then finds
12570 the previous insn that used this register. */
12572 if (place && regno < FIRST_PSEUDO_REGISTER
12573 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12575 unsigned int endregno
12576 = regno + HARD_REGNO_NREGS (regno,
12577 GET_MODE (XEXP (note, 0)));
12581 for (i = regno; i < endregno; i++)
12582 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12583 && ! find_regno_fusage (place, USE, i))
12584 || dead_or_set_regno_p (place, i))
12589 /* Put only REG_DEAD notes for pieces that are
12590 not already dead or set. */
12592 for (i = regno; i < endregno;
12593 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12595 rtx piece = regno_reg_rtx[i];
12596 basic_block bb = this_basic_block;
12598 if (! dead_or_set_p (place, piece)
12599 && ! reg_bitfield_target_p (piece,
12603 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12605 distribute_notes (new_note, place, place,
12606 NULL_RTX, NULL_RTX, NULL_RTX);
12608 else if (! refers_to_regno_p (i, i + 1,
12609 PATTERN (place), 0)
12610 && ! find_regno_fusage (place, USE, i))
12611 for (tem = PREV_INSN (place); ;
12612 tem = PREV_INSN (tem))
12614 if (! INSN_P (tem))
12616 if (tem == bb->head)
12618 SET_BIT (refresh_blocks,
12619 this_basic_block->index);
12625 if (dead_or_set_p (tem, piece)
12626 || reg_bitfield_target_p (piece,
12630 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12645 /* Any other notes should not be present at this point in the
12652 XEXP (note, 1) = REG_NOTES (place);
12653 REG_NOTES (place) = note;
12655 else if ((REG_NOTE_KIND (note) == REG_DEAD
12656 || REG_NOTE_KIND (note) == REG_UNUSED)
12657 && GET_CODE (XEXP (note, 0)) == REG)
12658 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12662 if ((REG_NOTE_KIND (note) == REG_DEAD
12663 || REG_NOTE_KIND (note) == REG_UNUSED)
12664 && GET_CODE (XEXP (note, 0)) == REG)
12665 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12667 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12668 REG_NOTE_KIND (note),
12670 REG_NOTES (place2));
12675 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12676 I3, I2, and I1 to new locations. This is also called in one case to
12677 add a link pointing at I3 when I3's destination is changed. */
12680 distribute_links (links)
12683 rtx link, next_link;
12685 for (link = links; link; link = next_link)
12691 next_link = XEXP (link, 1);
12693 /* If the insn that this link points to is a NOTE or isn't a single
12694 set, ignore it. In the latter case, it isn't clear what we
12695 can do other than ignore the link, since we can't tell which
12696 register it was for. Such links wouldn't be used by combine
12699 It is not possible for the destination of the target of the link to
12700 have been changed by combine. The only potential of this is if we
12701 replace I3, I2, and I1 by I3 and I2. But in that case the
12702 destination of I2 also remains unchanged. */
12704 if (GET_CODE (XEXP (link, 0)) == NOTE
12705 || (set = single_set (XEXP (link, 0))) == 0)
12708 reg = SET_DEST (set);
12709 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12710 || GET_CODE (reg) == SIGN_EXTRACT
12711 || GET_CODE (reg) == STRICT_LOW_PART)
12712 reg = XEXP (reg, 0);
12714 /* A LOG_LINK is defined as being placed on the first insn that uses
12715 a register and points to the insn that sets the register. Start
12716 searching at the next insn after the target of the link and stop
12717 when we reach a set of the register or the end of the basic block.
12719 Note that this correctly handles the link that used to point from
12720 I3 to I2. Also note that not much searching is typically done here
12721 since most links don't point very far away. */
12723 for (insn = NEXT_INSN (XEXP (link, 0));
12724 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12725 || this_basic_block->next_bb->head != insn));
12726 insn = NEXT_INSN (insn))
12727 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12729 if (reg_referenced_p (reg, PATTERN (insn)))
12733 else if (GET_CODE (insn) == CALL_INSN
12734 && find_reg_fusage (insn, USE, reg))
12740 /* If we found a place to put the link, place it there unless there
12741 is already a link to the same insn as LINK at that point. */
12747 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12748 if (XEXP (link2, 0) == XEXP (link, 0))
12753 XEXP (link, 1) = LOG_LINKS (place);
12754 LOG_LINKS (place) = link;
12756 /* Set added_links_insn to the earliest insn we added a
12758 if (added_links_insn == 0
12759 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12760 added_links_insn = place;
12766 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12772 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12773 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12774 insn = NEXT_INSN (insn);
12776 if (INSN_UID (insn) > max_uid_cuid)
12779 return INSN_CUID (insn);
12783 dump_combine_stats (file)
12788 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12789 combine_attempts, combine_merges, combine_extras, combine_successes);
12793 dump_combine_total_stats (file)
12798 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12799 total_attempts, total_merges, total_extras, total_successes);