1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
84 #include "hard-reg-set.h"
85 #include "basic-block.h"
86 #include "insn-config.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-flags.h"
91 #include "insn-codes.h"
92 #include "insn-attr.h"
98 #ifndef ACCUMULATE_OUTGOING_ARGS
99 #define ACCUMULATE_OUTGOING_ARGS 0
102 /* Supply a default definition for PUSH_ARGS. */
105 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
111 /* It is not safe to use ordinary gen_lowpart in combine.
112 Use gen_lowpart_for_combine instead. See comments there. */
113 #define gen_lowpart dont_use_gen_lowpart_you_dummy
115 /* Number of attempts to combine instructions in this function. */
117 static int combine_attempts;
119 /* Number of attempts that got as far as substitution in this function. */
121 static int combine_merges;
123 /* Number of instructions combined with added SETs in this function. */
125 static int combine_extras;
127 /* Number of instructions combined in this function. */
129 static int combine_successes;
131 /* Totals over entire compilation. */
133 static int total_attempts, total_merges, total_extras, total_successes;
135 /* Define a default value for REVERSIBLE_CC_MODE.
136 We can never assume that a condition code mode is safe to reverse unless
137 the md tells us so. */
138 #ifndef REVERSIBLE_CC_MODE
139 #define REVERSIBLE_CC_MODE(MODE) 0
142 /* Vector mapping INSN_UIDs to cuids.
143 The cuids are like uids but increase monotonically always.
144 Combine always uses cuids so that it can compare them.
145 But actually renumbering the uids, which we used to do,
146 proves to be a bad idea because it makes it hard to compare
147 the dumps produced by earlier passes with those from later passes. */
149 static int *uid_cuid;
150 static int max_uid_cuid;
152 /* Get the cuid of an insn. */
154 #define INSN_CUID(INSN) \
155 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
157 /* Maximum register number, which is the size of the tables below. */
159 static unsigned int combine_max_regno;
161 /* Record last point of death of (hard or pseudo) register n. */
163 static rtx *reg_last_death;
165 /* Record last point of modification of (hard or pseudo) register n. */
167 static rtx *reg_last_set;
169 /* Record the cuid of the last insn that invalidated memory
170 (anything that writes memory, and subroutine calls, but not pushes). */
172 static int mem_last_set;
174 /* Record the cuid of the last CALL_INSN
175 so we can tell whether a potential combination crosses any calls. */
177 static int last_call_cuid;
179 /* When `subst' is called, this is the insn that is being modified
180 (by combining in a previous insn). The PATTERN of this insn
181 is still the old pattern partially modified and it should not be
182 looked at, but this may be used to examine the successors of the insn
183 to judge whether a simplification is valid. */
185 static rtx subst_insn;
187 /* This is an insn that belongs before subst_insn, but is not currently
188 on the insn chain. */
190 static rtx subst_prev_insn;
192 /* This is the lowest CUID that `subst' is currently dealing with.
193 get_last_value will not return a value if the register was set at or
194 after this CUID. If not for this mechanism, we could get confused if
195 I2 or I1 in try_combine were an insn that used the old value of a register
196 to obtain a new value. In that case, we might erroneously get the
197 new value of the register when we wanted the old one. */
199 static int subst_low_cuid;
201 /* This contains any hard registers that are used in newpat; reg_dead_at_p
202 must consider all these registers to be always live. */
204 static HARD_REG_SET newpat_used_regs;
206 /* This is an insn to which a LOG_LINKS entry has been added. If this
207 insn is the earlier than I2 or I3, combine should rescan starting at
210 static rtx added_links_insn;
212 /* Basic block number of the block in which we are performing combines. */
213 static int this_basic_block;
215 /* A bitmap indicating which blocks had registers go dead at entry.
216 After combine, we'll need to re-do global life analysis with
217 those blocks as starting points. */
218 static sbitmap refresh_blocks;
219 static int need_refresh;
221 /* The next group of arrays allows the recording of the last value assigned
222 to (hard or pseudo) register n. We use this information to see if a
223 operation being processed is redundant given a prior operation performed
224 on the register. For example, an `and' with a constant is redundant if
225 all the zero bits are already known to be turned off.
227 We use an approach similar to that used by cse, but change it in the
230 (1) We do not want to reinitialize at each label.
231 (2) It is useful, but not critical, to know the actual value assigned
232 to a register. Often just its form is helpful.
234 Therefore, we maintain the following arrays:
236 reg_last_set_value the last value assigned
237 reg_last_set_label records the value of label_tick when the
238 register was assigned
239 reg_last_set_table_tick records the value of label_tick when a
240 value using the register is assigned
241 reg_last_set_invalid set to non-zero when it is not valid
242 to use the value of this register in some
245 To understand the usage of these tables, it is important to understand
246 the distinction between the value in reg_last_set_value being valid
247 and the register being validly contained in some other expression in the
250 Entry I in reg_last_set_value is valid if it is non-zero, and either
251 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
253 Register I may validly appear in any expression returned for the value
254 of another register if reg_n_sets[i] is 1. It may also appear in the
255 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
256 reg_last_set_invalid[j] is zero.
258 If an expression is found in the table containing a register which may
259 not validly appear in an expression, the register is replaced by
260 something that won't match, (clobber (const_int 0)).
262 reg_last_set_invalid[i] is set non-zero when register I is being assigned
263 to and reg_last_set_table_tick[i] == label_tick. */
265 /* Record last value assigned to (hard or pseudo) register n. */
267 static rtx *reg_last_set_value;
269 /* Record the value of label_tick when the value for register n is placed in
270 reg_last_set_value[n]. */
272 static int *reg_last_set_label;
274 /* Record the value of label_tick when an expression involving register n
275 is placed in reg_last_set_value. */
277 static int *reg_last_set_table_tick;
279 /* Set non-zero if references to register n in expressions should not be
282 static char *reg_last_set_invalid;
284 /* Incremented for each label. */
286 static int label_tick;
288 /* Some registers that are set more than once and used in more than one
289 basic block are nevertheless always set in similar ways. For example,
290 a QImode register may be loaded from memory in two places on a machine
291 where byte loads zero extend.
293 We record in the following array what we know about the nonzero
294 bits of a register, specifically which bits are known to be zero.
296 If an entry is zero, it means that we don't know anything special. */
298 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
300 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
301 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero if we know that a register has some leading bits that are always
306 equal to the sign bit. */
308 static unsigned char *reg_sign_bit_copies;
310 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
311 It is zero while computing them and after combine has completed. This
312 former test prevents propagating values based on previously set values,
313 which can be incorrect if a variable is modified in a loop. */
315 static int nonzero_sign_valid;
317 /* These arrays are maintained in parallel with reg_last_set_value
318 and are used to store the mode in which the register was last set,
319 the bits that were known to be zero when it was last set, and the
320 number of sign bits copies it was known to have when it was last set. */
322 static enum machine_mode *reg_last_set_mode;
323 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
324 static char *reg_last_set_sign_bit_copies;
326 /* Record one modification to rtl structure
327 to be undone by storing old_contents into *where.
328 is_int is 1 if the contents are an int. */
334 union {rtx r; int i;} old_contents;
335 union {rtx *r; int *i;} where;
338 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
339 num_undo says how many are currently recorded.
341 storage is nonzero if we must undo the allocation of new storage.
342 The value of storage is what to pass to obfree.
344 other_insn is nonzero if we have modified some other insn in the process
345 of working on subst_insn. It must be verified too.
347 previous_undos is the value of undobuf.undos when we started processing
348 this substitution. This will prevent gen_rtx_combine from re-used a piece
349 from the previous expression. Doing so can produce circular rtl
357 struct undo *previous_undos;
361 static struct undobuf undobuf;
363 /* Number of times the pseudo being substituted for
364 was found and replaced. */
366 static int n_occurrences;
368 static void do_SUBST PARAMS ((rtx *, rtx));
369 static void do_SUBST_INT PARAMS ((int *, int));
370 static void init_reg_last_arrays PARAMS ((void));
371 static void setup_incoming_promotions PARAMS ((void));
372 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
373 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
374 static int sets_function_arg_p PARAMS ((rtx));
375 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
376 static int contains_muldiv PARAMS ((rtx));
377 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
378 static void undo_all PARAMS ((void));
379 static void undo_commit PARAMS ((void));
380 static rtx *find_split_point PARAMS ((rtx *, rtx));
381 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
382 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
383 static rtx simplify_if_then_else PARAMS ((rtx));
384 static rtx simplify_set PARAMS ((rtx));
385 static rtx simplify_logical PARAMS ((rtx, int));
386 static rtx expand_compound_operation PARAMS ((rtx));
387 static rtx expand_field_assignment PARAMS ((rtx));
388 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
389 rtx, unsigned HOST_WIDE_INT, int,
391 static rtx extract_left_shift PARAMS ((rtx, int));
392 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
393 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
394 unsigned HOST_WIDE_INT *));
395 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
396 unsigned HOST_WIDE_INT, rtx, int));
397 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
398 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
399 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
400 static rtx make_field_assignment PARAMS ((rtx));
401 static rtx apply_distributive_law PARAMS ((rtx));
402 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
403 unsigned HOST_WIDE_INT));
404 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
405 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
406 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
407 enum rtx_code, HOST_WIDE_INT,
408 enum machine_mode, int *));
409 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
411 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
412 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
413 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
415 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
417 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
418 enum machine_mode, rtx));
419 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
420 static int reversible_comparison_p PARAMS ((rtx));
421 static void update_table_tick PARAMS ((rtx));
422 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
423 static void check_promoted_subreg PARAMS ((rtx, rtx));
424 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
425 static void record_dead_and_set_regs PARAMS ((rtx));
426 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
427 static rtx get_last_value PARAMS ((rtx));
428 static int use_crosses_set_p PARAMS ((rtx, int));
429 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
430 static int reg_dead_at_p PARAMS ((rtx, rtx));
431 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
432 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
433 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
434 static void distribute_links PARAMS ((rtx));
435 static void mark_used_regs_combine PARAMS ((rtx));
436 static int insn_cuid PARAMS ((rtx));
437 static void record_promoted_value PARAMS ((rtx, rtx));
439 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
440 insn. The substitution can be undone by undo_all. If INTO is already
441 set to NEWVAL, do not record this change. Because computing NEWVAL might
442 also call SUBST, we have to compute it before we put anything into
446 do_SUBST(into, newval)
452 if (oldval == newval)
456 buf = undobuf.frees, undobuf.frees = buf->next;
458 buf = (struct undo *) xmalloc (sizeof (struct undo));
462 buf->old_contents.r = oldval;
465 buf->next = undobuf.undos, undobuf.undos = buf;
468 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
470 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
471 for the value of a HOST_WIDE_INT value (including CONST_INT) is
475 do_SUBST_INT(into, newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return non-zero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (f, nregs)
509 register rtx insn, next;
514 register rtx links, nextlinks;
516 int new_direct_jump_p = 0;
518 combine_attempts = 0;
521 combine_successes = 0;
523 combine_max_regno = nregs;
525 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
526 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
528 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
530 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
533 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
535 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
537 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits
539 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
540 reg_last_set_sign_bit_copies
541 = (char *) xmalloc (nregs * sizeof (char));
543 init_reg_last_arrays ();
545 init_recog_no_volatile ();
547 /* Compute maximum uid value so uid_cuid can be allocated. */
549 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
550 if (INSN_UID (insn) > i)
553 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
556 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
558 /* Don't use reg_nonzero_bits when computing it. This can cause problems
559 when, for example, we have j <<= 1 in a loop. */
561 nonzero_sign_valid = 0;
563 /* Compute the mapping from uids to cuids.
564 Cuids are numbers assigned to insns, like uids,
565 except that cuids increase monotonically through the code.
567 Scan all SETs and see if we can deduce anything about what
568 bits are known to be zero for some registers and how many copies
569 of the sign bit are known to exist for those registers.
571 Also set any known values so that we can use it while searching
572 for what bits are known to be set. */
576 /* We need to initialize it here, because record_dead_and_set_regs may call
578 subst_prev_insn = NULL_RTX;
580 setup_incoming_promotions ();
582 refresh_blocks = sbitmap_alloc (n_basic_blocks);
583 sbitmap_zero (refresh_blocks);
586 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
588 uid_cuid[INSN_UID (insn)] = ++i;
592 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
594 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
596 record_dead_and_set_regs (insn);
599 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
600 if (REG_NOTE_KIND (links) == REG_INC)
601 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
606 if (GET_CODE (insn) == CODE_LABEL)
610 nonzero_sign_valid = 1;
612 /* Now scan all the insns in forward order. */
614 this_basic_block = -1;
618 init_reg_last_arrays ();
619 setup_incoming_promotions ();
621 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
625 /* If INSN starts a new basic block, update our basic block number. */
626 if (this_basic_block + 1 < n_basic_blocks
627 && BLOCK_HEAD (this_basic_block + 1) == insn)
630 if (GET_CODE (insn) == CODE_LABEL)
633 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
635 /* See if we know about function return values before this
636 insn based upon SUBREG flags. */
637 check_promoted_subreg (insn, PATTERN (insn));
639 /* Try this insn with each insn it links back to. */
641 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
642 if ((next = try_combine (insn, XEXP (links, 0),
643 NULL_RTX, &new_direct_jump_p)) != 0)
646 /* Try each sequence of three linked insns ending with this one. */
648 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
650 rtx link = XEXP (links, 0);
652 /* If the linked insn has been replaced by a note, then there
653 is no point in persuing this chain any further. */
654 if (GET_CODE (link) == NOTE)
657 for (nextlinks = LOG_LINKS (link);
659 nextlinks = XEXP (nextlinks, 1))
660 if ((next = try_combine (insn, XEXP (links, 0),
662 &new_direct_jump_p)) != 0)
667 /* Try to combine a jump insn that uses CC0
668 with a preceding insn that sets CC0, and maybe with its
669 logical predecessor as well.
670 This is how we make decrement-and-branch insns.
671 We need this special code because data flow connections
672 via CC0 do not get entered in LOG_LINKS. */
674 if (GET_CODE (insn) == JUMP_INSN
675 && (prev = prev_nonnote_insn (insn)) != 0
676 && GET_CODE (prev) == INSN
677 && sets_cc0_p (PATTERN (prev)))
679 if ((next = try_combine (insn, prev,
680 NULL_RTX, &new_direct_jump_p)) != 0)
683 for (nextlinks = LOG_LINKS (prev); nextlinks;
684 nextlinks = XEXP (nextlinks, 1))
685 if ((next = try_combine (insn, prev,
687 &new_direct_jump_p)) != 0)
691 /* Do the same for an insn that explicitly references CC0. */
692 if (GET_CODE (insn) == INSN
693 && (prev = prev_nonnote_insn (insn)) != 0
694 && GET_CODE (prev) == INSN
695 && sets_cc0_p (PATTERN (prev))
696 && GET_CODE (PATTERN (insn)) == SET
697 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
699 if ((next = try_combine (insn, prev,
700 NULL_RTX, &new_direct_jump_p)) != 0)
703 for (nextlinks = LOG_LINKS (prev); nextlinks;
704 nextlinks = XEXP (nextlinks, 1))
705 if ((next = try_combine (insn, prev,
707 &new_direct_jump_p)) != 0)
711 /* Finally, see if any of the insns that this insn links to
712 explicitly references CC0. If so, try this insn, that insn,
713 and its predecessor if it sets CC0. */
714 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
715 if (GET_CODE (XEXP (links, 0)) == INSN
716 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
717 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
718 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
719 && GET_CODE (prev) == INSN
720 && sets_cc0_p (PATTERN (prev))
721 && (next = try_combine (insn, XEXP (links, 0),
722 prev, &new_direct_jump_p)) != 0)
726 /* Try combining an insn with two different insns whose results it
728 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
729 for (nextlinks = XEXP (links, 1); nextlinks;
730 nextlinks = XEXP (nextlinks, 1))
731 if ((next = try_combine (insn, XEXP (links, 0),
733 &new_direct_jump_p)) != 0)
736 if (GET_CODE (insn) != NOTE)
737 record_dead_and_set_regs (insn);
746 compute_bb_for_insn (get_max_uid ());
747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
797 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
798 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
799 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
800 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
801 bzero (reg_last_set_invalid, nregs * sizeof (char));
802 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
803 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
804 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 reg_nonzero_bits[REGNO (x)]
908 |= nonzero_bits (src, nonzero_bits_mode);
909 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
910 if (reg_sign_bit_copies[REGNO (x)] == 0
911 || reg_sign_bit_copies[REGNO (x)] > num)
912 reg_sign_bit_copies[REGNO (x)] = num;
916 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
917 reg_sign_bit_copies[REGNO (x)] = 1;
922 /* See if INSN can be combined into I3. PRED and SUCC are optionally
923 insns that were previously combined into I3 or that will be combined
924 into the merger of INSN and I3.
926 Return 0 if the combination is not allowed for any reason.
928 If the combination is allowed, *PDEST will be set to the single
929 destination of INSN and *PSRC to the single source, and this function
933 can_combine_p (insn, i3, pred, succ, pdest, psrc)
936 rtx pred ATTRIBUTE_UNUSED;
941 rtx set = 0, src, dest;
946 int all_adjacent = (succ ? (next_active_insn (insn) == succ
947 && next_active_insn (succ) == i3)
948 : next_active_insn (insn) == i3);
950 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
951 or a PARALLEL consisting of such a SET and CLOBBERs.
953 If INSN has CLOBBER parallel parts, ignore them for our processing.
954 By definition, these happen during the execution of the insn. When it
955 is merged with another insn, all bets are off. If they are, in fact,
956 needed and aren't also supplied in I3, they may be added by
957 recog_for_combine. Otherwise, it won't match.
959 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
962 Get the source and destination of INSN. If more than one, can't
965 if (GET_CODE (PATTERN (insn)) == SET)
966 set = PATTERN (insn);
967 else if (GET_CODE (PATTERN (insn)) == PARALLEL
968 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
972 rtx elt = XVECEXP (PATTERN (insn), 0, i);
974 switch (GET_CODE (elt))
976 /* This is important to combine floating point insns
979 /* Combining an isolated USE doesn't make sense.
980 We depend here on combinable_i3_pat to reject them. */
981 /* The code below this loop only verifies that the inputs of
982 the SET in INSN do not change. We call reg_set_between_p
983 to verify that the REG in the USE does not change betweeen
985 If the USE in INSN was for a pseudo register, the matching
986 insn pattern will likely match any register; combining this
987 with any other USE would only be safe if we knew that the
988 used registers have identical values, or if there was
989 something to tell them apart, e.g. different modes. For
990 now, we forgo such compilcated tests and simply disallow
991 combining of USES of pseudo registers with any other USE. */
992 if (GET_CODE (XEXP (elt, 0)) == REG
993 && GET_CODE (PATTERN (i3)) == PARALLEL)
995 rtx i3pat = PATTERN (i3);
996 int i = XVECLEN (i3pat, 0) - 1;
997 unsigned int regno = REGNO (XEXP (elt, 0));
1001 rtx i3elt = XVECEXP (i3pat, 0, i);
1003 if (GET_CODE (i3elt) == USE
1004 && GET_CODE (XEXP (i3elt, 0)) == REG
1005 && (REGNO (XEXP (i3elt, 0)) == regno
1006 ? reg_set_between_p (XEXP (elt, 0),
1007 PREV_INSN (insn), i3)
1008 : regno >= FIRST_PSEUDO_REGISTER))
1015 /* We can ignore CLOBBERs. */
1020 /* Ignore SETs whose result isn't used but not those that
1021 have side-effects. */
1022 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1023 && ! side_effects_p (elt))
1026 /* If we have already found a SET, this is a second one and
1027 so we cannot combine with this insn. */
1035 /* Anything else means we can't combine. */
1041 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1042 so don't do anything with it. */
1043 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1052 set = expand_field_assignment (set);
1053 src = SET_SRC (set), dest = SET_DEST (set);
1055 /* Don't eliminate a store in the stack pointer. */
1056 if (dest == stack_pointer_rtx
1057 /* If we couldn't eliminate a field assignment, we can't combine. */
1058 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1059 /* Don't combine with an insn that sets a register to itself if it has
1060 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1061 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1062 /* Can't merge a function call. */
1063 || GET_CODE (src) == CALL
1064 /* Don't eliminate a function call argument. */
1065 || (GET_CODE (i3) == CALL_INSN
1066 && (find_reg_fusage (i3, USE, dest)
1067 || (GET_CODE (dest) == REG
1068 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1069 && global_regs[REGNO (dest)])))
1070 /* Don't substitute into an incremented register. */
1071 || FIND_REG_INC_NOTE (i3, dest)
1072 || (succ && FIND_REG_INC_NOTE (succ, dest))
1074 /* Don't combine the end of a libcall into anything. */
1075 /* ??? This gives worse code, and appears to be unnecessary, since no
1076 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1077 use REG_RETVAL notes for noconflict blocks, but other code here
1078 makes sure that those insns don't disappear. */
1079 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1081 /* Make sure that DEST is not used after SUCC but before I3. */
1082 || (succ && ! all_adjacent
1083 && reg_used_between_p (dest, succ, i3))
1084 /* Make sure that the value that is to be substituted for the register
1085 does not use any registers whose values alter in between. However,
1086 If the insns are adjacent, a use can't cross a set even though we
1087 think it might (this can happen for a sequence of insns each setting
1088 the same destination; reg_last_set of that register might point to
1089 a NOTE). If INSN has a REG_EQUIV note, the register is always
1090 equivalent to the memory so the substitution is valid even if there
1091 are intervening stores. Also, don't move a volatile asm or
1092 UNSPEC_VOLATILE across any other insns. */
1094 && (((GET_CODE (src) != MEM
1095 || ! find_reg_note (insn, REG_EQUIV, src))
1096 && use_crosses_set_p (src, INSN_CUID (insn)))
1097 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1098 || GET_CODE (src) == UNSPEC_VOLATILE))
1099 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1100 better register allocation by not doing the combine. */
1101 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1102 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1103 /* Don't combine across a CALL_INSN, because that would possibly
1104 change whether the life span of some REGs crosses calls or not,
1105 and it is a pain to update that information.
1106 Exception: if source is a constant, moving it later can't hurt.
1107 Accept that special case, because it helps -fforce-addr a lot. */
1108 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1111 /* DEST must either be a REG or CC0. */
1112 if (GET_CODE (dest) == REG)
1114 /* If register alignment is being enforced for multi-word items in all
1115 cases except for parameters, it is possible to have a register copy
1116 insn referencing a hard register that is not allowed to contain the
1117 mode being copied and which would not be valid as an operand of most
1118 insns. Eliminate this problem by not combining with such an insn.
1120 Also, on some machines we don't want to extend the life of a hard
1123 This is the same test done in can_combine except that we don't test
1124 if SRC is a CALL operation to permit a hard register with
1125 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1128 if (GET_CODE (src) == REG
1129 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1130 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1131 /* Don't extend the life of a hard register unless it is
1132 user variable (if we have few registers) or it can't
1133 fit into the desired register (meaning something special
1135 Also avoid substituting a return register into I3, because
1136 reload can't handle a conflict with constraints of other
1138 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1139 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1140 || (SMALL_REGISTER_CLASSES
1141 && ((! all_adjacent && ! REG_USERVAR_P (src))
1142 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1143 && ! REG_USERVAR_P (src))))))))
1146 else if (GET_CODE (dest) != CC0)
1149 /* Don't substitute for a register intended as a clobberable operand.
1150 Similarly, don't substitute an expression containing a register that
1151 will be clobbered in I3. */
1152 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1153 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1154 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1155 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1157 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1160 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1161 or not), reject, unless nothing volatile comes between it and I3 */
1163 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1165 /* Make sure succ doesn't contain a volatile reference. */
1166 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1169 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1170 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1171 && p != succ && volatile_refs_p (PATTERN (p)))
1175 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1176 to be an explicit register variable, and was chosen for a reason. */
1178 if (GET_CODE (src) == ASM_OPERANDS
1179 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1182 /* If there are any volatile insns between INSN and I3, reject, because
1183 they might affect machine state. */
1185 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1186 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1187 && p != succ && volatile_insn_p (PATTERN (p)))
1190 /* If INSN or I2 contains an autoincrement or autodecrement,
1191 make sure that register is not used between there and I3,
1192 and not already used in I3 either.
1193 Also insist that I3 not be a jump; if it were one
1194 and the incremented register were spilled, we would lose. */
1197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1198 if (REG_NOTE_KIND (link) == REG_INC
1199 && (GET_CODE (i3) == JUMP_INSN
1200 || reg_used_between_p (XEXP (link, 0), insn, i3)
1201 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1206 /* Don't combine an insn that follows a CC0-setting insn.
1207 An insn that uses CC0 must not be separated from the one that sets it.
1208 We do, however, allow I2 to follow a CC0-setting insn if that insn
1209 is passed as I1; in that case it will be deleted also.
1210 We also allow combining in this case if all the insns are adjacent
1211 because that would leave the two CC0 insns adjacent as well.
1212 It would be more logical to test whether CC0 occurs inside I1 or I2,
1213 but that would be much slower, and this ought to be equivalent. */
1215 p = prev_nonnote_insn (insn);
1216 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1221 /* If we get here, we have passed all the tests and the combination is
1230 /* Check if PAT is an insn - or a part of it - used to set up an
1231 argument for a function in a hard register. */
1234 sets_function_arg_p (pat)
1240 switch (GET_CODE (pat))
1243 return sets_function_arg_p (PATTERN (pat));
1246 for (i = XVECLEN (pat, 0); --i >= 0;)
1247 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1253 inner_dest = SET_DEST (pat);
1254 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1255 || GET_CODE (inner_dest) == SUBREG
1256 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1257 inner_dest = XEXP (inner_dest, 0);
1259 return (GET_CODE (inner_dest) == REG
1260 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1261 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1270 /* LOC is the location within I3 that contains its pattern or the component
1271 of a PARALLEL of the pattern. We validate that it is valid for combining.
1273 One problem is if I3 modifies its output, as opposed to replacing it
1274 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1275 so would produce an insn that is not equivalent to the original insns.
1279 (set (reg:DI 101) (reg:DI 100))
1280 (set (subreg:SI (reg:DI 101) 0) <foo>)
1282 This is NOT equivalent to:
1284 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1285 (set (reg:DI 101) (reg:DI 100))])
1287 Not only does this modify 100 (in which case it might still be valid
1288 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1290 We can also run into a problem if I2 sets a register that I1
1291 uses and I1 gets directly substituted into I3 (not via I2). In that
1292 case, we would be getting the wrong value of I2DEST into I3, so we
1293 must reject the combination. This case occurs when I2 and I1 both
1294 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1295 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1296 of a SET must prevent combination from occurring.
1298 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1299 if the destination of a SET is a hard register that isn't a user
1302 Before doing the above check, we first try to expand a field assignment
1303 into a set of logical operations.
1305 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1306 we place a register that is both set and used within I3. If more than one
1307 such register is detected, we fail.
1309 Return 1 if the combination is valid, zero otherwise. */
1312 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1318 rtx *pi3dest_killed;
1322 if (GET_CODE (x) == SET)
1324 rtx set = expand_field_assignment (x);
1325 rtx dest = SET_DEST (set);
1326 rtx src = SET_SRC (set);
1327 rtx inner_dest = dest;
1330 rtx inner_src = src;
1335 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1336 || GET_CODE (inner_dest) == SUBREG
1337 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1338 inner_dest = XEXP (inner_dest, 0);
1340 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1343 while (GET_CODE (inner_src) == STRICT_LOW_PART
1344 || GET_CODE (inner_src) == SUBREG
1345 || GET_CODE (inner_src) == ZERO_EXTRACT)
1346 inner_src = XEXP (inner_src, 0);
1348 /* If it is better that two different modes keep two different pseudos,
1349 avoid combining them. This avoids producing the following pattern
1351 (set (subreg:SI (reg/v:QI 21) 0)
1352 (lshiftrt:SI (reg/v:SI 20)
1354 If that were made, reload could not handle the pair of
1355 reg 20/21, since it would try to get any GENERAL_REGS
1356 but some of them don't handle QImode. */
1358 if (rtx_equal_p (inner_src, i2dest)
1359 && GET_CODE (inner_dest) == REG
1360 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1364 /* Check for the case where I3 modifies its output, as
1366 if ((inner_dest != dest
1367 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1368 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1370 /* This is the same test done in can_combine_p except that we
1371 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1372 CALL operation. Moreover, we can't test all_adjacent; we don't
1373 have to, since this instruction will stay in place, thus we are
1374 not considering increasing the lifetime of INNER_DEST.
1376 Also, if this insn sets a function argument, combining it with
1377 something that might need a spill could clobber a previous
1378 function argument; the all_adjacent test in can_combine_p also
1379 checks this; here, we do a more specific test for this case. */
1381 || (GET_CODE (inner_dest) == REG
1382 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1383 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1384 GET_MODE (inner_dest))
1385 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1386 && ! REG_USERVAR_P (inner_dest)
1387 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1388 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1390 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1391 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1394 /* If DEST is used in I3, it is being killed in this insn,
1395 so record that for later.
1396 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1397 STACK_POINTER_REGNUM, since these are always considered to be
1398 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1399 if (pi3dest_killed && GET_CODE (dest) == REG
1400 && reg_referenced_p (dest, PATTERN (i3))
1401 && REGNO (dest) != FRAME_POINTER_REGNUM
1402 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1403 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1405 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1406 && (REGNO (dest) != ARG_POINTER_REGNUM
1407 || ! fixed_regs [REGNO (dest)])
1409 && REGNO (dest) != STACK_POINTER_REGNUM)
1411 if (*pi3dest_killed)
1414 *pi3dest_killed = dest;
1418 else if (GET_CODE (x) == PARALLEL)
1422 for (i = 0; i < XVECLEN (x, 0); i++)
1423 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1424 i1_not_in_src, pi3dest_killed))
1431 /* Return 1 if X is an arithmetic expression that contains a multiplication
1432 and division. We don't count multiplications by powers of two here. */
1438 switch (GET_CODE (x))
1440 case MOD: case DIV: case UMOD: case UDIV:
1444 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1445 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1447 switch (GET_RTX_CLASS (GET_CODE (x)))
1449 case 'c': case '<': case '2':
1450 return contains_muldiv (XEXP (x, 0))
1451 || contains_muldiv (XEXP (x, 1));
1454 return contains_muldiv (XEXP (x, 0));
1462 /* Try to combine the insns I1 and I2 into I3.
1463 Here I1 and I2 appear earlier than I3.
1464 I1 can be zero; then we combine just I2 into I3.
1466 It we are combining three insns and the resulting insn is not recognized,
1467 try splitting it into two insns. If that happens, I2 and I3 are retained
1468 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1471 Return 0 if the combination does not work. Then nothing is changed.
1472 If we did the combination, return the insn at which combine should
1475 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1476 new direct jump instruction. */
1479 try_combine (i3, i2, i1, new_direct_jump_p)
1480 register rtx i3, i2, i1;
1481 register int *new_direct_jump_p;
1483 /* New patterns for I3 and I2, respectively. */
1484 rtx newpat, newi2pat = 0;
1485 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1486 int added_sets_1, added_sets_2;
1487 /* Total number of SETs to put into I3. */
1489 /* Nonzero is I2's body now appears in I3. */
1491 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1492 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1493 /* Contains I3 if the destination of I3 is used in its source, which means
1494 that the old life of I3 is being killed. If that usage is placed into
1495 I2 and not in I3, a REG_DEAD note must be made. */
1496 rtx i3dest_killed = 0;
1497 /* SET_DEST and SET_SRC of I2 and I1. */
1498 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1499 /* PATTERN (I2), or a copy of it in certain cases. */
1501 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1502 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1503 int i1_feeds_i3 = 0;
1504 /* Notes that must be added to REG_NOTES in I3 and I2. */
1505 rtx new_i3_notes, new_i2_notes;
1506 /* Notes that we substituted I3 into I2 instead of the normal case. */
1507 int i3_subst_into_i2 = 0;
1508 /* Notes that I1, I2 or I3 is a MULT operation. */
1516 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1517 This can occur when flow deletes an insn that it has merged into an
1518 auto-increment address. We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1523 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1524 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1526 /* ??? This gives worse code, and appears to be unnecessary, since no
1527 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1528 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1534 undobuf.other_insn = 0;
1536 /* Save the current high-water-mark so we can free storage if we didn't
1537 accept this combination. */
1538 undobuf.storage = (char *) oballoc (0);
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs);
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1546 temp = i1, i1 = i2, i2 = temp;
1548 added_links_insn = 0;
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1558 We make very conservative checks below and only try to handle the
1559 most common cases of this. For example, we only handle the case
1560 where I2 and I3 are adjacent to avoid making difficult register
1563 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1564 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1565 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1566 && (! SMALL_REGISTER_CLASSES
1567 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1568 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1569 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1570 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1571 && GET_CODE (PATTERN (i2)) == PARALLEL
1572 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1573 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1574 below would need to check what is inside (and reg_overlap_mentioned_p
1575 doesn't support those codes anyway). Don't allow those destinations;
1576 the resulting insn isn't likely to be recognized anyway. */
1577 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1578 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1579 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1580 SET_DEST (PATTERN (i3)))
1581 && next_real_insn (i2) == i3)
1583 rtx p2 = PATTERN (i2);
1585 /* Make sure that the destination of I3,
1586 which we are going to substitute into one output of I2,
1587 is not used within another output of I2. We must avoid making this:
1588 (parallel [(set (mem (reg 69)) ...)
1589 (set (reg 69) ...)])
1590 which is not well-defined as to order of actions.
1591 (Besides, reload can't handle output reloads for this.)
1593 The problem can also happen if the dest of I3 is a memory ref,
1594 if another dest in I2 is an indirect memory ref. */
1595 for (i = 0; i < XVECLEN (p2, 0); i++)
1596 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1597 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1598 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1599 SET_DEST (XVECEXP (p2, 0, i))))
1602 if (i == XVECLEN (p2, 0))
1603 for (i = 0; i < XVECLEN (p2, 0); i++)
1604 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1605 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1606 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1611 subst_low_cuid = INSN_CUID (i2);
1613 added_sets_2 = added_sets_1 = 0;
1614 i2dest = SET_SRC (PATTERN (i3));
1616 /* Replace the dest in I2 with our dest and make the resulting
1617 insn the new pattern for I3. Then skip to where we
1618 validate the pattern. Everything was set up above. */
1619 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1620 SET_DEST (PATTERN (i3)));
1623 i3_subst_into_i2 = 1;
1624 goto validate_replacement;
1628 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1629 one of those words to another constant, merge them by making a new
1632 && (temp = single_set (i2)) != 0
1633 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1634 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1635 && GET_CODE (SET_DEST (temp)) == REG
1636 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1637 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1638 && GET_CODE (PATTERN (i3)) == SET
1639 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1640 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1641 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1642 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1643 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1645 HOST_WIDE_INT lo, hi;
1647 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1648 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1651 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1652 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1655 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1656 lo = INTVAL (SET_SRC (PATTERN (i3)));
1658 hi = INTVAL (SET_SRC (PATTERN (i3)));
1662 subst_low_cuid = INSN_CUID (i2);
1663 added_sets_2 = added_sets_1 = 0;
1664 i2dest = SET_DEST (temp);
1666 SUBST (SET_SRC (temp),
1667 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1669 newpat = PATTERN (i2);
1670 i3_subst_into_i2 = 1;
1671 goto validate_replacement;
1675 /* If we have no I1 and I2 looks like:
1676 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1678 make up a dummy I1 that is
1681 (set (reg:CC X) (compare:CC Y (const_int 0)))
1683 (We can ignore any trailing CLOBBERs.)
1685 This undoes a previous combination and allows us to match a branch-and-
1688 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1689 && XVECLEN (PATTERN (i2), 0) >= 2
1690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1691 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1693 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1694 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1695 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1696 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1697 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1698 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1700 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1701 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1706 /* We make I1 with the same INSN_UID as I2. This gives it
1707 the same INSN_CUID for value tracking. Our fake I1 will
1708 never appear in the insn stream so giving it the same INSN_UID
1709 as I2 will not cause a problem. */
1711 subst_prev_insn = i1
1712 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1713 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1716 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1717 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1718 SET_DEST (PATTERN (i1)));
1723 /* Verify that I2 and I1 are valid for combining. */
1724 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1725 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1731 /* Record whether I2DEST is used in I2SRC and similarly for the other
1732 cases. Knowing this will help in register status updating below. */
1733 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1734 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1735 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1737 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1739 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1741 /* Ensure that I3's pattern can be the destination of combines. */
1742 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1743 i1 && i2dest_in_i1src && i1_feeds_i3,
1750 /* See if any of the insns is a MULT operation. Unless one is, we will
1751 reject a combination that is, since it must be slower. Be conservative
1753 if (GET_CODE (i2src) == MULT
1754 || (i1 != 0 && GET_CODE (i1src) == MULT)
1755 || (GET_CODE (PATTERN (i3)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1759 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1760 We used to do this EXCEPT in one case: I3 has a post-inc in an
1761 output operand. However, that exception can give rise to insns like
1763 which is a famous insn on the PDP-11 where the value of r3 used as the
1764 source was model-dependent. Avoid this sort of thing. */
1767 if (!(GET_CODE (PATTERN (i3)) == SET
1768 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1769 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1770 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1771 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1772 /* It's not the exception. */
1775 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1776 if (REG_NOTE_KIND (link) == REG_INC
1777 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1779 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1786 /* See if the SETs in I1 or I2 need to be kept around in the merged
1787 instruction: whenever the value set there is still needed past I3.
1788 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1790 For the SET in I1, we have two cases: If I1 and I2 independently
1791 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1792 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1793 in I1 needs to be kept around unless I1DEST dies or is set in either
1794 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1795 I1DEST. If so, we know I1 feeds into I2. */
1797 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1800 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1801 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1803 /* If the set in I2 needs to be kept around, we must make a copy of
1804 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1805 PATTERN (I2), we are only substituting for the original I1DEST, not into
1806 an already-substituted copy. This also prevents making self-referential
1807 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1810 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1811 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1815 i2pat = copy_rtx (i2pat);
1819 /* Substitute in the latest insn for the regs set by the earlier ones. */
1821 maxreg = max_reg_num ();
1825 /* It is possible that the source of I2 or I1 may be performing an
1826 unneeded operation, such as a ZERO_EXTEND of something that is known
1827 to have the high part zero. Handle that case by letting subst look at
1828 the innermost one of them.
1830 Another way to do this would be to have a function that tries to
1831 simplify a single insn instead of merging two or more insns. We don't
1832 do this because of the potential of infinite loops and because
1833 of the potential extra memory required. However, doing it the way
1834 we are is a bit of a kludge and doesn't catch all cases.
1836 But only do this if -fexpensive-optimizations since it slows things down
1837 and doesn't usually win. */
1839 if (flag_expensive_optimizations)
1841 /* Pass pc_rtx so no substitutions are done, just simplifications.
1842 The cases that we are interested in here do not involve the few
1843 cases were is_replaced is checked. */
1846 subst_low_cuid = INSN_CUID (i1);
1847 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1851 subst_low_cuid = INSN_CUID (i2);
1852 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1855 undobuf.previous_undos = undobuf.undos;
1859 /* Many machines that don't use CC0 have insns that can both perform an
1860 arithmetic operation and set the condition code. These operations will
1861 be represented as a PARALLEL with the first element of the vector
1862 being a COMPARE of an arithmetic operation with the constant zero.
1863 The second element of the vector will set some pseudo to the result
1864 of the same arithmetic operation. If we simplify the COMPARE, we won't
1865 match such a pattern and so will generate an extra insn. Here we test
1866 for this case, where both the comparison and the operation result are
1867 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1868 I2SRC. Later we will make the PARALLEL that contains I2. */
1870 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1871 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1872 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1873 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1875 #ifdef EXTRA_CC_MODES
1877 enum machine_mode compare_mode;
1880 newpat = PATTERN (i3);
1881 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1885 #ifdef EXTRA_CC_MODES
1886 /* See if a COMPARE with the operand we substituted in should be done
1887 with the mode that is currently being used. If not, do the same
1888 processing we do in `subst' for a SET; namely, if the destination
1889 is used only once, try to replace it with a register of the proper
1890 mode and also replace the COMPARE. */
1891 if (undobuf.other_insn == 0
1892 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1893 &undobuf.other_insn))
1894 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1896 != GET_MODE (SET_DEST (newpat))))
1898 unsigned int regno = REGNO (SET_DEST (newpat));
1899 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1901 if (regno < FIRST_PSEUDO_REGISTER
1902 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1903 && ! REG_USERVAR_P (SET_DEST (newpat))))
1905 if (regno >= FIRST_PSEUDO_REGISTER)
1906 SUBST (regno_reg_rtx[regno], new_dest);
1908 SUBST (SET_DEST (newpat), new_dest);
1909 SUBST (XEXP (*cc_use, 0), new_dest);
1910 SUBST (SET_SRC (newpat),
1911 gen_rtx_combine (COMPARE, compare_mode,
1912 i2src, const0_rtx));
1915 undobuf.other_insn = 0;
1922 n_occurrences = 0; /* `subst' counts here */
1924 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1925 need to make a unique copy of I2SRC each time we substitute it
1926 to avoid self-referential rtl. */
1928 subst_low_cuid = INSN_CUID (i2);
1929 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1930 ! i1_feeds_i3 && i1dest_in_i1src);
1931 undobuf.previous_undos = undobuf.undos;
1933 /* Record whether i2's body now appears within i3's body. */
1934 i2_is_used = n_occurrences;
1937 /* If we already got a failure, don't try to do more. Otherwise,
1938 try to substitute in I1 if we have it. */
1940 if (i1 && GET_CODE (newpat) != CLOBBER)
1942 /* Before we can do this substitution, we must redo the test done
1943 above (see detailed comments there) that ensures that I1DEST
1944 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1946 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1954 subst_low_cuid = INSN_CUID (i1);
1955 newpat = subst (newpat, i1dest, i1src, 0, 0);
1956 undobuf.previous_undos = undobuf.undos;
1959 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1960 to count all the ways that I2SRC and I1SRC can be used. */
1961 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1962 && i2_is_used + added_sets_2 > 1)
1963 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1964 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1966 /* Fail if we tried to make a new register (we used to abort, but there's
1967 really no reason to). */
1968 || max_reg_num () != maxreg
1969 /* Fail if we couldn't do something and have a CLOBBER. */
1970 || GET_CODE (newpat) == CLOBBER
1971 /* Fail if this new pattern is a MULT and we didn't have one before
1972 at the outer level. */
1973 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1980 /* If the actions of the earlier insns must be kept
1981 in addition to substituting them into the latest one,
1982 we must make a new PARALLEL for the latest insn
1983 to hold additional the SETs. */
1985 if (added_sets_1 || added_sets_2)
1989 if (GET_CODE (newpat) == PARALLEL)
1991 rtvec old = XVEC (newpat, 0);
1992 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1993 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1994 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1995 sizeof (old->elem[0]) * old->num_elem);
2000 total_sets = 1 + added_sets_1 + added_sets_2;
2001 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2002 XVECEXP (newpat, 0, 0) = old;
2006 XVECEXP (newpat, 0, --total_sets)
2007 = (GET_CODE (PATTERN (i1)) == PARALLEL
2008 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2012 /* If there is no I1, use I2's body as is. We used to also not do
2013 the subst call below if I2 was substituted into I3,
2014 but that could lose a simplification. */
2016 XVECEXP (newpat, 0, --total_sets) = i2pat;
2018 /* See comment where i2pat is assigned. */
2019 XVECEXP (newpat, 0, --total_sets)
2020 = subst (i2pat, i1dest, i1src, 0, 0);
2024 /* We come here when we are replacing a destination in I2 with the
2025 destination of I3. */
2026 validate_replacement:
2028 /* Note which hard regs this insn has as inputs. */
2029 mark_used_regs_combine (newpat);
2031 /* Is the result of combination a valid instruction? */
2032 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2034 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2035 the second SET's destination is a register that is unused. In that case,
2036 we just need the first SET. This can occur when simplifying a divmod
2037 insn. We *must* test for this case here because the code below that
2038 splits two independent SETs doesn't handle this case correctly when it
2039 updates the register status. Also check the case where the first
2040 SET's destination is unused. That would not cause incorrect code, but
2041 does cause an unneeded insn to remain. */
2043 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2044 && XVECLEN (newpat, 0) == 2
2045 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2046 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2048 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2049 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2050 && asm_noperands (newpat) < 0)
2052 newpat = XVECEXP (newpat, 0, 0);
2053 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2056 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2060 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2061 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2062 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2063 && asm_noperands (newpat) < 0)
2065 newpat = XVECEXP (newpat, 0, 1);
2066 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2069 /* If we were combining three insns and the result is a simple SET
2070 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2071 insns. There are two ways to do this. It can be split using a
2072 machine-specific method (like when you have an addition of a large
2073 constant) or by combine in the function find_split_point. */
2075 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2076 && asm_noperands (newpat) < 0)
2078 rtx m_split, *split;
2079 rtx ni2dest = i2dest;
2081 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2082 use I2DEST as a scratch register will help. In the latter case,
2083 convert I2DEST to the mode of the source of NEWPAT if we can. */
2085 m_split = split_insns (newpat, i3);
2087 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2088 inputs of NEWPAT. */
2090 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2091 possible to try that as a scratch reg. This would require adding
2092 more code to make it work though. */
2094 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2096 /* If I2DEST is a hard register or the only use of a pseudo,
2097 we can change its mode. */
2098 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2099 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2100 && GET_CODE (i2dest) == REG
2101 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2102 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2103 && ! REG_USERVAR_P (i2dest))))
2104 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2107 m_split = split_insns (gen_rtx_PARALLEL
2109 gen_rtvec (2, newpat,
2110 gen_rtx_CLOBBER (VOIDmode,
2115 if (m_split && GET_CODE (m_split) == SEQUENCE
2116 && XVECLEN (m_split, 0) == 2
2117 && (next_real_insn (i2) == i3
2118 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2122 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2123 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2125 i3set = single_set (XVECEXP (m_split, 0, 1));
2126 i2set = single_set (XVECEXP (m_split, 0, 0));
2128 /* In case we changed the mode of I2DEST, replace it in the
2129 pseudo-register table here. We can't do it above in case this
2130 code doesn't get executed and we do a split the other way. */
2132 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2133 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2135 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2137 /* If I2 or I3 has multiple SETs, we won't know how to track
2138 register status, so don't use these insns. If I2's destination
2139 is used between I2 and I3, we also can't use these insns. */
2141 if (i2_code_number >= 0 && i2set && i3set
2142 && (next_real_insn (i2) == i3
2143 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2144 insn_code_number = recog_for_combine (&newi3pat, i3,
2146 if (insn_code_number >= 0)
2149 /* It is possible that both insns now set the destination of I3.
2150 If so, we must show an extra use of it. */
2152 if (insn_code_number >= 0)
2154 rtx new_i3_dest = SET_DEST (i3set);
2155 rtx new_i2_dest = SET_DEST (i2set);
2157 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2158 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2159 || GET_CODE (new_i3_dest) == SUBREG)
2160 new_i3_dest = XEXP (new_i3_dest, 0);
2162 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2163 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2164 || GET_CODE (new_i2_dest) == SUBREG)
2165 new_i2_dest = XEXP (new_i2_dest, 0);
2167 if (GET_CODE (new_i3_dest) == REG
2168 && GET_CODE (new_i2_dest) == REG
2169 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2170 REG_N_SETS (REGNO (new_i2_dest))++;
2174 /* If we can split it and use I2DEST, go ahead and see if that
2175 helps things be recognized. Verify that none of the registers
2176 are set between I2 and I3. */
2177 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2179 && GET_CODE (i2dest) == REG
2181 /* We need I2DEST in the proper mode. If it is a hard register
2182 or the only use of a pseudo, we can change its mode. */
2183 && (GET_MODE (*split) == GET_MODE (i2dest)
2184 || GET_MODE (*split) == VOIDmode
2185 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2186 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2187 && ! REG_USERVAR_P (i2dest)))
2188 && (next_real_insn (i2) == i3
2189 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2190 /* We can't overwrite I2DEST if its value is still used by
2192 && ! reg_referenced_p (i2dest, newpat))
2194 rtx newdest = i2dest;
2195 enum rtx_code split_code = GET_CODE (*split);
2196 enum machine_mode split_mode = GET_MODE (*split);
2198 /* Get NEWDEST as a register in the proper mode. We have already
2199 validated that we can do this. */
2200 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2202 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2204 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2205 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2208 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2209 an ASHIFT. This can occur if it was inside a PLUS and hence
2210 appeared to be a memory address. This is a kludge. */
2211 if (split_code == MULT
2212 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2213 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2215 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2216 XEXP (*split, 0), GEN_INT (i)));
2217 /* Update split_code because we may not have a multiply
2219 split_code = GET_CODE (*split);
2222 #ifdef INSN_SCHEDULING
2223 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2224 be written as a ZERO_EXTEND. */
2225 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2226 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2230 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2231 SUBST (*split, newdest);
2232 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2234 /* If the split point was a MULT and we didn't have one before,
2235 don't use one now. */
2236 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2237 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2241 /* Check for a case where we loaded from memory in a narrow mode and
2242 then sign extended it, but we need both registers. In that case,
2243 we have a PARALLEL with both loads from the same memory location.
2244 We can split this into a load from memory followed by a register-register
2245 copy. This saves at least one insn, more if register allocation can
2248 We cannot do this if the destination of the second assignment is
2249 a register that we have already assumed is zero-extended. Similarly
2250 for a SUBREG of such a register. */
2252 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2253 && GET_CODE (newpat) == PARALLEL
2254 && XVECLEN (newpat, 0) == 2
2255 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2256 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2257 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2258 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2259 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2260 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2262 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2263 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2264 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2265 (GET_CODE (temp) == REG
2266 && reg_nonzero_bits[REGNO (temp)] != 0
2267 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2268 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2269 && (reg_nonzero_bits[REGNO (temp)]
2270 != GET_MODE_MASK (word_mode))))
2271 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2272 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2273 (GET_CODE (temp) == REG
2274 && reg_nonzero_bits[REGNO (temp)] != 0
2275 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2276 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2277 && (reg_nonzero_bits[REGNO (temp)]
2278 != GET_MODE_MASK (word_mode)))))
2279 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2280 SET_SRC (XVECEXP (newpat, 0, 1)))
2281 && ! find_reg_note (i3, REG_UNUSED,
2282 SET_DEST (XVECEXP (newpat, 0, 0))))
2286 newi2pat = XVECEXP (newpat, 0, 0);
2287 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2288 newpat = XVECEXP (newpat, 0, 1);
2289 SUBST (SET_SRC (newpat),
2290 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2291 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2293 if (i2_code_number >= 0)
2294 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2296 if (insn_code_number >= 0)
2301 /* If we will be able to accept this, we have made a change to the
2302 destination of I3. This can invalidate a LOG_LINKS pointing
2303 to I3. No other part of combine.c makes such a transformation.
2305 The new I3 will have a destination that was previously the
2306 destination of I1 or I2 and which was used in i2 or I3. Call
2307 distribute_links to make a LOG_LINK from the next use of
2308 that destination. */
2310 PATTERN (i3) = newpat;
2311 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2313 /* I3 now uses what used to be its destination and which is
2314 now I2's destination. That means we need a LOG_LINK from
2315 I3 to I2. But we used to have one, so we still will.
2317 However, some later insn might be using I2's dest and have
2318 a LOG_LINK pointing at I3. We must remove this link.
2319 The simplest way to remove the link is to point it at I1,
2320 which we know will be a NOTE. */
2322 for (insn = NEXT_INSN (i3);
2323 insn && (this_basic_block == n_basic_blocks - 1
2324 || insn != BLOCK_HEAD (this_basic_block + 1));
2325 insn = NEXT_INSN (insn))
2327 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2328 && reg_referenced_p (ni2dest, PATTERN (insn)))
2330 for (link = LOG_LINKS (insn); link;
2331 link = XEXP (link, 1))
2332 if (XEXP (link, 0) == i3)
2333 XEXP (link, 0) = i1;
2341 /* Similarly, check for a case where we have a PARALLEL of two independent
2342 SETs but we started with three insns. In this case, we can do the sets
2343 as two separate insns. This case occurs when some SET allows two
2344 other insns to combine, but the destination of that SET is still live. */
2346 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2347 && GET_CODE (newpat) == PARALLEL
2348 && XVECLEN (newpat, 0) == 2
2349 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2350 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2351 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2352 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2353 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2354 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2355 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2357 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2358 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2359 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2360 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2361 XVECEXP (newpat, 0, 0))
2362 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2363 XVECEXP (newpat, 0, 1))
2364 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2365 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2367 /* Normally, it doesn't matter which of the two is done first,
2368 but it does if one references cc0. In that case, it has to
2371 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2373 newi2pat = XVECEXP (newpat, 0, 0);
2374 newpat = XVECEXP (newpat, 0, 1);
2379 newi2pat = XVECEXP (newpat, 0, 1);
2380 newpat = XVECEXP (newpat, 0, 0);
2383 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2385 if (i2_code_number >= 0)
2386 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2389 /* If it still isn't recognized, fail and change things back the way they
2391 if ((insn_code_number < 0
2392 /* Is the result a reasonable ASM_OPERANDS? */
2393 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2399 /* If we had to change another insn, make sure it is valid also. */
2400 if (undobuf.other_insn)
2402 rtx other_pat = PATTERN (undobuf.other_insn);
2403 rtx new_other_notes;
2406 CLEAR_HARD_REG_SET (newpat_used_regs);
2408 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2411 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2417 PATTERN (undobuf.other_insn) = other_pat;
2419 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2420 are still valid. Then add any non-duplicate notes added by
2421 recog_for_combine. */
2422 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2424 next = XEXP (note, 1);
2426 if (REG_NOTE_KIND (note) == REG_UNUSED
2427 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2429 if (GET_CODE (XEXP (note, 0)) == REG)
2430 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2432 remove_note (undobuf.other_insn, note);
2436 for (note = new_other_notes; note; note = XEXP (note, 1))
2437 if (GET_CODE (XEXP (note, 0)) == REG)
2438 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2440 distribute_notes (new_other_notes, undobuf.other_insn,
2441 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2444 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2445 they are adjacent to each other or not. */
2447 rtx p = prev_nonnote_insn (i3);
2448 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat && sets_cc0_p (newi2pat))
2456 /* We now know that we can do this combination. Merge the insns and
2457 update the status of registers and LOG_LINKS. */
2460 rtx i3notes, i2notes, i1notes = 0;
2461 rtx i3links, i2links, i1links = 0;
2464 /* Compute which registers we expect to eliminate. newi2pat may be setting
2465 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2466 same as i3dest, in which case newi2pat may be setting i1dest. */
2467 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2468 || i2dest_in_i2src || i2dest_in_i1src
2470 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2471 || (newi2pat && reg_set_p (i1dest, newi2pat))
2474 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2476 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2477 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2479 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2481 /* Ensure that we do not have something that should not be shared but
2482 occurs multiple times in the new insns. Check this by first
2483 resetting all the `used' flags and then copying anything is shared. */
2485 reset_used_flags (i3notes);
2486 reset_used_flags (i2notes);
2487 reset_used_flags (i1notes);
2488 reset_used_flags (newpat);
2489 reset_used_flags (newi2pat);
2490 if (undobuf.other_insn)
2491 reset_used_flags (PATTERN (undobuf.other_insn));
2493 i3notes = copy_rtx_if_shared (i3notes);
2494 i2notes = copy_rtx_if_shared (i2notes);
2495 i1notes = copy_rtx_if_shared (i1notes);
2496 newpat = copy_rtx_if_shared (newpat);
2497 newi2pat = copy_rtx_if_shared (newi2pat);
2498 if (undobuf.other_insn)
2499 reset_used_flags (PATTERN (undobuf.other_insn));
2501 INSN_CODE (i3) = insn_code_number;
2502 PATTERN (i3) = newpat;
2503 if (undobuf.other_insn)
2504 INSN_CODE (undobuf.other_insn) = other_code_number;
2506 /* We had one special case above where I2 had more than one set and
2507 we replaced a destination of one of those sets with the destination
2508 of I3. In that case, we have to update LOG_LINKS of insns later
2509 in this basic block. Note that this (expensive) case is rare.
2511 Also, in this case, we must pretend that all REG_NOTEs for I2
2512 actually came from I3, so that REG_UNUSED notes from I2 will be
2513 properly handled. */
2515 if (i3_subst_into_i2 && GET_CODE (PATTERN (i2)) == PARALLEL)
2517 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2519 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2520 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2521 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2522 && ! find_reg_note (i2, REG_UNUSED,
2523 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2524 for (temp = NEXT_INSN (i2);
2525 temp && (this_basic_block == n_basic_blocks - 1
2526 || BLOCK_HEAD (this_basic_block) != temp);
2527 temp = NEXT_INSN (temp))
2528 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2529 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2530 if (XEXP (link, 0) == i2)
2531 XEXP (link, 0) = i3;
2537 while (XEXP (link, 1))
2538 link = XEXP (link, 1);
2539 XEXP (link, 1) = i2notes;
2553 INSN_CODE (i2) = i2_code_number;
2554 PATTERN (i2) = newi2pat;
2558 PUT_CODE (i2, NOTE);
2559 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2560 NOTE_SOURCE_FILE (i2) = 0;
2567 PUT_CODE (i1, NOTE);
2568 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2569 NOTE_SOURCE_FILE (i1) = 0;
2572 /* Get death notes for everything that is now used in either I3 or
2573 I2 and used to die in a previous insn. If we built two new
2574 patterns, move from I1 to I2 then I2 to I3 so that we get the
2575 proper movement on registers that I2 modifies. */
2579 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2580 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2583 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2586 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2588 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2591 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2594 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2597 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2600 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2601 know these are REG_UNUSED and want them to go to the desired insn,
2602 so we always pass it as i3. We have not counted the notes in
2603 reg_n_deaths yet, so we need to do so now. */
2605 if (newi2pat && new_i2_notes)
2607 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2608 if (GET_CODE (XEXP (temp, 0)) == REG)
2609 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2611 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2616 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2617 if (GET_CODE (XEXP (temp, 0)) == REG)
2618 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2620 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2623 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2624 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2625 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2626 in that case, it might delete I2. Similarly for I2 and I1.
2627 Show an additional death due to the REG_DEAD note we make here. If
2628 we discard it in distribute_notes, we will decrement it again. */
2632 if (GET_CODE (i3dest_killed) == REG)
2633 REG_N_DEATHS (REGNO (i3dest_killed))++;
2635 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2636 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2638 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2640 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2642 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2646 if (i2dest_in_i2src)
2648 if (GET_CODE (i2dest) == REG)
2649 REG_N_DEATHS (REGNO (i2dest))++;
2651 if (newi2pat && reg_set_p (i2dest, newi2pat))
2652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2653 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2656 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2657 NULL_RTX, NULL_RTX);
2660 if (i1dest_in_i1src)
2662 if (GET_CODE (i1dest) == REG)
2663 REG_N_DEATHS (REGNO (i1dest))++;
2665 if (newi2pat && reg_set_p (i1dest, newi2pat))
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2667 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2670 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2671 NULL_RTX, NULL_RTX);
2674 distribute_links (i3links);
2675 distribute_links (i2links);
2676 distribute_links (i1links);
2678 if (GET_CODE (i2dest) == REG)
2681 rtx i2_insn = 0, i2_val = 0, set;
2683 /* The insn that used to set this register doesn't exist, and
2684 this life of the register may not exist either. See if one of
2685 I3's links points to an insn that sets I2DEST. If it does,
2686 that is now the last known value for I2DEST. If we don't update
2687 this and I2 set the register to a value that depended on its old
2688 contents, we will get confused. If this insn is used, thing
2689 will be set correctly in combine_instructions. */
2691 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2692 if ((set = single_set (XEXP (link, 0))) != 0
2693 && rtx_equal_p (i2dest, SET_DEST (set)))
2694 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2696 record_value_for_reg (i2dest, i2_insn, i2_val);
2698 /* If the reg formerly set in I2 died only once and that was in I3,
2699 zero its use count so it won't make `reload' do any work. */
2701 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2702 && ! i2dest_in_i2src)
2704 regno = REGNO (i2dest);
2705 REG_N_SETS (regno)--;
2709 if (i1 && GET_CODE (i1dest) == REG)
2712 rtx i1_insn = 0, i1_val = 0, set;
2714 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2715 if ((set = single_set (XEXP (link, 0))) != 0
2716 && rtx_equal_p (i1dest, SET_DEST (set)))
2717 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2719 record_value_for_reg (i1dest, i1_insn, i1_val);
2721 regno = REGNO (i1dest);
2722 if (! added_sets_1 && ! i1dest_in_i1src)
2723 REG_N_SETS (regno)--;
2726 /* Update reg_nonzero_bits et al for any changes that may have been made
2727 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2728 important. Because newi2pat can affect nonzero_bits of newpat */
2730 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2731 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2733 /* Set new_direct_jump_p if a new return or simple jump instruction
2736 If I3 is now an unconditional jump, ensure that it has a
2737 BARRIER following it since it may have initially been a
2738 conditional jump. It may also be the last nonnote insn. */
2740 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2742 *new_direct_jump_p = 1;
2744 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2745 || GET_CODE (temp) != BARRIER)
2746 emit_barrier_after (i3);
2750 combine_successes++;
2753 /* Clear this here, so that subsequent get_last_value calls are not
2755 subst_prev_insn = NULL_RTX;
2757 if (added_links_insn
2758 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2759 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2760 return added_links_insn;
2762 return newi2pat ? i2 : i3;
2765 /* Undo all the modifications recorded in undobuf. */
2770 struct undo *undo, *next;
2772 for (undo = undobuf.undos; undo; undo = next)
2776 *undo->where.i = undo->old_contents.i;
2778 *undo->where.r = undo->old_contents.r;
2780 undo->next = undobuf.frees;
2781 undobuf.frees = undo;
2784 obfree (undobuf.storage);
2785 undobuf.undos = undobuf.previous_undos = 0;
2787 /* Clear this here, so that subsequent get_last_value calls are not
2789 subst_prev_insn = NULL_RTX;
2792 /* We've committed to accepting the changes we made. Move all
2793 of the undos to the free list. */
2798 struct undo *undo, *next;
2800 for (undo = undobuf.undos; undo; undo = next)
2803 undo->next = undobuf.frees;
2804 undobuf.frees = undo;
2806 undobuf.undos = undobuf.previous_undos = 0;
2810 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2811 where we have an arithmetic expression and return that point. LOC will
2814 try_combine will call this function to see if an insn can be split into
2818 find_split_point (loc, insn)
2823 enum rtx_code code = GET_CODE (x);
2825 unsigned HOST_WIDE_INT len = 0;
2826 HOST_WIDE_INT pos = 0;
2828 rtx inner = NULL_RTX;
2830 /* First special-case some codes. */
2834 #ifdef INSN_SCHEDULING
2835 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2837 if (GET_CODE (SUBREG_REG (x)) == MEM)
2840 return find_split_point (&SUBREG_REG (x), insn);
2844 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2845 using LO_SUM and HIGH. */
2846 if (GET_CODE (XEXP (x, 0)) == CONST
2847 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2850 gen_rtx_combine (LO_SUM, Pmode,
2851 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2853 return &XEXP (XEXP (x, 0), 0);
2857 /* If we have a PLUS whose second operand is a constant and the
2858 address is not valid, perhaps will can split it up using
2859 the machine-specific way to split large constants. We use
2860 the first pseudo-reg (one of the virtual regs) as a placeholder;
2861 it will not remain in the result. */
2862 if (GET_CODE (XEXP (x, 0)) == PLUS
2863 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2864 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2866 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2867 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2870 /* This should have produced two insns, each of which sets our
2871 placeholder. If the source of the second is a valid address,
2872 we can make put both sources together and make a split point
2875 if (seq && XVECLEN (seq, 0) == 2
2876 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2877 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2878 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2879 && ! reg_mentioned_p (reg,
2880 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2881 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2882 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2883 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2884 && memory_address_p (GET_MODE (x),
2885 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2887 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2888 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2890 /* Replace the placeholder in SRC2 with SRC1. If we can
2891 find where in SRC2 it was placed, that can become our
2892 split point and we can replace this address with SRC2.
2893 Just try two obvious places. */
2895 src2 = replace_rtx (src2, reg, src1);
2897 if (XEXP (src2, 0) == src1)
2898 split = &XEXP (src2, 0);
2899 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2900 && XEXP (XEXP (src2, 0), 0) == src1)
2901 split = &XEXP (XEXP (src2, 0), 0);
2905 SUBST (XEXP (x, 0), src2);
2910 /* If that didn't work, perhaps the first operand is complex and
2911 needs to be computed separately, so make a split point there.
2912 This will occur on machines that just support REG + CONST
2913 and have a constant moved through some previous computation. */
2915 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2916 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2917 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2919 return &XEXP (XEXP (x, 0), 0);
2925 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2926 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2927 we need to put the operand into a register. So split at that
2930 if (SET_DEST (x) == cc0_rtx
2931 && GET_CODE (SET_SRC (x)) != COMPARE
2932 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2933 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2934 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2935 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2936 return &SET_SRC (x);
2939 /* See if we can split SET_SRC as it stands. */
2940 split = find_split_point (&SET_SRC (x), insn);
2941 if (split && split != &SET_SRC (x))
2944 /* See if we can split SET_DEST as it stands. */
2945 split = find_split_point (&SET_DEST (x), insn);
2946 if (split && split != &SET_DEST (x))
2949 /* See if this is a bitfield assignment with everything constant. If
2950 so, this is an IOR of an AND, so split it into that. */
2951 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2953 <= HOST_BITS_PER_WIDE_INT)
2954 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2955 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2956 && GET_CODE (SET_SRC (x)) == CONST_INT
2957 && ((INTVAL (XEXP (SET_DEST (x), 1))
2958 + INTVAL (XEXP (SET_DEST (x), 2)))
2959 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2960 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2962 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2963 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2964 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2965 rtx dest = XEXP (SET_DEST (x), 0);
2966 enum machine_mode mode = GET_MODE (dest);
2967 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2969 if (BITS_BIG_ENDIAN)
2970 pos = GET_MODE_BITSIZE (mode) - len - pos;
2974 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2977 gen_binary (IOR, mode,
2978 gen_binary (AND, mode, dest,
2979 GEN_INT (~ (mask << pos)
2980 & GET_MODE_MASK (mode))),
2981 GEN_INT (src << pos)));
2983 SUBST (SET_DEST (x), dest);
2985 split = find_split_point (&SET_SRC (x), insn);
2986 if (split && split != &SET_SRC (x))
2990 /* Otherwise, see if this is an operation that we can split into two.
2991 If so, try to split that. */
2992 code = GET_CODE (SET_SRC (x));
2997 /* If we are AND'ing with a large constant that is only a single
2998 bit and the result is only being used in a context where we
2999 need to know if it is zero or non-zero, replace it with a bit
3000 extraction. This will avoid the large constant, which might
3001 have taken more than one insn to make. If the constant were
3002 not a valid argument to the AND but took only one insn to make,
3003 this is no worse, but if it took more than one insn, it will
3006 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3007 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3008 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3009 && GET_CODE (SET_DEST (x)) == REG
3010 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3011 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3012 && XEXP (*split, 0) == SET_DEST (x)
3013 && XEXP (*split, 1) == const0_rtx)
3015 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3016 XEXP (SET_SRC (x), 0),
3017 pos, NULL_RTX, 1, 1, 0, 0);
3018 if (extraction != 0)
3020 SUBST (SET_SRC (x), extraction);
3021 return find_split_point (loc, insn);
3027 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3028 is known to be on, this can be converted into a NEG of a shift. */
3029 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3030 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3031 && 1 <= (pos = exact_log2
3032 (nonzero_bits (XEXP (SET_SRC (x), 0),
3033 GET_MODE (XEXP (SET_SRC (x), 0))))))
3035 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3038 gen_rtx_combine (NEG, mode,
3039 gen_rtx_combine (LSHIFTRT, mode,
3040 XEXP (SET_SRC (x), 0),
3043 split = find_split_point (&SET_SRC (x), insn);
3044 if (split && split != &SET_SRC (x))
3050 inner = XEXP (SET_SRC (x), 0);
3052 /* We can't optimize if either mode is a partial integer
3053 mode as we don't know how many bits are significant
3055 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3056 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3060 len = GET_MODE_BITSIZE (GET_MODE (inner));
3066 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3067 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3069 inner = XEXP (SET_SRC (x), 0);
3070 len = INTVAL (XEXP (SET_SRC (x), 1));
3071 pos = INTVAL (XEXP (SET_SRC (x), 2));
3073 if (BITS_BIG_ENDIAN)
3074 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3075 unsignedp = (code == ZERO_EXTRACT);
3083 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3085 enum machine_mode mode = GET_MODE (SET_SRC (x));
3087 /* For unsigned, we have a choice of a shift followed by an
3088 AND or two shifts. Use two shifts for field sizes where the
3089 constant might be too large. We assume here that we can
3090 always at least get 8-bit constants in an AND insn, which is
3091 true for every current RISC. */
3093 if (unsignedp && len <= 8)
3098 gen_rtx_combine (LSHIFTRT, mode,
3099 gen_lowpart_for_combine (mode, inner),
3101 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3103 split = find_split_point (&SET_SRC (x), insn);
3104 if (split && split != &SET_SRC (x))
3111 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3112 gen_rtx_combine (ASHIFT, mode,
3113 gen_lowpart_for_combine (mode, inner),
3114 GEN_INT (GET_MODE_BITSIZE (mode)
3116 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3118 split = find_split_point (&SET_SRC (x), insn);
3119 if (split && split != &SET_SRC (x))
3124 /* See if this is a simple operation with a constant as the second
3125 operand. It might be that this constant is out of range and hence
3126 could be used as a split point. */
3127 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3128 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3129 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3130 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3131 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3132 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3133 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3135 return &XEXP (SET_SRC (x), 1);
3137 /* Finally, see if this is a simple operation with its first operand
3138 not in a register. The operation might require this operand in a
3139 register, so return it as a split point. We can always do this
3140 because if the first operand were another operation, we would have
3141 already found it as a split point. */
3142 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3143 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3144 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3145 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3146 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3147 return &XEXP (SET_SRC (x), 0);
3153 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3154 it is better to write this as (not (ior A B)) so we can split it.
3155 Similarly for IOR. */
3156 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3159 gen_rtx_combine (NOT, GET_MODE (x),
3160 gen_rtx_combine (code == IOR ? AND : IOR,
3162 XEXP (XEXP (x, 0), 0),
3163 XEXP (XEXP (x, 1), 0))));
3164 return find_split_point (loc, insn);
3167 /* Many RISC machines have a large set of logical insns. If the
3168 second operand is a NOT, put it first so we will try to split the
3169 other operand first. */
3170 if (GET_CODE (XEXP (x, 1)) == NOT)
3172 rtx tem = XEXP (x, 0);
3173 SUBST (XEXP (x, 0), XEXP (x, 1));
3174 SUBST (XEXP (x, 1), tem);
3182 /* Otherwise, select our actions depending on our rtx class. */
3183 switch (GET_RTX_CLASS (code))
3185 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3187 split = find_split_point (&XEXP (x, 2), insn);
3190 /* ... fall through ... */
3194 split = find_split_point (&XEXP (x, 1), insn);
3197 /* ... fall through ... */
3199 /* Some machines have (and (shift ...) ...) insns. If X is not
3200 an AND, but XEXP (X, 0) is, use it as our split point. */
3201 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3202 return &XEXP (x, 0);
3204 split = find_split_point (&XEXP (x, 0), insn);
3210 /* Otherwise, we don't have a split point. */
3214 /* Throughout X, replace FROM with TO, and return the result.
3215 The result is TO if X is FROM;
3216 otherwise the result is X, but its contents may have been modified.
3217 If they were modified, a record was made in undobuf so that
3218 undo_all will (among other things) return X to its original state.
3220 If the number of changes necessary is too much to record to undo,
3221 the excess changes are not made, so the result is invalid.
3222 The changes already made can still be undone.
3223 undobuf.num_undo is incremented for such changes, so by testing that
3224 the caller can tell whether the result is valid.
3226 `n_occurrences' is incremented each time FROM is replaced.
3228 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3230 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3231 by copying if `n_occurrences' is non-zero. */
3234 subst (x, from, to, in_dest, unique_copy)
3235 register rtx x, from, to;
3239 register enum rtx_code code = GET_CODE (x);
3240 enum machine_mode op0_mode = VOIDmode;
3241 register const char *fmt;
3242 register int len, i;
3245 /* Two expressions are equal if they are identical copies of a shared
3246 RTX or if they are both registers with the same register number
3249 #define COMBINE_RTX_EQUAL_P(X,Y) \
3251 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3252 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3254 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3257 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3260 /* If X and FROM are the same register but different modes, they will
3261 not have been seen as equal above. However, flow.c will make a
3262 LOG_LINKS entry for that case. If we do nothing, we will try to
3263 rerecognize our original insn and, when it succeeds, we will
3264 delete the feeding insn, which is incorrect.
3266 So force this insn not to match in this (rare) case. */
3267 if (! in_dest && code == REG && GET_CODE (from) == REG
3268 && REGNO (x) == REGNO (from))
3269 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3271 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3272 of which may contain things that can be combined. */
3273 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3276 /* It is possible to have a subexpression appear twice in the insn.
3277 Suppose that FROM is a register that appears within TO.
3278 Then, after that subexpression has been scanned once by `subst',
3279 the second time it is scanned, TO may be found. If we were
3280 to scan TO here, we would find FROM within it and create a
3281 self-referent rtl structure which is completely wrong. */
3282 if (COMBINE_RTX_EQUAL_P (x, to))
3285 /* Parallel asm_operands need special attention because all of the
3286 inputs are shared across the arms. Furthermore, unsharing the
3287 rtl results in recognition failures. Failure to handle this case
3288 specially can result in circular rtl.
3290 Solve this by doing a normal pass across the first entry of the
3291 parallel, and only processing the SET_DESTs of the subsequent
3294 if (code == PARALLEL
3295 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3296 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3298 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3300 /* If this substitution failed, this whole thing fails. */
3301 if (GET_CODE (new) == CLOBBER
3302 && XEXP (new, 0) == const0_rtx)
3305 SUBST (XVECEXP (x, 0, 0), new);
3307 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3309 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3311 if (GET_CODE (dest) != REG
3312 && GET_CODE (dest) != CC0
3313 && GET_CODE (dest) != PC)
3315 new = subst (dest, from, to, 0, unique_copy);
3317 /* If this substitution failed, this whole thing fails. */
3318 if (GET_CODE (new) == CLOBBER
3319 && XEXP (new, 0) == const0_rtx)
3322 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3328 len = GET_RTX_LENGTH (code);
3329 fmt = GET_RTX_FORMAT (code);
3331 /* We don't need to process a SET_DEST that is a register, CC0,
3332 or PC, so set up to skip this common case. All other cases
3333 where we want to suppress replacing something inside a
3334 SET_SRC are handled via the IN_DEST operand. */
3336 && (GET_CODE (SET_DEST (x)) == REG
3337 || GET_CODE (SET_DEST (x)) == CC0
3338 || GET_CODE (SET_DEST (x)) == PC))
3341 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3344 op0_mode = GET_MODE (XEXP (x, 0));
3346 for (i = 0; i < len; i++)
3351 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3353 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3355 new = (unique_copy && n_occurrences
3356 ? copy_rtx (to) : to);
3361 new = subst (XVECEXP (x, i, j), from, to, 0,
3364 /* If this substitution failed, this whole thing
3366 if (GET_CODE (new) == CLOBBER
3367 && XEXP (new, 0) == const0_rtx)
3371 SUBST (XVECEXP (x, i, j), new);
3374 else if (fmt[i] == 'e')
3376 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3378 /* In general, don't install a subreg involving two
3379 modes not tieable. It can worsen register
3380 allocation, and can even make invalid reload
3381 insns, since the reg inside may need to be copied
3382 from in the outside mode, and that may be invalid
3383 if it is an fp reg copied in integer mode.
3385 We allow two exceptions to this: It is valid if
3386 it is inside another SUBREG and the mode of that
3387 SUBREG and the mode of the inside of TO is
3388 tieable and it is valid if X is a SET that copies
3391 if (GET_CODE (to) == SUBREG
3392 && ! MODES_TIEABLE_P (GET_MODE (to),
3393 GET_MODE (SUBREG_REG (to)))
3394 && ! (code == SUBREG
3395 && MODES_TIEABLE_P (GET_MODE (x),
3396 GET_MODE (SUBREG_REG (to))))
3398 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3401 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3403 #ifdef CLASS_CANNOT_CHANGE_MODE
3405 && GET_CODE (to) == REG
3406 && REGNO (to) < FIRST_PSEUDO_REGISTER
3407 && (TEST_HARD_REG_BIT
3408 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3410 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3412 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3415 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3419 /* If we are in a SET_DEST, suppress most cases unless we
3420 have gone inside a MEM, in which case we want to
3421 simplify the address. We assume here that things that
3422 are actually part of the destination have their inner
3423 parts in the first expression. This is true for SUBREG,
3424 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3425 things aside from REG and MEM that should appear in a
3427 new = subst (XEXP (x, i), from, to,
3429 && (code == SUBREG || code == STRICT_LOW_PART
3430 || code == ZERO_EXTRACT))
3432 && i == 0), unique_copy);
3434 /* If we found that we will have to reject this combination,
3435 indicate that by returning the CLOBBER ourselves, rather than
3436 an expression containing it. This will speed things up as
3437 well as prevent accidents where two CLOBBERs are considered
3438 to be equal, thus producing an incorrect simplification. */
3440 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3443 SUBST (XEXP (x, i), new);
3448 /* Try to simplify X. If the simplification changed the code, it is likely
3449 that further simplification will help, so loop, but limit the number
3450 of repetitions that will be performed. */
3452 for (i = 0; i < 4; i++)
3454 /* If X is sufficiently simple, don't bother trying to do anything
3456 if (code != CONST_INT && code != REG && code != CLOBBER)
3457 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3459 if (GET_CODE (x) == code)
3462 code = GET_CODE (x);
3464 /* We no longer know the original mode of operand 0 since we
3465 have changed the form of X) */
3466 op0_mode = VOIDmode;
3472 /* Simplify X, a piece of RTL. We just operate on the expression at the
3473 outer level; call `subst' to simplify recursively. Return the new
3476 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3477 will be the iteration even if an expression with a code different from
3478 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3481 combine_simplify_rtx (x, op0_mode, last, in_dest)
3483 enum machine_mode op0_mode;
3487 enum rtx_code code = GET_CODE (x);
3488 enum machine_mode mode = GET_MODE (x);
3492 /* If this is a commutative operation, put a constant last and a complex
3493 expression first. We don't need to do this for comparisons here. */
3494 if (GET_RTX_CLASS (code) == 'c'
3495 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3496 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3497 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3498 || (GET_CODE (XEXP (x, 0)) == SUBREG
3499 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3500 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3503 SUBST (XEXP (x, 0), XEXP (x, 1));
3504 SUBST (XEXP (x, 1), temp);
3507 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3508 sign extension of a PLUS with a constant, reverse the order of the sign
3509 extension and the addition. Note that this not the same as the original
3510 code, but overflow is undefined for signed values. Also note that the
3511 PLUS will have been partially moved "inside" the sign-extension, so that
3512 the first operand of X will really look like:
3513 (ashiftrt (plus (ashift A C4) C5) C4).
3515 (plus (ashiftrt (ashift A C4) C2) C4)
3516 and replace the first operand of X with that expression. Later parts
3517 of this function may simplify the expression further.
3519 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3520 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3521 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3523 We do this to simplify address expressions. */
3525 if ((code == PLUS || code == MINUS || code == MULT)
3526 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3527 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3528 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3529 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3530 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3531 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3532 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3533 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3534 XEXP (XEXP (XEXP (x, 0), 0), 1),
3535 XEXP (XEXP (x, 0), 1))) != 0)
3538 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3539 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3540 INTVAL (XEXP (XEXP (x, 0), 1)));
3542 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3543 INTVAL (XEXP (XEXP (x, 0), 1)));
3545 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3548 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3549 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3550 things. Check for cases where both arms are testing the same
3553 Don't do anything if all operands are very simple. */
3555 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3556 || GET_RTX_CLASS (code) == '<')
3557 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3558 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3559 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3561 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3562 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3563 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3565 || (GET_RTX_CLASS (code) == '1'
3566 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3567 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3568 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3571 rtx cond, true, false;
3573 cond = if_then_else_cond (x, &true, &false);
3575 /* If everything is a comparison, what we have is highly unlikely
3576 to be simpler, so don't use it. */
3577 && ! (GET_RTX_CLASS (code) == '<'
3578 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3579 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3581 rtx cop1 = const0_rtx;
3582 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3584 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3587 /* Simplify the alternative arms; this may collapse the true and
3588 false arms to store-flag values. */
3589 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3590 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3592 /* If true and false are not general_operands, an if_then_else
3593 is unlikely to be simpler. */
3594 if (general_operand (true, VOIDmode)
3595 && general_operand (false, VOIDmode))
3597 /* Restarting if we generate a store-flag expression will cause
3598 us to loop. Just drop through in this case. */
3600 /* If the result values are STORE_FLAG_VALUE and zero, we can
3601 just make the comparison operation. */
3602 if (true == const_true_rtx && false == const0_rtx)
3603 x = gen_binary (cond_code, mode, cond, cop1);
3604 else if (true == const0_rtx && false == const_true_rtx)
3605 x = gen_binary (reverse_condition (cond_code),
3608 /* Likewise, we can make the negate of a comparison operation
3609 if the result values are - STORE_FLAG_VALUE and zero. */
3610 else if (GET_CODE (true) == CONST_INT
3611 && INTVAL (true) == - STORE_FLAG_VALUE
3612 && false == const0_rtx)
3613 x = gen_unary (NEG, mode, mode,
3614 gen_binary (cond_code, mode, cond, cop1));
3615 else if (GET_CODE (false) == CONST_INT
3616 && INTVAL (false) == - STORE_FLAG_VALUE
3617 && true == const0_rtx)
3618 x = gen_unary (NEG, mode, mode,
3619 gen_binary (reverse_condition (cond_code),
3622 return gen_rtx_IF_THEN_ELSE (mode,
3623 gen_binary (cond_code, VOIDmode,
3627 code = GET_CODE (x);
3628 op0_mode = VOIDmode;
3633 /* Try to fold this expression in case we have constants that weren't
3636 switch (GET_RTX_CLASS (code))
3639 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3643 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3644 if (cmp_mode == VOIDmode)
3645 cmp_mode = GET_MODE (XEXP (x, 1));
3646 temp = simplify_relational_operation (code, cmp_mode,
3647 XEXP (x, 0), XEXP (x, 1));
3649 #ifdef FLOAT_STORE_FLAG_VALUE
3650 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3652 if (temp == const0_rtx)
3653 temp = CONST0_RTX (mode);
3655 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3661 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3665 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3666 XEXP (x, 1), XEXP (x, 2));
3671 x = temp, code = GET_CODE (temp);
3673 /* First see if we can apply the inverse distributive law. */
3674 if (code == PLUS || code == MINUS
3675 || code == AND || code == IOR || code == XOR)
3677 x = apply_distributive_law (x);
3678 code = GET_CODE (x);
3681 /* If CODE is an associative operation not otherwise handled, see if we
3682 can associate some operands. This can win if they are constants or
3683 if they are logically related (i.e. (a & b) & a. */
3684 if ((code == PLUS || code == MINUS
3685 || code == MULT || code == AND || code == IOR || code == XOR
3686 || code == DIV || code == UDIV
3687 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3688 && INTEGRAL_MODE_P (mode))
3690 if (GET_CODE (XEXP (x, 0)) == code)
3692 rtx other = XEXP (XEXP (x, 0), 0);
3693 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3694 rtx inner_op1 = XEXP (x, 1);
3697 /* Make sure we pass the constant operand if any as the second
3698 one if this is a commutative operation. */
3699 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3701 rtx tem = inner_op0;
3702 inner_op0 = inner_op1;
3705 inner = simplify_binary_operation (code == MINUS ? PLUS
3706 : code == DIV ? MULT
3707 : code == UDIV ? MULT
3709 mode, inner_op0, inner_op1);
3711 /* For commutative operations, try the other pair if that one
3713 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3715 other = XEXP (XEXP (x, 0), 1);
3716 inner = simplify_binary_operation (code, mode,
3717 XEXP (XEXP (x, 0), 0),
3722 return gen_binary (code, mode, other, inner);
3726 /* A little bit of algebraic simplification here. */
3730 /* Ensure that our address has any ASHIFTs converted to MULT in case
3731 address-recognizing predicates are called later. */
3732 temp = make_compound_operation (XEXP (x, 0), MEM);
3733 SUBST (XEXP (x, 0), temp);
3737 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3738 is paradoxical. If we can't do that safely, then it becomes
3739 something nonsensical so that this combination won't take place. */
3741 if (GET_CODE (SUBREG_REG (x)) == MEM
3742 && (GET_MODE_SIZE (mode)
3743 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3745 rtx inner = SUBREG_REG (x);
3746 int endian_offset = 0;
3747 /* Don't change the mode of the MEM
3748 if that would change the meaning of the address. */
3749 if (MEM_VOLATILE_P (SUBREG_REG (x))
3750 || mode_dependent_address_p (XEXP (inner, 0)))
3751 return gen_rtx_CLOBBER (mode, const0_rtx);
3753 if (BYTES_BIG_ENDIAN)
3755 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3756 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3757 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3758 endian_offset -= (UNITS_PER_WORD
3759 - GET_MODE_SIZE (GET_MODE (inner)));
3761 /* Note if the plus_constant doesn't make a valid address
3762 then this combination won't be accepted. */
3763 x = gen_rtx_MEM (mode,
3764 plus_constant (XEXP (inner, 0),
3765 (SUBREG_WORD (x) * UNITS_PER_WORD
3767 MEM_COPY_ATTRIBUTES (x, inner);
3771 /* If we are in a SET_DEST, these other cases can't apply. */
3775 /* Changing mode twice with SUBREG => just change it once,
3776 or not at all if changing back to starting mode. */
3777 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3779 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3780 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3781 return SUBREG_REG (SUBREG_REG (x));
3783 SUBST_INT (SUBREG_WORD (x),
3784 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3785 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3788 /* SUBREG of a hard register => just change the register number
3789 and/or mode. If the hard register is not valid in that mode,
3790 suppress this combination. If the hard register is the stack,
3791 frame, or argument pointer, leave this as a SUBREG. */
3793 if (GET_CODE (SUBREG_REG (x)) == REG
3794 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3795 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3796 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3797 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3799 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3800 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3802 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3804 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3806 return gen_rtx_REG (mode,
3807 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3809 return gen_rtx_CLOBBER (mode, const0_rtx);
3812 /* For a constant, try to pick up the part we want. Handle a full
3813 word and low-order part. Only do this if we are narrowing
3814 the constant; if it is being widened, we have no idea what
3815 the extra bits will have been set to. */
3817 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3818 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3819 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3820 && GET_MODE_CLASS (mode) == MODE_INT)
3822 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3828 /* If we want a subreg of a constant, at offset 0,
3829 take the low bits. On a little-endian machine, that's
3830 always valid. On a big-endian machine, it's valid
3831 only if the constant's mode fits in one word. Note that we
3832 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3833 if (CONSTANT_P (SUBREG_REG (x))
3834 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3835 || ! WORDS_BIG_ENDIAN)
3836 ? SUBREG_WORD (x) == 0
3838 == ((GET_MODE_SIZE (op0_mode)
3839 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3841 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3842 && (! WORDS_BIG_ENDIAN
3843 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3844 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3846 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3847 since we are saying that the high bits don't matter. */
3848 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3849 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3851 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3852 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3853 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3854 return SUBREG_REG (x);
3857 /* Note that we cannot do any narrowing for non-constants since
3858 we might have been counting on using the fact that some bits were
3859 zero. We now do this in the SET. */
3864 /* (not (plus X -1)) can become (neg X). */
3865 if (GET_CODE (XEXP (x, 0)) == PLUS
3866 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3867 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3869 /* Similarly, (not (neg X)) is (plus X -1). */
3870 if (GET_CODE (XEXP (x, 0)) == NEG)
3871 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3874 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3875 if (GET_CODE (XEXP (x, 0)) == XOR
3876 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3877 && (temp = simplify_unary_operation (NOT, mode,
3878 XEXP (XEXP (x, 0), 1),
3880 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3882 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3883 other than 1, but that is not valid. We could do a similar
3884 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3885 but this doesn't seem common enough to bother with. */
3886 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3887 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3888 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3889 XEXP (XEXP (x, 0), 1));
3891 if (GET_CODE (XEXP (x, 0)) == SUBREG
3892 && subreg_lowpart_p (XEXP (x, 0))
3893 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3894 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3895 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3896 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3898 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3900 x = gen_rtx_ROTATE (inner_mode,
3901 gen_unary (NOT, inner_mode, inner_mode,
3903 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3904 return gen_lowpart_for_combine (mode, x);
3907 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3908 reversing the comparison code if valid. */
3909 if (STORE_FLAG_VALUE == -1
3910 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3911 && reversible_comparison_p (XEXP (x, 0)))
3912 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3913 mode, XEXP (XEXP (x, 0), 0),
3914 XEXP (XEXP (x, 0), 1));
3916 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3917 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3918 perform the above simplification. */
3920 if (STORE_FLAG_VALUE == -1
3921 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3922 && XEXP (x, 1) == const1_rtx
3923 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3924 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3925 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3927 /* Apply De Morgan's laws to reduce number of patterns for machines
3928 with negating logical insns (and-not, nand, etc.). If result has
3929 only one NOT, put it first, since that is how the patterns are
3932 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3934 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3936 if (GET_CODE (in1) == NOT)
3937 in1 = XEXP (in1, 0);
3939 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3941 if (GET_CODE (in2) == NOT)
3942 in2 = XEXP (in2, 0);
3943 else if (GET_CODE (in2) == CONST_INT
3944 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3945 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3947 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3949 if (GET_CODE (in2) == NOT)
3952 in2 = in1; in1 = tem;
3955 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3961 /* (neg (plus X 1)) can become (not X). */
3962 if (GET_CODE (XEXP (x, 0)) == PLUS
3963 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3964 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3966 /* Similarly, (neg (not X)) is (plus X 1). */
3967 if (GET_CODE (XEXP (x, 0)) == NOT)
3968 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3970 /* (neg (minus X Y)) can become (minus Y X). */
3971 if (GET_CODE (XEXP (x, 0)) == MINUS
3972 && (! FLOAT_MODE_P (mode)
3973 /* x-y != -(y-x) with IEEE floating point. */
3974 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3976 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3977 XEXP (XEXP (x, 0), 0));
3979 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3980 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3981 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3982 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3984 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3985 if we can then eliminate the NEG (e.g.,
3986 if the operand is a constant). */
3988 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3990 temp = simplify_unary_operation (NEG, mode,
3991 XEXP (XEXP (x, 0), 0), mode);
3994 SUBST (XEXP (XEXP (x, 0), 0), temp);
3999 temp = expand_compound_operation (XEXP (x, 0));
4001 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4002 replaced by (lshiftrt X C). This will convert
4003 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4005 if (GET_CODE (temp) == ASHIFTRT
4006 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4007 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4008 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4009 INTVAL (XEXP (temp, 1)));
4011 /* If X has only a single bit that might be nonzero, say, bit I, convert
4012 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4013 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4014 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4015 or a SUBREG of one since we'd be making the expression more
4016 complex if it was just a register. */
4018 if (GET_CODE (temp) != REG
4019 && ! (GET_CODE (temp) == SUBREG
4020 && GET_CODE (SUBREG_REG (temp)) == REG)
4021 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4023 rtx temp1 = simplify_shift_const
4024 (NULL_RTX, ASHIFTRT, mode,
4025 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4026 GET_MODE_BITSIZE (mode) - 1 - i),
4027 GET_MODE_BITSIZE (mode) - 1 - i);
4029 /* If all we did was surround TEMP with the two shifts, we
4030 haven't improved anything, so don't use it. Otherwise,
4031 we are better off with TEMP1. */
4032 if (GET_CODE (temp1) != ASHIFTRT
4033 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4034 || XEXP (XEXP (temp1, 0), 0) != temp)
4040 /* We can't handle truncation to a partial integer mode here
4041 because we don't know the real bitsize of the partial
4043 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4046 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4047 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4048 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4050 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4051 GET_MODE_MASK (mode), NULL_RTX, 0));
4053 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4054 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4055 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4056 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4057 return XEXP (XEXP (x, 0), 0);
4059 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4060 (OP:SI foo:SI) if OP is NEG or ABS. */
4061 if ((GET_CODE (XEXP (x, 0)) == ABS
4062 || GET_CODE (XEXP (x, 0)) == NEG)
4063 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4064 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4065 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4066 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4067 XEXP (XEXP (XEXP (x, 0), 0), 0));
4069 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4071 if (GET_CODE (XEXP (x, 0)) == SUBREG
4072 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4073 && subreg_lowpart_p (XEXP (x, 0)))
4074 return SUBREG_REG (XEXP (x, 0));
4076 /* If we know that the value is already truncated, we can
4077 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4078 is nonzero for the corresponding modes. But don't do this
4079 for an (LSHIFTRT (MULT ...)) since this will cause problems
4080 with the umulXi3_highpart patterns. */
4081 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4082 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4083 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4084 >= GET_MODE_BITSIZE (mode) + 1
4085 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4086 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4087 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4089 /* A truncate of a comparison can be replaced with a subreg if
4090 STORE_FLAG_VALUE permits. This is like the previous test,
4091 but it works even if the comparison is done in a mode larger
4092 than HOST_BITS_PER_WIDE_INT. */
4093 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4094 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4095 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4096 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4098 /* Similarly, a truncate of a register whose value is a
4099 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4101 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4102 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4103 && (temp = get_last_value (XEXP (x, 0)))
4104 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4105 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4109 case FLOAT_TRUNCATE:
4110 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4111 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4112 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4113 return XEXP (XEXP (x, 0), 0);
4115 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4116 (OP:SF foo:SF) if OP is NEG or ABS. */
4117 if ((GET_CODE (XEXP (x, 0)) == ABS
4118 || GET_CODE (XEXP (x, 0)) == NEG)
4119 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4120 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4121 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4122 XEXP (XEXP (XEXP (x, 0), 0), 0));
4124 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4125 is (float_truncate:SF x). */
4126 if (GET_CODE (XEXP (x, 0)) == SUBREG
4127 && subreg_lowpart_p (XEXP (x, 0))
4128 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4129 return SUBREG_REG (XEXP (x, 0));
4134 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4135 using cc0, in which case we want to leave it as a COMPARE
4136 so we can distinguish it from a register-register-copy. */
4137 if (XEXP (x, 1) == const0_rtx)
4140 /* In IEEE floating point, x-0 is not the same as x. */
4141 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4142 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4144 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4150 /* (const (const X)) can become (const X). Do it this way rather than
4151 returning the inner CONST since CONST can be shared with a
4153 if (GET_CODE (XEXP (x, 0)) == CONST)
4154 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4159 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4160 can add in an offset. find_split_point will split this address up
4161 again if it doesn't match. */
4162 if (GET_CODE (XEXP (x, 0)) == HIGH
4163 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4169 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4170 outermost. That's because that's the way indexed addresses are
4171 supposed to appear. This code used to check many more cases, but
4172 they are now checked elsewhere. */
4173 if (GET_CODE (XEXP (x, 0)) == PLUS
4174 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4175 return gen_binary (PLUS, mode,
4176 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4178 XEXP (XEXP (x, 0), 1));
4180 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4181 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4182 bit-field and can be replaced by either a sign_extend or a
4183 sign_extract. The `and' may be a zero_extend and the two
4184 <c>, -<c> constants may be reversed. */
4185 if (GET_CODE (XEXP (x, 0)) == XOR
4186 && GET_CODE (XEXP (x, 1)) == CONST_INT
4187 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4188 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4189 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4190 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4191 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4192 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4193 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4194 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4195 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4196 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4197 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4198 == (unsigned int) i + 1))))
4199 return simplify_shift_const
4200 (NULL_RTX, ASHIFTRT, mode,
4201 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4202 XEXP (XEXP (XEXP (x, 0), 0), 0),
4203 GET_MODE_BITSIZE (mode) - (i + 1)),
4204 GET_MODE_BITSIZE (mode) - (i + 1));
4206 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4207 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4208 is 1. This produces better code than the alternative immediately
4210 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4211 && reversible_comparison_p (XEXP (x, 0))
4212 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4213 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4215 gen_unary (NEG, mode, mode,
4216 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4217 mode, XEXP (XEXP (x, 0), 0),
4218 XEXP (XEXP (x, 0), 1)));
4220 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4221 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4222 the bitsize of the mode - 1. This allows simplification of
4223 "a = (b & 8) == 0;" */
4224 if (XEXP (x, 1) == constm1_rtx
4225 && GET_CODE (XEXP (x, 0)) != REG
4226 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4227 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4228 && nonzero_bits (XEXP (x, 0), mode) == 1)
4229 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4230 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4231 gen_rtx_combine (XOR, mode,
4232 XEXP (x, 0), const1_rtx),
4233 GET_MODE_BITSIZE (mode) - 1),
4234 GET_MODE_BITSIZE (mode) - 1);
4236 /* If we are adding two things that have no bits in common, convert
4237 the addition into an IOR. This will often be further simplified,
4238 for example in cases like ((a & 1) + (a & 2)), which can
4241 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4242 && (nonzero_bits (XEXP (x, 0), mode)
4243 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4245 /* Try to simplify the expression further. */
4246 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4247 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4249 /* If we could, great. If not, do not go ahead with the IOR
4250 replacement, since PLUS appears in many special purpose
4251 address arithmetic instructions. */
4252 if (GET_CODE (temp) != CLOBBER && temp != tor)
4258 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4259 by reversing the comparison code if valid. */
4260 if (STORE_FLAG_VALUE == 1
4261 && XEXP (x, 0) == const1_rtx
4262 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4263 && reversible_comparison_p (XEXP (x, 1)))
4264 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4265 mode, XEXP (XEXP (x, 1), 0),
4266 XEXP (XEXP (x, 1), 1));
4268 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4269 (and <foo> (const_int pow2-1)) */
4270 if (GET_CODE (XEXP (x, 1)) == AND
4271 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4272 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4273 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4274 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4275 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4277 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4279 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4280 return gen_binary (MINUS, mode,
4281 gen_binary (MINUS, mode, XEXP (x, 0),
4282 XEXP (XEXP (x, 1), 0)),
4283 XEXP (XEXP (x, 1), 1));
4287 /* If we have (mult (plus A B) C), apply the distributive law and then
4288 the inverse distributive law to see if things simplify. This
4289 occurs mostly in addresses, often when unrolling loops. */
4291 if (GET_CODE (XEXP (x, 0)) == PLUS)
4293 x = apply_distributive_law
4294 (gen_binary (PLUS, mode,
4295 gen_binary (MULT, mode,
4296 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4297 gen_binary (MULT, mode,
4298 XEXP (XEXP (x, 0), 1),
4299 copy_rtx (XEXP (x, 1)))));
4301 if (GET_CODE (x) != MULT)
4307 /* If this is a divide by a power of two, treat it as a shift if
4308 its first operand is a shift. */
4309 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4310 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4311 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4312 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4313 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4314 || GET_CODE (XEXP (x, 0)) == ROTATE
4315 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4316 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4320 case GT: case GTU: case GE: case GEU:
4321 case LT: case LTU: case LE: case LEU:
4322 /* If the first operand is a condition code, we can't do anything
4324 if (GET_CODE (XEXP (x, 0)) == COMPARE
4325 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4327 && XEXP (x, 0) != cc0_rtx
4331 rtx op0 = XEXP (x, 0);
4332 rtx op1 = XEXP (x, 1);
4333 enum rtx_code new_code;
4335 if (GET_CODE (op0) == COMPARE)
4336 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4338 /* Simplify our comparison, if possible. */
4339 new_code = simplify_comparison (code, &op0, &op1);
4341 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4342 if only the low-order bit is possibly nonzero in X (such as when
4343 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4344 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4345 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4348 Remove any ZERO_EXTRACT we made when thinking this was a
4349 comparison. It may now be simpler to use, e.g., an AND. If a
4350 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4351 the call to make_compound_operation in the SET case. */
4353 if (STORE_FLAG_VALUE == 1
4354 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4355 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4356 return gen_lowpart_for_combine (mode,
4357 expand_compound_operation (op0));
4359 else if (STORE_FLAG_VALUE == 1
4360 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4361 && op1 == const0_rtx
4362 && (num_sign_bit_copies (op0, mode)
4363 == GET_MODE_BITSIZE (mode)))
4365 op0 = expand_compound_operation (op0);
4366 return gen_unary (NEG, mode, mode,
4367 gen_lowpart_for_combine (mode, op0));
4370 else if (STORE_FLAG_VALUE == 1
4371 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4372 && op1 == const0_rtx
4373 && nonzero_bits (op0, mode) == 1)
4375 op0 = expand_compound_operation (op0);
4376 return gen_binary (XOR, mode,
4377 gen_lowpart_for_combine (mode, op0),
4381 else if (STORE_FLAG_VALUE == 1
4382 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4383 && op1 == const0_rtx
4384 && (num_sign_bit_copies (op0, mode)
4385 == GET_MODE_BITSIZE (mode)))
4387 op0 = expand_compound_operation (op0);
4388 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4391 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4393 if (STORE_FLAG_VALUE == -1
4394 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4395 && op1 == const0_rtx
4396 && (num_sign_bit_copies (op0, mode)
4397 == GET_MODE_BITSIZE (mode)))
4398 return gen_lowpart_for_combine (mode,
4399 expand_compound_operation (op0));
4401 else if (STORE_FLAG_VALUE == -1
4402 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4403 && op1 == const0_rtx
4404 && nonzero_bits (op0, mode) == 1)
4406 op0 = expand_compound_operation (op0);
4407 return gen_unary (NEG, mode, mode,
4408 gen_lowpart_for_combine (mode, op0));
4411 else if (STORE_FLAG_VALUE == -1
4412 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4413 && op1 == const0_rtx
4414 && (num_sign_bit_copies (op0, mode)
4415 == GET_MODE_BITSIZE (mode)))
4417 op0 = expand_compound_operation (op0);
4418 return gen_unary (NOT, mode, mode,
4419 gen_lowpart_for_combine (mode, op0));
4422 /* If X is 0/1, (eq X 0) is X-1. */
4423 else if (STORE_FLAG_VALUE == -1
4424 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4425 && op1 == const0_rtx
4426 && nonzero_bits (op0, mode) == 1)
4428 op0 = expand_compound_operation (op0);
4429 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4432 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4433 one bit that might be nonzero, we can convert (ne x 0) to
4434 (ashift x c) where C puts the bit in the sign bit. Remove any
4435 AND with STORE_FLAG_VALUE when we are done, since we are only
4436 going to test the sign bit. */
4437 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4438 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4439 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4440 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4441 && op1 == const0_rtx
4442 && mode == GET_MODE (op0)
4443 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4445 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4446 expand_compound_operation (op0),
4447 GET_MODE_BITSIZE (mode) - 1 - i);
4448 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4454 /* If the code changed, return a whole new comparison. */
4455 if (new_code != code)
4456 return gen_rtx_combine (new_code, mode, op0, op1);
4458 /* Otherwise, keep this operation, but maybe change its operands.
4459 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4460 SUBST (XEXP (x, 0), op0);
4461 SUBST (XEXP (x, 1), op1);
4466 return simplify_if_then_else (x);
4472 /* If we are processing SET_DEST, we are done. */
4476 return expand_compound_operation (x);
4479 return simplify_set (x);
4484 return simplify_logical (x, last);
4487 /* (abs (neg <foo>)) -> (abs <foo>) */
4488 if (GET_CODE (XEXP (x, 0)) == NEG)
4489 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4491 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4493 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4496 /* If operand is something known to be positive, ignore the ABS. */
4497 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4498 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4499 <= HOST_BITS_PER_WIDE_INT)
4500 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4501 & ((HOST_WIDE_INT) 1
4502 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4507 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4508 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4509 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4514 /* (ffs (*_extend <X>)) = (ffs <X>) */
4515 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4516 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4517 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4521 /* (float (sign_extend <X>)) = (float <X>). */
4522 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4523 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4531 /* If this is a shift by a constant amount, simplify it. */
4532 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4533 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4534 INTVAL (XEXP (x, 1)));
4536 #ifdef SHIFT_COUNT_TRUNCATED
4537 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4539 force_to_mode (XEXP (x, 1), GET_MODE (x),
4541 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4555 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4558 simplify_if_then_else (x)
4561 enum machine_mode mode = GET_MODE (x);
4562 rtx cond = XEXP (x, 0);
4563 rtx true = XEXP (x, 1);
4564 rtx false = XEXP (x, 2);
4565 enum rtx_code true_code = GET_CODE (cond);
4566 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4570 /* Simplify storing of the truth value. */
4571 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4572 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4574 /* Also when the truth value has to be reversed. */
4575 if (comparison_p && reversible_comparison_p (cond)
4576 && true == const0_rtx && false == const_true_rtx)
4577 return gen_binary (reverse_condition (true_code),
4578 mode, XEXP (cond, 0), XEXP (cond, 1));
4580 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4581 in it is being compared against certain values. Get the true and false
4582 comparisons and see if that says anything about the value of each arm. */
4584 if (comparison_p && reversible_comparison_p (cond)
4585 && GET_CODE (XEXP (cond, 0)) == REG)
4588 rtx from = XEXP (cond, 0);
4589 enum rtx_code false_code = reverse_condition (true_code);
4590 rtx true_val = XEXP (cond, 1);
4591 rtx false_val = true_val;
4594 /* If FALSE_CODE is EQ, swap the codes and arms. */
4596 if (false_code == EQ)
4598 swapped = 1, true_code = EQ, false_code = NE;
4599 temp = true, true = false, false = temp;
4602 /* If we are comparing against zero and the expression being tested has
4603 only a single bit that might be nonzero, that is its value when it is
4604 not equal to zero. Similarly if it is known to be -1 or 0. */
4606 if (true_code == EQ && true_val == const0_rtx
4607 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4608 false_code = EQ, false_val = GEN_INT (nzb);
4609 else if (true_code == EQ && true_val == const0_rtx
4610 && (num_sign_bit_copies (from, GET_MODE (from))
4611 == GET_MODE_BITSIZE (GET_MODE (from))))
4612 false_code = EQ, false_val = constm1_rtx;
4614 /* Now simplify an arm if we know the value of the register in the
4615 branch and it is used in the arm. Be careful due to the potential
4616 of locally-shared RTL. */
4618 if (reg_mentioned_p (from, true))
4619 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4620 pc_rtx, pc_rtx, 0, 0);
4621 if (reg_mentioned_p (from, false))
4622 false = subst (known_cond (copy_rtx (false), false_code,
4624 pc_rtx, pc_rtx, 0, 0);
4626 SUBST (XEXP (x, 1), swapped ? false : true);
4627 SUBST (XEXP (x, 2), swapped ? true : false);
4629 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4632 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4633 reversed, do so to avoid needing two sets of patterns for
4634 subtract-and-branch insns. Similarly if we have a constant in the true
4635 arm, the false arm is the same as the first operand of the comparison, or
4636 the false arm is more complicated than the true arm. */
4638 if (comparison_p && reversible_comparison_p (cond)
4640 || (CONSTANT_P (true)
4641 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4642 || true == const0_rtx
4643 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4644 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4645 || (GET_CODE (true) == SUBREG
4646 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4647 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4648 || reg_mentioned_p (true, false)
4649 || rtx_equal_p (false, XEXP (cond, 0))))
4651 true_code = reverse_condition (true_code);
4653 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4656 SUBST (XEXP (x, 1), false);
4657 SUBST (XEXP (x, 2), true);
4659 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4661 /* It is possible that the conditional has been simplified out. */
4662 true_code = GET_CODE (cond);
4663 comparison_p = GET_RTX_CLASS (true_code) == '<';
4666 /* If the two arms are identical, we don't need the comparison. */
4668 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4671 /* Convert a == b ? b : a to "a". */
4672 if (true_code == EQ && ! side_effects_p (cond)
4673 && rtx_equal_p (XEXP (cond, 0), false)
4674 && rtx_equal_p (XEXP (cond, 1), true))
4676 else if (true_code == NE && ! side_effects_p (cond)
4677 && rtx_equal_p (XEXP (cond, 0), true)
4678 && rtx_equal_p (XEXP (cond, 1), false))
4681 /* Look for cases where we have (abs x) or (neg (abs X)). */
4683 if (GET_MODE_CLASS (mode) == MODE_INT
4684 && GET_CODE (false) == NEG
4685 && rtx_equal_p (true, XEXP (false, 0))
4687 && rtx_equal_p (true, XEXP (cond, 0))
4688 && ! side_effects_p (true))
4693 return gen_unary (ABS, mode, mode, true);
4696 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4701 /* Look for MIN or MAX. */
4703 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4705 && rtx_equal_p (XEXP (cond, 0), true)
4706 && rtx_equal_p (XEXP (cond, 1), false)
4707 && ! side_effects_p (cond))
4712 return gen_binary (SMAX, mode, true, false);
4715 return gen_binary (SMIN, mode, true, false);
4718 return gen_binary (UMAX, mode, true, false);
4721 return gen_binary (UMIN, mode, true, false);
4726 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4727 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4728 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4729 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4730 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4731 neither 1 or -1, but it isn't worth checking for. */
4733 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4734 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4736 rtx t = make_compound_operation (true, SET);
4737 rtx f = make_compound_operation (false, SET);
4738 rtx cond_op0 = XEXP (cond, 0);
4739 rtx cond_op1 = XEXP (cond, 1);
4740 enum rtx_code op = NIL, extend_op = NIL;
4741 enum machine_mode m = mode;
4742 rtx z = 0, c1 = NULL_RTX;
4744 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4745 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4746 || GET_CODE (t) == ASHIFT
4747 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4748 && rtx_equal_p (XEXP (t, 0), f))
4749 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4751 /* If an identity-zero op is commutative, check whether there
4752 would be a match if we swapped the operands. */
4753 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4754 || GET_CODE (t) == XOR)
4755 && rtx_equal_p (XEXP (t, 1), f))
4756 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4757 else if (GET_CODE (t) == SIGN_EXTEND
4758 && (GET_CODE (XEXP (t, 0)) == PLUS
4759 || GET_CODE (XEXP (t, 0)) == MINUS
4760 || GET_CODE (XEXP (t, 0)) == IOR
4761 || GET_CODE (XEXP (t, 0)) == XOR
4762 || GET_CODE (XEXP (t, 0)) == ASHIFT
4763 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4764 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4765 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4766 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4767 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4768 && (num_sign_bit_copies (f, GET_MODE (f))
4769 > (GET_MODE_BITSIZE (mode)
4770 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4772 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4773 extend_op = SIGN_EXTEND;
4774 m = GET_MODE (XEXP (t, 0));
4776 else if (GET_CODE (t) == SIGN_EXTEND
4777 && (GET_CODE (XEXP (t, 0)) == PLUS
4778 || GET_CODE (XEXP (t, 0)) == IOR
4779 || GET_CODE (XEXP (t, 0)) == XOR)
4780 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4781 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4782 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4783 && (num_sign_bit_copies (f, GET_MODE (f))
4784 > (GET_MODE_BITSIZE (mode)
4785 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4787 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4788 extend_op = SIGN_EXTEND;
4789 m = GET_MODE (XEXP (t, 0));
4791 else if (GET_CODE (t) == ZERO_EXTEND
4792 && (GET_CODE (XEXP (t, 0)) == PLUS
4793 || GET_CODE (XEXP (t, 0)) == MINUS
4794 || GET_CODE (XEXP (t, 0)) == IOR
4795 || GET_CODE (XEXP (t, 0)) == XOR
4796 || GET_CODE (XEXP (t, 0)) == ASHIFT
4797 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4798 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4799 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4800 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4801 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4802 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4803 && ((nonzero_bits (f, GET_MODE (f))
4804 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4807 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4808 extend_op = ZERO_EXTEND;
4809 m = GET_MODE (XEXP (t, 0));
4811 else if (GET_CODE (t) == ZERO_EXTEND
4812 && (GET_CODE (XEXP (t, 0)) == PLUS
4813 || GET_CODE (XEXP (t, 0)) == IOR
4814 || GET_CODE (XEXP (t, 0)) == XOR)
4815 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4816 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4817 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4818 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4819 && ((nonzero_bits (f, GET_MODE (f))
4820 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4823 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4824 extend_op = ZERO_EXTEND;
4825 m = GET_MODE (XEXP (t, 0));
4830 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4831 pc_rtx, pc_rtx, 0, 0);
4832 temp = gen_binary (MULT, m, temp,
4833 gen_binary (MULT, m, c1, const_true_rtx));
4834 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4835 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4837 if (extend_op != NIL)
4838 temp = gen_unary (extend_op, mode, m, temp);
4844 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4845 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4846 negation of a single bit, we can convert this operation to a shift. We
4847 can actually do this more generally, but it doesn't seem worth it. */
4849 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4850 && false == const0_rtx && GET_CODE (true) == CONST_INT
4851 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4852 && (i = exact_log2 (INTVAL (true))) >= 0)
4853 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4854 == GET_MODE_BITSIZE (mode))
4855 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4857 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4858 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4863 /* Simplify X, a SET expression. Return the new expression. */
4869 rtx src = SET_SRC (x);
4870 rtx dest = SET_DEST (x);
4871 enum machine_mode mode
4872 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4876 /* (set (pc) (return)) gets written as (return). */
4877 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4880 /* Now that we know for sure which bits of SRC we are using, see if we can
4881 simplify the expression for the object knowing that we only need the
4884 if (GET_MODE_CLASS (mode) == MODE_INT)
4886 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4887 SUBST (SET_SRC (x), src);
4890 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4891 the comparison result and try to simplify it unless we already have used
4892 undobuf.other_insn. */
4893 if ((GET_CODE (src) == COMPARE
4898 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4899 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4900 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4901 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4903 enum rtx_code old_code = GET_CODE (*cc_use);
4904 enum rtx_code new_code;
4906 int other_changed = 0;
4907 enum machine_mode compare_mode = GET_MODE (dest);
4909 if (GET_CODE (src) == COMPARE)
4910 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4912 op0 = src, op1 = const0_rtx;
4914 /* Simplify our comparison, if possible. */
4915 new_code = simplify_comparison (old_code, &op0, &op1);
4917 #ifdef EXTRA_CC_MODES
4918 /* If this machine has CC modes other than CCmode, check to see if we
4919 need to use a different CC mode here. */
4920 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4921 #endif /* EXTRA_CC_MODES */
4923 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4924 /* If the mode changed, we have to change SET_DEST, the mode in the
4925 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4926 a hard register, just build new versions with the proper mode. If it
4927 is a pseudo, we lose unless it is only time we set the pseudo, in
4928 which case we can safely change its mode. */
4929 if (compare_mode != GET_MODE (dest))
4931 unsigned int regno = REGNO (dest);
4932 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4934 if (regno < FIRST_PSEUDO_REGISTER
4935 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4937 if (regno >= FIRST_PSEUDO_REGISTER)
4938 SUBST (regno_reg_rtx[regno], new_dest);
4940 SUBST (SET_DEST (x), new_dest);
4941 SUBST (XEXP (*cc_use, 0), new_dest);
4949 /* If the code changed, we have to build a new comparison in
4950 undobuf.other_insn. */
4951 if (new_code != old_code)
4953 unsigned HOST_WIDE_INT mask;
4955 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4958 /* If the only change we made was to change an EQ into an NE or
4959 vice versa, OP0 has only one bit that might be nonzero, and OP1
4960 is zero, check if changing the user of the condition code will
4961 produce a valid insn. If it won't, we can keep the original code
4962 in that insn by surrounding our operation with an XOR. */
4964 if (((old_code == NE && new_code == EQ)
4965 || (old_code == EQ && new_code == NE))
4966 && ! other_changed && op1 == const0_rtx
4967 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4968 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4970 rtx pat = PATTERN (other_insn), note = 0;
4972 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4973 && ! check_asm_operands (pat)))
4975 PUT_CODE (*cc_use, old_code);
4978 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4986 undobuf.other_insn = other_insn;
4989 /* If we are now comparing against zero, change our source if
4990 needed. If we do not use cc0, we always have a COMPARE. */
4991 if (op1 == const0_rtx && dest == cc0_rtx)
4993 SUBST (SET_SRC (x), op0);
4999 /* Otherwise, if we didn't previously have a COMPARE in the
5000 correct mode, we need one. */
5001 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5004 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5009 /* Otherwise, update the COMPARE if needed. */
5010 SUBST (XEXP (src, 0), op0);
5011 SUBST (XEXP (src, 1), op1);
5016 /* Get SET_SRC in a form where we have placed back any
5017 compound expressions. Then do the checks below. */
5018 src = make_compound_operation (src, SET);
5019 SUBST (SET_SRC (x), src);
5022 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5023 and X being a REG or (subreg (reg)), we may be able to convert this to
5024 (set (subreg:m2 x) (op)).
5026 We can always do this if M1 is narrower than M2 because that means that
5027 we only care about the low bits of the result.
5029 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5030 perform a narrower operation than requested since the high-order bits will
5031 be undefined. On machine where it is defined, this transformation is safe
5032 as long as M1 and M2 have the same number of words. */
5034 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5035 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5036 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5038 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5039 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5040 #ifndef WORD_REGISTER_OPERATIONS
5041 && (GET_MODE_SIZE (GET_MODE (src))
5042 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5044 #ifdef CLASS_CANNOT_CHANGE_MODE
5045 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5046 && (TEST_HARD_REG_BIT
5047 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5049 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5050 GET_MODE (SUBREG_REG (src))))
5052 && (GET_CODE (dest) == REG
5053 || (GET_CODE (dest) == SUBREG
5054 && GET_CODE (SUBREG_REG (dest)) == REG)))
5056 SUBST (SET_DEST (x),
5057 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5059 SUBST (SET_SRC (x), SUBREG_REG (src));
5061 src = SET_SRC (x), dest = SET_DEST (x);
5064 #ifdef LOAD_EXTEND_OP
5065 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5066 would require a paradoxical subreg. Replace the subreg with a
5067 zero_extend to avoid the reload that would otherwise be required. */
5069 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5070 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5071 && SUBREG_WORD (src) == 0
5072 && (GET_MODE_SIZE (GET_MODE (src))
5073 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5074 && GET_CODE (SUBREG_REG (src)) == MEM)
5077 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5078 GET_MODE (src), XEXP (src, 0)));
5084 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5085 are comparing an item known to be 0 or -1 against 0, use a logical
5086 operation instead. Check for one of the arms being an IOR of the other
5087 arm with some value. We compute three terms to be IOR'ed together. In
5088 practice, at most two will be nonzero. Then we do the IOR's. */
5090 if (GET_CODE (dest) != PC
5091 && GET_CODE (src) == IF_THEN_ELSE
5092 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5093 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5094 && XEXP (XEXP (src, 0), 1) == const0_rtx
5095 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5096 #ifdef HAVE_conditional_move
5097 && ! can_conditionally_move_p (GET_MODE (src))
5099 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5100 GET_MODE (XEXP (XEXP (src, 0), 0)))
5101 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5102 && ! side_effects_p (src))
5104 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5105 ? XEXP (src, 1) : XEXP (src, 2));
5106 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5107 ? XEXP (src, 2) : XEXP (src, 1));
5108 rtx term1 = const0_rtx, term2, term3;
5110 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5111 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5112 else if (GET_CODE (true) == IOR
5113 && rtx_equal_p (XEXP (true, 1), false))
5114 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5115 else if (GET_CODE (false) == IOR
5116 && rtx_equal_p (XEXP (false, 0), true))
5117 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5118 else if (GET_CODE (false) == IOR
5119 && rtx_equal_p (XEXP (false, 1), true))
5120 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5122 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5123 term3 = gen_binary (AND, GET_MODE (src),
5124 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5125 XEXP (XEXP (src, 0), 0)),
5129 gen_binary (IOR, GET_MODE (src),
5130 gen_binary (IOR, GET_MODE (src), term1, term2),
5136 #ifdef HAVE_conditional_arithmetic
5137 /* If we have conditional arithmetic and the operand of a SET is
5138 a conditional expression, replace this with an IF_THEN_ELSE.
5139 We can either have a conditional expression or a MULT of that expression
5141 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5142 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5143 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5144 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5145 || (GET_CODE (XEXP (src, 0)) == MULT
5146 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5147 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5149 rtx cond = XEXP (src, 0);
5150 rtx true_val = const1_rtx;
5151 rtx false_arm, true_arm;
5153 if (GET_CODE (cond) == MULT)
5155 true_val = XEXP (cond, 1);
5156 cond = XEXP (cond, 0);
5159 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5161 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5162 GET_MODE (XEXP (src, 0)), true_val);
5163 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5164 GET_MODE (XEXP (src, 0)), const0_rtx);
5168 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5169 true_val, XEXP (src, 1));
5170 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5171 const0_rtx, XEXP (src, 1));
5174 /* Canonicalize if true_arm is the simpler one. */
5175 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5176 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5177 && reversible_comparison_p (cond))
5179 rtx temp = true_arm;
5181 true_arm = false_arm;
5184 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5185 GET_MODE (cond), XEXP (cond, 0),
5189 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5190 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5193 true_arm, false_arm);
5194 SUBST (SET_SRC (x), src);
5198 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5199 whole thing fail. */
5200 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5202 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5205 /* Convert this into a field assignment operation, if possible. */
5206 return make_field_assignment (x);
5209 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5210 result. LAST is nonzero if this is the last retry. */
5213 simplify_logical (x, last)
5217 enum machine_mode mode = GET_MODE (x);
5218 rtx op0 = XEXP (x, 0);
5219 rtx op1 = XEXP (x, 1);
5221 switch (GET_CODE (x))
5224 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5225 insn (and may simplify more). */
5226 if (GET_CODE (op0) == XOR
5227 && rtx_equal_p (XEXP (op0, 0), op1)
5228 && ! side_effects_p (op1))
5229 x = gen_binary (AND, mode,
5230 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5232 if (GET_CODE (op0) == XOR
5233 && rtx_equal_p (XEXP (op0, 1), op1)
5234 && ! side_effects_p (op1))
5235 x = gen_binary (AND, mode,
5236 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5238 /* Similarly for (~ (A ^ B)) & A. */
5239 if (GET_CODE (op0) == NOT
5240 && GET_CODE (XEXP (op0, 0)) == XOR
5241 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5242 && ! side_effects_p (op1))
5243 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5245 if (GET_CODE (op0) == NOT
5246 && GET_CODE (XEXP (op0, 0)) == XOR
5247 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5248 && ! side_effects_p (op1))
5249 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5251 /* We can call simplify_and_const_int only if we don't lose
5252 any (sign) bits when converting INTVAL (op1) to
5253 "unsigned HOST_WIDE_INT". */
5254 if (GET_CODE (op1) == CONST_INT
5255 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5256 || INTVAL (op1) > 0))
5258 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5260 /* If we have (ior (and (X C1) C2)) and the next restart would be
5261 the last, simplify this by making C1 as small as possible
5264 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5265 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5266 && GET_CODE (op1) == CONST_INT)
5267 return gen_binary (IOR, mode,
5268 gen_binary (AND, mode, XEXP (op0, 0),
5269 GEN_INT (INTVAL (XEXP (op0, 1))
5270 & ~ INTVAL (op1))), op1);
5272 if (GET_CODE (x) != AND)
5275 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5276 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5277 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5280 /* Convert (A | B) & A to A. */
5281 if (GET_CODE (op0) == IOR
5282 && (rtx_equal_p (XEXP (op0, 0), op1)
5283 || rtx_equal_p (XEXP (op0, 1), op1))
5284 && ! side_effects_p (XEXP (op0, 0))
5285 && ! side_effects_p (XEXP (op0, 1)))
5288 /* In the following group of tests (and those in case IOR below),
5289 we start with some combination of logical operations and apply
5290 the distributive law followed by the inverse distributive law.
5291 Most of the time, this results in no change. However, if some of
5292 the operands are the same or inverses of each other, simplifications
5295 For example, (and (ior A B) (not B)) can occur as the result of
5296 expanding a bit field assignment. When we apply the distributive
5297 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5298 which then simplifies to (and (A (not B))).
5300 If we have (and (ior A B) C), apply the distributive law and then
5301 the inverse distributive law to see if things simplify. */
5303 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5305 x = apply_distributive_law
5306 (gen_binary (GET_CODE (op0), mode,
5307 gen_binary (AND, mode, XEXP (op0, 0), op1),
5308 gen_binary (AND, mode, XEXP (op0, 1),
5310 if (GET_CODE (x) != AND)
5314 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5315 return apply_distributive_law
5316 (gen_binary (GET_CODE (op1), mode,
5317 gen_binary (AND, mode, XEXP (op1, 0), op0),
5318 gen_binary (AND, mode, XEXP (op1, 1),
5321 /* Similarly, taking advantage of the fact that
5322 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5324 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5325 return apply_distributive_law
5326 (gen_binary (XOR, mode,
5327 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5328 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5331 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5332 return apply_distributive_law
5333 (gen_binary (XOR, mode,
5334 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5335 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5339 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5340 if (GET_CODE (op1) == CONST_INT
5341 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5342 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5345 /* Convert (A & B) | A to A. */
5346 if (GET_CODE (op0) == AND
5347 && (rtx_equal_p (XEXP (op0, 0), op1)
5348 || rtx_equal_p (XEXP (op0, 1), op1))
5349 && ! side_effects_p (XEXP (op0, 0))
5350 && ! side_effects_p (XEXP (op0, 1)))
5353 /* If we have (ior (and A B) C), apply the distributive law and then
5354 the inverse distributive law to see if things simplify. */
5356 if (GET_CODE (op0) == AND)
5358 x = apply_distributive_law
5359 (gen_binary (AND, mode,
5360 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5361 gen_binary (IOR, mode, XEXP (op0, 1),
5364 if (GET_CODE (x) != IOR)
5368 if (GET_CODE (op1) == AND)
5370 x = apply_distributive_law
5371 (gen_binary (AND, mode,
5372 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5373 gen_binary (IOR, mode, XEXP (op1, 1),
5376 if (GET_CODE (x) != IOR)
5380 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5381 mode size to (rotate A CX). */
5383 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5384 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5385 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5386 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5387 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5388 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5389 == GET_MODE_BITSIZE (mode)))
5390 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5391 (GET_CODE (op0) == ASHIFT
5392 ? XEXP (op0, 1) : XEXP (op1, 1)));
5394 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5395 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5396 does not affect any of the bits in OP1, it can really be done
5397 as a PLUS and we can associate. We do this by seeing if OP1
5398 can be safely shifted left C bits. */
5399 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5400 && GET_CODE (XEXP (op0, 0)) == PLUS
5401 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5402 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5403 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5405 int count = INTVAL (XEXP (op0, 1));
5406 HOST_WIDE_INT mask = INTVAL (op1) << count;
5408 if (mask >> count == INTVAL (op1)
5409 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5411 SUBST (XEXP (XEXP (op0, 0), 1),
5412 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5419 /* If we are XORing two things that have no bits in common,
5420 convert them into an IOR. This helps to detect rotation encoded
5421 using those methods and possibly other simplifications. */
5423 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5424 && (nonzero_bits (op0, mode)
5425 & nonzero_bits (op1, mode)) == 0)
5426 return (gen_binary (IOR, mode, op0, op1));
5428 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5429 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5432 int num_negated = 0;
5434 if (GET_CODE (op0) == NOT)
5435 num_negated++, op0 = XEXP (op0, 0);
5436 if (GET_CODE (op1) == NOT)
5437 num_negated++, op1 = XEXP (op1, 0);
5439 if (num_negated == 2)
5441 SUBST (XEXP (x, 0), op0);
5442 SUBST (XEXP (x, 1), op1);
5444 else if (num_negated == 1)
5445 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5448 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5449 correspond to a machine insn or result in further simplifications
5450 if B is a constant. */
5452 if (GET_CODE (op0) == AND
5453 && rtx_equal_p (XEXP (op0, 1), op1)
5454 && ! side_effects_p (op1))
5455 return gen_binary (AND, mode,
5456 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5459 else if (GET_CODE (op0) == AND
5460 && rtx_equal_p (XEXP (op0, 0), op1)
5461 && ! side_effects_p (op1))
5462 return gen_binary (AND, mode,
5463 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5466 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5467 comparison if STORE_FLAG_VALUE is 1. */
5468 if (STORE_FLAG_VALUE == 1
5469 && op1 == const1_rtx
5470 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5471 && reversible_comparison_p (op0))
5472 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5473 mode, XEXP (op0, 0), XEXP (op0, 1));
5475 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5476 is (lt foo (const_int 0)), so we can perform the above
5477 simplification if STORE_FLAG_VALUE is 1. */
5479 if (STORE_FLAG_VALUE == 1
5480 && op1 == const1_rtx
5481 && GET_CODE (op0) == LSHIFTRT
5482 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5483 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5484 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5486 /* (xor (comparison foo bar) (const_int sign-bit))
5487 when STORE_FLAG_VALUE is the sign bit. */
5488 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5489 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5490 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5491 && op1 == const_true_rtx
5492 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5493 && reversible_comparison_p (op0))
5494 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5495 mode, XEXP (op0, 0), XEXP (op0, 1));
5506 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5507 operations" because they can be replaced with two more basic operations.
5508 ZERO_EXTEND is also considered "compound" because it can be replaced with
5509 an AND operation, which is simpler, though only one operation.
5511 The function expand_compound_operation is called with an rtx expression
5512 and will convert it to the appropriate shifts and AND operations,
5513 simplifying at each stage.
5515 The function make_compound_operation is called to convert an expression
5516 consisting of shifts and ANDs into the equivalent compound expression.
5517 It is the inverse of this function, loosely speaking. */
5520 expand_compound_operation (x)
5523 unsigned HOST_WIDE_INT pos = 0, len;
5525 unsigned int modewidth;
5528 switch (GET_CODE (x))
5533 /* We can't necessarily use a const_int for a multiword mode;
5534 it depends on implicitly extending the value.
5535 Since we don't know the right way to extend it,
5536 we can't tell whether the implicit way is right.
5538 Even for a mode that is no wider than a const_int,
5539 we can't win, because we need to sign extend one of its bits through
5540 the rest of it, and we don't know which bit. */
5541 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5544 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5545 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5546 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5547 reloaded. If not for that, MEM's would very rarely be safe.
5549 Reject MODEs bigger than a word, because we might not be able
5550 to reference a two-register group starting with an arbitrary register
5551 (and currently gen_lowpart might crash for a SUBREG). */
5553 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5556 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5557 /* If the inner object has VOIDmode (the only way this can happen
5558 is if it is a ASM_OPERANDS), we can't do anything since we don't
5559 know how much masking to do. */
5568 /* If the operand is a CLOBBER, just return it. */
5569 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5572 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5573 || GET_CODE (XEXP (x, 2)) != CONST_INT
5574 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5577 len = INTVAL (XEXP (x, 1));
5578 pos = INTVAL (XEXP (x, 2));
5580 /* If this goes outside the object being extracted, replace the object
5581 with a (use (mem ...)) construct that only combine understands
5582 and is used only for this purpose. */
5583 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5584 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5586 if (BITS_BIG_ENDIAN)
5587 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5594 /* Convert sign extension to zero extension, if we know that the high
5595 bit is not set, as this is easier to optimize. It will be converted
5596 back to cheaper alternative in make_extraction. */
5597 if (GET_CODE (x) == SIGN_EXTEND
5598 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5599 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5600 & ~ (((unsigned HOST_WIDE_INT)
5601 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5605 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5606 return expand_compound_operation (temp);
5609 /* We can optimize some special cases of ZERO_EXTEND. */
5610 if (GET_CODE (x) == ZERO_EXTEND)
5612 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5613 know that the last value didn't have any inappropriate bits
5615 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5616 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5617 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5618 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5619 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5620 return XEXP (XEXP (x, 0), 0);
5622 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5623 if (GET_CODE (XEXP (x, 0)) == SUBREG
5624 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5625 && subreg_lowpart_p (XEXP (x, 0))
5626 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5627 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5628 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5629 return SUBREG_REG (XEXP (x, 0));
5631 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5632 is a comparison and STORE_FLAG_VALUE permits. This is like
5633 the first case, but it works even when GET_MODE (x) is larger
5634 than HOST_WIDE_INT. */
5635 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5636 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5637 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5638 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5639 <= HOST_BITS_PER_WIDE_INT)
5640 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5641 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5642 return XEXP (XEXP (x, 0), 0);
5644 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5645 if (GET_CODE (XEXP (x, 0)) == SUBREG
5646 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5647 && subreg_lowpart_p (XEXP (x, 0))
5648 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5649 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5650 <= HOST_BITS_PER_WIDE_INT)
5651 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5652 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5653 return SUBREG_REG (XEXP (x, 0));
5657 /* If we reach here, we want to return a pair of shifts. The inner
5658 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5659 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5660 logical depending on the value of UNSIGNEDP.
5662 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5663 converted into an AND of a shift.
5665 We must check for the case where the left shift would have a negative
5666 count. This can happen in a case like (x >> 31) & 255 on machines
5667 that can't shift by a constant. On those machines, we would first
5668 combine the shift with the AND to produce a variable-position
5669 extraction. Then the constant of 31 would be substituted in to produce
5670 a such a position. */
5672 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5673 if (modewidth + len >= pos)
5674 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5676 simplify_shift_const (NULL_RTX, ASHIFT,
5679 modewidth - pos - len),
5682 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5683 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5684 simplify_shift_const (NULL_RTX, LSHIFTRT,
5687 ((HOST_WIDE_INT) 1 << len) - 1);
5689 /* Any other cases we can't handle. */
5693 /* If we couldn't do this for some reason, return the original
5695 if (GET_CODE (tem) == CLOBBER)
5701 /* X is a SET which contains an assignment of one object into
5702 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5703 or certain SUBREGS). If possible, convert it into a series of
5706 We half-heartedly support variable positions, but do not at all
5707 support variable lengths. */
5710 expand_field_assignment (x)
5714 rtx pos; /* Always counts from low bit. */
5717 enum machine_mode compute_mode;
5719 /* Loop until we find something we can't simplify. */
5722 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5723 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5725 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5726 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5727 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5729 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5730 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5732 inner = XEXP (SET_DEST (x), 0);
5733 len = INTVAL (XEXP (SET_DEST (x), 1));
5734 pos = XEXP (SET_DEST (x), 2);
5736 /* If the position is constant and spans the width of INNER,
5737 surround INNER with a USE to indicate this. */
5738 if (GET_CODE (pos) == CONST_INT
5739 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5740 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5742 if (BITS_BIG_ENDIAN)
5744 if (GET_CODE (pos) == CONST_INT)
5745 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5747 else if (GET_CODE (pos) == MINUS
5748 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5749 && (INTVAL (XEXP (pos, 1))
5750 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5751 /* If position is ADJUST - X, new position is X. */
5752 pos = XEXP (pos, 0);
5754 pos = gen_binary (MINUS, GET_MODE (pos),
5755 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5761 /* A SUBREG between two modes that occupy the same numbers of words
5762 can be done by moving the SUBREG to the source. */
5763 else if (GET_CODE (SET_DEST (x)) == SUBREG
5764 /* We need SUBREGs to compute nonzero_bits properly. */
5765 && nonzero_sign_valid
5766 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5767 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5768 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5769 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5771 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5772 gen_lowpart_for_combine
5773 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5780 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5781 inner = SUBREG_REG (inner);
5783 compute_mode = GET_MODE (inner);
5785 /* Don't attempt bitwise arithmetic on non-integral modes. */
5786 if (! INTEGRAL_MODE_P (compute_mode))
5788 enum machine_mode imode;
5790 /* Something is probably seriously wrong if this matches. */
5791 if (! FLOAT_MODE_P (compute_mode))
5794 /* Try to find an integral mode to pun with. */
5795 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5796 if (imode == BLKmode)
5799 compute_mode = imode;
5800 inner = gen_lowpart_for_combine (imode, inner);
5803 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5804 if (len < HOST_BITS_PER_WIDE_INT)
5805 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5809 /* Now compute the equivalent expression. Make a copy of INNER
5810 for the SET_DEST in case it is a MEM into which we will substitute;
5811 we don't want shared RTL in that case. */
5813 (VOIDmode, copy_rtx (inner),
5814 gen_binary (IOR, compute_mode,
5815 gen_binary (AND, compute_mode,
5816 gen_unary (NOT, compute_mode,
5822 gen_binary (ASHIFT, compute_mode,
5823 gen_binary (AND, compute_mode,
5824 gen_lowpart_for_combine
5825 (compute_mode, SET_SRC (x)),
5833 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5834 it is an RTX that represents a variable starting position; otherwise,
5835 POS is the (constant) starting bit position (counted from the LSB).
5837 INNER may be a USE. This will occur when we started with a bitfield
5838 that went outside the boundary of the object in memory, which is
5839 allowed on most machines. To isolate this case, we produce a USE
5840 whose mode is wide enough and surround the MEM with it. The only
5841 code that understands the USE is this routine. If it is not removed,
5842 it will cause the resulting insn not to match.
5844 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5847 IN_DEST is non-zero if this is a reference in the destination of a
5848 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5849 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5852 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5853 ZERO_EXTRACT should be built even for bits starting at bit 0.
5855 MODE is the desired mode of the result (if IN_DEST == 0).
5857 The result is an RTX for the extraction or NULL_RTX if the target
5861 make_extraction (mode, inner, pos, pos_rtx, len,
5862 unsignedp, in_dest, in_compare)
5863 enum machine_mode mode;
5867 unsigned HOST_WIDE_INT len;
5869 int in_dest, in_compare;
5871 /* This mode describes the size of the storage area
5872 to fetch the overall value from. Within that, we
5873 ignore the POS lowest bits, etc. */
5874 enum machine_mode is_mode = GET_MODE (inner);
5875 enum machine_mode inner_mode;
5876 enum machine_mode wanted_inner_mode = byte_mode;
5877 enum machine_mode wanted_inner_reg_mode = word_mode;
5878 enum machine_mode pos_mode = word_mode;
5879 enum machine_mode extraction_mode = word_mode;
5880 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5883 rtx orig_pos_rtx = pos_rtx;
5884 HOST_WIDE_INT orig_pos;
5886 /* Get some information about INNER and get the innermost object. */
5887 if (GET_CODE (inner) == USE)
5888 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5889 /* We don't need to adjust the position because we set up the USE
5890 to pretend that it was a full-word object. */
5891 spans_byte = 1, inner = XEXP (inner, 0);
5892 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5894 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5895 consider just the QI as the memory to extract from.
5896 The subreg adds or removes high bits; its mode is
5897 irrelevant to the meaning of this extraction,
5898 since POS and LEN count from the lsb. */
5899 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5900 is_mode = GET_MODE (SUBREG_REG (inner));
5901 inner = SUBREG_REG (inner);
5904 inner_mode = GET_MODE (inner);
5906 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5907 pos = INTVAL (pos_rtx), pos_rtx = 0;
5909 /* See if this can be done without an extraction. We never can if the
5910 width of the field is not the same as that of some integer mode. For
5911 registers, we can only avoid the extraction if the position is at the
5912 low-order bit and this is either not in the destination or we have the
5913 appropriate STRICT_LOW_PART operation available.
5915 For MEM, we can avoid an extract if the field starts on an appropriate
5916 boundary and we can change the mode of the memory reference. However,
5917 we cannot directly access the MEM if we have a USE and the underlying
5918 MEM is not TMODE. This combination means that MEM was being used in a
5919 context where bits outside its mode were being referenced; that is only
5920 valid in bit-field insns. */
5922 if (tmode != BLKmode
5923 && ! (spans_byte && inner_mode != tmode)
5924 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5925 && GET_CODE (inner) != MEM
5927 || (GET_CODE (inner) == REG
5928 && (movstrict_optab->handlers[(int) tmode].insn_code
5929 != CODE_FOR_nothing))))
5930 || (GET_CODE (inner) == MEM && pos_rtx == 0
5932 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5933 : BITS_PER_UNIT)) == 0
5934 /* We can't do this if we are widening INNER_MODE (it
5935 may not be aligned, for one thing). */
5936 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5937 && (inner_mode == tmode
5938 || (! mode_dependent_address_p (XEXP (inner, 0))
5939 && ! MEM_VOLATILE_P (inner))))))
5941 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5942 field. If the original and current mode are the same, we need not
5943 adjust the offset. Otherwise, we do if bytes big endian.
5945 If INNER is not a MEM, get a piece consisting of just the field
5946 of interest (in this case POS % BITS_PER_WORD must be 0). */
5948 if (GET_CODE (inner) == MEM)
5951 /* POS counts from lsb, but make OFFSET count in memory order. */
5952 if (BYTES_BIG_ENDIAN)
5953 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5955 offset = pos / BITS_PER_UNIT;
5957 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5958 MEM_COPY_ATTRIBUTES (new, inner);
5960 else if (GET_CODE (inner) == REG)
5962 /* We can't call gen_lowpart_for_combine here since we always want
5963 a SUBREG and it would sometimes return a new hard register. */
5964 if (tmode != inner_mode)
5965 new = gen_rtx_SUBREG (tmode, inner,
5967 && (GET_MODE_SIZE (inner_mode)
5969 ? (((GET_MODE_SIZE (inner_mode)
5970 - GET_MODE_SIZE (tmode))
5972 - pos / BITS_PER_WORD)
5973 : pos / BITS_PER_WORD));
5978 new = force_to_mode (inner, tmode,
5979 len >= HOST_BITS_PER_WIDE_INT
5980 ? ~(HOST_WIDE_INT) 0
5981 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5984 /* If this extraction is going into the destination of a SET,
5985 make a STRICT_LOW_PART unless we made a MEM. */
5988 return (GET_CODE (new) == MEM ? new
5989 : (GET_CODE (new) != SUBREG
5990 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5991 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5996 /* If we know that no extraneous bits are set, and that the high
5997 bit is not set, convert the extraction to the cheaper of
5998 sign and zero extension, that are equivalent in these cases. */
5999 if (flag_expensive_optimizations
6000 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6001 && ((nonzero_bits (new, tmode)
6002 & ~ (((unsigned HOST_WIDE_INT)
6003 GET_MODE_MASK (tmode))
6007 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6008 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6010 /* Prefer ZERO_EXTENSION, since it gives more information to
6012 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
6017 /* Otherwise, sign- or zero-extend unless we already are in the
6020 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6024 /* Unless this is a COMPARE or we have a funny memory reference,
6025 don't do anything with zero-extending field extracts starting at
6026 the low-order bit since they are simple AND operations. */
6027 if (pos_rtx == 0 && pos == 0 && ! in_dest
6028 && ! in_compare && ! spans_byte && unsignedp)
6031 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6032 we would be spanning bytes or if the position is not a constant and the
6033 length is not 1. In all other cases, we would only be going outside
6034 our object in cases when an original shift would have been
6036 if (! spans_byte && GET_CODE (inner) == MEM
6037 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6038 || (pos_rtx != 0 && len != 1)))
6041 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6042 and the mode for the result. */
6046 wanted_inner_reg_mode
6047 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6048 if (wanted_inner_reg_mode == VOIDmode)
6049 wanted_inner_reg_mode = word_mode;
6051 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6052 if (pos_mode == VOIDmode)
6053 pos_mode = word_mode;
6055 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6056 if (extraction_mode == VOIDmode)
6057 extraction_mode = word_mode;
6062 if (! in_dest && unsignedp)
6064 wanted_inner_reg_mode
6065 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6066 if (wanted_inner_reg_mode == VOIDmode)
6067 wanted_inner_reg_mode = word_mode;
6069 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6070 if (pos_mode == VOIDmode)
6071 pos_mode = word_mode;
6073 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6074 if (extraction_mode == VOIDmode)
6075 extraction_mode = word_mode;
6080 if (! in_dest && ! unsignedp)
6082 wanted_inner_reg_mode
6083 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6084 if (wanted_inner_reg_mode == VOIDmode)
6085 wanted_inner_reg_mode = word_mode;
6087 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6088 if (pos_mode == VOIDmode)
6089 pos_mode = word_mode;
6091 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6092 if (extraction_mode == VOIDmode)
6093 extraction_mode = word_mode;
6097 /* Never narrow an object, since that might not be safe. */
6099 if (mode != VOIDmode
6100 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6101 extraction_mode = mode;
6103 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6104 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6105 pos_mode = GET_MODE (pos_rtx);
6107 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6108 if we have to change the mode of memory and cannot, the desired mode is
6110 if (GET_CODE (inner) != MEM)
6111 wanted_inner_mode = wanted_inner_reg_mode;
6112 else if (inner_mode != wanted_inner_mode
6113 && (mode_dependent_address_p (XEXP (inner, 0))
6114 || MEM_VOLATILE_P (inner)))
6115 wanted_inner_mode = extraction_mode;
6119 if (BITS_BIG_ENDIAN)
6121 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6122 BITS_BIG_ENDIAN style. If position is constant, compute new
6123 position. Otherwise, build subtraction.
6124 Note that POS is relative to the mode of the original argument.
6125 If it's a MEM we need to recompute POS relative to that.
6126 However, if we're extracting from (or inserting into) a register,
6127 we want to recompute POS relative to wanted_inner_mode. */
6128 int width = (GET_CODE (inner) == MEM
6129 ? GET_MODE_BITSIZE (is_mode)
6130 : GET_MODE_BITSIZE (wanted_inner_mode));
6133 pos = width - len - pos;
6136 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6137 GEN_INT (width - len), pos_rtx);
6138 /* POS may be less than 0 now, but we check for that below.
6139 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6142 /* If INNER has a wider mode, make it smaller. If this is a constant
6143 extract, try to adjust the byte to point to the byte containing
6145 if (wanted_inner_mode != VOIDmode
6146 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6147 && ((GET_CODE (inner) == MEM
6148 && (inner_mode == wanted_inner_mode
6149 || (! mode_dependent_address_p (XEXP (inner, 0))
6150 && ! MEM_VOLATILE_P (inner))))))
6154 /* The computations below will be correct if the machine is big
6155 endian in both bits and bytes or little endian in bits and bytes.
6156 If it is mixed, we must adjust. */
6158 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6159 adjust OFFSET to compensate. */
6160 if (BYTES_BIG_ENDIAN
6162 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6163 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6165 /* If this is a constant position, we can move to the desired byte. */
6168 offset += pos / BITS_PER_UNIT;
6169 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6172 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6174 && is_mode != wanted_inner_mode)
6175 offset = (GET_MODE_SIZE (is_mode)
6176 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6178 if (offset != 0 || inner_mode != wanted_inner_mode)
6180 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6181 plus_constant (XEXP (inner, 0), offset));
6183 MEM_COPY_ATTRIBUTES (newmem, inner);
6188 /* If INNER is not memory, we can always get it into the proper mode. If we
6189 are changing its mode, POS must be a constant and smaller than the size
6191 else if (GET_CODE (inner) != MEM)
6193 if (GET_MODE (inner) != wanted_inner_mode
6195 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6198 inner = force_to_mode (inner, wanted_inner_mode,
6200 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6201 ? ~(HOST_WIDE_INT) 0
6202 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6207 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6208 have to zero extend. Otherwise, we can just use a SUBREG. */
6210 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6212 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6214 /* If we know that no extraneous bits are set, and that the high
6215 bit is not set, convert extraction to cheaper one - eighter
6216 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6218 if (flag_expensive_optimizations
6219 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6220 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6221 & ~ (((unsigned HOST_WIDE_INT)
6222 GET_MODE_MASK (GET_MODE (pos_rtx)))
6226 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6228 /* Preffer ZERO_EXTENSION, since it gives more information to
6230 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6235 else if (pos_rtx != 0
6236 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6237 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6239 /* Make POS_RTX unless we already have it and it is correct. If we don't
6240 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6242 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6243 pos_rtx = orig_pos_rtx;
6245 else if (pos_rtx == 0)
6246 pos_rtx = GEN_INT (pos);
6248 /* Make the required operation. See if we can use existing rtx. */
6249 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6250 extraction_mode, inner, GEN_INT (len), pos_rtx);
6252 new = gen_lowpart_for_combine (mode, new);
6257 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6258 with any other operations in X. Return X without that shift if so. */
6261 extract_left_shift (x, count)
6265 enum rtx_code code = GET_CODE (x);
6266 enum machine_mode mode = GET_MODE (x);
6272 /* This is the shift itself. If it is wide enough, we will return
6273 either the value being shifted if the shift count is equal to
6274 COUNT or a shift for the difference. */
6275 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6276 && INTVAL (XEXP (x, 1)) >= count)
6277 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6278 INTVAL (XEXP (x, 1)) - count);
6282 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6283 return gen_unary (code, mode, mode, tem);
6287 case PLUS: case IOR: case XOR: case AND:
6288 /* If we can safely shift this constant and we find the inner shift,
6289 make a new operation. */
6290 if (GET_CODE (XEXP (x,1)) == CONST_INT
6291 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6292 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6293 return gen_binary (code, mode, tem,
6294 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6305 /* Look at the expression rooted at X. Look for expressions
6306 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6307 Form these expressions.
6309 Return the new rtx, usually just X.
6311 Also, for machines like the Vax that don't have logical shift insns,
6312 try to convert logical to arithmetic shift operations in cases where
6313 they are equivalent. This undoes the canonicalizations to logical
6314 shifts done elsewhere.
6316 We try, as much as possible, to re-use rtl expressions to save memory.
6318 IN_CODE says what kind of expression we are processing. Normally, it is
6319 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6320 being kludges), it is MEM. When processing the arguments of a comparison
6321 or a COMPARE against zero, it is COMPARE. */
6324 make_compound_operation (x, in_code)
6326 enum rtx_code in_code;
6328 enum rtx_code code = GET_CODE (x);
6329 enum machine_mode mode = GET_MODE (x);
6330 int mode_width = GET_MODE_BITSIZE (mode);
6332 enum rtx_code next_code;
6338 /* Select the code to be used in recursive calls. Once we are inside an
6339 address, we stay there. If we have a comparison, set to COMPARE,
6340 but once inside, go back to our default of SET. */
6342 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6343 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6344 && XEXP (x, 1) == const0_rtx) ? COMPARE
6345 : in_code == COMPARE ? SET : in_code);
6347 /* Process depending on the code of this operation. If NEW is set
6348 non-zero, it will be returned. */
6353 /* Convert shifts by constants into multiplications if inside
6355 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6356 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6357 && INTVAL (XEXP (x, 1)) >= 0)
6359 new = make_compound_operation (XEXP (x, 0), next_code);
6360 new = gen_rtx_combine (MULT, mode, new,
6361 GEN_INT ((HOST_WIDE_INT) 1
6362 << INTVAL (XEXP (x, 1))));
6367 /* If the second operand is not a constant, we can't do anything
6369 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6372 /* If the constant is a power of two minus one and the first operand
6373 is a logical right shift, make an extraction. */
6374 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6375 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6377 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6378 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6379 0, in_code == COMPARE);
6382 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6383 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6384 && subreg_lowpart_p (XEXP (x, 0))
6385 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6386 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6388 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6390 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6391 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6392 0, in_code == COMPARE);
6394 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6395 else if ((GET_CODE (XEXP (x, 0)) == XOR
6396 || GET_CODE (XEXP (x, 0)) == IOR)
6397 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6398 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6399 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6401 /* Apply the distributive law, and then try to make extractions. */
6402 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6403 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6405 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6407 new = make_compound_operation (new, in_code);
6410 /* If we are have (and (rotate X C) M) and C is larger than the number
6411 of bits in M, this is an extraction. */
6413 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6414 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6415 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6416 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6418 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6419 new = make_extraction (mode, new,
6420 (GET_MODE_BITSIZE (mode)
6421 - INTVAL (XEXP (XEXP (x, 0), 1))),
6422 NULL_RTX, i, 1, 0, in_code == COMPARE);
6425 /* On machines without logical shifts, if the operand of the AND is
6426 a logical shift and our mask turns off all the propagated sign
6427 bits, we can replace the logical shift with an arithmetic shift. */
6428 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6429 && (lshr_optab->handlers[(int) mode].insn_code
6430 == CODE_FOR_nothing)
6431 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6432 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6433 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6434 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6435 && mode_width <= HOST_BITS_PER_WIDE_INT)
6437 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6439 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6440 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6442 gen_rtx_combine (ASHIFTRT, mode,
6443 make_compound_operation (XEXP (XEXP (x, 0), 0),
6445 XEXP (XEXP (x, 0), 1)));
6448 /* If the constant is one less than a power of two, this might be
6449 representable by an extraction even if no shift is present.
6450 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6451 we are in a COMPARE. */
6452 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6453 new = make_extraction (mode,
6454 make_compound_operation (XEXP (x, 0),
6456 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6458 /* If we are in a comparison and this is an AND with a power of two,
6459 convert this into the appropriate bit extract. */
6460 else if (in_code == COMPARE
6461 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6462 new = make_extraction (mode,
6463 make_compound_operation (XEXP (x, 0),
6465 i, NULL_RTX, 1, 1, 0, 1);
6470 /* If the sign bit is known to be zero, replace this with an
6471 arithmetic shift. */
6472 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6473 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6474 && mode_width <= HOST_BITS_PER_WIDE_INT
6475 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6477 new = gen_rtx_combine (ASHIFTRT, mode,
6478 make_compound_operation (XEXP (x, 0),
6484 /* ... fall through ... */
6490 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6491 this is a SIGN_EXTRACT. */
6492 if (GET_CODE (rhs) == CONST_INT
6493 && GET_CODE (lhs) == ASHIFT
6494 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6495 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6497 new = make_compound_operation (XEXP (lhs, 0), next_code);
6498 new = make_extraction (mode, new,
6499 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6500 NULL_RTX, mode_width - INTVAL (rhs),
6501 code == LSHIFTRT, 0, in_code == COMPARE);
6504 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6505 If so, try to merge the shifts into a SIGN_EXTEND. We could
6506 also do this for some cases of SIGN_EXTRACT, but it doesn't
6507 seem worth the effort; the case checked for occurs on Alpha. */
6509 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6510 && ! (GET_CODE (lhs) == SUBREG
6511 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6512 && GET_CODE (rhs) == CONST_INT
6513 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6514 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6515 new = make_extraction (mode, make_compound_operation (new, next_code),
6516 0, NULL_RTX, mode_width - INTVAL (rhs),
6517 code == LSHIFTRT, 0, in_code == COMPARE);
6522 /* Call ourselves recursively on the inner expression. If we are
6523 narrowing the object and it has a different RTL code from
6524 what it originally did, do this SUBREG as a force_to_mode. */
6526 tem = make_compound_operation (SUBREG_REG (x), in_code);
6527 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6528 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6529 && subreg_lowpart_p (x))
6531 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6534 /* If we have something other than a SUBREG, we might have
6535 done an expansion, so rerun outselves. */
6536 if (GET_CODE (newer) != SUBREG)
6537 newer = make_compound_operation (newer, in_code);
6542 /* If this is a paradoxical subreg, and the new code is a sign or
6543 zero extension, omit the subreg and widen the extension. If it
6544 is a regular subreg, we can still get rid of the subreg by not
6545 widening so much, or in fact removing the extension entirely. */
6546 if ((GET_CODE (tem) == SIGN_EXTEND
6547 || GET_CODE (tem) == ZERO_EXTEND)
6548 && subreg_lowpart_p (x))
6550 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6551 || (GET_MODE_SIZE (mode) >
6552 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6553 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6555 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6566 x = gen_lowpart_for_combine (mode, new);
6567 code = GET_CODE (x);
6570 /* Now recursively process each operand of this operation. */
6571 fmt = GET_RTX_FORMAT (code);
6572 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6575 new = make_compound_operation (XEXP (x, i), next_code);
6576 SUBST (XEXP (x, i), new);
6582 /* Given M see if it is a value that would select a field of bits
6583 within an item, but not the entire word. Return -1 if not.
6584 Otherwise, return the starting position of the field, where 0 is the
6587 *PLEN is set to the length of the field. */
6590 get_pos_from_mask (m, plen)
6591 unsigned HOST_WIDE_INT m;
6592 unsigned HOST_WIDE_INT *plen;
6594 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6595 int pos = exact_log2 (m & - m);
6601 /* Now shift off the low-order zero bits and see if we have a power of
6603 len = exact_log2 ((m >> pos) + 1);
6612 /* See if X can be simplified knowing that we will only refer to it in
6613 MODE and will only refer to those bits that are nonzero in MASK.
6614 If other bits are being computed or if masking operations are done
6615 that select a superset of the bits in MASK, they can sometimes be
6618 Return a possibly simplified expression, but always convert X to
6619 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6621 Also, if REG is non-zero and X is a register equal in value to REG,
6624 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6625 are all off in X. This is used when X will be complemented, by either
6626 NOT, NEG, or XOR. */
6629 force_to_mode (x, mode, mask, reg, just_select)
6631 enum machine_mode mode;
6632 unsigned HOST_WIDE_INT mask;
6636 enum rtx_code code = GET_CODE (x);
6637 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6638 enum machine_mode op_mode;
6639 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6642 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6643 code below will do the wrong thing since the mode of such an
6644 expression is VOIDmode.
6646 Also do nothing if X is a CLOBBER; this can happen if X was
6647 the return value from a call to gen_lowpart_for_combine. */
6648 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6651 /* We want to perform the operation is its present mode unless we know
6652 that the operation is valid in MODE, in which case we do the operation
6654 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6655 && code_to_optab[(int) code] != 0
6656 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6657 != CODE_FOR_nothing))
6658 ? mode : GET_MODE (x));
6660 /* It is not valid to do a right-shift in a narrower mode
6661 than the one it came in with. */
6662 if ((code == LSHIFTRT || code == ASHIFTRT)
6663 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6664 op_mode = GET_MODE (x);
6666 /* Truncate MASK to fit OP_MODE. */
6668 mask &= GET_MODE_MASK (op_mode);
6670 /* When we have an arithmetic operation, or a shift whose count we
6671 do not know, we need to assume that all bit the up to the highest-order
6672 bit in MASK will be needed. This is how we form such a mask. */
6674 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6675 ? GET_MODE_MASK (op_mode)
6676 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6679 fuller_mask = ~ (HOST_WIDE_INT) 0;
6681 /* Determine what bits of X are guaranteed to be (non)zero. */
6682 nonzero = nonzero_bits (x, mode);
6684 /* If none of the bits in X are needed, return a zero. */
6685 if (! just_select && (nonzero & mask) == 0)
6688 /* If X is a CONST_INT, return a new one. Do this here since the
6689 test below will fail. */
6690 if (GET_CODE (x) == CONST_INT)
6692 HOST_WIDE_INT cval = INTVAL (x) & mask;
6693 int width = GET_MODE_BITSIZE (mode);
6695 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6696 number, sign extend it. */
6697 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6698 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6699 cval |= (HOST_WIDE_INT) -1 << width;
6701 return GEN_INT (cval);
6704 /* If X is narrower than MODE and we want all the bits in X's mode, just
6705 get X in the proper mode. */
6706 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6707 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6708 return gen_lowpart_for_combine (mode, x);
6710 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6711 MASK are already known to be zero in X, we need not do anything. */
6712 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6718 /* If X is a (clobber (const_int)), return it since we know we are
6719 generating something that won't match. */
6723 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6724 spanned the boundary of the MEM. If we are now masking so it is
6725 within that boundary, we don't need the USE any more. */
6726 if (! BITS_BIG_ENDIAN
6727 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6728 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6735 x = expand_compound_operation (x);
6736 if (GET_CODE (x) != code)
6737 return force_to_mode (x, mode, mask, reg, next_select);
6741 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6742 || rtx_equal_p (reg, get_last_value (x))))
6747 if (subreg_lowpart_p (x)
6748 /* We can ignore the effect of this SUBREG if it narrows the mode or
6749 if the constant masks to zero all the bits the mode doesn't
6751 && ((GET_MODE_SIZE (GET_MODE (x))
6752 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6754 & GET_MODE_MASK (GET_MODE (x))
6755 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6756 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6760 /* If this is an AND with a constant, convert it into an AND
6761 whose constant is the AND of that constant with MASK. If it
6762 remains an AND of MASK, delete it since it is redundant. */
6764 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6766 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6767 mask & INTVAL (XEXP (x, 1)));
6769 /* If X is still an AND, see if it is an AND with a mask that
6770 is just some low-order bits. If so, and it is MASK, we don't
6773 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6774 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6777 /* If it remains an AND, try making another AND with the bits
6778 in the mode mask that aren't in MASK turned on. If the
6779 constant in the AND is wide enough, this might make a
6780 cheaper constant. */
6782 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6783 && GET_MODE_MASK (GET_MODE (x)) != mask
6784 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6786 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6787 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6788 int width = GET_MODE_BITSIZE (GET_MODE (x));
6791 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6792 number, sign extend it. */
6793 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6794 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6795 cval |= (HOST_WIDE_INT) -1 << width;
6797 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6798 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6808 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6809 low-order bits (as in an alignment operation) and FOO is already
6810 aligned to that boundary, mask C1 to that boundary as well.
6811 This may eliminate that PLUS and, later, the AND. */
6814 unsigned int width = GET_MODE_BITSIZE (mode);
6815 unsigned HOST_WIDE_INT smask = mask;
6817 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6818 number, sign extend it. */
6820 if (width < HOST_BITS_PER_WIDE_INT
6821 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6822 smask |= (HOST_WIDE_INT) -1 << width;
6824 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6825 && exact_log2 (- smask) >= 0)
6829 && (XEXP (x, 0) == stack_pointer_rtx
6830 || XEXP (x, 0) == frame_pointer_rtx))
6832 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6833 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6835 sp_mask &= ~ (sp_alignment - 1);
6836 if ((sp_mask & ~ smask) == 0
6837 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6838 return force_to_mode (plus_constant (XEXP (x, 0),
6839 ((INTVAL (XEXP (x, 1)) -
6840 STACK_BIAS) & smask)
6842 mode, smask, reg, next_select);
6845 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6846 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6847 return force_to_mode (plus_constant (XEXP (x, 0),
6848 (INTVAL (XEXP (x, 1))
6850 mode, smask, reg, next_select);
6854 /* ... fall through ... */
6857 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6858 most significant bit in MASK since carries from those bits will
6859 affect the bits we are interested in. */
6864 /* If X is (minus C Y) where C's least set bit is larger than any bit
6865 in the mask, then we may replace with (neg Y). */
6866 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6867 && (INTVAL (XEXP (x, 0)) & -INTVAL (XEXP (x, 0))) > mask)
6869 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6870 return force_to_mode (x, mode, mask, reg, next_select);
6873 /* Similarly, if C contains every bit in the mask, then we may
6874 replace with (not Y). */
6875 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6876 && (INTVAL (XEXP (x, 0)) | mask) == INTVAL (XEXP (x, 0)))
6878 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6879 return force_to_mode (x, mode, mask, reg, next_select);
6887 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6888 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6889 operation which may be a bitfield extraction. Ensure that the
6890 constant we form is not wider than the mode of X. */
6892 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6893 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6894 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6895 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6896 && GET_CODE (XEXP (x, 1)) == CONST_INT
6897 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6898 + floor_log2 (INTVAL (XEXP (x, 1))))
6899 < GET_MODE_BITSIZE (GET_MODE (x)))
6900 && (INTVAL (XEXP (x, 1))
6901 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6903 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6904 << INTVAL (XEXP (XEXP (x, 0), 1)));
6905 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6906 XEXP (XEXP (x, 0), 0), temp);
6907 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6908 XEXP (XEXP (x, 0), 1));
6909 return force_to_mode (x, mode, mask, reg, next_select);
6913 /* For most binary operations, just propagate into the operation and
6914 change the mode if we have an operation of that mode. */
6916 op0 = gen_lowpart_for_combine (op_mode,
6917 force_to_mode (XEXP (x, 0), mode, mask,
6919 op1 = gen_lowpart_for_combine (op_mode,
6920 force_to_mode (XEXP (x, 1), mode, mask,
6923 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6924 MASK since OP1 might have been sign-extended but we never want
6925 to turn on extra bits, since combine might have previously relied
6926 on them being off. */
6927 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6928 && (INTVAL (op1) & mask) != 0)
6929 op1 = GEN_INT (INTVAL (op1) & mask);
6931 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6932 x = gen_binary (code, op_mode, op0, op1);
6936 /* For left shifts, do the same, but just for the first operand.
6937 However, we cannot do anything with shifts where we cannot
6938 guarantee that the counts are smaller than the size of the mode
6939 because such a count will have a different meaning in a
6942 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6943 && INTVAL (XEXP (x, 1)) >= 0
6944 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6945 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6946 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6947 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6950 /* If the shift count is a constant and we can do arithmetic in
6951 the mode of the shift, refine which bits we need. Otherwise, use the
6952 conservative form of the mask. */
6953 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6954 && INTVAL (XEXP (x, 1)) >= 0
6955 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6956 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6957 mask >>= INTVAL (XEXP (x, 1));
6961 op0 = gen_lowpart_for_combine (op_mode,
6962 force_to_mode (XEXP (x, 0), op_mode,
6963 mask, reg, next_select));
6965 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6966 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6970 /* Here we can only do something if the shift count is a constant,
6971 this shift constant is valid for the host, and we can do arithmetic
6974 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6975 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6976 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6978 rtx inner = XEXP (x, 0);
6979 unsigned HOST_WIDE_INT inner_mask;
6981 /* Select the mask of the bits we need for the shift operand. */
6982 inner_mask = mask << INTVAL (XEXP (x, 1));
6984 /* We can only change the mode of the shift if we can do arithmetic
6985 in the mode of the shift and INNER_MASK is no wider than the
6986 width of OP_MODE. */
6987 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6988 || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6989 op_mode = GET_MODE (x);
6991 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6993 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6994 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6997 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6998 shift and AND produces only copies of the sign bit (C2 is one less
6999 than a power of two), we can do this with just a shift. */
7001 if (GET_CODE (x) == LSHIFTRT
7002 && GET_CODE (XEXP (x, 1)) == CONST_INT
7003 /* The shift puts one of the sign bit copies in the least significant
7005 && ((INTVAL (XEXP (x, 1))
7006 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7007 >= GET_MODE_BITSIZE (GET_MODE (x)))
7008 && exact_log2 (mask + 1) >= 0
7009 /* Number of bits left after the shift must be more than the mask
7011 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7012 <= GET_MODE_BITSIZE (GET_MODE (x)))
7013 /* Must be more sign bit copies than the mask needs. */
7014 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7015 >= exact_log2 (mask + 1)))
7016 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7017 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7018 - exact_log2 (mask + 1)));
7023 /* If we are just looking for the sign bit, we don't need this shift at
7024 all, even if it has a variable count. */
7025 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7026 && (mask == ((unsigned HOST_WIDE_INT) 1
7027 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7028 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7030 /* If this is a shift by a constant, get a mask that contains those bits
7031 that are not copies of the sign bit. We then have two cases: If
7032 MASK only includes those bits, this can be a logical shift, which may
7033 allow simplifications. If MASK is a single-bit field not within
7034 those bits, we are requesting a copy of the sign bit and hence can
7035 shift the sign bit to the appropriate location. */
7037 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7038 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7042 /* If the considered data is wider then HOST_WIDE_INT, we can't
7043 represent a mask for all its bits in a single scalar.
7044 But we only care about the lower bits, so calculate these. */
7046 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7048 nonzero = ~ (HOST_WIDE_INT) 0;
7050 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7051 is the number of bits a full-width mask would have set.
7052 We need only shift if these are fewer than nonzero can
7053 hold. If not, we must keep all bits set in nonzero. */
7055 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7056 < HOST_BITS_PER_WIDE_INT)
7057 nonzero >>= INTVAL (XEXP (x, 1))
7058 + HOST_BITS_PER_WIDE_INT
7059 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7063 nonzero = GET_MODE_MASK (GET_MODE (x));
7064 nonzero >>= INTVAL (XEXP (x, 1));
7067 if ((mask & ~ nonzero) == 0
7068 || (i = exact_log2 (mask)) >= 0)
7070 x = simplify_shift_const
7071 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7072 i < 0 ? INTVAL (XEXP (x, 1))
7073 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7075 if (GET_CODE (x) != ASHIFTRT)
7076 return force_to_mode (x, mode, mask, reg, next_select);
7080 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7081 even if the shift count isn't a constant. */
7083 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7087 /* If this is a zero- or sign-extension operation that just affects bits
7088 we don't care about, remove it. Be sure the call above returned
7089 something that is still a shift. */
7091 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7092 && GET_CODE (XEXP (x, 1)) == CONST_INT
7093 && INTVAL (XEXP (x, 1)) >= 0
7094 && (INTVAL (XEXP (x, 1))
7095 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7096 && GET_CODE (XEXP (x, 0)) == ASHIFT
7097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7098 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7099 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7106 /* If the shift count is constant and we can do computations
7107 in the mode of X, compute where the bits we care about are.
7108 Otherwise, we can't do anything. Don't change the mode of
7109 the shift or propagate MODE into the shift, though. */
7110 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7111 && INTVAL (XEXP (x, 1)) >= 0)
7113 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7114 GET_MODE (x), GEN_INT (mask),
7116 if (temp && GET_CODE(temp) == CONST_INT)
7118 force_to_mode (XEXP (x, 0), GET_MODE (x),
7119 INTVAL (temp), reg, next_select));
7124 /* If we just want the low-order bit, the NEG isn't needed since it
7125 won't change the low-order bit. */
7127 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7129 /* We need any bits less significant than the most significant bit in
7130 MASK since carries from those bits will affect the bits we are
7136 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7137 same as the XOR case above. Ensure that the constant we form is not
7138 wider than the mode of X. */
7140 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7141 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7142 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7143 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7144 < GET_MODE_BITSIZE (GET_MODE (x)))
7145 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7147 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7148 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7149 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7151 return force_to_mode (x, mode, mask, reg, next_select);
7154 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7155 use the full mask inside the NOT. */
7159 op0 = gen_lowpart_for_combine (op_mode,
7160 force_to_mode (XEXP (x, 0), mode, mask,
7162 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7163 x = gen_unary (code, op_mode, op_mode, op0);
7167 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7168 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7169 which is equal to STORE_FLAG_VALUE. */
7170 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7171 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7172 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7173 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7178 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7179 written in a narrower mode. We play it safe and do not do so. */
7182 gen_lowpart_for_combine (GET_MODE (x),
7183 force_to_mode (XEXP (x, 1), mode,
7184 mask, reg, next_select)));
7186 gen_lowpart_for_combine (GET_MODE (x),
7187 force_to_mode (XEXP (x, 2), mode,
7188 mask, reg,next_select)));
7195 /* Ensure we return a value of the proper mode. */
7196 return gen_lowpart_for_combine (mode, x);
7199 /* Return nonzero if X is an expression that has one of two values depending on
7200 whether some other value is zero or nonzero. In that case, we return the
7201 value that is being tested, *PTRUE is set to the value if the rtx being
7202 returned has a nonzero value, and *PFALSE is set to the other alternative.
7204 If we return zero, we set *PTRUE and *PFALSE to X. */
7207 if_then_else_cond (x, ptrue, pfalse)
7209 rtx *ptrue, *pfalse;
7211 enum machine_mode mode = GET_MODE (x);
7212 enum rtx_code code = GET_CODE (x);
7213 rtx cond0, cond1, true0, true1, false0, false1;
7214 unsigned HOST_WIDE_INT nz;
7216 /* If we are comparing a value against zero, we are done. */
7217 if ((code == NE || code == EQ)
7218 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7220 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7221 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7225 /* If this is a unary operation whose operand has one of two values, apply
7226 our opcode to compute those values. */
7227 else if (GET_RTX_CLASS (code) == '1'
7228 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7230 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7231 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7235 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7236 make can't possibly match and would suppress other optimizations. */
7237 else if (code == COMPARE)
7240 /* If this is a binary operation, see if either side has only one of two
7241 values. If either one does or if both do and they are conditional on
7242 the same value, compute the new true and false values. */
7243 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7244 || GET_RTX_CLASS (code) == '<')
7246 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7247 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7249 if ((cond0 != 0 || cond1 != 0)
7250 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7252 /* If if_then_else_cond returned zero, then true/false are the
7253 same rtl. We must copy one of them to prevent invalid rtl
7256 true0 = copy_rtx (true0);
7257 else if (cond1 == 0)
7258 true1 = copy_rtx (true1);
7260 *ptrue = gen_binary (code, mode, true0, true1);
7261 *pfalse = gen_binary (code, mode, false0, false1);
7262 return cond0 ? cond0 : cond1;
7265 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7266 operands is zero when the other is non-zero, and vice-versa,
7267 and STORE_FLAG_VALUE is 1 or -1. */
7269 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7270 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7272 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7274 rtx op0 = XEXP (XEXP (x, 0), 1);
7275 rtx op1 = XEXP (XEXP (x, 1), 1);
7277 cond0 = XEXP (XEXP (x, 0), 0);
7278 cond1 = XEXP (XEXP (x, 1), 0);
7280 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7281 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7282 && reversible_comparison_p (cond1)
7283 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7284 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7285 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7286 || ((swap_condition (GET_CODE (cond0))
7287 == reverse_condition (GET_CODE (cond1)))
7288 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7289 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7290 && ! side_effects_p (x))
7292 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7293 *pfalse = gen_binary (MULT, mode,
7295 ? gen_unary (NEG, mode, mode, op1) : op1),
7301 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7303 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7304 && (code == MULT || code == AND || code == UMIN)
7305 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7307 cond0 = XEXP (XEXP (x, 0), 0);
7308 cond1 = XEXP (XEXP (x, 1), 0);
7310 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7311 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7312 && reversible_comparison_p (cond1)
7313 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7314 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7315 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7316 || ((swap_condition (GET_CODE (cond0))
7317 == reverse_condition (GET_CODE (cond1)))
7318 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7319 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7320 && ! side_effects_p (x))
7322 *ptrue = *pfalse = const0_rtx;
7328 else if (code == IF_THEN_ELSE)
7330 /* If we have IF_THEN_ELSE already, extract the condition and
7331 canonicalize it if it is NE or EQ. */
7332 cond0 = XEXP (x, 0);
7333 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7334 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7335 return XEXP (cond0, 0);
7336 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7338 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7339 return XEXP (cond0, 0);
7345 /* If X is a normal SUBREG with both inner and outer modes integral,
7346 we can narrow both the true and false values of the inner expression,
7347 if there is a condition. */
7348 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7349 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7350 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7351 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7354 if ((GET_CODE (SUBREG_REG (x)) == REG
7355 || GET_CODE (SUBREG_REG (x)) == MEM
7356 || CONSTANT_P (SUBREG_REG (x)))
7357 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7358 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7360 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7361 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7363 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7365 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7370 /* If X is a constant, this isn't special and will cause confusions
7371 if we treat it as such. Likewise if it is equivalent to a constant. */
7372 else if (CONSTANT_P (x)
7373 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7376 /* If X is known to be either 0 or -1, those are the true and
7377 false values when testing X. */
7378 else if (x == constm1_rtx || x == const0_rtx
7379 || (mode != VOIDmode
7380 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7382 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7386 /* Likewise for 0 or a single bit. */
7387 else if (mode != VOIDmode
7388 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7389 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7391 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7395 /* Otherwise fail; show no condition with true and false values the same. */
7396 *ptrue = *pfalse = x;
7400 /* Return the value of expression X given the fact that condition COND
7401 is known to be true when applied to REG as its first operand and VAL
7402 as its second. X is known to not be shared and so can be modified in
7405 We only handle the simplest cases, and specifically those cases that
7406 arise with IF_THEN_ELSE expressions. */
7409 known_cond (x, cond, reg, val)
7414 enum rtx_code code = GET_CODE (x);
7419 if (side_effects_p (x))
7422 if (cond == EQ && rtx_equal_p (x, reg))
7425 /* If X is (abs REG) and we know something about REG's relationship
7426 with zero, we may be able to simplify this. */
7428 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7431 case GE: case GT: case EQ:
7434 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7440 /* The only other cases we handle are MIN, MAX, and comparisons if the
7441 operands are the same as REG and VAL. */
7443 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7445 if (rtx_equal_p (XEXP (x, 0), val))
7446 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7448 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7450 if (GET_RTX_CLASS (code) == '<')
7452 if (comparison_dominates_p (cond, code))
7453 return const_true_rtx;
7455 code = reverse_condition (code);
7457 && comparison_dominates_p (cond, code))
7462 else if (code == SMAX || code == SMIN
7463 || code == UMIN || code == UMAX)
7465 int unsignedp = (code == UMIN || code == UMAX);
7467 if (code == SMAX || code == UMAX)
7468 cond = reverse_condition (cond);
7473 return unsignedp ? x : XEXP (x, 1);
7475 return unsignedp ? x : XEXP (x, 0);
7477 return unsignedp ? XEXP (x, 1) : x;
7479 return unsignedp ? XEXP (x, 0) : x;
7487 fmt = GET_RTX_FORMAT (code);
7488 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7491 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7492 else if (fmt[i] == 'E')
7493 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7494 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7501 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7502 assignment as a field assignment. */
7505 rtx_equal_for_field_assignment_p (x, y)
7509 if (x == y || rtx_equal_p (x, y))
7512 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7515 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7516 Note that all SUBREGs of MEM are paradoxical; otherwise they
7517 would have been rewritten. */
7518 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7519 && GET_CODE (SUBREG_REG (y)) == MEM
7520 && rtx_equal_p (SUBREG_REG (y),
7521 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7524 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7525 && GET_CODE (SUBREG_REG (x)) == MEM
7526 && rtx_equal_p (SUBREG_REG (x),
7527 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7530 /* We used to see if get_last_value of X and Y were the same but that's
7531 not correct. In one direction, we'll cause the assignment to have
7532 the wrong destination and in the case, we'll import a register into this
7533 insn that might have already have been dead. So fail if none of the
7534 above cases are true. */
7538 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7539 Return that assignment if so.
7541 We only handle the most common cases. */
7544 make_field_assignment (x)
7547 rtx dest = SET_DEST (x);
7548 rtx src = SET_SRC (x);
7553 unsigned HOST_WIDE_INT len;
7555 enum machine_mode mode;
7557 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7558 a clear of a one-bit field. We will have changed it to
7559 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7562 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7563 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7564 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7565 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7567 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7570 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7574 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7575 && subreg_lowpart_p (XEXP (src, 0))
7576 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7577 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7578 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7579 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7580 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7582 assign = make_extraction (VOIDmode, dest, 0,
7583 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7586 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7590 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7592 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7593 && XEXP (XEXP (src, 0), 0) == const1_rtx
7594 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7596 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7599 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7603 /* The other case we handle is assignments into a constant-position
7604 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7605 a mask that has all one bits except for a group of zero bits and
7606 OTHER is known to have zeros where C1 has ones, this is such an
7607 assignment. Compute the position and length from C1. Shift OTHER
7608 to the appropriate position, force it to the required mode, and
7609 make the extraction. Check for the AND in both operands. */
7611 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7614 rhs = expand_compound_operation (XEXP (src, 0));
7615 lhs = expand_compound_operation (XEXP (src, 1));
7617 if (GET_CODE (rhs) == AND
7618 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7619 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7620 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7621 else if (GET_CODE (lhs) == AND
7622 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7623 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7624 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7628 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7629 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7630 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7631 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7634 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7638 /* The mode to use for the source is the mode of the assignment, or of
7639 what is inside a possible STRICT_LOW_PART. */
7640 mode = (GET_CODE (assign) == STRICT_LOW_PART
7641 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7643 /* Shift OTHER right POS places and make it the source, restricting it
7644 to the proper length and mode. */
7646 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7647 GET_MODE (src), other, pos),
7649 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7650 ? ~(HOST_WIDE_INT) 0
7651 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7654 return gen_rtx_combine (SET, VOIDmode, assign, src);
7657 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7661 apply_distributive_law (x)
7664 enum rtx_code code = GET_CODE (x);
7665 rtx lhs, rhs, other;
7667 enum rtx_code inner_code;
7669 /* Distributivity is not true for floating point.
7670 It can change the value. So don't do it.
7671 -- rms and moshier@world.std.com. */
7672 if (FLOAT_MODE_P (GET_MODE (x)))
7675 /* The outer operation can only be one of the following: */
7676 if (code != IOR && code != AND && code != XOR
7677 && code != PLUS && code != MINUS)
7680 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7682 /* If either operand is a primitive we can't do anything, so get out
7684 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7685 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7688 lhs = expand_compound_operation (lhs);
7689 rhs = expand_compound_operation (rhs);
7690 inner_code = GET_CODE (lhs);
7691 if (inner_code != GET_CODE (rhs))
7694 /* See if the inner and outer operations distribute. */
7701 /* These all distribute except over PLUS. */
7702 if (code == PLUS || code == MINUS)
7707 if (code != PLUS && code != MINUS)
7712 /* This is also a multiply, so it distributes over everything. */
7716 /* Non-paradoxical SUBREGs distributes over all operations, provided
7717 the inner modes and word numbers are the same, this is an extraction
7718 of a low-order part, we don't convert an fp operation to int or
7719 vice versa, and we would not be converting a single-word
7720 operation into a multi-word operation. The latter test is not
7721 required, but it prevents generating unneeded multi-word operations.
7722 Some of the previous tests are redundant given the latter test, but
7723 are retained because they are required for correctness.
7725 We produce the result slightly differently in this case. */
7727 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7728 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7729 || ! subreg_lowpart_p (lhs)
7730 || (GET_MODE_CLASS (GET_MODE (lhs))
7731 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7732 || (GET_MODE_SIZE (GET_MODE (lhs))
7733 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7734 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7737 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7738 SUBREG_REG (lhs), SUBREG_REG (rhs));
7739 return gen_lowpart_for_combine (GET_MODE (x), tem);
7745 /* Set LHS and RHS to the inner operands (A and B in the example
7746 above) and set OTHER to the common operand (C in the example).
7747 These is only one way to do this unless the inner operation is
7749 if (GET_RTX_CLASS (inner_code) == 'c'
7750 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7751 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7752 else if (GET_RTX_CLASS (inner_code) == 'c'
7753 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7754 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7755 else if (GET_RTX_CLASS (inner_code) == 'c'
7756 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7757 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7758 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7759 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7763 /* Form the new inner operation, seeing if it simplifies first. */
7764 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7766 /* There is one exception to the general way of distributing:
7767 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7768 if (code == XOR && inner_code == IOR)
7771 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7774 /* We may be able to continuing distributing the result, so call
7775 ourselves recursively on the inner operation before forming the
7776 outer operation, which we return. */
7777 return gen_binary (inner_code, GET_MODE (x),
7778 apply_distributive_law (tem), other);
7781 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7784 Return an equivalent form, if different from X. Otherwise, return X. If
7785 X is zero, we are to always construct the equivalent form. */
7788 simplify_and_const_int (x, mode, varop, constop)
7790 enum machine_mode mode;
7792 unsigned HOST_WIDE_INT constop;
7794 unsigned HOST_WIDE_INT nonzero;
7797 /* Simplify VAROP knowing that we will be only looking at some of the
7799 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7801 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7802 CONST_INT, we are done. */
7803 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7806 /* See what bits may be nonzero in VAROP. Unlike the general case of
7807 a call to nonzero_bits, here we don't care about bits outside
7810 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7811 nonzero = trunc_int_for_mode (nonzero, mode);
7813 /* Turn off all bits in the constant that are known to already be zero.
7814 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7815 which is tested below. */
7819 /* If we don't have any bits left, return zero. */
7823 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7824 a power of two, we can replace this with a ASHIFT. */
7825 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7826 && (i = exact_log2 (constop)) >= 0)
7827 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7829 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7830 or XOR, then try to apply the distributive law. This may eliminate
7831 operations if either branch can be simplified because of the AND.
7832 It may also make some cases more complex, but those cases probably
7833 won't match a pattern either with or without this. */
7835 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7837 gen_lowpart_for_combine
7839 apply_distributive_law
7840 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7841 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7842 XEXP (varop, 0), constop),
7843 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7844 XEXP (varop, 1), constop))));
7846 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7847 if we already had one (just check for the simplest cases). */
7848 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7849 && GET_MODE (XEXP (x, 0)) == mode
7850 && SUBREG_REG (XEXP (x, 0)) == varop)
7851 varop = XEXP (x, 0);
7853 varop = gen_lowpart_for_combine (mode, varop);
7855 /* If we can't make the SUBREG, try to return what we were given. */
7856 if (GET_CODE (varop) == CLOBBER)
7857 return x ? x : varop;
7859 /* If we are only masking insignificant bits, return VAROP. */
7860 if (constop == nonzero)
7863 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7864 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7865 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7869 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7870 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7871 SUBST (XEXP (x, 1), GEN_INT (constop));
7873 SUBST (XEXP (x, 0), varop);
7879 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7880 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7881 is less useful. We can't allow both, because that results in exponential
7882 run time recursion. There is a nullstone testcase that triggered
7883 this. This macro avoids accidental uses of num_sign_bit_copies. */
7884 #define num_sign_bit_copies()
7886 /* Given an expression, X, compute which bits in X can be non-zero.
7887 We don't care about bits outside of those defined in MODE.
7889 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7890 a shift, AND, or zero_extract, we can do better. */
7892 static unsigned HOST_WIDE_INT
7893 nonzero_bits (x, mode)
7895 enum machine_mode mode;
7897 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7898 unsigned HOST_WIDE_INT inner_nz;
7900 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7903 /* For floating-point values, assume all bits are needed. */
7904 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7907 /* If X is wider than MODE, use its mode instead. */
7908 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7910 mode = GET_MODE (x);
7911 nonzero = GET_MODE_MASK (mode);
7912 mode_width = GET_MODE_BITSIZE (mode);
7915 if (mode_width > HOST_BITS_PER_WIDE_INT)
7916 /* Our only callers in this case look for single bit values. So
7917 just return the mode mask. Those tests will then be false. */
7920 #ifndef WORD_REGISTER_OPERATIONS
7921 /* If MODE is wider than X, but both are a single word for both the host
7922 and target machines, we can compute this from which bits of the
7923 object might be nonzero in its own mode, taking into account the fact
7924 that on many CISC machines, accessing an object in a wider mode
7925 causes the high-order bits to become undefined. So they are
7926 not known to be zero. */
7928 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7929 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7930 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7931 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7933 nonzero &= nonzero_bits (x, GET_MODE (x));
7934 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7939 code = GET_CODE (x);
7943 #ifdef POINTERS_EXTEND_UNSIGNED
7944 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7945 all the bits above ptr_mode are known to be zero. */
7946 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7947 && REGNO_POINTER_FLAG (REGNO (x)))
7948 nonzero &= GET_MODE_MASK (ptr_mode);
7951 #ifdef STACK_BOUNDARY
7952 /* If this is the stack pointer, we may know something about its
7953 alignment. If PUSH_ROUNDING is defined, it is possible for the
7954 stack to be momentarily aligned only to that amount, so we pick
7955 the least alignment. */
7957 /* We can't check for arg_pointer_rtx here, because it is not
7958 guaranteed to have as much alignment as the stack pointer.
7959 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7960 alignment but the argument pointer has only 64 bit alignment. */
7962 if ((x == frame_pointer_rtx
7963 || x == stack_pointer_rtx
7964 || x == hard_frame_pointer_rtx
7965 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7966 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7972 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7974 #ifdef PUSH_ROUNDING
7975 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7976 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7979 /* We must return here, otherwise we may get a worse result from
7980 one of the choices below. There is nothing useful below as
7981 far as the stack pointer is concerned. */
7982 return nonzero &= ~ (sp_alignment - 1);
7986 /* If X is a register whose nonzero bits value is current, use it.
7987 Otherwise, if X is a register whose value we can find, use that
7988 value. Otherwise, use the previously-computed global nonzero bits
7989 for this register. */
7991 if (reg_last_set_value[REGNO (x)] != 0
7992 && reg_last_set_mode[REGNO (x)] == mode
7993 && (reg_last_set_label[REGNO (x)] == label_tick
7994 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7995 && REG_N_SETS (REGNO (x)) == 1
7996 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7998 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7999 return reg_last_set_nonzero_bits[REGNO (x)];
8001 tem = get_last_value (x);
8005 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8006 /* If X is narrower than MODE and TEM is a non-negative
8007 constant that would appear negative in the mode of X,
8008 sign-extend it for use in reg_nonzero_bits because some
8009 machines (maybe most) will actually do the sign-extension
8010 and this is the conservative approach.
8012 ??? For 2.5, try to tighten up the MD files in this regard
8013 instead of this kludge. */
8015 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8016 && GET_CODE (tem) == CONST_INT
8018 && 0 != (INTVAL (tem)
8019 & ((HOST_WIDE_INT) 1
8020 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8021 tem = GEN_INT (INTVAL (tem)
8022 | ((HOST_WIDE_INT) (-1)
8023 << GET_MODE_BITSIZE (GET_MODE (x))));
8025 return nonzero_bits (tem, mode);
8027 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8028 return reg_nonzero_bits[REGNO (x)] & nonzero;
8033 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8034 /* If X is negative in MODE, sign-extend the value. */
8035 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8036 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8037 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8043 #ifdef LOAD_EXTEND_OP
8044 /* In many, if not most, RISC machines, reading a byte from memory
8045 zeros the rest of the register. Noticing that fact saves a lot
8046 of extra zero-extends. */
8047 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8048 nonzero &= GET_MODE_MASK (GET_MODE (x));
8058 /* If this produces an integer result, we know which bits are set.
8059 Code here used to clear bits outside the mode of X, but that is
8062 if (GET_MODE_CLASS (mode) == MODE_INT
8063 && mode_width <= HOST_BITS_PER_WIDE_INT)
8064 nonzero = STORE_FLAG_VALUE;
8069 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8070 and num_sign_bit_copies. */
8071 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8072 == GET_MODE_BITSIZE (GET_MODE (x)))
8076 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8077 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
8082 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8083 and num_sign_bit_copies. */
8084 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8085 == GET_MODE_BITSIZE (GET_MODE (x)))
8091 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8095 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8096 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8097 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8101 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8102 Otherwise, show all the bits in the outer mode but not the inner
8104 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8105 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8107 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8109 & (((HOST_WIDE_INT) 1
8110 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8111 inner_nz |= (GET_MODE_MASK (mode)
8112 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8115 nonzero &= inner_nz;
8119 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8120 & nonzero_bits (XEXP (x, 1), mode));
8124 case UMIN: case UMAX: case SMIN: case SMAX:
8125 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8126 | nonzero_bits (XEXP (x, 1), mode));
8129 case PLUS: case MINUS:
8131 case DIV: case UDIV:
8132 case MOD: case UMOD:
8133 /* We can apply the rules of arithmetic to compute the number of
8134 high- and low-order zero bits of these operations. We start by
8135 computing the width (position of the highest-order non-zero bit)
8136 and the number of low-order zero bits for each value. */
8138 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8139 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8140 int width0 = floor_log2 (nz0) + 1;
8141 int width1 = floor_log2 (nz1) + 1;
8142 int low0 = floor_log2 (nz0 & -nz0);
8143 int low1 = floor_log2 (nz1 & -nz1);
8144 HOST_WIDE_INT op0_maybe_minusp
8145 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8146 HOST_WIDE_INT op1_maybe_minusp
8147 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8148 unsigned int result_width = mode_width;
8156 && (XEXP (x, 0) == stack_pointer_rtx
8157 || XEXP (x, 0) == frame_pointer_rtx)
8158 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8160 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8162 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8163 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8164 width0 = floor_log2 (nz0) + 1;
8165 width1 = floor_log2 (nz1) + 1;
8166 low0 = floor_log2 (nz0 & -nz0);
8167 low1 = floor_log2 (nz1 & -nz1);
8170 result_width = MAX (width0, width1) + 1;
8171 result_low = MIN (low0, low1);
8174 result_low = MIN (low0, low1);
8177 result_width = width0 + width1;
8178 result_low = low0 + low1;
8181 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8182 result_width = width0;
8185 result_width = width0;
8188 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8189 result_width = MIN (width0, width1);
8190 result_low = MIN (low0, low1);
8193 result_width = MIN (width0, width1);
8194 result_low = MIN (low0, low1);
8200 if (result_width < mode_width)
8201 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8204 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8209 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8210 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8211 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8215 /* If this is a SUBREG formed for a promoted variable that has
8216 been zero-extended, we know that at least the high-order bits
8217 are zero, though others might be too. */
8219 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8220 nonzero = (GET_MODE_MASK (GET_MODE (x))
8221 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8223 /* If the inner mode is a single word for both the host and target
8224 machines, we can compute this from which bits of the inner
8225 object might be nonzero. */
8226 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8227 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8228 <= HOST_BITS_PER_WIDE_INT))
8230 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8232 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8233 /* If this is a typical RISC machine, we only have to worry
8234 about the way loads are extended. */
8235 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8237 & (((unsigned HOST_WIDE_INT) 1
8238 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8240 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8243 /* On many CISC machines, accessing an object in a wider mode
8244 causes the high-order bits to become undefined. So they are
8245 not known to be zero. */
8246 if (GET_MODE_SIZE (GET_MODE (x))
8247 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8248 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8249 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8258 /* The nonzero bits are in two classes: any bits within MODE
8259 that aren't in GET_MODE (x) are always significant. The rest of the
8260 nonzero bits are those that are significant in the operand of
8261 the shift when shifted the appropriate number of bits. This
8262 shows that high-order bits are cleared by the right shift and
8263 low-order bits by left shifts. */
8264 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8265 && INTVAL (XEXP (x, 1)) >= 0
8266 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8268 enum machine_mode inner_mode = GET_MODE (x);
8269 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8270 int count = INTVAL (XEXP (x, 1));
8271 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8272 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8273 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8274 unsigned HOST_WIDE_INT outer = 0;
8276 if (mode_width > width)
8277 outer = (op_nonzero & nonzero & ~ mode_mask);
8279 if (code == LSHIFTRT)
8281 else if (code == ASHIFTRT)
8285 /* If the sign bit may have been nonzero before the shift, we
8286 need to mark all the places it could have been copied to
8287 by the shift as possibly nonzero. */
8288 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8289 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8291 else if (code == ASHIFT)
8294 inner = ((inner << (count % width)
8295 | (inner >> (width - (count % width)))) & mode_mask);
8297 nonzero &= (outer | inner);
8302 /* This is at most the number of bits in the mode. */
8303 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8307 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8308 | nonzero_bits (XEXP (x, 2), mode));
8318 /* See the macro definition above. */
8319 #undef num_sign_bit_copies
8321 /* Return the number of bits at the high-order end of X that are known to
8322 be equal to the sign bit. X will be used in mode MODE; if MODE is
8323 VOIDmode, X will be used in its own mode. The returned value will always
8324 be between 1 and the number of bits in MODE. */
8327 num_sign_bit_copies (x, mode)
8329 enum machine_mode mode;
8331 enum rtx_code code = GET_CODE (x);
8332 unsigned int bitwidth;
8333 int num0, num1, result;
8334 unsigned HOST_WIDE_INT nonzero;
8337 /* If we weren't given a mode, use the mode of X. If the mode is still
8338 VOIDmode, we don't know anything. Likewise if one of the modes is
8341 if (mode == VOIDmode)
8342 mode = GET_MODE (x);
8344 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8347 bitwidth = GET_MODE_BITSIZE (mode);
8349 /* For a smaller object, just ignore the high bits. */
8350 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8352 num0 = num_sign_bit_copies (x, GET_MODE (x));
8354 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8357 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8359 #ifndef WORD_REGISTER_OPERATIONS
8360 /* If this machine does not do all register operations on the entire
8361 register and MODE is wider than the mode of X, we can say nothing
8362 at all about the high-order bits. */
8365 /* Likewise on machines that do, if the mode of the object is smaller
8366 than a word and loads of that size don't sign extend, we can say
8367 nothing about the high order bits. */
8368 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8369 #ifdef LOAD_EXTEND_OP
8370 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8381 #ifdef POINTERS_EXTEND_UNSIGNED
8382 /* If pointers extend signed and this is a pointer in Pmode, say that
8383 all the bits above ptr_mode are known to be sign bit copies. */
8384 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8385 && REGNO_POINTER_FLAG (REGNO (x)))
8386 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8389 if (reg_last_set_value[REGNO (x)] != 0
8390 && reg_last_set_mode[REGNO (x)] == mode
8391 && (reg_last_set_label[REGNO (x)] == label_tick
8392 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8393 && REG_N_SETS (REGNO (x)) == 1
8394 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8396 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8397 return reg_last_set_sign_bit_copies[REGNO (x)];
8399 tem = get_last_value (x);
8401 return num_sign_bit_copies (tem, mode);
8403 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8404 return reg_sign_bit_copies[REGNO (x)];
8408 #ifdef LOAD_EXTEND_OP
8409 /* Some RISC machines sign-extend all loads of smaller than a word. */
8410 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8411 return MAX (1, ((int) bitwidth
8412 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8417 /* If the constant is negative, take its 1's complement and remask.
8418 Then see how many zero bits we have. */
8419 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8420 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8421 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8422 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8424 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8427 /* If this is a SUBREG for a promoted object that is sign-extended
8428 and we are looking at it in a wider mode, we know that at least the
8429 high-order bits are known to be sign bit copies. */
8431 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8433 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8434 return MAX ((int) bitwidth
8435 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8439 /* For a smaller object, just ignore the high bits. */
8440 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8442 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8443 return MAX (1, (num0
8444 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8448 #ifdef WORD_REGISTER_OPERATIONS
8449 #ifdef LOAD_EXTEND_OP
8450 /* For paradoxical SUBREGs on machines where all register operations
8451 affect the entire register, just look inside. Note that we are
8452 passing MODE to the recursive call, so the number of sign bit copies
8453 will remain relative to that mode, not the inner mode. */
8455 /* This works only if loads sign extend. Otherwise, if we get a
8456 reload for the inner part, it may be loaded from the stack, and
8457 then we lose all sign bit copies that existed before the store
8460 if ((GET_MODE_SIZE (GET_MODE (x))
8461 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8462 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8463 return num_sign_bit_copies (SUBREG_REG (x), mode);
8469 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8470 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8474 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8475 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8478 /* For a smaller object, just ignore the high bits. */
8479 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8480 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8484 return num_sign_bit_copies (XEXP (x, 0), mode);
8486 case ROTATE: case ROTATERT:
8487 /* If we are rotating left by a number of bits less than the number
8488 of sign bit copies, we can just subtract that amount from the
8490 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8491 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8493 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8494 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8495 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8500 /* In general, this subtracts one sign bit copy. But if the value
8501 is known to be positive, the number of sign bit copies is the
8502 same as that of the input. Finally, if the input has just one bit
8503 that might be nonzero, all the bits are copies of the sign bit. */
8504 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8505 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8506 return num0 > 1 ? num0 - 1 : 1;
8508 nonzero = nonzero_bits (XEXP (x, 0), mode);
8513 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8518 case IOR: case AND: case XOR:
8519 case SMIN: case SMAX: case UMIN: case UMAX:
8520 /* Logical operations will preserve the number of sign-bit copies.
8521 MIN and MAX operations always return one of the operands. */
8522 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8523 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8524 return MIN (num0, num1);
8526 case PLUS: case MINUS:
8527 /* For addition and subtraction, we can have a 1-bit carry. However,
8528 if we are subtracting 1 from a positive number, there will not
8529 be such a carry. Furthermore, if the positive number is known to
8530 be 0 or 1, we know the result is either -1 or 0. */
8532 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8533 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8535 nonzero = nonzero_bits (XEXP (x, 0), mode);
8536 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8537 return (nonzero == 1 || nonzero == 0 ? bitwidth
8538 : bitwidth - floor_log2 (nonzero) - 1);
8541 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8542 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8543 return MAX (1, MIN (num0, num1) - 1);
8546 /* The number of bits of the product is the sum of the number of
8547 bits of both terms. However, unless one of the terms if known
8548 to be positive, we must allow for an additional bit since negating
8549 a negative number can remove one sign bit copy. */
8551 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8552 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8554 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8556 && (bitwidth > HOST_BITS_PER_WIDE_INT
8557 || (((nonzero_bits (XEXP (x, 0), mode)
8558 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8559 && ((nonzero_bits (XEXP (x, 1), mode)
8560 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8563 return MAX (1, result);
8566 /* The result must be <= the first operand. If the first operand
8567 has the high bit set, we know nothing about the number of sign
8569 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8571 else if ((nonzero_bits (XEXP (x, 0), mode)
8572 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8575 return num_sign_bit_copies (XEXP (x, 0), mode);
8578 /* The result must be <= the scond operand. */
8579 return num_sign_bit_copies (XEXP (x, 1), mode);
8582 /* Similar to unsigned division, except that we have to worry about
8583 the case where the divisor is negative, in which case we have
8585 result = num_sign_bit_copies (XEXP (x, 0), mode);
8587 && (bitwidth > HOST_BITS_PER_WIDE_INT
8588 || (nonzero_bits (XEXP (x, 1), mode)
8589 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8595 result = num_sign_bit_copies (XEXP (x, 1), mode);
8597 && (bitwidth > HOST_BITS_PER_WIDE_INT
8598 || (nonzero_bits (XEXP (x, 1), mode)
8599 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8605 /* Shifts by a constant add to the number of bits equal to the
8607 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8608 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8609 && INTVAL (XEXP (x, 1)) > 0)
8610 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8615 /* Left shifts destroy copies. */
8616 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8617 || INTVAL (XEXP (x, 1)) < 0
8618 || INTVAL (XEXP (x, 1)) >= bitwidth)
8621 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8622 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8625 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8626 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8627 return MIN (num0, num1);
8629 case EQ: case NE: case GE: case GT: case LE: case LT:
8630 case GEU: case GTU: case LEU: case LTU:
8631 if (STORE_FLAG_VALUE == -1)
8639 /* If we haven't been able to figure it out by one of the above rules,
8640 see if some of the high-order bits are known to be zero. If so,
8641 count those bits and return one less than that amount. If we can't
8642 safely compute the mask for this mode, always return BITWIDTH. */
8644 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8647 nonzero = nonzero_bits (x, mode);
8648 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8649 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8652 /* Return the number of "extended" bits there are in X, when interpreted
8653 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8654 unsigned quantities, this is the number of high-order zero bits.
8655 For signed quantities, this is the number of copies of the sign bit
8656 minus 1. In both case, this function returns the number of "spare"
8657 bits. For example, if two quantities for which this function returns
8658 at least 1 are added, the addition is known not to overflow.
8660 This function will always return 0 unless called during combine, which
8661 implies that it must be called from a define_split. */
8664 extended_count (x, mode, unsignedp)
8666 enum machine_mode mode;
8669 if (nonzero_sign_valid == 0)
8673 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8674 ? (GET_MODE_BITSIZE (mode) - 1
8675 - floor_log2 (nonzero_bits (x, mode)))
8677 : num_sign_bit_copies (x, mode) - 1);
8680 /* This function is called from `simplify_shift_const' to merge two
8681 outer operations. Specifically, we have already found that we need
8682 to perform operation *POP0 with constant *PCONST0 at the outermost
8683 position. We would now like to also perform OP1 with constant CONST1
8684 (with *POP0 being done last).
8686 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8687 the resulting operation. *PCOMP_P is set to 1 if we would need to
8688 complement the innermost operand, otherwise it is unchanged.
8690 MODE is the mode in which the operation will be done. No bits outside
8691 the width of this mode matter. It is assumed that the width of this mode
8692 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8694 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8695 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8696 result is simply *PCONST0.
8698 If the resulting operation cannot be expressed as one operation, we
8699 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8702 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8703 enum rtx_code *pop0;
8704 HOST_WIDE_INT *pconst0;
8706 HOST_WIDE_INT const1;
8707 enum machine_mode mode;
8710 enum rtx_code op0 = *pop0;
8711 HOST_WIDE_INT const0 = *pconst0;
8713 const0 &= GET_MODE_MASK (mode);
8714 const1 &= GET_MODE_MASK (mode);
8716 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8720 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8723 if (op1 == NIL || op0 == SET)
8726 else if (op0 == NIL)
8727 op0 = op1, const0 = const1;
8729 else if (op0 == op1)
8753 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8754 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8757 /* If the two constants aren't the same, we can't do anything. The
8758 remaining six cases can all be done. */
8759 else if (const0 != const1)
8767 /* (a & b) | b == b */
8769 else /* op1 == XOR */
8770 /* (a ^ b) | b == a | b */
8776 /* (a & b) ^ b == (~a) & b */
8777 op0 = AND, *pcomp_p = 1;
8778 else /* op1 == IOR */
8779 /* (a | b) ^ b == a & ~b */
8780 op0 = AND, *pconst0 = ~ const0;
8785 /* (a | b) & b == b */
8787 else /* op1 == XOR */
8788 /* (a ^ b) & b) == (~a) & b */
8795 /* Check for NO-OP cases. */
8796 const0 &= GET_MODE_MASK (mode);
8798 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8800 else if (const0 == 0 && op0 == AND)
8802 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8806 /* ??? Slightly redundant with the above mask, but not entirely.
8807 Moving this above means we'd have to sign-extend the mode mask
8808 for the final test. */
8809 const0 = trunc_int_for_mode (const0, mode);
8817 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8818 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8819 that we started with.
8821 The shift is normally computed in the widest mode we find in VAROP, as
8822 long as it isn't a different number of words than RESULT_MODE. Exceptions
8823 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8826 simplify_shift_const (x, code, result_mode, varop, input_count)
8829 enum machine_mode result_mode;
8833 enum rtx_code orig_code = code;
8834 int orig_count = input_count;
8837 enum machine_mode mode = result_mode;
8838 enum machine_mode shift_mode, tmode;
8839 unsigned int mode_words
8840 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8841 /* We form (outer_op (code varop count) (outer_const)). */
8842 enum rtx_code outer_op = NIL;
8843 HOST_WIDE_INT outer_const = 0;
8845 int complement_p = 0;
8848 /* If we were given an invalid count, don't do anything except exactly
8849 what was requested. */
8851 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8856 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8859 count = input_count;
8861 /* Unless one of the branches of the `if' in this loop does a `continue',
8862 we will `break' the loop after the `if'. */
8866 /* If we have an operand of (clobber (const_int 0)), just return that
8868 if (GET_CODE (varop) == CLOBBER)
8871 /* If we discovered we had to complement VAROP, leave. Making a NOT
8872 here would cause an infinite loop. */
8876 /* Convert ROTATERT to ROTATE. */
8877 if (code == ROTATERT)
8878 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8880 /* We need to determine what mode we will do the shift in. If the
8881 shift is a right shift or a ROTATE, we must always do it in the mode
8882 it was originally done in. Otherwise, we can do it in MODE, the
8883 widest mode encountered. */
8885 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8886 ? result_mode : mode);
8888 /* Handle cases where the count is greater than the size of the mode
8889 minus 1. For ASHIFT, use the size minus one as the count (this can
8890 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8891 take the count modulo the size. For other shifts, the result is
8894 Since these shifts are being produced by the compiler by combining
8895 multiple operations, each of which are defined, we know what the
8896 result is supposed to be. */
8898 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8900 if (code == ASHIFTRT)
8901 count = GET_MODE_BITSIZE (shift_mode) - 1;
8902 else if (code == ROTATE || code == ROTATERT)
8903 count %= GET_MODE_BITSIZE (shift_mode);
8906 /* We can't simply return zero because there may be an
8914 /* An arithmetic right shift of a quantity known to be -1 or 0
8916 if (code == ASHIFTRT
8917 && (num_sign_bit_copies (varop, shift_mode)
8918 == GET_MODE_BITSIZE (shift_mode)))
8924 /* If we are doing an arithmetic right shift and discarding all but
8925 the sign bit copies, this is equivalent to doing a shift by the
8926 bitsize minus one. Convert it into that shift because it will often
8927 allow other simplifications. */
8929 if (code == ASHIFTRT
8930 && (count + num_sign_bit_copies (varop, shift_mode)
8931 >= GET_MODE_BITSIZE (shift_mode)))
8932 count = GET_MODE_BITSIZE (shift_mode) - 1;
8934 /* We simplify the tests below and elsewhere by converting
8935 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8936 `make_compound_operation' will convert it to a ASHIFTRT for
8937 those machines (such as Vax) that don't have a LSHIFTRT. */
8938 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8940 && ((nonzero_bits (varop, shift_mode)
8941 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8945 switch (GET_CODE (varop))
8951 new = expand_compound_operation (varop);
8960 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8961 minus the width of a smaller mode, we can do this with a
8962 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8963 if ((code == ASHIFTRT || code == LSHIFTRT)
8964 && ! mode_dependent_address_p (XEXP (varop, 0))
8965 && ! MEM_VOLATILE_P (varop)
8966 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8967 MODE_INT, 1)) != BLKmode)
8969 if (BYTES_BIG_ENDIAN)
8970 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8972 new = gen_rtx_MEM (tmode,
8973 plus_constant (XEXP (varop, 0),
8974 count / BITS_PER_UNIT));
8976 MEM_COPY_ATTRIBUTES (new, varop);
8977 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8978 : ZERO_EXTEND, mode, new);
8985 /* Similar to the case above, except that we can only do this if
8986 the resulting mode is the same as that of the underlying
8987 MEM and adjust the address depending on the *bits* endianness
8988 because of the way that bit-field extract insns are defined. */
8989 if ((code == ASHIFTRT || code == LSHIFTRT)
8990 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8991 MODE_INT, 1)) != BLKmode
8992 && tmode == GET_MODE (XEXP (varop, 0)))
8994 if (BITS_BIG_ENDIAN)
8995 new = XEXP (varop, 0);
8998 new = copy_rtx (XEXP (varop, 0));
8999 SUBST (XEXP (new, 0),
9000 plus_constant (XEXP (new, 0),
9001 count / BITS_PER_UNIT));
9004 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9005 : ZERO_EXTEND, mode, new);
9012 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9013 the same number of words as what we've seen so far. Then store
9014 the widest mode in MODE. */
9015 if (subreg_lowpart_p (varop)
9016 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9017 > GET_MODE_SIZE (GET_MODE (varop)))
9018 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9019 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9022 varop = SUBREG_REG (varop);
9023 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9024 mode = GET_MODE (varop);
9030 /* Some machines use MULT instead of ASHIFT because MULT
9031 is cheaper. But it is still better on those machines to
9032 merge two shifts into one. */
9033 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9034 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9037 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9038 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9044 /* Similar, for when divides are cheaper. */
9045 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9046 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9049 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9050 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9056 /* If we are extracting just the sign bit of an arithmetic right
9057 shift, that shift is not needed. */
9058 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9060 varop = XEXP (varop, 0);
9064 /* ... fall through ... */
9069 /* Here we have two nested shifts. The result is usually the
9070 AND of a new shift with a mask. We compute the result below. */
9071 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9072 && INTVAL (XEXP (varop, 1)) >= 0
9073 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9074 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9075 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9077 enum rtx_code first_code = GET_CODE (varop);
9078 unsigned int first_count = INTVAL (XEXP (varop, 1));
9079 unsigned HOST_WIDE_INT mask;
9082 /* We have one common special case. We can't do any merging if
9083 the inner code is an ASHIFTRT of a smaller mode. However, if
9084 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9085 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9086 we can convert it to
9087 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9088 This simplifies certain SIGN_EXTEND operations. */
9089 if (code == ASHIFT && first_code == ASHIFTRT
9090 && (GET_MODE_BITSIZE (result_mode)
9091 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9093 /* C3 has the low-order C1 bits zero. */
9095 mask = (GET_MODE_MASK (mode)
9096 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
9098 varop = simplify_and_const_int (NULL_RTX, result_mode,
9099 XEXP (varop, 0), mask);
9100 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9102 count = first_count;
9107 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9108 than C1 high-order bits equal to the sign bit, we can convert
9109 this to either an ASHIFT or a ASHIFTRT depending on the
9112 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9114 if (code == ASHIFTRT && first_code == ASHIFT
9115 && GET_MODE (varop) == shift_mode
9116 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9119 varop = XEXP (varop, 0);
9121 signed_count = count - first_count;
9122 if (signed_count < 0)
9123 count = - signed_count, code = ASHIFT;
9125 count = signed_count;
9130 /* There are some cases we can't do. If CODE is ASHIFTRT,
9131 we can only do this if FIRST_CODE is also ASHIFTRT.
9133 We can't do the case when CODE is ROTATE and FIRST_CODE is
9136 If the mode of this shift is not the mode of the outer shift,
9137 we can't do this if either shift is a right shift or ROTATE.
9139 Finally, we can't do any of these if the mode is too wide
9140 unless the codes are the same.
9142 Handle the case where the shift codes are the same
9145 if (code == first_code)
9147 if (GET_MODE (varop) != result_mode
9148 && (code == ASHIFTRT || code == LSHIFTRT
9152 count += first_count;
9153 varop = XEXP (varop, 0);
9157 if (code == ASHIFTRT
9158 || (code == ROTATE && first_code == ASHIFTRT)
9159 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9160 || (GET_MODE (varop) != result_mode
9161 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9162 || first_code == ROTATE
9163 || code == ROTATE)))
9166 /* To compute the mask to apply after the shift, shift the
9167 nonzero bits of the inner shift the same way the
9168 outer shift will. */
9170 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9173 = simplify_binary_operation (code, result_mode, mask_rtx,
9176 /* Give up if we can't compute an outer operation to use. */
9178 || GET_CODE (mask_rtx) != CONST_INT
9179 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9181 result_mode, &complement_p))
9184 /* If the shifts are in the same direction, we add the
9185 counts. Otherwise, we subtract them. */
9186 signed_count = count;
9187 if ((code == ASHIFTRT || code == LSHIFTRT)
9188 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9189 signed_count += first_count;
9191 signed_count -= first_count;
9193 /* If COUNT is positive, the new shift is usually CODE,
9194 except for the two exceptions below, in which case it is
9195 FIRST_CODE. If the count is negative, FIRST_CODE should
9197 if (signed_count > 0
9198 && ((first_code == ROTATE && code == ASHIFT)
9199 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9200 code = first_code, count = signed_count;
9201 else if (signed_count < 0)
9202 code = first_code, count = - signed_count;
9204 count = signed_count;
9206 varop = XEXP (varop, 0);
9210 /* If we have (A << B << C) for any shift, we can convert this to
9211 (A << C << B). This wins if A is a constant. Only try this if
9212 B is not a constant. */
9214 else if (GET_CODE (varop) == code
9215 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9217 = simplify_binary_operation (code, mode,
9221 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9228 /* Make this fit the case below. */
9229 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9230 GEN_INT (GET_MODE_MASK (mode)));
9236 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9237 with C the size of VAROP - 1 and the shift is logical if
9238 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9239 we have an (le X 0) operation. If we have an arithmetic shift
9240 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9241 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9243 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9244 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9245 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9246 && (code == LSHIFTRT || code == ASHIFTRT)
9247 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9248 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9251 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9254 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9255 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9260 /* If we have (shift (logical)), move the logical to the outside
9261 to allow it to possibly combine with another logical and the
9262 shift to combine with another shift. This also canonicalizes to
9263 what a ZERO_EXTRACT looks like. Also, some machines have
9264 (and (shift)) insns. */
9266 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9267 && (new = simplify_binary_operation (code, result_mode,
9269 GEN_INT (count))) != 0
9270 && GET_CODE(new) == CONST_INT
9271 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9272 INTVAL (new), result_mode, &complement_p))
9274 varop = XEXP (varop, 0);
9278 /* If we can't do that, try to simplify the shift in each arm of the
9279 logical expression, make a new logical expression, and apply
9280 the inverse distributive law. */
9282 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9283 XEXP (varop, 0), count);
9284 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9285 XEXP (varop, 1), count);
9287 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9288 varop = apply_distributive_law (varop);
9295 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9296 says that the sign bit can be tested, FOO has mode MODE, C is
9297 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9298 that may be nonzero. */
9299 if (code == LSHIFTRT
9300 && XEXP (varop, 1) == const0_rtx
9301 && GET_MODE (XEXP (varop, 0)) == result_mode
9302 && count == GET_MODE_BITSIZE (result_mode) - 1
9303 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9304 && ((STORE_FLAG_VALUE
9305 & ((HOST_WIDE_INT) 1
9306 < (GET_MODE_BITSIZE (result_mode) - 1))))
9307 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9308 && merge_outer_ops (&outer_op, &outer_const, XOR,
9309 (HOST_WIDE_INT) 1, result_mode,
9312 varop = XEXP (varop, 0);
9319 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9320 than the number of bits in the mode is equivalent to A. */
9321 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9322 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9324 varop = XEXP (varop, 0);
9329 /* NEG commutes with ASHIFT since it is multiplication. Move the
9330 NEG outside to allow shifts to combine. */
9332 && merge_outer_ops (&outer_op, &outer_const, NEG,
9333 (HOST_WIDE_INT) 0, result_mode,
9336 varop = XEXP (varop, 0);
9342 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9343 is one less than the number of bits in the mode is
9344 equivalent to (xor A 1). */
9345 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9346 && XEXP (varop, 1) == constm1_rtx
9347 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9348 && merge_outer_ops (&outer_op, &outer_const, XOR,
9349 (HOST_WIDE_INT) 1, result_mode,
9353 varop = XEXP (varop, 0);
9357 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9358 that might be nonzero in BAR are those being shifted out and those
9359 bits are known zero in FOO, we can replace the PLUS with FOO.
9360 Similarly in the other operand order. This code occurs when
9361 we are computing the size of a variable-size array. */
9363 if ((code == ASHIFTRT || code == LSHIFTRT)
9364 && count < HOST_BITS_PER_WIDE_INT
9365 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9366 && (nonzero_bits (XEXP (varop, 1), result_mode)
9367 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9369 varop = XEXP (varop, 0);
9372 else if ((code == ASHIFTRT || code == LSHIFTRT)
9373 && count < HOST_BITS_PER_WIDE_INT
9374 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9375 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9377 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9378 & nonzero_bits (XEXP (varop, 1),
9381 varop = XEXP (varop, 1);
9385 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9387 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9388 && (new = simplify_binary_operation (ASHIFT, result_mode,
9390 GEN_INT (count))) != 0
9391 && GET_CODE (new) == CONST_INT
9392 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9393 INTVAL (new), result_mode, &complement_p))
9395 varop = XEXP (varop, 0);
9401 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9402 with C the size of VAROP - 1 and the shift is logical if
9403 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9404 we have a (gt X 0) operation. If the shift is arithmetic with
9405 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9406 we have a (neg (gt X 0)) operation. */
9408 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9409 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9410 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9411 && (code == LSHIFTRT || code == ASHIFTRT)
9412 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9413 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9414 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9417 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9420 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9421 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9428 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9429 if the truncate does not affect the value. */
9430 if (code == LSHIFTRT
9431 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9432 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9433 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9434 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9435 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9437 rtx varop_inner = XEXP (varop, 0);
9440 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9441 XEXP (varop_inner, 0),
9443 + INTVAL (XEXP (varop_inner, 1))));
9444 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9458 /* We need to determine what mode to do the shift in. If the shift is
9459 a right shift or ROTATE, we must always do it in the mode it was
9460 originally done in. Otherwise, we can do it in MODE, the widest mode
9461 encountered. The code we care about is that of the shift that will
9462 actually be done, not the shift that was originally requested. */
9464 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9465 ? result_mode : mode);
9467 /* We have now finished analyzing the shift. The result should be
9468 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9469 OUTER_OP is non-NIL, it is an operation that needs to be applied
9470 to the result of the shift. OUTER_CONST is the relevant constant,
9471 but we must turn off all bits turned off in the shift.
9473 If we were passed a value for X, see if we can use any pieces of
9474 it. If not, make new rtx. */
9476 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9477 && GET_CODE (XEXP (x, 1)) == CONST_INT
9478 && INTVAL (XEXP (x, 1)) == count)
9479 const_rtx = XEXP (x, 1);
9481 const_rtx = GEN_INT (count);
9483 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9484 && GET_MODE (XEXP (x, 0)) == shift_mode
9485 && SUBREG_REG (XEXP (x, 0)) == varop)
9486 varop = XEXP (x, 0);
9487 else if (GET_MODE (varop) != shift_mode)
9488 varop = gen_lowpart_for_combine (shift_mode, varop);
9490 /* If we can't make the SUBREG, try to return what we were given. */
9491 if (GET_CODE (varop) == CLOBBER)
9492 return x ? x : varop;
9494 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9499 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9500 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9502 SUBST (XEXP (x, 0), varop);
9503 SUBST (XEXP (x, 1), const_rtx);
9506 /* If we have an outer operation and we just made a shift, it is
9507 possible that we could have simplified the shift were it not
9508 for the outer operation. So try to do the simplification
9511 if (outer_op != NIL && GET_CODE (x) == code
9512 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9513 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9514 INTVAL (XEXP (x, 1)));
9516 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9517 turn off all the bits that the shift would have turned off. */
9518 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9519 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9520 GET_MODE_MASK (result_mode) >> orig_count);
9522 /* Do the remainder of the processing in RESULT_MODE. */
9523 x = gen_lowpart_for_combine (result_mode, x);
9525 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9528 x = gen_unary (NOT, result_mode, result_mode, x);
9530 if (outer_op != NIL)
9532 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9533 outer_const = trunc_int_for_mode (outer_const, result_mode);
9535 if (outer_op == AND)
9536 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9537 else if (outer_op == SET)
9538 /* This means that we have determined that the result is
9539 equivalent to a constant. This should be rare. */
9540 x = GEN_INT (outer_const);
9541 else if (GET_RTX_CLASS (outer_op) == '1')
9542 x = gen_unary (outer_op, result_mode, result_mode, x);
9544 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9550 /* Like recog, but we receive the address of a pointer to a new pattern.
9551 We try to match the rtx that the pointer points to.
9552 If that fails, we may try to modify or replace the pattern,
9553 storing the replacement into the same pointer object.
9555 Modifications include deletion or addition of CLOBBERs.
9557 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9558 the CLOBBERs are placed.
9560 The value is the final insn code from the pattern ultimately matched,
9564 recog_for_combine (pnewpat, insn, pnotes)
9569 register rtx pat = *pnewpat;
9570 int insn_code_number;
9571 int num_clobbers_to_add = 0;
9575 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9576 we use to indicate that something didn't match. If we find such a
9577 thing, force rejection. */
9578 if (GET_CODE (pat) == PARALLEL)
9579 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9580 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9581 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9584 /* Is the result of combination a valid instruction? */
9585 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9587 /* If it isn't, there is the possibility that we previously had an insn
9588 that clobbered some register as a side effect, but the combined
9589 insn doesn't need to do that. So try once more without the clobbers
9590 unless this represents an ASM insn. */
9592 if (insn_code_number < 0 && ! check_asm_operands (pat)
9593 && GET_CODE (pat) == PARALLEL)
9597 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9598 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9601 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9605 SUBST_INT (XVECLEN (pat, 0), pos);
9608 pat = XVECEXP (pat, 0, 0);
9610 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9613 /* If we had any clobbers to add, make a new pattern than contains
9614 them. Then check to make sure that all of them are dead. */
9615 if (num_clobbers_to_add)
9617 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9618 gen_rtvec (GET_CODE (pat) == PARALLEL
9620 + num_clobbers_to_add)
9621 : num_clobbers_to_add + 1));
9623 if (GET_CODE (pat) == PARALLEL)
9624 for (i = 0; i < XVECLEN (pat, 0); i++)
9625 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9627 XVECEXP (newpat, 0, 0) = pat;
9629 add_clobbers (newpat, insn_code_number);
9631 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9632 i < XVECLEN (newpat, 0); i++)
9634 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9635 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9637 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9638 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9646 return insn_code_number;
9649 /* Like gen_lowpart but for use by combine. In combine it is not possible
9650 to create any new pseudoregs. However, it is safe to create
9651 invalid memory addresses, because combine will try to recognize
9652 them and all they will do is make the combine attempt fail.
9654 If for some reason this cannot do its job, an rtx
9655 (clobber (const_int 0)) is returned.
9656 An insn containing that will not be recognized. */
9661 gen_lowpart_for_combine (mode, x)
9662 enum machine_mode mode;
9667 if (GET_MODE (x) == mode)
9670 /* We can only support MODE being wider than a word if X is a
9671 constant integer or has a mode the same size. */
9673 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9674 && ! ((GET_MODE (x) == VOIDmode
9675 && (GET_CODE (x) == CONST_INT
9676 || GET_CODE (x) == CONST_DOUBLE))
9677 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9678 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9680 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9681 won't know what to do. So we will strip off the SUBREG here and
9682 process normally. */
9683 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9686 if (GET_MODE (x) == mode)
9690 result = gen_lowpart_common (mode, x);
9691 #ifdef CLASS_CANNOT_CHANGE_MODE
9693 && GET_CODE (result) == SUBREG
9694 && GET_CODE (SUBREG_REG (result)) == REG
9695 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9696 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9697 GET_MODE (SUBREG_REG (result))))
9698 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9704 if (GET_CODE (x) == MEM)
9706 register int offset = 0;
9709 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9711 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9712 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9714 /* If we want to refer to something bigger than the original memref,
9715 generate a perverse subreg instead. That will force a reload
9716 of the original memref X. */
9717 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9718 return gen_rtx_SUBREG (mode, x, 0);
9720 if (WORDS_BIG_ENDIAN)
9721 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9722 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9724 if (BYTES_BIG_ENDIAN)
9726 /* Adjust the address so that the address-after-the-data is
9728 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9729 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9731 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9732 MEM_COPY_ATTRIBUTES (new, x);
9736 /* If X is a comparison operator, rewrite it in a new mode. This
9737 probably won't match, but may allow further simplifications. */
9738 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9739 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9741 /* If we couldn't simplify X any other way, just enclose it in a
9742 SUBREG. Normally, this SUBREG won't match, but some patterns may
9743 include an explicit SUBREG or we may simplify it further in combine. */
9748 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9749 word = ((GET_MODE_SIZE (GET_MODE (x))
9750 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9752 return gen_rtx_SUBREG (mode, x, word);
9756 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9757 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9759 If the identical expression was previously in the insn (in the undobuf),
9760 it will be returned. Only if it is not found will a new expression
9765 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9767 #ifndef ANSI_PROTOTYPES
9769 enum machine_mode mode;
9781 #ifndef ANSI_PROTOTYPES
9782 code = va_arg (p, enum rtx_code);
9783 mode = va_arg (p, enum machine_mode);
9786 n_args = GET_RTX_LENGTH (code);
9787 fmt = GET_RTX_FORMAT (code);
9789 if (n_args == 0 || n_args > 3)
9792 /* Get each arg and verify that it is supposed to be an expression. */
9793 for (j = 0; j < n_args; j++)
9798 args[j] = va_arg (p, rtx);
9803 /* See if this is in undobuf. Be sure we don't use objects that came
9804 from another insn; this could produce circular rtl structures. */
9806 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9808 && GET_CODE (undo->old_contents.r) == code
9809 && GET_MODE (undo->old_contents.r) == mode)
9811 for (j = 0; j < n_args; j++)
9812 if (XEXP (undo->old_contents.r, j) != args[j])
9816 return undo->old_contents.r;
9819 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9820 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9821 rt = rtx_alloc (code);
9822 PUT_MODE (rt, mode);
9823 XEXP (rt, 0) = args[0];
9826 XEXP (rt, 1) = args[1];
9828 XEXP (rt, 2) = args[2];
9833 /* These routines make binary and unary operations by first seeing if they
9834 fold; if not, a new expression is allocated. */
9837 gen_binary (code, mode, op0, op1)
9839 enum machine_mode mode;
9845 if (GET_RTX_CLASS (code) == 'c'
9846 && (GET_CODE (op0) == CONST_INT
9847 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9848 tem = op0, op0 = op1, op1 = tem;
9850 if (GET_RTX_CLASS (code) == '<')
9852 enum machine_mode op_mode = GET_MODE (op0);
9854 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9855 just (REL_OP X Y). */
9856 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9858 op1 = XEXP (op0, 1);
9859 op0 = XEXP (op0, 0);
9860 op_mode = GET_MODE (op0);
9863 if (op_mode == VOIDmode)
9864 op_mode = GET_MODE (op1);
9865 result = simplify_relational_operation (code, op_mode, op0, op1);
9868 result = simplify_binary_operation (code, mode, op0, op1);
9873 /* Put complex operands first and constants second. */
9874 if (GET_RTX_CLASS (code) == 'c'
9875 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9876 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9877 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9878 || (GET_CODE (op0) == SUBREG
9879 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9880 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9881 return gen_rtx_combine (code, mode, op1, op0);
9883 /* If we are turning off bits already known off in OP0, we need not do
9885 else if (code == AND && GET_CODE (op1) == CONST_INT
9886 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9887 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9890 return gen_rtx_combine (code, mode, op0, op1);
9894 gen_unary (code, mode, op0_mode, op0)
9896 enum machine_mode mode, op0_mode;
9899 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9904 return gen_rtx_combine (code, mode, op0);
9907 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9908 comparison code that will be tested.
9910 The result is a possibly different comparison code to use. *POP0 and
9911 *POP1 may be updated.
9913 It is possible that we might detect that a comparison is either always
9914 true or always false. However, we do not perform general constant
9915 folding in combine, so this knowledge isn't useful. Such tautologies
9916 should have been detected earlier. Hence we ignore all such cases. */
9918 static enum rtx_code
9919 simplify_comparison (code, pop0, pop1)
9928 enum machine_mode mode, tmode;
9930 /* Try a few ways of applying the same transformation to both operands. */
9933 #ifndef WORD_REGISTER_OPERATIONS
9934 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9935 so check specially. */
9936 if (code != GTU && code != GEU && code != LTU && code != LEU
9937 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9938 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9939 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9940 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9941 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9942 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9943 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9944 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9945 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9946 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9947 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9948 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9949 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9950 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9951 && (INTVAL (XEXP (op0, 1))
9952 == (GET_MODE_BITSIZE (GET_MODE (op0))
9954 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9956 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9957 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9961 /* If both operands are the same constant shift, see if we can ignore the
9962 shift. We can if the shift is a rotate or if the bits shifted out of
9963 this shift are known to be zero for both inputs and if the type of
9964 comparison is compatible with the shift. */
9965 if (GET_CODE (op0) == GET_CODE (op1)
9966 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9967 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9968 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9969 && (code != GT && code != LT && code != GE && code != LE))
9970 || (GET_CODE (op0) == ASHIFTRT
9971 && (code != GTU && code != LTU
9972 && code != GEU && code != GEU)))
9973 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9974 && INTVAL (XEXP (op0, 1)) >= 0
9975 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9976 && XEXP (op0, 1) == XEXP (op1, 1))
9978 enum machine_mode mode = GET_MODE (op0);
9979 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9980 int shift_count = INTVAL (XEXP (op0, 1));
9982 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9983 mask &= (mask >> shift_count) << shift_count;
9984 else if (GET_CODE (op0) == ASHIFT)
9985 mask = (mask & (mask << shift_count)) >> shift_count;
9987 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9988 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9989 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9994 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9995 SUBREGs are of the same mode, and, in both cases, the AND would
9996 be redundant if the comparison was done in the narrower mode,
9997 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9998 and the operand's possibly nonzero bits are 0xffffff01; in that case
9999 if we only care about QImode, we don't need the AND). This case
10000 occurs if the output mode of an scc insn is not SImode and
10001 STORE_FLAG_VALUE == 1 (e.g., the 386).
10003 Similarly, check for a case where the AND's are ZERO_EXTEND
10004 operations from some narrower mode even though a SUBREG is not
10007 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10008 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10009 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10011 rtx inner_op0 = XEXP (op0, 0);
10012 rtx inner_op1 = XEXP (op1, 0);
10013 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10014 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10017 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10018 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10020 && (GET_MODE (SUBREG_REG (inner_op0))
10021 == GET_MODE (SUBREG_REG (inner_op1)))
10022 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10023 <= HOST_BITS_PER_WIDE_INT)
10024 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10025 GET_MODE (SUBREG_REG (inner_op0)))))
10026 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10027 GET_MODE (SUBREG_REG (inner_op1))))))
10029 op0 = SUBREG_REG (inner_op0);
10030 op1 = SUBREG_REG (inner_op1);
10032 /* The resulting comparison is always unsigned since we masked
10033 off the original sign bit. */
10034 code = unsigned_condition (code);
10040 for (tmode = GET_CLASS_NARROWEST_MODE
10041 (GET_MODE_CLASS (GET_MODE (op0)));
10042 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10043 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10045 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10046 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10047 code = unsigned_condition (code);
10056 /* If both operands are NOT, we can strip off the outer operation
10057 and adjust the comparison code for swapped operands; similarly for
10058 NEG, except that this must be an equality comparison. */
10059 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10060 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10061 && (code == EQ || code == NE)))
10062 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10068 /* If the first operand is a constant, swap the operands and adjust the
10069 comparison code appropriately, but don't do this if the second operand
10070 is already a constant integer. */
10071 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10073 tem = op0, op0 = op1, op1 = tem;
10074 code = swap_condition (code);
10077 /* We now enter a loop during which we will try to simplify the comparison.
10078 For the most part, we only are concerned with comparisons with zero,
10079 but some things may really be comparisons with zero but not start
10080 out looking that way. */
10082 while (GET_CODE (op1) == CONST_INT)
10084 enum machine_mode mode = GET_MODE (op0);
10085 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10086 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10087 int equality_comparison_p;
10088 int sign_bit_comparison_p;
10089 int unsigned_comparison_p;
10090 HOST_WIDE_INT const_op;
10092 /* We only want to handle integral modes. This catches VOIDmode,
10093 CCmode, and the floating-point modes. An exception is that we
10094 can handle VOIDmode if OP0 is a COMPARE or a comparison
10097 if (GET_MODE_CLASS (mode) != MODE_INT
10098 && ! (mode == VOIDmode
10099 && (GET_CODE (op0) == COMPARE
10100 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10103 /* Get the constant we are comparing against and turn off all bits
10104 not on in our mode. */
10105 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10107 /* If we are comparing against a constant power of two and the value
10108 being compared can only have that single bit nonzero (e.g., it was
10109 `and'ed with that bit), we can replace this with a comparison
10112 && (code == EQ || code == NE || code == GE || code == GEU
10113 || code == LT || code == LTU)
10114 && mode_width <= HOST_BITS_PER_WIDE_INT
10115 && exact_log2 (const_op) >= 0
10116 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10118 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10119 op1 = const0_rtx, const_op = 0;
10122 /* Similarly, if we are comparing a value known to be either -1 or
10123 0 with -1, change it to the opposite comparison against zero. */
10126 && (code == EQ || code == NE || code == GT || code == LE
10127 || code == GEU || code == LTU)
10128 && num_sign_bit_copies (op0, mode) == mode_width)
10130 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10131 op1 = const0_rtx, const_op = 0;
10134 /* Do some canonicalizations based on the comparison code. We prefer
10135 comparisons against zero and then prefer equality comparisons.
10136 If we can reduce the size of a constant, we will do that too. */
10141 /* < C is equivalent to <= (C - 1) */
10145 op1 = GEN_INT (const_op);
10147 /* ... fall through to LE case below. */
10153 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10157 op1 = GEN_INT (const_op);
10161 /* If we are doing a <= 0 comparison on a value known to have
10162 a zero sign bit, we can replace this with == 0. */
10163 else if (const_op == 0
10164 && mode_width <= HOST_BITS_PER_WIDE_INT
10165 && (nonzero_bits (op0, mode)
10166 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10171 /* >= C is equivalent to > (C - 1). */
10175 op1 = GEN_INT (const_op);
10177 /* ... fall through to GT below. */
10183 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10187 op1 = GEN_INT (const_op);
10191 /* If we are doing a > 0 comparison on a value known to have
10192 a zero sign bit, we can replace this with != 0. */
10193 else if (const_op == 0
10194 && mode_width <= HOST_BITS_PER_WIDE_INT
10195 && (nonzero_bits (op0, mode)
10196 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10201 /* < C is equivalent to <= (C - 1). */
10205 op1 = GEN_INT (const_op);
10207 /* ... fall through ... */
10210 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10211 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10212 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10214 const_op = 0, op1 = const0_rtx;
10222 /* unsigned <= 0 is equivalent to == 0 */
10226 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10227 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10228 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10230 const_op = 0, op1 = const0_rtx;
10236 /* >= C is equivalent to < (C - 1). */
10240 op1 = GEN_INT (const_op);
10242 /* ... fall through ... */
10245 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10246 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10247 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10249 const_op = 0, op1 = const0_rtx;
10257 /* unsigned > 0 is equivalent to != 0 */
10261 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10262 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10263 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10265 const_op = 0, op1 = const0_rtx;
10274 /* Compute some predicates to simplify code below. */
10276 equality_comparison_p = (code == EQ || code == NE);
10277 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10278 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10281 /* If this is a sign bit comparison and we can do arithmetic in
10282 MODE, say that we will only be needing the sign bit of OP0. */
10283 if (sign_bit_comparison_p
10284 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10285 op0 = force_to_mode (op0, mode,
10287 << (GET_MODE_BITSIZE (mode) - 1)),
10290 /* Now try cases based on the opcode of OP0. If none of the cases
10291 does a "continue", we exit this loop immediately after the
10294 switch (GET_CODE (op0))
10297 /* If we are extracting a single bit from a variable position in
10298 a constant that has only a single bit set and are comparing it
10299 with zero, we can convert this into an equality comparison
10300 between the position and the location of the single bit. */
10302 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10303 && XEXP (op0, 1) == const1_rtx
10304 && equality_comparison_p && const_op == 0
10305 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10307 if (BITS_BIG_ENDIAN)
10310 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10311 if (mode == VOIDmode)
10313 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10315 i = BITS_PER_WORD - 1 - i;
10319 op0 = XEXP (op0, 2);
10323 /* Result is nonzero iff shift count is equal to I. */
10324 code = reverse_condition (code);
10328 /* ... fall through ... */
10331 tem = expand_compound_operation (op0);
10340 /* If testing for equality, we can take the NOT of the constant. */
10341 if (equality_comparison_p
10342 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10344 op0 = XEXP (op0, 0);
10349 /* If just looking at the sign bit, reverse the sense of the
10351 if (sign_bit_comparison_p)
10353 op0 = XEXP (op0, 0);
10354 code = (code == GE ? LT : GE);
10360 /* If testing for equality, we can take the NEG of the constant. */
10361 if (equality_comparison_p
10362 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10364 op0 = XEXP (op0, 0);
10369 /* The remaining cases only apply to comparisons with zero. */
10373 /* When X is ABS or is known positive,
10374 (neg X) is < 0 if and only if X != 0. */
10376 if (sign_bit_comparison_p
10377 && (GET_CODE (XEXP (op0, 0)) == ABS
10378 || (mode_width <= HOST_BITS_PER_WIDE_INT
10379 && (nonzero_bits (XEXP (op0, 0), mode)
10380 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10382 op0 = XEXP (op0, 0);
10383 code = (code == LT ? NE : EQ);
10387 /* If we have NEG of something whose two high-order bits are the
10388 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10389 if (num_sign_bit_copies (op0, mode) >= 2)
10391 op0 = XEXP (op0, 0);
10392 code = swap_condition (code);
10398 /* If we are testing equality and our count is a constant, we
10399 can perform the inverse operation on our RHS. */
10400 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10401 && (tem = simplify_binary_operation (ROTATERT, mode,
10402 op1, XEXP (op0, 1))) != 0)
10404 op0 = XEXP (op0, 0);
10409 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10410 a particular bit. Convert it to an AND of a constant of that
10411 bit. This will be converted into a ZERO_EXTRACT. */
10412 if (const_op == 0 && sign_bit_comparison_p
10413 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10414 && mode_width <= HOST_BITS_PER_WIDE_INT)
10416 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10419 - INTVAL (XEXP (op0, 1)))));
10420 code = (code == LT ? NE : EQ);
10424 /* ... fall through ... */
10427 /* ABS is ignorable inside an equality comparison with zero. */
10428 if (const_op == 0 && equality_comparison_p)
10430 op0 = XEXP (op0, 0);
10437 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10438 to (compare FOO CONST) if CONST fits in FOO's mode and we
10439 are either testing inequality or have an unsigned comparison
10440 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10441 if (! unsigned_comparison_p
10442 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10443 <= HOST_BITS_PER_WIDE_INT)
10444 && ((unsigned HOST_WIDE_INT) const_op
10445 < (((unsigned HOST_WIDE_INT) 1
10446 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10448 op0 = XEXP (op0, 0);
10454 /* Check for the case where we are comparing A - C1 with C2,
10455 both constants are smaller than 1/2 the maximum positive
10456 value in MODE, and the comparison is equality or unsigned.
10457 In that case, if A is either zero-extended to MODE or has
10458 sufficient sign bits so that the high-order bit in MODE
10459 is a copy of the sign in the inner mode, we can prove that it is
10460 safe to do the operation in the wider mode. This simplifies
10461 many range checks. */
10463 if (mode_width <= HOST_BITS_PER_WIDE_INT
10464 && subreg_lowpart_p (op0)
10465 && GET_CODE (SUBREG_REG (op0)) == PLUS
10466 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10467 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10468 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10469 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10470 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10471 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10472 GET_MODE (SUBREG_REG (op0)))
10473 & ~ GET_MODE_MASK (mode))
10474 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10475 GET_MODE (SUBREG_REG (op0)))
10476 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10477 - GET_MODE_BITSIZE (mode)))))
10479 op0 = SUBREG_REG (op0);
10483 /* If the inner mode is narrower and we are extracting the low part,
10484 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10485 if (subreg_lowpart_p (op0)
10486 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10487 /* Fall through */ ;
10491 /* ... fall through ... */
10494 if ((unsigned_comparison_p || equality_comparison_p)
10495 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10496 <= HOST_BITS_PER_WIDE_INT)
10497 && ((unsigned HOST_WIDE_INT) const_op
10498 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10500 op0 = XEXP (op0, 0);
10506 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10507 this for equality comparisons due to pathological cases involving
10509 if (equality_comparison_p
10510 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10511 op1, XEXP (op0, 1))))
10513 op0 = XEXP (op0, 0);
10518 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10519 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10520 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10522 op0 = XEXP (XEXP (op0, 0), 0);
10523 code = (code == LT ? EQ : NE);
10529 /* We used to optimize signed comparisons against zero, but that
10530 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10531 arrive here as equality comparisons, or (GEU, LTU) are
10532 optimized away. No need to special-case them. */
10534 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10535 (eq B (minus A C)), whichever simplifies. We can only do
10536 this for equality comparisons due to pathological cases involving
10538 if (equality_comparison_p
10539 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10540 XEXP (op0, 1), op1)))
10542 op0 = XEXP (op0, 0);
10547 if (equality_comparison_p
10548 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10549 XEXP (op0, 0), op1)))
10551 op0 = XEXP (op0, 1);
10556 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10557 of bits in X minus 1, is one iff X > 0. */
10558 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10559 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10560 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10561 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10563 op0 = XEXP (op0, 1);
10564 code = (code == GE ? LE : GT);
10570 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10571 if C is zero or B is a constant. */
10572 if (equality_comparison_p
10573 && 0 != (tem = simplify_binary_operation (XOR, mode,
10574 XEXP (op0, 1), op1)))
10576 op0 = XEXP (op0, 0);
10583 case LT: case LTU: case LE: case LEU:
10584 case GT: case GTU: case GE: case GEU:
10585 /* We can't do anything if OP0 is a condition code value, rather
10586 than an actual data value. */
10589 || XEXP (op0, 0) == cc0_rtx
10591 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10594 /* Get the two operands being compared. */
10595 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10596 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10598 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10600 /* Check for the cases where we simply want the result of the
10601 earlier test or the opposite of that result. */
10603 || (code == EQ && reversible_comparison_p (op0))
10604 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10605 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10606 && (STORE_FLAG_VALUE
10607 & (((HOST_WIDE_INT) 1
10608 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10610 || (code == GE && reversible_comparison_p (op0)))))
10612 code = (code == LT || code == NE
10613 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10614 op0 = tem, op1 = tem1;
10620 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10622 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10623 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10624 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10626 op0 = XEXP (op0, 1);
10627 code = (code == GE ? GT : LE);
10633 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10634 will be converted to a ZERO_EXTRACT later. */
10635 if (const_op == 0 && equality_comparison_p
10636 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10637 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10639 op0 = simplify_and_const_int
10640 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10642 XEXP (XEXP (op0, 0), 1)),
10643 (HOST_WIDE_INT) 1);
10647 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10648 zero and X is a comparison and C1 and C2 describe only bits set
10649 in STORE_FLAG_VALUE, we can compare with X. */
10650 if (const_op == 0 && equality_comparison_p
10651 && mode_width <= HOST_BITS_PER_WIDE_INT
10652 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10653 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10654 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10655 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10656 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10658 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10659 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10660 if ((~ STORE_FLAG_VALUE & mask) == 0
10661 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10662 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10663 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10665 op0 = XEXP (XEXP (op0, 0), 0);
10670 /* If we are doing an equality comparison of an AND of a bit equal
10671 to the sign bit, replace this with a LT or GE comparison of
10672 the underlying value. */
10673 if (equality_comparison_p
10675 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10676 && mode_width <= HOST_BITS_PER_WIDE_INT
10677 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10678 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10680 op0 = XEXP (op0, 0);
10681 code = (code == EQ ? GE : LT);
10685 /* If this AND operation is really a ZERO_EXTEND from a narrower
10686 mode, the constant fits within that mode, and this is either an
10687 equality or unsigned comparison, try to do this comparison in
10688 the narrower mode. */
10689 if ((equality_comparison_p || unsigned_comparison_p)
10690 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10691 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10692 & GET_MODE_MASK (mode))
10694 && const_op >> i == 0
10695 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10697 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10701 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10702 in both M1 and M2 and the SUBREG is either paradoxical or
10703 represents the low part, permute the SUBREG and the AND and
10705 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10707 #ifdef WORD_REGISTER_OPERATIONS
10709 > (GET_MODE_BITSIZE
10710 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10711 && mode_width <= BITS_PER_WORD)
10714 <= (GET_MODE_BITSIZE
10715 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10716 && subreg_lowpart_p (XEXP (op0, 0))))
10717 #ifndef WORD_REGISTER_OPERATIONS
10718 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10719 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10720 As originally written the upper bits have a defined value
10721 due to the AND operation. However, if we commute the AND
10722 inside the SUBREG then they no longer have defined values
10723 and the meaning of the code has been changed. */
10724 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10725 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10727 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10728 && mode_width <= HOST_BITS_PER_WIDE_INT
10729 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10730 <= HOST_BITS_PER_WIDE_INT)
10731 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10732 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10733 & INTVAL (XEXP (op0, 1)))
10734 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10735 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10736 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10740 = gen_lowpart_for_combine
10742 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10743 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10750 /* If we have (compare (ashift FOO N) (const_int C)) and
10751 the high order N bits of FOO (N+1 if an inequality comparison)
10752 are known to be zero, we can do this by comparing FOO with C
10753 shifted right N bits so long as the low-order N bits of C are
10755 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10756 && INTVAL (XEXP (op0, 1)) >= 0
10757 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10758 < HOST_BITS_PER_WIDE_INT)
10760 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10761 && mode_width <= HOST_BITS_PER_WIDE_INT
10762 && (nonzero_bits (XEXP (op0, 0), mode)
10763 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10764 + ! equality_comparison_p))) == 0)
10766 /* We must perform a logical shift, not an arithmetic one,
10767 as we want the top N bits of C to be zero. */
10768 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10770 temp >>= INTVAL (XEXP (op0, 1));
10771 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10772 op0 = XEXP (op0, 0);
10776 /* If we are doing a sign bit comparison, it means we are testing
10777 a particular bit. Convert it to the appropriate AND. */
10778 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10779 && mode_width <= HOST_BITS_PER_WIDE_INT)
10781 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10784 - INTVAL (XEXP (op0, 1)))));
10785 code = (code == LT ? NE : EQ);
10789 /* If this an equality comparison with zero and we are shifting
10790 the low bit to the sign bit, we can convert this to an AND of the
10792 if (const_op == 0 && equality_comparison_p
10793 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10794 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10796 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10797 (HOST_WIDE_INT) 1);
10803 /* If this is an equality comparison with zero, we can do this
10804 as a logical shift, which might be much simpler. */
10805 if (equality_comparison_p && const_op == 0
10806 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10808 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10810 INTVAL (XEXP (op0, 1)));
10814 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10815 do the comparison in a narrower mode. */
10816 if (! unsigned_comparison_p
10817 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10818 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10819 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10820 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10821 MODE_INT, 1)) != BLKmode
10822 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10823 || ((unsigned HOST_WIDE_INT) - const_op
10824 <= GET_MODE_MASK (tmode))))
10826 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10830 /* Likewise if OP0 is a PLUS of a sign extension with a
10831 constant, which is usually represented with the PLUS
10832 between the shifts. */
10833 if (! unsigned_comparison_p
10834 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10835 && GET_CODE (XEXP (op0, 0)) == PLUS
10836 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10837 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10838 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10839 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10840 MODE_INT, 1)) != BLKmode
10841 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10842 || ((unsigned HOST_WIDE_INT) - const_op
10843 <= GET_MODE_MASK (tmode))))
10845 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10846 rtx add_const = XEXP (XEXP (op0, 0), 1);
10847 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10850 op0 = gen_binary (PLUS, tmode,
10851 gen_lowpart_for_combine (tmode, inner),
10856 /* ... fall through ... */
10858 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10859 the low order N bits of FOO are known to be zero, we can do this
10860 by comparing FOO with C shifted left N bits so long as no
10861 overflow occurs. */
10862 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10863 && INTVAL (XEXP (op0, 1)) >= 0
10864 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10865 && mode_width <= HOST_BITS_PER_WIDE_INT
10866 && (nonzero_bits (XEXP (op0, 0), mode)
10867 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10869 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10872 const_op <<= INTVAL (XEXP (op0, 1));
10873 op1 = GEN_INT (const_op);
10874 op0 = XEXP (op0, 0);
10878 /* If we are using this shift to extract just the sign bit, we
10879 can replace this with an LT or GE comparison. */
10881 && (equality_comparison_p || sign_bit_comparison_p)
10882 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10883 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10885 op0 = XEXP (op0, 0);
10886 code = (code == NE || code == GT ? LT : GE);
10898 /* Now make any compound operations involved in this comparison. Then,
10899 check for an outmost SUBREG on OP0 that is not doing anything or is
10900 paradoxical. The latter case can only occur when it is known that the
10901 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10902 We can never remove a SUBREG for a non-equality comparison because the
10903 sign bit is in a different place in the underlying object. */
10905 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10906 op1 = make_compound_operation (op1, SET);
10908 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10909 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10910 && (code == NE || code == EQ)
10911 && ((GET_MODE_SIZE (GET_MODE (op0))
10912 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10914 op0 = SUBREG_REG (op0);
10915 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10918 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10919 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10920 && (code == NE || code == EQ)
10921 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10922 <= HOST_BITS_PER_WIDE_INT)
10923 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10924 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10925 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10927 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10928 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10929 op0 = SUBREG_REG (op0), op1 = tem;
10931 /* We now do the opposite procedure: Some machines don't have compare
10932 insns in all modes. If OP0's mode is an integer mode smaller than a
10933 word and we can't do a compare in that mode, see if there is a larger
10934 mode for which we can do the compare. There are a number of cases in
10935 which we can use the wider mode. */
10937 mode = GET_MODE (op0);
10938 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10939 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10940 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10941 for (tmode = GET_MODE_WIDER_MODE (mode);
10943 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10944 tmode = GET_MODE_WIDER_MODE (tmode))
10945 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10947 /* If the only nonzero bits in OP0 and OP1 are those in the
10948 narrower mode and this is an equality or unsigned comparison,
10949 we can use the wider mode. Similarly for sign-extended
10950 values, in which case it is true for all comparisons. */
10951 if (((code == EQ || code == NE
10952 || code == GEU || code == GTU || code == LEU || code == LTU)
10953 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10954 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10955 || ((num_sign_bit_copies (op0, tmode)
10956 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10957 && (num_sign_bit_copies (op1, tmode)
10958 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10960 /* If OP0 is an AND and we don't have an AND in MODE either,
10961 make a new AND in the proper mode. */
10962 if (GET_CODE (op0) == AND
10963 && (add_optab->handlers[(int) mode].insn_code
10964 == CODE_FOR_nothing))
10965 op0 = gen_binary (AND, tmode,
10966 gen_lowpart_for_combine (tmode,
10968 gen_lowpart_for_combine (tmode,
10971 op0 = gen_lowpart_for_combine (tmode, op0);
10972 op1 = gen_lowpart_for_combine (tmode, op1);
10976 /* If this is a test for negative, we can make an explicit
10977 test of the sign bit. */
10979 if (op1 == const0_rtx && (code == LT || code == GE)
10980 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10982 op0 = gen_binary (AND, tmode,
10983 gen_lowpart_for_combine (tmode, op0),
10984 GEN_INT ((HOST_WIDE_INT) 1
10985 << (GET_MODE_BITSIZE (mode) - 1)));
10986 code = (code == LT) ? NE : EQ;
10991 #ifdef CANONICALIZE_COMPARISON
10992 /* If this machine only supports a subset of valid comparisons, see if we
10993 can convert an unsupported one into a supported one. */
10994 CANONICALIZE_COMPARISON (code, op0, op1);
11003 /* Return 1 if we know that X, a comparison operation, is not operating
11004 on a floating-point value or is EQ or NE, meaning that we can safely
11008 reversible_comparison_p (x)
11011 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
11013 || GET_CODE (x) == NE || GET_CODE (x) == EQ
11014 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
11017 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
11020 case MODE_PARTIAL_INT:
11021 case MODE_COMPLEX_INT:
11025 /* If the mode of the condition codes tells us that this is safe,
11026 we need look no further. */
11027 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
11030 /* Otherwise try and find where the condition codes were last set and
11032 x = get_last_value (XEXP (x, 0));
11033 return (x && GET_CODE (x) == COMPARE
11034 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
11041 /* Utility function for following routine. Called when X is part of a value
11042 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11043 for each register mentioned. Similar to mention_regs in cse.c */
11046 update_table_tick (x)
11049 register enum rtx_code code = GET_CODE (x);
11050 register const char *fmt = GET_RTX_FORMAT (code);
11055 unsigned int regno = REGNO (x);
11056 unsigned int endregno
11057 = regno + (regno < FIRST_PSEUDO_REGISTER
11058 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11061 for (r = regno; r < endregno; r++)
11062 reg_last_set_table_tick[r] = label_tick;
11067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11068 /* Note that we can't have an "E" in values stored; see
11069 get_last_value_validate. */
11071 update_table_tick (XEXP (x, i));
11074 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11075 are saying that the register is clobbered and we no longer know its
11076 value. If INSN is zero, don't update reg_last_set; this is only permitted
11077 with VALUE also zero and is used to invalidate the register. */
11080 record_value_for_reg (reg, insn, value)
11085 unsigned int regno = REGNO (reg);
11086 unsigned int endregno
11087 = regno + (regno < FIRST_PSEUDO_REGISTER
11088 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11091 /* If VALUE contains REG and we have a previous value for REG, substitute
11092 the previous value. */
11093 if (value && insn && reg_overlap_mentioned_p (reg, value))
11097 /* Set things up so get_last_value is allowed to see anything set up to
11099 subst_low_cuid = INSN_CUID (insn);
11100 tem = get_last_value (reg);
11102 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11103 it isn't going to be useful and will take a lot of time to process,
11104 so just use the CLOBBER. */
11108 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11109 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11110 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11111 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11112 tem = XEXP (tem, 0);
11114 value = replace_rtx (copy_rtx (value), reg, tem);
11118 /* For each register modified, show we don't know its value, that
11119 we don't know about its bitwise content, that its value has been
11120 updated, and that we don't know the location of the death of the
11122 for (i = regno; i < endregno; i++)
11125 reg_last_set[i] = insn;
11127 reg_last_set_value[i] = 0;
11128 reg_last_set_mode[i] = 0;
11129 reg_last_set_nonzero_bits[i] = 0;
11130 reg_last_set_sign_bit_copies[i] = 0;
11131 reg_last_death[i] = 0;
11134 /* Mark registers that are being referenced in this value. */
11136 update_table_tick (value);
11138 /* Now update the status of each register being set.
11139 If someone is using this register in this block, set this register
11140 to invalid since we will get confused between the two lives in this
11141 basic block. This makes using this register always invalid. In cse, we
11142 scan the table to invalidate all entries using this register, but this
11143 is too much work for us. */
11145 for (i = regno; i < endregno; i++)
11147 reg_last_set_label[i] = label_tick;
11148 if (value && reg_last_set_table_tick[i] == label_tick)
11149 reg_last_set_invalid[i] = 1;
11151 reg_last_set_invalid[i] = 0;
11154 /* The value being assigned might refer to X (like in "x++;"). In that
11155 case, we must replace it with (clobber (const_int 0)) to prevent
11157 if (value && ! get_last_value_validate (&value, insn,
11158 reg_last_set_label[regno], 0))
11160 value = copy_rtx (value);
11161 if (! get_last_value_validate (&value, insn,
11162 reg_last_set_label[regno], 1))
11166 /* For the main register being modified, update the value, the mode, the
11167 nonzero bits, and the number of sign bit copies. */
11169 reg_last_set_value[regno] = value;
11173 subst_low_cuid = INSN_CUID (insn);
11174 reg_last_set_mode[regno] = GET_MODE (reg);
11175 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11176 reg_last_set_sign_bit_copies[regno]
11177 = num_sign_bit_copies (value, GET_MODE (reg));
11181 /* Called via note_stores from record_dead_and_set_regs to handle one
11182 SET or CLOBBER in an insn. DATA is the instruction in which the
11183 set is occurring. */
11186 record_dead_and_set_regs_1 (dest, setter, data)
11190 rtx record_dead_insn = (rtx) data;
11192 if (GET_CODE (dest) == SUBREG)
11193 dest = SUBREG_REG (dest);
11195 if (GET_CODE (dest) == REG)
11197 /* If we are setting the whole register, we know its value. Otherwise
11198 show that we don't know the value. We can handle SUBREG in
11200 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11201 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11202 else if (GET_CODE (setter) == SET
11203 && GET_CODE (SET_DEST (setter)) == SUBREG
11204 && SUBREG_REG (SET_DEST (setter)) == dest
11205 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11206 && subreg_lowpart_p (SET_DEST (setter)))
11207 record_value_for_reg (dest, record_dead_insn,
11208 gen_lowpart_for_combine (GET_MODE (dest),
11209 SET_SRC (setter)));
11211 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11213 else if (GET_CODE (dest) == MEM
11214 /* Ignore pushes, they clobber nothing. */
11215 && ! push_operand (dest, GET_MODE (dest)))
11216 mem_last_set = INSN_CUID (record_dead_insn);
11219 /* Update the records of when each REG was most recently set or killed
11220 for the things done by INSN. This is the last thing done in processing
11221 INSN in the combiner loop.
11223 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11224 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11225 and also the similar information mem_last_set (which insn most recently
11226 modified memory) and last_call_cuid (which insn was the most recent
11227 subroutine call). */
11230 record_dead_and_set_regs (insn)
11236 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11238 if (REG_NOTE_KIND (link) == REG_DEAD
11239 && GET_CODE (XEXP (link, 0)) == REG)
11241 unsigned int regno = REGNO (XEXP (link, 0));
11242 unsigned int endregno
11243 = regno + (regno < FIRST_PSEUDO_REGISTER
11244 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11247 for (i = regno; i < endregno; i++)
11248 reg_last_death[i] = insn;
11250 else if (REG_NOTE_KIND (link) == REG_INC)
11251 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11254 if (GET_CODE (insn) == CALL_INSN)
11256 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11257 if (call_used_regs[i])
11259 reg_last_set_value[i] = 0;
11260 reg_last_set_mode[i] = 0;
11261 reg_last_set_nonzero_bits[i] = 0;
11262 reg_last_set_sign_bit_copies[i] = 0;
11263 reg_last_death[i] = 0;
11266 last_call_cuid = mem_last_set = INSN_CUID (insn);
11269 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11272 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11273 register present in the SUBREG, so for each such SUBREG go back and
11274 adjust nonzero and sign bit information of the registers that are
11275 known to have some zero/sign bits set.
11277 This is needed because when combine blows the SUBREGs away, the
11278 information on zero/sign bits is lost and further combines can be
11279 missed because of that. */
11282 record_promoted_value (insn, subreg)
11287 unsigned int regno = REGNO (SUBREG_REG (subreg));
11288 enum machine_mode mode = GET_MODE (subreg);
11290 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11293 for (links = LOG_LINKS (insn); links; )
11295 insn = XEXP (links, 0);
11296 set = single_set (insn);
11298 if (! set || GET_CODE (SET_DEST (set)) != REG
11299 || REGNO (SET_DEST (set)) != regno
11300 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11302 links = XEXP (links, 1);
11306 if (reg_last_set [regno] == insn)
11308 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11309 reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11312 if (GET_CODE (SET_SRC (set)) == REG)
11314 regno = REGNO (SET_SRC (set));
11315 links = LOG_LINKS (insn);
11322 /* Scan X for promoted SUBREGs. For each one found,
11323 note what it implies to the registers used in it. */
11326 check_promoted_subreg (insn, x)
11330 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11331 && GET_CODE (SUBREG_REG (x)) == REG)
11332 record_promoted_value (insn, x);
11335 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11338 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11339 switch (format [i])
11342 check_promoted_subreg (insn, XEXP (x, i));
11346 if (XVEC (x, i) != 0)
11347 for (j = 0; j < XVECLEN (x, i); j++)
11348 check_promoted_subreg (insn, XVECEXP (x, i, j));
11354 /* Utility routine for the following function. Verify that all the registers
11355 mentioned in *LOC are valid when *LOC was part of a value set when
11356 label_tick == TICK. Return 0 if some are not.
11358 If REPLACE is non-zero, replace the invalid reference with
11359 (clobber (const_int 0)) and return 1. This replacement is useful because
11360 we often can get useful information about the form of a value (e.g., if
11361 it was produced by a shift that always produces -1 or 0) even though
11362 we don't know exactly what registers it was produced from. */
11365 get_last_value_validate (loc, insn, tick, replace)
11372 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11373 int len = GET_RTX_LENGTH (GET_CODE (x));
11376 if (GET_CODE (x) == REG)
11378 unsigned int regno = REGNO (x);
11379 unsigned int endregno
11380 = regno + (regno < FIRST_PSEUDO_REGISTER
11381 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11384 for (j = regno; j < endregno; j++)
11385 if (reg_last_set_invalid[j]
11386 /* If this is a pseudo-register that was only set once and not
11387 live at the beginning of the function, it is always valid. */
11388 || (! (regno >= FIRST_PSEUDO_REGISTER
11389 && REG_N_SETS (regno) == 1
11390 && (! REGNO_REG_SET_P
11391 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11392 && reg_last_set_label[j] > tick))
11395 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11401 /* If this is a memory reference, make sure that there were
11402 no stores after it that might have clobbered the value. We don't
11403 have alias info, so we assume any store invalidates it. */
11404 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11405 && INSN_CUID (insn) <= mem_last_set)
11408 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11412 for (i = 0; i < len; i++)
11414 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11415 /* Don't bother with these. They shouldn't occur anyway. */
11419 /* If we haven't found a reason for it to be invalid, it is valid. */
11423 /* Get the last value assigned to X, if known. Some registers
11424 in the value may be replaced with (clobber (const_int 0)) if their value
11425 is known longer known reliably. */
11431 unsigned int regno;
11434 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11435 then convert it to the desired mode. If this is a paradoxical SUBREG,
11436 we cannot predict what values the "extra" bits might have. */
11437 if (GET_CODE (x) == SUBREG
11438 && subreg_lowpart_p (x)
11439 && (GET_MODE_SIZE (GET_MODE (x))
11440 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11441 && (value = get_last_value (SUBREG_REG (x))) != 0)
11442 return gen_lowpart_for_combine (GET_MODE (x), value);
11444 if (GET_CODE (x) != REG)
11448 value = reg_last_set_value[regno];
11450 /* If we don't have a value, or if it isn't for this basic block and
11451 it's either a hard register, set more than once, or it's a live
11452 at the beginning of the function, return 0.
11454 Because if it's not live at the beginnning of the function then the reg
11455 is always set before being used (is never used without being set).
11456 And, if it's set only once, and it's always set before use, then all
11457 uses must have the same last value, even if it's not from this basic
11461 || (reg_last_set_label[regno] != label_tick
11462 && (regno < FIRST_PSEUDO_REGISTER
11463 || REG_N_SETS (regno) != 1
11464 || (REGNO_REG_SET_P
11465 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11468 /* If the value was set in a later insn than the ones we are processing,
11469 we can't use it even if the register was only set once. */
11470 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11473 /* If the value has all its registers valid, return it. */
11474 if (get_last_value_validate (&value, reg_last_set[regno],
11475 reg_last_set_label[regno], 0))
11478 /* Otherwise, make a copy and replace any invalid register with
11479 (clobber (const_int 0)). If that fails for some reason, return 0. */
11481 value = copy_rtx (value);
11482 if (get_last_value_validate (&value, reg_last_set[regno],
11483 reg_last_set_label[regno], 1))
11489 /* Return nonzero if expression X refers to a REG or to memory
11490 that is set in an instruction more recent than FROM_CUID. */
11493 use_crosses_set_p (x, from_cuid)
11497 register const char *fmt;
11499 register enum rtx_code code = GET_CODE (x);
11503 unsigned int regno = REGNO (x);
11504 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11505 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11507 #ifdef PUSH_ROUNDING
11508 /* Don't allow uses of the stack pointer to be moved,
11509 because we don't know whether the move crosses a push insn. */
11510 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11513 for (; regno < endreg; regno++)
11514 if (reg_last_set[regno]
11515 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11520 if (code == MEM && mem_last_set > from_cuid)
11523 fmt = GET_RTX_FORMAT (code);
11525 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11530 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11531 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11534 else if (fmt[i] == 'e'
11535 && use_crosses_set_p (XEXP (x, i), from_cuid))
11541 /* Define three variables used for communication between the following
11544 static unsigned int reg_dead_regno, reg_dead_endregno;
11545 static int reg_dead_flag;
11547 /* Function called via note_stores from reg_dead_at_p.
11549 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11550 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11553 reg_dead_at_p_1 (dest, x, data)
11556 void *data ATTRIBUTE_UNUSED;
11558 unsigned int regno, endregno;
11560 if (GET_CODE (dest) != REG)
11563 regno = REGNO (dest);
11564 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11565 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11567 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11568 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11571 /* Return non-zero if REG is known to be dead at INSN.
11573 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11574 referencing REG, it is dead. If we hit a SET referencing REG, it is
11575 live. Otherwise, see if it is live or dead at the start of the basic
11576 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11577 must be assumed to be always live. */
11580 reg_dead_at_p (reg, insn)
11587 /* Set variables for reg_dead_at_p_1. */
11588 reg_dead_regno = REGNO (reg);
11589 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11590 ? HARD_REGNO_NREGS (reg_dead_regno,
11596 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11597 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11599 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11600 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11604 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11605 beginning of function. */
11606 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11607 insn = prev_nonnote_insn (insn))
11609 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11611 return reg_dead_flag == 1 ? 1 : 0;
11613 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11617 /* Get the basic block number that we were in. */
11622 for (block = 0; block < n_basic_blocks; block++)
11623 if (insn == BLOCK_HEAD (block))
11626 if (block == n_basic_blocks)
11630 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11631 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11637 /* Note hard registers in X that are used. This code is similar to
11638 that in flow.c, but much simpler since we don't care about pseudos. */
11641 mark_used_regs_combine (x)
11644 RTX_CODE code = GET_CODE (x);
11645 unsigned int regno;
11657 case ADDR_DIFF_VEC:
11660 /* CC0 must die in the insn after it is set, so we don't need to take
11661 special note of it here. */
11667 /* If we are clobbering a MEM, mark any hard registers inside the
11668 address as used. */
11669 if (GET_CODE (XEXP (x, 0)) == MEM)
11670 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11675 /* A hard reg in a wide mode may really be multiple registers.
11676 If so, mark all of them just like the first. */
11677 if (regno < FIRST_PSEUDO_REGISTER)
11679 unsigned int endregno, r;
11681 /* None of this applies to the stack, frame or arg pointers */
11682 if (regno == STACK_POINTER_REGNUM
11683 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11684 || regno == HARD_FRAME_POINTER_REGNUM
11686 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11687 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11689 || regno == FRAME_POINTER_REGNUM)
11692 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11693 for (r = regno; r < endregno; r++)
11694 SET_HARD_REG_BIT (newpat_used_regs, r);
11700 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11702 register rtx testreg = SET_DEST (x);
11704 while (GET_CODE (testreg) == SUBREG
11705 || GET_CODE (testreg) == ZERO_EXTRACT
11706 || GET_CODE (testreg) == SIGN_EXTRACT
11707 || GET_CODE (testreg) == STRICT_LOW_PART)
11708 testreg = XEXP (testreg, 0);
11710 if (GET_CODE (testreg) == MEM)
11711 mark_used_regs_combine (XEXP (testreg, 0));
11713 mark_used_regs_combine (SET_SRC (x));
11721 /* Recursively scan the operands of this expression. */
11724 register const char *fmt = GET_RTX_FORMAT (code);
11726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11729 mark_used_regs_combine (XEXP (x, i));
11730 else if (fmt[i] == 'E')
11734 for (j = 0; j < XVECLEN (x, i); j++)
11735 mark_used_regs_combine (XVECEXP (x, i, j));
11742 /* Remove register number REGNO from the dead registers list of INSN.
11744 Return the note used to record the death, if there was one. */
11747 remove_death (regno, insn)
11748 unsigned int regno;
11751 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11755 REG_N_DEATHS (regno)--;
11756 remove_note (insn, note);
11762 /* For each register (hardware or pseudo) used within expression X, if its
11763 death is in an instruction with cuid between FROM_CUID (inclusive) and
11764 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11765 list headed by PNOTES.
11767 That said, don't move registers killed by maybe_kill_insn.
11769 This is done when X is being merged by combination into TO_INSN. These
11770 notes will then be distributed as needed. */
11773 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11775 rtx maybe_kill_insn;
11780 register const char *fmt;
11781 register int len, i;
11782 register enum rtx_code code = GET_CODE (x);
11786 unsigned int regno = REGNO (x);
11787 register rtx where_dead = reg_last_death[regno];
11788 register rtx before_dead, after_dead;
11790 /* Don't move the register if it gets killed in between from and to */
11791 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11792 && ! reg_referenced_p (x, maybe_kill_insn))
11795 /* WHERE_DEAD could be a USE insn made by combine, so first we
11796 make sure that we have insns with valid INSN_CUID values. */
11797 before_dead = where_dead;
11798 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11799 before_dead = PREV_INSN (before_dead);
11801 after_dead = where_dead;
11802 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11803 after_dead = NEXT_INSN (after_dead);
11805 if (before_dead && after_dead
11806 && INSN_CUID (before_dead) >= from_cuid
11807 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11808 || (where_dead != after_dead
11809 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11811 rtx note = remove_death (regno, where_dead);
11813 /* It is possible for the call above to return 0. This can occur
11814 when reg_last_death points to I2 or I1 that we combined with.
11815 In that case make a new note.
11817 We must also check for the case where X is a hard register
11818 and NOTE is a death note for a range of hard registers
11819 including X. In that case, we must put REG_DEAD notes for
11820 the remaining registers in place of NOTE. */
11822 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11823 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11824 > GET_MODE_SIZE (GET_MODE (x))))
11826 unsigned int deadregno = REGNO (XEXP (note, 0));
11827 unsigned int deadend
11828 = (deadregno + HARD_REGNO_NREGS (deadregno,
11829 GET_MODE (XEXP (note, 0))));
11830 unsigned int ourend
11831 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11834 for (i = deadregno; i < deadend; i++)
11835 if (i < regno || i >= ourend)
11836 REG_NOTES (where_dead)
11837 = gen_rtx_EXPR_LIST (REG_DEAD,
11838 gen_rtx_REG (reg_raw_mode[i], i),
11839 REG_NOTES (where_dead));
11842 /* If we didn't find any note, or if we found a REG_DEAD note that
11843 covers only part of the given reg, and we have a multi-reg hard
11844 register, then to be safe we must check for REG_DEAD notes
11845 for each register other than the first. They could have
11846 their own REG_DEAD notes lying around. */
11847 else if ((note == 0
11849 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11850 < GET_MODE_SIZE (GET_MODE (x)))))
11851 && regno < FIRST_PSEUDO_REGISTER
11852 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11854 unsigned int ourend
11855 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11856 unsigned int i, offset;
11860 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11864 for (i = regno + offset; i < ourend; i++)
11865 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11866 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11869 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11871 XEXP (note, 1) = *pnotes;
11875 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11877 REG_N_DEATHS (regno)++;
11883 else if (GET_CODE (x) == SET)
11885 rtx dest = SET_DEST (x);
11887 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11889 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11890 that accesses one word of a multi-word item, some
11891 piece of everything register in the expression is used by
11892 this insn, so remove any old death. */
11894 if (GET_CODE (dest) == ZERO_EXTRACT
11895 || GET_CODE (dest) == STRICT_LOW_PART
11896 || (GET_CODE (dest) == SUBREG
11897 && (((GET_MODE_SIZE (GET_MODE (dest))
11898 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11899 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11900 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11902 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11906 /* If this is some other SUBREG, we know it replaces the entire
11907 value, so use that as the destination. */
11908 if (GET_CODE (dest) == SUBREG)
11909 dest = SUBREG_REG (dest);
11911 /* If this is a MEM, adjust deaths of anything used in the address.
11912 For a REG (the only other possibility), the entire value is
11913 being replaced so the old value is not used in this insn. */
11915 if (GET_CODE (dest) == MEM)
11916 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11921 else if (GET_CODE (x) == CLOBBER)
11924 len = GET_RTX_LENGTH (code);
11925 fmt = GET_RTX_FORMAT (code);
11927 for (i = 0; i < len; i++)
11932 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11933 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11936 else if (fmt[i] == 'e')
11937 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11941 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11942 pattern of an insn. X must be a REG. */
11945 reg_bitfield_target_p (x, body)
11951 if (GET_CODE (body) == SET)
11953 rtx dest = SET_DEST (body);
11955 unsigned int regno, tregno, endregno, endtregno;
11957 if (GET_CODE (dest) == ZERO_EXTRACT)
11958 target = XEXP (dest, 0);
11959 else if (GET_CODE (dest) == STRICT_LOW_PART)
11960 target = SUBREG_REG (XEXP (dest, 0));
11964 if (GET_CODE (target) == SUBREG)
11965 target = SUBREG_REG (target);
11967 if (GET_CODE (target) != REG)
11970 tregno = REGNO (target), regno = REGNO (x);
11971 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11972 return target == x;
11974 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11975 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11977 return endregno > tregno && regno < endtregno;
11980 else if (GET_CODE (body) == PARALLEL)
11981 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11982 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11988 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11989 as appropriate. I3 and I2 are the insns resulting from the combination
11990 insns including FROM (I2 may be zero).
11992 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11993 not need REG_DEAD notes because they are being substituted for. This
11994 saves searching in the most common cases.
11996 Each note in the list is either ignored or placed on some insns, depending
11997 on the type of note. */
12000 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12004 rtx elim_i2, elim_i1;
12006 rtx note, next_note;
12009 for (note = notes; note; note = next_note)
12011 rtx place = 0, place2 = 0;
12013 /* If this NOTE references a pseudo register, ensure it references
12014 the latest copy of that register. */
12015 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12016 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12017 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12019 next_note = XEXP (note, 1);
12020 switch (REG_NOTE_KIND (note))
12023 case REG_EXEC_COUNT:
12024 /* Doesn't matter much where we put this, as long as it's somewhere.
12025 It is preferable to keep these notes on branches, which is most
12026 likely to be i3. */
12030 case REG_EH_REGION:
12031 case REG_EH_RETHROW:
12032 /* These notes must remain with the call. It should not be
12033 possible for both I2 and I3 to be a call. */
12034 if (GET_CODE (i3) == CALL_INSN)
12036 else if (i2 && GET_CODE (i2) == CALL_INSN)
12043 /* Any clobbers for i3 may still exist, and so we must process
12044 REG_UNUSED notes from that insn.
12046 Any clobbers from i2 or i1 can only exist if they were added by
12047 recog_for_combine. In that case, recog_for_combine created the
12048 necessary REG_UNUSED notes. Trying to keep any original
12049 REG_UNUSED notes from these insns can cause incorrect output
12050 if it is for the same register as the original i3 dest.
12051 In that case, we will notice that the register is set in i3,
12052 and then add a REG_UNUSED note for the destination of i3, which
12053 is wrong. However, it is possible to have REG_UNUSED notes from
12054 i2 or i1 for register which were both used and clobbered, so
12055 we keep notes from i2 or i1 if they will turn into REG_DEAD
12058 /* If this register is set or clobbered in I3, put the note there
12059 unless there is one already. */
12060 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12062 if (from_insn != i3)
12065 if (! (GET_CODE (XEXP (note, 0)) == REG
12066 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12067 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12070 /* Otherwise, if this register is used by I3, then this register
12071 now dies here, so we must put a REG_DEAD note here unless there
12073 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12074 && ! (GET_CODE (XEXP (note, 0)) == REG
12075 ? find_regno_note (i3, REG_DEAD,
12076 REGNO (XEXP (note, 0)))
12077 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12079 PUT_REG_NOTE_KIND (note, REG_DEAD);
12088 /* These notes say something about results of an insn. We can
12089 only support them if they used to be on I3 in which case they
12090 remain on I3. Otherwise they are ignored.
12092 If the note refers to an expression that is not a constant, we
12093 must also ignore the note since we cannot tell whether the
12094 equivalence is still true. It might be possible to do
12095 slightly better than this (we only have a problem if I2DEST
12096 or I1DEST is present in the expression), but it doesn't
12097 seem worth the trouble. */
12099 if (from_insn == i3
12100 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12105 case REG_NO_CONFLICT:
12106 /* These notes say something about how a register is used. They must
12107 be present on any use of the register in I2 or I3. */
12108 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12111 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12121 /* This can show up in several ways -- either directly in the
12122 pattern, or hidden off in the constant pool with (or without?)
12123 a REG_EQUAL note. */
12124 /* ??? Ignore the without-reg_equal-note problem for now. */
12125 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12126 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12127 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12128 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12132 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12133 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12134 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12135 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12145 /* It is too much trouble to try to see if this note is still
12146 correct in all situations. It is better to simply delete it. */
12150 /* If the insn previously containing this note still exists,
12151 put it back where it was. Otherwise move it to the previous
12152 insn. Adjust the corresponding REG_LIBCALL note. */
12153 if (GET_CODE (from_insn) != NOTE)
12157 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12158 place = prev_real_insn (from_insn);
12160 XEXP (tem, 0) = place;
12165 /* This is handled similarly to REG_RETVAL. */
12166 if (GET_CODE (from_insn) != NOTE)
12170 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12171 place = next_real_insn (from_insn);
12173 XEXP (tem, 0) = place;
12178 /* If the register is used as an input in I3, it dies there.
12179 Similarly for I2, if it is non-zero and adjacent to I3.
12181 If the register is not used as an input in either I3 or I2
12182 and it is not one of the registers we were supposed to eliminate,
12183 there are two possibilities. We might have a non-adjacent I2
12184 or we might have somehow eliminated an additional register
12185 from a computation. For example, we might have had A & B where
12186 we discover that B will always be zero. In this case we will
12187 eliminate the reference to A.
12189 In both cases, we must search to see if we can find a previous
12190 use of A and put the death note there. */
12193 && GET_CODE (from_insn) == CALL_INSN
12194 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12196 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12198 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12199 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12202 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12207 basic_block bb = BASIC_BLOCK (this_basic_block);
12209 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12211 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12213 if (tem == bb->head)
12218 /* If the register is being set at TEM, see if that is all
12219 TEM is doing. If so, delete TEM. Otherwise, make this
12220 into a REG_UNUSED note instead. */
12221 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12223 rtx set = single_set (tem);
12224 rtx inner_dest = 0;
12226 rtx cc0_setter = NULL_RTX;
12230 for (inner_dest = SET_DEST (set);
12231 GET_CODE (inner_dest) == STRICT_LOW_PART
12232 || GET_CODE (inner_dest) == SUBREG
12233 || GET_CODE (inner_dest) == ZERO_EXTRACT;
12234 inner_dest = XEXP (inner_dest, 0))
12237 /* Verify that it was the set, and not a clobber that
12238 modified the register.
12240 CC0 targets must be careful to maintain setter/user
12241 pairs. If we cannot delete the setter due to side
12242 effects, mark the user with an UNUSED note instead
12245 if (set != 0 && ! side_effects_p (SET_SRC (set))
12246 && rtx_equal_p (XEXP (note, 0), inner_dest)
12248 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12249 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12250 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12254 /* Move the notes and links of TEM elsewhere.
12255 This might delete other dead insns recursively.
12256 First set the pattern to something that won't use
12259 PATTERN (tem) = pc_rtx;
12261 distribute_notes (REG_NOTES (tem), tem, tem,
12262 NULL_RTX, NULL_RTX, NULL_RTX);
12263 distribute_links (LOG_LINKS (tem));
12265 PUT_CODE (tem, NOTE);
12266 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12267 NOTE_SOURCE_FILE (tem) = 0;
12270 /* Delete the setter too. */
12273 PATTERN (cc0_setter) = pc_rtx;
12275 distribute_notes (REG_NOTES (cc0_setter),
12276 cc0_setter, cc0_setter,
12277 NULL_RTX, NULL_RTX, NULL_RTX);
12278 distribute_links (LOG_LINKS (cc0_setter));
12280 PUT_CODE (cc0_setter, NOTE);
12281 NOTE_LINE_NUMBER (cc0_setter)
12282 = NOTE_INSN_DELETED;
12283 NOTE_SOURCE_FILE (cc0_setter) = 0;
12287 /* If the register is both set and used here, put the
12288 REG_DEAD note here, but place a REG_UNUSED note
12289 here too unless there already is one. */
12290 else if (reg_referenced_p (XEXP (note, 0),
12295 if (! find_regno_note (tem, REG_UNUSED,
12296 REGNO (XEXP (note, 0))))
12298 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12303 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12305 /* If there isn't already a REG_UNUSED note, put one
12307 if (! find_regno_note (tem, REG_UNUSED,
12308 REGNO (XEXP (note, 0))))
12313 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12314 || (GET_CODE (tem) == CALL_INSN
12315 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12319 /* If we are doing a 3->2 combination, and we have a
12320 register which formerly died in i3 and was not used
12321 by i2, which now no longer dies in i3 and is used in
12322 i2 but does not die in i2, and place is between i2
12323 and i3, then we may need to move a link from place to
12325 if (i2 && INSN_UID (place) <= max_uid_cuid
12326 && INSN_CUID (place) > INSN_CUID (i2)
12327 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12328 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12330 rtx links = LOG_LINKS (place);
12331 LOG_LINKS (place) = 0;
12332 distribute_links (links);
12337 if (tem == bb->head)
12341 /* We haven't found an insn for the death note and it
12342 is still a REG_DEAD note, but we have hit the beginning
12343 of the block. If the existing life info says the reg
12344 was dead, there's nothing left to do. Otherwise, we'll
12345 need to do a global life update after combine. */
12346 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12347 && REGNO_REG_SET_P (bb->global_live_at_start,
12348 REGNO (XEXP (note, 0))))
12350 SET_BIT (refresh_blocks, this_basic_block);
12355 /* If the register is set or already dead at PLACE, we needn't do
12356 anything with this note if it is still a REG_DEAD note.
12357 We can here if it is set at all, not if is it totally replace,
12358 which is what `dead_or_set_p' checks, so also check for it being
12361 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12363 unsigned int regno = REGNO (XEXP (note, 0));
12365 if (dead_or_set_p (place, XEXP (note, 0))
12366 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12368 /* Unless the register previously died in PLACE, clear
12369 reg_last_death. [I no longer understand why this is
12371 if (reg_last_death[regno] != place)
12372 reg_last_death[regno] = 0;
12376 reg_last_death[regno] = place;
12378 /* If this is a death note for a hard reg that is occupying
12379 multiple registers, ensure that we are still using all
12380 parts of the object. If we find a piece of the object
12381 that is unused, we must add a USE for that piece before
12382 PLACE and put the appropriate REG_DEAD note on it.
12384 An alternative would be to put a REG_UNUSED for the pieces
12385 on the insn that set the register, but that can't be done if
12386 it is not in the same block. It is simpler, though less
12387 efficient, to add the USE insns. */
12389 if (place && regno < FIRST_PSEUDO_REGISTER
12390 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12392 unsigned int endregno
12393 = regno + HARD_REGNO_NREGS (regno,
12394 GET_MODE (XEXP (note, 0)));
12398 for (i = regno; i < endregno; i++)
12399 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12400 && ! find_regno_fusage (place, USE, i))
12402 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12405 /* See if we already placed a USE note for this
12406 register in front of PLACE. */
12408 GET_CODE (PREV_INSN (p)) == INSN
12409 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12411 if (rtx_equal_p (piece,
12412 XEXP (PATTERN (PREV_INSN (p)), 0)))
12421 = emit_insn_before (gen_rtx_USE (VOIDmode,
12424 REG_NOTES (use_insn)
12425 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12426 REG_NOTES (use_insn));
12432 /* Check for the case where the register dying partially
12433 overlaps the register set by this insn. */
12435 for (i = regno; i < endregno; i++)
12436 if (dead_or_set_regno_p (place, i))
12444 /* Put only REG_DEAD notes for pieces that are
12445 still used and that are not already dead or set. */
12447 for (i = regno; i < endregno; i++)
12449 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12451 if ((reg_referenced_p (piece, PATTERN (place))
12452 || (GET_CODE (place) == CALL_INSN
12453 && find_reg_fusage (place, USE, piece)))
12454 && ! dead_or_set_p (place, piece)
12455 && ! reg_bitfield_target_p (piece,
12458 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12459 REG_NOTES (place));
12469 /* Any other notes should not be present at this point in the
12476 XEXP (note, 1) = REG_NOTES (place);
12477 REG_NOTES (place) = note;
12479 else if ((REG_NOTE_KIND (note) == REG_DEAD
12480 || REG_NOTE_KIND (note) == REG_UNUSED)
12481 && GET_CODE (XEXP (note, 0)) == REG)
12482 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12486 if ((REG_NOTE_KIND (note) == REG_DEAD
12487 || REG_NOTE_KIND (note) == REG_UNUSED)
12488 && GET_CODE (XEXP (note, 0)) == REG)
12489 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12491 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12492 REG_NOTE_KIND (note),
12494 REG_NOTES (place2));
12499 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12500 I3, I2, and I1 to new locations. This is also called in one case to
12501 add a link pointing at I3 when I3's destination is changed. */
12504 distribute_links (links)
12507 rtx link, next_link;
12509 for (link = links; link; link = next_link)
12515 next_link = XEXP (link, 1);
12517 /* If the insn that this link points to is a NOTE or isn't a single
12518 set, ignore it. In the latter case, it isn't clear what we
12519 can do other than ignore the link, since we can't tell which
12520 register it was for. Such links wouldn't be used by combine
12523 It is not possible for the destination of the target of the link to
12524 have been changed by combine. The only potential of this is if we
12525 replace I3, I2, and I1 by I3 and I2. But in that case the
12526 destination of I2 also remains unchanged. */
12528 if (GET_CODE (XEXP (link, 0)) == NOTE
12529 || (set = single_set (XEXP (link, 0))) == 0)
12532 reg = SET_DEST (set);
12533 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12534 || GET_CODE (reg) == SIGN_EXTRACT
12535 || GET_CODE (reg) == STRICT_LOW_PART)
12536 reg = XEXP (reg, 0);
12538 /* A LOG_LINK is defined as being placed on the first insn that uses
12539 a register and points to the insn that sets the register. Start
12540 searching at the next insn after the target of the link and stop
12541 when we reach a set of the register or the end of the basic block.
12543 Note that this correctly handles the link that used to point from
12544 I3 to I2. Also note that not much searching is typically done here
12545 since most links don't point very far away. */
12547 for (insn = NEXT_INSN (XEXP (link, 0));
12548 (insn && (this_basic_block == n_basic_blocks - 1
12549 || BLOCK_HEAD (this_basic_block + 1) != insn));
12550 insn = NEXT_INSN (insn))
12551 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12552 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12554 if (reg_referenced_p (reg, PATTERN (insn)))
12558 else if (GET_CODE (insn) == CALL_INSN
12559 && find_reg_fusage (insn, USE, reg))
12565 /* If we found a place to put the link, place it there unless there
12566 is already a link to the same insn as LINK at that point. */
12572 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12573 if (XEXP (link2, 0) == XEXP (link, 0))
12578 XEXP (link, 1) = LOG_LINKS (place);
12579 LOG_LINKS (place) = link;
12581 /* Set added_links_insn to the earliest insn we added a
12583 if (added_links_insn == 0
12584 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12585 added_links_insn = place;
12591 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12597 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12598 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12599 insn = NEXT_INSN (insn);
12601 if (INSN_UID (insn) > max_uid_cuid)
12604 return INSN_CUID (insn);
12608 dump_combine_stats (file)
12613 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12614 combine_attempts, combine_merges, combine_extras, combine_successes);
12618 dump_combine_total_stats (file)
12623 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12624 total_attempts, total_merges, total_extras, total_successes);