1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999, 2000 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
120 /* Define a default value for REVERSIBLE_CC_MODE.
121 We can never assume that a condition code mode is safe to reverse unless
122 the md tells us so. */
123 #ifndef REVERSIBLE_CC_MODE
124 #define REVERSIBLE_CC_MODE(MODE) 0
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx *reg_last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx *reg_last_set;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn;
172 /* This is an insn that belongs before subst_insn, but is not currently
173 on the insn chain. */
175 static rtx subst_prev_insn;
177 /* This is the lowest CUID that `subst' is currently dealing with.
178 get_last_value will not return a value if the register was set at or
179 after this CUID. If not for this mechanism, we could get confused if
180 I2 or I1 in try_combine were an insn that used the old value of a register
181 to obtain a new value. In that case, we might erroneously get the
182 new value of the register when we wanted the old one. */
184 static int subst_low_cuid;
186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
187 must consider all these registers to be always live. */
189 static HARD_REG_SET newpat_used_regs;
191 /* This is an insn to which a LOG_LINKS entry has been added. If this
192 insn is the earlier than I2 or I3, combine should rescan starting at
195 static rtx added_links_insn;
197 /* Basic block number of the block in which we are performing combines. */
198 static int this_basic_block;
200 /* A bitmap indicating which blocks had registers go dead at entry.
201 After combine, we'll need to re-do global life analysis with
202 those blocks as starting points. */
203 static sbitmap refresh_blocks;
204 static int need_refresh;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx *reg_last_set_value;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid;
269 /* Incremented for each label. */
271 static int label_tick;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo *previous_undos;
346 static struct undobuf undobuf;
348 /* Number of times the pseudo being substituted for
349 was found and replaced. */
351 static int n_occurrences;
353 static void do_SUBST PARAMS ((rtx *, rtx));
354 static void do_SUBST_INT PARAMS ((int *, int));
355 static void init_reg_last_arrays PARAMS ((void));
356 static void setup_incoming_promotions PARAMS ((void));
357 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
358 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
359 static int sets_function_arg_p PARAMS ((rtx));
360 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
361 static int contains_muldiv PARAMS ((rtx));
362 static rtx try_combine PARAMS ((rtx, rtx, rtx));
363 static void undo_all PARAMS ((void));
364 static void undo_commit PARAMS ((void));
365 static rtx *find_split_point PARAMS ((rtx *, rtx));
366 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
367 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
368 static rtx simplify_if_then_else PARAMS ((rtx));
369 static rtx simplify_set PARAMS ((rtx));
370 static rtx simplify_logical PARAMS ((rtx, int));
371 static rtx expand_compound_operation PARAMS ((rtx));
372 static rtx expand_field_assignment PARAMS ((rtx));
373 static rtx make_extraction PARAMS ((enum machine_mode, rtx, int, rtx, int,
375 static rtx extract_left_shift PARAMS ((rtx, int));
376 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
377 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT, int *));
378 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
379 unsigned HOST_WIDE_INT, rtx, int));
380 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
381 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
382 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
383 static rtx make_field_assignment PARAMS ((rtx));
384 static rtx apply_distributive_law PARAMS ((rtx));
385 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
386 unsigned HOST_WIDE_INT));
387 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
388 static int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
389 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
390 enum rtx_code, HOST_WIDE_INT,
391 enum machine_mode, int *));
392 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
394 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
395 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
396 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
398 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
400 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
401 enum machine_mode, rtx));
402 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
403 static int reversible_comparison_p PARAMS ((rtx));
404 static void update_table_tick PARAMS ((rtx));
405 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
406 static void check_promoted_subreg PARAMS ((rtx, rtx));
407 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
408 static void record_dead_and_set_regs PARAMS ((rtx));
409 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
410 static rtx get_last_value PARAMS ((rtx));
411 static int use_crosses_set_p PARAMS ((rtx, int));
412 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
413 static int reg_dead_at_p PARAMS ((rtx, rtx));
414 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
415 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
416 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
417 static void distribute_links PARAMS ((rtx));
418 static void mark_used_regs_combine PARAMS ((rtx));
419 static int insn_cuid PARAMS ((rtx));
421 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
422 insn. The substitution can be undone by undo_all. If INTO is already
423 set to NEWVAL, do not record this change. Because computing NEWVAL might
424 also call SUBST, we have to compute it before we put anything into
428 do_SUBST(into, newval)
434 if (oldval == newval)
438 buf = undobuf.frees, undobuf.frees = buf->next;
440 buf = (struct undo *) xmalloc (sizeof (struct undo));
444 buf->old_contents.r = oldval;
447 buf->next = undobuf.undos, undobuf.undos = buf;
450 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
452 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
453 for the value of a HOST_WIDE_INT value (including CONST_INT) is
457 do_SUBST_INT(into, newval)
463 if (oldval == newval)
467 buf = undobuf.frees, undobuf.frees = buf->next;
469 buf = (struct undo *) xmalloc (sizeof (struct undo));
473 buf->old_contents.i = oldval;
476 buf->next = undobuf.undos, undobuf.undos = buf;
479 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
481 /* Main entry point for combiner. F is the first insn of the function.
482 NREGS is the first unused pseudo-reg number. */
485 combine_instructions (f, nregs)
489 register rtx insn, next;
494 register rtx links, nextlinks;
496 combine_attempts = 0;
499 combine_successes = 0;
501 combine_max_regno = nregs;
503 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
504 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
505 reg_sign_bit_copies = (char *) xcalloc (nregs, sizeof (char));
507 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
508 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
509 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
510 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
511 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
512 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
514 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
515 reg_last_set_nonzero_bits
516 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
517 reg_last_set_sign_bit_copies
518 = (char *) xmalloc (nregs * sizeof (char));
520 init_reg_last_arrays ();
522 init_recog_no_volatile ();
524 /* Compute maximum uid value so uid_cuid can be allocated. */
526 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
527 if (INSN_UID (insn) > i)
530 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
533 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
535 /* Don't use reg_nonzero_bits when computing it. This can cause problems
536 when, for example, we have j <<= 1 in a loop. */
538 nonzero_sign_valid = 0;
540 /* Compute the mapping from uids to cuids.
541 Cuids are numbers assigned to insns, like uids,
542 except that cuids increase monotonically through the code.
544 Scan all SETs and see if we can deduce anything about what
545 bits are known to be zero for some registers and how many copies
546 of the sign bit are known to exist for those registers.
548 Also set any known values so that we can use it while searching
549 for what bits are known to be set. */
553 /* We need to initialize it here, because record_dead_and_set_regs may call
555 subst_prev_insn = NULL_RTX;
557 setup_incoming_promotions ();
559 refresh_blocks = sbitmap_alloc (n_basic_blocks);
560 sbitmap_zero (refresh_blocks);
563 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
565 uid_cuid[INSN_UID (insn)] = ++i;
569 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
571 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
573 record_dead_and_set_regs (insn);
576 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
577 if (REG_NOTE_KIND (links) == REG_INC)
578 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
583 if (GET_CODE (insn) == CODE_LABEL)
587 nonzero_sign_valid = 1;
589 /* Now scan all the insns in forward order. */
591 this_basic_block = -1;
595 init_reg_last_arrays ();
596 setup_incoming_promotions ();
598 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
602 /* If INSN starts a new basic block, update our basic block number. */
603 if (this_basic_block + 1 < n_basic_blocks
604 && BLOCK_HEAD (this_basic_block + 1) == insn)
607 if (GET_CODE (insn) == CODE_LABEL)
610 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
612 /* See if we know about function return values before this
613 insn based upon SUBREG flags. */
614 check_promoted_subreg (insn, PATTERN (insn));
616 /* Try this insn with each insn it links back to. */
618 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
619 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
622 /* Try each sequence of three linked insns ending with this one. */
624 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
625 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
626 nextlinks = XEXP (nextlinks, 1))
627 if ((next = try_combine (insn, XEXP (links, 0),
628 XEXP (nextlinks, 0))) != 0)
632 /* Try to combine a jump insn that uses CC0
633 with a preceding insn that sets CC0, and maybe with its
634 logical predecessor as well.
635 This is how we make decrement-and-branch insns.
636 We need this special code because data flow connections
637 via CC0 do not get entered in LOG_LINKS. */
639 if (GET_CODE (insn) == JUMP_INSN
640 && (prev = prev_nonnote_insn (insn)) != 0
641 && GET_CODE (prev) == INSN
642 && sets_cc0_p (PATTERN (prev)))
644 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
647 for (nextlinks = LOG_LINKS (prev); nextlinks;
648 nextlinks = XEXP (nextlinks, 1))
649 if ((next = try_combine (insn, prev,
650 XEXP (nextlinks, 0))) != 0)
654 /* Do the same for an insn that explicitly references CC0. */
655 if (GET_CODE (insn) == INSN
656 && (prev = prev_nonnote_insn (insn)) != 0
657 && GET_CODE (prev) == INSN
658 && sets_cc0_p (PATTERN (prev))
659 && GET_CODE (PATTERN (insn)) == SET
660 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
662 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
665 for (nextlinks = LOG_LINKS (prev); nextlinks;
666 nextlinks = XEXP (nextlinks, 1))
667 if ((next = try_combine (insn, prev,
668 XEXP (nextlinks, 0))) != 0)
672 /* Finally, see if any of the insns that this insn links to
673 explicitly references CC0. If so, try this insn, that insn,
674 and its predecessor if it sets CC0. */
675 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
676 if (GET_CODE (XEXP (links, 0)) == INSN
677 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
678 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
679 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
680 && GET_CODE (prev) == INSN
681 && sets_cc0_p (PATTERN (prev))
682 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
686 /* Try combining an insn with two different insns whose results it
688 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
689 for (nextlinks = XEXP (links, 1); nextlinks;
690 nextlinks = XEXP (nextlinks, 1))
691 if ((next = try_combine (insn, XEXP (links, 0),
692 XEXP (nextlinks, 0))) != 0)
695 if (GET_CODE (insn) != NOTE)
696 record_dead_and_set_regs (insn);
705 compute_bb_for_insn (get_max_uid ());
706 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
711 sbitmap_free (refresh_blocks);
712 free (reg_nonzero_bits);
713 free (reg_sign_bit_copies);
714 free (reg_last_death);
716 free (reg_last_set_value);
717 free (reg_last_set_table_tick);
718 free (reg_last_set_label);
719 free (reg_last_set_invalid);
720 free (reg_last_set_mode);
721 free (reg_last_set_nonzero_bits);
722 free (reg_last_set_sign_bit_copies);
726 struct undo *undo, *next;
727 for (undo = undobuf.frees; undo; undo = next)
735 total_attempts += combine_attempts;
736 total_merges += combine_merges;
737 total_extras += combine_extras;
738 total_successes += combine_successes;
740 nonzero_sign_valid = 0;
742 /* Make recognizer allow volatile MEMs again. */
746 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
749 init_reg_last_arrays ()
751 int nregs = combine_max_regno;
753 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
754 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
755 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
756 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
757 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
758 bzero (reg_last_set_invalid, nregs * sizeof (char));
759 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
760 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
761 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
764 /* Set up any promoted values for incoming argument registers. */
767 setup_incoming_promotions ()
769 #ifdef PROMOTE_FUNCTION_ARGS
772 enum machine_mode mode;
774 rtx first = get_insns ();
776 #ifndef OUTGOING_REGNO
777 #define OUTGOING_REGNO(N) N
779 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
780 /* Check whether this register can hold an incoming pointer
781 argument. FUNCTION_ARG_REGNO_P tests outgoing register
782 numbers, so translate if necessary due to register windows. */
783 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
784 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
787 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
790 gen_rtx_CLOBBER (mode, const0_rtx)));
795 /* Called via note_stores. If X is a pseudo that is narrower than
796 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
798 If we are setting only a portion of X and we can't figure out what
799 portion, assume all bits will be used since we don't know what will
802 Similarly, set how many bits of X are known to be copies of the sign bit
803 at all locations in the function. This is the smallest number implied
807 set_nonzero_bits_and_sign_copies (x, set, data)
810 void *data ATTRIBUTE_UNUSED;
814 if (GET_CODE (x) == REG
815 && REGNO (x) >= FIRST_PSEUDO_REGISTER
816 /* If this register is undefined at the start of the file, we can't
817 say what its contents were. */
818 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
819 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
821 if (set == 0 || GET_CODE (set) == CLOBBER)
823 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
824 reg_sign_bit_copies[REGNO (x)] = 1;
828 /* If this is a complex assignment, see if we can convert it into a
829 simple assignment. */
830 set = expand_field_assignment (set);
832 /* If this is a simple assignment, or we have a paradoxical SUBREG,
833 set what we know about X. */
835 if (SET_DEST (set) == x
836 || (GET_CODE (SET_DEST (set)) == SUBREG
837 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
838 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
839 && SUBREG_REG (SET_DEST (set)) == x))
841 rtx src = SET_SRC (set);
843 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
844 /* If X is narrower than a word and SRC is a non-negative
845 constant that would appear negative in the mode of X,
846 sign-extend it for use in reg_nonzero_bits because some
847 machines (maybe most) will actually do the sign-extension
848 and this is the conservative approach.
850 ??? For 2.5, try to tighten up the MD files in this regard
851 instead of this kludge. */
853 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
854 && GET_CODE (src) == CONST_INT
856 && 0 != (INTVAL (src)
858 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
859 src = GEN_INT (INTVAL (src)
860 | ((HOST_WIDE_INT) (-1)
861 << GET_MODE_BITSIZE (GET_MODE (x))));
864 reg_nonzero_bits[REGNO (x)]
865 |= nonzero_bits (src, nonzero_bits_mode);
866 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
867 if (reg_sign_bit_copies[REGNO (x)] == 0
868 || reg_sign_bit_copies[REGNO (x)] > num)
869 reg_sign_bit_copies[REGNO (x)] = num;
873 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
874 reg_sign_bit_copies[REGNO (x)] = 1;
879 /* See if INSN can be combined into I3. PRED and SUCC are optionally
880 insns that were previously combined into I3 or that will be combined
881 into the merger of INSN and I3.
883 Return 0 if the combination is not allowed for any reason.
885 If the combination is allowed, *PDEST will be set to the single
886 destination of INSN and *PSRC to the single source, and this function
890 can_combine_p (insn, i3, pred, succ, pdest, psrc)
893 rtx pred ATTRIBUTE_UNUSED;
898 rtx set = 0, src, dest;
903 int all_adjacent = (succ ? (next_active_insn (insn) == succ
904 && next_active_insn (succ) == i3)
905 : next_active_insn (insn) == i3);
907 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
908 or a PARALLEL consisting of such a SET and CLOBBERs.
910 If INSN has CLOBBER parallel parts, ignore them for our processing.
911 By definition, these happen during the execution of the insn. When it
912 is merged with another insn, all bets are off. If they are, in fact,
913 needed and aren't also supplied in I3, they may be added by
914 recog_for_combine. Otherwise, it won't match.
916 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
919 Get the source and destination of INSN. If more than one, can't
922 if (GET_CODE (PATTERN (insn)) == SET)
923 set = PATTERN (insn);
924 else if (GET_CODE (PATTERN (insn)) == PARALLEL
925 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
927 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
929 rtx elt = XVECEXP (PATTERN (insn), 0, i);
931 switch (GET_CODE (elt))
933 /* This is important to combine floating point insns
936 /* Combining an isolated USE doesn't make sense.
937 We depend here on combinable_i3_pat to reject them. */
938 /* The code below this loop only verifies that the inputs of
939 the SET in INSN do not change. We call reg_set_between_p
940 to verify that the REG in the USE does not change betweeen
942 If the USE in INSN was for a pseudo register, the matching
943 insn pattern will likely match any register; combining this
944 with any other USE would only be safe if we knew that the
945 used registers have identical values, or if there was
946 something to tell them apart, e.g. different modes. For
947 now, we forgo such compilcated tests and simply disallow
948 combining of USES of pseudo registers with any other USE. */
949 if (GET_CODE (XEXP (elt, 0)) == REG
950 && GET_CODE (PATTERN (i3)) == PARALLEL)
952 rtx i3pat = PATTERN (i3);
953 int i = XVECLEN (i3pat, 0) - 1;
954 int regno = REGNO (XEXP (elt, 0));
957 rtx i3elt = XVECEXP (i3pat, 0, i);
958 if (GET_CODE (i3elt) == USE
959 && GET_CODE (XEXP (i3elt, 0)) == REG
960 && (REGNO (XEXP (i3elt, 0)) == regno
961 ? reg_set_between_p (XEXP (elt, 0),
962 PREV_INSN (insn), i3)
963 : regno >= FIRST_PSEUDO_REGISTER))
970 /* We can ignore CLOBBERs. */
975 /* Ignore SETs whose result isn't used but not those that
976 have side-effects. */
977 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
978 && ! side_effects_p (elt))
981 /* If we have already found a SET, this is a second one and
982 so we cannot combine with this insn. */
990 /* Anything else means we can't combine. */
996 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
997 so don't do anything with it. */
998 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1007 set = expand_field_assignment (set);
1008 src = SET_SRC (set), dest = SET_DEST (set);
1010 /* Don't eliminate a store in the stack pointer. */
1011 if (dest == stack_pointer_rtx
1012 /* If we couldn't eliminate a field assignment, we can't combine. */
1013 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1014 /* Don't combine with an insn that sets a register to itself if it has
1015 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1016 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1017 /* Can't merge a function call. */
1018 || GET_CODE (src) == CALL
1019 /* Don't eliminate a function call argument. */
1020 || (GET_CODE (i3) == CALL_INSN
1021 && (find_reg_fusage (i3, USE, dest)
1022 || (GET_CODE (dest) == REG
1023 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1024 && global_regs[REGNO (dest)])))
1025 /* Don't substitute into an incremented register. */
1026 || FIND_REG_INC_NOTE (i3, dest)
1027 || (succ && FIND_REG_INC_NOTE (succ, dest))
1029 /* Don't combine the end of a libcall into anything. */
1030 /* ??? This gives worse code, and appears to be unnecessary, since no
1031 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1032 use REG_RETVAL notes for noconflict blocks, but other code here
1033 makes sure that those insns don't disappear. */
1034 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1036 /* Make sure that DEST is not used after SUCC but before I3. */
1037 || (succ && ! all_adjacent
1038 && reg_used_between_p (dest, succ, i3))
1039 /* Make sure that the value that is to be substituted for the register
1040 does not use any registers whose values alter in between. However,
1041 If the insns are adjacent, a use can't cross a set even though we
1042 think it might (this can happen for a sequence of insns each setting
1043 the same destination; reg_last_set of that register might point to
1044 a NOTE). If INSN has a REG_EQUIV note, the register is always
1045 equivalent to the memory so the substitution is valid even if there
1046 are intervening stores. Also, don't move a volatile asm or
1047 UNSPEC_VOLATILE across any other insns. */
1049 && (((GET_CODE (src) != MEM
1050 || ! find_reg_note (insn, REG_EQUIV, src))
1051 && use_crosses_set_p (src, INSN_CUID (insn)))
1052 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1053 || GET_CODE (src) == UNSPEC_VOLATILE))
1054 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1055 better register allocation by not doing the combine. */
1056 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1057 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1058 /* Don't combine across a CALL_INSN, because that would possibly
1059 change whether the life span of some REGs crosses calls or not,
1060 and it is a pain to update that information.
1061 Exception: if source is a constant, moving it later can't hurt.
1062 Accept that special case, because it helps -fforce-addr a lot. */
1063 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1066 /* DEST must either be a REG or CC0. */
1067 if (GET_CODE (dest) == REG)
1069 /* If register alignment is being enforced for multi-word items in all
1070 cases except for parameters, it is possible to have a register copy
1071 insn referencing a hard register that is not allowed to contain the
1072 mode being copied and which would not be valid as an operand of most
1073 insns. Eliminate this problem by not combining with such an insn.
1075 Also, on some machines we don't want to extend the life of a hard
1078 This is the same test done in can_combine except that we don't test
1079 if SRC is a CALL operation to permit a hard register with
1080 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1083 if (GET_CODE (src) == REG
1084 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1085 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1086 /* Don't extend the life of a hard register unless it is
1087 user variable (if we have few registers) or it can't
1088 fit into the desired register (meaning something special
1090 Also avoid substituting a return register into I3, because
1091 reload can't handle a conflict with constraints of other
1093 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1094 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1095 || (SMALL_REGISTER_CLASSES
1096 && ((! all_adjacent && ! REG_USERVAR_P (src))
1097 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1098 && ! REG_USERVAR_P (src))))))))
1101 else if (GET_CODE (dest) != CC0)
1104 /* Don't substitute for a register intended as a clobberable operand.
1105 Similarly, don't substitute an expression containing a register that
1106 will be clobbered in I3. */
1107 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1108 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1109 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1110 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1112 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1115 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1116 or not), reject, unless nothing volatile comes between it and I3 */
1118 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1120 /* Make sure succ doesn't contain a volatile reference. */
1121 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1124 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1125 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1126 && p != succ && volatile_refs_p (PATTERN (p)))
1130 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1131 to be an explicit register variable, and was chosen for a reason. */
1133 if (GET_CODE (src) == ASM_OPERANDS
1134 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1137 /* If there are any volatile insns between INSN and I3, reject, because
1138 they might affect machine state. */
1140 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1141 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1142 && p != succ && volatile_insn_p (PATTERN (p)))
1145 /* If INSN or I2 contains an autoincrement or autodecrement,
1146 make sure that register is not used between there and I3,
1147 and not already used in I3 either.
1148 Also insist that I3 not be a jump; if it were one
1149 and the incremented register were spilled, we would lose. */
1152 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1153 if (REG_NOTE_KIND (link) == REG_INC
1154 && (GET_CODE (i3) == JUMP_INSN
1155 || reg_used_between_p (XEXP (link, 0), insn, i3)
1156 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1161 /* Don't combine an insn that follows a CC0-setting insn.
1162 An insn that uses CC0 must not be separated from the one that sets it.
1163 We do, however, allow I2 to follow a CC0-setting insn if that insn
1164 is passed as I1; in that case it will be deleted also.
1165 We also allow combining in this case if all the insns are adjacent
1166 because that would leave the two CC0 insns adjacent as well.
1167 It would be more logical to test whether CC0 occurs inside I1 or I2,
1168 but that would be much slower, and this ought to be equivalent. */
1170 p = prev_nonnote_insn (insn);
1171 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1176 /* If we get here, we have passed all the tests and the combination is
1185 /* Check if PAT is an insn - or a part of it - used to set up an
1186 argument for a function in a hard register. */
1189 sets_function_arg_p (pat)
1195 switch (GET_CODE (pat))
1198 return sets_function_arg_p (PATTERN (pat));
1201 for (i = XVECLEN (pat, 0); --i >= 0;)
1202 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1208 inner_dest = SET_DEST (pat);
1209 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1210 || GET_CODE (inner_dest) == SUBREG
1211 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1212 inner_dest = XEXP (inner_dest, 0);
1214 return (GET_CODE (inner_dest) == REG
1215 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1216 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1225 /* LOC is the location within I3 that contains its pattern or the component
1226 of a PARALLEL of the pattern. We validate that it is valid for combining.
1228 One problem is if I3 modifies its output, as opposed to replacing it
1229 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1230 so would produce an insn that is not equivalent to the original insns.
1234 (set (reg:DI 101) (reg:DI 100))
1235 (set (subreg:SI (reg:DI 101) 0) <foo>)
1237 This is NOT equivalent to:
1239 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1240 (set (reg:DI 101) (reg:DI 100))])
1242 Not only does this modify 100 (in which case it might still be valid
1243 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1245 We can also run into a problem if I2 sets a register that I1
1246 uses and I1 gets directly substituted into I3 (not via I2). In that
1247 case, we would be getting the wrong value of I2DEST into I3, so we
1248 must reject the combination. This case occurs when I2 and I1 both
1249 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1250 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1251 of a SET must prevent combination from occurring.
1253 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1254 if the destination of a SET is a hard register that isn't a user
1257 Before doing the above check, we first try to expand a field assignment
1258 into a set of logical operations.
1260 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1261 we place a register that is both set and used within I3. If more than one
1262 such register is detected, we fail.
1264 Return 1 if the combination is valid, zero otherwise. */
1267 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1273 rtx *pi3dest_killed;
1277 if (GET_CODE (x) == SET)
1279 rtx set = expand_field_assignment (x);
1280 rtx dest = SET_DEST (set);
1281 rtx src = SET_SRC (set);
1282 rtx inner_dest = dest;
1285 rtx inner_src = src;
1290 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1291 || GET_CODE (inner_dest) == SUBREG
1292 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1293 inner_dest = XEXP (inner_dest, 0);
1295 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1298 while (GET_CODE (inner_src) == STRICT_LOW_PART
1299 || GET_CODE (inner_src) == SUBREG
1300 || GET_CODE (inner_src) == ZERO_EXTRACT)
1301 inner_src = XEXP (inner_src, 0);
1303 /* If it is better that two different modes keep two different pseudos,
1304 avoid combining them. This avoids producing the following pattern
1306 (set (subreg:SI (reg/v:QI 21) 0)
1307 (lshiftrt:SI (reg/v:SI 20)
1309 If that were made, reload could not handle the pair of
1310 reg 20/21, since it would try to get any GENERAL_REGS
1311 but some of them don't handle QImode. */
1313 if (rtx_equal_p (inner_src, i2dest)
1314 && GET_CODE (inner_dest) == REG
1315 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1319 /* Check for the case where I3 modifies its output, as
1321 if ((inner_dest != dest
1322 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1323 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1325 /* This is the same test done in can_combine_p except that we
1326 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1327 CALL operation. Moreover, we can't test all_adjacent; we don't
1328 have to, since this instruction will stay in place, thus we are
1329 not considering increasing the lifetime of INNER_DEST.
1331 Also, if this insn sets a function argument, combining it with
1332 something that might need a spill could clobber a previous
1333 function argument; the all_adjacent test in can_combine_p also
1334 checks this; here, we do a more specific test for this case. */
1336 || (GET_CODE (inner_dest) == REG
1337 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1338 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1339 GET_MODE (inner_dest))
1340 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1341 && ! REG_USERVAR_P (inner_dest)
1342 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1343 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1345 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1346 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1349 /* If DEST is used in I3, it is being killed in this insn,
1350 so record that for later.
1351 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1352 STACK_POINTER_REGNUM, since these are always considered to be
1353 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1354 if (pi3dest_killed && GET_CODE (dest) == REG
1355 && reg_referenced_p (dest, PATTERN (i3))
1356 && REGNO (dest) != FRAME_POINTER_REGNUM
1357 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1358 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1360 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1361 && (REGNO (dest) != ARG_POINTER_REGNUM
1362 || ! fixed_regs [REGNO (dest)])
1364 && REGNO (dest) != STACK_POINTER_REGNUM)
1366 if (*pi3dest_killed)
1369 *pi3dest_killed = dest;
1373 else if (GET_CODE (x) == PARALLEL)
1377 for (i = 0; i < XVECLEN (x, 0); i++)
1378 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1379 i1_not_in_src, pi3dest_killed))
1386 /* Return 1 if X is an arithmetic expression that contains a multiplication
1387 and division. We don't count multiplications by powers of two here. */
1393 switch (GET_CODE (x))
1395 case MOD: case DIV: case UMOD: case UDIV:
1399 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1400 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1402 switch (GET_RTX_CLASS (GET_CODE (x)))
1404 case 'c': case '<': case '2':
1405 return contains_muldiv (XEXP (x, 0))
1406 || contains_muldiv (XEXP (x, 1));
1409 return contains_muldiv (XEXP (x, 0));
1417 /* Try to combine the insns I1 and I2 into I3.
1418 Here I1 and I2 appear earlier than I3.
1419 I1 can be zero; then we combine just I2 into I3.
1421 It we are combining three insns and the resulting insn is not recognized,
1422 try splitting it into two insns. If that happens, I2 and I3 are retained
1423 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1426 Return 0 if the combination does not work. Then nothing is changed.
1427 If we did the combination, return the insn at which combine should
1431 try_combine (i3, i2, i1)
1432 register rtx i3, i2, i1;
1434 /* New patterns for I3 and I3, respectively. */
1435 rtx newpat, newi2pat = 0;
1436 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1437 int added_sets_1, added_sets_2;
1438 /* Total number of SETs to put into I3. */
1440 /* Nonzero is I2's body now appears in I3. */
1442 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1443 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1444 /* Contains I3 if the destination of I3 is used in its source, which means
1445 that the old life of I3 is being killed. If that usage is placed into
1446 I2 and not in I3, a REG_DEAD note must be made. */
1447 rtx i3dest_killed = 0;
1448 /* SET_DEST and SET_SRC of I2 and I1. */
1449 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1450 /* PATTERN (I2), or a copy of it in certain cases. */
1452 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1453 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1454 int i1_feeds_i3 = 0;
1455 /* Notes that must be added to REG_NOTES in I3 and I2. */
1456 rtx new_i3_notes, new_i2_notes;
1457 /* Notes that we substituted I3 into I2 instead of the normal case. */
1458 int i3_subst_into_i2 = 0;
1459 /* Notes that I1, I2 or I3 is a MULT operation. */
1467 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1468 This can occur when flow deletes an insn that it has merged into an
1469 auto-increment address. We also can't do anything if I3 has a
1470 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1473 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1474 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1475 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1477 /* ??? This gives worse code, and appears to be unnecessary, since no
1478 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1479 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1485 undobuf.other_insn = 0;
1487 /* Save the current high-water-mark so we can free storage if we didn't
1488 accept this combination. */
1489 undobuf.storage = (char *) oballoc (0);
1491 /* Reset the hard register usage information. */
1492 CLEAR_HARD_REG_SET (newpat_used_regs);
1494 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1495 code below, set I1 to be the earlier of the two insns. */
1496 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1497 temp = i1, i1 = i2, i2 = temp;
1499 added_links_insn = 0;
1501 /* First check for one important special-case that the code below will
1502 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1503 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1504 we may be able to replace that destination with the destination of I3.
1505 This occurs in the common code where we compute both a quotient and
1506 remainder into a structure, in which case we want to do the computation
1507 directly into the structure to avoid register-register copies.
1509 We make very conservative checks below and only try to handle the
1510 most common cases of this. For example, we only handle the case
1511 where I2 and I3 are adjacent to avoid making difficult register
1514 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1515 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1516 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1517 && (! SMALL_REGISTER_CLASSES
1518 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1519 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1520 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1521 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1522 && GET_CODE (PATTERN (i2)) == PARALLEL
1523 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1524 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1525 below would need to check what is inside (and reg_overlap_mentioned_p
1526 doesn't support those codes anyway). Don't allow those destinations;
1527 the resulting insn isn't likely to be recognized anyway. */
1528 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1529 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1530 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1531 SET_DEST (PATTERN (i3)))
1532 && next_real_insn (i2) == i3)
1534 rtx p2 = PATTERN (i2);
1536 /* Make sure that the destination of I3,
1537 which we are going to substitute into one output of I2,
1538 is not used within another output of I2. We must avoid making this:
1539 (parallel [(set (mem (reg 69)) ...)
1540 (set (reg 69) ...)])
1541 which is not well-defined as to order of actions.
1542 (Besides, reload can't handle output reloads for this.)
1544 The problem can also happen if the dest of I3 is a memory ref,
1545 if another dest in I2 is an indirect memory ref. */
1546 for (i = 0; i < XVECLEN (p2, 0); i++)
1547 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1548 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1549 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1550 SET_DEST (XVECEXP (p2, 0, i))))
1553 if (i == XVECLEN (p2, 0))
1554 for (i = 0; i < XVECLEN (p2, 0); i++)
1555 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1556 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1557 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1562 subst_low_cuid = INSN_CUID (i2);
1564 added_sets_2 = added_sets_1 = 0;
1565 i2dest = SET_SRC (PATTERN (i3));
1567 /* Replace the dest in I2 with our dest and make the resulting
1568 insn the new pattern for I3. Then skip to where we
1569 validate the pattern. Everything was set up above. */
1570 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1571 SET_DEST (PATTERN (i3)));
1574 i3_subst_into_i2 = 1;
1575 goto validate_replacement;
1579 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1580 one of those words to another constant, merge them by making a new
1583 && (temp = single_set (i2)) != 0
1584 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1585 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1586 && GET_CODE (SET_DEST (temp)) == REG
1587 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1588 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1589 && GET_CODE (PATTERN (i3)) == SET
1590 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1591 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1592 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1593 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1594 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1596 HOST_WIDE_INT lo, hi;
1598 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1599 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1602 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1603 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1606 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1607 lo = INTVAL (SET_SRC (PATTERN (i3)));
1609 hi = INTVAL (SET_SRC (PATTERN (i3)));
1613 subst_low_cuid = INSN_CUID (i2);
1614 added_sets_2 = added_sets_1 = 0;
1615 i2dest = SET_DEST (temp);
1617 SUBST (SET_SRC (temp),
1618 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1620 newpat = PATTERN (i2);
1621 i3_subst_into_i2 = 1;
1622 goto validate_replacement;
1626 /* If we have no I1 and I2 looks like:
1627 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1629 make up a dummy I1 that is
1632 (set (reg:CC X) (compare:CC Y (const_int 0)))
1634 (We can ignore any trailing CLOBBERs.)
1636 This undoes a previous combination and allows us to match a branch-and-
1639 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1640 && XVECLEN (PATTERN (i2), 0) >= 2
1641 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1642 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1644 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1645 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1646 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1647 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1648 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1649 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1651 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1652 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1657 /* We make I1 with the same INSN_UID as I2. This gives it
1658 the same INSN_CUID for value tracking. Our fake I1 will
1659 never appear in the insn stream so giving it the same INSN_UID
1660 as I2 will not cause a problem. */
1662 subst_prev_insn = i1
1663 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1664 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1667 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1668 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1669 SET_DEST (PATTERN (i1)));
1674 /* Verify that I2 and I1 are valid for combining. */
1675 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1676 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1682 /* Record whether I2DEST is used in I2SRC and similarly for the other
1683 cases. Knowing this will help in register status updating below. */
1684 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1685 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1686 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1688 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1690 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1692 /* Ensure that I3's pattern can be the destination of combines. */
1693 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1694 i1 && i2dest_in_i1src && i1_feeds_i3,
1701 /* See if any of the insns is a MULT operation. Unless one is, we will
1702 reject a combination that is, since it must be slower. Be conservative
1704 if (GET_CODE (i2src) == MULT
1705 || (i1 != 0 && GET_CODE (i1src) == MULT)
1706 || (GET_CODE (PATTERN (i3)) == SET
1707 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1710 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1711 We used to do this EXCEPT in one case: I3 has a post-inc in an
1712 output operand. However, that exception can give rise to insns like
1714 which is a famous insn on the PDP-11 where the value of r3 used as the
1715 source was model-dependent. Avoid this sort of thing. */
1718 if (!(GET_CODE (PATTERN (i3)) == SET
1719 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1720 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1721 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1722 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1723 /* It's not the exception. */
1726 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1727 if (REG_NOTE_KIND (link) == REG_INC
1728 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1730 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1737 /* See if the SETs in I1 or I2 need to be kept around in the merged
1738 instruction: whenever the value set there is still needed past I3.
1739 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1741 For the SET in I1, we have two cases: If I1 and I2 independently
1742 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1743 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1744 in I1 needs to be kept around unless I1DEST dies or is set in either
1745 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1746 I1DEST. If so, we know I1 feeds into I2. */
1748 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1751 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1752 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1754 /* If the set in I2 needs to be kept around, we must make a copy of
1755 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1756 PATTERN (I2), we are only substituting for the original I1DEST, not into
1757 an already-substituted copy. This also prevents making self-referential
1758 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1761 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1762 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1766 i2pat = copy_rtx (i2pat);
1770 /* Substitute in the latest insn for the regs set by the earlier ones. */
1772 maxreg = max_reg_num ();
1776 /* It is possible that the source of I2 or I1 may be performing an
1777 unneeded operation, such as a ZERO_EXTEND of something that is known
1778 to have the high part zero. Handle that case by letting subst look at
1779 the innermost one of them.
1781 Another way to do this would be to have a function that tries to
1782 simplify a single insn instead of merging two or more insns. We don't
1783 do this because of the potential of infinite loops and because
1784 of the potential extra memory required. However, doing it the way
1785 we are is a bit of a kludge and doesn't catch all cases.
1787 But only do this if -fexpensive-optimizations since it slows things down
1788 and doesn't usually win. */
1790 if (flag_expensive_optimizations)
1792 /* Pass pc_rtx so no substitutions are done, just simplifications.
1793 The cases that we are interested in here do not involve the few
1794 cases were is_replaced is checked. */
1797 subst_low_cuid = INSN_CUID (i1);
1798 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1802 subst_low_cuid = INSN_CUID (i2);
1803 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1806 undobuf.previous_undos = undobuf.undos;
1810 /* Many machines that don't use CC0 have insns that can both perform an
1811 arithmetic operation and set the condition code. These operations will
1812 be represented as a PARALLEL with the first element of the vector
1813 being a COMPARE of an arithmetic operation with the constant zero.
1814 The second element of the vector will set some pseudo to the result
1815 of the same arithmetic operation. If we simplify the COMPARE, we won't
1816 match such a pattern and so will generate an extra insn. Here we test
1817 for this case, where both the comparison and the operation result are
1818 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1819 I2SRC. Later we will make the PARALLEL that contains I2. */
1821 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1822 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1823 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1824 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1826 #ifdef EXTRA_CC_MODES
1828 enum machine_mode compare_mode;
1831 newpat = PATTERN (i3);
1832 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1836 #ifdef EXTRA_CC_MODES
1837 /* See if a COMPARE with the operand we substituted in should be done
1838 with the mode that is currently being used. If not, do the same
1839 processing we do in `subst' for a SET; namely, if the destination
1840 is used only once, try to replace it with a register of the proper
1841 mode and also replace the COMPARE. */
1842 if (undobuf.other_insn == 0
1843 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1844 &undobuf.other_insn))
1845 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1847 != GET_MODE (SET_DEST (newpat))))
1849 int regno = REGNO (SET_DEST (newpat));
1850 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1852 if (regno < FIRST_PSEUDO_REGISTER
1853 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1854 && ! REG_USERVAR_P (SET_DEST (newpat))))
1856 if (regno >= FIRST_PSEUDO_REGISTER)
1857 SUBST (regno_reg_rtx[regno], new_dest);
1859 SUBST (SET_DEST (newpat), new_dest);
1860 SUBST (XEXP (*cc_use, 0), new_dest);
1861 SUBST (SET_SRC (newpat),
1862 gen_rtx_combine (COMPARE, compare_mode,
1863 i2src, const0_rtx));
1866 undobuf.other_insn = 0;
1873 n_occurrences = 0; /* `subst' counts here */
1875 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1876 need to make a unique copy of I2SRC each time we substitute it
1877 to avoid self-referential rtl. */
1879 subst_low_cuid = INSN_CUID (i2);
1880 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1881 ! i1_feeds_i3 && i1dest_in_i1src);
1882 undobuf.previous_undos = undobuf.undos;
1884 /* Record whether i2's body now appears within i3's body. */
1885 i2_is_used = n_occurrences;
1888 /* If we already got a failure, don't try to do more. Otherwise,
1889 try to substitute in I1 if we have it. */
1891 if (i1 && GET_CODE (newpat) != CLOBBER)
1893 /* Before we can do this substitution, we must redo the test done
1894 above (see detailed comments there) that ensures that I1DEST
1895 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1897 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1905 subst_low_cuid = INSN_CUID (i1);
1906 newpat = subst (newpat, i1dest, i1src, 0, 0);
1907 undobuf.previous_undos = undobuf.undos;
1910 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1911 to count all the ways that I2SRC and I1SRC can be used. */
1912 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1913 && i2_is_used + added_sets_2 > 1)
1914 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1915 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1917 /* Fail if we tried to make a new register (we used to abort, but there's
1918 really no reason to). */
1919 || max_reg_num () != maxreg
1920 /* Fail if we couldn't do something and have a CLOBBER. */
1921 || GET_CODE (newpat) == CLOBBER
1922 /* Fail if this new pattern is a MULT and we didn't have one before
1923 at the outer level. */
1924 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1931 /* If the actions of the earlier insns must be kept
1932 in addition to substituting them into the latest one,
1933 we must make a new PARALLEL for the latest insn
1934 to hold additional the SETs. */
1936 if (added_sets_1 || added_sets_2)
1940 if (GET_CODE (newpat) == PARALLEL)
1942 rtvec old = XVEC (newpat, 0);
1943 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1944 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1945 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1946 sizeof (old->elem[0]) * old->num_elem);
1951 total_sets = 1 + added_sets_1 + added_sets_2;
1952 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1953 XVECEXP (newpat, 0, 0) = old;
1957 XVECEXP (newpat, 0, --total_sets)
1958 = (GET_CODE (PATTERN (i1)) == PARALLEL
1959 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1963 /* If there is no I1, use I2's body as is. We used to also not do
1964 the subst call below if I2 was substituted into I3,
1965 but that could lose a simplification. */
1967 XVECEXP (newpat, 0, --total_sets) = i2pat;
1969 /* See comment where i2pat is assigned. */
1970 XVECEXP (newpat, 0, --total_sets)
1971 = subst (i2pat, i1dest, i1src, 0, 0);
1975 /* We come here when we are replacing a destination in I2 with the
1976 destination of I3. */
1977 validate_replacement:
1979 /* Note which hard regs this insn has as inputs. */
1980 mark_used_regs_combine (newpat);
1982 /* Is the result of combination a valid instruction? */
1983 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1985 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1986 the second SET's destination is a register that is unused. In that case,
1987 we just need the first SET. This can occur when simplifying a divmod
1988 insn. We *must* test for this case here because the code below that
1989 splits two independent SETs doesn't handle this case correctly when it
1990 updates the register status. Also check the case where the first
1991 SET's destination is unused. That would not cause incorrect code, but
1992 does cause an unneeded insn to remain. */
1994 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1995 && XVECLEN (newpat, 0) == 2
1996 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1997 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1998 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1999 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2000 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2001 && asm_noperands (newpat) < 0)
2003 newpat = XVECEXP (newpat, 0, 0);
2004 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2007 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2008 && XVECLEN (newpat, 0) == 2
2009 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2010 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2011 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2012 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2013 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2014 && asm_noperands (newpat) < 0)
2016 newpat = XVECEXP (newpat, 0, 1);
2017 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2020 /* If we were combining three insns and the result is a simple SET
2021 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2022 insns. There are two ways to do this. It can be split using a
2023 machine-specific method (like when you have an addition of a large
2024 constant) or by combine in the function find_split_point. */
2026 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2027 && asm_noperands (newpat) < 0)
2029 rtx m_split, *split;
2030 rtx ni2dest = i2dest;
2032 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2033 use I2DEST as a scratch register will help. In the latter case,
2034 convert I2DEST to the mode of the source of NEWPAT if we can. */
2036 m_split = split_insns (newpat, i3);
2038 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2039 inputs of NEWPAT. */
2041 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2042 possible to try that as a scratch reg. This would require adding
2043 more code to make it work though. */
2045 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2047 /* If I2DEST is a hard register or the only use of a pseudo,
2048 we can change its mode. */
2049 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2050 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2051 && GET_CODE (i2dest) == REG
2052 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2053 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2054 && ! REG_USERVAR_P (i2dest))))
2055 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2058 m_split = split_insns (gen_rtx_PARALLEL
2060 gen_rtvec (2, newpat,
2061 gen_rtx_CLOBBER (VOIDmode,
2066 if (m_split && GET_CODE (m_split) == SEQUENCE
2067 && XVECLEN (m_split, 0) == 2
2068 && (next_real_insn (i2) == i3
2069 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2073 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2074 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2076 i3set = single_set (XVECEXP (m_split, 0, 1));
2077 i2set = single_set (XVECEXP (m_split, 0, 0));
2079 /* In case we changed the mode of I2DEST, replace it in the
2080 pseudo-register table here. We can't do it above in case this
2081 code doesn't get executed and we do a split the other way. */
2083 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2084 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2086 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2088 /* If I2 or I3 has multiple SETs, we won't know how to track
2089 register status, so don't use these insns. If I2's destination
2090 is used between I2 and I3, we also can't use these insns. */
2092 if (i2_code_number >= 0 && i2set && i3set
2093 && (next_real_insn (i2) == i3
2094 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2095 insn_code_number = recog_for_combine (&newi3pat, i3,
2097 if (insn_code_number >= 0)
2100 /* It is possible that both insns now set the destination of I3.
2101 If so, we must show an extra use of it. */
2103 if (insn_code_number >= 0)
2105 rtx new_i3_dest = SET_DEST (i3set);
2106 rtx new_i2_dest = SET_DEST (i2set);
2108 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2109 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2110 || GET_CODE (new_i3_dest) == SUBREG)
2111 new_i3_dest = XEXP (new_i3_dest, 0);
2113 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2114 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2115 || GET_CODE (new_i2_dest) == SUBREG)
2116 new_i2_dest = XEXP (new_i2_dest, 0);
2118 if (GET_CODE (new_i3_dest) == REG
2119 && GET_CODE (new_i2_dest) == REG
2120 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2121 REG_N_SETS (REGNO (new_i2_dest))++;
2125 /* If we can split it and use I2DEST, go ahead and see if that
2126 helps things be recognized. Verify that none of the registers
2127 are set between I2 and I3. */
2128 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2130 && GET_CODE (i2dest) == REG
2132 /* We need I2DEST in the proper mode. If it is a hard register
2133 or the only use of a pseudo, we can change its mode. */
2134 && (GET_MODE (*split) == GET_MODE (i2dest)
2135 || GET_MODE (*split) == VOIDmode
2136 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2137 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2138 && ! REG_USERVAR_P (i2dest)))
2139 && (next_real_insn (i2) == i3
2140 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2141 /* We can't overwrite I2DEST if its value is still used by
2143 && ! reg_referenced_p (i2dest, newpat))
2145 rtx newdest = i2dest;
2146 enum rtx_code split_code = GET_CODE (*split);
2147 enum machine_mode split_mode = GET_MODE (*split);
2149 /* Get NEWDEST as a register in the proper mode. We have already
2150 validated that we can do this. */
2151 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2153 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2155 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2156 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2159 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2160 an ASHIFT. This can occur if it was inside a PLUS and hence
2161 appeared to be a memory address. This is a kludge. */
2162 if (split_code == MULT
2163 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2164 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2166 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2167 XEXP (*split, 0), GEN_INT (i)));
2168 /* Update split_code because we may not have a multiply
2170 split_code = GET_CODE (*split);
2173 #ifdef INSN_SCHEDULING
2174 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2175 be written as a ZERO_EXTEND. */
2176 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2177 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2181 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2182 SUBST (*split, newdest);
2183 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2185 /* If the split point was a MULT and we didn't have one before,
2186 don't use one now. */
2187 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2188 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2192 /* Check for a case where we loaded from memory in a narrow mode and
2193 then sign extended it, but we need both registers. In that case,
2194 we have a PARALLEL with both loads from the same memory location.
2195 We can split this into a load from memory followed by a register-register
2196 copy. This saves at least one insn, more if register allocation can
2199 We cannot do this if the destination of the second assignment is
2200 a register that we have already assumed is zero-extended. Similarly
2201 for a SUBREG of such a register. */
2203 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2204 && GET_CODE (newpat) == PARALLEL
2205 && XVECLEN (newpat, 0) == 2
2206 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2207 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2208 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2209 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2210 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2211 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2213 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2214 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2215 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2216 (GET_CODE (temp) == REG
2217 && reg_nonzero_bits[REGNO (temp)] != 0
2218 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2219 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2220 && (reg_nonzero_bits[REGNO (temp)]
2221 != GET_MODE_MASK (word_mode))))
2222 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2223 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2224 (GET_CODE (temp) == REG
2225 && reg_nonzero_bits[REGNO (temp)] != 0
2226 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2227 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2228 && (reg_nonzero_bits[REGNO (temp)]
2229 != GET_MODE_MASK (word_mode)))))
2230 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2231 SET_SRC (XVECEXP (newpat, 0, 1)))
2232 && ! find_reg_note (i3, REG_UNUSED,
2233 SET_DEST (XVECEXP (newpat, 0, 0))))
2237 newi2pat = XVECEXP (newpat, 0, 0);
2238 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2239 newpat = XVECEXP (newpat, 0, 1);
2240 SUBST (SET_SRC (newpat),
2241 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2242 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2244 if (i2_code_number >= 0)
2245 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2247 if (insn_code_number >= 0)
2252 /* If we will be able to accept this, we have made a change to the
2253 destination of I3. This can invalidate a LOG_LINKS pointing
2254 to I3. No other part of combine.c makes such a transformation.
2256 The new I3 will have a destination that was previously the
2257 destination of I1 or I2 and which was used in i2 or I3. Call
2258 distribute_links to make a LOG_LINK from the next use of
2259 that destination. */
2261 PATTERN (i3) = newpat;
2262 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2264 /* I3 now uses what used to be its destination and which is
2265 now I2's destination. That means we need a LOG_LINK from
2266 I3 to I2. But we used to have one, so we still will.
2268 However, some later insn might be using I2's dest and have
2269 a LOG_LINK pointing at I3. We must remove this link.
2270 The simplest way to remove the link is to point it at I1,
2271 which we know will be a NOTE. */
2273 for (insn = NEXT_INSN (i3);
2274 insn && (this_basic_block == n_basic_blocks - 1
2275 || insn != BLOCK_HEAD (this_basic_block + 1));
2276 insn = NEXT_INSN (insn))
2278 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2279 && reg_referenced_p (ni2dest, PATTERN (insn)))
2281 for (link = LOG_LINKS (insn); link;
2282 link = XEXP (link, 1))
2283 if (XEXP (link, 0) == i3)
2284 XEXP (link, 0) = i1;
2292 /* Similarly, check for a case where we have a PARALLEL of two independent
2293 SETs but we started with three insns. In this case, we can do the sets
2294 as two separate insns. This case occurs when some SET allows two
2295 other insns to combine, but the destination of that SET is still live. */
2297 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2298 && GET_CODE (newpat) == PARALLEL
2299 && XVECLEN (newpat, 0) == 2
2300 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2301 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2302 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2303 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2304 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2305 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2306 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2308 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2309 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2310 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2311 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2312 XVECEXP (newpat, 0, 0))
2313 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2314 XVECEXP (newpat, 0, 1))
2315 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2316 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2318 /* Normally, it doesn't matter which of the two is done first,
2319 but it does if one references cc0. In that case, it has to
2322 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2324 newi2pat = XVECEXP (newpat, 0, 0);
2325 newpat = XVECEXP (newpat, 0, 1);
2330 newi2pat = XVECEXP (newpat, 0, 1);
2331 newpat = XVECEXP (newpat, 0, 0);
2334 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2336 if (i2_code_number >= 0)
2337 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2340 /* If it still isn't recognized, fail and change things back the way they
2342 if ((insn_code_number < 0
2343 /* Is the result a reasonable ASM_OPERANDS? */
2344 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2350 /* If we had to change another insn, make sure it is valid also. */
2351 if (undobuf.other_insn)
2353 rtx other_pat = PATTERN (undobuf.other_insn);
2354 rtx new_other_notes;
2357 CLEAR_HARD_REG_SET (newpat_used_regs);
2359 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2362 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2368 PATTERN (undobuf.other_insn) = other_pat;
2370 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2371 are still valid. Then add any non-duplicate notes added by
2372 recog_for_combine. */
2373 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2375 next = XEXP (note, 1);
2377 if (REG_NOTE_KIND (note) == REG_UNUSED
2378 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2380 if (GET_CODE (XEXP (note, 0)) == REG)
2381 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2383 remove_note (undobuf.other_insn, note);
2387 for (note = new_other_notes; note; note = XEXP (note, 1))
2388 if (GET_CODE (XEXP (note, 0)) == REG)
2389 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2391 distribute_notes (new_other_notes, undobuf.other_insn,
2392 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2395 /* We now know that we can do this combination. Merge the insns and
2396 update the status of registers and LOG_LINKS. */
2399 rtx i3notes, i2notes, i1notes = 0;
2400 rtx i3links, i2links, i1links = 0;
2403 /* Compute which registers we expect to eliminate. newi2pat may be setting
2404 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2405 same as i3dest, in which case newi2pat may be setting i1dest. */
2406 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2407 || i2dest_in_i2src || i2dest_in_i1src
2409 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2410 || (newi2pat && reg_set_p (i1dest, newi2pat))
2413 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2415 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2416 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2418 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2420 /* Ensure that we do not have something that should not be shared but
2421 occurs multiple times in the new insns. Check this by first
2422 resetting all the `used' flags and then copying anything is shared. */
2424 reset_used_flags (i3notes);
2425 reset_used_flags (i2notes);
2426 reset_used_flags (i1notes);
2427 reset_used_flags (newpat);
2428 reset_used_flags (newi2pat);
2429 if (undobuf.other_insn)
2430 reset_used_flags (PATTERN (undobuf.other_insn));
2432 i3notes = copy_rtx_if_shared (i3notes);
2433 i2notes = copy_rtx_if_shared (i2notes);
2434 i1notes = copy_rtx_if_shared (i1notes);
2435 newpat = copy_rtx_if_shared (newpat);
2436 newi2pat = copy_rtx_if_shared (newi2pat);
2437 if (undobuf.other_insn)
2438 reset_used_flags (PATTERN (undobuf.other_insn));
2440 INSN_CODE (i3) = insn_code_number;
2441 PATTERN (i3) = newpat;
2442 if (undobuf.other_insn)
2443 INSN_CODE (undobuf.other_insn) = other_code_number;
2445 /* We had one special case above where I2 had more than one set and
2446 we replaced a destination of one of those sets with the destination
2447 of I3. In that case, we have to update LOG_LINKS of insns later
2448 in this basic block. Note that this (expensive) case is rare.
2450 Also, in this case, we must pretend that all REG_NOTEs for I2
2451 actually came from I3, so that REG_UNUSED notes from I2 will be
2452 properly handled. */
2454 if (i3_subst_into_i2)
2456 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2458 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2459 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2460 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2461 && ! find_reg_note (i2, REG_UNUSED,
2462 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2463 for (temp = NEXT_INSN (i2);
2464 temp && (this_basic_block == n_basic_blocks - 1
2465 || BLOCK_HEAD (this_basic_block) != temp);
2466 temp = NEXT_INSN (temp))
2467 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2468 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2469 if (XEXP (link, 0) == i2)
2470 XEXP (link, 0) = i3;
2476 while (XEXP (link, 1))
2477 link = XEXP (link, 1);
2478 XEXP (link, 1) = i2notes;
2492 INSN_CODE (i2) = i2_code_number;
2493 PATTERN (i2) = newi2pat;
2497 PUT_CODE (i2, NOTE);
2498 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2499 NOTE_SOURCE_FILE (i2) = 0;
2506 PUT_CODE (i1, NOTE);
2507 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2508 NOTE_SOURCE_FILE (i1) = 0;
2511 /* Get death notes for everything that is now used in either I3 or
2512 I2 and used to die in a previous insn. If we built two new
2513 patterns, move from I1 to I2 then I2 to I3 so that we get the
2514 proper movement on registers that I2 modifies. */
2518 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2519 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2522 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2525 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2527 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2530 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2533 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2536 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2539 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2540 know these are REG_UNUSED and want them to go to the desired insn,
2541 so we always pass it as i3. We have not counted the notes in
2542 reg_n_deaths yet, so we need to do so now. */
2544 if (newi2pat && new_i2_notes)
2546 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2547 if (GET_CODE (XEXP (temp, 0)) == REG)
2548 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2550 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2555 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2556 if (GET_CODE (XEXP (temp, 0)) == REG)
2557 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2559 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2562 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2563 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2564 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2565 in that case, it might delete I2. Similarly for I2 and I1.
2566 Show an additional death due to the REG_DEAD note we make here. If
2567 we discard it in distribute_notes, we will decrement it again. */
2571 if (GET_CODE (i3dest_killed) == REG)
2572 REG_N_DEATHS (REGNO (i3dest_killed))++;
2574 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2575 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2577 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2579 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2581 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2585 if (i2dest_in_i2src)
2587 if (GET_CODE (i2dest) == REG)
2588 REG_N_DEATHS (REGNO (i2dest))++;
2590 if (newi2pat && reg_set_p (i2dest, newi2pat))
2591 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2592 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2594 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2595 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2596 NULL_RTX, NULL_RTX);
2599 if (i1dest_in_i1src)
2601 if (GET_CODE (i1dest) == REG)
2602 REG_N_DEATHS (REGNO (i1dest))++;
2604 if (newi2pat && reg_set_p (i1dest, newi2pat))
2605 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2606 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2608 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2609 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2610 NULL_RTX, NULL_RTX);
2613 distribute_links (i3links);
2614 distribute_links (i2links);
2615 distribute_links (i1links);
2617 if (GET_CODE (i2dest) == REG)
2620 rtx i2_insn = 0, i2_val = 0, set;
2622 /* The insn that used to set this register doesn't exist, and
2623 this life of the register may not exist either. See if one of
2624 I3's links points to an insn that sets I2DEST. If it does,
2625 that is now the last known value for I2DEST. If we don't update
2626 this and I2 set the register to a value that depended on its old
2627 contents, we will get confused. If this insn is used, thing
2628 will be set correctly in combine_instructions. */
2630 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2631 if ((set = single_set (XEXP (link, 0))) != 0
2632 && rtx_equal_p (i2dest, SET_DEST (set)))
2633 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2635 record_value_for_reg (i2dest, i2_insn, i2_val);
2637 /* If the reg formerly set in I2 died only once and that was in I3,
2638 zero its use count so it won't make `reload' do any work. */
2640 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2641 && ! i2dest_in_i2src)
2643 regno = REGNO (i2dest);
2644 REG_N_SETS (regno)--;
2648 if (i1 && GET_CODE (i1dest) == REG)
2651 rtx i1_insn = 0, i1_val = 0, set;
2653 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2654 if ((set = single_set (XEXP (link, 0))) != 0
2655 && rtx_equal_p (i1dest, SET_DEST (set)))
2656 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2658 record_value_for_reg (i1dest, i1_insn, i1_val);
2660 regno = REGNO (i1dest);
2661 if (! added_sets_1 && ! i1dest_in_i1src)
2663 REG_N_SETS (regno)--;
2667 /* Update reg_nonzero_bits et al for any changes that may have been made
2670 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2672 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2674 /* If I3 is now an unconditional jump, ensure that it has a
2675 BARRIER following it since it may have initially been a
2676 conditional jump. It may also be the last nonnote insn. */
2678 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2679 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2680 || GET_CODE (temp) != BARRIER))
2681 emit_barrier_after (i3);
2684 combine_successes++;
2687 /* Clear this here, so that subsequent get_last_value calls are not
2689 subst_prev_insn = NULL_RTX;
2691 if (added_links_insn
2692 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2693 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2694 return added_links_insn;
2696 return newi2pat ? i2 : i3;
2699 /* Undo all the modifications recorded in undobuf. */
2704 struct undo *undo, *next;
2706 for (undo = undobuf.undos; undo; undo = next)
2710 *undo->where.i = undo->old_contents.i;
2712 *undo->where.r = undo->old_contents.r;
2714 undo->next = undobuf.frees;
2715 undobuf.frees = undo;
2718 obfree (undobuf.storage);
2719 undobuf.undos = undobuf.previous_undos = 0;
2721 /* Clear this here, so that subsequent get_last_value calls are not
2723 subst_prev_insn = NULL_RTX;
2726 /* We've committed to accepting the changes we made. Move all
2727 of the undos to the free list. */
2732 struct undo *undo, *next;
2734 for (undo = undobuf.undos; undo; undo = next)
2737 undo->next = undobuf.frees;
2738 undobuf.frees = undo;
2740 undobuf.undos = undobuf.previous_undos = 0;
2744 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2745 where we have an arithmetic expression and return that point. LOC will
2748 try_combine will call this function to see if an insn can be split into
2752 find_split_point (loc, insn)
2757 enum rtx_code code = GET_CODE (x);
2759 int len = 0, pos = 0, unsignedp = 0;
2760 rtx inner = NULL_RTX;
2762 /* First special-case some codes. */
2766 #ifdef INSN_SCHEDULING
2767 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2769 if (GET_CODE (SUBREG_REG (x)) == MEM)
2772 return find_split_point (&SUBREG_REG (x), insn);
2776 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2777 using LO_SUM and HIGH. */
2778 if (GET_CODE (XEXP (x, 0)) == CONST
2779 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2782 gen_rtx_combine (LO_SUM, Pmode,
2783 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2785 return &XEXP (XEXP (x, 0), 0);
2789 /* If we have a PLUS whose second operand is a constant and the
2790 address is not valid, perhaps will can split it up using
2791 the machine-specific way to split large constants. We use
2792 the first pseudo-reg (one of the virtual regs) as a placeholder;
2793 it will not remain in the result. */
2794 if (GET_CODE (XEXP (x, 0)) == PLUS
2795 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2796 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2798 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2799 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2802 /* This should have produced two insns, each of which sets our
2803 placeholder. If the source of the second is a valid address,
2804 we can make put both sources together and make a split point
2807 if (seq && XVECLEN (seq, 0) == 2
2808 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2809 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2810 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2811 && ! reg_mentioned_p (reg,
2812 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2813 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2814 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2815 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2816 && memory_address_p (GET_MODE (x),
2817 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2819 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2820 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2822 /* Replace the placeholder in SRC2 with SRC1. If we can
2823 find where in SRC2 it was placed, that can become our
2824 split point and we can replace this address with SRC2.
2825 Just try two obvious places. */
2827 src2 = replace_rtx (src2, reg, src1);
2829 if (XEXP (src2, 0) == src1)
2830 split = &XEXP (src2, 0);
2831 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2832 && XEXP (XEXP (src2, 0), 0) == src1)
2833 split = &XEXP (XEXP (src2, 0), 0);
2837 SUBST (XEXP (x, 0), src2);
2842 /* If that didn't work, perhaps the first operand is complex and
2843 needs to be computed separately, so make a split point there.
2844 This will occur on machines that just support REG + CONST
2845 and have a constant moved through some previous computation. */
2847 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2848 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2849 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2851 return &XEXP (XEXP (x, 0), 0);
2857 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2858 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2859 we need to put the operand into a register. So split at that
2862 if (SET_DEST (x) == cc0_rtx
2863 && GET_CODE (SET_SRC (x)) != COMPARE
2864 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2865 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2866 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2867 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2868 return &SET_SRC (x);
2871 /* See if we can split SET_SRC as it stands. */
2872 split = find_split_point (&SET_SRC (x), insn);
2873 if (split && split != &SET_SRC (x))
2876 /* See if we can split SET_DEST as it stands. */
2877 split = find_split_point (&SET_DEST (x), insn);
2878 if (split && split != &SET_DEST (x))
2881 /* See if this is a bitfield assignment with everything constant. If
2882 so, this is an IOR of an AND, so split it into that. */
2883 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2884 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2885 <= HOST_BITS_PER_WIDE_INT)
2886 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2887 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2888 && GET_CODE (SET_SRC (x)) == CONST_INT
2889 && ((INTVAL (XEXP (SET_DEST (x), 1))
2890 + INTVAL (XEXP (SET_DEST (x), 2)))
2891 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2892 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2894 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2895 int len = INTVAL (XEXP (SET_DEST (x), 1));
2896 int src = INTVAL (SET_SRC (x));
2897 rtx dest = XEXP (SET_DEST (x), 0);
2898 enum machine_mode mode = GET_MODE (dest);
2899 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2901 if (BITS_BIG_ENDIAN)
2902 pos = GET_MODE_BITSIZE (mode) - len - pos;
2904 if ((unsigned HOST_WIDE_INT) src == mask)
2906 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2909 gen_binary (IOR, mode,
2910 gen_binary (AND, mode, dest,
2911 GEN_INT (~ (mask << pos)
2912 & GET_MODE_MASK (mode))),
2913 GEN_INT (src << pos)));
2915 SUBST (SET_DEST (x), dest);
2917 split = find_split_point (&SET_SRC (x), insn);
2918 if (split && split != &SET_SRC (x))
2922 /* Otherwise, see if this is an operation that we can split into two.
2923 If so, try to split that. */
2924 code = GET_CODE (SET_SRC (x));
2929 /* If we are AND'ing with a large constant that is only a single
2930 bit and the result is only being used in a context where we
2931 need to know if it is zero or non-zero, replace it with a bit
2932 extraction. This will avoid the large constant, which might
2933 have taken more than one insn to make. If the constant were
2934 not a valid argument to the AND but took only one insn to make,
2935 this is no worse, but if it took more than one insn, it will
2938 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2939 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2940 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2941 && GET_CODE (SET_DEST (x)) == REG
2942 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2943 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2944 && XEXP (*split, 0) == SET_DEST (x)
2945 && XEXP (*split, 1) == const0_rtx)
2947 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2948 XEXP (SET_SRC (x), 0),
2949 pos, NULL_RTX, 1, 1, 0, 0);
2950 if (extraction != 0)
2952 SUBST (SET_SRC (x), extraction);
2953 return find_split_point (loc, insn);
2959 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2960 is known to be on, this can be converted into a NEG of a shift. */
2961 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2962 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2963 && 1 <= (pos = exact_log2
2964 (nonzero_bits (XEXP (SET_SRC (x), 0),
2965 GET_MODE (XEXP (SET_SRC (x), 0))))))
2967 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2970 gen_rtx_combine (NEG, mode,
2971 gen_rtx_combine (LSHIFTRT, mode,
2972 XEXP (SET_SRC (x), 0),
2975 split = find_split_point (&SET_SRC (x), insn);
2976 if (split && split != &SET_SRC (x))
2982 inner = XEXP (SET_SRC (x), 0);
2984 /* We can't optimize if either mode is a partial integer
2985 mode as we don't know how many bits are significant
2987 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2988 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2992 len = GET_MODE_BITSIZE (GET_MODE (inner));
2998 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2999 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3001 inner = XEXP (SET_SRC (x), 0);
3002 len = INTVAL (XEXP (SET_SRC (x), 1));
3003 pos = INTVAL (XEXP (SET_SRC (x), 2));
3005 if (BITS_BIG_ENDIAN)
3006 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3007 unsignedp = (code == ZERO_EXTRACT);
3015 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3017 enum machine_mode mode = GET_MODE (SET_SRC (x));
3019 /* For unsigned, we have a choice of a shift followed by an
3020 AND or two shifts. Use two shifts for field sizes where the
3021 constant might be too large. We assume here that we can
3022 always at least get 8-bit constants in an AND insn, which is
3023 true for every current RISC. */
3025 if (unsignedp && len <= 8)
3030 gen_rtx_combine (LSHIFTRT, mode,
3031 gen_lowpart_for_combine (mode, inner),
3033 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3035 split = find_split_point (&SET_SRC (x), insn);
3036 if (split && split != &SET_SRC (x))
3043 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3044 gen_rtx_combine (ASHIFT, mode,
3045 gen_lowpart_for_combine (mode, inner),
3046 GEN_INT (GET_MODE_BITSIZE (mode)
3048 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3050 split = find_split_point (&SET_SRC (x), insn);
3051 if (split && split != &SET_SRC (x))
3056 /* See if this is a simple operation with a constant as the second
3057 operand. It might be that this constant is out of range and hence
3058 could be used as a split point. */
3059 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3060 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3061 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3062 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3063 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3064 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3065 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3067 return &XEXP (SET_SRC (x), 1);
3069 /* Finally, see if this is a simple operation with its first operand
3070 not in a register. The operation might require this operand in a
3071 register, so return it as a split point. We can always do this
3072 because if the first operand were another operation, we would have
3073 already found it as a split point. */
3074 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3075 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3076 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3077 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3078 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3079 return &XEXP (SET_SRC (x), 0);
3085 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3086 it is better to write this as (not (ior A B)) so we can split it.
3087 Similarly for IOR. */
3088 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3091 gen_rtx_combine (NOT, GET_MODE (x),
3092 gen_rtx_combine (code == IOR ? AND : IOR,
3094 XEXP (XEXP (x, 0), 0),
3095 XEXP (XEXP (x, 1), 0))));
3096 return find_split_point (loc, insn);
3099 /* Many RISC machines have a large set of logical insns. If the
3100 second operand is a NOT, put it first so we will try to split the
3101 other operand first. */
3102 if (GET_CODE (XEXP (x, 1)) == NOT)
3104 rtx tem = XEXP (x, 0);
3105 SUBST (XEXP (x, 0), XEXP (x, 1));
3106 SUBST (XEXP (x, 1), tem);
3114 /* Otherwise, select our actions depending on our rtx class. */
3115 switch (GET_RTX_CLASS (code))
3117 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3119 split = find_split_point (&XEXP (x, 2), insn);
3122 /* ... fall through ... */
3126 split = find_split_point (&XEXP (x, 1), insn);
3129 /* ... fall through ... */
3131 /* Some machines have (and (shift ...) ...) insns. If X is not
3132 an AND, but XEXP (X, 0) is, use it as our split point. */
3133 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3134 return &XEXP (x, 0);
3136 split = find_split_point (&XEXP (x, 0), insn);
3142 /* Otherwise, we don't have a split point. */
3146 /* Throughout X, replace FROM with TO, and return the result.
3147 The result is TO if X is FROM;
3148 otherwise the result is X, but its contents may have been modified.
3149 If they were modified, a record was made in undobuf so that
3150 undo_all will (among other things) return X to its original state.
3152 If the number of changes necessary is too much to record to undo,
3153 the excess changes are not made, so the result is invalid.
3154 The changes already made can still be undone.
3155 undobuf.num_undo is incremented for such changes, so by testing that
3156 the caller can tell whether the result is valid.
3158 `n_occurrences' is incremented each time FROM is replaced.
3160 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3162 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3163 by copying if `n_occurrences' is non-zero. */
3166 subst (x, from, to, in_dest, unique_copy)
3167 register rtx x, from, to;
3171 register enum rtx_code code = GET_CODE (x);
3172 enum machine_mode op0_mode = VOIDmode;
3173 register const char *fmt;
3174 register int len, i;
3177 /* Two expressions are equal if they are identical copies of a shared
3178 RTX or if they are both registers with the same register number
3181 #define COMBINE_RTX_EQUAL_P(X,Y) \
3183 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3184 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3186 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3189 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3192 /* If X and FROM are the same register but different modes, they will
3193 not have been seen as equal above. However, flow.c will make a
3194 LOG_LINKS entry for that case. If we do nothing, we will try to
3195 rerecognize our original insn and, when it succeeds, we will
3196 delete the feeding insn, which is incorrect.
3198 So force this insn not to match in this (rare) case. */
3199 if (! in_dest && code == REG && GET_CODE (from) == REG
3200 && REGNO (x) == REGNO (from))
3201 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3203 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3204 of which may contain things that can be combined. */
3205 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3208 /* It is possible to have a subexpression appear twice in the insn.
3209 Suppose that FROM is a register that appears within TO.
3210 Then, after that subexpression has been scanned once by `subst',
3211 the second time it is scanned, TO may be found. If we were
3212 to scan TO here, we would find FROM within it and create a
3213 self-referent rtl structure which is completely wrong. */
3214 if (COMBINE_RTX_EQUAL_P (x, to))
3217 /* Parallel asm_operands need special attention because all of the
3218 inputs are shared across the arms. Furthermore, unsharing the
3219 rtl results in recognition failures. Failure to handle this case
3220 specially can result in circular rtl.
3222 Solve this by doing a normal pass across the first entry of the
3223 parallel, and only processing the SET_DESTs of the subsequent
3226 if (code == PARALLEL
3227 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3228 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3230 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3232 /* If this substitution failed, this whole thing fails. */
3233 if (GET_CODE (new) == CLOBBER
3234 && XEXP (new, 0) == const0_rtx)
3237 SUBST (XVECEXP (x, 0, 0), new);
3239 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3241 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3243 if (GET_CODE (dest) != REG
3244 && GET_CODE (dest) != CC0
3245 && GET_CODE (dest) != PC)
3247 new = subst (dest, from, to, 0, unique_copy);
3249 /* If this substitution failed, this whole thing fails. */
3250 if (GET_CODE (new) == CLOBBER
3251 && XEXP (new, 0) == const0_rtx)
3254 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3260 len = GET_RTX_LENGTH (code);
3261 fmt = GET_RTX_FORMAT (code);
3263 /* We don't need to process a SET_DEST that is a register, CC0,
3264 or PC, so set up to skip this common case. All other cases
3265 where we want to suppress replacing something inside a
3266 SET_SRC are handled via the IN_DEST operand. */
3268 && (GET_CODE (SET_DEST (x)) == REG
3269 || GET_CODE (SET_DEST (x)) == CC0
3270 || GET_CODE (SET_DEST (x)) == PC))
3273 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3276 op0_mode = GET_MODE (XEXP (x, 0));
3278 for (i = 0; i < len; i++)
3283 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3285 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3287 new = (unique_copy && n_occurrences
3288 ? copy_rtx (to) : to);
3293 new = subst (XVECEXP (x, i, j), from, to, 0,
3296 /* If this substitution failed, this whole thing
3298 if (GET_CODE (new) == CLOBBER
3299 && XEXP (new, 0) == const0_rtx)
3303 SUBST (XVECEXP (x, i, j), new);
3306 else if (fmt[i] == 'e')
3308 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3310 /* In general, don't install a subreg involving two
3311 modes not tieable. It can worsen register
3312 allocation, and can even make invalid reload
3313 insns, since the reg inside may need to be copied
3314 from in the outside mode, and that may be invalid
3315 if it is an fp reg copied in integer mode.
3317 We allow two exceptions to this: It is valid if
3318 it is inside another SUBREG and the mode of that
3319 SUBREG and the mode of the inside of TO is
3320 tieable and it is valid if X is a SET that copies
3323 if (GET_CODE (to) == SUBREG
3324 && ! MODES_TIEABLE_P (GET_MODE (to),
3325 GET_MODE (SUBREG_REG (to)))
3326 && ! (code == SUBREG
3327 && MODES_TIEABLE_P (GET_MODE (x),
3328 GET_MODE (SUBREG_REG (to))))
3330 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3333 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3335 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3339 /* If we are in a SET_DEST, suppress most cases unless we
3340 have gone inside a MEM, in which case we want to
3341 simplify the address. We assume here that things that
3342 are actually part of the destination have their inner
3343 parts in the first expression. This is true for SUBREG,
3344 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3345 things aside from REG and MEM that should appear in a
3347 new = subst (XEXP (x, i), from, to,
3349 && (code == SUBREG || code == STRICT_LOW_PART
3350 || code == ZERO_EXTRACT))
3352 && i == 0), unique_copy);
3354 /* If we found that we will have to reject this combination,
3355 indicate that by returning the CLOBBER ourselves, rather than
3356 an expression containing it. This will speed things up as
3357 well as prevent accidents where two CLOBBERs are considered
3358 to be equal, thus producing an incorrect simplification. */
3360 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3363 SUBST (XEXP (x, i), new);
3368 /* Try to simplify X. If the simplification changed the code, it is likely
3369 that further simplification will help, so loop, but limit the number
3370 of repetitions that will be performed. */
3372 for (i = 0; i < 4; i++)
3374 /* If X is sufficiently simple, don't bother trying to do anything
3376 if (code != CONST_INT && code != REG && code != CLOBBER)
3377 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3379 if (GET_CODE (x) == code)
3382 code = GET_CODE (x);
3384 /* We no longer know the original mode of operand 0 since we
3385 have changed the form of X) */
3386 op0_mode = VOIDmode;
3392 /* Simplify X, a piece of RTL. We just operate on the expression at the
3393 outer level; call `subst' to simplify recursively. Return the new
3396 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3397 will be the iteration even if an expression with a code different from
3398 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3401 combine_simplify_rtx (x, op0_mode, last, in_dest)
3403 enum machine_mode op0_mode;
3407 enum rtx_code code = GET_CODE (x);
3408 enum machine_mode mode = GET_MODE (x);
3412 /* If this is a commutative operation, put a constant last and a complex
3413 expression first. We don't need to do this for comparisons here. */
3414 if (GET_RTX_CLASS (code) == 'c'
3415 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3416 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3417 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3418 || (GET_CODE (XEXP (x, 0)) == SUBREG
3419 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3420 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3423 SUBST (XEXP (x, 0), XEXP (x, 1));
3424 SUBST (XEXP (x, 1), temp);
3427 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3428 sign extension of a PLUS with a constant, reverse the order of the sign
3429 extension and the addition. Note that this not the same as the original
3430 code, but overflow is undefined for signed values. Also note that the
3431 PLUS will have been partially moved "inside" the sign-extension, so that
3432 the first operand of X will really look like:
3433 (ashiftrt (plus (ashift A C4) C5) C4).
3435 (plus (ashiftrt (ashift A C4) C2) C4)
3436 and replace the first operand of X with that expression. Later parts
3437 of this function may simplify the expression further.
3439 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3440 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3441 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3443 We do this to simplify address expressions. */
3445 if ((code == PLUS || code == MINUS || code == MULT)
3446 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3447 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3448 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3449 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3450 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3451 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3452 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3453 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3454 XEXP (XEXP (XEXP (x, 0), 0), 1),
3455 XEXP (XEXP (x, 0), 1))) != 0)
3458 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3459 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3460 INTVAL (XEXP (XEXP (x, 0), 1)));
3462 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3463 INTVAL (XEXP (XEXP (x, 0), 1)));
3465 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3468 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3469 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3470 things. Check for cases where both arms are testing the same
3473 Don't do anything if all operands are very simple. */
3475 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3476 || GET_RTX_CLASS (code) == '<')
3477 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3478 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3479 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3481 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3482 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3483 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3485 || (GET_RTX_CLASS (code) == '1'
3486 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3487 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3488 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3491 rtx cond, true, false;
3493 cond = if_then_else_cond (x, &true, &false);
3495 /* If everything is a comparison, what we have is highly unlikely
3496 to be simpler, so don't use it. */
3497 && ! (GET_RTX_CLASS (code) == '<'
3498 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3499 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3501 rtx cop1 = const0_rtx;
3502 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3504 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3507 /* Simplify the alternative arms; this may collapse the true and
3508 false arms to store-flag values. */
3509 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3510 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3512 /* Restarting if we generate a store-flag expression will cause
3513 us to loop. Just drop through in this case. */
3515 /* If the result values are STORE_FLAG_VALUE and zero, we can
3516 just make the comparison operation. */
3517 if (true == const_true_rtx && false == const0_rtx)
3518 x = gen_binary (cond_code, mode, cond, cop1);
3519 else if (true == const0_rtx && false == const_true_rtx)
3520 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3522 /* Likewise, we can make the negate of a comparison operation
3523 if the result values are - STORE_FLAG_VALUE and zero. */
3524 else if (GET_CODE (true) == CONST_INT
3525 && INTVAL (true) == - STORE_FLAG_VALUE
3526 && false == const0_rtx)
3527 x = gen_unary (NEG, mode, mode,
3528 gen_binary (cond_code, mode, cond, cop1));
3529 else if (GET_CODE (false) == CONST_INT
3530 && INTVAL (false) == - STORE_FLAG_VALUE
3531 && true == const0_rtx)
3532 x = gen_unary (NEG, mode, mode,
3533 gen_binary (reverse_condition (cond_code),
3536 return gen_rtx_IF_THEN_ELSE (mode,
3537 gen_binary (cond_code, VOIDmode,
3541 code = GET_CODE (x);
3542 op0_mode = VOIDmode;
3546 /* Try to fold this expression in case we have constants that weren't
3549 switch (GET_RTX_CLASS (code))
3552 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3555 temp = simplify_relational_operation (code, op0_mode,
3556 XEXP (x, 0), XEXP (x, 1));
3557 #ifdef FLOAT_STORE_FLAG_VALUE
3558 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3560 if (temp == const0_rtx)
3561 temp = CONST0_RTX (mode);
3563 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3569 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3573 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3574 XEXP (x, 1), XEXP (x, 2));
3579 x = temp, code = GET_CODE (temp);
3581 /* First see if we can apply the inverse distributive law. */
3582 if (code == PLUS || code == MINUS
3583 || code == AND || code == IOR || code == XOR)
3585 x = apply_distributive_law (x);
3586 code = GET_CODE (x);
3589 /* If CODE is an associative operation not otherwise handled, see if we
3590 can associate some operands. This can win if they are constants or
3591 if they are logically related (i.e. (a & b) & a. */
3592 if ((code == PLUS || code == MINUS
3593 || code == MULT || code == AND || code == IOR || code == XOR
3594 || code == DIV || code == UDIV
3595 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3596 && INTEGRAL_MODE_P (mode))
3598 if (GET_CODE (XEXP (x, 0)) == code)
3600 rtx other = XEXP (XEXP (x, 0), 0);
3601 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3602 rtx inner_op1 = XEXP (x, 1);
3605 /* Make sure we pass the constant operand if any as the second
3606 one if this is a commutative operation. */
3607 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3609 rtx tem = inner_op0;
3610 inner_op0 = inner_op1;
3613 inner = simplify_binary_operation (code == MINUS ? PLUS
3614 : code == DIV ? MULT
3615 : code == UDIV ? MULT
3617 mode, inner_op0, inner_op1);
3619 /* For commutative operations, try the other pair if that one
3621 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3623 other = XEXP (XEXP (x, 0), 1);
3624 inner = simplify_binary_operation (code, mode,
3625 XEXP (XEXP (x, 0), 0),
3630 return gen_binary (code, mode, other, inner);
3634 /* A little bit of algebraic simplification here. */
3638 /* Ensure that our address has any ASHIFTs converted to MULT in case
3639 address-recognizing predicates are called later. */
3640 temp = make_compound_operation (XEXP (x, 0), MEM);
3641 SUBST (XEXP (x, 0), temp);
3645 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3646 is paradoxical. If we can't do that safely, then it becomes
3647 something nonsensical so that this combination won't take place. */
3649 if (GET_CODE (SUBREG_REG (x)) == MEM
3650 && (GET_MODE_SIZE (mode)
3651 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3653 rtx inner = SUBREG_REG (x);
3654 int endian_offset = 0;
3655 /* Don't change the mode of the MEM
3656 if that would change the meaning of the address. */
3657 if (MEM_VOLATILE_P (SUBREG_REG (x))
3658 || mode_dependent_address_p (XEXP (inner, 0)))
3659 return gen_rtx_CLOBBER (mode, const0_rtx);
3661 if (BYTES_BIG_ENDIAN)
3663 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3664 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3665 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3666 endian_offset -= (UNITS_PER_WORD
3667 - GET_MODE_SIZE (GET_MODE (inner)));
3669 /* Note if the plus_constant doesn't make a valid address
3670 then this combination won't be accepted. */
3671 x = gen_rtx_MEM (mode,
3672 plus_constant (XEXP (inner, 0),
3673 (SUBREG_WORD (x) * UNITS_PER_WORD
3675 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3676 MEM_COPY_ATTRIBUTES (x, inner);
3680 /* If we are in a SET_DEST, these other cases can't apply. */
3684 /* Changing mode twice with SUBREG => just change it once,
3685 or not at all if changing back to starting mode. */
3686 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3688 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3689 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3690 return SUBREG_REG (SUBREG_REG (x));
3692 SUBST_INT (SUBREG_WORD (x),
3693 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3694 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3697 /* SUBREG of a hard register => just change the register number
3698 and/or mode. If the hard register is not valid in that mode,
3699 suppress this combination. If the hard register is the stack,
3700 frame, or argument pointer, leave this as a SUBREG. */
3702 if (GET_CODE (SUBREG_REG (x)) == REG
3703 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3704 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3705 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3706 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3708 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3709 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3711 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3713 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3715 return gen_rtx_REG (mode,
3716 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3718 return gen_rtx_CLOBBER (mode, const0_rtx);
3721 /* For a constant, try to pick up the part we want. Handle a full
3722 word and low-order part. Only do this if we are narrowing
3723 the constant; if it is being widened, we have no idea what
3724 the extra bits will have been set to. */
3726 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3727 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3728 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3729 && GET_MODE_CLASS (mode) == MODE_INT)
3731 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3737 /* If we want a subreg of a constant, at offset 0,
3738 take the low bits. On a little-endian machine, that's
3739 always valid. On a big-endian machine, it's valid
3740 only if the constant's mode fits in one word. Note that we
3741 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3742 if (CONSTANT_P (SUBREG_REG (x))
3743 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3744 || ! WORDS_BIG_ENDIAN)
3745 ? SUBREG_WORD (x) == 0
3747 == ((GET_MODE_SIZE (op0_mode)
3748 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3750 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3751 && (! WORDS_BIG_ENDIAN
3752 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3753 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3755 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3756 since we are saying that the high bits don't matter. */
3757 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3758 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3760 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3761 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3762 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3763 return SUBREG_REG (x);
3766 /* Note that we cannot do any narrowing for non-constants since
3767 we might have been counting on using the fact that some bits were
3768 zero. We now do this in the SET. */
3773 /* (not (plus X -1)) can become (neg X). */
3774 if (GET_CODE (XEXP (x, 0)) == PLUS
3775 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3776 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3778 /* Similarly, (not (neg X)) is (plus X -1). */
3779 if (GET_CODE (XEXP (x, 0)) == NEG)
3780 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3783 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3784 if (GET_CODE (XEXP (x, 0)) == XOR
3785 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3786 && (temp = simplify_unary_operation (NOT, mode,
3787 XEXP (XEXP (x, 0), 1),
3789 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3791 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3792 other than 1, but that is not valid. We could do a similar
3793 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3794 but this doesn't seem common enough to bother with. */
3795 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3796 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3797 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3798 XEXP (XEXP (x, 0), 1));
3800 if (GET_CODE (XEXP (x, 0)) == SUBREG
3801 && subreg_lowpart_p (XEXP (x, 0))
3802 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3803 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3804 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3805 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3807 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3809 x = gen_rtx_ROTATE (inner_mode,
3810 gen_unary (NOT, inner_mode, inner_mode,
3812 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3813 return gen_lowpart_for_combine (mode, x);
3816 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3817 reversing the comparison code if valid. */
3818 if (STORE_FLAG_VALUE == -1
3819 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3820 && reversible_comparison_p (XEXP (x, 0)))
3821 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3822 mode, XEXP (XEXP (x, 0), 0),
3823 XEXP (XEXP (x, 0), 1));
3825 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3826 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3827 perform the above simplification. */
3829 if (STORE_FLAG_VALUE == -1
3830 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3831 && XEXP (x, 1) == const1_rtx
3832 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3833 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3834 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3836 /* Apply De Morgan's laws to reduce number of patterns for machines
3837 with negating logical insns (and-not, nand, etc.). If result has
3838 only one NOT, put it first, since that is how the patterns are
3841 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3843 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3845 if (GET_CODE (in1) == NOT)
3846 in1 = XEXP (in1, 0);
3848 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3850 if (GET_CODE (in2) == NOT)
3851 in2 = XEXP (in2, 0);
3852 else if (GET_CODE (in2) == CONST_INT
3853 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3854 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3856 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3858 if (GET_CODE (in2) == NOT)
3861 in2 = in1; in1 = tem;
3864 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3870 /* (neg (plus X 1)) can become (not X). */
3871 if (GET_CODE (XEXP (x, 0)) == PLUS
3872 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3873 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3875 /* Similarly, (neg (not X)) is (plus X 1). */
3876 if (GET_CODE (XEXP (x, 0)) == NOT)
3877 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3879 /* (neg (minus X Y)) can become (minus Y X). */
3880 if (GET_CODE (XEXP (x, 0)) == MINUS
3881 && (! FLOAT_MODE_P (mode)
3882 /* x-y != -(y-x) with IEEE floating point. */
3883 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3885 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3886 XEXP (XEXP (x, 0), 0));
3888 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3889 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3890 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3891 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3893 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3894 if we can then eliminate the NEG (e.g.,
3895 if the operand is a constant). */
3897 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3899 temp = simplify_unary_operation (NEG, mode,
3900 XEXP (XEXP (x, 0), 0), mode);
3903 SUBST (XEXP (XEXP (x, 0), 0), temp);
3908 temp = expand_compound_operation (XEXP (x, 0));
3910 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3911 replaced by (lshiftrt X C). This will convert
3912 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3914 if (GET_CODE (temp) == ASHIFTRT
3915 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3916 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3917 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3918 INTVAL (XEXP (temp, 1)));
3920 /* If X has only a single bit that might be nonzero, say, bit I, convert
3921 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3922 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3923 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3924 or a SUBREG of one since we'd be making the expression more
3925 complex if it was just a register. */
3927 if (GET_CODE (temp) != REG
3928 && ! (GET_CODE (temp) == SUBREG
3929 && GET_CODE (SUBREG_REG (temp)) == REG)
3930 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3932 rtx temp1 = simplify_shift_const
3933 (NULL_RTX, ASHIFTRT, mode,
3934 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3935 GET_MODE_BITSIZE (mode) - 1 - i),
3936 GET_MODE_BITSIZE (mode) - 1 - i);
3938 /* If all we did was surround TEMP with the two shifts, we
3939 haven't improved anything, so don't use it. Otherwise,
3940 we are better off with TEMP1. */
3941 if (GET_CODE (temp1) != ASHIFTRT
3942 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3943 || XEXP (XEXP (temp1, 0), 0) != temp)
3949 /* We can't handle truncation to a partial integer mode here
3950 because we don't know the real bitsize of the partial
3952 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3955 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3956 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3957 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3959 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3960 GET_MODE_MASK (mode), NULL_RTX, 0));
3962 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3963 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3964 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3965 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3966 return XEXP (XEXP (x, 0), 0);
3968 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3969 (OP:SI foo:SI) if OP is NEG or ABS. */
3970 if ((GET_CODE (XEXP (x, 0)) == ABS
3971 || GET_CODE (XEXP (x, 0)) == NEG)
3972 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3973 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3974 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3975 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3976 XEXP (XEXP (XEXP (x, 0), 0), 0));
3978 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3980 if (GET_CODE (XEXP (x, 0)) == SUBREG
3981 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3982 && subreg_lowpart_p (XEXP (x, 0)))
3983 return SUBREG_REG (XEXP (x, 0));
3985 /* If we know that the value is already truncated, we can
3986 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3987 is nonzero for the corresponding modes. But don't do this
3988 for an (LSHIFTRT (MULT ...)) since this will cause problems
3989 with the umulXi3_highpart patterns. */
3990 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3991 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3992 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3993 >= GET_MODE_BITSIZE (mode) + 1
3994 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
3995 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
3996 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3998 /* A truncate of a comparison can be replaced with a subreg if
3999 STORE_FLAG_VALUE permits. This is like the previous test,
4000 but it works even if the comparison is done in a mode larger
4001 than HOST_BITS_PER_WIDE_INT. */
4002 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4003 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4004 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4005 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4007 /* Similarly, a truncate of a register whose value is a
4008 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4010 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4011 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4012 && (temp = get_last_value (XEXP (x, 0)))
4013 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4014 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4018 case FLOAT_TRUNCATE:
4019 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4020 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4021 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4022 return XEXP (XEXP (x, 0), 0);
4024 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4025 (OP:SF foo:SF) if OP is NEG or ABS. */
4026 if ((GET_CODE (XEXP (x, 0)) == ABS
4027 || GET_CODE (XEXP (x, 0)) == NEG)
4028 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4029 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4030 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4031 XEXP (XEXP (XEXP (x, 0), 0), 0));
4033 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4034 is (float_truncate:SF x). */
4035 if (GET_CODE (XEXP (x, 0)) == SUBREG
4036 && subreg_lowpart_p (XEXP (x, 0))
4037 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4038 return SUBREG_REG (XEXP (x, 0));
4043 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4044 using cc0, in which case we want to leave it as a COMPARE
4045 so we can distinguish it from a register-register-copy. */
4046 if (XEXP (x, 1) == const0_rtx)
4049 /* In IEEE floating point, x-0 is not the same as x. */
4050 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4051 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4053 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4059 /* (const (const X)) can become (const X). Do it this way rather than
4060 returning the inner CONST since CONST can be shared with a
4062 if (GET_CODE (XEXP (x, 0)) == CONST)
4063 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4068 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4069 can add in an offset. find_split_point will split this address up
4070 again if it doesn't match. */
4071 if (GET_CODE (XEXP (x, 0)) == HIGH
4072 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4078 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4079 outermost. That's because that's the way indexed addresses are
4080 supposed to appear. This code used to check many more cases, but
4081 they are now checked elsewhere. */
4082 if (GET_CODE (XEXP (x, 0)) == PLUS
4083 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4084 return gen_binary (PLUS, mode,
4085 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4087 XEXP (XEXP (x, 0), 1));
4089 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4090 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4091 bit-field and can be replaced by either a sign_extend or a
4092 sign_extract. The `and' may be a zero_extend and the two
4093 <c>, -<c> constants may be reversed. */
4094 if (GET_CODE (XEXP (x, 0)) == XOR
4095 && GET_CODE (XEXP (x, 1)) == CONST_INT
4096 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4097 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4098 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4099 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4100 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4101 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4102 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4103 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4104 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4105 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4106 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4108 return simplify_shift_const
4109 (NULL_RTX, ASHIFTRT, mode,
4110 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4111 XEXP (XEXP (XEXP (x, 0), 0), 0),
4112 GET_MODE_BITSIZE (mode) - (i + 1)),
4113 GET_MODE_BITSIZE (mode) - (i + 1));
4115 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4116 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4117 is 1. This produces better code than the alternative immediately
4119 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4120 && reversible_comparison_p (XEXP (x, 0))
4121 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4122 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4124 gen_unary (NEG, mode, mode,
4125 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4126 mode, XEXP (XEXP (x, 0), 0),
4127 XEXP (XEXP (x, 0), 1)));
4129 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4130 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4131 the bitsize of the mode - 1. This allows simplification of
4132 "a = (b & 8) == 0;" */
4133 if (XEXP (x, 1) == constm1_rtx
4134 && GET_CODE (XEXP (x, 0)) != REG
4135 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4136 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4137 && nonzero_bits (XEXP (x, 0), mode) == 1)
4138 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4139 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4140 gen_rtx_combine (XOR, mode,
4141 XEXP (x, 0), const1_rtx),
4142 GET_MODE_BITSIZE (mode) - 1),
4143 GET_MODE_BITSIZE (mode) - 1);
4145 /* If we are adding two things that have no bits in common, convert
4146 the addition into an IOR. This will often be further simplified,
4147 for example in cases like ((a & 1) + (a & 2)), which can
4150 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4151 && (nonzero_bits (XEXP (x, 0), mode)
4152 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4153 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4157 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4158 by reversing the comparison code if valid. */
4159 if (STORE_FLAG_VALUE == 1
4160 && XEXP (x, 0) == const1_rtx
4161 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4162 && reversible_comparison_p (XEXP (x, 1)))
4163 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4164 mode, XEXP (XEXP (x, 1), 0),
4165 XEXP (XEXP (x, 1), 1));
4167 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4168 (and <foo> (const_int pow2-1)) */
4169 if (GET_CODE (XEXP (x, 1)) == AND
4170 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4171 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4172 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4173 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4174 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4176 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4178 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4179 return gen_binary (MINUS, mode,
4180 gen_binary (MINUS, mode, XEXP (x, 0),
4181 XEXP (XEXP (x, 1), 0)),
4182 XEXP (XEXP (x, 1), 1));
4186 /* If we have (mult (plus A B) C), apply the distributive law and then
4187 the inverse distributive law to see if things simplify. This
4188 occurs mostly in addresses, often when unrolling loops. */
4190 if (GET_CODE (XEXP (x, 0)) == PLUS)
4192 x = apply_distributive_law
4193 (gen_binary (PLUS, mode,
4194 gen_binary (MULT, mode,
4195 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4196 gen_binary (MULT, mode,
4197 XEXP (XEXP (x, 0), 1),
4198 copy_rtx (XEXP (x, 1)))));
4200 if (GET_CODE (x) != MULT)
4206 /* If this is a divide by a power of two, treat it as a shift if
4207 its first operand is a shift. */
4208 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4209 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4210 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4211 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4212 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4213 || GET_CODE (XEXP (x, 0)) == ROTATE
4214 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4215 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4219 case GT: case GTU: case GE: case GEU:
4220 case LT: case LTU: case LE: case LEU:
4221 /* If the first operand is a condition code, we can't do anything
4223 if (GET_CODE (XEXP (x, 0)) == COMPARE
4224 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4226 && XEXP (x, 0) != cc0_rtx
4230 rtx op0 = XEXP (x, 0);
4231 rtx op1 = XEXP (x, 1);
4232 enum rtx_code new_code;
4234 if (GET_CODE (op0) == COMPARE)
4235 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4237 /* Simplify our comparison, if possible. */
4238 new_code = simplify_comparison (code, &op0, &op1);
4240 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4241 if only the low-order bit is possibly nonzero in X (such as when
4242 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4243 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4244 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4247 Remove any ZERO_EXTRACT we made when thinking this was a
4248 comparison. It may now be simpler to use, e.g., an AND. If a
4249 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4250 the call to make_compound_operation in the SET case. */
4252 if (STORE_FLAG_VALUE == 1
4253 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4254 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4255 return gen_lowpart_for_combine (mode,
4256 expand_compound_operation (op0));
4258 else if (STORE_FLAG_VALUE == 1
4259 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4260 && op1 == const0_rtx
4261 && (num_sign_bit_copies (op0, mode)
4262 == GET_MODE_BITSIZE (mode)))
4264 op0 = expand_compound_operation (op0);
4265 return gen_unary (NEG, mode, mode,
4266 gen_lowpart_for_combine (mode, op0));
4269 else if (STORE_FLAG_VALUE == 1
4270 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4271 && op1 == const0_rtx
4272 && nonzero_bits (op0, mode) == 1)
4274 op0 = expand_compound_operation (op0);
4275 return gen_binary (XOR, mode,
4276 gen_lowpart_for_combine (mode, op0),
4280 else if (STORE_FLAG_VALUE == 1
4281 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4282 && op1 == const0_rtx
4283 && (num_sign_bit_copies (op0, mode)
4284 == GET_MODE_BITSIZE (mode)))
4286 op0 = expand_compound_operation (op0);
4287 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4290 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4292 if (STORE_FLAG_VALUE == -1
4293 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4294 && op1 == const0_rtx
4295 && (num_sign_bit_copies (op0, mode)
4296 == GET_MODE_BITSIZE (mode)))
4297 return gen_lowpart_for_combine (mode,
4298 expand_compound_operation (op0));
4300 else if (STORE_FLAG_VALUE == -1
4301 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4302 && op1 == const0_rtx
4303 && nonzero_bits (op0, mode) == 1)
4305 op0 = expand_compound_operation (op0);
4306 return gen_unary (NEG, mode, mode,
4307 gen_lowpart_for_combine (mode, op0));
4310 else if (STORE_FLAG_VALUE == -1
4311 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4312 && op1 == const0_rtx
4313 && (num_sign_bit_copies (op0, mode)
4314 == GET_MODE_BITSIZE (mode)))
4316 op0 = expand_compound_operation (op0);
4317 return gen_unary (NOT, mode, mode,
4318 gen_lowpart_for_combine (mode, op0));
4321 /* If X is 0/1, (eq X 0) is X-1. */
4322 else if (STORE_FLAG_VALUE == -1
4323 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4324 && op1 == const0_rtx
4325 && nonzero_bits (op0, mode) == 1)
4327 op0 = expand_compound_operation (op0);
4328 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4331 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4332 one bit that might be nonzero, we can convert (ne x 0) to
4333 (ashift x c) where C puts the bit in the sign bit. Remove any
4334 AND with STORE_FLAG_VALUE when we are done, since we are only
4335 going to test the sign bit. */
4336 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4337 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4338 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4339 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4340 && op1 == const0_rtx
4341 && mode == GET_MODE (op0)
4342 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4344 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4345 expand_compound_operation (op0),
4346 GET_MODE_BITSIZE (mode) - 1 - i);
4347 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4353 /* If the code changed, return a whole new comparison. */
4354 if (new_code != code)
4355 return gen_rtx_combine (new_code, mode, op0, op1);
4357 /* Otherwise, keep this operation, but maybe change its operands.
4358 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4359 SUBST (XEXP (x, 0), op0);
4360 SUBST (XEXP (x, 1), op1);
4365 return simplify_if_then_else (x);
4371 /* If we are processing SET_DEST, we are done. */
4375 return expand_compound_operation (x);
4378 return simplify_set (x);
4383 return simplify_logical (x, last);
4386 /* (abs (neg <foo>)) -> (abs <foo>) */
4387 if (GET_CODE (XEXP (x, 0)) == NEG)
4388 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4390 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4392 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4395 /* If operand is something known to be positive, ignore the ABS. */
4396 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4397 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4398 <= HOST_BITS_PER_WIDE_INT)
4399 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4400 & ((HOST_WIDE_INT) 1
4401 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4406 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4407 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4408 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4413 /* (ffs (*_extend <X>)) = (ffs <X>) */
4414 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4415 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4416 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4420 /* (float (sign_extend <X>)) = (float <X>). */
4421 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4422 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4430 /* If this is a shift by a constant amount, simplify it. */
4431 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4432 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4433 INTVAL (XEXP (x, 1)));
4435 #ifdef SHIFT_COUNT_TRUNCATED
4436 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4438 force_to_mode (XEXP (x, 1), GET_MODE (x),
4440 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4454 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4457 simplify_if_then_else (x)
4460 enum machine_mode mode = GET_MODE (x);
4461 rtx cond = XEXP (x, 0);
4462 rtx true = XEXP (x, 1);
4463 rtx false = XEXP (x, 2);
4464 enum rtx_code true_code = GET_CODE (cond);
4465 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4469 /* Simplify storing of the truth value. */
4470 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4471 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4473 /* Also when the truth value has to be reversed. */
4474 if (comparison_p && reversible_comparison_p (cond)
4475 && true == const0_rtx && false == const_true_rtx)
4476 return gen_binary (reverse_condition (true_code),
4477 mode, XEXP (cond, 0), XEXP (cond, 1));
4479 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4480 in it is being compared against certain values. Get the true and false
4481 comparisons and see if that says anything about the value of each arm. */
4483 if (comparison_p && reversible_comparison_p (cond)
4484 && GET_CODE (XEXP (cond, 0)) == REG)
4487 rtx from = XEXP (cond, 0);
4488 enum rtx_code false_code = reverse_condition (true_code);
4489 rtx true_val = XEXP (cond, 1);
4490 rtx false_val = true_val;
4493 /* If FALSE_CODE is EQ, swap the codes and arms. */
4495 if (false_code == EQ)
4497 swapped = 1, true_code = EQ, false_code = NE;
4498 temp = true, true = false, false = temp;
4501 /* If we are comparing against zero and the expression being tested has
4502 only a single bit that might be nonzero, that is its value when it is
4503 not equal to zero. Similarly if it is known to be -1 or 0. */
4505 if (true_code == EQ && true_val == const0_rtx
4506 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4507 false_code = EQ, false_val = GEN_INT (nzb);
4508 else if (true_code == EQ && true_val == const0_rtx
4509 && (num_sign_bit_copies (from, GET_MODE (from))
4510 == GET_MODE_BITSIZE (GET_MODE (from))))
4511 false_code = EQ, false_val = constm1_rtx;
4513 /* Now simplify an arm if we know the value of the register in the
4514 branch and it is used in the arm. Be careful due to the potential
4515 of locally-shared RTL. */
4517 if (reg_mentioned_p (from, true))
4518 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4519 pc_rtx, pc_rtx, 0, 0);
4520 if (reg_mentioned_p (from, false))
4521 false = subst (known_cond (copy_rtx (false), false_code,
4523 pc_rtx, pc_rtx, 0, 0);
4525 SUBST (XEXP (x, 1), swapped ? false : true);
4526 SUBST (XEXP (x, 2), swapped ? true : false);
4528 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4531 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4532 reversed, do so to avoid needing two sets of patterns for
4533 subtract-and-branch insns. Similarly if we have a constant in the true
4534 arm, the false arm is the same as the first operand of the comparison, or
4535 the false arm is more complicated than the true arm. */
4537 if (comparison_p && reversible_comparison_p (cond)
4539 || (CONSTANT_P (true)
4540 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4541 || true == const0_rtx
4542 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4543 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4544 || (GET_CODE (true) == SUBREG
4545 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4546 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4547 || reg_mentioned_p (true, false)
4548 || rtx_equal_p (false, XEXP (cond, 0))))
4550 true_code = reverse_condition (true_code);
4552 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4555 SUBST (XEXP (x, 1), false);
4556 SUBST (XEXP (x, 2), true);
4558 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4560 /* It is possible that the conditional has been simplified out. */
4561 true_code = GET_CODE (cond);
4562 comparison_p = GET_RTX_CLASS (true_code) == '<';
4565 /* If the two arms are identical, we don't need the comparison. */
4567 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4570 /* Convert a == b ? b : a to "a". */
4571 if (true_code == EQ && ! side_effects_p (cond)
4572 && rtx_equal_p (XEXP (cond, 0), false)
4573 && rtx_equal_p (XEXP (cond, 1), true))
4575 else if (true_code == NE && ! side_effects_p (cond)
4576 && rtx_equal_p (XEXP (cond, 0), true)
4577 && rtx_equal_p (XEXP (cond, 1), false))
4580 /* Look for cases where we have (abs x) or (neg (abs X)). */
4582 if (GET_MODE_CLASS (mode) == MODE_INT
4583 && GET_CODE (false) == NEG
4584 && rtx_equal_p (true, XEXP (false, 0))
4586 && rtx_equal_p (true, XEXP (cond, 0))
4587 && ! side_effects_p (true))
4592 return gen_unary (ABS, mode, mode, true);
4595 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4600 /* Look for MIN or MAX. */
4602 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4604 && rtx_equal_p (XEXP (cond, 0), true)
4605 && rtx_equal_p (XEXP (cond, 1), false)
4606 && ! side_effects_p (cond))
4611 return gen_binary (SMAX, mode, true, false);
4614 return gen_binary (SMIN, mode, true, false);
4617 return gen_binary (UMAX, mode, true, false);
4620 return gen_binary (UMIN, mode, true, false);
4625 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4626 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4627 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4628 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4629 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4630 neither 1 or -1, but it isn't worth checking for. */
4632 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4633 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4635 rtx t = make_compound_operation (true, SET);
4636 rtx f = make_compound_operation (false, SET);
4637 rtx cond_op0 = XEXP (cond, 0);
4638 rtx cond_op1 = XEXP (cond, 1);
4639 enum rtx_code op = NIL, extend_op = NIL;
4640 enum machine_mode m = mode;
4641 rtx z = 0, c1 = NULL_RTX;
4643 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4644 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4645 || GET_CODE (t) == ASHIFT
4646 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4647 && rtx_equal_p (XEXP (t, 0), f))
4648 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4650 /* If an identity-zero op is commutative, check whether there
4651 would be a match if we swapped the operands. */
4652 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4653 || GET_CODE (t) == XOR)
4654 && rtx_equal_p (XEXP (t, 1), f))
4655 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4656 else if (GET_CODE (t) == SIGN_EXTEND
4657 && (GET_CODE (XEXP (t, 0)) == PLUS
4658 || GET_CODE (XEXP (t, 0)) == MINUS
4659 || GET_CODE (XEXP (t, 0)) == IOR
4660 || GET_CODE (XEXP (t, 0)) == XOR
4661 || GET_CODE (XEXP (t, 0)) == ASHIFT
4662 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4663 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4664 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4665 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4666 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4667 && (num_sign_bit_copies (f, GET_MODE (f))
4668 > (GET_MODE_BITSIZE (mode)
4669 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4671 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4672 extend_op = SIGN_EXTEND;
4673 m = GET_MODE (XEXP (t, 0));
4675 else if (GET_CODE (t) == SIGN_EXTEND
4676 && (GET_CODE (XEXP (t, 0)) == PLUS
4677 || GET_CODE (XEXP (t, 0)) == IOR
4678 || GET_CODE (XEXP (t, 0)) == XOR)
4679 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4680 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4681 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4682 && (num_sign_bit_copies (f, GET_MODE (f))
4683 > (GET_MODE_BITSIZE (mode)
4684 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4686 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4687 extend_op = SIGN_EXTEND;
4688 m = GET_MODE (XEXP (t, 0));
4690 else if (GET_CODE (t) == ZERO_EXTEND
4691 && (GET_CODE (XEXP (t, 0)) == PLUS
4692 || GET_CODE (XEXP (t, 0)) == MINUS
4693 || GET_CODE (XEXP (t, 0)) == IOR
4694 || GET_CODE (XEXP (t, 0)) == XOR
4695 || GET_CODE (XEXP (t, 0)) == ASHIFT
4696 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4697 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4698 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4699 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4700 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4701 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4702 && ((nonzero_bits (f, GET_MODE (f))
4703 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4706 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4707 extend_op = ZERO_EXTEND;
4708 m = GET_MODE (XEXP (t, 0));
4710 else if (GET_CODE (t) == ZERO_EXTEND
4711 && (GET_CODE (XEXP (t, 0)) == PLUS
4712 || GET_CODE (XEXP (t, 0)) == IOR
4713 || GET_CODE (XEXP (t, 0)) == XOR)
4714 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4715 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4716 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4717 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4718 && ((nonzero_bits (f, GET_MODE (f))
4719 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4722 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4723 extend_op = ZERO_EXTEND;
4724 m = GET_MODE (XEXP (t, 0));
4729 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4730 pc_rtx, pc_rtx, 0, 0);
4731 temp = gen_binary (MULT, m, temp,
4732 gen_binary (MULT, m, c1, const_true_rtx));
4733 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4734 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4736 if (extend_op != NIL)
4737 temp = gen_unary (extend_op, mode, m, temp);
4743 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4744 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4745 negation of a single bit, we can convert this operation to a shift. We
4746 can actually do this more generally, but it doesn't seem worth it. */
4748 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4749 && false == const0_rtx && GET_CODE (true) == CONST_INT
4750 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4751 && (i = exact_log2 (INTVAL (true))) >= 0)
4752 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4753 == GET_MODE_BITSIZE (mode))
4754 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4756 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4757 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4762 /* Simplify X, a SET expression. Return the new expression. */
4768 rtx src = SET_SRC (x);
4769 rtx dest = SET_DEST (x);
4770 enum machine_mode mode
4771 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4775 /* (set (pc) (return)) gets written as (return). */
4776 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4779 /* Now that we know for sure which bits of SRC we are using, see if we can
4780 simplify the expression for the object knowing that we only need the
4783 if (GET_MODE_CLASS (mode) == MODE_INT)
4785 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4786 SUBST (SET_SRC (x), src);
4789 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4790 the comparison result and try to simplify it unless we already have used
4791 undobuf.other_insn. */
4792 if ((GET_CODE (src) == COMPARE
4797 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4798 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4799 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4800 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4802 enum rtx_code old_code = GET_CODE (*cc_use);
4803 enum rtx_code new_code;
4805 int other_changed = 0;
4806 enum machine_mode compare_mode = GET_MODE (dest);
4808 if (GET_CODE (src) == COMPARE)
4809 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4811 op0 = src, op1 = const0_rtx;
4813 /* Simplify our comparison, if possible. */
4814 new_code = simplify_comparison (old_code, &op0, &op1);
4816 #ifdef EXTRA_CC_MODES
4817 /* If this machine has CC modes other than CCmode, check to see if we
4818 need to use a different CC mode here. */
4819 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4820 #endif /* EXTRA_CC_MODES */
4822 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4823 /* If the mode changed, we have to change SET_DEST, the mode in the
4824 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4825 a hard register, just build new versions with the proper mode. If it
4826 is a pseudo, we lose unless it is only time we set the pseudo, in
4827 which case we can safely change its mode. */
4828 if (compare_mode != GET_MODE (dest))
4830 int regno = REGNO (dest);
4831 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4833 if (regno < FIRST_PSEUDO_REGISTER
4834 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4836 if (regno >= FIRST_PSEUDO_REGISTER)
4837 SUBST (regno_reg_rtx[regno], new_dest);
4839 SUBST (SET_DEST (x), new_dest);
4840 SUBST (XEXP (*cc_use, 0), new_dest);
4848 /* If the code changed, we have to build a new comparison in
4849 undobuf.other_insn. */
4850 if (new_code != old_code)
4852 unsigned HOST_WIDE_INT mask;
4854 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4857 /* If the only change we made was to change an EQ into an NE or
4858 vice versa, OP0 has only one bit that might be nonzero, and OP1
4859 is zero, check if changing the user of the condition code will
4860 produce a valid insn. If it won't, we can keep the original code
4861 in that insn by surrounding our operation with an XOR. */
4863 if (((old_code == NE && new_code == EQ)
4864 || (old_code == EQ && new_code == NE))
4865 && ! other_changed && op1 == const0_rtx
4866 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4867 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4869 rtx pat = PATTERN (other_insn), note = 0;
4871 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4872 && ! check_asm_operands (pat)))
4874 PUT_CODE (*cc_use, old_code);
4877 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4885 undobuf.other_insn = other_insn;
4888 /* If we are now comparing against zero, change our source if
4889 needed. If we do not use cc0, we always have a COMPARE. */
4890 if (op1 == const0_rtx && dest == cc0_rtx)
4892 SUBST (SET_SRC (x), op0);
4898 /* Otherwise, if we didn't previously have a COMPARE in the
4899 correct mode, we need one. */
4900 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4903 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4908 /* Otherwise, update the COMPARE if needed. */
4909 SUBST (XEXP (src, 0), op0);
4910 SUBST (XEXP (src, 1), op1);
4915 /* Get SET_SRC in a form where we have placed back any
4916 compound expressions. Then do the checks below. */
4917 src = make_compound_operation (src, SET);
4918 SUBST (SET_SRC (x), src);
4921 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4922 and X being a REG or (subreg (reg)), we may be able to convert this to
4923 (set (subreg:m2 x) (op)).
4925 We can always do this if M1 is narrower than M2 because that means that
4926 we only care about the low bits of the result.
4928 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4929 perform a narrower operation than requested since the high-order bits will
4930 be undefined. On machine where it is defined, this transformation is safe
4931 as long as M1 and M2 have the same number of words. */
4933 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4934 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4935 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4937 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4938 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4939 #ifndef WORD_REGISTER_OPERATIONS
4940 && (GET_MODE_SIZE (GET_MODE (src))
4941 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4943 #ifdef CLASS_CANNOT_CHANGE_SIZE
4944 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4945 && (TEST_HARD_REG_BIT
4946 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4948 && (GET_MODE_SIZE (GET_MODE (src))
4949 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4951 && (GET_CODE (dest) == REG
4952 || (GET_CODE (dest) == SUBREG
4953 && GET_CODE (SUBREG_REG (dest)) == REG)))
4955 SUBST (SET_DEST (x),
4956 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4958 SUBST (SET_SRC (x), SUBREG_REG (src));
4960 src = SET_SRC (x), dest = SET_DEST (x);
4963 #ifdef LOAD_EXTEND_OP
4964 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4965 would require a paradoxical subreg. Replace the subreg with a
4966 zero_extend to avoid the reload that would otherwise be required. */
4968 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4969 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4970 && SUBREG_WORD (src) == 0
4971 && (GET_MODE_SIZE (GET_MODE (src))
4972 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4973 && GET_CODE (SUBREG_REG (src)) == MEM)
4976 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4977 GET_MODE (src), XEXP (src, 0)));
4983 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4984 are comparing an item known to be 0 or -1 against 0, use a logical
4985 operation instead. Check for one of the arms being an IOR of the other
4986 arm with some value. We compute three terms to be IOR'ed together. In
4987 practice, at most two will be nonzero. Then we do the IOR's. */
4989 if (GET_CODE (dest) != PC
4990 && GET_CODE (src) == IF_THEN_ELSE
4991 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4992 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4993 && XEXP (XEXP (src, 0), 1) == const0_rtx
4994 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4995 #ifdef HAVE_conditional_move
4996 && ! can_conditionally_move_p (GET_MODE (src))
4998 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4999 GET_MODE (XEXP (XEXP (src, 0), 0)))
5000 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5001 && ! side_effects_p (src))
5003 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5004 ? XEXP (src, 1) : XEXP (src, 2));
5005 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5006 ? XEXP (src, 2) : XEXP (src, 1));
5007 rtx term1 = const0_rtx, term2, term3;
5009 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5010 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5011 else if (GET_CODE (true) == IOR
5012 && rtx_equal_p (XEXP (true, 1), false))
5013 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5014 else if (GET_CODE (false) == IOR
5015 && rtx_equal_p (XEXP (false, 0), true))
5016 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5017 else if (GET_CODE (false) == IOR
5018 && rtx_equal_p (XEXP (false, 1), true))
5019 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5021 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5022 term3 = gen_binary (AND, GET_MODE (src),
5023 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5024 XEXP (XEXP (src, 0), 0)),
5028 gen_binary (IOR, GET_MODE (src),
5029 gen_binary (IOR, GET_MODE (src), term1, term2),
5035 #ifdef HAVE_conditional_arithmetic
5036 /* If we have conditional arithmetic and the operand of a SET is
5037 a conditional expression, replace this with an IF_THEN_ELSE.
5038 We can either have a conditional expression or a MULT of that expression
5040 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5041 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5042 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5043 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5044 || (GET_CODE (XEXP (src, 0)) == MULT
5045 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5046 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5048 rtx cond = XEXP (src, 0);
5049 rtx true_val = const1_rtx;
5050 rtx false_arm, true_arm;
5052 if (GET_CODE (cond) == MULT)
5054 true_val = XEXP (cond, 1);
5055 cond = XEXP (cond, 0);
5058 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5060 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5061 GET_MODE (XEXP (src, 0)), true_val);
5062 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5063 GET_MODE (XEXP (src, 0)), const0_rtx);
5067 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5068 true_val, XEXP (src, 1));
5069 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5070 const0_rtx, XEXP (src, 1));
5073 /* Canonicalize if true_arm is the simpler one. */
5074 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5075 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5076 && reversible_comparison_p (cond))
5078 rtx temp = true_arm;
5080 true_arm = false_arm;
5083 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5084 GET_MODE (cond), XEXP (cond, 0),
5088 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5089 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5092 true_arm, false_arm);
5093 SUBST (SET_SRC (x), src);
5097 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5098 whole thing fail. */
5099 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5101 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5104 /* Convert this into a field assignment operation, if possible. */
5105 return make_field_assignment (x);
5108 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5109 result. LAST is nonzero if this is the last retry. */
5112 simplify_logical (x, last)
5116 enum machine_mode mode = GET_MODE (x);
5117 rtx op0 = XEXP (x, 0);
5118 rtx op1 = XEXP (x, 1);
5120 switch (GET_CODE (x))
5123 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5124 insn (and may simplify more). */
5125 if (GET_CODE (op0) == XOR
5126 && rtx_equal_p (XEXP (op0, 0), op1)
5127 && ! side_effects_p (op1))
5128 x = gen_binary (AND, mode,
5129 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5131 if (GET_CODE (op0) == XOR
5132 && rtx_equal_p (XEXP (op0, 1), op1)
5133 && ! side_effects_p (op1))
5134 x = gen_binary (AND, mode,
5135 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5137 /* Similarly for (~ (A ^ B)) & A. */
5138 if (GET_CODE (op0) == NOT
5139 && GET_CODE (XEXP (op0, 0)) == XOR
5140 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5141 && ! side_effects_p (op1))
5142 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5144 if (GET_CODE (op0) == NOT
5145 && GET_CODE (XEXP (op0, 0)) == XOR
5146 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5147 && ! side_effects_p (op1))
5148 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5150 /* We can call simplify_and_const_int only if we don't lose
5151 any (sign) bits when converting INTVAL (op1) to
5152 "unsigned HOST_WIDE_INT". */
5153 if (GET_CODE (op1) == CONST_INT
5154 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5155 || INTVAL (op1) > 0))
5157 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5159 /* If we have (ior (and (X C1) C2)) and the next restart would be
5160 the last, simplify this by making C1 as small as possible
5163 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5164 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5165 && GET_CODE (op1) == CONST_INT)
5166 return gen_binary (IOR, mode,
5167 gen_binary (AND, mode, XEXP (op0, 0),
5168 GEN_INT (INTVAL (XEXP (op0, 1))
5169 & ~ INTVAL (op1))), op1);
5171 if (GET_CODE (x) != AND)
5174 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5175 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5176 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5179 /* Convert (A | B) & A to A. */
5180 if (GET_CODE (op0) == IOR
5181 && (rtx_equal_p (XEXP (op0, 0), op1)
5182 || rtx_equal_p (XEXP (op0, 1), op1))
5183 && ! side_effects_p (XEXP (op0, 0))
5184 && ! side_effects_p (XEXP (op0, 1)))
5187 /* In the following group of tests (and those in case IOR below),
5188 we start with some combination of logical operations and apply
5189 the distributive law followed by the inverse distributive law.
5190 Most of the time, this results in no change. However, if some of
5191 the operands are the same or inverses of each other, simplifications
5194 For example, (and (ior A B) (not B)) can occur as the result of
5195 expanding a bit field assignment. When we apply the distributive
5196 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5197 which then simplifies to (and (A (not B))).
5199 If we have (and (ior A B) C), apply the distributive law and then
5200 the inverse distributive law to see if things simplify. */
5202 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5204 x = apply_distributive_law
5205 (gen_binary (GET_CODE (op0), mode,
5206 gen_binary (AND, mode, XEXP (op0, 0), op1),
5207 gen_binary (AND, mode, XEXP (op0, 1),
5209 if (GET_CODE (x) != AND)
5213 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5214 return apply_distributive_law
5215 (gen_binary (GET_CODE (op1), mode,
5216 gen_binary (AND, mode, XEXP (op1, 0), op0),
5217 gen_binary (AND, mode, XEXP (op1, 1),
5220 /* Similarly, taking advantage of the fact that
5221 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5223 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5224 return apply_distributive_law
5225 (gen_binary (XOR, mode,
5226 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5227 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5230 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5231 return apply_distributive_law
5232 (gen_binary (XOR, mode,
5233 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5234 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5238 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5239 if (GET_CODE (op1) == CONST_INT
5240 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5241 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5244 /* Convert (A & B) | A to A. */
5245 if (GET_CODE (op0) == AND
5246 && (rtx_equal_p (XEXP (op0, 0), op1)
5247 || rtx_equal_p (XEXP (op0, 1), op1))
5248 && ! side_effects_p (XEXP (op0, 0))
5249 && ! side_effects_p (XEXP (op0, 1)))
5252 /* If we have (ior (and A B) C), apply the distributive law and then
5253 the inverse distributive law to see if things simplify. */
5255 if (GET_CODE (op0) == AND)
5257 x = apply_distributive_law
5258 (gen_binary (AND, mode,
5259 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5260 gen_binary (IOR, mode, XEXP (op0, 1),
5263 if (GET_CODE (x) != IOR)
5267 if (GET_CODE (op1) == AND)
5269 x = apply_distributive_law
5270 (gen_binary (AND, mode,
5271 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5272 gen_binary (IOR, mode, XEXP (op1, 1),
5275 if (GET_CODE (x) != IOR)
5279 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5280 mode size to (rotate A CX). */
5282 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5283 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5284 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5285 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5286 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5287 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5288 == GET_MODE_BITSIZE (mode)))
5289 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5290 (GET_CODE (op0) == ASHIFT
5291 ? XEXP (op0, 1) : XEXP (op1, 1)));
5293 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5294 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5295 does not affect any of the bits in OP1, it can really be done
5296 as a PLUS and we can associate. We do this by seeing if OP1
5297 can be safely shifted left C bits. */
5298 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5299 && GET_CODE (XEXP (op0, 0)) == PLUS
5300 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5301 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5302 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5304 int count = INTVAL (XEXP (op0, 1));
5305 HOST_WIDE_INT mask = INTVAL (op1) << count;
5307 if (mask >> count == INTVAL (op1)
5308 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5310 SUBST (XEXP (XEXP (op0, 0), 1),
5311 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5318 /* If we are XORing two things that have no bits in common,
5319 convert them into an IOR. This helps to detect rotation encoded
5320 using those methods and possibly other simplifications. */
5322 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5323 && (nonzero_bits (op0, mode)
5324 & nonzero_bits (op1, mode)) == 0)
5325 return (gen_binary (IOR, mode, op0, op1));
5327 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5328 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5331 int num_negated = 0;
5333 if (GET_CODE (op0) == NOT)
5334 num_negated++, op0 = XEXP (op0, 0);
5335 if (GET_CODE (op1) == NOT)
5336 num_negated++, op1 = XEXP (op1, 0);
5338 if (num_negated == 2)
5340 SUBST (XEXP (x, 0), op0);
5341 SUBST (XEXP (x, 1), op1);
5343 else if (num_negated == 1)
5344 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5347 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5348 correspond to a machine insn or result in further simplifications
5349 if B is a constant. */
5351 if (GET_CODE (op0) == AND
5352 && rtx_equal_p (XEXP (op0, 1), op1)
5353 && ! side_effects_p (op1))
5354 return gen_binary (AND, mode,
5355 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5358 else if (GET_CODE (op0) == AND
5359 && rtx_equal_p (XEXP (op0, 0), op1)
5360 && ! side_effects_p (op1))
5361 return gen_binary (AND, mode,
5362 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5365 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5366 comparison if STORE_FLAG_VALUE is 1. */
5367 if (STORE_FLAG_VALUE == 1
5368 && op1 == const1_rtx
5369 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5370 && reversible_comparison_p (op0))
5371 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5372 mode, XEXP (op0, 0), XEXP (op0, 1));
5374 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5375 is (lt foo (const_int 0)), so we can perform the above
5376 simplification if STORE_FLAG_VALUE is 1. */
5378 if (STORE_FLAG_VALUE == 1
5379 && op1 == const1_rtx
5380 && GET_CODE (op0) == LSHIFTRT
5381 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5382 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5383 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5385 /* (xor (comparison foo bar) (const_int sign-bit))
5386 when STORE_FLAG_VALUE is the sign bit. */
5387 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5388 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5389 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5390 && op1 == const_true_rtx
5391 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5392 && reversible_comparison_p (op0))
5393 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5394 mode, XEXP (op0, 0), XEXP (op0, 1));
5405 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5406 operations" because they can be replaced with two more basic operations.
5407 ZERO_EXTEND is also considered "compound" because it can be replaced with
5408 an AND operation, which is simpler, though only one operation.
5410 The function expand_compound_operation is called with an rtx expression
5411 and will convert it to the appropriate shifts and AND operations,
5412 simplifying at each stage.
5414 The function make_compound_operation is called to convert an expression
5415 consisting of shifts and ANDs into the equivalent compound expression.
5416 It is the inverse of this function, loosely speaking. */
5419 expand_compound_operation (x)
5427 switch (GET_CODE (x))
5432 /* We can't necessarily use a const_int for a multiword mode;
5433 it depends on implicitly extending the value.
5434 Since we don't know the right way to extend it,
5435 we can't tell whether the implicit way is right.
5437 Even for a mode that is no wider than a const_int,
5438 we can't win, because we need to sign extend one of its bits through
5439 the rest of it, and we don't know which bit. */
5440 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5443 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5444 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5445 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5446 reloaded. If not for that, MEM's would very rarely be safe.
5448 Reject MODEs bigger than a word, because we might not be able
5449 to reference a two-register group starting with an arbitrary register
5450 (and currently gen_lowpart might crash for a SUBREG). */
5452 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5455 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5456 /* If the inner object has VOIDmode (the only way this can happen
5457 is if it is a ASM_OPERANDS), we can't do anything since we don't
5458 know how much masking to do. */
5467 /* If the operand is a CLOBBER, just return it. */
5468 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5471 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5472 || GET_CODE (XEXP (x, 2)) != CONST_INT
5473 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5476 len = INTVAL (XEXP (x, 1));
5477 pos = INTVAL (XEXP (x, 2));
5479 /* If this goes outside the object being extracted, replace the object
5480 with a (use (mem ...)) construct that only combine understands
5481 and is used only for this purpose. */
5482 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5483 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5485 if (BITS_BIG_ENDIAN)
5486 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5493 /* Convert sign extension to zero extension, if we know that the high
5494 bit is not set, as this is easier to optimize. It will be converted
5495 back to cheaper alternative in make_extraction. */
5496 if (GET_CODE (x) == SIGN_EXTEND
5497 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5498 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5499 & ~ (((unsigned HOST_WIDE_INT)
5500 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5504 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5505 return expand_compound_operation (temp);
5508 /* We can optimize some special cases of ZERO_EXTEND. */
5509 if (GET_CODE (x) == ZERO_EXTEND)
5511 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5512 know that the last value didn't have any inappropriate bits
5514 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5515 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5516 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5517 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5518 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5519 return XEXP (XEXP (x, 0), 0);
5521 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5522 if (GET_CODE (XEXP (x, 0)) == SUBREG
5523 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5524 && subreg_lowpart_p (XEXP (x, 0))
5525 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5526 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5527 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5528 return SUBREG_REG (XEXP (x, 0));
5530 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5531 is a comparison and STORE_FLAG_VALUE permits. This is like
5532 the first case, but it works even when GET_MODE (x) is larger
5533 than HOST_WIDE_INT. */
5534 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5535 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5536 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5537 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5538 <= HOST_BITS_PER_WIDE_INT)
5539 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5540 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5541 return XEXP (XEXP (x, 0), 0);
5543 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5544 if (GET_CODE (XEXP (x, 0)) == SUBREG
5545 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5546 && subreg_lowpart_p (XEXP (x, 0))
5547 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5548 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5549 <= HOST_BITS_PER_WIDE_INT)
5550 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5551 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5552 return SUBREG_REG (XEXP (x, 0));
5556 /* If we reach here, we want to return a pair of shifts. The inner
5557 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5558 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5559 logical depending on the value of UNSIGNEDP.
5561 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5562 converted into an AND of a shift.
5564 We must check for the case where the left shift would have a negative
5565 count. This can happen in a case like (x >> 31) & 255 on machines
5566 that can't shift by a constant. On those machines, we would first
5567 combine the shift with the AND to produce a variable-position
5568 extraction. Then the constant of 31 would be substituted in to produce
5569 a such a position. */
5571 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5572 if (modewidth >= pos - len)
5573 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5575 simplify_shift_const (NULL_RTX, ASHIFT,
5578 modewidth - pos - len),
5581 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5582 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5583 simplify_shift_const (NULL_RTX, LSHIFTRT,
5586 ((HOST_WIDE_INT) 1 << len) - 1);
5588 /* Any other cases we can't handle. */
5592 /* If we couldn't do this for some reason, return the original
5594 if (GET_CODE (tem) == CLOBBER)
5600 /* X is a SET which contains an assignment of one object into
5601 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5602 or certain SUBREGS). If possible, convert it into a series of
5605 We half-heartedly support variable positions, but do not at all
5606 support variable lengths. */
5609 expand_field_assignment (x)
5613 rtx pos; /* Always counts from low bit. */
5616 enum machine_mode compute_mode;
5618 /* Loop until we find something we can't simplify. */
5621 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5622 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5624 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5625 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5626 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5628 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5629 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5631 inner = XEXP (SET_DEST (x), 0);
5632 len = INTVAL (XEXP (SET_DEST (x), 1));
5633 pos = XEXP (SET_DEST (x), 2);
5635 /* If the position is constant and spans the width of INNER,
5636 surround INNER with a USE to indicate this. */
5637 if (GET_CODE (pos) == CONST_INT
5638 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5639 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5641 if (BITS_BIG_ENDIAN)
5643 if (GET_CODE (pos) == CONST_INT)
5644 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5646 else if (GET_CODE (pos) == MINUS
5647 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5648 && (INTVAL (XEXP (pos, 1))
5649 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5650 /* If position is ADJUST - X, new position is X. */
5651 pos = XEXP (pos, 0);
5653 pos = gen_binary (MINUS, GET_MODE (pos),
5654 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5660 /* A SUBREG between two modes that occupy the same numbers of words
5661 can be done by moving the SUBREG to the source. */
5662 else if (GET_CODE (SET_DEST (x)) == SUBREG
5663 /* We need SUBREGs to compute nonzero_bits properly. */
5664 && nonzero_sign_valid
5665 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5666 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5667 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5668 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5670 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5671 gen_lowpart_for_combine
5672 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5679 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5680 inner = SUBREG_REG (inner);
5682 compute_mode = GET_MODE (inner);
5684 /* Don't attempt bitwise arithmetic on non-integral modes. */
5685 if (! INTEGRAL_MODE_P (compute_mode))
5687 enum machine_mode imode;
5689 /* Something is probably seriously wrong if this matches. */
5690 if (! FLOAT_MODE_P (compute_mode))
5693 /* Try to find an integral mode to pun with. */
5694 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5695 if (imode == BLKmode)
5698 compute_mode = imode;
5699 inner = gen_lowpart_for_combine (imode, inner);
5702 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5703 if (len < HOST_BITS_PER_WIDE_INT)
5704 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5708 /* Now compute the equivalent expression. Make a copy of INNER
5709 for the SET_DEST in case it is a MEM into which we will substitute;
5710 we don't want shared RTL in that case. */
5712 (VOIDmode, copy_rtx (inner),
5713 gen_binary (IOR, compute_mode,
5714 gen_binary (AND, compute_mode,
5715 gen_unary (NOT, compute_mode,
5721 gen_binary (ASHIFT, compute_mode,
5722 gen_binary (AND, compute_mode,
5723 gen_lowpart_for_combine
5724 (compute_mode, SET_SRC (x)),
5732 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5733 it is an RTX that represents a variable starting position; otherwise,
5734 POS is the (constant) starting bit position (counted from the LSB).
5736 INNER may be a USE. This will occur when we started with a bitfield
5737 that went outside the boundary of the object in memory, which is
5738 allowed on most machines. To isolate this case, we produce a USE
5739 whose mode is wide enough and surround the MEM with it. The only
5740 code that understands the USE is this routine. If it is not removed,
5741 it will cause the resulting insn not to match.
5743 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5746 IN_DEST is non-zero if this is a reference in the destination of a
5747 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5748 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5751 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5752 ZERO_EXTRACT should be built even for bits starting at bit 0.
5754 MODE is the desired mode of the result (if IN_DEST == 0).
5756 The result is an RTX for the extraction or NULL_RTX if the target
5760 make_extraction (mode, inner, pos, pos_rtx, len,
5761 unsignedp, in_dest, in_compare)
5762 enum machine_mode mode;
5768 int in_dest, in_compare;
5770 /* This mode describes the size of the storage area
5771 to fetch the overall value from. Within that, we
5772 ignore the POS lowest bits, etc. */
5773 enum machine_mode is_mode = GET_MODE (inner);
5774 enum machine_mode inner_mode;
5775 enum machine_mode wanted_inner_mode = byte_mode;
5776 enum machine_mode wanted_inner_reg_mode = word_mode;
5777 enum machine_mode pos_mode = word_mode;
5778 enum machine_mode extraction_mode = word_mode;
5779 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5782 rtx orig_pos_rtx = pos_rtx;
5785 /* Get some information about INNER and get the innermost object. */
5786 if (GET_CODE (inner) == USE)
5787 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5788 /* We don't need to adjust the position because we set up the USE
5789 to pretend that it was a full-word object. */
5790 spans_byte = 1, inner = XEXP (inner, 0);
5791 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5793 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5794 consider just the QI as the memory to extract from.
5795 The subreg adds or removes high bits; its mode is
5796 irrelevant to the meaning of this extraction,
5797 since POS and LEN count from the lsb. */
5798 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5799 is_mode = GET_MODE (SUBREG_REG (inner));
5800 inner = SUBREG_REG (inner);
5803 inner_mode = GET_MODE (inner);
5805 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5806 pos = INTVAL (pos_rtx), pos_rtx = 0;
5808 /* See if this can be done without an extraction. We never can if the
5809 width of the field is not the same as that of some integer mode. For
5810 registers, we can only avoid the extraction if the position is at the
5811 low-order bit and this is either not in the destination or we have the
5812 appropriate STRICT_LOW_PART operation available.
5814 For MEM, we can avoid an extract if the field starts on an appropriate
5815 boundary and we can change the mode of the memory reference. However,
5816 we cannot directly access the MEM if we have a USE and the underlying
5817 MEM is not TMODE. This combination means that MEM was being used in a
5818 context where bits outside its mode were being referenced; that is only
5819 valid in bit-field insns. */
5821 if (tmode != BLKmode
5822 && ! (spans_byte && inner_mode != tmode)
5823 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5824 && GET_CODE (inner) != MEM
5826 || (GET_CODE (inner) == REG
5827 && (movstrict_optab->handlers[(int) tmode].insn_code
5828 != CODE_FOR_nothing))))
5829 || (GET_CODE (inner) == MEM && pos_rtx == 0
5831 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5832 : BITS_PER_UNIT)) == 0
5833 /* We can't do this if we are widening INNER_MODE (it
5834 may not be aligned, for one thing). */
5835 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5836 && (inner_mode == tmode
5837 || (! mode_dependent_address_p (XEXP (inner, 0))
5838 && ! MEM_VOLATILE_P (inner))))))
5840 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5841 field. If the original and current mode are the same, we need not
5842 adjust the offset. Otherwise, we do if bytes big endian.
5844 If INNER is not a MEM, get a piece consisting of just the field
5845 of interest (in this case POS % BITS_PER_WORD must be 0). */
5847 if (GET_CODE (inner) == MEM)
5850 /* POS counts from lsb, but make OFFSET count in memory order. */
5851 if (BYTES_BIG_ENDIAN)
5852 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5854 offset = pos / BITS_PER_UNIT;
5856 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5857 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5858 MEM_COPY_ATTRIBUTES (new, inner);
5860 else if (GET_CODE (inner) == REG)
5862 /* We can't call gen_lowpart_for_combine here since we always want
5863 a SUBREG and it would sometimes return a new hard register. */
5864 if (tmode != inner_mode)
5865 new = gen_rtx_SUBREG (tmode, inner,
5867 && (GET_MODE_SIZE (inner_mode)
5869 ? (((GET_MODE_SIZE (inner_mode)
5870 - GET_MODE_SIZE (tmode))
5872 - pos / BITS_PER_WORD)
5873 : pos / BITS_PER_WORD));
5878 new = force_to_mode (inner, tmode,
5879 len >= HOST_BITS_PER_WIDE_INT
5880 ? GET_MODE_MASK (tmode)
5881 : ((HOST_WIDE_INT) 1 << len) - 1,
5884 /* If this extraction is going into the destination of a SET,
5885 make a STRICT_LOW_PART unless we made a MEM. */
5888 return (GET_CODE (new) == MEM ? new
5889 : (GET_CODE (new) != SUBREG
5890 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5891 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5896 /* If we know that no extraneous bits are set, and that the high
5897 bit is not set, convert the extraction to the cheaper of
5898 sign and zero extension, that are equivalent in these cases. */
5899 if (flag_expensive_optimizations
5900 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5901 && ((nonzero_bits (new, tmode)
5902 & ~ (((unsigned HOST_WIDE_INT)
5903 GET_MODE_MASK (tmode))
5907 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5908 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5910 /* Prefer ZERO_EXTENSION, since it gives more information to
5912 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
5917 /* Otherwise, sign- or zero-extend unless we already are in the
5920 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5924 /* Unless this is a COMPARE or we have a funny memory reference,
5925 don't do anything with zero-extending field extracts starting at
5926 the low-order bit since they are simple AND operations. */
5927 if (pos_rtx == 0 && pos == 0 && ! in_dest
5928 && ! in_compare && ! spans_byte && unsignedp)
5931 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5932 we would be spanning bytes or if the position is not a constant and the
5933 length is not 1. In all other cases, we would only be going outside
5934 our object in cases when an original shift would have been
5936 if (! spans_byte && GET_CODE (inner) == MEM
5937 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5938 || (pos_rtx != 0 && len != 1)))
5941 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5942 and the mode for the result. */
5946 wanted_inner_reg_mode
5947 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
5948 if (wanted_inner_reg_mode == VOIDmode)
5949 wanted_inner_reg_mode = word_mode;
5951 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
5952 if (pos_mode == VOIDmode)
5953 pos_mode = word_mode;
5955 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
5956 if (extraction_mode == VOIDmode)
5957 extraction_mode = word_mode;
5962 if (! in_dest && unsignedp)
5964 wanted_inner_reg_mode
5965 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
5966 if (wanted_inner_reg_mode == VOIDmode)
5967 wanted_inner_reg_mode = word_mode;
5969 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
5970 if (pos_mode == VOIDmode)
5971 pos_mode = word_mode;
5973 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
5974 if (extraction_mode == VOIDmode)
5975 extraction_mode = word_mode;
5980 if (! in_dest && ! unsignedp)
5982 wanted_inner_reg_mode
5983 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
5984 if (wanted_inner_reg_mode == VOIDmode)
5985 wanted_inner_reg_mode = word_mode;
5987 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
5988 if (pos_mode == VOIDmode)
5989 pos_mode = word_mode;
5991 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
5992 if (extraction_mode == VOIDmode)
5993 extraction_mode = word_mode;
5997 /* Never narrow an object, since that might not be safe. */
5999 if (mode != VOIDmode
6000 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6001 extraction_mode = mode;
6003 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6004 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6005 pos_mode = GET_MODE (pos_rtx);
6007 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6008 if we have to change the mode of memory and cannot, the desired mode is
6010 if (GET_CODE (inner) != MEM)
6011 wanted_inner_mode = wanted_inner_reg_mode;
6012 else if (inner_mode != wanted_inner_mode
6013 && (mode_dependent_address_p (XEXP (inner, 0))
6014 || MEM_VOLATILE_P (inner)))
6015 wanted_inner_mode = extraction_mode;
6019 if (BITS_BIG_ENDIAN)
6021 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6022 BITS_BIG_ENDIAN style. If position is constant, compute new
6023 position. Otherwise, build subtraction.
6024 Note that POS is relative to the mode of the original argument.
6025 If it's a MEM we need to recompute POS relative to that.
6026 However, if we're extracting from (or inserting into) a register,
6027 we want to recompute POS relative to wanted_inner_mode. */
6028 int width = (GET_CODE (inner) == MEM
6029 ? GET_MODE_BITSIZE (is_mode)
6030 : GET_MODE_BITSIZE (wanted_inner_mode));
6033 pos = width - len - pos;
6036 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6037 GEN_INT (width - len), pos_rtx);
6038 /* POS may be less than 0 now, but we check for that below.
6039 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6042 /* If INNER has a wider mode, make it smaller. If this is a constant
6043 extract, try to adjust the byte to point to the byte containing
6045 if (wanted_inner_mode != VOIDmode
6046 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6047 && ((GET_CODE (inner) == MEM
6048 && (inner_mode == wanted_inner_mode
6049 || (! mode_dependent_address_p (XEXP (inner, 0))
6050 && ! MEM_VOLATILE_P (inner))))))
6054 /* The computations below will be correct if the machine is big
6055 endian in both bits and bytes or little endian in bits and bytes.
6056 If it is mixed, we must adjust. */
6058 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6059 adjust OFFSET to compensate. */
6060 if (BYTES_BIG_ENDIAN
6062 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6063 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6065 /* If this is a constant position, we can move to the desired byte. */
6068 offset += pos / BITS_PER_UNIT;
6069 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6072 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6074 && is_mode != wanted_inner_mode)
6075 offset = (GET_MODE_SIZE (is_mode)
6076 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6078 if (offset != 0 || inner_mode != wanted_inner_mode)
6080 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6081 plus_constant (XEXP (inner, 0), offset));
6082 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
6083 MEM_COPY_ATTRIBUTES (newmem, inner);
6088 /* If INNER is not memory, we can always get it into the proper mode. If we
6089 are changing its mode, POS must be a constant and smaller than the size
6091 else if (GET_CODE (inner) != MEM)
6093 if (GET_MODE (inner) != wanted_inner_mode
6095 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6098 inner = force_to_mode (inner, wanted_inner_mode,
6100 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6101 ? GET_MODE_MASK (wanted_inner_mode)
6102 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
6106 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6107 have to zero extend. Otherwise, we can just use a SUBREG. */
6109 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6111 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6113 /* If we know that no extraneous bits are set, and that the high
6114 bit is not set, convert extraction to cheaper one - eighter
6115 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6117 if (flag_expensive_optimizations
6118 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6119 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6120 & ~ (((unsigned HOST_WIDE_INT)
6121 GET_MODE_MASK (GET_MODE (pos_rtx)))
6125 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6127 /* Preffer ZERO_EXTENSION, since it gives more information to
6129 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6134 else if (pos_rtx != 0
6135 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6136 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6138 /* Make POS_RTX unless we already have it and it is correct. If we don't
6139 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6141 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6142 pos_rtx = orig_pos_rtx;
6144 else if (pos_rtx == 0)
6145 pos_rtx = GEN_INT (pos);
6147 /* Make the required operation. See if we can use existing rtx. */
6148 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6149 extraction_mode, inner, GEN_INT (len), pos_rtx);
6151 new = gen_lowpart_for_combine (mode, new);
6156 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6157 with any other operations in X. Return X without that shift if so. */
6160 extract_left_shift (x, count)
6164 enum rtx_code code = GET_CODE (x);
6165 enum machine_mode mode = GET_MODE (x);
6171 /* This is the shift itself. If it is wide enough, we will return
6172 either the value being shifted if the shift count is equal to
6173 COUNT or a shift for the difference. */
6174 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6175 && INTVAL (XEXP (x, 1)) >= count)
6176 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6177 INTVAL (XEXP (x, 1)) - count);
6181 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6182 return gen_unary (code, mode, mode, tem);
6186 case PLUS: case IOR: case XOR: case AND:
6187 /* If we can safely shift this constant and we find the inner shift,
6188 make a new operation. */
6189 if (GET_CODE (XEXP (x,1)) == CONST_INT
6190 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6191 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6192 return gen_binary (code, mode, tem,
6193 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6204 /* Look at the expression rooted at X. Look for expressions
6205 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6206 Form these expressions.
6208 Return the new rtx, usually just X.
6210 Also, for machines like the Vax that don't have logical shift insns,
6211 try to convert logical to arithmetic shift operations in cases where
6212 they are equivalent. This undoes the canonicalizations to logical
6213 shifts done elsewhere.
6215 We try, as much as possible, to re-use rtl expressions to save memory.
6217 IN_CODE says what kind of expression we are processing. Normally, it is
6218 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6219 being kludges), it is MEM. When processing the arguments of a comparison
6220 or a COMPARE against zero, it is COMPARE. */
6223 make_compound_operation (x, in_code)
6225 enum rtx_code in_code;
6227 enum rtx_code code = GET_CODE (x);
6228 enum machine_mode mode = GET_MODE (x);
6229 int mode_width = GET_MODE_BITSIZE (mode);
6231 enum rtx_code next_code;
6237 /* Select the code to be used in recursive calls. Once we are inside an
6238 address, we stay there. If we have a comparison, set to COMPARE,
6239 but once inside, go back to our default of SET. */
6241 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6242 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6243 && XEXP (x, 1) == const0_rtx) ? COMPARE
6244 : in_code == COMPARE ? SET : in_code);
6246 /* Process depending on the code of this operation. If NEW is set
6247 non-zero, it will be returned. */
6252 /* Convert shifts by constants into multiplications if inside
6254 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6255 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6256 && INTVAL (XEXP (x, 1)) >= 0)
6258 new = make_compound_operation (XEXP (x, 0), next_code);
6259 new = gen_rtx_combine (MULT, mode, new,
6260 GEN_INT ((HOST_WIDE_INT) 1
6261 << INTVAL (XEXP (x, 1))));
6266 /* If the second operand is not a constant, we can't do anything
6268 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6271 /* If the constant is a power of two minus one and the first operand
6272 is a logical right shift, make an extraction. */
6273 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6274 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6276 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6277 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6278 0, in_code == COMPARE);
6281 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6282 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6283 && subreg_lowpart_p (XEXP (x, 0))
6284 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6285 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6287 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6289 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6290 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6291 0, in_code == COMPARE);
6293 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6294 else if ((GET_CODE (XEXP (x, 0)) == XOR
6295 || GET_CODE (XEXP (x, 0)) == IOR)
6296 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6297 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6298 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6300 /* Apply the distributive law, and then try to make extractions. */
6301 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6302 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6304 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6306 new = make_compound_operation (new, in_code);
6309 /* If we are have (and (rotate X C) M) and C is larger than the number
6310 of bits in M, this is an extraction. */
6312 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6313 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6314 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6315 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6317 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6318 new = make_extraction (mode, new,
6319 (GET_MODE_BITSIZE (mode)
6320 - INTVAL (XEXP (XEXP (x, 0), 1))),
6321 NULL_RTX, i, 1, 0, in_code == COMPARE);
6324 /* On machines without logical shifts, if the operand of the AND is
6325 a logical shift and our mask turns off all the propagated sign
6326 bits, we can replace the logical shift with an arithmetic shift. */
6327 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6328 && (lshr_optab->handlers[(int) mode].insn_code
6329 == CODE_FOR_nothing)
6330 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6331 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6332 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6333 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6334 && mode_width <= HOST_BITS_PER_WIDE_INT)
6336 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6338 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6339 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6341 gen_rtx_combine (ASHIFTRT, mode,
6342 make_compound_operation (XEXP (XEXP (x, 0), 0),
6344 XEXP (XEXP (x, 0), 1)));
6347 /* If the constant is one less than a power of two, this might be
6348 representable by an extraction even if no shift is present.
6349 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6350 we are in a COMPARE. */
6351 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6352 new = make_extraction (mode,
6353 make_compound_operation (XEXP (x, 0),
6355 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6357 /* If we are in a comparison and this is an AND with a power of two,
6358 convert this into the appropriate bit extract. */
6359 else if (in_code == COMPARE
6360 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6361 new = make_extraction (mode,
6362 make_compound_operation (XEXP (x, 0),
6364 i, NULL_RTX, 1, 1, 0, 1);
6369 /* If the sign bit is known to be zero, replace this with an
6370 arithmetic shift. */
6371 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6372 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6373 && mode_width <= HOST_BITS_PER_WIDE_INT
6374 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6376 new = gen_rtx_combine (ASHIFTRT, mode,
6377 make_compound_operation (XEXP (x, 0),
6383 /* ... fall through ... */
6389 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6390 this is a SIGN_EXTRACT. */
6391 if (GET_CODE (rhs) == CONST_INT
6392 && GET_CODE (lhs) == ASHIFT
6393 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6394 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6396 new = make_compound_operation (XEXP (lhs, 0), next_code);
6397 new = make_extraction (mode, new,
6398 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6399 NULL_RTX, mode_width - INTVAL (rhs),
6400 code == LSHIFTRT, 0, in_code == COMPARE);
6403 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6404 If so, try to merge the shifts into a SIGN_EXTEND. We could
6405 also do this for some cases of SIGN_EXTRACT, but it doesn't
6406 seem worth the effort; the case checked for occurs on Alpha. */
6408 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6409 && ! (GET_CODE (lhs) == SUBREG
6410 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6411 && GET_CODE (rhs) == CONST_INT
6412 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6413 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6414 new = make_extraction (mode, make_compound_operation (new, next_code),
6415 0, NULL_RTX, mode_width - INTVAL (rhs),
6416 code == LSHIFTRT, 0, in_code == COMPARE);
6421 /* Call ourselves recursively on the inner expression. If we are
6422 narrowing the object and it has a different RTL code from
6423 what it originally did, do this SUBREG as a force_to_mode. */
6425 tem = make_compound_operation (SUBREG_REG (x), in_code);
6426 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6427 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6428 && subreg_lowpart_p (x))
6430 rtx newer = force_to_mode (tem, mode,
6431 GET_MODE_MASK (mode), NULL_RTX, 0);
6433 /* If we have something other than a SUBREG, we might have
6434 done an expansion, so rerun outselves. */
6435 if (GET_CODE (newer) != SUBREG)
6436 newer = make_compound_operation (newer, in_code);
6441 /* If this is a paradoxical subreg, and the new code is a sign or
6442 zero extension, omit the subreg and widen the extension. If it
6443 is a regular subreg, we can still get rid of the subreg by not
6444 widening so much, or in fact removing the extension entirely. */
6445 if ((GET_CODE (tem) == SIGN_EXTEND
6446 || GET_CODE (tem) == ZERO_EXTEND)
6447 && subreg_lowpart_p (x))
6449 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6450 || (GET_MODE_SIZE (mode) >
6451 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6452 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6454 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6465 x = gen_lowpart_for_combine (mode, new);
6466 code = GET_CODE (x);
6469 /* Now recursively process each operand of this operation. */
6470 fmt = GET_RTX_FORMAT (code);
6471 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6474 new = make_compound_operation (XEXP (x, i), next_code);
6475 SUBST (XEXP (x, i), new);
6481 /* Given M see if it is a value that would select a field of bits
6482 within an item, but not the entire word. Return -1 if not.
6483 Otherwise, return the starting position of the field, where 0 is the
6486 *PLEN is set to the length of the field. */
6489 get_pos_from_mask (m, plen)
6490 unsigned HOST_WIDE_INT m;
6493 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6494 int pos = exact_log2 (m & - m);
6499 /* Now shift off the low-order zero bits and see if we have a power of
6501 *plen = exact_log2 ((m >> pos) + 1);
6509 /* See if X can be simplified knowing that we will only refer to it in
6510 MODE and will only refer to those bits that are nonzero in MASK.
6511 If other bits are being computed or if masking operations are done
6512 that select a superset of the bits in MASK, they can sometimes be
6515 Return a possibly simplified expression, but always convert X to
6516 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6518 Also, if REG is non-zero and X is a register equal in value to REG,
6521 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6522 are all off in X. This is used when X will be complemented, by either
6523 NOT, NEG, or XOR. */
6526 force_to_mode (x, mode, mask, reg, just_select)
6528 enum machine_mode mode;
6529 unsigned HOST_WIDE_INT mask;
6533 enum rtx_code code = GET_CODE (x);
6534 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6535 enum machine_mode op_mode;
6536 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6539 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6540 code below will do the wrong thing since the mode of such an
6541 expression is VOIDmode.
6543 Also do nothing if X is a CLOBBER; this can happen if X was
6544 the return value from a call to gen_lowpart_for_combine. */
6545 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6548 /* We want to perform the operation is its present mode unless we know
6549 that the operation is valid in MODE, in which case we do the operation
6551 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6552 && code_to_optab[(int) code] != 0
6553 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6554 != CODE_FOR_nothing))
6555 ? mode : GET_MODE (x));
6557 /* It is not valid to do a right-shift in a narrower mode
6558 than the one it came in with. */
6559 if ((code == LSHIFTRT || code == ASHIFTRT)
6560 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6561 op_mode = GET_MODE (x);
6563 /* Truncate MASK to fit OP_MODE. */
6565 mask &= GET_MODE_MASK (op_mode);
6567 /* When we have an arithmetic operation, or a shift whose count we
6568 do not know, we need to assume that all bit the up to the highest-order
6569 bit in MASK will be needed. This is how we form such a mask. */
6571 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6572 ? GET_MODE_MASK (op_mode)
6573 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6575 fuller_mask = ~ (HOST_WIDE_INT) 0;
6577 /* Determine what bits of X are guaranteed to be (non)zero. */
6578 nonzero = nonzero_bits (x, mode);
6580 /* If none of the bits in X are needed, return a zero. */
6581 if (! just_select && (nonzero & mask) == 0)
6584 /* If X is a CONST_INT, return a new one. Do this here since the
6585 test below will fail. */
6586 if (GET_CODE (x) == CONST_INT)
6588 HOST_WIDE_INT cval = INTVAL (x) & mask;
6589 int width = GET_MODE_BITSIZE (mode);
6591 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6592 number, sign extend it. */
6593 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6594 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6595 cval |= (HOST_WIDE_INT) -1 << width;
6597 return GEN_INT (cval);
6600 /* If X is narrower than MODE and we want all the bits in X's mode, just
6601 get X in the proper mode. */
6602 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6603 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6604 return gen_lowpart_for_combine (mode, x);
6606 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6607 MASK are already known to be zero in X, we need not do anything. */
6608 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6614 /* If X is a (clobber (const_int)), return it since we know we are
6615 generating something that won't match. */
6619 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6620 spanned the boundary of the MEM. If we are now masking so it is
6621 within that boundary, we don't need the USE any more. */
6622 if (! BITS_BIG_ENDIAN
6623 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6624 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6631 x = expand_compound_operation (x);
6632 if (GET_CODE (x) != code)
6633 return force_to_mode (x, mode, mask, reg, next_select);
6637 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6638 || rtx_equal_p (reg, get_last_value (x))))
6643 if (subreg_lowpart_p (x)
6644 /* We can ignore the effect of this SUBREG if it narrows the mode or
6645 if the constant masks to zero all the bits the mode doesn't
6647 && ((GET_MODE_SIZE (GET_MODE (x))
6648 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6650 & GET_MODE_MASK (GET_MODE (x))
6651 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6652 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6656 /* If this is an AND with a constant, convert it into an AND
6657 whose constant is the AND of that constant with MASK. If it
6658 remains an AND of MASK, delete it since it is redundant. */
6660 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6662 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6663 mask & INTVAL (XEXP (x, 1)));
6665 /* If X is still an AND, see if it is an AND with a mask that
6666 is just some low-order bits. If so, and it is MASK, we don't
6669 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6670 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6673 /* If it remains an AND, try making another AND with the bits
6674 in the mode mask that aren't in MASK turned on. If the
6675 constant in the AND is wide enough, this might make a
6676 cheaper constant. */
6678 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6679 && GET_MODE_MASK (GET_MODE (x)) != mask
6680 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6682 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6683 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6684 int width = GET_MODE_BITSIZE (GET_MODE (x));
6687 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6688 number, sign extend it. */
6689 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6690 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6691 cval |= (HOST_WIDE_INT) -1 << width;
6693 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6694 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6704 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6705 low-order bits (as in an alignment operation) and FOO is already
6706 aligned to that boundary, mask C1 to that boundary as well.
6707 This may eliminate that PLUS and, later, the AND. */
6710 int width = GET_MODE_BITSIZE (mode);
6711 unsigned HOST_WIDE_INT smask = mask;
6713 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6714 number, sign extend it. */
6716 if (width < HOST_BITS_PER_WIDE_INT
6717 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6718 smask |= (HOST_WIDE_INT) -1 << width;
6720 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6721 && exact_log2 (- smask) >= 0)
6725 && (XEXP (x, 0) == stack_pointer_rtx
6726 || XEXP (x, 0) == frame_pointer_rtx))
6728 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6729 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6731 sp_mask &= ~ (sp_alignment - 1);
6732 if ((sp_mask & ~ smask) == 0
6733 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6734 return force_to_mode (plus_constant (XEXP (x, 0),
6735 ((INTVAL (XEXP (x, 1)) -
6736 STACK_BIAS) & smask)
6738 mode, smask, reg, next_select);
6741 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6742 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6743 return force_to_mode (plus_constant (XEXP (x, 0),
6744 (INTVAL (XEXP (x, 1))
6746 mode, smask, reg, next_select);
6750 /* ... fall through ... */
6754 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6755 most significant bit in MASK since carries from those bits will
6756 affect the bits we are interested in. */
6762 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6763 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6764 operation which may be a bitfield extraction. Ensure that the
6765 constant we form is not wider than the mode of X. */
6767 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6768 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6769 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6770 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6771 && GET_CODE (XEXP (x, 1)) == CONST_INT
6772 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6773 + floor_log2 (INTVAL (XEXP (x, 1))))
6774 < GET_MODE_BITSIZE (GET_MODE (x)))
6775 && (INTVAL (XEXP (x, 1))
6776 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6778 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6779 << INTVAL (XEXP (XEXP (x, 0), 1)));
6780 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6781 XEXP (XEXP (x, 0), 0), temp);
6782 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6783 XEXP (XEXP (x, 0), 1));
6784 return force_to_mode (x, mode, mask, reg, next_select);
6788 /* For most binary operations, just propagate into the operation and
6789 change the mode if we have an operation of that mode. */
6791 op0 = gen_lowpart_for_combine (op_mode,
6792 force_to_mode (XEXP (x, 0), mode, mask,
6794 op1 = gen_lowpart_for_combine (op_mode,
6795 force_to_mode (XEXP (x, 1), mode, mask,
6798 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6799 MASK since OP1 might have been sign-extended but we never want
6800 to turn on extra bits, since combine might have previously relied
6801 on them being off. */
6802 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6803 && (INTVAL (op1) & mask) != 0)
6804 op1 = GEN_INT (INTVAL (op1) & mask);
6806 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6807 x = gen_binary (code, op_mode, op0, op1);
6811 /* For left shifts, do the same, but just for the first operand.
6812 However, we cannot do anything with shifts where we cannot
6813 guarantee that the counts are smaller than the size of the mode
6814 because such a count will have a different meaning in a
6817 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6818 && INTVAL (XEXP (x, 1)) >= 0
6819 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6820 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6821 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6822 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6825 /* If the shift count is a constant and we can do arithmetic in
6826 the mode of the shift, refine which bits we need. Otherwise, use the
6827 conservative form of the mask. */
6828 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6829 && INTVAL (XEXP (x, 1)) >= 0
6830 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6831 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6832 mask >>= INTVAL (XEXP (x, 1));
6836 op0 = gen_lowpart_for_combine (op_mode,
6837 force_to_mode (XEXP (x, 0), op_mode,
6838 mask, reg, next_select));
6840 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6841 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6845 /* Here we can only do something if the shift count is a constant,
6846 this shift constant is valid for the host, and we can do arithmetic
6849 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6850 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6851 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6853 rtx inner = XEXP (x, 0);
6854 unsigned HOST_WIDE_INT inner_mask;
6856 /* Select the mask of the bits we need for the shift operand. */
6857 inner_mask = mask << INTVAL (XEXP (x, 1));
6859 /* We can only change the mode of the shift if we can do arithmetic
6860 in the mode of the shift and INNER_MASK is no wider than the
6861 width of OP_MODE. */
6862 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6863 || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6864 op_mode = GET_MODE (x);
6866 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6868 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6869 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6872 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6873 shift and AND produces only copies of the sign bit (C2 is one less
6874 than a power of two), we can do this with just a shift. */
6876 if (GET_CODE (x) == LSHIFTRT
6877 && GET_CODE (XEXP (x, 1)) == CONST_INT
6878 && ((INTVAL (XEXP (x, 1))
6879 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6880 >= GET_MODE_BITSIZE (GET_MODE (x)))
6881 && exact_log2 (mask + 1) >= 0
6882 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6883 >= exact_log2 (mask + 1)))
6884 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6885 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6886 - exact_log2 (mask + 1)));
6891 /* If we are just looking for the sign bit, we don't need this shift at
6892 all, even if it has a variable count. */
6893 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6894 && (mask == ((unsigned HOST_WIDE_INT) 1
6895 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6896 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6898 /* If this is a shift by a constant, get a mask that contains those bits
6899 that are not copies of the sign bit. We then have two cases: If
6900 MASK only includes those bits, this can be a logical shift, which may
6901 allow simplifications. If MASK is a single-bit field not within
6902 those bits, we are requesting a copy of the sign bit and hence can
6903 shift the sign bit to the appropriate location. */
6905 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6906 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6910 /* If the considered data is wider then HOST_WIDE_INT, we can't
6911 represent a mask for all its bits in a single scalar.
6912 But we only care about the lower bits, so calculate these. */
6914 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6916 nonzero = ~ (HOST_WIDE_INT) 0;
6918 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6919 is the number of bits a full-width mask would have set.
6920 We need only shift if these are fewer than nonzero can
6921 hold. If not, we must keep all bits set in nonzero. */
6923 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6924 < HOST_BITS_PER_WIDE_INT)
6925 nonzero >>= INTVAL (XEXP (x, 1))
6926 + HOST_BITS_PER_WIDE_INT
6927 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6931 nonzero = GET_MODE_MASK (GET_MODE (x));
6932 nonzero >>= INTVAL (XEXP (x, 1));
6935 if ((mask & ~ nonzero) == 0
6936 || (i = exact_log2 (mask)) >= 0)
6938 x = simplify_shift_const
6939 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6940 i < 0 ? INTVAL (XEXP (x, 1))
6941 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6943 if (GET_CODE (x) != ASHIFTRT)
6944 return force_to_mode (x, mode, mask, reg, next_select);
6948 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6949 even if the shift count isn't a constant. */
6951 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6955 /* If this is a zero- or sign-extension operation that just affects bits
6956 we don't care about, remove it. Be sure the call above returned
6957 something that is still a shift. */
6959 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6960 && GET_CODE (XEXP (x, 1)) == CONST_INT
6961 && INTVAL (XEXP (x, 1)) >= 0
6962 && (INTVAL (XEXP (x, 1))
6963 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6964 && GET_CODE (XEXP (x, 0)) == ASHIFT
6965 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6966 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6967 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6974 /* If the shift count is constant and we can do computations
6975 in the mode of X, compute where the bits we care about are.
6976 Otherwise, we can't do anything. Don't change the mode of
6977 the shift or propagate MODE into the shift, though. */
6978 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6979 && INTVAL (XEXP (x, 1)) >= 0)
6981 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6982 GET_MODE (x), GEN_INT (mask),
6984 if (temp && GET_CODE(temp) == CONST_INT)
6986 force_to_mode (XEXP (x, 0), GET_MODE (x),
6987 INTVAL (temp), reg, next_select));
6992 /* If we just want the low-order bit, the NEG isn't needed since it
6993 won't change the low-order bit. */
6995 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6997 /* We need any bits less significant than the most significant bit in
6998 MASK since carries from those bits will affect the bits we are
7004 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7005 same as the XOR case above. Ensure that the constant we form is not
7006 wider than the mode of X. */
7008 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7009 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7010 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7011 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7012 < GET_MODE_BITSIZE (GET_MODE (x)))
7013 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7015 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7016 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7017 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7019 return force_to_mode (x, mode, mask, reg, next_select);
7022 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7023 use the full mask inside the NOT. */
7027 op0 = gen_lowpart_for_combine (op_mode,
7028 force_to_mode (XEXP (x, 0), mode, mask,
7030 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7031 x = gen_unary (code, op_mode, op_mode, op0);
7035 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7036 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7037 which is equal to STORE_FLAG_VALUE. */
7038 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7039 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7040 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7041 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7046 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7047 written in a narrower mode. We play it safe and do not do so. */
7050 gen_lowpart_for_combine (GET_MODE (x),
7051 force_to_mode (XEXP (x, 1), mode,
7052 mask, reg, next_select)));
7054 gen_lowpart_for_combine (GET_MODE (x),
7055 force_to_mode (XEXP (x, 2), mode,
7056 mask, reg,next_select)));
7063 /* Ensure we return a value of the proper mode. */
7064 return gen_lowpart_for_combine (mode, x);
7067 /* Return nonzero if X is an expression that has one of two values depending on
7068 whether some other value is zero or nonzero. In that case, we return the
7069 value that is being tested, *PTRUE is set to the value if the rtx being
7070 returned has a nonzero value, and *PFALSE is set to the other alternative.
7072 If we return zero, we set *PTRUE and *PFALSE to X. */
7075 if_then_else_cond (x, ptrue, pfalse)
7077 rtx *ptrue, *pfalse;
7079 enum machine_mode mode = GET_MODE (x);
7080 enum rtx_code code = GET_CODE (x);
7081 int size = GET_MODE_BITSIZE (mode);
7082 rtx cond0, cond1, true0, true1, false0, false1;
7083 unsigned HOST_WIDE_INT nz;
7085 /* If we are comparing a value against zero, we are done. */
7086 if ((code == NE || code == EQ)
7087 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7089 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7090 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7094 /* If this is a unary operation whose operand has one of two values, apply
7095 our opcode to compute those values. */
7096 else if (GET_RTX_CLASS (code) == '1'
7097 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7099 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7100 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7104 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7105 make can't possibly match and would suppress other optimizations. */
7106 else if (code == COMPARE)
7109 /* If this is a binary operation, see if either side has only one of two
7110 values. If either one does or if both do and they are conditional on
7111 the same value, compute the new true and false values. */
7112 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7113 || GET_RTX_CLASS (code) == '<')
7115 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7116 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7118 if ((cond0 != 0 || cond1 != 0)
7119 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7121 /* If if_then_else_cond returned zero, then true/false are the
7122 same rtl. We must copy one of them to prevent invalid rtl
7125 true0 = copy_rtx (true0);
7126 else if (cond1 == 0)
7127 true1 = copy_rtx (true1);
7129 *ptrue = gen_binary (code, mode, true0, true1);
7130 *pfalse = gen_binary (code, mode, false0, false1);
7131 return cond0 ? cond0 : cond1;
7134 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7135 operands is zero when the other is non-zero, and vice-versa,
7136 and STORE_FLAG_VALUE is 1 or -1. */
7138 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7139 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7141 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7143 rtx op0 = XEXP (XEXP (x, 0), 1);
7144 rtx op1 = XEXP (XEXP (x, 1), 1);
7146 cond0 = XEXP (XEXP (x, 0), 0);
7147 cond1 = XEXP (XEXP (x, 1), 0);
7149 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7150 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7151 && reversible_comparison_p (cond1)
7152 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7153 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7154 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7155 || ((swap_condition (GET_CODE (cond0))
7156 == reverse_condition (GET_CODE (cond1)))
7157 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7158 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7159 && ! side_effects_p (x))
7161 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7162 *pfalse = gen_binary (MULT, mode,
7164 ? gen_unary (NEG, mode, mode, op1) : op1),
7170 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7172 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7173 && (code == MULT || code == AND || code == UMIN)
7174 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7176 cond0 = XEXP (XEXP (x, 0), 0);
7177 cond1 = XEXP (XEXP (x, 1), 0);
7179 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7180 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7181 && reversible_comparison_p (cond1)
7182 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7183 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7184 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7185 || ((swap_condition (GET_CODE (cond0))
7186 == reverse_condition (GET_CODE (cond1)))
7187 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7188 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7189 && ! side_effects_p (x))
7191 *ptrue = *pfalse = const0_rtx;
7197 else if (code == IF_THEN_ELSE)
7199 /* If we have IF_THEN_ELSE already, extract the condition and
7200 canonicalize it if it is NE or EQ. */
7201 cond0 = XEXP (x, 0);
7202 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7203 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7204 return XEXP (cond0, 0);
7205 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7207 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7208 return XEXP (cond0, 0);
7214 /* If X is a normal SUBREG with both inner and outer modes integral,
7215 we can narrow both the true and false values of the inner expression,
7216 if there is a condition. */
7217 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7218 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7219 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7220 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7223 if ((GET_CODE (SUBREG_REG (x)) == REG
7224 || GET_CODE (SUBREG_REG (x)) == MEM
7225 || CONSTANT_P (SUBREG_REG (x)))
7226 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7227 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7229 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7230 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7232 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7234 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7239 /* If X is a constant, this isn't special and will cause confusions
7240 if we treat it as such. Likewise if it is equivalent to a constant. */
7241 else if (CONSTANT_P (x)
7242 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7245 /* If X is known to be either 0 or -1, those are the true and
7246 false values when testing X. */
7247 else if (num_sign_bit_copies (x, mode) == size)
7249 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7253 /* Likewise for 0 or a single bit. */
7254 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7256 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7260 /* Otherwise fail; show no condition with true and false values the same. */
7261 *ptrue = *pfalse = x;
7265 /* Return the value of expression X given the fact that condition COND
7266 is known to be true when applied to REG as its first operand and VAL
7267 as its second. X is known to not be shared and so can be modified in
7270 We only handle the simplest cases, and specifically those cases that
7271 arise with IF_THEN_ELSE expressions. */
7274 known_cond (x, cond, reg, val)
7279 enum rtx_code code = GET_CODE (x);
7284 if (side_effects_p (x))
7287 if (cond == EQ && rtx_equal_p (x, reg))
7290 /* If X is (abs REG) and we know something about REG's relationship
7291 with zero, we may be able to simplify this. */
7293 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7296 case GE: case GT: case EQ:
7299 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7305 /* The only other cases we handle are MIN, MAX, and comparisons if the
7306 operands are the same as REG and VAL. */
7308 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7310 if (rtx_equal_p (XEXP (x, 0), val))
7311 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7313 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7315 if (GET_RTX_CLASS (code) == '<')
7317 if (comparison_dominates_p (cond, code))
7318 return const_true_rtx;
7320 code = reverse_condition (code);
7322 && comparison_dominates_p (cond, code))
7327 else if (code == SMAX || code == SMIN
7328 || code == UMIN || code == UMAX)
7330 int unsignedp = (code == UMIN || code == UMAX);
7332 if (code == SMAX || code == UMAX)
7333 cond = reverse_condition (cond);
7338 return unsignedp ? x : XEXP (x, 1);
7340 return unsignedp ? x : XEXP (x, 0);
7342 return unsignedp ? XEXP (x, 1) : x;
7344 return unsignedp ? XEXP (x, 0) : x;
7352 fmt = GET_RTX_FORMAT (code);
7353 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7356 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7357 else if (fmt[i] == 'E')
7358 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7359 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7366 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7367 assignment as a field assignment. */
7370 rtx_equal_for_field_assignment_p (x, y)
7374 if (x == y || rtx_equal_p (x, y))
7377 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7380 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7381 Note that all SUBREGs of MEM are paradoxical; otherwise they
7382 would have been rewritten. */
7383 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7384 && GET_CODE (SUBREG_REG (y)) == MEM
7385 && rtx_equal_p (SUBREG_REG (y),
7386 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7389 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7390 && GET_CODE (SUBREG_REG (x)) == MEM
7391 && rtx_equal_p (SUBREG_REG (x),
7392 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7395 /* We used to see if get_last_value of X and Y were the same but that's
7396 not correct. In one direction, we'll cause the assignment to have
7397 the wrong destination and in the case, we'll import a register into this
7398 insn that might have already have been dead. So fail if none of the
7399 above cases are true. */
7403 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7404 Return that assignment if so.
7406 We only handle the most common cases. */
7409 make_field_assignment (x)
7412 rtx dest = SET_DEST (x);
7413 rtx src = SET_SRC (x);
7419 enum machine_mode mode;
7421 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7422 a clear of a one-bit field. We will have changed it to
7423 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7426 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7427 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7428 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7429 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7431 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7434 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7438 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7439 && subreg_lowpart_p (XEXP (src, 0))
7440 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7441 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7442 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7443 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7444 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7446 assign = make_extraction (VOIDmode, dest, 0,
7447 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7450 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7454 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7456 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7457 && XEXP (XEXP (src, 0), 0) == const1_rtx
7458 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7460 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7463 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7467 /* The other case we handle is assignments into a constant-position
7468 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7469 a mask that has all one bits except for a group of zero bits and
7470 OTHER is known to have zeros where C1 has ones, this is such an
7471 assignment. Compute the position and length from C1. Shift OTHER
7472 to the appropriate position, force it to the required mode, and
7473 make the extraction. Check for the AND in both operands. */
7475 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7478 rhs = expand_compound_operation (XEXP (src, 0));
7479 lhs = expand_compound_operation (XEXP (src, 1));
7481 if (GET_CODE (rhs) == AND
7482 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7483 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7484 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7485 else if (GET_CODE (lhs) == AND
7486 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7487 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7488 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7492 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7493 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7494 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7495 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7498 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7502 /* The mode to use for the source is the mode of the assignment, or of
7503 what is inside a possible STRICT_LOW_PART. */
7504 mode = (GET_CODE (assign) == STRICT_LOW_PART
7505 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7507 /* Shift OTHER right POS places and make it the source, restricting it
7508 to the proper length and mode. */
7510 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7511 GET_MODE (src), other, pos),
7513 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7514 ? GET_MODE_MASK (mode)
7515 : ((HOST_WIDE_INT) 1 << len) - 1,
7518 return gen_rtx_combine (SET, VOIDmode, assign, src);
7521 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7525 apply_distributive_law (x)
7528 enum rtx_code code = GET_CODE (x);
7529 rtx lhs, rhs, other;
7531 enum rtx_code inner_code;
7533 /* Distributivity is not true for floating point.
7534 It can change the value. So don't do it.
7535 -- rms and moshier@world.std.com. */
7536 if (FLOAT_MODE_P (GET_MODE (x)))
7539 /* The outer operation can only be one of the following: */
7540 if (code != IOR && code != AND && code != XOR
7541 && code != PLUS && code != MINUS)
7544 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7546 /* If either operand is a primitive we can't do anything, so get out
7548 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7549 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7552 lhs = expand_compound_operation (lhs);
7553 rhs = expand_compound_operation (rhs);
7554 inner_code = GET_CODE (lhs);
7555 if (inner_code != GET_CODE (rhs))
7558 /* See if the inner and outer operations distribute. */
7565 /* These all distribute except over PLUS. */
7566 if (code == PLUS || code == MINUS)
7571 if (code != PLUS && code != MINUS)
7576 /* This is also a multiply, so it distributes over everything. */
7580 /* Non-paradoxical SUBREGs distributes over all operations, provided
7581 the inner modes and word numbers are the same, this is an extraction
7582 of a low-order part, we don't convert an fp operation to int or
7583 vice versa, and we would not be converting a single-word
7584 operation into a multi-word operation. The latter test is not
7585 required, but it prevents generating unneeded multi-word operations.
7586 Some of the previous tests are redundant given the latter test, but
7587 are retained because they are required for correctness.
7589 We produce the result slightly differently in this case. */
7591 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7592 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7593 || ! subreg_lowpart_p (lhs)
7594 || (GET_MODE_CLASS (GET_MODE (lhs))
7595 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7596 || (GET_MODE_SIZE (GET_MODE (lhs))
7597 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7598 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7601 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7602 SUBREG_REG (lhs), SUBREG_REG (rhs));
7603 return gen_lowpart_for_combine (GET_MODE (x), tem);
7609 /* Set LHS and RHS to the inner operands (A and B in the example
7610 above) and set OTHER to the common operand (C in the example).
7611 These is only one way to do this unless the inner operation is
7613 if (GET_RTX_CLASS (inner_code) == 'c'
7614 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7615 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7616 else if (GET_RTX_CLASS (inner_code) == 'c'
7617 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7618 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7619 else if (GET_RTX_CLASS (inner_code) == 'c'
7620 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7621 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7622 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7623 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7627 /* Form the new inner operation, seeing if it simplifies first. */
7628 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7630 /* There is one exception to the general way of distributing:
7631 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7632 if (code == XOR && inner_code == IOR)
7635 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7638 /* We may be able to continuing distributing the result, so call
7639 ourselves recursively on the inner operation before forming the
7640 outer operation, which we return. */
7641 return gen_binary (inner_code, GET_MODE (x),
7642 apply_distributive_law (tem), other);
7645 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7648 Return an equivalent form, if different from X. Otherwise, return X. If
7649 X is zero, we are to always construct the equivalent form. */
7652 simplify_and_const_int (x, mode, varop, constop)
7654 enum machine_mode mode;
7656 unsigned HOST_WIDE_INT constop;
7658 unsigned HOST_WIDE_INT nonzero;
7661 /* Simplify VAROP knowing that we will be only looking at some of the
7663 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7665 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7666 CONST_INT, we are done. */
7667 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7670 /* See what bits may be nonzero in VAROP. Unlike the general case of
7671 a call to nonzero_bits, here we don't care about bits outside
7674 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7675 nonzero = trunc_int_for_mode (nonzero, mode);
7677 /* Turn off all bits in the constant that are known to already be zero.
7678 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7679 which is tested below. */
7683 /* If we don't have any bits left, return zero. */
7687 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7688 a power of two, we can replace this with a ASHIFT. */
7689 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7690 && (i = exact_log2 (constop)) >= 0)
7691 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7693 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7694 or XOR, then try to apply the distributive law. This may eliminate
7695 operations if either branch can be simplified because of the AND.
7696 It may also make some cases more complex, but those cases probably
7697 won't match a pattern either with or without this. */
7699 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7701 gen_lowpart_for_combine
7703 apply_distributive_law
7704 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7705 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7706 XEXP (varop, 0), constop),
7707 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7708 XEXP (varop, 1), constop))));
7710 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7711 if we already had one (just check for the simplest cases). */
7712 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7713 && GET_MODE (XEXP (x, 0)) == mode
7714 && SUBREG_REG (XEXP (x, 0)) == varop)
7715 varop = XEXP (x, 0);
7717 varop = gen_lowpart_for_combine (mode, varop);
7719 /* If we can't make the SUBREG, try to return what we were given. */
7720 if (GET_CODE (varop) == CLOBBER)
7721 return x ? x : varop;
7723 /* If we are only masking insignificant bits, return VAROP. */
7724 if (constop == nonzero)
7727 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7728 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7729 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7733 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7734 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7735 SUBST (XEXP (x, 1), GEN_INT (constop));
7737 SUBST (XEXP (x, 0), varop);
7743 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7744 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7745 is less useful. We can't allow both, because that results in exponential
7746 run time recursion. There is a nullstone testcase that triggered
7747 this. This macro avoids accidental uses of num_sign_bit_copies. */
7748 #define num_sign_bit_copies()
7750 /* Given an expression, X, compute which bits in X can be non-zero.
7751 We don't care about bits outside of those defined in MODE.
7753 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7754 a shift, AND, or zero_extract, we can do better. */
7756 static unsigned HOST_WIDE_INT
7757 nonzero_bits (x, mode)
7759 enum machine_mode mode;
7761 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7762 unsigned HOST_WIDE_INT inner_nz;
7764 int mode_width = GET_MODE_BITSIZE (mode);
7767 /* For floating-point values, assume all bits are needed. */
7768 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7771 /* If X is wider than MODE, use its mode instead. */
7772 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7774 mode = GET_MODE (x);
7775 nonzero = GET_MODE_MASK (mode);
7776 mode_width = GET_MODE_BITSIZE (mode);
7779 if (mode_width > HOST_BITS_PER_WIDE_INT)
7780 /* Our only callers in this case look for single bit values. So
7781 just return the mode mask. Those tests will then be false. */
7784 #ifndef WORD_REGISTER_OPERATIONS
7785 /* If MODE is wider than X, but both are a single word for both the host
7786 and target machines, we can compute this from which bits of the
7787 object might be nonzero in its own mode, taking into account the fact
7788 that on many CISC machines, accessing an object in a wider mode
7789 causes the high-order bits to become undefined. So they are
7790 not known to be zero. */
7792 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7793 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7794 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7795 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7797 nonzero &= nonzero_bits (x, GET_MODE (x));
7798 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7803 code = GET_CODE (x);
7807 #ifdef POINTERS_EXTEND_UNSIGNED
7808 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7809 all the bits above ptr_mode are known to be zero. */
7810 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7811 && REGNO_POINTER_FLAG (REGNO (x)))
7812 nonzero &= GET_MODE_MASK (ptr_mode);
7815 #ifdef STACK_BOUNDARY
7816 /* If this is the stack pointer, we may know something about its
7817 alignment. If PUSH_ROUNDING is defined, it is possible for the
7818 stack to be momentarily aligned only to that amount, so we pick
7819 the least alignment. */
7821 /* We can't check for arg_pointer_rtx here, because it is not
7822 guaranteed to have as much alignment as the stack pointer.
7823 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7824 alignment but the argument pointer has only 64 bit alignment. */
7826 if ((x == frame_pointer_rtx
7827 || x == stack_pointer_rtx
7828 || x == hard_frame_pointer_rtx
7829 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7830 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7836 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7838 #ifdef PUSH_ROUNDING
7839 if (REGNO (x) == STACK_POINTER_REGNUM)
7840 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7843 /* We must return here, otherwise we may get a worse result from
7844 one of the choices below. There is nothing useful below as
7845 far as the stack pointer is concerned. */
7846 return nonzero &= ~ (sp_alignment - 1);
7850 /* If X is a register whose nonzero bits value is current, use it.
7851 Otherwise, if X is a register whose value we can find, use that
7852 value. Otherwise, use the previously-computed global nonzero bits
7853 for this register. */
7855 if (reg_last_set_value[REGNO (x)] != 0
7856 && reg_last_set_mode[REGNO (x)] == mode
7857 && (reg_last_set_label[REGNO (x)] == label_tick
7858 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7859 && REG_N_SETS (REGNO (x)) == 1
7860 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7862 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7863 return reg_last_set_nonzero_bits[REGNO (x)];
7865 tem = get_last_value (x);
7869 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7870 /* If X is narrower than MODE and TEM is a non-negative
7871 constant that would appear negative in the mode of X,
7872 sign-extend it for use in reg_nonzero_bits because some
7873 machines (maybe most) will actually do the sign-extension
7874 and this is the conservative approach.
7876 ??? For 2.5, try to tighten up the MD files in this regard
7877 instead of this kludge. */
7879 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7880 && GET_CODE (tem) == CONST_INT
7882 && 0 != (INTVAL (tem)
7883 & ((HOST_WIDE_INT) 1
7884 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7885 tem = GEN_INT (INTVAL (tem)
7886 | ((HOST_WIDE_INT) (-1)
7887 << GET_MODE_BITSIZE (GET_MODE (x))));
7889 return nonzero_bits (tem, mode);
7891 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7892 return reg_nonzero_bits[REGNO (x)] & nonzero;
7897 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7898 /* If X is negative in MODE, sign-extend the value. */
7899 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7900 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7901 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7907 #ifdef LOAD_EXTEND_OP
7908 /* In many, if not most, RISC machines, reading a byte from memory
7909 zeros the rest of the register. Noticing that fact saves a lot
7910 of extra zero-extends. */
7911 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7912 nonzero &= GET_MODE_MASK (GET_MODE (x));
7922 /* If this produces an integer result, we know which bits are set.
7923 Code here used to clear bits outside the mode of X, but that is
7926 if (GET_MODE_CLASS (mode) == MODE_INT
7927 && mode_width <= HOST_BITS_PER_WIDE_INT)
7928 nonzero = STORE_FLAG_VALUE;
7933 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7934 and num_sign_bit_copies. */
7935 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7936 == GET_MODE_BITSIZE (GET_MODE (x)))
7940 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7941 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7946 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7947 and num_sign_bit_copies. */
7948 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7949 == GET_MODE_BITSIZE (GET_MODE (x)))
7955 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7959 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7960 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7961 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7965 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7966 Otherwise, show all the bits in the outer mode but not the inner
7968 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7969 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7971 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7973 & (((HOST_WIDE_INT) 1
7974 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7975 inner_nz |= (GET_MODE_MASK (mode)
7976 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7979 nonzero &= inner_nz;
7983 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7984 & nonzero_bits (XEXP (x, 1), mode));
7988 case UMIN: case UMAX: case SMIN: case SMAX:
7989 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7990 | nonzero_bits (XEXP (x, 1), mode));
7993 case PLUS: case MINUS:
7995 case DIV: case UDIV:
7996 case MOD: case UMOD:
7997 /* We can apply the rules of arithmetic to compute the number of
7998 high- and low-order zero bits of these operations. We start by
7999 computing the width (position of the highest-order non-zero bit)
8000 and the number of low-order zero bits for each value. */
8002 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8003 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8004 int width0 = floor_log2 (nz0) + 1;
8005 int width1 = floor_log2 (nz1) + 1;
8006 int low0 = floor_log2 (nz0 & -nz0);
8007 int low1 = floor_log2 (nz1 & -nz1);
8008 HOST_WIDE_INT op0_maybe_minusp
8009 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8010 HOST_WIDE_INT op1_maybe_minusp
8011 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8012 int result_width = mode_width;
8020 && (XEXP (x, 0) == stack_pointer_rtx
8021 || XEXP (x, 0) == frame_pointer_rtx)
8022 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8024 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8026 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8027 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8028 width0 = floor_log2 (nz0) + 1;
8029 width1 = floor_log2 (nz1) + 1;
8030 low0 = floor_log2 (nz0 & -nz0);
8031 low1 = floor_log2 (nz1 & -nz1);
8034 result_width = MAX (width0, width1) + 1;
8035 result_low = MIN (low0, low1);
8038 result_low = MIN (low0, low1);
8041 result_width = width0 + width1;
8042 result_low = low0 + low1;
8045 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8046 result_width = width0;
8049 result_width = width0;
8052 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8053 result_width = MIN (width0, width1);
8054 result_low = MIN (low0, low1);
8057 result_width = MIN (width0, width1);
8058 result_low = MIN (low0, low1);
8064 if (result_width < mode_width)
8065 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8068 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8073 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8074 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8075 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8079 /* If this is a SUBREG formed for a promoted variable that has
8080 been zero-extended, we know that at least the high-order bits
8081 are zero, though others might be too. */
8083 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8084 nonzero = (GET_MODE_MASK (GET_MODE (x))
8085 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8087 /* If the inner mode is a single word for both the host and target
8088 machines, we can compute this from which bits of the inner
8089 object might be nonzero. */
8090 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8091 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8092 <= HOST_BITS_PER_WIDE_INT))
8094 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8096 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8097 /* If this is a typical RISC machine, we only have to worry
8098 about the way loads are extended. */
8099 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8101 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
8102 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8105 /* On many CISC machines, accessing an object in a wider mode
8106 causes the high-order bits to become undefined. So they are
8107 not known to be zero. */
8108 if (GET_MODE_SIZE (GET_MODE (x))
8109 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8110 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8111 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8120 /* The nonzero bits are in two classes: any bits within MODE
8121 that aren't in GET_MODE (x) are always significant. The rest of the
8122 nonzero bits are those that are significant in the operand of
8123 the shift when shifted the appropriate number of bits. This
8124 shows that high-order bits are cleared by the right shift and
8125 low-order bits by left shifts. */
8126 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8127 && INTVAL (XEXP (x, 1)) >= 0
8128 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8130 enum machine_mode inner_mode = GET_MODE (x);
8131 int width = GET_MODE_BITSIZE (inner_mode);
8132 int count = INTVAL (XEXP (x, 1));
8133 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8134 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8135 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8136 unsigned HOST_WIDE_INT outer = 0;
8138 if (mode_width > width)
8139 outer = (op_nonzero & nonzero & ~ mode_mask);
8141 if (code == LSHIFTRT)
8143 else if (code == ASHIFTRT)
8147 /* If the sign bit may have been nonzero before the shift, we
8148 need to mark all the places it could have been copied to
8149 by the shift as possibly nonzero. */
8150 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8151 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8153 else if (code == ASHIFT)
8156 inner = ((inner << (count % width)
8157 | (inner >> (width - (count % width)))) & mode_mask);
8159 nonzero &= (outer | inner);
8164 /* This is at most the number of bits in the mode. */
8165 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8169 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8170 | nonzero_bits (XEXP (x, 2), mode));
8180 /* See the macro definition above. */
8181 #undef num_sign_bit_copies
8183 /* Return the number of bits at the high-order end of X that are known to
8184 be equal to the sign bit. X will be used in mode MODE; if MODE is
8185 VOIDmode, X will be used in its own mode. The returned value will always
8186 be between 1 and the number of bits in MODE. */
8189 num_sign_bit_copies (x, mode)
8191 enum machine_mode mode;
8193 enum rtx_code code = GET_CODE (x);
8195 int num0, num1, result;
8196 unsigned HOST_WIDE_INT nonzero;
8199 /* If we weren't given a mode, use the mode of X. If the mode is still
8200 VOIDmode, we don't know anything. Likewise if one of the modes is
8203 if (mode == VOIDmode)
8204 mode = GET_MODE (x);
8206 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8209 bitwidth = GET_MODE_BITSIZE (mode);
8211 /* For a smaller object, just ignore the high bits. */
8212 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8213 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
8214 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
8216 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8218 #ifndef WORD_REGISTER_OPERATIONS
8219 /* If this machine does not do all register operations on the entire
8220 register and MODE is wider than the mode of X, we can say nothing
8221 at all about the high-order bits. */
8224 /* Likewise on machines that do, if the mode of the object is smaller
8225 than a word and loads of that size don't sign extend, we can say
8226 nothing about the high order bits. */
8227 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8228 #ifdef LOAD_EXTEND_OP
8229 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8240 #ifdef POINTERS_EXTEND_UNSIGNED
8241 /* If pointers extend signed and this is a pointer in Pmode, say that
8242 all the bits above ptr_mode are known to be sign bit copies. */
8243 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8244 && REGNO_POINTER_FLAG (REGNO (x)))
8245 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8248 if (reg_last_set_value[REGNO (x)] != 0
8249 && reg_last_set_mode[REGNO (x)] == mode
8250 && (reg_last_set_label[REGNO (x)] == label_tick
8251 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8252 && REG_N_SETS (REGNO (x)) == 1
8253 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8255 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8256 return reg_last_set_sign_bit_copies[REGNO (x)];
8258 tem = get_last_value (x);
8260 return num_sign_bit_copies (tem, mode);
8262 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8263 return reg_sign_bit_copies[REGNO (x)];
8267 #ifdef LOAD_EXTEND_OP
8268 /* Some RISC machines sign-extend all loads of smaller than a word. */
8269 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8270 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
8275 /* If the constant is negative, take its 1's complement and remask.
8276 Then see how many zero bits we have. */
8277 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8278 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8279 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8280 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8282 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8285 /* If this is a SUBREG for a promoted object that is sign-extended
8286 and we are looking at it in a wider mode, we know that at least the
8287 high-order bits are known to be sign bit copies. */
8289 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8290 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8291 num_sign_bit_copies (SUBREG_REG (x), mode));
8293 /* For a smaller object, just ignore the high bits. */
8294 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8296 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8297 return MAX (1, (num0
8298 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8302 #ifdef WORD_REGISTER_OPERATIONS
8303 #ifdef LOAD_EXTEND_OP
8304 /* For paradoxical SUBREGs on machines where all register operations
8305 affect the entire register, just look inside. Note that we are
8306 passing MODE to the recursive call, so the number of sign bit copies
8307 will remain relative to that mode, not the inner mode. */
8309 /* This works only if loads sign extend. Otherwise, if we get a
8310 reload for the inner part, it may be loaded from the stack, and
8311 then we lose all sign bit copies that existed before the store
8314 if ((GET_MODE_SIZE (GET_MODE (x))
8315 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8316 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8317 return num_sign_bit_copies (SUBREG_REG (x), mode);
8323 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8324 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
8328 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8329 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8332 /* For a smaller object, just ignore the high bits. */
8333 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8334 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8338 return num_sign_bit_copies (XEXP (x, 0), mode);
8340 case ROTATE: case ROTATERT:
8341 /* If we are rotating left by a number of bits less than the number
8342 of sign bit copies, we can just subtract that amount from the
8344 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8345 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8347 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8348 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8349 : bitwidth - INTVAL (XEXP (x, 1))));
8354 /* In general, this subtracts one sign bit copy. But if the value
8355 is known to be positive, the number of sign bit copies is the
8356 same as that of the input. Finally, if the input has just one bit
8357 that might be nonzero, all the bits are copies of the sign bit. */
8358 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8359 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8360 return num0 > 1 ? num0 - 1 : 1;
8362 nonzero = nonzero_bits (XEXP (x, 0), mode);
8367 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8372 case IOR: case AND: case XOR:
8373 case SMIN: case SMAX: case UMIN: case UMAX:
8374 /* Logical operations will preserve the number of sign-bit copies.
8375 MIN and MAX operations always return one of the operands. */
8376 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8377 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8378 return MIN (num0, num1);
8380 case PLUS: case MINUS:
8381 /* For addition and subtraction, we can have a 1-bit carry. However,
8382 if we are subtracting 1 from a positive number, there will not
8383 be such a carry. Furthermore, if the positive number is known to
8384 be 0 or 1, we know the result is either -1 or 0. */
8386 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8387 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8389 nonzero = nonzero_bits (XEXP (x, 0), mode);
8390 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8391 return (nonzero == 1 || nonzero == 0 ? bitwidth
8392 : bitwidth - floor_log2 (nonzero) - 1);
8395 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8396 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8397 return MAX (1, MIN (num0, num1) - 1);
8400 /* The number of bits of the product is the sum of the number of
8401 bits of both terms. However, unless one of the terms if known
8402 to be positive, we must allow for an additional bit since negating
8403 a negative number can remove one sign bit copy. */
8405 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8406 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8408 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8410 && (bitwidth > HOST_BITS_PER_WIDE_INT
8411 || (((nonzero_bits (XEXP (x, 0), mode)
8412 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8413 && ((nonzero_bits (XEXP (x, 1), mode)
8414 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8417 return MAX (1, result);
8420 /* The result must be <= the first operand. If the first operand
8421 has the high bit set, we know nothing about the number of sign
8423 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8425 else if ((nonzero_bits (XEXP (x, 0), mode)
8426 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8429 return num_sign_bit_copies (XEXP (x, 0), mode);
8432 /* The result must be <= the scond operand. */
8433 return num_sign_bit_copies (XEXP (x, 1), mode);
8436 /* Similar to unsigned division, except that we have to worry about
8437 the case where the divisor is negative, in which case we have
8439 result = num_sign_bit_copies (XEXP (x, 0), mode);
8441 && (bitwidth > HOST_BITS_PER_WIDE_INT
8442 || (nonzero_bits (XEXP (x, 1), mode)
8443 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8449 result = num_sign_bit_copies (XEXP (x, 1), mode);
8451 && (bitwidth > HOST_BITS_PER_WIDE_INT
8452 || (nonzero_bits (XEXP (x, 1), mode)
8453 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8459 /* Shifts by a constant add to the number of bits equal to the
8461 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8462 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8463 && INTVAL (XEXP (x, 1)) > 0)
8464 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8469 /* Left shifts destroy copies. */
8470 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8471 || INTVAL (XEXP (x, 1)) < 0
8472 || INTVAL (XEXP (x, 1)) >= bitwidth)
8475 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8476 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8479 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8480 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8481 return MIN (num0, num1);
8483 case EQ: case NE: case GE: case GT: case LE: case LT:
8484 case GEU: case GTU: case LEU: case LTU:
8485 if (STORE_FLAG_VALUE == -1)
8493 /* If we haven't been able to figure it out by one of the above rules,
8494 see if some of the high-order bits are known to be zero. If so,
8495 count those bits and return one less than that amount. If we can't
8496 safely compute the mask for this mode, always return BITWIDTH. */
8498 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8501 nonzero = nonzero_bits (x, mode);
8502 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8503 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8506 /* Return the number of "extended" bits there are in X, when interpreted
8507 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8508 unsigned quantities, this is the number of high-order zero bits.
8509 For signed quantities, this is the number of copies of the sign bit
8510 minus 1. In both case, this function returns the number of "spare"
8511 bits. For example, if two quantities for which this function returns
8512 at least 1 are added, the addition is known not to overflow.
8514 This function will always return 0 unless called during combine, which
8515 implies that it must be called from a define_split. */
8518 extended_count (x, mode, unsignedp)
8520 enum machine_mode mode;
8523 if (nonzero_sign_valid == 0)
8527 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8528 && (GET_MODE_BITSIZE (mode) - 1
8529 - floor_log2 (nonzero_bits (x, mode))))
8530 : num_sign_bit_copies (x, mode) - 1);
8533 /* This function is called from `simplify_shift_const' to merge two
8534 outer operations. Specifically, we have already found that we need
8535 to perform operation *POP0 with constant *PCONST0 at the outermost
8536 position. We would now like to also perform OP1 with constant CONST1
8537 (with *POP0 being done last).
8539 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8540 the resulting operation. *PCOMP_P is set to 1 if we would need to
8541 complement the innermost operand, otherwise it is unchanged.
8543 MODE is the mode in which the operation will be done. No bits outside
8544 the width of this mode matter. It is assumed that the width of this mode
8545 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8547 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8548 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8549 result is simply *PCONST0.
8551 If the resulting operation cannot be expressed as one operation, we
8552 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8555 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8556 enum rtx_code *pop0;
8557 HOST_WIDE_INT *pconst0;
8559 HOST_WIDE_INT const1;
8560 enum machine_mode mode;
8563 enum rtx_code op0 = *pop0;
8564 HOST_WIDE_INT const0 = *pconst0;
8566 const0 &= GET_MODE_MASK (mode);
8567 const1 &= GET_MODE_MASK (mode);
8569 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8573 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8576 if (op1 == NIL || op0 == SET)
8579 else if (op0 == NIL)
8580 op0 = op1, const0 = const1;
8582 else if (op0 == op1)
8606 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8607 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8610 /* If the two constants aren't the same, we can't do anything. The
8611 remaining six cases can all be done. */
8612 else if (const0 != const1)
8620 /* (a & b) | b == b */
8622 else /* op1 == XOR */
8623 /* (a ^ b) | b == a | b */
8629 /* (a & b) ^ b == (~a) & b */
8630 op0 = AND, *pcomp_p = 1;
8631 else /* op1 == IOR */
8632 /* (a | b) ^ b == a & ~b */
8633 op0 = AND, *pconst0 = ~ const0;
8638 /* (a | b) & b == b */
8640 else /* op1 == XOR */
8641 /* (a ^ b) & b) == (~a) & b */
8648 /* Check for NO-OP cases. */
8649 const0 &= GET_MODE_MASK (mode);
8651 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8653 else if (const0 == 0 && op0 == AND)
8655 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8659 /* ??? Slightly redundant with the above mask, but not entirely.
8660 Moving this above means we'd have to sign-extend the mode mask
8661 for the final test. */
8662 const0 = trunc_int_for_mode (const0, mode);
8670 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8671 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8672 that we started with.
8674 The shift is normally computed in the widest mode we find in VAROP, as
8675 long as it isn't a different number of words than RESULT_MODE. Exceptions
8676 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8679 simplify_shift_const (x, code, result_mode, varop, count)
8682 enum machine_mode result_mode;
8686 enum rtx_code orig_code = code;
8687 int orig_count = count;
8688 enum machine_mode mode = result_mode;
8689 enum machine_mode shift_mode, tmode;
8691 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8692 /* We form (outer_op (code varop count) (outer_const)). */
8693 enum rtx_code outer_op = NIL;
8694 HOST_WIDE_INT outer_const = 0;
8696 int complement_p = 0;
8699 /* If we were given an invalid count, don't do anything except exactly
8700 what was requested. */
8702 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8707 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8710 /* Unless one of the branches of the `if' in this loop does a `continue',
8711 we will `break' the loop after the `if'. */
8715 /* If we have an operand of (clobber (const_int 0)), just return that
8717 if (GET_CODE (varop) == CLOBBER)
8720 /* If we discovered we had to complement VAROP, leave. Making a NOT
8721 here would cause an infinite loop. */
8725 /* Convert ROTATERT to ROTATE. */
8726 if (code == ROTATERT)
8727 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8729 /* We need to determine what mode we will do the shift in. If the
8730 shift is a right shift or a ROTATE, we must always do it in the mode
8731 it was originally done in. Otherwise, we can do it in MODE, the
8732 widest mode encountered. */
8734 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8735 ? result_mode : mode);
8737 /* Handle cases where the count is greater than the size of the mode
8738 minus 1. For ASHIFT, use the size minus one as the count (this can
8739 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8740 take the count modulo the size. For other shifts, the result is
8743 Since these shifts are being produced by the compiler by combining
8744 multiple operations, each of which are defined, we know what the
8745 result is supposed to be. */
8747 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8749 if (code == ASHIFTRT)
8750 count = GET_MODE_BITSIZE (shift_mode) - 1;
8751 else if (code == ROTATE || code == ROTATERT)
8752 count %= GET_MODE_BITSIZE (shift_mode);
8755 /* We can't simply return zero because there may be an
8763 /* Negative counts are invalid and should not have been made (a
8764 programmer-specified negative count should have been handled
8769 /* An arithmetic right shift of a quantity known to be -1 or 0
8771 if (code == ASHIFTRT
8772 && (num_sign_bit_copies (varop, shift_mode)
8773 == GET_MODE_BITSIZE (shift_mode)))
8779 /* If we are doing an arithmetic right shift and discarding all but
8780 the sign bit copies, this is equivalent to doing a shift by the
8781 bitsize minus one. Convert it into that shift because it will often
8782 allow other simplifications. */
8784 if (code == ASHIFTRT
8785 && (count + num_sign_bit_copies (varop, shift_mode)
8786 >= GET_MODE_BITSIZE (shift_mode)))
8787 count = GET_MODE_BITSIZE (shift_mode) - 1;
8789 /* We simplify the tests below and elsewhere by converting
8790 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8791 `make_compound_operation' will convert it to a ASHIFTRT for
8792 those machines (such as Vax) that don't have a LSHIFTRT. */
8793 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8795 && ((nonzero_bits (varop, shift_mode)
8796 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8800 switch (GET_CODE (varop))
8806 new = expand_compound_operation (varop);
8815 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8816 minus the width of a smaller mode, we can do this with a
8817 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8818 if ((code == ASHIFTRT || code == LSHIFTRT)
8819 && ! mode_dependent_address_p (XEXP (varop, 0))
8820 && ! MEM_VOLATILE_P (varop)
8821 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8822 MODE_INT, 1)) != BLKmode)
8824 if (BYTES_BIG_ENDIAN)
8825 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8827 new = gen_rtx_MEM (tmode,
8828 plus_constant (XEXP (varop, 0),
8829 count / BITS_PER_UNIT));
8830 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8831 MEM_COPY_ATTRIBUTES (new, varop);
8832 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8833 : ZERO_EXTEND, mode, new);
8840 /* Similar to the case above, except that we can only do this if
8841 the resulting mode is the same as that of the underlying
8842 MEM and adjust the address depending on the *bits* endianness
8843 because of the way that bit-field extract insns are defined. */
8844 if ((code == ASHIFTRT || code == LSHIFTRT)
8845 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8846 MODE_INT, 1)) != BLKmode
8847 && tmode == GET_MODE (XEXP (varop, 0)))
8849 if (BITS_BIG_ENDIAN)
8850 new = XEXP (varop, 0);
8853 new = copy_rtx (XEXP (varop, 0));
8854 SUBST (XEXP (new, 0),
8855 plus_constant (XEXP (new, 0),
8856 count / BITS_PER_UNIT));
8859 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8860 : ZERO_EXTEND, mode, new);
8867 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8868 the same number of words as what we've seen so far. Then store
8869 the widest mode in MODE. */
8870 if (subreg_lowpart_p (varop)
8871 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8872 > GET_MODE_SIZE (GET_MODE (varop)))
8873 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8874 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8877 varop = SUBREG_REG (varop);
8878 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8879 mode = GET_MODE (varop);
8885 /* Some machines use MULT instead of ASHIFT because MULT
8886 is cheaper. But it is still better on those machines to
8887 merge two shifts into one. */
8888 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8889 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8891 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8892 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8898 /* Similar, for when divides are cheaper. */
8899 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8900 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8902 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8903 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8909 /* If we are extracting just the sign bit of an arithmetic right
8910 shift, that shift is not needed. */
8911 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8913 varop = XEXP (varop, 0);
8917 /* ... fall through ... */
8922 /* Here we have two nested shifts. The result is usually the
8923 AND of a new shift with a mask. We compute the result below. */
8924 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8925 && INTVAL (XEXP (varop, 1)) >= 0
8926 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8927 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8928 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8930 enum rtx_code first_code = GET_CODE (varop);
8931 int first_count = INTVAL (XEXP (varop, 1));
8932 unsigned HOST_WIDE_INT mask;
8935 /* We have one common special case. We can't do any merging if
8936 the inner code is an ASHIFTRT of a smaller mode. However, if
8937 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8938 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8939 we can convert it to
8940 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8941 This simplifies certain SIGN_EXTEND operations. */
8942 if (code == ASHIFT && first_code == ASHIFTRT
8943 && (GET_MODE_BITSIZE (result_mode)
8944 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8946 /* C3 has the low-order C1 bits zero. */
8948 mask = (GET_MODE_MASK (mode)
8949 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8951 varop = simplify_and_const_int (NULL_RTX, result_mode,
8952 XEXP (varop, 0), mask);
8953 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8955 count = first_count;
8960 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8961 than C1 high-order bits equal to the sign bit, we can convert
8962 this to either an ASHIFT or a ASHIFTRT depending on the
8965 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8967 if (code == ASHIFTRT && first_code == ASHIFT
8968 && GET_MODE (varop) == shift_mode
8969 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8972 count -= first_count;
8974 count = - count, code = ASHIFT;
8975 varop = XEXP (varop, 0);
8979 /* There are some cases we can't do. If CODE is ASHIFTRT,
8980 we can only do this if FIRST_CODE is also ASHIFTRT.
8982 We can't do the case when CODE is ROTATE and FIRST_CODE is
8985 If the mode of this shift is not the mode of the outer shift,
8986 we can't do this if either shift is a right shift or ROTATE.
8988 Finally, we can't do any of these if the mode is too wide
8989 unless the codes are the same.
8991 Handle the case where the shift codes are the same
8994 if (code == first_code)
8996 if (GET_MODE (varop) != result_mode
8997 && (code == ASHIFTRT || code == LSHIFTRT
9001 count += first_count;
9002 varop = XEXP (varop, 0);
9006 if (code == ASHIFTRT
9007 || (code == ROTATE && first_code == ASHIFTRT)
9008 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9009 || (GET_MODE (varop) != result_mode
9010 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9011 || first_code == ROTATE
9012 || code == ROTATE)))
9015 /* To compute the mask to apply after the shift, shift the
9016 nonzero bits of the inner shift the same way the
9017 outer shift will. */
9019 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9022 = simplify_binary_operation (code, result_mode, mask_rtx,
9025 /* Give up if we can't compute an outer operation to use. */
9027 || GET_CODE (mask_rtx) != CONST_INT
9028 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9030 result_mode, &complement_p))
9033 /* If the shifts are in the same direction, we add the
9034 counts. Otherwise, we subtract them. */
9035 if ((code == ASHIFTRT || code == LSHIFTRT)
9036 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9037 count += first_count;
9039 count -= first_count;
9041 /* If COUNT is positive, the new shift is usually CODE,
9042 except for the two exceptions below, in which case it is
9043 FIRST_CODE. If the count is negative, FIRST_CODE should
9046 && ((first_code == ROTATE && code == ASHIFT)
9047 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9050 code = first_code, count = - count;
9052 varop = XEXP (varop, 0);
9056 /* If we have (A << B << C) for any shift, we can convert this to
9057 (A << C << B). This wins if A is a constant. Only try this if
9058 B is not a constant. */
9060 else if (GET_CODE (varop) == code
9061 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9063 = simplify_binary_operation (code, mode,
9067 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9074 /* Make this fit the case below. */
9075 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9076 GEN_INT (GET_MODE_MASK (mode)));
9082 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9083 with C the size of VAROP - 1 and the shift is logical if
9084 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9085 we have an (le X 0) operation. If we have an arithmetic shift
9086 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9087 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9089 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9090 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9091 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9092 && (code == LSHIFTRT || code == ASHIFTRT)
9093 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9094 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9097 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9100 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9101 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9106 /* If we have (shift (logical)), move the logical to the outside
9107 to allow it to possibly combine with another logical and the
9108 shift to combine with another shift. This also canonicalizes to
9109 what a ZERO_EXTRACT looks like. Also, some machines have
9110 (and (shift)) insns. */
9112 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9113 && (new = simplify_binary_operation (code, result_mode,
9115 GEN_INT (count))) != 0
9116 && GET_CODE(new) == CONST_INT
9117 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9118 INTVAL (new), result_mode, &complement_p))
9120 varop = XEXP (varop, 0);
9124 /* If we can't do that, try to simplify the shift in each arm of the
9125 logical expression, make a new logical expression, and apply
9126 the inverse distributive law. */
9128 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9129 XEXP (varop, 0), count);
9130 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9131 XEXP (varop, 1), count);
9133 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9134 varop = apply_distributive_law (varop);
9141 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9142 says that the sign bit can be tested, FOO has mode MODE, C is
9143 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9144 that may be nonzero. */
9145 if (code == LSHIFTRT
9146 && XEXP (varop, 1) == const0_rtx
9147 && GET_MODE (XEXP (varop, 0)) == result_mode
9148 && count == GET_MODE_BITSIZE (result_mode) - 1
9149 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9150 && ((STORE_FLAG_VALUE
9151 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
9152 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9153 && merge_outer_ops (&outer_op, &outer_const, XOR,
9154 (HOST_WIDE_INT) 1, result_mode,
9157 varop = XEXP (varop, 0);
9164 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9165 than the number of bits in the mode is equivalent to A. */
9166 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9167 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9169 varop = XEXP (varop, 0);
9174 /* NEG commutes with ASHIFT since it is multiplication. Move the
9175 NEG outside to allow shifts to combine. */
9177 && merge_outer_ops (&outer_op, &outer_const, NEG,
9178 (HOST_WIDE_INT) 0, result_mode,
9181 varop = XEXP (varop, 0);
9187 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9188 is one less than the number of bits in the mode is
9189 equivalent to (xor A 1). */
9190 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9191 && XEXP (varop, 1) == constm1_rtx
9192 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9193 && merge_outer_ops (&outer_op, &outer_const, XOR,
9194 (HOST_WIDE_INT) 1, result_mode,
9198 varop = XEXP (varop, 0);
9202 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9203 that might be nonzero in BAR are those being shifted out and those
9204 bits are known zero in FOO, we can replace the PLUS with FOO.
9205 Similarly in the other operand order. This code occurs when
9206 we are computing the size of a variable-size array. */
9208 if ((code == ASHIFTRT || code == LSHIFTRT)
9209 && count < HOST_BITS_PER_WIDE_INT
9210 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9211 && (nonzero_bits (XEXP (varop, 1), result_mode)
9212 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9214 varop = XEXP (varop, 0);
9217 else if ((code == ASHIFTRT || code == LSHIFTRT)
9218 && count < HOST_BITS_PER_WIDE_INT
9219 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9220 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9222 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9223 & nonzero_bits (XEXP (varop, 1),
9226 varop = XEXP (varop, 1);
9230 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9232 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9233 && (new = simplify_binary_operation (ASHIFT, result_mode,
9235 GEN_INT (count))) != 0
9236 && GET_CODE(new) == CONST_INT
9237 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9238 INTVAL (new), result_mode, &complement_p))
9240 varop = XEXP (varop, 0);
9246 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9247 with C the size of VAROP - 1 and the shift is logical if
9248 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9249 we have a (gt X 0) operation. If the shift is arithmetic with
9250 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9251 we have a (neg (gt X 0)) operation. */
9253 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9254 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9255 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9256 && (code == LSHIFTRT || code == ASHIFTRT)
9257 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9258 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9259 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9262 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9265 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9266 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9273 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9274 if the truncate does not affect the value. */
9275 if (code == LSHIFTRT
9276 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9277 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9278 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9279 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9280 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9282 rtx varop_inner = XEXP (varop, 0);
9284 varop_inner = gen_rtx_combine (LSHIFTRT,
9285 GET_MODE (varop_inner),
9286 XEXP (varop_inner, 0),
9287 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
9288 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9302 /* We need to determine what mode to do the shift in. If the shift is
9303 a right shift or ROTATE, we must always do it in the mode it was
9304 originally done in. Otherwise, we can do it in MODE, the widest mode
9305 encountered. The code we care about is that of the shift that will
9306 actually be done, not the shift that was originally requested. */
9308 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9309 ? result_mode : mode);
9311 /* We have now finished analyzing the shift. The result should be
9312 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9313 OUTER_OP is non-NIL, it is an operation that needs to be applied
9314 to the result of the shift. OUTER_CONST is the relevant constant,
9315 but we must turn off all bits turned off in the shift.
9317 If we were passed a value for X, see if we can use any pieces of
9318 it. If not, make new rtx. */
9320 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9321 && GET_CODE (XEXP (x, 1)) == CONST_INT
9322 && INTVAL (XEXP (x, 1)) == count)
9323 const_rtx = XEXP (x, 1);
9325 const_rtx = GEN_INT (count);
9327 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9328 && GET_MODE (XEXP (x, 0)) == shift_mode
9329 && SUBREG_REG (XEXP (x, 0)) == varop)
9330 varop = XEXP (x, 0);
9331 else if (GET_MODE (varop) != shift_mode)
9332 varop = gen_lowpart_for_combine (shift_mode, varop);
9334 /* If we can't make the SUBREG, try to return what we were given. */
9335 if (GET_CODE (varop) == CLOBBER)
9336 return x ? x : varop;
9338 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9343 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9344 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9346 SUBST (XEXP (x, 0), varop);
9347 SUBST (XEXP (x, 1), const_rtx);
9350 /* If we have an outer operation and we just made a shift, it is
9351 possible that we could have simplified the shift were it not
9352 for the outer operation. So try to do the simplification
9355 if (outer_op != NIL && GET_CODE (x) == code
9356 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9357 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9358 INTVAL (XEXP (x, 1)));
9360 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9361 turn off all the bits that the shift would have turned off. */
9362 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9363 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9364 GET_MODE_MASK (result_mode) >> orig_count);
9366 /* Do the remainder of the processing in RESULT_MODE. */
9367 x = gen_lowpart_for_combine (result_mode, x);
9369 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9372 x = gen_unary (NOT, result_mode, result_mode, x);
9374 if (outer_op != NIL)
9376 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9377 outer_const = trunc_int_for_mode (outer_const, result_mode);
9379 if (outer_op == AND)
9380 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9381 else if (outer_op == SET)
9382 /* This means that we have determined that the result is
9383 equivalent to a constant. This should be rare. */
9384 x = GEN_INT (outer_const);
9385 else if (GET_RTX_CLASS (outer_op) == '1')
9386 x = gen_unary (outer_op, result_mode, result_mode, x);
9388 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9394 /* Like recog, but we receive the address of a pointer to a new pattern.
9395 We try to match the rtx that the pointer points to.
9396 If that fails, we may try to modify or replace the pattern,
9397 storing the replacement into the same pointer object.
9399 Modifications include deletion or addition of CLOBBERs.
9401 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9402 the CLOBBERs are placed.
9404 The value is the final insn code from the pattern ultimately matched,
9408 recog_for_combine (pnewpat, insn, pnotes)
9413 register rtx pat = *pnewpat;
9414 int insn_code_number;
9415 int num_clobbers_to_add = 0;
9419 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9420 we use to indicate that something didn't match. If we find such a
9421 thing, force rejection. */
9422 if (GET_CODE (pat) == PARALLEL)
9423 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9424 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9425 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9428 /* Is the result of combination a valid instruction? */
9429 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9431 /* If it isn't, there is the possibility that we previously had an insn
9432 that clobbered some register as a side effect, but the combined
9433 insn doesn't need to do that. So try once more without the clobbers
9434 unless this represents an ASM insn. */
9436 if (insn_code_number < 0 && ! check_asm_operands (pat)
9437 && GET_CODE (pat) == PARALLEL)
9441 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9442 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9445 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9449 SUBST_INT (XVECLEN (pat, 0), pos);
9452 pat = XVECEXP (pat, 0, 0);
9454 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9457 /* If we had any clobbers to add, make a new pattern than contains
9458 them. Then check to make sure that all of them are dead. */
9459 if (num_clobbers_to_add)
9461 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9462 gen_rtvec (GET_CODE (pat) == PARALLEL
9464 + num_clobbers_to_add)
9465 : num_clobbers_to_add + 1));
9467 if (GET_CODE (pat) == PARALLEL)
9468 for (i = 0; i < XVECLEN (pat, 0); i++)
9469 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9471 XVECEXP (newpat, 0, 0) = pat;
9473 add_clobbers (newpat, insn_code_number);
9475 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9476 i < XVECLEN (newpat, 0); i++)
9478 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9479 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9481 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9482 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9490 return insn_code_number;
9493 /* Like gen_lowpart but for use by combine. In combine it is not possible
9494 to create any new pseudoregs. However, it is safe to create
9495 invalid memory addresses, because combine will try to recognize
9496 them and all they will do is make the combine attempt fail.
9498 If for some reason this cannot do its job, an rtx
9499 (clobber (const_int 0)) is returned.
9500 An insn containing that will not be recognized. */
9505 gen_lowpart_for_combine (mode, x)
9506 enum machine_mode mode;
9511 if (GET_MODE (x) == mode)
9514 /* We can only support MODE being wider than a word if X is a
9515 constant integer or has a mode the same size. */
9517 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9518 && ! ((GET_MODE (x) == VOIDmode
9519 && (GET_CODE (x) == CONST_INT
9520 || GET_CODE (x) == CONST_DOUBLE))
9521 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9522 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9524 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9525 won't know what to do. So we will strip off the SUBREG here and
9526 process normally. */
9527 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9530 if (GET_MODE (x) == mode)
9534 result = gen_lowpart_common (mode, x);
9536 && GET_CODE (result) == SUBREG
9537 && GET_CODE (SUBREG_REG (result)) == REG
9538 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9539 && (GET_MODE_SIZE (GET_MODE (result))
9540 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9541 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9546 if (GET_CODE (x) == MEM)
9548 register int offset = 0;
9551 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9553 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9554 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9556 /* If we want to refer to something bigger than the original memref,
9557 generate a perverse subreg instead. That will force a reload
9558 of the original memref X. */
9559 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9560 return gen_rtx_SUBREG (mode, x, 0);
9562 if (WORDS_BIG_ENDIAN)
9563 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9564 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9566 if (BYTES_BIG_ENDIAN)
9568 /* Adjust the address so that the address-after-the-data is
9570 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9571 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9573 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9574 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9575 MEM_COPY_ATTRIBUTES (new, x);
9579 /* If X is a comparison operator, rewrite it in a new mode. This
9580 probably won't match, but may allow further simplifications. */
9581 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9582 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9584 /* If we couldn't simplify X any other way, just enclose it in a
9585 SUBREG. Normally, this SUBREG won't match, but some patterns may
9586 include an explicit SUBREG or we may simplify it further in combine. */
9591 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9592 word = ((GET_MODE_SIZE (GET_MODE (x))
9593 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9595 return gen_rtx_SUBREG (mode, x, word);
9599 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9600 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9602 If the identical expression was previously in the insn (in the undobuf),
9603 it will be returned. Only if it is not found will a new expression
9608 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9610 #ifndef ANSI_PROTOTYPES
9612 enum machine_mode mode;
9624 #ifndef ANSI_PROTOTYPES
9625 code = va_arg (p, enum rtx_code);
9626 mode = va_arg (p, enum machine_mode);
9629 n_args = GET_RTX_LENGTH (code);
9630 fmt = GET_RTX_FORMAT (code);
9632 if (n_args == 0 || n_args > 3)
9635 /* Get each arg and verify that it is supposed to be an expression. */
9636 for (j = 0; j < n_args; j++)
9641 args[j] = va_arg (p, rtx);
9646 /* See if this is in undobuf. Be sure we don't use objects that came
9647 from another insn; this could produce circular rtl structures. */
9649 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9651 && GET_CODE (undo->old_contents.r) == code
9652 && GET_MODE (undo->old_contents.r) == mode)
9654 for (j = 0; j < n_args; j++)
9655 if (XEXP (undo->old_contents.r, j) != args[j])
9659 return undo->old_contents.r;
9662 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9663 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9664 rt = rtx_alloc (code);
9665 PUT_MODE (rt, mode);
9666 XEXP (rt, 0) = args[0];
9669 XEXP (rt, 1) = args[1];
9671 XEXP (rt, 2) = args[2];
9676 /* These routines make binary and unary operations by first seeing if they
9677 fold; if not, a new expression is allocated. */
9680 gen_binary (code, mode, op0, op1)
9682 enum machine_mode mode;
9688 if (GET_RTX_CLASS (code) == 'c'
9689 && (GET_CODE (op0) == CONST_INT
9690 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9691 tem = op0, op0 = op1, op1 = tem;
9693 if (GET_RTX_CLASS (code) == '<')
9695 enum machine_mode op_mode = GET_MODE (op0);
9697 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9698 just (REL_OP X Y). */
9699 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9701 op1 = XEXP (op0, 1);
9702 op0 = XEXP (op0, 0);
9703 op_mode = GET_MODE (op0);
9706 if (op_mode == VOIDmode)
9707 op_mode = GET_MODE (op1);
9708 result = simplify_relational_operation (code, op_mode, op0, op1);
9711 result = simplify_binary_operation (code, mode, op0, op1);
9716 /* Put complex operands first and constants second. */
9717 if (GET_RTX_CLASS (code) == 'c'
9718 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9719 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9720 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9721 || (GET_CODE (op0) == SUBREG
9722 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9723 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9724 return gen_rtx_combine (code, mode, op1, op0);
9726 /* If we are turning off bits already known off in OP0, we need not do
9728 else if (code == AND && GET_CODE (op1) == CONST_INT
9729 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9730 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9733 return gen_rtx_combine (code, mode, op0, op1);
9737 gen_unary (code, mode, op0_mode, op0)
9739 enum machine_mode mode, op0_mode;
9742 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9747 return gen_rtx_combine (code, mode, op0);
9750 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9751 comparison code that will be tested.
9753 The result is a possibly different comparison code to use. *POP0 and
9754 *POP1 may be updated.
9756 It is possible that we might detect that a comparison is either always
9757 true or always false. However, we do not perform general constant
9758 folding in combine, so this knowledge isn't useful. Such tautologies
9759 should have been detected earlier. Hence we ignore all such cases. */
9761 static enum rtx_code
9762 simplify_comparison (code, pop0, pop1)
9771 enum machine_mode mode, tmode;
9773 /* Try a few ways of applying the same transformation to both operands. */
9776 #ifndef WORD_REGISTER_OPERATIONS
9777 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9778 so check specially. */
9779 if (code != GTU && code != GEU && code != LTU && code != LEU
9780 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9781 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9782 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9783 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9784 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9785 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9786 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9787 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9788 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9789 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9790 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9791 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9792 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9793 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9794 && (INTVAL (XEXP (op0, 1))
9795 == (GET_MODE_BITSIZE (GET_MODE (op0))
9797 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9799 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9800 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9804 /* If both operands are the same constant shift, see if we can ignore the
9805 shift. We can if the shift is a rotate or if the bits shifted out of
9806 this shift are known to be zero for both inputs and if the type of
9807 comparison is compatible with the shift. */
9808 if (GET_CODE (op0) == GET_CODE (op1)
9809 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9810 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9811 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9812 && (code != GT && code != LT && code != GE && code != LE))
9813 || (GET_CODE (op0) == ASHIFTRT
9814 && (code != GTU && code != LTU
9815 && code != GEU && code != GEU)))
9816 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9817 && INTVAL (XEXP (op0, 1)) >= 0
9818 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9819 && XEXP (op0, 1) == XEXP (op1, 1))
9821 enum machine_mode mode = GET_MODE (op0);
9822 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9823 int shift_count = INTVAL (XEXP (op0, 1));
9825 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9826 mask &= (mask >> shift_count) << shift_count;
9827 else if (GET_CODE (op0) == ASHIFT)
9828 mask = (mask & (mask << shift_count)) >> shift_count;
9830 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9831 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9832 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9837 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9838 SUBREGs are of the same mode, and, in both cases, the AND would
9839 be redundant if the comparison was done in the narrower mode,
9840 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9841 and the operand's possibly nonzero bits are 0xffffff01; in that case
9842 if we only care about QImode, we don't need the AND). This case
9843 occurs if the output mode of an scc insn is not SImode and
9844 STORE_FLAG_VALUE == 1 (e.g., the 386).
9846 Similarly, check for a case where the AND's are ZERO_EXTEND
9847 operations from some narrower mode even though a SUBREG is not
9850 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9851 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9852 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9854 rtx inner_op0 = XEXP (op0, 0);
9855 rtx inner_op1 = XEXP (op1, 0);
9856 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9857 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9860 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9861 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9862 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9863 && (GET_MODE (SUBREG_REG (inner_op0))
9864 == GET_MODE (SUBREG_REG (inner_op1)))
9865 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9866 <= HOST_BITS_PER_WIDE_INT)
9867 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9868 GET_MODE (SUBREG_REG (inner_op0)))))
9869 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9870 GET_MODE (SUBREG_REG (inner_op1))))))
9872 op0 = SUBREG_REG (inner_op0);
9873 op1 = SUBREG_REG (inner_op1);
9875 /* The resulting comparison is always unsigned since we masked
9876 off the original sign bit. */
9877 code = unsigned_condition (code);
9883 for (tmode = GET_CLASS_NARROWEST_MODE
9884 (GET_MODE_CLASS (GET_MODE (op0)));
9885 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9886 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9888 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9889 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9890 code = unsigned_condition (code);
9899 /* If both operands are NOT, we can strip off the outer operation
9900 and adjust the comparison code for swapped operands; similarly for
9901 NEG, except that this must be an equality comparison. */
9902 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9903 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9904 && (code == EQ || code == NE)))
9905 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9911 /* If the first operand is a constant, swap the operands and adjust the
9912 comparison code appropriately, but don't do this if the second operand
9913 is already a constant integer. */
9914 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9916 tem = op0, op0 = op1, op1 = tem;
9917 code = swap_condition (code);
9920 /* We now enter a loop during which we will try to simplify the comparison.
9921 For the most part, we only are concerned with comparisons with zero,
9922 but some things may really be comparisons with zero but not start
9923 out looking that way. */
9925 while (GET_CODE (op1) == CONST_INT)
9927 enum machine_mode mode = GET_MODE (op0);
9928 int mode_width = GET_MODE_BITSIZE (mode);
9929 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9930 int equality_comparison_p;
9931 int sign_bit_comparison_p;
9932 int unsigned_comparison_p;
9933 HOST_WIDE_INT const_op;
9935 /* We only want to handle integral modes. This catches VOIDmode,
9936 CCmode, and the floating-point modes. An exception is that we
9937 can handle VOIDmode if OP0 is a COMPARE or a comparison
9940 if (GET_MODE_CLASS (mode) != MODE_INT
9941 && ! (mode == VOIDmode
9942 && (GET_CODE (op0) == COMPARE
9943 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9946 /* Get the constant we are comparing against and turn off all bits
9947 not on in our mode. */
9948 const_op = INTVAL (op1);
9949 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9952 /* If we are comparing against a constant power of two and the value
9953 being compared can only have that single bit nonzero (e.g., it was
9954 `and'ed with that bit), we can replace this with a comparison
9957 && (code == EQ || code == NE || code == GE || code == GEU
9958 || code == LT || code == LTU)
9959 && mode_width <= HOST_BITS_PER_WIDE_INT
9960 && exact_log2 (const_op) >= 0
9961 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9963 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9964 op1 = const0_rtx, const_op = 0;
9967 /* Similarly, if we are comparing a value known to be either -1 or
9968 0 with -1, change it to the opposite comparison against zero. */
9971 && (code == EQ || code == NE || code == GT || code == LE
9972 || code == GEU || code == LTU)
9973 && num_sign_bit_copies (op0, mode) == mode_width)
9975 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9976 op1 = const0_rtx, const_op = 0;
9979 /* Do some canonicalizations based on the comparison code. We prefer
9980 comparisons against zero and then prefer equality comparisons.
9981 If we can reduce the size of a constant, we will do that too. */
9986 /* < C is equivalent to <= (C - 1) */
9990 op1 = GEN_INT (const_op);
9992 /* ... fall through to LE case below. */
9998 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10002 op1 = GEN_INT (const_op);
10006 /* If we are doing a <= 0 comparison on a value known to have
10007 a zero sign bit, we can replace this with == 0. */
10008 else if (const_op == 0
10009 && mode_width <= HOST_BITS_PER_WIDE_INT
10010 && (nonzero_bits (op0, mode)
10011 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10016 /* >= C is equivalent to > (C - 1). */
10020 op1 = GEN_INT (const_op);
10022 /* ... fall through to GT below. */
10028 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10032 op1 = GEN_INT (const_op);
10036 /* If we are doing a > 0 comparison on a value known to have
10037 a zero sign bit, we can replace this with != 0. */
10038 else if (const_op == 0
10039 && mode_width <= HOST_BITS_PER_WIDE_INT
10040 && (nonzero_bits (op0, mode)
10041 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10046 /* < C is equivalent to <= (C - 1). */
10050 op1 = GEN_INT (const_op);
10052 /* ... fall through ... */
10055 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10056 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10057 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10059 const_op = 0, op1 = const0_rtx;
10067 /* unsigned <= 0 is equivalent to == 0 */
10071 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10072 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10073 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10075 const_op = 0, op1 = const0_rtx;
10081 /* >= C is equivalent to < (C - 1). */
10085 op1 = GEN_INT (const_op);
10087 /* ... fall through ... */
10090 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10091 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10092 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10094 const_op = 0, op1 = const0_rtx;
10102 /* unsigned > 0 is equivalent to != 0 */
10106 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10107 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10108 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10110 const_op = 0, op1 = const0_rtx;
10119 /* Compute some predicates to simplify code below. */
10121 equality_comparison_p = (code == EQ || code == NE);
10122 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10123 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10126 /* If this is a sign bit comparison and we can do arithmetic in
10127 MODE, say that we will only be needing the sign bit of OP0. */
10128 if (sign_bit_comparison_p
10129 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10130 op0 = force_to_mode (op0, mode,
10132 << (GET_MODE_BITSIZE (mode) - 1)),
10135 /* Now try cases based on the opcode of OP0. If none of the cases
10136 does a "continue", we exit this loop immediately after the
10139 switch (GET_CODE (op0))
10142 /* If we are extracting a single bit from a variable position in
10143 a constant that has only a single bit set and are comparing it
10144 with zero, we can convert this into an equality comparison
10145 between the position and the location of the single bit. */
10147 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10148 && XEXP (op0, 1) == const1_rtx
10149 && equality_comparison_p && const_op == 0
10150 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10152 if (BITS_BIG_ENDIAN)
10155 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10156 if (mode == VOIDmode)
10158 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10160 i = BITS_PER_WORD - 1 - i;
10164 op0 = XEXP (op0, 2);
10168 /* Result is nonzero iff shift count is equal to I. */
10169 code = reverse_condition (code);
10173 /* ... fall through ... */
10176 tem = expand_compound_operation (op0);
10185 /* If testing for equality, we can take the NOT of the constant. */
10186 if (equality_comparison_p
10187 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10189 op0 = XEXP (op0, 0);
10194 /* If just looking at the sign bit, reverse the sense of the
10196 if (sign_bit_comparison_p)
10198 op0 = XEXP (op0, 0);
10199 code = (code == GE ? LT : GE);
10205 /* If testing for equality, we can take the NEG of the constant. */
10206 if (equality_comparison_p
10207 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10209 op0 = XEXP (op0, 0);
10214 /* The remaining cases only apply to comparisons with zero. */
10218 /* When X is ABS or is known positive,
10219 (neg X) is < 0 if and only if X != 0. */
10221 if (sign_bit_comparison_p
10222 && (GET_CODE (XEXP (op0, 0)) == ABS
10223 || (mode_width <= HOST_BITS_PER_WIDE_INT
10224 && (nonzero_bits (XEXP (op0, 0), mode)
10225 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10227 op0 = XEXP (op0, 0);
10228 code = (code == LT ? NE : EQ);
10232 /* If we have NEG of something whose two high-order bits are the
10233 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10234 if (num_sign_bit_copies (op0, mode) >= 2)
10236 op0 = XEXP (op0, 0);
10237 code = swap_condition (code);
10243 /* If we are testing equality and our count is a constant, we
10244 can perform the inverse operation on our RHS. */
10245 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10246 && (tem = simplify_binary_operation (ROTATERT, mode,
10247 op1, XEXP (op0, 1))) != 0)
10249 op0 = XEXP (op0, 0);
10254 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10255 a particular bit. Convert it to an AND of a constant of that
10256 bit. This will be converted into a ZERO_EXTRACT. */
10257 if (const_op == 0 && sign_bit_comparison_p
10258 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10259 && mode_width <= HOST_BITS_PER_WIDE_INT)
10261 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10264 - INTVAL (XEXP (op0, 1)))));
10265 code = (code == LT ? NE : EQ);
10269 /* ... fall through ... */
10272 /* ABS is ignorable inside an equality comparison with zero. */
10273 if (const_op == 0 && equality_comparison_p)
10275 op0 = XEXP (op0, 0);
10282 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10283 to (compare FOO CONST) if CONST fits in FOO's mode and we
10284 are either testing inequality or have an unsigned comparison
10285 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10286 if (! unsigned_comparison_p
10287 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10288 <= HOST_BITS_PER_WIDE_INT)
10289 && ((unsigned HOST_WIDE_INT) const_op
10290 < (((unsigned HOST_WIDE_INT) 1
10291 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10293 op0 = XEXP (op0, 0);
10299 /* Check for the case where we are comparing A - C1 with C2,
10300 both constants are smaller than 1/2 the maximum positive
10301 value in MODE, and the comparison is equality or unsigned.
10302 In that case, if A is either zero-extended to MODE or has
10303 sufficient sign bits so that the high-order bit in MODE
10304 is a copy of the sign in the inner mode, we can prove that it is
10305 safe to do the operation in the wider mode. This simplifies
10306 many range checks. */
10308 if (mode_width <= HOST_BITS_PER_WIDE_INT
10309 && subreg_lowpart_p (op0)
10310 && GET_CODE (SUBREG_REG (op0)) == PLUS
10311 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10312 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10313 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10314 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10315 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10316 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10317 GET_MODE (SUBREG_REG (op0)))
10318 & ~ GET_MODE_MASK (mode))
10319 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10320 GET_MODE (SUBREG_REG (op0)))
10321 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10322 - GET_MODE_BITSIZE (mode)))))
10324 op0 = SUBREG_REG (op0);
10328 /* If the inner mode is narrower and we are extracting the low part,
10329 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10330 if (subreg_lowpart_p (op0)
10331 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10332 /* Fall through */ ;
10336 /* ... fall through ... */
10339 if ((unsigned_comparison_p || equality_comparison_p)
10340 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10341 <= HOST_BITS_PER_WIDE_INT)
10342 && ((unsigned HOST_WIDE_INT) const_op
10343 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10345 op0 = XEXP (op0, 0);
10351 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10352 this for equality comparisons due to pathological cases involving
10354 if (equality_comparison_p
10355 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10356 op1, XEXP (op0, 1))))
10358 op0 = XEXP (op0, 0);
10363 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10364 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10365 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10367 op0 = XEXP (XEXP (op0, 0), 0);
10368 code = (code == LT ? EQ : NE);
10374 /* (op (minus A B) 0) -> (op A B) */
10375 if (op1 == const0_rtx)
10377 op1 = XEXP (op0, 1);
10378 op0 = XEXP (op0, 0);
10382 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10383 (eq B (minus A C)), whichever simplifies. We can only do
10384 this for equality comparisons due to pathological cases involving
10386 if (equality_comparison_p
10387 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10388 XEXP (op0, 1), op1)))
10390 op0 = XEXP (op0, 0);
10395 if (equality_comparison_p
10396 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10397 XEXP (op0, 0), op1)))
10399 op0 = XEXP (op0, 1);
10404 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10405 of bits in X minus 1, is one iff X > 0. */
10406 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10407 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10408 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10409 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10411 op0 = XEXP (op0, 1);
10412 code = (code == GE ? LE : GT);
10418 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10419 if C is zero or B is a constant. */
10420 if (equality_comparison_p
10421 && 0 != (tem = simplify_binary_operation (XOR, mode,
10422 XEXP (op0, 1), op1)))
10424 op0 = XEXP (op0, 0);
10431 case LT: case LTU: case LE: case LEU:
10432 case GT: case GTU: case GE: case GEU:
10433 /* We can't do anything if OP0 is a condition code value, rather
10434 than an actual data value. */
10437 || XEXP (op0, 0) == cc0_rtx
10439 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10442 /* Get the two operands being compared. */
10443 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10444 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10446 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10448 /* Check for the cases where we simply want the result of the
10449 earlier test or the opposite of that result. */
10451 || (code == EQ && reversible_comparison_p (op0))
10452 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10453 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10454 && (STORE_FLAG_VALUE
10455 & (((HOST_WIDE_INT) 1
10456 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10458 || (code == GE && reversible_comparison_p (op0)))))
10460 code = (code == LT || code == NE
10461 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10462 op0 = tem, op1 = tem1;
10468 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10470 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10471 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10472 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10474 op0 = XEXP (op0, 1);
10475 code = (code == GE ? GT : LE);
10481 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10482 will be converted to a ZERO_EXTRACT later. */
10483 if (const_op == 0 && equality_comparison_p
10484 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10485 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10487 op0 = simplify_and_const_int
10488 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10490 XEXP (XEXP (op0, 0), 1)),
10491 (HOST_WIDE_INT) 1);
10495 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10496 zero and X is a comparison and C1 and C2 describe only bits set
10497 in STORE_FLAG_VALUE, we can compare with X. */
10498 if (const_op == 0 && equality_comparison_p
10499 && mode_width <= HOST_BITS_PER_WIDE_INT
10500 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10501 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10502 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10503 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10504 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10506 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10507 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10508 if ((~ STORE_FLAG_VALUE & mask) == 0
10509 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10510 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10511 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10513 op0 = XEXP (XEXP (op0, 0), 0);
10518 /* If we are doing an equality comparison of an AND of a bit equal
10519 to the sign bit, replace this with a LT or GE comparison of
10520 the underlying value. */
10521 if (equality_comparison_p
10523 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10524 && mode_width <= HOST_BITS_PER_WIDE_INT
10525 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10526 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10528 op0 = XEXP (op0, 0);
10529 code = (code == EQ ? GE : LT);
10533 /* If this AND operation is really a ZERO_EXTEND from a narrower
10534 mode, the constant fits within that mode, and this is either an
10535 equality or unsigned comparison, try to do this comparison in
10536 the narrower mode. */
10537 if ((equality_comparison_p || unsigned_comparison_p)
10538 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10539 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10540 & GET_MODE_MASK (mode))
10542 && const_op >> i == 0
10543 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10545 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10549 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10550 in both M1 and M2 and the SUBREG is either paradoxical or
10551 represents the low part, permute the SUBREG and the AND and
10553 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10555 #ifdef WORD_REGISTER_OPERATIONS
10557 > (GET_MODE_BITSIZE
10558 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10559 && mode_width <= BITS_PER_WORD)
10562 <= (GET_MODE_BITSIZE
10563 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10564 && subreg_lowpart_p (XEXP (op0, 0))))
10565 #ifndef WORD_REGISTER_OPERATIONS
10566 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10567 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10568 As originally written the upper bits have a defined value
10569 due to the AND operation. However, if we commute the AND
10570 inside the SUBREG then they no longer have defined values
10571 and the meaning of the code has been changed. */
10572 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10573 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10575 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10576 && mode_width <= HOST_BITS_PER_WIDE_INT
10577 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10578 <= HOST_BITS_PER_WIDE_INT)
10579 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10580 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10581 & INTVAL (XEXP (op0, 1)))
10582 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10583 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10584 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10588 = gen_lowpart_for_combine
10590 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10591 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10598 /* If we have (compare (ashift FOO N) (const_int C)) and
10599 the high order N bits of FOO (N+1 if an inequality comparison)
10600 are known to be zero, we can do this by comparing FOO with C
10601 shifted right N bits so long as the low-order N bits of C are
10603 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10604 && INTVAL (XEXP (op0, 1)) >= 0
10605 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10606 < HOST_BITS_PER_WIDE_INT)
10608 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10609 && mode_width <= HOST_BITS_PER_WIDE_INT
10610 && (nonzero_bits (XEXP (op0, 0), mode)
10611 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10612 + ! equality_comparison_p))) == 0)
10614 /* We must perform a logical shift, not an arithmetic one,
10615 as we want the top N bits of C to be zero. */
10616 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10618 temp >>= INTVAL (XEXP (op0, 1));
10619 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10620 op0 = XEXP (op0, 0);
10624 /* If we are doing a sign bit comparison, it means we are testing
10625 a particular bit. Convert it to the appropriate AND. */
10626 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10627 && mode_width <= HOST_BITS_PER_WIDE_INT)
10629 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10632 - INTVAL (XEXP (op0, 1)))));
10633 code = (code == LT ? NE : EQ);
10637 /* If this an equality comparison with zero and we are shifting
10638 the low bit to the sign bit, we can convert this to an AND of the
10640 if (const_op == 0 && equality_comparison_p
10641 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10642 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10644 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10645 (HOST_WIDE_INT) 1);
10651 /* If this is an equality comparison with zero, we can do this
10652 as a logical shift, which might be much simpler. */
10653 if (equality_comparison_p && const_op == 0
10654 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10656 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10658 INTVAL (XEXP (op0, 1)));
10662 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10663 do the comparison in a narrower mode. */
10664 if (! unsigned_comparison_p
10665 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10666 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10667 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10668 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10669 MODE_INT, 1)) != BLKmode
10670 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10671 || ((unsigned HOST_WIDE_INT) - const_op
10672 <= GET_MODE_MASK (tmode))))
10674 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10678 /* Likewise if OP0 is a PLUS of a sign extension with a
10679 constant, which is usually represented with the PLUS
10680 between the shifts. */
10681 if (! unsigned_comparison_p
10682 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10683 && GET_CODE (XEXP (op0, 0)) == PLUS
10684 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10685 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10686 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10687 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10688 MODE_INT, 1)) != BLKmode
10689 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10690 || ((unsigned HOST_WIDE_INT) - const_op
10691 <= GET_MODE_MASK (tmode))))
10693 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10694 rtx add_const = XEXP (XEXP (op0, 0), 1);
10695 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10698 op0 = gen_binary (PLUS, tmode,
10699 gen_lowpart_for_combine (tmode, inner),
10704 /* ... fall through ... */
10706 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10707 the low order N bits of FOO are known to be zero, we can do this
10708 by comparing FOO with C shifted left N bits so long as no
10709 overflow occurs. */
10710 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10711 && INTVAL (XEXP (op0, 1)) >= 0
10712 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10713 && mode_width <= HOST_BITS_PER_WIDE_INT
10714 && (nonzero_bits (XEXP (op0, 0), mode)
10715 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10717 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10720 const_op <<= INTVAL (XEXP (op0, 1));
10721 op1 = GEN_INT (const_op);
10722 op0 = XEXP (op0, 0);
10726 /* If we are using this shift to extract just the sign bit, we
10727 can replace this with an LT or GE comparison. */
10729 && (equality_comparison_p || sign_bit_comparison_p)
10730 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10731 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10733 op0 = XEXP (op0, 0);
10734 code = (code == NE || code == GT ? LT : GE);
10746 /* Now make any compound operations involved in this comparison. Then,
10747 check for an outmost SUBREG on OP0 that is not doing anything or is
10748 paradoxical. The latter case can only occur when it is known that the
10749 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10750 We can never remove a SUBREG for a non-equality comparison because the
10751 sign bit is in a different place in the underlying object. */
10753 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10754 op1 = make_compound_operation (op1, SET);
10756 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10757 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10758 && (code == NE || code == EQ)
10759 && ((GET_MODE_SIZE (GET_MODE (op0))
10760 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10762 op0 = SUBREG_REG (op0);
10763 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10766 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10767 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10768 && (code == NE || code == EQ)
10769 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10770 <= HOST_BITS_PER_WIDE_INT)
10771 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10772 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10773 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10775 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10776 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10777 op0 = SUBREG_REG (op0), op1 = tem;
10779 /* We now do the opposite procedure: Some machines don't have compare
10780 insns in all modes. If OP0's mode is an integer mode smaller than a
10781 word and we can't do a compare in that mode, see if there is a larger
10782 mode for which we can do the compare. There are a number of cases in
10783 which we can use the wider mode. */
10785 mode = GET_MODE (op0);
10786 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10787 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10788 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10789 for (tmode = GET_MODE_WIDER_MODE (mode);
10791 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10792 tmode = GET_MODE_WIDER_MODE (tmode))
10793 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10795 /* If the only nonzero bits in OP0 and OP1 are those in the
10796 narrower mode and this is an equality or unsigned comparison,
10797 we can use the wider mode. Similarly for sign-extended
10798 values, in which case it is true for all comparisons. */
10799 if (((code == EQ || code == NE
10800 || code == GEU || code == GTU || code == LEU || code == LTU)
10801 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10802 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10803 || ((num_sign_bit_copies (op0, tmode)
10804 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10805 && (num_sign_bit_copies (op1, tmode)
10806 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10808 /* If OP0 is an AND and we don't have an AND in MODE either,
10809 make a new AND in the proper mode. */
10810 if (GET_CODE (op0) == AND
10811 && (add_optab->handlers[(int) mode].insn_code
10812 == CODE_FOR_nothing))
10813 op0 = gen_binary (AND, tmode,
10814 gen_lowpart_for_combine (tmode,
10816 gen_lowpart_for_combine (tmode,
10819 op0 = gen_lowpart_for_combine (tmode, op0);
10820 op1 = gen_lowpart_for_combine (tmode, op1);
10824 /* If this is a test for negative, we can make an explicit
10825 test of the sign bit. */
10827 if (op1 == const0_rtx && (code == LT || code == GE)
10828 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10830 op0 = gen_binary (AND, tmode,
10831 gen_lowpart_for_combine (tmode, op0),
10832 GEN_INT ((HOST_WIDE_INT) 1
10833 << (GET_MODE_BITSIZE (mode) - 1)));
10834 code = (code == LT) ? NE : EQ;
10839 #ifdef CANONICALIZE_COMPARISON
10840 /* If this machine only supports a subset of valid comparisons, see if we
10841 can convert an unsupported one into a supported one. */
10842 CANONICALIZE_COMPARISON (code, op0, op1);
10851 /* Return 1 if we know that X, a comparison operation, is not operating
10852 on a floating-point value or is EQ or NE, meaning that we can safely
10856 reversible_comparison_p (x)
10859 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10861 || GET_CODE (x) == NE || GET_CODE (x) == EQ
10862 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
10865 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10868 case MODE_PARTIAL_INT:
10869 case MODE_COMPLEX_INT:
10873 /* If the mode of the condition codes tells us that this is safe,
10874 we need look no further. */
10875 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10878 /* Otherwise try and find where the condition codes were last set and
10880 x = get_last_value (XEXP (x, 0));
10881 return (x && GET_CODE (x) == COMPARE
10882 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10889 /* Utility function for following routine. Called when X is part of a value
10890 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10891 for each register mentioned. Similar to mention_regs in cse.c */
10894 update_table_tick (x)
10897 register enum rtx_code code = GET_CODE (x);
10898 register const char *fmt = GET_RTX_FORMAT (code);
10903 int regno = REGNO (x);
10904 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10905 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10907 for (i = regno; i < endregno; i++)
10908 reg_last_set_table_tick[i] = label_tick;
10913 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10914 /* Note that we can't have an "E" in values stored; see
10915 get_last_value_validate. */
10917 update_table_tick (XEXP (x, i));
10920 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10921 are saying that the register is clobbered and we no longer know its
10922 value. If INSN is zero, don't update reg_last_set; this is only permitted
10923 with VALUE also zero and is used to invalidate the register. */
10926 record_value_for_reg (reg, insn, value)
10931 int regno = REGNO (reg);
10932 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10933 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10936 /* If VALUE contains REG and we have a previous value for REG, substitute
10937 the previous value. */
10938 if (value && insn && reg_overlap_mentioned_p (reg, value))
10942 /* Set things up so get_last_value is allowed to see anything set up to
10944 subst_low_cuid = INSN_CUID (insn);
10945 tem = get_last_value (reg);
10947 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10948 it isn't going to be useful and will take a lot of time to process,
10949 so just use the CLOBBER. */
10953 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
10954 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
10955 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10956 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10957 tem = XEXP (tem, 0);
10959 value = replace_rtx (copy_rtx (value), reg, tem);
10963 /* For each register modified, show we don't know its value, that
10964 we don't know about its bitwise content, that its value has been
10965 updated, and that we don't know the location of the death of the
10967 for (i = regno; i < endregno; i ++)
10970 reg_last_set[i] = insn;
10971 reg_last_set_value[i] = 0;
10972 reg_last_set_mode[i] = 0;
10973 reg_last_set_nonzero_bits[i] = 0;
10974 reg_last_set_sign_bit_copies[i] = 0;
10975 reg_last_death[i] = 0;
10978 /* Mark registers that are being referenced in this value. */
10980 update_table_tick (value);
10982 /* Now update the status of each register being set.
10983 If someone is using this register in this block, set this register
10984 to invalid since we will get confused between the two lives in this
10985 basic block. This makes using this register always invalid. In cse, we
10986 scan the table to invalidate all entries using this register, but this
10987 is too much work for us. */
10989 for (i = regno; i < endregno; i++)
10991 reg_last_set_label[i] = label_tick;
10992 if (value && reg_last_set_table_tick[i] == label_tick)
10993 reg_last_set_invalid[i] = 1;
10995 reg_last_set_invalid[i] = 0;
10998 /* The value being assigned might refer to X (like in "x++;"). In that
10999 case, we must replace it with (clobber (const_int 0)) to prevent
11001 if (value && ! get_last_value_validate (&value, insn,
11002 reg_last_set_label[regno], 0))
11004 value = copy_rtx (value);
11005 if (! get_last_value_validate (&value, insn,
11006 reg_last_set_label[regno], 1))
11010 /* For the main register being modified, update the value, the mode, the
11011 nonzero bits, and the number of sign bit copies. */
11013 reg_last_set_value[regno] = value;
11017 subst_low_cuid = INSN_CUID (insn);
11018 reg_last_set_mode[regno] = GET_MODE (reg);
11019 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11020 reg_last_set_sign_bit_copies[regno]
11021 = num_sign_bit_copies (value, GET_MODE (reg));
11025 /* Called via note_stores from record_dead_and_set_regs to handle one
11026 SET or CLOBBER in an insn. DATA is the instruction in which the
11027 set is occurring. */
11030 record_dead_and_set_regs_1 (dest, setter, data)
11034 rtx record_dead_insn = (rtx) data;
11036 if (GET_CODE (dest) == SUBREG)
11037 dest = SUBREG_REG (dest);
11039 if (GET_CODE (dest) == REG)
11041 /* If we are setting the whole register, we know its value. Otherwise
11042 show that we don't know the value. We can handle SUBREG in
11044 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11045 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11046 else if (GET_CODE (setter) == SET
11047 && GET_CODE (SET_DEST (setter)) == SUBREG
11048 && SUBREG_REG (SET_DEST (setter)) == dest
11049 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11050 && subreg_lowpart_p (SET_DEST (setter)))
11051 record_value_for_reg (dest, record_dead_insn,
11052 gen_lowpart_for_combine (GET_MODE (dest),
11053 SET_SRC (setter)));
11055 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11057 else if (GET_CODE (dest) == MEM
11058 /* Ignore pushes, they clobber nothing. */
11059 && ! push_operand (dest, GET_MODE (dest)))
11060 mem_last_set = INSN_CUID (record_dead_insn);
11063 /* Update the records of when each REG was most recently set or killed
11064 for the things done by INSN. This is the last thing done in processing
11065 INSN in the combiner loop.
11067 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11068 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11069 and also the similar information mem_last_set (which insn most recently
11070 modified memory) and last_call_cuid (which insn was the most recent
11071 subroutine call). */
11074 record_dead_and_set_regs (insn)
11080 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11082 if (REG_NOTE_KIND (link) == REG_DEAD
11083 && GET_CODE (XEXP (link, 0)) == REG)
11085 int regno = REGNO (XEXP (link, 0));
11087 = regno + (regno < FIRST_PSEUDO_REGISTER
11088 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11091 for (i = regno; i < endregno; i++)
11092 reg_last_death[i] = insn;
11094 else if (REG_NOTE_KIND (link) == REG_INC)
11095 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11098 if (GET_CODE (insn) == CALL_INSN)
11100 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11101 if (call_used_regs[i])
11103 reg_last_set_value[i] = 0;
11104 reg_last_set_mode[i] = 0;
11105 reg_last_set_nonzero_bits[i] = 0;
11106 reg_last_set_sign_bit_copies[i] = 0;
11107 reg_last_death[i] = 0;
11110 last_call_cuid = mem_last_set = INSN_CUID (insn);
11113 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11116 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11117 register present in the SUBREG, so for each such SUBREG go back and
11118 adjust nonzero and sign bit information of the registers that are
11119 known to have some zero/sign bits set.
11121 This is needed because when combine blows the SUBREGs away, the
11122 information on zero/sign bits is lost and further combines can be
11123 missed because of that. */
11126 record_promoted_value (insn, subreg)
11131 int regno = REGNO (SUBREG_REG (subreg));
11132 enum machine_mode mode = GET_MODE (subreg);
11134 if (GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT)
11137 for (links = LOG_LINKS (insn); links; )
11139 insn = XEXP (links, 0);
11140 set = single_set (insn);
11142 if (! set || GET_CODE (SET_DEST (set)) != REG
11143 || REGNO (SET_DEST (set)) != regno
11144 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11146 links = XEXP (links, 1);
11150 if (reg_last_set [regno] == insn)
11152 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11153 reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11156 if (GET_CODE (SET_SRC (set)) == REG)
11158 regno = REGNO (SET_SRC (set));
11159 links = LOG_LINKS (insn);
11166 /* Scan X for promoted SUBREGs. For each one found,
11167 note what it implies to the registers used in it. */
11170 check_promoted_subreg (insn, x)
11174 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11175 && GET_CODE (SUBREG_REG (x)) == REG)
11176 record_promoted_value (insn, x);
11179 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11182 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11183 switch (format [i])
11186 check_promoted_subreg (insn, XEXP (x, i));
11190 if (XVEC (x, i) != 0)
11191 for (j = 0; j < XVECLEN (x, i); j++)
11192 check_promoted_subreg (insn, XVECEXP (x, i, j));
11198 /* Utility routine for the following function. Verify that all the registers
11199 mentioned in *LOC are valid when *LOC was part of a value set when
11200 label_tick == TICK. Return 0 if some are not.
11202 If REPLACE is non-zero, replace the invalid reference with
11203 (clobber (const_int 0)) and return 1. This replacement is useful because
11204 we often can get useful information about the form of a value (e.g., if
11205 it was produced by a shift that always produces -1 or 0) even though
11206 we don't know exactly what registers it was produced from. */
11209 get_last_value_validate (loc, insn, tick, replace)
11216 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11217 int len = GET_RTX_LENGTH (GET_CODE (x));
11220 if (GET_CODE (x) == REG)
11222 int regno = REGNO (x);
11223 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11224 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11227 for (j = regno; j < endregno; j++)
11228 if (reg_last_set_invalid[j]
11229 /* If this is a pseudo-register that was only set once and not
11230 live at the beginning of the function, it is always valid. */
11231 || (! (regno >= FIRST_PSEUDO_REGISTER
11232 && REG_N_SETS (regno) == 1
11233 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
11234 && reg_last_set_label[j] > tick))
11237 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11243 /* If this is a memory reference, make sure that there were
11244 no stores after it that might have clobbered the value. We don't
11245 have alias info, so we assume any store invalidates it. */
11246 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11247 && INSN_CUID (insn) <= mem_last_set)
11250 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11254 for (i = 0; i < len; i++)
11256 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11257 /* Don't bother with these. They shouldn't occur anyway. */
11261 /* If we haven't found a reason for it to be invalid, it is valid. */
11265 /* Get the last value assigned to X, if known. Some registers
11266 in the value may be replaced with (clobber (const_int 0)) if their value
11267 is known longer known reliably. */
11276 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11277 then convert it to the desired mode. If this is a paradoxical SUBREG,
11278 we cannot predict what values the "extra" bits might have. */
11279 if (GET_CODE (x) == SUBREG
11280 && subreg_lowpart_p (x)
11281 && (GET_MODE_SIZE (GET_MODE (x))
11282 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11283 && (value = get_last_value (SUBREG_REG (x))) != 0)
11284 return gen_lowpart_for_combine (GET_MODE (x), value);
11286 if (GET_CODE (x) != REG)
11290 value = reg_last_set_value[regno];
11292 /* If we don't have a value, or if it isn't for this basic block and
11293 it's either a hard register, set more than once, or it's a live
11294 at the beginning of the function, return 0.
11296 Because if it's not live at the beginnning of the function then the reg
11297 is always set before being used (is never used without being set).
11298 And, if it's set only once, and it's always set before use, then all
11299 uses must have the same last value, even if it's not from this basic
11303 || (reg_last_set_label[regno] != label_tick
11304 && (regno < FIRST_PSEUDO_REGISTER
11305 || REG_N_SETS (regno) != 1
11306 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
11309 /* If the value was set in a later insn than the ones we are processing,
11310 we can't use it even if the register was only set once. */
11311 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11314 /* If the value has all its registers valid, return it. */
11315 if (get_last_value_validate (&value, reg_last_set[regno],
11316 reg_last_set_label[regno], 0))
11319 /* Otherwise, make a copy and replace any invalid register with
11320 (clobber (const_int 0)). If that fails for some reason, return 0. */
11322 value = copy_rtx (value);
11323 if (get_last_value_validate (&value, reg_last_set[regno],
11324 reg_last_set_label[regno], 1))
11330 /* Return nonzero if expression X refers to a REG or to memory
11331 that is set in an instruction more recent than FROM_CUID. */
11334 use_crosses_set_p (x, from_cuid)
11338 register const char *fmt;
11340 register enum rtx_code code = GET_CODE (x);
11344 register int regno = REGNO (x);
11345 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11346 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11348 #ifdef PUSH_ROUNDING
11349 /* Don't allow uses of the stack pointer to be moved,
11350 because we don't know whether the move crosses a push insn. */
11351 if (regno == STACK_POINTER_REGNUM)
11354 for (;regno < endreg; regno++)
11355 if (reg_last_set[regno]
11356 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11361 if (code == MEM && mem_last_set > from_cuid)
11364 fmt = GET_RTX_FORMAT (code);
11366 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11371 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11372 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11375 else if (fmt[i] == 'e'
11376 && use_crosses_set_p (XEXP (x, i), from_cuid))
11382 /* Define three variables used for communication between the following
11385 static int reg_dead_regno, reg_dead_endregno;
11386 static int reg_dead_flag;
11388 /* Function called via note_stores from reg_dead_at_p.
11390 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11391 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11394 reg_dead_at_p_1 (dest, x, data)
11397 void *data ATTRIBUTE_UNUSED;
11399 int regno, endregno;
11401 if (GET_CODE (dest) != REG)
11404 regno = REGNO (dest);
11405 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11406 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11408 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11409 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11412 /* Return non-zero if REG is known to be dead at INSN.
11414 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11415 referencing REG, it is dead. If we hit a SET referencing REG, it is
11416 live. Otherwise, see if it is live or dead at the start of the basic
11417 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11418 must be assumed to be always live. */
11421 reg_dead_at_p (reg, insn)
11427 /* Set variables for reg_dead_at_p_1. */
11428 reg_dead_regno = REGNO (reg);
11429 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11430 ? HARD_REGNO_NREGS (reg_dead_regno,
11436 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11437 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11439 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11440 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11444 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11445 beginning of function. */
11446 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11447 insn = prev_nonnote_insn (insn))
11449 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11451 return reg_dead_flag == 1 ? 1 : 0;
11453 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11457 /* Get the basic block number that we were in. */
11462 for (block = 0; block < n_basic_blocks; block++)
11463 if (insn == BLOCK_HEAD (block))
11466 if (block == n_basic_blocks)
11470 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11471 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11477 /* Note hard registers in X that are used. This code is similar to
11478 that in flow.c, but much simpler since we don't care about pseudos. */
11481 mark_used_regs_combine (x)
11484 register RTX_CODE code = GET_CODE (x);
11485 register int regno;
11497 case ADDR_DIFF_VEC:
11500 /* CC0 must die in the insn after it is set, so we don't need to take
11501 special note of it here. */
11507 /* If we are clobbering a MEM, mark any hard registers inside the
11508 address as used. */
11509 if (GET_CODE (XEXP (x, 0)) == MEM)
11510 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11515 /* A hard reg in a wide mode may really be multiple registers.
11516 If so, mark all of them just like the first. */
11517 if (regno < FIRST_PSEUDO_REGISTER)
11519 /* None of this applies to the stack, frame or arg pointers */
11520 if (regno == STACK_POINTER_REGNUM
11521 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11522 || regno == HARD_FRAME_POINTER_REGNUM
11524 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11525 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11527 || regno == FRAME_POINTER_REGNUM)
11530 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11532 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11538 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11540 register rtx testreg = SET_DEST (x);
11542 while (GET_CODE (testreg) == SUBREG
11543 || GET_CODE (testreg) == ZERO_EXTRACT
11544 || GET_CODE (testreg) == SIGN_EXTRACT
11545 || GET_CODE (testreg) == STRICT_LOW_PART)
11546 testreg = XEXP (testreg, 0);
11548 if (GET_CODE (testreg) == MEM)
11549 mark_used_regs_combine (XEXP (testreg, 0));
11551 mark_used_regs_combine (SET_SRC (x));
11559 /* Recursively scan the operands of this expression. */
11562 register const char *fmt = GET_RTX_FORMAT (code);
11564 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11567 mark_used_regs_combine (XEXP (x, i));
11568 else if (fmt[i] == 'E')
11572 for (j = 0; j < XVECLEN (x, i); j++)
11573 mark_used_regs_combine (XVECEXP (x, i, j));
11580 /* Remove register number REGNO from the dead registers list of INSN.
11582 Return the note used to record the death, if there was one. */
11585 remove_death (regno, insn)
11589 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11593 REG_N_DEATHS (regno)--;
11594 remove_note (insn, note);
11600 /* For each register (hardware or pseudo) used within expression X, if its
11601 death is in an instruction with cuid between FROM_CUID (inclusive) and
11602 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11603 list headed by PNOTES.
11605 That said, don't move registers killed by maybe_kill_insn.
11607 This is done when X is being merged by combination into TO_INSN. These
11608 notes will then be distributed as needed. */
11611 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11613 rtx maybe_kill_insn;
11618 register const char *fmt;
11619 register int len, i;
11620 register enum rtx_code code = GET_CODE (x);
11624 register int regno = REGNO (x);
11625 register rtx where_dead = reg_last_death[regno];
11626 register rtx before_dead, after_dead;
11628 /* Don't move the register if it gets killed in between from and to */
11629 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11630 && !reg_referenced_p (x, maybe_kill_insn))
11633 /* WHERE_DEAD could be a USE insn made by combine, so first we
11634 make sure that we have insns with valid INSN_CUID values. */
11635 before_dead = where_dead;
11636 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11637 before_dead = PREV_INSN (before_dead);
11638 after_dead = where_dead;
11639 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11640 after_dead = NEXT_INSN (after_dead);
11642 if (before_dead && after_dead
11643 && INSN_CUID (before_dead) >= from_cuid
11644 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11645 || (where_dead != after_dead
11646 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11648 rtx note = remove_death (regno, where_dead);
11650 /* It is possible for the call above to return 0. This can occur
11651 when reg_last_death points to I2 or I1 that we combined with.
11652 In that case make a new note.
11654 We must also check for the case where X is a hard register
11655 and NOTE is a death note for a range of hard registers
11656 including X. In that case, we must put REG_DEAD notes for
11657 the remaining registers in place of NOTE. */
11659 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11660 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11661 > GET_MODE_SIZE (GET_MODE (x))))
11663 int deadregno = REGNO (XEXP (note, 0));
11665 = (deadregno + HARD_REGNO_NREGS (deadregno,
11666 GET_MODE (XEXP (note, 0))));
11667 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11670 for (i = deadregno; i < deadend; i++)
11671 if (i < regno || i >= ourend)
11672 REG_NOTES (where_dead)
11673 = gen_rtx_EXPR_LIST (REG_DEAD,
11674 gen_rtx_REG (reg_raw_mode[i], i),
11675 REG_NOTES (where_dead));
11677 /* If we didn't find any note, or if we found a REG_DEAD note that
11678 covers only part of the given reg, and we have a multi-reg hard
11679 register, then to be safe we must check for REG_DEAD notes
11680 for each register other than the first. They could have
11681 their own REG_DEAD notes lying around. */
11682 else if ((note == 0
11684 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11685 < GET_MODE_SIZE (GET_MODE (x)))))
11686 && regno < FIRST_PSEUDO_REGISTER
11687 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11689 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11694 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11698 for (i = regno + offset; i < ourend; i++)
11699 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11700 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11703 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11705 XEXP (note, 1) = *pnotes;
11709 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11711 REG_N_DEATHS (regno)++;
11717 else if (GET_CODE (x) == SET)
11719 rtx dest = SET_DEST (x);
11721 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11723 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11724 that accesses one word of a multi-word item, some
11725 piece of everything register in the expression is used by
11726 this insn, so remove any old death. */
11728 if (GET_CODE (dest) == ZERO_EXTRACT
11729 || GET_CODE (dest) == STRICT_LOW_PART
11730 || (GET_CODE (dest) == SUBREG
11731 && (((GET_MODE_SIZE (GET_MODE (dest))
11732 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11733 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11734 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11736 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11740 /* If this is some other SUBREG, we know it replaces the entire
11741 value, so use that as the destination. */
11742 if (GET_CODE (dest) == SUBREG)
11743 dest = SUBREG_REG (dest);
11745 /* If this is a MEM, adjust deaths of anything used in the address.
11746 For a REG (the only other possibility), the entire value is
11747 being replaced so the old value is not used in this insn. */
11749 if (GET_CODE (dest) == MEM)
11750 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11755 else if (GET_CODE (x) == CLOBBER)
11758 len = GET_RTX_LENGTH (code);
11759 fmt = GET_RTX_FORMAT (code);
11761 for (i = 0; i < len; i++)
11766 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11767 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11770 else if (fmt[i] == 'e')
11771 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11775 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11776 pattern of an insn. X must be a REG. */
11779 reg_bitfield_target_p (x, body)
11785 if (GET_CODE (body) == SET)
11787 rtx dest = SET_DEST (body);
11789 int regno, tregno, endregno, endtregno;
11791 if (GET_CODE (dest) == ZERO_EXTRACT)
11792 target = XEXP (dest, 0);
11793 else if (GET_CODE (dest) == STRICT_LOW_PART)
11794 target = SUBREG_REG (XEXP (dest, 0));
11798 if (GET_CODE (target) == SUBREG)
11799 target = SUBREG_REG (target);
11801 if (GET_CODE (target) != REG)
11804 tregno = REGNO (target), regno = REGNO (x);
11805 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11806 return target == x;
11808 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11809 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11811 return endregno > tregno && regno < endtregno;
11814 else if (GET_CODE (body) == PARALLEL)
11815 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11816 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11822 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11823 as appropriate. I3 and I2 are the insns resulting from the combination
11824 insns including FROM (I2 may be zero).
11826 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11827 not need REG_DEAD notes because they are being substituted for. This
11828 saves searching in the most common cases.
11830 Each note in the list is either ignored or placed on some insns, depending
11831 on the type of note. */
11834 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11838 rtx elim_i2, elim_i1;
11840 rtx note, next_note;
11843 for (note = notes; note; note = next_note)
11845 rtx place = 0, place2 = 0;
11847 /* If this NOTE references a pseudo register, ensure it references
11848 the latest copy of that register. */
11849 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11850 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11851 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11853 next_note = XEXP (note, 1);
11854 switch (REG_NOTE_KIND (note))
11857 case REG_EXEC_COUNT:
11858 /* Doesn't matter much where we put this, as long as it's somewhere.
11859 It is preferable to keep these notes on branches, which is most
11860 likely to be i3. */
11864 case REG_EH_REGION:
11865 case REG_EH_RETHROW:
11866 /* These notes must remain with the call. It should not be
11867 possible for both I2 and I3 to be a call. */
11868 if (GET_CODE (i3) == CALL_INSN)
11870 else if (i2 && GET_CODE (i2) == CALL_INSN)
11877 /* Any clobbers for i3 may still exist, and so we must process
11878 REG_UNUSED notes from that insn.
11880 Any clobbers from i2 or i1 can only exist if they were added by
11881 recog_for_combine. In that case, recog_for_combine created the
11882 necessary REG_UNUSED notes. Trying to keep any original
11883 REG_UNUSED notes from these insns can cause incorrect output
11884 if it is for the same register as the original i3 dest.
11885 In that case, we will notice that the register is set in i3,
11886 and then add a REG_UNUSED note for the destination of i3, which
11887 is wrong. However, it is possible to have REG_UNUSED notes from
11888 i2 or i1 for register which were both used and clobbered, so
11889 we keep notes from i2 or i1 if they will turn into REG_DEAD
11892 /* If this register is set or clobbered in I3, put the note there
11893 unless there is one already. */
11894 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11896 if (from_insn != i3)
11899 if (! (GET_CODE (XEXP (note, 0)) == REG
11900 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11901 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11904 /* Otherwise, if this register is used by I3, then this register
11905 now dies here, so we must put a REG_DEAD note here unless there
11907 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11908 && ! (GET_CODE (XEXP (note, 0)) == REG
11909 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11910 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11912 PUT_REG_NOTE_KIND (note, REG_DEAD);
11921 /* These notes say something about results of an insn. We can
11922 only support them if they used to be on I3 in which case they
11923 remain on I3. Otherwise they are ignored.
11925 If the note refers to an expression that is not a constant, we
11926 must also ignore the note since we cannot tell whether the
11927 equivalence is still true. It might be possible to do
11928 slightly better than this (we only have a problem if I2DEST
11929 or I1DEST is present in the expression), but it doesn't
11930 seem worth the trouble. */
11932 if (from_insn == i3
11933 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11938 case REG_NO_CONFLICT:
11939 /* These notes say something about how a register is used. They must
11940 be present on any use of the register in I2 or I3. */
11941 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11944 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11954 /* This can show up in several ways -- either directly in the
11955 pattern, or hidden off in the constant pool with (or without?)
11956 a REG_EQUAL note. */
11957 /* ??? Ignore the without-reg_equal-note problem for now. */
11958 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11959 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11960 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11961 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11965 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11966 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11967 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11968 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11978 /* It is too much trouble to try to see if this note is still
11979 correct in all situations. It is better to simply delete it. */
11983 /* If the insn previously containing this note still exists,
11984 put it back where it was. Otherwise move it to the previous
11985 insn. Adjust the corresponding REG_LIBCALL note. */
11986 if (GET_CODE (from_insn) != NOTE)
11990 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11991 place = prev_real_insn (from_insn);
11993 XEXP (tem, 0) = place;
11998 /* This is handled similarly to REG_RETVAL. */
11999 if (GET_CODE (from_insn) != NOTE)
12003 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12004 place = next_real_insn (from_insn);
12006 XEXP (tem, 0) = place;
12011 /* If the register is used as an input in I3, it dies there.
12012 Similarly for I2, if it is non-zero and adjacent to I3.
12014 If the register is not used as an input in either I3 or I2
12015 and it is not one of the registers we were supposed to eliminate,
12016 there are two possibilities. We might have a non-adjacent I2
12017 or we might have somehow eliminated an additional register
12018 from a computation. For example, we might have had A & B where
12019 we discover that B will always be zero. In this case we will
12020 eliminate the reference to A.
12022 In both cases, we must search to see if we can find a previous
12023 use of A and put the death note there. */
12026 && GET_CODE (from_insn) == CALL_INSN
12027 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12029 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12031 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12032 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12035 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12040 basic_block bb = BASIC_BLOCK (this_basic_block);
12042 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12044 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12046 if (tem == bb->head)
12051 /* If the register is being set at TEM, see if that is all
12052 TEM is doing. If so, delete TEM. Otherwise, make this
12053 into a REG_UNUSED note instead. */
12054 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12056 rtx set = single_set (tem);
12057 rtx inner_dest = 0;
12059 rtx cc0_setter = NULL_RTX;
12063 for (inner_dest = SET_DEST (set);
12064 GET_CODE (inner_dest) == STRICT_LOW_PART
12065 || GET_CODE (inner_dest) == SUBREG
12066 || GET_CODE (inner_dest) == ZERO_EXTRACT;
12067 inner_dest = XEXP (inner_dest, 0))
12070 /* Verify that it was the set, and not a clobber that
12071 modified the register.
12073 CC0 targets must be careful to maintain setter/user
12074 pairs. If we cannot delete the setter due to side
12075 effects, mark the user with an UNUSED note instead
12078 if (set != 0 && ! side_effects_p (SET_SRC (set))
12079 && rtx_equal_p (XEXP (note, 0), inner_dest)
12081 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12082 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12083 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12087 /* Move the notes and links of TEM elsewhere.
12088 This might delete other dead insns recursively.
12089 First set the pattern to something that won't use
12092 PATTERN (tem) = pc_rtx;
12094 distribute_notes (REG_NOTES (tem), tem, tem,
12095 NULL_RTX, NULL_RTX, NULL_RTX);
12096 distribute_links (LOG_LINKS (tem));
12098 PUT_CODE (tem, NOTE);
12099 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12100 NOTE_SOURCE_FILE (tem) = 0;
12103 /* Delete the setter too. */
12106 PATTERN (cc0_setter) = pc_rtx;
12108 distribute_notes (REG_NOTES (cc0_setter),
12109 cc0_setter, cc0_setter,
12110 NULL_RTX, NULL_RTX, NULL_RTX);
12111 distribute_links (LOG_LINKS (cc0_setter));
12113 PUT_CODE (cc0_setter, NOTE);
12114 NOTE_LINE_NUMBER (cc0_setter)
12115 = NOTE_INSN_DELETED;
12116 NOTE_SOURCE_FILE (cc0_setter) = 0;
12120 /* If the register is both set and used here, put the
12121 REG_DEAD note here, but place a REG_UNUSED note
12122 here too unless there already is one. */
12123 else if (reg_referenced_p (XEXP (note, 0),
12128 if (! find_regno_note (tem, REG_UNUSED,
12129 REGNO (XEXP (note, 0))))
12131 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12136 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12138 /* If there isn't already a REG_UNUSED note, put one
12140 if (! find_regno_note (tem, REG_UNUSED,
12141 REGNO (XEXP (note, 0))))
12146 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12147 || (GET_CODE (tem) == CALL_INSN
12148 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12152 /* If we are doing a 3->2 combination, and we have a
12153 register which formerly died in i3 and was not used
12154 by i2, which now no longer dies in i3 and is used in
12155 i2 but does not die in i2, and place is between i2
12156 and i3, then we may need to move a link from place to
12158 if (i2 && INSN_UID (place) <= max_uid_cuid
12159 && INSN_CUID (place) > INSN_CUID (i2)
12160 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12161 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12163 rtx links = LOG_LINKS (place);
12164 LOG_LINKS (place) = 0;
12165 distribute_links (links);
12170 if (tem == bb->head)
12174 /* We haven't found an insn for the death note and it
12175 is still a REG_DEAD note, but we have hit the beginning
12176 of the block. If the existing life info says the reg
12177 was dead, there's nothing left to do. Otherwise, we'll
12178 need to do a global life update after combine. */
12179 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0)
12181 int regno = REGNO (XEXP (note, 0));
12182 if (REGNO_REG_SET_P (bb->global_live_at_start, regno))
12184 SET_BIT (refresh_blocks, this_basic_block);
12190 /* If the register is set or already dead at PLACE, we needn't do
12191 anything with this note if it is still a REG_DEAD note.
12192 We can here if it is set at all, not if is it totally replace,
12193 which is what `dead_or_set_p' checks, so also check for it being
12196 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12198 int regno = REGNO (XEXP (note, 0));
12200 if (dead_or_set_p (place, XEXP (note, 0))
12201 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12203 /* Unless the register previously died in PLACE, clear
12204 reg_last_death. [I no longer understand why this is
12206 if (reg_last_death[regno] != place)
12207 reg_last_death[regno] = 0;
12211 reg_last_death[regno] = place;
12213 /* If this is a death note for a hard reg that is occupying
12214 multiple registers, ensure that we are still using all
12215 parts of the object. If we find a piece of the object
12216 that is unused, we must add a USE for that piece before
12217 PLACE and put the appropriate REG_DEAD note on it.
12219 An alternative would be to put a REG_UNUSED for the pieces
12220 on the insn that set the register, but that can't be done if
12221 it is not in the same block. It is simpler, though less
12222 efficient, to add the USE insns. */
12224 if (place && regno < FIRST_PSEUDO_REGISTER
12225 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12228 = regno + HARD_REGNO_NREGS (regno,
12229 GET_MODE (XEXP (note, 0)));
12233 for (i = regno; i < endregno; i++)
12234 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12235 && ! find_regno_fusage (place, USE, i))
12237 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12240 /* See if we already placed a USE note for this
12241 register in front of PLACE. */
12243 GET_CODE (PREV_INSN (p)) == INSN
12244 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12246 if (rtx_equal_p (piece,
12247 XEXP (PATTERN (PREV_INSN (p)), 0)))
12256 = emit_insn_before (gen_rtx_USE (VOIDmode,
12259 REG_NOTES (use_insn)
12260 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12261 REG_NOTES (use_insn));
12267 /* Check for the case where the register dying partially
12268 overlaps the register set by this insn. */
12270 for (i = regno; i < endregno; i++)
12271 if (dead_or_set_regno_p (place, i))
12279 /* Put only REG_DEAD notes for pieces that are
12280 still used and that are not already dead or set. */
12282 for (i = regno; i < endregno; i++)
12284 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12286 if ((reg_referenced_p (piece, PATTERN (place))
12287 || (GET_CODE (place) == CALL_INSN
12288 && find_reg_fusage (place, USE, piece)))
12289 && ! dead_or_set_p (place, piece)
12290 && ! reg_bitfield_target_p (piece,
12293 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12294 REG_NOTES (place));
12304 /* Any other notes should not be present at this point in the
12311 XEXP (note, 1) = REG_NOTES (place);
12312 REG_NOTES (place) = note;
12314 else if ((REG_NOTE_KIND (note) == REG_DEAD
12315 || REG_NOTE_KIND (note) == REG_UNUSED)
12316 && GET_CODE (XEXP (note, 0)) == REG)
12317 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12321 if ((REG_NOTE_KIND (note) == REG_DEAD
12322 || REG_NOTE_KIND (note) == REG_UNUSED)
12323 && GET_CODE (XEXP (note, 0)) == REG)
12324 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12326 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12327 REG_NOTE_KIND (note),
12329 REG_NOTES (place2));
12334 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12335 I3, I2, and I1 to new locations. This is also called in one case to
12336 add a link pointing at I3 when I3's destination is changed. */
12339 distribute_links (links)
12342 rtx link, next_link;
12344 for (link = links; link; link = next_link)
12350 next_link = XEXP (link, 1);
12352 /* If the insn that this link points to is a NOTE or isn't a single
12353 set, ignore it. In the latter case, it isn't clear what we
12354 can do other than ignore the link, since we can't tell which
12355 register it was for. Such links wouldn't be used by combine
12358 It is not possible for the destination of the target of the link to
12359 have been changed by combine. The only potential of this is if we
12360 replace I3, I2, and I1 by I3 and I2. But in that case the
12361 destination of I2 also remains unchanged. */
12363 if (GET_CODE (XEXP (link, 0)) == NOTE
12364 || (set = single_set (XEXP (link, 0))) == 0)
12367 reg = SET_DEST (set);
12368 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12369 || GET_CODE (reg) == SIGN_EXTRACT
12370 || GET_CODE (reg) == STRICT_LOW_PART)
12371 reg = XEXP (reg, 0);
12373 /* A LOG_LINK is defined as being placed on the first insn that uses
12374 a register and points to the insn that sets the register. Start
12375 searching at the next insn after the target of the link and stop
12376 when we reach a set of the register or the end of the basic block.
12378 Note that this correctly handles the link that used to point from
12379 I3 to I2. Also note that not much searching is typically done here
12380 since most links don't point very far away. */
12382 for (insn = NEXT_INSN (XEXP (link, 0));
12383 (insn && (this_basic_block == n_basic_blocks - 1
12384 || BLOCK_HEAD (this_basic_block + 1) != insn));
12385 insn = NEXT_INSN (insn))
12386 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12387 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12389 if (reg_referenced_p (reg, PATTERN (insn)))
12393 else if (GET_CODE (insn) == CALL_INSN
12394 && find_reg_fusage (insn, USE, reg))
12400 /* If we found a place to put the link, place it there unless there
12401 is already a link to the same insn as LINK at that point. */
12407 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12408 if (XEXP (link2, 0) == XEXP (link, 0))
12413 XEXP (link, 1) = LOG_LINKS (place);
12414 LOG_LINKS (place) = link;
12416 /* Set added_links_insn to the earliest insn we added a
12418 if (added_links_insn == 0
12419 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12420 added_links_insn = place;
12426 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12432 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12433 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12434 insn = NEXT_INSN (insn);
12436 if (INSN_UID (insn) > max_uid_cuid)
12439 return INSN_CUID (insn);
12443 dump_combine_stats (file)
12448 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12449 combine_attempts, combine_merges, combine_extras, combine_successes);
12453 dump_combine_total_stats (file)
12458 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12459 total_attempts, total_merges, total_extras, total_successes);