1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
81 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
85 #include "insn-flags.h"
86 #include "insn-codes.h"
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND
97 for cases when we don't care which is true. Define LOAD_EXTEND to
98 be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */
100 #ifdef BYTE_LOADS_ZERO_EXTEND
101 #define BYTE_LOADS_EXTEND
102 #define LOAD_EXTEND ZERO_EXTEND
105 #ifdef BYTE_LOADS_SIGN_EXTEND
106 #define BYTE_LOADS_EXTEND
107 #define LOAD_EXTEND SIGN_EXTEND
110 /* Number of attempts to combine instructions in this function. */
112 static int combine_attempts;
114 /* Number of attempts that got as far as substitution in this function. */
116 static int combine_merges;
118 /* Number of instructions combined with added SETs in this function. */
120 static int combine_extras;
122 /* Number of instructions combined in this function. */
124 static int combine_successes;
126 /* Totals over entire compilation. */
128 static int total_attempts, total_merges, total_extras, total_successes;
130 /* Vector mapping INSN_UIDs to cuids.
131 The cuids are like uids but increase monotonically always.
132 Combine always uses cuids so that it can compare them.
133 But actually renumbering the uids, which we used to do,
134 proves to be a bad idea because it makes it hard to compare
135 the dumps produced by earlier passes with those from later passes. */
137 static int *uid_cuid;
139 /* Get the cuid of an insn. */
141 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
143 /* Maximum register number, which is the size of the tables below. */
145 static int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
149 static rtx *reg_last_death;
151 /* Record last point of modification of (hard or pseudo) register n. */
153 static rtx *reg_last_set;
155 /* Record the cuid of the last insn that invalidated memory
156 (anything that writes memory, and subroutine calls, but not pushes). */
158 static int mem_last_set;
160 /* Record the cuid of the last CALL_INSN
161 so we can tell whether a potential combination crosses any calls. */
163 static int last_call_cuid;
165 /* When `subst' is called, this is the insn that is being modified
166 (by combining in a previous insn). The PATTERN of this insn
167 is still the old pattern partially modified and it should not be
168 looked at, but this may be used to examine the successors of the insn
169 to judge whether a simplification is valid. */
171 static rtx subst_insn;
173 /* This is the lowest CUID that `subst' is currently dealing with.
174 get_last_value will not return a value if the register was set at or
175 after this CUID. If not for this mechanism, we could get confused if
176 I2 or I1 in try_combine were an insn that used the old value of a register
177 to obtain a new value. In that case, we might erroneously get the
178 new value of the register when we wanted the old one. */
180 static int subst_low_cuid;
182 /* This is the value of undobuf.num_undo when we started processing this
183 substitution. This will prevent gen_rtx_combine from re-used a piece
184 from the previous expression. Doing so can produce circular rtl
187 static int previous_num_undos;
189 /* The next group of arrays allows the recording of the last value assigned
190 to (hard or pseudo) register n. We use this information to see if a
191 operation being processed is redundant given a prior operation performed
192 on the register. For example, an `and' with a constant is redundant if
193 all the zero bits are already known to be turned off.
195 We use an approach similar to that used by cse, but change it in the
198 (1) We do not want to reinitialize at each label.
199 (2) It is useful, but not critical, to know the actual value assigned
200 to a register. Often just its form is helpful.
202 Therefore, we maintain the following arrays:
204 reg_last_set_value the last value assigned
205 reg_last_set_label records the value of label_tick when the
206 register was assigned
207 reg_last_set_table_tick records the value of label_tick when a
208 value using the register is assigned
209 reg_last_set_invalid set to non-zero when it is not valid
210 to use the value of this register in some
213 To understand the usage of these tables, it is important to understand
214 the distinction between the value in reg_last_set_value being valid
215 and the register being validly contained in some other expression in the
218 Entry I in reg_last_set_value is valid if it is non-zero, and either
219 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
221 Register I may validly appear in any expression returned for the value
222 of another register if reg_n_sets[i] is 1. It may also appear in the
223 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
224 reg_last_set_invalid[j] is zero.
226 If an expression is found in the table containing a register which may
227 not validly appear in an expression, the register is replaced by
228 something that won't match, (clobber (const_int 0)).
230 reg_last_set_invalid[i] is set non-zero when register I is being assigned
231 to and reg_last_set_table_tick[i] == label_tick. */
233 /* Record last value assigned to (hard or pseudo) register n. */
235 static rtx *reg_last_set_value;
237 /* Record the value of label_tick when the value for register n is placed in
238 reg_last_set_value[n]. */
240 static int *reg_last_set_label;
242 /* Record the value of label_tick when an expression involving register n
243 is placed in reg_last_set_value. */
245 static int *reg_last_set_table_tick;
247 /* Set non-zero if references to register n in expressions should not be
250 static char *reg_last_set_invalid;
252 /* Incremented for each label. */
254 static int label_tick;
256 /* Some registers that are set more than once and used in more than one
257 basic block are nevertheless always set in similar ways. For example,
258 a QImode register may be loaded from memory in two places on a machine
259 where byte loads zero extend.
261 We record in the following array what we know about the nonzero
262 bits of a register, specifically which bits are known to be zero.
264 If an entry is zero, it means that we don't know anything special. */
266 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
268 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
269 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
271 static enum machine_mode nonzero_bits_mode;
273 /* Nonzero if we know that a register has some leading bits that are always
274 equal to the sign bit. */
276 static char *reg_sign_bit_copies;
278 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
279 It is zero while computing them and after combine has completed. This
280 former test prevents propagating values based on previously set values,
281 which can be incorrect if a variable is modified in a loop. */
283 static int nonzero_sign_valid;
285 /* These arrays are maintained in parallel with reg_last_set_value
286 and are used to store the mode in which the register was last set,
287 the bits that were known to be zero when it was last set, and the
288 number of sign bits copies it was known to have when it was last set. */
290 static enum machine_mode *reg_last_set_mode;
291 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
292 static char *reg_last_set_sign_bit_copies;
294 /* Record one modification to rtl structure
295 to be undone by storing old_contents into *where.
296 is_int is 1 if the contents are an int. */
301 union {rtx rtx; int i;} old_contents;
302 union {rtx *rtx; int *i;} where;
305 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
306 num_undo says how many are currently recorded.
308 storage is nonzero if we must undo the allocation of new storage.
309 The value of storage is what to pass to obfree.
311 other_insn is nonzero if we have modified some other insn in the process
312 of working on subst_insn. It must be verified too. */
320 struct undo undo[MAX_UNDO];
324 static struct undobuf undobuf;
326 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
327 insn. The substitution can be undone by undo_all. If INTO is already
328 set to NEWVAL, do not record this change. Because computing NEWVAL might
329 also call SUBST, we have to compute it before we put anything into
332 #define SUBST(INTO, NEWVAL) \
333 do { rtx _new = (NEWVAL); \
334 if (undobuf.num_undo < MAX_UNDO) \
336 undobuf.undo[undobuf.num_undo].is_int = 0; \
337 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
338 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
340 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
341 undobuf.num_undo++; \
345 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
347 Note that substitution for the value of a CONST_INT is not safe. */
349 #define SUBST_INT(INTO, NEWVAL) \
350 do { if (undobuf.num_undo < MAX_UNDO) \
352 undobuf.undo[undobuf.num_undo].is_int = 1; \
353 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
354 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
356 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
357 undobuf.num_undo++; \
361 /* Number of times the pseudo being substituted for
362 was found and replaced. */
364 static int n_occurrences;
366 static void set_nonzero_bits_and_sign_copies ();
367 static void setup_incoming_promotions ();
368 static void move_deaths ();
370 static void record_value_for_reg ();
371 static void record_dead_and_set_regs ();
372 static int use_crosses_set_p ();
373 static rtx try_combine ();
374 static rtx *find_split_point ();
376 static void undo_all ();
377 static int reg_dead_at_p ();
378 static rtx expand_compound_operation ();
379 static rtx expand_field_assignment ();
380 static rtx make_extraction ();
381 static int get_pos_from_mask ();
382 static rtx force_to_mode ();
383 static rtx known_cond ();
384 static rtx make_field_assignment ();
385 static rtx make_compound_operation ();
386 static rtx apply_distributive_law ();
387 static rtx simplify_and_const_int ();
388 static unsigned HOST_WIDE_INT nonzero_bits ();
389 static int num_sign_bit_copies ();
390 static int merge_outer_ops ();
391 static rtx simplify_shift_const ();
392 static int recog_for_combine ();
393 static rtx gen_lowpart_for_combine ();
394 static rtx gen_rtx_combine ();
395 static rtx gen_binary ();
396 static rtx gen_unary ();
397 static enum rtx_code simplify_comparison ();
398 static int reversible_comparison_p ();
399 static int get_last_value_validate ();
400 static rtx get_last_value ();
401 static void distribute_notes ();
402 static void distribute_links ();
404 /* Main entry point for combiner. F is the first insn of the function.
405 NREGS is the first unused pseudo-reg number. */
408 combine_instructions (f, nregs)
412 register rtx insn, next, prev;
414 register rtx links, nextlinks;
416 combine_attempts = 0;
419 combine_successes = 0;
420 undobuf.num_undo = previous_num_undos = 0;
422 combine_max_regno = nregs;
424 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
425 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
426 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
427 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
428 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
429 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
431 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
432 reg_last_set_nonzero_bits
433 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
434 reg_last_set_sign_bit_copies
435 = (char *) alloca (nregs * sizeof (char));
438 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
439 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
441 bzero (reg_last_death, nregs * sizeof (rtx));
442 bzero (reg_last_set, nregs * sizeof (rtx));
443 bzero (reg_last_set_value, nregs * sizeof (rtx));
444 bzero (reg_last_set_table_tick, nregs * sizeof (int));
445 bzero (reg_last_set_label, nregs * sizeof (int));
446 bzero (reg_last_set_invalid, nregs * sizeof (char));
447 bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode));
448 bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
449 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
450 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
451 bzero (reg_sign_bit_copies, nregs * sizeof (char));
453 init_recog_no_volatile ();
455 /* Compute maximum uid value so uid_cuid can be allocated. */
457 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
458 if (INSN_UID (insn) > i)
461 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
463 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
465 /* Don't use reg_nonzero_bits when computing it. This can cause problems
466 when, for example, we have j <<= 1 in a loop. */
468 nonzero_sign_valid = 0;
470 /* Compute the mapping from uids to cuids.
471 Cuids are numbers assigned to insns, like uids,
472 except that cuids increase monotonically through the code.
474 Scan all SETs and see if we can deduce anything about what
475 bits are known to be zero for some registers and how many copies
476 of the sign bit are known to exist for those registers.
478 Also set any known values so that we can use it while searching
479 for what bits are known to be set. */
483 setup_incoming_promotions ();
485 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
487 INSN_CUID (insn) = ++i;
491 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
493 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
494 record_dead_and_set_regs (insn);
497 if (GET_CODE (insn) == CODE_LABEL)
501 nonzero_sign_valid = 1;
503 /* Now scan all the insns in forward order. */
508 bzero (reg_last_death, nregs * sizeof (rtx));
509 bzero (reg_last_set, nregs * sizeof (rtx));
510 bzero (reg_last_set_value, nregs * sizeof (rtx));
511 bzero (reg_last_set_table_tick, nregs * sizeof (int));
512 bzero (reg_last_set_label, nregs * sizeof (int));
513 bzero (reg_last_set_invalid, nregs * sizeof (char));
515 setup_incoming_promotions ();
517 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
521 if (GET_CODE (insn) == CODE_LABEL)
524 else if (GET_CODE (insn) == INSN
525 || GET_CODE (insn) == CALL_INSN
526 || GET_CODE (insn) == JUMP_INSN)
528 /* Try this insn with each insn it links back to. */
530 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
531 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
534 /* Try each sequence of three linked insns ending with this one. */
536 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
537 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
538 nextlinks = XEXP (nextlinks, 1))
539 if ((next = try_combine (insn, XEXP (links, 0),
540 XEXP (nextlinks, 0))) != 0)
544 /* Try to combine a jump insn that uses CC0
545 with a preceding insn that sets CC0, and maybe with its
546 logical predecessor as well.
547 This is how we make decrement-and-branch insns.
548 We need this special code because data flow connections
549 via CC0 do not get entered in LOG_LINKS. */
551 if (GET_CODE (insn) == JUMP_INSN
552 && (prev = prev_nonnote_insn (insn)) != 0
553 && GET_CODE (prev) == INSN
554 && sets_cc0_p (PATTERN (prev)))
556 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
559 for (nextlinks = LOG_LINKS (prev); nextlinks;
560 nextlinks = XEXP (nextlinks, 1))
561 if ((next = try_combine (insn, prev,
562 XEXP (nextlinks, 0))) != 0)
566 /* Do the same for an insn that explicitly references CC0. */
567 if (GET_CODE (insn) == INSN
568 && (prev = prev_nonnote_insn (insn)) != 0
569 && GET_CODE (prev) == INSN
570 && sets_cc0_p (PATTERN (prev))
571 && GET_CODE (PATTERN (insn)) == SET
572 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
574 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
577 for (nextlinks = LOG_LINKS (prev); nextlinks;
578 nextlinks = XEXP (nextlinks, 1))
579 if ((next = try_combine (insn, prev,
580 XEXP (nextlinks, 0))) != 0)
584 /* Finally, see if any of the insns that this insn links to
585 explicitly references CC0. If so, try this insn, that insn,
586 and its predecessor if it sets CC0. */
587 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
588 if (GET_CODE (XEXP (links, 0)) == INSN
589 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
590 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
591 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
592 && GET_CODE (prev) == INSN
593 && sets_cc0_p (PATTERN (prev))
594 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
598 /* Try combining an insn with two different insns whose results it
600 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
601 for (nextlinks = XEXP (links, 1); nextlinks;
602 nextlinks = XEXP (nextlinks, 1))
603 if ((next = try_combine (insn, XEXP (links, 0),
604 XEXP (nextlinks, 0))) != 0)
607 if (GET_CODE (insn) != NOTE)
608 record_dead_and_set_regs (insn);
615 total_attempts += combine_attempts;
616 total_merges += combine_merges;
617 total_extras += combine_extras;
618 total_successes += combine_successes;
620 nonzero_sign_valid = 0;
623 /* Set up any promoted values for incoming argument registers. */
626 setup_incoming_promotions ()
628 #ifdef PROMOTE_FUNCTION_ARGS
631 enum machine_mode mode;
633 rtx first = get_insns ();
635 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
636 if (FUNCTION_ARG_REGNO_P (regno)
637 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
638 record_value_for_reg (reg, first,
639 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
641 gen_rtx (CLOBBER, mode, const0_rtx)));
645 /* Called via note_stores. If X is a pseudo that is used in more than
646 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
647 set, record what bits are known zero. If we are clobbering X,
648 ignore this "set" because the clobbered value won't be used.
650 If we are setting only a portion of X and we can't figure out what
651 portion, assume all bits will be used since we don't know what will
654 Similarly, set how many bits of X are known to be copies of the sign bit
655 at all locations in the function. This is the smallest number implied
659 set_nonzero_bits_and_sign_copies (x, set)
665 if (GET_CODE (x) == REG
666 && REGNO (x) >= FIRST_PSEUDO_REGISTER
667 && reg_n_sets[REGNO (x)] > 1
668 && reg_basic_block[REGNO (x)] < 0
669 /* If this register is undefined at the start of the file, we can't
670 say what its contents were. */
671 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
672 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
673 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
675 if (GET_CODE (set) == CLOBBER)
677 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
678 reg_sign_bit_copies[REGNO (x)] = 0;
682 /* If this is a complex assignment, see if we can convert it into a
683 simple assignment. */
684 set = expand_field_assignment (set);
686 /* If this is a simple assignment, or we have a paradoxical SUBREG,
687 set what we know about X. */
689 if (SET_DEST (set) == x
690 || (GET_CODE (SET_DEST (set)) == SUBREG
691 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
692 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
693 && SUBREG_REG (SET_DEST (set)) == x))
695 rtx src = SET_SRC (set);
697 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
698 /* If X is narrower than a word and SRC is a non-negative
699 constant that would appear negative in the mode of X,
700 sign-extend it for use in reg_nonzero_bits because some
701 machines (maybe most) will actually do the sign-extension
702 and this is the conservative approach.
704 ??? For 2.5, try to tighten up the MD files in this regard
705 instead of this kludge. */
707 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
708 && GET_CODE (src) == CONST_INT
710 && 0 != (INTVAL (src)
712 << GET_MODE_BITSIZE (GET_MODE (x)))))
713 src = GEN_INT (INTVAL (src)
714 | ((HOST_WIDE_INT) (-1)
715 << GET_MODE_BITSIZE (GET_MODE (x))));
718 reg_nonzero_bits[REGNO (x)]
719 |= nonzero_bits (src, nonzero_bits_mode);
720 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
721 if (reg_sign_bit_copies[REGNO (x)] == 0
722 || reg_sign_bit_copies[REGNO (x)] > num)
723 reg_sign_bit_copies[REGNO (x)] = num;
727 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
728 reg_sign_bit_copies[REGNO (x)] = 0;
733 /* See if INSN can be combined into I3. PRED and SUCC are optionally
734 insns that were previously combined into I3 or that will be combined
735 into the merger of INSN and I3.
737 Return 0 if the combination is not allowed for any reason.
739 If the combination is allowed, *PDEST will be set to the single
740 destination of INSN and *PSRC to the single source, and this function
744 can_combine_p (insn, i3, pred, succ, pdest, psrc)
751 rtx set = 0, src, dest;
753 int all_adjacent = (succ ? (next_active_insn (insn) == succ
754 && next_active_insn (succ) == i3)
755 : next_active_insn (insn) == i3);
757 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
758 or a PARALLEL consisting of such a SET and CLOBBERs.
760 If INSN has CLOBBER parallel parts, ignore them for our processing.
761 By definition, these happen during the execution of the insn. When it
762 is merged with another insn, all bets are off. If they are, in fact,
763 needed and aren't also supplied in I3, they may be added by
764 recog_for_combine. Otherwise, it won't match.
766 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
769 Get the source and destination of INSN. If more than one, can't
772 if (GET_CODE (PATTERN (insn)) == SET)
773 set = PATTERN (insn);
774 else if (GET_CODE (PATTERN (insn)) == PARALLEL
775 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
777 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
779 rtx elt = XVECEXP (PATTERN (insn), 0, i);
781 switch (GET_CODE (elt))
783 /* We can ignore CLOBBERs. */
788 /* Ignore SETs whose result isn't used but not those that
789 have side-effects. */
790 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
791 && ! side_effects_p (elt))
794 /* If we have already found a SET, this is a second one and
795 so we cannot combine with this insn. */
803 /* Anything else means we can't combine. */
809 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
810 so don't do anything with it. */
811 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
820 set = expand_field_assignment (set);
821 src = SET_SRC (set), dest = SET_DEST (set);
823 /* Don't eliminate a store in the stack pointer. */
824 if (dest == stack_pointer_rtx
825 /* Don't install a subreg involving two modes not tieable.
826 It can worsen register allocation, and can even make invalid reload
827 insns, since the reg inside may need to be copied from in the
828 outside mode, and that may be invalid if it is an fp reg copied in
829 integer mode. As a special exception, we can allow this if
830 I3 is simply copying DEST, a REG, to CC0. */
831 || (GET_CODE (src) == SUBREG
832 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
834 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
835 && SET_DEST (PATTERN (i3)) == cc0_rtx
836 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
839 /* If we couldn't eliminate a field assignment, we can't combine. */
840 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
841 /* Don't combine with an insn that sets a register to itself if it has
842 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
843 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
844 /* Can't merge a function call. */
845 || GET_CODE (src) == CALL
846 /* Don't substitute into an incremented register. */
847 || FIND_REG_INC_NOTE (i3, dest)
848 || (succ && FIND_REG_INC_NOTE (succ, dest))
849 /* Don't combine the end of a libcall into anything. */
850 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
851 /* Make sure that DEST is not used after SUCC but before I3. */
852 || (succ && ! all_adjacent
853 && reg_used_between_p (dest, succ, i3))
854 /* Make sure that the value that is to be substituted for the register
855 does not use any registers whose values alter in between. However,
856 If the insns are adjacent, a use can't cross a set even though we
857 think it might (this can happen for a sequence of insns each setting
858 the same destination; reg_last_set of that register might point to
859 a NOTE). Also, don't move a volatile asm or UNSPEC_VOLATILE across
862 && (use_crosses_set_p (src, INSN_CUID (insn))
863 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
864 || GET_CODE (src) == UNSPEC_VOLATILE))
865 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
866 better register allocation by not doing the combine. */
867 || find_reg_note (i3, REG_NO_CONFLICT, dest)
868 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
869 /* Don't combine across a CALL_INSN, because that would possibly
870 change whether the life span of some REGs crosses calls or not,
871 and it is a pain to update that information.
872 Exception: if source is a constant, moving it later can't hurt.
873 Accept that special case, because it helps -fforce-addr a lot. */
874 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
877 /* DEST must either be a REG or CC0. */
878 if (GET_CODE (dest) == REG)
880 /* If register alignment is being enforced for multi-word items in all
881 cases except for parameters, it is possible to have a register copy
882 insn referencing a hard register that is not allowed to contain the
883 mode being copied and which would not be valid as an operand of most
884 insns. Eliminate this problem by not combining with such an insn.
886 Also, on some machines we don't want to extend the life of a hard
889 if (GET_CODE (src) == REG
890 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
891 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
892 #ifdef SMALL_REGISTER_CLASSES
893 /* Don't extend the life of a hard register. */
894 || REGNO (src) < FIRST_PSEUDO_REGISTER
896 || (REGNO (src) < FIRST_PSEUDO_REGISTER
897 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
902 else if (GET_CODE (dest) != CC0)
905 /* Don't substitute for a register intended as a clobberable operand.
906 Similarly, don't substitute an expression containing a register that
907 will be clobbered in I3. */
908 if (GET_CODE (PATTERN (i3)) == PARALLEL)
909 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
910 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
911 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
913 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
916 /* If INSN contains anything volatile, or is an `asm' (whether volatile
917 or not), reject, unless nothing volatile comes between it and I3,
918 with the exception of SUCC. */
920 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
921 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
922 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
923 && p != succ && volatile_refs_p (PATTERN (p)))
926 /* If INSN or I2 contains an autoincrement or autodecrement,
927 make sure that register is not used between there and I3,
928 and not already used in I3 either.
929 Also insist that I3 not be a jump; if it were one
930 and the incremented register were spilled, we would lose. */
933 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
934 if (REG_NOTE_KIND (link) == REG_INC
935 && (GET_CODE (i3) == JUMP_INSN
936 || reg_used_between_p (XEXP (link, 0), insn, i3)
937 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
942 /* Don't combine an insn that follows a CC0-setting insn.
943 An insn that uses CC0 must not be separated from the one that sets it.
944 We do, however, allow I2 to follow a CC0-setting insn if that insn
945 is passed as I1; in that case it will be deleted also.
946 We also allow combining in this case if all the insns are adjacent
947 because that would leave the two CC0 insns adjacent as well.
948 It would be more logical to test whether CC0 occurs inside I1 or I2,
949 but that would be much slower, and this ought to be equivalent. */
951 p = prev_nonnote_insn (insn);
952 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
957 /* If we get here, we have passed all the tests and the combination is
966 /* LOC is the location within I3 that contains its pattern or the component
967 of a PARALLEL of the pattern. We validate that it is valid for combining.
969 One problem is if I3 modifies its output, as opposed to replacing it
970 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
971 so would produce an insn that is not equivalent to the original insns.
975 (set (reg:DI 101) (reg:DI 100))
976 (set (subreg:SI (reg:DI 101) 0) <foo>)
978 This is NOT equivalent to:
980 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
981 (set (reg:DI 101) (reg:DI 100))])
983 Not only does this modify 100 (in which case it might still be valid
984 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
986 We can also run into a problem if I2 sets a register that I1
987 uses and I1 gets directly substituted into I3 (not via I2). In that
988 case, we would be getting the wrong value of I2DEST into I3, so we
989 must reject the combination. This case occurs when I2 and I1 both
990 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
991 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
992 of a SET must prevent combination from occurring.
994 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
995 if the destination of a SET is a hard register.
997 Before doing the above check, we first try to expand a field assignment
998 into a set of logical operations.
1000 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1001 we place a register that is both set and used within I3. If more than one
1002 such register is detected, we fail.
1004 Return 1 if the combination is valid, zero otherwise. */
1007 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1013 rtx *pi3dest_killed;
1017 if (GET_CODE (x) == SET)
1019 rtx set = expand_field_assignment (x);
1020 rtx dest = SET_DEST (set);
1021 rtx src = SET_SRC (set);
1022 rtx inner_dest = dest, inner_src = src;
1026 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1027 || GET_CODE (inner_dest) == SUBREG
1028 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1029 inner_dest = XEXP (inner_dest, 0);
1031 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1034 while (GET_CODE (inner_src) == STRICT_LOW_PART
1035 || GET_CODE (inner_src) == SUBREG
1036 || GET_CODE (inner_src) == ZERO_EXTRACT)
1037 inner_src = XEXP (inner_src, 0);
1039 /* If it is better that two different modes keep two different pseudos,
1040 avoid combining them. This avoids producing the following pattern
1042 (set (subreg:SI (reg/v:QI 21) 0)
1043 (lshiftrt:SI (reg/v:SI 20)
1045 If that were made, reload could not handle the pair of
1046 reg 20/21, since it would try to get any GENERAL_REGS
1047 but some of them don't handle QImode. */
1049 if (rtx_equal_p (inner_src, i2dest)
1050 && GET_CODE (inner_dest) == REG
1051 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1055 /* Check for the case where I3 modifies its output, as
1057 if ((inner_dest != dest
1058 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1059 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1060 /* This is the same test done in can_combine_p except that we
1061 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1063 || (GET_CODE (inner_dest) == REG
1064 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1065 #ifdef SMALL_REGISTER_CLASSES
1066 && GET_CODE (src) != CALL
1068 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1069 GET_MODE (inner_dest))
1073 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1076 /* If DEST is used in I3, it is being killed in this insn,
1077 so record that for later.
1078 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1079 STACK_POINTER_REGNUM, since these are always considered to be
1080 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1081 if (pi3dest_killed && GET_CODE (dest) == REG
1082 && reg_referenced_p (dest, PATTERN (i3))
1083 && REGNO (dest) != FRAME_POINTER_REGNUM
1084 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1085 && (REGNO (dest) != ARG_POINTER_REGNUM
1086 || ! fixed_regs [REGNO (dest)])
1088 && REGNO (dest) != STACK_POINTER_REGNUM)
1090 if (*pi3dest_killed)
1093 *pi3dest_killed = dest;
1097 else if (GET_CODE (x) == PARALLEL)
1101 for (i = 0; i < XVECLEN (x, 0); i++)
1102 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1103 i1_not_in_src, pi3dest_killed))
1110 /* Try to combine the insns I1 and I2 into I3.
1111 Here I1 and I2 appear earlier than I3.
1112 I1 can be zero; then we combine just I2 into I3.
1114 It we are combining three insns and the resulting insn is not recognized,
1115 try splitting it into two insns. If that happens, I2 and I3 are retained
1116 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1119 If we created two insns, return I2; otherwise return I3.
1120 Return 0 if the combination does not work. Then nothing is changed. */
1123 try_combine (i3, i2, i1)
1124 register rtx i3, i2, i1;
1126 /* New patterns for I3 and I3, respectively. */
1127 rtx newpat, newi2pat = 0;
1128 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1129 int added_sets_1, added_sets_2;
1130 /* Total number of SETs to put into I3. */
1132 /* Nonzero is I2's body now appears in I3. */
1134 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1135 int insn_code_number, i2_code_number, other_code_number;
1136 /* Contains I3 if the destination of I3 is used in its source, which means
1137 that the old life of I3 is being killed. If that usage is placed into
1138 I2 and not in I3, a REG_DEAD note must be made. */
1139 rtx i3dest_killed = 0;
1140 /* SET_DEST and SET_SRC of I2 and I1. */
1141 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1142 /* PATTERN (I2), or a copy of it in certain cases. */
1144 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1145 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1146 int i1_feeds_i3 = 0;
1147 /* Notes that must be added to REG_NOTES in I3 and I2. */
1148 rtx new_i3_notes, new_i2_notes;
1155 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1156 This can occur when flow deletes an insn that it has merged into an
1157 auto-increment address. We also can't do anything if I3 has a
1158 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1161 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1162 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1163 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1164 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1169 undobuf.num_undo = previous_num_undos = 0;
1170 undobuf.other_insn = 0;
1172 /* Save the current high-water-mark so we can free storage if we didn't
1173 accept this combination. */
1174 undobuf.storage = (char *) oballoc (0);
1176 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1177 code below, set I1 to be the earlier of the two insns. */
1178 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1179 temp = i1, i1 = i2, i2 = temp;
1181 /* First check for one important special-case that the code below will
1182 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1183 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1184 we may be able to replace that destination with the destination of I3.
1185 This occurs in the common code where we compute both a quotient and
1186 remainder into a structure, in which case we want to do the computation
1187 directly into the structure to avoid register-register copies.
1189 We make very conservative checks below and only try to handle the
1190 most common cases of this. For example, we only handle the case
1191 where I2 and I3 are adjacent to avoid making difficult register
1194 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1195 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1196 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1197 #ifdef SMALL_REGISTER_CLASSES
1198 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1199 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1201 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1202 && GET_CODE (PATTERN (i2)) == PARALLEL
1203 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1204 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1205 below would need to check what is inside (and reg_overlap_mentioned_p
1206 doesn't support those codes anyway). Don't allow those destinations;
1207 the resulting insn isn't likely to be recognized anyway. */
1208 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1209 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1210 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1211 SET_DEST (PATTERN (i3)))
1212 && next_real_insn (i2) == i3)
1214 rtx p2 = PATTERN (i2);
1216 /* Make sure that the destination of I3,
1217 which we are going to substitute into one output of I2,
1218 is not used within another output of I2. We must avoid making this:
1219 (parallel [(set (mem (reg 69)) ...)
1220 (set (reg 69) ...)])
1221 which is not well-defined as to order of actions.
1222 (Besides, reload can't handle output reloads for this.)
1224 The problem can also happen if the dest of I3 is a memory ref,
1225 if another dest in I2 is an indirect memory ref. */
1226 for (i = 0; i < XVECLEN (p2, 0); i++)
1227 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1228 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1229 SET_DEST (XVECEXP (p2, 0, i))))
1232 if (i == XVECLEN (p2, 0))
1233 for (i = 0; i < XVECLEN (p2, 0); i++)
1234 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1239 subst_low_cuid = INSN_CUID (i2);
1242 i2dest = SET_SRC (PATTERN (i3));
1244 /* Replace the dest in I2 with our dest and make the resulting
1245 insn the new pattern for I3. Then skip to where we
1246 validate the pattern. Everything was set up above. */
1247 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1248 SET_DEST (PATTERN (i3)));
1251 goto validate_replacement;
1256 /* If we have no I1 and I2 looks like:
1257 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1259 make up a dummy I1 that is
1262 (set (reg:CC X) (compare:CC Y (const_int 0)))
1264 (We can ignore any trailing CLOBBERs.)
1266 This undoes a previous combination and allows us to match a branch-and-
1269 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1270 && XVECLEN (PATTERN (i2), 0) >= 2
1271 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1272 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1274 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1275 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1276 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1277 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1278 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1279 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1281 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1282 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1287 /* We make I1 with the same INSN_UID as I2. This gives it
1288 the same INSN_CUID for value tracking. Our fake I1 will
1289 never appear in the insn stream so giving it the same INSN_UID
1290 as I2 will not cause a problem. */
1292 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1293 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1295 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1296 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1297 SET_DEST (PATTERN (i1)));
1302 /* Verify that I2 and I1 are valid for combining. */
1303 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1304 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1310 /* Record whether I2DEST is used in I2SRC and similarly for the other
1311 cases. Knowing this will help in register status updating below. */
1312 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1313 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1314 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1316 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1318 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1320 /* Ensure that I3's pattern can be the destination of combines. */
1321 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1322 i1 && i2dest_in_i1src && i1_feeds_i3,
1329 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1330 We used to do this EXCEPT in one case: I3 has a post-inc in an
1331 output operand. However, that exception can give rise to insns like
1333 which is a famous insn on the PDP-11 where the value of r3 used as the
1334 source was model-dependent. Avoid this sort of thing. */
1337 if (!(GET_CODE (PATTERN (i3)) == SET
1338 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1339 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1340 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1341 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1342 /* It's not the exception. */
1345 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1346 if (REG_NOTE_KIND (link) == REG_INC
1347 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1349 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1356 /* See if the SETs in I1 or I2 need to be kept around in the merged
1357 instruction: whenever the value set there is still needed past I3.
1358 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1360 For the SET in I1, we have two cases: If I1 and I2 independently
1361 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1362 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1363 in I1 needs to be kept around unless I1DEST dies or is set in either
1364 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1365 I1DEST. If so, we know I1 feeds into I2. */
1367 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1370 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1371 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1373 /* If the set in I2 needs to be kept around, we must make a copy of
1374 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1375 PATTERN (I2), we are only substituting for the original I1DEST, not into
1376 an already-substituted copy. This also prevents making self-referential
1377 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1380 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1381 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1385 i2pat = copy_rtx (i2pat);
1389 /* Substitute in the latest insn for the regs set by the earlier ones. */
1391 maxreg = max_reg_num ();
1395 /* It is possible that the source of I2 or I1 may be performing an
1396 unneeded operation, such as a ZERO_EXTEND of something that is known
1397 to have the high part zero. Handle that case by letting subst look at
1398 the innermost one of them.
1400 Another way to do this would be to have a function that tries to
1401 simplify a single insn instead of merging two or more insns. We don't
1402 do this because of the potential of infinite loops and because
1403 of the potential extra memory required. However, doing it the way
1404 we are is a bit of a kludge and doesn't catch all cases.
1406 But only do this if -fexpensive-optimizations since it slows things down
1407 and doesn't usually win. */
1409 if (flag_expensive_optimizations)
1411 /* Pass pc_rtx so no substitutions are done, just simplifications.
1412 The cases that we are interested in here do not involve the few
1413 cases were is_replaced is checked. */
1416 subst_low_cuid = INSN_CUID (i1);
1417 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1421 subst_low_cuid = INSN_CUID (i2);
1422 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1425 previous_num_undos = undobuf.num_undo;
1429 /* Many machines that don't use CC0 have insns that can both perform an
1430 arithmetic operation and set the condition code. These operations will
1431 be represented as a PARALLEL with the first element of the vector
1432 being a COMPARE of an arithmetic operation with the constant zero.
1433 The second element of the vector will set some pseudo to the result
1434 of the same arithmetic operation. If we simplify the COMPARE, we won't
1435 match such a pattern and so will generate an extra insn. Here we test
1436 for this case, where both the comparison and the operation result are
1437 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1438 I2SRC. Later we will make the PARALLEL that contains I2. */
1440 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1441 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1442 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1443 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1446 enum machine_mode compare_mode;
1448 newpat = PATTERN (i3);
1449 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1453 #ifdef EXTRA_CC_MODES
1454 /* See if a COMPARE with the operand we substituted in should be done
1455 with the mode that is currently being used. If not, do the same
1456 processing we do in `subst' for a SET; namely, if the destination
1457 is used only once, try to replace it with a register of the proper
1458 mode and also replace the COMPARE. */
1459 if (undobuf.other_insn == 0
1460 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1461 &undobuf.other_insn))
1462 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1464 != GET_MODE (SET_DEST (newpat))))
1466 int regno = REGNO (SET_DEST (newpat));
1467 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1469 if (regno < FIRST_PSEUDO_REGISTER
1470 || (reg_n_sets[regno] == 1 && ! added_sets_2
1471 && ! REG_USERVAR_P (SET_DEST (newpat))))
1473 if (regno >= FIRST_PSEUDO_REGISTER)
1474 SUBST (regno_reg_rtx[regno], new_dest);
1476 SUBST (SET_DEST (newpat), new_dest);
1477 SUBST (XEXP (*cc_use, 0), new_dest);
1478 SUBST (SET_SRC (newpat),
1479 gen_rtx_combine (COMPARE, compare_mode,
1480 i2src, const0_rtx));
1483 undobuf.other_insn = 0;
1490 n_occurrences = 0; /* `subst' counts here */
1492 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1493 need to make a unique copy of I2SRC each time we substitute it
1494 to avoid self-referential rtl. */
1496 subst_low_cuid = INSN_CUID (i2);
1497 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1498 ! i1_feeds_i3 && i1dest_in_i1src);
1499 previous_num_undos = undobuf.num_undo;
1501 /* Record whether i2's body now appears within i3's body. */
1502 i2_is_used = n_occurrences;
1505 /* If we already got a failure, don't try to do more. Otherwise,
1506 try to substitute in I1 if we have it. */
1508 if (i1 && GET_CODE (newpat) != CLOBBER)
1510 /* Before we can do this substitution, we must redo the test done
1511 above (see detailed comments there) that ensures that I1DEST
1512 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1514 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1522 subst_low_cuid = INSN_CUID (i1);
1523 newpat = subst (newpat, i1dest, i1src, 0, 0);
1524 previous_num_undos = undobuf.num_undo;
1527 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1528 to count all the ways that I2SRC and I1SRC can be used. */
1529 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1530 && i2_is_used + added_sets_2 > 1)
1531 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1532 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1534 /* Fail if we tried to make a new register (we used to abort, but there's
1535 really no reason to). */
1536 || max_reg_num () != maxreg
1537 /* Fail if we couldn't do something and have a CLOBBER. */
1538 || GET_CODE (newpat) == CLOBBER)
1544 /* If the actions of the earlier insns must be kept
1545 in addition to substituting them into the latest one,
1546 we must make a new PARALLEL for the latest insn
1547 to hold additional the SETs. */
1549 if (added_sets_1 || added_sets_2)
1553 if (GET_CODE (newpat) == PARALLEL)
1555 rtvec old = XVEC (newpat, 0);
1556 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1557 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1558 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1559 sizeof (old->elem[0]) * old->num_elem);
1564 total_sets = 1 + added_sets_1 + added_sets_2;
1565 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1566 XVECEXP (newpat, 0, 0) = old;
1570 XVECEXP (newpat, 0, --total_sets)
1571 = (GET_CODE (PATTERN (i1)) == PARALLEL
1572 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1576 /* If there is no I1, use I2's body as is. We used to also not do
1577 the subst call below if I2 was substituted into I3,
1578 but that could lose a simplification. */
1580 XVECEXP (newpat, 0, --total_sets) = i2pat;
1582 /* See comment where i2pat is assigned. */
1583 XVECEXP (newpat, 0, --total_sets)
1584 = subst (i2pat, i1dest, i1src, 0, 0);
1588 /* We come here when we are replacing a destination in I2 with the
1589 destination of I3. */
1590 validate_replacement:
1592 /* Is the result of combination a valid instruction? */
1593 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1595 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1596 the second SET's destination is a register that is unused. In that case,
1597 we just need the first SET. This can occur when simplifying a divmod
1598 insn. We *must* test for this case here because the code below that
1599 splits two independent SETs doesn't handle this case correctly when it
1600 updates the register status. Also check the case where the first
1601 SET's destination is unused. That would not cause incorrect code, but
1602 does cause an unneeded insn to remain. */
1604 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1605 && XVECLEN (newpat, 0) == 2
1606 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1607 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1608 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1609 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1610 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1611 && asm_noperands (newpat) < 0)
1613 newpat = XVECEXP (newpat, 0, 0);
1614 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1617 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1618 && XVECLEN (newpat, 0) == 2
1619 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1620 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1621 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1622 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1623 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1624 && asm_noperands (newpat) < 0)
1626 newpat = XVECEXP (newpat, 0, 1);
1627 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1630 /* See if this is an XOR. If so, perhaps the problem is that the
1631 constant is out of range. Replace it with a complemented XOR with
1632 a complemented constant; it might be in range. */
1634 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1635 && GET_CODE (SET_SRC (newpat)) == XOR
1636 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1637 && ((temp = simplify_unary_operation (NOT,
1638 GET_MODE (SET_SRC (newpat)),
1639 XEXP (SET_SRC (newpat), 1),
1640 GET_MODE (SET_SRC (newpat))))
1643 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1645 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1646 gen_unary (NOT, i_mode,
1647 gen_binary (XOR, i_mode,
1648 XEXP (SET_SRC (newpat), 0),
1651 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1652 if (insn_code_number >= 0)
1656 /* If we were combining three insns and the result is a simple SET
1657 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1658 insns. There are two ways to do this. It can be split using a
1659 machine-specific method (like when you have an addition of a large
1660 constant) or by combine in the function find_split_point. */
1662 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1663 && asm_noperands (newpat) < 0)
1665 rtx m_split, *split;
1666 rtx ni2dest = i2dest;
1668 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1669 use I2DEST as a scratch register will help. In the latter case,
1670 convert I2DEST to the mode of the source of NEWPAT if we can. */
1672 m_split = split_insns (newpat, i3);
1674 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1675 inputs of NEWPAT. */
1677 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1678 possible to try that as a scratch reg. This would require adding
1679 more code to make it work though. */
1681 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1683 /* If I2DEST is a hard register or the only use of a pseudo,
1684 we can change its mode. */
1685 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1686 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1687 && GET_CODE (i2dest) == REG
1688 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1689 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1690 && ! REG_USERVAR_P (i2dest))))
1691 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1694 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1695 gen_rtvec (2, newpat,
1702 if (m_split && GET_CODE (m_split) == SEQUENCE
1703 && XVECLEN (m_split, 0) == 2
1704 && (next_real_insn (i2) == i3
1705 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1709 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1710 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1712 i3set = single_set (XVECEXP (m_split, 0, 1));
1713 i2set = single_set (XVECEXP (m_split, 0, 0));
1715 /* In case we changed the mode of I2DEST, replace it in the
1716 pseudo-register table here. We can't do it above in case this
1717 code doesn't get executed and we do a split the other way. */
1719 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1720 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1722 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1724 /* If I2 or I3 has multiple SETs, we won't know how to track
1725 register status, so don't use these insns. */
1727 if (i2_code_number >= 0 && i2set && i3set)
1728 insn_code_number = recog_for_combine (&newi3pat, i3,
1731 if (insn_code_number >= 0)
1734 /* It is possible that both insns now set the destination of I3.
1735 If so, we must show an extra use of it. */
1737 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1738 && GET_CODE (SET_DEST (i2set)) == REG
1739 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1740 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1743 /* If we can split it and use I2DEST, go ahead and see if that
1744 helps things be recognized. Verify that none of the registers
1745 are set between I2 and I3. */
1746 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1748 && GET_CODE (i2dest) == REG
1750 /* We need I2DEST in the proper mode. If it is a hard register
1751 or the only use of a pseudo, we can change its mode. */
1752 && (GET_MODE (*split) == GET_MODE (i2dest)
1753 || GET_MODE (*split) == VOIDmode
1754 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1755 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1756 && ! REG_USERVAR_P (i2dest)))
1757 && (next_real_insn (i2) == i3
1758 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1759 /* We can't overwrite I2DEST if its value is still used by
1761 && ! reg_referenced_p (i2dest, newpat))
1763 rtx newdest = i2dest;
1765 /* Get NEWDEST as a register in the proper mode. We have already
1766 validated that we can do this. */
1767 if (GET_MODE (i2dest) != GET_MODE (*split)
1768 && GET_MODE (*split) != VOIDmode)
1770 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1772 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1773 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1776 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1777 an ASHIFT. This can occur if it was inside a PLUS and hence
1778 appeared to be a memory address. This is a kludge. */
1779 if (GET_CODE (*split) == MULT
1780 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1781 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1782 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1783 XEXP (*split, 0), GEN_INT (i)));
1785 #ifdef INSN_SCHEDULING
1786 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1787 be written as a ZERO_EXTEND. */
1788 if (GET_CODE (*split) == SUBREG
1789 && GET_CODE (SUBREG_REG (*split)) == MEM)
1790 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1794 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1795 SUBST (*split, newdest);
1796 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1797 if (i2_code_number >= 0)
1798 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1802 /* Check for a case where we loaded from memory in a narrow mode and
1803 then sign extended it, but we need both registers. In that case,
1804 we have a PARALLEL with both loads from the same memory location.
1805 We can split this into a load from memory followed by a register-register
1806 copy. This saves at least one insn, more if register allocation can
1807 eliminate the copy. */
1809 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1810 && GET_CODE (newpat) == PARALLEL
1811 && XVECLEN (newpat, 0) == 2
1812 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1813 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1814 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1815 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1816 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1817 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1819 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1820 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1821 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1822 SET_SRC (XVECEXP (newpat, 0, 1)))
1823 && ! find_reg_note (i3, REG_UNUSED,
1824 SET_DEST (XVECEXP (newpat, 0, 0))))
1828 newi2pat = XVECEXP (newpat, 0, 0);
1829 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1830 newpat = XVECEXP (newpat, 0, 1);
1831 SUBST (SET_SRC (newpat),
1832 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1833 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1834 if (i2_code_number >= 0)
1835 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1837 if (insn_code_number >= 0)
1842 /* If we will be able to accept this, we have made a change to the
1843 destination of I3. This can invalidate a LOG_LINKS pointing
1844 to I3. No other part of combine.c makes such a transformation.
1846 The new I3 will have a destination that was previously the
1847 destination of I1 or I2 and which was used in i2 or I3. Call
1848 distribute_links to make a LOG_LINK from the next use of
1849 that destination. */
1851 PATTERN (i3) = newpat;
1852 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1854 /* I3 now uses what used to be its destination and which is
1855 now I2's destination. That means we need a LOG_LINK from
1856 I3 to I2. But we used to have one, so we still will.
1858 However, some later insn might be using I2's dest and have
1859 a LOG_LINK pointing at I3. We must remove this link.
1860 The simplest way to remove the link is to point it at I1,
1861 which we know will be a NOTE. */
1863 for (insn = NEXT_INSN (i3);
1864 insn && GET_CODE (insn) != CODE_LABEL
1865 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1866 insn = NEXT_INSN (insn))
1868 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1869 && reg_referenced_p (ni2dest, PATTERN (insn)))
1871 for (link = LOG_LINKS (insn); link;
1872 link = XEXP (link, 1))
1873 if (XEXP (link, 0) == i3)
1874 XEXP (link, 0) = i1;
1882 /* Similarly, check for a case where we have a PARALLEL of two independent
1883 SETs but we started with three insns. In this case, we can do the sets
1884 as two separate insns. This case occurs when some SET allows two
1885 other insns to combine, but the destination of that SET is still live. */
1887 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1888 && GET_CODE (newpat) == PARALLEL
1889 && XVECLEN (newpat, 0) == 2
1890 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1891 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1892 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1893 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1894 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1895 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1896 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1898 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1899 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1900 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1901 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1902 XVECEXP (newpat, 0, 0))
1903 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1904 XVECEXP (newpat, 0, 1)))
1906 newi2pat = XVECEXP (newpat, 0, 1);
1907 newpat = XVECEXP (newpat, 0, 0);
1909 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1910 if (i2_code_number >= 0)
1911 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1914 /* If it still isn't recognized, fail and change things back the way they
1916 if ((insn_code_number < 0
1917 /* Is the result a reasonable ASM_OPERANDS? */
1918 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1924 /* If we had to change another insn, make sure it is valid also. */
1925 if (undobuf.other_insn)
1927 rtx other_notes = REG_NOTES (undobuf.other_insn);
1928 rtx other_pat = PATTERN (undobuf.other_insn);
1929 rtx new_other_notes;
1932 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1935 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1941 PATTERN (undobuf.other_insn) = other_pat;
1943 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1944 are still valid. Then add any non-duplicate notes added by
1945 recog_for_combine. */
1946 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1948 next = XEXP (note, 1);
1950 if (REG_NOTE_KIND (note) == REG_UNUSED
1951 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1953 if (GET_CODE (XEXP (note, 0)) == REG)
1954 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1956 remove_note (undobuf.other_insn, note);
1960 for (note = new_other_notes; note; note = XEXP (note, 1))
1961 if (GET_CODE (XEXP (note, 0)) == REG)
1962 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1964 distribute_notes (new_other_notes, undobuf.other_insn,
1965 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1968 /* We now know that we can do this combination. Merge the insns and
1969 update the status of registers and LOG_LINKS. */
1972 rtx i3notes, i2notes, i1notes = 0;
1973 rtx i3links, i2links, i1links = 0;
1975 int all_adjacent = (next_real_insn (i2) == i3
1976 && (i1 == 0 || next_real_insn (i1) == i2));
1978 /* Compute which registers we expect to eliminate. */
1979 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1981 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1983 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1985 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1986 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1988 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1990 /* Ensure that we do not have something that should not be shared but
1991 occurs multiple times in the new insns. Check this by first
1992 resetting all the `used' flags and then copying anything is shared. */
1994 reset_used_flags (i3notes);
1995 reset_used_flags (i2notes);
1996 reset_used_flags (i1notes);
1997 reset_used_flags (newpat);
1998 reset_used_flags (newi2pat);
1999 if (undobuf.other_insn)
2000 reset_used_flags (PATTERN (undobuf.other_insn));
2002 i3notes = copy_rtx_if_shared (i3notes);
2003 i2notes = copy_rtx_if_shared (i2notes);
2004 i1notes = copy_rtx_if_shared (i1notes);
2005 newpat = copy_rtx_if_shared (newpat);
2006 newi2pat = copy_rtx_if_shared (newi2pat);
2007 if (undobuf.other_insn)
2008 reset_used_flags (PATTERN (undobuf.other_insn));
2010 INSN_CODE (i3) = insn_code_number;
2011 PATTERN (i3) = newpat;
2012 if (undobuf.other_insn)
2013 INSN_CODE (undobuf.other_insn) = other_code_number;
2015 /* We had one special case above where I2 had more than one set and
2016 we replaced a destination of one of those sets with the destination
2017 of I3. In that case, we have to update LOG_LINKS of insns later
2018 in this basic block. Note that this (expensive) case is rare. */
2020 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2021 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2022 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2023 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2024 && ! find_reg_note (i2, REG_UNUSED,
2025 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2029 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
2031 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2032 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2033 if (XEXP (link, 0) == i2)
2034 XEXP (link, 0) = i3;
2036 if (GET_CODE (insn) == CODE_LABEL
2037 || GET_CODE (insn) == JUMP_INSN)
2049 INSN_CODE (i2) = i2_code_number;
2050 PATTERN (i2) = newi2pat;
2054 PUT_CODE (i2, NOTE);
2055 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2056 NOTE_SOURCE_FILE (i2) = 0;
2063 PUT_CODE (i1, NOTE);
2064 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2065 NOTE_SOURCE_FILE (i1) = 0;
2068 /* Get death notes for everything that is now used in either I3 or
2069 I2 and used to die in a previous insn. */
2071 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2073 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2075 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2077 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2080 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2083 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2086 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2089 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2090 know these are REG_UNUSED and want them to go to the desired insn,
2091 so we always pass it as i3. We have not counted the notes in
2092 reg_n_deaths yet, so we need to do so now. */
2094 if (newi2pat && new_i2_notes)
2096 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2097 if (GET_CODE (XEXP (temp, 0)) == REG)
2098 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2100 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2105 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2106 if (GET_CODE (XEXP (temp, 0)) == REG)
2107 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2109 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2112 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2113 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2114 Show an additional death due to the REG_DEAD note we make here. If
2115 we discard it in distribute_notes, we will decrement it again. */
2119 if (GET_CODE (i3dest_killed) == REG)
2120 reg_n_deaths[REGNO (i3dest_killed)]++;
2122 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2124 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2125 NULL_RTX, NULL_RTX);
2128 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2129 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2130 we passed I3 in that case, it might delete I2. */
2132 if (i2dest_in_i2src)
2134 if (GET_CODE (i2dest) == REG)
2135 reg_n_deaths[REGNO (i2dest)]++;
2137 if (newi2pat && reg_set_p (i2dest, newi2pat))
2138 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2139 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2141 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2142 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2143 NULL_RTX, NULL_RTX);
2146 if (i1dest_in_i1src)
2148 if (GET_CODE (i1dest) == REG)
2149 reg_n_deaths[REGNO (i1dest)]++;
2151 if (newi2pat && reg_set_p (i1dest, newi2pat))
2152 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2153 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2155 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2156 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2157 NULL_RTX, NULL_RTX);
2160 distribute_links (i3links);
2161 distribute_links (i2links);
2162 distribute_links (i1links);
2164 if (GET_CODE (i2dest) == REG)
2167 rtx i2_insn = 0, i2_val = 0, set;
2169 /* The insn that used to set this register doesn't exist, and
2170 this life of the register may not exist either. See if one of
2171 I3's links points to an insn that sets I2DEST. If it does,
2172 that is now the last known value for I2DEST. If we don't update
2173 this and I2 set the register to a value that depended on its old
2174 contents, we will get confused. If this insn is used, thing
2175 will be set correctly in combine_instructions. */
2177 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2178 if ((set = single_set (XEXP (link, 0))) != 0
2179 && rtx_equal_p (i2dest, SET_DEST (set)))
2180 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2182 record_value_for_reg (i2dest, i2_insn, i2_val);
2184 /* If the reg formerly set in I2 died only once and that was in I3,
2185 zero its use count so it won't make `reload' do any work. */
2186 if (! added_sets_2 && newi2pat == 0)
2188 regno = REGNO (i2dest);
2189 reg_n_sets[regno]--;
2190 if (reg_n_sets[regno] == 0
2191 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2192 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2193 reg_n_refs[regno] = 0;
2197 if (i1 && GET_CODE (i1dest) == REG)
2200 rtx i1_insn = 0, i1_val = 0, set;
2202 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2203 if ((set = single_set (XEXP (link, 0))) != 0
2204 && rtx_equal_p (i1dest, SET_DEST (set)))
2205 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2207 record_value_for_reg (i1dest, i1_insn, i1_val);
2209 regno = REGNO (i1dest);
2212 reg_n_sets[regno]--;
2213 if (reg_n_sets[regno] == 0
2214 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2215 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2216 reg_n_refs[regno] = 0;
2220 /* Update reg_nonzero_bits et al for any changes that may have been made
2223 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2225 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2227 /* If I3 is now an unconditional jump, ensure that it has a
2228 BARRIER following it since it may have initially been a
2229 conditional jump. It may also be the last nonnote insn. */
2231 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2232 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2233 || GET_CODE (temp) != BARRIER))
2234 emit_barrier_after (i3);
2237 combine_successes++;
2239 return newi2pat ? i2 : i3;
2242 /* Undo all the modifications recorded in undobuf. */
2248 if (undobuf.num_undo > MAX_UNDO)
2249 undobuf.num_undo = MAX_UNDO;
2250 for (i = undobuf.num_undo - 1; i >= 0; i--)
2252 if (undobuf.undo[i].is_int)
2253 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2255 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2259 obfree (undobuf.storage);
2260 undobuf.num_undo = 0;
2263 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2264 where we have an arithmetic expression and return that point. LOC will
2267 try_combine will call this function to see if an insn can be split into
2271 find_split_point (loc, insn)
2276 enum rtx_code code = GET_CODE (x);
2278 int len = 0, pos, unsignedp;
2281 /* First special-case some codes. */
2285 #ifdef INSN_SCHEDULING
2286 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2288 if (GET_CODE (SUBREG_REG (x)) == MEM)
2291 return find_split_point (&SUBREG_REG (x), insn);
2295 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2296 using LO_SUM and HIGH. */
2297 if (GET_CODE (XEXP (x, 0)) == CONST
2298 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2301 gen_rtx_combine (LO_SUM, Pmode,
2302 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2304 return &XEXP (XEXP (x, 0), 0);
2308 /* If we have a PLUS whose second operand is a constant and the
2309 address is not valid, perhaps will can split it up using
2310 the machine-specific way to split large constants. We use
2311 the first psuedo-reg (one of the virtual regs) as a placeholder;
2312 it will not remain in the result. */
2313 if (GET_CODE (XEXP (x, 0)) == PLUS
2314 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2315 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2317 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2318 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2321 /* This should have produced two insns, each of which sets our
2322 placeholder. If the source of the second is a valid address,
2323 we can make put both sources together and make a split point
2326 if (seq && XVECLEN (seq, 0) == 2
2327 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2328 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2329 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2330 && ! reg_mentioned_p (reg,
2331 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2332 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2333 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2334 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2335 && memory_address_p (GET_MODE (x),
2336 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2338 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2339 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2341 /* Replace the placeholder in SRC2 with SRC1. If we can
2342 find where in SRC2 it was placed, that can become our
2343 split point and we can replace this address with SRC2.
2344 Just try two obvious places. */
2346 src2 = replace_rtx (src2, reg, src1);
2348 if (XEXP (src2, 0) == src1)
2349 split = &XEXP (src2, 0);
2350 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2351 && XEXP (XEXP (src2, 0), 0) == src1)
2352 split = &XEXP (XEXP (src2, 0), 0);
2356 SUBST (XEXP (x, 0), src2);
2361 /* If that didn't work, perhaps the first operand is complex and
2362 needs to be computed separately, so make a split point there.
2363 This will occur on machines that just support REG + CONST
2364 and have a constant moved through some previous computation. */
2366 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2367 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2368 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2370 return &XEXP (XEXP (x, 0), 0);
2376 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2377 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2378 we need to put the operand into a register. So split at that
2381 if (SET_DEST (x) == cc0_rtx
2382 && GET_CODE (SET_SRC (x)) != COMPARE
2383 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2384 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2385 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2386 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2387 return &SET_SRC (x);
2390 /* See if we can split SET_SRC as it stands. */
2391 split = find_split_point (&SET_SRC (x), insn);
2392 if (split && split != &SET_SRC (x))
2395 /* See if this is a bitfield assignment with everything constant. If
2396 so, this is an IOR of an AND, so split it into that. */
2397 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2398 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2399 <= HOST_BITS_PER_WIDE_INT)
2400 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2401 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2402 && GET_CODE (SET_SRC (x)) == CONST_INT
2403 && ((INTVAL (XEXP (SET_DEST (x), 1))
2404 + INTVAL (XEXP (SET_DEST (x), 2)))
2405 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2406 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2408 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2409 int len = INTVAL (XEXP (SET_DEST (x), 1));
2410 int src = INTVAL (SET_SRC (x));
2411 rtx dest = XEXP (SET_DEST (x), 0);
2412 enum machine_mode mode = GET_MODE (dest);
2413 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2416 pos = GET_MODE_BITSIZE (mode) - len - pos;
2421 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2424 gen_binary (IOR, mode,
2425 gen_binary (AND, mode, dest,
2426 GEN_INT (~ (mask << pos)
2427 & GET_MODE_MASK (mode))),
2428 GEN_INT (src << pos)));
2430 SUBST (SET_DEST (x), dest);
2432 split = find_split_point (&SET_SRC (x), insn);
2433 if (split && split != &SET_SRC (x))
2437 /* Otherwise, see if this is an operation that we can split into two.
2438 If so, try to split that. */
2439 code = GET_CODE (SET_SRC (x));
2444 /* If we are AND'ing with a large constant that is only a single
2445 bit and the result is only being used in a context where we
2446 need to know if it is zero or non-zero, replace it with a bit
2447 extraction. This will avoid the large constant, which might
2448 have taken more than one insn to make. If the constant were
2449 not a valid argument to the AND but took only one insn to make,
2450 this is no worse, but if it took more than one insn, it will
2453 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2454 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2455 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2456 && GET_CODE (SET_DEST (x)) == REG
2457 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2458 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2459 && XEXP (*split, 0) == SET_DEST (x)
2460 && XEXP (*split, 1) == const0_rtx)
2463 make_extraction (GET_MODE (SET_DEST (x)),
2464 XEXP (SET_SRC (x), 0),
2465 pos, NULL_RTX, 1, 1, 0, 0));
2466 return find_split_point (loc, insn);
2471 inner = XEXP (SET_SRC (x), 0);
2473 len = GET_MODE_BITSIZE (GET_MODE (inner));
2479 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2480 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2482 inner = XEXP (SET_SRC (x), 0);
2483 len = INTVAL (XEXP (SET_SRC (x), 1));
2484 pos = INTVAL (XEXP (SET_SRC (x), 2));
2487 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2489 unsignedp = (code == ZERO_EXTRACT);
2494 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2496 enum machine_mode mode = GET_MODE (SET_SRC (x));
2498 /* For unsigned, we have a choice of a shift followed by an
2499 AND or two shifts. Use two shifts for field sizes where the
2500 constant might be too large. We assume here that we can
2501 always at least get 8-bit constants in an AND insn, which is
2502 true for every current RISC. */
2504 if (unsignedp && len <= 8)
2509 gen_rtx_combine (LSHIFTRT, mode,
2510 gen_lowpart_for_combine (mode, inner),
2512 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2514 split = find_split_point (&SET_SRC (x), insn);
2515 if (split && split != &SET_SRC (x))
2522 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2523 gen_rtx_combine (ASHIFT, mode,
2524 gen_lowpart_for_combine (mode, inner),
2525 GEN_INT (GET_MODE_BITSIZE (mode)
2527 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2529 split = find_split_point (&SET_SRC (x), insn);
2530 if (split && split != &SET_SRC (x))
2535 /* See if this is a simple operation with a constant as the second
2536 operand. It might be that this constant is out of range and hence
2537 could be used as a split point. */
2538 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2539 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2540 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2541 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2542 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2543 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2544 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2546 return &XEXP (SET_SRC (x), 1);
2548 /* Finally, see if this is a simple operation with its first operand
2549 not in a register. The operation might require this operand in a
2550 register, so return it as a split point. We can always do this
2551 because if the first operand were another operation, we would have
2552 already found it as a split point. */
2553 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2554 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2555 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2556 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2557 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2558 return &XEXP (SET_SRC (x), 0);
2564 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2565 it is better to write this as (not (ior A B)) so we can split it.
2566 Similarly for IOR. */
2567 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2570 gen_rtx_combine (NOT, GET_MODE (x),
2571 gen_rtx_combine (code == IOR ? AND : IOR,
2573 XEXP (XEXP (x, 0), 0),
2574 XEXP (XEXP (x, 1), 0))));
2575 return find_split_point (loc, insn);
2578 /* Many RISC machines have a large set of logical insns. If the
2579 second operand is a NOT, put it first so we will try to split the
2580 other operand first. */
2581 if (GET_CODE (XEXP (x, 1)) == NOT)
2583 rtx tem = XEXP (x, 0);
2584 SUBST (XEXP (x, 0), XEXP (x, 1));
2585 SUBST (XEXP (x, 1), tem);
2590 /* Otherwise, select our actions depending on our rtx class. */
2591 switch (GET_RTX_CLASS (code))
2593 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2595 split = find_split_point (&XEXP (x, 2), insn);
2598 /* ... fall through ... */
2602 split = find_split_point (&XEXP (x, 1), insn);
2605 /* ... fall through ... */
2607 /* Some machines have (and (shift ...) ...) insns. If X is not
2608 an AND, but XEXP (X, 0) is, use it as our split point. */
2609 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2610 return &XEXP (x, 0);
2612 split = find_split_point (&XEXP (x, 0), insn);
2618 /* Otherwise, we don't have a split point. */
2622 /* Throughout X, replace FROM with TO, and return the result.
2623 The result is TO if X is FROM;
2624 otherwise the result is X, but its contents may have been modified.
2625 If they were modified, a record was made in undobuf so that
2626 undo_all will (among other things) return X to its original state.
2628 If the number of changes necessary is too much to record to undo,
2629 the excess changes are not made, so the result is invalid.
2630 The changes already made can still be undone.
2631 undobuf.num_undo is incremented for such changes, so by testing that
2632 the caller can tell whether the result is valid.
2634 `n_occurrences' is incremented each time FROM is replaced.
2636 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2638 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2639 by copying if `n_occurrences' is non-zero. */
2642 subst (x, from, to, in_dest, unique_copy)
2643 register rtx x, from, to;
2648 register int len, i;
2649 register enum rtx_code code = GET_CODE (x), orig_code = code;
2651 enum machine_mode mode = GET_MODE (x);
2652 enum machine_mode op0_mode = VOIDmode;
2657 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2658 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2659 If it is 0, that cannot be done. We can now do this for any MEM
2660 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2661 If not for that, MEM's would very rarely be safe. */
2663 /* Reject MODEs bigger than a word, because we might not be able
2664 to reference a two-register group starting with an arbitrary register
2665 (and currently gen_lowpart might crash for a SUBREG). */
2667 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2668 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2670 /* Two expressions are equal if they are identical copies of a shared
2671 RTX or if they are both registers with the same register number
2674 #define COMBINE_RTX_EQUAL_P(X,Y) \
2676 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2677 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2679 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2682 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2685 /* If X and FROM are the same register but different modes, they will
2686 not have been seen as equal above. However, flow.c will make a
2687 LOG_LINKS entry for that case. If we do nothing, we will try to
2688 rerecognize our original insn and, when it succeeds, we will
2689 delete the feeding insn, which is incorrect.
2691 So force this insn not to match in this (rare) case. */
2692 if (! in_dest && code == REG && GET_CODE (from) == REG
2693 && REGNO (x) == REGNO (from))
2694 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2696 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2697 of which may contain things that can be combined. */
2698 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2701 /* It is possible to have a subexpression appear twice in the insn.
2702 Suppose that FROM is a register that appears within TO.
2703 Then, after that subexpression has been scanned once by `subst',
2704 the second time it is scanned, TO may be found. If we were
2705 to scan TO here, we would find FROM within it and create a
2706 self-referent rtl structure which is completely wrong. */
2707 if (COMBINE_RTX_EQUAL_P (x, to))
2710 len = GET_RTX_LENGTH (code);
2711 fmt = GET_RTX_FORMAT (code);
2713 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2714 set up to skip this common case. All other cases where we want to
2715 suppress replacing something inside a SET_SRC are handled via the
2718 && (GET_CODE (SET_DEST (x)) == REG
2719 || GET_CODE (SET_DEST (x)) == CC0
2720 || GET_CODE (SET_DEST (x)) == PC))
2723 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2725 op0_mode = GET_MODE (XEXP (x, 0));
2727 for (i = 0; i < len; i++)
2732 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2735 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2737 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2742 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2744 /* If this substitution failed, this whole thing fails. */
2745 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2749 SUBST (XVECEXP (x, i, j), new);
2752 else if (fmt[i] == 'e')
2756 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2758 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2762 /* If we are in a SET_DEST, suppress most cases unless we
2763 have gone inside a MEM, in which case we want to
2764 simplify the address. We assume here that things that
2765 are actually part of the destination have their inner
2766 parts in the first expression. This is true for SUBREG,
2767 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2768 things aside from REG and MEM that should appear in a
2770 new = subst (XEXP (x, i), from, to,
2772 && (code == SUBREG || code == STRICT_LOW_PART
2773 || code == ZERO_EXTRACT))
2775 && i == 0), unique_copy);
2777 /* If we found that we will have to reject this combination,
2778 indicate that by returning the CLOBBER ourselves, rather than
2779 an expression containing it. This will speed things up as
2780 well as prevent accidents where two CLOBBERs are considered
2781 to be equal, thus producing an incorrect simplification. */
2783 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2786 SUBST (XEXP (x, i), new);
2790 /* We come back to here if we have replaced the expression with one of
2791 a different code and it is likely that further simplification will be
2796 /* If we have restarted more than 4 times, we are probably looping, so
2798 if (++n_restarts > 4)
2801 /* If we are restarting at all, it means that we no longer know the
2802 original mode of operand 0 (since we have probably changed the
2806 op0_mode = VOIDmode;
2808 code = GET_CODE (x);
2810 /* If this is a commutative operation, put a constant last and a complex
2811 expression first. We don't need to do this for comparisons here. */
2812 if (GET_RTX_CLASS (code) == 'c'
2813 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2814 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2815 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2816 || (GET_CODE (XEXP (x, 0)) == SUBREG
2817 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2818 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2821 SUBST (XEXP (x, 0), XEXP (x, 1));
2822 SUBST (XEXP (x, 1), temp);
2825 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2826 sign extension of a PLUS with a constant, reverse the order of the sign
2827 extension and the addition. Note that this not the same as the original
2828 code, but overflow is undefined for signed values. Also note that the
2829 PLUS will have been partially moved "inside" the sign-extension, so that
2830 the first operand of X will really look like:
2831 (ashiftrt (plus (ashift A C4) C5) C4).
2833 (plus (ashiftrt (ashift A C4) C2) C4)
2834 and replace the first operand of X with that expression. Later parts
2835 of this function may simplify the expression further.
2837 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2838 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2839 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2841 We do this to simplify address expressions. */
2843 if ((code == PLUS || code == MINUS || code == MULT)
2844 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2845 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2846 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2847 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2848 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2849 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2850 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2851 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2852 XEXP (XEXP (XEXP (x, 0), 0), 1),
2853 XEXP (XEXP (x, 0), 1))) != 0)
2856 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2857 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2858 INTVAL (XEXP (XEXP (x, 0), 1)));
2860 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2861 INTVAL (XEXP (XEXP (x, 0), 1)));
2863 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2866 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2867 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2868 things. Don't deal with operations that change modes here. */
2870 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2871 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2873 /* Don't do this by using SUBST inside X since we might be messing
2874 up a shared expression. */
2875 rtx cond = XEXP (XEXP (x, 0), 0);
2876 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2878 pc_rtx, pc_rtx, 0, 0);
2879 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2881 pc_rtx, pc_rtx, 0, 0);
2884 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2888 else if (GET_RTX_CLASS (code) == '1'
2889 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2890 && GET_MODE (XEXP (x, 0)) == mode)
2892 rtx cond = XEXP (XEXP (x, 0), 0);
2893 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2894 pc_rtx, pc_rtx, 0, 0);
2895 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2896 pc_rtx, pc_rtx, 0, 0);
2898 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2902 /* Try to fold this expression in case we have constants that weren't
2905 switch (GET_RTX_CLASS (code))
2908 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2911 temp = simplify_relational_operation (code, op0_mode,
2912 XEXP (x, 0), XEXP (x, 1));
2913 #ifdef FLOAT_STORE_FLAG_VALUE
2914 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2915 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2916 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2921 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2925 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2926 XEXP (x, 1), XEXP (x, 2));
2931 x = temp, code = GET_CODE (temp);
2933 /* First see if we can apply the inverse distributive law. */
2934 if (code == PLUS || code == MINUS
2935 || code == AND || code == IOR || code == XOR)
2937 x = apply_distributive_law (x);
2938 code = GET_CODE (x);
2941 /* If CODE is an associative operation not otherwise handled, see if we
2942 can associate some operands. This can win if they are constants or
2943 if they are logically related (i.e. (a & b) & a. */
2944 if ((code == PLUS || code == MINUS
2945 || code == MULT || code == AND || code == IOR || code == XOR
2946 || code == DIV || code == UDIV
2947 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2948 && INTEGRAL_MODE_P (mode))
2950 if (GET_CODE (XEXP (x, 0)) == code)
2952 rtx other = XEXP (XEXP (x, 0), 0);
2953 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2954 rtx inner_op1 = XEXP (x, 1);
2957 /* Make sure we pass the constant operand if any as the second
2958 one if this is a commutative operation. */
2959 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2961 rtx tem = inner_op0;
2962 inner_op0 = inner_op1;
2965 inner = simplify_binary_operation (code == MINUS ? PLUS
2966 : code == DIV ? MULT
2967 : code == UDIV ? MULT
2969 mode, inner_op0, inner_op1);
2971 /* For commutative operations, try the other pair if that one
2973 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2975 other = XEXP (XEXP (x, 0), 1);
2976 inner = simplify_binary_operation (code, mode,
2977 XEXP (XEXP (x, 0), 0),
2983 x = gen_binary (code, mode, other, inner);
2990 /* A little bit of algebraic simplification here. */
2994 /* Ensure that our address has any ASHIFTs converted to MULT in case
2995 address-recognizing predicates are called later. */
2996 temp = make_compound_operation (XEXP (x, 0), MEM);
2997 SUBST (XEXP (x, 0), temp);
3001 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3002 is paradoxical. If we can't do that safely, then it becomes
3003 something nonsensical so that this combination won't take place. */
3005 if (GET_CODE (SUBREG_REG (x)) == MEM
3006 && (GET_MODE_SIZE (mode)
3007 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3009 rtx inner = SUBREG_REG (x);
3010 int endian_offset = 0;
3011 /* Don't change the mode of the MEM
3012 if that would change the meaning of the address. */
3013 if (MEM_VOLATILE_P (SUBREG_REG (x))
3014 || mode_dependent_address_p (XEXP (inner, 0)))
3015 return gen_rtx (CLOBBER, mode, const0_rtx);
3017 #if BYTES_BIG_ENDIAN
3018 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3019 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3020 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3021 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
3023 /* Note if the plus_constant doesn't make a valid address
3024 then this combination won't be accepted. */
3025 x = gen_rtx (MEM, mode,
3026 plus_constant (XEXP (inner, 0),
3027 (SUBREG_WORD (x) * UNITS_PER_WORD
3029 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3030 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3031 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3035 /* If we are in a SET_DEST, these other cases can't apply. */
3039 /* Changing mode twice with SUBREG => just change it once,
3040 or not at all if changing back to starting mode. */
3041 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3043 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3044 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3045 return SUBREG_REG (SUBREG_REG (x));
3047 SUBST_INT (SUBREG_WORD (x),
3048 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3049 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3052 /* SUBREG of a hard register => just change the register number
3053 and/or mode. If the hard register is not valid in that mode,
3054 suppress this combination. If the hard register is the stack,
3055 frame, or argument pointer, leave this as a SUBREG. */
3057 if (GET_CODE (SUBREG_REG (x)) == REG
3058 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3059 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3060 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3061 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3063 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3065 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3067 return gen_rtx (REG, mode,
3068 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3070 return gen_rtx (CLOBBER, mode, const0_rtx);
3073 /* For a constant, try to pick up the part we want. Handle a full
3074 word and low-order part. Only do this if we are narrowing
3075 the constant; if it is being widened, we have no idea what
3076 the extra bits will have been set to. */
3078 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3079 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3080 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3081 && GET_MODE_CLASS (mode) == MODE_INT)
3083 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3089 /* If we want a subreg of a constant, at offset 0,
3090 take the low bits. On a little-endian machine, that's
3091 always valid. On a big-endian machine, it's valid
3092 only if the constant's mode fits in one word. */
3093 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3094 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)
3095 #if WORDS_BIG_ENDIAN
3096 && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD
3099 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3101 /* If we are narrowing the object, we need to see if we can simplify
3102 the expression for the object knowing that we only need the
3105 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3106 && subreg_lowpart_p (x))
3107 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
3112 /* (not (plus X -1)) can become (neg X). */
3113 if (GET_CODE (XEXP (x, 0)) == PLUS
3114 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3116 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3120 /* Similarly, (not (neg X)) is (plus X -1). */
3121 if (GET_CODE (XEXP (x, 0)) == NEG)
3123 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3127 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3128 if (GET_CODE (XEXP (x, 0)) == XOR
3129 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3130 && (temp = simplify_unary_operation (NOT, mode,
3131 XEXP (XEXP (x, 0), 1),
3134 SUBST (XEXP (XEXP (x, 0), 1), temp);
3138 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3139 other than 1, but that is not valid. We could do a similar
3140 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3141 but this doesn't seem common enough to bother with. */
3142 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3143 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3145 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3146 XEXP (XEXP (x, 0), 1));
3150 if (GET_CODE (XEXP (x, 0)) == SUBREG
3151 && subreg_lowpart_p (XEXP (x, 0))
3152 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3153 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3154 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3155 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3157 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3159 x = gen_rtx (ROTATE, inner_mode,
3160 gen_unary (NOT, inner_mode, const1_rtx),
3161 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3162 x = gen_lowpart_for_combine (mode, x);
3166 #if STORE_FLAG_VALUE == -1
3167 /* (not (comparison foo bar)) can be done by reversing the comparison
3169 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3170 && reversible_comparison_p (XEXP (x, 0)))
3171 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3172 mode, XEXP (XEXP (x, 0), 0),
3173 XEXP (XEXP (x, 0), 1));
3175 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3176 is (lt foo (const_int 0)), so we can perform the above
3179 if (XEXP (x, 1) == const1_rtx
3180 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3181 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3182 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3183 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3186 /* Apply De Morgan's laws to reduce number of patterns for machines
3187 with negating logical insns (and-not, nand, etc.). If result has
3188 only one NOT, put it first, since that is how the patterns are
3191 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3193 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3195 if (GET_CODE (in1) == NOT)
3196 in1 = XEXP (in1, 0);
3198 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3200 if (GET_CODE (in2) == NOT)
3201 in2 = XEXP (in2, 0);
3202 else if (GET_CODE (in2) == CONST_INT
3203 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3204 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3206 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3208 if (GET_CODE (in2) == NOT)
3211 in2 = in1; in1 = tem;
3214 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3221 /* (neg (plus X 1)) can become (not X). */
3222 if (GET_CODE (XEXP (x, 0)) == PLUS
3223 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3225 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3229 /* Similarly, (neg (not X)) is (plus X 1). */
3230 if (GET_CODE (XEXP (x, 0)) == NOT)
3232 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3236 /* (neg (minus X Y)) can become (minus Y X). */
3237 if (GET_CODE (XEXP (x, 0)) == MINUS
3238 && (! FLOAT_MODE_P (mode)
3239 /* x-y != -(y-x) with IEEE floating point. */
3240 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3242 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3243 XEXP (XEXP (x, 0), 0));
3247 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3248 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3249 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3251 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3255 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3256 if we can then eliminate the NEG (e.g.,
3257 if the operand is a constant). */
3259 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3261 temp = simplify_unary_operation (NEG, mode,
3262 XEXP (XEXP (x, 0), 0), mode);
3265 SUBST (XEXP (XEXP (x, 0), 0), temp);
3270 temp = expand_compound_operation (XEXP (x, 0));
3272 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3273 replaced by (lshiftrt X C). This will convert
3274 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3276 if (GET_CODE (temp) == ASHIFTRT
3277 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3278 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3280 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3281 INTVAL (XEXP (temp, 1)));
3285 /* If X has only a single bit that might be nonzero, say, bit I, convert
3286 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3287 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3288 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3289 or a SUBREG of one since we'd be making the expression more
3290 complex if it was just a register. */
3292 if (GET_CODE (temp) != REG
3293 && ! (GET_CODE (temp) == SUBREG
3294 && GET_CODE (SUBREG_REG (temp)) == REG)
3295 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3297 rtx temp1 = simplify_shift_const
3298 (NULL_RTX, ASHIFTRT, mode,
3299 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3300 GET_MODE_BITSIZE (mode) - 1 - i),
3301 GET_MODE_BITSIZE (mode) - 1 - i);
3303 /* If all we did was surround TEMP with the two shifts, we
3304 haven't improved anything, so don't use it. Otherwise,
3305 we are better off with TEMP1. */
3306 if (GET_CODE (temp1) != ASHIFTRT
3307 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3308 || XEXP (XEXP (temp1, 0), 0) != temp)
3316 case FLOAT_TRUNCATE:
3317 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3318 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3319 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3320 return XEXP (XEXP (x, 0), 0);
3325 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3326 using cc0, in which case we want to leave it as a COMPARE
3327 so we can distinguish it from a register-register-copy. */
3328 if (XEXP (x, 1) == const0_rtx)
3331 /* In IEEE floating point, x-0 is not the same as x. */
3332 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3333 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))))
3334 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3340 /* (const (const X)) can become (const X). Do it this way rather than
3341 returning the inner CONST since CONST can be shared with a
3343 if (GET_CODE (XEXP (x, 0)) == CONST)
3344 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3349 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3350 can add in an offset. find_split_point will split this address up
3351 again if it doesn't match. */
3352 if (GET_CODE (XEXP (x, 0)) == HIGH
3353 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3359 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3360 outermost. That's because that's the way indexed addresses are
3361 supposed to appear. This code used to check many more cases, but
3362 they are now checked elsewhere. */
3363 if (GET_CODE (XEXP (x, 0)) == PLUS
3364 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3365 return gen_binary (PLUS, mode,
3366 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3368 XEXP (XEXP (x, 0), 1));
3370 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3371 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3372 bit-field and can be replaced by either a sign_extend or a
3373 sign_extract. The `and' may be a zero_extend. */
3374 if (GET_CODE (XEXP (x, 0)) == XOR
3375 && GET_CODE (XEXP (x, 1)) == CONST_INT
3376 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3377 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3378 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3379 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3380 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3381 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3382 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3383 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3384 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3385 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3388 x = simplify_shift_const
3389 (NULL_RTX, ASHIFTRT, mode,
3390 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3391 XEXP (XEXP (XEXP (x, 0), 0), 0),
3392 GET_MODE_BITSIZE (mode) - (i + 1)),
3393 GET_MODE_BITSIZE (mode) - (i + 1));
3397 /* If only the low-order bit of X is possible nonzero, (plus x -1)
3398 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3399 the bitsize of the mode - 1. This allows simplification of
3400 "a = (b & 8) == 0;" */
3401 if (XEXP (x, 1) == constm1_rtx
3402 && GET_CODE (XEXP (x, 0)) != REG
3403 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3404 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3405 && nonzero_bits (XEXP (x, 0), mode) == 1)
3407 x = simplify_shift_const
3408 (NULL_RTX, ASHIFTRT, mode,
3409 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3410 gen_rtx_combine (XOR, mode,
3411 XEXP (x, 0), const1_rtx),
3412 GET_MODE_BITSIZE (mode) - 1),
3413 GET_MODE_BITSIZE (mode) - 1);
3417 /* If we are adding two things that have no bits in common, convert
3418 the addition into an IOR. This will often be further simplified,
3419 for example in cases like ((a & 1) + (a & 2)), which can
3422 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3423 && (nonzero_bits (XEXP (x, 0), mode)
3424 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3426 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3432 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3433 (and <foo> (const_int pow2-1)) */
3434 if (GET_CODE (XEXP (x, 1)) == AND
3435 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3436 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3437 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3439 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3440 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3446 /* If we have (mult (plus A B) C), apply the distributive law and then
3447 the inverse distributive law to see if things simplify. This
3448 occurs mostly in addresses, often when unrolling loops. */
3450 if (GET_CODE (XEXP (x, 0)) == PLUS)
3452 x = apply_distributive_law
3453 (gen_binary (PLUS, mode,
3454 gen_binary (MULT, mode,
3455 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3456 gen_binary (MULT, mode,
3457 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3459 if (GET_CODE (x) != MULT)
3463 /* If this is multiplication by a power of two and its first operand is
3464 a shift, treat the multiply as a shift to allow the shifts to
3465 possibly combine. */
3466 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3467 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3468 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3469 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3470 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3471 || GET_CODE (XEXP (x, 0)) == ROTATE
3472 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3474 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3478 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3479 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3480 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3481 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3482 XEXP (XEXP (x, 0), 1));
3486 /* If this is a divide by a power of two, treat it as a shift if
3487 its first operand is a shift. */
3488 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3489 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3490 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3491 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3492 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3493 || GET_CODE (XEXP (x, 0)) == ROTATE
3494 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3496 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3502 case GT: case GTU: case GE: case GEU:
3503 case LT: case LTU: case LE: case LEU:
3504 /* If the first operand is a condition code, we can't do anything
3506 if (GET_CODE (XEXP (x, 0)) == COMPARE
3507 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3509 && XEXP (x, 0) != cc0_rtx
3513 rtx op0 = XEXP (x, 0);
3514 rtx op1 = XEXP (x, 1);
3515 enum rtx_code new_code;
3517 if (GET_CODE (op0) == COMPARE)
3518 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3520 /* Simplify our comparison, if possible. */
3521 new_code = simplify_comparison (code, &op0, &op1);
3523 #if STORE_FLAG_VALUE == 1
3524 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3525 if only the low-order bit is possibly nonzero in X (such as when
3526 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3527 EQ to (xor X 1). Remove any ZERO_EXTRACT we made when thinking
3528 this was a comparison. It may now be simpler to use, e.g., an
3529 AND. If a ZERO_EXTRACT is indeed appropriate, it will
3530 be placed back by the call to make_compound_operation in the
3532 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3533 && op1 == const0_rtx
3534 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3535 return gen_lowpart_for_combine (mode,
3536 expand_compound_operation (op0));
3537 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3538 && op1 == const0_rtx
3539 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3541 op0 = expand_compound_operation (op0);
3543 x = gen_rtx_combine (XOR, mode,
3544 gen_lowpart_for_combine (mode, op0),
3550 #if STORE_FLAG_VALUE == -1
3551 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3552 to (neg x) if only the low-order bit of X can be nonzero.
3553 This converts (ne (zero_extract X 1 Y) 0) to
3554 (sign_extract X 1 Y). */
3555 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3556 && op1 == const0_rtx
3557 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3559 op0 = expand_compound_operation (op0);
3560 x = gen_rtx_combine (NEG, mode,
3561 gen_lowpart_for_combine (mode, op0));
3566 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3567 one bit that might be nonzero, we can convert (ne x 0) to
3568 (ashift x c) where C puts the bit in the sign bit. Remove any
3569 AND with STORE_FLAG_VALUE when we are done, since we are only
3570 going to test the sign bit. */
3571 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3572 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3573 && (STORE_FLAG_VALUE
3574 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3575 && op1 == const0_rtx
3576 && mode == GET_MODE (op0)
3577 && (i = exact_log2 (nonzero_bits (op0, GET_MODE (op0)))) >= 0)
3579 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3580 expand_compound_operation (op0),
3581 GET_MODE_BITSIZE (mode) - 1 - i);
3582 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3588 /* If the code changed, return a whole new comparison. */
3589 if (new_code != code)
3590 return gen_rtx_combine (new_code, mode, op0, op1);
3592 /* Otherwise, keep this operation, but maybe change its operands.
3593 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3594 SUBST (XEXP (x, 0), op0);
3595 SUBST (XEXP (x, 1), op1);
3600 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3601 used in it is being compared against certain values. Get the
3602 true and false comparisons and see if that says anything about the
3603 value of each arm. */
3605 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3606 && reversible_comparison_p (XEXP (x, 0))
3607 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3610 rtx from = XEXP (XEXP (x, 0), 0);
3611 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3612 enum rtx_code false_code = reverse_condition (true_code);
3613 rtx true_val = XEXP (XEXP (x, 0), 1);
3614 rtx false_val = true_val;
3615 rtx true_arm = XEXP (x, 1);
3616 rtx false_arm = XEXP (x, 2);
3619 /* If FALSE_CODE is EQ, swap the codes and arms. */
3621 if (false_code == EQ)
3623 swapped = 1, true_code = EQ, false_code = NE;
3624 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3627 /* If we are comparing against zero and the expression being tested
3628 has only a single bit that might be nonzero, that is its value
3629 when it is not equal to zero. Similarly if it is known to be
3632 if (true_code == EQ && true_val == const0_rtx
3633 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3634 false_code = EQ, false_val = GEN_INT (nzb);
3635 else if (true_code == EQ && true_val == const0_rtx
3636 && (num_sign_bit_copies (from, GET_MODE (from))
3637 == GET_MODE_BITSIZE (GET_MODE (from))))
3638 false_code = EQ, false_val = constm1_rtx;
3640 /* Now simplify an arm if we know the value of the register
3641 in the branch and it is used in the arm. Be carefull due to
3642 the potential of locally-shared RTL. */
3644 if (reg_mentioned_p (from, true_arm))
3645 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3647 pc_rtx, pc_rtx, 0, 0);
3648 if (reg_mentioned_p (from, false_arm))
3649 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3651 pc_rtx, pc_rtx, 0, 0);
3653 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3654 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3657 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3658 reversed, do so to avoid needing two sets of patterns for
3659 subtract-and-branch insns. Similarly if we have a constant in that
3660 position or if the third operand is the same as the first operand
3661 of the comparison. */
3663 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3664 && reversible_comparison_p (XEXP (x, 0))
3665 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3666 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3669 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3670 GET_MODE (XEXP (x, 0)),
3671 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3674 SUBST (XEXP (x, 1), XEXP (x, 2));
3675 SUBST (XEXP (x, 2), temp);
3678 /* If the two arms are identical, we don't need the comparison. */
3680 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3681 && ! side_effects_p (XEXP (x, 0)))
3684 /* Look for cases where we have (abs x) or (neg (abs X)). */
3686 if (GET_MODE_CLASS (mode) == MODE_INT
3687 && GET_CODE (XEXP (x, 2)) == NEG
3688 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3689 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3690 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3691 && ! side_effects_p (XEXP (x, 1)))
3692 switch (GET_CODE (XEXP (x, 0)))
3696 x = gen_unary (ABS, mode, XEXP (x, 1));
3700 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3704 /* Look for MIN or MAX. */
3706 if (! FLOAT_MODE_P (mode)
3707 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3708 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3709 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3710 && ! side_effects_p (XEXP (x, 0)))
3711 switch (GET_CODE (XEXP (x, 0)))
3715 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3719 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3723 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3727 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3731 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3732 A is known to be either 0 or 1, and OP is an identity when its
3733 second operand is zero, this can be done as (OP X (mult A C)).
3734 Similarly if A is known to be 0 or -1 and also similarly if we have
3735 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3736 we don't destroy it). */
3738 if (mode != VOIDmode
3739 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3740 && XEXP (XEXP (x, 0), 1) == const0_rtx
3741 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3742 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3743 == GET_MODE_BITSIZE (mode))))
3745 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3746 ? XEXP (x, 1) : XEXP (x, 2));
3747 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3748 rtx dir = (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3749 ? const1_rtx : constm1_rtx);
3751 enum machine_mode m = mode;
3752 enum rtx_code op, extend_op = 0;
3754 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3755 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3756 || GET_CODE (nz) == ASHIFT
3757 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3758 && rtx_equal_p (XEXP (nz, 0), z))
3759 c = XEXP (nz, 1), op = GET_CODE (nz);
3760 else if (GET_CODE (nz) == SIGN_EXTEND
3761 && (GET_CODE (XEXP (nz, 0)) == PLUS
3762 || GET_CODE (XEXP (nz, 0)) == MINUS
3763 || GET_CODE (XEXP (nz, 0)) == IOR
3764 || GET_CODE (XEXP (nz, 0)) == XOR
3765 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3766 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3767 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3768 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3769 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3770 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3771 && (num_sign_bit_copies (z, GET_MODE (z))
3772 >= (GET_MODE_BITSIZE (mode)
3773 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3775 c = XEXP (XEXP (nz, 0), 1);
3776 op = GET_CODE (XEXP (nz, 0));
3777 extend_op = SIGN_EXTEND;
3778 m = GET_MODE (XEXP (nz, 0));
3780 else if (GET_CODE (nz) == ZERO_EXTEND
3781 && (GET_CODE (XEXP (nz, 0)) == PLUS
3782 || GET_CODE (XEXP (nz, 0)) == MINUS
3783 || GET_CODE (XEXP (nz, 0)) == IOR
3784 || GET_CODE (XEXP (nz, 0)) == XOR
3785 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3786 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3787 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3788 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3789 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3790 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3791 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3792 && ((nonzero_bits (z, GET_MODE (z))
3793 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3796 c = XEXP (XEXP (nz, 0), 1);
3797 op = GET_CODE (XEXP (nz, 0));
3798 extend_op = ZERO_EXTEND;
3799 m = GET_MODE (XEXP (nz, 0));
3802 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3805 = gen_binary (MULT, m,
3806 gen_lowpart_for_combine (m,
3807 XEXP (XEXP (x, 0), 0)),
3808 gen_binary (MULT, m, c, dir));
3810 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3813 temp = gen_unary (extend_op, mode, temp);
3819 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to
3820 be 0 or 1 and C1 is a single bit or A is known to be 0 or -1 and
3821 C1 is the negation of a single bit, we can convert this operation
3822 to a shift. We can actually do this in more general cases, but it
3823 doesn't seem worth it. */
3825 if (GET_CODE (XEXP (x, 0)) == NE && XEXP (XEXP (x, 0), 1) == const0_rtx
3826 && XEXP (x, 2) == const0_rtx && GET_CODE (XEXP (x, 1)) == CONST_INT
3827 && ((1 == nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
3828 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
3829 || ((num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3830 == GET_MODE_BITSIZE (mode))
3831 && (i = exact_log2 (- INTVAL (XEXP (x, 1)))) >= 0)))
3833 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3834 gen_lowpart_for_combine (mode,
3835 XEXP (XEXP (x, 0), 0)),
3843 /* If we are processing SET_DEST, we are done. */
3847 x = expand_compound_operation (x);
3848 if (GET_CODE (x) != code)
3853 /* (set (pc) (return)) gets written as (return). */
3854 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3857 /* Convert this into a field assignment operation, if possible. */
3858 x = make_field_assignment (x);
3860 /* If we are setting CC0 or if the source is a COMPARE, look for the
3861 use of the comparison result and try to simplify it unless we already
3862 have used undobuf.other_insn. */
3863 if ((GET_CODE (SET_SRC (x)) == COMPARE
3865 || SET_DEST (x) == cc0_rtx
3868 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3870 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3871 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3872 && XEXP (*cc_use, 0) == SET_DEST (x))
3874 enum rtx_code old_code = GET_CODE (*cc_use);
3875 enum rtx_code new_code;
3877 int other_changed = 0;
3878 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3880 if (GET_CODE (SET_SRC (x)) == COMPARE)
3881 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3883 op0 = SET_SRC (x), op1 = const0_rtx;
3885 /* Simplify our comparison, if possible. */
3886 new_code = simplify_comparison (old_code, &op0, &op1);
3888 #ifdef EXTRA_CC_MODES
3889 /* If this machine has CC modes other than CCmode, check to see
3890 if we need to use a different CC mode here. */
3891 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3892 #endif /* EXTRA_CC_MODES */
3894 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3895 /* If the mode changed, we have to change SET_DEST, the mode
3896 in the compare, and the mode in the place SET_DEST is used.
3897 If SET_DEST is a hard register, just build new versions with
3898 the proper mode. If it is a pseudo, we lose unless it is only
3899 time we set the pseudo, in which case we can safely change
3901 if (compare_mode != GET_MODE (SET_DEST (x)))
3903 int regno = REGNO (SET_DEST (x));
3904 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3906 if (regno < FIRST_PSEUDO_REGISTER
3907 || (reg_n_sets[regno] == 1
3908 && ! REG_USERVAR_P (SET_DEST (x))))
3910 if (regno >= FIRST_PSEUDO_REGISTER)
3911 SUBST (regno_reg_rtx[regno], new_dest);
3913 SUBST (SET_DEST (x), new_dest);
3914 SUBST (XEXP (*cc_use, 0), new_dest);
3920 /* If the code changed, we have to build a new comparison
3921 in undobuf.other_insn. */
3922 if (new_code != old_code)
3924 unsigned HOST_WIDE_INT mask;
3926 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3927 SET_DEST (x), const0_rtx));
3929 /* If the only change we made was to change an EQ into an
3930 NE or vice versa, OP0 has only one bit that might be nonzero,
3931 and OP1 is zero, check if changing the user of the condition
3932 code will produce a valid insn. If it won't, we can keep
3933 the original code in that insn by surrounding our operation
3936 if (((old_code == NE && new_code == EQ)
3937 || (old_code == EQ && new_code == NE))
3938 && ! other_changed && op1 == const0_rtx
3939 && (GET_MODE_BITSIZE (GET_MODE (op0))
3940 <= HOST_BITS_PER_WIDE_INT)
3941 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
3944 rtx pat = PATTERN (other_insn), note = 0;
3946 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
3947 && ! check_asm_operands (pat)))
3949 PUT_CODE (*cc_use, old_code);
3952 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3961 undobuf.other_insn = other_insn;
3964 /* If we are now comparing against zero, change our source if
3965 needed. If we do not use cc0, we always have a COMPARE. */
3966 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3967 SUBST (SET_SRC (x), op0);
3971 /* Otherwise, if we didn't previously have a COMPARE in the
3972 correct mode, we need one. */
3973 if (GET_CODE (SET_SRC (x)) != COMPARE
3974 || GET_MODE (SET_SRC (x)) != compare_mode)
3975 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3979 /* Otherwise, update the COMPARE if needed. */
3980 SUBST (XEXP (SET_SRC (x), 0), op0);
3981 SUBST (XEXP (SET_SRC (x), 1), op1);
3986 /* Get SET_SRC in a form where we have placed back any
3987 compound expressions. Then do the checks below. */
3988 temp = make_compound_operation (SET_SRC (x), SET);
3989 SUBST (SET_SRC (x), temp);
3992 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3993 operation, and X being a REG or (subreg (reg)), we may be able to
3994 convert this to (set (subreg:m2 x) (op)).
3996 We can always do this if M1 is narrower than M2 because that
3997 means that we only care about the low bits of the result.
3999 However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND
4000 nor BYTES_LOADS_SIGN_EXTEND defined), we cannot perform a
4001 narrower operation that requested since the high-order bits will
4002 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
4003 however, this transformation is safe as long as M1 and M2 have
4004 the same number of words. */
4006 if (GET_CODE (SET_SRC (x)) == SUBREG
4007 && subreg_lowpart_p (SET_SRC (x))
4008 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
4009 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
4011 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
4012 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4013 #ifndef BYTE_LOADS_EXTEND
4014 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4015 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4017 && (GET_CODE (SET_DEST (x)) == REG
4018 || (GET_CODE (SET_DEST (x)) == SUBREG
4019 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
4021 SUBST (SET_DEST (x),
4022 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
4024 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
4027 #ifdef BYTE_LOADS_EXTEND
4028 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
4029 M wider than N, this would require a paradoxical subreg.
4030 Replace the subreg with a zero_extend to avoid the reload that
4031 would otherwise be required. */
4033 if (GET_CODE (SET_SRC (x)) == SUBREG
4034 && subreg_lowpart_p (SET_SRC (x))
4035 && SUBREG_WORD (SET_SRC (x)) == 0
4036 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
4037 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
4038 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
4039 SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND,
4040 GET_MODE (SET_SRC (x)),
4041 XEXP (SET_SRC (x), 0)));
4044 #ifndef HAVE_conditional_move
4046 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
4047 and we are comparing an item known to be 0 or -1 against 0, use a
4048 logical operation instead. Check for one of the arms being an IOR
4049 of the other arm with some value. We compute three terms to be
4050 IOR'ed together. In practice, at most two will be nonzero. Then
4053 if (GET_CODE (SET_DEST (x)) != PC
4054 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
4055 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
4056 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
4057 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
4058 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
4059 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
4060 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
4061 && ! side_effects_p (SET_SRC (x)))
4063 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4064 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
4065 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
4066 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
4067 rtx term1 = const0_rtx, term2, term3;
4069 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4070 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4071 else if (GET_CODE (true) == IOR
4072 && rtx_equal_p (XEXP (true, 1), false))
4073 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4074 else if (GET_CODE (false) == IOR
4075 && rtx_equal_p (XEXP (false, 0), true))
4076 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4077 else if (GET_CODE (false) == IOR
4078 && rtx_equal_p (XEXP (false, 1), true))
4079 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4081 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4082 XEXP (XEXP (SET_SRC (x), 0), 0), true);
4083 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4084 gen_unary (NOT, GET_MODE (SET_SRC (x)),
4085 XEXP (XEXP (SET_SRC (x), 0), 0)),
4089 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4090 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4098 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4100 x = simplify_and_const_int (x, mode, XEXP (x, 0),
4101 INTVAL (XEXP (x, 1)));
4103 /* If we have (ior (and (X C1) C2)) and the next restart would be
4104 the last, simplify this by making C1 as small as possible
4106 if (n_restarts >= 3 && GET_CODE (x) == IOR
4107 && GET_CODE (XEXP (x, 0)) == AND
4108 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4109 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4111 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
4112 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
4113 & ~ INTVAL (XEXP (x, 1))));
4114 return gen_binary (IOR, mode, temp, XEXP (x, 1));
4117 if (GET_CODE (x) != AND)
4121 /* Convert (A | B) & A to A. */
4122 if (GET_CODE (XEXP (x, 0)) == IOR
4123 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4124 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4125 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4126 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4129 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4130 insn (and may simplify more). */
4131 else if (GET_CODE (XEXP (x, 0)) == XOR
4132 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4133 && ! side_effects_p (XEXP (x, 1)))
4135 x = gen_binary (AND, mode,
4136 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4140 else if (GET_CODE (XEXP (x, 0)) == XOR
4141 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4142 && ! side_effects_p (XEXP (x, 1)))
4144 x = gen_binary (AND, mode,
4145 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4150 /* Similarly for (~ (A ^ B)) & A. */
4151 else if (GET_CODE (XEXP (x, 0)) == NOT
4152 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4153 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
4154 && ! side_effects_p (XEXP (x, 1)))
4156 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
4160 else if (GET_CODE (XEXP (x, 0)) == NOT
4161 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4162 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
4163 && ! side_effects_p (XEXP (x, 1)))
4165 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
4170 /* If we have (and A B) with A not an object but that is known to
4171 be -1 or 0, this is equivalent to the expression
4172 (if_then_else (ne A (const_int 0)) B (const_int 0))
4173 We make this conversion because it may allow further
4174 simplifications and then allow use of conditional move insns.
4175 If the machine doesn't have condition moves, code in case SET
4176 will convert the IF_THEN_ELSE back to the logical operation.
4177 We build the IF_THEN_ELSE here in case further simplification
4178 is possible (e.g., we can convert it to ABS). */
4180 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4181 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4182 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4183 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4184 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4186 rtx op0 = XEXP (x, 0);
4187 rtx op1 = const0_rtx;
4188 enum rtx_code comp_code
4189 = simplify_comparison (NE, &op0, &op1);
4191 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4192 gen_binary (comp_code, VOIDmode, op0, op1),
4193 XEXP (x, 1), const0_rtx);
4197 /* In the following group of tests (and those in case IOR below),
4198 we start with some combination of logical operations and apply
4199 the distributive law followed by the inverse distributive law.
4200 Most of the time, this results in no change. However, if some of
4201 the operands are the same or inverses of each other, simplifications
4204 For example, (and (ior A B) (not B)) can occur as the result of
4205 expanding a bit field assignment. When we apply the distributive
4206 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4207 which then simplifies to (and (A (not B))). */
4209 /* If we have (and (ior A B) C), apply the distributive law and then
4210 the inverse distributive law to see if things simplify. */
4212 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4214 x = apply_distributive_law
4215 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4216 gen_binary (AND, mode,
4217 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4218 gen_binary (AND, mode,
4219 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4220 if (GET_CODE (x) != AND)
4224 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4226 x = apply_distributive_law
4227 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4228 gen_binary (AND, mode,
4229 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4230 gen_binary (AND, mode,
4231 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4232 if (GET_CODE (x) != AND)
4236 /* Similarly, taking advantage of the fact that
4237 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4239 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4241 x = apply_distributive_law
4242 (gen_binary (XOR, mode,
4243 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4244 XEXP (XEXP (x, 1), 0)),
4245 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4246 XEXP (XEXP (x, 1), 1))));
4247 if (GET_CODE (x) != AND)
4251 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4253 x = apply_distributive_law
4254 (gen_binary (XOR, mode,
4255 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4256 XEXP (XEXP (x, 0), 0)),
4257 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4258 XEXP (XEXP (x, 0), 1))));
4259 if (GET_CODE (x) != AND)
4265 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4266 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4267 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4268 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4271 /* Convert (A & B) | A to A. */
4272 if (GET_CODE (XEXP (x, 0)) == AND
4273 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4274 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4275 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4276 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4279 /* If we have (ior (and A B) C), apply the distributive law and then
4280 the inverse distributive law to see if things simplify. */
4282 if (GET_CODE (XEXP (x, 0)) == AND)
4284 x = apply_distributive_law
4285 (gen_binary (AND, mode,
4286 gen_binary (IOR, mode,
4287 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4288 gen_binary (IOR, mode,
4289 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4291 if (GET_CODE (x) != IOR)
4295 if (GET_CODE (XEXP (x, 1)) == AND)
4297 x = apply_distributive_law
4298 (gen_binary (AND, mode,
4299 gen_binary (IOR, mode,
4300 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4301 gen_binary (IOR, mode,
4302 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4304 if (GET_CODE (x) != IOR)
4308 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4309 mode size to (rotate A CX). */
4311 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4312 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4313 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4314 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4315 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4317 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4318 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4319 == GET_MODE_BITSIZE (mode)))
4323 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4324 shift_count = XEXP (XEXP (x, 0), 1);
4326 shift_count = XEXP (XEXP (x, 1), 1);
4327 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4333 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4334 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4337 int num_negated = 0;
4338 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4340 if (GET_CODE (in1) == NOT)
4341 num_negated++, in1 = XEXP (in1, 0);
4342 if (GET_CODE (in2) == NOT)
4343 num_negated++, in2 = XEXP (in2, 0);
4345 if (num_negated == 2)
4347 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4348 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4350 else if (num_negated == 1)
4352 x = gen_unary (NOT, mode,
4353 gen_binary (XOR, mode, in1, in2));
4358 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4359 correspond to a machine insn or result in further simplifications
4360 if B is a constant. */
4362 if (GET_CODE (XEXP (x, 0)) == AND
4363 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4364 && ! side_effects_p (XEXP (x, 1)))
4366 x = gen_binary (AND, mode,
4367 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4371 else if (GET_CODE (XEXP (x, 0)) == AND
4372 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4373 && ! side_effects_p (XEXP (x, 1)))
4375 x = gen_binary (AND, mode,
4376 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4382 #if STORE_FLAG_VALUE == 1
4383 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4385 if (XEXP (x, 1) == const1_rtx
4386 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4387 && reversible_comparison_p (XEXP (x, 0)))
4388 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4389 mode, XEXP (XEXP (x, 0), 0),
4390 XEXP (XEXP (x, 0), 1));
4392 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4393 is (lt foo (const_int 0)), so we can perform the above
4396 if (XEXP (x, 1) == const1_rtx
4397 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4398 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4399 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
4400 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
4403 /* (xor (comparison foo bar) (const_int sign-bit))
4404 when STORE_FLAG_VALUE is the sign bit. */
4405 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4406 && (STORE_FLAG_VALUE
4407 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4408 && XEXP (x, 1) == const_true_rtx
4409 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4410 && reversible_comparison_p (XEXP (x, 0)))
4411 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4412 mode, XEXP (XEXP (x, 0), 0),
4413 XEXP (XEXP (x, 0), 1));
4417 /* (abs (neg <foo>)) -> (abs <foo>) */
4418 if (GET_CODE (XEXP (x, 0)) == NEG)
4419 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4421 /* If operand is something known to be positive, ignore the ABS. */
4422 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4423 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4424 <= HOST_BITS_PER_WIDE_INT)
4425 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4426 & ((HOST_WIDE_INT) 1
4427 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4432 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4433 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4435 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4441 /* (ffs (*_extend <X>)) = (ffs <X>) */
4442 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4443 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4444 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4448 /* (float (sign_extend <X>)) = (float <X>). */
4449 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4450 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4459 /* If this is a shift by a constant amount, simplify it. */
4460 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4462 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4463 INTVAL (XEXP (x, 1)));
4464 if (GET_CODE (x) != code)
4468 #ifdef SHIFT_COUNT_TRUNCATED
4469 else if (GET_CODE (XEXP (x, 1)) != REG)
4471 force_to_mode (XEXP (x, 1), GET_MODE (x),
4472 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4482 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4483 operations" because they can be replaced with two more basic operations.
4484 ZERO_EXTEND is also considered "compound" because it can be replaced with
4485 an AND operation, which is simpler, though only one operation.
4487 The function expand_compound_operation is called with an rtx expression
4488 and will convert it to the appropriate shifts and AND operations,
4489 simplifying at each stage.
4491 The function make_compound_operation is called to convert an expression
4492 consisting of shifts and ANDs into the equivalent compound expression.
4493 It is the inverse of this function, loosely speaking. */
4496 expand_compound_operation (x)
4504 switch (GET_CODE (x))
4509 /* We can't necessarily use a const_int for a multiword mode;
4510 it depends on implicitly extending the value.
4511 Since we don't know the right way to extend it,
4512 we can't tell whether the implicit way is right.
4514 Even for a mode that is no wider than a const_int,
4515 we can't win, because we need to sign extend one of its bits through
4516 the rest of it, and we don't know which bit. */
4517 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4520 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4523 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4524 /* If the inner object has VOIDmode (the only way this can happen
4525 is if it is a ASM_OPERANDS), we can't do anything since we don't
4526 know how much masking to do. */
4535 /* If the operand is a CLOBBER, just return it. */
4536 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4539 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4540 || GET_CODE (XEXP (x, 2)) != CONST_INT
4541 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4544 len = INTVAL (XEXP (x, 1));
4545 pos = INTVAL (XEXP (x, 2));
4547 /* If this goes outside the object being extracted, replace the object
4548 with a (use (mem ...)) construct that only combine understands
4549 and is used only for this purpose. */
4550 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4551 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4554 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4562 /* If we reach here, we want to return a pair of shifts. The inner
4563 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4564 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4565 logical depending on the value of UNSIGNEDP.
4567 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4568 converted into an AND of a shift.
4570 We must check for the case where the left shift would have a negative
4571 count. This can happen in a case like (x >> 31) & 255 on machines
4572 that can't shift by a constant. On those machines, we would first
4573 combine the shift with the AND to produce a variable-position
4574 extraction. Then the constant of 31 would be substituted in to produce
4575 a such a position. */
4577 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4578 if (modewidth >= pos - len)
4579 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4581 simplify_shift_const (NULL_RTX, ASHIFT,
4584 modewidth - pos - len),
4587 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4588 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4589 simplify_shift_const (NULL_RTX, LSHIFTRT,
4592 ((HOST_WIDE_INT) 1 << len) - 1);
4594 /* Any other cases we can't handle. */
4598 /* If we couldn't do this for some reason, return the original
4600 if (GET_CODE (tem) == CLOBBER)
4606 /* X is a SET which contains an assignment of one object into
4607 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4608 or certain SUBREGS). If possible, convert it into a series of
4611 We half-heartedly support variable positions, but do not at all
4612 support variable lengths. */
4615 expand_field_assignment (x)
4619 rtx pos; /* Always counts from low bit. */
4622 enum machine_mode compute_mode;
4624 /* Loop until we find something we can't simplify. */
4627 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4628 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4630 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4631 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4634 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4635 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4637 inner = XEXP (SET_DEST (x), 0);
4638 len = INTVAL (XEXP (SET_DEST (x), 1));
4639 pos = XEXP (SET_DEST (x), 2);
4641 /* If the position is constant and spans the width of INNER,
4642 surround INNER with a USE to indicate this. */
4643 if (GET_CODE (pos) == CONST_INT
4644 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4645 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4648 if (GET_CODE (pos) == CONST_INT)
4649 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4651 else if (GET_CODE (pos) == MINUS
4652 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4653 && (INTVAL (XEXP (pos, 1))
4654 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4655 /* If position is ADJUST - X, new position is X. */
4656 pos = XEXP (pos, 0);
4658 pos = gen_binary (MINUS, GET_MODE (pos),
4659 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4665 /* A SUBREG between two modes that occupy the same numbers of words
4666 can be done by moving the SUBREG to the source. */
4667 else if (GET_CODE (SET_DEST (x)) == SUBREG
4668 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4669 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4670 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4671 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4673 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4674 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4681 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4682 inner = SUBREG_REG (inner);
4684 compute_mode = GET_MODE (inner);
4686 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4687 if (len < HOST_BITS_PER_WIDE_INT)
4688 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4692 /* Now compute the equivalent expression. Make a copy of INNER
4693 for the SET_DEST in case it is a MEM into which we will substitute;
4694 we don't want shared RTL in that case. */
4695 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4696 gen_binary (IOR, compute_mode,
4697 gen_binary (AND, compute_mode,
4698 gen_unary (NOT, compute_mode,
4703 gen_binary (ASHIFT, compute_mode,
4704 gen_binary (AND, compute_mode,
4705 gen_lowpart_for_combine
4715 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4716 it is an RTX that represents a variable starting position; otherwise,
4717 POS is the (constant) starting bit position (counted from the LSB).
4719 INNER may be a USE. This will occur when we started with a bitfield
4720 that went outside the boundary of the object in memory, which is
4721 allowed on most machines. To isolate this case, we produce a USE
4722 whose mode is wide enough and surround the MEM with it. The only
4723 code that understands the USE is this routine. If it is not removed,
4724 it will cause the resulting insn not to match.
4726 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4729 IN_DEST is non-zero if this is a reference in the destination of a
4730 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4731 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4734 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4735 ZERO_EXTRACT should be built even for bits starting at bit 0.
4737 MODE is the desired mode of the result (if IN_DEST == 0). */
4740 make_extraction (mode, inner, pos, pos_rtx, len,
4741 unsignedp, in_dest, in_compare)
4742 enum machine_mode mode;
4748 int in_dest, in_compare;
4750 /* This mode describes the size of the storage area
4751 to fetch the overall value from. Within that, we
4752 ignore the POS lowest bits, etc. */
4753 enum machine_mode is_mode = GET_MODE (inner);
4754 enum machine_mode inner_mode;
4755 enum machine_mode wanted_mem_mode = byte_mode;
4756 enum machine_mode pos_mode = word_mode;
4757 enum machine_mode extraction_mode = word_mode;
4758 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4761 rtx orig_pos_rtx = pos_rtx;
4763 /* Get some information about INNER and get the innermost object. */
4764 if (GET_CODE (inner) == USE)
4765 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4766 /* We don't need to adjust the position because we set up the USE
4767 to pretend that it was a full-word object. */
4768 spans_byte = 1, inner = XEXP (inner, 0);
4769 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4771 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4772 consider just the QI as the memory to extract from.
4773 The subreg adds or removes high bits; its mode is
4774 irrelevant to the meaning of this extraction,
4775 since POS and LEN count from the lsb. */
4776 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4777 is_mode = GET_MODE (SUBREG_REG (inner));
4778 inner = SUBREG_REG (inner);
4781 inner_mode = GET_MODE (inner);
4783 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4784 pos = INTVAL (pos_rtx), pos_rtx = 0;
4786 /* See if this can be done without an extraction. We never can if the
4787 width of the field is not the same as that of some integer mode. For
4788 registers, we can only avoid the extraction if the position is at the
4789 low-order bit and this is either not in the destination or we have the
4790 appropriate STRICT_LOW_PART operation available.
4792 For MEM, we can avoid an extract if the field starts on an appropriate
4793 boundary and we can change the mode of the memory reference. However,
4794 we cannot directly access the MEM if we have a USE and the underlying
4795 MEM is not TMODE. This combination means that MEM was being used in a
4796 context where bits outside its mode were being referenced; that is only
4797 valid in bit-field insns. */
4799 if (tmode != BLKmode
4800 && ! (spans_byte && inner_mode != tmode)
4801 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
4803 || (GET_CODE (inner) == REG
4804 && (movstrict_optab->handlers[(int) tmode].insn_code
4805 != CODE_FOR_nothing))))
4806 || (GET_CODE (inner) == MEM && pos_rtx == 0
4808 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4809 : BITS_PER_UNIT)) == 0
4810 /* We can't do this if we are widening INNER_MODE (it
4811 may not be aligned, for one thing). */
4812 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4813 && (inner_mode == tmode
4814 || (! mode_dependent_address_p (XEXP (inner, 0))
4815 && ! MEM_VOLATILE_P (inner))))))
4817 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4818 field. If the original and current mode are the same, we need not
4819 adjust the offset. Otherwise, we do if bytes big endian.
4821 If INNER is not a MEM, get a piece consisting of the just the field
4822 of interest (in this case POS must be 0). */
4824 if (GET_CODE (inner) == MEM)
4827 /* POS counts from lsb, but make OFFSET count in memory order. */
4828 if (BYTES_BIG_ENDIAN)
4829 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4831 offset = pos / BITS_PER_UNIT;
4833 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4834 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4835 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4836 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4838 else if (GET_CODE (inner) == REG)
4839 /* We can't call gen_lowpart_for_combine here since we always want
4840 a SUBREG and it would sometimes return a new hard register. */
4841 new = gen_rtx (SUBREG, tmode, inner,
4843 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4844 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
4848 new = force_to_mode (inner, tmode, len, NULL_RTX);
4850 /* If this extraction is going into the destination of a SET,
4851 make a STRICT_LOW_PART unless we made a MEM. */
4854 return (GET_CODE (new) == MEM ? new
4855 : (GET_CODE (new) != SUBREG
4856 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4857 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4859 /* Otherwise, sign- or zero-extend unless we already are in the
4862 return (mode == tmode ? new
4863 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4867 /* Unless this is a COMPARE or we have a funny memory reference,
4868 don't do anything with zero-extending field extracts starting at
4869 the low-order bit since they are simple AND operations. */
4870 if (pos_rtx == 0 && pos == 0 && ! in_dest
4871 && ! in_compare && ! spans_byte && unsignedp)
4874 /* Get the mode to use should INNER be a MEM, the mode for the position,
4875 and the mode for the result. */
4879 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4880 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4881 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4886 if (! in_dest && unsignedp)
4888 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4889 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4890 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4895 if (! in_dest && ! unsignedp)
4897 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4898 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4899 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4903 /* Never narrow an object, since that might not be safe. */
4905 if (mode != VOIDmode
4906 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4907 extraction_mode = mode;
4909 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4910 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4911 pos_mode = GET_MODE (pos_rtx);
4913 /* If this is not from memory or we have to change the mode of memory and
4914 cannot, the desired mode is EXTRACTION_MODE. */
4915 if (GET_CODE (inner) != MEM
4916 || (inner_mode != wanted_mem_mode
4917 && (mode_dependent_address_p (XEXP (inner, 0))
4918 || MEM_VOLATILE_P (inner))))
4919 wanted_mem_mode = extraction_mode;
4922 /* If position is constant, compute new position. Otherwise, build
4925 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4929 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4930 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4931 GET_MODE_BITSIZE (wanted_mem_mode))
4936 /* If INNER has a wider mode, make it smaller. If this is a constant
4937 extract, try to adjust the byte to point to the byte containing
4939 if (wanted_mem_mode != VOIDmode
4940 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4941 && ((GET_CODE (inner) == MEM
4942 && (inner_mode == wanted_mem_mode
4943 || (! mode_dependent_address_p (XEXP (inner, 0))
4944 && ! MEM_VOLATILE_P (inner))))))
4948 /* The computations below will be correct if the machine is big
4949 endian in both bits and bytes or little endian in bits and bytes.
4950 If it is mixed, we must adjust. */
4952 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4953 adjust OFFSET to compensate. */
4954 #if BYTES_BIG_ENDIAN
4956 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4957 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4960 /* If this is a constant position, we can move to the desired byte. */
4963 offset += pos / BITS_PER_UNIT;
4964 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4967 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4968 if (! spans_byte && is_mode != wanted_mem_mode)
4969 offset = (GET_MODE_SIZE (is_mode)
4970 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4973 if (offset != 0 || inner_mode != wanted_mem_mode)
4975 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4976 plus_constant (XEXP (inner, 0), offset));
4977 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4978 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4979 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4984 /* If INNER is not memory, we can always get it into the proper mode. */
4985 else if (GET_CODE (inner) != MEM)
4986 inner = force_to_mode (inner, extraction_mode,
4987 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4991 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4992 have to zero extend. Otherwise, we can just use a SUBREG. */
4994 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4995 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4996 else if (pos_rtx != 0
4997 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4998 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5000 /* Make POS_RTX unless we already have it and it is correct. If we don't
5001 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5003 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5004 pos_rtx = orig_pos_rtx;
5006 else if (pos_rtx == 0)
5007 pos_rtx = GEN_INT (pos);
5009 /* Make the required operation. See if we can use existing rtx. */
5010 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5011 extraction_mode, inner, GEN_INT (len), pos_rtx);
5013 new = gen_lowpart_for_combine (mode, new);
5018 /* Look at the expression rooted at X. Look for expressions
5019 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5020 Form these expressions.
5022 Return the new rtx, usually just X.
5024 Also, for machines like the Vax that don't have logical shift insns,
5025 try to convert logical to arithmetic shift operations in cases where
5026 they are equivalent. This undoes the canonicalizations to logical
5027 shifts done elsewhere.
5029 We try, as much as possible, to re-use rtl expressions to save memory.
5031 IN_CODE says what kind of expression we are processing. Normally, it is
5032 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5033 being kludges), it is MEM. When processing the arguments of a comparison
5034 or a COMPARE against zero, it is COMPARE. */
5037 make_compound_operation (x, in_code)
5039 enum rtx_code in_code;
5041 enum rtx_code code = GET_CODE (x);
5042 enum machine_mode mode = GET_MODE (x);
5043 int mode_width = GET_MODE_BITSIZE (mode);
5044 enum rtx_code next_code;
5050 /* Select the code to be used in recursive calls. Once we are inside an
5051 address, we stay there. If we have a comparison, set to COMPARE,
5052 but once inside, go back to our default of SET. */
5054 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5055 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5056 && XEXP (x, 1) == const0_rtx) ? COMPARE
5057 : in_code == COMPARE ? SET : in_code);
5059 /* Process depending on the code of this operation. If NEW is set
5060 non-zero, it will be returned. */
5066 /* Convert shifts by constants into multiplications if inside
5068 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5069 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5070 && INTVAL (XEXP (x, 1)) >= 0)
5072 new = make_compound_operation (XEXP (x, 0), next_code);
5073 new = gen_rtx_combine (MULT, mode, new,
5074 GEN_INT ((HOST_WIDE_INT) 1
5075 << INTVAL (XEXP (x, 1))));
5080 /* If the second operand is not a constant, we can't do anything
5082 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5085 /* If the constant is a power of two minus one and the first operand
5086 is a logical right shift, make an extraction. */
5087 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5088 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5090 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5091 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5092 0, in_code == COMPARE);
5095 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5096 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5097 && subreg_lowpart_p (XEXP (x, 0))
5098 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5099 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5101 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5103 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5104 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5105 0, in_code == COMPARE);
5108 /* If we are have (and (rotate X C) M) and C is larger than the number
5109 of bits in M, this is an extraction. */
5111 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5112 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5113 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5114 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5116 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5117 new = make_extraction (mode, new,
5118 (GET_MODE_BITSIZE (mode)
5119 - INTVAL (XEXP (XEXP (x, 0), 1))),
5120 NULL_RTX, i, 1, 0, in_code == COMPARE);
5123 /* On machines without logical shifts, if the operand of the AND is
5124 a logical shift and our mask turns off all the propagated sign
5125 bits, we can replace the logical shift with an arithmetic shift. */
5126 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5127 && (lshr_optab->handlers[(int) mode].insn_code
5128 == CODE_FOR_nothing)
5129 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5130 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5131 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5132 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5133 && mode_width <= HOST_BITS_PER_WIDE_INT)
5135 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5137 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5138 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5140 gen_rtx_combine (ASHIFTRT, mode,
5141 make_compound_operation (XEXP (XEXP (x, 0), 0),
5143 XEXP (XEXP (x, 0), 1)));
5146 /* If the constant is one less than a power of two, this might be
5147 representable by an extraction even if no shift is present.
5148 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5149 we are in a COMPARE. */
5150 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5151 new = make_extraction (mode,
5152 make_compound_operation (XEXP (x, 0),
5154 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5156 /* If we are in a comparison and this is an AND with a power of two,
5157 convert this into the appropriate bit extract. */
5158 else if (in_code == COMPARE
5159 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5160 new = make_extraction (mode,
5161 make_compound_operation (XEXP (x, 0),
5163 i, NULL_RTX, 1, 1, 0, 1);
5168 /* If the sign bit is known to be zero, replace this with an
5169 arithmetic shift. */
5170 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5171 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5172 && mode_width <= HOST_BITS_PER_WIDE_INT
5173 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5175 new = gen_rtx_combine (ASHIFTRT, mode,
5176 make_compound_operation (XEXP (x, 0),
5182 /* ... fall through ... */
5185 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5186 this is a SIGN_EXTRACT. */
5187 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5188 && GET_CODE (XEXP (x, 0)) == ASHIFT
5189 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5190 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5192 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5193 new = make_extraction (mode, new,
5194 (INTVAL (XEXP (x, 1))
5195 - INTVAL (XEXP (XEXP (x, 0), 1))),
5196 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5197 code == LSHIFTRT, 0, in_code == COMPARE);
5200 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5201 cases, we are better off returning a SIGN_EXTEND of the operation. */
5203 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5204 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5205 || GET_CODE (XEXP (x, 0)) == XOR
5206 || GET_CODE (XEXP (x, 0)) == PLUS)
5207 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5208 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5209 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5210 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5211 && 0 == (INTVAL (XEXP (XEXP (x, 0), 1))
5212 & (((HOST_WIDE_INT) 1
5213 << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)),
5214 INTVAL (XEXP (x, 1)))
5217 rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1);
5218 rtx c2 = XEXP (x, 1);
5219 rtx c3 = XEXP (XEXP (x, 0), 1);
5220 HOST_WIDE_INT newop1;
5221 rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0);
5223 /* If C1 > C2, INNER needs to have the shift performed on it
5225 if (INTVAL (c1) > INTVAL (c2))
5227 inner = gen_binary (ASHIFT, mode, inner,
5228 GEN_INT (INTVAL (c1) - INTVAL (c2)));
5232 newop1 = INTVAL (c3) >> INTVAL (c1);
5233 new = make_compound_operation (inner,
5234 GET_CODE (XEXP (x, 0)) == PLUS
5235 ? MEM : GET_CODE (XEXP (x, 0)));
5236 new = make_extraction (mode,
5237 gen_binary (GET_CODE (XEXP (x, 0)), mode, new,
5239 INTVAL (c2) - INTVAL (c1),
5240 NULL_RTX, mode_width - INTVAL (c2),
5241 code == LSHIFTRT, 0, in_code == COMPARE);
5244 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5245 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5246 && GET_CODE (XEXP (x, 0)) == NEG
5247 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5248 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5249 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5251 new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0),
5253 new = make_extraction (mode,
5254 gen_unary (GET_CODE (XEXP (x, 0)), mode,
5256 (INTVAL (XEXP (x, 1))
5257 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5258 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5259 code == LSHIFTRT, 0, in_code == COMPARE);
5264 /* Call ourselves recursively on the inner expression. If we are
5265 narrowing the object and it has a different RTL code from
5266 what it originally did, do this SUBREG as a force_to_mode. */
5268 tem = make_compound_operation (SUBREG_REG (x), in_code);
5269 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5270 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5271 && subreg_lowpart_p (x))
5273 rtx newer = force_to_mode (tem, mode,
5274 GET_MODE_BITSIZE (mode), NULL_RTX);
5276 /* If we have something other than a SUBREG, we might have
5277 done an expansion, so rerun outselves. */
5278 if (GET_CODE (newer) != SUBREG)
5279 newer = make_compound_operation (newer, in_code);
5287 x = gen_lowpart_for_combine (mode, new);
5288 code = GET_CODE (x);
5291 /* Now recursively process each operand of this operation. */
5292 fmt = GET_RTX_FORMAT (code);
5293 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5296 new = make_compound_operation (XEXP (x, i), next_code);
5297 SUBST (XEXP (x, i), new);
5303 /* Given M see if it is a value that would select a field of bits
5304 within an item, but not the entire word. Return -1 if not.
5305 Otherwise, return the starting position of the field, where 0 is the
5308 *PLEN is set to the length of the field. */
5311 get_pos_from_mask (m, plen)
5312 unsigned HOST_WIDE_INT m;
5315 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5316 int pos = exact_log2 (m & - m);
5321 /* Now shift off the low-order zero bits and see if we have a power of
5323 *plen = exact_log2 ((m >> pos) + 1);
5331 /* Rewrite X so that it is an expression in MODE. We only care about the
5332 low-order BITS bits so we can ignore AND operations that just clear
5335 Also, if REG is non-zero and X is a register equal in value to REG,
5336 replace X with REG. */
5339 force_to_mode (x, mode, bits, reg)
5341 enum machine_mode mode;
5345 enum rtx_code code = GET_CODE (x);
5346 enum machine_mode op_mode = mode;
5348 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5349 just get X in the proper mode. */
5351 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5352 || bits > GET_MODE_BITSIZE (mode))
5353 return gen_lowpart_for_combine (mode, x);
5361 x = expand_compound_operation (x);
5362 if (GET_CODE (x) != code)
5363 return force_to_mode (x, mode, bits, reg);
5367 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5368 || rtx_equal_p (reg, get_last_value (x))))
5373 if (bits < HOST_BITS_PER_WIDE_INT)
5374 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5378 /* Ignore low-order SUBREGs. */
5379 if (subreg_lowpart_p (x))
5380 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5384 /* If this is an AND with a constant. Otherwise, we fall through to
5385 do the general binary case. */
5387 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5389 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5390 int len = exact_log2 (mask + 1);
5391 rtx op = XEXP (x, 0);
5393 /* If this is masking some low-order bits, we may be able to
5394 impose a stricter constraint on what bits of the operand are
5397 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5400 if (bits < HOST_BITS_PER_WIDE_INT)
5401 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5403 /* If we have no AND in MODE, use the original mode for the
5406 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5407 op_mode = GET_MODE (x);
5409 x = simplify_and_const_int (x, op_mode, op, mask);
5411 /* If X is still an AND, see if it is an AND with a mask that
5412 is just some low-order bits. If so, and it is BITS wide (it
5413 can't be wider), we don't need it. */
5415 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5416 && bits < HOST_BITS_PER_WIDE_INT
5417 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5423 /* ... fall through ... */
5430 /* For most binary operations, just propagate into the operation and
5431 change the mode if we have an operation of that mode. */
5434 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5436 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5437 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5438 == CODE_FOR_nothing))
5440 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5442 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5443 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5444 == CODE_FOR_nothing)))
5445 op_mode = GET_MODE (x);
5447 x = gen_binary (code, op_mode,
5448 gen_lowpart_for_combine (op_mode,
5449 force_to_mode (XEXP (x, 0),
5452 gen_lowpart_for_combine (op_mode,
5453 force_to_mode (XEXP (x, 1),
5460 /* For left shifts, do the same, but just for the first operand.
5461 However, we cannot do anything with shifts where we cannot
5462 guarantee that the counts are smaller than the size of the mode
5463 because such a count will have a different meaning in a
5466 If we can narrow the shift and know the count, we need even fewer
5467 bits of the first operand. */
5469 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
5470 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
5471 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
5472 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
5473 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
5476 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5477 bits -= INTVAL (XEXP (x, 1));
5480 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5481 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5482 == CODE_FOR_nothing)))
5483 op_mode = GET_MODE (x);
5485 x = gen_binary (code, op_mode,
5486 gen_lowpart_for_combine (op_mode,
5487 force_to_mode (XEXP (x, 0),
5494 /* Here we can only do something if the shift count is a constant and
5495 the count plus BITS is no larger than the width of MODE. In that
5496 case, we can do the shift in MODE. */
5498 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5499 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5501 rtx inner = force_to_mode (XEXP (x, 0), mode,
5502 bits + INTVAL (XEXP (x, 1)), reg);
5504 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5505 op_mode = GET_MODE (x);
5507 x = gen_binary (LSHIFTRT, op_mode,
5508 gen_lowpart_for_combine (op_mode, inner),
5514 /* If this is a sign-extension operation that just affects bits
5515 we don't care about, remove it. */
5517 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5518 && INTVAL (XEXP (x, 1)) >= 0
5519 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5520 && GET_CODE (XEXP (x, 0)) == ASHIFT
5521 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5522 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5523 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5529 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5530 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5531 == CODE_FOR_nothing)))
5532 op_mode = GET_MODE (x);
5534 /* Handle these similarly to the way we handle most binary operations. */
5535 x = gen_unary (code, op_mode,
5536 gen_lowpart_for_combine (op_mode,
5537 force_to_mode (XEXP (x, 0), mode,
5542 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5543 written in a narrower mode. We play it safe and do not do so. */
5546 gen_lowpart_for_combine (GET_MODE (x),
5547 force_to_mode (XEXP (x, 1), mode,
5550 gen_lowpart_for_combine (GET_MODE (x),
5551 force_to_mode (XEXP (x, 2), mode,
5556 /* Ensure we return a value of the proper mode. */
5557 return gen_lowpart_for_combine (mode, x);
5560 /* Return the value of expression X given the fact that condition COND
5561 is known to be true when applied to REG as its first operand and VAL
5562 as its second. X is known to not be shared and so can be modified in
5565 We only handle the simplest cases, and specifically those cases that
5566 arise with IF_THEN_ELSE expressions. */
5569 known_cond (x, cond, reg, val)
5574 enum rtx_code code = GET_CODE (x);
5579 if (side_effects_p (x))
5582 if (cond == EQ && rtx_equal_p (x, reg))
5585 /* If X is (abs REG) and we know something about REG's relationship
5586 with zero, we may be able to simplify this. */
5588 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5591 case GE: case GT: case EQ:
5594 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5597 /* The only other cases we handle are MIN, MAX, and comparisons if the
5598 operands are the same as REG and VAL. */
5600 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5602 if (rtx_equal_p (XEXP (x, 0), val))
5603 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5605 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5607 if (GET_RTX_CLASS (code) == '<')
5608 return (comparison_dominates_p (cond, code) ? const_true_rtx
5609 : (comparison_dominates_p (cond,
5610 reverse_condition (code))
5613 else if (code == SMAX || code == SMIN
5614 || code == UMIN || code == UMAX)
5616 int unsignedp = (code == UMIN || code == UMAX);
5618 if (code == SMAX || code == UMAX)
5619 cond = reverse_condition (cond);
5624 return unsignedp ? x : XEXP (x, 1);
5626 return unsignedp ? x : XEXP (x, 0);
5628 return unsignedp ? XEXP (x, 1) : x;
5630 return unsignedp ? XEXP (x, 0) : x;
5636 fmt = GET_RTX_FORMAT (code);
5637 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5640 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5641 else if (fmt[i] == 'E')
5642 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5643 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5650 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5651 Return that assignment if so.
5653 We only handle the most common cases. */
5656 make_field_assignment (x)
5659 rtx dest = SET_DEST (x);
5660 rtx src = SET_SRC (x);
5666 enum machine_mode mode;
5668 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5669 a clear of a one-bit field. We will have changed it to
5670 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5673 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5674 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5675 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5676 && (rtx_equal_p (dest, XEXP (src, 1))
5677 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5678 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5680 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5682 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5685 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5686 && subreg_lowpart_p (XEXP (src, 0))
5687 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5688 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5689 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5690 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5691 && (rtx_equal_p (dest, XEXP (src, 1))
5692 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5693 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5695 assign = make_extraction (VOIDmode, dest, 0,
5696 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5698 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5701 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5703 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5704 && XEXP (XEXP (src, 0), 0) == const1_rtx
5705 && (rtx_equal_p (dest, XEXP (src, 1))
5706 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5707 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5709 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5711 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5714 /* The other case we handle is assignments into a constant-position
5715 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5716 a mask that has all one bits except for a group of zero bits and
5717 OTHER is known to have zeros where C1 has ones, this is such an
5718 assignment. Compute the position and length from C1. Shift OTHER
5719 to the appropriate position, force it to the required mode, and
5720 make the extraction. Check for the AND in both operands. */
5722 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5723 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5724 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5725 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5726 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5727 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5728 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5729 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5730 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5731 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5732 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5734 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5738 pos = get_pos_from_mask (~c1, &len);
5739 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5740 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5741 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
5744 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5746 /* The mode to use for the source is the mode of the assignment, or of
5747 what is inside a possible STRICT_LOW_PART. */
5748 mode = (GET_CODE (assign) == STRICT_LOW_PART
5749 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5751 /* Shift OTHER right POS places and make it the source, restricting it
5752 to the proper length and mode. */
5754 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5755 GET_MODE (src), other, pos),
5758 return gen_rtx_combine (SET, VOIDmode, assign, src);
5761 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5765 apply_distributive_law (x)
5768 enum rtx_code code = GET_CODE (x);
5769 rtx lhs, rhs, other;
5771 enum rtx_code inner_code;
5773 /* Distributivity is not true for floating point.
5774 It can change the value. So don't do it.
5775 -- rms and moshier@world.std.com. */
5776 if (FLOAT_MODE_P (GET_MODE (x)))
5779 /* The outer operation can only be one of the following: */
5780 if (code != IOR && code != AND && code != XOR
5781 && code != PLUS && code != MINUS)
5784 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5786 /* If either operand is a primitive we can't do anything, so get out fast. */
5787 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5788 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5791 lhs = expand_compound_operation (lhs);
5792 rhs = expand_compound_operation (rhs);
5793 inner_code = GET_CODE (lhs);
5794 if (inner_code != GET_CODE (rhs))
5797 /* See if the inner and outer operations distribute. */
5804 /* These all distribute except over PLUS. */
5805 if (code == PLUS || code == MINUS)
5810 if (code != PLUS && code != MINUS)
5816 /* These are also multiplies, so they distribute over everything. */
5820 /* Non-paradoxical SUBREGs distributes over all operations, provided
5821 the inner modes and word numbers are the same, this is an extraction
5822 of a low-order part, we don't convert an fp operation to int or
5823 vice versa, and we would not be converting a single-word
5824 operation into a multi-word operation. The latter test is not
5825 required, but it prevents generating unneeded multi-word operations.
5826 Some of the previous tests are redundant given the latter test, but
5827 are retained because they are required for correctness.
5829 We produce the result slightly differently in this case. */
5831 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5832 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5833 || ! subreg_lowpart_p (lhs)
5834 || (GET_MODE_CLASS (GET_MODE (lhs))
5835 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5836 || (GET_MODE_SIZE (GET_MODE (lhs))
5837 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5838 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5841 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5842 SUBREG_REG (lhs), SUBREG_REG (rhs));
5843 return gen_lowpart_for_combine (GET_MODE (x), tem);
5849 /* Set LHS and RHS to the inner operands (A and B in the example
5850 above) and set OTHER to the common operand (C in the example).
5851 These is only one way to do this unless the inner operation is
5853 if (GET_RTX_CLASS (inner_code) == 'c'
5854 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5855 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5856 else if (GET_RTX_CLASS (inner_code) == 'c'
5857 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5858 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5859 else if (GET_RTX_CLASS (inner_code) == 'c'
5860 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5861 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5862 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5863 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5867 /* Form the new inner operation, seeing if it simplifies first. */
5868 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5870 /* There is one exception to the general way of distributing:
5871 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5872 if (code == XOR && inner_code == IOR)
5875 other = gen_unary (NOT, GET_MODE (x), other);
5878 /* We may be able to continuing distributing the result, so call
5879 ourselves recursively on the inner operation before forming the
5880 outer operation, which we return. */
5881 return gen_binary (inner_code, GET_MODE (x),
5882 apply_distributive_law (tem), other);
5885 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5888 Return an equivalent form, if different from X. Otherwise, return X. If
5889 X is zero, we are to always construct the equivalent form. */
5892 simplify_and_const_int (x, mode, varop, constop)
5894 enum machine_mode mode;
5896 unsigned HOST_WIDE_INT constop;
5898 register enum machine_mode tmode;
5900 unsigned HOST_WIDE_INT nonzero;
5902 /* There is a large class of optimizations based on the principle that
5903 some operations produce results where certain bits are known to be zero,
5904 and hence are not significant to the AND. For example, if we have just
5905 done a left shift of one bit, the low-order bit is known to be zero and
5906 hence an AND with a mask of ~1 would not do anything.
5908 At the end of the following loop, we set:
5910 VAROP to be the item to be AND'ed with;
5911 CONSTOP to the constant value to AND it with. */
5915 /* If we ever encounter a mode wider than the host machine's widest
5916 integer size, we can't compute the masks accurately, so give up. */
5917 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5920 /* Unless one of the cases below does a `continue',
5921 a `break' will be executed to exit the loop. */
5923 switch (GET_CODE (varop))
5926 /* If VAROP is a (clobber (const_int)), return it since we know
5927 we are generating something that won't match. */
5930 #if ! BITS_BIG_ENDIAN
5932 /* VAROP is a (use (mem ..)) that was made from a bit-field
5933 extraction that spanned the boundary of the MEM. If we are
5934 now masking so it is within that boundary, we don't need the
5936 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5938 varop = XEXP (varop, 0);
5945 if (subreg_lowpart_p (varop)
5946 /* We can ignore the effect this SUBREG if it narrows the mode
5947 or, on machines where byte operations extend, if the
5948 constant masks to zero all the bits the mode doesn't have. */
5949 && ((GET_MODE_SIZE (GET_MODE (varop))
5950 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5951 #ifdef BYTE_LOADS_EXTEND
5953 & GET_MODE_MASK (GET_MODE (varop))
5954 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5958 varop = SUBREG_REG (varop);
5967 /* Try to expand these into a series of shifts and then work
5968 with that result. If we can't, for example, if the extract
5969 isn't at a fixed position, give up. */
5970 temp = expand_compound_operation (varop);
5979 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5981 constop &= INTVAL (XEXP (varop, 1));
5982 varop = XEXP (varop, 0);
5989 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5990 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5991 operation which may be a bitfield extraction. Ensure
5992 that the constant we form is not wider than the mode of
5995 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5996 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5997 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5998 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5999 && GET_CODE (XEXP (varop, 1)) == CONST_INT
6000 && ((INTVAL (XEXP (XEXP (varop, 0), 1))
6001 + floor_log2 (INTVAL (XEXP (varop, 1))))
6002 < GET_MODE_BITSIZE (GET_MODE (varop)))
6003 && (INTVAL (XEXP (varop, 1))
6004 & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0))
6006 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
6007 << INTVAL (XEXP (XEXP (varop, 0), 1)));
6008 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
6009 XEXP (XEXP (varop, 0), 0), temp);
6010 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6011 temp, XEXP (varop, 1));
6015 /* Apply the AND to both branches of the IOR or XOR, then try to
6016 apply the distributive law. This may eliminate operations
6017 if either branch can be simplified because of the AND.
6018 It may also make some cases more complex, but those cases
6019 probably won't match a pattern either with or without this. */
6021 gen_lowpart_for_combine
6022 (mode, apply_distributive_law
6024 (GET_CODE (varop), GET_MODE (varop),
6025 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6026 XEXP (varop, 0), constop),
6027 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6028 XEXP (varop, 1), constop))));
6031 /* (and (not FOO)) is (and (xor FOO CONST)), so if FOO is an
6032 LSHIFTRT, we can do the same as above. Ensure that the constant
6033 we form is not wider than the mode of VAROP. */
6035 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
6036 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6037 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
6038 && (INTVAL (XEXP (XEXP (varop, 0), 1)) + floor_log2 (constop)
6039 < GET_MODE_BITSIZE (GET_MODE (varop)))
6040 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6042 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
6043 temp = gen_binary (XOR, GET_MODE (varop),
6044 XEXP (XEXP (varop, 0), 0), temp);
6045 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6046 temp, XEXP (XEXP (varop, 0), 1));
6052 /* If we are just looking for the sign bit, we don't need this
6053 shift at all, even if it has a variable count. */
6054 if (constop == ((HOST_WIDE_INT) 1
6055 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
6057 varop = XEXP (varop, 0);
6061 /* If this is a shift by a constant, get a mask that contains
6062 those bits that are not copies of the sign bit. We then have
6063 two cases: If CONSTOP only includes those bits, this can be
6064 a logical shift, which may allow simplifications. If CONSTOP
6065 is a single-bit field not within those bits, we are requesting
6066 a copy of the sign bit and hence can shift the sign bit to
6067 the appropriate location. */
6068 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6069 && INTVAL (XEXP (varop, 1)) >= 0
6070 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
6074 nonzero = GET_MODE_MASK (GET_MODE (varop));
6075 nonzero >>= INTVAL (XEXP (varop, 1));
6077 if ((constop & ~ nonzero) == 0
6078 || (i = exact_log2 (constop)) >= 0)
6080 varop = simplify_shift_const
6081 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6082 i < 0 ? INTVAL (XEXP (varop, 1))
6083 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
6084 if (GET_CODE (varop) != ASHIFTRT)
6089 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
6090 even if the shift count isn't a constant. */
6092 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6093 XEXP (varop, 0), XEXP (varop, 1));
6097 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6098 shift and AND produces only copies of the sign bit (C2 is one less
6099 than a power of two), we can do this with just a shift. */
6101 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6102 && ((INTVAL (XEXP (varop, 1))
6103 + num_sign_bit_copies (XEXP (varop, 0),
6104 GET_MODE (XEXP (varop, 0))))
6105 >= GET_MODE_BITSIZE (GET_MODE (varop)))
6106 && exact_log2 (constop + 1) >= 0)
6108 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6109 GEN_INT (GET_MODE_BITSIZE (GET_MODE (varop))
6110 - exact_log2 (constop + 1)));
6114 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
6115 included in STORE_FLAG_VALUE and FOO has no bits that might be
6116 nonzero not in CONST. */
6117 if ((constop & ~ STORE_FLAG_VALUE) == 0
6118 && XEXP (varop, 0) == const0_rtx
6119 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6121 varop = XEXP (varop, 0);
6127 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6128 low-order bits (as in an alignment operation) and FOO is already
6129 aligned to that boundary, we can convert remove this AND
6130 and possibly the PLUS if it is now adding zero. */
6131 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6132 && exact_log2 (-constop) >= 0
6133 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6135 varop = plus_constant (XEXP (varop, 0),
6136 INTVAL (XEXP (varop, 1)) & constop);
6141 /* ... fall through ... */
6144 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
6145 less than powers of two and M2 is narrower than M1, we can
6146 eliminate the inner AND. This occurs when incrementing
6149 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
6150 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
6151 SUBST (XEXP (varop, 0),
6152 expand_compound_operation (XEXP (varop, 0)));
6154 if (GET_CODE (XEXP (varop, 0)) == AND
6155 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6156 && exact_log2 (constop + 1) >= 0
6157 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
6158 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
6159 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
6166 /* If we have reached a constant, this whole thing is constant. */
6167 if (GET_CODE (varop) == CONST_INT)
6168 return GEN_INT (constop & INTVAL (varop));
6170 /* See what bits may be nonzero in VAROP. Unlike the general case of
6171 a call to nonzero_bits, here we don't care about bits outside
6174 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6176 /* Turn off all bits in the constant that are known to already be zero.
6177 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6178 which is tested below. */
6182 /* If we don't have any bits left, return zero. */
6186 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6187 if we already had one (just check for the simplest cases). */
6188 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6189 && GET_MODE (XEXP (x, 0)) == mode
6190 && SUBREG_REG (XEXP (x, 0)) == varop)
6191 varop = XEXP (x, 0);
6193 varop = gen_lowpart_for_combine (mode, varop);
6195 /* If we can't make the SUBREG, try to return what we were given. */
6196 if (GET_CODE (varop) == CLOBBER)
6197 return x ? x : varop;
6199 /* If we are only masking insignificant bits, return VAROP. */
6200 if (constop == nonzero)
6203 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6204 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6205 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
6209 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6210 || INTVAL (XEXP (x, 1)) != constop)
6211 SUBST (XEXP (x, 1), GEN_INT (constop));
6213 SUBST (XEXP (x, 0), varop);
6219 /* Given an expression, X, compute which bits in X can be non-zero.
6220 We don't care about bits outside of those defined in MODE.
6222 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6223 a shift, AND, or zero_extract, we can do better. */
6225 static unsigned HOST_WIDE_INT
6226 nonzero_bits (x, mode)
6228 enum machine_mode mode;
6230 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6231 unsigned HOST_WIDE_INT inner_nz;
6233 int mode_width = GET_MODE_BITSIZE (mode);
6236 /* If X is wider than MODE, use its mode instead. */
6237 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6239 mode = GET_MODE (x);
6240 nonzero = GET_MODE_MASK (mode);
6241 mode_width = GET_MODE_BITSIZE (mode);
6244 if (mode_width > HOST_BITS_PER_WIDE_INT)
6245 /* Our only callers in this case look for single bit values. So
6246 just return the mode mask. Those tests will then be false. */
6249 code = GET_CODE (x);
6253 #ifdef STACK_BOUNDARY
6254 /* If this is the stack pointer, we may know something about its
6255 alignment. If PUSH_ROUNDING is defined, it is possible for the
6256 stack to be momentarily aligned only to that amount, so we pick
6257 the least alignment. */
6259 if (x == stack_pointer_rtx)
6261 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6263 #ifdef PUSH_ROUNDING
6264 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6267 return nonzero & ~ (sp_alignment - 1);
6271 /* If X is a register whose nonzero bits value is current, use it.
6272 Otherwise, if X is a register whose value we can find, use that
6273 value. Otherwise, use the previously-computed global nonzero bits
6274 for this register. */
6276 if (reg_last_set_value[REGNO (x)] != 0
6277 && reg_last_set_mode[REGNO (x)] == mode
6278 && (reg_n_sets[REGNO (x)] == 1
6279 || reg_last_set_label[REGNO (x)] == label_tick)
6280 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6281 return reg_last_set_nonzero_bits[REGNO (x)];
6283 tem = get_last_value (x);
6287 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6288 /* If X is narrower than MODE and TEM is a non-negative
6289 constant that would appear negative in the mode of X,
6290 sign-extend it for use in reg_nonzero_bits because some
6291 machines (maybe most) will actually do the sign-extension
6292 and this is the conservative approach.
6294 ??? For 2.5, try to tighten up the MD files in this regard
6295 instead of this kludge. */
6297 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
6298 && GET_CODE (tem) == CONST_INT
6300 && 0 != (INTVAL (tem)
6301 & ((HOST_WIDE_INT) 1
6302 << GET_MODE_BITSIZE (GET_MODE (x)))))
6303 tem = GEN_INT (INTVAL (tem)
6304 | ((HOST_WIDE_INT) (-1)
6305 << GET_MODE_BITSIZE (GET_MODE (x))));
6307 return nonzero_bits (tem, mode);
6309 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6310 return reg_nonzero_bits[REGNO (x)] & nonzero;
6315 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
6316 /* If X is negative in MODE, sign-extend the value. */
6319 & ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (GET_MODE (x)))))
6321 | ((HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (GET_MODE (x))));
6326 #ifdef BYTE_LOADS_ZERO_EXTEND
6328 /* In many, if not most, RISC machines, reading a byte from memory
6329 zeros the rest of the register. Noticing that fact saves a lot
6330 of extra zero-extends. */
6331 nonzero &= GET_MODE_MASK (GET_MODE (x));
6335 #if STORE_FLAG_VALUE == 1
6342 if (GET_MODE_CLASS (mode) == MODE_INT)
6345 /* A comparison operation only sets the bits given by its mode. The
6346 rest are set undefined. */
6347 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6348 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6353 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6354 == GET_MODE_BITSIZE (GET_MODE (x)))
6357 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6358 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6362 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6363 == GET_MODE_BITSIZE (GET_MODE (x)))
6368 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6372 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6373 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6374 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6378 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6379 Otherwise, show all the bits in the outer mode but not the inner
6381 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6382 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6384 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6387 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6388 inner_nz |= (GET_MODE_MASK (mode)
6389 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6392 nonzero &= inner_nz;
6396 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6397 & nonzero_bits (XEXP (x, 1), mode));
6401 case UMIN: case UMAX: case SMIN: case SMAX:
6402 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6403 | nonzero_bits (XEXP (x, 1), mode));
6406 case PLUS: case MINUS:
6408 case DIV: case UDIV:
6409 case MOD: case UMOD:
6410 /* We can apply the rules of arithmetic to compute the number of
6411 high- and low-order zero bits of these operations. We start by
6412 computing the width (position of the highest-order non-zero bit)
6413 and the number of low-order zero bits for each value. */
6415 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6416 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6417 int width0 = floor_log2 (nz0) + 1;
6418 int width1 = floor_log2 (nz1) + 1;
6419 int low0 = floor_log2 (nz0 & -nz0);
6420 int low1 = floor_log2 (nz1 & -nz1);
6421 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6422 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6423 int result_width = mode_width;
6429 result_width = MAX (width0, width1) + 1;
6430 result_low = MIN (low0, low1);
6433 result_low = MIN (low0, low1);
6436 result_width = width0 + width1;
6437 result_low = low0 + low1;
6440 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6441 result_width = width0;
6444 result_width = width0;
6447 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6448 result_width = MIN (width0, width1);
6449 result_low = MIN (low0, low1);
6452 result_width = MIN (width0, width1);
6453 result_low = MIN (low0, low1);
6457 if (result_width < mode_width)
6458 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6461 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6466 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6467 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6468 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6472 /* If this is a SUBREG formed for a promoted variable that has
6473 been zero-extended, we know that at least the high-order bits
6474 are zero, though others might be too. */
6476 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6477 nonzero = (GET_MODE_MASK (GET_MODE (x))
6478 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6480 /* If the inner mode is a single word for both the host and target
6481 machines, we can compute this from which bits of the inner
6482 object might be nonzero. */
6483 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6484 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6485 <= HOST_BITS_PER_WIDE_INT))
6487 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6488 #ifndef BYTE_LOADS_EXTEND
6489 /* On many CISC machines, accessing an object in a wider mode
6490 causes the high-order bits to become undefined. So they are
6491 not known to be zero. */
6492 if (GET_MODE_SIZE (GET_MODE (x))
6493 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6494 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6495 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6505 /* The nonzero bits are in two classes: any bits within MODE
6506 that aren't in GET_MODE (x) are always significant. The rest of the
6507 nonzero bits are those that are significant in the operand of
6508 the shift when shifted the appropriate number of bits. This
6509 shows that high-order bits are cleared by the right shift and
6510 low-order bits by left shifts. */
6511 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6512 && INTVAL (XEXP (x, 1)) >= 0
6513 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6515 enum machine_mode inner_mode = GET_MODE (x);
6516 int width = GET_MODE_BITSIZE (inner_mode);
6517 int count = INTVAL (XEXP (x, 1));
6518 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6519 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6520 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6521 unsigned HOST_WIDE_INT outer = 0;
6523 if (mode_width > width)
6524 outer = (op_nonzero & nonzero & ~ mode_mask);
6526 if (code == LSHIFTRT)
6528 else if (code == ASHIFTRT)
6532 /* If the sign bit may have been nonzero before the shift, we
6533 need to mark all the places it could have been copied to
6534 by the shift as possibly nonzero. */
6535 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6536 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6538 else if (code == LSHIFT || code == ASHIFT)
6541 inner = ((inner << (count % width)
6542 | (inner >> (width - (count % width)))) & mode_mask);
6544 nonzero &= (outer | inner);
6549 /* This is at most the number of bits in the mode. */
6550 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6554 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6555 | nonzero_bits (XEXP (x, 2), mode));
6562 /* Return the number of bits at the high-order end of X that are known to
6563 be equal to the sign bit. This number will always be between 1 and
6564 the number of bits in the mode of X. MODE is the mode to be used
6565 if X is VOIDmode. */
6568 num_sign_bit_copies (x, mode)
6570 enum machine_mode mode;
6572 enum rtx_code code = GET_CODE (x);
6574 int num0, num1, result;
6575 unsigned HOST_WIDE_INT nonzero;
6578 /* If we weren't given a mode, use the mode of X. If the mode is still
6579 VOIDmode, we don't know anything. */
6581 if (mode == VOIDmode)
6582 mode = GET_MODE (x);
6584 if (mode == VOIDmode)
6587 bitwidth = GET_MODE_BITSIZE (mode);
6593 if (reg_last_set_value[REGNO (x)] != 0
6594 && reg_last_set_mode[REGNO (x)] == mode
6595 && (reg_n_sets[REGNO (x)] == 1
6596 || reg_last_set_label[REGNO (x)] == label_tick)
6597 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6598 return reg_last_set_sign_bit_copies[REGNO (x)];
6600 tem = get_last_value (x);
6602 return num_sign_bit_copies (tem, mode);
6604 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6605 return reg_sign_bit_copies[REGNO (x)];
6608 #ifdef BYTE_LOADS_SIGN_EXTEND
6610 /* Some RISC machines sign-extend all loads of smaller than a word. */
6611 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6615 /* If the constant is negative, take its 1's complement and remask.
6616 Then see how many zero bits we have. */
6617 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6618 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6619 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6620 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6622 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6625 /* If this is a SUBREG for a promoted object that is sign-extended
6626 and we are looking at it in a wider mode, we know that at least the
6627 high-order bits are known to be sign bit copies. */
6629 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6630 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
6631 num_sign_bit_copies (SUBREG_REG (x), mode));
6633 /* For a smaller object, just ignore the high bits. */
6634 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6636 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6637 return MAX (1, (num0
6638 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6642 #ifdef BYTE_LOADS_EXTEND
6643 /* For paradoxical SUBREGs, just look inside since, on machines with
6644 one of these defined, we assume that operations are actually
6645 performed on the full register. Note that we are passing MODE
6646 to the recursive call, so the number of sign bit copies will
6647 remain relative to that mode, not the inner mode. */
6649 if (GET_MODE_SIZE (GET_MODE (x))
6650 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6651 return num_sign_bit_copies (SUBREG_REG (x), mode);
6657 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6658 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6662 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6663 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6666 /* For a smaller object, just ignore the high bits. */
6667 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6668 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6672 return num_sign_bit_copies (XEXP (x, 0), mode);
6674 case ROTATE: case ROTATERT:
6675 /* If we are rotating left by a number of bits less than the number
6676 of sign bit copies, we can just subtract that amount from the
6678 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6679 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6681 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6682 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6683 : bitwidth - INTVAL (XEXP (x, 1))));
6688 /* In general, this subtracts one sign bit copy. But if the value
6689 is known to be positive, the number of sign bit copies is the
6690 same as that of the input. Finally, if the input has just one bit
6691 that might be nonzero, all the bits are copies of the sign bit. */
6692 nonzero = nonzero_bits (XEXP (x, 0), mode);
6696 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6698 && bitwidth <= HOST_BITS_PER_WIDE_INT
6699 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6704 case IOR: case AND: case XOR:
6705 case SMIN: case SMAX: case UMIN: case UMAX:
6706 /* Logical operations will preserve the number of sign-bit copies.
6707 MIN and MAX operations always return one of the operands. */
6708 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6709 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6710 return MIN (num0, num1);
6712 case PLUS: case MINUS:
6713 /* For addition and subtraction, we can have a 1-bit carry. However,
6714 if we are subtracting 1 from a positive number, there will not
6715 be such a carry. Furthermore, if the positive number is known to
6716 be 0 or 1, we know the result is either -1 or 0. */
6718 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6719 && bitwidth <= HOST_BITS_PER_WIDE_INT)
6721 nonzero = nonzero_bits (XEXP (x, 0), mode);
6722 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6723 return (nonzero == 1 || nonzero == 0 ? bitwidth
6724 : bitwidth - floor_log2 (nonzero) - 1);
6727 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6728 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6729 return MAX (1, MIN (num0, num1) - 1);
6732 /* The number of bits of the product is the sum of the number of
6733 bits of both terms. However, unless one of the terms if known
6734 to be positive, we must allow for an additional bit since negating
6735 a negative number can remove one sign bit copy. */
6737 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6738 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6740 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6742 && bitwidth <= HOST_BITS_PER_WIDE_INT
6743 && ((nonzero_bits (XEXP (x, 0), mode)
6744 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6745 && (nonzero_bits (XEXP (x, 1), mode)
6746 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6749 return MAX (1, result);
6752 /* The result must be <= the first operand. */
6753 return num_sign_bit_copies (XEXP (x, 0), mode);
6756 /* The result must be <= the scond operand. */
6757 return num_sign_bit_copies (XEXP (x, 1), mode);
6760 /* Similar to unsigned division, except that we have to worry about
6761 the case where the divisor is negative, in which case we have
6763 result = num_sign_bit_copies (XEXP (x, 0), mode);
6765 && bitwidth <= HOST_BITS_PER_WIDE_INT
6766 && (nonzero_bits (XEXP (x, 1), mode)
6767 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6773 result = num_sign_bit_copies (XEXP (x, 1), mode);
6775 && bitwidth <= HOST_BITS_PER_WIDE_INT
6776 && (nonzero_bits (XEXP (x, 1), mode)
6777 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6783 /* Shifts by a constant add to the number of bits equal to the
6785 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6786 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6787 && INTVAL (XEXP (x, 1)) > 0)
6788 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6794 /* Left shifts destroy copies. */
6795 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6796 || INTVAL (XEXP (x, 1)) < 0
6797 || INTVAL (XEXP (x, 1)) >= bitwidth)
6800 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6801 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6804 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6805 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6806 return MIN (num0, num1);
6808 #if STORE_FLAG_VALUE == -1
6809 case EQ: case NE: case GE: case GT: case LE: case LT:
6810 case GEU: case GTU: case LEU: case LTU:
6815 /* If we haven't been able to figure it out by one of the above rules,
6816 see if some of the high-order bits are known to be zero. If so,
6817 count those bits and return one less than that amount. If we can't
6818 safely compute the mask for this mode, always return BITWIDTH. */
6820 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6823 nonzero = nonzero_bits (x, mode);
6824 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
6825 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
6828 /* Return the number of "extended" bits there are in X, when interpreted
6829 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6830 unsigned quantities, this is the number of high-order zero bits.
6831 For signed quantities, this is the number of copies of the sign bit
6832 minus 1. In both case, this function returns the number of "spare"
6833 bits. For example, if two quantities for which this function returns
6834 at least 1 are added, the addition is known not to overflow.
6836 This function will always return 0 unless called during combine, which
6837 implies that it must be called from a define_split. */
6840 extended_count (x, mode, unsignedp)
6842 enum machine_mode mode;
6845 if (nonzero_sign_valid == 0)
6849 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6850 && (GET_MODE_BITSIZE (mode) - 1
6851 - floor_log2 (nonzero_bits (x, mode))))
6852 : num_sign_bit_copies (x, mode) - 1);
6855 /* This function is called from `simplify_shift_const' to merge two
6856 outer operations. Specifically, we have already found that we need
6857 to perform operation *POP0 with constant *PCONST0 at the outermost
6858 position. We would now like to also perform OP1 with constant CONST1
6859 (with *POP0 being done last).
6861 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6862 the resulting operation. *PCOMP_P is set to 1 if we would need to
6863 complement the innermost operand, otherwise it is unchanged.
6865 MODE is the mode in which the operation will be done. No bits outside
6866 the width of this mode matter. It is assumed that the width of this mode
6867 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6869 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6870 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6871 result is simply *PCONST0.
6873 If the resulting operation cannot be expressed as one operation, we
6874 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6877 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6878 enum rtx_code *pop0;
6879 HOST_WIDE_INT *pconst0;
6881 HOST_WIDE_INT const1;
6882 enum machine_mode mode;
6885 enum rtx_code op0 = *pop0;
6886 HOST_WIDE_INT const0 = *pconst0;
6888 const0 &= GET_MODE_MASK (mode);
6889 const1 &= GET_MODE_MASK (mode);
6891 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6895 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6898 if (op1 == NIL || op0 == SET)
6901 else if (op0 == NIL)
6902 op0 = op1, const0 = const1;
6904 else if (op0 == op1)
6926 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6927 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6930 /* If the two constants aren't the same, we can't do anything. The
6931 remaining six cases can all be done. */
6932 else if (const0 != const1)
6940 /* (a & b) | b == b */
6942 else /* op1 == XOR */
6943 /* (a ^ b) | b == a | b */
6949 /* (a & b) ^ b == (~a) & b */
6950 op0 = AND, *pcomp_p = 1;
6951 else /* op1 == IOR */
6952 /* (a | b) ^ b == a & ~b */
6953 op0 = AND, *pconst0 = ~ const0;
6958 /* (a | b) & b == b */
6960 else /* op1 == XOR */
6961 /* (a ^ b) & b) == (~a) & b */
6966 /* Check for NO-OP cases. */
6967 const0 &= GET_MODE_MASK (mode);
6969 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6971 else if (const0 == 0 && op0 == AND)
6973 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6982 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6983 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6984 that we started with.
6986 The shift is normally computed in the widest mode we find in VAROP, as
6987 long as it isn't a different number of words than RESULT_MODE. Exceptions
6988 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6991 simplify_shift_const (x, code, result_mode, varop, count)
6994 enum machine_mode result_mode;
6998 enum rtx_code orig_code = code;
6999 int orig_count = count;
7000 enum machine_mode mode = result_mode;
7001 enum machine_mode shift_mode, tmode;
7003 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7004 /* We form (outer_op (code varop count) (outer_const)). */
7005 enum rtx_code outer_op = NIL;
7006 HOST_WIDE_INT outer_const;
7008 int complement_p = 0;
7011 /* If we were given an invalid count, don't do anything except exactly
7012 what was requested. */
7014 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7019 return gen_rtx (code, mode, varop, GEN_INT (count));
7022 /* Unless one of the branches of the `if' in this loop does a `continue',
7023 we will `break' the loop after the `if'. */
7027 /* If we have an operand of (clobber (const_int 0)), just return that
7029 if (GET_CODE (varop) == CLOBBER)
7032 /* If we discovered we had to complement VAROP, leave. Making a NOT
7033 here would cause an infinite loop. */
7037 /* Convert ROTATETRT to ROTATE. */
7038 if (code == ROTATERT)
7039 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7041 /* Canonicalize LSHIFT to ASHIFT. */
7045 /* We need to determine what mode we will do the shift in. If the
7046 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
7047 was originally done in. Otherwise, we can do it in MODE, the widest
7048 mode encountered. */
7049 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7051 /* Handle cases where the count is greater than the size of the mode
7052 minus 1. For ASHIFT, use the size minus one as the count (this can
7053 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7054 take the count modulo the size. For other shifts, the result is
7057 Since these shifts are being produced by the compiler by combining
7058 multiple operations, each of which are defined, we know what the
7059 result is supposed to be. */
7061 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7063 if (code == ASHIFTRT)
7064 count = GET_MODE_BITSIZE (shift_mode) - 1;
7065 else if (code == ROTATE || code == ROTATERT)
7066 count %= GET_MODE_BITSIZE (shift_mode);
7069 /* We can't simply return zero because there may be an
7077 /* Negative counts are invalid and should not have been made (a
7078 programmer-specified negative count should have been handled
7083 /* An arithmetic right shift of a quantity known to be -1 or 0
7085 if (code == ASHIFTRT
7086 && (num_sign_bit_copies (varop, shift_mode)
7087 == GET_MODE_BITSIZE (shift_mode)))
7093 /* If we are doing an arithmetic right shift and discarding all but
7094 the sign bit copies, this is equivalent to doing a shift by the
7095 bitsize minus one. Convert it into that shift because it will often
7096 allow other simplifications. */
7098 if (code == ASHIFTRT
7099 && (count + num_sign_bit_copies (varop, shift_mode)
7100 >= GET_MODE_BITSIZE (shift_mode)))
7101 count = GET_MODE_BITSIZE (shift_mode) - 1;
7103 /* We simplify the tests below and elsewhere by converting
7104 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7105 `make_compound_operation' will convert it to a ASHIFTRT for
7106 those machines (such as Vax) that don't have a LSHIFTRT. */
7107 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7109 && ((nonzero_bits (varop, shift_mode)
7110 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7114 switch (GET_CODE (varop))
7120 new = expand_compound_operation (varop);
7129 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7130 minus the width of a smaller mode, we can do this with a
7131 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7132 if ((code == ASHIFTRT || code == LSHIFTRT)
7133 && ! mode_dependent_address_p (XEXP (varop, 0))
7134 && ! MEM_VOLATILE_P (varop)
7135 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7136 MODE_INT, 1)) != BLKmode)
7138 #if BYTES_BIG_ENDIAN
7139 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7141 new = gen_rtx (MEM, tmode,
7142 plus_constant (XEXP (varop, 0),
7143 count / BITS_PER_UNIT));
7144 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7145 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7146 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7148 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7149 : ZERO_EXTEND, mode, new);
7156 /* Similar to the case above, except that we can only do this if
7157 the resulting mode is the same as that of the underlying
7158 MEM and adjust the address depending on the *bits* endianness
7159 because of the way that bit-field extract insns are defined. */
7160 if ((code == ASHIFTRT || code == LSHIFTRT)
7161 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7162 MODE_INT, 1)) != BLKmode
7163 && tmode == GET_MODE (XEXP (varop, 0)))
7166 new = XEXP (varop, 0);
7168 new = copy_rtx (XEXP (varop, 0));
7169 SUBST (XEXP (new, 0),
7170 plus_constant (XEXP (new, 0),
7171 count / BITS_PER_UNIT));
7174 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7175 : ZERO_EXTEND, mode, new);
7182 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7183 the same number of words as what we've seen so far. Then store
7184 the widest mode in MODE. */
7185 if (subreg_lowpart_p (varop)
7186 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7187 > GET_MODE_SIZE (GET_MODE (varop)))
7188 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7189 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7192 varop = SUBREG_REG (varop);
7193 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7194 mode = GET_MODE (varop);
7200 /* Some machines use MULT instead of ASHIFT because MULT
7201 is cheaper. But it is still better on those machines to
7202 merge two shifts into one. */
7203 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7204 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7206 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7207 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7213 /* Similar, for when divides are cheaper. */
7214 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7215 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7217 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7218 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7224 /* If we are extracting just the sign bit of an arithmetic right
7225 shift, that shift is not needed. */
7226 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7228 varop = XEXP (varop, 0);
7232 /* ... fall through ... */
7238 /* Here we have two nested shifts. The result is usually the
7239 AND of a new shift with a mask. We compute the result below. */
7240 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7241 && INTVAL (XEXP (varop, 1)) >= 0
7242 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
7243 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7244 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7246 enum rtx_code first_code = GET_CODE (varop);
7247 int first_count = INTVAL (XEXP (varop, 1));
7248 unsigned HOST_WIDE_INT mask;
7252 if (first_code == LSHIFT)
7253 first_code = ASHIFT;
7255 /* We have one common special case. We can't do any merging if
7256 the inner code is an ASHIFTRT of a smaller mode. However, if
7257 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7258 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7259 we can convert it to
7260 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7261 This simplifies certain SIGN_EXTEND operations. */
7262 if (code == ASHIFT && first_code == ASHIFTRT
7263 && (GET_MODE_BITSIZE (result_mode)
7264 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
7266 /* C3 has the low-order C1 bits zero. */
7268 mask = (GET_MODE_MASK (mode)
7269 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7271 varop = simplify_and_const_int (NULL_RTX, result_mode,
7272 XEXP (varop, 0), mask);
7273 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7275 count = first_count;
7280 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7281 than C1 high-order bits equal to the sign bit, we can convert
7282 this to either an ASHIFT or a ASHIFTRT depending on the
7285 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7287 if (code == ASHIFTRT && first_code == ASHIFT
7288 && GET_MODE (varop) == shift_mode
7289 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7292 count -= first_count;
7294 count = - count, code = ASHIFT;
7295 varop = XEXP (varop, 0);
7299 /* There are some cases we can't do. If CODE is ASHIFTRT,
7300 we can only do this if FIRST_CODE is also ASHIFTRT.
7302 We can't do the case when CODE is ROTATE and FIRST_CODE is
7305 If the mode of this shift is not the mode of the outer shift,
7306 we can't do this if either shift is ASHIFTRT or ROTATE.
7308 Finally, we can't do any of these if the mode is too wide
7309 unless the codes are the same.
7311 Handle the case where the shift codes are the same
7314 if (code == first_code)
7316 if (GET_MODE (varop) != result_mode
7317 && (code == ASHIFTRT || code == ROTATE))
7320 count += first_count;
7321 varop = XEXP (varop, 0);
7325 if (code == ASHIFTRT
7326 || (code == ROTATE && first_code == ASHIFTRT)
7327 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7328 || (GET_MODE (varop) != result_mode
7329 && (first_code == ASHIFTRT || first_code == ROTATE
7330 || code == ROTATE)))
7333 /* To compute the mask to apply after the shift, shift the
7334 nonzero bits of the inner shift the same way the
7335 outer shift will. */
7337 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7340 = simplify_binary_operation (code, result_mode, mask_rtx,
7343 /* Give up if we can't compute an outer operation to use. */
7345 || GET_CODE (mask_rtx) != CONST_INT
7346 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7348 result_mode, &complement_p))
7351 /* If the shifts are in the same direction, we add the
7352 counts. Otherwise, we subtract them. */
7353 if ((code == ASHIFTRT || code == LSHIFTRT)
7354 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7355 count += first_count;
7357 count -= first_count;
7359 /* If COUNT is positive, the new shift is usually CODE,
7360 except for the two exceptions below, in which case it is
7361 FIRST_CODE. If the count is negative, FIRST_CODE should
7364 && ((first_code == ROTATE && code == ASHIFT)
7365 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7368 code = first_code, count = - count;
7370 varop = XEXP (varop, 0);
7374 /* If we have (A << B << C) for any shift, we can convert this to
7375 (A << C << B). This wins if A is a constant. Only try this if
7376 B is not a constant. */
7378 else if (GET_CODE (varop) == code
7379 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7381 = simplify_binary_operation (code, mode,
7385 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7392 /* Make this fit the case below. */
7393 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7394 GEN_INT (GET_MODE_MASK (mode)));
7400 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7401 with C the size of VAROP - 1 and the shift is logical if
7402 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7403 we have an (le X 0) operation. If we have an arithmetic shift
7404 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7405 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7407 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7408 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7409 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7410 && (code == LSHIFTRT || code == ASHIFTRT)
7411 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7412 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7415 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7418 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7419 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7424 /* If we have (shift (logical)), move the logical to the outside
7425 to allow it to possibly combine with another logical and the
7426 shift to combine with another shift. This also canonicalizes to
7427 what a ZERO_EXTRACT looks like. Also, some machines have
7428 (and (shift)) insns. */
7430 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7431 && (new = simplify_binary_operation (code, result_mode,
7433 GEN_INT (count))) != 0
7434 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7435 INTVAL (new), result_mode, &complement_p))
7437 varop = XEXP (varop, 0);
7441 /* If we can't do that, try to simplify the shift in each arm of the
7442 logical expression, make a new logical expression, and apply
7443 the inverse distributive law. */
7445 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7446 XEXP (varop, 0), count);
7447 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7448 XEXP (varop, 1), count);
7450 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7451 varop = apply_distributive_law (varop);
7458 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7459 says that the sign bit can be tested, FOO has mode MODE, C is
7460 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7463 && XEXP (varop, 1) == const0_rtx
7464 && GET_MODE (XEXP (varop, 0)) == result_mode
7465 && count == GET_MODE_BITSIZE (result_mode) - 1
7466 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7467 && ((STORE_FLAG_VALUE
7468 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7469 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7470 && merge_outer_ops (&outer_op, &outer_const, XOR,
7471 (HOST_WIDE_INT) 1, result_mode,
7474 varop = XEXP (varop, 0);
7481 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7482 than the number of bits in the mode is equivalent to A. */
7483 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7484 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7486 varop = XEXP (varop, 0);
7491 /* NEG commutes with ASHIFT since it is multiplication. Move the
7492 NEG outside to allow shifts to combine. */
7494 && merge_outer_ops (&outer_op, &outer_const, NEG,
7495 (HOST_WIDE_INT) 0, result_mode,
7498 varop = XEXP (varop, 0);
7504 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7505 is one less than the number of bits in the mode is
7506 equivalent to (xor A 1). */
7507 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7508 && XEXP (varop, 1) == constm1_rtx
7509 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7510 && merge_outer_ops (&outer_op, &outer_const, XOR,
7511 (HOST_WIDE_INT) 1, result_mode,
7515 varop = XEXP (varop, 0);
7519 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7520 that might be nonzero in BAR are those being shifted out and those
7521 bits are known zero in FOO, we can replace the PLUS with FOO.
7522 Similarly in the other operand order. This code occurs when
7523 we are computing the size of a variable-size array. */
7525 if ((code == ASHIFTRT || code == LSHIFTRT)
7526 && count < HOST_BITS_PER_WIDE_INT
7527 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7528 && (nonzero_bits (XEXP (varop, 1), result_mode)
7529 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7531 varop = XEXP (varop, 0);
7534 else if ((code == ASHIFTRT || code == LSHIFTRT)
7535 && count < HOST_BITS_PER_WIDE_INT
7536 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7537 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7539 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7540 & nonzero_bits (XEXP (varop, 1),
7543 varop = XEXP (varop, 1);
7547 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7549 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7550 && (new = simplify_binary_operation (ASHIFT, result_mode,
7552 GEN_INT (count))) != 0
7553 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7554 INTVAL (new), result_mode, &complement_p))
7556 varop = XEXP (varop, 0);
7562 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7563 with C the size of VAROP - 1 and the shift is logical if
7564 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7565 we have a (gt X 0) operation. If the shift is arithmetic with
7566 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7567 we have a (neg (gt X 0)) operation. */
7569 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7570 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7571 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7572 && (code == LSHIFTRT || code == ASHIFTRT)
7573 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7574 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7575 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7578 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7581 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7582 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7592 /* We need to determine what mode to do the shift in. If the shift is
7593 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7594 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7595 The code we care about is that of the shift that will actually be done,
7596 not the shift that was originally requested. */
7597 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7599 /* We have now finished analyzing the shift. The result should be
7600 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7601 OUTER_OP is non-NIL, it is an operation that needs to be applied
7602 to the result of the shift. OUTER_CONST is the relevant constant,
7603 but we must turn off all bits turned off in the shift.
7605 If we were passed a value for X, see if we can use any pieces of
7606 it. If not, make new rtx. */
7608 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7609 && GET_CODE (XEXP (x, 1)) == CONST_INT
7610 && INTVAL (XEXP (x, 1)) == count)
7611 const_rtx = XEXP (x, 1);
7613 const_rtx = GEN_INT (count);
7615 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7616 && GET_MODE (XEXP (x, 0)) == shift_mode
7617 && SUBREG_REG (XEXP (x, 0)) == varop)
7618 varop = XEXP (x, 0);
7619 else if (GET_MODE (varop) != shift_mode)
7620 varop = gen_lowpart_for_combine (shift_mode, varop);
7622 /* If we can't make the SUBREG, try to return what we were given. */
7623 if (GET_CODE (varop) == CLOBBER)
7624 return x ? x : varop;
7626 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7631 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7632 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7634 SUBST (XEXP (x, 0), varop);
7635 SUBST (XEXP (x, 1), const_rtx);
7638 /* If we have an outer operation and we just made a shift, it is
7639 possible that we could have simplified the shift were it not
7640 for the outer operation. So try to do the simplification
7643 if (outer_op != NIL && GET_CODE (x) == code
7644 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7645 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
7646 INTVAL (XEXP (x, 1)));
7648 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7649 turn off all the bits that the shift would have turned off. */
7650 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7651 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7652 GET_MODE_MASK (result_mode) >> orig_count);
7654 /* Do the remainder of the processing in RESULT_MODE. */
7655 x = gen_lowpart_for_combine (result_mode, x);
7657 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7660 x = gen_unary (NOT, result_mode, x);
7662 if (outer_op != NIL)
7664 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7665 outer_const &= GET_MODE_MASK (result_mode);
7667 if (outer_op == AND)
7668 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7669 else if (outer_op == SET)
7670 /* This means that we have determined that the result is
7671 equivalent to a constant. This should be rare. */
7672 x = GEN_INT (outer_const);
7673 else if (GET_RTX_CLASS (outer_op) == '1')
7674 x = gen_unary (outer_op, result_mode, x);
7676 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7682 /* Like recog, but we receive the address of a pointer to a new pattern.
7683 We try to match the rtx that the pointer points to.
7684 If that fails, we may try to modify or replace the pattern,
7685 storing the replacement into the same pointer object.
7687 Modifications include deletion or addition of CLOBBERs.
7689 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7690 the CLOBBERs are placed.
7692 The value is the final insn code from the pattern ultimately matched,
7696 recog_for_combine (pnewpat, insn, pnotes)
7701 register rtx pat = *pnewpat;
7702 int insn_code_number;
7703 int num_clobbers_to_add = 0;
7707 /* Is the result of combination a valid instruction? */
7708 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7710 /* If it isn't, there is the possibility that we previously had an insn
7711 that clobbered some register as a side effect, but the combined
7712 insn doesn't need to do that. So try once more without the clobbers
7713 unless this represents an ASM insn. */
7715 if (insn_code_number < 0 && ! check_asm_operands (pat)
7716 && GET_CODE (pat) == PARALLEL)
7720 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7721 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7724 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7728 SUBST_INT (XVECLEN (pat, 0), pos);
7731 pat = XVECEXP (pat, 0, 0);
7733 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7736 /* If we had any clobbers to add, make a new pattern than contains
7737 them. Then check to make sure that all of them are dead. */
7738 if (num_clobbers_to_add)
7740 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7741 gen_rtvec (GET_CODE (pat) == PARALLEL
7742 ? XVECLEN (pat, 0) + num_clobbers_to_add
7743 : num_clobbers_to_add + 1));
7745 if (GET_CODE (pat) == PARALLEL)
7746 for (i = 0; i < XVECLEN (pat, 0); i++)
7747 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7749 XVECEXP (newpat, 0, 0) = pat;
7751 add_clobbers (newpat, insn_code_number);
7753 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7754 i < XVECLEN (newpat, 0); i++)
7756 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7757 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7759 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7760 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7768 return insn_code_number;
7771 /* Like gen_lowpart but for use by combine. In combine it is not possible
7772 to create any new pseudoregs. However, it is safe to create
7773 invalid memory addresses, because combine will try to recognize
7774 them and all they will do is make the combine attempt fail.
7776 If for some reason this cannot do its job, an rtx
7777 (clobber (const_int 0)) is returned.
7778 An insn containing that will not be recognized. */
7783 gen_lowpart_for_combine (mode, x)
7784 enum machine_mode mode;
7789 if (GET_MODE (x) == mode)
7792 /* We can only support MODE being wider than a word if X is a
7793 constant integer or has a mode the same size. */
7795 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7796 && ! ((GET_MODE (x) == VOIDmode
7797 && (GET_CODE (x) == CONST_INT
7798 || GET_CODE (x) == CONST_DOUBLE))
7799 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7800 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7802 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7803 won't know what to do. So we will strip off the SUBREG here and
7804 process normally. */
7805 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7808 if (GET_MODE (x) == mode)
7812 result = gen_lowpart_common (mode, x);
7816 if (GET_CODE (x) == MEM)
7818 register int offset = 0;
7821 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7823 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7824 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7826 /* If we want to refer to something bigger than the original memref,
7827 generate a perverse subreg instead. That will force a reload
7828 of the original memref X. */
7829 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7830 return gen_rtx (SUBREG, mode, x, 0);
7832 #if WORDS_BIG_ENDIAN
7833 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7834 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7836 #if BYTES_BIG_ENDIAN
7837 /* Adjust the address so that the address-after-the-data
7839 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7840 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7842 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7843 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7844 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7845 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7849 /* If X is a comparison operator, rewrite it in a new mode. This
7850 probably won't match, but may allow further simplifications. */
7851 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7852 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7854 /* If we couldn't simplify X any other way, just enclose it in a
7855 SUBREG. Normally, this SUBREG won't match, but some patterns may
7856 include an explicit SUBREG or we may simplify it further in combine. */
7861 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7862 word = ((GET_MODE_SIZE (GET_MODE (x))
7863 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7865 return gen_rtx (SUBREG, mode, x, word);
7869 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7870 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7872 If the identical expression was previously in the insn (in the undobuf),
7873 it will be returned. Only if it is not found will a new expression
7878 gen_rtx_combine (va_alist)
7883 enum machine_mode mode;
7891 code = va_arg (p, enum rtx_code);
7892 mode = va_arg (p, enum machine_mode);
7893 n_args = GET_RTX_LENGTH (code);
7894 fmt = GET_RTX_FORMAT (code);
7896 if (n_args == 0 || n_args > 3)
7899 /* Get each arg and verify that it is supposed to be an expression. */
7900 for (j = 0; j < n_args; j++)
7905 args[j] = va_arg (p, rtx);
7908 /* See if this is in undobuf. Be sure we don't use objects that came
7909 from another insn; this could produce circular rtl structures. */
7911 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7912 if (!undobuf.undo[i].is_int
7913 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7914 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7916 for (j = 0; j < n_args; j++)
7917 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7921 return undobuf.undo[i].old_contents.rtx;
7924 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7925 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7926 rt = rtx_alloc (code);
7927 PUT_MODE (rt, mode);
7928 XEXP (rt, 0) = args[0];
7931 XEXP (rt, 1) = args[1];
7933 XEXP (rt, 2) = args[2];
7938 /* These routines make binary and unary operations by first seeing if they
7939 fold; if not, a new expression is allocated. */
7942 gen_binary (code, mode, op0, op1)
7944 enum machine_mode mode;
7950 if (GET_RTX_CLASS (code) == 'c'
7951 && (GET_CODE (op0) == CONST_INT
7952 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7953 tem = op0, op0 = op1, op1 = tem;
7955 if (GET_RTX_CLASS (code) == '<')
7957 enum machine_mode op_mode = GET_MODE (op0);
7958 if (op_mode == VOIDmode)
7959 op_mode = GET_MODE (op1);
7960 result = simplify_relational_operation (code, op_mode, op0, op1);
7963 result = simplify_binary_operation (code, mode, op0, op1);
7968 /* Put complex operands first and constants second. */
7969 if (GET_RTX_CLASS (code) == 'c'
7970 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7971 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7972 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7973 || (GET_CODE (op0) == SUBREG
7974 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7975 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7976 return gen_rtx_combine (code, mode, op1, op0);
7978 return gen_rtx_combine (code, mode, op0, op1);
7982 gen_unary (code, mode, op0)
7984 enum machine_mode mode;
7987 rtx result = simplify_unary_operation (code, mode, op0, mode);
7992 return gen_rtx_combine (code, mode, op0);
7995 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7996 comparison code that will be tested.
7998 The result is a possibly different comparison code to use. *POP0 and
7999 *POP1 may be updated.
8001 It is possible that we might detect that a comparison is either always
8002 true or always false. However, we do not perform general constant
8003 folding in combine, so this knowledge isn't useful. Such tautologies
8004 should have been detected earlier. Hence we ignore all such cases. */
8006 static enum rtx_code
8007 simplify_comparison (code, pop0, pop1)
8016 enum machine_mode mode, tmode;
8018 /* Try a few ways of applying the same transformation to both operands. */
8021 /* If both operands are the same constant shift, see if we can ignore the
8022 shift. We can if the shift is a rotate or if the bits shifted out of
8023 this shift are known to be zero for both inputs and if the type of
8024 comparison is compatible with the shift. */
8025 if (GET_CODE (op0) == GET_CODE (op1)
8026 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8027 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8028 || ((GET_CODE (op0) == LSHIFTRT
8029 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8030 && (code != GT && code != LT && code != GE && code != LE))
8031 || (GET_CODE (op0) == ASHIFTRT
8032 && (code != GTU && code != LTU
8033 && code != GEU && code != GEU)))
8034 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8035 && INTVAL (XEXP (op0, 1)) >= 0
8036 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8037 && XEXP (op0, 1) == XEXP (op1, 1))
8039 enum machine_mode mode = GET_MODE (op0);
8040 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8041 int shift_count = INTVAL (XEXP (op0, 1));
8043 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8044 mask &= (mask >> shift_count) << shift_count;
8045 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
8046 mask = (mask & (mask << shift_count)) >> shift_count;
8048 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8049 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8050 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8055 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8056 SUBREGs are of the same mode, and, in both cases, the AND would
8057 be redundant if the comparison was done in the narrower mode,
8058 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8059 and the operand's possibly nonzero bits are 0xffffff01; in that case
8060 if we only care about QImode, we don't need the AND). This case
8061 occurs if the output mode of an scc insn is not SImode and
8062 STORE_FLAG_VALUE == 1 (e.g., the 386). */
8064 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8065 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8066 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8067 && GET_CODE (XEXP (op0, 0)) == SUBREG
8068 && GET_CODE (XEXP (op1, 0)) == SUBREG
8069 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
8070 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
8071 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
8072 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8073 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8074 <= HOST_BITS_PER_WIDE_INT)
8075 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
8076 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
8077 & ~ INTVAL (XEXP (op0, 1))) == 0
8078 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
8079 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
8080 & ~ INTVAL (XEXP (op1, 1))) == 0)
8082 op0 = SUBREG_REG (XEXP (op0, 0));
8083 op1 = SUBREG_REG (XEXP (op1, 0));
8085 /* the resulting comparison is always unsigned since we masked off
8086 the original sign bit. */
8087 code = unsigned_condition (code);
8093 /* If the first operand is a constant, swap the operands and adjust the
8094 comparison code appropriately. */
8095 if (CONSTANT_P (op0))
8097 tem = op0, op0 = op1, op1 = tem;
8098 code = swap_condition (code);
8101 /* We now enter a loop during which we will try to simplify the comparison.
8102 For the most part, we only are concerned with comparisons with zero,
8103 but some things may really be comparisons with zero but not start
8104 out looking that way. */
8106 while (GET_CODE (op1) == CONST_INT)
8108 enum machine_mode mode = GET_MODE (op0);
8109 int mode_width = GET_MODE_BITSIZE (mode);
8110 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8111 int equality_comparison_p;
8112 int sign_bit_comparison_p;
8113 int unsigned_comparison_p;
8114 HOST_WIDE_INT const_op;
8116 /* We only want to handle integral modes. This catches VOIDmode,
8117 CCmode, and the floating-point modes. An exception is that we
8118 can handle VOIDmode if OP0 is a COMPARE or a comparison
8121 if (GET_MODE_CLASS (mode) != MODE_INT
8122 && ! (mode == VOIDmode
8123 && (GET_CODE (op0) == COMPARE
8124 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
8127 /* Get the constant we are comparing against and turn off all bits
8128 not on in our mode. */
8129 const_op = INTVAL (op1);
8130 if (mode_width <= HOST_BITS_PER_WIDE_INT)
8133 /* If we are comparing against a constant power of two and the value
8134 being compared can only have that single bit nonzero (e.g., it was
8135 `and'ed with that bit), we can replace this with a comparison
8138 && (code == EQ || code == NE || code == GE || code == GEU
8139 || code == LT || code == LTU)
8140 && mode_width <= HOST_BITS_PER_WIDE_INT
8141 && exact_log2 (const_op) >= 0
8142 && nonzero_bits (op0, mode) == const_op)
8144 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
8145 op1 = const0_rtx, const_op = 0;
8148 /* Similarly, if we are comparing a value known to be either -1 or
8149 0 with -1, change it to the opposite comparison against zero. */
8152 && (code == EQ || code == NE || code == GT || code == LE
8153 || code == GEU || code == LTU)
8154 && num_sign_bit_copies (op0, mode) == mode_width)
8156 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
8157 op1 = const0_rtx, const_op = 0;
8160 /* Do some canonicalizations based on the comparison code. We prefer
8161 comparisons against zero and then prefer equality comparisons.
8162 If we can reduce the size of a constant, we will do that too. */
8167 /* < C is equivalent to <= (C - 1) */
8171 op1 = GEN_INT (const_op);
8173 /* ... fall through to LE case below. */
8179 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8183 op1 = GEN_INT (const_op);
8187 /* If we are doing a <= 0 comparison on a value known to have
8188 a zero sign bit, we can replace this with == 0. */
8189 else if (const_op == 0
8190 && mode_width <= HOST_BITS_PER_WIDE_INT
8191 && (nonzero_bits (op0, mode)
8192 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8197 /* >= C is equivalent to > (C - 1). */
8201 op1 = GEN_INT (const_op);
8203 /* ... fall through to GT below. */
8209 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8213 op1 = GEN_INT (const_op);
8217 /* If we are doing a > 0 comparison on a value known to have
8218 a zero sign bit, we can replace this with != 0. */
8219 else if (const_op == 0
8220 && mode_width <= HOST_BITS_PER_WIDE_INT
8221 && (nonzero_bits (op0, mode)
8222 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8227 /* < C is equivalent to <= (C - 1). */
8231 op1 = GEN_INT (const_op);
8233 /* ... fall through ... */
8236 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8237 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8239 const_op = 0, op1 = const0_rtx;
8247 /* unsigned <= 0 is equivalent to == 0 */
8251 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8252 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8254 const_op = 0, op1 = const0_rtx;
8260 /* >= C is equivalent to < (C - 1). */
8264 op1 = GEN_INT (const_op);
8266 /* ... fall through ... */
8269 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8270 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8272 const_op = 0, op1 = const0_rtx;
8279 /* unsigned > 0 is equivalent to != 0 */
8283 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8284 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8286 const_op = 0, op1 = const0_rtx;
8292 /* Compute some predicates to simplify code below. */
8294 equality_comparison_p = (code == EQ || code == NE);
8295 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8296 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8299 /* Now try cases based on the opcode of OP0. If none of the cases
8300 does a "continue", we exit this loop immediately after the
8303 switch (GET_CODE (op0))
8306 /* If we are extracting a single bit from a variable position in
8307 a constant that has only a single bit set and are comparing it
8308 with zero, we can convert this into an equality comparison
8309 between the position and the location of the single bit. We can't
8310 do this if bit endian and we don't have an extzv since we then
8311 can't know what mode to use for the endianness adjustment. */
8313 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8314 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8315 && XEXP (op0, 1) == const1_rtx
8316 && equality_comparison_p && const_op == 0
8317 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8320 i = (GET_MODE_BITSIZE
8321 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8324 op0 = XEXP (op0, 2);
8328 /* Result is nonzero iff shift count is equal to I. */
8329 code = reverse_condition (code);
8334 /* ... fall through ... */
8337 tem = expand_compound_operation (op0);
8346 /* If testing for equality, we can take the NOT of the constant. */
8347 if (equality_comparison_p
8348 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8350 op0 = XEXP (op0, 0);
8355 /* If just looking at the sign bit, reverse the sense of the
8357 if (sign_bit_comparison_p)
8359 op0 = XEXP (op0, 0);
8360 code = (code == GE ? LT : GE);
8366 /* If testing for equality, we can take the NEG of the constant. */
8367 if (equality_comparison_p
8368 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8370 op0 = XEXP (op0, 0);
8375 /* The remaining cases only apply to comparisons with zero. */
8379 /* When X is ABS or is known positive,
8380 (neg X) is < 0 if and only if X != 0. */
8382 if (sign_bit_comparison_p
8383 && (GET_CODE (XEXP (op0, 0)) == ABS
8384 || (mode_width <= HOST_BITS_PER_WIDE_INT
8385 && (nonzero_bits (XEXP (op0, 0), mode)
8386 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8388 op0 = XEXP (op0, 0);
8389 code = (code == LT ? NE : EQ);
8393 /* If we have NEG of something whose two high-order bits are the
8394 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8395 if (num_sign_bit_copies (op0, mode) >= 2)
8397 op0 = XEXP (op0, 0);
8398 code = swap_condition (code);
8404 /* If we are testing equality and our count is a constant, we
8405 can perform the inverse operation on our RHS. */
8406 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8407 && (tem = simplify_binary_operation (ROTATERT, mode,
8408 op1, XEXP (op0, 1))) != 0)
8410 op0 = XEXP (op0, 0);
8415 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8416 a particular bit. Convert it to an AND of a constant of that
8417 bit. This will be converted into a ZERO_EXTRACT. */
8418 if (const_op == 0 && sign_bit_comparison_p
8419 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8420 && mode_width <= HOST_BITS_PER_WIDE_INT)
8422 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8425 - INTVAL (XEXP (op0, 1)))));
8426 code = (code == LT ? NE : EQ);
8430 /* ... fall through ... */
8433 /* ABS is ignorable inside an equality comparison with zero. */
8434 if (const_op == 0 && equality_comparison_p)
8436 op0 = XEXP (op0, 0);
8443 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8444 to (compare FOO CONST) if CONST fits in FOO's mode and we
8445 are either testing inequality or have an unsigned comparison
8446 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8447 if (! unsigned_comparison_p
8448 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8449 <= HOST_BITS_PER_WIDE_INT)
8450 && ((unsigned HOST_WIDE_INT) const_op
8451 < (((HOST_WIDE_INT) 1
8452 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8454 op0 = XEXP (op0, 0);
8460 /* Check for the case where we are comparing A - C1 with C2,
8461 both constants are smaller than 1/2 the maxium positive
8462 value in MODE, and the comparison is equality or unsigned.
8463 In that case, if A is either zero-extended to MODE or has
8464 sufficient sign bits so that the high-order bit in MODE
8465 is a copy of the sign in the inner mode, we can prove that it is
8466 safe to do the operation in the wider mode. This simplifies
8467 many range checks. */
8469 if (mode_width <= HOST_BITS_PER_WIDE_INT
8470 && subreg_lowpart_p (op0)
8471 && GET_CODE (SUBREG_REG (op0)) == PLUS
8472 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8473 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8474 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8475 < GET_MODE_MASK (mode) / 2)
8476 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
8477 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8478 GET_MODE (SUBREG_REG (op0)))
8479 & ~ GET_MODE_MASK (mode))
8480 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8481 GET_MODE (SUBREG_REG (op0)))
8482 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8483 - GET_MODE_BITSIZE (mode)))))
8485 op0 = SUBREG_REG (op0);
8489 /* If the inner mode is narrower and we are extracting the low part,
8490 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8491 if (subreg_lowpart_p (op0)
8492 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8493 /* Fall through */ ;
8497 /* ... fall through ... */
8500 if ((unsigned_comparison_p || equality_comparison_p)
8501 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8502 <= HOST_BITS_PER_WIDE_INT)
8503 && ((unsigned HOST_WIDE_INT) const_op
8504 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8506 op0 = XEXP (op0, 0);
8512 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
8513 this for equality comparisons due to pathological cases involving
8515 if (equality_comparison_p
8516 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8517 op1, XEXP (op0, 1))))
8519 op0 = XEXP (op0, 0);
8524 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8525 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8526 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8528 op0 = XEXP (XEXP (op0, 0), 0);
8529 code = (code == LT ? EQ : NE);
8535 /* (eq (minus A B) C) -> (eq A (plus B C)) or
8536 (eq B (minus A C)), whichever simplifies. We can only do
8537 this for equality comparisons due to pathological cases involving
8539 if (equality_comparison_p
8540 && 0 != (tem = simplify_binary_operation (PLUS, mode,
8541 XEXP (op0, 1), op1)))
8543 op0 = XEXP (op0, 0);
8548 if (equality_comparison_p
8549 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8550 XEXP (op0, 0), op1)))
8552 op0 = XEXP (op0, 1);
8557 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8558 of bits in X minus 1, is one iff X > 0. */
8559 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8560 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8561 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8562 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8564 op0 = XEXP (op0, 1);
8565 code = (code == GE ? LE : GT);
8571 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8572 if C is zero or B is a constant. */
8573 if (equality_comparison_p
8574 && 0 != (tem = simplify_binary_operation (XOR, mode,
8575 XEXP (op0, 1), op1)))
8577 op0 = XEXP (op0, 0);
8584 case LT: case LTU: case LE: case LEU:
8585 case GT: case GTU: case GE: case GEU:
8586 /* We can't do anything if OP0 is a condition code value, rather
8587 than an actual data value. */
8590 || XEXP (op0, 0) == cc0_rtx
8592 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8595 /* Get the two operands being compared. */
8596 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8597 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8599 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8601 /* Check for the cases where we simply want the result of the
8602 earlier test or the opposite of that result. */
8604 || (code == EQ && reversible_comparison_p (op0))
8605 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8606 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8607 && (STORE_FLAG_VALUE
8608 & (((HOST_WIDE_INT) 1
8609 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8611 || (code == GE && reversible_comparison_p (op0)))))
8613 code = (code == LT || code == NE
8614 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8615 op0 = tem, op1 = tem1;
8621 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8623 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8624 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8625 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8627 op0 = XEXP (op0, 1);
8628 code = (code == GE ? GT : LE);
8634 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8635 will be converted to a ZERO_EXTRACT later. */
8636 if (const_op == 0 && equality_comparison_p
8637 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8638 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8639 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8641 op0 = simplify_and_const_int
8642 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8644 XEXP (XEXP (op0, 0), 1)),
8649 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8650 zero and X is a comparison and C1 and C2 describe only bits set
8651 in STORE_FLAG_VALUE, we can compare with X. */
8652 if (const_op == 0 && equality_comparison_p
8653 && mode_width <= HOST_BITS_PER_WIDE_INT
8654 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8655 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8656 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8657 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8658 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8660 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8661 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8662 if ((~ STORE_FLAG_VALUE & mask) == 0
8663 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8664 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8665 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8667 op0 = XEXP (XEXP (op0, 0), 0);
8672 /* If we are doing an equality comparison of an AND of a bit equal
8673 to the sign bit, replace this with a LT or GE comparison of
8674 the underlying value. */
8675 if (equality_comparison_p
8677 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8678 && mode_width <= HOST_BITS_PER_WIDE_INT
8679 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8680 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8682 op0 = XEXP (op0, 0);
8683 code = (code == EQ ? GE : LT);
8687 /* If this AND operation is really a ZERO_EXTEND from a narrower
8688 mode, the constant fits within that mode, and this is either an
8689 equality or unsigned comparison, try to do this comparison in
8690 the narrower mode. */
8691 if ((equality_comparison_p || unsigned_comparison_p)
8692 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8693 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8694 & GET_MODE_MASK (mode))
8696 && const_op >> i == 0
8697 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8699 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8706 /* If we have (compare (xshift FOO N) (const_int C)) and
8707 the high order N bits of FOO (N+1 if an inequality comparison)
8708 are known to be zero, we can do this by comparing FOO with C
8709 shifted right N bits so long as the low-order N bits of C are
8711 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8712 && INTVAL (XEXP (op0, 1)) >= 0
8713 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8714 < HOST_BITS_PER_WIDE_INT)
8716 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8717 && mode_width <= HOST_BITS_PER_WIDE_INT
8718 && (nonzero_bits (XEXP (op0, 0), mode)
8719 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8720 + ! equality_comparison_p))) == 0)
8722 const_op >>= INTVAL (XEXP (op0, 1));
8723 op1 = GEN_INT (const_op);
8724 op0 = XEXP (op0, 0);
8728 /* If we are doing a sign bit comparison, it means we are testing
8729 a particular bit. Convert it to the appropriate AND. */
8730 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8731 && mode_width <= HOST_BITS_PER_WIDE_INT)
8733 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8736 - INTVAL (XEXP (op0, 1)))));
8737 code = (code == LT ? NE : EQ);
8741 /* If this an equality comparison with zero and we are shifting
8742 the low bit to the sign bit, we can convert this to an AND of the
8744 if (const_op == 0 && equality_comparison_p
8745 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8746 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8748 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8755 /* If this is an equality comparison with zero, we can do this
8756 as a logical shift, which might be much simpler. */
8757 if (equality_comparison_p && const_op == 0
8758 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8760 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8762 INTVAL (XEXP (op0, 1)));
8766 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8767 do the comparison in a narrower mode. */
8768 if (! unsigned_comparison_p
8769 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8770 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8771 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8772 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8773 MODE_INT, 1)) != BLKmode
8774 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8775 || ((unsigned HOST_WIDE_INT) - const_op
8776 <= GET_MODE_MASK (tmode))))
8778 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8782 /* ... fall through ... */
8784 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8785 the low order N bits of FOO are known to be zero, we can do this
8786 by comparing FOO with C shifted left N bits so long as no
8788 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8789 && INTVAL (XEXP (op0, 1)) >= 0
8790 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8791 && mode_width <= HOST_BITS_PER_WIDE_INT
8792 && (nonzero_bits (XEXP (op0, 0), mode)
8793 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8795 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8798 const_op <<= INTVAL (XEXP (op0, 1));
8799 op1 = GEN_INT (const_op);
8800 op0 = XEXP (op0, 0);
8804 /* If we are using this shift to extract just the sign bit, we
8805 can replace this with an LT or GE comparison. */
8807 && (equality_comparison_p || sign_bit_comparison_p)
8808 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8809 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8811 op0 = XEXP (op0, 0);
8812 code = (code == NE || code == GT ? LT : GE);
8821 /* Now make any compound operations involved in this comparison. Then,
8822 check for an outmost SUBREG on OP0 that isn't doing anything or is
8823 paradoxical. The latter case can only occur when it is known that the
8824 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8825 We can never remove a SUBREG for a non-equality comparison because the
8826 sign bit is in a different place in the underlying object. */
8828 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8829 op1 = make_compound_operation (op1, SET);
8831 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8832 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8833 && (code == NE || code == EQ)
8834 && ((GET_MODE_SIZE (GET_MODE (op0))
8835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8837 op0 = SUBREG_REG (op0);
8838 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8841 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8842 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8843 && (code == NE || code == EQ)
8844 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8845 <= HOST_BITS_PER_WIDE_INT)
8846 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8847 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8848 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8850 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
8851 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8852 op0 = SUBREG_REG (op0), op1 = tem;
8854 /* We now do the opposite procedure: Some machines don't have compare
8855 insns in all modes. If OP0's mode is an integer mode smaller than a
8856 word and we can't do a compare in that mode, see if there is a larger
8857 mode for which we can do the compare. There are a number of cases in
8858 which we can use the wider mode. */
8860 mode = GET_MODE (op0);
8861 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8862 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8863 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8864 for (tmode = GET_MODE_WIDER_MODE (mode);
8866 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8867 tmode = GET_MODE_WIDER_MODE (tmode))
8868 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8870 /* If the only nonzero bits in OP0 and OP1 are those in the
8871 narrower mode and this is an equality or unsigned comparison,
8872 we can use the wider mode. Similarly for sign-extended
8873 values and equality or signed comparisons. */
8874 if (((code == EQ || code == NE
8875 || code == GEU || code == GTU || code == LEU || code == LTU)
8876 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
8877 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
8878 || ((code == EQ || code == NE
8879 || code == GE || code == GT || code == LE || code == LT)
8880 && (num_sign_bit_copies (op0, tmode)
8881 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8882 && (num_sign_bit_copies (op1, tmode)
8883 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8885 op0 = gen_lowpart_for_combine (tmode, op0);
8886 op1 = gen_lowpart_for_combine (tmode, op1);
8890 /* If this is a test for negative, we can make an explicit
8891 test of the sign bit. */
8893 if (op1 == const0_rtx && (code == LT || code == GE)
8894 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8896 op0 = gen_binary (AND, tmode,
8897 gen_lowpart_for_combine (tmode, op0),
8898 GEN_INT ((HOST_WIDE_INT) 1
8899 << (GET_MODE_BITSIZE (mode) - 1)));
8900 code = (code == LT) ? NE : EQ;
8911 /* Return 1 if we know that X, a comparison operation, is not operating
8912 on a floating-point value or is EQ or NE, meaning that we can safely
8916 reversible_comparison_p (x)
8919 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8920 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8923 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8926 case MODE_PARTIAL_INT:
8927 case MODE_COMPLEX_INT:
8931 x = get_last_value (XEXP (x, 0));
8932 return (x && GET_CODE (x) == COMPARE
8933 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
8939 /* Utility function for following routine. Called when X is part of a value
8940 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8941 for each register mentioned. Similar to mention_regs in cse.c */
8944 update_table_tick (x)
8947 register enum rtx_code code = GET_CODE (x);
8948 register char *fmt = GET_RTX_FORMAT (code);
8953 int regno = REGNO (x);
8954 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8955 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8957 for (i = regno; i < endregno; i++)
8958 reg_last_set_table_tick[i] = label_tick;
8963 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8964 /* Note that we can't have an "E" in values stored; see
8965 get_last_value_validate. */
8967 update_table_tick (XEXP (x, i));
8970 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8971 are saying that the register is clobbered and we no longer know its
8972 value. If INSN is zero, don't update reg_last_set; this is only permitted
8973 with VALUE also zero and is used to invalidate the register. */
8976 record_value_for_reg (reg, insn, value)
8981 int regno = REGNO (reg);
8982 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8983 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8986 /* If VALUE contains REG and we have a previous value for REG, substitute
8987 the previous value. */
8988 if (value && insn && reg_overlap_mentioned_p (reg, value))
8992 /* Set things up so get_last_value is allowed to see anything set up to
8994 subst_low_cuid = INSN_CUID (insn);
8995 tem = get_last_value (reg);
8998 value = replace_rtx (copy_rtx (value), reg, tem);
9001 /* For each register modified, show we don't know its value, that
9002 its value has been updated, and that we don't know the location of
9003 the death of the register. */
9004 for (i = regno; i < endregno; i ++)
9007 reg_last_set[i] = insn;
9008 reg_last_set_value[i] = 0;
9009 reg_last_death[i] = 0;
9012 /* Mark registers that are being referenced in this value. */
9014 update_table_tick (value);
9016 /* Now update the status of each register being set.
9017 If someone is using this register in this block, set this register
9018 to invalid since we will get confused between the two lives in this
9019 basic block. This makes using this register always invalid. In cse, we
9020 scan the table to invalidate all entries using this register, but this
9021 is too much work for us. */
9023 for (i = regno; i < endregno; i++)
9025 reg_last_set_label[i] = label_tick;
9026 if (value && reg_last_set_table_tick[i] == label_tick)
9027 reg_last_set_invalid[i] = 1;
9029 reg_last_set_invalid[i] = 0;
9032 /* The value being assigned might refer to X (like in "x++;"). In that
9033 case, we must replace it with (clobber (const_int 0)) to prevent
9035 if (value && ! get_last_value_validate (&value,
9036 reg_last_set_label[regno], 0))
9038 value = copy_rtx (value);
9039 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9043 /* For the main register being modified, update the value, the mode, the
9044 nonzero bits, and the number of sign bit copies. */
9046 reg_last_set_value[regno] = value;
9050 subst_low_cuid = INSN_CUID (insn);
9051 reg_last_set_mode[regno] = GET_MODE (reg);
9052 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
9053 reg_last_set_sign_bit_copies[regno]
9054 = num_sign_bit_copies (value, GET_MODE (reg));
9058 /* Used for communication between the following two routines. */
9059 static rtx record_dead_insn;
9061 /* Called via note_stores from record_dead_and_set_regs to handle one
9062 SET or CLOBBER in an insn. */
9065 record_dead_and_set_regs_1 (dest, setter)
9068 if (GET_CODE (dest) == REG)
9070 /* If we are setting the whole register, we know its value. Otherwise
9071 show that we don't know the value. We can handle SUBREG in
9073 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
9074 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
9075 else if (GET_CODE (setter) == SET
9076 && GET_CODE (SET_DEST (setter)) == SUBREG
9077 && SUBREG_REG (SET_DEST (setter)) == dest
9078 && subreg_lowpart_p (SET_DEST (setter)))
9079 record_value_for_reg (dest, record_dead_insn,
9080 gen_lowpart_for_combine (GET_MODE (dest),
9083 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
9085 else if (GET_CODE (dest) == MEM
9086 /* Ignore pushes, they clobber nothing. */
9087 && ! push_operand (dest, GET_MODE (dest)))
9088 mem_last_set = INSN_CUID (record_dead_insn);
9091 /* Update the records of when each REG was most recently set or killed
9092 for the things done by INSN. This is the last thing done in processing
9093 INSN in the combiner loop.
9095 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
9096 similar information mem_last_set (which insn most recently modified memory)
9097 and last_call_cuid (which insn was the most recent subroutine call). */
9100 record_dead_and_set_regs (insn)
9106 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
9108 if (REG_NOTE_KIND (link) == REG_DEAD
9109 && GET_CODE (XEXP (link, 0)) == REG)
9111 int regno = REGNO (XEXP (link, 0));
9113 = regno + (regno < FIRST_PSEUDO_REGISTER
9114 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
9117 for (i = regno; i < endregno; i++)
9118 reg_last_death[i] = insn;
9120 else if (REG_NOTE_KIND (link) == REG_INC)
9121 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
9124 if (GET_CODE (insn) == CALL_INSN)
9126 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9127 if (call_used_regs[i])
9129 reg_last_set_value[i] = 0;
9130 reg_last_death[i] = 0;
9133 last_call_cuid = mem_last_set = INSN_CUID (insn);
9136 record_dead_insn = insn;
9137 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
9140 /* Utility routine for the following function. Verify that all the registers
9141 mentioned in *LOC are valid when *LOC was part of a value set when
9142 label_tick == TICK. Return 0 if some are not.
9144 If REPLACE is non-zero, replace the invalid reference with
9145 (clobber (const_int 0)) and return 1. This replacement is useful because
9146 we often can get useful information about the form of a value (e.g., if
9147 it was produced by a shift that always produces -1 or 0) even though
9148 we don't know exactly what registers it was produced from. */
9151 get_last_value_validate (loc, tick, replace)
9157 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9158 int len = GET_RTX_LENGTH (GET_CODE (x));
9161 if (GET_CODE (x) == REG)
9163 int regno = REGNO (x);
9164 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9165 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9168 for (j = regno; j < endregno; j++)
9169 if (reg_last_set_invalid[j]
9170 /* If this is a pseudo-register that was only set once, it is
9172 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
9173 && reg_last_set_label[j] > tick))
9176 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9183 for (i = 0; i < len; i++)
9185 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
9186 /* Don't bother with these. They shouldn't occur anyway. */
9190 /* If we haven't found a reason for it to be invalid, it is valid. */
9194 /* Get the last value assigned to X, if known. Some registers
9195 in the value may be replaced with (clobber (const_int 0)) if their value
9196 is known longer known reliably. */
9205 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9206 then convert it to the desired mode. If this is a paradoxical SUBREG,
9207 we cannot predict what values the "extra" bits might have. */
9208 if (GET_CODE (x) == SUBREG
9209 && subreg_lowpart_p (x)
9210 && (GET_MODE_SIZE (GET_MODE (x))
9211 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
9212 && (value = get_last_value (SUBREG_REG (x))) != 0)
9213 return gen_lowpart_for_combine (GET_MODE (x), value);
9215 if (GET_CODE (x) != REG)
9219 value = reg_last_set_value[regno];
9221 /* If we don't have a value or if it isn't for this basic block, return 0. */
9224 || (reg_n_sets[regno] != 1
9225 && reg_last_set_label[regno] != label_tick))
9228 /* If the value was set in a later insn that the ones we are processing,
9229 we can't use it even if the register was only set once, but make a quick
9230 check to see if the previous insn set it to something. This is commonly
9231 the case when the same pseudo is used by repeated insns. */
9233 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
9237 for (insn = prev_nonnote_insn (subst_insn);
9238 insn && INSN_CUID (insn) >= subst_low_cuid;
9239 insn = prev_nonnote_insn (insn))
9243 && (set = single_set (insn)) != 0
9244 && rtx_equal_p (SET_DEST (set), x))
9246 value = SET_SRC (set);
9248 /* Make sure that VALUE doesn't reference X. Replace any
9249 expliit references with a CLOBBER. If there are any remaining
9250 references (rare), don't use the value. */
9252 if (reg_mentioned_p (x, value))
9253 value = replace_rtx (copy_rtx (value), x,
9254 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
9256 if (reg_overlap_mentioned_p (x, value))
9263 /* If the value has all its registers valid, return it. */
9264 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
9267 /* Otherwise, make a copy and replace any invalid register with
9268 (clobber (const_int 0)). If that fails for some reason, return 0. */
9270 value = copy_rtx (value);
9271 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
9277 /* Return nonzero if expression X refers to a REG or to memory
9278 that is set in an instruction more recent than FROM_CUID. */
9281 use_crosses_set_p (x, from_cuid)
9287 register enum rtx_code code = GET_CODE (x);
9291 register int regno = REGNO (x);
9292 #ifdef PUSH_ROUNDING
9293 /* Don't allow uses of the stack pointer to be moved,
9294 because we don't know whether the move crosses a push insn. */
9295 if (regno == STACK_POINTER_REGNUM)
9298 return (reg_last_set[regno]
9299 && INSN_CUID (reg_last_set[regno]) > from_cuid);
9302 if (code == MEM && mem_last_set > from_cuid)
9305 fmt = GET_RTX_FORMAT (code);
9307 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9312 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9313 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
9316 else if (fmt[i] == 'e'
9317 && use_crosses_set_p (XEXP (x, i), from_cuid))
9323 /* Define three variables used for communication between the following
9326 static int reg_dead_regno, reg_dead_endregno;
9327 static int reg_dead_flag;
9329 /* Function called via note_stores from reg_dead_at_p.
9331 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9332 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9335 reg_dead_at_p_1 (dest, x)
9339 int regno, endregno;
9341 if (GET_CODE (dest) != REG)
9344 regno = REGNO (dest);
9345 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9346 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9348 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9349 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9352 /* Return non-zero if REG is known to be dead at INSN.
9354 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9355 referencing REG, it is dead. If we hit a SET referencing REG, it is
9356 live. Otherwise, see if it is live or dead at the start of the basic
9360 reg_dead_at_p (reg, insn)
9366 /* Set variables for reg_dead_at_p_1. */
9367 reg_dead_regno = REGNO (reg);
9368 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9369 ? HARD_REGNO_NREGS (reg_dead_regno,
9375 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9376 beginning of function. */
9377 for (; insn && GET_CODE (insn) != CODE_LABEL;
9378 insn = prev_nonnote_insn (insn))
9380 note_stores (PATTERN (insn), reg_dead_at_p_1);
9382 return reg_dead_flag == 1 ? 1 : 0;
9384 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9388 /* Get the basic block number that we were in. */
9393 for (block = 0; block < n_basic_blocks; block++)
9394 if (insn == basic_block_head[block])
9397 if (block == n_basic_blocks)
9401 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9402 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9403 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9409 /* Remove register number REGNO from the dead registers list of INSN.
9411 Return the note used to record the death, if there was one. */
9414 remove_death (regno, insn)
9418 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9422 reg_n_deaths[regno]--;
9423 remove_note (insn, note);
9429 /* For each register (hardware or pseudo) used within expression X, if its
9430 death is in an instruction with cuid between FROM_CUID (inclusive) and
9431 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9432 list headed by PNOTES.
9434 This is done when X is being merged by combination into TO_INSN. These
9435 notes will then be distributed as needed. */
9438 move_deaths (x, from_cuid, to_insn, pnotes)
9445 register int len, i;
9446 register enum rtx_code code = GET_CODE (x);
9450 register int regno = REGNO (x);
9451 register rtx where_dead = reg_last_death[regno];
9453 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9454 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9456 rtx note = remove_death (regno, where_dead);
9458 /* It is possible for the call above to return 0. This can occur
9459 when reg_last_death points to I2 or I1 that we combined with.
9460 In that case make a new note.
9462 We must also check for the case where X is a hard register
9463 and NOTE is a death note for a range of hard registers
9464 including X. In that case, we must put REG_DEAD notes for
9465 the remaining registers in place of NOTE. */
9467 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
9468 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
9469 != GET_MODE_SIZE (GET_MODE (x))))
9471 int deadregno = REGNO (XEXP (note, 0));
9473 = (deadregno + HARD_REGNO_NREGS (deadregno,
9474 GET_MODE (XEXP (note, 0))));
9475 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9478 for (i = deadregno; i < deadend; i++)
9479 if (i < regno || i >= ourend)
9480 REG_NOTES (where_dead)
9481 = gen_rtx (EXPR_LIST, REG_DEAD,
9482 gen_rtx (REG, word_mode, i),
9483 REG_NOTES (where_dead));
9486 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
9488 XEXP (note, 1) = *pnotes;
9492 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9494 reg_n_deaths[regno]++;
9500 else if (GET_CODE (x) == SET)
9502 rtx dest = SET_DEST (x);
9504 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9506 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9507 that accesses one word of a multi-word item, some
9508 piece of everything register in the expression is used by
9509 this insn, so remove any old death. */
9511 if (GET_CODE (dest) == ZERO_EXTRACT
9512 || GET_CODE (dest) == STRICT_LOW_PART
9513 || (GET_CODE (dest) == SUBREG
9514 && (((GET_MODE_SIZE (GET_MODE (dest))
9515 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9516 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9517 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9519 move_deaths (dest, from_cuid, to_insn, pnotes);
9523 /* If this is some other SUBREG, we know it replaces the entire
9524 value, so use that as the destination. */
9525 if (GET_CODE (dest) == SUBREG)
9526 dest = SUBREG_REG (dest);
9528 /* If this is a MEM, adjust deaths of anything used in the address.
9529 For a REG (the only other possibility), the entire value is
9530 being replaced so the old value is not used in this insn. */
9532 if (GET_CODE (dest) == MEM)
9533 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9537 else if (GET_CODE (x) == CLOBBER)
9540 len = GET_RTX_LENGTH (code);
9541 fmt = GET_RTX_FORMAT (code);
9543 for (i = 0; i < len; i++)
9548 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9549 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9551 else if (fmt[i] == 'e')
9552 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9556 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9557 pattern of an insn. X must be a REG. */
9560 reg_bitfield_target_p (x, body)
9566 if (GET_CODE (body) == SET)
9568 rtx dest = SET_DEST (body);
9570 int regno, tregno, endregno, endtregno;
9572 if (GET_CODE (dest) == ZERO_EXTRACT)
9573 target = XEXP (dest, 0);
9574 else if (GET_CODE (dest) == STRICT_LOW_PART)
9575 target = SUBREG_REG (XEXP (dest, 0));
9579 if (GET_CODE (target) == SUBREG)
9580 target = SUBREG_REG (target);
9582 if (GET_CODE (target) != REG)
9585 tregno = REGNO (target), regno = REGNO (x);
9586 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9589 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9590 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9592 return endregno > tregno && regno < endtregno;
9595 else if (GET_CODE (body) == PARALLEL)
9596 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9597 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9603 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9604 as appropriate. I3 and I2 are the insns resulting from the combination
9605 insns including FROM (I2 may be zero).
9607 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9608 not need REG_DEAD notes because they are being substituted for. This
9609 saves searching in the most common cases.
9611 Each note in the list is either ignored or placed on some insns, depending
9612 on the type of note. */
9615 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9619 rtx elim_i2, elim_i1;
9621 rtx note, next_note;
9624 for (note = notes; note; note = next_note)
9626 rtx place = 0, place2 = 0;
9628 /* If this NOTE references a pseudo register, ensure it references
9629 the latest copy of that register. */
9630 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9631 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9632 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9634 next_note = XEXP (note, 1);
9635 switch (REG_NOTE_KIND (note))
9638 /* If this register is set or clobbered in I3, put the note there
9639 unless there is one already. */
9640 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9642 if (! (GET_CODE (XEXP (note, 0)) == REG
9643 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9644 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9647 /* Otherwise, if this register is used by I3, then this register
9648 now dies here, so we must put a REG_DEAD note here unless there
9650 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9651 && ! (GET_CODE (XEXP (note, 0)) == REG
9652 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9653 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9655 PUT_REG_NOTE_KIND (note, REG_DEAD);
9663 /* These notes say something about results of an insn. We can
9664 only support them if they used to be on I3 in which case they
9665 remain on I3. Otherwise they are ignored.
9667 If the note refers to an expression that is not a constant, we
9668 must also ignore the note since we cannot tell whether the
9669 equivalence is still true. It might be possible to do
9670 slightly better than this (we only have a problem if I2DEST
9671 or I1DEST is present in the expression), but it doesn't
9672 seem worth the trouble. */
9675 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9680 case REG_NO_CONFLICT:
9682 /* These notes say something about how a register is used. They must
9683 be present on any use of the register in I2 or I3. */
9684 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9687 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9697 /* It is too much trouble to try to see if this note is still
9698 correct in all situations. It is better to simply delete it. */
9702 /* If the insn previously containing this note still exists,
9703 put it back where it was. Otherwise move it to the previous
9704 insn. Adjust the corresponding REG_LIBCALL note. */
9705 if (GET_CODE (from_insn) != NOTE)
9709 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9710 place = prev_real_insn (from_insn);
9712 XEXP (tem, 0) = place;
9717 /* This is handled similarly to REG_RETVAL. */
9718 if (GET_CODE (from_insn) != NOTE)
9722 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9723 place = next_real_insn (from_insn);
9725 XEXP (tem, 0) = place;
9730 /* If the register is used as an input in I3, it dies there.
9731 Similarly for I2, if it is non-zero and adjacent to I3.
9733 If the register is not used as an input in either I3 or I2
9734 and it is not one of the registers we were supposed to eliminate,
9735 there are two possibilities. We might have a non-adjacent I2
9736 or we might have somehow eliminated an additional register
9737 from a computation. For example, we might have had A & B where
9738 we discover that B will always be zero. In this case we will
9739 eliminate the reference to A.
9741 In both cases, we must search to see if we can find a previous
9742 use of A and put the death note there. */
9744 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9746 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9747 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9750 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9753 /* If the register is used in both I2 and I3 and it dies in I3,
9754 we might have added another reference to it. If reg_n_refs
9755 was 2, bump it to 3. This has to be correct since the
9756 register must have been set somewhere. The reason this is
9757 done is because local-alloc.c treats 2 references as a
9760 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9761 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9762 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9763 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9766 for (tem = prev_nonnote_insn (i3);
9767 tem && (GET_CODE (tem) == INSN
9768 || GET_CODE (tem) == CALL_INSN);
9769 tem = prev_nonnote_insn (tem))
9771 /* If the register is being set at TEM, see if that is all
9772 TEM is doing. If so, delete TEM. Otherwise, make this
9773 into a REG_UNUSED note instead. */
9774 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9776 rtx set = single_set (tem);
9778 /* Verify that it was the set, and not a clobber that
9779 modified the register. */
9781 if (set != 0 && ! side_effects_p (SET_SRC (set))
9782 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9784 /* Move the notes and links of TEM elsewhere.
9785 This might delete other dead insns recursively.
9786 First set the pattern to something that won't use
9789 PATTERN (tem) = pc_rtx;
9791 distribute_notes (REG_NOTES (tem), tem, tem,
9792 NULL_RTX, NULL_RTX, NULL_RTX);
9793 distribute_links (LOG_LINKS (tem));
9795 PUT_CODE (tem, NOTE);
9796 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9797 NOTE_SOURCE_FILE (tem) = 0;
9801 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9803 /* If there isn't already a REG_UNUSED note, put one
9805 if (! find_regno_note (tem, REG_UNUSED,
9806 REGNO (XEXP (note, 0))))
9811 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9818 /* If the register is set or already dead at PLACE, we needn't do
9819 anything with this note if it is still a REG_DEAD note.
9821 Note that we cannot use just `dead_or_set_p' here since we can
9822 convert an assignment to a register into a bit-field assignment.
9823 Therefore, we must also omit the note if the register is the
9824 target of a bitfield assignment. */
9826 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9828 int regno = REGNO (XEXP (note, 0));
9830 if (dead_or_set_p (place, XEXP (note, 0))
9831 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9833 /* Unless the register previously died in PLACE, clear
9834 reg_last_death. [I no longer understand why this is
9836 if (reg_last_death[regno] != place)
9837 reg_last_death[regno] = 0;
9841 reg_last_death[regno] = place;
9843 /* If this is a death note for a hard reg that is occupying
9844 multiple registers, ensure that we are still using all
9845 parts of the object. If we find a piece of the object
9846 that is unused, we must add a USE for that piece before
9847 PLACE and put the appropriate REG_DEAD note on it.
9849 An alternative would be to put a REG_UNUSED for the pieces
9850 on the insn that set the register, but that can't be done if
9851 it is not in the same block. It is simpler, though less
9852 efficient, to add the USE insns. */
9854 if (place && regno < FIRST_PSEUDO_REGISTER
9855 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9858 = regno + HARD_REGNO_NREGS (regno,
9859 GET_MODE (XEXP (note, 0)));
9863 for (i = regno; i < endregno; i++)
9864 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9866 rtx piece = gen_rtx (REG, word_mode, i);
9869 /* See if we already placed a USE note for this
9870 register in front of PLACE. */
9872 GET_CODE (PREV_INSN (p)) == INSN
9873 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9875 if (rtx_equal_p (piece,
9876 XEXP (PATTERN (PREV_INSN (p)), 0)))
9885 = emit_insn_before (gen_rtx (USE, VOIDmode,
9888 REG_NOTES (use_insn)
9889 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9890 REG_NOTES (use_insn));
9896 /* Check for the case where the register dying partially
9897 overlaps the register set by this insn. */
9899 for (i = regno; i < endregno; i++)
9900 if (dead_or_set_regno_p (place, i))
9908 /* Put only REG_DEAD notes for pieces that are
9909 still used and that are not already dead or set. */
9911 for (i = regno; i < endregno; i++)
9913 rtx piece = gen_rtx (REG, word_mode, i);
9915 if (reg_referenced_p (piece, PATTERN (place))
9916 && ! dead_or_set_p (place, piece)
9917 && ! reg_bitfield_target_p (piece,
9919 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9931 /* Any other notes should not be present at this point in the
9938 XEXP (note, 1) = REG_NOTES (place);
9939 REG_NOTES (place) = note;
9941 else if ((REG_NOTE_KIND (note) == REG_DEAD
9942 || REG_NOTE_KIND (note) == REG_UNUSED)
9943 && GET_CODE (XEXP (note, 0)) == REG)
9944 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9948 if ((REG_NOTE_KIND (note) == REG_DEAD
9949 || REG_NOTE_KIND (note) == REG_UNUSED)
9950 && GET_CODE (XEXP (note, 0)) == REG)
9951 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9953 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9954 XEXP (note, 0), REG_NOTES (place2));
9959 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9960 I3, I2, and I1 to new locations. This is also called in one case to
9961 add a link pointing at I3 when I3's destination is changed. */
9964 distribute_links (links)
9967 rtx link, next_link;
9969 for (link = links; link; link = next_link)
9975 next_link = XEXP (link, 1);
9977 /* If the insn that this link points to is a NOTE or isn't a single
9978 set, ignore it. In the latter case, it isn't clear what we
9979 can do other than ignore the link, since we can't tell which
9980 register it was for. Such links wouldn't be used by combine
9983 It is not possible for the destination of the target of the link to
9984 have been changed by combine. The only potential of this is if we
9985 replace I3, I2, and I1 by I3 and I2. But in that case the
9986 destination of I2 also remains unchanged. */
9988 if (GET_CODE (XEXP (link, 0)) == NOTE
9989 || (set = single_set (XEXP (link, 0))) == 0)
9992 reg = SET_DEST (set);
9993 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9994 || GET_CODE (reg) == SIGN_EXTRACT
9995 || GET_CODE (reg) == STRICT_LOW_PART)
9996 reg = XEXP (reg, 0);
9998 /* A LOG_LINK is defined as being placed on the first insn that uses
9999 a register and points to the insn that sets the register. Start
10000 searching at the next insn after the target of the link and stop
10001 when we reach a set of the register or the end of the basic block.
10003 Note that this correctly handles the link that used to point from
10004 I3 to I2. Also note that not much searching is typically done here
10005 since most links don't point very far away. */
10007 for (insn = NEXT_INSN (XEXP (link, 0));
10008 (insn && GET_CODE (insn) != CODE_LABEL
10009 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
10010 insn = NEXT_INSN (insn))
10011 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
10012 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
10014 if (reg_referenced_p (reg, PATTERN (insn)))
10019 /* If we found a place to put the link, place it there unless there
10020 is already a link to the same insn as LINK at that point. */
10026 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
10027 if (XEXP (link2, 0) == XEXP (link, 0))
10032 XEXP (link, 1) = LOG_LINKS (place);
10033 LOG_LINKS (place) = link;
10040 dump_combine_stats (file)
10045 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
10046 combine_attempts, combine_merges, combine_extras, combine_successes);
10050 dump_combine_total_stats (file)
10055 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
10056 total_attempts, total_merges, total_extras, total_successes);