1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
82 #include "basic-block.h"
83 #include "insn-config.h"
84 #include "insn-flags.h"
85 #include "insn-codes.h"
86 #include "insn-attr.h"
91 /* It is not safe to use ordinary gen_lowpart in combine.
92 Use gen_lowpart_for_combine instead. See comments there. */
93 #define gen_lowpart dont_use_gen_lowpart_you_dummy
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras;
107 /* Number of instructions combined in this function. */
109 static int combine_successes;
111 /* Totals over entire compilation. */
113 static int total_attempts, total_merges, total_extras, total_successes;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid;
124 /* Get the cuid of an insn. */
126 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
128 /* Maximum register number, which is the size of the tables below. */
130 static int combine_max_regno;
132 /* Record last point of death of (hard or pseudo) register n. */
134 static rtx *reg_last_death;
136 /* Record last point of modification of (hard or pseudo) register n. */
138 static rtx *reg_last_set;
140 /* Record the cuid of the last insn that invalidated memory
141 (anything that writes memory, and subroutine calls, but not pushes). */
143 static int mem_last_set;
145 /* Record the cuid of the last CALL_INSN
146 so we can tell whether a potential combination crosses any calls. */
148 static int last_call_cuid;
150 /* When `subst' is called, this is the insn that is being modified
151 (by combining in a previous insn). The PATTERN of this insn
152 is still the old pattern partially modified and it should not be
153 looked at, but this may be used to examine the successors of the insn
154 to judge whether a simplification is valid. */
156 static rtx subst_insn;
158 /* This is the lowest CUID that `subst' is currently dealing with.
159 get_last_value will not return a value if the register was set at or
160 after this CUID. If not for this mechanism, we could get confused if
161 I2 or I1 in try_combine were an insn that used the old value of a register
162 to obtain a new value. In that case, we might erroneously get the
163 new value of the register when we wanted the old one. */
165 static int subst_low_cuid;
167 /* This is the value of undobuf.num_undo when we started processing this
168 substitution. This will prevent gen_rtx_combine from re-used a piece
169 from the previous expression. Doing so can produce circular rtl
172 static int previous_num_undos;
174 /* The next group of arrays allows the recording of the last value assigned
175 to (hard or pseudo) register n. We use this information to see if a
176 operation being processed is redundant given a prior operation performed
177 on the register. For example, an `and' with a constant is redundant if
178 all the zero bits are already known to be turned off.
180 We use an approach similar to that used by cse, but change it in the
183 (1) We do not want to reinitialize at each label.
184 (2) It is useful, but not critical, to know the actual value assigned
185 to a register. Often just its form is helpful.
187 Therefore, we maintain the following arrays:
189 reg_last_set_value the last value assigned
190 reg_last_set_label records the value of label_tick when the
191 register was assigned
192 reg_last_set_table_tick records the value of label_tick when a
193 value using the register is assigned
194 reg_last_set_invalid set to non-zero when it is not valid
195 to use the value of this register in some
198 To understand the usage of these tables, it is important to understand
199 the distinction between the value in reg_last_set_value being valid
200 and the register being validly contained in some other expression in the
203 Entry I in reg_last_set_value is valid if it is non-zero, and either
204 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
206 Register I may validly appear in any expression returned for the value
207 of another register if reg_n_sets[i] is 1. It may also appear in the
208 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
209 reg_last_set_invalid[j] is zero.
211 If an expression is found in the table containing a register which may
212 not validly appear in an expression, the register is replaced by
213 something that won't match, (clobber (const_int 0)).
215 reg_last_set_invalid[i] is set non-zero when register I is being assigned
216 to and reg_last_set_table_tick[i] == label_tick. */
218 /* Record last value assigned to (hard or pseudo) register n. */
220 static rtx *reg_last_set_value;
222 /* Record the value of label_tick when the value for register n is placed in
223 reg_last_set_value[n]. */
225 static short *reg_last_set_label;
227 /* Record the value of label_tick when an expression involving register n
228 is placed in reg_last_set_value. */
230 static short *reg_last_set_table_tick;
232 /* Set non-zero if references to register n in expressions should not be
235 static char *reg_last_set_invalid;
237 /* Incremented for each label. */
239 static short label_tick;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following array what we know about the significant
247 bits of a register, specifically which bits are known to be zero.
249 If an entry is zero, it means that we don't know anything special. */
251 static HOST_WIDE_INT *reg_significant;
253 /* Mode used to compute significance in reg_significant. It is the largest
254 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
256 static enum machine_mode significant_mode;
258 /* Nonzero if we know that a register has some leading bits that are always
259 equal to the sign bit. */
261 static char *reg_sign_bit_copies;
263 /* Nonzero when reg_significant and reg_sign_bit_copies can be safely used.
264 It is zero while computing them and after combine has completed. This
265 former test prevents propagating values based on previously set values,
266 which can be incorrect if a variable is modified in a loop. */
268 static int significant_valid;
270 /* Record one modification to rtl structure
271 to be undone by storing old_contents into *where.
272 is_int is 1 if the contents are an int. */
277 union {rtx rtx; int i;} old_contents;
278 union {rtx *rtx; int *i;} where;
281 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
282 num_undo says how many are currently recorded.
284 storage is nonzero if we must undo the allocation of new storage.
285 The value of storage is what to pass to obfree.
287 other_insn is nonzero if we have modified some other insn in the process
288 of working on subst_insn. It must be verified too. */
296 struct undo undo[MAX_UNDO];
300 static struct undobuf undobuf;
302 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
303 insn. The substitution can be undone by undo_all. If INTO is already
304 set to NEWVAL, do not record this change. Because computing NEWVAL might
305 also call SUBST, we have to compute it before we put anything into
308 #define SUBST(INTO, NEWVAL) \
309 do { rtx _new = (NEWVAL); \
310 if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].is_int = 0; \
313 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
314 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
316 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
328 undobuf.undo[undobuf.num_undo].is_int = 1; \
329 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
330 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
332 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
333 undobuf.num_undo++; \
337 /* Number of times the pseudo being substituted for
338 was found and replaced. */
340 static int n_occurrences;
342 static void set_significant ();
343 static void move_deaths ();
345 static void record_value_for_reg ();
346 static void record_dead_and_set_regs ();
347 static int use_crosses_set_p ();
348 static rtx try_combine ();
349 static rtx *find_split_point ();
351 static void undo_all ();
352 static int reg_dead_at_p ();
353 static rtx expand_compound_operation ();
354 static rtx expand_field_assignment ();
355 static rtx make_extraction ();
356 static int get_pos_from_mask ();
357 static rtx force_to_mode ();
358 static rtx known_cond ();
359 static rtx make_field_assignment ();
360 static rtx make_compound_operation ();
361 static rtx apply_distributive_law ();
362 static rtx simplify_and_const_int ();
363 static unsigned HOST_WIDE_INT significant_bits ();
364 static int num_sign_bit_copies ();
365 static int merge_outer_ops ();
366 static rtx simplify_shift_const ();
367 static int recog_for_combine ();
368 static rtx gen_lowpart_for_combine ();
369 static rtx gen_rtx_combine ();
370 static rtx gen_binary ();
371 static rtx gen_unary ();
372 static enum rtx_code simplify_comparison ();
373 static int reversible_comparison_p ();
374 static int get_last_value_validate ();
375 static rtx get_last_value ();
376 static void distribute_notes ();
377 static void distribute_links ();
379 /* Main entry point for combiner. F is the first insn of the function.
380 NREGS is the first unused pseudo-reg number. */
383 combine_instructions (f, nregs)
387 register rtx insn, next, prev;
389 register rtx links, nextlinks;
391 combine_attempts = 0;
394 combine_successes = 0;
396 combine_max_regno = nregs;
398 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
401 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
403 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
404 reg_significant = (HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
405 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
407 bzero (reg_last_death, nregs * sizeof (rtx));
408 bzero (reg_last_set, nregs * sizeof (rtx));
409 bzero (reg_last_set_value, nregs * sizeof (rtx));
410 bzero (reg_last_set_table_tick, nregs * sizeof (short));
411 bzero (reg_last_set_invalid, nregs * sizeof (char));
412 bzero (reg_significant, nregs * sizeof (HOST_WIDE_INT));
413 bzero (reg_sign_bit_copies, nregs * sizeof (char));
415 init_recog_no_volatile ();
417 /* Compute maximum uid value so uid_cuid can be allocated. */
419 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
420 if (INSN_UID (insn) > i)
423 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
425 significant_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
427 /* Don't use reg_significant when computing it. This can cause problems
428 when, for example, we have j <<= 1 in a loop. */
430 significant_valid = 0;
432 /* Compute the mapping from uids to cuids.
433 Cuids are numbers assigned to insns, like uids,
434 except that cuids increase monotonically through the code.
436 Scan all SETs and see if we can deduce anything about what
437 bits are significant for some registers. */
439 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
441 INSN_CUID (insn) = ++i;
442 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
443 note_stores (PATTERN (insn), set_significant);
446 significant_valid = 1;
448 /* Now scan all the insns in forward order. */
454 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
458 if (GET_CODE (insn) == CODE_LABEL)
461 else if (GET_CODE (insn) == INSN
462 || GET_CODE (insn) == CALL_INSN
463 || GET_CODE (insn) == JUMP_INSN)
465 /* Try this insn with each insn it links back to. */
467 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
468 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
471 /* Try each sequence of three linked insns ending with this one. */
473 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
474 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
475 nextlinks = XEXP (nextlinks, 1))
476 if ((next = try_combine (insn, XEXP (links, 0),
477 XEXP (nextlinks, 0))) != 0)
481 /* Try to combine a jump insn that uses CC0
482 with a preceding insn that sets CC0, and maybe with its
483 logical predecessor as well.
484 This is how we make decrement-and-branch insns.
485 We need this special code because data flow connections
486 via CC0 do not get entered in LOG_LINKS. */
488 if (GET_CODE (insn) == JUMP_INSN
489 && (prev = prev_nonnote_insn (insn)) != 0
490 && GET_CODE (prev) == INSN
491 && sets_cc0_p (PATTERN (prev)))
493 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
496 for (nextlinks = LOG_LINKS (prev); nextlinks;
497 nextlinks = XEXP (nextlinks, 1))
498 if ((next = try_combine (insn, prev,
499 XEXP (nextlinks, 0))) != 0)
503 /* Do the same for an insn that explicitly references CC0. */
504 if (GET_CODE (insn) == INSN
505 && (prev = prev_nonnote_insn (insn)) != 0
506 && GET_CODE (prev) == INSN
507 && sets_cc0_p (PATTERN (prev))
508 && GET_CODE (PATTERN (insn)) == SET
509 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
511 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
514 for (nextlinks = LOG_LINKS (prev); nextlinks;
515 nextlinks = XEXP (nextlinks, 1))
516 if ((next = try_combine (insn, prev,
517 XEXP (nextlinks, 0))) != 0)
521 /* Finally, see if any of the insns that this insn links to
522 explicitly references CC0. If so, try this insn, that insn,
523 and its predecessor if it sets CC0. */
524 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
525 if (GET_CODE (XEXP (links, 0)) == INSN
526 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
527 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
528 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
529 && GET_CODE (prev) == INSN
530 && sets_cc0_p (PATTERN (prev))
531 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
535 /* Try combining an insn with two different insns whose results it
537 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
538 for (nextlinks = XEXP (links, 1); nextlinks;
539 nextlinks = XEXP (nextlinks, 1))
540 if ((next = try_combine (insn, XEXP (links, 0),
541 XEXP (nextlinks, 0))) != 0)
544 if (GET_CODE (insn) != NOTE)
545 record_dead_and_set_regs (insn);
552 total_attempts += combine_attempts;
553 total_merges += combine_merges;
554 total_extras += combine_extras;
555 total_successes += combine_successes;
557 significant_valid = 0;
560 /* Called via note_stores. If X is a pseudo that is used in more than
561 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
562 set, record what bits are significant. If we are clobbering X,
563 ignore this "set" because the clobbered value won't be used.
565 If we are setting only a portion of X and we can't figure out what
566 portion, assume all bits will be used since we don't know what will
569 Similarly, set how many bits of X are known to be copies of the sign bit
570 at all locations in the function. This is the smallest number implied
574 set_significant (x, set)
580 if (GET_CODE (x) == REG
581 && REGNO (x) >= FIRST_PSEUDO_REGISTER
582 && reg_n_sets[REGNO (x)] > 1
583 && reg_basic_block[REGNO (x)] < 0
584 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
586 if (GET_CODE (set) == CLOBBER)
589 /* If this is a complex assignment, see if we can convert it into a
590 simple assignment. */
591 set = expand_field_assignment (set);
592 if (SET_DEST (set) == x)
594 reg_significant[REGNO (x)]
595 |= significant_bits (SET_SRC (set), significant_mode);
596 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
597 if (reg_sign_bit_copies[REGNO (x)] == 0
598 || reg_sign_bit_copies[REGNO (x)] > num)
599 reg_sign_bit_copies[REGNO (x)] = num;
603 reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
604 reg_sign_bit_copies[REGNO (x)] = 0;
609 /* See if INSN can be combined into I3. PRED and SUCC are optionally
610 insns that were previously combined into I3 or that will be combined
611 into the merger of INSN and I3.
613 Return 0 if the combination is not allowed for any reason.
615 If the combination is allowed, *PDEST will be set to the single
616 destination of INSN and *PSRC to the single source, and this function
620 can_combine_p (insn, i3, pred, succ, pdest, psrc)
627 rtx set = 0, src, dest;
629 int all_adjacent = (succ ? (next_active_insn (insn) == succ
630 && next_active_insn (succ) == i3)
631 : next_active_insn (insn) == i3);
633 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
634 or a PARALLEL consisting of such a SET and CLOBBERs.
636 If INSN has CLOBBER parallel parts, ignore them for our processing.
637 By definition, these happen during the execution of the insn. When it
638 is merged with another insn, all bets are off. If they are, in fact,
639 needed and aren't also supplied in I3, they may be added by
640 recog_for_combine. Otherwise, it won't match.
642 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
645 Get the source and destination of INSN. If more than one, can't
648 if (GET_CODE (PATTERN (insn)) == SET)
649 set = PATTERN (insn);
650 else if (GET_CODE (PATTERN (insn)) == PARALLEL
651 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
653 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
655 rtx elt = XVECEXP (PATTERN (insn), 0, i);
657 switch (GET_CODE (elt))
659 /* We can ignore CLOBBERs. */
664 /* Ignore SETs whose result isn't used but not those that
665 have side-effects. */
666 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
667 && ! side_effects_p (elt))
670 /* If we have already found a SET, this is a second one and
671 so we cannot combine with this insn. */
679 /* Anything else means we can't combine. */
685 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
686 so don't do anything with it. */
687 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
696 set = expand_field_assignment (set);
697 src = SET_SRC (set), dest = SET_DEST (set);
699 /* Don't eliminate a store in the stack pointer. */
700 if (dest == stack_pointer_rtx
701 /* Don't install a subreg involving two modes not tieable.
702 It can worsen register allocation, and can even make invalid reload
703 insns, since the reg inside may need to be copied from in the
704 outside mode, and that may be invalid if it is an fp reg copied in
705 integer mode. As a special exception, we can allow this if
706 I3 is simply copying DEST, a REG, to CC0. */
707 || (GET_CODE (src) == SUBREG
708 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
710 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
711 && SET_DEST (PATTERN (i3)) == cc0_rtx
712 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
715 /* If we couldn't eliminate a field assignment, we can't combine. */
716 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
717 /* Don't combine with an insn that sets a register to itself if it has
718 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
719 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
720 /* Can't merge a function call. */
721 || GET_CODE (src) == CALL
722 /* Don't substitute into an incremented register. */
723 || FIND_REG_INC_NOTE (i3, dest)
724 || (succ && FIND_REG_INC_NOTE (succ, dest))
725 /* Don't combine the end of a libcall into anything. */
726 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
727 /* Make sure that DEST is not used after SUCC but before I3. */
728 || (succ && ! all_adjacent
729 && reg_used_between_p (dest, succ, i3))
730 /* Make sure that the value that is to be substituted for the register
731 does not use any registers whose values alter in between. However,
732 If the insns are adjacent, a use can't cross a set even though we
733 think it might (this can happen for a sequence of insns each setting
734 the same destination; reg_last_set of that register might point to
735 a NOTE). Also, don't move a volatile asm across any other insns. */
737 && (use_crosses_set_p (src, INSN_CUID (insn))
738 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
739 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
740 better register allocation by not doing the combine. */
741 || find_reg_note (i3, REG_NO_CONFLICT, dest)
742 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
743 /* Don't combine across a CALL_INSN, because that would possibly
744 change whether the life span of some REGs crosses calls or not,
745 and it is a pain to update that information.
746 Exception: if source is a constant, moving it later can't hurt.
747 Accept that special case, because it helps -fforce-addr a lot. */
748 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
751 /* DEST must either be a REG or CC0. */
752 if (GET_CODE (dest) == REG)
754 /* If register alignment is being enforced for multi-word items in all
755 cases except for parameters, it is possible to have a register copy
756 insn referencing a hard register that is not allowed to contain the
757 mode being copied and which would not be valid as an operand of most
758 insns. Eliminate this problem by not combining with such an insn.
760 Also, on some machines we don't want to extend the life of a hard
763 if (GET_CODE (src) == REG
764 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
765 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
766 #ifdef SMALL_REGISTER_CLASSES
767 /* Don't extend the life of a hard register. */
768 || REGNO (src) < FIRST_PSEUDO_REGISTER
770 || (REGNO (src) < FIRST_PSEUDO_REGISTER
771 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
776 else if (GET_CODE (dest) != CC0)
779 /* Don't substitute for a register intended as a clobberable operand.
780 Similarly, don't substitute an expression containing a register that
781 will be clobbered in I3. */
782 if (GET_CODE (PATTERN (i3)) == PARALLEL)
783 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
784 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
785 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
787 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
790 /* If INSN contains anything volatile, or is an `asm' (whether volatile
791 or not), reject, unless nothing volatile comes between it and I3,
792 with the exception of SUCC. */
794 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
795 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
796 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
797 && p != succ && volatile_refs_p (PATTERN (p)))
800 /* If INSN or I2 contains an autoincrement or autodecrement,
801 make sure that register is not used between there and I3,
802 and not already used in I3 either.
803 Also insist that I3 not be a jump; if it were one
804 and the incremented register were spilled, we would lose. */
807 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
808 if (REG_NOTE_KIND (link) == REG_INC
809 && (GET_CODE (i3) == JUMP_INSN
810 || reg_used_between_p (XEXP (link, 0), insn, i3)
811 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
816 /* Don't combine an insn that follows a CC0-setting insn.
817 An insn that uses CC0 must not be separated from the one that sets it.
818 We do, however, allow I2 to follow a CC0-setting insn if that insn
819 is passed as I1; in that case it will be deleted also.
820 We also allow combining in this case if all the insns are adjacent
821 because that would leave the two CC0 insns adjacent as well.
822 It would be more logical to test whether CC0 occurs inside I1 or I2,
823 but that would be much slower, and this ought to be equivalent. */
825 p = prev_nonnote_insn (insn);
826 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
831 /* If we get here, we have passed all the tests and the combination is
840 /* LOC is the location within I3 that contains its pattern or the component
841 of a PARALLEL of the pattern. We validate that it is valid for combining.
843 One problem is if I3 modifies its output, as opposed to replacing it
844 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
845 so would produce an insn that is not equivalent to the original insns.
849 (set (reg:DI 101) (reg:DI 100))
850 (set (subreg:SI (reg:DI 101) 0) <foo>)
852 This is NOT equivalent to:
854 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
855 (set (reg:DI 101) (reg:DI 100))])
857 Not only does this modify 100 (in which case it might still be valid
858 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
860 We can also run into a problem if I2 sets a register that I1
861 uses and I1 gets directly substituted into I3 (not via I2). In that
862 case, we would be getting the wrong value of I2DEST into I3, so we
863 must reject the combination. This case occurs when I2 and I1 both
864 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
865 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
866 of a SET must prevent combination from occurring.
868 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
869 if the destination of a SET is a hard register.
871 Before doing the above check, we first try to expand a field assignment
872 into a set of logical operations.
874 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
875 we place a register that is both set and used within I3. If more than one
876 such register is detected, we fail.
878 Return 1 if the combination is valid, zero otherwise. */
881 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
891 if (GET_CODE (x) == SET)
893 rtx set = expand_field_assignment (x);
894 rtx dest = SET_DEST (set);
895 rtx src = SET_SRC (set);
896 rtx inner_dest = dest, inner_src = src;
900 while (GET_CODE (inner_dest) == STRICT_LOW_PART
901 || GET_CODE (inner_dest) == SUBREG
902 || GET_CODE (inner_dest) == ZERO_EXTRACT)
903 inner_dest = XEXP (inner_dest, 0);
905 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
908 while (GET_CODE (inner_src) == STRICT_LOW_PART
909 || GET_CODE (inner_src) == SUBREG
910 || GET_CODE (inner_src) == ZERO_EXTRACT)
911 inner_src = XEXP (inner_src, 0);
913 /* If it is better that two different modes keep two different pseudos,
914 avoid combining them. This avoids producing the following pattern
916 (set (subreg:SI (reg/v:QI 21) 0)
917 (lshiftrt:SI (reg/v:SI 20)
919 If that were made, reload could not handle the pair of
920 reg 20/21, since it would try to get any GENERAL_REGS
921 but some of them don't handle QImode. */
923 if (rtx_equal_p (inner_src, i2dest)
924 && GET_CODE (inner_dest) == REG
925 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
929 /* Check for the case where I3 modifies its output, as
931 if ((inner_dest != dest
932 && (reg_overlap_mentioned_p (i2dest, inner_dest)
933 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
934 /* This is the same test done in can_combine_p except that we
935 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
937 || (GET_CODE (inner_dest) == REG
938 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
939 #ifdef SMALL_REGISTER_CLASSES
940 && GET_CODE (src) != CALL
942 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
943 GET_MODE (inner_dest))
947 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
950 /* If DEST is used in I3, it is being killed in this insn,
951 so record that for later. */
952 if (pi3dest_killed && GET_CODE (dest) == REG
953 && reg_referenced_p (dest, PATTERN (i3)))
958 *pi3dest_killed = dest;
962 else if (GET_CODE (x) == PARALLEL)
966 for (i = 0; i < XVECLEN (x, 0); i++)
967 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
968 i1_not_in_src, pi3dest_killed))
975 /* Try to combine the insns I1 and I2 into I3.
976 Here I1 and I2 appear earlier than I3.
977 I1 can be zero; then we combine just I2 into I3.
979 It we are combining three insns and the resulting insn is not recognized,
980 try splitting it into two insns. If that happens, I2 and I3 are retained
981 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
984 If we created two insns, return I2; otherwise return I3.
985 Return 0 if the combination does not work. Then nothing is changed. */
988 try_combine (i3, i2, i1)
989 register rtx i3, i2, i1;
991 /* New patterns for I3 and I3, respectively. */
992 rtx newpat, newi2pat = 0;
993 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
994 int added_sets_1, added_sets_2;
995 /* Total number of SETs to put into I3. */
997 /* Nonzero is I2's body now appears in I3. */
999 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1000 int insn_code_number, i2_code_number, other_code_number;
1001 /* Contains I3 if the destination of I3 is used in its source, which means
1002 that the old life of I3 is being killed. If that usage is placed into
1003 I2 and not in I3, a REG_DEAD note must be made. */
1004 rtx i3dest_killed = 0;
1005 /* SET_DEST and SET_SRC of I2 and I1. */
1006 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1007 /* PATTERN (I2), or a copy of it in certain cases. */
1009 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1010 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1011 int i1_feeds_i3 = 0;
1012 /* Notes that must be added to REG_NOTES in I3 and I2. */
1013 rtx new_i3_notes, new_i2_notes;
1020 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1021 This can occur when flow deletes an insn that it has merged into an
1022 auto-increment address. We also can't do anything if I3 has a
1023 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1026 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1027 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1028 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1029 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1034 undobuf.num_undo = previous_num_undos = 0;
1035 undobuf.other_insn = 0;
1037 /* Save the current high-water-mark so we can free storage if we didn't
1038 accept this combination. */
1039 undobuf.storage = (char *) oballoc (0);
1041 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1042 code below, set I1 to be the earlier of the two insns. */
1043 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1044 temp = i1, i1 = i2, i2 = temp;
1046 /* First check for one important special-case that the code below will
1047 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1048 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1049 we may be able to replace that destination with the destination of I3.
1050 This occurs in the common code where we compute both a quotient and
1051 remainder into a structure, in which case we want to do the computation
1052 directly into the structure to avoid register-register copies.
1054 We make very conservative checks below and only try to handle the
1055 most common cases of this. For example, we only handle the case
1056 where I2 and I3 are adjacent to avoid making difficult register
1059 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1060 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1061 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1062 #ifdef SMALL_REGISTER_CLASSES
1063 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1064 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1066 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1067 && GET_CODE (PATTERN (i2)) == PARALLEL
1068 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1069 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1070 below would need to check what is inside (and reg_overlap_mentioned_p
1071 doesn't support those codes anyway). Don't allow those destinations;
1072 the resulting insn isn't likely to be recognized anyway. */
1073 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1074 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1075 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1076 SET_DEST (PATTERN (i3)))
1077 && next_real_insn (i2) == i3)
1079 rtx p2 = PATTERN (i2);
1081 /* Make sure that the destination of I3,
1082 which we are going to substitute into one output of I2,
1083 is not used within another output of I2. We must avoid making this:
1084 (parallel [(set (mem (reg 69)) ...)
1085 (set (reg 69) ...)])
1086 which is not well-defined as to order of actions.
1087 (Besides, reload can't handle output reloads for this.)
1089 The problem can also happen if the dest of I3 is a memory ref,
1090 if another dest in I2 is an indirect memory ref. */
1091 for (i = 0; i < XVECLEN (p2, 0); i++)
1092 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1093 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1094 SET_DEST (XVECEXP (p2, 0, i))))
1097 if (i == XVECLEN (p2, 0))
1098 for (i = 0; i < XVECLEN (p2, 0); i++)
1099 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1104 subst_low_cuid = INSN_CUID (i2);
1107 i2dest = SET_SRC (PATTERN (i3));
1109 /* Replace the dest in I2 with our dest and make the resulting
1110 insn the new pattern for I3. Then skip to where we
1111 validate the pattern. Everything was set up above. */
1112 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1113 SET_DEST (PATTERN (i3)));
1116 goto validate_replacement;
1121 /* If we have no I1 and I2 looks like:
1122 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1124 make up a dummy I1 that is
1127 (set (reg:CC X) (compare:CC Y (const_int 0)))
1129 (We can ignore any trailing CLOBBERs.)
1131 This undoes a previous combination and allows us to match a branch-and-
1134 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1135 && XVECLEN (PATTERN (i2), 0) >= 2
1136 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1137 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1139 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1140 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1141 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1142 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1143 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1144 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1146 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1147 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1152 /* We make I1 with the same INSN_UID as I2. This gives it
1153 the same INSN_CUID for value tracking. Our fake I1 will
1154 never appear in the insn stream so giving it the same INSN_UID
1155 as I2 will not cause a problem. */
1157 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1158 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1160 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1161 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1162 SET_DEST (PATTERN (i1)));
1167 /* Verify that I2 and I1 are valid for combining. */
1168 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1169 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1175 /* Record whether I2DEST is used in I2SRC and similarly for the other
1176 cases. Knowing this will help in register status updating below. */
1177 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1178 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1179 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1181 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1183 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1185 /* Ensure that I3's pattern can be the destination of combines. */
1186 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1187 i1 && i2dest_in_i1src && i1_feeds_i3,
1194 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1195 We used to do this EXCEPT in one case: I3 has a post-inc in an
1196 output operand. However, that exception can give rise to insns like
1198 which is a famous insn on the PDP-11 where the value of r3 used as the
1199 source was model-dependent. Avoid this sort of thing. */
1202 if (!(GET_CODE (PATTERN (i3)) == SET
1203 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1204 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1205 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1206 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1207 /* It's not the exception. */
1210 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1211 if (REG_NOTE_KIND (link) == REG_INC
1212 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1214 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1221 /* See if the SETs in I1 or I2 need to be kept around in the merged
1222 instruction: whenever the value set there is still needed past I3.
1223 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1225 For the SET in I1, we have two cases: If I1 and I2 independently
1226 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1227 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1228 in I1 needs to be kept around unless I1DEST dies or is set in either
1229 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1230 I1DEST. If so, we know I1 feeds into I2. */
1232 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1235 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1236 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1238 /* If the set in I2 needs to be kept around, we must make a copy of
1239 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1240 PATTERN (I2), we are only substituting for the original I1DEST, not into
1241 an already-substituted copy. This also prevents making self-referential
1242 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1245 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1246 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1250 i2pat = copy_rtx (i2pat);
1254 /* Substitute in the latest insn for the regs set by the earlier ones. */
1256 maxreg = max_reg_num ();
1260 /* It is possible that the source of I2 or I1 may be performing an
1261 unneeded operation, such as a ZERO_EXTEND of something that is known
1262 to have the high part zero. Handle that case by letting subst look at
1263 the innermost one of them.
1265 Another way to do this would be to have a function that tries to
1266 simplify a single insn instead of merging two or more insns. We don't
1267 do this because of the potential of infinite loops and because
1268 of the potential extra memory required. However, doing it the way
1269 we are is a bit of a kludge and doesn't catch all cases.
1271 But only do this if -fexpensive-optimizations since it slows things down
1272 and doesn't usually win. */
1274 if (flag_expensive_optimizations)
1276 /* Pass pc_rtx so no substitutions are done, just simplifications.
1277 The cases that we are interested in here do not involve the few
1278 cases were is_replaced is checked. */
1281 subst_low_cuid = INSN_CUID (i1);
1282 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1286 subst_low_cuid = INSN_CUID (i2);
1287 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1290 previous_num_undos = undobuf.num_undo;
1294 /* Many machines that don't use CC0 have insns that can both perform an
1295 arithmetic operation and set the condition code. These operations will
1296 be represented as a PARALLEL with the first element of the vector
1297 being a COMPARE of an arithmetic operation with the constant zero.
1298 The second element of the vector will set some pseudo to the result
1299 of the same arithmetic operation. If we simplify the COMPARE, we won't
1300 match such a pattern and so will generate an extra insn. Here we test
1301 for this case, where both the comparison and the operation result are
1302 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1303 I2SRC. Later we will make the PARALLEL that contains I2. */
1305 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1306 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1307 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1308 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1311 enum machine_mode compare_mode;
1313 newpat = PATTERN (i3);
1314 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1318 #ifdef EXTRA_CC_MODES
1319 /* See if a COMPARE with the operand we substituted in should be done
1320 with the mode that is currently being used. If not, do the same
1321 processing we do in `subst' for a SET; namely, if the destination
1322 is used only once, try to replace it with a register of the proper
1323 mode and also replace the COMPARE. */
1324 if (undobuf.other_insn == 0
1325 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1326 &undobuf.other_insn))
1327 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1329 != GET_MODE (SET_DEST (newpat))))
1331 int regno = REGNO (SET_DEST (newpat));
1332 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1334 if (regno < FIRST_PSEUDO_REGISTER
1335 || (reg_n_sets[regno] == 1 && ! added_sets_2
1336 && ! REG_USERVAR_P (SET_DEST (newpat))))
1338 if (regno >= FIRST_PSEUDO_REGISTER)
1339 SUBST (regno_reg_rtx[regno], new_dest);
1341 SUBST (SET_DEST (newpat), new_dest);
1342 SUBST (XEXP (*cc_use, 0), new_dest);
1343 SUBST (SET_SRC (newpat),
1344 gen_rtx_combine (COMPARE, compare_mode,
1345 i2src, const0_rtx));
1348 undobuf.other_insn = 0;
1355 n_occurrences = 0; /* `subst' counts here */
1357 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1358 need to make a unique copy of I2SRC each time we substitute it
1359 to avoid self-referential rtl. */
1361 subst_low_cuid = INSN_CUID (i2);
1362 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1363 ! i1_feeds_i3 && i1dest_in_i1src);
1364 previous_num_undos = undobuf.num_undo;
1366 /* Record whether i2's body now appears within i3's body. */
1367 i2_is_used = n_occurrences;
1370 /* If we already got a failure, don't try to do more. Otherwise,
1371 try to substitute in I1 if we have it. */
1373 if (i1 && GET_CODE (newpat) != CLOBBER)
1375 /* Before we can do this substitution, we must redo the test done
1376 above (see detailed comments there) that ensures that I1DEST
1377 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1379 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1387 subst_low_cuid = INSN_CUID (i1);
1388 newpat = subst (newpat, i1dest, i1src, 0, 0);
1389 previous_num_undos = undobuf.num_undo;
1392 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1393 to count all the ways that I2SRC and I1SRC can be used. */
1394 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1395 && i2_is_used + added_sets_2 > 1)
1396 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1397 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1399 /* Fail if we tried to make a new register (we used to abort, but there's
1400 really no reason to). */
1401 || max_reg_num () != maxreg
1402 /* Fail if we couldn't do something and have a CLOBBER. */
1403 || GET_CODE (newpat) == CLOBBER)
1409 /* If the actions of the earlier insns must be kept
1410 in addition to substituting them into the latest one,
1411 we must make a new PARALLEL for the latest insn
1412 to hold additional the SETs. */
1414 if (added_sets_1 || added_sets_2)
1418 if (GET_CODE (newpat) == PARALLEL)
1420 rtvec old = XVEC (newpat, 0);
1421 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1422 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1423 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1424 sizeof (old->elem[0]) * old->num_elem);
1429 total_sets = 1 + added_sets_1 + added_sets_2;
1430 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1431 XVECEXP (newpat, 0, 0) = old;
1435 XVECEXP (newpat, 0, --total_sets)
1436 = (GET_CODE (PATTERN (i1)) == PARALLEL
1437 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1441 /* If there is no I1, use I2's body as is. We used to also not do
1442 the subst call below if I2 was substituted into I3,
1443 but that could lose a simplification. */
1445 XVECEXP (newpat, 0, --total_sets) = i2pat;
1447 /* See comment where i2pat is assigned. */
1448 XVECEXP (newpat, 0, --total_sets)
1449 = subst (i2pat, i1dest, i1src, 0, 0);
1453 /* We come here when we are replacing a destination in I2 with the
1454 destination of I3. */
1455 validate_replacement:
1457 /* Is the result of combination a valid instruction? */
1458 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1460 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1461 the second SET's destination is a register that is unused. In that case,
1462 we just need the first SET. This can occur when simplifying a divmod
1463 insn. We *must* test for this case here because the code below that
1464 splits two independent SETs doesn't handle this case correctly when it
1465 updates the register status. Also check the case where the first
1466 SET's destination is unused. That would not cause incorrect code, but
1467 does cause an unneeded insn to remain. */
1469 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1470 && XVECLEN (newpat, 0) == 2
1471 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1472 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1473 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1474 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1475 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1476 && asm_noperands (newpat) < 0)
1478 newpat = XVECEXP (newpat, 0, 0);
1479 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1482 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1483 && XVECLEN (newpat, 0) == 2
1484 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1485 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1486 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1487 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1488 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1489 && asm_noperands (newpat) < 0)
1491 newpat = XVECEXP (newpat, 0, 1);
1492 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1495 /* See if this is an XOR. If so, perhaps the problem is that the
1496 constant is out of range. Replace it with a complemented XOR with
1497 a complemented constant; it might be in range. */
1499 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1500 && GET_CODE (SET_SRC (newpat)) == XOR
1501 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1502 && ((temp = simplify_unary_operation (NOT,
1503 GET_MODE (SET_SRC (newpat)),
1504 XEXP (SET_SRC (newpat), 1),
1505 GET_MODE (SET_SRC (newpat))))
1508 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1510 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1511 gen_unary (NOT, i_mode,
1512 gen_binary (XOR, i_mode,
1513 XEXP (SET_SRC (newpat), 0),
1516 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1517 if (insn_code_number >= 0)
1521 /* If we were combining three insns and the result is a simple SET
1522 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1523 insns. There are two ways to do this. It can be split using a
1524 machine-specific method (like when you have an addition of a large
1525 constant) or by combine in the function find_split_point. */
1527 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1528 && asm_noperands (newpat) < 0)
1530 rtx m_split, *split;
1531 rtx ni2dest = i2dest;
1533 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1534 use I2DEST as a scratch register will help. In the latter case,
1535 convert I2DEST to the mode of the source of NEWPAT if we can. */
1537 m_split = split_insns (newpat, i3);
1539 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1540 inputs of NEWPAT. */
1542 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1543 possible to try that as a scratch reg. This would require adding
1544 more code to make it work though. */
1546 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1548 /* If I2DEST is a hard register or the only use of a pseudo,
1549 we can change its mode. */
1550 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1551 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1552 && GET_CODE (i2dest) == REG
1553 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1554 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1555 && ! REG_USERVAR_P (i2dest))))
1556 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1559 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1560 gen_rtvec (2, newpat,
1567 if (m_split && GET_CODE (m_split) == SEQUENCE
1568 && XVECLEN (m_split, 0) == 2
1569 && (next_real_insn (i2) == i3
1570 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1574 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1575 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1577 i3set = single_set (XVECEXP (m_split, 0, 1));
1578 i2set = single_set (XVECEXP (m_split, 0, 0));
1580 /* In case we changed the mode of I2DEST, replace it in the
1581 pseudo-register table here. We can't do it above in case this
1582 code doesn't get executed and we do a split the other way. */
1584 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1585 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1587 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1589 /* If I2 or I3 has multiple SETs, we won't know how to track
1590 register status, so don't use these insns. */
1592 if (i2_code_number >= 0 && i2set && i3set)
1593 insn_code_number = recog_for_combine (&newi3pat, i3,
1596 if (insn_code_number >= 0)
1599 /* It is possible that both insns now set the destination of I3.
1600 If so, we must show an extra use of it. */
1602 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1603 && GET_CODE (SET_DEST (i2set)) == REG
1604 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1605 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1608 /* If we can split it and use I2DEST, go ahead and see if that
1609 helps things be recognized. Verify that none of the registers
1610 are set between I2 and I3. */
1611 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1613 && GET_CODE (i2dest) == REG
1615 /* We need I2DEST in the proper mode. If it is a hard register
1616 or the only use of a pseudo, we can change its mode. */
1617 && (GET_MODE (*split) == GET_MODE (i2dest)
1618 || GET_MODE (*split) == VOIDmode
1619 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1620 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1621 && ! REG_USERVAR_P (i2dest)))
1622 && (next_real_insn (i2) == i3
1623 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1624 /* We can't overwrite I2DEST if its value is still used by
1626 && ! reg_referenced_p (i2dest, newpat))
1628 rtx newdest = i2dest;
1630 /* Get NEWDEST as a register in the proper mode. We have already
1631 validated that we can do this. */
1632 if (GET_MODE (i2dest) != GET_MODE (*split)
1633 && GET_MODE (*split) != VOIDmode)
1635 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1637 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1638 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1641 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1642 an ASHIFT. This can occur if it was inside a PLUS and hence
1643 appeared to be a memory address. This is a kludge. */
1644 if (GET_CODE (*split) == MULT
1645 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1646 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1647 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1648 XEXP (*split, 0), GEN_INT (i)));
1650 #ifdef INSN_SCHEDULING
1651 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1652 be written as a ZERO_EXTEND. */
1653 if (GET_CODE (*split) == SUBREG
1654 && GET_CODE (SUBREG_REG (*split)) == MEM)
1655 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1659 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1660 SUBST (*split, newdest);
1661 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1662 if (i2_code_number >= 0)
1663 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1667 /* Check for a case where we loaded from memory in a narrow mode and
1668 then sign extended it, but we need both registers. In that case,
1669 we have a PARALLEL with both loads from the same memory location.
1670 We can split this into a load from memory followed by a register-register
1671 copy. This saves at least one insn, more if register allocation can
1672 eliminate the copy. */
1674 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1675 && GET_CODE (newpat) == PARALLEL
1676 && XVECLEN (newpat, 0) == 2
1677 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1678 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1679 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1680 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1681 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1682 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1684 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1685 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1686 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1687 SET_SRC (XVECEXP (newpat, 0, 1)))
1688 && ! find_reg_note (i3, REG_UNUSED,
1689 SET_DEST (XVECEXP (newpat, 0, 0))))
1693 newi2pat = XVECEXP (newpat, 0, 0);
1694 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1695 newpat = XVECEXP (newpat, 0, 1);
1696 SUBST (SET_SRC (newpat),
1697 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1698 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1699 if (i2_code_number >= 0)
1700 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1702 if (insn_code_number >= 0)
1707 /* If we will be able to accept this, we have made a change to the
1708 destination of I3. This can invalidate a LOG_LINKS pointing
1709 to I3. No other part of combine.c makes such a transformation.
1711 The new I3 will have a destination that was previously the
1712 destination of I1 or I2 and which was used in i2 or I3. Call
1713 distribute_links to make a LOG_LINK from the next use of
1714 that destination. */
1716 PATTERN (i3) = newpat;
1717 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1719 /* I3 now uses what used to be its destination and which is
1720 now I2's destination. That means we need a LOG_LINK from
1721 I3 to I2. But we used to have one, so we still will.
1723 However, some later insn might be using I2's dest and have
1724 a LOG_LINK pointing at I3. We must remove this link.
1725 The simplest way to remove the link is to point it at I1,
1726 which we know will be a NOTE. */
1728 for (insn = NEXT_INSN (i3);
1729 insn && GET_CODE (insn) != CODE_LABEL
1730 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1731 insn = NEXT_INSN (insn))
1733 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1734 && reg_referenced_p (ni2dest, PATTERN (insn)))
1736 for (link = LOG_LINKS (insn); link;
1737 link = XEXP (link, 1))
1738 if (XEXP (link, 0) == i3)
1739 XEXP (link, 0) = i1;
1747 /* Similarly, check for a case where we have a PARALLEL of two independent
1748 SETs but we started with three insns. In this case, we can do the sets
1749 as two separate insns. This case occurs when some SET allows two
1750 other insns to combine, but the destination of that SET is still live. */
1752 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1753 && GET_CODE (newpat) == PARALLEL
1754 && XVECLEN (newpat, 0) == 2
1755 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1756 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1757 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1758 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1759 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1760 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1761 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1763 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1764 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1765 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1766 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1767 XVECEXP (newpat, 0, 0))
1768 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1769 XVECEXP (newpat, 0, 1)))
1771 newi2pat = XVECEXP (newpat, 0, 1);
1772 newpat = XVECEXP (newpat, 0, 0);
1774 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1775 if (i2_code_number >= 0)
1776 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1779 /* If it still isn't recognized, fail and change things back the way they
1781 if ((insn_code_number < 0
1782 /* Is the result a reasonable ASM_OPERANDS? */
1783 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1789 /* If we had to change another insn, make sure it is valid also. */
1790 if (undobuf.other_insn)
1792 rtx other_notes = REG_NOTES (undobuf.other_insn);
1793 rtx other_pat = PATTERN (undobuf.other_insn);
1794 rtx new_other_notes;
1797 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1800 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1806 PATTERN (undobuf.other_insn) = other_pat;
1808 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1809 are still valid. Then add any non-duplicate notes added by
1810 recog_for_combine. */
1811 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1813 next = XEXP (note, 1);
1815 if (REG_NOTE_KIND (note) == REG_UNUSED
1816 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1818 if (GET_CODE (XEXP (note, 0)) == REG)
1819 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1821 remove_note (undobuf.other_insn, note);
1825 for (note = new_other_notes; note; note = XEXP (note, 1))
1826 if (GET_CODE (XEXP (note, 0)) == REG)
1827 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1829 distribute_notes (new_other_notes, undobuf.other_insn,
1830 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1833 /* We now know that we can do this combination. Merge the insns and
1834 update the status of registers and LOG_LINKS. */
1837 rtx i3notes, i2notes, i1notes = 0;
1838 rtx i3links, i2links, i1links = 0;
1840 int all_adjacent = (next_real_insn (i2) == i3
1841 && (i1 == 0 || next_real_insn (i1) == i2));
1843 /* Compute which registers we expect to eliminate. */
1844 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1846 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1848 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1850 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1851 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1853 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1855 /* Ensure that we do not have something that should not be shared but
1856 occurs multiple times in the new insns. Check this by first
1857 resetting all the `used' flags and then copying anything is shared. */
1859 reset_used_flags (i3notes);
1860 reset_used_flags (i2notes);
1861 reset_used_flags (i1notes);
1862 reset_used_flags (newpat);
1863 reset_used_flags (newi2pat);
1864 if (undobuf.other_insn)
1865 reset_used_flags (PATTERN (undobuf.other_insn));
1867 i3notes = copy_rtx_if_shared (i3notes);
1868 i2notes = copy_rtx_if_shared (i2notes);
1869 i1notes = copy_rtx_if_shared (i1notes);
1870 newpat = copy_rtx_if_shared (newpat);
1871 newi2pat = copy_rtx_if_shared (newi2pat);
1872 if (undobuf.other_insn)
1873 reset_used_flags (PATTERN (undobuf.other_insn));
1875 INSN_CODE (i3) = insn_code_number;
1876 PATTERN (i3) = newpat;
1877 if (undobuf.other_insn)
1878 INSN_CODE (undobuf.other_insn) = other_code_number;
1880 /* We had one special case above where I2 had more than one set and
1881 we replaced a destination of one of those sets with the destination
1882 of I3. In that case, we have to update LOG_LINKS of insns later
1883 in this basic block. Note that this (expensive) case is rare. */
1885 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1886 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1887 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1888 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1889 && ! find_reg_note (i2, REG_UNUSED,
1890 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1894 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1896 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1897 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1898 if (XEXP (link, 0) == i2)
1899 XEXP (link, 0) = i3;
1901 if (GET_CODE (insn) == CODE_LABEL
1902 || GET_CODE (insn) == JUMP_INSN)
1914 INSN_CODE (i2) = i2_code_number;
1915 PATTERN (i2) = newi2pat;
1919 PUT_CODE (i2, NOTE);
1920 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1921 NOTE_SOURCE_FILE (i2) = 0;
1928 PUT_CODE (i1, NOTE);
1929 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1930 NOTE_SOURCE_FILE (i1) = 0;
1933 /* Get death notes for everything that is now used in either I3 or
1934 I2 and used to die in a previous insn. */
1936 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1938 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1940 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1942 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
1945 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
1948 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
1951 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1954 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1955 know these are REG_UNUSED and want them to go to the desired insn,
1956 so we always pass it as i3. We have not counted the notes in
1957 reg_n_deaths yet, so we need to do so now. */
1959 if (newi2pat && new_i2_notes)
1961 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
1962 if (GET_CODE (XEXP (temp, 0)) == REG)
1963 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1965 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
1970 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
1971 if (GET_CODE (XEXP (temp, 0)) == REG)
1972 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1974 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
1977 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1978 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
1979 Show an additional death due to the REG_DEAD note we make here. If
1980 we discard it in distribute_notes, we will decrement it again. */
1984 if (GET_CODE (i3dest_killed) == REG)
1985 reg_n_deaths[REGNO (i3dest_killed)]++;
1987 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
1989 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1990 NULL_RTX, NULL_RTX);
1993 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
1994 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
1995 we passed I3 in that case, it might delete I2. */
1997 if (i2dest_in_i2src)
1999 if (GET_CODE (i2dest) == REG)
2000 reg_n_deaths[REGNO (i2dest)]++;
2002 if (newi2pat && reg_set_p (i2dest, newi2pat))
2003 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2004 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2006 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2007 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2008 NULL_RTX, NULL_RTX);
2011 if (i1dest_in_i1src)
2013 if (GET_CODE (i1dest) == REG)
2014 reg_n_deaths[REGNO (i1dest)]++;
2016 if (newi2pat && reg_set_p (i1dest, newi2pat))
2017 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2018 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2020 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2021 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2022 NULL_RTX, NULL_RTX);
2025 distribute_links (i3links);
2026 distribute_links (i2links);
2027 distribute_links (i1links);
2029 if (GET_CODE (i2dest) == REG)
2032 rtx i2_insn = 0, i2_val = 0, set;
2034 /* The insn that used to set this register doesn't exist, and
2035 this life of the register may not exist either. See if one of
2036 I3's links points to an insn that sets I2DEST. If it does,
2037 that is now the last known value for I2DEST. If we don't update
2038 this and I2 set the register to a value that depended on its old
2039 contents, we will get confused. If this insn is used, thing
2040 will be set correctly in combine_instructions. */
2042 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2043 if ((set = single_set (XEXP (link, 0))) != 0
2044 && rtx_equal_p (i2dest, SET_DEST (set)))
2045 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2047 record_value_for_reg (i2dest, i2_insn, i2_val);
2049 /* If the reg formerly set in I2 died only once and that was in I3,
2050 zero its use count so it won't make `reload' do any work. */
2051 if (! added_sets_2 && newi2pat == 0)
2053 regno = REGNO (i2dest);
2054 reg_n_sets[regno]--;
2055 if (reg_n_sets[regno] == 0
2056 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2057 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2058 reg_n_refs[regno] = 0;
2062 if (i1 && GET_CODE (i1dest) == REG)
2065 rtx i1_insn = 0, i1_val = 0, set;
2067 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2068 if ((set = single_set (XEXP (link, 0))) != 0
2069 && rtx_equal_p (i1dest, SET_DEST (set)))
2070 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2072 record_value_for_reg (i1dest, i1_insn, i1_val);
2074 regno = REGNO (i1dest);
2077 reg_n_sets[regno]--;
2078 if (reg_n_sets[regno] == 0
2079 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2080 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2081 reg_n_refs[regno] = 0;
2085 /* Update reg_significant et al for any changes that may have been made
2088 note_stores (newpat, set_significant);
2090 note_stores (newi2pat, set_significant);
2092 /* If I3 is now an unconditional jump, ensure that it has a
2093 BARRIER following it since it may have initially been a
2094 conditional jump. It may also be the last nonnote insn. */
2096 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2097 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2098 || GET_CODE (temp) != BARRIER))
2099 emit_barrier_after (i3);
2102 combine_successes++;
2104 return newi2pat ? i2 : i3;
2107 /* Undo all the modifications recorded in undobuf. */
2113 if (undobuf.num_undo > MAX_UNDO)
2114 undobuf.num_undo = MAX_UNDO;
2115 for (i = undobuf.num_undo - 1; i >= 0; i--)
2117 if (undobuf.undo[i].is_int)
2118 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2120 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2124 obfree (undobuf.storage);
2125 undobuf.num_undo = 0;
2128 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2129 where we have an arithmetic expression and return that point. LOC will
2132 try_combine will call this function to see if an insn can be split into
2136 find_split_point (loc, insn)
2141 enum rtx_code code = GET_CODE (x);
2143 int len = 0, pos, unsignedp;
2146 /* First special-case some codes. */
2150 #ifdef INSN_SCHEDULING
2151 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2153 if (GET_CODE (SUBREG_REG (x)) == MEM)
2156 return find_split_point (&SUBREG_REG (x), insn);
2160 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2161 using LO_SUM and HIGH. */
2162 if (GET_CODE (XEXP (x, 0)) == CONST
2163 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2166 gen_rtx_combine (LO_SUM, Pmode,
2167 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2169 return &XEXP (XEXP (x, 0), 0);
2173 /* If we have a PLUS whose second operand is a constant and the
2174 address is not valid, perhaps will can split it up using
2175 the machine-specific way to split large constants. We use
2176 the first psuedo-reg (one of the virtual regs) as a placeholder;
2177 it will not remain in the result. */
2178 if (GET_CODE (XEXP (x, 0)) == PLUS
2179 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2180 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2182 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2183 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2186 /* This should have produced two insns, each of which sets our
2187 placeholder. If the source of the second is a valid address,
2188 we can make put both sources together and make a split point
2191 if (seq && XVECLEN (seq, 0) == 2
2192 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2193 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2194 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2195 && ! reg_mentioned_p (reg,
2196 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2197 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2198 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2199 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2200 && memory_address_p (GET_MODE (x),
2201 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2203 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2204 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2206 /* Replace the placeholder in SRC2 with SRC1. If we can
2207 find where in SRC2 it was placed, that can become our
2208 split point and we can replace this address with SRC2.
2209 Just try two obvious places. */
2211 src2 = replace_rtx (src2, reg, src1);
2213 if (XEXP (src2, 0) == src1)
2214 split = &XEXP (src2, 0);
2215 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2216 && XEXP (XEXP (src2, 0), 0) == src1)
2217 split = &XEXP (XEXP (src2, 0), 0);
2221 SUBST (XEXP (x, 0), src2);
2226 /* If that didn't work, perhaps the first operand is complex and
2227 needs to be computed separately, so make a split point there.
2228 This will occur on machines that just support REG + CONST
2229 and have a constant moved through some previous computation. */
2231 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2232 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2233 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2235 return &XEXP (XEXP (x, 0), 0);
2241 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2242 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2243 we need to put the operand into a register. So split at that
2246 if (SET_DEST (x) == cc0_rtx
2247 && GET_CODE (SET_SRC (x)) != COMPARE
2248 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2249 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2250 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2251 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2252 return &SET_SRC (x);
2255 /* See if we can split SET_SRC as it stands. */
2256 split = find_split_point (&SET_SRC (x), insn);
2257 if (split && split != &SET_SRC (x))
2260 /* See if this is a bitfield assignment with everything constant. If
2261 so, this is an IOR of an AND, so split it into that. */
2262 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2263 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2264 <= HOST_BITS_PER_WIDE_INT)
2265 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2266 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2267 && GET_CODE (SET_SRC (x)) == CONST_INT
2268 && ((INTVAL (XEXP (SET_DEST (x), 1))
2269 + INTVAL (XEXP (SET_DEST (x), 2)))
2270 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2271 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2273 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2274 int len = INTVAL (XEXP (SET_DEST (x), 1));
2275 int src = INTVAL (SET_SRC (x));
2276 rtx dest = XEXP (SET_DEST (x), 0);
2277 enum machine_mode mode = GET_MODE (dest);
2278 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2281 pos = GET_MODE_BITSIZE (mode) - len - pos;
2286 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2289 gen_binary (IOR, mode,
2290 gen_binary (AND, mode, dest,
2291 GEN_INT (~ (mask << pos)
2292 & GET_MODE_MASK (mode))),
2293 GEN_INT (src << pos)));
2295 SUBST (SET_DEST (x), dest);
2297 split = find_split_point (&SET_SRC (x), insn);
2298 if (split && split != &SET_SRC (x))
2302 /* Otherwise, see if this is an operation that we can split into two.
2303 If so, try to split that. */
2304 code = GET_CODE (SET_SRC (x));
2309 /* If we are AND'ing with a large constant that is only a single
2310 bit and the result is only being used in a context where we
2311 need to know if it is zero or non-zero, replace it with a bit
2312 extraction. This will avoid the large constant, which might
2313 have taken more than one insn to make. If the constant were
2314 not a valid argument to the AND but took only one insn to make,
2315 this is no worse, but if it took more than one insn, it will
2318 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2319 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2320 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2321 && GET_CODE (SET_DEST (x)) == REG
2322 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2323 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2324 && XEXP (*split, 0) == SET_DEST (x)
2325 && XEXP (*split, 1) == const0_rtx)
2328 make_extraction (GET_MODE (SET_DEST (x)),
2329 XEXP (SET_SRC (x), 0),
2330 pos, NULL_RTX, 1, 1, 0, 0));
2331 return find_split_point (loc, insn);
2336 inner = XEXP (SET_SRC (x), 0);
2338 len = GET_MODE_BITSIZE (GET_MODE (inner));
2344 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2345 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2347 inner = XEXP (SET_SRC (x), 0);
2348 len = INTVAL (XEXP (SET_SRC (x), 1));
2349 pos = INTVAL (XEXP (SET_SRC (x), 2));
2352 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2354 unsignedp = (code == ZERO_EXTRACT);
2359 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2361 enum machine_mode mode = GET_MODE (SET_SRC (x));
2363 /* For unsigned, we have a choice of a shift followed by an
2364 AND or two shifts. Use two shifts for field sizes where the
2365 constant might be too large. We assume here that we can
2366 always at least get 8-bit constants in an AND insn, which is
2367 true for every current RISC. */
2369 if (unsignedp && len <= 8)
2374 gen_rtx_combine (LSHIFTRT, mode,
2375 gen_lowpart_for_combine (mode, inner),
2377 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2379 split = find_split_point (&SET_SRC (x), insn);
2380 if (split && split != &SET_SRC (x))
2387 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2388 gen_rtx_combine (ASHIFT, mode,
2389 gen_lowpart_for_combine (mode, inner),
2390 GEN_INT (GET_MODE_BITSIZE (mode)
2392 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2394 split = find_split_point (&SET_SRC (x), insn);
2395 if (split && split != &SET_SRC (x))
2400 /* See if this is a simple operation with a constant as the second
2401 operand. It might be that this constant is out of range and hence
2402 could be used as a split point. */
2403 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2404 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2405 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2406 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2407 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2408 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2409 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2411 return &XEXP (SET_SRC (x), 1);
2413 /* Finally, see if this is a simple operation with its first operand
2414 not in a register. The operation might require this operand in a
2415 register, so return it as a split point. We can always do this
2416 because if the first operand were another operation, we would have
2417 already found it as a split point. */
2418 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2419 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2420 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2421 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2422 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2423 return &XEXP (SET_SRC (x), 0);
2429 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2430 it is better to write this as (not (ior A B)) so we can split it.
2431 Similarly for IOR. */
2432 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2435 gen_rtx_combine (NOT, GET_MODE (x),
2436 gen_rtx_combine (code == IOR ? AND : IOR,
2438 XEXP (XEXP (x, 0), 0),
2439 XEXP (XEXP (x, 1), 0))));
2440 return find_split_point (loc, insn);
2443 /* Many RISC machines have a large set of logical insns. If the
2444 second operand is a NOT, put it first so we will try to split the
2445 other operand first. */
2446 if (GET_CODE (XEXP (x, 1)) == NOT)
2448 rtx tem = XEXP (x, 0);
2449 SUBST (XEXP (x, 0), XEXP (x, 1));
2450 SUBST (XEXP (x, 1), tem);
2455 /* Otherwise, select our actions depending on our rtx class. */
2456 switch (GET_RTX_CLASS (code))
2458 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2460 split = find_split_point (&XEXP (x, 2), insn);
2463 /* ... fall through ... */
2467 split = find_split_point (&XEXP (x, 1), insn);
2470 /* ... fall through ... */
2472 /* Some machines have (and (shift ...) ...) insns. If X is not
2473 an AND, but XEXP (X, 0) is, use it as our split point. */
2474 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2475 return &XEXP (x, 0);
2477 split = find_split_point (&XEXP (x, 0), insn);
2483 /* Otherwise, we don't have a split point. */
2487 /* Throughout X, replace FROM with TO, and return the result.
2488 The result is TO if X is FROM;
2489 otherwise the result is X, but its contents may have been modified.
2490 If they were modified, a record was made in undobuf so that
2491 undo_all will (among other things) return X to its original state.
2493 If the number of changes necessary is too much to record to undo,
2494 the excess changes are not made, so the result is invalid.
2495 The changes already made can still be undone.
2496 undobuf.num_undo is incremented for such changes, so by testing that
2497 the caller can tell whether the result is valid.
2499 `n_occurrences' is incremented each time FROM is replaced.
2501 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2503 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2504 by copying if `n_occurrences' is non-zero. */
2507 subst (x, from, to, in_dest, unique_copy)
2508 register rtx x, from, to;
2513 register int len, i;
2514 register enum rtx_code code = GET_CODE (x), orig_code = code;
2516 enum machine_mode mode = GET_MODE (x);
2517 enum machine_mode op0_mode = VOIDmode;
2522 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2523 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2524 If it is 0, that cannot be done. We can now do this for any MEM
2525 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2526 If not for that, MEM's would very rarely be safe. */
2528 /* Reject MODEs bigger than a word, because we might not be able
2529 to reference a two-register group starting with an arbitrary register
2530 (and currently gen_lowpart might crash for a SUBREG). */
2532 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2533 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2535 /* Two expressions are equal if they are identical copies of a shared
2536 RTX or if they are both registers with the same register number
2539 #define COMBINE_RTX_EQUAL_P(X,Y) \
2541 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2542 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2544 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2547 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2550 /* If X and FROM are the same register but different modes, they will
2551 not have been seen as equal above. However, flow.c will make a
2552 LOG_LINKS entry for that case. If we do nothing, we will try to
2553 rerecognize our original insn and, when it succeeds, we will
2554 delete the feeding insn, which is incorrect.
2556 So force this insn not to match in this (rare) case. */
2557 if (! in_dest && code == REG && GET_CODE (from) == REG
2558 && REGNO (x) == REGNO (from))
2559 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2561 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2562 of which may contain things that can be combined. */
2563 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2566 /* It is possible to have a subexpression appear twice in the insn.
2567 Suppose that FROM is a register that appears within TO.
2568 Then, after that subexpression has been scanned once by `subst',
2569 the second time it is scanned, TO may be found. If we were
2570 to scan TO here, we would find FROM within it and create a
2571 self-referent rtl structure which is completely wrong. */
2572 if (COMBINE_RTX_EQUAL_P (x, to))
2575 len = GET_RTX_LENGTH (code);
2576 fmt = GET_RTX_FORMAT (code);
2578 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2579 set up to skip this common case. All other cases where we want to
2580 suppress replacing something inside a SET_SRC are handled via the
2583 && (GET_CODE (SET_DEST (x)) == REG
2584 || GET_CODE (SET_DEST (x)) == CC0
2585 || GET_CODE (SET_DEST (x)) == PC))
2588 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2590 op0_mode = GET_MODE (XEXP (x, 0));
2592 for (i = 0; i < len; i++)
2597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2600 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2602 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2607 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2609 /* If this substitution failed, this whole thing fails. */
2610 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2614 SUBST (XVECEXP (x, i, j), new);
2617 else if (fmt[i] == 'e')
2621 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2623 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2627 /* If we are in a SET_DEST, suppress most cases unless we
2628 have gone inside a MEM, in which case we want to
2629 simplify the address. We assume here that things that
2630 are actually part of the destination have their inner
2631 parts in the first expression. This is true for SUBREG,
2632 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2633 things aside from REG and MEM that should appear in a
2635 new = subst (XEXP (x, i), from, to,
2637 && (code == SUBREG || code == STRICT_LOW_PART
2638 || code == ZERO_EXTRACT))
2640 && i == 0), unique_copy);
2642 /* If we found that we will have to reject this combination,
2643 indicate that by returning the CLOBBER ourselves, rather than
2644 an expression containing it. This will speed things up as
2645 well as prevent accidents where two CLOBBERs are considered
2646 to be equal, thus producing an incorrect simplification. */
2648 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2651 SUBST (XEXP (x, i), new);
2655 /* We come back to here if we have replaced the expression with one of
2656 a different code and it is likely that further simplification will be
2661 /* If we have restarted more than 4 times, we are probably looping, so
2663 if (++n_restarts > 4)
2666 /* If we are restarting at all, it means that we no longer know the
2667 original mode of operand 0 (since we have probably changed the
2671 op0_mode = VOIDmode;
2673 code = GET_CODE (x);
2675 /* If this is a commutative operation, put a constant last and a complex
2676 expression first. We don't need to do this for comparisons here. */
2677 if (GET_RTX_CLASS (code) == 'c'
2678 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2679 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2680 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2681 || (GET_CODE (XEXP (x, 0)) == SUBREG
2682 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2683 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2686 SUBST (XEXP (x, 0), XEXP (x, 1));
2687 SUBST (XEXP (x, 1), temp);
2690 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2691 sign extension of a PLUS with a constant, reverse the order of the sign
2692 extension and the addition. Note that this not the same as the original
2693 code, but overflow is undefined for signed values. Also note that the
2694 PLUS will have been partially moved "inside" the sign-extension, so that
2695 the first operand of X will really look like:
2696 (ashiftrt (plus (ashift A C4) C5) C4).
2698 (plus (ashiftrt (ashift A C4) C2) C4)
2699 and replace the first operand of X with that expression. Later parts
2700 of this function may simplify the expression further.
2702 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2703 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2704 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2706 We do this to simplify address expressions. */
2708 if ((code == PLUS || code == MINUS || code == MULT)
2709 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2710 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2711 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2712 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2713 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2714 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2715 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2716 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2717 XEXP (XEXP (XEXP (x, 0), 0), 1),
2718 XEXP (XEXP (x, 0), 1))) != 0)
2721 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2722 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2723 INTVAL (XEXP (XEXP (x, 0), 1)));
2725 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2726 INTVAL (XEXP (XEXP (x, 0), 1)));
2728 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2731 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2732 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2733 things. Don't deal with operations that change modes here. */
2735 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2736 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2738 /* Don't do this by using SUBST inside X since we might be messing
2739 up a shared expression. */
2740 rtx cond = XEXP (XEXP (x, 0), 0);
2741 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2743 pc_rtx, pc_rtx, 0, 0);
2744 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2746 pc_rtx, pc_rtx, 0, 0);
2749 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2753 else if (GET_RTX_CLASS (code) == '1'
2754 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2755 && GET_MODE (XEXP (x, 0)) == mode)
2757 rtx cond = XEXP (XEXP (x, 0), 0);
2758 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2759 pc_rtx, pc_rtx, 0, 0);
2760 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2761 pc_rtx, pc_rtx, 0, 0);
2763 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2767 /* Try to fold this expression in case we have constants that weren't
2770 switch (GET_RTX_CLASS (code))
2773 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2776 temp = simplify_relational_operation (code, op0_mode,
2777 XEXP (x, 0), XEXP (x, 1));
2778 #ifdef FLOAT_STORE_FLAG_VALUE
2779 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2780 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2781 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2786 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2790 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2791 XEXP (x, 1), XEXP (x, 2));
2796 x = temp, code = GET_CODE (temp);
2798 /* First see if we can apply the inverse distributive law. */
2799 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2801 x = apply_distributive_law (x);
2802 code = GET_CODE (x);
2805 /* If CODE is an associative operation not otherwise handled, see if we
2806 can associate some operands. This can win if they are constants or
2807 if they are logically related (i.e. (a & b) & a. */
2808 if ((code == PLUS || code == MINUS
2809 || code == MULT || code == AND || code == IOR || code == XOR
2810 || code == DIV || code == UDIV
2811 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2812 && GET_MODE_CLASS (mode) == MODE_INT)
2814 if (GET_CODE (XEXP (x, 0)) == code)
2816 rtx other = XEXP (XEXP (x, 0), 0);
2817 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2818 rtx inner_op1 = XEXP (x, 1);
2821 /* Make sure we pass the constant operand if any as the second
2822 one if this is a commutative operation. */
2823 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2825 rtx tem = inner_op0;
2826 inner_op0 = inner_op1;
2829 inner = simplify_binary_operation (code == MINUS ? PLUS
2830 : code == DIV ? MULT
2831 : code == UDIV ? MULT
2833 mode, inner_op0, inner_op1);
2835 /* For commutative operations, try the other pair if that one
2837 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2839 other = XEXP (XEXP (x, 0), 1);
2840 inner = simplify_binary_operation (code, mode,
2841 XEXP (XEXP (x, 0), 0),
2847 x = gen_binary (code, mode, other, inner);
2854 /* A little bit of algebraic simplification here. */
2858 /* Ensure that our address has any ASHIFTs converted to MULT in case
2859 address-recognizing predicates are called later. */
2860 temp = make_compound_operation (XEXP (x, 0), MEM);
2861 SUBST (XEXP (x, 0), temp);
2865 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2866 is paradoxical. If we can't do that safely, then it becomes
2867 something nonsensical so that this combination won't take place. */
2869 if (GET_CODE (SUBREG_REG (x)) == MEM
2870 && (GET_MODE_SIZE (mode)
2871 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2873 rtx inner = SUBREG_REG (x);
2874 int endian_offset = 0;
2875 /* Don't change the mode of the MEM
2876 if that would change the meaning of the address. */
2877 if (MEM_VOLATILE_P (SUBREG_REG (x))
2878 || mode_dependent_address_p (XEXP (inner, 0)))
2879 return gen_rtx (CLOBBER, mode, const0_rtx);
2881 #if BYTES_BIG_ENDIAN
2882 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2883 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2884 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2885 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2887 /* Note if the plus_constant doesn't make a valid address
2888 then this combination won't be accepted. */
2889 x = gen_rtx (MEM, mode,
2890 plus_constant (XEXP (inner, 0),
2891 (SUBREG_WORD (x) * UNITS_PER_WORD
2893 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2894 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2895 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2899 /* If we are in a SET_DEST, these other cases can't apply. */
2903 /* Changing mode twice with SUBREG => just change it once,
2904 or not at all if changing back to starting mode. */
2905 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2907 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2908 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2909 return SUBREG_REG (SUBREG_REG (x));
2911 SUBST_INT (SUBREG_WORD (x),
2912 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2913 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2916 /* SUBREG of a hard register => just change the register number
2917 and/or mode. If the hard register is not valid in that mode,
2918 suppress this combination. If the hard register is the stack,
2919 frame, or argument pointer, leave this as a SUBREG. */
2921 if (GET_CODE (SUBREG_REG (x)) == REG
2922 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
2923 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
2924 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2925 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
2927 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
2929 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2931 return gen_rtx (REG, mode,
2932 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2934 return gen_rtx (CLOBBER, mode, const0_rtx);
2937 /* For a constant, try to pick up the part we want. Handle a full
2938 word and low-order part. Only do this if we are narrowing
2939 the constant; if it is being widened, we have no idea what
2940 the extra bits will have been set to. */
2942 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2943 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2944 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2945 && GET_MODE_CLASS (mode) == MODE_INT)
2947 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2953 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2954 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2955 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2957 /* If we are narrowing the object, we need to see if we can simplify
2958 the expression for the object knowing that we only need the
2961 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2962 && subreg_lowpart_p (x))
2963 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
2968 /* (not (plus X -1)) can become (neg X). */
2969 if (GET_CODE (XEXP (x, 0)) == PLUS
2970 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2972 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2976 /* Similarly, (not (neg X)) is (plus X -1). */
2977 if (GET_CODE (XEXP (x, 0)) == NEG)
2979 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2983 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
2984 if (GET_CODE (XEXP (x, 0)) == XOR
2985 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2986 && (temp = simplify_unary_operation (NOT, mode,
2987 XEXP (XEXP (x, 0), 1),
2990 SUBST (XEXP (XEXP (x, 0), 1), temp);
2994 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2995 other than 1, but that is not valid. We could do a similar
2996 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2997 but this doesn't seem common enough to bother with. */
2998 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2999 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3001 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3002 XEXP (XEXP (x, 0), 1));
3006 if (GET_CODE (XEXP (x, 0)) == SUBREG
3007 && subreg_lowpart_p (XEXP (x, 0))
3008 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3009 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3010 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3011 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3013 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3015 x = gen_rtx (ROTATE, inner_mode,
3016 gen_unary (NOT, inner_mode, const1_rtx),
3017 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3018 x = gen_lowpart_for_combine (mode, x);
3022 #if STORE_FLAG_VALUE == -1
3023 /* (not (comparison foo bar)) can be done by reversing the comparison
3025 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3026 && reversible_comparison_p (XEXP (x, 0)))
3027 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3028 mode, XEXP (XEXP (x, 0), 0),
3029 XEXP (XEXP (x, 0), 1));
3032 /* Apply De Morgan's laws to reduce number of patterns for machines
3033 with negating logical insns (and-not, nand, etc.). If result has
3034 only one NOT, put it first, since that is how the patterns are
3037 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3039 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3041 if (GET_CODE (in1) == NOT)
3042 in1 = XEXP (in1, 0);
3044 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3046 if (GET_CODE (in2) == NOT)
3047 in2 = XEXP (in2, 0);
3048 else if (GET_CODE (in2) == CONST_INT
3049 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3050 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3052 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3054 if (GET_CODE (in2) == NOT)
3057 in2 = in1; in1 = tem;
3060 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3067 /* (neg (plus X 1)) can become (not X). */
3068 if (GET_CODE (XEXP (x, 0)) == PLUS
3069 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3071 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3075 /* Similarly, (neg (not X)) is (plus X 1). */
3076 if (GET_CODE (XEXP (x, 0)) == NOT)
3078 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3082 /* (neg (minus X Y)) can become (minus Y X). */
3083 if (GET_CODE (XEXP (x, 0)) == MINUS
3084 && (GET_MODE_CLASS (mode) != MODE_FLOAT
3085 /* x-y != -(y-x) with IEEE floating point. */
3086 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3088 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3089 XEXP (XEXP (x, 0), 0));
3093 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3094 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3095 && significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3097 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3101 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3102 if we can then eliminate the NEG (e.g.,
3103 if the operand is a constant). */
3105 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3107 temp = simplify_unary_operation (NEG, mode,
3108 XEXP (XEXP (x, 0), 0), mode);
3111 SUBST (XEXP (XEXP (x, 0), 0), temp);
3116 temp = expand_compound_operation (XEXP (x, 0));
3118 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3119 replaced by (lshiftrt X C). This will convert
3120 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3122 if (GET_CODE (temp) == ASHIFTRT
3123 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3124 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3126 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3127 INTVAL (XEXP (temp, 1)));
3131 /* If X has only a single bit significant, say, bit I, convert
3132 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3133 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3134 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3135 or a SUBREG of one since we'd be making the expression more
3136 complex if it was just a register. */
3138 if (GET_CODE (temp) != REG
3139 && ! (GET_CODE (temp) == SUBREG
3140 && GET_CODE (SUBREG_REG (temp)) == REG)
3141 && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
3143 rtx temp1 = simplify_shift_const
3144 (NULL_RTX, ASHIFTRT, mode,
3145 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3146 GET_MODE_BITSIZE (mode) - 1 - i),
3147 GET_MODE_BITSIZE (mode) - 1 - i);
3149 /* If all we did was surround TEMP with the two shifts, we
3150 haven't improved anything, so don't use it. Otherwise,
3151 we are better off with TEMP1. */
3152 if (GET_CODE (temp1) != ASHIFTRT
3153 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3154 || XEXP (XEXP (temp1, 0), 0) != temp)
3162 case FLOAT_TRUNCATE:
3163 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3164 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3165 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3166 return XEXP (XEXP (x, 0), 0);
3171 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3172 using cc0, in which case we want to leave it as a COMPARE
3173 so we can distinguish it from a register-register-copy. */
3174 if (XEXP (x, 1) == const0_rtx)
3177 /* In IEEE floating point, x-0 is not the same as x. */
3178 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3179 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3180 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3186 /* (const (const X)) can become (const X). Do it this way rather than
3187 returning the inner CONST since CONST can be shared with a
3189 if (GET_CODE (XEXP (x, 0)) == CONST)
3190 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3195 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3196 can add in an offset. find_split_point will split this address up
3197 again if it doesn't match. */
3198 if (GET_CODE (XEXP (x, 0)) == HIGH
3199 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3205 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3206 outermost. That's because that's the way indexed addresses are
3207 supposed to appear. This code used to check many more cases, but
3208 they are now checked elsewhere. */
3209 if (GET_CODE (XEXP (x, 0)) == PLUS
3210 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3211 return gen_binary (PLUS, mode,
3212 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3214 XEXP (XEXP (x, 0), 1));
3216 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3217 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3218 bit-field and can be replaced by either a sign_extend or a
3219 sign_extract. The `and' may be a zero_extend. */
3220 if (GET_CODE (XEXP (x, 0)) == XOR
3221 && GET_CODE (XEXP (x, 1)) == CONST_INT
3222 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3223 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3224 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3225 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3226 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3227 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3228 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3229 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3230 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3231 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3234 x = simplify_shift_const
3235 (NULL_RTX, ASHIFTRT, mode,
3236 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3237 XEXP (XEXP (XEXP (x, 0), 0), 0),
3238 GET_MODE_BITSIZE (mode) - (i + 1)),
3239 GET_MODE_BITSIZE (mode) - (i + 1));
3243 /* If only the low-order bit of X is significant, (plus x -1)
3244 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3245 the bitsize of the mode - 1. This allows simplification of
3246 "a = (b & 8) == 0;" */
3247 if (XEXP (x, 1) == constm1_rtx
3248 && GET_CODE (XEXP (x, 0)) != REG
3249 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3250 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3251 && significant_bits (XEXP (x, 0), mode) == 1)
3253 x = simplify_shift_const
3254 (NULL_RTX, ASHIFTRT, mode,
3255 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3256 gen_rtx_combine (XOR, mode,
3257 XEXP (x, 0), const1_rtx),
3258 GET_MODE_BITSIZE (mode) - 1),
3259 GET_MODE_BITSIZE (mode) - 1);
3263 /* If we are adding two things that have no bits in common, convert
3264 the addition into an IOR. This will often be further simplified,
3265 for example in cases like ((a & 1) + (a & 2)), which can
3268 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3269 && (significant_bits (XEXP (x, 0), mode)
3270 & significant_bits (XEXP (x, 1), mode)) == 0)
3272 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3278 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3279 (and <foo> (const_int pow2-1)) */
3280 if (GET_CODE (XEXP (x, 1)) == AND
3281 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3282 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3283 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3285 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3286 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3292 /* If we have (mult (plus A B) C), apply the distributive law and then
3293 the inverse distributive law to see if things simplify. This
3294 occurs mostly in addresses, often when unrolling loops. */
3296 if (GET_CODE (XEXP (x, 0)) == PLUS)
3298 x = apply_distributive_law
3299 (gen_binary (PLUS, mode,
3300 gen_binary (MULT, mode,
3301 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3302 gen_binary (MULT, mode,
3303 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3305 if (GET_CODE (x) != MULT)
3309 /* If this is multiplication by a power of two and its first operand is
3310 a shift, treat the multiply as a shift to allow the shifts to
3311 possibly combine. */
3312 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3313 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3314 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3315 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3316 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3317 || GET_CODE (XEXP (x, 0)) == ROTATE
3318 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3320 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3324 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3325 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3326 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3327 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3328 XEXP (XEXP (x, 0), 1));
3332 /* If this is a divide by a power of two, treat it as a shift if
3333 its first operand is a shift. */
3334 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3335 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3336 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3337 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3338 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3339 || GET_CODE (XEXP (x, 0)) == ROTATE
3340 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3342 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3348 case GT: case GTU: case GE: case GEU:
3349 case LT: case LTU: case LE: case LEU:
3350 /* If the first operand is a condition code, we can't do anything
3352 if (GET_CODE (XEXP (x, 0)) == COMPARE
3353 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3355 && XEXP (x, 0) != cc0_rtx
3359 rtx op0 = XEXP (x, 0);
3360 rtx op1 = XEXP (x, 1);
3361 enum rtx_code new_code;
3363 if (GET_CODE (op0) == COMPARE)
3364 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3366 /* Simplify our comparison, if possible. */
3367 new_code = simplify_comparison (code, &op0, &op1);
3369 #if STORE_FLAG_VALUE == 1
3370 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3371 if only the low-order bit is significant in X (such as when
3372 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3374 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3375 && op1 == const0_rtx
3376 && significant_bits (op0, GET_MODE (op0)) == 1)
3377 return gen_lowpart_for_combine (mode, op0);
3378 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3379 && op1 == const0_rtx
3380 && significant_bits (op0, GET_MODE (op0)) == 1)
3381 return gen_rtx_combine (XOR, mode,
3382 gen_lowpart_for_combine (mode, op0),
3386 #if STORE_FLAG_VALUE == -1
3387 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3388 to (neg x) if only the low-order bit of X is significant.
3389 This converts (ne (zero_extract X 1 Y) 0) to
3390 (sign_extract X 1 Y). */
3391 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3392 && op1 == const0_rtx
3393 && significant_bits (op0, GET_MODE (op0)) == 1)
3395 x = gen_rtx_combine (NEG, mode,
3396 gen_lowpart_for_combine (mode, op0));
3401 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3402 one significant bit, we can convert (ne x 0) to (ashift x c)
3403 where C puts the bit in the sign bit. Remove any AND with
3404 STORE_FLAG_VALUE when we are done, since we are only going to
3405 test the sign bit. */
3406 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3407 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3408 && (STORE_FLAG_VALUE
3409 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3410 && op1 == const0_rtx
3411 && mode == GET_MODE (op0)
3412 && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3414 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, op0,
3415 GET_MODE_BITSIZE (mode) - 1 - i);
3416 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3422 /* If the code changed, return a whole new comparison. */
3423 if (new_code != code)
3424 return gen_rtx_combine (new_code, mode, op0, op1);
3426 /* Otherwise, keep this operation, but maybe change its operands.
3427 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3428 SUBST (XEXP (x, 0), op0);
3429 SUBST (XEXP (x, 1), op1);
3434 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3435 used in it is being compared against certain values. Get the
3436 true and false comparisons and see if that says anything about the
3437 value of each arm. */
3439 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3440 && reversible_comparison_p (XEXP (x, 0))
3441 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3444 rtx from = XEXP (XEXP (x, 0), 0);
3445 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3446 enum rtx_code false_code = reverse_condition (true_code);
3447 rtx true_val = XEXP (XEXP (x, 0), 1);
3448 rtx false_val = true_val;
3449 rtx true_arm = XEXP (x, 1);
3450 rtx false_arm = XEXP (x, 2);
3453 /* If FALSE_CODE is EQ, swap the codes and arms. */
3455 if (false_code == EQ)
3457 swapped = 1, true_code = EQ, false_code = NE;
3458 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3461 /* If we are comparing against zero and the expression being tested
3462 has only a single significant bit, that is its value when it is
3463 not equal to zero. Similarly if it is known to be -1 or 0. */
3465 if (true_code == EQ && true_val == const0_rtx
3466 && exact_log2 (sig = significant_bits (from,
3467 GET_MODE (from))) >= 0)
3468 false_code = EQ, false_val = GEN_INT (sig);
3469 else if (true_code == EQ && true_val == const0_rtx
3470 && (num_sign_bit_copies (from, GET_MODE (from))
3471 == GET_MODE_BITSIZE (GET_MODE (from))))
3472 false_code = EQ, false_val = constm1_rtx;
3474 /* Now simplify an arm if we know the value of the register
3475 in the branch and it is used in the arm. Be carefull due to
3476 the potential of locally-shared RTL. */
3478 if (reg_mentioned_p (from, true_arm))
3479 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3481 pc_rtx, pc_rtx, 0, 0);
3482 if (reg_mentioned_p (from, false_arm))
3483 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3485 pc_rtx, pc_rtx, 0, 0);
3487 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3488 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3491 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3492 reversed, do so to avoid needing two sets of patterns for
3493 subtract-and-branch insns. Similarly if we have a constant in that
3494 position or if the third operand is the same as the first operand
3495 of the comparison. */
3497 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3498 && reversible_comparison_p (XEXP (x, 0))
3499 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3500 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3503 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3504 GET_MODE (XEXP (x, 0)),
3505 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3508 SUBST (XEXP (x, 1), XEXP (x, 2));
3509 SUBST (XEXP (x, 2), temp);
3512 /* If the two arms are identical, we don't need the comparison. */
3514 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3515 && ! side_effects_p (XEXP (x, 0)))
3518 /* Look for cases where we have (abs x) or (neg (abs X)). */
3520 if (GET_MODE_CLASS (mode) == MODE_INT
3521 && GET_CODE (XEXP (x, 2)) == NEG
3522 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3523 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3524 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3525 && ! side_effects_p (XEXP (x, 1)))
3526 switch (GET_CODE (XEXP (x, 0)))
3530 x = gen_unary (ABS, mode, XEXP (x, 1));
3534 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3538 /* Look for MIN or MAX. */
3540 if (GET_MODE_CLASS (mode) == MODE_INT
3541 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3542 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3543 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3544 && ! side_effects_p (XEXP (x, 0)))
3545 switch (GET_CODE (XEXP (x, 0)))
3549 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3553 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3557 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3561 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3565 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3566 A is known to be either 0 or 1, and OP is an identity when its
3567 second operand is zero, this can be done as (OP X (mult A C)).
3568 Similarly if A is known to be 0 or -1 and also similarly if we have
3569 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3570 we don't destroy it). */
3572 if (mode != VOIDmode
3573 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3574 && XEXP (XEXP (x, 0), 1) == const0_rtx
3575 && (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3576 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3577 == GET_MODE_BITSIZE (mode))))
3579 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3580 ? XEXP (x, 1) : XEXP (x, 2));
3581 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3582 rtx dir = (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3583 ? const1_rtx : constm1_rtx);
3585 enum machine_mode m = mode;
3586 enum rtx_code op, extend_op = 0;
3588 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3589 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3590 || GET_CODE (nz) == ASHIFT
3591 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3592 && rtx_equal_p (XEXP (nz, 0), z))
3593 c = XEXP (nz, 1), op = GET_CODE (nz);
3594 else if (GET_CODE (nz) == SIGN_EXTEND
3595 && (GET_CODE (XEXP (nz, 0)) == PLUS
3596 || GET_CODE (XEXP (nz, 0)) == MINUS
3597 || GET_CODE (XEXP (nz, 0)) == IOR
3598 || GET_CODE (XEXP (nz, 0)) == XOR
3599 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3600 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3601 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3602 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3603 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3604 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3605 && (num_sign_bit_copies (z, GET_MODE (z))
3606 >= (GET_MODE_BITSIZE (mode)
3607 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3609 c = XEXP (XEXP (nz, 0), 1);
3610 op = GET_CODE (XEXP (nz, 0));
3611 extend_op = SIGN_EXTEND;
3612 m = GET_MODE (XEXP (nz, 0));
3614 else if (GET_CODE (nz) == ZERO_EXTEND
3615 && (GET_CODE (XEXP (nz, 0)) == PLUS
3616 || GET_CODE (XEXP (nz, 0)) == MINUS
3617 || GET_CODE (XEXP (nz, 0)) == IOR
3618 || GET_CODE (XEXP (nz, 0)) == XOR
3619 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3620 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3621 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3622 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3623 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3624 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3625 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3626 && ((significant_bits (z, GET_MODE (z))
3627 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3630 c = XEXP (XEXP (nz, 0), 1);
3631 op = GET_CODE (XEXP (nz, 0));
3632 extend_op = ZERO_EXTEND;
3633 m = GET_MODE (XEXP (nz, 0));
3636 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3639 = gen_binary (MULT, m,
3640 gen_lowpart_for_combine (m,
3641 XEXP (XEXP (x, 0), 0)),
3642 gen_binary (MULT, m, c, dir));
3644 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3647 temp = gen_unary (extend_op, mode, temp);
3658 /* If we are processing SET_DEST, we are done. */
3662 x = expand_compound_operation (x);
3663 if (GET_CODE (x) != code)
3668 /* (set (pc) (return)) gets written as (return). */
3669 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3672 /* Convert this into a field assignment operation, if possible. */
3673 x = make_field_assignment (x);
3675 /* If we are setting CC0 or if the source is a COMPARE, look for the
3676 use of the comparison result and try to simplify it unless we already
3677 have used undobuf.other_insn. */
3678 if ((GET_CODE (SET_SRC (x)) == COMPARE
3680 || SET_DEST (x) == cc0_rtx
3683 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3685 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3686 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3687 && XEXP (*cc_use, 0) == SET_DEST (x))
3689 enum rtx_code old_code = GET_CODE (*cc_use);
3690 enum rtx_code new_code;
3692 int other_changed = 0;
3693 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3695 if (GET_CODE (SET_SRC (x)) == COMPARE)
3696 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3698 op0 = SET_SRC (x), op1 = const0_rtx;
3700 /* Simplify our comparison, if possible. */
3701 new_code = simplify_comparison (old_code, &op0, &op1);
3703 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3704 /* If this machine has CC modes other than CCmode, check to see
3705 if we need to use a different CC mode here. */
3706 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3708 /* If the mode changed, we have to change SET_DEST, the mode
3709 in the compare, and the mode in the place SET_DEST is used.
3710 If SET_DEST is a hard register, just build new versions with
3711 the proper mode. If it is a pseudo, we lose unless it is only
3712 time we set the pseudo, in which case we can safely change
3714 if (compare_mode != GET_MODE (SET_DEST (x)))
3716 int regno = REGNO (SET_DEST (x));
3717 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3719 if (regno < FIRST_PSEUDO_REGISTER
3720 || (reg_n_sets[regno] == 1
3721 && ! REG_USERVAR_P (SET_DEST (x))))
3723 if (regno >= FIRST_PSEUDO_REGISTER)
3724 SUBST (regno_reg_rtx[regno], new_dest);
3726 SUBST (SET_DEST (x), new_dest);
3727 SUBST (XEXP (*cc_use, 0), new_dest);
3733 /* If the code changed, we have to build a new comparison
3734 in undobuf.other_insn. */
3735 if (new_code != old_code)
3739 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3740 SET_DEST (x), const0_rtx));
3742 /* If the only change we made was to change an EQ into an
3743 NE or vice versa, OP0 has only one significant bit,
3744 and OP1 is zero, check if changing the user of the condition
3745 code will produce a valid insn. If it won't, we can keep
3746 the original code in that insn by surrounding our operation
3749 if (((old_code == NE && new_code == EQ)
3750 || (old_code == EQ && new_code == NE))
3751 && ! other_changed && op1 == const0_rtx
3752 && (GET_MODE_BITSIZE (GET_MODE (op0))
3753 <= HOST_BITS_PER_WIDE_INT)
3754 && (exact_log2 (mask = significant_bits (op0,
3758 rtx pat = PATTERN (other_insn), note = 0;
3760 if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3761 && ! check_asm_operands (pat)))
3763 PUT_CODE (*cc_use, old_code);
3766 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3775 undobuf.other_insn = other_insn;
3778 /* If we are now comparing against zero, change our source if
3779 needed. If we do not use cc0, we always have a COMPARE. */
3780 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3781 SUBST (SET_SRC (x), op0);
3785 /* Otherwise, if we didn't previously have a COMPARE in the
3786 correct mode, we need one. */
3787 if (GET_CODE (SET_SRC (x)) != COMPARE
3788 || GET_MODE (SET_SRC (x)) != compare_mode)
3789 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3793 /* Otherwise, update the COMPARE if needed. */
3794 SUBST (XEXP (SET_SRC (x), 0), op0);
3795 SUBST (XEXP (SET_SRC (x), 1), op1);
3800 /* Get SET_SRC in a form where we have placed back any
3801 compound expressions. Then do the checks below. */
3802 temp = make_compound_operation (SET_SRC (x), SET);
3803 SUBST (SET_SRC (x), temp);
3806 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3807 operation, and X being a REG or (subreg (reg)), we may be able to
3808 convert this to (set (subreg:m2 x) (op)).
3810 We can always do this if M1 is narrower than M2 because that
3811 means that we only care about the low bits of the result.
3813 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3814 and BYTES_LOADS_SIGN_EXTEND not defined), we cannot perform a
3815 narrower operation that requested since the high-order bits will
3816 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
3817 however, this transformation is safe as long as M1 and M2 have
3818 the same number of words. */
3820 if (GET_CODE (SET_SRC (x)) == SUBREG
3821 && subreg_lowpart_p (SET_SRC (x))
3822 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3823 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3825 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3826 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3827 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined (BYTE_LOADS_SIGN_EXTEND)
3828 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3829 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3831 && (GET_CODE (SET_DEST (x)) == REG
3832 || (GET_CODE (SET_DEST (x)) == SUBREG
3833 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3835 SUBST (SET_DEST (x),
3836 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
3838 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3841 #ifdef BYTE_LOADS_ZERO_EXTEND
3842 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3843 M wider than N, this would require a paradoxical subreg.
3844 Replace the subreg with a zero_extend to avoid the reload that
3845 would otherwise be required. */
3846 if (GET_CODE (SET_SRC (x)) == SUBREG
3847 && subreg_lowpart_p (SET_SRC (x))
3848 && SUBREG_WORD (SET_SRC (x)) == 0
3849 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3850 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3851 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3852 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3853 GET_MODE (SET_SRC (x)),
3854 XEXP (SET_SRC (x), 0)));
3857 #ifndef HAVE_conditional_move
3859 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
3860 and we are comparing an item known to be 0 or -1 against 0, use a
3861 logical operation instead. Check for one of the arms being an IOR
3862 of the other arm with some value. We compute three terms to be
3863 IOR'ed together. In practice, at most two will be nonzero. Then
3866 if (GET_CODE (SET_DEST (x)) != PC
3867 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
3868 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
3869 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
3870 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
3871 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
3872 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
3873 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
3874 && ! side_effects_p (SET_SRC (x)))
3876 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3877 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
3878 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3879 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
3880 rtx term1 = const0_rtx, term2, term3;
3882 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
3883 term1 = false, true = XEXP (true, 1), false = const0_rtx;
3884 else if (GET_CODE (true) == IOR
3885 && rtx_equal_p (XEXP (true, 1), false))
3886 term1 = false, true = XEXP (true, 0), false = const0_rtx;
3887 else if (GET_CODE (false) == IOR
3888 && rtx_equal_p (XEXP (false, 0), true))
3889 term1 = true, false = XEXP (false, 1), true = const0_rtx;
3890 else if (GET_CODE (false) == IOR
3891 && rtx_equal_p (XEXP (false, 1), true))
3892 term1 = true, false = XEXP (false, 0), true = const0_rtx;
3894 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3895 XEXP (XEXP (SET_SRC (x), 0), 0), true);
3896 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3897 gen_unary (NOT, GET_MODE (SET_SRC (x)),
3898 XEXP (XEXP (SET_SRC (x), 0), 0)),
3902 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3903 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3911 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3913 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3914 INTVAL (XEXP (x, 1)));
3916 /* If we have (ior (and (X C1) C2)) and the next restart would be
3917 the last, simplify this by making C1 as small as possible
3919 if (n_restarts >= 3 && GET_CODE (x) == IOR
3920 && GET_CODE (XEXP (x, 0)) == AND
3921 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3922 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3924 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3925 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
3926 & ~ INTVAL (XEXP (x, 1))));
3927 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3930 if (GET_CODE (x) != AND)
3934 /* Convert (A | B) & A to A. */
3935 if (GET_CODE (XEXP (x, 0)) == IOR
3936 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3937 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3938 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3939 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3942 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3943 insn (and may simplify more). */
3944 else if (GET_CODE (XEXP (x, 0)) == XOR
3945 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3946 && ! side_effects_p (XEXP (x, 1)))
3948 x = gen_binary (AND, mode,
3949 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3953 else if (GET_CODE (XEXP (x, 0)) == XOR
3954 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3955 && ! side_effects_p (XEXP (x, 1)))
3957 x = gen_binary (AND, mode,
3958 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3963 /* Similarly for (~ (A ^ B)) & A. */
3964 else if (GET_CODE (XEXP (x, 0)) == NOT
3965 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3966 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3967 && ! side_effects_p (XEXP (x, 1)))
3969 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3973 else if (GET_CODE (XEXP (x, 0)) == NOT
3974 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3975 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3976 && ! side_effects_p (XEXP (x, 1)))
3978 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3983 /* If we have (and A B) with A not an object but that is known to
3984 be -1 or 0, this is equivalent to the expression
3985 (if_then_else (ne A (const_int 0)) B (const_int 0))
3986 We make this conversion because it may allow further
3987 simplifications and then allow use of conditional move insns.
3988 If the machine doesn't have condition moves, code in case SET
3989 will convert the IF_THEN_ELSE back to the logical operation.
3990 We build the IF_THEN_ELSE here in case further simplification
3991 is possible (e.g., we can convert it to ABS). */
3993 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3994 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3995 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
3996 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3997 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3999 rtx op0 = XEXP (x, 0);
4000 rtx op1 = const0_rtx;
4001 enum rtx_code comp_code
4002 = simplify_comparison (NE, &op0, &op1);
4004 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4005 gen_binary (comp_code, VOIDmode, op0, op1),
4006 XEXP (x, 1), const0_rtx);
4010 /* In the following group of tests (and those in case IOR below),
4011 we start with some combination of logical operations and apply
4012 the distributive law followed by the inverse distributive law.
4013 Most of the time, this results in no change. However, if some of
4014 the operands are the same or inverses of each other, simplifications
4017 For example, (and (ior A B) (not B)) can occur as the result of
4018 expanding a bit field assignment. When we apply the distributive
4019 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4020 which then simplifies to (and (A (not B))). */
4022 /* If we have (and (ior A B) C), apply the distributive law and then
4023 the inverse distributive law to see if things simplify. */
4025 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4027 x = apply_distributive_law
4028 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4029 gen_binary (AND, mode,
4030 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4031 gen_binary (AND, mode,
4032 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4033 if (GET_CODE (x) != AND)
4037 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4039 x = apply_distributive_law
4040 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4041 gen_binary (AND, mode,
4042 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4043 gen_binary (AND, mode,
4044 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4045 if (GET_CODE (x) != AND)
4049 /* Similarly, taking advantage of the fact that
4050 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4052 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4054 x = apply_distributive_law
4055 (gen_binary (XOR, mode,
4056 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4057 XEXP (XEXP (x, 1), 0)),
4058 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4059 XEXP (XEXP (x, 1), 1))));
4060 if (GET_CODE (x) != AND)
4064 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4066 x = apply_distributive_law
4067 (gen_binary (XOR, mode,
4068 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4069 XEXP (XEXP (x, 0), 0)),
4070 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4071 XEXP (XEXP (x, 0), 1))));
4072 if (GET_CODE (x) != AND)
4078 /* (ior A C) is C if all significant bits of A are on in C. */
4079 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4080 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4081 && (significant_bits (XEXP (x, 0), mode)
4082 & ~ INTVAL (XEXP (x, 1))) == 0)
4085 /* Convert (A & B) | A to A. */
4086 if (GET_CODE (XEXP (x, 0)) == AND
4087 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4088 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4089 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4090 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4093 /* If we have (ior (and A B) C), apply the distributive law and then
4094 the inverse distributive law to see if things simplify. */
4096 if (GET_CODE (XEXP (x, 0)) == AND)
4098 x = apply_distributive_law
4099 (gen_binary (AND, mode,
4100 gen_binary (IOR, mode,
4101 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4102 gen_binary (IOR, mode,
4103 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4105 if (GET_CODE (x) != IOR)
4109 if (GET_CODE (XEXP (x, 1)) == AND)
4111 x = apply_distributive_law
4112 (gen_binary (AND, mode,
4113 gen_binary (IOR, mode,
4114 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4115 gen_binary (IOR, mode,
4116 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4118 if (GET_CODE (x) != IOR)
4122 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4123 mode size to (rotate A CX). */
4125 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4126 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4127 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4128 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4129 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4130 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4131 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4132 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4133 == GET_MODE_BITSIZE (mode)))
4137 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4138 shift_count = XEXP (XEXP (x, 0), 1);
4140 shift_count = XEXP (XEXP (x, 1), 1);
4141 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4147 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4148 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4151 int num_negated = 0;
4152 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4154 if (GET_CODE (in1) == NOT)
4155 num_negated++, in1 = XEXP (in1, 0);
4156 if (GET_CODE (in2) == NOT)
4157 num_negated++, in2 = XEXP (in2, 0);
4159 if (num_negated == 2)
4161 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4162 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4164 else if (num_negated == 1)
4166 x = gen_unary (NOT, mode,
4167 gen_binary (XOR, mode, in1, in2));
4172 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4173 correspond to a machine insn or result in further simplifications
4174 if B is a constant. */
4176 if (GET_CODE (XEXP (x, 0)) == AND
4177 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4178 && ! side_effects_p (XEXP (x, 1)))
4180 x = gen_binary (AND, mode,
4181 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4185 else if (GET_CODE (XEXP (x, 0)) == AND
4186 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4187 && ! side_effects_p (XEXP (x, 1)))
4189 x = gen_binary (AND, mode,
4190 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4196 #if STORE_FLAG_VALUE == 1
4197 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4199 if (XEXP (x, 1) == const1_rtx
4200 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4201 && reversible_comparison_p (XEXP (x, 0)))
4202 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4203 mode, XEXP (XEXP (x, 0), 0),
4204 XEXP (XEXP (x, 0), 1));
4207 /* (xor (comparison foo bar) (const_int sign-bit))
4208 when STORE_FLAG_VALUE is the sign bit. */
4209 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4210 && (STORE_FLAG_VALUE
4211 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4212 && XEXP (x, 1) == const_true_rtx
4213 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4214 && reversible_comparison_p (XEXP (x, 0)))
4215 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4216 mode, XEXP (XEXP (x, 0), 0),
4217 XEXP (XEXP (x, 0), 1));
4221 /* (abs (neg <foo>)) -> (abs <foo>) */
4222 if (GET_CODE (XEXP (x, 0)) == NEG)
4223 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4225 /* If operand is something known to be positive, ignore the ABS. */
4226 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4227 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4228 <= HOST_BITS_PER_WIDE_INT)
4229 && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4230 & ((HOST_WIDE_INT) 1
4231 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4236 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4237 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4239 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4245 /* (ffs (*_extend <X>)) = (ffs <X>) */
4246 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4247 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4248 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4252 /* (float (sign_extend <X>)) = (float <X>). */
4253 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4254 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4263 /* If this is a shift by a constant amount, simplify it. */
4264 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4266 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4267 INTVAL (XEXP (x, 1)));
4268 if (GET_CODE (x) != code)
4272 #ifdef SHIFT_COUNT_TRUNCATED
4273 else if (GET_CODE (XEXP (x, 1)) != REG)
4275 force_to_mode (XEXP (x, 1), GET_MODE (x),
4276 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4286 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4287 operations" because they can be replaced with two more basic operations.
4288 ZERO_EXTEND is also considered "compound" because it can be replaced with
4289 an AND operation, which is simpler, though only one operation.
4291 The function expand_compound_operation is called with an rtx expression
4292 and will convert it to the appropriate shifts and AND operations,
4293 simplifying at each stage.
4295 The function make_compound_operation is called to convert an expression
4296 consisting of shifts and ANDs into the equivalent compound expression.
4297 It is the inverse of this function, loosely speaking. */
4300 expand_compound_operation (x)
4308 switch (GET_CODE (x))
4313 /* We can't necessarily use a const_int for a multiword mode;
4314 it depends on implicitly extending the value.
4315 Since we don't know the right way to extend it,
4316 we can't tell whether the implicit way is right.
4318 Even for a mode that is no wider than a const_int,
4319 we can't win, because we need to sign extend one of its bits through
4320 the rest of it, and we don't know which bit. */
4321 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4324 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4327 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4328 /* If the inner object has VOIDmode (the only way this can happen
4329 is if it is a ASM_OPERANDS), we can't do anything since we don't
4330 know how much masking to do. */
4339 /* If the operand is a CLOBBER, just return it. */
4340 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4343 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4344 || GET_CODE (XEXP (x, 2)) != CONST_INT
4345 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4348 len = INTVAL (XEXP (x, 1));
4349 pos = INTVAL (XEXP (x, 2));
4351 /* If this goes outside the object being extracted, replace the object
4352 with a (use (mem ...)) construct that only combine understands
4353 and is used only for this purpose. */
4354 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4355 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4358 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4366 /* If we reach here, we want to return a pair of shifts. The inner
4367 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4368 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4369 logical depending on the value of UNSIGNEDP.
4371 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4372 converted into an AND of a shift.
4374 We must check for the case where the left shift would have a negative
4375 count. This can happen in a case like (x >> 31) & 255 on machines
4376 that can't shift by a constant. On those machines, we would first
4377 combine the shift with the AND to produce a variable-position
4378 extraction. Then the constant of 31 would be substituted in to produce
4379 a such a position. */
4381 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4382 if (modewidth >= pos - len)
4383 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4385 simplify_shift_const (NULL_RTX, ASHIFT,
4388 modewidth - pos - len),
4391 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4392 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4393 simplify_shift_const (NULL_RTX, LSHIFTRT,
4396 ((HOST_WIDE_INT) 1 << len) - 1);
4398 /* Any other cases we can't handle. */
4402 /* If we couldn't do this for some reason, return the original
4404 if (GET_CODE (tem) == CLOBBER)
4410 /* X is a SET which contains an assignment of one object into
4411 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4412 or certain SUBREGS). If possible, convert it into a series of
4415 We half-heartedly support variable positions, but do not at all
4416 support variable lengths. */
4419 expand_field_assignment (x)
4423 rtx pos; /* Always counts from low bit. */
4426 enum machine_mode compute_mode;
4428 /* Loop until we find something we can't simplify. */
4431 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4432 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4434 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4435 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4438 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4439 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4441 inner = XEXP (SET_DEST (x), 0);
4442 len = INTVAL (XEXP (SET_DEST (x), 1));
4443 pos = XEXP (SET_DEST (x), 2);
4445 /* If the position is constant and spans the width of INNER,
4446 surround INNER with a USE to indicate this. */
4447 if (GET_CODE (pos) == CONST_INT
4448 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4449 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4452 if (GET_CODE (pos) == CONST_INT)
4453 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4455 else if (GET_CODE (pos) == MINUS
4456 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4457 && (INTVAL (XEXP (pos, 1))
4458 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4459 /* If position is ADJUST - X, new position is X. */
4460 pos = XEXP (pos, 0);
4462 pos = gen_binary (MINUS, GET_MODE (pos),
4463 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4469 /* A SUBREG between two modes that occupy the same numbers of words
4470 can be done by moving the SUBREG to the source. */
4471 else if (GET_CODE (SET_DEST (x)) == SUBREG
4472 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4473 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4474 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4475 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4477 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4478 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4485 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4486 inner = SUBREG_REG (inner);
4488 compute_mode = GET_MODE (inner);
4490 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4491 if (len < HOST_BITS_PER_WIDE_INT)
4492 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4496 /* Now compute the equivalent expression. Make a copy of INNER
4497 for the SET_DEST in case it is a MEM into which we will substitute;
4498 we don't want shared RTL in that case. */
4499 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4500 gen_binary (IOR, compute_mode,
4501 gen_binary (AND, compute_mode,
4502 gen_unary (NOT, compute_mode,
4507 gen_binary (ASHIFT, compute_mode,
4508 gen_binary (AND, compute_mode,
4509 gen_lowpart_for_combine
4519 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
4520 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
4521 the starting bit position.
4523 INNER may be a USE. This will occur when we started with a bitfield
4524 that went outside the boundary of the object in memory, which is
4525 allowed on most machines. To isolate this case, we produce a USE
4526 whose mode is wide enough and surround the MEM with it. The only
4527 code that understands the USE is this routine. If it is not removed,
4528 it will cause the resulting insn not to match.
4530 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4533 IN_DEST is non-zero if this is a reference in the destination of a
4534 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4535 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4538 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4539 ZERO_EXTRACT should be built even for bits starting at bit 0.
4541 MODE is the desired mode of the result (if IN_DEST == 0). */
4544 make_extraction (mode, inner, pos, pos_rtx, len,
4545 unsignedp, in_dest, in_compare)
4546 enum machine_mode mode;
4552 int in_dest, in_compare;
4554 /* This mode describes the size of the storage area
4555 to fetch the overall value from. Within that, we
4556 ignore the POS lowest bits, etc. */
4557 enum machine_mode is_mode = GET_MODE (inner);
4558 enum machine_mode inner_mode;
4559 enum machine_mode wanted_mem_mode = byte_mode;
4560 enum machine_mode pos_mode = word_mode;
4561 enum machine_mode extraction_mode = word_mode;
4562 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4566 /* Get some information about INNER and get the innermost object. */
4567 if (GET_CODE (inner) == USE)
4568 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4569 /* We don't need to adjust the position because we set up the USE
4570 to pretend that it was a full-word object. */
4571 spans_byte = 1, inner = XEXP (inner, 0);
4572 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4574 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4575 consider just the QI as the memory to extract from.
4576 The subreg adds or removes high bits; its mode is
4577 irrelevant to the meaning of this extraction,
4578 since POS and LEN count from the lsb. */
4579 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4580 is_mode = GET_MODE (SUBREG_REG (inner));
4581 inner = SUBREG_REG (inner);
4584 inner_mode = GET_MODE (inner);
4586 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4587 pos = INTVAL (pos_rtx);
4589 /* See if this can be done without an extraction. We never can if the
4590 width of the field is not the same as that of some integer mode. For
4591 registers, we can only avoid the extraction if the position is at the
4592 low-order bit and this is either not in the destination or we have the
4593 appropriate STRICT_LOW_PART operation available.
4595 For MEM, we can avoid an extract if the field starts on an appropriate
4596 boundary and we can change the mode of the memory reference. However,
4597 we cannot directly access the MEM if we have a USE and the underlying
4598 MEM is not TMODE. This combination means that MEM was being used in a
4599 context where bits outside its mode were being referenced; that is only
4600 valid in bit-field insns. */
4602 if (tmode != BLKmode
4603 && ! (spans_byte && inner_mode != tmode)
4604 && ((pos == 0 && GET_CODE (inner) != MEM
4606 || (GET_CODE (inner) == REG
4607 && (movstrict_optab->handlers[(int) tmode].insn_code
4608 != CODE_FOR_nothing))))
4609 || (GET_CODE (inner) == MEM && pos >= 0
4611 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4612 : BITS_PER_UNIT)) == 0
4613 /* We can't do this if we are widening INNER_MODE (it
4614 may not be aligned, for one thing). */
4615 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4616 && (inner_mode == tmode
4617 || (! mode_dependent_address_p (XEXP (inner, 0))
4618 && ! MEM_VOLATILE_P (inner))))))
4620 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4621 field. If the original and current mode are the same, we need not
4622 adjust the offset. Otherwise, we do if bytes big endian.
4624 If INNER is not a MEM, get a piece consisting of the just the field
4625 of interest (in this case POS must be 0). */
4627 if (GET_CODE (inner) == MEM)
4630 /* POS counts from lsb, but make OFFSET count in memory order. */
4631 if (BYTES_BIG_ENDIAN)
4632 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4634 offset = pos / BITS_PER_UNIT;
4636 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4637 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4638 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4639 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4641 else if (GET_CODE (inner) == REG)
4642 /* We can't call gen_lowpart_for_combine here since we always want
4643 a SUBREG and it would sometimes return a new hard register. */
4644 new = gen_rtx (SUBREG, tmode, inner,
4646 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4647 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
4651 new = force_to_mode (inner, tmode, len, NULL_RTX);
4653 /* If this extraction is going into the destination of a SET,
4654 make a STRICT_LOW_PART unless we made a MEM. */
4657 return (GET_CODE (new) == MEM ? new
4658 : (GET_CODE (new) != SUBREG
4659 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4660 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4662 /* Otherwise, sign- or zero-extend unless we already are in the
4665 return (mode == tmode ? new
4666 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4670 /* Unless this is a COMPARE or we have a funny memory reference,
4671 don't do anything with zero-extending field extracts starting at
4672 the low-order bit since they are simple AND operations. */
4673 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte && unsignedp)
4676 /* Get the mode to use should INNER be a MEM, the mode for the position,
4677 and the mode for the result. */
4681 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4682 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4683 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4688 if (! in_dest && unsignedp)
4690 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4691 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4692 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4697 if (! in_dest && ! unsignedp)
4699 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4700 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4701 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4705 /* Never narrow an object, since that might not be safe. */
4707 if (mode != VOIDmode
4708 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4709 extraction_mode = mode;
4711 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4712 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4713 pos_mode = GET_MODE (pos_rtx);
4715 /* If this is not from memory or we have to change the mode of memory and
4716 cannot, the desired mode is EXTRACTION_MODE. */
4717 if (GET_CODE (inner) != MEM
4718 || (inner_mode != wanted_mem_mode
4719 && (mode_dependent_address_p (XEXP (inner, 0))
4720 || MEM_VOLATILE_P (inner))))
4721 wanted_mem_mode = extraction_mode;
4724 /* If position is constant, compute new position. Otherwise, build
4727 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4731 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4732 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4733 GET_MODE_BITSIZE (wanted_mem_mode))
4738 /* If INNER has a wider mode, make it smaller. If this is a constant
4739 extract, try to adjust the byte to point to the byte containing
4741 if (wanted_mem_mode != VOIDmode
4742 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4743 && ((GET_CODE (inner) == MEM
4744 && (inner_mode == wanted_mem_mode
4745 || (! mode_dependent_address_p (XEXP (inner, 0))
4746 && ! MEM_VOLATILE_P (inner))))))
4750 /* The computations below will be correct if the machine is big
4751 endian in both bits and bytes or little endian in bits and bytes.
4752 If it is mixed, we must adjust. */
4754 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4755 if (! spans_byte && is_mode != wanted_mem_mode)
4756 offset = (GET_MODE_SIZE (is_mode)
4757 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4760 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4761 adjust OFFSET to compensate. */
4762 #if BYTES_BIG_ENDIAN
4764 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4765 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4768 /* If this is a constant position, we can move to the desired byte. */
4771 offset += pos / BITS_PER_UNIT;
4772 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4775 if (offset != 0 || inner_mode != wanted_mem_mode)
4777 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4778 plus_constant (XEXP (inner, 0), offset));
4779 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4780 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4781 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4786 /* If INNER is not memory, we can always get it into the proper mode. */
4787 else if (GET_CODE (inner) != MEM)
4788 inner = force_to_mode (inner, extraction_mode,
4789 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4793 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4794 have to zero extend. Otherwise, we can just use a SUBREG. */
4796 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4797 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4799 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4800 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4802 /* Make POS_RTX unless we already have it and it is correct. */
4803 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4804 pos_rtx = GEN_INT (pos);
4806 /* Make the required operation. See if we can use existing rtx. */
4807 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4808 extraction_mode, inner, GEN_INT (len), pos_rtx);
4810 new = gen_lowpart_for_combine (mode, new);
4815 /* Look at the expression rooted at X. Look for expressions
4816 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4817 Form these expressions.
4819 Return the new rtx, usually just X.
4821 Also, for machines like the Vax that don't have logical shift insns,
4822 try to convert logical to arithmetic shift operations in cases where
4823 they are equivalent. This undoes the canonicalizations to logical
4824 shifts done elsewhere.
4826 We try, as much as possible, to re-use rtl expressions to save memory.
4828 IN_CODE says what kind of expression we are processing. Normally, it is
4829 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4830 being kludges), it is MEM. When processing the arguments of a comparison
4831 or a COMPARE against zero, it is COMPARE. */
4834 make_compound_operation (x, in_code)
4836 enum rtx_code in_code;
4838 enum rtx_code code = GET_CODE (x);
4839 enum machine_mode mode = GET_MODE (x);
4840 int mode_width = GET_MODE_BITSIZE (mode);
4841 enum rtx_code next_code;
4846 /* Select the code to be used in recursive calls. Once we are inside an
4847 address, we stay there. If we have a comparison, set to COMPARE,
4848 but once inside, go back to our default of SET. */
4850 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4851 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4852 && XEXP (x, 1) == const0_rtx) ? COMPARE
4853 : in_code == COMPARE ? SET : in_code);
4855 /* Process depending on the code of this operation. If NEW is set
4856 non-zero, it will be returned. */
4862 /* Convert shifts by constants into multiplications if inside
4864 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4865 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
4866 && INTVAL (XEXP (x, 1)) >= 0)
4867 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4868 GEN_INT ((HOST_WIDE_INT) 1
4869 << INTVAL (XEXP (x, 1))));
4873 /* If the second operand is not a constant, we can't do anything
4875 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4878 /* If the constant is a power of two minus one and the first operand
4879 is a logical right shift, make an extraction. */
4880 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4881 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4882 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4883 XEXP (XEXP (x, 0), 1), i, 1,
4884 0, in_code == COMPARE);
4886 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4887 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4888 && subreg_lowpart_p (XEXP (x, 0))
4889 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4890 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4891 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4892 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4893 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4894 0, in_code == COMPARE);
4897 /* If we are have (and (rotate X C) M) and C is larger than the number
4898 of bits in M, this is an extraction. */
4900 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4901 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4902 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4903 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4904 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4905 (GET_MODE_BITSIZE (mode)
4906 - INTVAL (XEXP (XEXP (x, 0), 1))),
4907 NULL_RTX, i, 1, 0, in_code == COMPARE);
4909 /* On machines without logical shifts, if the operand of the AND is
4910 a logical shift and our mask turns off all the propagated sign
4911 bits, we can replace the logical shift with an arithmetic shift. */
4912 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4913 && (lshr_optab->handlers[(int) mode].insn_code
4914 == CODE_FOR_nothing)
4915 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4916 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4917 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4918 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
4919 && mode_width <= HOST_BITS_PER_WIDE_INT)
4921 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
4923 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4924 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4926 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4927 XEXP (XEXP (x, 0), 1)));
4930 /* If the constant is one less than a power of two, this might be
4931 representable by an extraction even if no shift is present.
4932 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4933 we are in a COMPARE. */
4934 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4935 new = make_extraction (mode, XEXP (x, 0), 0, NULL_RTX, i, 1,
4936 0, in_code == COMPARE);
4938 /* If we are in a comparison and this is an AND with a power of two,
4939 convert this into the appropriate bit extract. */
4940 else if (in_code == COMPARE
4941 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4942 new = make_extraction (mode, XEXP (x, 0), i, NULL_RTX, 1, 1, 0, 1);
4947 /* If the sign bit is known to be zero, replace this with an
4948 arithmetic shift. */
4949 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
4950 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4951 && mode_width <= HOST_BITS_PER_WIDE_INT
4952 && (significant_bits (XEXP (x, 0), mode)
4953 & (1 << (mode_width - 1))) == 0)
4955 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4959 /* ... fall through ... */
4962 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4963 this is a SIGN_EXTRACT. */
4964 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4965 && GET_CODE (XEXP (x, 0)) == ASHIFT
4966 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4967 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4968 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4969 (INTVAL (XEXP (x, 1))
4970 - INTVAL (XEXP (XEXP (x, 0), 1))),
4971 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
4972 code == LSHIFTRT, 0, in_code == COMPARE);
4974 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
4975 cases, we are better off returning a SIGN_EXTEND of the operation. */
4977 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4978 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
4979 || GET_CODE (XEXP (x, 0)) == XOR
4980 || GET_CODE (XEXP (x, 0)) == PLUS)
4981 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
4982 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4983 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4984 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
4985 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4986 && (INTVAL (XEXP (XEXP (x, 0), 1))
4987 & (((HOST_WIDE_INT) 1
4988 << INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) - 1)) == 0)
4990 HOST_WIDE_INT newop1
4991 = (INTVAL (XEXP (XEXP (x, 0), 1))
4992 >> INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
4994 new = make_extraction (mode,
4995 gen_binary (GET_CODE (XEXP (x, 0)), mode,
4996 XEXP (XEXP (XEXP (x, 0), 0), 0),
4998 (INTVAL (XEXP (x, 1))
4999 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5000 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5001 code == LSHIFTRT, 0, in_code == COMPARE);
5004 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5005 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5006 && GET_CODE (XEXP (x, 0)) == NEG
5007 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5008 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5009 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5010 new = make_extraction (mode,
5011 gen_unary (GET_CODE (XEXP (x, 0)), mode,
5012 XEXP (XEXP (XEXP (x, 0), 0), 0)),
5013 (INTVAL (XEXP (x, 1))
5014 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5015 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5016 code == LSHIFTRT, 0, in_code == COMPARE);
5022 x = gen_lowpart_for_combine (mode, new);
5023 code = GET_CODE (x);
5026 /* Now recursively process each operand of this operation. */
5027 fmt = GET_RTX_FORMAT (code);
5028 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5031 new = make_compound_operation (XEXP (x, i), next_code);
5032 SUBST (XEXP (x, i), new);
5038 /* Given M see if it is a value that would select a field of bits
5039 within an item, but not the entire word. Return -1 if not.
5040 Otherwise, return the starting position of the field, where 0 is the
5043 *PLEN is set to the length of the field. */
5046 get_pos_from_mask (m, plen)
5047 unsigned HOST_WIDE_INT m;
5050 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5051 int pos = exact_log2 (m & - m);
5056 /* Now shift off the low-order zero bits and see if we have a power of
5058 *plen = exact_log2 ((m >> pos) + 1);
5066 /* Rewrite X so that it is an expression in MODE. We only care about the
5067 low-order BITS bits so we can ignore AND operations that just clear
5070 Also, if REG is non-zero and X is a register equal in value to REG,
5071 replace X with REG. */
5074 force_to_mode (x, mode, bits, reg)
5076 enum machine_mode mode;
5080 enum rtx_code code = GET_CODE (x);
5081 enum machine_mode op_mode = mode;
5083 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5084 just get X in the proper mode. */
5086 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5087 || bits > GET_MODE_BITSIZE (mode))
5088 return gen_lowpart_for_combine (mode, x);
5096 x = expand_compound_operation (x);
5097 if (GET_CODE (x) != code)
5098 return force_to_mode (x, mode, bits, reg);
5102 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5103 || rtx_equal_p (reg, get_last_value (x))))
5108 if (bits < HOST_BITS_PER_WIDE_INT)
5109 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5113 /* Ignore low-order SUBREGs. */
5114 if (subreg_lowpart_p (x))
5115 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5119 /* If this is an AND with a constant. Otherwise, we fall through to
5120 do the general binary case. */
5122 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5124 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5125 int len = exact_log2 (mask + 1);
5126 rtx op = XEXP (x, 0);
5128 /* If this is masking some low-order bits, we may be able to
5129 impose a stricter constraint on what bits of the operand are
5132 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5135 if (bits < HOST_BITS_PER_WIDE_INT)
5136 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5138 /* If we have no AND in MODE, use the original mode for the
5141 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5142 op_mode = GET_MODE (x);
5144 x = simplify_and_const_int (x, op_mode, op, mask);
5146 /* If X is still an AND, see if it is an AND with a mask that
5147 is just some low-order bits. If so, and it is BITS wide (it
5148 can't be wider), we don't need it. */
5150 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5151 && bits < HOST_BITS_PER_WIDE_INT
5152 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5158 /* ... fall through ... */
5165 /* For most binary operations, just propagate into the operation and
5166 change the mode if we have an operation of that mode. */
5169 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5171 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5172 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5173 == CODE_FOR_nothing))
5175 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5177 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5178 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5179 == CODE_FOR_nothing)))
5180 op_mode = GET_MODE (x);
5182 x = gen_binary (code, op_mode,
5183 gen_lowpart_for_combine (op_mode,
5184 force_to_mode (XEXP (x, 0),
5187 gen_lowpart_for_combine (op_mode,
5188 force_to_mode (XEXP (x, 1),
5195 /* For left shifts, do the same, but just for the first operand.
5196 If the shift count is a constant, we need even fewer bits of the
5199 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5200 bits -= INTVAL (XEXP (x, 1));
5203 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5204 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5205 == CODE_FOR_nothing)))
5206 op_mode = GET_MODE (x);
5208 x = gen_binary (code, op_mode,
5209 gen_lowpart_for_combine (op_mode,
5210 force_to_mode (XEXP (x, 0),
5217 /* Here we can only do something if the shift count is a constant and
5218 the count plus BITS is no larger than the width of MODE, we can do
5219 the shift in MODE. */
5221 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5222 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5224 rtx inner = force_to_mode (XEXP (x, 0), mode,
5225 bits + INTVAL (XEXP (x, 1)), reg);
5227 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5228 op_mode = GET_MODE (x);
5230 x = gen_binary (LSHIFTRT, op_mode,
5231 gen_lowpart_for_combine (op_mode, inner),
5237 /* If this is a sign-extension operation that just affects bits
5238 we don't care about, remove it. */
5240 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5241 && INTVAL (XEXP (x, 1)) >= 0
5242 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5243 && GET_CODE (XEXP (x, 0)) == ASHIFT
5244 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5245 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5246 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5252 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5253 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5254 == CODE_FOR_nothing)))
5255 op_mode = GET_MODE (x);
5257 /* Handle these similarly to the way we handle most binary operations. */
5258 x = gen_unary (code, op_mode,
5259 gen_lowpart_for_combine (op_mode,
5260 force_to_mode (XEXP (x, 0), mode,
5265 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5266 written in a narrower mode. We play it safe and do not do so. */
5269 gen_lowpart_for_combine (GET_MODE (x),
5270 force_to_mode (XEXP (x, 1), mode,
5273 gen_lowpart_for_combine (GET_MODE (x),
5274 force_to_mode (XEXP (x, 2), mode,
5279 /* Ensure we return a value of the proper mode. */
5280 return gen_lowpart_for_combine (mode, x);
5283 /* Return the value of expression X given the fact that condition COND
5284 is known to be true when applied to REG as its first operand and VAL
5285 as its second. X is known to not be shared and so can be modified in
5288 We only handle the simplest cases, and specifically those cases that
5289 arise with IF_THEN_ELSE expressions. */
5292 known_cond (x, cond, reg, val)
5297 enum rtx_code code = GET_CODE (x);
5302 if (side_effects_p (x))
5305 if (cond == EQ && rtx_equal_p (x, reg))
5308 /* If X is (abs REG) and we know something about REG's relationship
5309 with zero, we may be able to simplify this. */
5311 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5314 case GE: case GT: case EQ:
5317 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5320 /* The only other cases we handle are MIN, MAX, and comparisons if the
5321 operands are the same as REG and VAL. */
5323 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5325 if (rtx_equal_p (XEXP (x, 0), val))
5326 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5328 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5330 if (GET_RTX_CLASS (code) == '<')
5331 return (comparison_dominates_p (cond, code) ? const_true_rtx
5332 : (comparison_dominates_p (cond,
5333 reverse_condition (code))
5336 else if (code == SMAX || code == SMIN
5337 || code == UMIN || code == UMAX)
5339 int unsignedp = (code == UMIN || code == UMAX);
5341 if (code == SMAX || code == UMAX)
5342 cond = reverse_condition (cond);
5347 return unsignedp ? x : XEXP (x, 1);
5349 return unsignedp ? x : XEXP (x, 0);
5351 return unsignedp ? XEXP (x, 1) : x;
5353 return unsignedp ? XEXP (x, 0) : x;
5359 fmt = GET_RTX_FORMAT (code);
5360 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5363 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5364 else if (fmt[i] == 'E')
5365 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5366 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5373 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5374 Return that assignment if so.
5376 We only handle the most common cases. */
5379 make_field_assignment (x)
5382 rtx dest = SET_DEST (x);
5383 rtx src = SET_SRC (x);
5389 enum machine_mode mode;
5391 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5392 a clear of a one-bit field. We will have changed it to
5393 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5396 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5397 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5398 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5399 && (rtx_equal_p (dest, XEXP (src, 1))
5400 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5401 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5403 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5405 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5408 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5409 && subreg_lowpart_p (XEXP (src, 0))
5410 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5411 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5412 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5413 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5414 && (rtx_equal_p (dest, XEXP (src, 1))
5415 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5416 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5418 assign = make_extraction (VOIDmode, dest, -1,
5419 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5421 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5424 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5426 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5427 && XEXP (XEXP (src, 0), 0) == const1_rtx
5428 && (rtx_equal_p (dest, XEXP (src, 1))
5429 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5430 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5432 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5434 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5437 /* The other case we handle is assignments into a constant-position
5438 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5439 a mask that has all one bits except for a group of zero bits and
5440 OTHER is known to have zeros where C1 has ones, this is such an
5441 assignment. Compute the position and length from C1. Shift OTHER
5442 to the appropriate position, force it to the required mode, and
5443 make the extraction. Check for the AND in both operands. */
5445 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5446 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5447 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5448 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5449 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5450 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5451 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5452 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5453 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5454 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5455 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5457 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5461 pos = get_pos_from_mask (~c1, &len);
5462 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5463 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5464 && (c1 & significant_bits (other, GET_MODE (other))) != 0))
5467 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5469 /* The mode to use for the source is the mode of the assignment, or of
5470 what is inside a possible STRICT_LOW_PART. */
5471 mode = (GET_CODE (assign) == STRICT_LOW_PART
5472 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5474 /* Shift OTHER right POS places and make it the source, restricting it
5475 to the proper length and mode. */
5477 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5478 GET_MODE (src), other, pos),
5481 return gen_rtx_combine (SET, VOIDmode, assign, src);
5484 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5488 apply_distributive_law (x)
5491 enum rtx_code code = GET_CODE (x);
5492 rtx lhs, rhs, other;
5494 enum rtx_code inner_code;
5496 /* The outer operation can only be one of the following: */
5497 if (code != IOR && code != AND && code != XOR
5498 && code != PLUS && code != MINUS)
5501 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5503 /* If either operand is a primitive we can't do anything, so get out fast. */
5504 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5505 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5508 lhs = expand_compound_operation (lhs);
5509 rhs = expand_compound_operation (rhs);
5510 inner_code = GET_CODE (lhs);
5511 if (inner_code != GET_CODE (rhs))
5514 /* See if the inner and outer operations distribute. */
5521 /* These all distribute except over PLUS. */
5522 if (code == PLUS || code == MINUS)
5527 if (code != PLUS && code != MINUS)
5533 /* These are also multiplies, so they distribute over everything. */
5537 /* Non-paradoxical SUBREGs distributes over all operations, provided
5538 the inner modes and word numbers are the same, this is an extraction
5539 of a low-order part, we don't convert an fp operation to int or
5540 vice versa, and we would not be converting a single-word
5541 operation into a multi-word operation. The latter test is not
5542 required, but it prevents generating unneeded multi-word operations.
5543 Some of the previous tests are redundant given the latter test, but
5544 are retained because they are required for correctness.
5546 We produce the result slightly differently in this case. */
5548 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5549 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5550 || ! subreg_lowpart_p (lhs)
5551 || (GET_MODE_CLASS (GET_MODE (lhs))
5552 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5553 || (GET_MODE_SIZE (GET_MODE (lhs))
5554 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5555 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5558 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5559 SUBREG_REG (lhs), SUBREG_REG (rhs));
5560 return gen_lowpart_for_combine (GET_MODE (x), tem);
5566 /* Set LHS and RHS to the inner operands (A and B in the example
5567 above) and set OTHER to the common operand (C in the example).
5568 These is only one way to do this unless the inner operation is
5570 if (GET_RTX_CLASS (inner_code) == 'c'
5571 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5572 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5573 else if (GET_RTX_CLASS (inner_code) == 'c'
5574 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5575 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5576 else if (GET_RTX_CLASS (inner_code) == 'c'
5577 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5578 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5579 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5580 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5584 /* Form the new inner operation, seeing if it simplifies first. */
5585 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5587 /* There is one exception to the general way of distributing:
5588 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5589 if (code == XOR && inner_code == IOR)
5592 other = gen_unary (NOT, GET_MODE (x), other);
5595 /* We may be able to continuing distributing the result, so call
5596 ourselves recursively on the inner operation before forming the
5597 outer operation, which we return. */
5598 return gen_binary (inner_code, GET_MODE (x),
5599 apply_distributive_law (tem), other);
5602 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5605 Return an equivalent form, if different from X. Otherwise, return X. If
5606 X is zero, we are to always construct the equivalent form. */
5609 simplify_and_const_int (x, mode, varop, constop)
5611 enum machine_mode mode;
5613 unsigned HOST_WIDE_INT constop;
5615 register enum machine_mode tmode;
5617 unsigned HOST_WIDE_INT significant;
5619 /* There is a large class of optimizations based on the principle that
5620 some operations produce results where certain bits are known to be zero,
5621 and hence are not significant to the AND. For example, if we have just
5622 done a left shift of one bit, the low-order bit is known to be zero and
5623 hence an AND with a mask of ~1 would not do anything.
5625 At the end of the following loop, we set:
5627 VAROP to be the item to be AND'ed with;
5628 CONSTOP to the constant value to AND it with. */
5632 /* If we ever encounter a mode wider than the host machine's widest
5633 integer size, we can't compute the masks accurately, so give up. */
5634 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5637 /* Unless one of the cases below does a `continue',
5638 a `break' will be executed to exit the loop. */
5640 switch (GET_CODE (varop))
5643 /* If VAROP is a (clobber (const_int)), return it since we know
5644 we are generating something that won't match. */
5647 #if ! BITS_BIG_ENDIAN
5649 /* VAROP is a (use (mem ..)) that was made from a bit-field
5650 extraction that spanned the boundary of the MEM. If we are
5651 now masking so it is within that boundary, we don't need the
5653 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5655 varop = XEXP (varop, 0);
5662 if (subreg_lowpart_p (varop)
5663 /* We can ignore the effect this SUBREG if it narrows the mode
5664 or, on machines where byte operations extend, if the
5665 constant masks to zero all the bits the mode doesn't have. */
5666 && ((GET_MODE_SIZE (GET_MODE (varop))
5667 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5668 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
5670 & GET_MODE_MASK (GET_MODE (varop))
5671 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5675 varop = SUBREG_REG (varop);
5684 /* Try to expand these into a series of shifts and then work
5685 with that result. If we can't, for example, if the extract
5686 isn't at a fixed position, give up. */
5687 temp = expand_compound_operation (varop);
5696 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5698 constop &= INTVAL (XEXP (varop, 1));
5699 varop = XEXP (varop, 0);
5706 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5707 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5708 operation which may be a bitfield extraction. */
5710 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5711 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5712 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5713 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5714 && GET_CODE (XEXP (varop, 1)) == CONST_INT
5715 && (INTVAL (XEXP (varop, 1))
5716 & ~ significant_bits (XEXP (varop, 0),
5717 GET_MODE (varop)) == 0))
5719 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
5720 << INTVAL (XEXP (XEXP (varop, 0), 1)));
5721 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5722 XEXP (XEXP (varop, 0), 0), temp);
5723 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5724 temp, XEXP (varop, 1));
5728 /* Apply the AND to both branches of the IOR or XOR, then try to
5729 apply the distributive law. This may eliminate operations
5730 if either branch can be simplified because of the AND.
5731 It may also make some cases more complex, but those cases
5732 probably won't match a pattern either with or without this. */
5734 gen_lowpart_for_combine
5735 (mode, apply_distributive_law
5737 (GET_CODE (varop), GET_MODE (varop),
5738 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5739 XEXP (varop, 0), constop),
5740 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5741 XEXP (varop, 1), constop))));
5744 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5745 LSHIFTRT we can do the same as above. */
5747 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5748 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5749 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5750 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5752 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
5753 temp = gen_binary (XOR, GET_MODE (varop),
5754 XEXP (XEXP (varop, 0), 0), temp);
5755 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5756 temp, XEXP (XEXP (varop, 0), 1));
5762 /* If we are just looking for the sign bit, we don't need this
5763 shift at all, even if it has a variable count. */
5764 if (constop == ((HOST_WIDE_INT) 1
5765 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
5767 varop = XEXP (varop, 0);
5771 /* If this is a shift by a constant, get a mask that contains
5772 those bits that are not copies of the sign bit. We then have
5773 two cases: If CONSTOP only includes those bits, this can be
5774 a logical shift, which may allow simplifications. If CONSTOP
5775 is a single-bit field not within those bits, we are requesting
5776 a copy of the sign bit and hence can shift the sign bit to
5777 the appropriate location. */
5778 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5779 && INTVAL (XEXP (varop, 1)) >= 0
5780 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
5784 significant = GET_MODE_MASK (GET_MODE (varop));
5785 significant >>= INTVAL (XEXP (varop, 1));
5787 if ((constop & ~significant) == 0
5788 || (i = exact_log2 (constop)) >= 0)
5790 varop = simplify_shift_const
5791 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5792 i < 0 ? INTVAL (XEXP (varop, 1))
5793 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
5794 if (GET_CODE (varop) != ASHIFTRT)
5799 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5800 even if the shift count isn't a constant. */
5802 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5803 XEXP (varop, 0), XEXP (varop, 1));
5807 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5808 included in STORE_FLAG_VALUE and FOO has no significant bits
5810 if ((constop & ~ STORE_FLAG_VALUE) == 0
5811 && XEXP (varop, 0) == const0_rtx
5812 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5814 varop = XEXP (varop, 0);
5820 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5821 low-order bits (as in an alignment operation) and FOO is already
5822 aligned to that boundary, we can convert remove this AND
5823 and possibly the PLUS if it is now adding zero. */
5824 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5825 && exact_log2 (-constop) >= 0
5826 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5828 varop = plus_constant (XEXP (varop, 0),
5829 INTVAL (XEXP (varop, 1)) & constop);
5834 /* ... fall through ... */
5837 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5838 less than powers of two and M2 is narrower than M1, we can
5839 eliminate the inner AND. This occurs when incrementing
5842 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5843 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5844 SUBST (XEXP (varop, 0),
5845 expand_compound_operation (XEXP (varop, 0)));
5847 if (GET_CODE (XEXP (varop, 0)) == AND
5848 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5849 && exact_log2 (constop + 1) >= 0
5850 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5851 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5852 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5859 /* If we have reached a constant, this whole thing is constant. */
5860 if (GET_CODE (varop) == CONST_INT)
5861 return GEN_INT (constop & INTVAL (varop));
5863 /* See what bits are significant in VAROP. */
5864 significant = significant_bits (varop, mode);
5866 /* Turn off all bits in the constant that are known to already be zero.
5867 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5868 which is tested below. */
5870 constop &= significant;
5872 /* If we don't have any bits left, return zero. */
5876 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5877 if we already had one (just check for the simplest cases). */
5878 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5879 && GET_MODE (XEXP (x, 0)) == mode
5880 && SUBREG_REG (XEXP (x, 0)) == varop)
5881 varop = XEXP (x, 0);
5883 varop = gen_lowpart_for_combine (mode, varop);
5885 /* If we can't make the SUBREG, try to return what we were given. */
5886 if (GET_CODE (varop) == CLOBBER)
5887 return x ? x : varop;
5889 /* If we are only masking insignificant bits, return VAROP. */
5890 if (constop == significant)
5893 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5894 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5895 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
5899 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5900 || INTVAL (XEXP (x, 1)) != constop)
5901 SUBST (XEXP (x, 1), GEN_INT (constop));
5903 SUBST (XEXP (x, 0), varop);
5909 /* Given an expression, X, compute which bits in X can be non-zero.
5910 We don't care about bits outside of those defined in MODE.
5912 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5913 a shift, AND, or zero_extract, we can do better. */
5915 static unsigned HOST_WIDE_INT
5916 significant_bits (x, mode)
5918 enum machine_mode mode;
5920 unsigned HOST_WIDE_INT significant = GET_MODE_MASK (mode);
5921 unsigned HOST_WIDE_INT inner_sig;
5923 int mode_width = GET_MODE_BITSIZE (mode);
5926 /* If X is wider than MODE, use its mode instead. */
5927 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5929 mode = GET_MODE (x);
5930 significant = GET_MODE_MASK (mode);
5931 mode_width = GET_MODE_BITSIZE (mode);
5934 if (mode_width > HOST_BITS_PER_WIDE_INT)
5935 /* Our only callers in this case look for single bit values. So
5936 just return the mode mask. Those tests will then be false. */
5939 code = GET_CODE (x);
5943 #ifdef STACK_BOUNDARY
5944 /* If this is the stack pointer, we may know something about its
5945 alignment. If PUSH_ROUNDING is defined, it is possible for the
5946 stack to be momentarily aligned only to that amount, so we pick
5947 the least alignment. */
5949 if (x == stack_pointer_rtx)
5951 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5953 #ifdef PUSH_ROUNDING
5954 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5957 return significant & ~ (sp_alignment - 1);
5961 /* If X is a register whose value we can find, use that value.
5962 Otherwise, use the previously-computed significant bits for this
5965 tem = get_last_value (x);
5967 return significant_bits (tem, mode);
5968 else if (significant_valid && reg_significant[REGNO (x)])
5969 return reg_significant[REGNO (x)] & significant;
5976 #ifdef BYTE_LOADS_ZERO_EXTEND
5978 /* In many, if not most, RISC machines, reading a byte from memory
5979 zeros the rest of the register. Noticing that fact saves a lot
5980 of extra zero-extends. */
5981 significant &= GET_MODE_MASK (GET_MODE (x));
5985 #if STORE_FLAG_VALUE == 1
5992 if (GET_MODE_CLASS (mode) == MODE_INT)
5995 /* A comparison operation only sets the bits given by its mode. The
5996 rest are set undefined. */
5997 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5998 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6003 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6004 == GET_MODE_BITSIZE (GET_MODE (x)))
6007 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6008 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6012 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6013 == GET_MODE_BITSIZE (GET_MODE (x)))
6018 significant &= (significant_bits (XEXP (x, 0), mode)
6019 & GET_MODE_MASK (mode));
6023 significant &= significant_bits (XEXP (x, 0), mode);
6024 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6025 significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6029 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6030 Otherwise, show all the bits in the outer mode but not the inner
6032 inner_sig = significant_bits (XEXP (x, 0), mode);
6033 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6035 inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6038 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6039 inner_sig |= (GET_MODE_MASK (mode)
6040 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6043 significant &= inner_sig;
6047 significant &= (significant_bits (XEXP (x, 0), mode)
6048 & significant_bits (XEXP (x, 1), mode));
6052 case UMIN: case UMAX: case SMIN: case SMAX:
6053 significant &= (significant_bits (XEXP (x, 0), mode)
6054 | significant_bits (XEXP (x, 1), mode));
6057 case PLUS: case MINUS:
6059 case DIV: case UDIV:
6060 case MOD: case UMOD:
6061 /* We can apply the rules of arithmetic to compute the number of
6062 high- and low-order zero bits of these operations. We start by
6063 computing the width (position of the highest-order non-zero bit)
6064 and the number of low-order zero bits for each value. */
6066 unsigned HOST_WIDE_INT sig0 = significant_bits (XEXP (x, 0), mode);
6067 unsigned HOST_WIDE_INT sig1 = significant_bits (XEXP (x, 1), mode);
6068 int width0 = floor_log2 (sig0) + 1;
6069 int width1 = floor_log2 (sig1) + 1;
6070 int low0 = floor_log2 (sig0 & -sig0);
6071 int low1 = floor_log2 (sig1 & -sig1);
6072 int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
6073 int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
6074 int result_width = mode_width;
6080 result_width = MAX (width0, width1) + 1;
6081 result_low = MIN (low0, low1);
6084 result_low = MIN (low0, low1);
6087 result_width = width0 + width1;
6088 result_low = low0 + low1;
6091 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6092 result_width = width0;
6095 result_width = width0;
6098 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6099 result_width = MIN (width0, width1);
6100 result_low = MIN (low0, low1);
6103 result_width = MIN (width0, width1);
6104 result_low = MIN (low0, low1);
6108 if (result_width < mode_width)
6109 significant &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6112 significant &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6117 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6118 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6119 significant &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6123 /* If this is a SUBREG formed for a promoted variable that has
6124 been zero-extended, we know that at least the high-order bits
6125 are zero, though others might be too. */
6127 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6128 significant = (GET_MODE_MASK (GET_MODE (x))
6129 & significant_bits (SUBREG_REG (x), GET_MODE (x)));
6131 /* If the inner mode is a single word for both the host and target
6132 machines, we can compute this from which bits of the inner
6133 object are known significant. */
6134 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6135 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6136 <= HOST_BITS_PER_WIDE_INT))
6138 significant &= significant_bits (SUBREG_REG (x), mode);
6139 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND)
6140 /* On many CISC machines, accessing an object in a wider mode
6141 causes the high-order bits to become undefined. So they are
6142 not known to be zero. */
6143 if (GET_MODE_SIZE (GET_MODE (x))
6144 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6145 significant |= (GET_MODE_MASK (GET_MODE (x))
6146 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6156 /* The significant bits are in two classes: any bits within MODE
6157 that aren't in GET_MODE (x) are always significant. The rest of the
6158 significant bits are those that are significant in the operand of
6159 the shift when shifted the appropriate number of bits. This
6160 shows that high-order bits are cleared by the right shift and
6161 low-order bits by left shifts. */
6162 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6163 && INTVAL (XEXP (x, 1)) >= 0
6164 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6166 enum machine_mode inner_mode = GET_MODE (x);
6167 int width = GET_MODE_BITSIZE (inner_mode);
6168 int count = INTVAL (XEXP (x, 1));
6169 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6170 unsigned HOST_WIDE_INT op_significant
6171 = significant_bits (XEXP (x, 0), mode);
6172 unsigned HOST_WIDE_INT inner = op_significant & mode_mask;
6173 unsigned HOST_WIDE_INT outer = 0;
6175 if (mode_width > width)
6176 outer = (op_significant & significant & ~ mode_mask);
6178 if (code == LSHIFTRT)
6180 else if (code == ASHIFTRT)
6184 /* If the sign bit was significant at before the shift, we
6185 need to mark all the places it could have been copied to
6186 by the shift significant. */
6187 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6188 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6190 else if (code == LSHIFT || code == ASHIFT)
6193 inner = ((inner << (count % width)
6194 | (inner >> (width - (count % width)))) & mode_mask);
6196 significant &= (outer | inner);
6201 /* This is at most the number of bits in the mode. */
6202 significant = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6206 significant &= (significant_bits (XEXP (x, 1), mode)
6207 | significant_bits (XEXP (x, 2), mode));
6214 /* Return the number of bits at the high-order end of X that are known to
6215 be equal to the sign bit. This number will always be between 1 and
6216 the number of bits in the mode of X. MODE is the mode to be used
6217 if X is VOIDmode. */
6220 num_sign_bit_copies (x, mode)
6222 enum machine_mode mode;
6224 enum rtx_code code = GET_CODE (x);
6226 int num0, num1, result;
6227 unsigned HOST_WIDE_INT sig;
6230 /* If we weren't given a mode, use the mode of X. If the mode is still
6231 VOIDmode, we don't know anything. */
6233 if (mode == VOIDmode)
6234 mode = GET_MODE (x);
6236 if (mode == VOIDmode)
6239 bitwidth = GET_MODE_BITSIZE (mode);
6244 if (significant_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6245 return reg_sign_bit_copies[REGNO (x)];
6247 tem = get_last_value (x);
6249 return num_sign_bit_copies (tem, mode);
6252 #ifdef BYTE_LOADS_SIGN_EXTEND
6254 /* Some RISC machines sign-extend all loads of smaller than a word. */
6255 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6259 /* If the constant is negative, take its 1's complement and remask.
6260 Then see how many zero bits we have. */
6261 sig = INTVAL (x) & GET_MODE_MASK (mode);
6262 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6263 && (sig & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6264 sig = (~ sig) & GET_MODE_MASK (mode);
6266 return (sig == 0 ? bitwidth : bitwidth - floor_log2 (sig) - 1);
6269 /* If this is a SUBREG for a promoted object that is sign-extended
6270 and we are looking at it in a wider mode, we know that at least the
6271 high-order bits are known to be sign bit copies. */
6273 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6274 return (GET_MODE_BITSIZE (mode) - GET_MODE_BITSIZE (GET_MODE (x))
6275 + num_sign_bit_copies (SUBREG_REG (x), GET_MODE (x)));
6277 /* For a smaller object, just ignore the high bits. */
6278 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6280 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6281 return MAX (1, (num0
6282 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6286 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
6287 /* For paradoxical SUBREGs, just look inside since, on machines with
6288 one of these defined, we assume that operations are actually
6289 performed on the full register. Note that we are passing MODE
6290 to the recursive call, so the number of sign bit copies will
6291 remain relative to that mode, not the inner mode. */
6293 if (GET_MODE_SIZE (GET_MODE (x))
6294 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6295 return num_sign_bit_copies (SUBREG_REG (x), mode);
6301 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6302 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6306 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6307 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6310 /* For a smaller object, just ignore the high bits. */
6311 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6312 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6316 return num_sign_bit_copies (XEXP (x, 0), mode);
6318 case ROTATE: case ROTATERT:
6319 /* If we are rotating left by a number of bits less than the number
6320 of sign bit copies, we can just subtract that amount from the
6322 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6323 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6325 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6326 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6327 : bitwidth - INTVAL (XEXP (x, 1))));
6332 /* In general, this subtracts one sign bit copy. But if the value
6333 is known to be positive, the number of sign bit copies is the
6334 same as that of the input. Finally, if the input has just one
6335 significant bit, all the bits are copies of the sign bit. */
6336 sig = significant_bits (XEXP (x, 0), mode);
6340 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6342 && bitwidth <= HOST_BITS_PER_WIDE_INT
6343 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig))
6348 case IOR: case AND: case XOR:
6349 case SMIN: case SMAX: case UMIN: case UMAX:
6350 /* Logical operations will preserve the number of sign-bit copies.
6351 MIN and MAX operations always return one of the operands. */
6352 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6353 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6354 return MIN (num0, num1);
6356 case PLUS: case MINUS:
6357 /* For addition and subtraction, we can have a 1-bit carry. However,
6358 if we are subtracting 1 from a positive number, there will not
6359 be such a carry. Furthermore, if the positive number is known to
6360 be 0 or 1, we know the result is either -1 or 0. */
6362 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6363 /* Don't do this if XEXP (x, 0) is a paradoxical subreg
6364 because in principle we don't know what the high bits are. */
6365 && !(GET_CODE (XEXP (x, 0)) == SUBREG
6366 && (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
6367 < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))))
6369 sig = significant_bits (XEXP (x, 0), mode);
6370 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig) == 0)
6371 return (sig == 1 || sig == 0 ? bitwidth
6372 : bitwidth - floor_log2 (sig) - 1);
6375 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6376 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6377 return MAX (1, MIN (num0, num1) - 1);
6380 /* The number of bits of the product is the sum of the number of
6381 bits of both terms. However, unless one of the terms if known
6382 to be positive, we must allow for an additional bit since negating
6383 a negative number can remove one sign bit copy. */
6385 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6386 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6388 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6390 && bitwidth <= HOST_BITS_PER_INT
6391 && ((significant_bits (XEXP (x, 0), mode)
6392 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6393 && (significant_bits (XEXP (x, 1), mode)
6394 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6397 return MAX (1, result);
6400 /* The result must be <= the first operand. */
6401 return num_sign_bit_copies (XEXP (x, 0), mode);
6404 /* The result must be <= the scond operand. */
6405 return num_sign_bit_copies (XEXP (x, 1), mode);
6408 /* Similar to unsigned division, except that we have to worry about
6409 the case where the divisor is negative, in which case we have
6411 result = num_sign_bit_copies (XEXP (x, 0), mode);
6413 && bitwidth <= HOST_BITS_PER_WIDE_INT
6414 && (significant_bits (XEXP (x, 1), mode)
6415 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6421 result = num_sign_bit_copies (XEXP (x, 1), mode);
6423 && bitwidth <= HOST_BITS_PER_WIDE_INT
6424 && (significant_bits (XEXP (x, 1), mode)
6425 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6431 /* Shifts by a constant add to the number of bits equal to the
6433 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6434 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6435 && INTVAL (XEXP (x, 1)) > 0)
6436 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6442 /* Left shifts destroy copies. */
6443 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6444 || INTVAL (XEXP (x, 1)) < 0
6445 || INTVAL (XEXP (x, 1)) >= bitwidth)
6448 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6449 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6452 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6453 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6454 return MIN (num0, num1);
6456 #if STORE_FLAG_VALUE == -1
6457 case EQ: case NE: case GE: case GT: case LE: case LT:
6458 case GEU: case GTU: case LEU: case LTU:
6463 /* If we haven't been able to figure it out by one of the above rules,
6464 see if some of the high-order bits are known to be zero. If so,
6465 count those bits and return one less than that amount. If we can't
6466 safely compute the mask for this mode, always return BITWIDTH. */
6468 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6471 sig = significant_bits (x, mode);
6472 return sig == GET_MODE_MASK (mode) ? 1 : bitwidth - floor_log2 (sig) - 1;
6475 /* Return the number of "extended" bits there are in X, when interpreted
6476 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6477 unsigned quantities, this is the number of high-order zero bits.
6478 For signed quantities, this is the number of copies of the sign bit
6479 minus 1. In both case, this function returns the number of "spare"
6480 bits. For example, if two quantities for which this function returns
6481 at least 1 are added, the addition is known not to overflow.
6483 This function will always return 0 unless called during combine, which
6484 implies that it must be called from a define_split. */
6487 extended_count (x, mode, unsignedp)
6489 enum machine_mode mode;
6492 if (significant_valid == 0)
6496 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6497 && (GET_MODE_BITSIZE (mode) - 1
6498 - floor_log2 (significant_bits (x, mode))))
6499 : num_sign_bit_copies (x, mode) - 1);
6502 /* This function is called from `simplify_shift_const' to merge two
6503 outer operations. Specifically, we have already found that we need
6504 to perform operation *POP0 with constant *PCONST0 at the outermost
6505 position. We would now like to also perform OP1 with constant CONST1
6506 (with *POP0 being done last).
6508 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6509 the resulting operation. *PCOMP_P is set to 1 if we would need to
6510 complement the innermost operand, otherwise it is unchanged.
6512 MODE is the mode in which the operation will be done. No bits outside
6513 the width of this mode matter. It is assumed that the width of this mode
6514 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6516 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6517 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6518 result is simply *PCONST0.
6520 If the resulting operation cannot be expressed as one operation, we
6521 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6524 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6525 enum rtx_code *pop0;
6526 HOST_WIDE_INT *pconst0;
6528 HOST_WIDE_INT const1;
6529 enum machine_mode mode;
6532 enum rtx_code op0 = *pop0;
6533 HOST_WIDE_INT const0 = *pconst0;
6535 const0 &= GET_MODE_MASK (mode);
6536 const1 &= GET_MODE_MASK (mode);
6538 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6542 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6545 if (op1 == NIL || op0 == SET)
6548 else if (op0 == NIL)
6549 op0 = op1, const0 = const1;
6551 else if (op0 == op1)
6573 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6574 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6577 /* If the two constants aren't the same, we can't do anything. The
6578 remaining six cases can all be done. */
6579 else if (const0 != const1)
6587 /* (a & b) | b == b */
6589 else /* op1 == XOR */
6590 /* (a ^ b) | b == a | b */
6596 /* (a & b) ^ b == (~a) & b */
6597 op0 = AND, *pcomp_p = 1;
6598 else /* op1 == IOR */
6599 /* (a | b) ^ b == a & ~b */
6600 op0 = AND, *pconst0 = ~ const0;
6605 /* (a | b) & b == b */
6607 else /* op1 == XOR */
6608 /* (a ^ b) & b) == (~a) & b */
6613 /* Check for NO-OP cases. */
6614 const0 &= GET_MODE_MASK (mode);
6616 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6618 else if (const0 == 0 && op0 == AND)
6620 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6629 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6630 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6631 that we started with.
6633 The shift is normally computed in the widest mode we find in VAROP, as
6634 long as it isn't a different number of words than RESULT_MODE. Exceptions
6635 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6638 simplify_shift_const (x, code, result_mode, varop, count)
6641 enum machine_mode result_mode;
6645 enum rtx_code orig_code = code;
6646 int orig_count = count;
6647 enum machine_mode mode = result_mode;
6648 enum machine_mode shift_mode, tmode;
6650 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6651 /* We form (outer_op (code varop count) (outer_const)). */
6652 enum rtx_code outer_op = NIL;
6653 HOST_WIDE_INT outer_const;
6655 int complement_p = 0;
6658 /* If we were given an invalid count, don't do anything except exactly
6659 what was requested. */
6661 if (count < 0 || count > GET_MODE_BITSIZE (mode))
6666 return gen_rtx (code, mode, varop, GEN_INT (count));
6669 /* Unless one of the branches of the `if' in this loop does a `continue',
6670 we will `break' the loop after the `if'. */
6674 /* If we have an operand of (clobber (const_int 0)), just return that
6676 if (GET_CODE (varop) == CLOBBER)
6679 /* If we discovered we had to complement VAROP, leave. Making a NOT
6680 here would cause an infinite loop. */
6684 /* Convert ROTATETRT to ROTATE. */
6685 if (code == ROTATERT)
6686 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6688 /* Canonicalize LSHIFT to ASHIFT. */
6692 /* We need to determine what mode we will do the shift in. If the
6693 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6694 was originally done in. Otherwise, we can do it in MODE, the widest
6695 mode encountered. */
6696 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6698 /* Handle cases where the count is greater than the size of the mode
6699 minus 1. For ASHIFT, use the size minus one as the count (this can
6700 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6701 take the count modulo the size. For other shifts, the result is
6704 Since these shifts are being produced by the compiler by combining
6705 multiple operations, each of which are defined, we know what the
6706 result is supposed to be. */
6708 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6710 if (code == ASHIFTRT)
6711 count = GET_MODE_BITSIZE (shift_mode) - 1;
6712 else if (code == ROTATE || code == ROTATERT)
6713 count %= GET_MODE_BITSIZE (shift_mode);
6716 /* We can't simply return zero because there may be an
6724 /* Negative counts are invalid and should not have been made (a
6725 programmer-specified negative count should have been handled
6730 /* An arithmetic right shift of a quantity known to be -1 or 0
6732 if (code == ASHIFTRT
6733 && (num_sign_bit_copies (varop, shift_mode)
6734 == GET_MODE_BITSIZE (shift_mode)))
6740 /* We simplify the tests below and elsewhere by converting
6741 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6742 `make_compound_operation' will convert it to a ASHIFTRT for
6743 those machines (such as Vax) that don't have a LSHIFTRT. */
6744 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
6746 && ((significant_bits (varop, shift_mode)
6747 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
6751 switch (GET_CODE (varop))
6757 new = expand_compound_operation (varop);
6766 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
6767 minus the width of a smaller mode, we can do this with a
6768 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
6769 if ((code == ASHIFTRT || code == LSHIFTRT)
6770 && ! mode_dependent_address_p (XEXP (varop, 0))
6771 && ! MEM_VOLATILE_P (varop)
6772 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6773 MODE_INT, 1)) != BLKmode)
6775 #if BYTES_BIG_ENDIAN
6776 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
6778 new = gen_rtx (MEM, tmode,
6779 plus_constant (XEXP (varop, 0),
6780 count / BITS_PER_UNIT));
6781 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
6782 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
6783 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
6785 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6786 : ZERO_EXTEND, mode, new);
6793 /* Similar to the case above, except that we can only do this if
6794 the resulting mode is the same as that of the underlying
6795 MEM and adjust the address depending on the *bits* endianness
6796 because of the way that bit-field extract insns are defined. */
6797 if ((code == ASHIFTRT || code == LSHIFTRT)
6798 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6799 MODE_INT, 1)) != BLKmode
6800 && tmode == GET_MODE (XEXP (varop, 0)))
6803 new = XEXP (varop, 0);
6805 new = copy_rtx (XEXP (varop, 0));
6806 SUBST (XEXP (new, 0),
6807 plus_constant (XEXP (new, 0),
6808 count / BITS_PER_UNIT));
6811 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6812 : ZERO_EXTEND, mode, new);
6819 /* If VAROP is a SUBREG, strip it as long as the inner operand has
6820 the same number of words as what we've seen so far. Then store
6821 the widest mode in MODE. */
6822 if (subreg_lowpart_p (varop)
6823 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6824 > GET_MODE_SIZE (GET_MODE (varop)))
6825 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6826 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6829 varop = SUBREG_REG (varop);
6830 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
6831 mode = GET_MODE (varop);
6837 /* Some machines use MULT instead of ASHIFT because MULT
6838 is cheaper. But it is still better on those machines to
6839 merge two shifts into one. */
6840 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6841 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6843 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
6844 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
6850 /* Similar, for when divides are cheaper. */
6851 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6852 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6854 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6855 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
6861 /* If we are extracting just the sign bit of an arithmetic right
6862 shift, that shift is not needed. */
6863 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
6865 varop = XEXP (varop, 0);
6869 /* ... fall through ... */
6875 /* Here we have two nested shifts. The result is usually the
6876 AND of a new shift with a mask. We compute the result below. */
6877 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6878 && INTVAL (XEXP (varop, 1)) >= 0
6879 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
6880 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
6881 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6883 enum rtx_code first_code = GET_CODE (varop);
6884 int first_count = INTVAL (XEXP (varop, 1));
6885 unsigned HOST_WIDE_INT mask;
6889 if (first_code == LSHIFT)
6890 first_code = ASHIFT;
6892 /* We have one common special case. We can't do any merging if
6893 the inner code is an ASHIFTRT of a smaller mode. However, if
6894 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
6895 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
6896 we can convert it to
6897 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
6898 This simplifies certain SIGN_EXTEND operations. */
6899 if (code == ASHIFT && first_code == ASHIFTRT
6900 && (GET_MODE_BITSIZE (result_mode)
6901 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
6903 /* C3 has the low-order C1 bits zero. */
6905 mask = (GET_MODE_MASK (mode)
6906 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
6908 varop = simplify_and_const_int (NULL_RTX, result_mode,
6909 XEXP (varop, 0), mask);
6910 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
6912 count = first_count;
6917 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
6918 than C1 high-order bits equal to the sign bit, we can convert
6919 this to either an ASHIFT or a ASHIFTRT depending on the
6922 We cannot do this if VAROP's mode is not SHIFT_MODE. */
6924 if (code == ASHIFTRT && first_code == ASHIFT
6925 && GET_MODE (varop) == shift_mode
6926 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
6929 count -= first_count;
6931 count = - count, code = ASHIFT;
6932 varop = XEXP (varop, 0);
6936 /* There are some cases we can't do. If CODE is ASHIFTRT,
6937 we can only do this if FIRST_CODE is also ASHIFTRT.
6939 We can't do the case when CODE is ROTATE and FIRST_CODE is
6942 If the mode of this shift is not the mode of the outer shift,
6943 we can't do this if either shift is ASHIFTRT or ROTATE.
6945 Finally, we can't do any of these if the mode is too wide
6946 unless the codes are the same.
6948 Handle the case where the shift codes are the same
6951 if (code == first_code)
6953 if (GET_MODE (varop) != result_mode
6954 && (code == ASHIFTRT || code == ROTATE))
6957 count += first_count;
6958 varop = XEXP (varop, 0);
6962 if (code == ASHIFTRT
6963 || (code == ROTATE && first_code == ASHIFTRT)
6964 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
6965 || (GET_MODE (varop) != result_mode
6966 && (first_code == ASHIFTRT || first_code == ROTATE
6967 || code == ROTATE)))
6970 /* To compute the mask to apply after the shift, shift the
6971 significant bits of the inner shift the same way the
6972 outer shift will. */
6974 mask_rtx = GEN_INT (significant_bits (varop, GET_MODE (varop)));
6977 = simplify_binary_operation (code, result_mode, mask_rtx,
6980 /* Give up if we can't compute an outer operation to use. */
6982 || GET_CODE (mask_rtx) != CONST_INT
6983 || ! merge_outer_ops (&outer_op, &outer_const, AND,
6985 result_mode, &complement_p))
6988 /* If the shifts are in the same direction, we add the
6989 counts. Otherwise, we subtract them. */
6990 if ((code == ASHIFTRT || code == LSHIFTRT)
6991 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
6992 count += first_count;
6994 count -= first_count;
6996 /* If COUNT is positive, the new shift is usually CODE,
6997 except for the two exceptions below, in which case it is
6998 FIRST_CODE. If the count is negative, FIRST_CODE should
7001 && ((first_code == ROTATE && code == ASHIFT)
7002 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7005 code = first_code, count = - count;
7007 varop = XEXP (varop, 0);
7011 /* If we have (A << B << C) for any shift, we can convert this to
7012 (A << C << B). This wins if A is a constant. Only try this if
7013 B is not a constant. */
7015 else if (GET_CODE (varop) == code
7016 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7018 = simplify_binary_operation (code, mode,
7022 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7029 /* Make this fit the case below. */
7030 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7031 GEN_INT (GET_MODE_MASK (mode)));
7037 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7038 with C the size of VAROP - 1 and the shift is logical if
7039 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7040 we have an (le X 0) operation. If we have an arithmetic shift
7041 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7042 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7044 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7045 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7046 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7047 && (code == LSHIFTRT || code == ASHIFTRT)
7048 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7049 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7052 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7055 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7056 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7061 /* If we have (shift (logical)), move the logical to the outside
7062 to allow it to possibly combine with another logical and the
7063 shift to combine with another shift. This also canonicalizes to
7064 what a ZERO_EXTRACT looks like. Also, some machines have
7065 (and (shift)) insns. */
7067 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7068 && (new = simplify_binary_operation (code, result_mode,
7070 GEN_INT (count))) != 0
7071 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7072 INTVAL (new), result_mode, &complement_p))
7074 varop = XEXP (varop, 0);
7078 /* If we can't do that, try to simplify the shift in each arm of the
7079 logical expression, make a new logical expression, and apply
7080 the inverse distributive law. */
7082 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7083 XEXP (varop, 0), count);
7084 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7085 XEXP (varop, 1), count);
7087 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7088 varop = apply_distributive_law (varop);
7095 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7096 says that the sign bit can be tested, FOO has mode MODE, C is
7097 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7100 && XEXP (varop, 1) == const0_rtx
7101 && GET_MODE (XEXP (varop, 0)) == result_mode
7102 && count == GET_MODE_BITSIZE (result_mode) - 1
7103 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7104 && ((STORE_FLAG_VALUE
7105 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7106 && significant_bits (XEXP (varop, 0), result_mode) == 1
7107 && merge_outer_ops (&outer_op, &outer_const, XOR,
7108 (HOST_WIDE_INT) 1, result_mode,
7111 varop = XEXP (varop, 0);
7118 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7119 than the number of bits in the mode is equivalent to A. */
7120 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7121 && significant_bits (XEXP (varop, 0), result_mode) == 1)
7123 varop = XEXP (varop, 0);
7128 /* NEG commutes with ASHIFT since it is multiplication. Move the
7129 NEG outside to allow shifts to combine. */
7131 && merge_outer_ops (&outer_op, &outer_const, NEG,
7132 (HOST_WIDE_INT) 0, result_mode,
7135 varop = XEXP (varop, 0);
7141 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7142 is one less than the number of bits in the mode is
7143 equivalent to (xor A 1). */
7144 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7145 && XEXP (varop, 1) == constm1_rtx
7146 && significant_bits (XEXP (varop, 0), result_mode) == 1
7147 && merge_outer_ops (&outer_op, &outer_const, XOR,
7148 (HOST_WIDE_INT) 1, result_mode,
7152 varop = XEXP (varop, 0);
7156 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7157 significant in BAR are those being shifted out and those
7158 bits are known zero in FOO, we can replace the PLUS with FOO.
7159 Similarly in the other operand order. This code occurs when
7160 we are computing the size of a variable-size array. */
7162 if ((code == ASHIFTRT || code == LSHIFTRT)
7163 && count < HOST_BITS_PER_WIDE_INT
7164 && significant_bits (XEXP (varop, 1), result_mode) >> count == 0
7165 && (significant_bits (XEXP (varop, 1), result_mode)
7166 & significant_bits (XEXP (varop, 0), result_mode)) == 0)
7168 varop = XEXP (varop, 0);
7171 else if ((code == ASHIFTRT || code == LSHIFTRT)
7172 && count < HOST_BITS_PER_WIDE_INT
7173 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7174 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7176 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7177 & significant_bits (XEXP (varop, 1),
7180 varop = XEXP (varop, 1);
7184 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7186 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7187 && (new = simplify_binary_operation (ASHIFT, result_mode,
7189 GEN_INT (count))) != 0
7190 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7191 INTVAL (new), result_mode, &complement_p))
7193 varop = XEXP (varop, 0);
7199 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7200 with C the size of VAROP - 1 and the shift is logical if
7201 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7202 we have a (gt X 0) operation. If the shift is arithmetic with
7203 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7204 we have a (neg (gt X 0)) operation. */
7206 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7207 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7208 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7209 && (code == LSHIFTRT || code == ASHIFTRT)
7210 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7211 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7212 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7215 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7218 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7219 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7229 /* We need to determine what mode to do the shift in. If the shift is
7230 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7231 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7232 The code we care about is that of the shift that will actually be done,
7233 not the shift that was originally requested. */
7234 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7236 /* We have now finished analyzing the shift. The result should be
7237 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7238 OUTER_OP is non-NIL, it is an operation that needs to be applied
7239 to the result of the shift. OUTER_CONST is the relevant constant,
7240 but we must turn off all bits turned off in the shift.
7242 If we were passed a value for X, see if we can use any pieces of
7243 it. If not, make new rtx. */
7245 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7246 && GET_CODE (XEXP (x, 1)) == CONST_INT
7247 && INTVAL (XEXP (x, 1)) == count)
7248 const_rtx = XEXP (x, 1);
7250 const_rtx = GEN_INT (count);
7252 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7253 && GET_MODE (XEXP (x, 0)) == shift_mode
7254 && SUBREG_REG (XEXP (x, 0)) == varop)
7255 varop = XEXP (x, 0);
7256 else if (GET_MODE (varop) != shift_mode)
7257 varop = gen_lowpart_for_combine (shift_mode, varop);
7259 /* If we can't make the SUBREG, try to return what we were given. */
7260 if (GET_CODE (varop) == CLOBBER)
7261 return x ? x : varop;
7263 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7268 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7269 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7271 SUBST (XEXP (x, 0), varop);
7272 SUBST (XEXP (x, 1), const_rtx);
7275 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7276 turn off all the bits that the shift would have turned off. */
7277 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7278 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7279 GET_MODE_MASK (result_mode) >> orig_count);
7281 /* Do the remainder of the processing in RESULT_MODE. */
7282 x = gen_lowpart_for_combine (result_mode, x);
7284 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7287 x = gen_unary (NOT, result_mode, x);
7289 if (outer_op != NIL)
7291 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7292 outer_const &= GET_MODE_MASK (result_mode);
7294 if (outer_op == AND)
7295 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7296 else if (outer_op == SET)
7297 /* This means that we have determined that the result is
7298 equivalent to a constant. This should be rare. */
7299 x = GEN_INT (outer_const);
7300 else if (GET_RTX_CLASS (outer_op) == '1')
7301 x = gen_unary (outer_op, result_mode, x);
7303 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7309 /* Like recog, but we receive the address of a pointer to a new pattern.
7310 We try to match the rtx that the pointer points to.
7311 If that fails, we may try to modify or replace the pattern,
7312 storing the replacement into the same pointer object.
7314 Modifications include deletion or addition of CLOBBERs.
7316 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7317 the CLOBBERs are placed.
7319 The value is the final insn code from the pattern ultimately matched,
7323 recog_for_combine (pnewpat, insn, pnotes)
7328 register rtx pat = *pnewpat;
7329 int insn_code_number;
7330 int num_clobbers_to_add = 0;
7334 /* Is the result of combination a valid instruction? */
7335 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7337 /* If it isn't, there is the possibility that we previously had an insn
7338 that clobbered some register as a side effect, but the combined
7339 insn doesn't need to do that. So try once more without the clobbers
7340 unless this represents an ASM insn. */
7342 if (insn_code_number < 0 && ! check_asm_operands (pat)
7343 && GET_CODE (pat) == PARALLEL)
7347 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7348 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7351 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7355 SUBST_INT (XVECLEN (pat, 0), pos);
7358 pat = XVECEXP (pat, 0, 0);
7360 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7363 /* If we had any clobbers to add, make a new pattern than contains
7364 them. Then check to make sure that all of them are dead. */
7365 if (num_clobbers_to_add)
7367 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7368 gen_rtvec (GET_CODE (pat) == PARALLEL
7369 ? XVECLEN (pat, 0) + num_clobbers_to_add
7370 : num_clobbers_to_add + 1));
7372 if (GET_CODE (pat) == PARALLEL)
7373 for (i = 0; i < XVECLEN (pat, 0); i++)
7374 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7376 XVECEXP (newpat, 0, 0) = pat;
7378 add_clobbers (newpat, insn_code_number);
7380 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7381 i < XVECLEN (newpat, 0); i++)
7383 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7384 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7386 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7387 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7395 return insn_code_number;
7398 /* Like gen_lowpart but for use by combine. In combine it is not possible
7399 to create any new pseudoregs. However, it is safe to create
7400 invalid memory addresses, because combine will try to recognize
7401 them and all they will do is make the combine attempt fail.
7403 If for some reason this cannot do its job, an rtx
7404 (clobber (const_int 0)) is returned.
7405 An insn containing that will not be recognized. */
7410 gen_lowpart_for_combine (mode, x)
7411 enum machine_mode mode;
7416 if (GET_MODE (x) == mode)
7419 /* We can only support MODE being wider than a word if X is a
7420 constant integer or has a mode the same size. */
7422 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7423 && ! ((GET_MODE (x) == VOIDmode
7424 && (GET_CODE (x) == CONST_INT
7425 || GET_CODE (x) == CONST_DOUBLE))
7426 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7427 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7429 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7430 won't know what to do. So we will strip off the SUBREG here and
7431 process normally. */
7432 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7435 if (GET_MODE (x) == mode)
7439 result = gen_lowpart_common (mode, x);
7443 if (GET_CODE (x) == MEM)
7445 register int offset = 0;
7448 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7450 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7451 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7453 /* If we want to refer to something bigger than the original memref,
7454 generate a perverse subreg instead. That will force a reload
7455 of the original memref X. */
7456 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7457 return gen_rtx (SUBREG, mode, x, 0);
7459 #if WORDS_BIG_ENDIAN
7460 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7461 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7463 #if BYTES_BIG_ENDIAN
7464 /* Adjust the address so that the address-after-the-data
7466 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7467 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7469 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7470 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7471 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7472 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7476 /* If X is a comparison operator, rewrite it in a new mode. This
7477 probably won't match, but may allow further simplifications. */
7478 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7479 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7481 /* If we couldn't simplify X any other way, just enclose it in a
7482 SUBREG. Normally, this SUBREG won't match, but some patterns may
7483 include an explicit SUBREG or we may simplify it further in combine. */
7488 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7489 word = ((GET_MODE_SIZE (GET_MODE (x))
7490 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7492 return gen_rtx (SUBREG, mode, x, word);
7496 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7497 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7499 If the identical expression was previously in the insn (in the undobuf),
7500 it will be returned. Only if it is not found will a new expression
7505 gen_rtx_combine (va_alist)
7510 enum machine_mode mode;
7518 code = va_arg (p, enum rtx_code);
7519 mode = va_arg (p, enum machine_mode);
7520 n_args = GET_RTX_LENGTH (code);
7521 fmt = GET_RTX_FORMAT (code);
7523 if (n_args == 0 || n_args > 3)
7526 /* Get each arg and verify that it is supposed to be an expression. */
7527 for (j = 0; j < n_args; j++)
7532 args[j] = va_arg (p, rtx);
7535 /* See if this is in undobuf. Be sure we don't use objects that came
7536 from another insn; this could produce circular rtl structures. */
7538 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7539 if (!undobuf.undo[i].is_int
7540 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7541 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7543 for (j = 0; j < n_args; j++)
7544 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7548 return undobuf.undo[i].old_contents.rtx;
7551 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7552 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7553 rt = rtx_alloc (code);
7554 PUT_MODE (rt, mode);
7555 XEXP (rt, 0) = args[0];
7558 XEXP (rt, 1) = args[1];
7560 XEXP (rt, 2) = args[2];
7565 /* These routines make binary and unary operations by first seeing if they
7566 fold; if not, a new expression is allocated. */
7569 gen_binary (code, mode, op0, op1)
7571 enum machine_mode mode;
7577 if (GET_RTX_CLASS (code) == 'c'
7578 && (GET_CODE (op0) == CONST_INT
7579 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7580 tem = op0, op0 = op1, op1 = tem;
7582 if (GET_RTX_CLASS (code) == '<')
7584 enum machine_mode op_mode = GET_MODE (op0);
7585 if (op_mode == VOIDmode)
7586 op_mode = GET_MODE (op1);
7587 result = simplify_relational_operation (code, op_mode, op0, op1);
7590 result = simplify_binary_operation (code, mode, op0, op1);
7595 /* Put complex operands first and constants second. */
7596 if (GET_RTX_CLASS (code) == 'c'
7597 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7598 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7599 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7600 || (GET_CODE (op0) == SUBREG
7601 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7602 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7603 return gen_rtx_combine (code, mode, op1, op0);
7605 return gen_rtx_combine (code, mode, op0, op1);
7609 gen_unary (code, mode, op0)
7611 enum machine_mode mode;
7614 rtx result = simplify_unary_operation (code, mode, op0, mode);
7619 return gen_rtx_combine (code, mode, op0);
7622 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7623 comparison code that will be tested.
7625 The result is a possibly different comparison code to use. *POP0 and
7626 *POP1 may be updated.
7628 It is possible that we might detect that a comparison is either always
7629 true or always false. However, we do not perform general constant
7630 folding in combine, so this knowledge isn't useful. Such tautologies
7631 should have been detected earlier. Hence we ignore all such cases. */
7633 static enum rtx_code
7634 simplify_comparison (code, pop0, pop1)
7643 enum machine_mode mode, tmode;
7645 /* Try a few ways of applying the same transformation to both operands. */
7648 /* If both operands are the same constant shift, see if we can ignore the
7649 shift. We can if the shift is a rotate or if the bits shifted out of
7650 this shift are not significant for either input and if the type of
7651 comparison is compatible with the shift. */
7652 if (GET_CODE (op0) == GET_CODE (op1)
7653 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
7654 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7655 || ((GET_CODE (op0) == LSHIFTRT
7656 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7657 && (code != GT && code != LT && code != GE && code != LE))
7658 || (GET_CODE (op0) == ASHIFTRT
7659 && (code != GTU && code != LTU
7660 && code != GEU && code != GEU)))
7661 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7662 && INTVAL (XEXP (op0, 1)) >= 0
7663 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
7664 && XEXP (op0, 1) == XEXP (op1, 1))
7666 enum machine_mode mode = GET_MODE (op0);
7667 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7668 int shift_count = INTVAL (XEXP (op0, 1));
7670 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7671 mask &= (mask >> shift_count) << shift_count;
7672 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7673 mask = (mask & (mask << shift_count)) >> shift_count;
7675 if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7676 && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7677 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7682 /* If both operands are AND's of a paradoxical SUBREG by constant, the
7683 SUBREGs are of the same mode, and, in both cases, the AND would
7684 be redundant if the comparison was done in the narrower mode,
7685 do the comparison in the narrower mode (e.g., we are AND'ing with 1
7686 and the operand's significant bits are 0xffffff01; in that case if
7687 we only care about QImode, we don't need the AND). This case occurs
7688 if the output mode of an scc insn is not SImode and
7689 STORE_FLAG_VALUE == 1 (e.g., the 386). */
7691 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7692 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7693 && GET_CODE (XEXP (op1, 1)) == CONST_INT
7694 && GET_CODE (XEXP (op0, 0)) == SUBREG
7695 && GET_CODE (XEXP (op1, 0)) == SUBREG
7696 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7697 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7698 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7699 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7700 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7701 <= HOST_BITS_PER_WIDE_INT)
7702 && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
7703 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7704 & ~ INTVAL (XEXP (op0, 1))) == 0
7705 && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
7706 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7707 & ~ INTVAL (XEXP (op1, 1))) == 0)
7709 op0 = SUBREG_REG (XEXP (op0, 0));
7710 op1 = SUBREG_REG (XEXP (op1, 0));
7712 /* the resulting comparison is always unsigned since we masked off
7713 the original sign bit. */
7714 code = unsigned_condition (code);
7720 /* If the first operand is a constant, swap the operands and adjust the
7721 comparison code appropriately. */
7722 if (CONSTANT_P (op0))
7724 tem = op0, op0 = op1, op1 = tem;
7725 code = swap_condition (code);
7728 /* We now enter a loop during which we will try to simplify the comparison.
7729 For the most part, we only are concerned with comparisons with zero,
7730 but some things may really be comparisons with zero but not start
7731 out looking that way. */
7733 while (GET_CODE (op1) == CONST_INT)
7735 enum machine_mode mode = GET_MODE (op0);
7736 int mode_width = GET_MODE_BITSIZE (mode);
7737 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7738 int equality_comparison_p;
7739 int sign_bit_comparison_p;
7740 int unsigned_comparison_p;
7741 HOST_WIDE_INT const_op;
7743 /* We only want to handle integral modes. This catches VOIDmode,
7744 CCmode, and the floating-point modes. An exception is that we
7745 can handle VOIDmode if OP0 is a COMPARE or a comparison
7748 if (GET_MODE_CLASS (mode) != MODE_INT
7749 && ! (mode == VOIDmode
7750 && (GET_CODE (op0) == COMPARE
7751 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
7754 /* Get the constant we are comparing against and turn off all bits
7755 not on in our mode. */
7756 const_op = INTVAL (op1);
7757 if (mode_width <= HOST_BITS_PER_WIDE_INT)
7760 /* If we are comparing against a constant power of two and the value
7761 being compared has only that single significant bit (e.g., it was
7762 `and'ed with that bit), we can replace this with a comparison
7765 && (code == EQ || code == NE || code == GE || code == GEU
7766 || code == LT || code == LTU)
7767 && mode_width <= HOST_BITS_PER_WIDE_INT
7768 && exact_log2 (const_op) >= 0
7769 && significant_bits (op0, mode) == const_op)
7771 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
7772 op1 = const0_rtx, const_op = 0;
7775 /* Similarly, if we are comparing a value known to be either -1 or
7776 0 with -1, change it to the opposite comparison against zero. */
7779 && (code == EQ || code == NE || code == GT || code == LE
7780 || code == GEU || code == LTU)
7781 && num_sign_bit_copies (op0, mode) == mode_width)
7783 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
7784 op1 = const0_rtx, const_op = 0;
7787 /* Do some canonicalizations based on the comparison code. We prefer
7788 comparisons against zero and then prefer equality comparisons.
7789 If we can reduce the size of a constant, we will do that too. */
7794 /* < C is equivalent to <= (C - 1) */
7798 op1 = GEN_INT (const_op);
7800 /* ... fall through to LE case below. */
7806 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
7810 op1 = GEN_INT (const_op);
7814 /* If we are doing a <= 0 comparison on a value known to have
7815 a zero sign bit, we can replace this with == 0. */
7816 else if (const_op == 0
7817 && mode_width <= HOST_BITS_PER_WIDE_INT
7818 && (significant_bits (op0, mode)
7819 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7824 /* >= C is equivalent to > (C - 1). */
7828 op1 = GEN_INT (const_op);
7830 /* ... fall through to GT below. */
7836 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
7840 op1 = GEN_INT (const_op);
7844 /* If we are doing a > 0 comparison on a value known to have
7845 a zero sign bit, we can replace this with != 0. */
7846 else if (const_op == 0
7847 && mode_width <= HOST_BITS_PER_WIDE_INT
7848 && (significant_bits (op0, mode)
7849 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7854 /* < C is equivalent to <= (C - 1). */
7858 op1 = GEN_INT (const_op);
7860 /* ... fall through ... */
7863 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
7864 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7866 const_op = 0, op1 = const0_rtx;
7874 /* unsigned <= 0 is equivalent to == 0 */
7878 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
7879 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7881 const_op = 0, op1 = const0_rtx;
7887 /* >= C is equivalent to < (C - 1). */
7891 op1 = GEN_INT (const_op);
7893 /* ... fall through ... */
7896 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
7897 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7899 const_op = 0, op1 = const0_rtx;
7906 /* unsigned > 0 is equivalent to != 0 */
7910 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
7911 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7913 const_op = 0, op1 = const0_rtx;
7919 /* Compute some predicates to simplify code below. */
7921 equality_comparison_p = (code == EQ || code == NE);
7922 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
7923 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
7926 /* Now try cases based on the opcode of OP0. If none of the cases
7927 does a "continue", we exit this loop immediately after the
7930 switch (GET_CODE (op0))
7933 /* If we are extracting a single bit from a variable position in
7934 a constant that has only a single bit set and are comparing it
7935 with zero, we can convert this into an equality comparison
7936 between the position and the location of the single bit. We can't
7937 do this if bit endian and we don't have an extzv since we then
7938 can't know what mode to use for the endianness adjustment. */
7940 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
7941 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
7942 && XEXP (op0, 1) == const1_rtx
7943 && equality_comparison_p && const_op == 0
7944 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
7947 i = (GET_MODE_BITSIZE
7948 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
7951 op0 = XEXP (op0, 2);
7955 /* Result is nonzero iff shift count is equal to I. */
7956 code = reverse_condition (code);
7961 /* ... fall through ... */
7964 tem = expand_compound_operation (op0);
7973 /* If testing for equality, we can take the NOT of the constant. */
7974 if (equality_comparison_p
7975 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
7977 op0 = XEXP (op0, 0);
7982 /* If just looking at the sign bit, reverse the sense of the
7984 if (sign_bit_comparison_p)
7986 op0 = XEXP (op0, 0);
7987 code = (code == GE ? LT : GE);
7993 /* If testing for equality, we can take the NEG of the constant. */
7994 if (equality_comparison_p
7995 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
7997 op0 = XEXP (op0, 0);
8002 /* The remaining cases only apply to comparisons with zero. */
8006 /* When X is ABS or is known positive,
8007 (neg X) is < 0 if and only if X != 0. */
8009 if (sign_bit_comparison_p
8010 && (GET_CODE (XEXP (op0, 0)) == ABS
8011 || (mode_width <= HOST_BITS_PER_WIDE_INT
8012 && (significant_bits (XEXP (op0, 0), mode)
8013 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8015 op0 = XEXP (op0, 0);
8016 code = (code == LT ? NE : EQ);
8020 /* If we have NEG of something that is the result of a
8021 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
8022 two high-order bits must be the same and hence that
8023 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
8025 if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
8026 || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
8027 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8028 && (INTVAL (XEXP (XEXP (op0, 0), 1))
8029 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
8030 || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8031 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8032 && XEXP (XEXP (op0, 0), 1) != const0_rtx)
8033 || ((tem = get_last_value (XEXP (op0, 0))) != 0
8034 && (GET_CODE (tem) == SIGN_EXTEND
8035 || (GET_CODE (tem) == SIGN_EXTRACT
8036 && GET_CODE (XEXP (tem, 1)) == CONST_INT
8037 && (INTVAL (XEXP (tem, 1))
8038 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
8039 || (GET_CODE (tem) == ASHIFTRT
8040 && GET_CODE (XEXP (tem, 1)) == CONST_INT
8041 && XEXP (tem, 1) != const0_rtx))))
8043 op0 = XEXP (op0, 0);
8044 code = swap_condition (code);
8050 /* If we are testing equality and our count is a constant, we
8051 can perform the inverse operation on our RHS. */
8052 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8053 && (tem = simplify_binary_operation (ROTATERT, mode,
8054 op1, XEXP (op0, 1))) != 0)
8056 op0 = XEXP (op0, 0);
8061 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8062 a particular bit. Convert it to an AND of a constant of that
8063 bit. This will be converted into a ZERO_EXTRACT. */
8064 if (const_op == 0 && sign_bit_comparison_p
8065 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8066 && mode_width <= HOST_BITS_PER_WIDE_INT)
8068 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8071 - INTVAL (XEXP (op0, 1)))));
8072 code = (code == LT ? NE : EQ);
8076 /* ... fall through ... */
8079 /* ABS is ignorable inside an equality comparison with zero. */
8080 if (const_op == 0 && equality_comparison_p)
8082 op0 = XEXP (op0, 0);
8089 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8090 to (compare FOO CONST) if CONST fits in FOO's mode and we
8091 are either testing inequality or have an unsigned comparison
8092 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8093 if (! unsigned_comparison_p
8094 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8095 <= HOST_BITS_PER_WIDE_INT)
8096 && ((unsigned HOST_WIDE_INT) const_op
8097 < (((HOST_WIDE_INT) 1
8098 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8100 op0 = XEXP (op0, 0);
8106 /* Check for the case where we are comparing A - C1 with C2,
8107 both constants are smaller than 1/2 the maxium positive
8108 value in MODE, and the comparison is equality or unsigned.
8109 In that case, if A is either zero-extended to MODE or has
8110 sufficient sign bits so that the high-order bit in MODE
8111 is a copy of the sign in the inner mode, we can prove that it is
8112 safe to do the operation in the wider mode. This simplifies
8113 many range checks. */
8115 if (mode_width <= HOST_BITS_PER_WIDE_INT
8116 && subreg_lowpart_p (op0)
8117 && GET_CODE (SUBREG_REG (op0)) == PLUS
8118 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8119 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8120 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8121 < GET_MODE_MASK (mode) / 2)
8122 && (unsigned) const_op < GET_MODE_MASK (mode) / 2
8123 && (0 == (significant_bits (XEXP (SUBREG_REG (op0), 0),
8124 GET_MODE (SUBREG_REG (op0)))
8125 & ~ GET_MODE_MASK (mode))
8126 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8127 GET_MODE (SUBREG_REG (op0)))
8128 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8129 - GET_MODE_BITSIZE (mode)))))
8131 op0 = SUBREG_REG (op0);
8135 /* If the inner mode is narrower and we are extracting the low part,
8136 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8137 if (subreg_lowpart_p (op0)
8138 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8139 /* Fall through */ ;
8143 /* ... fall through ... */
8146 if ((unsigned_comparison_p || equality_comparison_p)
8147 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8148 <= HOST_BITS_PER_WIDE_INT)
8149 && ((unsigned HOST_WIDE_INT) const_op
8150 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8152 op0 = XEXP (op0, 0);
8158 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
8159 this for equality comparisons due to pathological cases involving
8161 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8162 && (tem = simplify_binary_operation (MINUS, mode, op1,
8163 XEXP (op0, 1))) != 0)
8165 op0 = XEXP (op0, 0);
8170 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8171 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8172 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8174 op0 = XEXP (XEXP (op0, 0), 0);
8175 code = (code == LT ? EQ : NE);
8181 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8182 of bits in X minus 1, is one iff X > 0. */
8183 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8184 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8185 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8186 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8188 op0 = XEXP (op0, 1);
8189 code = (code == GE ? LE : GT);
8195 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8196 if C is zero or B is a constant. */
8197 if (equality_comparison_p
8198 && 0 != (tem = simplify_binary_operation (XOR, mode,
8199 XEXP (op0, 1), op1)))
8201 op0 = XEXP (op0, 0);
8208 case LT: case LTU: case LE: case LEU:
8209 case GT: case GTU: case GE: case GEU:
8210 /* We can't do anything if OP0 is a condition code value, rather
8211 than an actual data value. */
8214 || XEXP (op0, 0) == cc0_rtx
8216 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8219 /* Get the two operands being compared. */
8220 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8221 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8223 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8225 /* Check for the cases where we simply want the result of the
8226 earlier test or the opposite of that result. */
8228 || (code == EQ && reversible_comparison_p (op0))
8229 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8230 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8231 && (STORE_FLAG_VALUE
8232 & (((HOST_WIDE_INT) 1
8233 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8235 || (code == GE && reversible_comparison_p (op0)))))
8237 code = (code == LT || code == NE
8238 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8239 op0 = tem, op1 = tem1;
8245 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8247 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8248 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8249 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8251 op0 = XEXP (op0, 1);
8252 code = (code == GE ? GT : LE);
8258 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8259 will be converted to a ZERO_EXTRACT later. */
8260 if (const_op == 0 && equality_comparison_p
8261 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8262 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8263 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8265 op0 = simplify_and_const_int
8266 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8268 XEXP (XEXP (op0, 0), 1)),
8273 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8274 zero and X is a comparison and C1 and C2 describe only bits set
8275 in STORE_FLAG_VALUE, we can compare with X. */
8276 if (const_op == 0 && equality_comparison_p
8277 && mode_width <= HOST_BITS_PER_WIDE_INT
8278 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8279 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8280 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8281 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8282 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8284 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8285 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8286 if ((~ STORE_FLAG_VALUE & mask) == 0
8287 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8288 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8289 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8291 op0 = XEXP (XEXP (op0, 0), 0);
8296 /* If we are doing an equality comparison of an AND of a bit equal
8297 to the sign bit, replace this with a LT or GE comparison of
8298 the underlying value. */
8299 if (equality_comparison_p
8301 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8302 && mode_width <= HOST_BITS_PER_WIDE_INT
8303 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8304 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8306 op0 = XEXP (op0, 0);
8307 code = (code == EQ ? GE : LT);
8311 /* If this AND operation is really a ZERO_EXTEND from a narrower
8312 mode, the constant fits within that mode, and this is either an
8313 equality or unsigned comparison, try to do this comparison in
8314 the narrower mode. */
8315 if ((equality_comparison_p || unsigned_comparison_p)
8316 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8317 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8318 & GET_MODE_MASK (mode))
8320 && const_op >> i == 0
8321 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8323 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8330 /* If we have (compare (xshift FOO N) (const_int C)) and
8331 the high order N bits of FOO (N+1 if an inequality comparison)
8332 are not significant, we can do this by comparing FOO with C
8333 shifted right N bits so long as the low-order N bits of C are
8335 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8336 && INTVAL (XEXP (op0, 1)) >= 0
8337 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8338 < HOST_BITS_PER_WIDE_INT)
8340 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8341 && mode_width <= HOST_BITS_PER_WIDE_INT
8342 && (significant_bits (XEXP (op0, 0), mode)
8343 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8344 + ! equality_comparison_p))) == 0)
8346 const_op >>= INTVAL (XEXP (op0, 1));
8347 op1 = GEN_INT (const_op);
8348 op0 = XEXP (op0, 0);
8352 /* If we are doing a sign bit comparison, it means we are testing
8353 a particular bit. Convert it to the appropriate AND. */
8354 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8355 && mode_width <= HOST_BITS_PER_WIDE_INT)
8357 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8360 - INTVAL (XEXP (op0, 1)))));
8361 code = (code == LT ? NE : EQ);
8365 /* If this an equality comparison with zero and we are shifting
8366 the low bit to the sign bit, we can convert this to an AND of the
8368 if (const_op == 0 && equality_comparison_p
8369 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8370 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8372 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8379 /* If this is an equality comparison with zero, we can do this
8380 as a logical shift, which might be much simpler. */
8381 if (equality_comparison_p && const_op == 0
8382 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8384 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8386 INTVAL (XEXP (op0, 1)));
8390 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8391 do the comparison in a narrower mode. */
8392 if (! unsigned_comparison_p
8393 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8394 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8395 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8396 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8397 MODE_INT, 1)) != BLKmode
8398 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8399 || ((unsigned HOST_WIDE_INT) - const_op
8400 <= GET_MODE_MASK (tmode))))
8402 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8406 /* ... fall through ... */
8408 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8409 the low order N bits of FOO are not significant, we can do this
8410 by comparing FOO with C shifted left N bits so long as no
8412 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8413 && INTVAL (XEXP (op0, 1)) >= 0
8414 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8415 && mode_width <= HOST_BITS_PER_WIDE_INT
8416 && (significant_bits (XEXP (op0, 0), mode)
8417 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8419 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8422 const_op <<= INTVAL (XEXP (op0, 1));
8423 op1 = GEN_INT (const_op);
8424 op0 = XEXP (op0, 0);
8428 /* If we are using this shift to extract just the sign bit, we
8429 can replace this with an LT or GE comparison. */
8431 && (equality_comparison_p || sign_bit_comparison_p)
8432 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8433 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8435 op0 = XEXP (op0, 0);
8436 code = (code == NE || code == GT ? LT : GE);
8445 /* Now make any compound operations involved in this comparison. Then,
8446 check for an outmost SUBREG on OP0 that isn't doing anything or is
8447 paradoxical. The latter case can only occur when it is known that the
8448 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8449 We can never remove a SUBREG for a non-equality comparison because the
8450 sign bit is in a different place in the underlying object. */
8452 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8453 op1 = make_compound_operation (op1, SET);
8455 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8456 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8457 && (code == NE || code == EQ)
8458 && ((GET_MODE_SIZE (GET_MODE (op0))
8459 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8461 op0 = SUBREG_REG (op0);
8462 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8465 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8466 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8467 && (code == NE || code == EQ)
8468 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8469 <= HOST_BITS_PER_WIDE_INT)
8470 && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8471 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8472 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8474 (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
8475 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8476 op0 = SUBREG_REG (op0), op1 = tem;
8478 /* We now do the opposite procedure: Some machines don't have compare
8479 insns in all modes. If OP0's mode is an integer mode smaller than a
8480 word and we can't do a compare in that mode, see if there is a larger
8481 mode for which we can do the compare. There are a number of cases in
8482 which we can use the wider mode. */
8484 mode = GET_MODE (op0);
8485 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8486 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8487 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8488 for (tmode = GET_MODE_WIDER_MODE (mode);
8490 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8491 tmode = GET_MODE_WIDER_MODE (tmode))
8492 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8494 /* If the only significant bits in OP0 and OP1 are those in the
8495 narrower mode and this is an equality or unsigned comparison,
8496 we can use the wider mode. Similarly for sign-extended
8497 values and equality or signed comparisons. */
8498 if (((code == EQ || code == NE
8499 || code == GEU || code == GTU || code == LEU || code == LTU)
8500 && ((significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode))
8502 && ((significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode))
8504 || ((code == EQ || code == NE
8505 || code == GE || code == GT || code == LE || code == LT)
8506 && (num_sign_bit_copies (op0, tmode)
8507 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8508 && (num_sign_bit_copies (op1, tmode)
8509 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8511 op0 = gen_lowpart_for_combine (tmode, op0);
8512 op1 = gen_lowpart_for_combine (tmode, op1);
8516 /* If this is a test for negative, we can make an explicit
8517 test of the sign bit. */
8519 if (op1 == const0_rtx && (code == LT || code == GE)
8520 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8522 op0 = gen_binary (AND, tmode,
8523 gen_lowpart_for_combine (tmode, op0),
8524 GEN_INT ((HOST_WIDE_INT) 1
8525 << (GET_MODE_BITSIZE (mode) - 1)));
8526 code = (code == LT) ? NE : EQ;
8537 /* Return 1 if we know that X, a comparison operation, is not operating
8538 on a floating-point value or is EQ or NE, meaning that we can safely
8542 reversible_comparison_p (x)
8545 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8546 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8549 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8555 x = get_last_value (XEXP (x, 0));
8556 return (x && GET_CODE (x) == COMPARE
8557 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8563 /* Utility function for following routine. Called when X is part of a value
8564 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8565 for each register mentioned. Similar to mention_regs in cse.c */
8568 update_table_tick (x)
8571 register enum rtx_code code = GET_CODE (x);
8572 register char *fmt = GET_RTX_FORMAT (code);
8577 int regno = REGNO (x);
8578 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8579 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8581 for (i = regno; i < endregno; i++)
8582 reg_last_set_table_tick[i] = label_tick;
8587 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8588 /* Note that we can't have an "E" in values stored; see
8589 get_last_value_validate. */
8591 update_table_tick (XEXP (x, i));
8594 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8595 are saying that the register is clobbered and we no longer know its
8596 value. If INSN is zero, don't update reg_last_set; this call is normally
8597 done with VALUE also zero to invalidate the register. */
8600 record_value_for_reg (reg, insn, value)
8605 int regno = REGNO (reg);
8606 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8607 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8610 /* If VALUE contains REG and we have a previous value for REG, substitute
8611 the previous value. */
8612 if (value && insn && reg_overlap_mentioned_p (reg, value))
8616 /* Set things up so get_last_value is allowed to see anything set up to
8618 subst_low_cuid = INSN_CUID (insn);
8619 tem = get_last_value (reg);
8622 value = replace_rtx (copy_rtx (value), reg, tem);
8625 /* For each register modified, show we don't know its value, that
8626 its value has been updated, and that we don't know the location of
8627 the death of the register. */
8628 for (i = regno; i < endregno; i ++)
8631 reg_last_set[i] = insn;
8632 reg_last_set_value[i] = 0;
8633 reg_last_death[i] = 0;
8636 /* Mark registers that are being referenced in this value. */
8638 update_table_tick (value);
8640 /* Now update the status of each register being set.
8641 If someone is using this register in this block, set this register
8642 to invalid since we will get confused between the two lives in this
8643 basic block. This makes using this register always invalid. In cse, we
8644 scan the table to invalidate all entries using this register, but this
8645 is too much work for us. */
8647 for (i = regno; i < endregno; i++)
8649 reg_last_set_label[i] = label_tick;
8650 if (value && reg_last_set_table_tick[i] == label_tick)
8651 reg_last_set_invalid[i] = 1;
8653 reg_last_set_invalid[i] = 0;
8656 /* The value being assigned might refer to X (like in "x++;"). In that
8657 case, we must replace it with (clobber (const_int 0)) to prevent
8659 if (value && ! get_last_value_validate (&value,
8660 reg_last_set_label[regno], 0))
8662 value = copy_rtx (value);
8663 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8667 /* For the main register being modified, update the value. */
8668 reg_last_set_value[regno] = value;
8672 /* Used for communication between the following two routines. */
8673 static rtx record_dead_insn;
8675 /* Called via note_stores from record_dead_and_set_regs to handle one
8676 SET or CLOBBER in an insn. */
8679 record_dead_and_set_regs_1 (dest, setter)
8682 if (GET_CODE (dest) == REG)
8684 /* If we are setting the whole register, we know its value. Otherwise
8685 show that we don't know the value. We can handle SUBREG in
8687 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8688 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8689 else if (GET_CODE (setter) == SET
8690 && GET_CODE (SET_DEST (setter)) == SUBREG
8691 && SUBREG_REG (SET_DEST (setter)) == dest
8692 && subreg_lowpart_p (SET_DEST (setter)))
8693 record_value_for_reg (dest, record_dead_insn,
8694 gen_lowpart_for_combine (GET_MODE (dest),
8697 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
8699 else if (GET_CODE (dest) == MEM
8700 /* Ignore pushes, they clobber nothing. */
8701 && ! push_operand (dest, GET_MODE (dest)))
8702 mem_last_set = INSN_CUID (record_dead_insn);
8705 /* Update the records of when each REG was most recently set or killed
8706 for the things done by INSN. This is the last thing done in processing
8707 INSN in the combiner loop.
8709 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8710 similar information mem_last_set (which insn most recently modified memory)
8711 and last_call_cuid (which insn was the most recent subroutine call). */
8714 record_dead_and_set_regs (insn)
8718 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8720 if (REG_NOTE_KIND (link) == REG_DEAD)
8721 reg_last_death[REGNO (XEXP (link, 0))] = insn;
8722 else if (REG_NOTE_KIND (link) == REG_INC)
8723 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
8726 if (GET_CODE (insn) == CALL_INSN)
8727 last_call_cuid = mem_last_set = INSN_CUID (insn);
8729 record_dead_insn = insn;
8730 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
8733 /* Utility routine for the following function. Verify that all the registers
8734 mentioned in *LOC are valid when *LOC was part of a value set when
8735 label_tick == TICK. Return 0 if some are not.
8737 If REPLACE is non-zero, replace the invalid reference with
8738 (clobber (const_int 0)) and return 1. This replacement is useful because
8739 we often can get useful information about the form of a value (e.g., if
8740 it was produced by a shift that always produces -1 or 0) even though
8741 we don't know exactly what registers it was produced from. */
8744 get_last_value_validate (loc, tick, replace)
8750 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
8751 int len = GET_RTX_LENGTH (GET_CODE (x));
8754 if (GET_CODE (x) == REG)
8756 int regno = REGNO (x);
8757 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8758 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8761 for (j = regno; j < endregno; j++)
8762 if (reg_last_set_invalid[j]
8763 /* If this is a pseudo-register that was only set once, it is
8765 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
8766 && reg_last_set_label[j] > tick))
8769 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8776 for (i = 0; i < len; i++)
8778 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
8779 /* Don't bother with these. They shouldn't occur anyway. */
8783 /* If we haven't found a reason for it to be invalid, it is valid. */
8787 /* Get the last value assigned to X, if known. Some registers
8788 in the value may be replaced with (clobber (const_int 0)) if their value
8789 is known longer known reliably. */
8798 /* If this is a non-paradoxical SUBREG, get the value of its operand and
8799 then convert it to the desired mode. If this is a paradoxical SUBREG,
8800 we cannot predict what values the "extra" bits might have. */
8801 if (GET_CODE (x) == SUBREG
8802 && subreg_lowpart_p (x)
8803 && (GET_MODE_SIZE (GET_MODE (x))
8804 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8805 && (value = get_last_value (SUBREG_REG (x))) != 0)
8806 return gen_lowpart_for_combine (GET_MODE (x), value);
8808 if (GET_CODE (x) != REG)
8812 value = reg_last_set_value[regno];
8814 /* If we don't have a value or if it isn't for this basic block, return 0. */
8817 || (reg_n_sets[regno] != 1
8818 && (reg_last_set_label[regno] != label_tick)))
8821 /* If the value was set in a later insn that the ones we are processing,
8822 we can't use it even if the register was only set once, but make a quick
8823 check to see if the previous insn set it to something. This is commonly
8824 the case when the same pseudo is used by repeated insns. */
8826 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
8830 for (insn = prev_nonnote_insn (subst_insn);
8831 insn && INSN_CUID (insn) >= subst_low_cuid;
8832 insn = prev_nonnote_insn (insn))
8836 && (set = single_set (insn)) != 0
8837 && rtx_equal_p (SET_DEST (set), x))
8839 value = SET_SRC (set);
8841 /* Make sure that VALUE doesn't reference X. Replace any
8842 expliit references with a CLOBBER. If there are any remaining
8843 references (rare), don't use the value. */
8845 if (reg_mentioned_p (x, value))
8846 value = replace_rtx (copy_rtx (value), x,
8847 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
8849 if (reg_overlap_mentioned_p (x, value))
8856 /* If the value has all its registers valid, return it. */
8857 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
8860 /* Otherwise, make a copy and replace any invalid register with
8861 (clobber (const_int 0)). If that fails for some reason, return 0. */
8863 value = copy_rtx (value);
8864 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
8870 /* Return nonzero if expression X refers to a REG or to memory
8871 that is set in an instruction more recent than FROM_CUID. */
8874 use_crosses_set_p (x, from_cuid)
8880 register enum rtx_code code = GET_CODE (x);
8884 register int regno = REGNO (x);
8885 #ifdef PUSH_ROUNDING
8886 /* Don't allow uses of the stack pointer to be moved,
8887 because we don't know whether the move crosses a push insn. */
8888 if (regno == STACK_POINTER_REGNUM)
8891 return (reg_last_set[regno]
8892 && INSN_CUID (reg_last_set[regno]) > from_cuid);
8895 if (code == MEM && mem_last_set > from_cuid)
8898 fmt = GET_RTX_FORMAT (code);
8900 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8905 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8906 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
8909 else if (fmt[i] == 'e'
8910 && use_crosses_set_p (XEXP (x, i), from_cuid))
8916 /* Define three variables used for communication between the following
8919 static int reg_dead_regno, reg_dead_endregno;
8920 static int reg_dead_flag;
8922 /* Function called via note_stores from reg_dead_at_p.
8924 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
8925 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
8928 reg_dead_at_p_1 (dest, x)
8932 int regno, endregno;
8934 if (GET_CODE (dest) != REG)
8937 regno = REGNO (dest);
8938 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8939 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
8941 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
8942 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
8945 /* Return non-zero if REG is known to be dead at INSN.
8947 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
8948 referencing REG, it is dead. If we hit a SET referencing REG, it is
8949 live. Otherwise, see if it is live or dead at the start of the basic
8953 reg_dead_at_p (reg, insn)
8959 /* Set variables for reg_dead_at_p_1. */
8960 reg_dead_regno = REGNO (reg);
8961 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
8962 ? HARD_REGNO_NREGS (reg_dead_regno,
8968 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
8969 beginning of function. */
8970 for (; insn && GET_CODE (insn) != CODE_LABEL;
8971 insn = prev_nonnote_insn (insn))
8973 note_stores (PATTERN (insn), reg_dead_at_p_1);
8975 return reg_dead_flag == 1 ? 1 : 0;
8977 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
8981 /* Get the basic block number that we were in. */
8986 for (block = 0; block < n_basic_blocks; block++)
8987 if (insn == basic_block_head[block])
8990 if (block == n_basic_blocks)
8994 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8995 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
8996 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9002 /* Remove register number REGNO from the dead registers list of INSN.
9004 Return the note used to record the death, if there was one. */
9007 remove_death (regno, insn)
9011 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9015 reg_n_deaths[regno]--;
9016 remove_note (insn, note);
9022 /* For each register (hardware or pseudo) used within expression X, if its
9023 death is in an instruction with cuid between FROM_CUID (inclusive) and
9024 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9025 list headed by PNOTES.
9027 This is done when X is being merged by combination into TO_INSN. These
9028 notes will then be distributed as needed. */
9031 move_deaths (x, from_cuid, to_insn, pnotes)
9038 register int len, i;
9039 register enum rtx_code code = GET_CODE (x);
9043 register int regno = REGNO (x);
9044 register rtx where_dead = reg_last_death[regno];
9046 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9047 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9049 rtx note = remove_death (regno, reg_last_death[regno]);
9051 /* It is possible for the call above to return 0. This can occur
9052 when reg_last_death points to I2 or I1 that we combined with.
9053 In that case make a new note. */
9057 XEXP (note, 1) = *pnotes;
9061 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9063 reg_n_deaths[regno]++;
9069 else if (GET_CODE (x) == SET)
9071 rtx dest = SET_DEST (x);
9073 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9075 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9076 that accesses one word of a multi-word item, some
9077 piece of everything register in the expression is used by
9078 this insn, so remove any old death. */
9080 if (GET_CODE (dest) == ZERO_EXTRACT
9081 || GET_CODE (dest) == STRICT_LOW_PART
9082 || (GET_CODE (dest) == SUBREG
9083 && (((GET_MODE_SIZE (GET_MODE (dest))
9084 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9085 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9086 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9088 move_deaths (dest, from_cuid, to_insn, pnotes);
9092 /* If this is some other SUBREG, we know it replaces the entire
9093 value, so use that as the destination. */
9094 if (GET_CODE (dest) == SUBREG)
9095 dest = SUBREG_REG (dest);
9097 /* If this is a MEM, adjust deaths of anything used in the address.
9098 For a REG (the only other possibility), the entire value is
9099 being replaced so the old value is not used in this insn. */
9101 if (GET_CODE (dest) == MEM)
9102 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9106 else if (GET_CODE (x) == CLOBBER)
9109 len = GET_RTX_LENGTH (code);
9110 fmt = GET_RTX_FORMAT (code);
9112 for (i = 0; i < len; i++)
9117 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9118 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9120 else if (fmt[i] == 'e')
9121 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9125 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9126 pattern of an insn. X must be a REG. */
9129 reg_bitfield_target_p (x, body)
9135 if (GET_CODE (body) == SET)
9137 rtx dest = SET_DEST (body);
9139 int regno, tregno, endregno, endtregno;
9141 if (GET_CODE (dest) == ZERO_EXTRACT)
9142 target = XEXP (dest, 0);
9143 else if (GET_CODE (dest) == STRICT_LOW_PART)
9144 target = SUBREG_REG (XEXP (dest, 0));
9148 if (GET_CODE (target) == SUBREG)
9149 target = SUBREG_REG (target);
9151 if (GET_CODE (target) != REG)
9154 tregno = REGNO (target), regno = REGNO (x);
9155 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9158 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9159 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9161 return endregno > tregno && regno < endtregno;
9164 else if (GET_CODE (body) == PARALLEL)
9165 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9166 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9172 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9173 as appropriate. I3 and I2 are the insns resulting from the combination
9174 insns including FROM (I2 may be zero).
9176 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9177 not need REG_DEAD notes because they are being substituted for. This
9178 saves searching in the most common cases.
9180 Each note in the list is either ignored or placed on some insns, depending
9181 on the type of note. */
9184 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9188 rtx elim_i2, elim_i1;
9190 rtx note, next_note;
9193 for (note = notes; note; note = next_note)
9195 rtx place = 0, place2 = 0;
9197 /* If this NOTE references a pseudo register, ensure it references
9198 the latest copy of that register. */
9199 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9200 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9201 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9203 next_note = XEXP (note, 1);
9204 switch (REG_NOTE_KIND (note))
9207 /* If this register is set or clobbered in I3, put the note there
9208 unless there is one already. */
9209 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9211 if (! (GET_CODE (XEXP (note, 0)) == REG
9212 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9213 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9216 /* Otherwise, if this register is used by I3, then this register
9217 now dies here, so we must put a REG_DEAD note here unless there
9219 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9220 && ! (GET_CODE (XEXP (note, 0)) == REG
9221 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9222 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9224 PUT_REG_NOTE_KIND (note, REG_DEAD);
9232 /* These notes say something about results of an insn. We can
9233 only support them if they used to be on I3 in which case they
9234 remain on I3. Otherwise they are ignored.
9236 If the note refers to an expression that is not a constant, we
9237 must also ignore the note since we cannot tell whether the
9238 equivalence is still true. It might be possible to do
9239 slightly better than this (we only have a problem if I2DEST
9240 or I1DEST is present in the expression), but it doesn't
9241 seem worth the trouble. */
9244 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9249 case REG_NO_CONFLICT:
9251 /* These notes say something about how a register is used. They must
9252 be present on any use of the register in I2 or I3. */
9253 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9256 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9266 /* It is too much trouble to try to see if this note is still
9267 correct in all situations. It is better to simply delete it. */
9271 /* If the insn previously containing this note still exists,
9272 put it back where it was. Otherwise move it to the previous
9273 insn. Adjust the corresponding REG_LIBCALL note. */
9274 if (GET_CODE (from_insn) != NOTE)
9278 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9279 place = prev_real_insn (from_insn);
9281 XEXP (tem, 0) = place;
9286 /* This is handled similarly to REG_RETVAL. */
9287 if (GET_CODE (from_insn) != NOTE)
9291 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9292 place = next_real_insn (from_insn);
9294 XEXP (tem, 0) = place;
9299 /* If the register is used as an input in I3, it dies there.
9300 Similarly for I2, if it is non-zero and adjacent to I3.
9302 If the register is not used as an input in either I3 or I2
9303 and it is not one of the registers we were supposed to eliminate,
9304 there are two possibilities. We might have a non-adjacent I2
9305 or we might have somehow eliminated an additional register
9306 from a computation. For example, we might have had A & B where
9307 we discover that B will always be zero. In this case we will
9308 eliminate the reference to A.
9310 In both cases, we must search to see if we can find a previous
9311 use of A and put the death note there. */
9313 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9315 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9316 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9319 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9322 /* If the register is used in both I2 and I3 and it dies in I3,
9323 we might have added another reference to it. If reg_n_refs
9324 was 2, bump it to 3. This has to be correct since the
9325 register must have been set somewhere. The reason this is
9326 done is because local-alloc.c treats 2 references as a
9329 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9330 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9331 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9332 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9335 for (tem = prev_nonnote_insn (i3);
9336 tem && (GET_CODE (tem) == INSN
9337 || GET_CODE (tem) == CALL_INSN);
9338 tem = prev_nonnote_insn (tem))
9340 /* If the register is being set at TEM, see if that is all
9341 TEM is doing. If so, delete TEM. Otherwise, make this
9342 into a REG_UNUSED note instead. */
9343 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9345 rtx set = single_set (tem);
9347 /* Verify that it was the set, and not a clobber that
9348 modified the register. */
9350 if (set != 0 && ! side_effects_p (SET_SRC (set))
9351 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9353 /* Move the notes and links of TEM elsewhere.
9354 This might delete other dead insns recursively.
9355 First set the pattern to something that won't use
9358 PATTERN (tem) = pc_rtx;
9360 distribute_notes (REG_NOTES (tem), tem, tem,
9361 NULL_RTX, NULL_RTX, NULL_RTX);
9362 distribute_links (LOG_LINKS (tem));
9364 PUT_CODE (tem, NOTE);
9365 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9366 NOTE_SOURCE_FILE (tem) = 0;
9370 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9372 /* If there isn't already a REG_UNUSED note, put one
9374 if (! find_regno_note (tem, REG_UNUSED,
9375 REGNO (XEXP (note, 0))))
9380 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9387 /* If the register is set or already dead at PLACE, we needn't do
9388 anything with this note if it is still a REG_DEAD note.
9390 Note that we cannot use just `dead_or_set_p' here since we can
9391 convert an assignment to a register into a bit-field assignment.
9392 Therefore, we must also omit the note if the register is the
9393 target of a bitfield assignment. */
9395 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9397 int regno = REGNO (XEXP (note, 0));
9399 if (dead_or_set_p (place, XEXP (note, 0))
9400 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9402 /* Unless the register previously died in PLACE, clear
9403 reg_last_death. [I no longer understand why this is
9405 if (reg_last_death[regno] != place)
9406 reg_last_death[regno] = 0;
9410 reg_last_death[regno] = place;
9412 /* If this is a death note for a hard reg that is occupying
9413 multiple registers, ensure that we are still using all
9414 parts of the object. If we find a piece of the object
9415 that is unused, we must add a USE for that piece before
9416 PLACE and put the appropriate REG_DEAD note on it.
9418 An alternative would be to put a REG_UNUSED for the pieces
9419 on the insn that set the register, but that can't be done if
9420 it is not in the same block. It is simpler, though less
9421 efficient, to add the USE insns. */
9423 if (place && regno < FIRST_PSEUDO_REGISTER
9424 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9427 = regno + HARD_REGNO_NREGS (regno,
9428 GET_MODE (XEXP (note, 0)));
9432 for (i = regno; i < endregno; i++)
9433 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9435 rtx piece = gen_rtx (REG, word_mode, i);
9438 /* See if we already placed a USE note for this
9439 register in front of PLACE. */
9441 GET_CODE (PREV_INSN (p)) == INSN
9442 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9444 if (rtx_equal_p (piece,
9445 XEXP (PATTERN (PREV_INSN (p)), 0)))
9454 = emit_insn_before (gen_rtx (USE, VOIDmode,
9457 REG_NOTES (use_insn)
9458 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9459 REG_NOTES (use_insn));
9467 /* Put only REG_DEAD notes for pieces that are
9468 still used and that are not already dead or set. */
9470 for (i = regno; i < endregno; i++)
9472 rtx piece = gen_rtx (REG, word_mode, i);
9474 if (reg_referenced_p (piece, PATTERN (place))
9475 && ! dead_or_set_p (place, piece)
9476 && ! reg_bitfield_target_p (piece,
9478 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9490 /* Any other notes should not be present at this point in the
9497 XEXP (note, 1) = REG_NOTES (place);
9498 REG_NOTES (place) = note;
9500 else if ((REG_NOTE_KIND (note) == REG_DEAD
9501 || REG_NOTE_KIND (note) == REG_UNUSED)
9502 && GET_CODE (XEXP (note, 0)) == REG)
9503 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9507 if ((REG_NOTE_KIND (note) == REG_DEAD
9508 || REG_NOTE_KIND (note) == REG_UNUSED)
9509 && GET_CODE (XEXP (note, 0)) == REG)
9510 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9512 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9513 XEXP (note, 0), REG_NOTES (place2));
9518 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9519 I3, I2, and I1 to new locations. This is also called in one case to
9520 add a link pointing at I3 when I3's destination is changed. */
9523 distribute_links (links)
9526 rtx link, next_link;
9528 for (link = links; link; link = next_link)
9534 next_link = XEXP (link, 1);
9536 /* If the insn that this link points to is a NOTE or isn't a single
9537 set, ignore it. In the latter case, it isn't clear what we
9538 can do other than ignore the link, since we can't tell which
9539 register it was for. Such links wouldn't be used by combine
9542 It is not possible for the destination of the target of the link to
9543 have been changed by combine. The only potential of this is if we
9544 replace I3, I2, and I1 by I3 and I2. But in that case the
9545 destination of I2 also remains unchanged. */
9547 if (GET_CODE (XEXP (link, 0)) == NOTE
9548 || (set = single_set (XEXP (link, 0))) == 0)
9551 reg = SET_DEST (set);
9552 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9553 || GET_CODE (reg) == SIGN_EXTRACT
9554 || GET_CODE (reg) == STRICT_LOW_PART)
9555 reg = XEXP (reg, 0);
9557 /* A LOG_LINK is defined as being placed on the first insn that uses
9558 a register and points to the insn that sets the register. Start
9559 searching at the next insn after the target of the link and stop
9560 when we reach a set of the register or the end of the basic block.
9562 Note that this correctly handles the link that used to point from
9563 I3 to I2. Also note that not much searching is typically done here
9564 since most links don't point very far away. */
9566 for (insn = NEXT_INSN (XEXP (link, 0));
9567 (insn && GET_CODE (insn) != CODE_LABEL
9568 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9569 insn = NEXT_INSN (insn))
9570 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9571 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9573 if (reg_referenced_p (reg, PATTERN (insn)))
9578 /* If we found a place to put the link, place it there unless there
9579 is already a link to the same insn as LINK at that point. */
9585 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9586 if (XEXP (link2, 0) == XEXP (link, 0))
9591 XEXP (link, 1) = LOG_LINKS (place);
9592 LOG_LINKS (place) = link;
9599 dump_combine_stats (file)
9604 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9605 combine_attempts, combine_merges, combine_extras, combine_successes);
9609 dump_combine_total_stats (file)
9614 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9615 total_attempts, total_merges, total_extras, total_successes);