1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
83 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
117 /* Vector mapping INSN_UIDs to cuids.
118 The cuids are like uids but increase monotonically always.
119 Combine always uses cuids so that it can compare them.
120 But actually renumbering the uids, which we used to do,
121 proves to be a bad idea because it makes it hard to compare
122 the dumps produced by earlier passes with those from later passes. */
124 static int *uid_cuid;
125 static int max_uid_cuid;
127 /* Get the cuid of an insn. */
129 #define INSN_CUID(INSN) \
130 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
132 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
133 BITS_PER_WORD would invoke undefined behavior. Work around it. */
135 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
136 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
138 #define nonzero_bits(X, M) \
139 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
141 #define num_sign_bit_copies(X, M) \
142 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno;
148 /* Record last point of death of (hard or pseudo) register n. */
150 static rtx *reg_last_death;
152 /* Record last point of modification of (hard or pseudo) register n. */
154 static rtx *reg_last_set;
156 /* Record the cuid of the last insn that invalidated memory
157 (anything that writes memory, and subroutine calls, but not pushes). */
159 static int mem_last_set;
161 /* Record the cuid of the last CALL_INSN
162 so we can tell whether a potential combination crosses any calls. */
164 static int last_call_cuid;
166 /* When `subst' is called, this is the insn that is being modified
167 (by combining in a previous insn). The PATTERN of this insn
168 is still the old pattern partially modified and it should not be
169 looked at, but this may be used to examine the successors of the insn
170 to judge whether a simplification is valid. */
172 static rtx subst_insn;
174 /* This is the lowest CUID that `subst' is currently dealing with.
175 get_last_value will not return a value if the register was set at or
176 after this CUID. If not for this mechanism, we could get confused if
177 I2 or I1 in try_combine were an insn that used the old value of a register
178 to obtain a new value. In that case, we might erroneously get the
179 new value of the register when we wanted the old one. */
181 static int subst_low_cuid;
183 /* This contains any hard registers that are used in newpat; reg_dead_at_p
184 must consider all these registers to be always live. */
186 static HARD_REG_SET newpat_used_regs;
188 /* This is an insn to which a LOG_LINKS entry has been added. If this
189 insn is the earlier than I2 or I3, combine should rescan starting at
192 static rtx added_links_insn;
194 /* Basic block in which we are performing combines. */
195 static basic_block this_basic_block;
197 /* A bitmap indicating which blocks had registers go dead at entry.
198 After combine, we'll need to re-do global life analysis with
199 those blocks as starting points. */
200 static sbitmap refresh_blocks;
202 /* The next group of arrays allows the recording of the last value assigned
203 to (hard or pseudo) register n. We use this information to see if an
204 operation being processed is redundant given a prior operation performed
205 on the register. For example, an `and' with a constant is redundant if
206 all the zero bits are already known to be turned off.
208 We use an approach similar to that used by cse, but change it in the
211 (1) We do not want to reinitialize at each label.
212 (2) It is useful, but not critical, to know the actual value assigned
213 to a register. Often just its form is helpful.
215 Therefore, we maintain the following arrays:
217 reg_last_set_value the last value assigned
218 reg_last_set_label records the value of label_tick when the
219 register was assigned
220 reg_last_set_table_tick records the value of label_tick when a
221 value using the register is assigned
222 reg_last_set_invalid set to nonzero when it is not valid
223 to use the value of this register in some
226 To understand the usage of these tables, it is important to understand
227 the distinction between the value in reg_last_set_value being valid
228 and the register being validly contained in some other expression in the
231 Entry I in reg_last_set_value is valid if it is nonzero, and either
232 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
234 Register I may validly appear in any expression returned for the value
235 of another register if reg_n_sets[i] is 1. It may also appear in the
236 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
237 reg_last_set_invalid[j] is zero.
239 If an expression is found in the table containing a register which may
240 not validly appear in an expression, the register is replaced by
241 something that won't match, (clobber (const_int 0)).
243 reg_last_set_invalid[i] is set nonzero when register I is being assigned
244 to and reg_last_set_table_tick[i] == label_tick. */
246 /* Record last value assigned to (hard or pseudo) register n. */
248 static rtx *reg_last_set_value;
250 /* Record the value of label_tick when the value for register n is placed in
251 reg_last_set_value[n]. */
253 static int *reg_last_set_label;
255 /* Record the value of label_tick when an expression involving register n
256 is placed in reg_last_set_value. */
258 static int *reg_last_set_table_tick;
260 /* Set nonzero if references to register n in expressions should not be
263 static char *reg_last_set_invalid;
265 /* Incremented for each label. */
267 static int label_tick;
269 /* Some registers that are set more than once and used in more than one
270 basic block are nevertheless always set in similar ways. For example,
271 a QImode register may be loaded from memory in two places on a machine
272 where byte loads zero extend.
274 We record in the following array what we know about the nonzero
275 bits of a register, specifically which bits are known to be zero.
277 If an entry is zero, it means that we don't know anything special. */
279 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
281 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
282 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
284 static enum machine_mode nonzero_bits_mode;
286 /* Nonzero if we know that a register has some leading bits that are always
287 equal to the sign bit. */
289 static unsigned char *reg_sign_bit_copies;
291 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
292 It is zero while computing them and after combine has completed. This
293 former test prevents propagating values based on previously set values,
294 which can be incorrect if a variable is modified in a loop. */
296 static int nonzero_sign_valid;
298 /* These arrays are maintained in parallel with reg_last_set_value
299 and are used to store the mode in which the register was last set,
300 the bits that were known to be zero when it was last set, and the
301 number of sign bits copies it was known to have when it was last set. */
303 static enum machine_mode *reg_last_set_mode;
304 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
305 static char *reg_last_set_sign_bit_copies;
307 /* Record one modification to rtl structure
308 to be undone by storing old_contents into *where.
309 is_int is 1 if the contents are an int. */
315 union {rtx r; int i;} old_contents;
316 union {rtx *r; int *i;} where;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too. */
332 static struct undobuf undobuf;
334 /* Number of times the pseudo being substituted for
335 was found and replaced. */
337 static int n_occurrences;
339 static void do_SUBST (rtx *, rtx);
340 static void do_SUBST_INT (int *, int);
341 static void init_reg_last_arrays (void);
342 static void setup_incoming_promotions (void);
343 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
344 static int cant_combine_insn_p (rtx);
345 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
346 static int sets_function_arg_p (rtx);
347 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
348 static int contains_muldiv (rtx);
349 static rtx try_combine (rtx, rtx, rtx, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx *find_split_point (rtx *, rtx);
353 static rtx subst (rtx, rtx, rtx, int, int);
354 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
355 static rtx simplify_if_then_else (rtx);
356 static rtx simplify_set (rtx);
357 static rtx simplify_logical (rtx, int);
358 static rtx expand_compound_operation (rtx);
359 static rtx expand_field_assignment (rtx);
360 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
361 rtx, unsigned HOST_WIDE_INT, int, int, int);
362 static rtx extract_left_shift (rtx, int);
363 static rtx make_compound_operation (rtx, enum rtx_code);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
365 unsigned HOST_WIDE_INT *);
366 static rtx force_to_mode (rtx, enum machine_mode,
367 unsigned HOST_WIDE_INT, rtx, int);
368 static rtx if_then_else_cond (rtx, rtx *, rtx *);
369 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
370 static int rtx_equal_for_field_assignment_p (rtx, rtx);
371 static rtx make_field_assignment (rtx);
372 static rtx apply_distributive_law (rtx);
373 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
374 unsigned HOST_WIDE_INT);
375 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
376 rtx, enum machine_mode,
377 unsigned HOST_WIDE_INT);
378 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
380 unsigned HOST_WIDE_INT);
381 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
384 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
385 enum machine_mode, unsigned int);
386 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
387 HOST_WIDE_INT, enum machine_mode, int *);
388 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
390 static int recog_for_combine (rtx *, rtx, rtx *);
391 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
392 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
393 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
394 static void update_table_tick (rtx);
395 static void record_value_for_reg (rtx, rtx, rtx);
396 static void check_promoted_subreg (rtx, rtx);
397 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
398 static void record_dead_and_set_regs (rtx);
399 static int get_last_value_validate (rtx *, rtx, int, int);
400 static rtx get_last_value (rtx);
401 static int use_crosses_set_p (rtx, int);
402 static void reg_dead_at_p_1 (rtx, rtx, void *);
403 static int reg_dead_at_p (rtx, rtx);
404 static void move_deaths (rtx, rtx, int, rtx, rtx *);
405 static int reg_bitfield_target_p (rtx, rtx);
406 static void distribute_notes (rtx, rtx, rtx, rtx);
407 static void distribute_links (rtx);
408 static void mark_used_regs_combine (rtx);
409 static int insn_cuid (rtx);
410 static void record_promoted_value (rtx, rtx);
411 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
412 static enum rtx_code combine_reversed_comparison_code (rtx);
414 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
415 insn. The substitution can be undone by undo_all. If INTO is already
416 set to NEWVAL, do not record this change. Because computing NEWVAL might
417 also call SUBST, we have to compute it before we put anything into
421 do_SUBST (rtx *into, rtx newval)
426 if (oldval == newval)
429 /* We'd like to catch as many invalid transformations here as
430 possible. Unfortunately, there are way too many mode changes
431 that are perfectly valid, so we'd waste too much effort for
432 little gain doing the checks here. Focus on catching invalid
433 transformations involving integer constants. */
434 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
435 && GET_CODE (newval) == CONST_INT)
437 /* Sanity check that we're replacing oldval with a CONST_INT
438 that is a valid sign-extension for the original mode. */
439 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
443 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
444 CONST_INT is not valid, because after the replacement, the
445 original mode would be gone. Unfortunately, we can't tell
446 when do_SUBST is called to replace the operand thereof, so we
447 perform this test on oldval instead, checking whether an
448 invalid replacement took place before we got here. */
449 if ((GET_CODE (oldval) == SUBREG
450 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
451 || (GET_CODE (oldval) == ZERO_EXTEND
452 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
457 buf = undobuf.frees, undobuf.frees = buf->next;
459 buf = xmalloc (sizeof (struct undo));
463 buf->old_contents.r = oldval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
471 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
472 for the value of a HOST_WIDE_INT value (including CONST_INT) is
476 do_SUBST_INT (int *into, int newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return nonzero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (rtx f, unsigned int nregs)
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT));
524 reg_sign_bit_copies = xcalloc (nregs, sizeof (unsigned char));
526 reg_last_death = xmalloc (nregs * sizeof (rtx));
527 reg_last_set = xmalloc (nregs * sizeof (rtx));
528 reg_last_set_value = xmalloc (nregs * sizeof (rtx));
529 reg_last_set_table_tick = xmalloc (nregs * sizeof (int));
530 reg_last_set_label = xmalloc (nregs * sizeof (int));
531 reg_last_set_invalid = xmalloc (nregs * sizeof (char));
532 reg_last_set_mode = xmalloc (nregs * sizeof (enum machine_mode));
533 reg_last_set_nonzero_bits = xmalloc (nregs * sizeof (HOST_WIDE_INT));
534 reg_last_set_sign_bit_copies = xmalloc (nregs * sizeof (char));
536 init_reg_last_arrays ();
538 init_recog_no_volatile ();
540 /* Compute maximum uid value so uid_cuid can be allocated. */
542 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
543 if (INSN_UID (insn) > i)
546 uid_cuid = xmalloc ((i + 1) * sizeof (int));
549 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
551 /* Don't use reg_nonzero_bits when computing it. This can cause problems
552 when, for example, we have j <<= 1 in a loop. */
554 nonzero_sign_valid = 0;
556 /* Compute the mapping from uids to cuids.
557 Cuids are numbers assigned to insns, like uids,
558 except that cuids increase monotonically through the code.
560 Scan all SETs and see if we can deduce anything about what
561 bits are known to be zero for some registers and how many copies
562 of the sign bit are known to exist for those registers.
564 Also set any known values so that we can use it while searching
565 for what bits are known to be set. */
569 setup_incoming_promotions ();
571 refresh_blocks = sbitmap_alloc (last_basic_block);
572 sbitmap_zero (refresh_blocks);
574 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
576 uid_cuid[INSN_UID (insn)] = ++i;
582 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
584 record_dead_and_set_regs (insn);
587 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
588 if (REG_NOTE_KIND (links) == REG_INC)
589 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
594 if (GET_CODE (insn) == CODE_LABEL)
598 nonzero_sign_valid = 1;
600 /* Now scan all the insns in forward order. */
605 init_reg_last_arrays ();
606 setup_incoming_promotions ();
608 FOR_EACH_BB (this_basic_block)
610 for (insn = this_basic_block->head;
611 insn != NEXT_INSN (this_basic_block->end);
612 insn = next ? next : NEXT_INSN (insn))
616 if (GET_CODE (insn) == CODE_LABEL)
619 else if (INSN_P (insn))
621 /* See if we know about function return values before this
622 insn based upon SUBREG flags. */
623 check_promoted_subreg (insn, PATTERN (insn));
625 /* Try this insn with each insn it links back to. */
627 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
628 if ((next = try_combine (insn, XEXP (links, 0),
629 NULL_RTX, &new_direct_jump_p)) != 0)
632 /* Try each sequence of three linked insns ending with this one. */
634 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
636 rtx link = XEXP (links, 0);
638 /* If the linked insn has been replaced by a note, then there
639 is no point in pursuing this chain any further. */
640 if (GET_CODE (link) == NOTE)
643 for (nextlinks = LOG_LINKS (link);
645 nextlinks = XEXP (nextlinks, 1))
646 if ((next = try_combine (insn, link,
648 &new_direct_jump_p)) != 0)
653 /* Try to combine a jump insn that uses CC0
654 with a preceding insn that sets CC0, and maybe with its
655 logical predecessor as well.
656 This is how we make decrement-and-branch insns.
657 We need this special code because data flow connections
658 via CC0 do not get entered in LOG_LINKS. */
660 if (GET_CODE (insn) == JUMP_INSN
661 && (prev = prev_nonnote_insn (insn)) != 0
662 && GET_CODE (prev) == INSN
663 && sets_cc0_p (PATTERN (prev)))
665 if ((next = try_combine (insn, prev,
666 NULL_RTX, &new_direct_jump_p)) != 0)
669 for (nextlinks = LOG_LINKS (prev); nextlinks;
670 nextlinks = XEXP (nextlinks, 1))
671 if ((next = try_combine (insn, prev,
673 &new_direct_jump_p)) != 0)
677 /* Do the same for an insn that explicitly references CC0. */
678 if (GET_CODE (insn) == INSN
679 && (prev = prev_nonnote_insn (insn)) != 0
680 && GET_CODE (prev) == INSN
681 && sets_cc0_p (PATTERN (prev))
682 && GET_CODE (PATTERN (insn)) == SET
683 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
685 if ((next = try_combine (insn, prev,
686 NULL_RTX, &new_direct_jump_p)) != 0)
689 for (nextlinks = LOG_LINKS (prev); nextlinks;
690 nextlinks = XEXP (nextlinks, 1))
691 if ((next = try_combine (insn, prev,
693 &new_direct_jump_p)) != 0)
697 /* Finally, see if any of the insns that this insn links to
698 explicitly references CC0. If so, try this insn, that insn,
699 and its predecessor if it sets CC0. */
700 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
701 if (GET_CODE (XEXP (links, 0)) == INSN
702 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
703 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
704 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
705 && GET_CODE (prev) == INSN
706 && sets_cc0_p (PATTERN (prev))
707 && (next = try_combine (insn, XEXP (links, 0),
708 prev, &new_direct_jump_p)) != 0)
712 /* Try combining an insn with two different insns whose results it
714 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
715 for (nextlinks = XEXP (links, 1); nextlinks;
716 nextlinks = XEXP (nextlinks, 1))
717 if ((next = try_combine (insn, XEXP (links, 0),
719 &new_direct_jump_p)) != 0)
722 if (GET_CODE (insn) != NOTE)
723 record_dead_and_set_regs (insn);
732 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
733 BASIC_BLOCK (i)->flags |= BB_DIRTY);
734 new_direct_jump_p |= purge_all_dead_edges (0);
735 delete_noop_moves (f);
737 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
738 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
739 | PROP_KILL_DEAD_CODE);
742 sbitmap_free (refresh_blocks);
743 free (reg_nonzero_bits);
744 free (reg_sign_bit_copies);
745 free (reg_last_death);
747 free (reg_last_set_value);
748 free (reg_last_set_table_tick);
749 free (reg_last_set_label);
750 free (reg_last_set_invalid);
751 free (reg_last_set_mode);
752 free (reg_last_set_nonzero_bits);
753 free (reg_last_set_sign_bit_copies);
757 struct undo *undo, *next;
758 for (undo = undobuf.frees; undo; undo = next)
766 total_attempts += combine_attempts;
767 total_merges += combine_merges;
768 total_extras += combine_extras;
769 total_successes += combine_successes;
771 nonzero_sign_valid = 0;
773 /* Make recognizer allow volatile MEMs again. */
776 return new_direct_jump_p;
779 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
782 init_reg_last_arrays (void)
784 unsigned int nregs = combine_max_regno;
786 memset (reg_last_death, 0, nregs * sizeof (rtx));
787 memset (reg_last_set, 0, nregs * sizeof (rtx));
788 memset (reg_last_set_value, 0, nregs * sizeof (rtx));
789 memset (reg_last_set_table_tick, 0, nregs * sizeof (int));
790 memset (reg_last_set_label, 0, nregs * sizeof (int));
791 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
792 memset (reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
793 memset (reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
794 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
797 /* Set up any promoted values for incoming argument registers. */
800 setup_incoming_promotions (void)
802 #ifdef PROMOTE_FUNCTION_ARGS
805 enum machine_mode mode;
807 rtx first = get_insns ();
809 #ifndef OUTGOING_REGNO
810 #define OUTGOING_REGNO(N) N
812 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
813 /* Check whether this register can hold an incoming pointer
814 argument. FUNCTION_ARG_REGNO_P tests outgoing register
815 numbers, so translate if necessary due to register windows. */
816 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
817 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
820 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
823 gen_rtx_CLOBBER (mode, const0_rtx)));
828 /* Called via note_stores. If X is a pseudo that is narrower than
829 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
831 If we are setting only a portion of X and we can't figure out what
832 portion, assume all bits will be used since we don't know what will
835 Similarly, set how many bits of X are known to be copies of the sign bit
836 at all locations in the function. This is the smallest number implied
840 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
841 void *data ATTRIBUTE_UNUSED)
845 if (GET_CODE (x) == REG
846 && REGNO (x) >= FIRST_PSEUDO_REGISTER
847 /* If this register is undefined at the start of the file, we can't
848 say what its contents were. */
849 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
850 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
852 if (set == 0 || GET_CODE (set) == CLOBBER)
854 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
855 reg_sign_bit_copies[REGNO (x)] = 1;
859 /* If this is a complex assignment, see if we can convert it into a
860 simple assignment. */
861 set = expand_field_assignment (set);
863 /* If this is a simple assignment, or we have a paradoxical SUBREG,
864 set what we know about X. */
866 if (SET_DEST (set) == x
867 || (GET_CODE (SET_DEST (set)) == SUBREG
868 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
869 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
870 && SUBREG_REG (SET_DEST (set)) == x))
872 rtx src = SET_SRC (set);
874 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
875 /* If X is narrower than a word and SRC is a non-negative
876 constant that would appear negative in the mode of X,
877 sign-extend it for use in reg_nonzero_bits because some
878 machines (maybe most) will actually do the sign-extension
879 and this is the conservative approach.
881 ??? For 2.5, try to tighten up the MD files in this regard
882 instead of this kludge. */
884 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
885 && GET_CODE (src) == CONST_INT
887 && 0 != (INTVAL (src)
889 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
890 src = GEN_INT (INTVAL (src)
891 | ((HOST_WIDE_INT) (-1)
892 << GET_MODE_BITSIZE (GET_MODE (x))));
895 /* Don't call nonzero_bits if it cannot change anything. */
896 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
897 reg_nonzero_bits[REGNO (x)]
898 |= nonzero_bits (src, nonzero_bits_mode);
899 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
900 if (reg_sign_bit_copies[REGNO (x)] == 0
901 || reg_sign_bit_copies[REGNO (x)] > num)
902 reg_sign_bit_copies[REGNO (x)] = num;
906 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
907 reg_sign_bit_copies[REGNO (x)] = 1;
912 /* See if INSN can be combined into I3. PRED and SUCC are optionally
913 insns that were previously combined into I3 or that will be combined
914 into the merger of INSN and I3.
916 Return 0 if the combination is not allowed for any reason.
918 If the combination is allowed, *PDEST will be set to the single
919 destination of INSN and *PSRC to the single source, and this function
923 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
924 rtx *pdest, rtx *psrc)
927 rtx set = 0, src, dest;
932 int all_adjacent = (succ ? (next_active_insn (insn) == succ
933 && next_active_insn (succ) == i3)
934 : next_active_insn (insn) == i3);
936 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
937 or a PARALLEL consisting of such a SET and CLOBBERs.
939 If INSN has CLOBBER parallel parts, ignore them for our processing.
940 By definition, these happen during the execution of the insn. When it
941 is merged with another insn, all bets are off. If they are, in fact,
942 needed and aren't also supplied in I3, they may be added by
943 recog_for_combine. Otherwise, it won't match.
945 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
948 Get the source and destination of INSN. If more than one, can't
951 if (GET_CODE (PATTERN (insn)) == SET)
952 set = PATTERN (insn);
953 else if (GET_CODE (PATTERN (insn)) == PARALLEL
954 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
956 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
958 rtx elt = XVECEXP (PATTERN (insn), 0, i);
960 switch (GET_CODE (elt))
962 /* This is important to combine floating point insns
965 /* Combining an isolated USE doesn't make sense.
966 We depend here on combinable_i3pat to reject them. */
967 /* The code below this loop only verifies that the inputs of
968 the SET in INSN do not change. We call reg_set_between_p
969 to verify that the REG in the USE does not change between
971 If the USE in INSN was for a pseudo register, the matching
972 insn pattern will likely match any register; combining this
973 with any other USE would only be safe if we knew that the
974 used registers have identical values, or if there was
975 something to tell them apart, e.g. different modes. For
976 now, we forgo such complicated tests and simply disallow
977 combining of USES of pseudo registers with any other USE. */
978 if (GET_CODE (XEXP (elt, 0)) == REG
979 && GET_CODE (PATTERN (i3)) == PARALLEL)
981 rtx i3pat = PATTERN (i3);
982 int i = XVECLEN (i3pat, 0) - 1;
983 unsigned int regno = REGNO (XEXP (elt, 0));
987 rtx i3elt = XVECEXP (i3pat, 0, i);
989 if (GET_CODE (i3elt) == USE
990 && GET_CODE (XEXP (i3elt, 0)) == REG
991 && (REGNO (XEXP (i3elt, 0)) == regno
992 ? reg_set_between_p (XEXP (elt, 0),
993 PREV_INSN (insn), i3)
994 : regno >= FIRST_PSEUDO_REGISTER))
1001 /* We can ignore CLOBBERs. */
1006 /* Ignore SETs whose result isn't used but not those that
1007 have side-effects. */
1008 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1009 && ! side_effects_p (elt))
1012 /* If we have already found a SET, this is a second one and
1013 so we cannot combine with this insn. */
1021 /* Anything else means we can't combine. */
1027 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1028 so don't do anything with it. */
1029 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1038 set = expand_field_assignment (set);
1039 src = SET_SRC (set), dest = SET_DEST (set);
1041 /* Don't eliminate a store in the stack pointer. */
1042 if (dest == stack_pointer_rtx
1043 /* Don't combine with an insn that sets a register to itself if it has
1044 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1045 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1046 /* Can't merge an ASM_OPERANDS. */
1047 || GET_CODE (src) == ASM_OPERANDS
1048 /* Can't merge a function call. */
1049 || GET_CODE (src) == CALL
1050 /* Don't eliminate a function call argument. */
1051 || (GET_CODE (i3) == CALL_INSN
1052 && (find_reg_fusage (i3, USE, dest)
1053 || (GET_CODE (dest) == REG
1054 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1055 && global_regs[REGNO (dest)])))
1056 /* Don't substitute into an incremented register. */
1057 || FIND_REG_INC_NOTE (i3, dest)
1058 || (succ && FIND_REG_INC_NOTE (succ, dest))
1060 /* Don't combine the end of a libcall into anything. */
1061 /* ??? This gives worse code, and appears to be unnecessary, since no
1062 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1063 use REG_RETVAL notes for noconflict blocks, but other code here
1064 makes sure that those insns don't disappear. */
1065 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1067 /* Make sure that DEST is not used after SUCC but before I3. */
1068 || (succ && ! all_adjacent
1069 && reg_used_between_p (dest, succ, i3))
1070 /* Make sure that the value that is to be substituted for the register
1071 does not use any registers whose values alter in between. However,
1072 If the insns are adjacent, a use can't cross a set even though we
1073 think it might (this can happen for a sequence of insns each setting
1074 the same destination; reg_last_set of that register might point to
1075 a NOTE). If INSN has a REG_EQUIV note, the register is always
1076 equivalent to the memory so the substitution is valid even if there
1077 are intervening stores. Also, don't move a volatile asm or
1078 UNSPEC_VOLATILE across any other insns. */
1080 && (((GET_CODE (src) != MEM
1081 || ! find_reg_note (insn, REG_EQUIV, src))
1082 && use_crosses_set_p (src, INSN_CUID (insn)))
1083 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1084 || GET_CODE (src) == UNSPEC_VOLATILE))
1085 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1086 better register allocation by not doing the combine. */
1087 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1088 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1089 /* Don't combine across a CALL_INSN, because that would possibly
1090 change whether the life span of some REGs crosses calls or not,
1091 and it is a pain to update that information.
1092 Exception: if source is a constant, moving it later can't hurt.
1093 Accept that special case, because it helps -fforce-addr a lot. */
1094 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1097 /* DEST must either be a REG or CC0. */
1098 if (GET_CODE (dest) == REG)
1100 /* If register alignment is being enforced for multi-word items in all
1101 cases except for parameters, it is possible to have a register copy
1102 insn referencing a hard register that is not allowed to contain the
1103 mode being copied and which would not be valid as an operand of most
1104 insns. Eliminate this problem by not combining with such an insn.
1106 Also, on some machines we don't want to extend the life of a hard
1109 if (GET_CODE (src) == REG
1110 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1111 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1112 /* Don't extend the life of a hard register unless it is
1113 user variable (if we have few registers) or it can't
1114 fit into the desired register (meaning something special
1116 Also avoid substituting a return register into I3, because
1117 reload can't handle a conflict with constraints of other
1119 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1120 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1123 else if (GET_CODE (dest) != CC0)
1126 /* Don't substitute for a register intended as a clobberable operand.
1127 Similarly, don't substitute an expression containing a register that
1128 will be clobbered in I3. */
1129 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1130 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1131 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1132 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1134 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1137 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1138 or not), reject, unless nothing volatile comes between it and I3 */
1140 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1142 /* Make sure succ doesn't contain a volatile reference. */
1143 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1146 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1147 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1151 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1152 to be an explicit register variable, and was chosen for a reason. */
1154 if (GET_CODE (src) == ASM_OPERANDS
1155 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1158 /* If there are any volatile insns between INSN and I3, reject, because
1159 they might affect machine state. */
1161 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1162 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1165 /* If INSN or I2 contains an autoincrement or autodecrement,
1166 make sure that register is not used between there and I3,
1167 and not already used in I3 either.
1168 Also insist that I3 not be a jump; if it were one
1169 and the incremented register were spilled, we would lose. */
1172 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1173 if (REG_NOTE_KIND (link) == REG_INC
1174 && (GET_CODE (i3) == JUMP_INSN
1175 || reg_used_between_p (XEXP (link, 0), insn, i3)
1176 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1181 /* Don't combine an insn that follows a CC0-setting insn.
1182 An insn that uses CC0 must not be separated from the one that sets it.
1183 We do, however, allow I2 to follow a CC0-setting insn if that insn
1184 is passed as I1; in that case it will be deleted also.
1185 We also allow combining in this case if all the insns are adjacent
1186 because that would leave the two CC0 insns adjacent as well.
1187 It would be more logical to test whether CC0 occurs inside I1 or I2,
1188 but that would be much slower, and this ought to be equivalent. */
1190 p = prev_nonnote_insn (insn);
1191 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1196 /* If we get here, we have passed all the tests and the combination is
1205 /* Check if PAT is an insn - or a part of it - used to set up an
1206 argument for a function in a hard register. */
1209 sets_function_arg_p (rtx pat)
1214 switch (GET_CODE (pat))
1217 return sets_function_arg_p (PATTERN (pat));
1220 for (i = XVECLEN (pat, 0); --i >= 0;)
1221 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1227 inner_dest = SET_DEST (pat);
1228 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1229 || GET_CODE (inner_dest) == SUBREG
1230 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1231 inner_dest = XEXP (inner_dest, 0);
1233 return (GET_CODE (inner_dest) == REG
1234 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1235 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1244 /* LOC is the location within I3 that contains its pattern or the component
1245 of a PARALLEL of the pattern. We validate that it is valid for combining.
1247 One problem is if I3 modifies its output, as opposed to replacing it
1248 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1249 so would produce an insn that is not equivalent to the original insns.
1253 (set (reg:DI 101) (reg:DI 100))
1254 (set (subreg:SI (reg:DI 101) 0) <foo>)
1256 This is NOT equivalent to:
1258 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1259 (set (reg:DI 101) (reg:DI 100))])
1261 Not only does this modify 100 (in which case it might still be valid
1262 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1264 We can also run into a problem if I2 sets a register that I1
1265 uses and I1 gets directly substituted into I3 (not via I2). In that
1266 case, we would be getting the wrong value of I2DEST into I3, so we
1267 must reject the combination. This case occurs when I2 and I1 both
1268 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1269 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1270 of a SET must prevent combination from occurring.
1272 Before doing the above check, we first try to expand a field assignment
1273 into a set of logical operations.
1275 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1276 we place a register that is both set and used within I3. If more than one
1277 such register is detected, we fail.
1279 Return 1 if the combination is valid, zero otherwise. */
1282 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1283 int i1_not_in_src, rtx *pi3dest_killed)
1287 if (GET_CODE (x) == SET)
1290 rtx dest = SET_DEST (set);
1291 rtx src = SET_SRC (set);
1292 rtx inner_dest = dest;
1294 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1295 || GET_CODE (inner_dest) == SUBREG
1296 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1297 inner_dest = XEXP (inner_dest, 0);
1299 /* Check for the case where I3 modifies its output, as discussed
1300 above. We don't want to prevent pseudos from being combined
1301 into the address of a MEM, so only prevent the combination if
1302 i1 or i2 set the same MEM. */
1303 if ((inner_dest != dest &&
1304 (GET_CODE (inner_dest) != MEM
1305 || rtx_equal_p (i2dest, inner_dest)
1306 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1307 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1308 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1310 /* This is the same test done in can_combine_p except we can't test
1311 all_adjacent; we don't have to, since this instruction will stay
1312 in place, thus we are not considering increasing the lifetime of
1315 Also, if this insn sets a function argument, combining it with
1316 something that might need a spill could clobber a previous
1317 function argument; the all_adjacent test in can_combine_p also
1318 checks this; here, we do a more specific test for this case. */
1320 || (GET_CODE (inner_dest) == REG
1321 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1322 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1323 GET_MODE (inner_dest))))
1324 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1327 /* If DEST is used in I3, it is being killed in this insn,
1328 so record that for later.
1329 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1330 STACK_POINTER_REGNUM, since these are always considered to be
1331 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1332 if (pi3dest_killed && GET_CODE (dest) == REG
1333 && reg_referenced_p (dest, PATTERN (i3))
1334 && REGNO (dest) != FRAME_POINTER_REGNUM
1335 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1336 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1338 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && (REGNO (dest) != ARG_POINTER_REGNUM
1340 || ! fixed_regs [REGNO (dest)])
1342 && REGNO (dest) != STACK_POINTER_REGNUM)
1344 if (*pi3dest_killed)
1347 *pi3dest_killed = dest;
1351 else if (GET_CODE (x) == PARALLEL)
1355 for (i = 0; i < XVECLEN (x, 0); i++)
1356 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1357 i1_not_in_src, pi3dest_killed))
1364 /* Return 1 if X is an arithmetic expression that contains a multiplication
1365 and division. We don't count multiplications by powers of two here. */
1368 contains_muldiv (rtx x)
1370 switch (GET_CODE (x))
1372 case MOD: case DIV: case UMOD: case UDIV:
1376 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1377 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1379 switch (GET_RTX_CLASS (GET_CODE (x)))
1381 case 'c': case '<': case '2':
1382 return contains_muldiv (XEXP (x, 0))
1383 || contains_muldiv (XEXP (x, 1));
1386 return contains_muldiv (XEXP (x, 0));
1394 /* Determine whether INSN can be used in a combination. Return nonzero if
1395 not. This is used in try_combine to detect early some cases where we
1396 can't perform combinations. */
1399 cant_combine_insn_p (rtx insn)
1404 /* If this isn't really an insn, we can't do anything.
1405 This can occur when flow deletes an insn that it has merged into an
1406 auto-increment address. */
1407 if (! INSN_P (insn))
1410 /* Never combine loads and stores involving hard regs that are likely
1411 to be spilled. The register allocator can usually handle such
1412 reg-reg moves by tying. If we allow the combiner to make
1413 substitutions of likely-spilled regs, we may abort in reload.
1414 As an exception, we allow combinations involving fixed regs; these are
1415 not available to the register allocator so there's no risk involved. */
1417 set = single_set (insn);
1420 src = SET_SRC (set);
1421 dest = SET_DEST (set);
1422 if (GET_CODE (src) == SUBREG)
1423 src = SUBREG_REG (src);
1424 if (GET_CODE (dest) == SUBREG)
1425 dest = SUBREG_REG (dest);
1426 if (REG_P (src) && REG_P (dest)
1427 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1428 && ! fixed_regs[REGNO (src)]
1429 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1430 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs[REGNO (dest)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1438 /* Try to combine the insns I1 and I2 into I3.
1439 Here I1 and I2 appear earlier than I3.
1440 I1 can be zero; then we combine just I2 into I3.
1442 If we are combining three insns and the resulting insn is not recognized,
1443 try splitting it into two insns. If that happens, I2 and I3 are retained
1444 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1447 Return 0 if the combination does not work. Then nothing is changed.
1448 If we did the combination, return the insn at which combine should
1451 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1452 new direct jump instruction. */
1455 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1457 /* New patterns for I3 and I2, respectively. */
1458 rtx newpat, newi2pat = 0;
1459 int substed_i2 = 0, substed_i1 = 0;
1460 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1461 int added_sets_1, added_sets_2;
1462 /* Total number of SETs to put into I3. */
1464 /* Nonzero is I2's body now appears in I3. */
1466 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1467 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1468 /* Contains I3 if the destination of I3 is used in its source, which means
1469 that the old life of I3 is being killed. If that usage is placed into
1470 I2 and not in I3, a REG_DEAD note must be made. */
1471 rtx i3dest_killed = 0;
1472 /* SET_DEST and SET_SRC of I2 and I1. */
1473 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1474 /* PATTERN (I2), or a copy of it in certain cases. */
1476 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1477 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1478 int i1_feeds_i3 = 0;
1479 /* Notes that must be added to REG_NOTES in I3 and I2. */
1480 rtx new_i3_notes, new_i2_notes;
1481 /* Notes that we substituted I3 into I2 instead of the normal case. */
1482 int i3_subst_into_i2 = 0;
1483 /* Notes that I1, I2 or I3 is a MULT operation. */
1491 /* Exit early if one of the insns involved can't be used for
1493 if (cant_combine_insn_p (i3)
1494 || cant_combine_insn_p (i2)
1495 || (i1 && cant_combine_insn_p (i1))
1496 /* We also can't do anything if I3 has a
1497 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1500 /* ??? This gives worse code, and appears to be unnecessary, since no
1501 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1502 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1508 undobuf.other_insn = 0;
1510 /* Reset the hard register usage information. */
1511 CLEAR_HARD_REG_SET (newpat_used_regs);
1513 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1514 code below, set I1 to be the earlier of the two insns. */
1515 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1516 temp = i1, i1 = i2, i2 = temp;
1518 added_links_insn = 0;
1520 /* First check for one important special-case that the code below will
1521 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1522 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1523 we may be able to replace that destination with the destination of I3.
1524 This occurs in the common code where we compute both a quotient and
1525 remainder into a structure, in which case we want to do the computation
1526 directly into the structure to avoid register-register copies.
1528 Note that this case handles both multiple sets in I2 and also
1529 cases where I2 has a number of CLOBBER or PARALLELs.
1531 We make very conservative checks below and only try to handle the
1532 most common cases of this. For example, we only handle the case
1533 where I2 and I3 are adjacent to avoid making difficult register
1536 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1537 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1538 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1539 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1540 && GET_CODE (PATTERN (i2)) == PARALLEL
1541 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1542 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1543 below would need to check what is inside (and reg_overlap_mentioned_p
1544 doesn't support those codes anyway). Don't allow those destinations;
1545 the resulting insn isn't likely to be recognized anyway. */
1546 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1547 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1548 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1549 SET_DEST (PATTERN (i3)))
1550 && next_real_insn (i2) == i3)
1552 rtx p2 = PATTERN (i2);
1554 /* Make sure that the destination of I3,
1555 which we are going to substitute into one output of I2,
1556 is not used within another output of I2. We must avoid making this:
1557 (parallel [(set (mem (reg 69)) ...)
1558 (set (reg 69) ...)])
1559 which is not well-defined as to order of actions.
1560 (Besides, reload can't handle output reloads for this.)
1562 The problem can also happen if the dest of I3 is a memory ref,
1563 if another dest in I2 is an indirect memory ref. */
1564 for (i = 0; i < XVECLEN (p2, 0); i++)
1565 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1566 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1567 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1568 SET_DEST (XVECEXP (p2, 0, i))))
1571 if (i == XVECLEN (p2, 0))
1572 for (i = 0; i < XVECLEN (p2, 0); i++)
1573 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1574 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1575 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1580 subst_low_cuid = INSN_CUID (i2);
1582 added_sets_2 = added_sets_1 = 0;
1583 i2dest = SET_SRC (PATTERN (i3));
1585 /* Replace the dest in I2 with our dest and make the resulting
1586 insn the new pattern for I3. Then skip to where we
1587 validate the pattern. Everything was set up above. */
1588 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1589 SET_DEST (PATTERN (i3)));
1592 i3_subst_into_i2 = 1;
1593 goto validate_replacement;
1597 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1598 one of those words to another constant, merge them by making a new
1601 && (temp = single_set (i2)) != 0
1602 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1603 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1604 && GET_CODE (SET_DEST (temp)) == REG
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1607 && GET_CODE (PATTERN (i3)) == SET
1608 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1609 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1610 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1611 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1612 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1614 HOST_WIDE_INT lo, hi;
1616 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1617 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1620 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1621 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1624 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1626 /* We don't handle the case of the target word being wider
1627 than a host wide int. */
1628 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1631 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1632 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1633 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1635 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1636 hi = INTVAL (SET_SRC (PATTERN (i3)));
1637 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1639 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1640 >> (HOST_BITS_PER_WIDE_INT - 1));
1642 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1643 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1644 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1645 (INTVAL (SET_SRC (PATTERN (i3)))));
1647 hi = lo < 0 ? -1 : 0;
1650 /* We don't handle the case of the higher word not fitting
1651 entirely in either hi or lo. */
1656 subst_low_cuid = INSN_CUID (i2);
1657 added_sets_2 = added_sets_1 = 0;
1658 i2dest = SET_DEST (temp);
1660 SUBST (SET_SRC (temp),
1661 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1663 newpat = PATTERN (i2);
1664 goto validate_replacement;
1668 /* If we have no I1 and I2 looks like:
1669 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1671 make up a dummy I1 that is
1674 (set (reg:CC X) (compare:CC Y (const_int 0)))
1676 (We can ignore any trailing CLOBBERs.)
1678 This undoes a previous combination and allows us to match a branch-and-
1681 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1682 && XVECLEN (PATTERN (i2), 0) >= 2
1683 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1684 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1686 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1687 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1688 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1689 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1690 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1691 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1693 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1694 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1699 /* We make I1 with the same INSN_UID as I2. This gives it
1700 the same INSN_CUID for value tracking. Our fake I1 will
1701 never appear in the insn stream so giving it the same INSN_UID
1702 as I2 will not cause a problem. */
1704 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1705 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1706 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1709 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1710 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1711 SET_DEST (PATTERN (i1)));
1716 /* Verify that I2 and I1 are valid for combining. */
1717 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1718 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1724 /* Record whether I2DEST is used in I2SRC and similarly for the other
1725 cases. Knowing this will help in register status updating below. */
1726 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1727 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1728 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1732 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1734 /* Ensure that I3's pattern can be the destination of combines. */
1735 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1736 i1 && i2dest_in_i1src && i1_feeds_i3,
1743 /* See if any of the insns is a MULT operation. Unless one is, we will
1744 reject a combination that is, since it must be slower. Be conservative
1746 if (GET_CODE (i2src) == MULT
1747 || (i1 != 0 && GET_CODE (i1src) == MULT)
1748 || (GET_CODE (PATTERN (i3)) == SET
1749 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1753 We used to do this EXCEPT in one case: I3 has a post-inc in an
1754 output operand. However, that exception can give rise to insns like
1756 which is a famous insn on the PDP-11 where the value of r3 used as the
1757 source was model-dependent. Avoid this sort of thing. */
1760 if (!(GET_CODE (PATTERN (i3)) == SET
1761 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1762 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1765 /* It's not the exception. */
1768 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1769 if (REG_NOTE_KIND (link) == REG_INC
1770 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1772 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1779 /* See if the SETs in I1 or I2 need to be kept around in the merged
1780 instruction: whenever the value set there is still needed past I3.
1781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1783 For the SET in I1, we have two cases: If I1 and I2 independently
1784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1786 in I1 needs to be kept around unless I1DEST dies or is set in either
1787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1788 I1DEST. If so, we know I1 feeds into I2. */
1790 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1793 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1794 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1796 /* If the set in I2 needs to be kept around, we must make a copy of
1797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1798 PATTERN (I2), we are only substituting for the original I1DEST, not into
1799 an already-substituted copy. This also prevents making self-referential
1800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1803 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1804 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1808 i2pat = copy_rtx (i2pat);
1812 /* Substitute in the latest insn for the regs set by the earlier ones. */
1814 maxreg = max_reg_num ();
1818 /* It is possible that the source of I2 or I1 may be performing an
1819 unneeded operation, such as a ZERO_EXTEND of something that is known
1820 to have the high part zero. Handle that case by letting subst look at
1821 the innermost one of them.
1823 Another way to do this would be to have a function that tries to
1824 simplify a single insn instead of merging two or more insns. We don't
1825 do this because of the potential of infinite loops and because
1826 of the potential extra memory required. However, doing it the way
1827 we are is a bit of a kludge and doesn't catch all cases.
1829 But only do this if -fexpensive-optimizations since it slows things down
1830 and doesn't usually win. */
1832 if (flag_expensive_optimizations)
1834 /* Pass pc_rtx so no substitutions are done, just simplifications.
1835 The cases that we are interested in here do not involve the few
1836 cases were is_replaced is checked. */
1839 subst_low_cuid = INSN_CUID (i1);
1840 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1844 subst_low_cuid = INSN_CUID (i2);
1845 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1850 /* Many machines that don't use CC0 have insns that can both perform an
1851 arithmetic operation and set the condition code. These operations will
1852 be represented as a PARALLEL with the first element of the vector
1853 being a COMPARE of an arithmetic operation with the constant zero.
1854 The second element of the vector will set some pseudo to the result
1855 of the same arithmetic operation. If we simplify the COMPARE, we won't
1856 match such a pattern and so will generate an extra insn. Here we test
1857 for this case, where both the comparison and the operation result are
1858 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1859 I2SRC. Later we will make the PARALLEL that contains I2. */
1861 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1862 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1863 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1864 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1866 #ifdef EXTRA_CC_MODES
1868 enum machine_mode compare_mode;
1871 newpat = PATTERN (i3);
1872 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1876 #ifdef EXTRA_CC_MODES
1877 /* See if a COMPARE with the operand we substituted in should be done
1878 with the mode that is currently being used. If not, do the same
1879 processing we do in `subst' for a SET; namely, if the destination
1880 is used only once, try to replace it with a register of the proper
1881 mode and also replace the COMPARE. */
1882 if (undobuf.other_insn == 0
1883 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1884 &undobuf.other_insn))
1885 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1887 != GET_MODE (SET_DEST (newpat))))
1889 unsigned int regno = REGNO (SET_DEST (newpat));
1890 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1892 if (regno < FIRST_PSEUDO_REGISTER
1893 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1894 && ! REG_USERVAR_P (SET_DEST (newpat))))
1896 if (regno >= FIRST_PSEUDO_REGISTER)
1897 SUBST (regno_reg_rtx[regno], new_dest);
1899 SUBST (SET_DEST (newpat), new_dest);
1900 SUBST (XEXP (*cc_use, 0), new_dest);
1901 SUBST (SET_SRC (newpat),
1902 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1905 undobuf.other_insn = 0;
1912 n_occurrences = 0; /* `subst' counts here */
1914 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1915 need to make a unique copy of I2SRC each time we substitute it
1916 to avoid self-referential rtl. */
1918 subst_low_cuid = INSN_CUID (i2);
1919 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1920 ! i1_feeds_i3 && i1dest_in_i1src);
1923 /* Record whether i2's body now appears within i3's body. */
1924 i2_is_used = n_occurrences;
1927 /* If we already got a failure, don't try to do more. Otherwise,
1928 try to substitute in I1 if we have it. */
1930 if (i1 && GET_CODE (newpat) != CLOBBER)
1932 /* Before we can do this substitution, we must redo the test done
1933 above (see detailed comments there) that ensures that I1DEST
1934 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1936 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1944 subst_low_cuid = INSN_CUID (i1);
1945 newpat = subst (newpat, i1dest, i1src, 0, 0);
1949 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1950 to count all the ways that I2SRC and I1SRC can be used. */
1951 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1952 && i2_is_used + added_sets_2 > 1)
1953 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1954 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1956 /* Fail if we tried to make a new register (we used to abort, but there's
1957 really no reason to). */
1958 || max_reg_num () != maxreg
1959 /* Fail if we couldn't do something and have a CLOBBER. */
1960 || GET_CODE (newpat) == CLOBBER
1961 /* Fail if this new pattern is a MULT and we didn't have one before
1962 at the outer level. */
1963 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1970 /* If the actions of the earlier insns must be kept
1971 in addition to substituting them into the latest one,
1972 we must make a new PARALLEL for the latest insn
1973 to hold additional the SETs. */
1975 if (added_sets_1 || added_sets_2)
1979 if (GET_CODE (newpat) == PARALLEL)
1981 rtvec old = XVEC (newpat, 0);
1982 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1983 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1984 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1985 sizeof (old->elem[0]) * old->num_elem);
1990 total_sets = 1 + added_sets_1 + added_sets_2;
1991 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1992 XVECEXP (newpat, 0, 0) = old;
1996 XVECEXP (newpat, 0, --total_sets)
1997 = (GET_CODE (PATTERN (i1)) == PARALLEL
1998 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2002 /* If there is no I1, use I2's body as is. We used to also not do
2003 the subst call below if I2 was substituted into I3,
2004 but that could lose a simplification. */
2006 XVECEXP (newpat, 0, --total_sets) = i2pat;
2008 /* See comment where i2pat is assigned. */
2009 XVECEXP (newpat, 0, --total_sets)
2010 = subst (i2pat, i1dest, i1src, 0, 0);
2014 /* We come here when we are replacing a destination in I2 with the
2015 destination of I3. */
2016 validate_replacement:
2018 /* Note which hard regs this insn has as inputs. */
2019 mark_used_regs_combine (newpat);
2021 /* Is the result of combination a valid instruction? */
2022 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2024 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2025 the second SET's destination is a register that is unused. In that case,
2026 we just need the first SET. This can occur when simplifying a divmod
2027 insn. We *must* test for this case here because the code below that
2028 splits two independent SETs doesn't handle this case correctly when it
2029 updates the register status. Also check the case where the first
2030 SET's destination is unused. That would not cause incorrect code, but
2031 does cause an unneeded insn to remain. */
2033 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2034 && XVECLEN (newpat, 0) == 2
2035 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2036 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2037 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2038 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2039 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2040 && asm_noperands (newpat) < 0)
2042 newpat = XVECEXP (newpat, 0, 0);
2043 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2046 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2047 && XVECLEN (newpat, 0) == 2
2048 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2049 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2051 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2052 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2053 && asm_noperands (newpat) < 0)
2055 newpat = XVECEXP (newpat, 0, 1);
2056 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2059 /* If we were combining three insns and the result is a simple SET
2060 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2061 insns. There are two ways to do this. It can be split using a
2062 machine-specific method (like when you have an addition of a large
2063 constant) or by combine in the function find_split_point. */
2065 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2066 && asm_noperands (newpat) < 0)
2068 rtx m_split, *split;
2069 rtx ni2dest = i2dest;
2071 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2072 use I2DEST as a scratch register will help. In the latter case,
2073 convert I2DEST to the mode of the source of NEWPAT if we can. */
2075 m_split = split_insns (newpat, i3);
2077 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2078 inputs of NEWPAT. */
2080 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2081 possible to try that as a scratch reg. This would require adding
2082 more code to make it work though. */
2084 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2086 /* If I2DEST is a hard register or the only use of a pseudo,
2087 we can change its mode. */
2088 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2089 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2090 && GET_CODE (i2dest) == REG
2091 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2092 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2093 && ! REG_USERVAR_P (i2dest))))
2094 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2097 m_split = split_insns (gen_rtx_PARALLEL
2099 gen_rtvec (2, newpat,
2100 gen_rtx_CLOBBER (VOIDmode,
2103 /* If the split with the mode-changed register didn't work, try
2104 the original register. */
2105 if (! m_split && ni2dest != i2dest)
2108 m_split = split_insns (gen_rtx_PARALLEL
2110 gen_rtvec (2, newpat,
2111 gen_rtx_CLOBBER (VOIDmode,
2117 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2119 m_split = PATTERN (m_split);
2120 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2121 if (insn_code_number >= 0)
2124 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2125 && (next_real_insn (i2) == i3
2126 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2129 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2130 newi2pat = PATTERN (m_split);
2132 i3set = single_set (NEXT_INSN (m_split));
2133 i2set = single_set (m_split);
2135 /* In case we changed the mode of I2DEST, replace it in the
2136 pseudo-register table here. We can't do it above in case this
2137 code doesn't get executed and we do a split the other way. */
2139 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2140 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2142 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2144 /* If I2 or I3 has multiple SETs, we won't know how to track
2145 register status, so don't use these insns. If I2's destination
2146 is used between I2 and I3, we also can't use these insns. */
2148 if (i2_code_number >= 0 && i2set && i3set
2149 && (next_real_insn (i2) == i3
2150 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2151 insn_code_number = recog_for_combine (&newi3pat, i3,
2153 if (insn_code_number >= 0)
2156 /* It is possible that both insns now set the destination of I3.
2157 If so, we must show an extra use of it. */
2159 if (insn_code_number >= 0)
2161 rtx new_i3_dest = SET_DEST (i3set);
2162 rtx new_i2_dest = SET_DEST (i2set);
2164 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2165 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2166 || GET_CODE (new_i3_dest) == SUBREG)
2167 new_i3_dest = XEXP (new_i3_dest, 0);
2169 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2170 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2171 || GET_CODE (new_i2_dest) == SUBREG)
2172 new_i2_dest = XEXP (new_i2_dest, 0);
2174 if (GET_CODE (new_i3_dest) == REG
2175 && GET_CODE (new_i2_dest) == REG
2176 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2177 REG_N_SETS (REGNO (new_i2_dest))++;
2181 /* If we can split it and use I2DEST, go ahead and see if that
2182 helps things be recognized. Verify that none of the registers
2183 are set between I2 and I3. */
2184 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2186 && GET_CODE (i2dest) == REG
2188 /* We need I2DEST in the proper mode. If it is a hard register
2189 or the only use of a pseudo, we can change its mode. */
2190 && (GET_MODE (*split) == GET_MODE (i2dest)
2191 || GET_MODE (*split) == VOIDmode
2192 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2193 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2194 && ! REG_USERVAR_P (i2dest)))
2195 && (next_real_insn (i2) == i3
2196 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2197 /* We can't overwrite I2DEST if its value is still used by
2199 && ! reg_referenced_p (i2dest, newpat))
2201 rtx newdest = i2dest;
2202 enum rtx_code split_code = GET_CODE (*split);
2203 enum machine_mode split_mode = GET_MODE (*split);
2205 /* Get NEWDEST as a register in the proper mode. We have already
2206 validated that we can do this. */
2207 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2209 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2211 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2212 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2215 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2216 an ASHIFT. This can occur if it was inside a PLUS and hence
2217 appeared to be a memory address. This is a kludge. */
2218 if (split_code == MULT
2219 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2220 && INTVAL (XEXP (*split, 1)) > 0
2221 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2223 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2224 XEXP (*split, 0), GEN_INT (i)));
2225 /* Update split_code because we may not have a multiply
2227 split_code = GET_CODE (*split);
2230 #ifdef INSN_SCHEDULING
2231 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2232 be written as a ZERO_EXTEND. */
2233 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2235 #ifdef LOAD_EXTEND_OP
2236 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2237 what it really is. */
2238 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2240 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2241 SUBREG_REG (*split)));
2244 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2245 SUBREG_REG (*split)));
2249 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2250 SUBST (*split, newdest);
2251 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2253 /* If the split point was a MULT and we didn't have one before,
2254 don't use one now. */
2255 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2256 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2260 /* Check for a case where we loaded from memory in a narrow mode and
2261 then sign extended it, but we need both registers. In that case,
2262 we have a PARALLEL with both loads from the same memory location.
2263 We can split this into a load from memory followed by a register-register
2264 copy. This saves at least one insn, more if register allocation can
2267 We cannot do this if the destination of the first assignment is a
2268 condition code register or cc0. We eliminate this case by making sure
2269 the SET_DEST and SET_SRC have the same mode.
2271 We cannot do this if the destination of the second assignment is
2272 a register that we have already assumed is zero-extended. Similarly
2273 for a SUBREG of such a register. */
2275 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2276 && GET_CODE (newpat) == PARALLEL
2277 && XVECLEN (newpat, 0) == 2
2278 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2279 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2280 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2281 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2282 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2287 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2290 (GET_CODE (temp) == REG
2291 && reg_nonzero_bits[REGNO (temp)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits[REGNO (temp)]
2295 != GET_MODE_MASK (word_mode))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2297 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2298 (GET_CODE (temp) == REG
2299 && reg_nonzero_bits[REGNO (temp)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits[REGNO (temp)]
2303 != GET_MODE_MASK (word_mode)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2305 SET_SRC (XVECEXP (newpat, 0, 1)))
2306 && ! find_reg_note (i3, REG_UNUSED,
2307 SET_DEST (XVECEXP (newpat, 0, 0))))
2311 newi2pat = XVECEXP (newpat, 0, 0);
2312 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2313 newpat = XVECEXP (newpat, 0, 1);
2314 SUBST (SET_SRC (newpat),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2316 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2318 if (i2_code_number >= 0)
2319 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2321 if (insn_code_number >= 0)
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3) = newpat;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn = NEXT_INSN (i3);
2348 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2349 || insn != this_basic_block->next_bb->head);
2350 insn = NEXT_INSN (insn))
2352 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2354 for (link = LOG_LINKS (insn); link;
2355 link = XEXP (link, 1))
2356 if (XEXP (link, 0) == i3)
2357 XEXP (link, 0) = i1;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2371 && GET_CODE (newpat) == PARALLEL
2372 && XVECLEN (newpat, 0) == 2
2373 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2385 XVECEXP (newpat, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2387 XVECEXP (newpat, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2395 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2397 newi2pat = XVECEXP (newpat, 0, 0);
2398 newpat = XVECEXP (newpat, 0, 1);
2403 newi2pat = XVECEXP (newpat, 0, 1);
2404 newpat = XVECEXP (newpat, 0, 0);
2407 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2409 if (i2_code_number >= 0)
2410 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2413 /* If it still isn't recognized, fail and change things back the way they
2415 if ((insn_code_number < 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf.other_insn)
2426 rtx other_pat = PATTERN (undobuf.other_insn);
2427 rtx new_other_notes;
2430 CLEAR_HARD_REG_SET (newpat_used_regs);
2432 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2435 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2441 PATTERN (undobuf.other_insn) = other_pat;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2448 next = XEXP (note, 1);
2450 if (REG_NOTE_KIND (note) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2453 if (GET_CODE (XEXP (note, 0)) == REG)
2454 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2456 remove_note (undobuf.other_insn, note);
2460 for (note = new_other_notes; note; note = XEXP (note, 1))
2461 if (GET_CODE (XEXP (note, 0)) == REG)
2462 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2464 distribute_notes (new_other_notes, undobuf.other_insn,
2465 undobuf.other_insn, NULL_RTX);
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p = prev_nonnote_insn (i3);
2472 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2473 && sets_cc0_p (newi2pat))
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes, i2notes, i1notes = 0;
2486 rtx i3links, i2links, i1links = 0;
2490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2492 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2493 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2495 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2497 /* Ensure that we do not have something that should not be shared but
2498 occurs multiple times in the new insns. Check this by first
2499 resetting all the `used' flags and then copying anything is shared. */
2501 reset_used_flags (i3notes);
2502 reset_used_flags (i2notes);
2503 reset_used_flags (i1notes);
2504 reset_used_flags (newpat);
2505 reset_used_flags (newi2pat);
2506 if (undobuf.other_insn)
2507 reset_used_flags (PATTERN (undobuf.other_insn));
2509 i3notes = copy_rtx_if_shared (i3notes);
2510 i2notes = copy_rtx_if_shared (i2notes);
2511 i1notes = copy_rtx_if_shared (i1notes);
2512 newpat = copy_rtx_if_shared (newpat);
2513 newi2pat = copy_rtx_if_shared (newi2pat);
2514 if (undobuf.other_insn)
2515 reset_used_flags (PATTERN (undobuf.other_insn));
2517 INSN_CODE (i3) = insn_code_number;
2518 PATTERN (i3) = newpat;
2520 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2522 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2524 reset_used_flags (call_usage);
2525 call_usage = copy_rtx (call_usage);
2528 replace_rtx (call_usage, i2dest, i2src);
2531 replace_rtx (call_usage, i1dest, i1src);
2533 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2536 if (undobuf.other_insn)
2537 INSN_CODE (undobuf.other_insn) = other_code_number;
2539 /* We had one special case above where I2 had more than one set and
2540 we replaced a destination of one of those sets with the destination
2541 of I3. In that case, we have to update LOG_LINKS of insns later
2542 in this basic block. Note that this (expensive) case is rare.
2544 Also, in this case, we must pretend that all REG_NOTEs for I2
2545 actually came from I3, so that REG_UNUSED notes from I2 will be
2546 properly handled. */
2548 if (i3_subst_into_i2)
2550 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2551 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2552 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2553 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2554 && ! find_reg_note (i2, REG_UNUSED,
2555 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2556 for (temp = NEXT_INSN (i2);
2557 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2558 || this_basic_block->head != temp);
2559 temp = NEXT_INSN (temp))
2560 if (temp != i3 && INSN_P (temp))
2561 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2562 if (XEXP (link, 0) == i2)
2563 XEXP (link, 0) = i3;
2568 while (XEXP (link, 1))
2569 link = XEXP (link, 1);
2570 XEXP (link, 1) = i2notes;
2584 INSN_CODE (i2) = i2_code_number;
2585 PATTERN (i2) = newi2pat;
2589 PUT_CODE (i2, NOTE);
2590 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2591 NOTE_SOURCE_FILE (i2) = 0;
2598 PUT_CODE (i1, NOTE);
2599 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2600 NOTE_SOURCE_FILE (i1) = 0;
2603 /* Get death notes for everything that is now used in either I3 or
2604 I2 and used to die in a previous insn. If we built two new
2605 patterns, move from I1 to I2 then I2 to I3 so that we get the
2606 proper movement on registers that I2 modifies. */
2610 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2611 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2614 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2617 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2619 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2621 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2623 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2625 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2627 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2628 know these are REG_UNUSED and want them to go to the desired insn,
2629 so we always pass it as i3. We have not counted the notes in
2630 reg_n_deaths yet, so we need to do so now. */
2632 if (newi2pat && new_i2_notes)
2634 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2635 if (GET_CODE (XEXP (temp, 0)) == REG)
2636 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2638 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2643 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2644 if (GET_CODE (XEXP (temp, 0)) == REG)
2645 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2647 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2650 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2651 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2652 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2653 in that case, it might delete I2. Similarly for I2 and I1.
2654 Show an additional death due to the REG_DEAD note we make here. If
2655 we discard it in distribute_notes, we will decrement it again. */
2659 if (GET_CODE (i3dest_killed) == REG)
2660 REG_N_DEATHS (REGNO (i3dest_killed))++;
2662 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2665 NULL_RTX, i2, NULL_RTX);
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2669 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2672 if (i2dest_in_i2src)
2674 if (GET_CODE (i2dest) == REG)
2675 REG_N_DEATHS (REGNO (i2dest))++;
2677 if (newi2pat && reg_set_p (i2dest, newi2pat))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2679 NULL_RTX, i2, NULL_RTX);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2682 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2685 if (i1dest_in_i1src)
2687 if (GET_CODE (i1dest) == REG)
2688 REG_N_DEATHS (REGNO (i1dest))++;
2690 if (newi2pat && reg_set_p (i1dest, newi2pat))
2691 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2692 NULL_RTX, i2, NULL_RTX);
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2695 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2698 distribute_links (i3links);
2699 distribute_links (i2links);
2700 distribute_links (i1links);
2702 if (GET_CODE (i2dest) == REG)
2705 rtx i2_insn = 0, i2_val = 0, set;
2707 /* The insn that used to set this register doesn't exist, and
2708 this life of the register may not exist either. See if one of
2709 I3's links points to an insn that sets I2DEST. If it does,
2710 that is now the last known value for I2DEST. If we don't update
2711 this and I2 set the register to a value that depended on its old
2712 contents, we will get confused. If this insn is used, thing
2713 will be set correctly in combine_instructions. */
2715 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2716 if ((set = single_set (XEXP (link, 0))) != 0
2717 && rtx_equal_p (i2dest, SET_DEST (set)))
2718 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2720 record_value_for_reg (i2dest, i2_insn, i2_val);
2722 /* If the reg formerly set in I2 died only once and that was in I3,
2723 zero its use count so it won't make `reload' do any work. */
2725 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2726 && ! i2dest_in_i2src)
2728 regno = REGNO (i2dest);
2729 REG_N_SETS (regno)--;
2733 if (i1 && GET_CODE (i1dest) == REG)
2736 rtx i1_insn = 0, i1_val = 0, set;
2738 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2739 if ((set = single_set (XEXP (link, 0))) != 0
2740 && rtx_equal_p (i1dest, SET_DEST (set)))
2741 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2743 record_value_for_reg (i1dest, i1_insn, i1_val);
2745 regno = REGNO (i1dest);
2746 if (! added_sets_1 && ! i1dest_in_i1src)
2747 REG_N_SETS (regno)--;
2750 /* Update reg_nonzero_bits et al for any changes that may have been made
2751 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2752 important. Because newi2pat can affect nonzero_bits of newpat */
2754 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2755 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2757 /* Set new_direct_jump_p if a new return or simple jump instruction
2760 If I3 is now an unconditional jump, ensure that it has a
2761 BARRIER following it since it may have initially been a
2762 conditional jump. It may also be the last nonnote insn. */
2764 if (returnjump_p (i3) || any_uncondjump_p (i3))
2766 *new_direct_jump_p = 1;
2767 mark_jump_label (PATTERN (i3), i3, 0);
2769 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2770 || GET_CODE (temp) != BARRIER)
2771 emit_barrier_after (i3);
2774 if (undobuf.other_insn != NULL_RTX
2775 && (returnjump_p (undobuf.other_insn)
2776 || any_uncondjump_p (undobuf.other_insn)))
2778 *new_direct_jump_p = 1;
2780 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2781 || GET_CODE (temp) != BARRIER)
2782 emit_barrier_after (undobuf.other_insn);
2785 /* An NOOP jump does not need barrier, but it does need cleaning up
2787 if (GET_CODE (newpat) == SET
2788 && SET_SRC (newpat) == pc_rtx
2789 && SET_DEST (newpat) == pc_rtx)
2790 *new_direct_jump_p = 1;
2793 combine_successes++;
2796 if (added_links_insn
2797 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2798 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2799 return added_links_insn;
2801 return newi2pat ? i2 : i3;
2804 /* Undo all the modifications recorded in undobuf. */
2809 struct undo *undo, *next;
2811 for (undo = undobuf.undos; undo; undo = next)
2815 *undo->where.i = undo->old_contents.i;
2817 *undo->where.r = undo->old_contents.r;
2819 undo->next = undobuf.frees;
2820 undobuf.frees = undo;
2826 /* We've committed to accepting the changes we made. Move all
2827 of the undos to the free list. */
2832 struct undo *undo, *next;
2834 for (undo = undobuf.undos; undo; undo = next)
2837 undo->next = undobuf.frees;
2838 undobuf.frees = undo;
2844 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2845 where we have an arithmetic expression and return that point. LOC will
2848 try_combine will call this function to see if an insn can be split into
2852 find_split_point (rtx *loc, rtx insn)
2855 enum rtx_code code = GET_CODE (x);
2857 unsigned HOST_WIDE_INT len = 0;
2858 HOST_WIDE_INT pos = 0;
2860 rtx inner = NULL_RTX;
2862 /* First special-case some codes. */
2866 #ifdef INSN_SCHEDULING
2867 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2869 if (GET_CODE (SUBREG_REG (x)) == MEM)
2872 return find_split_point (&SUBREG_REG (x), insn);
2876 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2877 using LO_SUM and HIGH. */
2878 if (GET_CODE (XEXP (x, 0)) == CONST
2879 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2882 gen_rtx_LO_SUM (Pmode,
2883 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2885 return &XEXP (XEXP (x, 0), 0);
2889 /* If we have a PLUS whose second operand is a constant and the
2890 address is not valid, perhaps will can split it up using
2891 the machine-specific way to split large constants. We use
2892 the first pseudo-reg (one of the virtual regs) as a placeholder;
2893 it will not remain in the result. */
2894 if (GET_CODE (XEXP (x, 0)) == PLUS
2895 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2896 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2898 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2899 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2902 /* This should have produced two insns, each of which sets our
2903 placeholder. If the source of the second is a valid address,
2904 we can make put both sources together and make a split point
2908 && NEXT_INSN (seq) != NULL_RTX
2909 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2910 && GET_CODE (seq) == INSN
2911 && GET_CODE (PATTERN (seq)) == SET
2912 && SET_DEST (PATTERN (seq)) == reg
2913 && ! reg_mentioned_p (reg,
2914 SET_SRC (PATTERN (seq)))
2915 && GET_CODE (NEXT_INSN (seq)) == INSN
2916 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2917 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2918 && memory_address_p (GET_MODE (x),
2919 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2921 rtx src1 = SET_SRC (PATTERN (seq));
2922 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2924 /* Replace the placeholder in SRC2 with SRC1. If we can
2925 find where in SRC2 it was placed, that can become our
2926 split point and we can replace this address with SRC2.
2927 Just try two obvious places. */
2929 src2 = replace_rtx (src2, reg, src1);
2931 if (XEXP (src2, 0) == src1)
2932 split = &XEXP (src2, 0);
2933 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2934 && XEXP (XEXP (src2, 0), 0) == src1)
2935 split = &XEXP (XEXP (src2, 0), 0);
2939 SUBST (XEXP (x, 0), src2);
2944 /* If that didn't work, perhaps the first operand is complex and
2945 needs to be computed separately, so make a split point there.
2946 This will occur on machines that just support REG + CONST
2947 and have a constant moved through some previous computation. */
2949 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2950 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2951 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2953 return &XEXP (XEXP (x, 0), 0);
2959 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2960 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2961 we need to put the operand into a register. So split at that
2964 if (SET_DEST (x) == cc0_rtx
2965 && GET_CODE (SET_SRC (x)) != COMPARE
2966 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2967 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2968 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2969 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2970 return &SET_SRC (x);
2973 /* See if we can split SET_SRC as it stands. */
2974 split = find_split_point (&SET_SRC (x), insn);
2975 if (split && split != &SET_SRC (x))
2978 /* See if we can split SET_DEST as it stands. */
2979 split = find_split_point (&SET_DEST (x), insn);
2980 if (split && split != &SET_DEST (x))
2983 /* See if this is a bitfield assignment with everything constant. If
2984 so, this is an IOR of an AND, so split it into that. */
2985 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2986 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2987 <= HOST_BITS_PER_WIDE_INT)
2988 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2989 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2990 && GET_CODE (SET_SRC (x)) == CONST_INT
2991 && ((INTVAL (XEXP (SET_DEST (x), 1))
2992 + INTVAL (XEXP (SET_DEST (x), 2)))
2993 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2994 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2996 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2997 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2998 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2999 rtx dest = XEXP (SET_DEST (x), 0);
3000 enum machine_mode mode = GET_MODE (dest);
3001 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3003 if (BITS_BIG_ENDIAN)
3004 pos = GET_MODE_BITSIZE (mode) - len - pos;
3008 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3011 gen_binary (IOR, mode,
3012 gen_binary (AND, mode, dest,
3013 gen_int_mode (~(mask << pos),
3015 GEN_INT (src << pos)));
3017 SUBST (SET_DEST (x), dest);
3019 split = find_split_point (&SET_SRC (x), insn);
3020 if (split && split != &SET_SRC (x))
3024 /* Otherwise, see if this is an operation that we can split into two.
3025 If so, try to split that. */
3026 code = GET_CODE (SET_SRC (x));
3031 /* If we are AND'ing with a large constant that is only a single
3032 bit and the result is only being used in a context where we
3033 need to know if it is zero or nonzero, replace it with a bit
3034 extraction. This will avoid the large constant, which might
3035 have taken more than one insn to make. If the constant were
3036 not a valid argument to the AND but took only one insn to make,
3037 this is no worse, but if it took more than one insn, it will
3040 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3041 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3042 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3043 && GET_CODE (SET_DEST (x)) == REG
3044 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3045 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3046 && XEXP (*split, 0) == SET_DEST (x)
3047 && XEXP (*split, 1) == const0_rtx)
3049 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3050 XEXP (SET_SRC (x), 0),
3051 pos, NULL_RTX, 1, 1, 0, 0);
3052 if (extraction != 0)
3054 SUBST (SET_SRC (x), extraction);
3055 return find_split_point (loc, insn);
3061 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3062 is known to be on, this can be converted into a NEG of a shift. */
3063 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3064 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3065 && 1 <= (pos = exact_log2
3066 (nonzero_bits (XEXP (SET_SRC (x), 0),
3067 GET_MODE (XEXP (SET_SRC (x), 0))))))
3069 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3073 gen_rtx_LSHIFTRT (mode,
3074 XEXP (SET_SRC (x), 0),
3077 split = find_split_point (&SET_SRC (x), insn);
3078 if (split && split != &SET_SRC (x))
3084 inner = XEXP (SET_SRC (x), 0);
3086 /* We can't optimize if either mode is a partial integer
3087 mode as we don't know how many bits are significant
3089 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3090 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3094 len = GET_MODE_BITSIZE (GET_MODE (inner));
3100 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3101 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3103 inner = XEXP (SET_SRC (x), 0);
3104 len = INTVAL (XEXP (SET_SRC (x), 1));
3105 pos = INTVAL (XEXP (SET_SRC (x), 2));
3107 if (BITS_BIG_ENDIAN)
3108 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3109 unsignedp = (code == ZERO_EXTRACT);
3117 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3119 enum machine_mode mode = GET_MODE (SET_SRC (x));
3121 /* For unsigned, we have a choice of a shift followed by an
3122 AND or two shifts. Use two shifts for field sizes where the
3123 constant might be too large. We assume here that we can
3124 always at least get 8-bit constants in an AND insn, which is
3125 true for every current RISC. */
3127 if (unsignedp && len <= 8)
3132 (mode, gen_lowpart_for_combine (mode, inner),
3134 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3136 split = find_split_point (&SET_SRC (x), insn);
3137 if (split && split != &SET_SRC (x))
3144 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3145 gen_rtx_ASHIFT (mode,
3146 gen_lowpart_for_combine (mode, inner),
3147 GEN_INT (GET_MODE_BITSIZE (mode)
3149 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3151 split = find_split_point (&SET_SRC (x), insn);
3152 if (split && split != &SET_SRC (x))
3157 /* See if this is a simple operation with a constant as the second
3158 operand. It might be that this constant is out of range and hence
3159 could be used as a split point. */
3160 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3161 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3162 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3163 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3164 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3165 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3166 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3168 return &XEXP (SET_SRC (x), 1);
3170 /* Finally, see if this is a simple operation with its first operand
3171 not in a register. The operation might require this operand in a
3172 register, so return it as a split point. We can always do this
3173 because if the first operand were another operation, we would have
3174 already found it as a split point. */
3175 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3179 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3180 return &XEXP (SET_SRC (x), 0);
3186 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3187 it is better to write this as (not (ior A B)) so we can split it.
3188 Similarly for IOR. */
3189 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3192 gen_rtx_NOT (GET_MODE (x),
3193 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3195 XEXP (XEXP (x, 0), 0),
3196 XEXP (XEXP (x, 1), 0))));
3197 return find_split_point (loc, insn);
3200 /* Many RISC machines have a large set of logical insns. If the
3201 second operand is a NOT, put it first so we will try to split the
3202 other operand first. */
3203 if (GET_CODE (XEXP (x, 1)) == NOT)
3205 rtx tem = XEXP (x, 0);
3206 SUBST (XEXP (x, 0), XEXP (x, 1));
3207 SUBST (XEXP (x, 1), tem);
3215 /* Otherwise, select our actions depending on our rtx class. */
3216 switch (GET_RTX_CLASS (code))
3218 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3220 split = find_split_point (&XEXP (x, 2), insn);
3223 /* ... fall through ... */
3227 split = find_split_point (&XEXP (x, 1), insn);
3230 /* ... fall through ... */
3232 /* Some machines have (and (shift ...) ...) insns. If X is not
3233 an AND, but XEXP (X, 0) is, use it as our split point. */
3234 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3235 return &XEXP (x, 0);
3237 split = find_split_point (&XEXP (x, 0), insn);
3243 /* Otherwise, we don't have a split point. */
3247 /* Throughout X, replace FROM with TO, and return the result.
3248 The result is TO if X is FROM;
3249 otherwise the result is X, but its contents may have been modified.
3250 If they were modified, a record was made in undobuf so that
3251 undo_all will (among other things) return X to its original state.
3253 If the number of changes necessary is too much to record to undo,
3254 the excess changes are not made, so the result is invalid.
3255 The changes already made can still be undone.
3256 undobuf.num_undo is incremented for such changes, so by testing that
3257 the caller can tell whether the result is valid.
3259 `n_occurrences' is incremented each time FROM is replaced.
3261 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3263 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3264 by copying if `n_occurrences' is nonzero. */
3267 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3269 enum rtx_code code = GET_CODE (x);
3270 enum machine_mode op0_mode = VOIDmode;
3275 /* Two expressions are equal if they are identical copies of a shared
3276 RTX or if they are both registers with the same register number
3279 #define COMBINE_RTX_EQUAL_P(X,Y) \
3281 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3282 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3284 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3287 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3290 /* If X and FROM are the same register but different modes, they will
3291 not have been seen as equal above. However, flow.c will make a
3292 LOG_LINKS entry for that case. If we do nothing, we will try to
3293 rerecognize our original insn and, when it succeeds, we will
3294 delete the feeding insn, which is incorrect.
3296 So force this insn not to match in this (rare) case. */
3297 if (! in_dest && code == REG && GET_CODE (from) == REG
3298 && REGNO (x) == REGNO (from))
3299 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3301 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3302 of which may contain things that can be combined. */
3303 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3306 /* It is possible to have a subexpression appear twice in the insn.
3307 Suppose that FROM is a register that appears within TO.
3308 Then, after that subexpression has been scanned once by `subst',
3309 the second time it is scanned, TO may be found. If we were
3310 to scan TO here, we would find FROM within it and create a
3311 self-referent rtl structure which is completely wrong. */
3312 if (COMBINE_RTX_EQUAL_P (x, to))
3315 /* Parallel asm_operands need special attention because all of the
3316 inputs are shared across the arms. Furthermore, unsharing the
3317 rtl results in recognition failures. Failure to handle this case
3318 specially can result in circular rtl.
3320 Solve this by doing a normal pass across the first entry of the
3321 parallel, and only processing the SET_DESTs of the subsequent
3324 if (code == PARALLEL
3325 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3326 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3328 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3330 /* If this substitution failed, this whole thing fails. */
3331 if (GET_CODE (new) == CLOBBER
3332 && XEXP (new, 0) == const0_rtx)
3335 SUBST (XVECEXP (x, 0, 0), new);
3337 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3339 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3341 if (GET_CODE (dest) != REG
3342 && GET_CODE (dest) != CC0
3343 && GET_CODE (dest) != PC)
3345 new = subst (dest, from, to, 0, unique_copy);
3347 /* If this substitution failed, this whole thing fails. */
3348 if (GET_CODE (new) == CLOBBER
3349 && XEXP (new, 0) == const0_rtx)
3352 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3358 len = GET_RTX_LENGTH (code);
3359 fmt = GET_RTX_FORMAT (code);
3361 /* We don't need to process a SET_DEST that is a register, CC0,
3362 or PC, so set up to skip this common case. All other cases
3363 where we want to suppress replacing something inside a
3364 SET_SRC are handled via the IN_DEST operand. */
3366 && (GET_CODE (SET_DEST (x)) == REG
3367 || GET_CODE (SET_DEST (x)) == CC0
3368 || GET_CODE (SET_DEST (x)) == PC))
3371 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3374 op0_mode = GET_MODE (XEXP (x, 0));
3376 for (i = 0; i < len; i++)
3381 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3383 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3385 new = (unique_copy && n_occurrences
3386 ? copy_rtx (to) : to);
3391 new = subst (XVECEXP (x, i, j), from, to, 0,
3394 /* If this substitution failed, this whole thing
3396 if (GET_CODE (new) == CLOBBER
3397 && XEXP (new, 0) == const0_rtx)
3401 SUBST (XVECEXP (x, i, j), new);
3404 else if (fmt[i] == 'e')
3406 /* If this is a register being set, ignore it. */
3409 && (code == SUBREG || code == STRICT_LOW_PART
3410 || code == ZERO_EXTRACT)
3412 && GET_CODE (new) == REG)
3415 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3417 /* In general, don't install a subreg involving two
3418 modes not tieable. It can worsen register
3419 allocation, and can even make invalid reload
3420 insns, since the reg inside may need to be copied
3421 from in the outside mode, and that may be invalid
3422 if it is an fp reg copied in integer mode.
3424 We allow two exceptions to this: It is valid if
3425 it is inside another SUBREG and the mode of that
3426 SUBREG and the mode of the inside of TO is
3427 tieable and it is valid if X is a SET that copies
3430 if (GET_CODE (to) == SUBREG
3431 && ! MODES_TIEABLE_P (GET_MODE (to),
3432 GET_MODE (SUBREG_REG (to)))
3433 && ! (code == SUBREG
3434 && MODES_TIEABLE_P (GET_MODE (x),
3435 GET_MODE (SUBREG_REG (to))))
3437 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3440 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3442 #ifdef CANNOT_CHANGE_MODE_CLASS
3444 && GET_CODE (to) == REG
3445 && REGNO (to) < FIRST_PSEUDO_REGISTER
3446 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3449 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3452 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3456 /* If we are in a SET_DEST, suppress most cases unless we
3457 have gone inside a MEM, in which case we want to
3458 simplify the address. We assume here that things that
3459 are actually part of the destination have their inner
3460 parts in the first expression. This is true for SUBREG,
3461 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3462 things aside from REG and MEM that should appear in a
3464 new = subst (XEXP (x, i), from, to,
3466 && (code == SUBREG || code == STRICT_LOW_PART
3467 || code == ZERO_EXTRACT))
3469 && i == 0), unique_copy);
3471 /* If we found that we will have to reject this combination,
3472 indicate that by returning the CLOBBER ourselves, rather than
3473 an expression containing it. This will speed things up as
3474 well as prevent accidents where two CLOBBERs are considered
3475 to be equal, thus producing an incorrect simplification. */
3477 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3480 if (GET_CODE (x) == SUBREG
3481 && (GET_CODE (new) == CONST_INT
3482 || GET_CODE (new) == CONST_DOUBLE))
3484 enum machine_mode mode = GET_MODE (x);
3486 x = simplify_subreg (GET_MODE (x), new,
3487 GET_MODE (SUBREG_REG (x)),
3490 x = gen_rtx_CLOBBER (mode, const0_rtx);
3492 else if (GET_CODE (new) == CONST_INT
3493 && GET_CODE (x) == ZERO_EXTEND)
3495 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3496 new, GET_MODE (XEXP (x, 0)));
3501 SUBST (XEXP (x, i), new);
3506 /* Try to simplify X. If the simplification changed the code, it is likely
3507 that further simplification will help, so loop, but limit the number
3508 of repetitions that will be performed. */
3510 for (i = 0; i < 4; i++)
3512 /* If X is sufficiently simple, don't bother trying to do anything
3514 if (code != CONST_INT && code != REG && code != CLOBBER)
3515 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3517 if (GET_CODE (x) == code)
3520 code = GET_CODE (x);
3522 /* We no longer know the original mode of operand 0 since we
3523 have changed the form of X) */
3524 op0_mode = VOIDmode;
3530 /* Simplify X, a piece of RTL. We just operate on the expression at the
3531 outer level; call `subst' to simplify recursively. Return the new
3534 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3535 will be the iteration even if an expression with a code different from
3536 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3539 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3542 enum rtx_code code = GET_CODE (x);
3543 enum machine_mode mode = GET_MODE (x);
3548 /* If this is a commutative operation, put a constant last and a complex
3549 expression first. We don't need to do this for comparisons here. */
3550 if (GET_RTX_CLASS (code) == 'c'
3551 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3554 SUBST (XEXP (x, 0), XEXP (x, 1));
3555 SUBST (XEXP (x, 1), temp);
3558 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3559 sign extension of a PLUS with a constant, reverse the order of the sign
3560 extension and the addition. Note that this not the same as the original
3561 code, but overflow is undefined for signed values. Also note that the
3562 PLUS will have been partially moved "inside" the sign-extension, so that
3563 the first operand of X will really look like:
3564 (ashiftrt (plus (ashift A C4) C5) C4).
3566 (plus (ashiftrt (ashift A C4) C2) C4)
3567 and replace the first operand of X with that expression. Later parts
3568 of this function may simplify the expression further.
3570 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3571 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3572 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3574 We do this to simplify address expressions. */
3576 if ((code == PLUS || code == MINUS || code == MULT)
3577 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3578 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3579 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3580 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3581 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3582 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3583 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3584 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3585 XEXP (XEXP (XEXP (x, 0), 0), 1),
3586 XEXP (XEXP (x, 0), 1))) != 0)
3589 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3590 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3591 INTVAL (XEXP (XEXP (x, 0), 1)));
3593 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3594 INTVAL (XEXP (XEXP (x, 0), 1)));
3596 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3599 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3600 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3601 things. Check for cases where both arms are testing the same
3604 Don't do anything if all operands are very simple. */
3606 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3607 || GET_RTX_CLASS (code) == '<')
3608 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3609 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3610 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3612 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3613 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3614 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3616 || (GET_RTX_CLASS (code) == '1'
3617 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3618 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3619 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3622 rtx cond, true_rtx, false_rtx;
3624 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3626 /* If everything is a comparison, what we have is highly unlikely
3627 to be simpler, so don't use it. */
3628 && ! (GET_RTX_CLASS (code) == '<'
3629 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3630 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3632 rtx cop1 = const0_rtx;
3633 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3635 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3638 /* Simplify the alternative arms; this may collapse the true and
3639 false arms to store-flag values. Be careful to use copy_rtx
3640 here since true_rtx or false_rtx might share RTL with x as a
3641 result of the if_then_else_cond call above. */
3642 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3643 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3645 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3646 is unlikely to be simpler. */
3647 if (general_operand (true_rtx, VOIDmode)
3648 && general_operand (false_rtx, VOIDmode))
3650 enum rtx_code reversed;
3652 /* Restarting if we generate a store-flag expression will cause
3653 us to loop. Just drop through in this case. */
3655 /* If the result values are STORE_FLAG_VALUE and zero, we can
3656 just make the comparison operation. */
3657 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3658 x = gen_binary (cond_code, mode, cond, cop1);
3659 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3660 && ((reversed = reversed_comparison_code_parts
3661 (cond_code, cond, cop1, NULL))
3663 x = gen_binary (reversed, mode, cond, cop1);
3665 /* Likewise, we can make the negate of a comparison operation
3666 if the result values are - STORE_FLAG_VALUE and zero. */
3667 else if (GET_CODE (true_rtx) == CONST_INT
3668 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3669 && false_rtx == const0_rtx)
3670 x = simplify_gen_unary (NEG, mode,
3671 gen_binary (cond_code, mode, cond,
3674 else if (GET_CODE (false_rtx) == CONST_INT
3675 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3676 && true_rtx == const0_rtx
3677 && ((reversed = reversed_comparison_code_parts
3678 (cond_code, cond, cop1, NULL))
3680 x = simplify_gen_unary (NEG, mode,
3681 gen_binary (reversed, mode,
3685 return gen_rtx_IF_THEN_ELSE (mode,
3686 gen_binary (cond_code, VOIDmode,
3688 true_rtx, false_rtx);
3690 code = GET_CODE (x);
3691 op0_mode = VOIDmode;
3696 /* Try to fold this expression in case we have constants that weren't
3699 switch (GET_RTX_CLASS (code))
3702 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3706 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3707 if (cmp_mode == VOIDmode)
3709 cmp_mode = GET_MODE (XEXP (x, 1));
3710 if (cmp_mode == VOIDmode)
3711 cmp_mode = op0_mode;
3713 temp = simplify_relational_operation (code, cmp_mode,
3714 XEXP (x, 0), XEXP (x, 1));
3716 #ifdef FLOAT_STORE_FLAG_VALUE
3717 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3719 if (temp == const0_rtx)
3720 temp = CONST0_RTX (mode);
3722 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3729 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3733 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3734 XEXP (x, 1), XEXP (x, 2));
3741 code = GET_CODE (temp);
3742 op0_mode = VOIDmode;
3743 mode = GET_MODE (temp);
3746 /* First see if we can apply the inverse distributive law. */
3747 if (code == PLUS || code == MINUS
3748 || code == AND || code == IOR || code == XOR)
3750 x = apply_distributive_law (x);
3751 code = GET_CODE (x);
3752 op0_mode = VOIDmode;
3755 /* If CODE is an associative operation not otherwise handled, see if we
3756 can associate some operands. This can win if they are constants or
3757 if they are logically related (i.e. (a & b) & a). */
3758 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3759 || code == AND || code == IOR || code == XOR
3760 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3761 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3762 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3764 if (GET_CODE (XEXP (x, 0)) == code)
3766 rtx other = XEXP (XEXP (x, 0), 0);
3767 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3768 rtx inner_op1 = XEXP (x, 1);
3771 /* Make sure we pass the constant operand if any as the second
3772 one if this is a commutative operation. */
3773 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3775 rtx tem = inner_op0;
3776 inner_op0 = inner_op1;
3779 inner = simplify_binary_operation (code == MINUS ? PLUS
3780 : code == DIV ? MULT
3782 mode, inner_op0, inner_op1);
3784 /* For commutative operations, try the other pair if that one
3786 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3788 other = XEXP (XEXP (x, 0), 1);
3789 inner = simplify_binary_operation (code, mode,
3790 XEXP (XEXP (x, 0), 0),
3795 return gen_binary (code, mode, other, inner);
3799 /* A little bit of algebraic simplification here. */
3803 /* Ensure that our address has any ASHIFTs converted to MULT in case
3804 address-recognizing predicates are called later. */
3805 temp = make_compound_operation (XEXP (x, 0), MEM);
3806 SUBST (XEXP (x, 0), temp);
3810 if (op0_mode == VOIDmode)
3811 op0_mode = GET_MODE (SUBREG_REG (x));
3813 /* simplify_subreg can't use gen_lowpart_for_combine. */
3814 if (CONSTANT_P (SUBREG_REG (x))
3815 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3816 /* Don't call gen_lowpart_for_combine if the inner mode
3817 is VOIDmode and we cannot simplify it, as SUBREG without
3818 inner mode is invalid. */
3819 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3820 || gen_lowpart_common (mode, SUBREG_REG (x))))
3821 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3823 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3827 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3833 /* Don't change the mode of the MEM if that would change the meaning
3835 if (GET_CODE (SUBREG_REG (x)) == MEM
3836 && (MEM_VOLATILE_P (SUBREG_REG (x))
3837 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3838 return gen_rtx_CLOBBER (mode, const0_rtx);
3840 /* Note that we cannot do any narrowing for non-constants since
3841 we might have been counting on using the fact that some bits were
3842 zero. We now do this in the SET. */
3847 /* (not (plus X -1)) can become (neg X). */
3848 if (GET_CODE (XEXP (x, 0)) == PLUS
3849 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3850 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3852 /* Similarly, (not (neg X)) is (plus X -1). */
3853 if (GET_CODE (XEXP (x, 0)) == NEG)
3854 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3856 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3857 if (GET_CODE (XEXP (x, 0)) == XOR
3858 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3859 && (temp = simplify_unary_operation (NOT, mode,
3860 XEXP (XEXP (x, 0), 1),
3862 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3864 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3865 other than 1, but that is not valid. We could do a similar
3866 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3867 but this doesn't seem common enough to bother with. */
3868 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3869 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3870 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3872 XEXP (XEXP (x, 0), 1));
3874 if (GET_CODE (XEXP (x, 0)) == SUBREG
3875 && subreg_lowpart_p (XEXP (x, 0))
3876 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3877 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3878 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3879 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3881 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3883 x = gen_rtx_ROTATE (inner_mode,
3884 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3886 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3887 return gen_lowpart_for_combine (mode, x);
3890 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3891 reversing the comparison code if valid. */
3892 if (STORE_FLAG_VALUE == -1
3893 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3894 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3895 XEXP (XEXP (x, 0), 1))))
3898 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3899 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3900 perform the above simplification. */
3902 if (STORE_FLAG_VALUE == -1
3903 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3904 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3905 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3906 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3908 /* Apply De Morgan's laws to reduce number of patterns for machines
3909 with negating logical insns (and-not, nand, etc.). If result has
3910 only one NOT, put it first, since that is how the patterns are
3913 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3915 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3916 enum machine_mode op_mode;
3918 op_mode = GET_MODE (in1);
3919 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3921 op_mode = GET_MODE (in2);
3922 if (op_mode == VOIDmode)
3924 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3926 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3929 in2 = in1; in1 = tem;
3932 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3938 /* (neg (plus X 1)) can become (not X). */
3939 if (GET_CODE (XEXP (x, 0)) == PLUS
3940 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3941 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3943 /* Similarly, (neg (not X)) is (plus X 1). */
3944 if (GET_CODE (XEXP (x, 0)) == NOT)
3945 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3947 /* (neg (minus X Y)) can become (minus Y X). This transformation
3948 isn't safe for modes with signed zeros, since if X and Y are
3949 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3950 mode is towards +infinity (or -infinity) then the two expressions
3951 will be rounded differently. */
3952 if (GET_CODE (XEXP (x, 0)) == MINUS
3953 && !HONOR_SIGNED_ZEROS (mode)
3954 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3955 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3956 XEXP (XEXP (x, 0), 0));
3958 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
3959 if (GET_CODE (XEXP (x, 0)) == PLUS
3960 && !HONOR_SIGNED_ZEROS (mode)
3961 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3963 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3964 temp = combine_simplify_rtx (temp, mode, last, in_dest);
3965 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
3968 /* (neg (mult A B)) becomes (mult (neg A) B).
3969 This works even for floating-point values. */
3970 if (GET_CODE (XEXP (x, 0)) == MULT)
3972 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3973 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
3976 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3977 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3978 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3979 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3981 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3982 if we can then eliminate the NEG (e.g.,
3983 if the operand is a constant). */
3985 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3987 temp = simplify_unary_operation (NEG, mode,
3988 XEXP (XEXP (x, 0), 0), mode);
3990 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3993 temp = expand_compound_operation (XEXP (x, 0));
3995 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3996 replaced by (lshiftrt X C). This will convert
3997 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3999 if (GET_CODE (temp) == ASHIFTRT
4000 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4001 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4002 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4003 INTVAL (XEXP (temp, 1)));
4005 /* If X has only a single bit that might be nonzero, say, bit I, convert
4006 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4007 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4008 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4009 or a SUBREG of one since we'd be making the expression more
4010 complex if it was just a register. */
4012 if (GET_CODE (temp) != REG
4013 && ! (GET_CODE (temp) == SUBREG
4014 && GET_CODE (SUBREG_REG (temp)) == REG)
4015 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4017 rtx temp1 = simplify_shift_const
4018 (NULL_RTX, ASHIFTRT, mode,
4019 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4020 GET_MODE_BITSIZE (mode) - 1 - i),
4021 GET_MODE_BITSIZE (mode) - 1 - i);
4023 /* If all we did was surround TEMP with the two shifts, we
4024 haven't improved anything, so don't use it. Otherwise,
4025 we are better off with TEMP1. */
4026 if (GET_CODE (temp1) != ASHIFTRT
4027 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4028 || XEXP (XEXP (temp1, 0), 0) != temp)
4034 /* We can't handle truncation to a partial integer mode here
4035 because we don't know the real bitsize of the partial
4037 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4040 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4041 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4042 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4044 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4045 GET_MODE_MASK (mode), NULL_RTX, 0));
4047 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4048 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4049 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4050 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4051 return XEXP (XEXP (x, 0), 0);
4053 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4054 (OP:SI foo:SI) if OP is NEG or ABS. */
4055 if ((GET_CODE (XEXP (x, 0)) == ABS
4056 || GET_CODE (XEXP (x, 0)) == NEG)
4057 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4058 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4059 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4060 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4061 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4063 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4065 if (GET_CODE (XEXP (x, 0)) == SUBREG
4066 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4067 && subreg_lowpart_p (XEXP (x, 0)))
4068 return SUBREG_REG (XEXP (x, 0));
4070 /* If we know that the value is already truncated, we can
4071 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4072 is nonzero for the corresponding modes. But don't do this
4073 for an (LSHIFTRT (MULT ...)) since this will cause problems
4074 with the umulXi3_highpart patterns. */
4075 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4076 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4077 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4078 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4079 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4080 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4081 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4083 /* A truncate of a comparison can be replaced with a subreg if
4084 STORE_FLAG_VALUE permits. This is like the previous test,
4085 but it works even if the comparison is done in a mode larger
4086 than HOST_BITS_PER_WIDE_INT. */
4087 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4088 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4089 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4090 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4092 /* Similarly, a truncate of a register whose value is a
4093 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4095 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4096 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4097 && (temp = get_last_value (XEXP (x, 0)))
4098 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4099 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4103 case FLOAT_TRUNCATE:
4104 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4105 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4106 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4107 return XEXP (XEXP (x, 0), 0);
4109 /* (float_truncate:SF (float_truncate:DF foo:XF))
4110 = (float_truncate:SF foo:XF).
4111 This may eliminate double rounding, so it is unsafe.
4113 (float_truncate:SF (float_extend:XF foo:DF))
4114 = (float_truncate:SF foo:DF).
4116 (float_truncate:DF (float_extend:XF foo:SF))
4117 = (float_extend:SF foo:DF). */
4118 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4119 && flag_unsafe_math_optimizations)
4120 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4121 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4123 > GET_MODE_SIZE (mode)
4124 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4126 XEXP (XEXP (x, 0), 0), mode);
4128 /* (float_truncate (float x)) is (float x) */
4129 if (GET_CODE (XEXP (x, 0)) == FLOAT
4130 && (flag_unsafe_math_optimizations
4131 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4132 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4133 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4134 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4135 return simplify_gen_unary (FLOAT, mode,
4136 XEXP (XEXP (x, 0), 0),
4137 GET_MODE (XEXP (XEXP (x, 0), 0)));
4139 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4140 (OP:SF foo:SF) if OP is NEG or ABS. */
4141 if ((GET_CODE (XEXP (x, 0)) == ABS
4142 || GET_CODE (XEXP (x, 0)) == NEG)
4143 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4144 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4145 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4146 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4148 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4149 is (float_truncate:SF x). */
4150 if (GET_CODE (XEXP (x, 0)) == SUBREG
4151 && subreg_lowpart_p (XEXP (x, 0))
4152 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4153 return SUBREG_REG (XEXP (x, 0));
4156 /* (float_extend (float_extend x)) is (float_extend x)
4158 (float_extend (float x)) is (float x) assuming that double
4159 rounding can't happen.
4161 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4162 || (GET_CODE (XEXP (x, 0)) == FLOAT
4163 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4164 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4165 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4166 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4167 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4168 XEXP (XEXP (x, 0), 0),
4169 GET_MODE (XEXP (XEXP (x, 0), 0)));
4174 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4175 using cc0, in which case we want to leave it as a COMPARE
4176 so we can distinguish it from a register-register-copy. */
4177 if (XEXP (x, 1) == const0_rtx)
4180 /* x - 0 is the same as x unless x's mode has signed zeros and
4181 allows rounding towards -infinity. Under those conditions,
4183 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4184 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4185 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4191 /* (const (const X)) can become (const X). Do it this way rather than
4192 returning the inner CONST since CONST can be shared with a
4194 if (GET_CODE (XEXP (x, 0)) == CONST)
4195 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4200 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4201 can add in an offset. find_split_point will split this address up
4202 again if it doesn't match. */
4203 if (GET_CODE (XEXP (x, 0)) == HIGH
4204 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4210 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4212 if (GET_CODE (XEXP (x, 0)) == MULT
4213 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4217 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4218 in2 = XEXP (XEXP (x, 0), 1);
4219 return gen_binary (MINUS, mode, XEXP (x, 1),
4220 gen_binary (MULT, mode, in1, in2));
4223 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4224 outermost. That's because that's the way indexed addresses are
4225 supposed to appear. This code used to check many more cases, but
4226 they are now checked elsewhere. */
4227 if (GET_CODE (XEXP (x, 0)) == PLUS
4228 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4229 return gen_binary (PLUS, mode,
4230 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4232 XEXP (XEXP (x, 0), 1));
4234 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4235 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4236 bit-field and can be replaced by either a sign_extend or a
4237 sign_extract. The `and' may be a zero_extend and the two
4238 <c>, -<c> constants may be reversed. */
4239 if (GET_CODE (XEXP (x, 0)) == XOR
4240 && GET_CODE (XEXP (x, 1)) == CONST_INT
4241 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4242 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4243 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4244 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4245 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4246 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4247 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4248 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4249 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4250 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4251 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4252 == (unsigned int) i + 1))))
4253 return simplify_shift_const
4254 (NULL_RTX, ASHIFTRT, mode,
4255 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4256 XEXP (XEXP (XEXP (x, 0), 0), 0),
4257 GET_MODE_BITSIZE (mode) - (i + 1)),
4258 GET_MODE_BITSIZE (mode) - (i + 1));
4260 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4261 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4262 is 1. This produces better code than the alternative immediately
4264 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4265 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4266 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4267 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4268 XEXP (XEXP (x, 0), 0),
4269 XEXP (XEXP (x, 0), 1))))
4271 simplify_gen_unary (NEG, mode, reversed, mode);
4273 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4274 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4275 the bitsize of the mode - 1. This allows simplification of
4276 "a = (b & 8) == 0;" */
4277 if (XEXP (x, 1) == constm1_rtx
4278 && GET_CODE (XEXP (x, 0)) != REG
4279 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4280 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4281 && nonzero_bits (XEXP (x, 0), mode) == 1)
4282 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4283 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4284 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4285 GET_MODE_BITSIZE (mode) - 1),
4286 GET_MODE_BITSIZE (mode) - 1);
4288 /* If we are adding two things that have no bits in common, convert
4289 the addition into an IOR. This will often be further simplified,
4290 for example in cases like ((a & 1) + (a & 2)), which can
4293 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4294 && (nonzero_bits (XEXP (x, 0), mode)
4295 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4297 /* Try to simplify the expression further. */
4298 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4299 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4301 /* If we could, great. If not, do not go ahead with the IOR
4302 replacement, since PLUS appears in many special purpose
4303 address arithmetic instructions. */
4304 if (GET_CODE (temp) != CLOBBER && temp != tor)
4310 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4311 by reversing the comparison code if valid. */
4312 if (STORE_FLAG_VALUE == 1
4313 && XEXP (x, 0) == const1_rtx
4314 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4315 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4316 XEXP (XEXP (x, 1), 0),
4317 XEXP (XEXP (x, 1), 1))))
4320 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4321 (and <foo> (const_int pow2-1)) */
4322 if (GET_CODE (XEXP (x, 1)) == AND
4323 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4324 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4325 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4326 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4327 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4329 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4331 if (GET_CODE (XEXP (x, 1)) == MULT
4332 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4336 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4337 in2 = XEXP (XEXP (x, 1), 1);
4338 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4342 /* Canonicalize (minus (neg A) (mult B C)) to
4343 (minus (mult (neg B) C) A). */
4344 if (GET_CODE (XEXP (x, 1)) == MULT
4345 && GET_CODE (XEXP (x, 0)) == NEG)
4349 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4350 in2 = XEXP (XEXP (x, 1), 1);
4351 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4352 XEXP (XEXP (x, 0), 0));
4355 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4357 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4358 return gen_binary (MINUS, mode,
4359 gen_binary (MINUS, mode, XEXP (x, 0),
4360 XEXP (XEXP (x, 1), 0)),
4361 XEXP (XEXP (x, 1), 1));
4365 /* If we have (mult (plus A B) C), apply the distributive law and then
4366 the inverse distributive law to see if things simplify. This
4367 occurs mostly in addresses, often when unrolling loops. */
4369 if (GET_CODE (XEXP (x, 0)) == PLUS)
4371 x = apply_distributive_law
4372 (gen_binary (PLUS, mode,
4373 gen_binary (MULT, mode,
4374 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4375 gen_binary (MULT, mode,
4376 XEXP (XEXP (x, 0), 1),
4377 copy_rtx (XEXP (x, 1)))));
4379 if (GET_CODE (x) != MULT)
4382 /* Try simplify a*(b/c) as (a*b)/c. */
4383 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4384 && GET_CODE (XEXP (x, 0)) == DIV)
4386 rtx tem = simplify_binary_operation (MULT, mode,
4387 XEXP (XEXP (x, 0), 0),
4390 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4395 /* If this is a divide by a power of two, treat it as a shift if
4396 its first operand is a shift. */
4397 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4398 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4399 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4400 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4401 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4402 || GET_CODE (XEXP (x, 0)) == ROTATE
4403 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4404 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4408 case GT: case GTU: case GE: case GEU:
4409 case LT: case LTU: case LE: case LEU:
4410 case UNEQ: case LTGT:
4411 case UNGT: case UNGE:
4412 case UNLT: case UNLE:
4413 case UNORDERED: case ORDERED:
4414 /* If the first operand is a condition code, we can't do anything
4416 if (GET_CODE (XEXP (x, 0)) == COMPARE
4417 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4418 && ! CC0_P (XEXP (x, 0))))
4420 rtx op0 = XEXP (x, 0);
4421 rtx op1 = XEXP (x, 1);
4422 enum rtx_code new_code;
4424 if (GET_CODE (op0) == COMPARE)
4425 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4427 /* Simplify our comparison, if possible. */
4428 new_code = simplify_comparison (code, &op0, &op1);
4430 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4431 if only the low-order bit is possibly nonzero in X (such as when
4432 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4433 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4434 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4437 Remove any ZERO_EXTRACT we made when thinking this was a
4438 comparison. It may now be simpler to use, e.g., an AND. If a
4439 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4440 the call to make_compound_operation in the SET case. */
4442 if (STORE_FLAG_VALUE == 1
4443 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4444 && op1 == const0_rtx
4445 && mode == GET_MODE (op0)
4446 && nonzero_bits (op0, mode) == 1)
4447 return gen_lowpart_for_combine (mode,
4448 expand_compound_operation (op0));
4450 else if (STORE_FLAG_VALUE == 1
4451 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4452 && op1 == const0_rtx
4453 && mode == GET_MODE (op0)
4454 && (num_sign_bit_copies (op0, mode)
4455 == GET_MODE_BITSIZE (mode)))
4457 op0 = expand_compound_operation (op0);
4458 return simplify_gen_unary (NEG, mode,
4459 gen_lowpart_for_combine (mode, op0),
4463 else if (STORE_FLAG_VALUE == 1
4464 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4465 && op1 == const0_rtx
4466 && mode == GET_MODE (op0)
4467 && nonzero_bits (op0, mode) == 1)
4469 op0 = expand_compound_operation (op0);
4470 return gen_binary (XOR, mode,
4471 gen_lowpart_for_combine (mode, op0),
4475 else if (STORE_FLAG_VALUE == 1
4476 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4477 && op1 == const0_rtx
4478 && mode == GET_MODE (op0)
4479 && (num_sign_bit_copies (op0, mode)
4480 == GET_MODE_BITSIZE (mode)))
4482 op0 = expand_compound_operation (op0);
4483 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4486 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4488 if (STORE_FLAG_VALUE == -1
4489 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4490 && op1 == const0_rtx
4491 && (num_sign_bit_copies (op0, mode)
4492 == GET_MODE_BITSIZE (mode)))
4493 return gen_lowpart_for_combine (mode,
4494 expand_compound_operation (op0));
4496 else if (STORE_FLAG_VALUE == -1
4497 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4498 && op1 == const0_rtx
4499 && mode == GET_MODE (op0)
4500 && nonzero_bits (op0, mode) == 1)
4502 op0 = expand_compound_operation (op0);
4503 return simplify_gen_unary (NEG, mode,
4504 gen_lowpart_for_combine (mode, op0),
4508 else if (STORE_FLAG_VALUE == -1
4509 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4510 && op1 == const0_rtx
4511 && mode == GET_MODE (op0)
4512 && (num_sign_bit_copies (op0, mode)
4513 == GET_MODE_BITSIZE (mode)))
4515 op0 = expand_compound_operation (op0);
4516 return simplify_gen_unary (NOT, mode,
4517 gen_lowpart_for_combine (mode, op0),
4521 /* If X is 0/1, (eq X 0) is X-1. */
4522 else if (STORE_FLAG_VALUE == -1
4523 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4524 && op1 == const0_rtx
4525 && mode == GET_MODE (op0)
4526 && nonzero_bits (op0, mode) == 1)
4528 op0 = expand_compound_operation (op0);
4529 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4532 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4533 one bit that might be nonzero, we can convert (ne x 0) to
4534 (ashift x c) where C puts the bit in the sign bit. Remove any
4535 AND with STORE_FLAG_VALUE when we are done, since we are only
4536 going to test the sign bit. */
4537 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4538 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4539 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4540 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4541 && op1 == const0_rtx
4542 && mode == GET_MODE (op0)
4543 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4545 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4546 expand_compound_operation (op0),
4547 GET_MODE_BITSIZE (mode) - 1 - i);
4548 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4554 /* If the code changed, return a whole new comparison. */
4555 if (new_code != code)
4556 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4558 /* Otherwise, keep this operation, but maybe change its operands.
4559 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4560 SUBST (XEXP (x, 0), op0);
4561 SUBST (XEXP (x, 1), op1);
4566 return simplify_if_then_else (x);
4572 /* If we are processing SET_DEST, we are done. */
4576 return expand_compound_operation (x);
4579 return simplify_set (x);
4584 return simplify_logical (x, last);
4587 /* (abs (neg <foo>)) -> (abs <foo>) */
4588 if (GET_CODE (XEXP (x, 0)) == NEG)
4589 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4591 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4593 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4596 /* If operand is something known to be positive, ignore the ABS. */
4597 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4598 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4599 <= HOST_BITS_PER_WIDE_INT)
4600 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4601 & ((HOST_WIDE_INT) 1
4602 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4606 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4607 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4608 return gen_rtx_NEG (mode, XEXP (x, 0));
4613 /* (ffs (*_extend <X>)) = (ffs <X>) */
4614 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4615 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4616 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4621 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4622 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4623 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4627 /* (float (sign_extend <X>)) = (float <X>). */
4628 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4629 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4637 /* If this is a shift by a constant amount, simplify it. */
4638 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4639 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4640 INTVAL (XEXP (x, 1)));
4642 #ifdef SHIFT_COUNT_TRUNCATED
4643 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4645 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4647 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4656 rtx op0 = XEXP (x, 0);
4657 rtx op1 = XEXP (x, 1);
4660 if (GET_CODE (op1) != PARALLEL)
4662 len = XVECLEN (op1, 0);
4664 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4665 && GET_CODE (op0) == VEC_CONCAT)
4667 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4669 /* Try to find the element in the VEC_CONCAT. */
4672 if (GET_MODE (op0) == GET_MODE (x))
4674 if (GET_CODE (op0) == VEC_CONCAT)
4676 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4677 if (op0_size < offset)
4678 op0 = XEXP (op0, 0);
4682 op0 = XEXP (op0, 1);
4700 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4703 simplify_if_then_else (rtx x)
4705 enum machine_mode mode = GET_MODE (x);
4706 rtx cond = XEXP (x, 0);
4707 rtx true_rtx = XEXP (x, 1);
4708 rtx false_rtx = XEXP (x, 2);
4709 enum rtx_code true_code = GET_CODE (cond);
4710 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4713 enum rtx_code false_code;
4716 /* Simplify storing of the truth value. */
4717 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4718 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4720 /* Also when the truth value has to be reversed. */
4722 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4723 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4727 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4728 in it is being compared against certain values. Get the true and false
4729 comparisons and see if that says anything about the value of each arm. */
4732 && ((false_code = combine_reversed_comparison_code (cond))
4734 && GET_CODE (XEXP (cond, 0)) == REG)
4737 rtx from = XEXP (cond, 0);
4738 rtx true_val = XEXP (cond, 1);
4739 rtx false_val = true_val;
4742 /* If FALSE_CODE is EQ, swap the codes and arms. */
4744 if (false_code == EQ)
4746 swapped = 1, true_code = EQ, false_code = NE;
4747 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4750 /* If we are comparing against zero and the expression being tested has
4751 only a single bit that might be nonzero, that is its value when it is
4752 not equal to zero. Similarly if it is known to be -1 or 0. */
4754 if (true_code == EQ && true_val == const0_rtx
4755 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4756 false_code = EQ, false_val = GEN_INT (nzb);
4757 else if (true_code == EQ && true_val == const0_rtx
4758 && (num_sign_bit_copies (from, GET_MODE (from))
4759 == GET_MODE_BITSIZE (GET_MODE (from))))
4760 false_code = EQ, false_val = constm1_rtx;
4762 /* Now simplify an arm if we know the value of the register in the
4763 branch and it is used in the arm. Be careful due to the potential
4764 of locally-shared RTL. */
4766 if (reg_mentioned_p (from, true_rtx))
4767 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4769 pc_rtx, pc_rtx, 0, 0);
4770 if (reg_mentioned_p (from, false_rtx))
4771 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4773 pc_rtx, pc_rtx, 0, 0);
4775 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4776 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4778 true_rtx = XEXP (x, 1);
4779 false_rtx = XEXP (x, 2);
4780 true_code = GET_CODE (cond);
4783 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4784 reversed, do so to avoid needing two sets of patterns for
4785 subtract-and-branch insns. Similarly if we have a constant in the true
4786 arm, the false arm is the same as the first operand of the comparison, or
4787 the false arm is more complicated than the true arm. */
4790 && combine_reversed_comparison_code (cond) != UNKNOWN
4791 && (true_rtx == pc_rtx
4792 || (CONSTANT_P (true_rtx)
4793 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4794 || true_rtx == const0_rtx
4795 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4796 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4797 || (GET_CODE (true_rtx) == SUBREG
4798 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4799 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4800 || reg_mentioned_p (true_rtx, false_rtx)
4801 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4803 true_code = reversed_comparison_code (cond, NULL);
4805 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4808 SUBST (XEXP (x, 1), false_rtx);
4809 SUBST (XEXP (x, 2), true_rtx);
4811 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4814 /* It is possible that the conditional has been simplified out. */
4815 true_code = GET_CODE (cond);
4816 comparison_p = GET_RTX_CLASS (true_code) == '<';
4819 /* If the two arms are identical, we don't need the comparison. */
4821 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4824 /* Convert a == b ? b : a to "a". */
4825 if (true_code == EQ && ! side_effects_p (cond)
4826 && !HONOR_NANS (mode)
4827 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4828 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4830 else if (true_code == NE && ! side_effects_p (cond)
4831 && !HONOR_NANS (mode)
4832 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4833 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4836 /* Look for cases where we have (abs x) or (neg (abs X)). */
4838 if (GET_MODE_CLASS (mode) == MODE_INT
4839 && GET_CODE (false_rtx) == NEG
4840 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4842 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4843 && ! side_effects_p (true_rtx))
4848 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4852 simplify_gen_unary (NEG, mode,
4853 simplify_gen_unary (ABS, mode, true_rtx, mode),
4859 /* Look for MIN or MAX. */
4861 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4863 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4864 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4865 && ! side_effects_p (cond))
4870 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4873 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4876 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4879 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4884 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4885 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4886 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4887 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4888 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4889 neither 1 or -1, but it isn't worth checking for. */
4891 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4893 && GET_MODE_CLASS (mode) == MODE_INT
4894 && ! side_effects_p (x))
4896 rtx t = make_compound_operation (true_rtx, SET);
4897 rtx f = make_compound_operation (false_rtx, SET);
4898 rtx cond_op0 = XEXP (cond, 0);
4899 rtx cond_op1 = XEXP (cond, 1);
4900 enum rtx_code op = NIL, extend_op = NIL;
4901 enum machine_mode m = mode;
4902 rtx z = 0, c1 = NULL_RTX;
4904 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4905 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4906 || GET_CODE (t) == ASHIFT
4907 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4908 && rtx_equal_p (XEXP (t, 0), f))
4909 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4911 /* If an identity-zero op is commutative, check whether there
4912 would be a match if we swapped the operands. */
4913 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4914 || GET_CODE (t) == XOR)
4915 && rtx_equal_p (XEXP (t, 1), f))
4916 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4917 else if (GET_CODE (t) == SIGN_EXTEND
4918 && (GET_CODE (XEXP (t, 0)) == PLUS
4919 || GET_CODE (XEXP (t, 0)) == MINUS
4920 || GET_CODE (XEXP (t, 0)) == IOR
4921 || GET_CODE (XEXP (t, 0)) == XOR
4922 || GET_CODE (XEXP (t, 0)) == ASHIFT
4923 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4924 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4925 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4926 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4927 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4928 && (num_sign_bit_copies (f, GET_MODE (f))
4930 (GET_MODE_BITSIZE (mode)
4931 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4933 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4934 extend_op = SIGN_EXTEND;
4935 m = GET_MODE (XEXP (t, 0));
4937 else if (GET_CODE (t) == SIGN_EXTEND
4938 && (GET_CODE (XEXP (t, 0)) == PLUS
4939 || GET_CODE (XEXP (t, 0)) == IOR
4940 || GET_CODE (XEXP (t, 0)) == XOR)
4941 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4942 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4943 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4944 && (num_sign_bit_copies (f, GET_MODE (f))
4946 (GET_MODE_BITSIZE (mode)
4947 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4949 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4950 extend_op = SIGN_EXTEND;
4951 m = GET_MODE (XEXP (t, 0));
4953 else if (GET_CODE (t) == ZERO_EXTEND
4954 && (GET_CODE (XEXP (t, 0)) == PLUS
4955 || GET_CODE (XEXP (t, 0)) == MINUS
4956 || GET_CODE (XEXP (t, 0)) == IOR
4957 || GET_CODE (XEXP (t, 0)) == XOR
4958 || GET_CODE (XEXP (t, 0)) == ASHIFT
4959 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4960 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4961 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4962 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4963 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4964 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4965 && ((nonzero_bits (f, GET_MODE (f))
4966 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4969 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4970 extend_op = ZERO_EXTEND;
4971 m = GET_MODE (XEXP (t, 0));
4973 else if (GET_CODE (t) == ZERO_EXTEND
4974 && (GET_CODE (XEXP (t, 0)) == PLUS
4975 || GET_CODE (XEXP (t, 0)) == IOR
4976 || GET_CODE (XEXP (t, 0)) == XOR)
4977 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4978 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4979 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4980 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4981 && ((nonzero_bits (f, GET_MODE (f))
4982 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4985 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4986 extend_op = ZERO_EXTEND;
4987 m = GET_MODE (XEXP (t, 0));
4992 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4993 pc_rtx, pc_rtx, 0, 0);
4994 temp = gen_binary (MULT, m, temp,
4995 gen_binary (MULT, m, c1, const_true_rtx));
4996 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4997 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4999 if (extend_op != NIL)
5000 temp = simplify_gen_unary (extend_op, mode, temp, m);
5006 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5007 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5008 negation of a single bit, we can convert this operation to a shift. We
5009 can actually do this more generally, but it doesn't seem worth it. */
5011 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5012 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5013 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5014 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5015 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5016 == GET_MODE_BITSIZE (mode))
5017 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5019 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5020 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5022 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5023 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5024 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5025 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5026 == nonzero_bits (XEXP (cond, 0), mode)
5027 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5028 return XEXP (cond, 0);
5033 /* Simplify X, a SET expression. Return the new expression. */
5036 simplify_set (rtx x)
5038 rtx src = SET_SRC (x);
5039 rtx dest = SET_DEST (x);
5040 enum machine_mode mode
5041 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5045 /* (set (pc) (return)) gets written as (return). */
5046 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5049 /* Now that we know for sure which bits of SRC we are using, see if we can
5050 simplify the expression for the object knowing that we only need the
5053 if (GET_MODE_CLASS (mode) == MODE_INT
5054 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5056 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5057 SUBST (SET_SRC (x), src);
5060 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5061 the comparison result and try to simplify it unless we already have used
5062 undobuf.other_insn. */
5063 if ((GET_MODE_CLASS (mode) == MODE_CC
5064 || GET_CODE (src) == COMPARE
5066 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5067 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5068 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5069 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5071 enum rtx_code old_code = GET_CODE (*cc_use);
5072 enum rtx_code new_code;
5074 int other_changed = 0;
5075 enum machine_mode compare_mode = GET_MODE (dest);
5076 enum machine_mode tmp_mode;
5078 if (GET_CODE (src) == COMPARE)
5079 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5081 op0 = src, op1 = const0_rtx;
5083 /* Check whether the comparison is known at compile time. */
5084 if (GET_MODE (op0) != VOIDmode)
5085 tmp_mode = GET_MODE (op0);
5086 else if (GET_MODE (op1) != VOIDmode)
5087 tmp_mode = GET_MODE (op1);
5089 tmp_mode = compare_mode;
5090 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5091 if (tmp != NULL_RTX)
5093 rtx pat = PATTERN (other_insn);
5094 undobuf.other_insn = other_insn;
5095 SUBST (*cc_use, tmp);
5097 /* Attempt to simplify CC user. */
5098 if (GET_CODE (pat) == SET)
5100 rtx new = simplify_rtx (SET_SRC (pat));
5101 if (new != NULL_RTX)
5102 SUBST (SET_SRC (pat), new);
5105 /* Convert X into a no-op move. */
5106 SUBST (SET_DEST (x), pc_rtx);
5107 SUBST (SET_SRC (x), pc_rtx);
5111 /* Simplify our comparison, if possible. */
5112 new_code = simplify_comparison (old_code, &op0, &op1);
5114 #ifdef EXTRA_CC_MODES
5115 /* If this machine has CC modes other than CCmode, check to see if we
5116 need to use a different CC mode here. */
5117 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5118 #endif /* EXTRA_CC_MODES */
5120 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5121 /* If the mode changed, we have to change SET_DEST, the mode in the
5122 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5123 a hard register, just build new versions with the proper mode. If it
5124 is a pseudo, we lose unless it is only time we set the pseudo, in
5125 which case we can safely change its mode. */
5126 if (compare_mode != GET_MODE (dest))
5128 unsigned int regno = REGNO (dest);
5129 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5131 if (regno < FIRST_PSEUDO_REGISTER
5132 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5134 if (regno >= FIRST_PSEUDO_REGISTER)
5135 SUBST (regno_reg_rtx[regno], new_dest);
5137 SUBST (SET_DEST (x), new_dest);
5138 SUBST (XEXP (*cc_use, 0), new_dest);
5146 /* If the code changed, we have to build a new comparison in
5147 undobuf.other_insn. */
5148 if (new_code != old_code)
5150 unsigned HOST_WIDE_INT mask;
5152 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5155 /* If the only change we made was to change an EQ into an NE or
5156 vice versa, OP0 has only one bit that might be nonzero, and OP1
5157 is zero, check if changing the user of the condition code will
5158 produce a valid insn. If it won't, we can keep the original code
5159 in that insn by surrounding our operation with an XOR. */
5161 if (((old_code == NE && new_code == EQ)
5162 || (old_code == EQ && new_code == NE))
5163 && ! other_changed && op1 == const0_rtx
5164 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5165 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5167 rtx pat = PATTERN (other_insn), note = 0;
5169 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5170 && ! check_asm_operands (pat)))
5172 PUT_CODE (*cc_use, old_code);
5175 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5183 undobuf.other_insn = other_insn;
5186 /* If we are now comparing against zero, change our source if
5187 needed. If we do not use cc0, we always have a COMPARE. */
5188 if (op1 == const0_rtx && dest == cc0_rtx)
5190 SUBST (SET_SRC (x), op0);
5196 /* Otherwise, if we didn't previously have a COMPARE in the
5197 correct mode, we need one. */
5198 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5200 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5205 /* Otherwise, update the COMPARE if needed. */
5206 SUBST (XEXP (src, 0), op0);
5207 SUBST (XEXP (src, 1), op1);
5212 /* Get SET_SRC in a form where we have placed back any
5213 compound expressions. Then do the checks below. */
5214 src = make_compound_operation (src, SET);
5215 SUBST (SET_SRC (x), src);
5218 #ifdef WORD_REGISTER_OPERATIONS
5219 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5220 and X being a REG or (subreg (reg)), we may be able to convert this to
5221 (set (subreg:m2 x) (op)).
5223 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5224 transformation is safe as long as M1 and M2 have the same number
5227 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5228 we cannot apply this transformation because it would create a
5229 paradoxical subreg in SET_DEST. */
5231 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5232 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5233 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5235 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5236 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5237 #ifdef CANNOT_CHANGE_MODE_CLASS
5238 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5239 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5240 GET_MODE (SUBREG_REG (src)),
5243 && (GET_CODE (dest) == REG
5244 || (GET_CODE (dest) == SUBREG
5245 && GET_CODE (SUBREG_REG (dest)) == REG)))
5247 SUBST (SET_DEST (x),
5248 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5250 SUBST (SET_SRC (x), SUBREG_REG (src));
5252 src = SET_SRC (x), dest = SET_DEST (x);
5257 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5260 && GET_CODE (src) == SUBREG
5261 && subreg_lowpart_p (src)
5262 && (GET_MODE_BITSIZE (GET_MODE (src))
5263 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5265 rtx inner = SUBREG_REG (src);
5266 enum machine_mode inner_mode = GET_MODE (inner);
5268 /* Here we make sure that we don't have a sign bit on. */
5269 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5270 && (nonzero_bits (inner, inner_mode)
5271 < ((unsigned HOST_WIDE_INT) 1
5272 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5274 SUBST (SET_SRC (x), inner);
5280 #ifdef LOAD_EXTEND_OP
5281 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5282 would require a paradoxical subreg. Replace the subreg with a
5283 zero_extend to avoid the reload that would otherwise be required. */
5285 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5286 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5287 && SUBREG_BYTE (src) == 0
5288 && (GET_MODE_SIZE (GET_MODE (src))
5289 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5290 && GET_CODE (SUBREG_REG (src)) == MEM)
5293 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5294 GET_MODE (src), SUBREG_REG (src)));
5300 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5301 are comparing an item known to be 0 or -1 against 0, use a logical
5302 operation instead. Check for one of the arms being an IOR of the other
5303 arm with some value. We compute three terms to be IOR'ed together. In
5304 practice, at most two will be nonzero. Then we do the IOR's. */
5306 if (GET_CODE (dest) != PC
5307 && GET_CODE (src) == IF_THEN_ELSE
5308 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5309 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5310 && XEXP (XEXP (src, 0), 1) == const0_rtx
5311 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5312 #ifdef HAVE_conditional_move
5313 && ! can_conditionally_move_p (GET_MODE (src))
5315 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5316 GET_MODE (XEXP (XEXP (src, 0), 0)))
5317 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5318 && ! side_effects_p (src))
5320 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5321 ? XEXP (src, 1) : XEXP (src, 2));
5322 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5323 ? XEXP (src, 2) : XEXP (src, 1));
5324 rtx term1 = const0_rtx, term2, term3;
5326 if (GET_CODE (true_rtx) == IOR
5327 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5328 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5329 else if (GET_CODE (true_rtx) == IOR
5330 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5331 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5332 else if (GET_CODE (false_rtx) == IOR
5333 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5334 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5335 else if (GET_CODE (false_rtx) == IOR
5336 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5337 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5339 term2 = gen_binary (AND, GET_MODE (src),
5340 XEXP (XEXP (src, 0), 0), true_rtx);
5341 term3 = gen_binary (AND, GET_MODE (src),
5342 simplify_gen_unary (NOT, GET_MODE (src),
5343 XEXP (XEXP (src, 0), 0),
5348 gen_binary (IOR, GET_MODE (src),
5349 gen_binary (IOR, GET_MODE (src), term1, term2),
5355 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5356 whole thing fail. */
5357 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5359 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5362 /* Convert this into a field assignment operation, if possible. */
5363 return make_field_assignment (x);
5366 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5367 result. LAST is nonzero if this is the last retry. */
5370 simplify_logical (rtx x, int last)
5372 enum machine_mode mode = GET_MODE (x);
5373 rtx op0 = XEXP (x, 0);
5374 rtx op1 = XEXP (x, 1);
5377 switch (GET_CODE (x))
5380 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5381 insn (and may simplify more). */
5382 if (GET_CODE (op0) == XOR
5383 && rtx_equal_p (XEXP (op0, 0), op1)
5384 && ! side_effects_p (op1))
5385 x = gen_binary (AND, mode,
5386 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5389 if (GET_CODE (op0) == XOR
5390 && rtx_equal_p (XEXP (op0, 1), op1)
5391 && ! side_effects_p (op1))
5392 x = gen_binary (AND, mode,
5393 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5396 /* Similarly for (~(A ^ B)) & A. */
5397 if (GET_CODE (op0) == NOT
5398 && GET_CODE (XEXP (op0, 0)) == XOR
5399 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5400 && ! side_effects_p (op1))
5401 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5403 if (GET_CODE (op0) == NOT
5404 && GET_CODE (XEXP (op0, 0)) == XOR
5405 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5406 && ! side_effects_p (op1))
5407 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5409 /* We can call simplify_and_const_int only if we don't lose
5410 any (sign) bits when converting INTVAL (op1) to
5411 "unsigned HOST_WIDE_INT". */
5412 if (GET_CODE (op1) == CONST_INT
5413 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5414 || INTVAL (op1) > 0))
5416 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5418 /* If we have (ior (and (X C1) C2)) and the next restart would be
5419 the last, simplify this by making C1 as small as possible
5422 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5423 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5424 && GET_CODE (op1) == CONST_INT)
5425 return gen_binary (IOR, mode,
5426 gen_binary (AND, mode, XEXP (op0, 0),
5427 GEN_INT (INTVAL (XEXP (op0, 1))
5428 & ~INTVAL (op1))), op1);
5430 if (GET_CODE (x) != AND)
5433 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5434 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5435 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5438 /* Convert (A | B) & A to A. */
5439 if (GET_CODE (op0) == IOR
5440 && (rtx_equal_p (XEXP (op0, 0), op1)
5441 || rtx_equal_p (XEXP (op0, 1), op1))
5442 && ! side_effects_p (XEXP (op0, 0))
5443 && ! side_effects_p (XEXP (op0, 1)))
5446 /* In the following group of tests (and those in case IOR below),
5447 we start with some combination of logical operations and apply
5448 the distributive law followed by the inverse distributive law.
5449 Most of the time, this results in no change. However, if some of
5450 the operands are the same or inverses of each other, simplifications
5453 For example, (and (ior A B) (not B)) can occur as the result of
5454 expanding a bit field assignment. When we apply the distributive
5455 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5456 which then simplifies to (and (A (not B))).
5458 If we have (and (ior A B) C), apply the distributive law and then
5459 the inverse distributive law to see if things simplify. */
5461 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5463 x = apply_distributive_law
5464 (gen_binary (GET_CODE (op0), mode,
5465 gen_binary (AND, mode, XEXP (op0, 0), op1),
5466 gen_binary (AND, mode, XEXP (op0, 1),
5468 if (GET_CODE (x) != AND)
5472 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5473 return apply_distributive_law
5474 (gen_binary (GET_CODE (op1), mode,
5475 gen_binary (AND, mode, XEXP (op1, 0), op0),
5476 gen_binary (AND, mode, XEXP (op1, 1),
5479 /* Similarly, taking advantage of the fact that
5480 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5482 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5483 return apply_distributive_law
5484 (gen_binary (XOR, mode,
5485 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5486 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5489 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5490 return apply_distributive_law
5491 (gen_binary (XOR, mode,
5492 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5493 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5497 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5498 if (GET_CODE (op1) == CONST_INT
5499 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5500 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5503 /* Convert (A & B) | A to A. */
5504 if (GET_CODE (op0) == AND
5505 && (rtx_equal_p (XEXP (op0, 0), op1)
5506 || rtx_equal_p (XEXP (op0, 1), op1))
5507 && ! side_effects_p (XEXP (op0, 0))
5508 && ! side_effects_p (XEXP (op0, 1)))
5511 /* If we have (ior (and A B) C), apply the distributive law and then
5512 the inverse distributive law to see if things simplify. */
5514 if (GET_CODE (op0) == AND)
5516 x = apply_distributive_law
5517 (gen_binary (AND, mode,
5518 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5519 gen_binary (IOR, mode, XEXP (op0, 1),
5522 if (GET_CODE (x) != IOR)
5526 if (GET_CODE (op1) == AND)
5528 x = apply_distributive_law
5529 (gen_binary (AND, mode,
5530 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5531 gen_binary (IOR, mode, XEXP (op1, 1),
5534 if (GET_CODE (x) != IOR)
5538 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5539 mode size to (rotate A CX). */
5541 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5542 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5543 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5544 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5545 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5546 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5547 == GET_MODE_BITSIZE (mode)))
5548 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5549 (GET_CODE (op0) == ASHIFT
5550 ? XEXP (op0, 1) : XEXP (op1, 1)));
5552 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5553 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5554 does not affect any of the bits in OP1, it can really be done
5555 as a PLUS and we can associate. We do this by seeing if OP1
5556 can be safely shifted left C bits. */
5557 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5558 && GET_CODE (XEXP (op0, 0)) == PLUS
5559 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5560 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5561 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5563 int count = INTVAL (XEXP (op0, 1));
5564 HOST_WIDE_INT mask = INTVAL (op1) << count;
5566 if (mask >> count == INTVAL (op1)
5567 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5569 SUBST (XEXP (XEXP (op0, 0), 1),
5570 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5577 /* If we are XORing two things that have no bits in common,
5578 convert them into an IOR. This helps to detect rotation encoded
5579 using those methods and possibly other simplifications. */
5581 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5582 && (nonzero_bits (op0, mode)
5583 & nonzero_bits (op1, mode)) == 0)
5584 return (gen_binary (IOR, mode, op0, op1));
5586 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5587 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5590 int num_negated = 0;
5592 if (GET_CODE (op0) == NOT)
5593 num_negated++, op0 = XEXP (op0, 0);
5594 if (GET_CODE (op1) == NOT)
5595 num_negated++, op1 = XEXP (op1, 0);
5597 if (num_negated == 2)
5599 SUBST (XEXP (x, 0), op0);
5600 SUBST (XEXP (x, 1), op1);
5602 else if (num_negated == 1)
5604 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5608 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5609 correspond to a machine insn or result in further simplifications
5610 if B is a constant. */
5612 if (GET_CODE (op0) == AND
5613 && rtx_equal_p (XEXP (op0, 1), op1)
5614 && ! side_effects_p (op1))
5615 return gen_binary (AND, mode,
5616 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5619 else if (GET_CODE (op0) == AND
5620 && rtx_equal_p (XEXP (op0, 0), op1)
5621 && ! side_effects_p (op1))
5622 return gen_binary (AND, mode,
5623 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5626 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5627 comparison if STORE_FLAG_VALUE is 1. */
5628 if (STORE_FLAG_VALUE == 1
5629 && op1 == const1_rtx
5630 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5631 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5635 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5636 is (lt foo (const_int 0)), so we can perform the above
5637 simplification if STORE_FLAG_VALUE is 1. */
5639 if (STORE_FLAG_VALUE == 1
5640 && op1 == const1_rtx
5641 && GET_CODE (op0) == LSHIFTRT
5642 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5643 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5644 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5646 /* (xor (comparison foo bar) (const_int sign-bit))
5647 when STORE_FLAG_VALUE is the sign bit. */
5648 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5649 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5650 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5651 && op1 == const_true_rtx
5652 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5653 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5666 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5667 operations" because they can be replaced with two more basic operations.
5668 ZERO_EXTEND is also considered "compound" because it can be replaced with
5669 an AND operation, which is simpler, though only one operation.
5671 The function expand_compound_operation is called with an rtx expression
5672 and will convert it to the appropriate shifts and AND operations,
5673 simplifying at each stage.
5675 The function make_compound_operation is called to convert an expression
5676 consisting of shifts and ANDs into the equivalent compound expression.
5677 It is the inverse of this function, loosely speaking. */
5680 expand_compound_operation (rtx x)
5682 unsigned HOST_WIDE_INT pos = 0, len;
5684 unsigned int modewidth;
5687 switch (GET_CODE (x))
5692 /* We can't necessarily use a const_int for a multiword mode;
5693 it depends on implicitly extending the value.
5694 Since we don't know the right way to extend it,
5695 we can't tell whether the implicit way is right.
5697 Even for a mode that is no wider than a const_int,
5698 we can't win, because we need to sign extend one of its bits through
5699 the rest of it, and we don't know which bit. */
5700 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5703 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5704 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5705 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5706 reloaded. If not for that, MEM's would very rarely be safe.
5708 Reject MODEs bigger than a word, because we might not be able
5709 to reference a two-register group starting with an arbitrary register
5710 (and currently gen_lowpart might crash for a SUBREG). */
5712 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5715 /* Reject MODEs that aren't scalar integers because turning vector
5716 or complex modes into shifts causes problems. */
5718 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5721 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5722 /* If the inner object has VOIDmode (the only way this can happen
5723 is if it is an ASM_OPERANDS), we can't do anything since we don't
5724 know how much masking to do. */
5733 /* If the operand is a CLOBBER, just return it. */
5734 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5737 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5738 || GET_CODE (XEXP (x, 2)) != CONST_INT
5739 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5742 /* Reject MODEs that aren't scalar integers because turning vector
5743 or complex modes into shifts causes problems. */
5745 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5748 len = INTVAL (XEXP (x, 1));
5749 pos = INTVAL (XEXP (x, 2));
5751 /* If this goes outside the object being extracted, replace the object
5752 with a (use (mem ...)) construct that only combine understands
5753 and is used only for this purpose. */
5754 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5755 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5757 if (BITS_BIG_ENDIAN)
5758 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5765 /* Convert sign extension to zero extension, if we know that the high
5766 bit is not set, as this is easier to optimize. It will be converted
5767 back to cheaper alternative in make_extraction. */
5768 if (GET_CODE (x) == SIGN_EXTEND
5769 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5770 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5771 & ~(((unsigned HOST_WIDE_INT)
5772 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5776 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5777 rtx temp2 = expand_compound_operation (temp);
5779 /* Make sure this is a profitable operation. */
5780 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5782 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5788 /* We can optimize some special cases of ZERO_EXTEND. */
5789 if (GET_CODE (x) == ZERO_EXTEND)
5791 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5792 know that the last value didn't have any inappropriate bits
5794 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5795 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5796 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5797 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5798 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5799 return XEXP (XEXP (x, 0), 0);
5801 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5802 if (GET_CODE (XEXP (x, 0)) == SUBREG
5803 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5804 && subreg_lowpart_p (XEXP (x, 0))
5805 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5806 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5807 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5808 return SUBREG_REG (XEXP (x, 0));
5810 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5811 is a comparison and STORE_FLAG_VALUE permits. This is like
5812 the first case, but it works even when GET_MODE (x) is larger
5813 than HOST_WIDE_INT. */
5814 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5815 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5816 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5817 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5818 <= HOST_BITS_PER_WIDE_INT)
5819 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5820 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5821 return XEXP (XEXP (x, 0), 0);
5823 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5824 if (GET_CODE (XEXP (x, 0)) == SUBREG
5825 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5826 && subreg_lowpart_p (XEXP (x, 0))
5827 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5828 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5829 <= HOST_BITS_PER_WIDE_INT)
5830 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5831 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5832 return SUBREG_REG (XEXP (x, 0));
5836 /* If we reach here, we want to return a pair of shifts. The inner
5837 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5838 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5839 logical depending on the value of UNSIGNEDP.
5841 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5842 converted into an AND of a shift.
5844 We must check for the case where the left shift would have a negative
5845 count. This can happen in a case like (x >> 31) & 255 on machines
5846 that can't shift by a constant. On those machines, we would first
5847 combine the shift with the AND to produce a variable-position
5848 extraction. Then the constant of 31 would be substituted in to produce
5849 a such a position. */
5851 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5852 if (modewidth + len >= pos)
5853 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5855 simplify_shift_const (NULL_RTX, ASHIFT,
5858 modewidth - pos - len),
5861 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5862 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5863 simplify_shift_const (NULL_RTX, LSHIFTRT,
5866 ((HOST_WIDE_INT) 1 << len) - 1);
5868 /* Any other cases we can't handle. */
5871 /* If we couldn't do this for some reason, return the original
5873 if (GET_CODE (tem) == CLOBBER)
5879 /* X is a SET which contains an assignment of one object into
5880 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5881 or certain SUBREGS). If possible, convert it into a series of
5884 We half-heartedly support variable positions, but do not at all
5885 support variable lengths. */
5888 expand_field_assignment (rtx x)
5891 rtx pos; /* Always counts from low bit. */
5894 enum machine_mode compute_mode;
5896 /* Loop until we find something we can't simplify. */
5899 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5900 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5902 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5903 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5904 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5906 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5907 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5909 inner = XEXP (SET_DEST (x), 0);
5910 len = INTVAL (XEXP (SET_DEST (x), 1));
5911 pos = XEXP (SET_DEST (x), 2);
5913 /* If the position is constant and spans the width of INNER,
5914 surround INNER with a USE to indicate this. */
5915 if (GET_CODE (pos) == CONST_INT
5916 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5917 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5919 if (BITS_BIG_ENDIAN)
5921 if (GET_CODE (pos) == CONST_INT)
5922 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5924 else if (GET_CODE (pos) == MINUS
5925 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5926 && (INTVAL (XEXP (pos, 1))
5927 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5928 /* If position is ADJUST - X, new position is X. */
5929 pos = XEXP (pos, 0);
5931 pos = gen_binary (MINUS, GET_MODE (pos),
5932 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5938 /* A SUBREG between two modes that occupy the same numbers of words
5939 can be done by moving the SUBREG to the source. */
5940 else if (GET_CODE (SET_DEST (x)) == SUBREG
5941 /* We need SUBREGs to compute nonzero_bits properly. */
5942 && nonzero_sign_valid
5943 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5944 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5945 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5946 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5948 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5949 gen_lowpart_for_combine
5950 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5957 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5958 inner = SUBREG_REG (inner);
5960 compute_mode = GET_MODE (inner);
5962 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5963 if (! SCALAR_INT_MODE_P (compute_mode))
5965 enum machine_mode imode;
5967 /* Don't do anything for vector or complex integral types. */
5968 if (! FLOAT_MODE_P (compute_mode))
5971 /* Try to find an integral mode to pun with. */
5972 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5973 if (imode == BLKmode)
5976 compute_mode = imode;
5977 inner = gen_lowpart_for_combine (imode, inner);
5980 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5981 if (len < HOST_BITS_PER_WIDE_INT)
5982 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5986 /* Now compute the equivalent expression. Make a copy of INNER
5987 for the SET_DEST in case it is a MEM into which we will substitute;
5988 we don't want shared RTL in that case. */
5990 (VOIDmode, copy_rtx (inner),
5991 gen_binary (IOR, compute_mode,
5992 gen_binary (AND, compute_mode,
5993 simplify_gen_unary (NOT, compute_mode,
5999 gen_binary (ASHIFT, compute_mode,
6000 gen_binary (AND, compute_mode,
6001 gen_lowpart_for_combine
6002 (compute_mode, SET_SRC (x)),
6010 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6011 it is an RTX that represents a variable starting position; otherwise,
6012 POS is the (constant) starting bit position (counted from the LSB).
6014 INNER may be a USE. This will occur when we started with a bitfield
6015 that went outside the boundary of the object in memory, which is
6016 allowed on most machines. To isolate this case, we produce a USE
6017 whose mode is wide enough and surround the MEM with it. The only
6018 code that understands the USE is this routine. If it is not removed,
6019 it will cause the resulting insn not to match.
6021 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6024 IN_DEST is nonzero if this is a reference in the destination of a
6025 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6026 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6029 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6030 ZERO_EXTRACT should be built even for bits starting at bit 0.
6032 MODE is the desired mode of the result (if IN_DEST == 0).
6034 The result is an RTX for the extraction or NULL_RTX if the target
6038 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6039 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6040 int in_dest, int in_compare)
6042 /* This mode describes the size of the storage area
6043 to fetch the overall value from. Within that, we
6044 ignore the POS lowest bits, etc. */
6045 enum machine_mode is_mode = GET_MODE (inner);
6046 enum machine_mode inner_mode;
6047 enum machine_mode wanted_inner_mode = byte_mode;
6048 enum machine_mode wanted_inner_reg_mode = word_mode;
6049 enum machine_mode pos_mode = word_mode;
6050 enum machine_mode extraction_mode = word_mode;
6051 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6054 rtx orig_pos_rtx = pos_rtx;
6055 HOST_WIDE_INT orig_pos;
6057 /* Get some information about INNER and get the innermost object. */
6058 if (GET_CODE (inner) == USE)
6059 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6060 /* We don't need to adjust the position because we set up the USE
6061 to pretend that it was a full-word object. */
6062 spans_byte = 1, inner = XEXP (inner, 0);
6063 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6065 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6066 consider just the QI as the memory to extract from.
6067 The subreg adds or removes high bits; its mode is
6068 irrelevant to the meaning of this extraction,
6069 since POS and LEN count from the lsb. */
6070 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6071 is_mode = GET_MODE (SUBREG_REG (inner));
6072 inner = SUBREG_REG (inner);
6074 else if (GET_CODE (inner) == ASHIFT
6075 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6076 && pos_rtx == 0 && pos == 0
6077 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6079 /* We're extracting the least significant bits of an rtx
6080 (ashift X (const_int C)), where LEN > C. Extract the
6081 least significant (LEN - C) bits of X, giving an rtx
6082 whose mode is MODE, then shift it left C times. */
6083 new = make_extraction (mode, XEXP (inner, 0),
6084 0, 0, len - INTVAL (XEXP (inner, 1)),
6085 unsignedp, in_dest, in_compare);
6087 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6090 inner_mode = GET_MODE (inner);
6092 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6093 pos = INTVAL (pos_rtx), pos_rtx = 0;
6095 /* See if this can be done without an extraction. We never can if the
6096 width of the field is not the same as that of some integer mode. For
6097 registers, we can only avoid the extraction if the position is at the
6098 low-order bit and this is either not in the destination or we have the
6099 appropriate STRICT_LOW_PART operation available.
6101 For MEM, we can avoid an extract if the field starts on an appropriate
6102 boundary and we can change the mode of the memory reference. However,
6103 we cannot directly access the MEM if we have a USE and the underlying
6104 MEM is not TMODE. This combination means that MEM was being used in a
6105 context where bits outside its mode were being referenced; that is only
6106 valid in bit-field insns. */
6108 if (tmode != BLKmode
6109 && ! (spans_byte && inner_mode != tmode)
6110 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6111 && GET_CODE (inner) != MEM
6113 || (GET_CODE (inner) == REG
6114 && have_insn_for (STRICT_LOW_PART, tmode))))
6115 || (GET_CODE (inner) == MEM && pos_rtx == 0
6117 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6118 : BITS_PER_UNIT)) == 0
6119 /* We can't do this if we are widening INNER_MODE (it
6120 may not be aligned, for one thing). */
6121 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6122 && (inner_mode == tmode
6123 || (! mode_dependent_address_p (XEXP (inner, 0))
6124 && ! MEM_VOLATILE_P (inner))))))
6126 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6127 field. If the original and current mode are the same, we need not
6128 adjust the offset. Otherwise, we do if bytes big endian.
6130 If INNER is not a MEM, get a piece consisting of just the field
6131 of interest (in this case POS % BITS_PER_WORD must be 0). */
6133 if (GET_CODE (inner) == MEM)
6135 HOST_WIDE_INT offset;
6137 /* POS counts from lsb, but make OFFSET count in memory order. */
6138 if (BYTES_BIG_ENDIAN)
6139 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6141 offset = pos / BITS_PER_UNIT;
6143 new = adjust_address_nv (inner, tmode, offset);
6145 else if (GET_CODE (inner) == REG)
6147 if (tmode != inner_mode)
6151 /* We can't call gen_lowpart_for_combine here since we always want
6152 a SUBREG and it would sometimes return a new hard register. */
6153 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6155 if (WORDS_BIG_ENDIAN
6156 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6157 final_word = ((GET_MODE_SIZE (inner_mode)
6158 - GET_MODE_SIZE (tmode))
6159 / UNITS_PER_WORD) - final_word;
6161 final_word *= UNITS_PER_WORD;
6162 if (BYTES_BIG_ENDIAN &&
6163 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6164 final_word += (GET_MODE_SIZE (inner_mode)
6165 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6167 /* Avoid creating invalid subregs, for example when
6168 simplifying (x>>32)&255. */
6169 if (final_word >= GET_MODE_SIZE (inner_mode))
6172 new = gen_rtx_SUBREG (tmode, inner, final_word);
6175 new = gen_lowpart_for_combine (tmode, inner);
6181 new = force_to_mode (inner, tmode,
6182 len >= HOST_BITS_PER_WIDE_INT
6183 ? ~(unsigned HOST_WIDE_INT) 0
6184 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6187 /* If this extraction is going into the destination of a SET,
6188 make a STRICT_LOW_PART unless we made a MEM. */
6191 return (GET_CODE (new) == MEM ? new
6192 : (GET_CODE (new) != SUBREG
6193 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6194 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6199 if (GET_CODE (new) == CONST_INT)
6200 return gen_int_mode (INTVAL (new), mode);
6202 /* If we know that no extraneous bits are set, and that the high
6203 bit is not set, convert the extraction to the cheaper of
6204 sign and zero extension, that are equivalent in these cases. */
6205 if (flag_expensive_optimizations
6206 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6207 && ((nonzero_bits (new, tmode)
6208 & ~(((unsigned HOST_WIDE_INT)
6209 GET_MODE_MASK (tmode))
6213 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6214 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6216 /* Prefer ZERO_EXTENSION, since it gives more information to
6218 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6223 /* Otherwise, sign- or zero-extend unless we already are in the
6226 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6230 /* Unless this is a COMPARE or we have a funny memory reference,
6231 don't do anything with zero-extending field extracts starting at
6232 the low-order bit since they are simple AND operations. */
6233 if (pos_rtx == 0 && pos == 0 && ! in_dest
6234 && ! in_compare && ! spans_byte && unsignedp)
6237 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6238 we would be spanning bytes or if the position is not a constant and the
6239 length is not 1. In all other cases, we would only be going outside
6240 our object in cases when an original shift would have been
6242 if (! spans_byte && GET_CODE (inner) == MEM
6243 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6244 || (pos_rtx != 0 && len != 1)))
6247 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6248 and the mode for the result. */
6249 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6251 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6252 pos_mode = mode_for_extraction (EP_insv, 2);
6253 extraction_mode = mode_for_extraction (EP_insv, 3);
6256 if (! in_dest && unsignedp
6257 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6259 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6260 pos_mode = mode_for_extraction (EP_extzv, 3);
6261 extraction_mode = mode_for_extraction (EP_extzv, 0);
6264 if (! in_dest && ! unsignedp
6265 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6267 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6268 pos_mode = mode_for_extraction (EP_extv, 3);
6269 extraction_mode = mode_for_extraction (EP_extv, 0);
6272 /* Never narrow an object, since that might not be safe. */
6274 if (mode != VOIDmode
6275 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6276 extraction_mode = mode;
6278 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6279 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6280 pos_mode = GET_MODE (pos_rtx);
6282 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6283 if we have to change the mode of memory and cannot, the desired mode is
6285 if (GET_CODE (inner) != MEM)
6286 wanted_inner_mode = wanted_inner_reg_mode;
6287 else if (inner_mode != wanted_inner_mode
6288 && (mode_dependent_address_p (XEXP (inner, 0))
6289 || MEM_VOLATILE_P (inner)))
6290 wanted_inner_mode = extraction_mode;
6294 if (BITS_BIG_ENDIAN)
6296 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6297 BITS_BIG_ENDIAN style. If position is constant, compute new
6298 position. Otherwise, build subtraction.
6299 Note that POS is relative to the mode of the original argument.
6300 If it's a MEM we need to recompute POS relative to that.
6301 However, if we're extracting from (or inserting into) a register,
6302 we want to recompute POS relative to wanted_inner_mode. */
6303 int width = (GET_CODE (inner) == MEM
6304 ? GET_MODE_BITSIZE (is_mode)
6305 : GET_MODE_BITSIZE (wanted_inner_mode));
6308 pos = width - len - pos;
6311 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6312 /* POS may be less than 0 now, but we check for that below.
6313 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6316 /* If INNER has a wider mode, make it smaller. If this is a constant
6317 extract, try to adjust the byte to point to the byte containing
6319 if (wanted_inner_mode != VOIDmode
6320 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6321 && ((GET_CODE (inner) == MEM
6322 && (inner_mode == wanted_inner_mode
6323 || (! mode_dependent_address_p (XEXP (inner, 0))
6324 && ! MEM_VOLATILE_P (inner))))))
6328 /* The computations below will be correct if the machine is big
6329 endian in both bits and bytes or little endian in bits and bytes.
6330 If it is mixed, we must adjust. */
6332 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6333 adjust OFFSET to compensate. */
6334 if (BYTES_BIG_ENDIAN
6336 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6337 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6339 /* If this is a constant position, we can move to the desired byte. */
6342 offset += pos / BITS_PER_UNIT;
6343 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6346 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6348 && is_mode != wanted_inner_mode)
6349 offset = (GET_MODE_SIZE (is_mode)
6350 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6352 if (offset != 0 || inner_mode != wanted_inner_mode)
6353 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6356 /* If INNER is not memory, we can always get it into the proper mode. If we
6357 are changing its mode, POS must be a constant and smaller than the size
6359 else if (GET_CODE (inner) != MEM)
6361 if (GET_MODE (inner) != wanted_inner_mode
6363 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6366 inner = force_to_mode (inner, wanted_inner_mode,
6368 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6369 ? ~(unsigned HOST_WIDE_INT) 0
6370 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6375 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6376 have to zero extend. Otherwise, we can just use a SUBREG. */
6378 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6380 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6382 /* If we know that no extraneous bits are set, and that the high
6383 bit is not set, convert extraction to cheaper one - either
6384 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6386 if (flag_expensive_optimizations
6387 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6388 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6389 & ~(((unsigned HOST_WIDE_INT)
6390 GET_MODE_MASK (GET_MODE (pos_rtx)))
6394 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6396 /* Prefer ZERO_EXTENSION, since it gives more information to
6398 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6403 else if (pos_rtx != 0
6404 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6405 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6407 /* Make POS_RTX unless we already have it and it is correct. If we don't
6408 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6410 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6411 pos_rtx = orig_pos_rtx;
6413 else if (pos_rtx == 0)
6414 pos_rtx = GEN_INT (pos);
6416 /* Make the required operation. See if we can use existing rtx. */
6417 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6418 extraction_mode, inner, GEN_INT (len), pos_rtx);
6420 new = gen_lowpart_for_combine (mode, new);
6425 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6426 with any other operations in X. Return X without that shift if so. */
6429 extract_left_shift (rtx x, int count)
6431 enum rtx_code code = GET_CODE (x);
6432 enum machine_mode mode = GET_MODE (x);
6438 /* This is the shift itself. If it is wide enough, we will return
6439 either the value being shifted if the shift count is equal to
6440 COUNT or a shift for the difference. */
6441 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6442 && INTVAL (XEXP (x, 1)) >= count)
6443 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6444 INTVAL (XEXP (x, 1)) - count);
6448 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6449 return simplify_gen_unary (code, mode, tem, mode);
6453 case PLUS: case IOR: case XOR: case AND:
6454 /* If we can safely shift this constant and we find the inner shift,
6455 make a new operation. */
6456 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6457 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6458 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6459 return gen_binary (code, mode, tem,
6460 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6471 /* Look at the expression rooted at X. Look for expressions
6472 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6473 Form these expressions.
6475 Return the new rtx, usually just X.
6477 Also, for machines like the VAX that don't have logical shift insns,
6478 try to convert logical to arithmetic shift operations in cases where
6479 they are equivalent. This undoes the canonicalizations to logical
6480 shifts done elsewhere.
6482 We try, as much as possible, to re-use rtl expressions to save memory.
6484 IN_CODE says what kind of expression we are processing. Normally, it is
6485 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6486 being kludges), it is MEM. When processing the arguments of a comparison
6487 or a COMPARE against zero, it is COMPARE. */
6490 make_compound_operation (rtx x, enum rtx_code in_code)
6492 enum rtx_code code = GET_CODE (x);
6493 enum machine_mode mode = GET_MODE (x);
6494 int mode_width = GET_MODE_BITSIZE (mode);
6496 enum rtx_code next_code;
6502 /* Select the code to be used in recursive calls. Once we are inside an
6503 address, we stay there. If we have a comparison, set to COMPARE,
6504 but once inside, go back to our default of SET. */
6506 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6507 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6508 && XEXP (x, 1) == const0_rtx) ? COMPARE
6509 : in_code == COMPARE ? SET : in_code);
6511 /* Process depending on the code of this operation. If NEW is set
6512 nonzero, it will be returned. */
6517 /* Convert shifts by constants into multiplications if inside
6519 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6520 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6521 && INTVAL (XEXP (x, 1)) >= 0)
6523 new = make_compound_operation (XEXP (x, 0), next_code);
6524 new = gen_rtx_MULT (mode, new,
6525 GEN_INT ((HOST_WIDE_INT) 1
6526 << INTVAL (XEXP (x, 1))));
6531 /* If the second operand is not a constant, we can't do anything
6533 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6536 /* If the constant is a power of two minus one and the first operand
6537 is a logical right shift, make an extraction. */
6538 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6539 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6541 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6542 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6543 0, in_code == COMPARE);
6546 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6547 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6548 && subreg_lowpart_p (XEXP (x, 0))
6549 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6550 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6552 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6554 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6555 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6556 0, in_code == COMPARE);
6558 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6559 else if ((GET_CODE (XEXP (x, 0)) == XOR
6560 || GET_CODE (XEXP (x, 0)) == IOR)
6561 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6562 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6563 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6565 /* Apply the distributive law, and then try to make extractions. */
6566 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6567 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6569 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6571 new = make_compound_operation (new, in_code);
6574 /* If we are have (and (rotate X C) M) and C is larger than the number
6575 of bits in M, this is an extraction. */
6577 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6578 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6579 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6580 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6582 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6583 new = make_extraction (mode, new,
6584 (GET_MODE_BITSIZE (mode)
6585 - INTVAL (XEXP (XEXP (x, 0), 1))),
6586 NULL_RTX, i, 1, 0, in_code == COMPARE);
6589 /* On machines without logical shifts, if the operand of the AND is
6590 a logical shift and our mask turns off all the propagated sign
6591 bits, we can replace the logical shift with an arithmetic shift. */
6592 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6593 && !have_insn_for (LSHIFTRT, mode)
6594 && have_insn_for (ASHIFTRT, mode)
6595 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6596 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6597 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6598 && mode_width <= HOST_BITS_PER_WIDE_INT)
6600 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6602 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6603 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6605 gen_rtx_ASHIFTRT (mode,
6606 make_compound_operation
6607 (XEXP (XEXP (x, 0), 0), next_code),
6608 XEXP (XEXP (x, 0), 1)));
6611 /* If the constant is one less than a power of two, this might be
6612 representable by an extraction even if no shift is present.
6613 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6614 we are in a COMPARE. */
6615 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6616 new = make_extraction (mode,
6617 make_compound_operation (XEXP (x, 0),
6619 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6621 /* If we are in a comparison and this is an AND with a power of two,
6622 convert this into the appropriate bit extract. */
6623 else if (in_code == COMPARE
6624 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6625 new = make_extraction (mode,
6626 make_compound_operation (XEXP (x, 0),
6628 i, NULL_RTX, 1, 1, 0, 1);
6633 /* If the sign bit is known to be zero, replace this with an
6634 arithmetic shift. */
6635 if (have_insn_for (ASHIFTRT, mode)
6636 && ! have_insn_for (LSHIFTRT, mode)
6637 && mode_width <= HOST_BITS_PER_WIDE_INT
6638 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6640 new = gen_rtx_ASHIFTRT (mode,
6641 make_compound_operation (XEXP (x, 0),
6647 /* ... fall through ... */
6653 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6654 this is a SIGN_EXTRACT. */
6655 if (GET_CODE (rhs) == CONST_INT
6656 && GET_CODE (lhs) == ASHIFT
6657 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6658 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6660 new = make_compound_operation (XEXP (lhs, 0), next_code);
6661 new = make_extraction (mode, new,
6662 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6663 NULL_RTX, mode_width - INTVAL (rhs),
6664 code == LSHIFTRT, 0, in_code == COMPARE);
6668 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6669 If so, try to merge the shifts into a SIGN_EXTEND. We could
6670 also do this for some cases of SIGN_EXTRACT, but it doesn't
6671 seem worth the effort; the case checked for occurs on Alpha. */
6673 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6674 && ! (GET_CODE (lhs) == SUBREG
6675 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6676 && GET_CODE (rhs) == CONST_INT
6677 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6678 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6679 new = make_extraction (mode, make_compound_operation (new, next_code),
6680 0, NULL_RTX, mode_width - INTVAL (rhs),
6681 code == LSHIFTRT, 0, in_code == COMPARE);
6686 /* Call ourselves recursively on the inner expression. If we are
6687 narrowing the object and it has a different RTL code from
6688 what it originally did, do this SUBREG as a force_to_mode. */
6690 tem = make_compound_operation (SUBREG_REG (x), in_code);
6691 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6692 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6693 && subreg_lowpart_p (x))
6695 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6698 /* If we have something other than a SUBREG, we might have
6699 done an expansion, so rerun ourselves. */
6700 if (GET_CODE (newer) != SUBREG)
6701 newer = make_compound_operation (newer, in_code);
6706 /* If this is a paradoxical subreg, and the new code is a sign or
6707 zero extension, omit the subreg and widen the extension. If it
6708 is a regular subreg, we can still get rid of the subreg by not
6709 widening so much, or in fact removing the extension entirely. */
6710 if ((GET_CODE (tem) == SIGN_EXTEND
6711 || GET_CODE (tem) == ZERO_EXTEND)
6712 && subreg_lowpart_p (x))
6714 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6715 || (GET_MODE_SIZE (mode) >
6716 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6718 if (! SCALAR_INT_MODE_P (mode))
6720 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6723 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6734 x = gen_lowpart_for_combine (mode, new);
6735 code = GET_CODE (x);
6738 /* Now recursively process each operand of this operation. */
6739 fmt = GET_RTX_FORMAT (code);
6740 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6743 new = make_compound_operation (XEXP (x, i), next_code);
6744 SUBST (XEXP (x, i), new);
6750 /* Given M see if it is a value that would select a field of bits
6751 within an item, but not the entire word. Return -1 if not.
6752 Otherwise, return the starting position of the field, where 0 is the
6755 *PLEN is set to the length of the field. */
6758 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6760 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6761 int pos = exact_log2 (m & -m);
6767 /* Now shift off the low-order zero bits and see if we have a power of
6769 len = exact_log2 ((m >> pos) + 1);
6778 /* See if X can be simplified knowing that we will only refer to it in
6779 MODE and will only refer to those bits that are nonzero in MASK.
6780 If other bits are being computed or if masking operations are done
6781 that select a superset of the bits in MASK, they can sometimes be
6784 Return a possibly simplified expression, but always convert X to
6785 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6787 Also, if REG is nonzero and X is a register equal in value to REG,
6790 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6791 are all off in X. This is used when X will be complemented, by either
6792 NOT, NEG, or XOR. */
6795 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6796 rtx reg, int just_select)
6798 enum rtx_code code = GET_CODE (x);
6799 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6800 enum machine_mode op_mode;
6801 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6804 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6805 code below will do the wrong thing since the mode of such an
6806 expression is VOIDmode.
6808 Also do nothing if X is a CLOBBER; this can happen if X was
6809 the return value from a call to gen_lowpart_for_combine. */
6810 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6813 /* We want to perform the operation is its present mode unless we know
6814 that the operation is valid in MODE, in which case we do the operation
6816 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6817 && have_insn_for (code, mode))
6818 ? mode : GET_MODE (x));
6820 /* It is not valid to do a right-shift in a narrower mode
6821 than the one it came in with. */
6822 if ((code == LSHIFTRT || code == ASHIFTRT)
6823 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6824 op_mode = GET_MODE (x);
6826 /* Truncate MASK to fit OP_MODE. */
6828 mask &= GET_MODE_MASK (op_mode);
6830 /* When we have an arithmetic operation, or a shift whose count we
6831 do not know, we need to assume that all bit the up to the highest-order
6832 bit in MASK will be needed. This is how we form such a mask. */
6834 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6835 ? GET_MODE_MASK (op_mode)
6836 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6839 fuller_mask = ~(HOST_WIDE_INT) 0;
6841 /* Determine what bits of X are guaranteed to be (non)zero. */
6842 nonzero = nonzero_bits (x, mode);
6844 /* If none of the bits in X are needed, return a zero. */
6845 if (! just_select && (nonzero & mask) == 0)
6848 /* If X is a CONST_INT, return a new one. Do this here since the
6849 test below will fail. */
6850 if (GET_CODE (x) == CONST_INT)
6852 if (SCALAR_INT_MODE_P (mode))
6853 return gen_int_mode (INTVAL (x) & mask, mode);
6856 x = GEN_INT (INTVAL (x) & mask);
6857 return gen_lowpart_common (mode, x);
6861 /* If X is narrower than MODE and we want all the bits in X's mode, just
6862 get X in the proper mode. */
6863 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6864 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6865 return gen_lowpart_for_combine (mode, x);
6867 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6868 MASK are already known to be zero in X, we need not do anything. */
6869 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6875 /* If X is a (clobber (const_int)), return it since we know we are
6876 generating something that won't match. */
6880 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6881 spanned the boundary of the MEM. If we are now masking so it is
6882 within that boundary, we don't need the USE any more. */
6883 if (! BITS_BIG_ENDIAN
6884 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6885 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6892 x = expand_compound_operation (x);
6893 if (GET_CODE (x) != code)
6894 return force_to_mode (x, mode, mask, reg, next_select);
6898 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6899 || rtx_equal_p (reg, get_last_value (x))))
6904 if (subreg_lowpart_p (x)
6905 /* We can ignore the effect of this SUBREG if it narrows the mode or
6906 if the constant masks to zero all the bits the mode doesn't
6908 && ((GET_MODE_SIZE (GET_MODE (x))
6909 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6911 & GET_MODE_MASK (GET_MODE (x))
6912 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6913 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6917 /* If this is an AND with a constant, convert it into an AND
6918 whose constant is the AND of that constant with MASK. If it
6919 remains an AND of MASK, delete it since it is redundant. */
6921 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6923 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6924 mask & INTVAL (XEXP (x, 1)));
6926 /* If X is still an AND, see if it is an AND with a mask that
6927 is just some low-order bits. If so, and it is MASK, we don't
6930 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6931 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6935 /* If it remains an AND, try making another AND with the bits
6936 in the mode mask that aren't in MASK turned on. If the
6937 constant in the AND is wide enough, this might make a
6938 cheaper constant. */
6940 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6941 && GET_MODE_MASK (GET_MODE (x)) != mask
6942 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6944 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6945 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6946 int width = GET_MODE_BITSIZE (GET_MODE (x));
6949 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6950 number, sign extend it. */
6951 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6952 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6953 cval |= (HOST_WIDE_INT) -1 << width;
6955 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6956 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6966 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6967 low-order bits (as in an alignment operation) and FOO is already
6968 aligned to that boundary, mask C1 to that boundary as well.
6969 This may eliminate that PLUS and, later, the AND. */
6972 unsigned int width = GET_MODE_BITSIZE (mode);
6973 unsigned HOST_WIDE_INT smask = mask;
6975 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6976 number, sign extend it. */
6978 if (width < HOST_BITS_PER_WIDE_INT
6979 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6980 smask |= (HOST_WIDE_INT) -1 << width;
6982 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6983 && exact_log2 (- smask) >= 0
6984 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6985 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6986 return force_to_mode (plus_constant (XEXP (x, 0),
6987 (INTVAL (XEXP (x, 1)) & smask)),
6988 mode, smask, reg, next_select);
6991 /* ... fall through ... */
6994 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6995 most significant bit in MASK since carries from those bits will
6996 affect the bits we are interested in. */
7001 /* If X is (minus C Y) where C's least set bit is larger than any bit
7002 in the mask, then we may replace with (neg Y). */
7003 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7004 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7005 & -INTVAL (XEXP (x, 0))))
7008 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7010 return force_to_mode (x, mode, mask, reg, next_select);
7013 /* Similarly, if C contains every bit in the fuller_mask, then we may
7014 replace with (not Y). */
7015 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7016 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7017 == INTVAL (XEXP (x, 0))))
7019 x = simplify_gen_unary (NOT, GET_MODE (x),
7020 XEXP (x, 1), GET_MODE (x));
7021 return force_to_mode (x, mode, mask, reg, next_select);
7029 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7030 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7031 operation which may be a bitfield extraction. Ensure that the
7032 constant we form is not wider than the mode of X. */
7034 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7035 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7036 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7037 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7038 && GET_CODE (XEXP (x, 1)) == CONST_INT
7039 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7040 + floor_log2 (INTVAL (XEXP (x, 1))))
7041 < GET_MODE_BITSIZE (GET_MODE (x)))
7042 && (INTVAL (XEXP (x, 1))
7043 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7045 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7046 << INTVAL (XEXP (XEXP (x, 0), 1)));
7047 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7048 XEXP (XEXP (x, 0), 0), temp);
7049 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7050 XEXP (XEXP (x, 0), 1));
7051 return force_to_mode (x, mode, mask, reg, next_select);
7055 /* For most binary operations, just propagate into the operation and
7056 change the mode if we have an operation of that mode. */
7058 op0 = gen_lowpart_for_combine (op_mode,
7059 force_to_mode (XEXP (x, 0), mode, mask,
7061 op1 = gen_lowpart_for_combine (op_mode,
7062 force_to_mode (XEXP (x, 1), mode, mask,
7065 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7066 x = gen_binary (code, op_mode, op0, op1);
7070 /* For left shifts, do the same, but just for the first operand.
7071 However, we cannot do anything with shifts where we cannot
7072 guarantee that the counts are smaller than the size of the mode
7073 because such a count will have a different meaning in a
7076 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7077 && INTVAL (XEXP (x, 1)) >= 0
7078 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7079 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7080 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7081 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7084 /* If the shift count is a constant and we can do arithmetic in
7085 the mode of the shift, refine which bits we need. Otherwise, use the
7086 conservative form of the mask. */
7087 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7088 && INTVAL (XEXP (x, 1)) >= 0
7089 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7090 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7091 mask >>= INTVAL (XEXP (x, 1));
7095 op0 = gen_lowpart_for_combine (op_mode,
7096 force_to_mode (XEXP (x, 0), op_mode,
7097 mask, reg, next_select));
7099 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7100 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7104 /* Here we can only do something if the shift count is a constant,
7105 this shift constant is valid for the host, and we can do arithmetic
7108 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7109 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7110 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7112 rtx inner = XEXP (x, 0);
7113 unsigned HOST_WIDE_INT inner_mask;
7115 /* Select the mask of the bits we need for the shift operand. */
7116 inner_mask = mask << INTVAL (XEXP (x, 1));
7118 /* We can only change the mode of the shift if we can do arithmetic
7119 in the mode of the shift and INNER_MASK is no wider than the
7120 width of OP_MODE. */
7121 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7122 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7123 op_mode = GET_MODE (x);
7125 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7127 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7128 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7131 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7132 shift and AND produces only copies of the sign bit (C2 is one less
7133 than a power of two), we can do this with just a shift. */
7135 if (GET_CODE (x) == LSHIFTRT
7136 && GET_CODE (XEXP (x, 1)) == CONST_INT
7137 /* The shift puts one of the sign bit copies in the least significant
7139 && ((INTVAL (XEXP (x, 1))
7140 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7141 >= GET_MODE_BITSIZE (GET_MODE (x)))
7142 && exact_log2 (mask + 1) >= 0
7143 /* Number of bits left after the shift must be more than the mask
7145 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7146 <= GET_MODE_BITSIZE (GET_MODE (x)))
7147 /* Must be more sign bit copies than the mask needs. */
7148 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7149 >= exact_log2 (mask + 1)))
7150 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7151 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7152 - exact_log2 (mask + 1)));
7157 /* If we are just looking for the sign bit, we don't need this shift at
7158 all, even if it has a variable count. */
7159 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7160 && (mask == ((unsigned HOST_WIDE_INT) 1
7161 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7162 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7164 /* If this is a shift by a constant, get a mask that contains those bits
7165 that are not copies of the sign bit. We then have two cases: If
7166 MASK only includes those bits, this can be a logical shift, which may
7167 allow simplifications. If MASK is a single-bit field not within
7168 those bits, we are requesting a copy of the sign bit and hence can
7169 shift the sign bit to the appropriate location. */
7171 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7172 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7176 /* If the considered data is wider than HOST_WIDE_INT, we can't
7177 represent a mask for all its bits in a single scalar.
7178 But we only care about the lower bits, so calculate these. */
7180 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7182 nonzero = ~(HOST_WIDE_INT) 0;
7184 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7185 is the number of bits a full-width mask would have set.
7186 We need only shift if these are fewer than nonzero can
7187 hold. If not, we must keep all bits set in nonzero. */
7189 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7190 < HOST_BITS_PER_WIDE_INT)
7191 nonzero >>= INTVAL (XEXP (x, 1))
7192 + HOST_BITS_PER_WIDE_INT
7193 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7197 nonzero = GET_MODE_MASK (GET_MODE (x));
7198 nonzero >>= INTVAL (XEXP (x, 1));
7201 if ((mask & ~nonzero) == 0
7202 || (i = exact_log2 (mask)) >= 0)
7204 x = simplify_shift_const
7205 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7206 i < 0 ? INTVAL (XEXP (x, 1))
7207 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7209 if (GET_CODE (x) != ASHIFTRT)
7210 return force_to_mode (x, mode, mask, reg, next_select);
7214 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7215 even if the shift count isn't a constant. */
7217 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7221 /* If this is a zero- or sign-extension operation that just affects bits
7222 we don't care about, remove it. Be sure the call above returned
7223 something that is still a shift. */
7225 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7226 && GET_CODE (XEXP (x, 1)) == CONST_INT
7227 && INTVAL (XEXP (x, 1)) >= 0
7228 && (INTVAL (XEXP (x, 1))
7229 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7230 && GET_CODE (XEXP (x, 0)) == ASHIFT
7231 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7232 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7239 /* If the shift count is constant and we can do computations
7240 in the mode of X, compute where the bits we care about are.
7241 Otherwise, we can't do anything. Don't change the mode of
7242 the shift or propagate MODE into the shift, though. */
7243 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7244 && INTVAL (XEXP (x, 1)) >= 0)
7246 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7247 GET_MODE (x), GEN_INT (mask),
7249 if (temp && GET_CODE (temp) == CONST_INT)
7251 force_to_mode (XEXP (x, 0), GET_MODE (x),
7252 INTVAL (temp), reg, next_select));
7257 /* If we just want the low-order bit, the NEG isn't needed since it
7258 won't change the low-order bit. */
7260 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7262 /* We need any bits less significant than the most significant bit in
7263 MASK since carries from those bits will affect the bits we are
7269 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7270 same as the XOR case above. Ensure that the constant we form is not
7271 wider than the mode of X. */
7273 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7274 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7275 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7276 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7277 < GET_MODE_BITSIZE (GET_MODE (x)))
7278 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7280 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7282 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7283 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7285 return force_to_mode (x, mode, mask, reg, next_select);
7288 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7289 use the full mask inside the NOT. */
7293 op0 = gen_lowpart_for_combine (op_mode,
7294 force_to_mode (XEXP (x, 0), mode, mask,
7296 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7297 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7301 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7302 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7303 which is equal to STORE_FLAG_VALUE. */
7304 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7305 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7306 && (nonzero_bits (XEXP (x, 0), mode)
7307 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7308 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7313 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7314 written in a narrower mode. We play it safe and do not do so. */
7317 gen_lowpart_for_combine (GET_MODE (x),
7318 force_to_mode (XEXP (x, 1), mode,
7319 mask, reg, next_select)));
7321 gen_lowpart_for_combine (GET_MODE (x),
7322 force_to_mode (XEXP (x, 2), mode,
7323 mask, reg, next_select)));
7330 /* Ensure we return a value of the proper mode. */
7331 return gen_lowpart_for_combine (mode, x);
7334 /* Return nonzero if X is an expression that has one of two values depending on
7335 whether some other value is zero or nonzero. In that case, we return the
7336 value that is being tested, *PTRUE is set to the value if the rtx being
7337 returned has a nonzero value, and *PFALSE is set to the other alternative.
7339 If we return zero, we set *PTRUE and *PFALSE to X. */
7342 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7344 enum machine_mode mode = GET_MODE (x);
7345 enum rtx_code code = GET_CODE (x);
7346 rtx cond0, cond1, true0, true1, false0, false1;
7347 unsigned HOST_WIDE_INT nz;
7349 /* If we are comparing a value against zero, we are done. */
7350 if ((code == NE || code == EQ)
7351 && XEXP (x, 1) == const0_rtx)
7353 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7354 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7358 /* If this is a unary operation whose operand has one of two values, apply
7359 our opcode to compute those values. */
7360 else if (GET_RTX_CLASS (code) == '1'
7361 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7363 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7364 *pfalse = simplify_gen_unary (code, mode, false0,
7365 GET_MODE (XEXP (x, 0)));
7369 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7370 make can't possibly match and would suppress other optimizations. */
7371 else if (code == COMPARE)
7374 /* If this is a binary operation, see if either side has only one of two
7375 values. If either one does or if both do and they are conditional on
7376 the same value, compute the new true and false values. */
7377 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7378 || GET_RTX_CLASS (code) == '<')
7380 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7381 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7383 if ((cond0 != 0 || cond1 != 0)
7384 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7386 /* If if_then_else_cond returned zero, then true/false are the
7387 same rtl. We must copy one of them to prevent invalid rtl
7390 true0 = copy_rtx (true0);
7391 else if (cond1 == 0)
7392 true1 = copy_rtx (true1);
7394 *ptrue = gen_binary (code, mode, true0, true1);
7395 *pfalse = gen_binary (code, mode, false0, false1);
7396 return cond0 ? cond0 : cond1;
7399 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7400 operands is zero when the other is nonzero, and vice-versa,
7401 and STORE_FLAG_VALUE is 1 or -1. */
7403 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7404 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7406 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7408 rtx op0 = XEXP (XEXP (x, 0), 1);
7409 rtx op1 = XEXP (XEXP (x, 1), 1);
7411 cond0 = XEXP (XEXP (x, 0), 0);
7412 cond1 = XEXP (XEXP (x, 1), 0);
7414 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7415 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7416 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7417 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7418 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7419 || ((swap_condition (GET_CODE (cond0))
7420 == combine_reversed_comparison_code (cond1))
7421 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7422 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7423 && ! side_effects_p (x))
7425 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7426 *pfalse = gen_binary (MULT, mode,
7428 ? simplify_gen_unary (NEG, mode, op1,
7436 /* Similarly for MULT, AND and UMIN, except that for these the result
7438 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7439 && (code == MULT || code == AND || code == UMIN)
7440 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7442 cond0 = XEXP (XEXP (x, 0), 0);
7443 cond1 = XEXP (XEXP (x, 1), 0);
7445 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7446 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7447 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7448 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7449 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7450 || ((swap_condition (GET_CODE (cond0))
7451 == combine_reversed_comparison_code (cond1))
7452 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7453 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7454 && ! side_effects_p (x))
7456 *ptrue = *pfalse = const0_rtx;
7462 else if (code == IF_THEN_ELSE)
7464 /* If we have IF_THEN_ELSE already, extract the condition and
7465 canonicalize it if it is NE or EQ. */
7466 cond0 = XEXP (x, 0);
7467 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7468 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7469 return XEXP (cond0, 0);
7470 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7472 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7473 return XEXP (cond0, 0);
7479 /* If X is a SUBREG, we can narrow both the true and false values
7480 if the inner expression, if there is a condition. */
7481 else if (code == SUBREG
7482 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7485 *ptrue = simplify_gen_subreg (mode, true0,
7486 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7487 *pfalse = simplify_gen_subreg (mode, false0,
7488 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7493 /* If X is a constant, this isn't special and will cause confusions
7494 if we treat it as such. Likewise if it is equivalent to a constant. */
7495 else if (CONSTANT_P (x)
7496 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7499 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7500 will be least confusing to the rest of the compiler. */
7501 else if (mode == BImode)
7503 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7507 /* If X is known to be either 0 or -1, those are the true and
7508 false values when testing X. */
7509 else if (x == constm1_rtx || x == const0_rtx
7510 || (mode != VOIDmode
7511 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7513 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7517 /* Likewise for 0 or a single bit. */
7518 else if (mode != VOIDmode
7519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7520 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7522 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7526 /* Otherwise fail; show no condition with true and false values the same. */
7527 *ptrue = *pfalse = x;
7531 /* Return the value of expression X given the fact that condition COND
7532 is known to be true when applied to REG as its first operand and VAL
7533 as its second. X is known to not be shared and so can be modified in
7536 We only handle the simplest cases, and specifically those cases that
7537 arise with IF_THEN_ELSE expressions. */
7540 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7542 enum rtx_code code = GET_CODE (x);
7547 if (side_effects_p (x))
7550 /* If either operand of the condition is a floating point value,
7551 then we have to avoid collapsing an EQ comparison. */
7553 && rtx_equal_p (x, reg)
7554 && ! FLOAT_MODE_P (GET_MODE (x))
7555 && ! FLOAT_MODE_P (GET_MODE (val)))
7558 if (cond == UNEQ && rtx_equal_p (x, reg))
7561 /* If X is (abs REG) and we know something about REG's relationship
7562 with zero, we may be able to simplify this. */
7564 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7567 case GE: case GT: case EQ:
7570 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7572 GET_MODE (XEXP (x, 0)));
7577 /* The only other cases we handle are MIN, MAX, and comparisons if the
7578 operands are the same as REG and VAL. */
7580 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7582 if (rtx_equal_p (XEXP (x, 0), val))
7583 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7585 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7587 if (GET_RTX_CLASS (code) == '<')
7589 if (comparison_dominates_p (cond, code))
7590 return const_true_rtx;
7592 code = combine_reversed_comparison_code (x);
7594 && comparison_dominates_p (cond, code))
7599 else if (code == SMAX || code == SMIN
7600 || code == UMIN || code == UMAX)
7602 int unsignedp = (code == UMIN || code == UMAX);
7604 /* Do not reverse the condition when it is NE or EQ.
7605 This is because we cannot conclude anything about
7606 the value of 'SMAX (x, y)' when x is not equal to y,
7607 but we can when x equals y. */
7608 if ((code == SMAX || code == UMAX)
7609 && ! (cond == EQ || cond == NE))
7610 cond = reverse_condition (cond);
7615 return unsignedp ? x : XEXP (x, 1);
7617 return unsignedp ? x : XEXP (x, 0);
7619 return unsignedp ? XEXP (x, 1) : x;
7621 return unsignedp ? XEXP (x, 0) : x;
7628 else if (code == SUBREG)
7630 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7631 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7633 if (SUBREG_REG (x) != r)
7635 /* We must simplify subreg here, before we lose track of the
7636 original inner_mode. */
7637 new = simplify_subreg (GET_MODE (x), r,
7638 inner_mode, SUBREG_BYTE (x));
7642 SUBST (SUBREG_REG (x), r);
7647 /* We don't have to handle SIGN_EXTEND here, because even in the
7648 case of replacing something with a modeless CONST_INT, a
7649 CONST_INT is already (supposed to be) a valid sign extension for
7650 its narrower mode, which implies it's already properly
7651 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7652 story is different. */
7653 else if (code == ZERO_EXTEND)
7655 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7656 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7658 if (XEXP (x, 0) != r)
7660 /* We must simplify the zero_extend here, before we lose
7661 track of the original inner_mode. */
7662 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7667 SUBST (XEXP (x, 0), r);
7673 fmt = GET_RTX_FORMAT (code);
7674 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7677 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7678 else if (fmt[i] == 'E')
7679 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7680 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7687 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7688 assignment as a field assignment. */
7691 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7693 if (x == y || rtx_equal_p (x, y))
7696 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7699 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7700 Note that all SUBREGs of MEM are paradoxical; otherwise they
7701 would have been rewritten. */
7702 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7703 && GET_CODE (SUBREG_REG (y)) == MEM
7704 && rtx_equal_p (SUBREG_REG (y),
7705 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7708 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7709 && GET_CODE (SUBREG_REG (x)) == MEM
7710 && rtx_equal_p (SUBREG_REG (x),
7711 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7714 /* We used to see if get_last_value of X and Y were the same but that's
7715 not correct. In one direction, we'll cause the assignment to have
7716 the wrong destination and in the case, we'll import a register into this
7717 insn that might have already have been dead. So fail if none of the
7718 above cases are true. */
7722 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7723 Return that assignment if so.
7725 We only handle the most common cases. */
7728 make_field_assignment (rtx x)
7730 rtx dest = SET_DEST (x);
7731 rtx src = SET_SRC (x);
7736 unsigned HOST_WIDE_INT len;
7738 enum machine_mode mode;
7740 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7741 a clear of a one-bit field. We will have changed it to
7742 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7745 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7746 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7747 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7748 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7750 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7753 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7757 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7758 && subreg_lowpart_p (XEXP (src, 0))
7759 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7760 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7761 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7762 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7763 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7765 assign = make_extraction (VOIDmode, dest, 0,
7766 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7769 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7773 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7775 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7776 && XEXP (XEXP (src, 0), 0) == const1_rtx
7777 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7779 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7782 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7786 /* The other case we handle is assignments into a constant-position
7787 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7788 a mask that has all one bits except for a group of zero bits and
7789 OTHER is known to have zeros where C1 has ones, this is such an
7790 assignment. Compute the position and length from C1. Shift OTHER
7791 to the appropriate position, force it to the required mode, and
7792 make the extraction. Check for the AND in both operands. */
7794 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7797 rhs = expand_compound_operation (XEXP (src, 0));
7798 lhs = expand_compound_operation (XEXP (src, 1));
7800 if (GET_CODE (rhs) == AND
7801 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7802 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7803 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7804 else if (GET_CODE (lhs) == AND
7805 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7806 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7807 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7811 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7812 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7813 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7814 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7817 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7821 /* The mode to use for the source is the mode of the assignment, or of
7822 what is inside a possible STRICT_LOW_PART. */
7823 mode = (GET_CODE (assign) == STRICT_LOW_PART
7824 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7826 /* Shift OTHER right POS places and make it the source, restricting it
7827 to the proper length and mode. */
7829 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7830 GET_MODE (src), other, pos),
7832 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7833 ? ~(unsigned HOST_WIDE_INT) 0
7834 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7837 /* If SRC is masked by an AND that does not make a difference in
7838 the value being stored, strip it. */
7839 if (GET_CODE (assign) == ZERO_EXTRACT
7840 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7841 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7842 && GET_CODE (src) == AND
7843 && GET_CODE (XEXP (src, 1)) == CONST_INT
7844 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7845 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7846 src = XEXP (src, 0);
7848 return gen_rtx_SET (VOIDmode, assign, src);
7851 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7855 apply_distributive_law (rtx x)
7857 enum rtx_code code = GET_CODE (x);
7858 rtx lhs, rhs, other;
7860 enum rtx_code inner_code;
7862 /* Distributivity is not true for floating point.
7863 It can change the value. So don't do it.
7864 -- rms and moshier@world.std.com. */
7865 if (FLOAT_MODE_P (GET_MODE (x)))
7868 /* The outer operation can only be one of the following: */
7869 if (code != IOR && code != AND && code != XOR
7870 && code != PLUS && code != MINUS)
7873 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7875 /* If either operand is a primitive we can't do anything, so get out
7877 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7878 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7881 lhs = expand_compound_operation (lhs);
7882 rhs = expand_compound_operation (rhs);
7883 inner_code = GET_CODE (lhs);
7884 if (inner_code != GET_CODE (rhs))
7887 /* See if the inner and outer operations distribute. */
7894 /* These all distribute except over PLUS. */
7895 if (code == PLUS || code == MINUS)
7900 if (code != PLUS && code != MINUS)
7905 /* This is also a multiply, so it distributes over everything. */
7909 /* Non-paradoxical SUBREGs distributes over all operations, provided
7910 the inner modes and byte offsets are the same, this is an extraction
7911 of a low-order part, we don't convert an fp operation to int or
7912 vice versa, and we would not be converting a single-word
7913 operation into a multi-word operation. The latter test is not
7914 required, but it prevents generating unneeded multi-word operations.
7915 Some of the previous tests are redundant given the latter test, but
7916 are retained because they are required for correctness.
7918 We produce the result slightly differently in this case. */
7920 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7921 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7922 || ! subreg_lowpart_p (lhs)
7923 || (GET_MODE_CLASS (GET_MODE (lhs))
7924 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7925 || (GET_MODE_SIZE (GET_MODE (lhs))
7926 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7927 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7930 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7931 SUBREG_REG (lhs), SUBREG_REG (rhs));
7932 return gen_lowpart_for_combine (GET_MODE (x), tem);
7938 /* Set LHS and RHS to the inner operands (A and B in the example
7939 above) and set OTHER to the common operand (C in the example).
7940 These is only one way to do this unless the inner operation is
7942 if (GET_RTX_CLASS (inner_code) == 'c'
7943 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7944 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7945 else if (GET_RTX_CLASS (inner_code) == 'c'
7946 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7947 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7948 else if (GET_RTX_CLASS (inner_code) == 'c'
7949 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7950 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7951 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7952 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7956 /* Form the new inner operation, seeing if it simplifies first. */
7957 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7959 /* There is one exception to the general way of distributing:
7960 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7961 if (code == XOR && inner_code == IOR)
7964 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7967 /* We may be able to continuing distributing the result, so call
7968 ourselves recursively on the inner operation before forming the
7969 outer operation, which we return. */
7970 return gen_binary (inner_code, GET_MODE (x),
7971 apply_distributive_law (tem), other);
7974 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7977 Return an equivalent form, if different from X. Otherwise, return X. If
7978 X is zero, we are to always construct the equivalent form. */
7981 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7982 unsigned HOST_WIDE_INT constop)
7984 unsigned HOST_WIDE_INT nonzero;
7987 /* Simplify VAROP knowing that we will be only looking at some of the
7990 Note by passing in CONSTOP, we guarantee that the bits not set in
7991 CONSTOP are not significant and will never be examined. We must
7992 ensure that is the case by explicitly masking out those bits
7993 before returning. */
7994 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7996 /* If VAROP is a CLOBBER, we will fail so return it. */
7997 if (GET_CODE (varop) == CLOBBER)
8000 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8001 to VAROP and return the new constant. */
8002 if (GET_CODE (varop) == CONST_INT)
8003 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8005 /* See what bits may be nonzero in VAROP. Unlike the general case of
8006 a call to nonzero_bits, here we don't care about bits outside
8009 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8011 /* Turn off all bits in the constant that are known to already be zero.
8012 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8013 which is tested below. */
8017 /* If we don't have any bits left, return zero. */
8021 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8022 a power of two, we can replace this with an ASHIFT. */
8023 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8024 && (i = exact_log2 (constop)) >= 0)
8025 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8027 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8028 or XOR, then try to apply the distributive law. This may eliminate
8029 operations if either branch can be simplified because of the AND.
8030 It may also make some cases more complex, but those cases probably
8031 won't match a pattern either with or without this. */
8033 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8035 gen_lowpart_for_combine
8037 apply_distributive_law
8038 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8039 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8040 XEXP (varop, 0), constop),
8041 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8042 XEXP (varop, 1), constop))));
8044 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8045 the AND and see if one of the operands simplifies to zero. If so, we
8046 may eliminate it. */
8048 if (GET_CODE (varop) == PLUS
8049 && exact_log2 (constop + 1) >= 0)
8053 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8054 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8055 if (o0 == const0_rtx)
8057 if (o1 == const0_rtx)
8061 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8062 if we already had one (just check for the simplest cases). */
8063 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8064 && GET_MODE (XEXP (x, 0)) == mode
8065 && SUBREG_REG (XEXP (x, 0)) == varop)
8066 varop = XEXP (x, 0);
8068 varop = gen_lowpart_for_combine (mode, varop);
8070 /* If we can't make the SUBREG, try to return what we were given. */
8071 if (GET_CODE (varop) == CLOBBER)
8072 return x ? x : varop;
8074 /* If we are only masking insignificant bits, return VAROP. */
8075 if (constop == nonzero)
8079 /* Otherwise, return an AND. */
8080 constop = trunc_int_for_mode (constop, mode);
8081 /* See how much, if any, of X we can use. */
8082 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8083 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8087 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8088 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8089 SUBST (XEXP (x, 1), GEN_INT (constop));
8091 SUBST (XEXP (x, 0), varop);
8098 #define nonzero_bits_with_known(X, MODE) \
8099 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8101 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8102 It avoids exponential behavior in nonzero_bits1 when X has
8103 identical subexpressions on the first or the second level. */
8105 static unsigned HOST_WIDE_INT
8106 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8107 enum machine_mode known_mode,
8108 unsigned HOST_WIDE_INT known_ret)
8110 if (x == known_x && mode == known_mode)
8113 /* Try to find identical subexpressions. If found call
8114 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8115 precomputed value for the subexpression as KNOWN_RET. */
8117 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8118 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8120 rtx x0 = XEXP (x, 0);
8121 rtx x1 = XEXP (x, 1);
8123 /* Check the first level. */
8125 return nonzero_bits1 (x, mode, x0, mode,
8126 nonzero_bits_with_known (x0, mode));
8128 /* Check the second level. */
8129 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8130 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8131 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8132 return nonzero_bits1 (x, mode, x1, mode,
8133 nonzero_bits_with_known (x1, mode));
8135 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8136 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8137 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8138 return nonzero_bits1 (x, mode, x0, mode,
8139 nonzero_bits_with_known (x0, mode));
8142 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8145 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8146 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8147 is less useful. We can't allow both, because that results in exponential
8148 run time recursion. There is a nullstone testcase that triggered
8149 this. This macro avoids accidental uses of num_sign_bit_copies. */
8150 #define cached_num_sign_bit_copies()
8152 /* Given an expression, X, compute which bits in X can be nonzero.
8153 We don't care about bits outside of those defined in MODE.
8155 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8156 a shift, AND, or zero_extract, we can do better. */
8158 static unsigned HOST_WIDE_INT
8159 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8160 enum machine_mode known_mode,
8161 unsigned HOST_WIDE_INT known_ret)
8163 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8164 unsigned HOST_WIDE_INT inner_nz;
8166 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8169 /* For floating-point values, assume all bits are needed. */
8170 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8173 /* If X is wider than MODE, use its mode instead. */
8174 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8176 mode = GET_MODE (x);
8177 nonzero = GET_MODE_MASK (mode);
8178 mode_width = GET_MODE_BITSIZE (mode);
8181 if (mode_width > HOST_BITS_PER_WIDE_INT)
8182 /* Our only callers in this case look for single bit values. So
8183 just return the mode mask. Those tests will then be false. */
8186 #ifndef WORD_REGISTER_OPERATIONS
8187 /* If MODE is wider than X, but both are a single word for both the host
8188 and target machines, we can compute this from which bits of the
8189 object might be nonzero in its own mode, taking into account the fact
8190 that on many CISC machines, accessing an object in a wider mode
8191 causes the high-order bits to become undefined. So they are
8192 not known to be zero. */
8194 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8195 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8196 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8197 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8199 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8200 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8205 code = GET_CODE (x);
8209 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8210 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8211 all the bits above ptr_mode are known to be zero. */
8212 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8214 nonzero &= GET_MODE_MASK (ptr_mode);
8217 /* Include declared information about alignment of pointers. */
8218 /* ??? We don't properly preserve REG_POINTER changes across
8219 pointer-to-integer casts, so we can't trust it except for
8220 things that we know must be pointers. See execute/960116-1.c. */
8221 if ((x == stack_pointer_rtx
8222 || x == frame_pointer_rtx
8223 || x == arg_pointer_rtx)
8224 && REGNO_POINTER_ALIGN (REGNO (x)))
8226 unsigned HOST_WIDE_INT alignment
8227 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8229 #ifdef PUSH_ROUNDING
8230 /* If PUSH_ROUNDING is defined, it is possible for the
8231 stack to be momentarily aligned only to that amount,
8232 so we pick the least alignment. */
8233 if (x == stack_pointer_rtx && PUSH_ARGS)
8234 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8238 nonzero &= ~(alignment - 1);
8241 /* If X is a register whose nonzero bits value is current, use it.
8242 Otherwise, if X is a register whose value we can find, use that
8243 value. Otherwise, use the previously-computed global nonzero bits
8244 for this register. */
8246 if (reg_last_set_value[REGNO (x)] != 0
8247 && (reg_last_set_mode[REGNO (x)] == mode
8248 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8249 && GET_MODE_CLASS (mode) == MODE_INT))
8250 && (reg_last_set_label[REGNO (x)] == label_tick
8251 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8252 && REG_N_SETS (REGNO (x)) == 1
8253 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8255 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8256 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8258 tem = get_last_value (x);
8262 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8263 /* If X is narrower than MODE and TEM is a non-negative
8264 constant that would appear negative in the mode of X,
8265 sign-extend it for use in reg_nonzero_bits because some
8266 machines (maybe most) will actually do the sign-extension
8267 and this is the conservative approach.
8269 ??? For 2.5, try to tighten up the MD files in this regard
8270 instead of this kludge. */
8272 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8273 && GET_CODE (tem) == CONST_INT
8275 && 0 != (INTVAL (tem)
8276 & ((HOST_WIDE_INT) 1
8277 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8278 tem = GEN_INT (INTVAL (tem)
8279 | ((HOST_WIDE_INT) (-1)
8280 << GET_MODE_BITSIZE (GET_MODE (x))));
8282 return nonzero_bits_with_known (tem, mode) & nonzero;
8284 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8286 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8288 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8289 /* We don't know anything about the upper bits. */
8290 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8291 return nonzero & mask;
8297 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8298 /* If X is negative in MODE, sign-extend the value. */
8299 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8300 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8301 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8307 #ifdef LOAD_EXTEND_OP
8308 /* In many, if not most, RISC machines, reading a byte from memory
8309 zeros the rest of the register. Noticing that fact saves a lot
8310 of extra zero-extends. */
8311 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8312 nonzero &= GET_MODE_MASK (GET_MODE (x));
8317 case UNEQ: case LTGT:
8318 case GT: case GTU: case UNGT:
8319 case LT: case LTU: case UNLT:
8320 case GE: case GEU: case UNGE:
8321 case LE: case LEU: case UNLE:
8322 case UNORDERED: case ORDERED:
8324 /* If this produces an integer result, we know which bits are set.
8325 Code here used to clear bits outside the mode of X, but that is
8328 if (GET_MODE_CLASS (mode) == MODE_INT
8329 && mode_width <= HOST_BITS_PER_WIDE_INT)
8330 nonzero = STORE_FLAG_VALUE;
8335 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8336 and num_sign_bit_copies. */
8337 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8338 == GET_MODE_BITSIZE (GET_MODE (x)))
8342 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8343 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8348 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8349 and num_sign_bit_copies. */
8350 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8351 == GET_MODE_BITSIZE (GET_MODE (x)))
8357 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8358 & GET_MODE_MASK (mode));
8362 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8363 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8364 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8368 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8369 Otherwise, show all the bits in the outer mode but not the inner
8371 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8372 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8374 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8376 & (((HOST_WIDE_INT) 1
8377 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8378 inner_nz |= (GET_MODE_MASK (mode)
8379 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8382 nonzero &= inner_nz;
8386 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8387 & nonzero_bits_with_known (XEXP (x, 1), mode));
8391 case UMIN: case UMAX: case SMIN: case SMAX:
8393 unsigned HOST_WIDE_INT nonzero0 =
8394 nonzero_bits_with_known (XEXP (x, 0), mode);
8396 /* Don't call nonzero_bits for the second time if it cannot change
8398 if ((nonzero & nonzero0) != nonzero)
8399 nonzero &= (nonzero0
8400 | nonzero_bits_with_known (XEXP (x, 1), mode));
8404 case PLUS: case MINUS:
8406 case DIV: case UDIV:
8407 case MOD: case UMOD:
8408 /* We can apply the rules of arithmetic to compute the number of
8409 high- and low-order zero bits of these operations. We start by
8410 computing the width (position of the highest-order nonzero bit)
8411 and the number of low-order zero bits for each value. */
8413 unsigned HOST_WIDE_INT nz0 =
8414 nonzero_bits_with_known (XEXP (x, 0), mode);
8415 unsigned HOST_WIDE_INT nz1 =
8416 nonzero_bits_with_known (XEXP (x, 1), mode);
8417 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8418 int width0 = floor_log2 (nz0) + 1;
8419 int width1 = floor_log2 (nz1) + 1;
8420 int low0 = floor_log2 (nz0 & -nz0);
8421 int low1 = floor_log2 (nz1 & -nz1);
8422 HOST_WIDE_INT op0_maybe_minusp
8423 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8424 HOST_WIDE_INT op1_maybe_minusp
8425 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8426 unsigned int result_width = mode_width;
8432 result_width = MAX (width0, width1) + 1;
8433 result_low = MIN (low0, low1);
8436 result_low = MIN (low0, low1);
8439 result_width = width0 + width1;
8440 result_low = low0 + low1;
8445 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8446 result_width = width0;
8451 result_width = width0;
8456 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8457 result_width = MIN (width0, width1);
8458 result_low = MIN (low0, low1);
8463 result_width = MIN (width0, width1);
8464 result_low = MIN (low0, low1);
8470 if (result_width < mode_width)
8471 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8474 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8476 #ifdef POINTERS_EXTEND_UNSIGNED
8477 /* If pointers extend unsigned and this is an addition or subtraction
8478 to a pointer in Pmode, all the bits above ptr_mode are known to be
8480 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8481 && (code == PLUS || code == MINUS)
8482 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8483 nonzero &= GET_MODE_MASK (ptr_mode);
8489 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8490 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8491 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8495 /* If this is a SUBREG formed for a promoted variable that has
8496 been zero-extended, we know that at least the high-order bits
8497 are zero, though others might be too. */
8499 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8500 nonzero = (GET_MODE_MASK (GET_MODE (x))
8501 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8503 /* If the inner mode is a single word for both the host and target
8504 machines, we can compute this from which bits of the inner
8505 object might be nonzero. */
8506 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8507 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8508 <= HOST_BITS_PER_WIDE_INT))
8510 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8512 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8513 /* If this is a typical RISC machine, we only have to worry
8514 about the way loads are extended. */
8515 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8517 & (((unsigned HOST_WIDE_INT) 1
8518 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8520 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8521 || GET_CODE (SUBREG_REG (x)) != MEM)
8524 /* On many CISC machines, accessing an object in a wider mode
8525 causes the high-order bits to become undefined. So they are
8526 not known to be zero. */
8527 if (GET_MODE_SIZE (GET_MODE (x))
8528 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8529 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8530 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8539 /* The nonzero bits are in two classes: any bits within MODE
8540 that aren't in GET_MODE (x) are always significant. The rest of the
8541 nonzero bits are those that are significant in the operand of
8542 the shift when shifted the appropriate number of bits. This
8543 shows that high-order bits are cleared by the right shift and
8544 low-order bits by left shifts. */
8545 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8546 && INTVAL (XEXP (x, 1)) >= 0
8547 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8549 enum machine_mode inner_mode = GET_MODE (x);
8550 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8551 int count = INTVAL (XEXP (x, 1));
8552 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8553 unsigned HOST_WIDE_INT op_nonzero =
8554 nonzero_bits_with_known (XEXP (x, 0), mode);
8555 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8556 unsigned HOST_WIDE_INT outer = 0;
8558 if (mode_width > width)
8559 outer = (op_nonzero & nonzero & ~mode_mask);
8561 if (code == LSHIFTRT)
8563 else if (code == ASHIFTRT)
8567 /* If the sign bit may have been nonzero before the shift, we
8568 need to mark all the places it could have been copied to
8569 by the shift as possibly nonzero. */
8570 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8571 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8573 else if (code == ASHIFT)
8576 inner = ((inner << (count % width)
8577 | (inner >> (width - (count % width)))) & mode_mask);
8579 nonzero &= (outer | inner);
8585 /* This is at most the number of bits in the mode. */
8586 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8590 /* If CLZ has a known value at zero, then the nonzero bits are
8591 that value, plus the number of bits in the mode minus one. */
8592 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8593 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8599 /* If CTZ has a known value at zero, then the nonzero bits are
8600 that value, plus the number of bits in the mode minus one. */
8601 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8602 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8612 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8613 | nonzero_bits_with_known (XEXP (x, 2), mode));
8623 /* See the macro definition above. */
8624 #undef cached_num_sign_bit_copies
8626 #define num_sign_bit_copies_with_known(X, M) \
8627 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8629 /* The function cached_num_sign_bit_copies is a wrapper around
8630 num_sign_bit_copies1. It avoids exponential behavior in
8631 num_sign_bit_copies1 when X has identical subexpressions on the
8632 first or the second level. */
8635 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8636 enum machine_mode known_mode,
8637 unsigned int known_ret)
8639 if (x == known_x && mode == known_mode)
8642 /* Try to find identical subexpressions. If found call
8643 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8644 the precomputed value for the subexpression as KNOWN_RET. */
8646 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8647 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8649 rtx x0 = XEXP (x, 0);
8650 rtx x1 = XEXP (x, 1);
8652 /* Check the first level. */
8655 num_sign_bit_copies1 (x, mode, x0, mode,
8656 num_sign_bit_copies_with_known (x0, mode));
8658 /* Check the second level. */
8659 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8660 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8661 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8663 num_sign_bit_copies1 (x, mode, x1, mode,
8664 num_sign_bit_copies_with_known (x1, mode));
8666 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8667 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8668 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8670 num_sign_bit_copies1 (x, mode, x0, mode,
8671 num_sign_bit_copies_with_known (x0, mode));
8674 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8677 /* Return the number of bits at the high-order end of X that are known to
8678 be equal to the sign bit. X will be used in mode MODE; if MODE is
8679 VOIDmode, X will be used in its own mode. The returned value will always
8680 be between 1 and the number of bits in MODE. */
8683 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8684 enum machine_mode known_mode,
8685 unsigned int known_ret)
8687 enum rtx_code code = GET_CODE (x);
8688 unsigned int bitwidth;
8689 int num0, num1, result;
8690 unsigned HOST_WIDE_INT nonzero;
8693 /* If we weren't given a mode, use the mode of X. If the mode is still
8694 VOIDmode, we don't know anything. Likewise if one of the modes is
8697 if (mode == VOIDmode)
8698 mode = GET_MODE (x);
8700 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8703 bitwidth = GET_MODE_BITSIZE (mode);
8705 /* For a smaller object, just ignore the high bits. */
8706 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8708 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8710 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8713 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8715 #ifndef WORD_REGISTER_OPERATIONS
8716 /* If this machine does not do all register operations on the entire
8717 register and MODE is wider than the mode of X, we can say nothing
8718 at all about the high-order bits. */
8721 /* Likewise on machines that do, if the mode of the object is smaller
8722 than a word and loads of that size don't sign extend, we can say
8723 nothing about the high order bits. */
8724 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8725 #ifdef LOAD_EXTEND_OP
8726 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8737 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8738 /* If pointers extend signed and this is a pointer in Pmode, say that
8739 all the bits above ptr_mode are known to be sign bit copies. */
8740 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8742 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8745 if (reg_last_set_value[REGNO (x)] != 0
8746 && reg_last_set_mode[REGNO (x)] == mode
8747 && (reg_last_set_label[REGNO (x)] == label_tick
8748 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8749 && REG_N_SETS (REGNO (x)) == 1
8750 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8752 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8753 return reg_last_set_sign_bit_copies[REGNO (x)];
8755 tem = get_last_value (x);
8757 return num_sign_bit_copies_with_known (tem, mode);
8759 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8760 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8761 return reg_sign_bit_copies[REGNO (x)];
8765 #ifdef LOAD_EXTEND_OP
8766 /* Some RISC machines sign-extend all loads of smaller than a word. */
8767 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8768 return MAX (1, ((int) bitwidth
8769 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8774 /* If the constant is negative, take its 1's complement and remask.
8775 Then see how many zero bits we have. */
8776 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8777 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8778 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8779 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8781 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8784 /* If this is a SUBREG for a promoted object that is sign-extended
8785 and we are looking at it in a wider mode, we know that at least the
8786 high-order bits are known to be sign bit copies. */
8788 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8790 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8791 return MAX ((int) bitwidth
8792 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8796 /* For a smaller object, just ignore the high bits. */
8797 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8799 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8800 return MAX (1, (num0
8801 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8805 #ifdef WORD_REGISTER_OPERATIONS
8806 #ifdef LOAD_EXTEND_OP
8807 /* For paradoxical SUBREGs on machines where all register operations
8808 affect the entire register, just look inside. Note that we are
8809 passing MODE to the recursive call, so the number of sign bit copies
8810 will remain relative to that mode, not the inner mode. */
8812 /* This works only if loads sign extend. Otherwise, if we get a
8813 reload for the inner part, it may be loaded from the stack, and
8814 then we lose all sign bit copies that existed before the store
8817 if ((GET_MODE_SIZE (GET_MODE (x))
8818 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8819 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8820 && GET_CODE (SUBREG_REG (x)) == MEM)
8821 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8827 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8828 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8832 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8833 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8836 /* For a smaller object, just ignore the high bits. */
8837 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8838 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8842 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8844 case ROTATE: case ROTATERT:
8845 /* If we are rotating left by a number of bits less than the number
8846 of sign bit copies, we can just subtract that amount from the
8848 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8849 && INTVAL (XEXP (x, 1)) >= 0
8850 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8852 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8853 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8854 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8859 /* In general, this subtracts one sign bit copy. But if the value
8860 is known to be positive, the number of sign bit copies is the
8861 same as that of the input. Finally, if the input has just one bit
8862 that might be nonzero, all the bits are copies of the sign bit. */
8863 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8864 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8865 return num0 > 1 ? num0 - 1 : 1;
8867 nonzero = nonzero_bits (XEXP (x, 0), mode);
8872 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8877 case IOR: case AND: case XOR:
8878 case SMIN: case SMAX: case UMIN: case UMAX:
8879 /* Logical operations will preserve the number of sign-bit copies.
8880 MIN and MAX operations always return one of the operands. */
8881 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8882 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8883 return MIN (num0, num1);
8885 case PLUS: case MINUS:
8886 /* For addition and subtraction, we can have a 1-bit carry. However,
8887 if we are subtracting 1 from a positive number, there will not
8888 be such a carry. Furthermore, if the positive number is known to
8889 be 0 or 1, we know the result is either -1 or 0. */
8891 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8892 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8894 nonzero = nonzero_bits (XEXP (x, 0), mode);
8895 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8896 return (nonzero == 1 || nonzero == 0 ? bitwidth
8897 : bitwidth - floor_log2 (nonzero) - 1);
8900 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8901 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8902 result = MAX (1, MIN (num0, num1) - 1);
8904 #ifdef POINTERS_EXTEND_UNSIGNED
8905 /* If pointers extend signed and this is an addition or subtraction
8906 to a pointer in Pmode, all the bits above ptr_mode are known to be
8908 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8909 && (code == PLUS || code == MINUS)
8910 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8911 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8912 - GET_MODE_BITSIZE (ptr_mode) + 1),
8918 /* The number of bits of the product is the sum of the number of
8919 bits of both terms. However, unless one of the terms if known
8920 to be positive, we must allow for an additional bit since negating
8921 a negative number can remove one sign bit copy. */
8923 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8924 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8926 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8928 && (bitwidth > HOST_BITS_PER_WIDE_INT
8929 || (((nonzero_bits (XEXP (x, 0), mode)
8930 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8931 && ((nonzero_bits (XEXP (x, 1), mode)
8932 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8935 return MAX (1, result);
8938 /* The result must be <= the first operand. If the first operand
8939 has the high bit set, we know nothing about the number of sign
8941 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8943 else if ((nonzero_bits (XEXP (x, 0), mode)
8944 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8947 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8950 /* The result must be <= the second operand. */
8951 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8954 /* Similar to unsigned division, except that we have to worry about
8955 the case where the divisor is negative, in which case we have
8957 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8959 && (bitwidth > HOST_BITS_PER_WIDE_INT
8960 || (nonzero_bits (XEXP (x, 1), mode)
8961 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8967 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8969 && (bitwidth > HOST_BITS_PER_WIDE_INT
8970 || (nonzero_bits (XEXP (x, 1), mode)
8971 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8977 /* Shifts by a constant add to the number of bits equal to the
8979 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8980 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8981 && INTVAL (XEXP (x, 1)) > 0)
8982 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8987 /* Left shifts destroy copies. */
8988 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8989 || INTVAL (XEXP (x, 1)) < 0
8990 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8993 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8994 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8997 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8998 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8999 return MIN (num0, num1);
9001 case EQ: case NE: case GE: case GT: case LE: case LT:
9002 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
9003 case GEU: case GTU: case LEU: case LTU:
9004 case UNORDERED: case ORDERED:
9005 /* If the constant is negative, take its 1's complement and remask.
9006 Then see how many zero bits we have. */
9007 nonzero = STORE_FLAG_VALUE;
9008 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9009 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9010 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9012 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9019 /* If we haven't been able to figure it out by one of the above rules,
9020 see if some of the high-order bits are known to be zero. If so,
9021 count those bits and return one less than that amount. If we can't
9022 safely compute the mask for this mode, always return BITWIDTH. */
9024 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9027 nonzero = nonzero_bits (x, mode);
9028 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9029 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9032 /* Return the number of "extended" bits there are in X, when interpreted
9033 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9034 unsigned quantities, this is the number of high-order zero bits.
9035 For signed quantities, this is the number of copies of the sign bit
9036 minus 1. In both case, this function returns the number of "spare"
9037 bits. For example, if two quantities for which this function returns
9038 at least 1 are added, the addition is known not to overflow.
9040 This function will always return 0 unless called during combine, which
9041 implies that it must be called from a define_split. */
9044 extended_count (rtx x, enum machine_mode mode, int unsignedp)
9046 if (nonzero_sign_valid == 0)
9050 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9051 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9052 - floor_log2 (nonzero_bits (x, mode)))
9054 : num_sign_bit_copies (x, mode) - 1);
9057 /* This function is called from `simplify_shift_const' to merge two
9058 outer operations. Specifically, we have already found that we need
9059 to perform operation *POP0 with constant *PCONST0 at the outermost
9060 position. We would now like to also perform OP1 with constant CONST1
9061 (with *POP0 being done last).
9063 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9064 the resulting operation. *PCOMP_P is set to 1 if we would need to
9065 complement the innermost operand, otherwise it is unchanged.
9067 MODE is the mode in which the operation will be done. No bits outside
9068 the width of this mode matter. It is assumed that the width of this mode
9069 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9071 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9072 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9073 result is simply *PCONST0.
9075 If the resulting operation cannot be expressed as one operation, we
9076 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9079 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9081 enum rtx_code op0 = *pop0;
9082 HOST_WIDE_INT const0 = *pconst0;
9084 const0 &= GET_MODE_MASK (mode);
9085 const1 &= GET_MODE_MASK (mode);
9087 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9091 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9094 if (op1 == NIL || op0 == SET)
9097 else if (op0 == NIL)
9098 op0 = op1, const0 = const1;
9100 else if (op0 == op1)
9124 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9125 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9128 /* If the two constants aren't the same, we can't do anything. The
9129 remaining six cases can all be done. */
9130 else if (const0 != const1)
9138 /* (a & b) | b == b */
9140 else /* op1 == XOR */
9141 /* (a ^ b) | b == a | b */
9147 /* (a & b) ^ b == (~a) & b */
9148 op0 = AND, *pcomp_p = 1;
9149 else /* op1 == IOR */
9150 /* (a | b) ^ b == a & ~b */
9151 op0 = AND, const0 = ~const0;
9156 /* (a | b) & b == b */
9158 else /* op1 == XOR */
9159 /* (a ^ b) & b) == (~a) & b */
9166 /* Check for NO-OP cases. */
9167 const0 &= GET_MODE_MASK (mode);
9169 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9171 else if (const0 == 0 && op0 == AND)
9173 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9177 /* ??? Slightly redundant with the above mask, but not entirely.
9178 Moving this above means we'd have to sign-extend the mode mask
9179 for the final test. */
9180 const0 = trunc_int_for_mode (const0, mode);
9188 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9189 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9190 that we started with.
9192 The shift is normally computed in the widest mode we find in VAROP, as
9193 long as it isn't a different number of words than RESULT_MODE. Exceptions
9194 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9197 simplify_shift_const (rtx x, enum rtx_code code,
9198 enum machine_mode result_mode, rtx varop,
9201 enum rtx_code orig_code = code;
9204 enum machine_mode mode = result_mode;
9205 enum machine_mode shift_mode, tmode;
9206 unsigned int mode_words
9207 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9208 /* We form (outer_op (code varop count) (outer_const)). */
9209 enum rtx_code outer_op = NIL;
9210 HOST_WIDE_INT outer_const = 0;
9212 int complement_p = 0;
9215 /* Make sure and truncate the "natural" shift on the way in. We don't
9216 want to do this inside the loop as it makes it more difficult to
9218 #ifdef SHIFT_COUNT_TRUNCATED
9219 if (SHIFT_COUNT_TRUNCATED)
9220 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9223 /* If we were given an invalid count, don't do anything except exactly
9224 what was requested. */
9226 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9231 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9236 /* Unless one of the branches of the `if' in this loop does a `continue',
9237 we will `break' the loop after the `if'. */
9241 /* If we have an operand of (clobber (const_int 0)), just return that
9243 if (GET_CODE (varop) == CLOBBER)
9246 /* If we discovered we had to complement VAROP, leave. Making a NOT
9247 here would cause an infinite loop. */
9251 /* Convert ROTATERT to ROTATE. */
9252 if (code == ROTATERT)
9254 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9256 if (VECTOR_MODE_P (result_mode))
9257 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9259 count = bitsize - count;
9262 /* We need to determine what mode we will do the shift in. If the
9263 shift is a right shift or a ROTATE, we must always do it in the mode
9264 it was originally done in. Otherwise, we can do it in MODE, the
9265 widest mode encountered. */
9267 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9268 ? result_mode : mode);
9270 /* Handle cases where the count is greater than the size of the mode
9271 minus 1. For ASHIFT, use the size minus one as the count (this can
9272 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9273 take the count modulo the size. For other shifts, the result is
9276 Since these shifts are being produced by the compiler by combining
9277 multiple operations, each of which are defined, we know what the
9278 result is supposed to be. */
9280 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9282 if (code == ASHIFTRT)
9283 count = GET_MODE_BITSIZE (shift_mode) - 1;
9284 else if (code == ROTATE || code == ROTATERT)
9285 count %= GET_MODE_BITSIZE (shift_mode);
9288 /* We can't simply return zero because there may be an
9296 /* An arithmetic right shift of a quantity known to be -1 or 0
9298 if (code == ASHIFTRT
9299 && (num_sign_bit_copies (varop, shift_mode)
9300 == GET_MODE_BITSIZE (shift_mode)))
9306 /* If we are doing an arithmetic right shift and discarding all but
9307 the sign bit copies, this is equivalent to doing a shift by the
9308 bitsize minus one. Convert it into that shift because it will often
9309 allow other simplifications. */
9311 if (code == ASHIFTRT
9312 && (count + num_sign_bit_copies (varop, shift_mode)
9313 >= GET_MODE_BITSIZE (shift_mode)))
9314 count = GET_MODE_BITSIZE (shift_mode) - 1;
9316 /* We simplify the tests below and elsewhere by converting
9317 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9318 `make_compound_operation' will convert it to an ASHIFTRT for
9319 those machines (such as VAX) that don't have an LSHIFTRT. */
9320 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9322 && ((nonzero_bits (varop, shift_mode)
9323 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9327 if (code == LSHIFTRT
9328 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9329 && !(nonzero_bits (varop, shift_mode) >> count))
9332 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9333 && !((nonzero_bits (varop, shift_mode) << count)
9334 & GET_MODE_MASK (shift_mode)))
9337 switch (GET_CODE (varop))
9343 new = expand_compound_operation (varop);
9352 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9353 minus the width of a smaller mode, we can do this with a
9354 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9355 if ((code == ASHIFTRT || code == LSHIFTRT)
9356 && ! mode_dependent_address_p (XEXP (varop, 0))
9357 && ! MEM_VOLATILE_P (varop)
9358 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9359 MODE_INT, 1)) != BLKmode)
9361 new = adjust_address_nv (varop, tmode,
9362 BYTES_BIG_ENDIAN ? 0
9363 : count / BITS_PER_UNIT);
9365 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9366 : ZERO_EXTEND, mode, new);
9373 /* Similar to the case above, except that we can only do this if
9374 the resulting mode is the same as that of the underlying
9375 MEM and adjust the address depending on the *bits* endianness
9376 because of the way that bit-field extract insns are defined. */
9377 if ((code == ASHIFTRT || code == LSHIFTRT)
9378 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9379 MODE_INT, 1)) != BLKmode
9380 && tmode == GET_MODE (XEXP (varop, 0)))
9382 if (BITS_BIG_ENDIAN)
9383 new = XEXP (varop, 0);
9386 new = copy_rtx (XEXP (varop, 0));
9387 SUBST (XEXP (new, 0),
9388 plus_constant (XEXP (new, 0),
9389 count / BITS_PER_UNIT));
9392 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9393 : ZERO_EXTEND, mode, new);
9400 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9401 the same number of words as what we've seen so far. Then store
9402 the widest mode in MODE. */
9403 if (subreg_lowpart_p (varop)
9404 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9405 > GET_MODE_SIZE (GET_MODE (varop)))
9406 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9407 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9410 varop = SUBREG_REG (varop);
9411 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9412 mode = GET_MODE (varop);
9418 /* Some machines use MULT instead of ASHIFT because MULT
9419 is cheaper. But it is still better on those machines to
9420 merge two shifts into one. */
9421 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9422 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9425 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9426 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9432 /* Similar, for when divides are cheaper. */
9433 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9434 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9437 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9438 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9444 /* If we are extracting just the sign bit of an arithmetic
9445 right shift, that shift is not needed. However, the sign
9446 bit of a wider mode may be different from what would be
9447 interpreted as the sign bit in a narrower mode, so, if
9448 the result is narrower, don't discard the shift. */
9449 if (code == LSHIFTRT
9450 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9451 && (GET_MODE_BITSIZE (result_mode)
9452 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9454 varop = XEXP (varop, 0);
9458 /* ... fall through ... */
9463 /* Here we have two nested shifts. The result is usually the
9464 AND of a new shift with a mask. We compute the result below. */
9465 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9466 && INTVAL (XEXP (varop, 1)) >= 0
9467 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9468 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9469 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9471 enum rtx_code first_code = GET_CODE (varop);
9472 unsigned int first_count = INTVAL (XEXP (varop, 1));
9473 unsigned HOST_WIDE_INT mask;
9476 /* We have one common special case. We can't do any merging if
9477 the inner code is an ASHIFTRT of a smaller mode. However, if
9478 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9479 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9480 we can convert it to
9481 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9482 This simplifies certain SIGN_EXTEND operations. */
9483 if (code == ASHIFT && first_code == ASHIFTRT
9484 && count == (unsigned int)
9485 (GET_MODE_BITSIZE (result_mode)
9486 - GET_MODE_BITSIZE (GET_MODE (varop))))
9488 /* C3 has the low-order C1 bits zero. */
9490 mask = (GET_MODE_MASK (mode)
9491 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9493 varop = simplify_and_const_int (NULL_RTX, result_mode,
9494 XEXP (varop, 0), mask);
9495 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9497 count = first_count;
9502 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9503 than C1 high-order bits equal to the sign bit, we can convert
9504 this to either an ASHIFT or an ASHIFTRT depending on the
9507 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9509 if (code == ASHIFTRT && first_code == ASHIFT
9510 && GET_MODE (varop) == shift_mode
9511 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9514 varop = XEXP (varop, 0);
9516 signed_count = count - first_count;
9517 if (signed_count < 0)
9518 count = -signed_count, code = ASHIFT;
9520 count = signed_count;
9525 /* There are some cases we can't do. If CODE is ASHIFTRT,
9526 we can only do this if FIRST_CODE is also ASHIFTRT.
9528 We can't do the case when CODE is ROTATE and FIRST_CODE is
9531 If the mode of this shift is not the mode of the outer shift,
9532 we can't do this if either shift is a right shift or ROTATE.
9534 Finally, we can't do any of these if the mode is too wide
9535 unless the codes are the same.
9537 Handle the case where the shift codes are the same
9540 if (code == first_code)
9542 if (GET_MODE (varop) != result_mode
9543 && (code == ASHIFTRT || code == LSHIFTRT
9547 count += first_count;
9548 varop = XEXP (varop, 0);
9552 if (code == ASHIFTRT
9553 || (code == ROTATE && first_code == ASHIFTRT)
9554 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9555 || (GET_MODE (varop) != result_mode
9556 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9557 || first_code == ROTATE
9558 || code == ROTATE)))
9561 /* To compute the mask to apply after the shift, shift the
9562 nonzero bits of the inner shift the same way the
9563 outer shift will. */
9565 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9568 = simplify_binary_operation (code, result_mode, mask_rtx,
9571 /* Give up if we can't compute an outer operation to use. */
9573 || GET_CODE (mask_rtx) != CONST_INT
9574 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9576 result_mode, &complement_p))
9579 /* If the shifts are in the same direction, we add the
9580 counts. Otherwise, we subtract them. */
9581 signed_count = count;
9582 if ((code == ASHIFTRT || code == LSHIFTRT)
9583 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9584 signed_count += first_count;
9586 signed_count -= first_count;
9588 /* If COUNT is positive, the new shift is usually CODE,
9589 except for the two exceptions below, in which case it is
9590 FIRST_CODE. If the count is negative, FIRST_CODE should
9592 if (signed_count > 0
9593 && ((first_code == ROTATE && code == ASHIFT)
9594 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9595 code = first_code, count = signed_count;
9596 else if (signed_count < 0)
9597 code = first_code, count = -signed_count;
9599 count = signed_count;
9601 varop = XEXP (varop, 0);
9605 /* If we have (A << B << C) for any shift, we can convert this to
9606 (A << C << B). This wins if A is a constant. Only try this if
9607 B is not a constant. */
9609 else if (GET_CODE (varop) == code
9610 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9612 = simplify_binary_operation (code, mode,
9616 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9623 /* Make this fit the case below. */
9624 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9625 GEN_INT (GET_MODE_MASK (mode)));
9631 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9632 with C the size of VAROP - 1 and the shift is logical if
9633 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9634 we have an (le X 0) operation. If we have an arithmetic shift
9635 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9636 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9638 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9639 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9640 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9641 && (code == LSHIFTRT || code == ASHIFTRT)
9642 && count == (unsigned int)
9643 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9644 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9647 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9650 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9651 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9656 /* If we have (shift (logical)), move the logical to the outside
9657 to allow it to possibly combine with another logical and the
9658 shift to combine with another shift. This also canonicalizes to
9659 what a ZERO_EXTRACT looks like. Also, some machines have
9660 (and (shift)) insns. */
9662 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9663 && (new = simplify_binary_operation (code, result_mode,
9665 GEN_INT (count))) != 0
9666 && GET_CODE (new) == CONST_INT
9667 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9668 INTVAL (new), result_mode, &complement_p))
9670 varop = XEXP (varop, 0);
9674 /* If we can't do that, try to simplify the shift in each arm of the
9675 logical expression, make a new logical expression, and apply
9676 the inverse distributive law. */
9678 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9679 XEXP (varop, 0), count);
9680 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9681 XEXP (varop, 1), count);
9683 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9684 varop = apply_distributive_law (varop);
9691 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9692 says that the sign bit can be tested, FOO has mode MODE, C is
9693 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9694 that may be nonzero. */
9695 if (code == LSHIFTRT
9696 && XEXP (varop, 1) == const0_rtx
9697 && GET_MODE (XEXP (varop, 0)) == result_mode
9698 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9699 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9700 && ((STORE_FLAG_VALUE
9701 & ((HOST_WIDE_INT) 1
9702 < (GET_MODE_BITSIZE (result_mode) - 1))))
9703 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9704 && merge_outer_ops (&outer_op, &outer_const, XOR,
9705 (HOST_WIDE_INT) 1, result_mode,
9708 varop = XEXP (varop, 0);
9715 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9716 than the number of bits in the mode is equivalent to A. */
9717 if (code == LSHIFTRT
9718 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9719 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9721 varop = XEXP (varop, 0);
9726 /* NEG commutes with ASHIFT since it is multiplication. Move the
9727 NEG outside to allow shifts to combine. */
9729 && merge_outer_ops (&outer_op, &outer_const, NEG,
9730 (HOST_WIDE_INT) 0, result_mode,
9733 varop = XEXP (varop, 0);
9739 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9740 is one less than the number of bits in the mode is
9741 equivalent to (xor A 1). */
9742 if (code == LSHIFTRT
9743 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9744 && XEXP (varop, 1) == constm1_rtx
9745 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9746 && merge_outer_ops (&outer_op, &outer_const, XOR,
9747 (HOST_WIDE_INT) 1, result_mode,
9751 varop = XEXP (varop, 0);
9755 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9756 that might be nonzero in BAR are those being shifted out and those
9757 bits are known zero in FOO, we can replace the PLUS with FOO.
9758 Similarly in the other operand order. This code occurs when
9759 we are computing the size of a variable-size array. */
9761 if ((code == ASHIFTRT || code == LSHIFTRT)
9762 && count < HOST_BITS_PER_WIDE_INT
9763 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9764 && (nonzero_bits (XEXP (varop, 1), result_mode)
9765 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9767 varop = XEXP (varop, 0);
9770 else if ((code == ASHIFTRT || code == LSHIFTRT)
9771 && count < HOST_BITS_PER_WIDE_INT
9772 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9773 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9775 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9776 & nonzero_bits (XEXP (varop, 1),
9779 varop = XEXP (varop, 1);
9783 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9785 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9786 && (new = simplify_binary_operation (ASHIFT, result_mode,
9788 GEN_INT (count))) != 0
9789 && GET_CODE (new) == CONST_INT
9790 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9791 INTVAL (new), result_mode, &complement_p))
9793 varop = XEXP (varop, 0);
9799 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9800 with C the size of VAROP - 1 and the shift is logical if
9801 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9802 we have a (gt X 0) operation. If the shift is arithmetic with
9803 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9804 we have a (neg (gt X 0)) operation. */
9806 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9807 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9808 && count == (unsigned int)
9809 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9810 && (code == LSHIFTRT || code == ASHIFTRT)
9811 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9812 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9814 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9817 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9820 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9821 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9828 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9829 if the truncate does not affect the value. */
9830 if (code == LSHIFTRT
9831 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9832 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9833 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9834 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9835 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9837 rtx varop_inner = XEXP (varop, 0);
9840 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9841 XEXP (varop_inner, 0),
9843 (count + INTVAL (XEXP (varop_inner, 1))));
9844 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9857 /* We need to determine what mode to do the shift in. If the shift is
9858 a right shift or ROTATE, we must always do it in the mode it was
9859 originally done in. Otherwise, we can do it in MODE, the widest mode
9860 encountered. The code we care about is that of the shift that will
9861 actually be done, not the shift that was originally requested. */
9863 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9864 ? result_mode : mode);
9866 /* We have now finished analyzing the shift. The result should be
9867 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9868 OUTER_OP is non-NIL, it is an operation that needs to be applied
9869 to the result of the shift. OUTER_CONST is the relevant constant,
9870 but we must turn off all bits turned off in the shift.
9872 If we were passed a value for X, see if we can use any pieces of
9873 it. If not, make new rtx. */
9875 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9876 && GET_CODE (XEXP (x, 1)) == CONST_INT
9877 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9878 const_rtx = XEXP (x, 1);
9880 const_rtx = GEN_INT (count);
9882 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9883 && GET_MODE (XEXP (x, 0)) == shift_mode
9884 && SUBREG_REG (XEXP (x, 0)) == varop)
9885 varop = XEXP (x, 0);
9886 else if (GET_MODE (varop) != shift_mode)
9887 varop = gen_lowpart_for_combine (shift_mode, varop);
9889 /* If we can't make the SUBREG, try to return what we were given. */
9890 if (GET_CODE (varop) == CLOBBER)
9891 return x ? x : varop;
9893 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9897 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9899 /* If we have an outer operation and we just made a shift, it is
9900 possible that we could have simplified the shift were it not
9901 for the outer operation. So try to do the simplification
9904 if (outer_op != NIL && GET_CODE (x) == code
9905 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9906 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9907 INTVAL (XEXP (x, 1)));
9909 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9910 turn off all the bits that the shift would have turned off. */
9911 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9912 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9913 GET_MODE_MASK (result_mode) >> orig_count);
9915 /* Do the remainder of the processing in RESULT_MODE. */
9916 x = gen_lowpart_for_combine (result_mode, x);
9918 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9921 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9923 if (outer_op != NIL)
9925 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9926 outer_const = trunc_int_for_mode (outer_const, result_mode);
9928 if (outer_op == AND)
9929 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9930 else if (outer_op == SET)
9931 /* This means that we have determined that the result is
9932 equivalent to a constant. This should be rare. */
9933 x = GEN_INT (outer_const);
9934 else if (GET_RTX_CLASS (outer_op) == '1')
9935 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9937 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9943 /* Like recog, but we receive the address of a pointer to a new pattern.
9944 We try to match the rtx that the pointer points to.
9945 If that fails, we may try to modify or replace the pattern,
9946 storing the replacement into the same pointer object.
9948 Modifications include deletion or addition of CLOBBERs.
9950 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9951 the CLOBBERs are placed.
9953 The value is the final insn code from the pattern ultimately matched,
9957 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9960 int insn_code_number;
9961 int num_clobbers_to_add = 0;
9966 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9967 we use to indicate that something didn't match. If we find such a
9968 thing, force rejection. */
9969 if (GET_CODE (pat) == PARALLEL)
9970 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9971 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9972 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9975 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9976 instruction for pattern recognition. */
9977 dummy_insn = shallow_copy_rtx (insn);
9978 PATTERN (dummy_insn) = pat;
9979 REG_NOTES (dummy_insn) = 0;
9981 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9983 /* If it isn't, there is the possibility that we previously had an insn
9984 that clobbered some register as a side effect, but the combined
9985 insn doesn't need to do that. So try once more without the clobbers
9986 unless this represents an ASM insn. */
9988 if (insn_code_number < 0 && ! check_asm_operands (pat)
9989 && GET_CODE (pat) == PARALLEL)
9993 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9994 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9997 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10001 SUBST_INT (XVECLEN (pat, 0), pos);
10004 pat = XVECEXP (pat, 0, 0);
10006 PATTERN (dummy_insn) = pat;
10007 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10010 /* Recognize all noop sets, these will be killed by followup pass. */
10011 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10012 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10014 /* If we had any clobbers to add, make a new pattern than contains
10015 them. Then check to make sure that all of them are dead. */
10016 if (num_clobbers_to_add)
10018 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10019 rtvec_alloc (GET_CODE (pat) == PARALLEL
10020 ? (XVECLEN (pat, 0)
10021 + num_clobbers_to_add)
10022 : num_clobbers_to_add + 1));
10024 if (GET_CODE (pat) == PARALLEL)
10025 for (i = 0; i < XVECLEN (pat, 0); i++)
10026 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10028 XVECEXP (newpat, 0, 0) = pat;
10030 add_clobbers (newpat, insn_code_number);
10032 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10033 i < XVECLEN (newpat, 0); i++)
10035 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10036 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10038 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10039 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10047 return insn_code_number;
10050 /* Like gen_lowpart but for use by combine. In combine it is not possible
10051 to create any new pseudoregs. However, it is safe to create
10052 invalid memory addresses, because combine will try to recognize
10053 them and all they will do is make the combine attempt fail.
10055 If for some reason this cannot do its job, an rtx
10056 (clobber (const_int 0)) is returned.
10057 An insn containing that will not be recognized. */
10062 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
10066 if (GET_MODE (x) == mode)
10069 /* Return identity if this is a CONST or symbolic
10072 && (GET_CODE (x) == CONST
10073 || GET_CODE (x) == SYMBOL_REF
10074 || GET_CODE (x) == LABEL_REF))
10077 /* We can only support MODE being wider than a word if X is a
10078 constant integer or has a mode the same size. */
10080 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10081 && ! ((GET_MODE (x) == VOIDmode
10082 && (GET_CODE (x) == CONST_INT
10083 || GET_CODE (x) == CONST_DOUBLE))
10084 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10085 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10087 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10088 won't know what to do. So we will strip off the SUBREG here and
10089 process normally. */
10090 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10092 x = SUBREG_REG (x);
10093 if (GET_MODE (x) == mode)
10097 result = gen_lowpart_common (mode, x);
10098 #ifdef CANNOT_CHANGE_MODE_CLASS
10100 && GET_CODE (result) == SUBREG
10101 && GET_CODE (SUBREG_REG (result)) == REG
10102 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10103 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10105 + GET_MODE (result));
10111 if (GET_CODE (x) == MEM)
10115 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10117 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10118 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10120 /* If we want to refer to something bigger than the original memref,
10121 generate a perverse subreg instead. That will force a reload
10122 of the original memref X. */
10123 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10124 return gen_rtx_SUBREG (mode, x, 0);
10126 if (WORDS_BIG_ENDIAN)
10127 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10128 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10130 if (BYTES_BIG_ENDIAN)
10132 /* Adjust the address so that the address-after-the-data is
10134 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10135 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10138 return adjust_address_nv (x, mode, offset);
10141 /* If X is a comparison operator, rewrite it in a new mode. This
10142 probably won't match, but may allow further simplifications. */
10143 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10144 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10146 /* If we couldn't simplify X any other way, just enclose it in a
10147 SUBREG. Normally, this SUBREG won't match, but some patterns may
10148 include an explicit SUBREG or we may simplify it further in combine. */
10153 enum machine_mode sub_mode = GET_MODE (x);
10155 offset = subreg_lowpart_offset (mode, sub_mode);
10156 if (sub_mode == VOIDmode)
10158 sub_mode = int_mode_for_mode (mode);
10159 x = gen_lowpart_common (sub_mode, x);
10161 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10163 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10166 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10170 /* These routines make binary and unary operations by first seeing if they
10171 fold; if not, a new expression is allocated. */
10174 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10179 if (GET_CODE (op0) == CLOBBER)
10181 else if (GET_CODE (op1) == CLOBBER)
10184 if (GET_RTX_CLASS (code) == 'c'
10185 && swap_commutative_operands_p (op0, op1))
10186 tem = op0, op0 = op1, op1 = tem;
10188 if (GET_RTX_CLASS (code) == '<')
10190 enum machine_mode op_mode = GET_MODE (op0);
10192 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10193 just (REL_OP X Y). */
10194 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10196 op1 = XEXP (op0, 1);
10197 op0 = XEXP (op0, 0);
10198 op_mode = GET_MODE (op0);
10201 if (op_mode == VOIDmode)
10202 op_mode = GET_MODE (op1);
10203 result = simplify_relational_operation (code, op_mode, op0, op1);
10206 result = simplify_binary_operation (code, mode, op0, op1);
10211 /* Put complex operands first and constants second. */
10212 if (GET_RTX_CLASS (code) == 'c'
10213 && swap_commutative_operands_p (op0, op1))
10214 return gen_rtx_fmt_ee (code, mode, op1, op0);
10216 /* If we are turning off bits already known off in OP0, we need not do
10218 else if (code == AND && GET_CODE (op1) == CONST_INT
10219 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10220 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10223 return gen_rtx_fmt_ee (code, mode, op0, op1);
10226 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10227 comparison code that will be tested.
10229 The result is a possibly different comparison code to use. *POP0 and
10230 *POP1 may be updated.
10232 It is possible that we might detect that a comparison is either always
10233 true or always false. However, we do not perform general constant
10234 folding in combine, so this knowledge isn't useful. Such tautologies
10235 should have been detected earlier. Hence we ignore all such cases. */
10237 static enum rtx_code
10238 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10244 enum machine_mode mode, tmode;
10246 /* Try a few ways of applying the same transformation to both operands. */
10249 #ifndef WORD_REGISTER_OPERATIONS
10250 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10251 so check specially. */
10252 if (code != GTU && code != GEU && code != LTU && code != LEU
10253 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10254 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10255 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10256 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10257 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10258 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10259 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10260 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10261 && XEXP (op0, 1) == XEXP (op1, 1)
10262 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10263 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10264 && (INTVAL (XEXP (op0, 1))
10265 == (GET_MODE_BITSIZE (GET_MODE (op0))
10266 - (GET_MODE_BITSIZE
10267 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10269 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10270 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10274 /* If both operands are the same constant shift, see if we can ignore the
10275 shift. We can if the shift is a rotate or if the bits shifted out of
10276 this shift are known to be zero for both inputs and if the type of
10277 comparison is compatible with the shift. */
10278 if (GET_CODE (op0) == GET_CODE (op1)
10279 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10280 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10281 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10282 && (code != GT && code != LT && code != GE && code != LE))
10283 || (GET_CODE (op0) == ASHIFTRT
10284 && (code != GTU && code != LTU
10285 && code != GEU && code != LEU)))
10286 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10287 && INTVAL (XEXP (op0, 1)) >= 0
10288 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10289 && XEXP (op0, 1) == XEXP (op1, 1))
10291 enum machine_mode mode = GET_MODE (op0);
10292 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10293 int shift_count = INTVAL (XEXP (op0, 1));
10295 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10296 mask &= (mask >> shift_count) << shift_count;
10297 else if (GET_CODE (op0) == ASHIFT)
10298 mask = (mask & (mask << shift_count)) >> shift_count;
10300 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10301 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10302 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10307 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10308 SUBREGs are of the same mode, and, in both cases, the AND would
10309 be redundant if the comparison was done in the narrower mode,
10310 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10311 and the operand's possibly nonzero bits are 0xffffff01; in that case
10312 if we only care about QImode, we don't need the AND). This case
10313 occurs if the output mode of an scc insn is not SImode and
10314 STORE_FLAG_VALUE == 1 (e.g., the 386).
10316 Similarly, check for a case where the AND's are ZERO_EXTEND
10317 operations from some narrower mode even though a SUBREG is not
10320 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10321 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10322 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10324 rtx inner_op0 = XEXP (op0, 0);
10325 rtx inner_op1 = XEXP (op1, 0);
10326 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10327 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10330 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10331 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10332 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10333 && (GET_MODE (SUBREG_REG (inner_op0))
10334 == GET_MODE (SUBREG_REG (inner_op1)))
10335 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10336 <= HOST_BITS_PER_WIDE_INT)
10337 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10338 GET_MODE (SUBREG_REG (inner_op0)))))
10339 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10340 GET_MODE (SUBREG_REG (inner_op1))))))
10342 op0 = SUBREG_REG (inner_op0);
10343 op1 = SUBREG_REG (inner_op1);
10345 /* The resulting comparison is always unsigned since we masked
10346 off the original sign bit. */
10347 code = unsigned_condition (code);
10353 for (tmode = GET_CLASS_NARROWEST_MODE
10354 (GET_MODE_CLASS (GET_MODE (op0)));
10355 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10356 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10358 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10359 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10360 code = unsigned_condition (code);
10369 /* If both operands are NOT, we can strip off the outer operation
10370 and adjust the comparison code for swapped operands; similarly for
10371 NEG, except that this must be an equality comparison. */
10372 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10373 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10374 && (code == EQ || code == NE)))
10375 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10381 /* If the first operand is a constant, swap the operands and adjust the
10382 comparison code appropriately, but don't do this if the second operand
10383 is already a constant integer. */
10384 if (swap_commutative_operands_p (op0, op1))
10386 tem = op0, op0 = op1, op1 = tem;
10387 code = swap_condition (code);
10390 /* We now enter a loop during which we will try to simplify the comparison.
10391 For the most part, we only are concerned with comparisons with zero,
10392 but some things may really be comparisons with zero but not start
10393 out looking that way. */
10395 while (GET_CODE (op1) == CONST_INT)
10397 enum machine_mode mode = GET_MODE (op0);
10398 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10399 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10400 int equality_comparison_p;
10401 int sign_bit_comparison_p;
10402 int unsigned_comparison_p;
10403 HOST_WIDE_INT const_op;
10405 /* We only want to handle integral modes. This catches VOIDmode,
10406 CCmode, and the floating-point modes. An exception is that we
10407 can handle VOIDmode if OP0 is a COMPARE or a comparison
10410 if (GET_MODE_CLASS (mode) != MODE_INT
10411 && ! (mode == VOIDmode
10412 && (GET_CODE (op0) == COMPARE
10413 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10416 /* Get the constant we are comparing against and turn off all bits
10417 not on in our mode. */
10418 const_op = INTVAL (op1);
10419 if (mode != VOIDmode)
10420 const_op = trunc_int_for_mode (const_op, mode);
10421 op1 = GEN_INT (const_op);
10423 /* If we are comparing against a constant power of two and the value
10424 being compared can only have that single bit nonzero (e.g., it was
10425 `and'ed with that bit), we can replace this with a comparison
10428 && (code == EQ || code == NE || code == GE || code == GEU
10429 || code == LT || code == LTU)
10430 && mode_width <= HOST_BITS_PER_WIDE_INT
10431 && exact_log2 (const_op) >= 0
10432 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10434 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10435 op1 = const0_rtx, const_op = 0;
10438 /* Similarly, if we are comparing a value known to be either -1 or
10439 0 with -1, change it to the opposite comparison against zero. */
10442 && (code == EQ || code == NE || code == GT || code == LE
10443 || code == GEU || code == LTU)
10444 && num_sign_bit_copies (op0, mode) == mode_width)
10446 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10447 op1 = const0_rtx, const_op = 0;
10450 /* Do some canonicalizations based on the comparison code. We prefer
10451 comparisons against zero and then prefer equality comparisons.
10452 If we can reduce the size of a constant, we will do that too. */
10457 /* < C is equivalent to <= (C - 1) */
10461 op1 = GEN_INT (const_op);
10463 /* ... fall through to LE case below. */
10469 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10473 op1 = GEN_INT (const_op);
10477 /* If we are doing a <= 0 comparison on a value known to have
10478 a zero sign bit, we can replace this with == 0. */
10479 else if (const_op == 0
10480 && mode_width <= HOST_BITS_PER_WIDE_INT
10481 && (nonzero_bits (op0, mode)
10482 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10487 /* >= C is equivalent to > (C - 1). */
10491 op1 = GEN_INT (const_op);
10493 /* ... fall through to GT below. */
10499 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10503 op1 = GEN_INT (const_op);
10507 /* If we are doing a > 0 comparison on a value known to have
10508 a zero sign bit, we can replace this with != 0. */
10509 else if (const_op == 0
10510 && mode_width <= HOST_BITS_PER_WIDE_INT
10511 && (nonzero_bits (op0, mode)
10512 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10517 /* < C is equivalent to <= (C - 1). */
10521 op1 = GEN_INT (const_op);
10523 /* ... fall through ... */
10526 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10527 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10528 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10530 const_op = 0, op1 = const0_rtx;
10538 /* unsigned <= 0 is equivalent to == 0 */
10542 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10543 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10544 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10546 const_op = 0, op1 = const0_rtx;
10552 /* >= C is equivalent to < (C - 1). */
10556 op1 = GEN_INT (const_op);
10558 /* ... fall through ... */
10561 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10562 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10563 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10565 const_op = 0, op1 = const0_rtx;
10573 /* unsigned > 0 is equivalent to != 0 */
10577 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10578 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10579 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10581 const_op = 0, op1 = const0_rtx;
10590 /* Compute some predicates to simplify code below. */
10592 equality_comparison_p = (code == EQ || code == NE);
10593 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10594 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10597 /* If this is a sign bit comparison and we can do arithmetic in
10598 MODE, say that we will only be needing the sign bit of OP0. */
10599 if (sign_bit_comparison_p
10600 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10601 op0 = force_to_mode (op0, mode,
10603 << (GET_MODE_BITSIZE (mode) - 1)),
10606 /* Now try cases based on the opcode of OP0. If none of the cases
10607 does a "continue", we exit this loop immediately after the
10610 switch (GET_CODE (op0))
10613 /* If we are extracting a single bit from a variable position in
10614 a constant that has only a single bit set and are comparing it
10615 with zero, we can convert this into an equality comparison
10616 between the position and the location of the single bit. */
10618 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10619 && XEXP (op0, 1) == const1_rtx
10620 && equality_comparison_p && const_op == 0
10621 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10623 if (BITS_BIG_ENDIAN)
10625 enum machine_mode new_mode
10626 = mode_for_extraction (EP_extzv, 1);
10627 if (new_mode == MAX_MACHINE_MODE)
10628 i = BITS_PER_WORD - 1 - i;
10632 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10636 op0 = XEXP (op0, 2);
10640 /* Result is nonzero iff shift count is equal to I. */
10641 code = reverse_condition (code);
10645 /* ... fall through ... */
10648 tem = expand_compound_operation (op0);
10657 /* If testing for equality, we can take the NOT of the constant. */
10658 if (equality_comparison_p
10659 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10661 op0 = XEXP (op0, 0);
10666 /* If just looking at the sign bit, reverse the sense of the
10668 if (sign_bit_comparison_p)
10670 op0 = XEXP (op0, 0);
10671 code = (code == GE ? LT : GE);
10677 /* If testing for equality, we can take the NEG of the constant. */
10678 if (equality_comparison_p
10679 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10681 op0 = XEXP (op0, 0);
10686 /* The remaining cases only apply to comparisons with zero. */
10690 /* When X is ABS or is known positive,
10691 (neg X) is < 0 if and only if X != 0. */
10693 if (sign_bit_comparison_p
10694 && (GET_CODE (XEXP (op0, 0)) == ABS
10695 || (mode_width <= HOST_BITS_PER_WIDE_INT
10696 && (nonzero_bits (XEXP (op0, 0), mode)
10697 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10699 op0 = XEXP (op0, 0);
10700 code = (code == LT ? NE : EQ);
10704 /* If we have NEG of something whose two high-order bits are the
10705 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10706 if (num_sign_bit_copies (op0, mode) >= 2)
10708 op0 = XEXP (op0, 0);
10709 code = swap_condition (code);
10715 /* If we are testing equality and our count is a constant, we
10716 can perform the inverse operation on our RHS. */
10717 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10718 && (tem = simplify_binary_operation (ROTATERT, mode,
10719 op1, XEXP (op0, 1))) != 0)
10721 op0 = XEXP (op0, 0);
10726 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10727 a particular bit. Convert it to an AND of a constant of that
10728 bit. This will be converted into a ZERO_EXTRACT. */
10729 if (const_op == 0 && sign_bit_comparison_p
10730 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10731 && mode_width <= HOST_BITS_PER_WIDE_INT)
10733 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10736 - INTVAL (XEXP (op0, 1)))));
10737 code = (code == LT ? NE : EQ);
10741 /* Fall through. */
10744 /* ABS is ignorable inside an equality comparison with zero. */
10745 if (const_op == 0 && equality_comparison_p)
10747 op0 = XEXP (op0, 0);
10753 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10754 to (compare FOO CONST) if CONST fits in FOO's mode and we
10755 are either testing inequality or have an unsigned comparison
10756 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10757 if (! unsigned_comparison_p
10758 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10759 <= HOST_BITS_PER_WIDE_INT)
10760 && ((unsigned HOST_WIDE_INT) const_op
10761 < (((unsigned HOST_WIDE_INT) 1
10762 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10764 op0 = XEXP (op0, 0);
10770 /* Check for the case where we are comparing A - C1 with C2,
10771 both constants are smaller than 1/2 the maximum positive
10772 value in MODE, and the comparison is equality or unsigned.
10773 In that case, if A is either zero-extended to MODE or has
10774 sufficient sign bits so that the high-order bit in MODE
10775 is a copy of the sign in the inner mode, we can prove that it is
10776 safe to do the operation in the wider mode. This simplifies
10777 many range checks. */
10779 if (mode_width <= HOST_BITS_PER_WIDE_INT
10780 && subreg_lowpart_p (op0)
10781 && GET_CODE (SUBREG_REG (op0)) == PLUS
10782 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10783 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10784 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10785 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10786 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10787 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10788 GET_MODE (SUBREG_REG (op0)))
10789 & ~GET_MODE_MASK (mode))
10790 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10791 GET_MODE (SUBREG_REG (op0)))
10793 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10794 - GET_MODE_BITSIZE (mode)))))
10796 op0 = SUBREG_REG (op0);
10800 /* If the inner mode is narrower and we are extracting the low part,
10801 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10802 if (subreg_lowpart_p (op0)
10803 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10804 /* Fall through */ ;
10808 /* ... fall through ... */
10811 if ((unsigned_comparison_p || equality_comparison_p)
10812 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10813 <= HOST_BITS_PER_WIDE_INT)
10814 && ((unsigned HOST_WIDE_INT) const_op
10815 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10817 op0 = XEXP (op0, 0);
10823 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10824 this for equality comparisons due to pathological cases involving
10826 if (equality_comparison_p
10827 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10828 op1, XEXP (op0, 1))))
10830 op0 = XEXP (op0, 0);
10835 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10836 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10837 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10839 op0 = XEXP (XEXP (op0, 0), 0);
10840 code = (code == LT ? EQ : NE);
10846 /* We used to optimize signed comparisons against zero, but that
10847 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10848 arrive here as equality comparisons, or (GEU, LTU) are
10849 optimized away. No need to special-case them. */
10851 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10852 (eq B (minus A C)), whichever simplifies. We can only do
10853 this for equality comparisons due to pathological cases involving
10855 if (equality_comparison_p
10856 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10857 XEXP (op0, 1), op1)))
10859 op0 = XEXP (op0, 0);
10864 if (equality_comparison_p
10865 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10866 XEXP (op0, 0), op1)))
10868 op0 = XEXP (op0, 1);
10873 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10874 of bits in X minus 1, is one iff X > 0. */
10875 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10876 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10877 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10879 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10881 op0 = XEXP (op0, 1);
10882 code = (code == GE ? LE : GT);
10888 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10889 if C is zero or B is a constant. */
10890 if (equality_comparison_p
10891 && 0 != (tem = simplify_binary_operation (XOR, mode,
10892 XEXP (op0, 1), op1)))
10894 op0 = XEXP (op0, 0);
10901 case UNEQ: case LTGT:
10902 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10903 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10904 case UNORDERED: case ORDERED:
10905 /* We can't do anything if OP0 is a condition code value, rather
10906 than an actual data value. */
10908 || CC0_P (XEXP (op0, 0))
10909 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10912 /* Get the two operands being compared. */
10913 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10914 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10916 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10918 /* Check for the cases where we simply want the result of the
10919 earlier test or the opposite of that result. */
10920 if (code == NE || code == EQ
10921 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10922 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10923 && (STORE_FLAG_VALUE
10924 & (((HOST_WIDE_INT) 1
10925 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10926 && (code == LT || code == GE)))
10928 enum rtx_code new_code;
10929 if (code == LT || code == NE)
10930 new_code = GET_CODE (op0);
10932 new_code = combine_reversed_comparison_code (op0);
10934 if (new_code != UNKNOWN)
10945 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10947 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10948 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10949 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10951 op0 = XEXP (op0, 1);
10952 code = (code == GE ? GT : LE);
10958 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10959 will be converted to a ZERO_EXTRACT later. */
10960 if (const_op == 0 && equality_comparison_p
10961 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10962 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10964 op0 = simplify_and_const_int
10965 (op0, mode, gen_rtx_LSHIFTRT (mode,
10967 XEXP (XEXP (op0, 0), 1)),
10968 (HOST_WIDE_INT) 1);
10972 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10973 zero and X is a comparison and C1 and C2 describe only bits set
10974 in STORE_FLAG_VALUE, we can compare with X. */
10975 if (const_op == 0 && equality_comparison_p
10976 && mode_width <= HOST_BITS_PER_WIDE_INT
10977 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10978 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10979 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10980 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10981 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10983 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10984 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10985 if ((~STORE_FLAG_VALUE & mask) == 0
10986 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10987 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10988 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10990 op0 = XEXP (XEXP (op0, 0), 0);
10995 /* If we are doing an equality comparison of an AND of a bit equal
10996 to the sign bit, replace this with a LT or GE comparison of
10997 the underlying value. */
10998 if (equality_comparison_p
11000 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11001 && mode_width <= HOST_BITS_PER_WIDE_INT
11002 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11003 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11005 op0 = XEXP (op0, 0);
11006 code = (code == EQ ? GE : LT);
11010 /* If this AND operation is really a ZERO_EXTEND from a narrower
11011 mode, the constant fits within that mode, and this is either an
11012 equality or unsigned comparison, try to do this comparison in
11013 the narrower mode. */
11014 if ((equality_comparison_p || unsigned_comparison_p)
11015 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11016 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11017 & GET_MODE_MASK (mode))
11019 && const_op >> i == 0
11020 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11022 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11026 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11027 fits in both M1 and M2 and the SUBREG is either paradoxical
11028 or represents the low part, permute the SUBREG and the AND
11030 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11032 unsigned HOST_WIDE_INT c1;
11033 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11034 /* Require an integral mode, to avoid creating something like
11036 if (SCALAR_INT_MODE_P (tmode)
11037 /* It is unsafe to commute the AND into the SUBREG if the
11038 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11039 not defined. As originally written the upper bits
11040 have a defined value due to the AND operation.
11041 However, if we commute the AND inside the SUBREG then
11042 they no longer have defined values and the meaning of
11043 the code has been changed. */
11045 #ifdef WORD_REGISTER_OPERATIONS
11046 || (mode_width > GET_MODE_BITSIZE (tmode)
11047 && mode_width <= BITS_PER_WORD)
11049 || (mode_width <= GET_MODE_BITSIZE (tmode)
11050 && subreg_lowpart_p (XEXP (op0, 0))))
11051 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11052 && mode_width <= HOST_BITS_PER_WIDE_INT
11053 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11054 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11055 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11057 && c1 != GET_MODE_MASK (tmode))
11059 op0 = gen_binary (AND, tmode,
11060 SUBREG_REG (XEXP (op0, 0)),
11061 gen_int_mode (c1, tmode));
11062 op0 = gen_lowpart_for_combine (mode, op0);
11067 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11068 if (const_op == 0 && equality_comparison_p
11069 && XEXP (op0, 1) == const1_rtx
11070 && GET_CODE (XEXP (op0, 0)) == NOT)
11072 op0 = simplify_and_const_int
11073 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11074 code = (code == NE ? EQ : NE);
11078 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11079 (eq (and (lshiftrt X) 1) 0). */
11080 if (const_op == 0 && equality_comparison_p
11081 && XEXP (op0, 1) == const1_rtx
11082 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11083 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11085 op0 = simplify_and_const_int
11087 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11088 XEXP (XEXP (op0, 0), 1)),
11089 (HOST_WIDE_INT) 1);
11090 code = (code == NE ? EQ : NE);
11096 /* If we have (compare (ashift FOO N) (const_int C)) and
11097 the high order N bits of FOO (N+1 if an inequality comparison)
11098 are known to be zero, we can do this by comparing FOO with C
11099 shifted right N bits so long as the low-order N bits of C are
11101 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11102 && INTVAL (XEXP (op0, 1)) >= 0
11103 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11104 < HOST_BITS_PER_WIDE_INT)
11106 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11107 && mode_width <= HOST_BITS_PER_WIDE_INT
11108 && (nonzero_bits (XEXP (op0, 0), mode)
11109 & ~(mask >> (INTVAL (XEXP (op0, 1))
11110 + ! equality_comparison_p))) == 0)
11112 /* We must perform a logical shift, not an arithmetic one,
11113 as we want the top N bits of C to be zero. */
11114 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11116 temp >>= INTVAL (XEXP (op0, 1));
11117 op1 = gen_int_mode (temp, mode);
11118 op0 = XEXP (op0, 0);
11122 /* If we are doing a sign bit comparison, it means we are testing
11123 a particular bit. Convert it to the appropriate AND. */
11124 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11125 && mode_width <= HOST_BITS_PER_WIDE_INT)
11127 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11130 - INTVAL (XEXP (op0, 1)))));
11131 code = (code == LT ? NE : EQ);
11135 /* If this an equality comparison with zero and we are shifting
11136 the low bit to the sign bit, we can convert this to an AND of the
11138 if (const_op == 0 && equality_comparison_p
11139 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11140 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11143 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11144 (HOST_WIDE_INT) 1);
11150 /* If this is an equality comparison with zero, we can do this
11151 as a logical shift, which might be much simpler. */
11152 if (equality_comparison_p && const_op == 0
11153 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11155 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11157 INTVAL (XEXP (op0, 1)));
11161 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11162 do the comparison in a narrower mode. */
11163 if (! unsigned_comparison_p
11164 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11165 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11166 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11167 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11168 MODE_INT, 1)) != BLKmode
11169 && (((unsigned HOST_WIDE_INT) const_op
11170 + (GET_MODE_MASK (tmode) >> 1) + 1)
11171 <= GET_MODE_MASK (tmode)))
11173 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11177 /* Likewise if OP0 is a PLUS of a sign extension with a
11178 constant, which is usually represented with the PLUS
11179 between the shifts. */
11180 if (! unsigned_comparison_p
11181 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11182 && GET_CODE (XEXP (op0, 0)) == PLUS
11183 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11184 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11185 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11186 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11187 MODE_INT, 1)) != BLKmode
11188 && (((unsigned HOST_WIDE_INT) const_op
11189 + (GET_MODE_MASK (tmode) >> 1) + 1)
11190 <= GET_MODE_MASK (tmode)))
11192 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11193 rtx add_const = XEXP (XEXP (op0, 0), 1);
11194 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11197 op0 = gen_binary (PLUS, tmode,
11198 gen_lowpart_for_combine (tmode, inner),
11203 /* ... fall through ... */
11205 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11206 the low order N bits of FOO are known to be zero, we can do this
11207 by comparing FOO with C shifted left N bits so long as no
11208 overflow occurs. */
11209 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11210 && INTVAL (XEXP (op0, 1)) >= 0
11211 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11212 && mode_width <= HOST_BITS_PER_WIDE_INT
11213 && (nonzero_bits (XEXP (op0, 0), mode)
11214 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11215 && (((unsigned HOST_WIDE_INT) const_op
11216 + (GET_CODE (op0) != LSHIFTRT
11217 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11220 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11222 /* If the shift was logical, then we must make the condition
11224 if (GET_CODE (op0) == LSHIFTRT)
11225 code = unsigned_condition (code);
11227 const_op <<= INTVAL (XEXP (op0, 1));
11228 op1 = GEN_INT (const_op);
11229 op0 = XEXP (op0, 0);
11233 /* If we are using this shift to extract just the sign bit, we
11234 can replace this with an LT or GE comparison. */
11236 && (equality_comparison_p || sign_bit_comparison_p)
11237 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11238 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11241 op0 = XEXP (op0, 0);
11242 code = (code == NE || code == GT ? LT : GE);
11254 /* Now make any compound operations involved in this comparison. Then,
11255 check for an outmost SUBREG on OP0 that is not doing anything or is
11256 paradoxical. The latter transformation must only be performed when
11257 it is known that the "extra" bits will be the same in op0 and op1 or
11258 that they don't matter. There are three cases to consider:
11260 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11261 care bits and we can assume they have any convenient value. So
11262 making the transformation is safe.
11264 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11265 In this case the upper bits of op0 are undefined. We should not make
11266 the simplification in that case as we do not know the contents of
11269 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11270 NIL. In that case we know those bits are zeros or ones. We must
11271 also be sure that they are the same as the upper bits of op1.
11273 We can never remove a SUBREG for a non-equality comparison because
11274 the sign bit is in a different place in the underlying object. */
11276 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11277 op1 = make_compound_operation (op1, SET);
11279 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11280 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11282 && GET_CODE (SUBREG_REG (op0)) == REG
11283 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11284 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11285 && (code == NE || code == EQ))
11287 if (GET_MODE_SIZE (GET_MODE (op0))
11288 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11290 op0 = SUBREG_REG (op0);
11291 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11293 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11294 <= HOST_BITS_PER_WIDE_INT)
11295 && (nonzero_bits (SUBREG_REG (op0),
11296 GET_MODE (SUBREG_REG (op0)))
11297 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11299 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11301 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11302 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11303 op0 = SUBREG_REG (op0), op1 = tem;
11307 /* We now do the opposite procedure: Some machines don't have compare
11308 insns in all modes. If OP0's mode is an integer mode smaller than a
11309 word and we can't do a compare in that mode, see if there is a larger
11310 mode for which we can do the compare. There are a number of cases in
11311 which we can use the wider mode. */
11313 mode = GET_MODE (op0);
11314 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11315 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11316 && ! have_insn_for (COMPARE, mode))
11317 for (tmode = GET_MODE_WIDER_MODE (mode);
11319 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11320 tmode = GET_MODE_WIDER_MODE (tmode))
11321 if (have_insn_for (COMPARE, tmode))
11325 /* If the only nonzero bits in OP0 and OP1 are those in the
11326 narrower mode and this is an equality or unsigned comparison,
11327 we can use the wider mode. Similarly for sign-extended
11328 values, in which case it is true for all comparisons. */
11329 zero_extended = ((code == EQ || code == NE
11330 || code == GEU || code == GTU
11331 || code == LEU || code == LTU)
11332 && (nonzero_bits (op0, tmode)
11333 & ~GET_MODE_MASK (mode)) == 0
11334 && ((GET_CODE (op1) == CONST_INT
11335 || (nonzero_bits (op1, tmode)
11336 & ~GET_MODE_MASK (mode)) == 0)));
11339 || ((num_sign_bit_copies (op0, tmode)
11340 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11341 - GET_MODE_BITSIZE (mode)))
11342 && (num_sign_bit_copies (op1, tmode)
11343 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11344 - GET_MODE_BITSIZE (mode)))))
11346 /* If OP0 is an AND and we don't have an AND in MODE either,
11347 make a new AND in the proper mode. */
11348 if (GET_CODE (op0) == AND
11349 && !have_insn_for (AND, mode))
11350 op0 = gen_binary (AND, tmode,
11351 gen_lowpart_for_combine (tmode,
11353 gen_lowpart_for_combine (tmode,
11356 op0 = gen_lowpart_for_combine (tmode, op0);
11357 if (zero_extended && GET_CODE (op1) == CONST_INT)
11358 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11359 op1 = gen_lowpart_for_combine (tmode, op1);
11363 /* If this is a test for negative, we can make an explicit
11364 test of the sign bit. */
11366 if (op1 == const0_rtx && (code == LT || code == GE)
11367 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11369 op0 = gen_binary (AND, tmode,
11370 gen_lowpart_for_combine (tmode, op0),
11371 GEN_INT ((HOST_WIDE_INT) 1
11372 << (GET_MODE_BITSIZE (mode) - 1)));
11373 code = (code == LT) ? NE : EQ;
11378 #ifdef CANONICALIZE_COMPARISON
11379 /* If this machine only supports a subset of valid comparisons, see if we
11380 can convert an unsupported one into a supported one. */
11381 CANONICALIZE_COMPARISON (code, op0, op1);
11390 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11391 searching backward. */
11392 static enum rtx_code
11393 combine_reversed_comparison_code (rtx exp)
11395 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11398 if (code1 != UNKNOWN
11399 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11401 /* Otherwise try and find where the condition codes were last set and
11403 x = get_last_value (XEXP (exp, 0));
11404 if (!x || GET_CODE (x) != COMPARE)
11406 return reversed_comparison_code_parts (GET_CODE (exp),
11407 XEXP (x, 0), XEXP (x, 1), NULL);
11410 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11411 Return NULL_RTX in case we fail to do the reversal. */
11413 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11415 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11416 if (reversed_code == UNKNOWN)
11419 return gen_binary (reversed_code, mode, op0, op1);
11422 /* Utility function for following routine. Called when X is part of a value
11423 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11424 for each register mentioned. Similar to mention_regs in cse.c */
11427 update_table_tick (rtx x)
11429 enum rtx_code code = GET_CODE (x);
11430 const char *fmt = GET_RTX_FORMAT (code);
11435 unsigned int regno = REGNO (x);
11436 unsigned int endregno
11437 = regno + (regno < FIRST_PSEUDO_REGISTER
11438 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11441 for (r = regno; r < endregno; r++)
11442 reg_last_set_table_tick[r] = label_tick;
11447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11448 /* Note that we can't have an "E" in values stored; see
11449 get_last_value_validate. */
11452 /* Check for identical subexpressions. If x contains
11453 identical subexpression we only have to traverse one of
11456 && (GET_RTX_CLASS (code) == '2'
11457 || GET_RTX_CLASS (code) == 'c'))
11459 /* Note that at this point x1 has already been
11461 rtx x0 = XEXP (x, 0);
11462 rtx x1 = XEXP (x, 1);
11464 /* If x0 and x1 are identical then there is no need to
11469 /* If x0 is identical to a subexpression of x1 then while
11470 processing x1, x0 has already been processed. Thus we
11471 are done with x. */
11472 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11473 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11474 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11477 /* If x1 is identical to a subexpression of x0 then we
11478 still have to process the rest of x0. */
11479 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11480 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11481 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11483 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11488 update_table_tick (XEXP (x, i));
11492 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11493 are saying that the register is clobbered and we no longer know its
11494 value. If INSN is zero, don't update reg_last_set; this is only permitted
11495 with VALUE also zero and is used to invalidate the register. */
11498 record_value_for_reg (rtx reg, rtx insn, rtx value)
11500 unsigned int regno = REGNO (reg);
11501 unsigned int endregno
11502 = regno + (regno < FIRST_PSEUDO_REGISTER
11503 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11506 /* If VALUE contains REG and we have a previous value for REG, substitute
11507 the previous value. */
11508 if (value && insn && reg_overlap_mentioned_p (reg, value))
11512 /* Set things up so get_last_value is allowed to see anything set up to
11514 subst_low_cuid = INSN_CUID (insn);
11515 tem = get_last_value (reg);
11517 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11518 it isn't going to be useful and will take a lot of time to process,
11519 so just use the CLOBBER. */
11523 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11524 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11525 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11526 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11527 tem = XEXP (tem, 0);
11529 value = replace_rtx (copy_rtx (value), reg, tem);
11533 /* For each register modified, show we don't know its value, that
11534 we don't know about its bitwise content, that its value has been
11535 updated, and that we don't know the location of the death of the
11537 for (i = regno; i < endregno; i++)
11540 reg_last_set[i] = insn;
11542 reg_last_set_value[i] = 0;
11543 reg_last_set_mode[i] = 0;
11544 reg_last_set_nonzero_bits[i] = 0;
11545 reg_last_set_sign_bit_copies[i] = 0;
11546 reg_last_death[i] = 0;
11549 /* Mark registers that are being referenced in this value. */
11551 update_table_tick (value);
11553 /* Now update the status of each register being set.
11554 If someone is using this register in this block, set this register
11555 to invalid since we will get confused between the two lives in this
11556 basic block. This makes using this register always invalid. In cse, we
11557 scan the table to invalidate all entries using this register, but this
11558 is too much work for us. */
11560 for (i = regno; i < endregno; i++)
11562 reg_last_set_label[i] = label_tick;
11563 if (value && reg_last_set_table_tick[i] == label_tick)
11564 reg_last_set_invalid[i] = 1;
11566 reg_last_set_invalid[i] = 0;
11569 /* The value being assigned might refer to X (like in "x++;"). In that
11570 case, we must replace it with (clobber (const_int 0)) to prevent
11572 if (value && ! get_last_value_validate (&value, insn,
11573 reg_last_set_label[regno], 0))
11575 value = copy_rtx (value);
11576 if (! get_last_value_validate (&value, insn,
11577 reg_last_set_label[regno], 1))
11581 /* For the main register being modified, update the value, the mode, the
11582 nonzero bits, and the number of sign bit copies. */
11584 reg_last_set_value[regno] = value;
11588 enum machine_mode mode = GET_MODE (reg);
11589 subst_low_cuid = INSN_CUID (insn);
11590 reg_last_set_mode[regno] = mode;
11591 if (GET_MODE_CLASS (mode) == MODE_INT
11592 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11593 mode = nonzero_bits_mode;
11594 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11595 reg_last_set_sign_bit_copies[regno]
11596 = num_sign_bit_copies (value, GET_MODE (reg));
11600 /* Called via note_stores from record_dead_and_set_regs to handle one
11601 SET or CLOBBER in an insn. DATA is the instruction in which the
11602 set is occurring. */
11605 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11607 rtx record_dead_insn = (rtx) data;
11609 if (GET_CODE (dest) == SUBREG)
11610 dest = SUBREG_REG (dest);
11612 if (GET_CODE (dest) == REG)
11614 /* If we are setting the whole register, we know its value. Otherwise
11615 show that we don't know the value. We can handle SUBREG in
11617 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11618 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11619 else if (GET_CODE (setter) == SET
11620 && GET_CODE (SET_DEST (setter)) == SUBREG
11621 && SUBREG_REG (SET_DEST (setter)) == dest
11622 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11623 && subreg_lowpart_p (SET_DEST (setter)))
11624 record_value_for_reg (dest, record_dead_insn,
11625 gen_lowpart_for_combine (GET_MODE (dest),
11626 SET_SRC (setter)));
11628 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11630 else if (GET_CODE (dest) == MEM
11631 /* Ignore pushes, they clobber nothing. */
11632 && ! push_operand (dest, GET_MODE (dest)))
11633 mem_last_set = INSN_CUID (record_dead_insn);
11636 /* Update the records of when each REG was most recently set or killed
11637 for the things done by INSN. This is the last thing done in processing
11638 INSN in the combiner loop.
11640 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11641 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11642 and also the similar information mem_last_set (which insn most recently
11643 modified memory) and last_call_cuid (which insn was the most recent
11644 subroutine call). */
11647 record_dead_and_set_regs (rtx insn)
11652 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11654 if (REG_NOTE_KIND (link) == REG_DEAD
11655 && GET_CODE (XEXP (link, 0)) == REG)
11657 unsigned int regno = REGNO (XEXP (link, 0));
11658 unsigned int endregno
11659 = regno + (regno < FIRST_PSEUDO_REGISTER
11660 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11663 for (i = regno; i < endregno; i++)
11664 reg_last_death[i] = insn;
11666 else if (REG_NOTE_KIND (link) == REG_INC)
11667 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11670 if (GET_CODE (insn) == CALL_INSN)
11672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11673 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11675 reg_last_set_value[i] = 0;
11676 reg_last_set_mode[i] = 0;
11677 reg_last_set_nonzero_bits[i] = 0;
11678 reg_last_set_sign_bit_copies[i] = 0;
11679 reg_last_death[i] = 0;
11682 last_call_cuid = mem_last_set = INSN_CUID (insn);
11684 /* Don't bother recording what this insn does. It might set the
11685 return value register, but we can't combine into a call
11686 pattern anyway, so there's no point trying (and it may cause
11687 a crash, if e.g. we wind up asking for last_set_value of a
11688 SUBREG of the return value register). */
11692 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11695 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11696 register present in the SUBREG, so for each such SUBREG go back and
11697 adjust nonzero and sign bit information of the registers that are
11698 known to have some zero/sign bits set.
11700 This is needed because when combine blows the SUBREGs away, the
11701 information on zero/sign bits is lost and further combines can be
11702 missed because of that. */
11705 record_promoted_value (rtx insn, rtx subreg)
11708 unsigned int regno = REGNO (SUBREG_REG (subreg));
11709 enum machine_mode mode = GET_MODE (subreg);
11711 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11714 for (links = LOG_LINKS (insn); links;)
11716 insn = XEXP (links, 0);
11717 set = single_set (insn);
11719 if (! set || GET_CODE (SET_DEST (set)) != REG
11720 || REGNO (SET_DEST (set)) != regno
11721 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11723 links = XEXP (links, 1);
11727 if (reg_last_set[regno] == insn)
11729 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11730 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11733 if (GET_CODE (SET_SRC (set)) == REG)
11735 regno = REGNO (SET_SRC (set));
11736 links = LOG_LINKS (insn);
11743 /* Scan X for promoted SUBREGs. For each one found,
11744 note what it implies to the registers used in it. */
11747 check_promoted_subreg (rtx insn, rtx x)
11749 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11750 && GET_CODE (SUBREG_REG (x)) == REG)
11751 record_promoted_value (insn, x);
11754 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11757 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11761 check_promoted_subreg (insn, XEXP (x, i));
11765 if (XVEC (x, i) != 0)
11766 for (j = 0; j < XVECLEN (x, i); j++)
11767 check_promoted_subreg (insn, XVECEXP (x, i, j));
11773 /* Utility routine for the following function. Verify that all the registers
11774 mentioned in *LOC are valid when *LOC was part of a value set when
11775 label_tick == TICK. Return 0 if some are not.
11777 If REPLACE is nonzero, replace the invalid reference with
11778 (clobber (const_int 0)) and return 1. This replacement is useful because
11779 we often can get useful information about the form of a value (e.g., if
11780 it was produced by a shift that always produces -1 or 0) even though
11781 we don't know exactly what registers it was produced from. */
11784 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11787 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11788 int len = GET_RTX_LENGTH (GET_CODE (x));
11791 if (GET_CODE (x) == REG)
11793 unsigned int regno = REGNO (x);
11794 unsigned int endregno
11795 = regno + (regno < FIRST_PSEUDO_REGISTER
11796 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11799 for (j = regno; j < endregno; j++)
11800 if (reg_last_set_invalid[j]
11801 /* If this is a pseudo-register that was only set once and not
11802 live at the beginning of the function, it is always valid. */
11803 || (! (regno >= FIRST_PSEUDO_REGISTER
11804 && REG_N_SETS (regno) == 1
11805 && (! REGNO_REG_SET_P
11806 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11807 && reg_last_set_label[j] > tick))
11810 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11816 /* If this is a memory reference, make sure that there were
11817 no stores after it that might have clobbered the value. We don't
11818 have alias info, so we assume any store invalidates it. */
11819 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11820 && INSN_CUID (insn) <= mem_last_set)
11823 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11827 for (i = 0; i < len; i++)
11831 /* Check for identical subexpressions. If x contains
11832 identical subexpression we only have to traverse one of
11835 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11836 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11838 /* Note that at this point x0 has already been checked
11839 and found valid. */
11840 rtx x0 = XEXP (x, 0);
11841 rtx x1 = XEXP (x, 1);
11843 /* If x0 and x1 are identical then x is also valid. */
11847 /* If x1 is identical to a subexpression of x0 then
11848 while checking x0, x1 has already been checked. Thus
11849 it is valid and so as x. */
11850 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11851 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11852 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11855 /* If x0 is identical to a subexpression of x1 then x is
11856 valid iff the rest of x1 is valid. */
11857 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11858 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11859 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11861 get_last_value_validate (&XEXP (x1,
11862 x0 == XEXP (x1, 0) ? 1 : 0),
11863 insn, tick, replace);
11866 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11870 /* Don't bother with these. They shouldn't occur anyway. */
11871 else if (fmt[i] == 'E')
11875 /* If we haven't found a reason for it to be invalid, it is valid. */
11879 /* Get the last value assigned to X, if known. Some registers
11880 in the value may be replaced with (clobber (const_int 0)) if their value
11881 is known longer known reliably. */
11884 get_last_value (rtx x)
11886 unsigned int regno;
11889 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11890 then convert it to the desired mode. If this is a paradoxical SUBREG,
11891 we cannot predict what values the "extra" bits might have. */
11892 if (GET_CODE (x) == SUBREG
11893 && subreg_lowpart_p (x)
11894 && (GET_MODE_SIZE (GET_MODE (x))
11895 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11896 && (value = get_last_value (SUBREG_REG (x))) != 0)
11897 return gen_lowpart_for_combine (GET_MODE (x), value);
11899 if (GET_CODE (x) != REG)
11903 value = reg_last_set_value[regno];
11905 /* If we don't have a value, or if it isn't for this basic block and
11906 it's either a hard register, set more than once, or it's a live
11907 at the beginning of the function, return 0.
11909 Because if it's not live at the beginning of the function then the reg
11910 is always set before being used (is never used without being set).
11911 And, if it's set only once, and it's always set before use, then all
11912 uses must have the same last value, even if it's not from this basic
11916 || (reg_last_set_label[regno] != label_tick
11917 && (regno < FIRST_PSEUDO_REGISTER
11918 || REG_N_SETS (regno) != 1
11919 || (REGNO_REG_SET_P
11920 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11923 /* If the value was set in a later insn than the ones we are processing,
11924 we can't use it even if the register was only set once. */
11925 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11928 /* If the value has all its registers valid, return it. */
11929 if (get_last_value_validate (&value, reg_last_set[regno],
11930 reg_last_set_label[regno], 0))
11933 /* Otherwise, make a copy and replace any invalid register with
11934 (clobber (const_int 0)). If that fails for some reason, return 0. */
11936 value = copy_rtx (value);
11937 if (get_last_value_validate (&value, reg_last_set[regno],
11938 reg_last_set_label[regno], 1))
11944 /* Return nonzero if expression X refers to a REG or to memory
11945 that is set in an instruction more recent than FROM_CUID. */
11948 use_crosses_set_p (rtx x, int from_cuid)
11952 enum rtx_code code = GET_CODE (x);
11956 unsigned int regno = REGNO (x);
11957 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11958 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11960 #ifdef PUSH_ROUNDING
11961 /* Don't allow uses of the stack pointer to be moved,
11962 because we don't know whether the move crosses a push insn. */
11963 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11966 for (; regno < endreg; regno++)
11967 if (reg_last_set[regno]
11968 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11973 if (code == MEM && mem_last_set > from_cuid)
11976 fmt = GET_RTX_FORMAT (code);
11978 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11983 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11984 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11987 else if (fmt[i] == 'e'
11988 && use_crosses_set_p (XEXP (x, i), from_cuid))
11994 /* Define three variables used for communication between the following
11997 static unsigned int reg_dead_regno, reg_dead_endregno;
11998 static int reg_dead_flag;
12000 /* Function called via note_stores from reg_dead_at_p.
12002 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12003 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12006 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
12008 unsigned int regno, endregno;
12010 if (GET_CODE (dest) != REG)
12013 regno = REGNO (dest);
12014 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
12015 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
12017 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12018 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12021 /* Return nonzero if REG is known to be dead at INSN.
12023 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12024 referencing REG, it is dead. If we hit a SET referencing REG, it is
12025 live. Otherwise, see if it is live or dead at the start of the basic
12026 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12027 must be assumed to be always live. */
12030 reg_dead_at_p (rtx reg, rtx insn)
12035 /* Set variables for reg_dead_at_p_1. */
12036 reg_dead_regno = REGNO (reg);
12037 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12038 ? HARD_REGNO_NREGS (reg_dead_regno,
12044 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12045 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12047 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12048 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12052 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12053 beginning of function. */
12054 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12055 insn = prev_nonnote_insn (insn))
12057 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12059 return reg_dead_flag == 1 ? 1 : 0;
12061 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12065 /* Get the basic block that we were in. */
12067 block = ENTRY_BLOCK_PTR->next_bb;
12070 FOR_EACH_BB (block)
12071 if (insn == block->head)
12074 if (block == EXIT_BLOCK_PTR)
12078 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12079 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12085 /* Note hard registers in X that are used. This code is similar to
12086 that in flow.c, but much simpler since we don't care about pseudos. */
12089 mark_used_regs_combine (rtx x)
12091 RTX_CODE code = GET_CODE (x);
12092 unsigned int regno;
12105 case ADDR_DIFF_VEC:
12108 /* CC0 must die in the insn after it is set, so we don't need to take
12109 special note of it here. */
12115 /* If we are clobbering a MEM, mark any hard registers inside the
12116 address as used. */
12117 if (GET_CODE (XEXP (x, 0)) == MEM)
12118 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12123 /* A hard reg in a wide mode may really be multiple registers.
12124 If so, mark all of them just like the first. */
12125 if (regno < FIRST_PSEUDO_REGISTER)
12127 unsigned int endregno, r;
12129 /* None of this applies to the stack, frame or arg pointers. */
12130 if (regno == STACK_POINTER_REGNUM
12131 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12132 || regno == HARD_FRAME_POINTER_REGNUM
12134 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12135 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12137 || regno == FRAME_POINTER_REGNUM)
12140 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12141 for (r = regno; r < endregno; r++)
12142 SET_HARD_REG_BIT (newpat_used_regs, r);
12148 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12150 rtx testreg = SET_DEST (x);
12152 while (GET_CODE (testreg) == SUBREG
12153 || GET_CODE (testreg) == ZERO_EXTRACT
12154 || GET_CODE (testreg) == SIGN_EXTRACT
12155 || GET_CODE (testreg) == STRICT_LOW_PART)
12156 testreg = XEXP (testreg, 0);
12158 if (GET_CODE (testreg) == MEM)
12159 mark_used_regs_combine (XEXP (testreg, 0));
12161 mark_used_regs_combine (SET_SRC (x));
12169 /* Recursively scan the operands of this expression. */
12172 const char *fmt = GET_RTX_FORMAT (code);
12174 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12177 mark_used_regs_combine (XEXP (x, i));
12178 else if (fmt[i] == 'E')
12182 for (j = 0; j < XVECLEN (x, i); j++)
12183 mark_used_regs_combine (XVECEXP (x, i, j));
12189 /* Remove register number REGNO from the dead registers list of INSN.
12191 Return the note used to record the death, if there was one. */
12194 remove_death (unsigned int regno, rtx insn)
12196 rtx note = find_regno_note (insn, REG_DEAD, regno);
12200 REG_N_DEATHS (regno)--;
12201 remove_note (insn, note);
12207 /* For each register (hardware or pseudo) used within expression X, if its
12208 death is in an instruction with cuid between FROM_CUID (inclusive) and
12209 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12210 list headed by PNOTES.
12212 That said, don't move registers killed by maybe_kill_insn.
12214 This is done when X is being merged by combination into TO_INSN. These
12215 notes will then be distributed as needed. */
12218 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12223 enum rtx_code code = GET_CODE (x);
12227 unsigned int regno = REGNO (x);
12228 rtx where_dead = reg_last_death[regno];
12229 rtx before_dead, after_dead;
12231 /* Don't move the register if it gets killed in between from and to. */
12232 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12233 && ! reg_referenced_p (x, maybe_kill_insn))
12236 /* WHERE_DEAD could be a USE insn made by combine, so first we
12237 make sure that we have insns with valid INSN_CUID values. */
12238 before_dead = where_dead;
12239 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12240 before_dead = PREV_INSN (before_dead);
12242 after_dead = where_dead;
12243 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12244 after_dead = NEXT_INSN (after_dead);
12246 if (before_dead && after_dead
12247 && INSN_CUID (before_dead) >= from_cuid
12248 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12249 || (where_dead != after_dead
12250 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12252 rtx note = remove_death (regno, where_dead);
12254 /* It is possible for the call above to return 0. This can occur
12255 when reg_last_death points to I2 or I1 that we combined with.
12256 In that case make a new note.
12258 We must also check for the case where X is a hard register
12259 and NOTE is a death note for a range of hard registers
12260 including X. In that case, we must put REG_DEAD notes for
12261 the remaining registers in place of NOTE. */
12263 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12264 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12265 > GET_MODE_SIZE (GET_MODE (x))))
12267 unsigned int deadregno = REGNO (XEXP (note, 0));
12268 unsigned int deadend
12269 = (deadregno + HARD_REGNO_NREGS (deadregno,
12270 GET_MODE (XEXP (note, 0))));
12271 unsigned int ourend
12272 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12275 for (i = deadregno; i < deadend; i++)
12276 if (i < regno || i >= ourend)
12277 REG_NOTES (where_dead)
12278 = gen_rtx_EXPR_LIST (REG_DEAD,
12280 REG_NOTES (where_dead));
12283 /* If we didn't find any note, or if we found a REG_DEAD note that
12284 covers only part of the given reg, and we have a multi-reg hard
12285 register, then to be safe we must check for REG_DEAD notes
12286 for each register other than the first. They could have
12287 their own REG_DEAD notes lying around. */
12288 else if ((note == 0
12290 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12291 < GET_MODE_SIZE (GET_MODE (x)))))
12292 && regno < FIRST_PSEUDO_REGISTER
12293 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12295 unsigned int ourend
12296 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12297 unsigned int i, offset;
12301 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12305 for (i = regno + offset; i < ourend; i++)
12306 move_deaths (regno_reg_rtx[i],
12307 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12310 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12312 XEXP (note, 1) = *pnotes;
12316 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12318 REG_N_DEATHS (regno)++;
12324 else if (GET_CODE (x) == SET)
12326 rtx dest = SET_DEST (x);
12328 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12330 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12331 that accesses one word of a multi-word item, some
12332 piece of everything register in the expression is used by
12333 this insn, so remove any old death. */
12334 /* ??? So why do we test for equality of the sizes? */
12336 if (GET_CODE (dest) == ZERO_EXTRACT
12337 || GET_CODE (dest) == STRICT_LOW_PART
12338 || (GET_CODE (dest) == SUBREG
12339 && (((GET_MODE_SIZE (GET_MODE (dest))
12340 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12341 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12342 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12344 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12348 /* If this is some other SUBREG, we know it replaces the entire
12349 value, so use that as the destination. */
12350 if (GET_CODE (dest) == SUBREG)
12351 dest = SUBREG_REG (dest);
12353 /* If this is a MEM, adjust deaths of anything used in the address.
12354 For a REG (the only other possibility), the entire value is
12355 being replaced so the old value is not used in this insn. */
12357 if (GET_CODE (dest) == MEM)
12358 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12363 else if (GET_CODE (x) == CLOBBER)
12366 len = GET_RTX_LENGTH (code);
12367 fmt = GET_RTX_FORMAT (code);
12369 for (i = 0; i < len; i++)
12374 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12375 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12378 else if (fmt[i] == 'e')
12379 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12383 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12384 pattern of an insn. X must be a REG. */
12387 reg_bitfield_target_p (rtx x, rtx body)
12391 if (GET_CODE (body) == SET)
12393 rtx dest = SET_DEST (body);
12395 unsigned int regno, tregno, endregno, endtregno;
12397 if (GET_CODE (dest) == ZERO_EXTRACT)
12398 target = XEXP (dest, 0);
12399 else if (GET_CODE (dest) == STRICT_LOW_PART)
12400 target = SUBREG_REG (XEXP (dest, 0));
12404 if (GET_CODE (target) == SUBREG)
12405 target = SUBREG_REG (target);
12407 if (GET_CODE (target) != REG)
12410 tregno = REGNO (target), regno = REGNO (x);
12411 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12412 return target == x;
12414 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12415 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12417 return endregno > tregno && regno < endtregno;
12420 else if (GET_CODE (body) == PARALLEL)
12421 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12422 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12428 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12429 as appropriate. I3 and I2 are the insns resulting from the combination
12430 insns including FROM (I2 may be zero).
12432 Each note in the list is either ignored or placed on some insns, depending
12433 on the type of note. */
12436 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12438 rtx note, next_note;
12441 for (note = notes; note; note = next_note)
12443 rtx place = 0, place2 = 0;
12445 /* If this NOTE references a pseudo register, ensure it references
12446 the latest copy of that register. */
12447 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12448 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12449 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12451 next_note = XEXP (note, 1);
12452 switch (REG_NOTE_KIND (note))
12456 /* Doesn't matter much where we put this, as long as it's somewhere.
12457 It is preferable to keep these notes on branches, which is most
12458 likely to be i3. */
12462 case REG_VALUE_PROFILE:
12463 /* Just get rid of this note, as it is unused later anyway. */
12466 case REG_VTABLE_REF:
12467 /* ??? Should remain with *a particular* memory load. Given the
12468 nature of vtable data, the last insn seems relatively safe. */
12472 case REG_NON_LOCAL_GOTO:
12473 if (GET_CODE (i3) == JUMP_INSN)
12475 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12481 case REG_EH_REGION:
12482 /* These notes must remain with the call or trapping instruction. */
12483 if (GET_CODE (i3) == CALL_INSN)
12485 else if (i2 && GET_CODE (i2) == CALL_INSN)
12487 else if (flag_non_call_exceptions)
12489 if (may_trap_p (i3))
12491 else if (i2 && may_trap_p (i2))
12493 /* ??? Otherwise assume we've combined things such that we
12494 can now prove that the instructions can't trap. Drop the
12495 note in this case. */
12501 case REG_ALWAYS_RETURN:
12504 /* These notes must remain with the call. It should not be
12505 possible for both I2 and I3 to be a call. */
12506 if (GET_CODE (i3) == CALL_INSN)
12508 else if (i2 && GET_CODE (i2) == CALL_INSN)
12515 /* Any clobbers for i3 may still exist, and so we must process
12516 REG_UNUSED notes from that insn.
12518 Any clobbers from i2 or i1 can only exist if they were added by
12519 recog_for_combine. In that case, recog_for_combine created the
12520 necessary REG_UNUSED notes. Trying to keep any original
12521 REG_UNUSED notes from these insns can cause incorrect output
12522 if it is for the same register as the original i3 dest.
12523 In that case, we will notice that the register is set in i3,
12524 and then add a REG_UNUSED note for the destination of i3, which
12525 is wrong. However, it is possible to have REG_UNUSED notes from
12526 i2 or i1 for register which were both used and clobbered, so
12527 we keep notes from i2 or i1 if they will turn into REG_DEAD
12530 /* If this register is set or clobbered in I3, put the note there
12531 unless there is one already. */
12532 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12534 if (from_insn != i3)
12537 if (! (GET_CODE (XEXP (note, 0)) == REG
12538 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12539 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12542 /* Otherwise, if this register is used by I3, then this register
12543 now dies here, so we must put a REG_DEAD note here unless there
12545 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12546 && ! (GET_CODE (XEXP (note, 0)) == REG
12547 ? find_regno_note (i3, REG_DEAD,
12548 REGNO (XEXP (note, 0)))
12549 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12551 PUT_REG_NOTE_KIND (note, REG_DEAD);
12559 /* These notes say something about results of an insn. We can
12560 only support them if they used to be on I3 in which case they
12561 remain on I3. Otherwise they are ignored.
12563 If the note refers to an expression that is not a constant, we
12564 must also ignore the note since we cannot tell whether the
12565 equivalence is still true. It might be possible to do
12566 slightly better than this (we only have a problem if I2DEST
12567 or I1DEST is present in the expression), but it doesn't
12568 seem worth the trouble. */
12570 if (from_insn == i3
12571 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12576 case REG_NO_CONFLICT:
12577 /* These notes say something about how a register is used. They must
12578 be present on any use of the register in I2 or I3. */
12579 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12582 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12592 /* This can show up in several ways -- either directly in the
12593 pattern, or hidden off in the constant pool with (or without?)
12594 a REG_EQUAL note. */
12595 /* ??? Ignore the without-reg_equal-note problem for now. */
12596 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12597 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12598 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12599 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12603 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12604 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12605 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12606 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12614 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12615 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12616 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12618 if (JUMP_LABEL (place) != XEXP (note, 0))
12620 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12621 LABEL_NUSES (JUMP_LABEL (place))--;
12624 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12626 if (JUMP_LABEL (place2) != XEXP (note, 0))
12628 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12629 LABEL_NUSES (JUMP_LABEL (place2))--;
12635 /* This note says something about the value of a register prior
12636 to the execution of an insn. It is too much trouble to see
12637 if the note is still correct in all situations. It is better
12638 to simply delete it. */
12642 /* If the insn previously containing this note still exists,
12643 put it back where it was. Otherwise move it to the previous
12644 insn. Adjust the corresponding REG_LIBCALL note. */
12645 if (GET_CODE (from_insn) != NOTE)
12649 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12650 place = prev_real_insn (from_insn);
12652 XEXP (tem, 0) = place;
12653 /* If we're deleting the last remaining instruction of a
12654 libcall sequence, don't add the notes. */
12655 else if (XEXP (note, 0) == from_insn)
12661 /* This is handled similarly to REG_RETVAL. */
12662 if (GET_CODE (from_insn) != NOTE)
12666 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12667 place = next_real_insn (from_insn);
12669 XEXP (tem, 0) = place;
12670 /* If we're deleting the last remaining instruction of a
12671 libcall sequence, don't add the notes. */
12672 else if (XEXP (note, 0) == from_insn)
12678 /* If the register is used as an input in I3, it dies there.
12679 Similarly for I2, if it is nonzero and adjacent to I3.
12681 If the register is not used as an input in either I3 or I2
12682 and it is not one of the registers we were supposed to eliminate,
12683 there are two possibilities. We might have a non-adjacent I2
12684 or we might have somehow eliminated an additional register
12685 from a computation. For example, we might have had A & B where
12686 we discover that B will always be zero. In this case we will
12687 eliminate the reference to A.
12689 In both cases, we must search to see if we can find a previous
12690 use of A and put the death note there. */
12693 && GET_CODE (from_insn) == CALL_INSN
12694 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12696 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12698 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12699 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12704 basic_block bb = this_basic_block;
12706 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12708 if (! INSN_P (tem))
12710 if (tem == bb->head)
12715 /* If the register is being set at TEM, see if that is all
12716 TEM is doing. If so, delete TEM. Otherwise, make this
12717 into a REG_UNUSED note instead. */
12718 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12720 rtx set = single_set (tem);
12721 rtx inner_dest = 0;
12723 rtx cc0_setter = NULL_RTX;
12727 for (inner_dest = SET_DEST (set);
12728 (GET_CODE (inner_dest) == STRICT_LOW_PART
12729 || GET_CODE (inner_dest) == SUBREG
12730 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12731 inner_dest = XEXP (inner_dest, 0))
12734 /* Verify that it was the set, and not a clobber that
12735 modified the register.
12737 CC0 targets must be careful to maintain setter/user
12738 pairs. If we cannot delete the setter due to side
12739 effects, mark the user with an UNUSED note instead
12742 if (set != 0 && ! side_effects_p (SET_SRC (set))
12743 && rtx_equal_p (XEXP (note, 0), inner_dest)
12745 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12746 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12747 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12751 /* Move the notes and links of TEM elsewhere.
12752 This might delete other dead insns recursively.
12753 First set the pattern to something that won't use
12756 PATTERN (tem) = pc_rtx;
12758 distribute_notes (REG_NOTES (tem), tem, tem,
12760 distribute_links (LOG_LINKS (tem));
12762 PUT_CODE (tem, NOTE);
12763 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12764 NOTE_SOURCE_FILE (tem) = 0;
12767 /* Delete the setter too. */
12770 PATTERN (cc0_setter) = pc_rtx;
12772 distribute_notes (REG_NOTES (cc0_setter),
12773 cc0_setter, cc0_setter,
12775 distribute_links (LOG_LINKS (cc0_setter));
12777 PUT_CODE (cc0_setter, NOTE);
12778 NOTE_LINE_NUMBER (cc0_setter)
12779 = NOTE_INSN_DELETED;
12780 NOTE_SOURCE_FILE (cc0_setter) = 0;
12784 /* If the register is both set and used here, put the
12785 REG_DEAD note here, but place a REG_UNUSED note
12786 here too unless there already is one. */
12787 else if (reg_referenced_p (XEXP (note, 0),
12792 if (! find_regno_note (tem, REG_UNUSED,
12793 REGNO (XEXP (note, 0))))
12795 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12800 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12802 /* If there isn't already a REG_UNUSED note, put one
12804 if (! find_regno_note (tem, REG_UNUSED,
12805 REGNO (XEXP (note, 0))))
12810 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12811 || (GET_CODE (tem) == CALL_INSN
12812 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12816 /* If we are doing a 3->2 combination, and we have a
12817 register which formerly died in i3 and was not used
12818 by i2, which now no longer dies in i3 and is used in
12819 i2 but does not die in i2, and place is between i2
12820 and i3, then we may need to move a link from place to
12822 if (i2 && INSN_UID (place) <= max_uid_cuid
12823 && INSN_CUID (place) > INSN_CUID (i2)
12825 && INSN_CUID (from_insn) > INSN_CUID (i2)
12826 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12828 rtx links = LOG_LINKS (place);
12829 LOG_LINKS (place) = 0;
12830 distribute_links (links);
12835 if (tem == bb->head)
12839 /* We haven't found an insn for the death note and it
12840 is still a REG_DEAD note, but we have hit the beginning
12841 of the block. If the existing life info says the reg
12842 was dead, there's nothing left to do. Otherwise, we'll
12843 need to do a global life update after combine. */
12844 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12845 && REGNO_REG_SET_P (bb->global_live_at_start,
12846 REGNO (XEXP (note, 0))))
12847 SET_BIT (refresh_blocks, this_basic_block->index);
12850 /* If the register is set or already dead at PLACE, we needn't do
12851 anything with this note if it is still a REG_DEAD note.
12852 We can here if it is set at all, not if is it totally replace,
12853 which is what `dead_or_set_p' checks, so also check for it being
12856 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12858 unsigned int regno = REGNO (XEXP (note, 0));
12860 /* Similarly, if the instruction on which we want to place
12861 the note is a noop, we'll need do a global live update
12862 after we remove them in delete_noop_moves. */
12863 if (noop_move_p (place))
12864 SET_BIT (refresh_blocks, this_basic_block->index);
12866 if (dead_or_set_p (place, XEXP (note, 0))
12867 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12869 /* Unless the register previously died in PLACE, clear
12870 reg_last_death. [I no longer understand why this is
12872 if (reg_last_death[regno] != place)
12873 reg_last_death[regno] = 0;
12877 reg_last_death[regno] = place;
12879 /* If this is a death note for a hard reg that is occupying
12880 multiple registers, ensure that we are still using all
12881 parts of the object. If we find a piece of the object
12882 that is unused, we must arrange for an appropriate REG_DEAD
12883 note to be added for it. However, we can't just emit a USE
12884 and tag the note to it, since the register might actually
12885 be dead; so we recourse, and the recursive call then finds
12886 the previous insn that used this register. */
12888 if (place && regno < FIRST_PSEUDO_REGISTER
12889 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12891 unsigned int endregno
12892 = regno + HARD_REGNO_NREGS (regno,
12893 GET_MODE (XEXP (note, 0)));
12897 for (i = regno; i < endregno; i++)
12898 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12899 && ! find_regno_fusage (place, USE, i))
12900 || dead_or_set_regno_p (place, i))
12905 /* Put only REG_DEAD notes for pieces that are
12906 not already dead or set. */
12908 for (i = regno; i < endregno;
12909 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12911 rtx piece = regno_reg_rtx[i];
12912 basic_block bb = this_basic_block;
12914 if (! dead_or_set_p (place, piece)
12915 && ! reg_bitfield_target_p (piece,
12919 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12921 distribute_notes (new_note, place, place,
12924 else if (! refers_to_regno_p (i, i + 1,
12925 PATTERN (place), 0)
12926 && ! find_regno_fusage (place, USE, i))
12927 for (tem = PREV_INSN (place); ;
12928 tem = PREV_INSN (tem))
12930 if (! INSN_P (tem))
12932 if (tem == bb->head)
12934 SET_BIT (refresh_blocks,
12935 this_basic_block->index);
12940 if (dead_or_set_p (tem, piece)
12941 || reg_bitfield_target_p (piece,
12945 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12960 /* Any other notes should not be present at this point in the
12967 XEXP (note, 1) = REG_NOTES (place);
12968 REG_NOTES (place) = note;
12970 else if ((REG_NOTE_KIND (note) == REG_DEAD
12971 || REG_NOTE_KIND (note) == REG_UNUSED)
12972 && GET_CODE (XEXP (note, 0)) == REG)
12973 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12977 if ((REG_NOTE_KIND (note) == REG_DEAD
12978 || REG_NOTE_KIND (note) == REG_UNUSED)
12979 && GET_CODE (XEXP (note, 0)) == REG)
12980 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12982 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12983 REG_NOTE_KIND (note),
12985 REG_NOTES (place2));
12990 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12991 I3, I2, and I1 to new locations. This is also called in one case to
12992 add a link pointing at I3 when I3's destination is changed. */
12995 distribute_links (rtx links)
12997 rtx link, next_link;
12999 for (link = links; link; link = next_link)
13005 next_link = XEXP (link, 1);
13007 /* If the insn that this link points to is a NOTE or isn't a single
13008 set, ignore it. In the latter case, it isn't clear what we
13009 can do other than ignore the link, since we can't tell which
13010 register it was for. Such links wouldn't be used by combine
13013 It is not possible for the destination of the target of the link to
13014 have been changed by combine. The only potential of this is if we
13015 replace I3, I2, and I1 by I3 and I2. But in that case the
13016 destination of I2 also remains unchanged. */
13018 if (GET_CODE (XEXP (link, 0)) == NOTE
13019 || (set = single_set (XEXP (link, 0))) == 0)
13022 reg = SET_DEST (set);
13023 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13024 || GET_CODE (reg) == SIGN_EXTRACT
13025 || GET_CODE (reg) == STRICT_LOW_PART)
13026 reg = XEXP (reg, 0);
13028 /* A LOG_LINK is defined as being placed on the first insn that uses
13029 a register and points to the insn that sets the register. Start
13030 searching at the next insn after the target of the link and stop
13031 when we reach a set of the register or the end of the basic block.
13033 Note that this correctly handles the link that used to point from
13034 I3 to I2. Also note that not much searching is typically done here
13035 since most links don't point very far away. */
13037 for (insn = NEXT_INSN (XEXP (link, 0));
13038 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13039 || this_basic_block->next_bb->head != insn));
13040 insn = NEXT_INSN (insn))
13041 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13043 if (reg_referenced_p (reg, PATTERN (insn)))
13047 else if (GET_CODE (insn) == CALL_INSN
13048 && find_reg_fusage (insn, USE, reg))
13054 /* If we found a place to put the link, place it there unless there
13055 is already a link to the same insn as LINK at that point. */
13061 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13062 if (XEXP (link2, 0) == XEXP (link, 0))
13067 XEXP (link, 1) = LOG_LINKS (place);
13068 LOG_LINKS (place) = link;
13070 /* Set added_links_insn to the earliest insn we added a
13072 if (added_links_insn == 0
13073 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13074 added_links_insn = place;
13080 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13083 insn_cuid (rtx insn)
13085 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13086 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13087 insn = NEXT_INSN (insn);
13089 if (INSN_UID (insn) > max_uid_cuid)
13092 return INSN_CUID (insn);
13096 dump_combine_stats (FILE *file)
13100 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13101 combine_attempts, combine_merges, combine_extras, combine_successes);
13105 dump_combine_total_stats (FILE *file)
13109 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13110 total_attempts, total_merges, total_extras, total_successes);