1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
126 /* Sometimes combine tries to replace the right hand side of an insn
127 with the value of a REG_EQUAL note. This is the insn that has been
128 so modified, or null if none. */
130 static rtx replaced_rhs_insn;
132 /* Vector mapping INSN_UIDs to cuids.
133 The cuids are like uids but increase monotonically always.
134 Combine always uses cuids so that it can compare them.
135 But actually renumbering the uids, which we used to do,
136 proves to be a bad idea because it makes it hard to compare
137 the dumps produced by earlier passes with those from later passes. */
139 static int *uid_cuid;
140 static int max_uid_cuid;
142 /* Get the cuid of an insn. */
144 #define INSN_CUID(INSN) \
145 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
147 /* Maximum register number, which is the size of the tables below. */
149 static unsigned int combine_max_regno;
152 /* Record last point of death of (hard or pseudo) register n. */
155 /* Record last point of modification of (hard or pseudo) register n. */
158 /* The next group of fields allows the recording of the last value assigned
159 to (hard or pseudo) register n. We use this information to see if an
160 operation being processed is redundant given a prior operation performed
161 on the register. For example, an `and' with a constant is redundant if
162 all the zero bits are already known to be turned off.
164 We use an approach similar to that used by cse, but change it in the
167 (1) We do not want to reinitialize at each label.
168 (2) It is useful, but not critical, to know the actual value assigned
169 to a register. Often just its form is helpful.
171 Therefore, we maintain the following fields:
173 last_set_value the last value assigned
174 last_set_label records the value of label_tick when the
175 register was assigned
176 last_set_table_tick records the value of label_tick when a
177 value using the register is assigned
178 last_set_invalid set to nonzero when it is not valid
179 to use the value of this register in some
182 To understand the usage of these tables, it is important to understand
183 the distinction between the value in last_set_value being valid and
184 the register being validly contained in some other expression in the
187 (The next two parameters are out of date).
189 reg_stat[i].last_set_value is valid if it is nonzero, and either
190 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
192 Register I may validly appear in any expression returned for the value
193 of another register if reg_n_sets[i] is 1. It may also appear in the
194 value for register J if reg_stat[j].last_set_invalid is zero, or
195 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
197 If an expression is found in the table containing a register which may
198 not validly appear in an expression, the register is replaced by
199 something that won't match, (clobber (const_int 0)). */
201 /* Record last value assigned to (hard or pseudo) register n. */
205 /* Record the value of label_tick when an expression involving register n
206 is placed in last_set_value. */
208 int last_set_table_tick;
210 /* Record the value of label_tick when the value for register n is placed in
215 /* These fields are maintained in parallel with last_set_value and are
216 used to store the mode in which the register was last set, the bits
217 that were known to be zero when it was last set, and the number of
218 sign bits copies it was known to have when it was last set. */
220 unsigned HOST_WIDE_INT last_set_nonzero_bits;
221 char last_set_sign_bit_copies;
222 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
224 /* Set nonzero if references to register n in expressions should not be
225 used. last_set_invalid is set nonzero when this register is being
226 assigned to and last_set_table_tick == label_tick. */
228 char last_set_invalid;
230 /* Some registers that are set more than once and used in more than one
231 basic block are nevertheless always set in similar ways. For example,
232 a QImode register may be loaded from memory in two places on a machine
233 where byte loads zero extend.
235 We record in the following fields if a register has some leading bits
236 that are always equal to the sign bit, and what we know about the
237 nonzero bits of a register, specifically which bits are known to be
240 If an entry is zero, it means that we don't know anything special. */
242 unsigned char sign_bit_copies;
244 unsigned HOST_WIDE_INT nonzero_bits;
246 /* Record the value of the label_tick when the last truncation
247 happened. The field truncated_to_mode is only valid if
248 truncation_label == label_tick. */
250 int truncation_label;
252 /* Record the last truncation seen for this register. If truncation
253 is not a nop to this mode we might be able to save an explicit
254 truncation if we know that value already contains a truncated
257 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
260 static struct reg_stat *reg_stat;
262 /* Record the cuid of the last insn that invalidated memory
263 (anything that writes memory, and subroutine calls, but not pushes). */
265 static int mem_last_set;
267 /* Record the cuid of the last CALL_INSN
268 so we can tell whether a potential combination crosses any calls. */
270 static int last_call_cuid;
272 /* When `subst' is called, this is the insn that is being modified
273 (by combining in a previous insn). The PATTERN of this insn
274 is still the old pattern partially modified and it should not be
275 looked at, but this may be used to examine the successors of the insn
276 to judge whether a simplification is valid. */
278 static rtx subst_insn;
280 /* This is the lowest CUID that `subst' is currently dealing with.
281 get_last_value will not return a value if the register was set at or
282 after this CUID. If not for this mechanism, we could get confused if
283 I2 or I1 in try_combine were an insn that used the old value of a register
284 to obtain a new value. In that case, we might erroneously get the
285 new value of the register when we wanted the old one. */
287 static int subst_low_cuid;
289 /* This contains any hard registers that are used in newpat; reg_dead_at_p
290 must consider all these registers to be always live. */
292 static HARD_REG_SET newpat_used_regs;
294 /* This is an insn to which a LOG_LINKS entry has been added. If this
295 insn is the earlier than I2 or I3, combine should rescan starting at
298 static rtx added_links_insn;
300 /* Basic block in which we are performing combines. */
301 static basic_block this_basic_block;
303 /* A bitmap indicating which blocks had registers go dead at entry.
304 After combine, we'll need to re-do global life analysis with
305 those blocks as starting points. */
306 static sbitmap refresh_blocks;
308 /* The following array records the insn_rtx_cost for every insn
309 in the instruction stream. */
311 static int *uid_insn_cost;
313 /* Length of the currently allocated uid_insn_cost array. */
315 static int last_insn_cost;
317 /* Incremented for each label. */
319 static int label_tick;
321 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
322 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
324 static enum machine_mode nonzero_bits_mode;
326 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
327 be safely used. It is zero while computing them and after combine has
328 completed. This former test prevents propagating values based on
329 previously set values, which can be incorrect if a variable is modified
332 static int nonzero_sign_valid;
335 /* Record one modification to rtl structure
336 to be undone by storing old_contents into *where. */
341 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
342 union { rtx r; int i; enum machine_mode m; } old_contents;
343 union { rtx *r; int *i; } where;
346 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
347 num_undo says how many are currently recorded.
349 other_insn is nonzero if we have modified some other insn in the process
350 of working on subst_insn. It must be verified too. */
359 static struct undobuf undobuf;
361 /* Number of times the pseudo being substituted for
362 was found and replaced. */
364 static int n_occurrences;
366 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
368 unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *);
370 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
372 unsigned int, unsigned int *);
373 static void do_SUBST (rtx *, rtx);
374 static void do_SUBST_INT (int *, int);
375 static void init_reg_last (void);
376 static void setup_incoming_promotions (void);
377 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
378 static int cant_combine_insn_p (rtx);
379 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
380 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
381 static int contains_muldiv (rtx);
382 static rtx try_combine (rtx, rtx, rtx, int *);
383 static void undo_all (void);
384 static void undo_commit (void);
385 static rtx *find_split_point (rtx *, rtx);
386 static rtx subst (rtx, rtx, rtx, int, int);
387 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
388 static rtx simplify_if_then_else (rtx);
389 static rtx simplify_set (rtx);
390 static rtx simplify_logical (rtx);
391 static rtx expand_compound_operation (rtx);
392 static rtx expand_field_assignment (rtx);
393 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
394 rtx, unsigned HOST_WIDE_INT, int, int, int);
395 static rtx extract_left_shift (rtx, int);
396 static rtx make_compound_operation (rtx, enum rtx_code);
397 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
398 unsigned HOST_WIDE_INT *);
399 static rtx canon_reg_for_combine (rtx, rtx);
400 static rtx force_to_mode (rtx, enum machine_mode,
401 unsigned HOST_WIDE_INT, int);
402 static rtx if_then_else_cond (rtx, rtx *, rtx *);
403 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
404 static int rtx_equal_for_field_assignment_p (rtx, rtx);
405 static rtx make_field_assignment (rtx);
406 static rtx apply_distributive_law (rtx);
407 static rtx distribute_and_simplify_rtx (rtx, int);
408 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
409 unsigned HOST_WIDE_INT);
410 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
411 unsigned HOST_WIDE_INT);
412 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
413 HOST_WIDE_INT, enum machine_mode, int *);
414 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
415 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
417 static int recog_for_combine (rtx *, rtx, rtx *);
418 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
419 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
420 static void update_table_tick (rtx);
421 static void record_value_for_reg (rtx, rtx, rtx);
422 static void check_conversions (rtx, rtx);
423 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
424 static void record_dead_and_set_regs (rtx);
425 static int get_last_value_validate (rtx *, rtx, int, int);
426 static rtx get_last_value (rtx);
427 static int use_crosses_set_p (rtx, int);
428 static void reg_dead_at_p_1 (rtx, rtx, void *);
429 static int reg_dead_at_p (rtx, rtx);
430 static void move_deaths (rtx, rtx, int, rtx, rtx *);
431 static int reg_bitfield_target_p (rtx, rtx);
432 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
433 static void distribute_links (rtx);
434 static void mark_used_regs_combine (rtx);
435 static int insn_cuid (rtx);
436 static void record_promoted_value (rtx, rtx);
437 static int unmentioned_reg_p_1 (rtx *, void *);
438 static bool unmentioned_reg_p (rtx, rtx);
439 static void record_truncated_value (rtx);
440 static bool reg_truncated_to_mode (enum machine_mode, rtx);
441 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
444 /* It is not safe to use ordinary gen_lowpart in combine.
445 See comments in gen_lowpart_for_combine. */
446 #undef RTL_HOOKS_GEN_LOWPART
447 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
449 /* Our implementation of gen_lowpart never emits a new pseudo. */
450 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
451 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
453 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
454 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
456 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
457 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
459 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
460 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
462 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
465 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
466 insn. The substitution can be undone by undo_all. If INTO is already
467 set to NEWVAL, do not record this change. Because computing NEWVAL might
468 also call SUBST, we have to compute it before we put anything into
472 do_SUBST (rtx *into, rtx newval)
477 if (oldval == newval)
480 /* We'd like to catch as many invalid transformations here as
481 possible. Unfortunately, there are way too many mode changes
482 that are perfectly valid, so we'd waste too much effort for
483 little gain doing the checks here. Focus on catching invalid
484 transformations involving integer constants. */
485 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
486 && GET_CODE (newval) == CONST_INT)
488 /* Sanity check that we're replacing oldval with a CONST_INT
489 that is a valid sign-extension for the original mode. */
490 gcc_assert (INTVAL (newval)
491 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
493 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
494 CONST_INT is not valid, because after the replacement, the
495 original mode would be gone. Unfortunately, we can't tell
496 when do_SUBST is called to replace the operand thereof, so we
497 perform this test on oldval instead, checking whether an
498 invalid replacement took place before we got here. */
499 gcc_assert (!(GET_CODE (oldval) == SUBREG
500 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
501 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
502 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
506 buf = undobuf.frees, undobuf.frees = buf->next;
508 buf = XNEW (struct undo);
510 buf->kind = UNDO_RTX;
512 buf->old_contents.r = oldval;
515 buf->next = undobuf.undos, undobuf.undos = buf;
518 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
520 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
521 for the value of a HOST_WIDE_INT value (including CONST_INT) is
525 do_SUBST_INT (int *into, int newval)
530 if (oldval == newval)
534 buf = undobuf.frees, undobuf.frees = buf->next;
536 buf = XNEW (struct undo);
538 buf->kind = UNDO_INT;
540 buf->old_contents.i = oldval;
543 buf->next = undobuf.undos, undobuf.undos = buf;
546 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
548 /* Similar to SUBST, but just substitute the mode. This is used when
549 changing the mode of a pseudo-register, so that any other
550 references to the entry in the regno_reg_rtx array will change as
554 do_SUBST_MODE (rtx *into, enum machine_mode newval)
557 enum machine_mode oldval = GET_MODE (*into);
559 if (oldval == newval)
563 buf = undobuf.frees, undobuf.frees = buf->next;
565 buf = XNEW (struct undo);
567 buf->kind = UNDO_MODE;
569 buf->old_contents.m = oldval;
570 PUT_MODE (*into, newval);
572 buf->next = undobuf.undos, undobuf.undos = buf;
575 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
577 /* Subroutine of try_combine. Determine whether the combine replacement
578 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
579 that the original instruction sequence I1, I2 and I3. Note that I1
580 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
581 costs of all instructions can be estimated, and the replacements are
582 more expensive than the original sequence. */
585 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
587 int i1_cost, i2_cost, i3_cost;
588 int new_i2_cost, new_i3_cost;
589 int old_cost, new_cost;
591 /* Lookup the original insn_rtx_costs. */
592 i2_cost = INSN_UID (i2) <= last_insn_cost
593 ? uid_insn_cost[INSN_UID (i2)] : 0;
594 i3_cost = INSN_UID (i3) <= last_insn_cost
595 ? uid_insn_cost[INSN_UID (i3)] : 0;
599 i1_cost = INSN_UID (i1) <= last_insn_cost
600 ? uid_insn_cost[INSN_UID (i1)] : 0;
601 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
602 ? i1_cost + i2_cost + i3_cost : 0;
606 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
610 /* Calculate the replacement insn_rtx_costs. */
611 new_i3_cost = insn_rtx_cost (newpat);
614 new_i2_cost = insn_rtx_cost (newi2pat);
615 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
616 ? new_i2_cost + new_i3_cost : 0;
620 new_cost = new_i3_cost;
624 if (undobuf.other_insn)
626 int old_other_cost, new_other_cost;
628 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
629 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
630 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
631 if (old_other_cost > 0 && new_other_cost > 0)
633 old_cost += old_other_cost;
634 new_cost += new_other_cost;
640 /* Disallow this recombination if both new_cost and old_cost are
641 greater than zero, and new_cost is greater than old cost. */
643 && new_cost > old_cost)
650 "rejecting combination of insns %d, %d and %d\n",
651 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
652 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
653 i1_cost, i2_cost, i3_cost, old_cost);
658 "rejecting combination of insns %d and %d\n",
659 INSN_UID (i2), INSN_UID (i3));
660 fprintf (dump_file, "original costs %d + %d = %d\n",
661 i2_cost, i3_cost, old_cost);
666 fprintf (dump_file, "replacement costs %d + %d = %d\n",
667 new_i2_cost, new_i3_cost, new_cost);
670 fprintf (dump_file, "replacement cost %d\n", new_cost);
676 /* Update the uid_insn_cost array with the replacement costs. */
677 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
678 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
680 uid_insn_cost[INSN_UID (i1)] = 0;
685 /* Main entry point for combiner. F is the first insn of the function.
686 NREGS is the first unused pseudo-reg number.
688 Return nonzero if the combiner has turned an indirect jump
689 instruction into a direct jump. */
691 combine_instructions (rtx f, unsigned int nregs)
699 rtx links, nextlinks;
700 sbitmap_iterator sbi;
702 int new_direct_jump_p = 0;
704 combine_attempts = 0;
707 combine_successes = 0;
709 combine_max_regno = nregs;
711 rtl_hooks = combine_rtl_hooks;
713 reg_stat = XCNEWVEC (struct reg_stat, nregs);
715 init_recog_no_volatile ();
717 /* Compute maximum uid value so uid_cuid can be allocated. */
719 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
720 if (INSN_UID (insn) > i)
723 uid_cuid = XNEWVEC (int, i + 1);
726 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
728 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
729 problems when, for example, we have j <<= 1 in a loop. */
731 nonzero_sign_valid = 0;
733 /* Compute the mapping from uids to cuids.
734 Cuids are numbers assigned to insns, like uids,
735 except that cuids increase monotonically through the code.
737 Scan all SETs and see if we can deduce anything about what
738 bits are known to be zero for some registers and how many copies
739 of the sign bit are known to exist for those registers.
741 Also set any known values so that we can use it while searching
742 for what bits are known to be set. */
746 setup_incoming_promotions ();
748 refresh_blocks = sbitmap_alloc (last_basic_block);
749 sbitmap_zero (refresh_blocks);
751 /* Allocate array of current insn_rtx_costs. */
752 uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
753 last_insn_cost = max_uid_cuid;
755 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
757 uid_cuid[INSN_UID (insn)] = ++i;
763 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
765 record_dead_and_set_regs (insn);
768 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
769 if (REG_NOTE_KIND (links) == REG_INC)
770 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
774 /* Record the current insn_rtx_cost of this instruction. */
775 if (NONJUMP_INSN_P (insn))
776 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
778 fprintf(dump_file, "insn_cost %d: %d\n",
779 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
786 nonzero_sign_valid = 1;
788 /* Now scan all the insns in forward order. */
794 setup_incoming_promotions ();
796 FOR_EACH_BB (this_basic_block)
798 for (insn = BB_HEAD (this_basic_block);
799 insn != NEXT_INSN (BB_END (this_basic_block));
800 insn = next ? next : NEXT_INSN (insn))
807 else if (INSN_P (insn))
809 /* See if we know about function return values before this
810 insn based upon SUBREG flags. */
811 check_conversions (insn, PATTERN (insn));
813 /* Try this insn with each insn it links back to. */
815 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
816 if ((next = try_combine (insn, XEXP (links, 0),
817 NULL_RTX, &new_direct_jump_p)) != 0)
820 /* Try each sequence of three linked insns ending with this one. */
822 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
824 rtx link = XEXP (links, 0);
826 /* If the linked insn has been replaced by a note, then there
827 is no point in pursuing this chain any further. */
831 for (nextlinks = LOG_LINKS (link);
833 nextlinks = XEXP (nextlinks, 1))
834 if ((next = try_combine (insn, link,
836 &new_direct_jump_p)) != 0)
841 /* Try to combine a jump insn that uses CC0
842 with a preceding insn that sets CC0, and maybe with its
843 logical predecessor as well.
844 This is how we make decrement-and-branch insns.
845 We need this special code because data flow connections
846 via CC0 do not get entered in LOG_LINKS. */
849 && (prev = prev_nonnote_insn (insn)) != 0
850 && NONJUMP_INSN_P (prev)
851 && sets_cc0_p (PATTERN (prev)))
853 if ((next = try_combine (insn, prev,
854 NULL_RTX, &new_direct_jump_p)) != 0)
857 for (nextlinks = LOG_LINKS (prev); nextlinks;
858 nextlinks = XEXP (nextlinks, 1))
859 if ((next = try_combine (insn, prev,
861 &new_direct_jump_p)) != 0)
865 /* Do the same for an insn that explicitly references CC0. */
866 if (NONJUMP_INSN_P (insn)
867 && (prev = prev_nonnote_insn (insn)) != 0
868 && NONJUMP_INSN_P (prev)
869 && sets_cc0_p (PATTERN (prev))
870 && GET_CODE (PATTERN (insn)) == SET
871 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
873 if ((next = try_combine (insn, prev,
874 NULL_RTX, &new_direct_jump_p)) != 0)
877 for (nextlinks = LOG_LINKS (prev); nextlinks;
878 nextlinks = XEXP (nextlinks, 1))
879 if ((next = try_combine (insn, prev,
881 &new_direct_jump_p)) != 0)
885 /* Finally, see if any of the insns that this insn links to
886 explicitly references CC0. If so, try this insn, that insn,
887 and its predecessor if it sets CC0. */
888 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
889 if (NONJUMP_INSN_P (XEXP (links, 0))
890 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
891 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
892 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
893 && NONJUMP_INSN_P (prev)
894 && sets_cc0_p (PATTERN (prev))
895 && (next = try_combine (insn, XEXP (links, 0),
896 prev, &new_direct_jump_p)) != 0)
900 /* Try combining an insn with two different insns whose results it
902 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
903 for (nextlinks = XEXP (links, 1); nextlinks;
904 nextlinks = XEXP (nextlinks, 1))
905 if ((next = try_combine (insn, XEXP (links, 0),
907 &new_direct_jump_p)) != 0)
910 /* Try this insn with each REG_EQUAL note it links back to. */
911 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
914 rtx temp = XEXP (links, 0);
915 if ((set = single_set (temp)) != 0
916 && (note = find_reg_equal_equiv_note (temp)) != 0
917 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
918 /* Avoid using a register that may already been marked
919 dead by an earlier instruction. */
920 && ! unmentioned_reg_p (note, SET_SRC (set))
921 && (GET_MODE (note) == VOIDmode
922 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
923 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
925 /* Temporarily replace the set's source with the
926 contents of the REG_EQUAL note. The insn will
927 be deleted or recognized by try_combine. */
928 rtx orig = SET_SRC (set);
929 SET_SRC (set) = note;
930 replaced_rhs_insn = temp;
931 next = try_combine (insn, temp, NULL_RTX,
933 replaced_rhs_insn = NULL;
936 SET_SRC (set) = orig;
941 record_dead_and_set_regs (insn);
950 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
951 BASIC_BLOCK (j)->flags |= BB_DIRTY;
952 new_direct_jump_p |= purge_all_dead_edges ();
953 delete_noop_moves ();
955 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
956 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
957 | PROP_KILL_DEAD_CODE);
960 sbitmap_free (refresh_blocks);
961 free (uid_insn_cost);
966 struct undo *undo, *next;
967 for (undo = undobuf.frees; undo; undo = next)
975 total_attempts += combine_attempts;
976 total_merges += combine_merges;
977 total_extras += combine_extras;
978 total_successes += combine_successes;
980 nonzero_sign_valid = 0;
981 rtl_hooks = general_rtl_hooks;
983 /* Make recognizer allow volatile MEMs again. */
986 return new_direct_jump_p;
989 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
995 for (i = 0; i < combine_max_regno; i++)
996 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
999 /* Set up any promoted values for incoming argument registers. */
1002 setup_incoming_promotions (void)
1006 enum machine_mode mode;
1008 rtx first = get_insns ();
1010 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1012 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1013 /* Check whether this register can hold an incoming pointer
1014 argument. FUNCTION_ARG_REGNO_P tests outgoing register
1015 numbers, so translate if necessary due to register windows. */
1016 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1017 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1019 record_value_for_reg
1020 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1023 gen_rtx_CLOBBER (mode, const0_rtx)));
1028 /* Called via note_stores. If X is a pseudo that is narrower than
1029 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1031 If we are setting only a portion of X and we can't figure out what
1032 portion, assume all bits will be used since we don't know what will
1035 Similarly, set how many bits of X are known to be copies of the sign bit
1036 at all locations in the function. This is the smallest number implied
1040 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1041 void *data ATTRIBUTE_UNUSED)
1046 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1047 /* If this register is undefined at the start of the file, we can't
1048 say what its contents were. */
1049 && ! REGNO_REG_SET_P
1050 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1051 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1053 if (set == 0 || GET_CODE (set) == CLOBBER)
1055 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1056 reg_stat[REGNO (x)].sign_bit_copies = 1;
1060 /* If this is a complex assignment, see if we can convert it into a
1061 simple assignment. */
1062 set = expand_field_assignment (set);
1064 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1065 set what we know about X. */
1067 if (SET_DEST (set) == x
1068 || (GET_CODE (SET_DEST (set)) == SUBREG
1069 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1070 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1071 && SUBREG_REG (SET_DEST (set)) == x))
1073 rtx src = SET_SRC (set);
1075 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1076 /* If X is narrower than a word and SRC is a non-negative
1077 constant that would appear negative in the mode of X,
1078 sign-extend it for use in reg_stat[].nonzero_bits because some
1079 machines (maybe most) will actually do the sign-extension
1080 and this is the conservative approach.
1082 ??? For 2.5, try to tighten up the MD files in this regard
1083 instead of this kludge. */
1085 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1086 && GET_CODE (src) == CONST_INT
1088 && 0 != (INTVAL (src)
1089 & ((HOST_WIDE_INT) 1
1090 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1091 src = GEN_INT (INTVAL (src)
1092 | ((HOST_WIDE_INT) (-1)
1093 << GET_MODE_BITSIZE (GET_MODE (x))));
1096 /* Don't call nonzero_bits if it cannot change anything. */
1097 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1098 reg_stat[REGNO (x)].nonzero_bits
1099 |= nonzero_bits (src, nonzero_bits_mode);
1100 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1101 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1102 || reg_stat[REGNO (x)].sign_bit_copies > num)
1103 reg_stat[REGNO (x)].sign_bit_copies = num;
1107 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1108 reg_stat[REGNO (x)].sign_bit_copies = 1;
1113 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1114 insns that were previously combined into I3 or that will be combined
1115 into the merger of INSN and I3.
1117 Return 0 if the combination is not allowed for any reason.
1119 If the combination is allowed, *PDEST will be set to the single
1120 destination of INSN and *PSRC to the single source, and this function
1124 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1125 rtx *pdest, rtx *psrc)
1128 rtx set = 0, src, dest;
1133 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1134 && next_active_insn (succ) == i3)
1135 : next_active_insn (insn) == i3);
1137 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1138 or a PARALLEL consisting of such a SET and CLOBBERs.
1140 If INSN has CLOBBER parallel parts, ignore them for our processing.
1141 By definition, these happen during the execution of the insn. When it
1142 is merged with another insn, all bets are off. If they are, in fact,
1143 needed and aren't also supplied in I3, they may be added by
1144 recog_for_combine. Otherwise, it won't match.
1146 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1149 Get the source and destination of INSN. If more than one, can't
1152 if (GET_CODE (PATTERN (insn)) == SET)
1153 set = PATTERN (insn);
1154 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1155 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1157 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1159 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1162 switch (GET_CODE (elt))
1164 /* This is important to combine floating point insns
1165 for the SH4 port. */
1167 /* Combining an isolated USE doesn't make sense.
1168 We depend here on combinable_i3pat to reject them. */
1169 /* The code below this loop only verifies that the inputs of
1170 the SET in INSN do not change. We call reg_set_between_p
1171 to verify that the REG in the USE does not change between
1173 If the USE in INSN was for a pseudo register, the matching
1174 insn pattern will likely match any register; combining this
1175 with any other USE would only be safe if we knew that the
1176 used registers have identical values, or if there was
1177 something to tell them apart, e.g. different modes. For
1178 now, we forgo such complicated tests and simply disallow
1179 combining of USES of pseudo registers with any other USE. */
1180 if (REG_P (XEXP (elt, 0))
1181 && GET_CODE (PATTERN (i3)) == PARALLEL)
1183 rtx i3pat = PATTERN (i3);
1184 int i = XVECLEN (i3pat, 0) - 1;
1185 unsigned int regno = REGNO (XEXP (elt, 0));
1189 rtx i3elt = XVECEXP (i3pat, 0, i);
1191 if (GET_CODE (i3elt) == USE
1192 && REG_P (XEXP (i3elt, 0))
1193 && (REGNO (XEXP (i3elt, 0)) == regno
1194 ? reg_set_between_p (XEXP (elt, 0),
1195 PREV_INSN (insn), i3)
1196 : regno >= FIRST_PSEUDO_REGISTER))
1203 /* We can ignore CLOBBERs. */
1208 /* Ignore SETs whose result isn't used but not those that
1209 have side-effects. */
1210 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1211 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1212 || INTVAL (XEXP (note, 0)) <= 0)
1213 && ! side_effects_p (elt))
1216 /* If we have already found a SET, this is a second one and
1217 so we cannot combine with this insn. */
1225 /* Anything else means we can't combine. */
1231 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1232 so don't do anything with it. */
1233 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1242 set = expand_field_assignment (set);
1243 src = SET_SRC (set), dest = SET_DEST (set);
1245 /* Don't eliminate a store in the stack pointer. */
1246 if (dest == stack_pointer_rtx
1247 /* Don't combine with an insn that sets a register to itself if it has
1248 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1249 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1250 /* Can't merge an ASM_OPERANDS. */
1251 || GET_CODE (src) == ASM_OPERANDS
1252 /* Can't merge a function call. */
1253 || GET_CODE (src) == CALL
1254 /* Don't eliminate a function call argument. */
1256 && (find_reg_fusage (i3, USE, dest)
1258 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1259 && global_regs[REGNO (dest)])))
1260 /* Don't substitute into an incremented register. */
1261 || FIND_REG_INC_NOTE (i3, dest)
1262 || (succ && FIND_REG_INC_NOTE (succ, dest))
1263 /* Don't substitute into a non-local goto, this confuses CFG. */
1264 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1266 /* Don't combine the end of a libcall into anything. */
1267 /* ??? This gives worse code, and appears to be unnecessary, since no
1268 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1269 use REG_RETVAL notes for noconflict blocks, but other code here
1270 makes sure that those insns don't disappear. */
1271 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1273 /* Make sure that DEST is not used after SUCC but before I3. */
1274 || (succ && ! all_adjacent
1275 && reg_used_between_p (dest, succ, i3))
1276 /* Make sure that the value that is to be substituted for the register
1277 does not use any registers whose values alter in between. However,
1278 If the insns are adjacent, a use can't cross a set even though we
1279 think it might (this can happen for a sequence of insns each setting
1280 the same destination; last_set of that register might point to
1281 a NOTE). If INSN has a REG_EQUIV note, the register is always
1282 equivalent to the memory so the substitution is valid even if there
1283 are intervening stores. Also, don't move a volatile asm or
1284 UNSPEC_VOLATILE across any other insns. */
1287 || ! find_reg_note (insn, REG_EQUIV, src))
1288 && use_crosses_set_p (src, INSN_CUID (insn)))
1289 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1290 || GET_CODE (src) == UNSPEC_VOLATILE))
1291 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1292 better register allocation by not doing the combine. */
1293 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1294 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1295 /* Don't combine across a CALL_INSN, because that would possibly
1296 change whether the life span of some REGs crosses calls or not,
1297 and it is a pain to update that information.
1298 Exception: if source is a constant, moving it later can't hurt.
1299 Accept that special case, because it helps -fforce-addr a lot. */
1300 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1303 /* DEST must either be a REG or CC0. */
1306 /* If register alignment is being enforced for multi-word items in all
1307 cases except for parameters, it is possible to have a register copy
1308 insn referencing a hard register that is not allowed to contain the
1309 mode being copied and which would not be valid as an operand of most
1310 insns. Eliminate this problem by not combining with such an insn.
1312 Also, on some machines we don't want to extend the life of a hard
1316 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1317 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1318 /* Don't extend the life of a hard register unless it is
1319 user variable (if we have few registers) or it can't
1320 fit into the desired register (meaning something special
1322 Also avoid substituting a return register into I3, because
1323 reload can't handle a conflict with constraints of other
1325 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1326 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1329 else if (GET_CODE (dest) != CC0)
1333 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1334 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1335 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1337 /* Don't substitute for a register intended as a clobberable
1339 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1340 if (rtx_equal_p (reg, dest))
1343 /* If the clobber represents an earlyclobber operand, we must not
1344 substitute an expression containing the clobbered register.
1345 As we do not analyze the constraint strings here, we have to
1346 make the conservative assumption. However, if the register is
1347 a fixed hard reg, the clobber cannot represent any operand;
1348 we leave it up to the machine description to either accept or
1349 reject use-and-clobber patterns. */
1351 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1352 || !fixed_regs[REGNO (reg)])
1353 if (reg_overlap_mentioned_p (reg, src))
1357 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1358 or not), reject, unless nothing volatile comes between it and I3 */
1360 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1362 /* Make sure succ doesn't contain a volatile reference. */
1363 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1366 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1367 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1371 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1372 to be an explicit register variable, and was chosen for a reason. */
1374 if (GET_CODE (src) == ASM_OPERANDS
1375 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1378 /* If there are any volatile insns between INSN and I3, reject, because
1379 they might affect machine state. */
1381 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1382 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1385 /* If INSN contains an autoincrement or autodecrement, make sure that
1386 register is not used between there and I3, and not already used in
1387 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1388 Also insist that I3 not be a jump; if it were one
1389 and the incremented register were spilled, we would lose. */
1392 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1393 if (REG_NOTE_KIND (link) == REG_INC
1395 || reg_used_between_p (XEXP (link, 0), insn, i3)
1396 || (pred != NULL_RTX
1397 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1398 || (succ != NULL_RTX
1399 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1400 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1405 /* Don't combine an insn that follows a CC0-setting insn.
1406 An insn that uses CC0 must not be separated from the one that sets it.
1407 We do, however, allow I2 to follow a CC0-setting insn if that insn
1408 is passed as I1; in that case it will be deleted also.
1409 We also allow combining in this case if all the insns are adjacent
1410 because that would leave the two CC0 insns adjacent as well.
1411 It would be more logical to test whether CC0 occurs inside I1 or I2,
1412 but that would be much slower, and this ought to be equivalent. */
1414 p = prev_nonnote_insn (insn);
1415 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1420 /* If we get here, we have passed all the tests and the combination is
1429 /* LOC is the location within I3 that contains its pattern or the component
1430 of a PARALLEL of the pattern. We validate that it is valid for combining.
1432 One problem is if I3 modifies its output, as opposed to replacing it
1433 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1434 so would produce an insn that is not equivalent to the original insns.
1438 (set (reg:DI 101) (reg:DI 100))
1439 (set (subreg:SI (reg:DI 101) 0) <foo>)
1441 This is NOT equivalent to:
1443 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1444 (set (reg:DI 101) (reg:DI 100))])
1446 Not only does this modify 100 (in which case it might still be valid
1447 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1449 We can also run into a problem if I2 sets a register that I1
1450 uses and I1 gets directly substituted into I3 (not via I2). In that
1451 case, we would be getting the wrong value of I2DEST into I3, so we
1452 must reject the combination. This case occurs when I2 and I1 both
1453 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1454 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1455 of a SET must prevent combination from occurring.
1457 Before doing the above check, we first try to expand a field assignment
1458 into a set of logical operations.
1460 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1461 we place a register that is both set and used within I3. If more than one
1462 such register is detected, we fail.
1464 Return 1 if the combination is valid, zero otherwise. */
1467 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1468 int i1_not_in_src, rtx *pi3dest_killed)
1472 if (GET_CODE (x) == SET)
1475 rtx dest = SET_DEST (set);
1476 rtx src = SET_SRC (set);
1477 rtx inner_dest = dest;
1480 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1481 || GET_CODE (inner_dest) == SUBREG
1482 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1483 inner_dest = XEXP (inner_dest, 0);
1485 /* Check for the case where I3 modifies its output, as discussed
1486 above. We don't want to prevent pseudos from being combined
1487 into the address of a MEM, so only prevent the combination if
1488 i1 or i2 set the same MEM. */
1489 if ((inner_dest != dest &&
1490 (!MEM_P (inner_dest)
1491 || rtx_equal_p (i2dest, inner_dest)
1492 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1493 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1494 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1496 /* This is the same test done in can_combine_p except we can't test
1497 all_adjacent; we don't have to, since this instruction will stay
1498 in place, thus we are not considering increasing the lifetime of
1501 Also, if this insn sets a function argument, combining it with
1502 something that might need a spill could clobber a previous
1503 function argument; the all_adjacent test in can_combine_p also
1504 checks this; here, we do a more specific test for this case. */
1506 || (REG_P (inner_dest)
1507 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1508 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1509 GET_MODE (inner_dest))))
1510 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1513 /* If DEST is used in I3, it is being killed in this insn, so
1514 record that for later. We have to consider paradoxical
1515 subregs here, since they kill the whole register, but we
1516 ignore partial subregs, STRICT_LOW_PART, etc.
1517 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1518 STACK_POINTER_REGNUM, since these are always considered to be
1519 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1521 if (GET_CODE (subdest) == SUBREG
1522 && (GET_MODE_SIZE (GET_MODE (subdest))
1523 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1524 subdest = SUBREG_REG (subdest);
1527 && reg_referenced_p (subdest, PATTERN (i3))
1528 && REGNO (subdest) != FRAME_POINTER_REGNUM
1529 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1530 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1532 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1533 && (REGNO (subdest) != ARG_POINTER_REGNUM
1534 || ! fixed_regs [REGNO (subdest)])
1536 && REGNO (subdest) != STACK_POINTER_REGNUM)
1538 if (*pi3dest_killed)
1541 *pi3dest_killed = subdest;
1545 else if (GET_CODE (x) == PARALLEL)
1549 for (i = 0; i < XVECLEN (x, 0); i++)
1550 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1551 i1_not_in_src, pi3dest_killed))
1558 /* Return 1 if X is an arithmetic expression that contains a multiplication
1559 and division. We don't count multiplications by powers of two here. */
1562 contains_muldiv (rtx x)
1564 switch (GET_CODE (x))
1566 case MOD: case DIV: case UMOD: case UDIV:
1570 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1571 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1574 return contains_muldiv (XEXP (x, 0))
1575 || contains_muldiv (XEXP (x, 1));
1578 return contains_muldiv (XEXP (x, 0));
1584 /* Determine whether INSN can be used in a combination. Return nonzero if
1585 not. This is used in try_combine to detect early some cases where we
1586 can't perform combinations. */
1589 cant_combine_insn_p (rtx insn)
1594 /* If this isn't really an insn, we can't do anything.
1595 This can occur when flow deletes an insn that it has merged into an
1596 auto-increment address. */
1597 if (! INSN_P (insn))
1600 /* Never combine loads and stores involving hard regs that are likely
1601 to be spilled. The register allocator can usually handle such
1602 reg-reg moves by tying. If we allow the combiner to make
1603 substitutions of likely-spilled regs, reload might die.
1604 As an exception, we allow combinations involving fixed regs; these are
1605 not available to the register allocator so there's no risk involved. */
1607 set = single_set (insn);
1610 src = SET_SRC (set);
1611 dest = SET_DEST (set);
1612 if (GET_CODE (src) == SUBREG)
1613 src = SUBREG_REG (src);
1614 if (GET_CODE (dest) == SUBREG)
1615 dest = SUBREG_REG (dest);
1616 if (REG_P (src) && REG_P (dest)
1617 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1618 && ! fixed_regs[REGNO (src)]
1619 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1620 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1621 && ! fixed_regs[REGNO (dest)]
1622 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1628 struct likely_spilled_retval_info
1630 unsigned regno, nregs;
1634 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1635 hard registers that are known to be written to / clobbered in full. */
1637 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1639 struct likely_spilled_retval_info *info = data;
1640 unsigned regno, nregs;
1643 if (!REG_P (XEXP (set, 0)))
1646 if (regno >= info->regno + info->nregs)
1648 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1649 if (regno + nregs <= info->regno)
1651 new_mask = (2U << (nregs - 1)) - 1;
1652 if (regno < info->regno)
1653 new_mask >>= info->regno - regno;
1655 new_mask <<= regno - info->regno;
1656 info->mask &= new_mask;
1659 /* Return nonzero iff part of the return value is live during INSN, and
1660 it is likely spilled. This can happen when more than one insn is needed
1661 to copy the return value, e.g. when we consider to combine into the
1662 second copy insn for a complex value. */
1665 likely_spilled_retval_p (rtx insn)
1667 rtx use = BB_END (this_basic_block);
1669 unsigned regno, nregs;
1670 /* We assume here that no machine mode needs more than
1671 32 hard registers when the value overlaps with a register
1672 for which FUNCTION_VALUE_REGNO_P is true. */
1674 struct likely_spilled_retval_info info;
1676 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1678 reg = XEXP (PATTERN (use), 0);
1679 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1681 regno = REGNO (reg);
1682 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1685 mask = (2U << (nregs - 1)) - 1;
1687 /* Disregard parts of the return value that are set later. */
1691 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1692 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1695 /* Check if any of the (probably) live return value registers is
1700 if ((mask & 1 << nregs)
1701 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1707 /* Adjust INSN after we made a change to its destination.
1709 Changing the destination can invalidate notes that say something about
1710 the results of the insn and a LOG_LINK pointing to the insn. */
1713 adjust_for_new_dest (rtx insn)
1717 /* For notes, be conservative and simply remove them. */
1718 loc = ®_NOTES (insn);
1721 enum reg_note kind = REG_NOTE_KIND (*loc);
1722 if (kind == REG_EQUAL || kind == REG_EQUIV)
1723 *loc = XEXP (*loc, 1);
1725 loc = &XEXP (*loc, 1);
1728 /* The new insn will have a destination that was previously the destination
1729 of an insn just above it. Call distribute_links to make a LOG_LINK from
1730 the next use of that destination. */
1731 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1734 /* Return TRUE if combine can reuse reg X in mode MODE.
1735 ADDED_SETS is nonzero if the original set is still required. */
1737 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1745 /* Allow hard registers if the new mode is legal, and occupies no more
1746 registers than the old mode. */
1747 if (regno < FIRST_PSEUDO_REGISTER)
1748 return (HARD_REGNO_MODE_OK (regno, mode)
1749 && (hard_regno_nregs[regno][GET_MODE (x)]
1750 >= hard_regno_nregs[regno][mode]));
1752 /* Or a pseudo that is only used once. */
1753 return (REG_N_SETS (regno) == 1 && !added_sets
1754 && !REG_USERVAR_P (x));
1758 /* Check whether X, the destination of a set, refers to part of
1759 the register specified by REG. */
1762 reg_subword_p (rtx x, rtx reg)
1764 /* Check that reg is an integer mode register. */
1765 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1768 if (GET_CODE (x) == STRICT_LOW_PART
1769 || GET_CODE (x) == ZERO_EXTRACT)
1772 return GET_CODE (x) == SUBREG
1773 && SUBREG_REG (x) == reg
1774 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1778 /* Try to combine the insns I1 and I2 into I3.
1779 Here I1 and I2 appear earlier than I3.
1780 I1 can be zero; then we combine just I2 into I3.
1782 If we are combining three insns and the resulting insn is not recognized,
1783 try splitting it into two insns. If that happens, I2 and I3 are retained
1784 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1787 Return 0 if the combination does not work. Then nothing is changed.
1788 If we did the combination, return the insn at which combine should
1791 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1792 new direct jump instruction. */
1795 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1797 /* New patterns for I3 and I2, respectively. */
1798 rtx newpat, newi2pat = 0;
1799 rtvec newpat_vec_with_clobbers = 0;
1800 int substed_i2 = 0, substed_i1 = 0;
1801 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1802 int added_sets_1, added_sets_2;
1803 /* Total number of SETs to put into I3. */
1805 /* Nonzero if I2's body now appears in I3. */
1807 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1808 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1809 /* Contains I3 if the destination of I3 is used in its source, which means
1810 that the old life of I3 is being killed. If that usage is placed into
1811 I2 and not in I3, a REG_DEAD note must be made. */
1812 rtx i3dest_killed = 0;
1813 /* SET_DEST and SET_SRC of I2 and I1. */
1814 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1815 /* PATTERN (I2), or a copy of it in certain cases. */
1817 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1818 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1819 int i2dest_killed = 0, i1dest_killed = 0;
1820 int i1_feeds_i3 = 0;
1821 /* Notes that must be added to REG_NOTES in I3 and I2. */
1822 rtx new_i3_notes, new_i2_notes;
1823 /* Notes that we substituted I3 into I2 instead of the normal case. */
1824 int i3_subst_into_i2 = 0;
1825 /* Notes that I1, I2 or I3 is a MULT operation. */
1834 /* Exit early if one of the insns involved can't be used for
1836 if (cant_combine_insn_p (i3)
1837 || cant_combine_insn_p (i2)
1838 || (i1 && cant_combine_insn_p (i1))
1839 || likely_spilled_retval_p (i3)
1840 /* We also can't do anything if I3 has a
1841 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1844 /* ??? This gives worse code, and appears to be unnecessary, since no
1845 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1846 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1852 undobuf.other_insn = 0;
1854 /* Reset the hard register usage information. */
1855 CLEAR_HARD_REG_SET (newpat_used_regs);
1857 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1858 code below, set I1 to be the earlier of the two insns. */
1859 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1860 temp = i1, i1 = i2, i2 = temp;
1862 added_links_insn = 0;
1864 /* First check for one important special-case that the code below will
1865 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1866 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1867 we may be able to replace that destination with the destination of I3.
1868 This occurs in the common code where we compute both a quotient and
1869 remainder into a structure, in which case we want to do the computation
1870 directly into the structure to avoid register-register copies.
1872 Note that this case handles both multiple sets in I2 and also
1873 cases where I2 has a number of CLOBBER or PARALLELs.
1875 We make very conservative checks below and only try to handle the
1876 most common cases of this. For example, we only handle the case
1877 where I2 and I3 are adjacent to avoid making difficult register
1880 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1881 && REG_P (SET_SRC (PATTERN (i3)))
1882 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1883 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1884 && GET_CODE (PATTERN (i2)) == PARALLEL
1885 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1886 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1887 below would need to check what is inside (and reg_overlap_mentioned_p
1888 doesn't support those codes anyway). Don't allow those destinations;
1889 the resulting insn isn't likely to be recognized anyway. */
1890 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1891 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1892 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1893 SET_DEST (PATTERN (i3)))
1894 && next_real_insn (i2) == i3)
1896 rtx p2 = PATTERN (i2);
1898 /* Make sure that the destination of I3,
1899 which we are going to substitute into one output of I2,
1900 is not used within another output of I2. We must avoid making this:
1901 (parallel [(set (mem (reg 69)) ...)
1902 (set (reg 69) ...)])
1903 which is not well-defined as to order of actions.
1904 (Besides, reload can't handle output reloads for this.)
1906 The problem can also happen if the dest of I3 is a memory ref,
1907 if another dest in I2 is an indirect memory ref. */
1908 for (i = 0; i < XVECLEN (p2, 0); i++)
1909 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1910 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1911 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1912 SET_DEST (XVECEXP (p2, 0, i))))
1915 if (i == XVECLEN (p2, 0))
1916 for (i = 0; i < XVECLEN (p2, 0); i++)
1917 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1918 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1919 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1924 subst_low_cuid = INSN_CUID (i2);
1926 added_sets_2 = added_sets_1 = 0;
1927 i2dest = SET_SRC (PATTERN (i3));
1928 i2dest_killed = dead_or_set_p (i2, i2dest);
1930 /* Replace the dest in I2 with our dest and make the resulting
1931 insn the new pattern for I3. Then skip to where we
1932 validate the pattern. Everything was set up above. */
1933 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1934 SET_DEST (PATTERN (i3)));
1937 i3_subst_into_i2 = 1;
1938 goto validate_replacement;
1942 /* If I2 is setting a pseudo to a constant and I3 is setting some
1943 sub-part of it to another constant, merge them by making a new
1946 && (temp = single_set (i2)) != 0
1947 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1948 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1949 && GET_CODE (PATTERN (i3)) == SET
1950 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1951 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1952 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1954 rtx dest = SET_DEST (PATTERN (i3));
1958 if (GET_CODE (dest) == ZERO_EXTRACT)
1960 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1961 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1963 width = INTVAL (XEXP (dest, 1));
1964 offset = INTVAL (XEXP (dest, 2));
1965 dest = XEXP (dest, 0);
1966 if (BITS_BIG_ENDIAN)
1967 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1972 if (GET_CODE (dest) == STRICT_LOW_PART)
1973 dest = XEXP (dest, 0);
1974 width = GET_MODE_BITSIZE (GET_MODE (dest));
1980 /* If this is the low part, we're done. */
1981 if (subreg_lowpart_p (dest))
1983 /* Handle the case where inner is twice the size of outer. */
1984 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1985 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1986 offset += GET_MODE_BITSIZE (GET_MODE (dest));
1987 /* Otherwise give up for now. */
1994 HOST_WIDE_INT mhi, ohi, ihi;
1995 HOST_WIDE_INT mlo, olo, ilo;
1996 rtx inner = SET_SRC (PATTERN (i3));
1997 rtx outer = SET_SRC (temp);
1999 if (GET_CODE (outer) == CONST_INT)
2001 olo = INTVAL (outer);
2002 ohi = olo < 0 ? -1 : 0;
2006 olo = CONST_DOUBLE_LOW (outer);
2007 ohi = CONST_DOUBLE_HIGH (outer);
2010 if (GET_CODE (inner) == CONST_INT)
2012 ilo = INTVAL (inner);
2013 ihi = ilo < 0 ? -1 : 0;
2017 ilo = CONST_DOUBLE_LOW (inner);
2018 ihi = CONST_DOUBLE_HIGH (inner);
2021 if (width < HOST_BITS_PER_WIDE_INT)
2023 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2026 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2028 mhi = ((unsigned HOST_WIDE_INT) 1
2029 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2041 if (offset >= HOST_BITS_PER_WIDE_INT)
2043 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2045 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2048 else if (offset > 0)
2050 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2051 >> (HOST_BITS_PER_WIDE_INT - offset));
2052 mlo = mlo << offset;
2053 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2054 >> (HOST_BITS_PER_WIDE_INT - offset));
2055 ilo = ilo << offset;
2058 olo = (olo & ~mlo) | ilo;
2059 ohi = (ohi & ~mhi) | ihi;
2063 subst_low_cuid = INSN_CUID (i2);
2064 added_sets_2 = added_sets_1 = 0;
2065 i2dest = SET_DEST (temp);
2066 i2dest_killed = dead_or_set_p (i2, i2dest);
2068 SUBST (SET_SRC (temp),
2069 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2071 newpat = PATTERN (i2);
2072 goto validate_replacement;
2077 /* If we have no I1 and I2 looks like:
2078 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2080 make up a dummy I1 that is
2083 (set (reg:CC X) (compare:CC Y (const_int 0)))
2085 (We can ignore any trailing CLOBBERs.)
2087 This undoes a previous combination and allows us to match a branch-and-
2090 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2091 && XVECLEN (PATTERN (i2), 0) >= 2
2092 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2093 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2095 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2096 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2097 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2098 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2099 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2100 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2102 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2103 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2108 /* We make I1 with the same INSN_UID as I2. This gives it
2109 the same INSN_CUID for value tracking. Our fake I1 will
2110 never appear in the insn stream so giving it the same INSN_UID
2111 as I2 will not cause a problem. */
2113 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2114 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2115 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2118 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2119 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2120 SET_DEST (PATTERN (i1)));
2125 /* Verify that I2 and I1 are valid for combining. */
2126 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2127 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2133 /* Record whether I2DEST is used in I2SRC and similarly for the other
2134 cases. Knowing this will help in register status updating below. */
2135 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2136 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2137 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2138 i2dest_killed = dead_or_set_p (i2, i2dest);
2139 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2141 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2143 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2145 /* Ensure that I3's pattern can be the destination of combines. */
2146 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2147 i1 && i2dest_in_i1src && i1_feeds_i3,
2154 /* See if any of the insns is a MULT operation. Unless one is, we will
2155 reject a combination that is, since it must be slower. Be conservative
2157 if (GET_CODE (i2src) == MULT
2158 || (i1 != 0 && GET_CODE (i1src) == MULT)
2159 || (GET_CODE (PATTERN (i3)) == SET
2160 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2163 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2164 We used to do this EXCEPT in one case: I3 has a post-inc in an
2165 output operand. However, that exception can give rise to insns like
2167 which is a famous insn on the PDP-11 where the value of r3 used as the
2168 source was model-dependent. Avoid this sort of thing. */
2171 if (!(GET_CODE (PATTERN (i3)) == SET
2172 && REG_P (SET_SRC (PATTERN (i3)))
2173 && MEM_P (SET_DEST (PATTERN (i3)))
2174 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2175 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2176 /* It's not the exception. */
2179 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2180 if (REG_NOTE_KIND (link) == REG_INC
2181 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2183 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2190 /* See if the SETs in I1 or I2 need to be kept around in the merged
2191 instruction: whenever the value set there is still needed past I3.
2192 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2194 For the SET in I1, we have two cases: If I1 and I2 independently
2195 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2196 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2197 in I1 needs to be kept around unless I1DEST dies or is set in either
2198 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2199 I1DEST. If so, we know I1 feeds into I2. */
2201 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2204 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2205 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2207 /* If the set in I2 needs to be kept around, we must make a copy of
2208 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2209 PATTERN (I2), we are only substituting for the original I1DEST, not into
2210 an already-substituted copy. This also prevents making self-referential
2211 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2214 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2215 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2219 i2pat = copy_rtx (i2pat);
2223 /* Substitute in the latest insn for the regs set by the earlier ones. */
2225 maxreg = max_reg_num ();
2230 /* Many machines that don't use CC0 have insns that can both perform an
2231 arithmetic operation and set the condition code. These operations will
2232 be represented as a PARALLEL with the first element of the vector
2233 being a COMPARE of an arithmetic operation with the constant zero.
2234 The second element of the vector will set some pseudo to the result
2235 of the same arithmetic operation. If we simplify the COMPARE, we won't
2236 match such a pattern and so will generate an extra insn. Here we test
2237 for this case, where both the comparison and the operation result are
2238 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2239 I2SRC. Later we will make the PARALLEL that contains I2. */
2241 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2242 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2243 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2244 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2246 #ifdef SELECT_CC_MODE
2248 enum machine_mode compare_mode;
2251 newpat = PATTERN (i3);
2252 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2256 #ifdef SELECT_CC_MODE
2257 /* See if a COMPARE with the operand we substituted in should be done
2258 with the mode that is currently being used. If not, do the same
2259 processing we do in `subst' for a SET; namely, if the destination
2260 is used only once, try to replace it with a register of the proper
2261 mode and also replace the COMPARE. */
2262 if (undobuf.other_insn == 0
2263 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2264 &undobuf.other_insn))
2265 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2267 != GET_MODE (SET_DEST (newpat))))
2269 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2272 unsigned int regno = REGNO (SET_DEST (newpat));
2275 if (regno < FIRST_PSEUDO_REGISTER)
2276 new_dest = gen_rtx_REG (compare_mode, regno);
2279 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2280 new_dest = regno_reg_rtx[regno];
2283 SUBST (SET_DEST (newpat), new_dest);
2284 SUBST (XEXP (*cc_use, 0), new_dest);
2285 SUBST (SET_SRC (newpat),
2286 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2289 undobuf.other_insn = 0;
2296 /* It is possible that the source of I2 or I1 may be performing
2297 an unneeded operation, such as a ZERO_EXTEND of something
2298 that is known to have the high part zero. Handle that case
2299 by letting subst look at the innermost one of them.
2301 Another way to do this would be to have a function that tries
2302 to simplify a single insn instead of merging two or more
2303 insns. We don't do this because of the potential of infinite
2304 loops and because of the potential extra memory required.
2305 However, doing it the way we are is a bit of a kludge and
2306 doesn't catch all cases.
2308 But only do this if -fexpensive-optimizations since it slows
2309 things down and doesn't usually win.
2311 This is not done in the COMPARE case above because the
2312 unmodified I2PAT is used in the PARALLEL and so a pattern
2313 with a modified I2SRC would not match. */
2315 if (flag_expensive_optimizations)
2317 /* Pass pc_rtx so no substitutions are done, just
2321 subst_low_cuid = INSN_CUID (i1);
2322 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2326 subst_low_cuid = INSN_CUID (i2);
2327 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2331 n_occurrences = 0; /* `subst' counts here */
2333 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2334 need to make a unique copy of I2SRC each time we substitute it
2335 to avoid self-referential rtl. */
2337 subst_low_cuid = INSN_CUID (i2);
2338 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2339 ! i1_feeds_i3 && i1dest_in_i1src);
2342 /* Record whether i2's body now appears within i3's body. */
2343 i2_is_used = n_occurrences;
2346 /* If we already got a failure, don't try to do more. Otherwise,
2347 try to substitute in I1 if we have it. */
2349 if (i1 && GET_CODE (newpat) != CLOBBER)
2351 /* Before we can do this substitution, we must redo the test done
2352 above (see detailed comments there) that ensures that I1DEST
2353 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2355 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2363 subst_low_cuid = INSN_CUID (i1);
2364 newpat = subst (newpat, i1dest, i1src, 0, 0);
2368 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2369 to count all the ways that I2SRC and I1SRC can be used. */
2370 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2371 && i2_is_used + added_sets_2 > 1)
2372 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2373 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2375 /* Fail if we tried to make a new register. */
2376 || max_reg_num () != maxreg
2377 /* Fail if we couldn't do something and have a CLOBBER. */
2378 || GET_CODE (newpat) == CLOBBER
2379 /* Fail if this new pattern is a MULT and we didn't have one before
2380 at the outer level. */
2381 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2388 /* If the actions of the earlier insns must be kept
2389 in addition to substituting them into the latest one,
2390 we must make a new PARALLEL for the latest insn
2391 to hold additional the SETs. */
2393 if (added_sets_1 || added_sets_2)
2397 if (GET_CODE (newpat) == PARALLEL)
2399 rtvec old = XVEC (newpat, 0);
2400 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2401 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2402 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2403 sizeof (old->elem[0]) * old->num_elem);
2408 total_sets = 1 + added_sets_1 + added_sets_2;
2409 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2410 XVECEXP (newpat, 0, 0) = old;
2414 XVECEXP (newpat, 0, --total_sets)
2415 = (GET_CODE (PATTERN (i1)) == PARALLEL
2416 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2420 /* If there is no I1, use I2's body as is. We used to also not do
2421 the subst call below if I2 was substituted into I3,
2422 but that could lose a simplification. */
2424 XVECEXP (newpat, 0, --total_sets) = i2pat;
2426 /* See comment where i2pat is assigned. */
2427 XVECEXP (newpat, 0, --total_sets)
2428 = subst (i2pat, i1dest, i1src, 0, 0);
2432 /* We come here when we are replacing a destination in I2 with the
2433 destination of I3. */
2434 validate_replacement:
2436 /* Note which hard regs this insn has as inputs. */
2437 mark_used_regs_combine (newpat);
2439 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2440 consider splitting this pattern, we might need these clobbers. */
2441 if (i1 && GET_CODE (newpat) == PARALLEL
2442 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2444 int len = XVECLEN (newpat, 0);
2446 newpat_vec_with_clobbers = rtvec_alloc (len);
2447 for (i = 0; i < len; i++)
2448 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2451 /* Is the result of combination a valid instruction? */
2452 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2454 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2455 the second SET's destination is a register that is unused and isn't
2456 marked as an instruction that might trap in an EH region. In that case,
2457 we just need the first SET. This can occur when simplifying a divmod
2458 insn. We *must* test for this case here because the code below that
2459 splits two independent SETs doesn't handle this case correctly when it
2460 updates the register status.
2462 It's pointless doing this if we originally had two sets, one from
2463 i3, and one from i2. Combining then splitting the parallel results
2464 in the original i2 again plus an invalid insn (which we delete).
2465 The net effect is only to move instructions around, which makes
2466 debug info less accurate.
2468 Also check the case where the first SET's destination is unused.
2469 That would not cause incorrect code, but does cause an unneeded
2472 if (insn_code_number < 0
2473 && !(added_sets_2 && i1 == 0)
2474 && GET_CODE (newpat) == PARALLEL
2475 && XVECLEN (newpat, 0) == 2
2476 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2477 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2478 && asm_noperands (newpat) < 0)
2480 rtx set0 = XVECEXP (newpat, 0, 0);
2481 rtx set1 = XVECEXP (newpat, 0, 1);
2484 if (((REG_P (SET_DEST (set1))
2485 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2486 || (GET_CODE (SET_DEST (set1)) == SUBREG
2487 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2488 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2489 || INTVAL (XEXP (note, 0)) <= 0)
2490 && ! side_effects_p (SET_SRC (set1)))
2493 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2496 else if (((REG_P (SET_DEST (set0))
2497 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2498 || (GET_CODE (SET_DEST (set0)) == SUBREG
2499 && find_reg_note (i3, REG_UNUSED,
2500 SUBREG_REG (SET_DEST (set0)))))
2501 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2502 || INTVAL (XEXP (note, 0)) <= 0)
2503 && ! side_effects_p (SET_SRC (set0)))
2506 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2508 if (insn_code_number >= 0)
2510 /* If we will be able to accept this, we have made a
2511 change to the destination of I3. This requires us to
2512 do a few adjustments. */
2514 PATTERN (i3) = newpat;
2515 adjust_for_new_dest (i3);
2520 /* If we were combining three insns and the result is a simple SET
2521 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2522 insns. There are two ways to do this. It can be split using a
2523 machine-specific method (like when you have an addition of a large
2524 constant) or by combine in the function find_split_point. */
2526 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2527 && asm_noperands (newpat) < 0)
2529 rtx m_split, *split;
2531 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2532 use I2DEST as a scratch register will help. In the latter case,
2533 convert I2DEST to the mode of the source of NEWPAT if we can. */
2535 m_split = split_insns (newpat, i3);
2537 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2538 inputs of NEWPAT. */
2540 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2541 possible to try that as a scratch reg. This would require adding
2542 more code to make it work though. */
2544 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2546 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2548 /* First try to split using the original register as a
2549 scratch register. */
2550 m_split = split_insns (gen_rtx_PARALLEL
2552 gen_rtvec (2, newpat,
2553 gen_rtx_CLOBBER (VOIDmode,
2557 /* If that didn't work, try changing the mode of I2DEST if
2560 && new_mode != GET_MODE (i2dest)
2561 && new_mode != VOIDmode
2562 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2564 enum machine_mode old_mode = GET_MODE (i2dest);
2567 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2568 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2571 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2572 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2575 m_split = split_insns (gen_rtx_PARALLEL
2577 gen_rtvec (2, newpat,
2578 gen_rtx_CLOBBER (VOIDmode,
2583 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2587 PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2588 buf = undobuf.undos;
2589 undobuf.undos = buf->next;
2590 buf->next = undobuf.frees;
2591 undobuf.frees = buf;
2596 /* If recog_for_combine has discarded clobbers, try to use them
2597 again for the split. */
2598 if (m_split == 0 && newpat_vec_with_clobbers)
2600 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2601 newpat_vec_with_clobbers), i3);
2603 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2605 m_split = PATTERN (m_split);
2606 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2607 if (insn_code_number >= 0)
2610 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2611 && (next_real_insn (i2) == i3
2612 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2615 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2616 newi2pat = PATTERN (m_split);
2618 i3set = single_set (NEXT_INSN (m_split));
2619 i2set = single_set (m_split);
2621 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2623 /* If I2 or I3 has multiple SETs, we won't know how to track
2624 register status, so don't use these insns. If I2's destination
2625 is used between I2 and I3, we also can't use these insns. */
2627 if (i2_code_number >= 0 && i2set && i3set
2628 && (next_real_insn (i2) == i3
2629 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2630 insn_code_number = recog_for_combine (&newi3pat, i3,
2632 if (insn_code_number >= 0)
2635 /* It is possible that both insns now set the destination of I3.
2636 If so, we must show an extra use of it. */
2638 if (insn_code_number >= 0)
2640 rtx new_i3_dest = SET_DEST (i3set);
2641 rtx new_i2_dest = SET_DEST (i2set);
2643 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2644 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2645 || GET_CODE (new_i3_dest) == SUBREG)
2646 new_i3_dest = XEXP (new_i3_dest, 0);
2648 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2649 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2650 || GET_CODE (new_i2_dest) == SUBREG)
2651 new_i2_dest = XEXP (new_i2_dest, 0);
2653 if (REG_P (new_i3_dest)
2654 && REG_P (new_i2_dest)
2655 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2656 REG_N_SETS (REGNO (new_i2_dest))++;
2660 /* If we can split it and use I2DEST, go ahead and see if that
2661 helps things be recognized. Verify that none of the registers
2662 are set between I2 and I3. */
2663 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2667 /* We need I2DEST in the proper mode. If it is a hard register
2668 or the only use of a pseudo, we can change its mode.
2669 Make sure we don't change a hard register to have a mode that
2670 isn't valid for it, or change the number of registers. */
2671 && (GET_MODE (*split) == GET_MODE (i2dest)
2672 || GET_MODE (*split) == VOIDmode
2673 || can_change_dest_mode (i2dest, added_sets_2,
2675 && (next_real_insn (i2) == i3
2676 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2677 /* We can't overwrite I2DEST if its value is still used by
2679 && ! reg_referenced_p (i2dest, newpat))
2681 rtx newdest = i2dest;
2682 enum rtx_code split_code = GET_CODE (*split);
2683 enum machine_mode split_mode = GET_MODE (*split);
2684 bool subst_done = false;
2685 newi2pat = NULL_RTX;
2687 /* Get NEWDEST as a register in the proper mode. We have already
2688 validated that we can do this. */
2689 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2691 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2692 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2695 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2696 newdest = regno_reg_rtx[REGNO (i2dest)];
2700 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2701 an ASHIFT. This can occur if it was inside a PLUS and hence
2702 appeared to be a memory address. This is a kludge. */
2703 if (split_code == MULT
2704 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2705 && INTVAL (XEXP (*split, 1)) > 0
2706 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2708 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2709 XEXP (*split, 0), GEN_INT (i)));
2710 /* Update split_code because we may not have a multiply
2712 split_code = GET_CODE (*split);
2715 #ifdef INSN_SCHEDULING
2716 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2717 be written as a ZERO_EXTEND. */
2718 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2720 #ifdef LOAD_EXTEND_OP
2721 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2722 what it really is. */
2723 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2725 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2726 SUBREG_REG (*split)));
2729 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2730 SUBREG_REG (*split)));
2734 /* Attempt to split binary operators using arithmetic identities. */
2735 if (BINARY_P (SET_SRC (newpat))
2736 && split_mode == GET_MODE (SET_SRC (newpat))
2737 && ! side_effects_p (SET_SRC (newpat)))
2739 rtx setsrc = SET_SRC (newpat);
2740 enum machine_mode mode = GET_MODE (setsrc);
2741 enum rtx_code code = GET_CODE (setsrc);
2742 rtx src_op0 = XEXP (setsrc, 0);
2743 rtx src_op1 = XEXP (setsrc, 1);
2745 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2746 if (rtx_equal_p (src_op0, src_op1))
2748 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2749 SUBST (XEXP (setsrc, 0), newdest);
2750 SUBST (XEXP (setsrc, 1), newdest);
2753 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2754 else if ((code == PLUS || code == MULT)
2755 && GET_CODE (src_op0) == code
2756 && GET_CODE (XEXP (src_op0, 0)) == code
2757 && (INTEGRAL_MODE_P (mode)
2758 || (FLOAT_MODE_P (mode)
2759 && flag_unsafe_math_optimizations)))
2761 rtx p = XEXP (XEXP (src_op0, 0), 0);
2762 rtx q = XEXP (XEXP (src_op0, 0), 1);
2763 rtx r = XEXP (src_op0, 1);
2766 /* Split both "((X op Y) op X) op Y" and
2767 "((X op Y) op Y) op X" as "T op T" where T is
2769 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2770 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2772 newi2pat = gen_rtx_SET (VOIDmode, newdest,
2774 SUBST (XEXP (setsrc, 0), newdest);
2775 SUBST (XEXP (setsrc, 1), newdest);
2778 /* Split "((X op X) op Y) op Y)" as "T op T" where
2780 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2782 rtx tmp = simplify_gen_binary (code, mode, p, r);
2783 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2784 SUBST (XEXP (setsrc, 0), newdest);
2785 SUBST (XEXP (setsrc, 1), newdest);
2793 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2794 SUBST (*split, newdest);
2797 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2799 /* recog_for_combine might have added CLOBBERs to newi2pat.
2800 Make sure NEWPAT does not depend on the clobbered regs. */
2801 if (GET_CODE (newi2pat) == PARALLEL)
2802 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2803 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2805 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2806 if (reg_overlap_mentioned_p (reg, newpat))
2813 /* If the split point was a MULT and we didn't have one before,
2814 don't use one now. */
2815 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2816 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2820 /* Check for a case where we loaded from memory in a narrow mode and
2821 then sign extended it, but we need both registers. In that case,
2822 we have a PARALLEL with both loads from the same memory location.
2823 We can split this into a load from memory followed by a register-register
2824 copy. This saves at least one insn, more if register allocation can
2827 We cannot do this if the destination of the first assignment is a
2828 condition code register or cc0. We eliminate this case by making sure
2829 the SET_DEST and SET_SRC have the same mode.
2831 We cannot do this if the destination of the second assignment is
2832 a register that we have already assumed is zero-extended. Similarly
2833 for a SUBREG of such a register. */
2835 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2836 && GET_CODE (newpat) == PARALLEL
2837 && XVECLEN (newpat, 0) == 2
2838 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2839 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2840 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2841 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2842 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2843 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2844 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2845 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2847 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2848 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2849 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2851 && reg_stat[REGNO (temp)].nonzero_bits != 0
2852 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2853 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2854 && (reg_stat[REGNO (temp)].nonzero_bits
2855 != GET_MODE_MASK (word_mode))))
2856 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2857 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2859 && reg_stat[REGNO (temp)].nonzero_bits != 0
2860 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2861 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2862 && (reg_stat[REGNO (temp)].nonzero_bits
2863 != GET_MODE_MASK (word_mode)))))
2864 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2865 SET_SRC (XVECEXP (newpat, 0, 1)))
2866 && ! find_reg_note (i3, REG_UNUSED,
2867 SET_DEST (XVECEXP (newpat, 0, 0))))
2871 newi2pat = XVECEXP (newpat, 0, 0);
2872 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2873 newpat = XVECEXP (newpat, 0, 1);
2874 SUBST (SET_SRC (newpat),
2875 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2876 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2878 if (i2_code_number >= 0)
2879 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2881 if (insn_code_number >= 0)
2885 /* Similarly, check for a case where we have a PARALLEL of two independent
2886 SETs but we started with three insns. In this case, we can do the sets
2887 as two separate insns. This case occurs when some SET allows two
2888 other insns to combine, but the destination of that SET is still live. */
2890 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2891 && GET_CODE (newpat) == PARALLEL
2892 && XVECLEN (newpat, 0) == 2
2893 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2894 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2895 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2896 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2897 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2898 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2899 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2901 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2902 XVECEXP (newpat, 0, 0))
2903 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2904 XVECEXP (newpat, 0, 1))
2905 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2906 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2908 /* We cannot split the parallel into two sets if both sets
2910 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2911 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2915 /* Normally, it doesn't matter which of the two is done first,
2916 but it does if one references cc0. In that case, it has to
2919 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2921 newi2pat = XVECEXP (newpat, 0, 0);
2922 newpat = XVECEXP (newpat, 0, 1);
2927 newi2pat = XVECEXP (newpat, 0, 1);
2928 newpat = XVECEXP (newpat, 0, 0);
2931 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2933 if (i2_code_number >= 0)
2934 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2937 /* If it still isn't recognized, fail and change things back the way they
2939 if ((insn_code_number < 0
2940 /* Is the result a reasonable ASM_OPERANDS? */
2941 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2947 /* If we had to change another insn, make sure it is valid also. */
2948 if (undobuf.other_insn)
2950 rtx other_pat = PATTERN (undobuf.other_insn);
2951 rtx new_other_notes;
2954 CLEAR_HARD_REG_SET (newpat_used_regs);
2956 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2959 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2965 PATTERN (undobuf.other_insn) = other_pat;
2967 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2968 are still valid. Then add any non-duplicate notes added by
2969 recog_for_combine. */
2970 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2972 next = XEXP (note, 1);
2974 if (REG_NOTE_KIND (note) == REG_UNUSED
2975 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2977 if (REG_P (XEXP (note, 0)))
2978 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2980 remove_note (undobuf.other_insn, note);
2984 for (note = new_other_notes; note; note = XEXP (note, 1))
2985 if (REG_P (XEXP (note, 0)))
2986 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2988 distribute_notes (new_other_notes, undobuf.other_insn,
2989 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2992 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2993 they are adjacent to each other or not. */
2995 rtx p = prev_nonnote_insn (i3);
2996 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2997 && sets_cc0_p (newi2pat))
3005 /* Only allow this combination if insn_rtx_costs reports that the
3006 replacement instructions are cheaper than the originals. */
3007 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3013 /* We now know that we can do this combination. Merge the insns and
3014 update the status of registers and LOG_LINKS. */
3022 /* I3 now uses what used to be its destination and which is now
3023 I2's destination. This requires us to do a few adjustments. */
3024 PATTERN (i3) = newpat;
3025 adjust_for_new_dest (i3);
3027 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3030 However, some later insn might be using I2's dest and have
3031 a LOG_LINK pointing at I3. We must remove this link.
3032 The simplest way to remove the link is to point it at I1,
3033 which we know will be a NOTE. */
3035 /* newi2pat is usually a SET here; however, recog_for_combine might
3036 have added some clobbers. */
3037 if (GET_CODE (newi2pat) == PARALLEL)
3038 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3040 ni2dest = SET_DEST (newi2pat);
3042 for (insn = NEXT_INSN (i3);
3043 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3044 || insn != BB_HEAD (this_basic_block->next_bb));
3045 insn = NEXT_INSN (insn))
3047 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3049 for (link = LOG_LINKS (insn); link;
3050 link = XEXP (link, 1))
3051 if (XEXP (link, 0) == i3)
3052 XEXP (link, 0) = i1;
3060 rtx i3notes, i2notes, i1notes = 0;
3061 rtx i3links, i2links, i1links = 0;
3064 /* Compute which registers we expect to eliminate. newi2pat may be setting
3065 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3066 same as i3dest, in which case newi2pat may be setting i1dest. */
3067 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3068 || i2dest_in_i2src || i2dest_in_i1src
3071 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3072 || (newi2pat && reg_set_p (i1dest, newi2pat))
3076 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3078 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3079 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3081 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3083 /* Ensure that we do not have something that should not be shared but
3084 occurs multiple times in the new insns. Check this by first
3085 resetting all the `used' flags and then copying anything is shared. */
3087 reset_used_flags (i3notes);
3088 reset_used_flags (i2notes);
3089 reset_used_flags (i1notes);
3090 reset_used_flags (newpat);
3091 reset_used_flags (newi2pat);
3092 if (undobuf.other_insn)
3093 reset_used_flags (PATTERN (undobuf.other_insn));
3095 i3notes = copy_rtx_if_shared (i3notes);
3096 i2notes = copy_rtx_if_shared (i2notes);
3097 i1notes = copy_rtx_if_shared (i1notes);
3098 newpat = copy_rtx_if_shared (newpat);
3099 newi2pat = copy_rtx_if_shared (newi2pat);
3100 if (undobuf.other_insn)
3101 reset_used_flags (PATTERN (undobuf.other_insn));
3103 INSN_CODE (i3) = insn_code_number;
3104 PATTERN (i3) = newpat;
3106 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3108 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3110 reset_used_flags (call_usage);
3111 call_usage = copy_rtx (call_usage);
3114 replace_rtx (call_usage, i2dest, i2src);
3117 replace_rtx (call_usage, i1dest, i1src);
3119 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3122 if (undobuf.other_insn)
3123 INSN_CODE (undobuf.other_insn) = other_code_number;
3125 /* We had one special case above where I2 had more than one set and
3126 we replaced a destination of one of those sets with the destination
3127 of I3. In that case, we have to update LOG_LINKS of insns later
3128 in this basic block. Note that this (expensive) case is rare.
3130 Also, in this case, we must pretend that all REG_NOTEs for I2
3131 actually came from I3, so that REG_UNUSED notes from I2 will be
3132 properly handled. */
3134 if (i3_subst_into_i2)
3136 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3137 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3138 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3139 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3140 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3141 && ! find_reg_note (i2, REG_UNUSED,
3142 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3143 for (temp = NEXT_INSN (i2);
3144 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3145 || BB_HEAD (this_basic_block) != temp);
3146 temp = NEXT_INSN (temp))
3147 if (temp != i3 && INSN_P (temp))
3148 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3149 if (XEXP (link, 0) == i2)
3150 XEXP (link, 0) = i3;
3155 while (XEXP (link, 1))
3156 link = XEXP (link, 1);
3157 XEXP (link, 1) = i2notes;
3171 INSN_CODE (i2) = i2_code_number;
3172 PATTERN (i2) = newi2pat;
3175 SET_INSN_DELETED (i2);
3181 SET_INSN_DELETED (i1);
3184 /* Get death notes for everything that is now used in either I3 or
3185 I2 and used to die in a previous insn. If we built two new
3186 patterns, move from I1 to I2 then I2 to I3 so that we get the
3187 proper movement on registers that I2 modifies. */
3191 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3192 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3195 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3198 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3200 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3203 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3206 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3209 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3212 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3213 know these are REG_UNUSED and want them to go to the desired insn,
3214 so we always pass it as i3. We have not counted the notes in
3215 reg_n_deaths yet, so we need to do so now. */
3217 if (newi2pat && new_i2_notes)
3219 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3220 if (REG_P (XEXP (temp, 0)))
3221 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3223 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3228 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3229 if (REG_P (XEXP (temp, 0)))
3230 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3232 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3235 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3236 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3237 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3238 in that case, it might delete I2. Similarly for I2 and I1.
3239 Show an additional death due to the REG_DEAD note we make here. If
3240 we discard it in distribute_notes, we will decrement it again. */
3244 if (REG_P (i3dest_killed))
3245 REG_N_DEATHS (REGNO (i3dest_killed))++;
3247 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3248 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3250 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3252 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3254 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3258 if (i2dest_in_i2src)
3261 REG_N_DEATHS (REGNO (i2dest))++;
3263 if (newi2pat && reg_set_p (i2dest, newi2pat))
3264 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3265 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3267 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3268 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3269 NULL_RTX, NULL_RTX);
3272 if (i1dest_in_i1src)
3275 REG_N_DEATHS (REGNO (i1dest))++;
3277 if (newi2pat && reg_set_p (i1dest, newi2pat))
3278 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3279 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3281 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3282 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3283 NULL_RTX, NULL_RTX);
3286 distribute_links (i3links);
3287 distribute_links (i2links);
3288 distribute_links (i1links);
3293 rtx i2_insn = 0, i2_val = 0, set;
3295 /* The insn that used to set this register doesn't exist, and
3296 this life of the register may not exist either. See if one of
3297 I3's links points to an insn that sets I2DEST. If it does,
3298 that is now the last known value for I2DEST. If we don't update
3299 this and I2 set the register to a value that depended on its old
3300 contents, we will get confused. If this insn is used, thing
3301 will be set correctly in combine_instructions. */
3303 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3304 if ((set = single_set (XEXP (link, 0))) != 0
3305 && rtx_equal_p (i2dest, SET_DEST (set)))
3306 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3308 record_value_for_reg (i2dest, i2_insn, i2_val);
3310 /* If the reg formerly set in I2 died only once and that was in I3,
3311 zero its use count so it won't make `reload' do any work. */
3313 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3314 && ! i2dest_in_i2src)
3316 regno = REGNO (i2dest);
3317 REG_N_SETS (regno)--;
3321 if (i1 && REG_P (i1dest))
3324 rtx i1_insn = 0, i1_val = 0, set;
3326 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3327 if ((set = single_set (XEXP (link, 0))) != 0
3328 && rtx_equal_p (i1dest, SET_DEST (set)))
3329 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3331 record_value_for_reg (i1dest, i1_insn, i1_val);
3333 regno = REGNO (i1dest);
3334 if (! added_sets_1 && ! i1dest_in_i1src)
3335 REG_N_SETS (regno)--;
3338 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3339 been made to this insn. The order of
3340 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3341 can affect nonzero_bits of newpat */
3343 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3344 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3346 /* Set new_direct_jump_p if a new return or simple jump instruction
3349 If I3 is now an unconditional jump, ensure that it has a
3350 BARRIER following it since it may have initially been a
3351 conditional jump. It may also be the last nonnote insn. */
3353 if (returnjump_p (i3) || any_uncondjump_p (i3))
3355 *new_direct_jump_p = 1;
3356 mark_jump_label (PATTERN (i3), i3, 0);
3358 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3359 || !BARRIER_P (temp))
3360 emit_barrier_after (i3);
3363 if (undobuf.other_insn != NULL_RTX
3364 && (returnjump_p (undobuf.other_insn)
3365 || any_uncondjump_p (undobuf.other_insn)))
3367 *new_direct_jump_p = 1;
3369 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3370 || !BARRIER_P (temp))
3371 emit_barrier_after (undobuf.other_insn);
3374 /* An NOOP jump does not need barrier, but it does need cleaning up
3376 if (GET_CODE (newpat) == SET
3377 && SET_SRC (newpat) == pc_rtx
3378 && SET_DEST (newpat) == pc_rtx)
3379 *new_direct_jump_p = 1;
3382 combine_successes++;
3385 if (added_links_insn
3386 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3387 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3388 return added_links_insn;
3390 return newi2pat ? i2 : i3;
3393 /* Undo all the modifications recorded in undobuf. */
3398 struct undo *undo, *next;
3400 for (undo = undobuf.undos; undo; undo = next)
3406 *undo->where.r = undo->old_contents.r;
3409 *undo->where.i = undo->old_contents.i;
3412 PUT_MODE (*undo->where.r, undo->old_contents.m);
3418 undo->next = undobuf.frees;
3419 undobuf.frees = undo;
3425 /* We've committed to accepting the changes we made. Move all
3426 of the undos to the free list. */
3431 struct undo *undo, *next;
3433 for (undo = undobuf.undos; undo; undo = next)
3436 undo->next = undobuf.frees;
3437 undobuf.frees = undo;
3442 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3443 where we have an arithmetic expression and return that point. LOC will
3446 try_combine will call this function to see if an insn can be split into
3450 find_split_point (rtx *loc, rtx insn)
3453 enum rtx_code code = GET_CODE (x);
3455 unsigned HOST_WIDE_INT len = 0;
3456 HOST_WIDE_INT pos = 0;
3458 rtx inner = NULL_RTX;
3460 /* First special-case some codes. */
3464 #ifdef INSN_SCHEDULING
3465 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3467 if (MEM_P (SUBREG_REG (x)))
3470 return find_split_point (&SUBREG_REG (x), insn);
3474 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3475 using LO_SUM and HIGH. */
3476 if (GET_CODE (XEXP (x, 0)) == CONST
3477 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3480 gen_rtx_LO_SUM (Pmode,
3481 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3483 return &XEXP (XEXP (x, 0), 0);
3487 /* If we have a PLUS whose second operand is a constant and the
3488 address is not valid, perhaps will can split it up using
3489 the machine-specific way to split large constants. We use
3490 the first pseudo-reg (one of the virtual regs) as a placeholder;
3491 it will not remain in the result. */
3492 if (GET_CODE (XEXP (x, 0)) == PLUS
3493 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3494 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3496 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3497 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3500 /* This should have produced two insns, each of which sets our
3501 placeholder. If the source of the second is a valid address,
3502 we can make put both sources together and make a split point
3506 && NEXT_INSN (seq) != NULL_RTX
3507 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3508 && NONJUMP_INSN_P (seq)
3509 && GET_CODE (PATTERN (seq)) == SET
3510 && SET_DEST (PATTERN (seq)) == reg
3511 && ! reg_mentioned_p (reg,
3512 SET_SRC (PATTERN (seq)))
3513 && NONJUMP_INSN_P (NEXT_INSN (seq))
3514 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3515 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3516 && memory_address_p (GET_MODE (x),
3517 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3519 rtx src1 = SET_SRC (PATTERN (seq));
3520 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3522 /* Replace the placeholder in SRC2 with SRC1. If we can
3523 find where in SRC2 it was placed, that can become our
3524 split point and we can replace this address with SRC2.
3525 Just try two obvious places. */
3527 src2 = replace_rtx (src2, reg, src1);
3529 if (XEXP (src2, 0) == src1)
3530 split = &XEXP (src2, 0);
3531 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3532 && XEXP (XEXP (src2, 0), 0) == src1)
3533 split = &XEXP (XEXP (src2, 0), 0);
3537 SUBST (XEXP (x, 0), src2);
3542 /* If that didn't work, perhaps the first operand is complex and
3543 needs to be computed separately, so make a split point there.
3544 This will occur on machines that just support REG + CONST
3545 and have a constant moved through some previous computation. */
3547 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3548 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3549 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3550 return &XEXP (XEXP (x, 0), 0);
3556 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3557 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3558 we need to put the operand into a register. So split at that
3561 if (SET_DEST (x) == cc0_rtx
3562 && GET_CODE (SET_SRC (x)) != COMPARE
3563 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3564 && !OBJECT_P (SET_SRC (x))
3565 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3566 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3567 return &SET_SRC (x);
3570 /* See if we can split SET_SRC as it stands. */
3571 split = find_split_point (&SET_SRC (x), insn);
3572 if (split && split != &SET_SRC (x))
3575 /* See if we can split SET_DEST as it stands. */
3576 split = find_split_point (&SET_DEST (x), insn);
3577 if (split && split != &SET_DEST (x))
3580 /* See if this is a bitfield assignment with everything constant. If
3581 so, this is an IOR of an AND, so split it into that. */
3582 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3583 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3584 <= HOST_BITS_PER_WIDE_INT)
3585 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3586 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3587 && GET_CODE (SET_SRC (x)) == CONST_INT
3588 && ((INTVAL (XEXP (SET_DEST (x), 1))
3589 + INTVAL (XEXP (SET_DEST (x), 2)))
3590 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3591 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3593 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3594 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3595 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3596 rtx dest = XEXP (SET_DEST (x), 0);
3597 enum machine_mode mode = GET_MODE (dest);
3598 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3601 if (BITS_BIG_ENDIAN)
3602 pos = GET_MODE_BITSIZE (mode) - len - pos;
3604 or_mask = gen_int_mode (src << pos, mode);
3607 simplify_gen_binary (IOR, mode, dest, or_mask));
3610 rtx negmask = gen_int_mode (~(mask << pos), mode);
3612 simplify_gen_binary (IOR, mode,
3613 simplify_gen_binary (AND, mode,
3618 SUBST (SET_DEST (x), dest);
3620 split = find_split_point (&SET_SRC (x), insn);
3621 if (split && split != &SET_SRC (x))
3625 /* Otherwise, see if this is an operation that we can split into two.
3626 If so, try to split that. */
3627 code = GET_CODE (SET_SRC (x));
3632 /* If we are AND'ing with a large constant that is only a single
3633 bit and the result is only being used in a context where we
3634 need to know if it is zero or nonzero, replace it with a bit
3635 extraction. This will avoid the large constant, which might
3636 have taken more than one insn to make. If the constant were
3637 not a valid argument to the AND but took only one insn to make,
3638 this is no worse, but if it took more than one insn, it will
3641 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3642 && REG_P (XEXP (SET_SRC (x), 0))
3643 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3644 && REG_P (SET_DEST (x))
3645 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3646 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3647 && XEXP (*split, 0) == SET_DEST (x)
3648 && XEXP (*split, 1) == const0_rtx)
3650 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3651 XEXP (SET_SRC (x), 0),
3652 pos, NULL_RTX, 1, 1, 0, 0);
3653 if (extraction != 0)
3655 SUBST (SET_SRC (x), extraction);
3656 return find_split_point (loc, insn);
3662 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3663 is known to be on, this can be converted into a NEG of a shift. */
3664 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3665 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3666 && 1 <= (pos = exact_log2
3667 (nonzero_bits (XEXP (SET_SRC (x), 0),
3668 GET_MODE (XEXP (SET_SRC (x), 0))))))
3670 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3674 gen_rtx_LSHIFTRT (mode,
3675 XEXP (SET_SRC (x), 0),
3678 split = find_split_point (&SET_SRC (x), insn);
3679 if (split && split != &SET_SRC (x))
3685 inner = XEXP (SET_SRC (x), 0);
3687 /* We can't optimize if either mode is a partial integer
3688 mode as we don't know how many bits are significant
3690 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3691 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3695 len = GET_MODE_BITSIZE (GET_MODE (inner));
3701 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3702 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3704 inner = XEXP (SET_SRC (x), 0);
3705 len = INTVAL (XEXP (SET_SRC (x), 1));
3706 pos = INTVAL (XEXP (SET_SRC (x), 2));
3708 if (BITS_BIG_ENDIAN)
3709 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3710 unsignedp = (code == ZERO_EXTRACT);
3718 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3720 enum machine_mode mode = GET_MODE (SET_SRC (x));
3722 /* For unsigned, we have a choice of a shift followed by an
3723 AND or two shifts. Use two shifts for field sizes where the
3724 constant might be too large. We assume here that we can
3725 always at least get 8-bit constants in an AND insn, which is
3726 true for every current RISC. */
3728 if (unsignedp && len <= 8)
3733 (mode, gen_lowpart (mode, inner),
3735 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3737 split = find_split_point (&SET_SRC (x), insn);
3738 if (split && split != &SET_SRC (x))
3745 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3746 gen_rtx_ASHIFT (mode,
3747 gen_lowpart (mode, inner),
3748 GEN_INT (GET_MODE_BITSIZE (mode)
3750 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3752 split = find_split_point (&SET_SRC (x), insn);
3753 if (split && split != &SET_SRC (x))
3758 /* See if this is a simple operation with a constant as the second
3759 operand. It might be that this constant is out of range and hence
3760 could be used as a split point. */
3761 if (BINARY_P (SET_SRC (x))
3762 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3763 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3764 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3765 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3766 return &XEXP (SET_SRC (x), 1);
3768 /* Finally, see if this is a simple operation with its first operand
3769 not in a register. The operation might require this operand in a
3770 register, so return it as a split point. We can always do this
3771 because if the first operand were another operation, we would have
3772 already found it as a split point. */
3773 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3774 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3775 return &XEXP (SET_SRC (x), 0);
3781 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3782 it is better to write this as (not (ior A B)) so we can split it.
3783 Similarly for IOR. */
3784 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3787 gen_rtx_NOT (GET_MODE (x),
3788 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3790 XEXP (XEXP (x, 0), 0),
3791 XEXP (XEXP (x, 1), 0))));
3792 return find_split_point (loc, insn);
3795 /* Many RISC machines have a large set of logical insns. If the
3796 second operand is a NOT, put it first so we will try to split the
3797 other operand first. */
3798 if (GET_CODE (XEXP (x, 1)) == NOT)
3800 rtx tem = XEXP (x, 0);
3801 SUBST (XEXP (x, 0), XEXP (x, 1));
3802 SUBST (XEXP (x, 1), tem);
3810 /* Otherwise, select our actions depending on our rtx class. */
3811 switch (GET_RTX_CLASS (code))
3813 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3815 split = find_split_point (&XEXP (x, 2), insn);
3818 /* ... fall through ... */
3820 case RTX_COMM_ARITH:
3822 case RTX_COMM_COMPARE:
3823 split = find_split_point (&XEXP (x, 1), insn);
3826 /* ... fall through ... */
3828 /* Some machines have (and (shift ...) ...) insns. If X is not
3829 an AND, but XEXP (X, 0) is, use it as our split point. */
3830 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3831 return &XEXP (x, 0);
3833 split = find_split_point (&XEXP (x, 0), insn);
3839 /* Otherwise, we don't have a split point. */
3844 /* Throughout X, replace FROM with TO, and return the result.
3845 The result is TO if X is FROM;
3846 otherwise the result is X, but its contents may have been modified.
3847 If they were modified, a record was made in undobuf so that
3848 undo_all will (among other things) return X to its original state.
3850 If the number of changes necessary is too much to record to undo,
3851 the excess changes are not made, so the result is invalid.
3852 The changes already made can still be undone.
3853 undobuf.num_undo is incremented for such changes, so by testing that
3854 the caller can tell whether the result is valid.
3856 `n_occurrences' is incremented each time FROM is replaced.
3858 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3860 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3861 by copying if `n_occurrences' is nonzero. */
3864 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3866 enum rtx_code code = GET_CODE (x);
3867 enum machine_mode op0_mode = VOIDmode;
3872 /* Two expressions are equal if they are identical copies of a shared
3873 RTX or if they are both registers with the same register number
3876 #define COMBINE_RTX_EQUAL_P(X,Y) \
3878 || (REG_P (X) && REG_P (Y) \
3879 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3881 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3884 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3887 /* If X and FROM are the same register but different modes, they will
3888 not have been seen as equal above. However, flow.c will make a
3889 LOG_LINKS entry for that case. If we do nothing, we will try to
3890 rerecognize our original insn and, when it succeeds, we will
3891 delete the feeding insn, which is incorrect.
3893 So force this insn not to match in this (rare) case. */
3894 if (! in_dest && code == REG && REG_P (from)
3895 && REGNO (x) == REGNO (from))
3896 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3898 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3899 of which may contain things that can be combined. */
3900 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3903 /* It is possible to have a subexpression appear twice in the insn.
3904 Suppose that FROM is a register that appears within TO.
3905 Then, after that subexpression has been scanned once by `subst',
3906 the second time it is scanned, TO may be found. If we were
3907 to scan TO here, we would find FROM within it and create a
3908 self-referent rtl structure which is completely wrong. */
3909 if (COMBINE_RTX_EQUAL_P (x, to))
3912 /* Parallel asm_operands need special attention because all of the
3913 inputs are shared across the arms. Furthermore, unsharing the
3914 rtl results in recognition failures. Failure to handle this case
3915 specially can result in circular rtl.
3917 Solve this by doing a normal pass across the first entry of the
3918 parallel, and only processing the SET_DESTs of the subsequent
3921 if (code == PARALLEL
3922 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3923 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3925 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3927 /* If this substitution failed, this whole thing fails. */
3928 if (GET_CODE (new) == CLOBBER
3929 && XEXP (new, 0) == const0_rtx)
3932 SUBST (XVECEXP (x, 0, 0), new);
3934 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3936 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3939 && GET_CODE (dest) != CC0
3940 && GET_CODE (dest) != PC)
3942 new = subst (dest, from, to, 0, unique_copy);
3944 /* If this substitution failed, this whole thing fails. */
3945 if (GET_CODE (new) == CLOBBER
3946 && XEXP (new, 0) == const0_rtx)
3949 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3955 len = GET_RTX_LENGTH (code);
3956 fmt = GET_RTX_FORMAT (code);
3958 /* We don't need to process a SET_DEST that is a register, CC0,
3959 or PC, so set up to skip this common case. All other cases
3960 where we want to suppress replacing something inside a
3961 SET_SRC are handled via the IN_DEST operand. */
3963 && (REG_P (SET_DEST (x))
3964 || GET_CODE (SET_DEST (x)) == CC0
3965 || GET_CODE (SET_DEST (x)) == PC))
3968 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3971 op0_mode = GET_MODE (XEXP (x, 0));
3973 for (i = 0; i < len; i++)
3978 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3980 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3982 new = (unique_copy && n_occurrences
3983 ? copy_rtx (to) : to);
3988 new = subst (XVECEXP (x, i, j), from, to, 0,
3991 /* If this substitution failed, this whole thing
3993 if (GET_CODE (new) == CLOBBER
3994 && XEXP (new, 0) == const0_rtx)
3998 SUBST (XVECEXP (x, i, j), new);
4001 else if (fmt[i] == 'e')
4003 /* If this is a register being set, ignore it. */
4007 && (((code == SUBREG || code == ZERO_EXTRACT)
4009 || code == STRICT_LOW_PART))
4012 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4014 /* In general, don't install a subreg involving two
4015 modes not tieable. It can worsen register
4016 allocation, and can even make invalid reload
4017 insns, since the reg inside may need to be copied
4018 from in the outside mode, and that may be invalid
4019 if it is an fp reg copied in integer mode.
4021 We allow two exceptions to this: It is valid if
4022 it is inside another SUBREG and the mode of that
4023 SUBREG and the mode of the inside of TO is
4024 tieable and it is valid if X is a SET that copies
4027 if (GET_CODE (to) == SUBREG
4028 && ! MODES_TIEABLE_P (GET_MODE (to),
4029 GET_MODE (SUBREG_REG (to)))
4030 && ! (code == SUBREG
4031 && MODES_TIEABLE_P (GET_MODE (x),
4032 GET_MODE (SUBREG_REG (to))))
4034 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4037 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4039 #ifdef CANNOT_CHANGE_MODE_CLASS
4042 && REGNO (to) < FIRST_PSEUDO_REGISTER
4043 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4046 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4049 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4053 /* If we are in a SET_DEST, suppress most cases unless we
4054 have gone inside a MEM, in which case we want to
4055 simplify the address. We assume here that things that
4056 are actually part of the destination have their inner
4057 parts in the first expression. This is true for SUBREG,
4058 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4059 things aside from REG and MEM that should appear in a
4061 new = subst (XEXP (x, i), from, to,
4063 && (code == SUBREG || code == STRICT_LOW_PART
4064 || code == ZERO_EXTRACT))
4066 && i == 0), unique_copy);
4068 /* If we found that we will have to reject this combination,
4069 indicate that by returning the CLOBBER ourselves, rather than
4070 an expression containing it. This will speed things up as
4071 well as prevent accidents where two CLOBBERs are considered
4072 to be equal, thus producing an incorrect simplification. */
4074 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4077 if (GET_CODE (x) == SUBREG
4078 && (GET_CODE (new) == CONST_INT
4079 || GET_CODE (new) == CONST_DOUBLE))
4081 enum machine_mode mode = GET_MODE (x);
4083 x = simplify_subreg (GET_MODE (x), new,
4084 GET_MODE (SUBREG_REG (x)),
4087 x = gen_rtx_CLOBBER (mode, const0_rtx);
4089 else if (GET_CODE (new) == CONST_INT
4090 && GET_CODE (x) == ZERO_EXTEND)
4092 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4093 new, GET_MODE (XEXP (x, 0)));
4097 SUBST (XEXP (x, i), new);
4102 /* Try to simplify X. If the simplification changed the code, it is likely
4103 that further simplification will help, so loop, but limit the number
4104 of repetitions that will be performed. */
4106 for (i = 0; i < 4; i++)
4108 /* If X is sufficiently simple, don't bother trying to do anything
4110 if (code != CONST_INT && code != REG && code != CLOBBER)
4111 x = combine_simplify_rtx (x, op0_mode, in_dest);
4113 if (GET_CODE (x) == code)
4116 code = GET_CODE (x);
4118 /* We no longer know the original mode of operand 0 since we
4119 have changed the form of X) */
4120 op0_mode = VOIDmode;
4126 /* Simplify X, a piece of RTL. We just operate on the expression at the
4127 outer level; call `subst' to simplify recursively. Return the new
4130 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4131 if we are inside a SET_DEST. */
4134 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4136 enum rtx_code code = GET_CODE (x);
4137 enum machine_mode mode = GET_MODE (x);
4141 /* If this is a commutative operation, put a constant last and a complex
4142 expression first. We don't need to do this for comparisons here. */
4143 if (COMMUTATIVE_ARITH_P (x)
4144 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4147 SUBST (XEXP (x, 0), XEXP (x, 1));
4148 SUBST (XEXP (x, 1), temp);
4151 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4152 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4153 things. Check for cases where both arms are testing the same
4156 Don't do anything if all operands are very simple. */
4159 && ((!OBJECT_P (XEXP (x, 0))
4160 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4161 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4162 || (!OBJECT_P (XEXP (x, 1))
4163 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4164 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4166 && (!OBJECT_P (XEXP (x, 0))
4167 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4168 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4170 rtx cond, true_rtx, false_rtx;
4172 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4174 /* If everything is a comparison, what we have is highly unlikely
4175 to be simpler, so don't use it. */
4176 && ! (COMPARISON_P (x)
4177 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4179 rtx cop1 = const0_rtx;
4180 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4182 if (cond_code == NE && COMPARISON_P (cond))
4185 /* Simplify the alternative arms; this may collapse the true and
4186 false arms to store-flag values. Be careful to use copy_rtx
4187 here since true_rtx or false_rtx might share RTL with x as a
4188 result of the if_then_else_cond call above. */
4189 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4190 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4192 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4193 is unlikely to be simpler. */
4194 if (general_operand (true_rtx, VOIDmode)
4195 && general_operand (false_rtx, VOIDmode))
4197 enum rtx_code reversed;
4199 /* Restarting if we generate a store-flag expression will cause
4200 us to loop. Just drop through in this case. */
4202 /* If the result values are STORE_FLAG_VALUE and zero, we can
4203 just make the comparison operation. */
4204 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4205 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4207 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4208 && ((reversed = reversed_comparison_code_parts
4209 (cond_code, cond, cop1, NULL))
4211 x = simplify_gen_relational (reversed, mode, VOIDmode,
4214 /* Likewise, we can make the negate of a comparison operation
4215 if the result values are - STORE_FLAG_VALUE and zero. */
4216 else if (GET_CODE (true_rtx) == CONST_INT
4217 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4218 && false_rtx == const0_rtx)
4219 x = simplify_gen_unary (NEG, mode,
4220 simplify_gen_relational (cond_code,
4224 else if (GET_CODE (false_rtx) == CONST_INT
4225 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4226 && true_rtx == const0_rtx
4227 && ((reversed = reversed_comparison_code_parts
4228 (cond_code, cond, cop1, NULL))
4230 x = simplify_gen_unary (NEG, mode,
4231 simplify_gen_relational (reversed,
4236 return gen_rtx_IF_THEN_ELSE (mode,
4237 simplify_gen_relational (cond_code,
4242 true_rtx, false_rtx);
4244 code = GET_CODE (x);
4245 op0_mode = VOIDmode;
4250 /* Try to fold this expression in case we have constants that weren't
4253 switch (GET_RTX_CLASS (code))
4256 if (op0_mode == VOIDmode)
4257 op0_mode = GET_MODE (XEXP (x, 0));
4258 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4261 case RTX_COMM_COMPARE:
4263 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4264 if (cmp_mode == VOIDmode)
4266 cmp_mode = GET_MODE (XEXP (x, 1));
4267 if (cmp_mode == VOIDmode)
4268 cmp_mode = op0_mode;
4270 temp = simplify_relational_operation (code, mode, cmp_mode,
4271 XEXP (x, 0), XEXP (x, 1));
4274 case RTX_COMM_ARITH:
4276 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4278 case RTX_BITFIELD_OPS:
4280 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4281 XEXP (x, 1), XEXP (x, 2));
4290 code = GET_CODE (temp);
4291 op0_mode = VOIDmode;
4292 mode = GET_MODE (temp);
4295 /* First see if we can apply the inverse distributive law. */
4296 if (code == PLUS || code == MINUS
4297 || code == AND || code == IOR || code == XOR)
4299 x = apply_distributive_law (x);
4300 code = GET_CODE (x);
4301 op0_mode = VOIDmode;
4304 /* If CODE is an associative operation not otherwise handled, see if we
4305 can associate some operands. This can win if they are constants or
4306 if they are logically related (i.e. (a & b) & a). */
4307 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4308 || code == AND || code == IOR || code == XOR
4309 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4310 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4311 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4313 if (GET_CODE (XEXP (x, 0)) == code)
4315 rtx other = XEXP (XEXP (x, 0), 0);
4316 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4317 rtx inner_op1 = XEXP (x, 1);
4320 /* Make sure we pass the constant operand if any as the second
4321 one if this is a commutative operation. */
4322 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4324 rtx tem = inner_op0;
4325 inner_op0 = inner_op1;
4328 inner = simplify_binary_operation (code == MINUS ? PLUS
4329 : code == DIV ? MULT
4331 mode, inner_op0, inner_op1);
4333 /* For commutative operations, try the other pair if that one
4335 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4337 other = XEXP (XEXP (x, 0), 1);
4338 inner = simplify_binary_operation (code, mode,
4339 XEXP (XEXP (x, 0), 0),
4344 return simplify_gen_binary (code, mode, other, inner);
4348 /* A little bit of algebraic simplification here. */
4352 /* Ensure that our address has any ASHIFTs converted to MULT in case
4353 address-recognizing predicates are called later. */
4354 temp = make_compound_operation (XEXP (x, 0), MEM);
4355 SUBST (XEXP (x, 0), temp);
4359 if (op0_mode == VOIDmode)
4360 op0_mode = GET_MODE (SUBREG_REG (x));
4362 /* See if this can be moved to simplify_subreg. */
4363 if (CONSTANT_P (SUBREG_REG (x))
4364 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4365 /* Don't call gen_lowpart if the inner mode
4366 is VOIDmode and we cannot simplify it, as SUBREG without
4367 inner mode is invalid. */
4368 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4369 || gen_lowpart_common (mode, SUBREG_REG (x))))
4370 return gen_lowpart (mode, SUBREG_REG (x));
4372 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4376 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4382 /* Don't change the mode of the MEM if that would change the meaning
4384 if (MEM_P (SUBREG_REG (x))
4385 && (MEM_VOLATILE_P (SUBREG_REG (x))
4386 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4387 return gen_rtx_CLOBBER (mode, const0_rtx);
4389 /* Note that we cannot do any narrowing for non-constants since
4390 we might have been counting on using the fact that some bits were
4391 zero. We now do this in the SET. */
4396 temp = expand_compound_operation (XEXP (x, 0));
4398 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4399 replaced by (lshiftrt X C). This will convert
4400 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4402 if (GET_CODE (temp) == ASHIFTRT
4403 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4404 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4405 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4406 INTVAL (XEXP (temp, 1)));
4408 /* If X has only a single bit that might be nonzero, say, bit I, convert
4409 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4410 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4411 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4412 or a SUBREG of one since we'd be making the expression more
4413 complex if it was just a register. */
4416 && ! (GET_CODE (temp) == SUBREG
4417 && REG_P (SUBREG_REG (temp)))
4418 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4420 rtx temp1 = simplify_shift_const
4421 (NULL_RTX, ASHIFTRT, mode,
4422 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4423 GET_MODE_BITSIZE (mode) - 1 - i),
4424 GET_MODE_BITSIZE (mode) - 1 - i);
4426 /* If all we did was surround TEMP with the two shifts, we
4427 haven't improved anything, so don't use it. Otherwise,
4428 we are better off with TEMP1. */
4429 if (GET_CODE (temp1) != ASHIFTRT
4430 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4431 || XEXP (XEXP (temp1, 0), 0) != temp)
4437 /* We can't handle truncation to a partial integer mode here
4438 because we don't know the real bitsize of the partial
4440 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4443 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4444 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4445 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4447 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4448 GET_MODE_MASK (mode), 0));
4450 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4451 whose value is a comparison can be replaced with a subreg if
4452 STORE_FLAG_VALUE permits. */
4453 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4454 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4455 && (temp = get_last_value (XEXP (x, 0)))
4456 && COMPARISON_P (temp))
4457 return gen_lowpart (mode, XEXP (x, 0));
4462 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4463 using cc0, in which case we want to leave it as a COMPARE
4464 so we can distinguish it from a register-register-copy. */
4465 if (XEXP (x, 1) == const0_rtx)
4468 /* x - 0 is the same as x unless x's mode has signed zeros and
4469 allows rounding towards -infinity. Under those conditions,
4471 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4472 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4473 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4479 /* (const (const X)) can become (const X). Do it this way rather than
4480 returning the inner CONST since CONST can be shared with a
4482 if (GET_CODE (XEXP (x, 0)) == CONST)
4483 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4488 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4489 can add in an offset. find_split_point will split this address up
4490 again if it doesn't match. */
4491 if (GET_CODE (XEXP (x, 0)) == HIGH
4492 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4498 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4499 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4500 bit-field and can be replaced by either a sign_extend or a
4501 sign_extract. The `and' may be a zero_extend and the two
4502 <c>, -<c> constants may be reversed. */
4503 if (GET_CODE (XEXP (x, 0)) == XOR
4504 && GET_CODE (XEXP (x, 1)) == CONST_INT
4505 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4506 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4507 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4508 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4509 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4510 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4511 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4512 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4513 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4514 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4515 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4516 == (unsigned int) i + 1))))
4517 return simplify_shift_const
4518 (NULL_RTX, ASHIFTRT, mode,
4519 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4520 XEXP (XEXP (XEXP (x, 0), 0), 0),
4521 GET_MODE_BITSIZE (mode) - (i + 1)),
4522 GET_MODE_BITSIZE (mode) - (i + 1));
4524 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4525 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4526 the bitsize of the mode - 1. This allows simplification of
4527 "a = (b & 8) == 0;" */
4528 if (XEXP (x, 1) == constm1_rtx
4529 && !REG_P (XEXP (x, 0))
4530 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4531 && REG_P (SUBREG_REG (XEXP (x, 0))))
4532 && nonzero_bits (XEXP (x, 0), mode) == 1)
4533 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4534 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4535 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4536 GET_MODE_BITSIZE (mode) - 1),
4537 GET_MODE_BITSIZE (mode) - 1);
4539 /* If we are adding two things that have no bits in common, convert
4540 the addition into an IOR. This will often be further simplified,
4541 for example in cases like ((a & 1) + (a & 2)), which can
4544 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4545 && (nonzero_bits (XEXP (x, 0), mode)
4546 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4548 /* Try to simplify the expression further. */
4549 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4550 temp = combine_simplify_rtx (tor, mode, in_dest);
4552 /* If we could, great. If not, do not go ahead with the IOR
4553 replacement, since PLUS appears in many special purpose
4554 address arithmetic instructions. */
4555 if (GET_CODE (temp) != CLOBBER && temp != tor)
4561 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4562 (and <foo> (const_int pow2-1)) */
4563 if (GET_CODE (XEXP (x, 1)) == AND
4564 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4565 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4566 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4567 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4568 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4572 /* If we have (mult (plus A B) C), apply the distributive law and then
4573 the inverse distributive law to see if things simplify. This
4574 occurs mostly in addresses, often when unrolling loops. */
4576 if (GET_CODE (XEXP (x, 0)) == PLUS)
4578 rtx result = distribute_and_simplify_rtx (x, 0);
4583 /* Try simplify a*(b/c) as (a*b)/c. */
4584 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4585 && GET_CODE (XEXP (x, 0)) == DIV)
4587 rtx tem = simplify_binary_operation (MULT, mode,
4588 XEXP (XEXP (x, 0), 0),
4591 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4596 /* If this is a divide by a power of two, treat it as a shift if
4597 its first operand is a shift. */
4598 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4599 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4600 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4601 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4602 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4603 || GET_CODE (XEXP (x, 0)) == ROTATE
4604 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4605 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4609 case GT: case GTU: case GE: case GEU:
4610 case LT: case LTU: case LE: case LEU:
4611 case UNEQ: case LTGT:
4612 case UNGT: case UNGE:
4613 case UNLT: case UNLE:
4614 case UNORDERED: case ORDERED:
4615 /* If the first operand is a condition code, we can't do anything
4617 if (GET_CODE (XEXP (x, 0)) == COMPARE
4618 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4619 && ! CC0_P (XEXP (x, 0))))
4621 rtx op0 = XEXP (x, 0);
4622 rtx op1 = XEXP (x, 1);
4623 enum rtx_code new_code;
4625 if (GET_CODE (op0) == COMPARE)
4626 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4628 /* Simplify our comparison, if possible. */
4629 new_code = simplify_comparison (code, &op0, &op1);
4631 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4632 if only the low-order bit is possibly nonzero in X (such as when
4633 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4634 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4635 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4638 Remove any ZERO_EXTRACT we made when thinking this was a
4639 comparison. It may now be simpler to use, e.g., an AND. If a
4640 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4641 the call to make_compound_operation in the SET case. */
4643 if (STORE_FLAG_VALUE == 1
4644 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4645 && op1 == const0_rtx
4646 && mode == GET_MODE (op0)
4647 && nonzero_bits (op0, mode) == 1)
4648 return gen_lowpart (mode,
4649 expand_compound_operation (op0));
4651 else if (STORE_FLAG_VALUE == 1
4652 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4653 && op1 == const0_rtx
4654 && mode == GET_MODE (op0)
4655 && (num_sign_bit_copies (op0, mode)
4656 == GET_MODE_BITSIZE (mode)))
4658 op0 = expand_compound_operation (op0);
4659 return simplify_gen_unary (NEG, mode,
4660 gen_lowpart (mode, op0),
4664 else if (STORE_FLAG_VALUE == 1
4665 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4666 && op1 == const0_rtx
4667 && mode == GET_MODE (op0)
4668 && nonzero_bits (op0, mode) == 1)
4670 op0 = expand_compound_operation (op0);
4671 return simplify_gen_binary (XOR, mode,
4672 gen_lowpart (mode, op0),
4676 else if (STORE_FLAG_VALUE == 1
4677 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4678 && op1 == const0_rtx
4679 && mode == GET_MODE (op0)
4680 && (num_sign_bit_copies (op0, mode)
4681 == GET_MODE_BITSIZE (mode)))
4683 op0 = expand_compound_operation (op0);
4684 return plus_constant (gen_lowpart (mode, op0), 1);
4687 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4689 if (STORE_FLAG_VALUE == -1
4690 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4691 && op1 == const0_rtx
4692 && (num_sign_bit_copies (op0, mode)
4693 == GET_MODE_BITSIZE (mode)))
4694 return gen_lowpart (mode,
4695 expand_compound_operation (op0));
4697 else if (STORE_FLAG_VALUE == -1
4698 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4699 && op1 == const0_rtx
4700 && mode == GET_MODE (op0)
4701 && nonzero_bits (op0, mode) == 1)
4703 op0 = expand_compound_operation (op0);
4704 return simplify_gen_unary (NEG, mode,
4705 gen_lowpart (mode, op0),
4709 else if (STORE_FLAG_VALUE == -1
4710 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4711 && op1 == const0_rtx
4712 && mode == GET_MODE (op0)
4713 && (num_sign_bit_copies (op0, mode)
4714 == GET_MODE_BITSIZE (mode)))
4716 op0 = expand_compound_operation (op0);
4717 return simplify_gen_unary (NOT, mode,
4718 gen_lowpart (mode, op0),
4722 /* If X is 0/1, (eq X 0) is X-1. */
4723 else if (STORE_FLAG_VALUE == -1
4724 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4725 && op1 == const0_rtx
4726 && mode == GET_MODE (op0)
4727 && nonzero_bits (op0, mode) == 1)
4729 op0 = expand_compound_operation (op0);
4730 return plus_constant (gen_lowpart (mode, op0), -1);
4733 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4734 one bit that might be nonzero, we can convert (ne x 0) to
4735 (ashift x c) where C puts the bit in the sign bit. Remove any
4736 AND with STORE_FLAG_VALUE when we are done, since we are only
4737 going to test the sign bit. */
4738 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4739 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4740 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4741 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4742 && op1 == const0_rtx
4743 && mode == GET_MODE (op0)
4744 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4746 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4747 expand_compound_operation (op0),
4748 GET_MODE_BITSIZE (mode) - 1 - i);
4749 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4755 /* If the code changed, return a whole new comparison. */
4756 if (new_code != code)
4757 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4759 /* Otherwise, keep this operation, but maybe change its operands.
4760 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4761 SUBST (XEXP (x, 0), op0);
4762 SUBST (XEXP (x, 1), op1);
4767 return simplify_if_then_else (x);
4773 /* If we are processing SET_DEST, we are done. */
4777 return expand_compound_operation (x);
4780 return simplify_set (x);
4784 return simplify_logical (x);
4791 /* If this is a shift by a constant amount, simplify it. */
4792 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4793 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4794 INTVAL (XEXP (x, 1)));
4796 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4798 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4800 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4812 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4815 simplify_if_then_else (rtx x)
4817 enum machine_mode mode = GET_MODE (x);
4818 rtx cond = XEXP (x, 0);
4819 rtx true_rtx = XEXP (x, 1);
4820 rtx false_rtx = XEXP (x, 2);
4821 enum rtx_code true_code = GET_CODE (cond);
4822 int comparison_p = COMPARISON_P (cond);
4825 enum rtx_code false_code;
4828 /* Simplify storing of the truth value. */
4829 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4830 return simplify_gen_relational (true_code, mode, VOIDmode,
4831 XEXP (cond, 0), XEXP (cond, 1));
4833 /* Also when the truth value has to be reversed. */
4835 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4836 && (reversed = reversed_comparison (cond, mode)))
4839 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4840 in it is being compared against certain values. Get the true and false
4841 comparisons and see if that says anything about the value of each arm. */
4844 && ((false_code = reversed_comparison_code (cond, NULL))
4846 && REG_P (XEXP (cond, 0)))
4849 rtx from = XEXP (cond, 0);
4850 rtx true_val = XEXP (cond, 1);
4851 rtx false_val = true_val;
4854 /* If FALSE_CODE is EQ, swap the codes and arms. */
4856 if (false_code == EQ)
4858 swapped = 1, true_code = EQ, false_code = NE;
4859 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4862 /* If we are comparing against zero and the expression being tested has
4863 only a single bit that might be nonzero, that is its value when it is
4864 not equal to zero. Similarly if it is known to be -1 or 0. */
4866 if (true_code == EQ && true_val == const0_rtx
4867 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4868 false_code = EQ, false_val = GEN_INT (nzb);
4869 else if (true_code == EQ && true_val == const0_rtx
4870 && (num_sign_bit_copies (from, GET_MODE (from))
4871 == GET_MODE_BITSIZE (GET_MODE (from))))
4872 false_code = EQ, false_val = constm1_rtx;
4874 /* Now simplify an arm if we know the value of the register in the
4875 branch and it is used in the arm. Be careful due to the potential
4876 of locally-shared RTL. */
4878 if (reg_mentioned_p (from, true_rtx))
4879 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4881 pc_rtx, pc_rtx, 0, 0);
4882 if (reg_mentioned_p (from, false_rtx))
4883 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4885 pc_rtx, pc_rtx, 0, 0);
4887 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4888 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4890 true_rtx = XEXP (x, 1);
4891 false_rtx = XEXP (x, 2);
4892 true_code = GET_CODE (cond);
4895 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4896 reversed, do so to avoid needing two sets of patterns for
4897 subtract-and-branch insns. Similarly if we have a constant in the true
4898 arm, the false arm is the same as the first operand of the comparison, or
4899 the false arm is more complicated than the true arm. */
4902 && reversed_comparison_code (cond, NULL) != UNKNOWN
4903 && (true_rtx == pc_rtx
4904 || (CONSTANT_P (true_rtx)
4905 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4906 || true_rtx == const0_rtx
4907 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4908 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4909 && !OBJECT_P (false_rtx))
4910 || reg_mentioned_p (true_rtx, false_rtx)
4911 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4913 true_code = reversed_comparison_code (cond, NULL);
4914 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4915 SUBST (XEXP (x, 1), false_rtx);
4916 SUBST (XEXP (x, 2), true_rtx);
4918 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4921 /* It is possible that the conditional has been simplified out. */
4922 true_code = GET_CODE (cond);
4923 comparison_p = COMPARISON_P (cond);
4926 /* If the two arms are identical, we don't need the comparison. */
4928 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4931 /* Convert a == b ? b : a to "a". */
4932 if (true_code == EQ && ! side_effects_p (cond)
4933 && !HONOR_NANS (mode)
4934 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4935 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4937 else if (true_code == NE && ! side_effects_p (cond)
4938 && !HONOR_NANS (mode)
4939 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4940 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4943 /* Look for cases where we have (abs x) or (neg (abs X)). */
4945 if (GET_MODE_CLASS (mode) == MODE_INT
4946 && GET_CODE (false_rtx) == NEG
4947 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4949 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4950 && ! side_effects_p (true_rtx))
4955 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4959 simplify_gen_unary (NEG, mode,
4960 simplify_gen_unary (ABS, mode, true_rtx, mode),
4966 /* Look for MIN or MAX. */
4968 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4970 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4971 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4972 && ! side_effects_p (cond))
4977 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4980 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4983 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4986 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4991 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4992 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4993 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4994 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4995 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4996 neither 1 or -1, but it isn't worth checking for. */
4998 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5000 && GET_MODE_CLASS (mode) == MODE_INT
5001 && ! side_effects_p (x))
5003 rtx t = make_compound_operation (true_rtx, SET);
5004 rtx f = make_compound_operation (false_rtx, SET);
5005 rtx cond_op0 = XEXP (cond, 0);
5006 rtx cond_op1 = XEXP (cond, 1);
5007 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5008 enum machine_mode m = mode;
5009 rtx z = 0, c1 = NULL_RTX;
5011 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5012 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5013 || GET_CODE (t) == ASHIFT
5014 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5015 && rtx_equal_p (XEXP (t, 0), f))
5016 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5018 /* If an identity-zero op is commutative, check whether there
5019 would be a match if we swapped the operands. */
5020 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5021 || GET_CODE (t) == XOR)
5022 && rtx_equal_p (XEXP (t, 1), f))
5023 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5024 else if (GET_CODE (t) == SIGN_EXTEND
5025 && (GET_CODE (XEXP (t, 0)) == PLUS
5026 || GET_CODE (XEXP (t, 0)) == MINUS
5027 || GET_CODE (XEXP (t, 0)) == IOR
5028 || GET_CODE (XEXP (t, 0)) == XOR
5029 || GET_CODE (XEXP (t, 0)) == ASHIFT
5030 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5031 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5032 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5033 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5034 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5035 && (num_sign_bit_copies (f, GET_MODE (f))
5037 (GET_MODE_BITSIZE (mode)
5038 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5040 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5041 extend_op = SIGN_EXTEND;
5042 m = GET_MODE (XEXP (t, 0));
5044 else if (GET_CODE (t) == SIGN_EXTEND
5045 && (GET_CODE (XEXP (t, 0)) == PLUS
5046 || GET_CODE (XEXP (t, 0)) == IOR
5047 || GET_CODE (XEXP (t, 0)) == XOR)
5048 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5049 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5050 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5051 && (num_sign_bit_copies (f, GET_MODE (f))
5053 (GET_MODE_BITSIZE (mode)
5054 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5056 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5057 extend_op = SIGN_EXTEND;
5058 m = GET_MODE (XEXP (t, 0));
5060 else if (GET_CODE (t) == ZERO_EXTEND
5061 && (GET_CODE (XEXP (t, 0)) == PLUS
5062 || GET_CODE (XEXP (t, 0)) == MINUS
5063 || GET_CODE (XEXP (t, 0)) == IOR
5064 || GET_CODE (XEXP (t, 0)) == XOR
5065 || GET_CODE (XEXP (t, 0)) == ASHIFT
5066 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5067 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5068 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5069 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5070 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5071 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5072 && ((nonzero_bits (f, GET_MODE (f))
5073 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5076 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5077 extend_op = ZERO_EXTEND;
5078 m = GET_MODE (XEXP (t, 0));
5080 else if (GET_CODE (t) == ZERO_EXTEND
5081 && (GET_CODE (XEXP (t, 0)) == PLUS
5082 || GET_CODE (XEXP (t, 0)) == IOR
5083 || GET_CODE (XEXP (t, 0)) == XOR)
5084 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5085 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5086 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5087 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5088 && ((nonzero_bits (f, GET_MODE (f))
5089 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5092 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5093 extend_op = ZERO_EXTEND;
5094 m = GET_MODE (XEXP (t, 0));
5099 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5100 cond_op0, cond_op1),
5101 pc_rtx, pc_rtx, 0, 0);
5102 temp = simplify_gen_binary (MULT, m, temp,
5103 simplify_gen_binary (MULT, m, c1,
5105 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5106 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5108 if (extend_op != UNKNOWN)
5109 temp = simplify_gen_unary (extend_op, mode, temp, m);
5115 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5116 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5117 negation of a single bit, we can convert this operation to a shift. We
5118 can actually do this more generally, but it doesn't seem worth it. */
5120 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5121 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5122 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5123 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5124 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5125 == GET_MODE_BITSIZE (mode))
5126 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5128 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5129 gen_lowpart (mode, XEXP (cond, 0)), i);
5131 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5132 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5133 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5134 && GET_MODE (XEXP (cond, 0)) == mode
5135 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5136 == nonzero_bits (XEXP (cond, 0), mode)
5137 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5138 return XEXP (cond, 0);
5143 /* Simplify X, a SET expression. Return the new expression. */
5146 simplify_set (rtx x)
5148 rtx src = SET_SRC (x);
5149 rtx dest = SET_DEST (x);
5150 enum machine_mode mode
5151 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5155 /* (set (pc) (return)) gets written as (return). */
5156 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5159 /* Now that we know for sure which bits of SRC we are using, see if we can
5160 simplify the expression for the object knowing that we only need the
5163 if (GET_MODE_CLASS (mode) == MODE_INT
5164 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5166 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5167 SUBST (SET_SRC (x), src);
5170 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5171 the comparison result and try to simplify it unless we already have used
5172 undobuf.other_insn. */
5173 if ((GET_MODE_CLASS (mode) == MODE_CC
5174 || GET_CODE (src) == COMPARE
5176 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5177 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5178 && COMPARISON_P (*cc_use)
5179 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5181 enum rtx_code old_code = GET_CODE (*cc_use);
5182 enum rtx_code new_code;
5184 int other_changed = 0;
5185 enum machine_mode compare_mode = GET_MODE (dest);
5187 if (GET_CODE (src) == COMPARE)
5188 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5190 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5192 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5195 new_code = old_code;
5196 else if (!CONSTANT_P (tmp))
5198 new_code = GET_CODE (tmp);
5199 op0 = XEXP (tmp, 0);
5200 op1 = XEXP (tmp, 1);
5204 rtx pat = PATTERN (other_insn);
5205 undobuf.other_insn = other_insn;
5206 SUBST (*cc_use, tmp);
5208 /* Attempt to simplify CC user. */
5209 if (GET_CODE (pat) == SET)
5211 rtx new = simplify_rtx (SET_SRC (pat));
5212 if (new != NULL_RTX)
5213 SUBST (SET_SRC (pat), new);
5216 /* Convert X into a no-op move. */
5217 SUBST (SET_DEST (x), pc_rtx);
5218 SUBST (SET_SRC (x), pc_rtx);
5222 /* Simplify our comparison, if possible. */
5223 new_code = simplify_comparison (new_code, &op0, &op1);
5225 #ifdef SELECT_CC_MODE
5226 /* If this machine has CC modes other than CCmode, check to see if we
5227 need to use a different CC mode here. */
5228 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5229 compare_mode = GET_MODE (op0);
5231 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5234 /* If the mode changed, we have to change SET_DEST, the mode in the
5235 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5236 a hard register, just build new versions with the proper mode. If it
5237 is a pseudo, we lose unless it is only time we set the pseudo, in
5238 which case we can safely change its mode. */
5239 if (compare_mode != GET_MODE (dest))
5241 if (can_change_dest_mode (dest, 0, compare_mode))
5243 unsigned int regno = REGNO (dest);
5246 if (regno < FIRST_PSEUDO_REGISTER)
5247 new_dest = gen_rtx_REG (compare_mode, regno);
5250 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5251 new_dest = regno_reg_rtx[regno];
5254 SUBST (SET_DEST (x), new_dest);
5255 SUBST (XEXP (*cc_use, 0), new_dest);
5262 #endif /* SELECT_CC_MODE */
5264 /* If the code changed, we have to build a new comparison in
5265 undobuf.other_insn. */
5266 if (new_code != old_code)
5268 int other_changed_previously = other_changed;
5269 unsigned HOST_WIDE_INT mask;
5271 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5275 /* If the only change we made was to change an EQ into an NE or
5276 vice versa, OP0 has only one bit that might be nonzero, and OP1
5277 is zero, check if changing the user of the condition code will
5278 produce a valid insn. If it won't, we can keep the original code
5279 in that insn by surrounding our operation with an XOR. */
5281 if (((old_code == NE && new_code == EQ)
5282 || (old_code == EQ && new_code == NE))
5283 && ! other_changed_previously && op1 == const0_rtx
5284 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5285 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5287 rtx pat = PATTERN (other_insn), note = 0;
5289 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5290 && ! check_asm_operands (pat)))
5292 PUT_CODE (*cc_use, old_code);
5295 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5296 op0, GEN_INT (mask));
5302 undobuf.other_insn = other_insn;
5305 /* If we are now comparing against zero, change our source if
5306 needed. If we do not use cc0, we always have a COMPARE. */
5307 if (op1 == const0_rtx && dest == cc0_rtx)
5309 SUBST (SET_SRC (x), op0);
5315 /* Otherwise, if we didn't previously have a COMPARE in the
5316 correct mode, we need one. */
5317 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5319 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5322 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5324 SUBST(SET_SRC (x), op0);
5329 /* Otherwise, update the COMPARE if needed. */
5330 SUBST (XEXP (src, 0), op0);
5331 SUBST (XEXP (src, 1), op1);
5336 /* Get SET_SRC in a form where we have placed back any
5337 compound expressions. Then do the checks below. */
5338 src = make_compound_operation (src, SET);
5339 SUBST (SET_SRC (x), src);
5342 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5343 and X being a REG or (subreg (reg)), we may be able to convert this to
5344 (set (subreg:m2 x) (op)).
5346 We can always do this if M1 is narrower than M2 because that means that
5347 we only care about the low bits of the result.
5349 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5350 perform a narrower operation than requested since the high-order bits will
5351 be undefined. On machine where it is defined, this transformation is safe
5352 as long as M1 and M2 have the same number of words. */
5354 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5355 && !OBJECT_P (SUBREG_REG (src))
5356 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5358 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5359 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5360 #ifndef WORD_REGISTER_OPERATIONS
5361 && (GET_MODE_SIZE (GET_MODE (src))
5362 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5364 #ifdef CANNOT_CHANGE_MODE_CLASS
5365 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5366 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5367 GET_MODE (SUBREG_REG (src)),
5371 || (GET_CODE (dest) == SUBREG
5372 && REG_P (SUBREG_REG (dest)))))
5374 SUBST (SET_DEST (x),
5375 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5377 SUBST (SET_SRC (x), SUBREG_REG (src));
5379 src = SET_SRC (x), dest = SET_DEST (x);
5383 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5386 && GET_CODE (src) == SUBREG
5387 && subreg_lowpart_p (src)
5388 && (GET_MODE_BITSIZE (GET_MODE (src))
5389 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5391 rtx inner = SUBREG_REG (src);
5392 enum machine_mode inner_mode = GET_MODE (inner);
5394 /* Here we make sure that we don't have a sign bit on. */
5395 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5396 && (nonzero_bits (inner, inner_mode)
5397 < ((unsigned HOST_WIDE_INT) 1
5398 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5400 SUBST (SET_SRC (x), inner);
5406 #ifdef LOAD_EXTEND_OP
5407 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5408 would require a paradoxical subreg. Replace the subreg with a
5409 zero_extend to avoid the reload that would otherwise be required. */
5411 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5412 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5413 && SUBREG_BYTE (src) == 0
5414 && (GET_MODE_SIZE (GET_MODE (src))
5415 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5416 && MEM_P (SUBREG_REG (src)))
5419 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5420 GET_MODE (src), SUBREG_REG (src)));
5426 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5427 are comparing an item known to be 0 or -1 against 0, use a logical
5428 operation instead. Check for one of the arms being an IOR of the other
5429 arm with some value. We compute three terms to be IOR'ed together. In
5430 practice, at most two will be nonzero. Then we do the IOR's. */
5432 if (GET_CODE (dest) != PC
5433 && GET_CODE (src) == IF_THEN_ELSE
5434 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5435 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5436 && XEXP (XEXP (src, 0), 1) == const0_rtx
5437 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5438 #ifdef HAVE_conditional_move
5439 && ! can_conditionally_move_p (GET_MODE (src))
5441 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5442 GET_MODE (XEXP (XEXP (src, 0), 0)))
5443 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5444 && ! side_effects_p (src))
5446 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5447 ? XEXP (src, 1) : XEXP (src, 2));
5448 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5449 ? XEXP (src, 2) : XEXP (src, 1));
5450 rtx term1 = const0_rtx, term2, term3;
5452 if (GET_CODE (true_rtx) == IOR
5453 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5454 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5455 else if (GET_CODE (true_rtx) == IOR
5456 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5457 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5458 else if (GET_CODE (false_rtx) == IOR
5459 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5460 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5461 else if (GET_CODE (false_rtx) == IOR
5462 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5463 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5465 term2 = simplify_gen_binary (AND, GET_MODE (src),
5466 XEXP (XEXP (src, 0), 0), true_rtx);
5467 term3 = simplify_gen_binary (AND, GET_MODE (src),
5468 simplify_gen_unary (NOT, GET_MODE (src),
5469 XEXP (XEXP (src, 0), 0),
5474 simplify_gen_binary (IOR, GET_MODE (src),
5475 simplify_gen_binary (IOR, GET_MODE (src),
5482 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5483 whole thing fail. */
5484 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5486 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5489 /* Convert this into a field assignment operation, if possible. */
5490 return make_field_assignment (x);
5493 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5497 simplify_logical (rtx x)
5499 enum machine_mode mode = GET_MODE (x);
5500 rtx op0 = XEXP (x, 0);
5501 rtx op1 = XEXP (x, 1);
5503 switch (GET_CODE (x))
5506 /* We can call simplify_and_const_int only if we don't lose
5507 any (sign) bits when converting INTVAL (op1) to
5508 "unsigned HOST_WIDE_INT". */
5509 if (GET_CODE (op1) == CONST_INT
5510 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5511 || INTVAL (op1) > 0))
5513 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5514 if (GET_CODE (x) != AND)
5521 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5522 apply the distributive law and then the inverse distributive
5523 law to see if things simplify. */
5524 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5526 rtx result = distribute_and_simplify_rtx (x, 0);
5530 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5532 rtx result = distribute_and_simplify_rtx (x, 1);
5539 /* If we have (ior (and A B) C), apply the distributive law and then
5540 the inverse distributive law to see if things simplify. */
5542 if (GET_CODE (op0) == AND)
5544 rtx result = distribute_and_simplify_rtx (x, 0);
5549 if (GET_CODE (op1) == AND)
5551 rtx result = distribute_and_simplify_rtx (x, 1);
5564 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5565 operations" because they can be replaced with two more basic operations.
5566 ZERO_EXTEND is also considered "compound" because it can be replaced with
5567 an AND operation, which is simpler, though only one operation.
5569 The function expand_compound_operation is called with an rtx expression
5570 and will convert it to the appropriate shifts and AND operations,
5571 simplifying at each stage.
5573 The function make_compound_operation is called to convert an expression
5574 consisting of shifts and ANDs into the equivalent compound expression.
5575 It is the inverse of this function, loosely speaking. */
5578 expand_compound_operation (rtx x)
5580 unsigned HOST_WIDE_INT pos = 0, len;
5582 unsigned int modewidth;
5585 switch (GET_CODE (x))
5590 /* We can't necessarily use a const_int for a multiword mode;
5591 it depends on implicitly extending the value.
5592 Since we don't know the right way to extend it,
5593 we can't tell whether the implicit way is right.
5595 Even for a mode that is no wider than a const_int,
5596 we can't win, because we need to sign extend one of its bits through
5597 the rest of it, and we don't know which bit. */
5598 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5601 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5602 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5603 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5604 reloaded. If not for that, MEM's would very rarely be safe.
5606 Reject MODEs bigger than a word, because we might not be able
5607 to reference a two-register group starting with an arbitrary register
5608 (and currently gen_lowpart might crash for a SUBREG). */
5610 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5613 /* Reject MODEs that aren't scalar integers because turning vector
5614 or complex modes into shifts causes problems. */
5616 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5619 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5620 /* If the inner object has VOIDmode (the only way this can happen
5621 is if it is an ASM_OPERANDS), we can't do anything since we don't
5622 know how much masking to do. */
5631 /* ... fall through ... */
5634 /* If the operand is a CLOBBER, just return it. */
5635 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5638 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5639 || GET_CODE (XEXP (x, 2)) != CONST_INT
5640 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5643 /* Reject MODEs that aren't scalar integers because turning vector
5644 or complex modes into shifts causes problems. */
5646 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5649 len = INTVAL (XEXP (x, 1));
5650 pos = INTVAL (XEXP (x, 2));
5652 /* This should stay within the object being extracted, fail otherwise. */
5653 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5656 if (BITS_BIG_ENDIAN)
5657 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5664 /* Convert sign extension to zero extension, if we know that the high
5665 bit is not set, as this is easier to optimize. It will be converted
5666 back to cheaper alternative in make_extraction. */
5667 if (GET_CODE (x) == SIGN_EXTEND
5668 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5669 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5670 & ~(((unsigned HOST_WIDE_INT)
5671 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5675 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5676 rtx temp2 = expand_compound_operation (temp);
5678 /* Make sure this is a profitable operation. */
5679 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5681 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5687 /* We can optimize some special cases of ZERO_EXTEND. */
5688 if (GET_CODE (x) == ZERO_EXTEND)
5690 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5691 know that the last value didn't have any inappropriate bits
5693 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5694 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5695 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5696 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5697 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5698 return XEXP (XEXP (x, 0), 0);
5700 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5701 if (GET_CODE (XEXP (x, 0)) == SUBREG
5702 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5703 && subreg_lowpart_p (XEXP (x, 0))
5704 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5705 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5706 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5707 return SUBREG_REG (XEXP (x, 0));
5709 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5710 is a comparison and STORE_FLAG_VALUE permits. This is like
5711 the first case, but it works even when GET_MODE (x) is larger
5712 than HOST_WIDE_INT. */
5713 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5714 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5715 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5716 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5717 <= HOST_BITS_PER_WIDE_INT)
5718 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5719 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5720 return XEXP (XEXP (x, 0), 0);
5722 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5723 if (GET_CODE (XEXP (x, 0)) == SUBREG
5724 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5725 && subreg_lowpart_p (XEXP (x, 0))
5726 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5727 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5728 <= HOST_BITS_PER_WIDE_INT)
5729 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5730 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5731 return SUBREG_REG (XEXP (x, 0));
5735 /* If we reach here, we want to return a pair of shifts. The inner
5736 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5737 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5738 logical depending on the value of UNSIGNEDP.
5740 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5741 converted into an AND of a shift.
5743 We must check for the case where the left shift would have a negative
5744 count. This can happen in a case like (x >> 31) & 255 on machines
5745 that can't shift by a constant. On those machines, we would first
5746 combine the shift with the AND to produce a variable-position
5747 extraction. Then the constant of 31 would be substituted in to produce
5748 a such a position. */
5750 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5751 if (modewidth + len >= pos)
5753 enum machine_mode mode = GET_MODE (x);
5754 tem = gen_lowpart (mode, XEXP (x, 0));
5755 if (!tem || GET_CODE (tem) == CLOBBER)
5757 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5758 tem, modewidth - pos - len);
5759 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5760 mode, tem, modewidth - len);
5762 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5763 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5764 simplify_shift_const (NULL_RTX, LSHIFTRT,
5767 ((HOST_WIDE_INT) 1 << len) - 1);
5769 /* Any other cases we can't handle. */
5772 /* If we couldn't do this for some reason, return the original
5774 if (GET_CODE (tem) == CLOBBER)
5780 /* X is a SET which contains an assignment of one object into
5781 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5782 or certain SUBREGS). If possible, convert it into a series of
5785 We half-heartedly support variable positions, but do not at all
5786 support variable lengths. */
5789 expand_field_assignment (rtx x)
5792 rtx pos; /* Always counts from low bit. */
5794 rtx mask, cleared, masked;
5795 enum machine_mode compute_mode;
5797 /* Loop until we find something we can't simplify. */
5800 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5801 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5803 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5804 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5805 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5807 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5808 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5810 inner = XEXP (SET_DEST (x), 0);
5811 len = INTVAL (XEXP (SET_DEST (x), 1));
5812 pos = XEXP (SET_DEST (x), 2);
5814 /* A constant position should stay within the width of INNER. */
5815 if (GET_CODE (pos) == CONST_INT
5816 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5819 if (BITS_BIG_ENDIAN)
5821 if (GET_CODE (pos) == CONST_INT)
5822 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5824 else if (GET_CODE (pos) == MINUS
5825 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5826 && (INTVAL (XEXP (pos, 1))
5827 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5828 /* If position is ADJUST - X, new position is X. */
5829 pos = XEXP (pos, 0);
5831 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5832 GEN_INT (GET_MODE_BITSIZE (
5839 /* A SUBREG between two modes that occupy the same numbers of words
5840 can be done by moving the SUBREG to the source. */
5841 else if (GET_CODE (SET_DEST (x)) == SUBREG
5842 /* We need SUBREGs to compute nonzero_bits properly. */
5843 && nonzero_sign_valid
5844 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5845 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5847 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5849 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5851 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5858 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5859 inner = SUBREG_REG (inner);
5861 compute_mode = GET_MODE (inner);
5863 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5864 if (! SCALAR_INT_MODE_P (compute_mode))
5866 enum machine_mode imode;
5868 /* Don't do anything for vector or complex integral types. */
5869 if (! FLOAT_MODE_P (compute_mode))
5872 /* Try to find an integral mode to pun with. */
5873 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5874 if (imode == BLKmode)
5877 compute_mode = imode;
5878 inner = gen_lowpart (imode, inner);
5881 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5882 if (len >= HOST_BITS_PER_WIDE_INT)
5885 /* Now compute the equivalent expression. Make a copy of INNER
5886 for the SET_DEST in case it is a MEM into which we will substitute;
5887 we don't want shared RTL in that case. */
5888 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5889 cleared = simplify_gen_binary (AND, compute_mode,
5890 simplify_gen_unary (NOT, compute_mode,
5891 simplify_gen_binary (ASHIFT,
5896 masked = simplify_gen_binary (ASHIFT, compute_mode,
5897 simplify_gen_binary (
5899 gen_lowpart (compute_mode, SET_SRC (x)),
5903 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5904 simplify_gen_binary (IOR, compute_mode,
5911 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5912 it is an RTX that represents a variable starting position; otherwise,
5913 POS is the (constant) starting bit position (counted from the LSB).
5915 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5918 IN_DEST is nonzero if this is a reference in the destination of a
5919 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5920 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5923 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5924 ZERO_EXTRACT should be built even for bits starting at bit 0.
5926 MODE is the desired mode of the result (if IN_DEST == 0).
5928 The result is an RTX for the extraction or NULL_RTX if the target
5932 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5933 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5934 int in_dest, int in_compare)
5936 /* This mode describes the size of the storage area
5937 to fetch the overall value from. Within that, we
5938 ignore the POS lowest bits, etc. */
5939 enum machine_mode is_mode = GET_MODE (inner);
5940 enum machine_mode inner_mode;
5941 enum machine_mode wanted_inner_mode;
5942 enum machine_mode wanted_inner_reg_mode = word_mode;
5943 enum machine_mode pos_mode = word_mode;
5944 enum machine_mode extraction_mode = word_mode;
5945 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5947 rtx orig_pos_rtx = pos_rtx;
5948 HOST_WIDE_INT orig_pos;
5950 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5952 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5953 consider just the QI as the memory to extract from.
5954 The subreg adds or removes high bits; its mode is
5955 irrelevant to the meaning of this extraction,
5956 since POS and LEN count from the lsb. */
5957 if (MEM_P (SUBREG_REG (inner)))
5958 is_mode = GET_MODE (SUBREG_REG (inner));
5959 inner = SUBREG_REG (inner);
5961 else if (GET_CODE (inner) == ASHIFT
5962 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5963 && pos_rtx == 0 && pos == 0
5964 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5966 /* We're extracting the least significant bits of an rtx
5967 (ashift X (const_int C)), where LEN > C. Extract the
5968 least significant (LEN - C) bits of X, giving an rtx
5969 whose mode is MODE, then shift it left C times. */
5970 new = make_extraction (mode, XEXP (inner, 0),
5971 0, 0, len - INTVAL (XEXP (inner, 1)),
5972 unsignedp, in_dest, in_compare);
5974 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5977 inner_mode = GET_MODE (inner);
5979 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5980 pos = INTVAL (pos_rtx), pos_rtx = 0;
5982 /* See if this can be done without an extraction. We never can if the
5983 width of the field is not the same as that of some integer mode. For
5984 registers, we can only avoid the extraction if the position is at the
5985 low-order bit and this is either not in the destination or we have the
5986 appropriate STRICT_LOW_PART operation available.
5988 For MEM, we can avoid an extract if the field starts on an appropriate
5989 boundary and we can change the mode of the memory reference. */
5991 if (tmode != BLKmode
5992 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5994 && (inner_mode == tmode
5996 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5997 GET_MODE_BITSIZE (inner_mode))
5998 || reg_truncated_to_mode (tmode, inner))
6001 && have_insn_for (STRICT_LOW_PART, tmode))))
6002 || (MEM_P (inner) && pos_rtx == 0
6004 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6005 : BITS_PER_UNIT)) == 0
6006 /* We can't do this if we are widening INNER_MODE (it
6007 may not be aligned, for one thing). */
6008 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6009 && (inner_mode == tmode
6010 || (! mode_dependent_address_p (XEXP (inner, 0))
6011 && ! MEM_VOLATILE_P (inner))))))
6013 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6014 field. If the original and current mode are the same, we need not
6015 adjust the offset. Otherwise, we do if bytes big endian.
6017 If INNER is not a MEM, get a piece consisting of just the field
6018 of interest (in this case POS % BITS_PER_WORD must be 0). */
6022 HOST_WIDE_INT offset;
6024 /* POS counts from lsb, but make OFFSET count in memory order. */
6025 if (BYTES_BIG_ENDIAN)
6026 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6028 offset = pos / BITS_PER_UNIT;
6030 new = adjust_address_nv (inner, tmode, offset);
6032 else if (REG_P (inner))
6034 if (tmode != inner_mode)
6036 /* We can't call gen_lowpart in a DEST since we
6037 always want a SUBREG (see below) and it would sometimes
6038 return a new hard register. */
6041 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6043 if (WORDS_BIG_ENDIAN
6044 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6045 final_word = ((GET_MODE_SIZE (inner_mode)
6046 - GET_MODE_SIZE (tmode))
6047 / UNITS_PER_WORD) - final_word;
6049 final_word *= UNITS_PER_WORD;
6050 if (BYTES_BIG_ENDIAN &&
6051 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6052 final_word += (GET_MODE_SIZE (inner_mode)
6053 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6055 /* Avoid creating invalid subregs, for example when
6056 simplifying (x>>32)&255. */
6057 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6060 new = gen_rtx_SUBREG (tmode, inner, final_word);
6063 new = gen_lowpart (tmode, inner);
6069 new = force_to_mode (inner, tmode,
6070 len >= HOST_BITS_PER_WIDE_INT
6071 ? ~(unsigned HOST_WIDE_INT) 0
6072 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6075 /* If this extraction is going into the destination of a SET,
6076 make a STRICT_LOW_PART unless we made a MEM. */
6079 return (MEM_P (new) ? new
6080 : (GET_CODE (new) != SUBREG
6081 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6082 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6087 if (GET_CODE (new) == CONST_INT)
6088 return gen_int_mode (INTVAL (new), mode);
6090 /* If we know that no extraneous bits are set, and that the high
6091 bit is not set, convert the extraction to the cheaper of
6092 sign and zero extension, that are equivalent in these cases. */
6093 if (flag_expensive_optimizations
6094 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6095 && ((nonzero_bits (new, tmode)
6096 & ~(((unsigned HOST_WIDE_INT)
6097 GET_MODE_MASK (tmode))
6101 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6102 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6104 /* Prefer ZERO_EXTENSION, since it gives more information to
6106 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6111 /* Otherwise, sign- or zero-extend unless we already are in the
6114 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6118 /* Unless this is a COMPARE or we have a funny memory reference,
6119 don't do anything with zero-extending field extracts starting at
6120 the low-order bit since they are simple AND operations. */
6121 if (pos_rtx == 0 && pos == 0 && ! in_dest
6122 && ! in_compare && unsignedp)
6125 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6126 if the position is not a constant and the length is not 1. In all
6127 other cases, we would only be going outside our object in cases when
6128 an original shift would have been undefined. */
6130 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6131 || (pos_rtx != 0 && len != 1)))
6134 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6135 and the mode for the result. */
6136 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6138 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6139 pos_mode = mode_for_extraction (EP_insv, 2);
6140 extraction_mode = mode_for_extraction (EP_insv, 3);
6143 if (! in_dest && unsignedp
6144 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6146 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6147 pos_mode = mode_for_extraction (EP_extzv, 3);
6148 extraction_mode = mode_for_extraction (EP_extzv, 0);
6151 if (! in_dest && ! unsignedp
6152 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6154 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6155 pos_mode = mode_for_extraction (EP_extv, 3);
6156 extraction_mode = mode_for_extraction (EP_extv, 0);
6159 /* Never narrow an object, since that might not be safe. */
6161 if (mode != VOIDmode
6162 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6163 extraction_mode = mode;
6165 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6166 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6167 pos_mode = GET_MODE (pos_rtx);
6169 /* If this is not from memory, the desired mode is the preferred mode
6170 for an extraction pattern's first input operand, or word_mode if there
6173 wanted_inner_mode = wanted_inner_reg_mode;
6176 /* Be careful not to go beyond the extracted object and maintain the
6177 natural alignment of the memory. */
6178 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6179 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6180 > GET_MODE_BITSIZE (wanted_inner_mode))
6182 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6183 gcc_assert (wanted_inner_mode != VOIDmode);
6186 /* If we have to change the mode of memory and cannot, the desired mode
6187 is EXTRACTION_MODE. */
6188 if (inner_mode != wanted_inner_mode
6189 && (mode_dependent_address_p (XEXP (inner, 0))
6190 || MEM_VOLATILE_P (inner)
6192 wanted_inner_mode = extraction_mode;
6197 if (BITS_BIG_ENDIAN)
6199 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6200 BITS_BIG_ENDIAN style. If position is constant, compute new
6201 position. Otherwise, build subtraction.
6202 Note that POS is relative to the mode of the original argument.
6203 If it's a MEM we need to recompute POS relative to that.
6204 However, if we're extracting from (or inserting into) a register,
6205 we want to recompute POS relative to wanted_inner_mode. */
6206 int width = (MEM_P (inner)
6207 ? GET_MODE_BITSIZE (is_mode)
6208 : GET_MODE_BITSIZE (wanted_inner_mode));
6211 pos = width - len - pos;
6214 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6215 /* POS may be less than 0 now, but we check for that below.
6216 Note that it can only be less than 0 if !MEM_P (inner). */
6219 /* If INNER has a wider mode, and this is a constant extraction, try to
6220 make it smaller and adjust the byte to point to the byte containing
6222 if (wanted_inner_mode != VOIDmode
6223 && inner_mode != wanted_inner_mode
6225 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6227 && ! mode_dependent_address_p (XEXP (inner, 0))
6228 && ! MEM_VOLATILE_P (inner))
6232 /* The computations below will be correct if the machine is big
6233 endian in both bits and bytes or little endian in bits and bytes.
6234 If it is mixed, we must adjust. */
6236 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6237 adjust OFFSET to compensate. */
6238 if (BYTES_BIG_ENDIAN
6239 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6240 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6242 /* We can now move to the desired byte. */
6243 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6244 * GET_MODE_SIZE (wanted_inner_mode);
6245 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6247 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6248 && is_mode != wanted_inner_mode)
6249 offset = (GET_MODE_SIZE (is_mode)
6250 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6252 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6255 /* If INNER is not memory, we can always get it into the proper mode. If we
6256 are changing its mode, POS must be a constant and smaller than the size
6258 else if (!MEM_P (inner))
6260 if (GET_MODE (inner) != wanted_inner_mode
6262 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6268 inner = force_to_mode (inner, wanted_inner_mode,
6270 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6271 ? ~(unsigned HOST_WIDE_INT) 0
6272 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6277 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6278 have to zero extend. Otherwise, we can just use a SUBREG. */
6280 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6282 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6284 /* If we know that no extraneous bits are set, and that the high
6285 bit is not set, convert extraction to cheaper one - either
6286 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6288 if (flag_expensive_optimizations
6289 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6290 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6291 & ~(((unsigned HOST_WIDE_INT)
6292 GET_MODE_MASK (GET_MODE (pos_rtx)))
6296 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6298 /* Prefer ZERO_EXTENSION, since it gives more information to
6300 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6305 else if (pos_rtx != 0
6306 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6307 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6309 /* Make POS_RTX unless we already have it and it is correct. If we don't
6310 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6312 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6313 pos_rtx = orig_pos_rtx;
6315 else if (pos_rtx == 0)
6316 pos_rtx = GEN_INT (pos);
6318 /* Make the required operation. See if we can use existing rtx. */
6319 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6320 extraction_mode, inner, GEN_INT (len), pos_rtx);
6322 new = gen_lowpart (mode, new);
6327 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6328 with any other operations in X. Return X without that shift if so. */
6331 extract_left_shift (rtx x, int count)
6333 enum rtx_code code = GET_CODE (x);
6334 enum machine_mode mode = GET_MODE (x);
6340 /* This is the shift itself. If it is wide enough, we will return
6341 either the value being shifted if the shift count is equal to
6342 COUNT or a shift for the difference. */
6343 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6344 && INTVAL (XEXP (x, 1)) >= count)
6345 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6346 INTVAL (XEXP (x, 1)) - count);
6350 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6351 return simplify_gen_unary (code, mode, tem, mode);
6355 case PLUS: case IOR: case XOR: case AND:
6356 /* If we can safely shift this constant and we find the inner shift,
6357 make a new operation. */
6358 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6359 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6360 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6361 return simplify_gen_binary (code, mode, tem,
6362 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6373 /* Look at the expression rooted at X. Look for expressions
6374 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6375 Form these expressions.
6377 Return the new rtx, usually just X.
6379 Also, for machines like the VAX that don't have logical shift insns,
6380 try to convert logical to arithmetic shift operations in cases where
6381 they are equivalent. This undoes the canonicalizations to logical
6382 shifts done elsewhere.
6384 We try, as much as possible, to re-use rtl expressions to save memory.
6386 IN_CODE says what kind of expression we are processing. Normally, it is
6387 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6388 being kludges), it is MEM. When processing the arguments of a comparison
6389 or a COMPARE against zero, it is COMPARE. */
6392 make_compound_operation (rtx x, enum rtx_code in_code)
6394 enum rtx_code code = GET_CODE (x);
6395 enum machine_mode mode = GET_MODE (x);
6396 int mode_width = GET_MODE_BITSIZE (mode);
6398 enum rtx_code next_code;
6404 /* Select the code to be used in recursive calls. Once we are inside an
6405 address, we stay there. If we have a comparison, set to COMPARE,
6406 but once inside, go back to our default of SET. */
6408 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6409 : ((code == COMPARE || COMPARISON_P (x))
6410 && XEXP (x, 1) == const0_rtx) ? COMPARE
6411 : in_code == COMPARE ? SET : in_code);
6413 /* Process depending on the code of this operation. If NEW is set
6414 nonzero, it will be returned. */
6419 /* Convert shifts by constants into multiplications if inside
6421 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6422 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6423 && INTVAL (XEXP (x, 1)) >= 0)
6425 new = make_compound_operation (XEXP (x, 0), next_code);
6426 new = gen_rtx_MULT (mode, new,
6427 GEN_INT ((HOST_WIDE_INT) 1
6428 << INTVAL (XEXP (x, 1))));
6433 /* If the second operand is not a constant, we can't do anything
6435 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6438 /* If the constant is a power of two minus one and the first operand
6439 is a logical right shift, make an extraction. */
6440 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6441 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6443 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6444 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6445 0, in_code == COMPARE);
6448 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6449 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6450 && subreg_lowpart_p (XEXP (x, 0))
6451 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6452 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6454 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6456 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6457 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6458 0, in_code == COMPARE);
6460 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6461 else if ((GET_CODE (XEXP (x, 0)) == XOR
6462 || GET_CODE (XEXP (x, 0)) == IOR)
6463 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6464 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6465 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6467 /* Apply the distributive law, and then try to make extractions. */
6468 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6469 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6471 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6473 new = make_compound_operation (new, in_code);
6476 /* If we are have (and (rotate X C) M) and C is larger than the number
6477 of bits in M, this is an extraction. */
6479 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6480 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6481 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6482 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6484 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6485 new = make_extraction (mode, new,
6486 (GET_MODE_BITSIZE (mode)
6487 - INTVAL (XEXP (XEXP (x, 0), 1))),
6488 NULL_RTX, i, 1, 0, in_code == COMPARE);
6491 /* On machines without logical shifts, if the operand of the AND is
6492 a logical shift and our mask turns off all the propagated sign
6493 bits, we can replace the logical shift with an arithmetic shift. */
6494 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6495 && !have_insn_for (LSHIFTRT, mode)
6496 && have_insn_for (ASHIFTRT, mode)
6497 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6498 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6499 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6500 && mode_width <= HOST_BITS_PER_WIDE_INT)
6502 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6504 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6505 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6507 gen_rtx_ASHIFTRT (mode,
6508 make_compound_operation
6509 (XEXP (XEXP (x, 0), 0), next_code),
6510 XEXP (XEXP (x, 0), 1)));
6513 /* If the constant is one less than a power of two, this might be
6514 representable by an extraction even if no shift is present.
6515 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6516 we are in a COMPARE. */
6517 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6518 new = make_extraction (mode,
6519 make_compound_operation (XEXP (x, 0),
6521 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6523 /* If we are in a comparison and this is an AND with a power of two,
6524 convert this into the appropriate bit extract. */
6525 else if (in_code == COMPARE
6526 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6527 new = make_extraction (mode,
6528 make_compound_operation (XEXP (x, 0),
6530 i, NULL_RTX, 1, 1, 0, 1);
6535 /* If the sign bit is known to be zero, replace this with an
6536 arithmetic shift. */
6537 if (have_insn_for (ASHIFTRT, mode)
6538 && ! have_insn_for (LSHIFTRT, mode)
6539 && mode_width <= HOST_BITS_PER_WIDE_INT
6540 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6542 new = gen_rtx_ASHIFTRT (mode,
6543 make_compound_operation (XEXP (x, 0),
6549 /* ... fall through ... */
6555 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6556 this is a SIGN_EXTRACT. */
6557 if (GET_CODE (rhs) == CONST_INT
6558 && GET_CODE (lhs) == ASHIFT
6559 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6560 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6562 new = make_compound_operation (XEXP (lhs, 0), next_code);
6563 new = make_extraction (mode, new,
6564 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6565 NULL_RTX, mode_width - INTVAL (rhs),
6566 code == LSHIFTRT, 0, in_code == COMPARE);
6570 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6571 If so, try to merge the shifts into a SIGN_EXTEND. We could
6572 also do this for some cases of SIGN_EXTRACT, but it doesn't
6573 seem worth the effort; the case checked for occurs on Alpha. */
6576 && ! (GET_CODE (lhs) == SUBREG
6577 && (OBJECT_P (SUBREG_REG (lhs))))
6578 && GET_CODE (rhs) == CONST_INT
6579 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6580 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6581 new = make_extraction (mode, make_compound_operation (new, next_code),
6582 0, NULL_RTX, mode_width - INTVAL (rhs),
6583 code == LSHIFTRT, 0, in_code == COMPARE);
6588 /* Call ourselves recursively on the inner expression. If we are
6589 narrowing the object and it has a different RTL code from
6590 what it originally did, do this SUBREG as a force_to_mode. */
6592 tem = make_compound_operation (SUBREG_REG (x), in_code);
6596 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6602 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6603 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6604 && subreg_lowpart_p (x))
6606 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6609 /* If we have something other than a SUBREG, we might have
6610 done an expansion, so rerun ourselves. */
6611 if (GET_CODE (newer) != SUBREG)
6612 newer = make_compound_operation (newer, in_code);
6628 x = gen_lowpart (mode, new);
6629 code = GET_CODE (x);
6632 /* Now recursively process each operand of this operation. */
6633 fmt = GET_RTX_FORMAT (code);
6634 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6637 new = make_compound_operation (XEXP (x, i), next_code);
6638 SUBST (XEXP (x, i), new);
6641 /* If this is a commutative operation, the changes to the operands
6642 may have made it noncanonical. */
6643 if (COMMUTATIVE_ARITH_P (x)
6644 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6647 SUBST (XEXP (x, 0), XEXP (x, 1));
6648 SUBST (XEXP (x, 1), tem);
6654 /* Given M see if it is a value that would select a field of bits
6655 within an item, but not the entire word. Return -1 if not.
6656 Otherwise, return the starting position of the field, where 0 is the
6659 *PLEN is set to the length of the field. */
6662 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6664 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6665 int pos = exact_log2 (m & -m);
6669 /* Now shift off the low-order zero bits and see if we have a
6670 power of two minus 1. */
6671 len = exact_log2 ((m >> pos) + 1);
6680 /* If X refers to a register that equals REG in value, replace these
6681 references with REG. */
6683 canon_reg_for_combine (rtx x, rtx reg)
6690 enum rtx_code code = GET_CODE (x);
6691 switch (GET_RTX_CLASS (code))
6694 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6695 if (op0 != XEXP (x, 0))
6696 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6701 case RTX_COMM_ARITH:
6702 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6703 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6704 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6705 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6709 case RTX_COMM_COMPARE:
6710 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6711 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6712 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6713 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6714 GET_MODE (op0), op0, op1);
6718 case RTX_BITFIELD_OPS:
6719 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6720 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6721 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6722 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6723 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6724 GET_MODE (op0), op0, op1, op2);
6729 if (rtx_equal_p (get_last_value (reg), x)
6730 || rtx_equal_p (reg, get_last_value (x)))
6739 fmt = GET_RTX_FORMAT (code);
6741 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6744 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6745 if (op != XEXP (x, i))
6755 else if (fmt[i] == 'E')
6758 for (j = 0; j < XVECLEN (x, i); j++)
6760 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6761 if (op != XVECEXP (x, i, j))
6768 XVECEXP (x, i, j) = op;
6779 /* Return X converted to MODE. If the value is already truncated to
6780 MODE we can just return a subreg even though in the general case we
6781 would need an explicit truncation. */
6784 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6786 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6787 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6788 GET_MODE_BITSIZE (GET_MODE (x)))
6789 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6790 return gen_lowpart (mode, x);
6792 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6795 /* See if X can be simplified knowing that we will only refer to it in
6796 MODE and will only refer to those bits that are nonzero in MASK.
6797 If other bits are being computed or if masking operations are done
6798 that select a superset of the bits in MASK, they can sometimes be
6801 Return a possibly simplified expression, but always convert X to
6802 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6804 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6805 are all off in X. This is used when X will be complemented, by either
6806 NOT, NEG, or XOR. */
6809 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6812 enum rtx_code code = GET_CODE (x);
6813 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6814 enum machine_mode op_mode;
6815 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6818 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6819 code below will do the wrong thing since the mode of such an
6820 expression is VOIDmode.
6822 Also do nothing if X is a CLOBBER; this can happen if X was
6823 the return value from a call to gen_lowpart. */
6824 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6827 /* We want to perform the operation is its present mode unless we know
6828 that the operation is valid in MODE, in which case we do the operation
6830 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6831 && have_insn_for (code, mode))
6832 ? mode : GET_MODE (x));
6834 /* It is not valid to do a right-shift in a narrower mode
6835 than the one it came in with. */
6836 if ((code == LSHIFTRT || code == ASHIFTRT)
6837 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6838 op_mode = GET_MODE (x);
6840 /* Truncate MASK to fit OP_MODE. */
6842 mask &= GET_MODE_MASK (op_mode);
6844 /* When we have an arithmetic operation, or a shift whose count we
6845 do not know, we need to assume that all bits up to the highest-order
6846 bit in MASK will be needed. This is how we form such a mask. */
6847 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6848 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6850 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6853 /* Determine what bits of X are guaranteed to be (non)zero. */
6854 nonzero = nonzero_bits (x, mode);
6856 /* If none of the bits in X are needed, return a zero. */
6857 if (! just_select && (nonzero & mask) == 0)
6860 /* If X is a CONST_INT, return a new one. Do this here since the
6861 test below will fail. */
6862 if (GET_CODE (x) == CONST_INT)
6864 if (SCALAR_INT_MODE_P (mode))
6865 return gen_int_mode (INTVAL (x) & mask, mode);
6868 x = GEN_INT (INTVAL (x) & mask);
6869 return gen_lowpart_common (mode, x);
6873 /* If X is narrower than MODE and we want all the bits in X's mode, just
6874 get X in the proper mode. */
6875 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6876 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6877 return gen_lowpart (mode, x);
6882 /* If X is a (clobber (const_int)), return it since we know we are
6883 generating something that won't match. */
6890 x = expand_compound_operation (x);
6891 if (GET_CODE (x) != code)
6892 return force_to_mode (x, mode, mask, next_select);
6896 if (subreg_lowpart_p (x)
6897 /* We can ignore the effect of this SUBREG if it narrows the mode or
6898 if the constant masks to zero all the bits the mode doesn't
6900 && ((GET_MODE_SIZE (GET_MODE (x))
6901 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6903 & GET_MODE_MASK (GET_MODE (x))
6904 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6905 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6909 /* If this is an AND with a constant, convert it into an AND
6910 whose constant is the AND of that constant with MASK. If it
6911 remains an AND of MASK, delete it since it is redundant. */
6913 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6915 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6916 mask & INTVAL (XEXP (x, 1)));
6918 /* If X is still an AND, see if it is an AND with a mask that
6919 is just some low-order bits. If so, and it is MASK, we don't
6922 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6923 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6927 /* If it remains an AND, try making another AND with the bits
6928 in the mode mask that aren't in MASK turned on. If the
6929 constant in the AND is wide enough, this might make a
6930 cheaper constant. */
6932 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6933 && GET_MODE_MASK (GET_MODE (x)) != mask
6934 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6936 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6937 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6938 int width = GET_MODE_BITSIZE (GET_MODE (x));
6941 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6942 number, sign extend it. */
6943 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6944 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6945 cval |= (HOST_WIDE_INT) -1 << width;
6947 y = simplify_gen_binary (AND, GET_MODE (x),
6948 XEXP (x, 0), GEN_INT (cval));
6949 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6959 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6960 low-order bits (as in an alignment operation) and FOO is already
6961 aligned to that boundary, mask C1 to that boundary as well.
6962 This may eliminate that PLUS and, later, the AND. */
6965 unsigned int width = GET_MODE_BITSIZE (mode);
6966 unsigned HOST_WIDE_INT smask = mask;
6968 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6969 number, sign extend it. */
6971 if (width < HOST_BITS_PER_WIDE_INT
6972 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6973 smask |= (HOST_WIDE_INT) -1 << width;
6975 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6976 && exact_log2 (- smask) >= 0
6977 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6978 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6979 return force_to_mode (plus_constant (XEXP (x, 0),
6980 (INTVAL (XEXP (x, 1)) & smask)),
6981 mode, smask, next_select);
6984 /* ... fall through ... */
6987 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6988 most significant bit in MASK since carries from those bits will
6989 affect the bits we are interested in. */
6994 /* If X is (minus C Y) where C's least set bit is larger than any bit
6995 in the mask, then we may replace with (neg Y). */
6996 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6997 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6998 & -INTVAL (XEXP (x, 0))))
7001 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7003 return force_to_mode (x, mode, mask, next_select);
7006 /* Similarly, if C contains every bit in the fuller_mask, then we may
7007 replace with (not Y). */
7008 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7009 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7010 == INTVAL (XEXP (x, 0))))
7012 x = simplify_gen_unary (NOT, GET_MODE (x),
7013 XEXP (x, 1), GET_MODE (x));
7014 return force_to_mode (x, mode, mask, next_select);
7022 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7023 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7024 operation which may be a bitfield extraction. Ensure that the
7025 constant we form is not wider than the mode of X. */
7027 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7028 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7029 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7030 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7031 && GET_CODE (XEXP (x, 1)) == CONST_INT
7032 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7033 + floor_log2 (INTVAL (XEXP (x, 1))))
7034 < GET_MODE_BITSIZE (GET_MODE (x)))
7035 && (INTVAL (XEXP (x, 1))
7036 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7038 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7039 << INTVAL (XEXP (XEXP (x, 0), 1)));
7040 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7041 XEXP (XEXP (x, 0), 0), temp);
7042 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7043 XEXP (XEXP (x, 0), 1));
7044 return force_to_mode (x, mode, mask, next_select);
7048 /* For most binary operations, just propagate into the operation and
7049 change the mode if we have an operation of that mode. */
7051 op0 = gen_lowpart_or_truncate (op_mode,
7052 force_to_mode (XEXP (x, 0), mode, mask,
7054 op1 = gen_lowpart_or_truncate (op_mode,
7055 force_to_mode (XEXP (x, 1), mode, mask,
7058 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7059 x = simplify_gen_binary (code, op_mode, op0, op1);
7063 /* For left shifts, do the same, but just for the first operand.
7064 However, we cannot do anything with shifts where we cannot
7065 guarantee that the counts are smaller than the size of the mode
7066 because such a count will have a different meaning in a
7069 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7070 && INTVAL (XEXP (x, 1)) >= 0
7071 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7072 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7073 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7074 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7077 /* If the shift count is a constant and we can do arithmetic in
7078 the mode of the shift, refine which bits we need. Otherwise, use the
7079 conservative form of the mask. */
7080 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7081 && INTVAL (XEXP (x, 1)) >= 0
7082 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7083 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7084 mask >>= INTVAL (XEXP (x, 1));
7088 op0 = gen_lowpart_or_truncate (op_mode,
7089 force_to_mode (XEXP (x, 0), op_mode,
7090 mask, next_select));
7092 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7093 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7097 /* Here we can only do something if the shift count is a constant,
7098 this shift constant is valid for the host, and we can do arithmetic
7101 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7102 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7103 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7105 rtx inner = XEXP (x, 0);
7106 unsigned HOST_WIDE_INT inner_mask;
7108 /* Select the mask of the bits we need for the shift operand. */
7109 inner_mask = mask << INTVAL (XEXP (x, 1));
7111 /* We can only change the mode of the shift if we can do arithmetic
7112 in the mode of the shift and INNER_MASK is no wider than the
7113 width of X's mode. */
7114 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7115 op_mode = GET_MODE (x);
7117 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7119 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7120 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7123 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7124 shift and AND produces only copies of the sign bit (C2 is one less
7125 than a power of two), we can do this with just a shift. */
7127 if (GET_CODE (x) == LSHIFTRT
7128 && GET_CODE (XEXP (x, 1)) == CONST_INT
7129 /* The shift puts one of the sign bit copies in the least significant
7131 && ((INTVAL (XEXP (x, 1))
7132 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7133 >= GET_MODE_BITSIZE (GET_MODE (x)))
7134 && exact_log2 (mask + 1) >= 0
7135 /* Number of bits left after the shift must be more than the mask
7137 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7138 <= GET_MODE_BITSIZE (GET_MODE (x)))
7139 /* Must be more sign bit copies than the mask needs. */
7140 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7141 >= exact_log2 (mask + 1)))
7142 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7143 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7144 - exact_log2 (mask + 1)));
7149 /* If we are just looking for the sign bit, we don't need this shift at
7150 all, even if it has a variable count. */
7151 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7152 && (mask == ((unsigned HOST_WIDE_INT) 1
7153 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7154 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7156 /* If this is a shift by a constant, get a mask that contains those bits
7157 that are not copies of the sign bit. We then have two cases: If
7158 MASK only includes those bits, this can be a logical shift, which may
7159 allow simplifications. If MASK is a single-bit field not within
7160 those bits, we are requesting a copy of the sign bit and hence can
7161 shift the sign bit to the appropriate location. */
7163 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7164 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7168 /* If the considered data is wider than HOST_WIDE_INT, we can't
7169 represent a mask for all its bits in a single scalar.
7170 But we only care about the lower bits, so calculate these. */
7172 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7174 nonzero = ~(HOST_WIDE_INT) 0;
7176 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7177 is the number of bits a full-width mask would have set.
7178 We need only shift if these are fewer than nonzero can
7179 hold. If not, we must keep all bits set in nonzero. */
7181 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7182 < HOST_BITS_PER_WIDE_INT)
7183 nonzero >>= INTVAL (XEXP (x, 1))
7184 + HOST_BITS_PER_WIDE_INT
7185 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7189 nonzero = GET_MODE_MASK (GET_MODE (x));
7190 nonzero >>= INTVAL (XEXP (x, 1));
7193 if ((mask & ~nonzero) == 0)
7195 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7196 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7197 if (GET_CODE (x) != ASHIFTRT)
7198 return force_to_mode (x, mode, mask, next_select);
7201 else if ((i = exact_log2 (mask)) >= 0)
7203 x = simplify_shift_const
7204 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7205 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7207 if (GET_CODE (x) != ASHIFTRT)
7208 return force_to_mode (x, mode, mask, next_select);
7212 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7213 even if the shift count isn't a constant. */
7215 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7216 XEXP (x, 0), XEXP (x, 1));
7220 /* If this is a zero- or sign-extension operation that just affects bits
7221 we don't care about, remove it. Be sure the call above returned
7222 something that is still a shift. */
7224 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7225 && GET_CODE (XEXP (x, 1)) == CONST_INT
7226 && INTVAL (XEXP (x, 1)) >= 0
7227 && (INTVAL (XEXP (x, 1))
7228 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7229 && GET_CODE (XEXP (x, 0)) == ASHIFT
7230 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7231 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7238 /* If the shift count is constant and we can do computations
7239 in the mode of X, compute where the bits we care about are.
7240 Otherwise, we can't do anything. Don't change the mode of
7241 the shift or propagate MODE into the shift, though. */
7242 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7243 && INTVAL (XEXP (x, 1)) >= 0)
7245 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7246 GET_MODE (x), GEN_INT (mask),
7248 if (temp && GET_CODE (temp) == CONST_INT)
7250 force_to_mode (XEXP (x, 0), GET_MODE (x),
7251 INTVAL (temp), next_select));
7256 /* If we just want the low-order bit, the NEG isn't needed since it
7257 won't change the low-order bit. */
7259 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7261 /* We need any bits less significant than the most significant bit in
7262 MASK since carries from those bits will affect the bits we are
7268 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7269 same as the XOR case above. Ensure that the constant we form is not
7270 wider than the mode of X. */
7272 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7273 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7274 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7275 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7276 < GET_MODE_BITSIZE (GET_MODE (x)))
7277 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7279 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7281 temp = simplify_gen_binary (XOR, GET_MODE (x),
7282 XEXP (XEXP (x, 0), 0), temp);
7283 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7284 temp, XEXP (XEXP (x, 0), 1));
7286 return force_to_mode (x, mode, mask, next_select);
7289 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7290 use the full mask inside the NOT. */
7294 op0 = gen_lowpart_or_truncate (op_mode,
7295 force_to_mode (XEXP (x, 0), mode, mask,
7297 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7298 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7302 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7303 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7304 which is equal to STORE_FLAG_VALUE. */
7305 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7306 && GET_MODE (XEXP (x, 0)) == mode
7307 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7308 && (nonzero_bits (XEXP (x, 0), mode)
7309 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7310 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7315 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7316 written in a narrower mode. We play it safe and do not do so. */
7319 gen_lowpart_or_truncate (GET_MODE (x),
7320 force_to_mode (XEXP (x, 1), mode,
7321 mask, next_select)));
7323 gen_lowpart_or_truncate (GET_MODE (x),
7324 force_to_mode (XEXP (x, 2), mode,
7325 mask, next_select)));
7332 /* Ensure we return a value of the proper mode. */
7333 return gen_lowpart_or_truncate (mode, x);
7336 /* Return nonzero if X is an expression that has one of two values depending on
7337 whether some other value is zero or nonzero. In that case, we return the
7338 value that is being tested, *PTRUE is set to the value if the rtx being
7339 returned has a nonzero value, and *PFALSE is set to the other alternative.
7341 If we return zero, we set *PTRUE and *PFALSE to X. */
7344 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7346 enum machine_mode mode = GET_MODE (x);
7347 enum rtx_code code = GET_CODE (x);
7348 rtx cond0, cond1, true0, true1, false0, false1;
7349 unsigned HOST_WIDE_INT nz;
7351 /* If we are comparing a value against zero, we are done. */
7352 if ((code == NE || code == EQ)
7353 && XEXP (x, 1) == const0_rtx)
7355 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7356 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7360 /* If this is a unary operation whose operand has one of two values, apply
7361 our opcode to compute those values. */
7362 else if (UNARY_P (x)
7363 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7365 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7366 *pfalse = simplify_gen_unary (code, mode, false0,
7367 GET_MODE (XEXP (x, 0)));
7371 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7372 make can't possibly match and would suppress other optimizations. */
7373 else if (code == COMPARE)
7376 /* If this is a binary operation, see if either side has only one of two
7377 values. If either one does or if both do and they are conditional on
7378 the same value, compute the new true and false values. */
7379 else if (BINARY_P (x))
7381 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7382 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7384 if ((cond0 != 0 || cond1 != 0)
7385 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7387 /* If if_then_else_cond returned zero, then true/false are the
7388 same rtl. We must copy one of them to prevent invalid rtl
7391 true0 = copy_rtx (true0);
7392 else if (cond1 == 0)
7393 true1 = copy_rtx (true1);
7395 if (COMPARISON_P (x))
7397 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7399 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7404 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7405 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7408 return cond0 ? cond0 : cond1;
7411 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7412 operands is zero when the other is nonzero, and vice-versa,
7413 and STORE_FLAG_VALUE is 1 or -1. */
7415 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7416 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7418 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7420 rtx op0 = XEXP (XEXP (x, 0), 1);
7421 rtx op1 = XEXP (XEXP (x, 1), 1);
7423 cond0 = XEXP (XEXP (x, 0), 0);
7424 cond1 = XEXP (XEXP (x, 1), 0);
7426 if (COMPARISON_P (cond0)
7427 && COMPARISON_P (cond1)
7428 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7429 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7430 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7431 || ((swap_condition (GET_CODE (cond0))
7432 == reversed_comparison_code (cond1, NULL))
7433 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7434 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7435 && ! side_effects_p (x))
7437 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7438 *pfalse = simplify_gen_binary (MULT, mode,
7440 ? simplify_gen_unary (NEG, mode,
7448 /* Similarly for MULT, AND and UMIN, except that for these the result
7450 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7451 && (code == MULT || code == AND || code == UMIN)
7452 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7454 cond0 = XEXP (XEXP (x, 0), 0);
7455 cond1 = XEXP (XEXP (x, 1), 0);
7457 if (COMPARISON_P (cond0)
7458 && COMPARISON_P (cond1)
7459 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7460 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7461 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7462 || ((swap_condition (GET_CODE (cond0))
7463 == reversed_comparison_code (cond1, NULL))
7464 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7465 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7466 && ! side_effects_p (x))
7468 *ptrue = *pfalse = const0_rtx;
7474 else if (code == IF_THEN_ELSE)
7476 /* If we have IF_THEN_ELSE already, extract the condition and
7477 canonicalize it if it is NE or EQ. */
7478 cond0 = XEXP (x, 0);
7479 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7480 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7481 return XEXP (cond0, 0);
7482 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7484 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7485 return XEXP (cond0, 0);
7491 /* If X is a SUBREG, we can narrow both the true and false values
7492 if the inner expression, if there is a condition. */
7493 else if (code == SUBREG
7494 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7497 true0 = simplify_gen_subreg (mode, true0,
7498 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7499 false0 = simplify_gen_subreg (mode, false0,
7500 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7501 if (true0 && false0)
7509 /* If X is a constant, this isn't special and will cause confusions
7510 if we treat it as such. Likewise if it is equivalent to a constant. */
7511 else if (CONSTANT_P (x)
7512 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7515 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7516 will be least confusing to the rest of the compiler. */
7517 else if (mode == BImode)
7519 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7523 /* If X is known to be either 0 or -1, those are the true and
7524 false values when testing X. */
7525 else if (x == constm1_rtx || x == const0_rtx
7526 || (mode != VOIDmode
7527 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7529 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7533 /* Likewise for 0 or a single bit. */
7534 else if (SCALAR_INT_MODE_P (mode)
7535 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7536 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7538 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7542 /* Otherwise fail; show no condition with true and false values the same. */
7543 *ptrue = *pfalse = x;
7547 /* Return the value of expression X given the fact that condition COND
7548 is known to be true when applied to REG as its first operand and VAL
7549 as its second. X is known to not be shared and so can be modified in
7552 We only handle the simplest cases, and specifically those cases that
7553 arise with IF_THEN_ELSE expressions. */
7556 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7558 enum rtx_code code = GET_CODE (x);
7563 if (side_effects_p (x))
7566 /* If either operand of the condition is a floating point value,
7567 then we have to avoid collapsing an EQ comparison. */
7569 && rtx_equal_p (x, reg)
7570 && ! FLOAT_MODE_P (GET_MODE (x))
7571 && ! FLOAT_MODE_P (GET_MODE (val)))
7574 if (cond == UNEQ && rtx_equal_p (x, reg))
7577 /* If X is (abs REG) and we know something about REG's relationship
7578 with zero, we may be able to simplify this. */
7580 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7583 case GE: case GT: case EQ:
7586 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7588 GET_MODE (XEXP (x, 0)));
7593 /* The only other cases we handle are MIN, MAX, and comparisons if the
7594 operands are the same as REG and VAL. */
7596 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7598 if (rtx_equal_p (XEXP (x, 0), val))
7599 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7601 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7603 if (COMPARISON_P (x))
7605 if (comparison_dominates_p (cond, code))
7606 return const_true_rtx;
7608 code = reversed_comparison_code (x, NULL);
7610 && comparison_dominates_p (cond, code))
7615 else if (code == SMAX || code == SMIN
7616 || code == UMIN || code == UMAX)
7618 int unsignedp = (code == UMIN || code == UMAX);
7620 /* Do not reverse the condition when it is NE or EQ.
7621 This is because we cannot conclude anything about
7622 the value of 'SMAX (x, y)' when x is not equal to y,
7623 but we can when x equals y. */
7624 if ((code == SMAX || code == UMAX)
7625 && ! (cond == EQ || cond == NE))
7626 cond = reverse_condition (cond);
7631 return unsignedp ? x : XEXP (x, 1);
7633 return unsignedp ? x : XEXP (x, 0);
7635 return unsignedp ? XEXP (x, 1) : x;
7637 return unsignedp ? XEXP (x, 0) : x;
7644 else if (code == SUBREG)
7646 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7647 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7649 if (SUBREG_REG (x) != r)
7651 /* We must simplify subreg here, before we lose track of the
7652 original inner_mode. */
7653 new = simplify_subreg (GET_MODE (x), r,
7654 inner_mode, SUBREG_BYTE (x));
7658 SUBST (SUBREG_REG (x), r);
7663 /* We don't have to handle SIGN_EXTEND here, because even in the
7664 case of replacing something with a modeless CONST_INT, a
7665 CONST_INT is already (supposed to be) a valid sign extension for
7666 its narrower mode, which implies it's already properly
7667 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7668 story is different. */
7669 else if (code == ZERO_EXTEND)
7671 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7672 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7674 if (XEXP (x, 0) != r)
7676 /* We must simplify the zero_extend here, before we lose
7677 track of the original inner_mode. */
7678 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7683 SUBST (XEXP (x, 0), r);
7689 fmt = GET_RTX_FORMAT (code);
7690 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7693 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7694 else if (fmt[i] == 'E')
7695 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7696 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7703 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7704 assignment as a field assignment. */
7707 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7709 if (x == y || rtx_equal_p (x, y))
7712 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7715 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7716 Note that all SUBREGs of MEM are paradoxical; otherwise they
7717 would have been rewritten. */
7718 if (MEM_P (x) && GET_CODE (y) == SUBREG
7719 && MEM_P (SUBREG_REG (y))
7720 && rtx_equal_p (SUBREG_REG (y),
7721 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7724 if (MEM_P (y) && GET_CODE (x) == SUBREG
7725 && MEM_P (SUBREG_REG (x))
7726 && rtx_equal_p (SUBREG_REG (x),
7727 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7730 /* We used to see if get_last_value of X and Y were the same but that's
7731 not correct. In one direction, we'll cause the assignment to have
7732 the wrong destination and in the case, we'll import a register into this
7733 insn that might have already have been dead. So fail if none of the
7734 above cases are true. */
7738 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7739 Return that assignment if so.
7741 We only handle the most common cases. */
7744 make_field_assignment (rtx x)
7746 rtx dest = SET_DEST (x);
7747 rtx src = SET_SRC (x);
7752 unsigned HOST_WIDE_INT len;
7754 enum machine_mode mode;
7756 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7757 a clear of a one-bit field. We will have changed it to
7758 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7761 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7762 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7763 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7764 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7766 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7769 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7773 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7774 && subreg_lowpart_p (XEXP (src, 0))
7775 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7776 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7777 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7778 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7779 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7780 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7782 assign = make_extraction (VOIDmode, dest, 0,
7783 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7786 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7790 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7792 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7793 && XEXP (XEXP (src, 0), 0) == const1_rtx
7794 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7796 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7799 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7803 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7804 SRC is an AND with all bits of that field set, then we can discard
7806 if (GET_CODE (dest) == ZERO_EXTRACT
7807 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7808 && GET_CODE (src) == AND
7809 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7811 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7812 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7813 unsigned HOST_WIDE_INT ze_mask;
7815 if (width >= HOST_BITS_PER_WIDE_INT)
7818 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7820 /* Complete overlap. We can remove the source AND. */
7821 if ((and_mask & ze_mask) == ze_mask)
7822 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7824 /* Partial overlap. We can reduce the source AND. */
7825 if ((and_mask & ze_mask) != and_mask)
7827 mode = GET_MODE (src);
7828 src = gen_rtx_AND (mode, XEXP (src, 0),
7829 gen_int_mode (and_mask & ze_mask, mode));
7830 return gen_rtx_SET (VOIDmode, dest, src);
7834 /* The other case we handle is assignments into a constant-position
7835 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7836 a mask that has all one bits except for a group of zero bits and
7837 OTHER is known to have zeros where C1 has ones, this is such an
7838 assignment. Compute the position and length from C1. Shift OTHER
7839 to the appropriate position, force it to the required mode, and
7840 make the extraction. Check for the AND in both operands. */
7842 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7845 rhs = expand_compound_operation (XEXP (src, 0));
7846 lhs = expand_compound_operation (XEXP (src, 1));
7848 if (GET_CODE (rhs) == AND
7849 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7850 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7851 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7852 else if (GET_CODE (lhs) == AND
7853 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7854 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7855 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7859 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7860 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7861 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7862 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7865 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7869 /* The mode to use for the source is the mode of the assignment, or of
7870 what is inside a possible STRICT_LOW_PART. */
7871 mode = (GET_CODE (assign) == STRICT_LOW_PART
7872 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7874 /* Shift OTHER right POS places and make it the source, restricting it
7875 to the proper length and mode. */
7877 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7881 src = force_to_mode (src, mode,
7882 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7883 ? ~(unsigned HOST_WIDE_INT) 0
7884 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7887 /* If SRC is masked by an AND that does not make a difference in
7888 the value being stored, strip it. */
7889 if (GET_CODE (assign) == ZERO_EXTRACT
7890 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7891 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7892 && GET_CODE (src) == AND
7893 && GET_CODE (XEXP (src, 1)) == CONST_INT
7894 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7895 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7896 src = XEXP (src, 0);
7898 return gen_rtx_SET (VOIDmode, assign, src);
7901 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7905 apply_distributive_law (rtx x)
7907 enum rtx_code code = GET_CODE (x);
7908 enum rtx_code inner_code;
7909 rtx lhs, rhs, other;
7912 /* Distributivity is not true for floating point as it can change the
7913 value. So we don't do it unless -funsafe-math-optimizations. */
7914 if (FLOAT_MODE_P (GET_MODE (x))
7915 && ! flag_unsafe_math_optimizations)
7918 /* The outer operation can only be one of the following: */
7919 if (code != IOR && code != AND && code != XOR
7920 && code != PLUS && code != MINUS)
7926 /* If either operand is a primitive we can't do anything, so get out
7928 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7931 lhs = expand_compound_operation (lhs);
7932 rhs = expand_compound_operation (rhs);
7933 inner_code = GET_CODE (lhs);
7934 if (inner_code != GET_CODE (rhs))
7937 /* See if the inner and outer operations distribute. */
7944 /* These all distribute except over PLUS. */
7945 if (code == PLUS || code == MINUS)
7950 if (code != PLUS && code != MINUS)
7955 /* This is also a multiply, so it distributes over everything. */
7959 /* Non-paradoxical SUBREGs distributes over all operations,
7960 provided the inner modes and byte offsets are the same, this
7961 is an extraction of a low-order part, we don't convert an fp
7962 operation to int or vice versa, this is not a vector mode,
7963 and we would not be converting a single-word operation into a
7964 multi-word operation. The latter test is not required, but
7965 it prevents generating unneeded multi-word operations. Some
7966 of the previous tests are redundant given the latter test,
7967 but are retained because they are required for correctness.
7969 We produce the result slightly differently in this case. */
7971 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7972 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7973 || ! subreg_lowpart_p (lhs)
7974 || (GET_MODE_CLASS (GET_MODE (lhs))
7975 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7976 || (GET_MODE_SIZE (GET_MODE (lhs))
7977 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7978 || VECTOR_MODE_P (GET_MODE (lhs))
7979 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7980 /* Result might need to be truncated. Don't change mode if
7981 explicit truncation is needed. */
7982 || !TRULY_NOOP_TRUNCATION
7983 (GET_MODE_BITSIZE (GET_MODE (x)),
7984 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7987 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7988 SUBREG_REG (lhs), SUBREG_REG (rhs));
7989 return gen_lowpart (GET_MODE (x), tem);
7995 /* Set LHS and RHS to the inner operands (A and B in the example
7996 above) and set OTHER to the common operand (C in the example).
7997 There is only one way to do this unless the inner operation is
7999 if (COMMUTATIVE_ARITH_P (lhs)
8000 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8001 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8002 else if (COMMUTATIVE_ARITH_P (lhs)
8003 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8004 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8005 else if (COMMUTATIVE_ARITH_P (lhs)
8006 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8007 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8008 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8009 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8013 /* Form the new inner operation, seeing if it simplifies first. */
8014 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8016 /* There is one exception to the general way of distributing:
8017 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8018 if (code == XOR && inner_code == IOR)
8021 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8024 /* We may be able to continuing distributing the result, so call
8025 ourselves recursively on the inner operation before forming the
8026 outer operation, which we return. */
8027 return simplify_gen_binary (inner_code, GET_MODE (x),
8028 apply_distributive_law (tem), other);
8031 /* See if X is of the form (* (+ A B) C), and if so convert to
8032 (+ (* A C) (* B C)) and try to simplify.
8034 Most of the time, this results in no change. However, if some of
8035 the operands are the same or inverses of each other, simplifications
8038 For example, (and (ior A B) (not B)) can occur as the result of
8039 expanding a bit field assignment. When we apply the distributive
8040 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8041 which then simplifies to (and (A (not B))).
8043 Note that no checks happen on the validity of applying the inverse
8044 distributive law. This is pointless since we can do it in the
8045 few places where this routine is called.
8047 N is the index of the term that is decomposed (the arithmetic operation,
8048 i.e. (+ A B) in the first example above). !N is the index of the term that
8049 is distributed, i.e. of C in the first example above. */
8051 distribute_and_simplify_rtx (rtx x, int n)
8053 enum machine_mode mode;
8054 enum rtx_code outer_code, inner_code;
8055 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8057 decomposed = XEXP (x, n);
8058 if (!ARITHMETIC_P (decomposed))
8061 mode = GET_MODE (x);
8062 outer_code = GET_CODE (x);
8063 distributed = XEXP (x, !n);
8065 inner_code = GET_CODE (decomposed);
8066 inner_op0 = XEXP (decomposed, 0);
8067 inner_op1 = XEXP (decomposed, 1);
8069 /* Special case (and (xor B C) (not A)), which is equivalent to
8070 (xor (ior A B) (ior A C)) */
8071 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8073 distributed = XEXP (distributed, 0);
8079 /* Distribute the second term. */
8080 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8081 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8085 /* Distribute the first term. */
8086 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8087 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8090 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8092 if (GET_CODE (tmp) != outer_code
8093 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8099 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8100 in MODE. Return an equivalent form, if different from (and VAROP
8101 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8104 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8105 unsigned HOST_WIDE_INT constop)
8107 unsigned HOST_WIDE_INT nonzero;
8108 unsigned HOST_WIDE_INT orig_constop;
8113 orig_constop = constop;
8114 if (GET_CODE (varop) == CLOBBER)
8117 /* Simplify VAROP knowing that we will be only looking at some of the
8120 Note by passing in CONSTOP, we guarantee that the bits not set in
8121 CONSTOP are not significant and will never be examined. We must
8122 ensure that is the case by explicitly masking out those bits
8123 before returning. */
8124 varop = force_to_mode (varop, mode, constop, 0);
8126 /* If VAROP is a CLOBBER, we will fail so return it. */
8127 if (GET_CODE (varop) == CLOBBER)
8130 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8131 to VAROP and return the new constant. */
8132 if (GET_CODE (varop) == CONST_INT)
8133 return gen_int_mode (INTVAL (varop) & constop, mode);
8135 /* See what bits may be nonzero in VAROP. Unlike the general case of
8136 a call to nonzero_bits, here we don't care about bits outside
8139 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8141 /* Turn off all bits in the constant that are known to already be zero.
8142 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8143 which is tested below. */
8147 /* If we don't have any bits left, return zero. */
8151 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8152 a power of two, we can replace this with an ASHIFT. */
8153 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8154 && (i = exact_log2 (constop)) >= 0)
8155 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8157 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8158 or XOR, then try to apply the distributive law. This may eliminate
8159 operations if either branch can be simplified because of the AND.
8160 It may also make some cases more complex, but those cases probably
8161 won't match a pattern either with or without this. */
8163 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8167 apply_distributive_law
8168 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8169 simplify_and_const_int (NULL_RTX,
8173 simplify_and_const_int (NULL_RTX,
8178 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8179 the AND and see if one of the operands simplifies to zero. If so, we
8180 may eliminate it. */
8182 if (GET_CODE (varop) == PLUS
8183 && exact_log2 (constop + 1) >= 0)
8187 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8188 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8189 if (o0 == const0_rtx)
8191 if (o1 == const0_rtx)
8195 /* Make a SUBREG if necessary. If we can't make it, fail. */
8196 varop = gen_lowpart (mode, varop);
8197 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8200 /* If we are only masking insignificant bits, return VAROP. */
8201 if (constop == nonzero)
8204 if (varop == orig_varop && constop == orig_constop)
8207 /* Otherwise, return an AND. */
8208 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8212 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8215 Return an equivalent form, if different from X. Otherwise, return X. If
8216 X is zero, we are to always construct the equivalent form. */
8219 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8220 unsigned HOST_WIDE_INT constop)
8222 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8227 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8228 gen_int_mode (constop, mode));
8229 if (GET_MODE (x) != mode)
8230 x = gen_lowpart (mode, x);
8234 /* Given a REG, X, compute which bits in X can be nonzero.
8235 We don't care about bits outside of those defined in MODE.
8237 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8238 a shift, AND, or zero_extract, we can do better. */
8241 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8242 rtx known_x ATTRIBUTE_UNUSED,
8243 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8244 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8245 unsigned HOST_WIDE_INT *nonzero)
8249 /* If X is a register whose nonzero bits value is current, use it.
8250 Otherwise, if X is a register whose value we can find, use that
8251 value. Otherwise, use the previously-computed global nonzero bits
8252 for this register. */
8254 if (reg_stat[REGNO (x)].last_set_value != 0
8255 && (reg_stat[REGNO (x)].last_set_mode == mode
8256 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8257 && GET_MODE_CLASS (mode) == MODE_INT))
8258 && (reg_stat[REGNO (x)].last_set_label == label_tick
8259 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8260 && REG_N_SETS (REGNO (x)) == 1
8261 && ! REGNO_REG_SET_P
8262 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8264 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8266 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8270 tem = get_last_value (x);
8274 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8275 /* If X is narrower than MODE and TEM is a non-negative
8276 constant that would appear negative in the mode of X,
8277 sign-extend it for use in reg_nonzero_bits because some
8278 machines (maybe most) will actually do the sign-extension
8279 and this is the conservative approach.
8281 ??? For 2.5, try to tighten up the MD files in this regard
8282 instead of this kludge. */
8284 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8285 && GET_CODE (tem) == CONST_INT
8287 && 0 != (INTVAL (tem)
8288 & ((HOST_WIDE_INT) 1
8289 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8290 tem = GEN_INT (INTVAL (tem)
8291 | ((HOST_WIDE_INT) (-1)
8292 << GET_MODE_BITSIZE (GET_MODE (x))));
8296 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8298 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8300 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8301 /* We don't know anything about the upper bits. */
8302 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8309 /* Return the number of bits at the high-order end of X that are known to
8310 be equal to the sign bit. X will be used in mode MODE; if MODE is
8311 VOIDmode, X will be used in its own mode. The returned value will always
8312 be between 1 and the number of bits in MODE. */
8315 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8316 rtx known_x ATTRIBUTE_UNUSED,
8317 enum machine_mode known_mode
8319 unsigned int known_ret ATTRIBUTE_UNUSED,
8320 unsigned int *result)
8324 if (reg_stat[REGNO (x)].last_set_value != 0
8325 && reg_stat[REGNO (x)].last_set_mode == mode
8326 && (reg_stat[REGNO (x)].last_set_label == label_tick
8327 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8328 && REG_N_SETS (REGNO (x)) == 1
8329 && ! REGNO_REG_SET_P
8330 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8332 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8334 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8338 tem = get_last_value (x);
8342 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8343 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8344 *result = reg_stat[REGNO (x)].sign_bit_copies;
8349 /* Return the number of "extended" bits there are in X, when interpreted
8350 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8351 unsigned quantities, this is the number of high-order zero bits.
8352 For signed quantities, this is the number of copies of the sign bit
8353 minus 1. In both case, this function returns the number of "spare"
8354 bits. For example, if two quantities for which this function returns
8355 at least 1 are added, the addition is known not to overflow.
8357 This function will always return 0 unless called during combine, which
8358 implies that it must be called from a define_split. */
8361 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8363 if (nonzero_sign_valid == 0)
8367 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8368 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8369 - floor_log2 (nonzero_bits (x, mode)))
8371 : num_sign_bit_copies (x, mode) - 1);
8374 /* This function is called from `simplify_shift_const' to merge two
8375 outer operations. Specifically, we have already found that we need
8376 to perform operation *POP0 with constant *PCONST0 at the outermost
8377 position. We would now like to also perform OP1 with constant CONST1
8378 (with *POP0 being done last).
8380 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8381 the resulting operation. *PCOMP_P is set to 1 if we would need to
8382 complement the innermost operand, otherwise it is unchanged.
8384 MODE is the mode in which the operation will be done. No bits outside
8385 the width of this mode matter. It is assumed that the width of this mode
8386 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8388 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8389 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8390 result is simply *PCONST0.
8392 If the resulting operation cannot be expressed as one operation, we
8393 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8396 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8398 enum rtx_code op0 = *pop0;
8399 HOST_WIDE_INT const0 = *pconst0;
8401 const0 &= GET_MODE_MASK (mode);
8402 const1 &= GET_MODE_MASK (mode);
8404 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8408 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8411 if (op1 == UNKNOWN || op0 == SET)
8414 else if (op0 == UNKNOWN)
8415 op0 = op1, const0 = const1;
8417 else if (op0 == op1)
8441 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8442 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8445 /* If the two constants aren't the same, we can't do anything. The
8446 remaining six cases can all be done. */
8447 else if (const0 != const1)
8455 /* (a & b) | b == b */
8457 else /* op1 == XOR */
8458 /* (a ^ b) | b == a | b */
8464 /* (a & b) ^ b == (~a) & b */
8465 op0 = AND, *pcomp_p = 1;
8466 else /* op1 == IOR */
8467 /* (a | b) ^ b == a & ~b */
8468 op0 = AND, const0 = ~const0;
8473 /* (a | b) & b == b */
8475 else /* op1 == XOR */
8476 /* (a ^ b) & b) == (~a) & b */
8483 /* Check for NO-OP cases. */
8484 const0 &= GET_MODE_MASK (mode);
8486 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8488 else if (const0 == 0 && op0 == AND)
8490 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8494 /* ??? Slightly redundant with the above mask, but not entirely.
8495 Moving this above means we'd have to sign-extend the mode mask
8496 for the final test. */
8497 const0 = trunc_int_for_mode (const0, mode);
8505 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8506 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8507 simplify it. Otherwise, return a simplified value.
8509 The shift is normally computed in the widest mode we find in VAROP, as
8510 long as it isn't a different number of words than RESULT_MODE. Exceptions
8511 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8514 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8515 rtx varop, int orig_count)
8517 enum rtx_code orig_code = code;
8518 rtx orig_varop = varop;
8520 enum machine_mode mode = result_mode;
8521 enum machine_mode shift_mode, tmode;
8522 unsigned int mode_words
8523 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8524 /* We form (outer_op (code varop count) (outer_const)). */
8525 enum rtx_code outer_op = UNKNOWN;
8526 HOST_WIDE_INT outer_const = 0;
8527 int complement_p = 0;
8530 /* Make sure and truncate the "natural" shift on the way in. We don't
8531 want to do this inside the loop as it makes it more difficult to
8533 if (SHIFT_COUNT_TRUNCATED)
8534 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8536 /* If we were given an invalid count, don't do anything except exactly
8537 what was requested. */
8539 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8544 /* Unless one of the branches of the `if' in this loop does a `continue',
8545 we will `break' the loop after the `if'. */
8549 /* If we have an operand of (clobber (const_int 0)), fail. */
8550 if (GET_CODE (varop) == CLOBBER)
8553 /* If we discovered we had to complement VAROP, leave. Making a NOT
8554 here would cause an infinite loop. */
8558 /* Convert ROTATERT to ROTATE. */
8559 if (code == ROTATERT)
8561 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8563 if (VECTOR_MODE_P (result_mode))
8564 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8566 count = bitsize - count;
8569 /* We need to determine what mode we will do the shift in. If the
8570 shift is a right shift or a ROTATE, we must always do it in the mode
8571 it was originally done in. Otherwise, we can do it in MODE, the
8572 widest mode encountered. */
8574 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8575 ? result_mode : mode);
8577 /* Handle cases where the count is greater than the size of the mode
8578 minus 1. For ASHIFT, use the size minus one as the count (this can
8579 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8580 take the count modulo the size. For other shifts, the result is
8583 Since these shifts are being produced by the compiler by combining
8584 multiple operations, each of which are defined, we know what the
8585 result is supposed to be. */
8587 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8589 if (code == ASHIFTRT)
8590 count = GET_MODE_BITSIZE (shift_mode) - 1;
8591 else if (code == ROTATE || code == ROTATERT)
8592 count %= GET_MODE_BITSIZE (shift_mode);
8595 /* We can't simply return zero because there may be an
8603 /* An arithmetic right shift of a quantity known to be -1 or 0
8605 if (code == ASHIFTRT
8606 && (num_sign_bit_copies (varop, shift_mode)
8607 == GET_MODE_BITSIZE (shift_mode)))
8613 /* If we are doing an arithmetic right shift and discarding all but
8614 the sign bit copies, this is equivalent to doing a shift by the
8615 bitsize minus one. Convert it into that shift because it will often
8616 allow other simplifications. */
8618 if (code == ASHIFTRT
8619 && (count + num_sign_bit_copies (varop, shift_mode)
8620 >= GET_MODE_BITSIZE (shift_mode)))
8621 count = GET_MODE_BITSIZE (shift_mode) - 1;
8623 /* We simplify the tests below and elsewhere by converting
8624 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8625 `make_compound_operation' will convert it to an ASHIFTRT for
8626 those machines (such as VAX) that don't have an LSHIFTRT. */
8627 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8629 && ((nonzero_bits (varop, shift_mode)
8630 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8634 if (code == LSHIFTRT
8635 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8636 && !(nonzero_bits (varop, shift_mode) >> count))
8639 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8640 && !((nonzero_bits (varop, shift_mode) << count)
8641 & GET_MODE_MASK (shift_mode)))
8644 switch (GET_CODE (varop))
8650 new = expand_compound_operation (varop);
8659 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8660 minus the width of a smaller mode, we can do this with a
8661 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8662 if ((code == ASHIFTRT || code == LSHIFTRT)
8663 && ! mode_dependent_address_p (XEXP (varop, 0))
8664 && ! MEM_VOLATILE_P (varop)
8665 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8666 MODE_INT, 1)) != BLKmode)
8668 new = adjust_address_nv (varop, tmode,
8669 BYTES_BIG_ENDIAN ? 0
8670 : count / BITS_PER_UNIT);
8672 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8673 : ZERO_EXTEND, mode, new);
8680 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8681 the same number of words as what we've seen so far. Then store
8682 the widest mode in MODE. */
8683 if (subreg_lowpart_p (varop)
8684 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8685 > GET_MODE_SIZE (GET_MODE (varop)))
8686 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8687 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8690 varop = SUBREG_REG (varop);
8691 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8692 mode = GET_MODE (varop);
8698 /* Some machines use MULT instead of ASHIFT because MULT
8699 is cheaper. But it is still better on those machines to
8700 merge two shifts into one. */
8701 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8702 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8705 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8707 GEN_INT (exact_log2 (
8708 INTVAL (XEXP (varop, 1)))));
8714 /* Similar, for when divides are cheaper. */
8715 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8716 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8719 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8721 GEN_INT (exact_log2 (
8722 INTVAL (XEXP (varop, 1)))));
8728 /* If we are extracting just the sign bit of an arithmetic
8729 right shift, that shift is not needed. However, the sign
8730 bit of a wider mode may be different from what would be
8731 interpreted as the sign bit in a narrower mode, so, if
8732 the result is narrower, don't discard the shift. */
8733 if (code == LSHIFTRT
8734 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8735 && (GET_MODE_BITSIZE (result_mode)
8736 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8738 varop = XEXP (varop, 0);
8742 /* ... fall through ... */
8747 /* Here we have two nested shifts. The result is usually the
8748 AND of a new shift with a mask. We compute the result below. */
8749 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8750 && INTVAL (XEXP (varop, 1)) >= 0
8751 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8752 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8753 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8754 && !VECTOR_MODE_P (result_mode))
8756 enum rtx_code first_code = GET_CODE (varop);
8757 unsigned int first_count = INTVAL (XEXP (varop, 1));
8758 unsigned HOST_WIDE_INT mask;
8761 /* We have one common special case. We can't do any merging if
8762 the inner code is an ASHIFTRT of a smaller mode. However, if
8763 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8764 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8765 we can convert it to
8766 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8767 This simplifies certain SIGN_EXTEND operations. */
8768 if (code == ASHIFT && first_code == ASHIFTRT
8769 && count == (GET_MODE_BITSIZE (result_mode)
8770 - GET_MODE_BITSIZE (GET_MODE (varop))))
8772 /* C3 has the low-order C1 bits zero. */
8774 mask = (GET_MODE_MASK (mode)
8775 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8777 varop = simplify_and_const_int (NULL_RTX, result_mode,
8778 XEXP (varop, 0), mask);
8779 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8781 count = first_count;
8786 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8787 than C1 high-order bits equal to the sign bit, we can convert
8788 this to either an ASHIFT or an ASHIFTRT depending on the
8791 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8793 if (code == ASHIFTRT && first_code == ASHIFT
8794 && GET_MODE (varop) == shift_mode
8795 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8798 varop = XEXP (varop, 0);
8799 count -= first_count;
8809 /* There are some cases we can't do. If CODE is ASHIFTRT,
8810 we can only do this if FIRST_CODE is also ASHIFTRT.
8812 We can't do the case when CODE is ROTATE and FIRST_CODE is
8815 If the mode of this shift is not the mode of the outer shift,
8816 we can't do this if either shift is a right shift or ROTATE.
8818 Finally, we can't do any of these if the mode is too wide
8819 unless the codes are the same.
8821 Handle the case where the shift codes are the same
8824 if (code == first_code)
8826 if (GET_MODE (varop) != result_mode
8827 && (code == ASHIFTRT || code == LSHIFTRT
8831 count += first_count;
8832 varop = XEXP (varop, 0);
8836 if (code == ASHIFTRT
8837 || (code == ROTATE && first_code == ASHIFTRT)
8838 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8839 || (GET_MODE (varop) != result_mode
8840 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8841 || first_code == ROTATE
8842 || code == ROTATE)))
8845 /* To compute the mask to apply after the shift, shift the
8846 nonzero bits of the inner shift the same way the
8847 outer shift will. */
8849 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8852 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8855 /* Give up if we can't compute an outer operation to use. */
8857 || GET_CODE (mask_rtx) != CONST_INT
8858 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8860 result_mode, &complement_p))
8863 /* If the shifts are in the same direction, we add the
8864 counts. Otherwise, we subtract them. */
8865 if ((code == ASHIFTRT || code == LSHIFTRT)
8866 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8867 count += first_count;
8869 count -= first_count;
8871 /* If COUNT is positive, the new shift is usually CODE,
8872 except for the two exceptions below, in which case it is
8873 FIRST_CODE. If the count is negative, FIRST_CODE should
8876 && ((first_code == ROTATE && code == ASHIFT)
8877 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8880 code = first_code, count = -count;
8882 varop = XEXP (varop, 0);
8886 /* If we have (A << B << C) for any shift, we can convert this to
8887 (A << C << B). This wins if A is a constant. Only try this if
8888 B is not a constant. */
8890 else if (GET_CODE (varop) == code
8891 && GET_CODE (XEXP (varop, 0)) == CONST_INT
8892 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8894 rtx new = simplify_const_binary_operation (code, mode,
8897 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8904 /* Make this fit the case below. */
8905 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8906 GEN_INT (GET_MODE_MASK (mode)));
8912 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8913 with C the size of VAROP - 1 and the shift is logical if
8914 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8915 we have an (le X 0) operation. If we have an arithmetic shift
8916 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8917 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8919 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8920 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8921 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8922 && (code == LSHIFTRT || code == ASHIFTRT)
8923 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8924 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8927 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8930 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8931 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8936 /* If we have (shift (logical)), move the logical to the outside
8937 to allow it to possibly combine with another logical and the
8938 shift to combine with another shift. This also canonicalizes to
8939 what a ZERO_EXTRACT looks like. Also, some machines have
8940 (and (shift)) insns. */
8942 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8943 /* We can't do this if we have (ashiftrt (xor)) and the
8944 constant has its sign bit set in shift_mode. */
8945 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8946 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8948 && (new = simplify_const_binary_operation (code, result_mode,
8950 GEN_INT (count))) != 0
8951 && GET_CODE (new) == CONST_INT
8952 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8953 INTVAL (new), result_mode, &complement_p))
8955 varop = XEXP (varop, 0);
8959 /* If we can't do that, try to simplify the shift in each arm of the
8960 logical expression, make a new logical expression, and apply
8961 the inverse distributive law. This also can't be done
8962 for some (ashiftrt (xor)). */
8963 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8964 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8965 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8968 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8969 XEXP (varop, 0), count);
8970 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8971 XEXP (varop, 1), count);
8973 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8975 varop = apply_distributive_law (varop);
8983 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8984 says that the sign bit can be tested, FOO has mode MODE, C is
8985 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8986 that may be nonzero. */
8987 if (code == LSHIFTRT
8988 && XEXP (varop, 1) == const0_rtx
8989 && GET_MODE (XEXP (varop, 0)) == result_mode
8990 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8991 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8992 && STORE_FLAG_VALUE == -1
8993 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8994 && merge_outer_ops (&outer_op, &outer_const, XOR,
8995 (HOST_WIDE_INT) 1, result_mode,
8998 varop = XEXP (varop, 0);
9005 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9006 than the number of bits in the mode is equivalent to A. */
9007 if (code == LSHIFTRT
9008 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9009 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9011 varop = XEXP (varop, 0);
9016 /* NEG commutes with ASHIFT since it is multiplication. Move the
9017 NEG outside to allow shifts to combine. */
9019 && merge_outer_ops (&outer_op, &outer_const, NEG,
9020 (HOST_WIDE_INT) 0, result_mode,
9023 varop = XEXP (varop, 0);
9029 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9030 is one less than the number of bits in the mode is
9031 equivalent to (xor A 1). */
9032 if (code == LSHIFTRT
9033 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9034 && XEXP (varop, 1) == constm1_rtx
9035 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9036 && merge_outer_ops (&outer_op, &outer_const, XOR,
9037 (HOST_WIDE_INT) 1, result_mode,
9041 varop = XEXP (varop, 0);
9045 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9046 that might be nonzero in BAR are those being shifted out and those
9047 bits are known zero in FOO, we can replace the PLUS with FOO.
9048 Similarly in the other operand order. This code occurs when
9049 we are computing the size of a variable-size array. */
9051 if ((code == ASHIFTRT || code == LSHIFTRT)
9052 && count < HOST_BITS_PER_WIDE_INT
9053 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9054 && (nonzero_bits (XEXP (varop, 1), result_mode)
9055 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9057 varop = XEXP (varop, 0);
9060 else if ((code == ASHIFTRT || code == LSHIFTRT)
9061 && count < HOST_BITS_PER_WIDE_INT
9062 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9063 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9065 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9066 & nonzero_bits (XEXP (varop, 1),
9069 varop = XEXP (varop, 1);
9073 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9075 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9076 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9078 GEN_INT (count))) != 0
9079 && GET_CODE (new) == CONST_INT
9080 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9081 INTVAL (new), result_mode, &complement_p))
9083 varop = XEXP (varop, 0);
9087 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9088 signbit', and attempt to change the PLUS to an XOR and move it to
9089 the outer operation as is done above in the AND/IOR/XOR case
9090 leg for shift(logical). See details in logical handling above
9091 for reasoning in doing so. */
9092 if (code == LSHIFTRT
9093 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9094 && mode_signbit_p (result_mode, XEXP (varop, 1))
9095 && (new = simplify_const_binary_operation (code, result_mode,
9097 GEN_INT (count))) != 0
9098 && GET_CODE (new) == CONST_INT
9099 && merge_outer_ops (&outer_op, &outer_const, XOR,
9100 INTVAL (new), result_mode, &complement_p))
9102 varop = XEXP (varop, 0);
9109 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9110 with C the size of VAROP - 1 and the shift is logical if
9111 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9112 we have a (gt X 0) operation. If the shift is arithmetic with
9113 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9114 we have a (neg (gt X 0)) operation. */
9116 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9117 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9118 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9119 && (code == LSHIFTRT || code == ASHIFTRT)
9120 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9121 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9122 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9125 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9128 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9129 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9136 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9137 if the truncate does not affect the value. */
9138 if (code == LSHIFTRT
9139 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9140 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9141 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9142 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9143 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9145 rtx varop_inner = XEXP (varop, 0);
9148 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9149 XEXP (varop_inner, 0),
9151 (count + INTVAL (XEXP (varop_inner, 1))));
9152 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9165 /* We need to determine what mode to do the shift in. If the shift is
9166 a right shift or ROTATE, we must always do it in the mode it was
9167 originally done in. Otherwise, we can do it in MODE, the widest mode
9168 encountered. The code we care about is that of the shift that will
9169 actually be done, not the shift that was originally requested. */
9171 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9172 ? result_mode : mode);
9174 /* We have now finished analyzing the shift. The result should be
9175 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9176 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9177 to the result of the shift. OUTER_CONST is the relevant constant,
9178 but we must turn off all bits turned off in the shift. */
9180 if (outer_op == UNKNOWN
9181 && orig_code == code && orig_count == count
9182 && varop == orig_varop
9183 && shift_mode == GET_MODE (varop))
9186 /* Make a SUBREG if necessary. If we can't make it, fail. */
9187 varop = gen_lowpart (shift_mode, varop);
9188 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9191 /* If we have an outer operation and we just made a shift, it is
9192 possible that we could have simplified the shift were it not
9193 for the outer operation. So try to do the simplification
9196 if (outer_op != UNKNOWN)
9197 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9202 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9204 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9205 turn off all the bits that the shift would have turned off. */
9206 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9207 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9208 GET_MODE_MASK (result_mode) >> orig_count);
9210 /* Do the remainder of the processing in RESULT_MODE. */
9211 x = gen_lowpart_or_truncate (result_mode, x);
9213 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9216 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9218 if (outer_op != UNKNOWN)
9220 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9221 outer_const = trunc_int_for_mode (outer_const, result_mode);
9223 if (outer_op == AND)
9224 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9225 else if (outer_op == SET)
9226 /* This means that we have determined that the result is
9227 equivalent to a constant. This should be rare. */
9228 x = GEN_INT (outer_const);
9229 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9230 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9232 x = simplify_gen_binary (outer_op, result_mode, x,
9233 GEN_INT (outer_const));
9239 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9240 The result of the shift is RESULT_MODE. If we cannot simplify it,
9241 return X or, if it is NULL, synthesize the expression with
9242 simplify_gen_binary. Otherwise, return a simplified value.
9244 The shift is normally computed in the widest mode we find in VAROP, as
9245 long as it isn't a different number of words than RESULT_MODE. Exceptions
9246 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9249 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9250 rtx varop, int count)
9252 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9257 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9258 if (GET_MODE (x) != result_mode)
9259 x = gen_lowpart (result_mode, x);
9264 /* Like recog, but we receive the address of a pointer to a new pattern.
9265 We try to match the rtx that the pointer points to.
9266 If that fails, we may try to modify or replace the pattern,
9267 storing the replacement into the same pointer object.
9269 Modifications include deletion or addition of CLOBBERs.
9271 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9272 the CLOBBERs are placed.
9274 The value is the final insn code from the pattern ultimately matched,
9278 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9281 int insn_code_number;
9282 int num_clobbers_to_add = 0;
9285 rtx old_notes, old_pat;
9287 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9288 we use to indicate that something didn't match. If we find such a
9289 thing, force rejection. */
9290 if (GET_CODE (pat) == PARALLEL)
9291 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9292 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9293 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9296 old_pat = PATTERN (insn);
9297 old_notes = REG_NOTES (insn);
9298 PATTERN (insn) = pat;
9299 REG_NOTES (insn) = 0;
9301 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9303 /* If it isn't, there is the possibility that we previously had an insn
9304 that clobbered some register as a side effect, but the combined
9305 insn doesn't need to do that. So try once more without the clobbers
9306 unless this represents an ASM insn. */
9308 if (insn_code_number < 0 && ! check_asm_operands (pat)
9309 && GET_CODE (pat) == PARALLEL)
9313 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9314 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9317 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9321 SUBST_INT (XVECLEN (pat, 0), pos);
9324 pat = XVECEXP (pat, 0, 0);
9326 PATTERN (insn) = pat;
9327 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9329 PATTERN (insn) = old_pat;
9330 REG_NOTES (insn) = old_notes;
9332 /* Recognize all noop sets, these will be killed by followup pass. */
9333 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9334 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9336 /* If we had any clobbers to add, make a new pattern than contains
9337 them. Then check to make sure that all of them are dead. */
9338 if (num_clobbers_to_add)
9340 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9341 rtvec_alloc (GET_CODE (pat) == PARALLEL
9343 + num_clobbers_to_add)
9344 : num_clobbers_to_add + 1));
9346 if (GET_CODE (pat) == PARALLEL)
9347 for (i = 0; i < XVECLEN (pat, 0); i++)
9348 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9350 XVECEXP (newpat, 0, 0) = pat;
9352 add_clobbers (newpat, insn_code_number);
9354 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9355 i < XVECLEN (newpat, 0); i++)
9357 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9358 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9360 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9361 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9369 return insn_code_number;
9372 /* Like gen_lowpart_general but for use by combine. In combine it
9373 is not possible to create any new pseudoregs. However, it is
9374 safe to create invalid memory addresses, because combine will
9375 try to recognize them and all they will do is make the combine
9378 If for some reason this cannot do its job, an rtx
9379 (clobber (const_int 0)) is returned.
9380 An insn containing that will not be recognized. */
9383 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9385 enum machine_mode imode = GET_MODE (x);
9386 unsigned int osize = GET_MODE_SIZE (omode);
9387 unsigned int isize = GET_MODE_SIZE (imode);
9393 /* Return identity if this is a CONST or symbolic reference. */
9395 && (GET_CODE (x) == CONST
9396 || GET_CODE (x) == SYMBOL_REF
9397 || GET_CODE (x) == LABEL_REF))
9400 /* We can only support MODE being wider than a word if X is a
9401 constant integer or has a mode the same size. */
9402 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9403 && ! ((imode == VOIDmode
9404 && (GET_CODE (x) == CONST_INT
9405 || GET_CODE (x) == CONST_DOUBLE))
9409 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9410 won't know what to do. So we will strip off the SUBREG here and
9411 process normally. */
9412 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9416 /* For use in case we fall down into the address adjustments
9417 further below, we need to adjust the known mode and size of
9418 x; imode and isize, since we just adjusted x. */
9419 imode = GET_MODE (x);
9424 isize = GET_MODE_SIZE (imode);
9427 result = gen_lowpart_common (omode, x);
9429 #ifdef CANNOT_CHANGE_MODE_CLASS
9430 if (result != 0 && GET_CODE (result) == SUBREG)
9431 record_subregs_of_mode (result);
9441 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9443 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9446 /* If we want to refer to something bigger than the original memref,
9447 generate a paradoxical subreg instead. That will force a reload
9448 of the original memref X. */
9450 return gen_rtx_SUBREG (omode, x, 0);
9452 if (WORDS_BIG_ENDIAN)
9453 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9455 /* Adjust the address so that the address-after-the-data is
9457 if (BYTES_BIG_ENDIAN)
9458 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9460 return adjust_address_nv (x, omode, offset);
9463 /* If X is a comparison operator, rewrite it in a new mode. This
9464 probably won't match, but may allow further simplifications. */
9465 else if (COMPARISON_P (x))
9466 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9468 /* If we couldn't simplify X any other way, just enclose it in a
9469 SUBREG. Normally, this SUBREG won't match, but some patterns may
9470 include an explicit SUBREG or we may simplify it further in combine. */
9476 offset = subreg_lowpart_offset (omode, imode);
9477 if (imode == VOIDmode)
9479 imode = int_mode_for_mode (omode);
9480 x = gen_lowpart_common (imode, x);
9484 res = simplify_gen_subreg (omode, x, imode, offset);
9490 return gen_rtx_CLOBBER (imode, const0_rtx);
9493 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9494 comparison code that will be tested.
9496 The result is a possibly different comparison code to use. *POP0 and
9497 *POP1 may be updated.
9499 It is possible that we might detect that a comparison is either always
9500 true or always false. However, we do not perform general constant
9501 folding in combine, so this knowledge isn't useful. Such tautologies
9502 should have been detected earlier. Hence we ignore all such cases. */
9504 static enum rtx_code
9505 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9511 enum machine_mode mode, tmode;
9513 /* Try a few ways of applying the same transformation to both operands. */
9516 #ifndef WORD_REGISTER_OPERATIONS
9517 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9518 so check specially. */
9519 if (code != GTU && code != GEU && code != LTU && code != LEU
9520 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9521 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9522 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9523 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9524 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9525 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9526 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9527 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9528 && XEXP (op0, 1) == XEXP (op1, 1)
9529 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9530 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9531 && (INTVAL (XEXP (op0, 1))
9532 == (GET_MODE_BITSIZE (GET_MODE (op0))
9534 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9536 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9537 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9541 /* If both operands are the same constant shift, see if we can ignore the
9542 shift. We can if the shift is a rotate or if the bits shifted out of
9543 this shift are known to be zero for both inputs and if the type of
9544 comparison is compatible with the shift. */
9545 if (GET_CODE (op0) == GET_CODE (op1)
9546 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9547 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9548 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9549 && (code != GT && code != LT && code != GE && code != LE))
9550 || (GET_CODE (op0) == ASHIFTRT
9551 && (code != GTU && code != LTU
9552 && code != GEU && code != LEU)))
9553 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9554 && INTVAL (XEXP (op0, 1)) >= 0
9555 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9556 && XEXP (op0, 1) == XEXP (op1, 1))
9558 enum machine_mode mode = GET_MODE (op0);
9559 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9560 int shift_count = INTVAL (XEXP (op0, 1));
9562 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9563 mask &= (mask >> shift_count) << shift_count;
9564 else if (GET_CODE (op0) == ASHIFT)
9565 mask = (mask & (mask << shift_count)) >> shift_count;
9567 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9568 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9569 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9574 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9575 SUBREGs are of the same mode, and, in both cases, the AND would
9576 be redundant if the comparison was done in the narrower mode,
9577 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9578 and the operand's possibly nonzero bits are 0xffffff01; in that case
9579 if we only care about QImode, we don't need the AND). This case
9580 occurs if the output mode of an scc insn is not SImode and
9581 STORE_FLAG_VALUE == 1 (e.g., the 386).
9583 Similarly, check for a case where the AND's are ZERO_EXTEND
9584 operations from some narrower mode even though a SUBREG is not
9587 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9588 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9589 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9591 rtx inner_op0 = XEXP (op0, 0);
9592 rtx inner_op1 = XEXP (op1, 0);
9593 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9594 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9597 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9598 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9599 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9600 && (GET_MODE (SUBREG_REG (inner_op0))
9601 == GET_MODE (SUBREG_REG (inner_op1)))
9602 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9603 <= HOST_BITS_PER_WIDE_INT)
9604 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9605 GET_MODE (SUBREG_REG (inner_op0)))))
9606 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9607 GET_MODE (SUBREG_REG (inner_op1))))))
9609 op0 = SUBREG_REG (inner_op0);
9610 op1 = SUBREG_REG (inner_op1);
9612 /* The resulting comparison is always unsigned since we masked
9613 off the original sign bit. */
9614 code = unsigned_condition (code);
9620 for (tmode = GET_CLASS_NARROWEST_MODE
9621 (GET_MODE_CLASS (GET_MODE (op0)));
9622 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9623 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9625 op0 = gen_lowpart (tmode, inner_op0);
9626 op1 = gen_lowpart (tmode, inner_op1);
9627 code = unsigned_condition (code);
9636 /* If both operands are NOT, we can strip off the outer operation
9637 and adjust the comparison code for swapped operands; similarly for
9638 NEG, except that this must be an equality comparison. */
9639 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9640 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9641 && (code == EQ || code == NE)))
9642 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9648 /* If the first operand is a constant, swap the operands and adjust the
9649 comparison code appropriately, but don't do this if the second operand
9650 is already a constant integer. */
9651 if (swap_commutative_operands_p (op0, op1))
9653 tem = op0, op0 = op1, op1 = tem;
9654 code = swap_condition (code);
9657 /* We now enter a loop during which we will try to simplify the comparison.
9658 For the most part, we only are concerned with comparisons with zero,
9659 but some things may really be comparisons with zero but not start
9660 out looking that way. */
9662 while (GET_CODE (op1) == CONST_INT)
9664 enum machine_mode mode = GET_MODE (op0);
9665 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9666 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9667 int equality_comparison_p;
9668 int sign_bit_comparison_p;
9669 int unsigned_comparison_p;
9670 HOST_WIDE_INT const_op;
9672 /* We only want to handle integral modes. This catches VOIDmode,
9673 CCmode, and the floating-point modes. An exception is that we
9674 can handle VOIDmode if OP0 is a COMPARE or a comparison
9677 if (GET_MODE_CLASS (mode) != MODE_INT
9678 && ! (mode == VOIDmode
9679 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9682 /* Get the constant we are comparing against and turn off all bits
9683 not on in our mode. */
9684 const_op = INTVAL (op1);
9685 if (mode != VOIDmode)
9686 const_op = trunc_int_for_mode (const_op, mode);
9687 op1 = GEN_INT (const_op);
9689 /* If we are comparing against a constant power of two and the value
9690 being compared can only have that single bit nonzero (e.g., it was
9691 `and'ed with that bit), we can replace this with a comparison
9694 && (code == EQ || code == NE || code == GE || code == GEU
9695 || code == LT || code == LTU)
9696 && mode_width <= HOST_BITS_PER_WIDE_INT
9697 && exact_log2 (const_op) >= 0
9698 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9700 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9701 op1 = const0_rtx, const_op = 0;
9704 /* Similarly, if we are comparing a value known to be either -1 or
9705 0 with -1, change it to the opposite comparison against zero. */
9708 && (code == EQ || code == NE || code == GT || code == LE
9709 || code == GEU || code == LTU)
9710 && num_sign_bit_copies (op0, mode) == mode_width)
9712 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9713 op1 = const0_rtx, const_op = 0;
9716 /* Do some canonicalizations based on the comparison code. We prefer
9717 comparisons against zero and then prefer equality comparisons.
9718 If we can reduce the size of a constant, we will do that too. */
9723 /* < C is equivalent to <= (C - 1) */
9727 op1 = GEN_INT (const_op);
9729 /* ... fall through to LE case below. */
9735 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9739 op1 = GEN_INT (const_op);
9743 /* If we are doing a <= 0 comparison on a value known to have
9744 a zero sign bit, we can replace this with == 0. */
9745 else if (const_op == 0
9746 && mode_width <= HOST_BITS_PER_WIDE_INT
9747 && (nonzero_bits (op0, mode)
9748 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9753 /* >= C is equivalent to > (C - 1). */
9757 op1 = GEN_INT (const_op);
9759 /* ... fall through to GT below. */
9765 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9769 op1 = GEN_INT (const_op);
9773 /* If we are doing a > 0 comparison on a value known to have
9774 a zero sign bit, we can replace this with != 0. */
9775 else if (const_op == 0
9776 && mode_width <= HOST_BITS_PER_WIDE_INT
9777 && (nonzero_bits (op0, mode)
9778 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9783 /* < C is equivalent to <= (C - 1). */
9787 op1 = GEN_INT (const_op);
9789 /* ... fall through ... */
9792 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9793 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9794 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9796 const_op = 0, op1 = const0_rtx;
9804 /* unsigned <= 0 is equivalent to == 0 */
9808 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9809 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9810 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9812 const_op = 0, op1 = const0_rtx;
9818 /* >= C is equivalent to > (C - 1). */
9822 op1 = GEN_INT (const_op);
9824 /* ... fall through ... */
9827 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9828 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9829 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9831 const_op = 0, op1 = const0_rtx;
9839 /* unsigned > 0 is equivalent to != 0 */
9843 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9844 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9845 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9847 const_op = 0, op1 = const0_rtx;
9856 /* Compute some predicates to simplify code below. */
9858 equality_comparison_p = (code == EQ || code == NE);
9859 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9860 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9863 /* If this is a sign bit comparison and we can do arithmetic in
9864 MODE, say that we will only be needing the sign bit of OP0. */
9865 if (sign_bit_comparison_p
9866 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9867 op0 = force_to_mode (op0, mode,
9869 << (GET_MODE_BITSIZE (mode) - 1)),
9872 /* Now try cases based on the opcode of OP0. If none of the cases
9873 does a "continue", we exit this loop immediately after the
9876 switch (GET_CODE (op0))
9879 /* If we are extracting a single bit from a variable position in
9880 a constant that has only a single bit set and are comparing it
9881 with zero, we can convert this into an equality comparison
9882 between the position and the location of the single bit. */
9883 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9884 have already reduced the shift count modulo the word size. */
9885 if (!SHIFT_COUNT_TRUNCATED
9886 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9887 && XEXP (op0, 1) == const1_rtx
9888 && equality_comparison_p && const_op == 0
9889 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9891 if (BITS_BIG_ENDIAN)
9893 enum machine_mode new_mode
9894 = mode_for_extraction (EP_extzv, 1);
9895 if (new_mode == MAX_MACHINE_MODE)
9896 i = BITS_PER_WORD - 1 - i;
9900 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9904 op0 = XEXP (op0, 2);
9908 /* Result is nonzero iff shift count is equal to I. */
9909 code = reverse_condition (code);
9913 /* ... fall through ... */
9916 tem = expand_compound_operation (op0);
9925 /* If testing for equality, we can take the NOT of the constant. */
9926 if (equality_comparison_p
9927 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9929 op0 = XEXP (op0, 0);
9934 /* If just looking at the sign bit, reverse the sense of the
9936 if (sign_bit_comparison_p)
9938 op0 = XEXP (op0, 0);
9939 code = (code == GE ? LT : GE);
9945 /* If testing for equality, we can take the NEG of the constant. */
9946 if (equality_comparison_p
9947 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9949 op0 = XEXP (op0, 0);
9954 /* The remaining cases only apply to comparisons with zero. */
9958 /* When X is ABS or is known positive,
9959 (neg X) is < 0 if and only if X != 0. */
9961 if (sign_bit_comparison_p
9962 && (GET_CODE (XEXP (op0, 0)) == ABS
9963 || (mode_width <= HOST_BITS_PER_WIDE_INT
9964 && (nonzero_bits (XEXP (op0, 0), mode)
9965 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9967 op0 = XEXP (op0, 0);
9968 code = (code == LT ? NE : EQ);
9972 /* If we have NEG of something whose two high-order bits are the
9973 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9974 if (num_sign_bit_copies (op0, mode) >= 2)
9976 op0 = XEXP (op0, 0);
9977 code = swap_condition (code);
9983 /* If we are testing equality and our count is a constant, we
9984 can perform the inverse operation on our RHS. */
9985 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9986 && (tem = simplify_binary_operation (ROTATERT, mode,
9987 op1, XEXP (op0, 1))) != 0)
9989 op0 = XEXP (op0, 0);
9994 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9995 a particular bit. Convert it to an AND of a constant of that
9996 bit. This will be converted into a ZERO_EXTRACT. */
9997 if (const_op == 0 && sign_bit_comparison_p
9998 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9999 && mode_width <= HOST_BITS_PER_WIDE_INT)
10001 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10004 - INTVAL (XEXP (op0, 1)))));
10005 code = (code == LT ? NE : EQ);
10009 /* Fall through. */
10012 /* ABS is ignorable inside an equality comparison with zero. */
10013 if (const_op == 0 && equality_comparison_p)
10015 op0 = XEXP (op0, 0);
10021 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10022 (compare FOO CONST) if CONST fits in FOO's mode and we
10023 are either testing inequality or have an unsigned
10024 comparison with ZERO_EXTEND or a signed comparison with
10025 SIGN_EXTEND. But don't do it if we don't have a compare
10026 insn of the given mode, since we'd have to revert it
10027 later on, and then we wouldn't know whether to sign- or
10029 mode = GET_MODE (XEXP (op0, 0));
10030 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10031 && ! unsigned_comparison_p
10032 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10033 && ((unsigned HOST_WIDE_INT) const_op
10034 < (((unsigned HOST_WIDE_INT) 1
10035 << (GET_MODE_BITSIZE (mode) - 1))))
10036 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10038 op0 = XEXP (op0, 0);
10044 /* Check for the case where we are comparing A - C1 with C2, that is
10046 (subreg:MODE (plus (A) (-C1))) op (C2)
10048 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10049 comparison in the wider mode. One of the following two conditions
10050 must be true in order for this to be valid:
10052 1. The mode extension results in the same bit pattern being added
10053 on both sides and the comparison is equality or unsigned. As
10054 C2 has been truncated to fit in MODE, the pattern can only be
10057 2. The mode extension results in the sign bit being copied on
10060 The difficulty here is that we have predicates for A but not for
10061 (A - C1) so we need to check that C1 is within proper bounds so
10062 as to perturbate A as little as possible. */
10064 if (mode_width <= HOST_BITS_PER_WIDE_INT
10065 && subreg_lowpart_p (op0)
10066 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10067 && GET_CODE (SUBREG_REG (op0)) == PLUS
10068 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10070 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10071 rtx a = XEXP (SUBREG_REG (op0), 0);
10072 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10075 && (unsigned HOST_WIDE_INT) c1
10076 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10077 && (equality_comparison_p || unsigned_comparison_p)
10078 /* (A - C1) zero-extends if it is positive and sign-extends
10079 if it is negative, C2 both zero- and sign-extends. */
10080 && ((0 == (nonzero_bits (a, inner_mode)
10081 & ~GET_MODE_MASK (mode))
10083 /* (A - C1) sign-extends if it is positive and 1-extends
10084 if it is negative, C2 both sign- and 1-extends. */
10085 || (num_sign_bit_copies (a, inner_mode)
10086 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10089 || ((unsigned HOST_WIDE_INT) c1
10090 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10091 /* (A - C1) always sign-extends, like C2. */
10092 && num_sign_bit_copies (a, inner_mode)
10093 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10094 - (mode_width - 1))))
10096 op0 = SUBREG_REG (op0);
10101 /* If the inner mode is narrower and we are extracting the low part,
10102 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10103 if (subreg_lowpart_p (op0)
10104 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10105 /* Fall through */ ;
10109 /* ... fall through ... */
10112 mode = GET_MODE (XEXP (op0, 0));
10113 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10114 && (unsigned_comparison_p || equality_comparison_p)
10115 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10116 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10117 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10119 op0 = XEXP (op0, 0);
10125 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10126 this for equality comparisons due to pathological cases involving
10128 if (equality_comparison_p
10129 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10130 op1, XEXP (op0, 1))))
10132 op0 = XEXP (op0, 0);
10137 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10138 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10139 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10141 op0 = XEXP (XEXP (op0, 0), 0);
10142 code = (code == LT ? EQ : NE);
10148 /* We used to optimize signed comparisons against zero, but that
10149 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10150 arrive here as equality comparisons, or (GEU, LTU) are
10151 optimized away. No need to special-case them. */
10153 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10154 (eq B (minus A C)), whichever simplifies. We can only do
10155 this for equality comparisons due to pathological cases involving
10157 if (equality_comparison_p
10158 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10159 XEXP (op0, 1), op1)))
10161 op0 = XEXP (op0, 0);
10166 if (equality_comparison_p
10167 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10168 XEXP (op0, 0), op1)))
10170 op0 = XEXP (op0, 1);
10175 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10176 of bits in X minus 1, is one iff X > 0. */
10177 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10178 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10179 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10181 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10183 op0 = XEXP (op0, 1);
10184 code = (code == GE ? LE : GT);
10190 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10191 if C is zero or B is a constant. */
10192 if (equality_comparison_p
10193 && 0 != (tem = simplify_binary_operation (XOR, mode,
10194 XEXP (op0, 1), op1)))
10196 op0 = XEXP (op0, 0);
10203 case UNEQ: case LTGT:
10204 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10205 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10206 case UNORDERED: case ORDERED:
10207 /* We can't do anything if OP0 is a condition code value, rather
10208 than an actual data value. */
10210 || CC0_P (XEXP (op0, 0))
10211 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10214 /* Get the two operands being compared. */
10215 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10216 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10218 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10220 /* Check for the cases where we simply want the result of the
10221 earlier test or the opposite of that result. */
10222 if (code == NE || code == EQ
10223 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10224 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10225 && (STORE_FLAG_VALUE
10226 & (((HOST_WIDE_INT) 1
10227 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10228 && (code == LT || code == GE)))
10230 enum rtx_code new_code;
10231 if (code == LT || code == NE)
10232 new_code = GET_CODE (op0);
10234 new_code = reversed_comparison_code (op0, NULL);
10236 if (new_code != UNKNOWN)
10247 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10249 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10250 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10251 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10253 op0 = XEXP (op0, 1);
10254 code = (code == GE ? GT : LE);
10260 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10261 will be converted to a ZERO_EXTRACT later. */
10262 if (const_op == 0 && equality_comparison_p
10263 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10264 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10266 op0 = simplify_and_const_int
10267 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10269 XEXP (XEXP (op0, 0), 1)),
10270 (HOST_WIDE_INT) 1);
10274 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10275 zero and X is a comparison and C1 and C2 describe only bits set
10276 in STORE_FLAG_VALUE, we can compare with X. */
10277 if (const_op == 0 && equality_comparison_p
10278 && mode_width <= HOST_BITS_PER_WIDE_INT
10279 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10280 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10281 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10282 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10283 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10285 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10286 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10287 if ((~STORE_FLAG_VALUE & mask) == 0
10288 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10289 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10290 && COMPARISON_P (tem))))
10292 op0 = XEXP (XEXP (op0, 0), 0);
10297 /* If we are doing an equality comparison of an AND of a bit equal
10298 to the sign bit, replace this with a LT or GE comparison of
10299 the underlying value. */
10300 if (equality_comparison_p
10302 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10303 && mode_width <= HOST_BITS_PER_WIDE_INT
10304 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10305 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10307 op0 = XEXP (op0, 0);
10308 code = (code == EQ ? GE : LT);
10312 /* If this AND operation is really a ZERO_EXTEND from a narrower
10313 mode, the constant fits within that mode, and this is either an
10314 equality or unsigned comparison, try to do this comparison in
10319 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10320 -> (ne:DI (reg:SI 4) (const_int 0))
10322 unless TRULY_NOOP_TRUNCATION allows it or the register is
10323 known to hold a value of the required mode the
10324 transformation is invalid. */
10325 if ((equality_comparison_p || unsigned_comparison_p)
10326 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10327 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10328 & GET_MODE_MASK (mode))
10330 && const_op >> i == 0
10331 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10332 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10333 GET_MODE_BITSIZE (GET_MODE (op0)))
10334 || (REG_P (XEXP (op0, 0))
10335 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10337 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10341 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10342 fits in both M1 and M2 and the SUBREG is either paradoxical
10343 or represents the low part, permute the SUBREG and the AND
10345 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10347 unsigned HOST_WIDE_INT c1;
10348 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10349 /* Require an integral mode, to avoid creating something like
10351 if (SCALAR_INT_MODE_P (tmode)
10352 /* It is unsafe to commute the AND into the SUBREG if the
10353 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10354 not defined. As originally written the upper bits
10355 have a defined value due to the AND operation.
10356 However, if we commute the AND inside the SUBREG then
10357 they no longer have defined values and the meaning of
10358 the code has been changed. */
10360 #ifdef WORD_REGISTER_OPERATIONS
10361 || (mode_width > GET_MODE_BITSIZE (tmode)
10362 && mode_width <= BITS_PER_WORD)
10364 || (mode_width <= GET_MODE_BITSIZE (tmode)
10365 && subreg_lowpart_p (XEXP (op0, 0))))
10366 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10367 && mode_width <= HOST_BITS_PER_WIDE_INT
10368 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10369 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10370 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10372 && c1 != GET_MODE_MASK (tmode))
10374 op0 = simplify_gen_binary (AND, tmode,
10375 SUBREG_REG (XEXP (op0, 0)),
10376 gen_int_mode (c1, tmode));
10377 op0 = gen_lowpart (mode, op0);
10382 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10383 if (const_op == 0 && equality_comparison_p
10384 && XEXP (op0, 1) == const1_rtx
10385 && GET_CODE (XEXP (op0, 0)) == NOT)
10387 op0 = simplify_and_const_int
10388 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10389 code = (code == NE ? EQ : NE);
10393 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10394 (eq (and (lshiftrt X) 1) 0).
10395 Also handle the case where (not X) is expressed using xor. */
10396 if (const_op == 0 && equality_comparison_p
10397 && XEXP (op0, 1) == const1_rtx
10398 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10400 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10401 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10403 if (GET_CODE (shift_op) == NOT
10404 || (GET_CODE (shift_op) == XOR
10405 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10406 && GET_CODE (shift_count) == CONST_INT
10407 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10408 && (INTVAL (XEXP (shift_op, 1))
10409 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10411 op0 = simplify_and_const_int
10413 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10414 (HOST_WIDE_INT) 1);
10415 code = (code == NE ? EQ : NE);
10422 /* If we have (compare (ashift FOO N) (const_int C)) and
10423 the high order N bits of FOO (N+1 if an inequality comparison)
10424 are known to be zero, we can do this by comparing FOO with C
10425 shifted right N bits so long as the low-order N bits of C are
10427 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10428 && INTVAL (XEXP (op0, 1)) >= 0
10429 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10430 < HOST_BITS_PER_WIDE_INT)
10432 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10433 && mode_width <= HOST_BITS_PER_WIDE_INT
10434 && (nonzero_bits (XEXP (op0, 0), mode)
10435 & ~(mask >> (INTVAL (XEXP (op0, 1))
10436 + ! equality_comparison_p))) == 0)
10438 /* We must perform a logical shift, not an arithmetic one,
10439 as we want the top N bits of C to be zero. */
10440 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10442 temp >>= INTVAL (XEXP (op0, 1));
10443 op1 = gen_int_mode (temp, mode);
10444 op0 = XEXP (op0, 0);
10448 /* If we are doing a sign bit comparison, it means we are testing
10449 a particular bit. Convert it to the appropriate AND. */
10450 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10451 && mode_width <= HOST_BITS_PER_WIDE_INT)
10453 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10456 - INTVAL (XEXP (op0, 1)))));
10457 code = (code == LT ? NE : EQ);
10461 /* If this an equality comparison with zero and we are shifting
10462 the low bit to the sign bit, we can convert this to an AND of the
10464 if (const_op == 0 && equality_comparison_p
10465 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10466 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10469 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10470 (HOST_WIDE_INT) 1);
10476 /* If this is an equality comparison with zero, we can do this
10477 as a logical shift, which might be much simpler. */
10478 if (equality_comparison_p && const_op == 0
10479 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10481 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10483 INTVAL (XEXP (op0, 1)));
10487 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10488 do the comparison in a narrower mode. */
10489 if (! unsigned_comparison_p
10490 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10491 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10492 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10493 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10494 MODE_INT, 1)) != BLKmode
10495 && (((unsigned HOST_WIDE_INT) const_op
10496 + (GET_MODE_MASK (tmode) >> 1) + 1)
10497 <= GET_MODE_MASK (tmode)))
10499 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10503 /* Likewise if OP0 is a PLUS of a sign extension with a
10504 constant, which is usually represented with the PLUS
10505 between the shifts. */
10506 if (! unsigned_comparison_p
10507 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10508 && GET_CODE (XEXP (op0, 0)) == PLUS
10509 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10510 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10511 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10512 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10513 MODE_INT, 1)) != BLKmode
10514 && (((unsigned HOST_WIDE_INT) const_op
10515 + (GET_MODE_MASK (tmode) >> 1) + 1)
10516 <= GET_MODE_MASK (tmode)))
10518 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10519 rtx add_const = XEXP (XEXP (op0, 0), 1);
10520 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10521 add_const, XEXP (op0, 1));
10523 op0 = simplify_gen_binary (PLUS, tmode,
10524 gen_lowpart (tmode, inner),
10529 /* ... fall through ... */
10531 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10532 the low order N bits of FOO are known to be zero, we can do this
10533 by comparing FOO with C shifted left N bits so long as no
10534 overflow occurs. */
10535 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10536 && INTVAL (XEXP (op0, 1)) >= 0
10537 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10538 && mode_width <= HOST_BITS_PER_WIDE_INT
10539 && (nonzero_bits (XEXP (op0, 0), mode)
10540 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10541 && (((unsigned HOST_WIDE_INT) const_op
10542 + (GET_CODE (op0) != LSHIFTRT
10543 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10546 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10548 /* If the shift was logical, then we must make the condition
10550 if (GET_CODE (op0) == LSHIFTRT)
10551 code = unsigned_condition (code);
10553 const_op <<= INTVAL (XEXP (op0, 1));
10554 op1 = GEN_INT (const_op);
10555 op0 = XEXP (op0, 0);
10559 /* If we are using this shift to extract just the sign bit, we
10560 can replace this with an LT or GE comparison. */
10562 && (equality_comparison_p || sign_bit_comparison_p)
10563 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10564 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10567 op0 = XEXP (op0, 0);
10568 code = (code == NE || code == GT ? LT : GE);
10580 /* Now make any compound operations involved in this comparison. Then,
10581 check for an outmost SUBREG on OP0 that is not doing anything or is
10582 paradoxical. The latter transformation must only be performed when
10583 it is known that the "extra" bits will be the same in op0 and op1 or
10584 that they don't matter. There are three cases to consider:
10586 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10587 care bits and we can assume they have any convenient value. So
10588 making the transformation is safe.
10590 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10591 In this case the upper bits of op0 are undefined. We should not make
10592 the simplification in that case as we do not know the contents of
10595 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10596 UNKNOWN. In that case we know those bits are zeros or ones. We must
10597 also be sure that they are the same as the upper bits of op1.
10599 We can never remove a SUBREG for a non-equality comparison because
10600 the sign bit is in a different place in the underlying object. */
10602 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10603 op1 = make_compound_operation (op1, SET);
10605 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10606 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10607 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10608 && (code == NE || code == EQ))
10610 if (GET_MODE_SIZE (GET_MODE (op0))
10611 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10613 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10615 if (REG_P (SUBREG_REG (op0)))
10617 op0 = SUBREG_REG (op0);
10618 op1 = gen_lowpart (GET_MODE (op0), op1);
10621 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10622 <= HOST_BITS_PER_WIDE_INT)
10623 && (nonzero_bits (SUBREG_REG (op0),
10624 GET_MODE (SUBREG_REG (op0)))
10625 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10627 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10629 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10630 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10631 op0 = SUBREG_REG (op0), op1 = tem;
10635 /* We now do the opposite procedure: Some machines don't have compare
10636 insns in all modes. If OP0's mode is an integer mode smaller than a
10637 word and we can't do a compare in that mode, see if there is a larger
10638 mode for which we can do the compare. There are a number of cases in
10639 which we can use the wider mode. */
10641 mode = GET_MODE (op0);
10642 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10643 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10644 && ! have_insn_for (COMPARE, mode))
10645 for (tmode = GET_MODE_WIDER_MODE (mode);
10647 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10648 tmode = GET_MODE_WIDER_MODE (tmode))
10649 if (have_insn_for (COMPARE, tmode))
10653 /* If the only nonzero bits in OP0 and OP1 are those in the
10654 narrower mode and this is an equality or unsigned comparison,
10655 we can use the wider mode. Similarly for sign-extended
10656 values, in which case it is true for all comparisons. */
10657 zero_extended = ((code == EQ || code == NE
10658 || code == GEU || code == GTU
10659 || code == LEU || code == LTU)
10660 && (nonzero_bits (op0, tmode)
10661 & ~GET_MODE_MASK (mode)) == 0
10662 && ((GET_CODE (op1) == CONST_INT
10663 || (nonzero_bits (op1, tmode)
10664 & ~GET_MODE_MASK (mode)) == 0)));
10667 || ((num_sign_bit_copies (op0, tmode)
10668 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10669 - GET_MODE_BITSIZE (mode)))
10670 && (num_sign_bit_copies (op1, tmode)
10671 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10672 - GET_MODE_BITSIZE (mode)))))
10674 /* If OP0 is an AND and we don't have an AND in MODE either,
10675 make a new AND in the proper mode. */
10676 if (GET_CODE (op0) == AND
10677 && !have_insn_for (AND, mode))
10678 op0 = simplify_gen_binary (AND, tmode,
10679 gen_lowpart (tmode,
10681 gen_lowpart (tmode,
10684 op0 = gen_lowpart (tmode, op0);
10685 if (zero_extended && GET_CODE (op1) == CONST_INT)
10686 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10687 op1 = gen_lowpart (tmode, op1);
10691 /* If this is a test for negative, we can make an explicit
10692 test of the sign bit. */
10694 if (op1 == const0_rtx && (code == LT || code == GE)
10695 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10697 op0 = simplify_gen_binary (AND, tmode,
10698 gen_lowpart (tmode, op0),
10699 GEN_INT ((HOST_WIDE_INT) 1
10700 << (GET_MODE_BITSIZE (mode)
10702 code = (code == LT) ? NE : EQ;
10707 #ifdef CANONICALIZE_COMPARISON
10708 /* If this machine only supports a subset of valid comparisons, see if we
10709 can convert an unsupported one into a supported one. */
10710 CANONICALIZE_COMPARISON (code, op0, op1);
10719 /* Utility function for record_value_for_reg. Count number of
10724 enum rtx_code code = GET_CODE (x);
10728 if (GET_RTX_CLASS (code) == '2'
10729 || GET_RTX_CLASS (code) == 'c')
10731 rtx x0 = XEXP (x, 0);
10732 rtx x1 = XEXP (x, 1);
10735 return 1 + 2 * count_rtxs (x0);
10737 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10738 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10739 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10740 return 2 + 2 * count_rtxs (x0)
10741 + count_rtxs (x == XEXP (x1, 0)
10742 ? XEXP (x1, 1) : XEXP (x1, 0));
10744 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10745 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10746 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10747 return 2 + 2 * count_rtxs (x1)
10748 + count_rtxs (x == XEXP (x0, 0)
10749 ? XEXP (x0, 1) : XEXP (x0, 0));
10752 fmt = GET_RTX_FORMAT (code);
10753 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10755 ret += count_rtxs (XEXP (x, i));
10760 /* Utility function for following routine. Called when X is part of a value
10761 being stored into last_set_value. Sets last_set_table_tick
10762 for each register mentioned. Similar to mention_regs in cse.c */
10765 update_table_tick (rtx x)
10767 enum rtx_code code = GET_CODE (x);
10768 const char *fmt = GET_RTX_FORMAT (code);
10773 unsigned int regno = REGNO (x);
10774 unsigned int endregno
10775 = regno + (regno < FIRST_PSEUDO_REGISTER
10776 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10779 for (r = regno; r < endregno; r++)
10780 reg_stat[r].last_set_table_tick = label_tick;
10785 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10786 /* Note that we can't have an "E" in values stored; see
10787 get_last_value_validate. */
10790 /* Check for identical subexpressions. If x contains
10791 identical subexpression we only have to traverse one of
10793 if (i == 0 && ARITHMETIC_P (x))
10795 /* Note that at this point x1 has already been
10797 rtx x0 = XEXP (x, 0);
10798 rtx x1 = XEXP (x, 1);
10800 /* If x0 and x1 are identical then there is no need to
10805 /* If x0 is identical to a subexpression of x1 then while
10806 processing x1, x0 has already been processed. Thus we
10807 are done with x. */
10808 if (ARITHMETIC_P (x1)
10809 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10812 /* If x1 is identical to a subexpression of x0 then we
10813 still have to process the rest of x0. */
10814 if (ARITHMETIC_P (x0)
10815 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10817 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10822 update_table_tick (XEXP (x, i));
10826 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10827 are saying that the register is clobbered and we no longer know its
10828 value. If INSN is zero, don't update reg_stat[].last_set; this is
10829 only permitted with VALUE also zero and is used to invalidate the
10833 record_value_for_reg (rtx reg, rtx insn, rtx value)
10835 unsigned int regno = REGNO (reg);
10836 unsigned int endregno
10837 = regno + (regno < FIRST_PSEUDO_REGISTER
10838 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10841 /* If VALUE contains REG and we have a previous value for REG, substitute
10842 the previous value. */
10843 if (value && insn && reg_overlap_mentioned_p (reg, value))
10847 /* Set things up so get_last_value is allowed to see anything set up to
10849 subst_low_cuid = INSN_CUID (insn);
10850 tem = get_last_value (reg);
10852 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10853 it isn't going to be useful and will take a lot of time to process,
10854 so just use the CLOBBER. */
10858 if (ARITHMETIC_P (tem)
10859 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10860 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10861 tem = XEXP (tem, 0);
10862 else if (count_occurrences (value, reg, 1) >= 2)
10864 /* If there are two or more occurrences of REG in VALUE,
10865 prevent the value from growing too much. */
10866 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10867 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10870 value = replace_rtx (copy_rtx (value), reg, tem);
10874 /* For each register modified, show we don't know its value, that
10875 we don't know about its bitwise content, that its value has been
10876 updated, and that we don't know the location of the death of the
10878 for (i = regno; i < endregno; i++)
10881 reg_stat[i].last_set = insn;
10883 reg_stat[i].last_set_value = 0;
10884 reg_stat[i].last_set_mode = 0;
10885 reg_stat[i].last_set_nonzero_bits = 0;
10886 reg_stat[i].last_set_sign_bit_copies = 0;
10887 reg_stat[i].last_death = 0;
10888 reg_stat[i].truncated_to_mode = 0;
10891 /* Mark registers that are being referenced in this value. */
10893 update_table_tick (value);
10895 /* Now update the status of each register being set.
10896 If someone is using this register in this block, set this register
10897 to invalid since we will get confused between the two lives in this
10898 basic block. This makes using this register always invalid. In cse, we
10899 scan the table to invalidate all entries using this register, but this
10900 is too much work for us. */
10902 for (i = regno; i < endregno; i++)
10904 reg_stat[i].last_set_label = label_tick;
10905 if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10906 reg_stat[i].last_set_invalid = 1;
10908 reg_stat[i].last_set_invalid = 0;
10911 /* The value being assigned might refer to X (like in "x++;"). In that
10912 case, we must replace it with (clobber (const_int 0)) to prevent
10914 if (value && ! get_last_value_validate (&value, insn,
10915 reg_stat[regno].last_set_label, 0))
10917 value = copy_rtx (value);
10918 if (! get_last_value_validate (&value, insn,
10919 reg_stat[regno].last_set_label, 1))
10923 /* For the main register being modified, update the value, the mode, the
10924 nonzero bits, and the number of sign bit copies. */
10926 reg_stat[regno].last_set_value = value;
10930 enum machine_mode mode = GET_MODE (reg);
10931 subst_low_cuid = INSN_CUID (insn);
10932 reg_stat[regno].last_set_mode = mode;
10933 if (GET_MODE_CLASS (mode) == MODE_INT
10934 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10935 mode = nonzero_bits_mode;
10936 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10937 reg_stat[regno].last_set_sign_bit_copies
10938 = num_sign_bit_copies (value, GET_MODE (reg));
10942 /* Called via note_stores from record_dead_and_set_regs to handle one
10943 SET or CLOBBER in an insn. DATA is the instruction in which the
10944 set is occurring. */
10947 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10949 rtx record_dead_insn = (rtx) data;
10951 if (GET_CODE (dest) == SUBREG)
10952 dest = SUBREG_REG (dest);
10954 if (!record_dead_insn)
10957 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10963 /* If we are setting the whole register, we know its value. Otherwise
10964 show that we don't know the value. We can handle SUBREG in
10966 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10967 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10968 else if (GET_CODE (setter) == SET
10969 && GET_CODE (SET_DEST (setter)) == SUBREG
10970 && SUBREG_REG (SET_DEST (setter)) == dest
10971 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10972 && subreg_lowpart_p (SET_DEST (setter)))
10973 record_value_for_reg (dest, record_dead_insn,
10974 gen_lowpart (GET_MODE (dest),
10975 SET_SRC (setter)));
10977 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10979 else if (MEM_P (dest)
10980 /* Ignore pushes, they clobber nothing. */
10981 && ! push_operand (dest, GET_MODE (dest)))
10982 mem_last_set = INSN_CUID (record_dead_insn);
10985 /* Update the records of when each REG was most recently set or killed
10986 for the things done by INSN. This is the last thing done in processing
10987 INSN in the combiner loop.
10989 We update reg_stat[], in particular fields last_set, last_set_value,
10990 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10991 last_death, and also the similar information mem_last_set (which insn
10992 most recently modified memory) and last_call_cuid (which insn was the
10993 most recent subroutine call). */
10996 record_dead_and_set_regs (rtx insn)
11001 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11003 if (REG_NOTE_KIND (link) == REG_DEAD
11004 && REG_P (XEXP (link, 0)))
11006 unsigned int regno = REGNO (XEXP (link, 0));
11007 unsigned int endregno
11008 = regno + (regno < FIRST_PSEUDO_REGISTER
11009 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11012 for (i = regno; i < endregno; i++)
11013 reg_stat[i].last_death = insn;
11015 else if (REG_NOTE_KIND (link) == REG_INC)
11016 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11021 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11022 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11024 reg_stat[i].last_set_value = 0;
11025 reg_stat[i].last_set_mode = 0;
11026 reg_stat[i].last_set_nonzero_bits = 0;
11027 reg_stat[i].last_set_sign_bit_copies = 0;
11028 reg_stat[i].last_death = 0;
11029 reg_stat[i].truncated_to_mode = 0;
11032 last_call_cuid = mem_last_set = INSN_CUID (insn);
11034 /* We can't combine into a call pattern. Remember, though, that
11035 the return value register is set at this CUID. We could
11036 still replace a register with the return value from the
11037 wrong subroutine call! */
11038 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11041 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11044 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11045 register present in the SUBREG, so for each such SUBREG go back and
11046 adjust nonzero and sign bit information of the registers that are
11047 known to have some zero/sign bits set.
11049 This is needed because when combine blows the SUBREGs away, the
11050 information on zero/sign bits is lost and further combines can be
11051 missed because of that. */
11054 record_promoted_value (rtx insn, rtx subreg)
11057 unsigned int regno = REGNO (SUBREG_REG (subreg));
11058 enum machine_mode mode = GET_MODE (subreg);
11060 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11063 for (links = LOG_LINKS (insn); links;)
11065 insn = XEXP (links, 0);
11066 set = single_set (insn);
11068 if (! set || !REG_P (SET_DEST (set))
11069 || REGNO (SET_DEST (set)) != regno
11070 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11072 links = XEXP (links, 1);
11076 if (reg_stat[regno].last_set == insn)
11078 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11079 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11082 if (REG_P (SET_SRC (set)))
11084 regno = REGNO (SET_SRC (set));
11085 links = LOG_LINKS (insn);
11092 /* Check if X, a register, is known to contain a value already
11093 truncated to MODE. In this case we can use a subreg to refer to
11094 the truncated value even though in the generic case we would need
11095 an explicit truncation. */
11098 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11100 enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11102 if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11104 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11106 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11107 GET_MODE_BITSIZE (truncated)))
11112 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11113 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11114 a truncate into a subreg using this information. */
11117 record_truncated_value (rtx x)
11119 enum machine_mode truncated_mode;
11121 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11123 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11124 truncated_mode = GET_MODE (x);
11126 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11129 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11130 GET_MODE_BITSIZE (original_mode)))
11133 x = SUBREG_REG (x);
11135 /* ??? For hard-regs we now record everything. We might be able to
11136 optimize this using last_set_mode. */
11137 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11138 truncated_mode = GET_MODE (x);
11142 if (reg_stat[REGNO (x)].truncated_to_mode == 0
11143 || reg_stat[REGNO (x)].truncation_label < label_tick
11144 || (GET_MODE_SIZE (truncated_mode)
11145 < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11147 reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11148 reg_stat[REGNO (x)].truncation_label = label_tick;
11152 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11153 found, note what it implies to the registers used in it. */
11156 check_conversions (rtx insn, rtx x)
11158 if (GET_CODE (x) == SUBREG || REG_P (x))
11160 if (GET_CODE (x) == SUBREG
11161 && SUBREG_PROMOTED_VAR_P (x)
11162 && REG_P (SUBREG_REG (x)))
11163 record_promoted_value (insn, x);
11165 record_truncated_value (x);
11169 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11172 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11176 check_conversions (insn, XEXP (x, i));
11180 if (XVEC (x, i) != 0)
11181 for (j = 0; j < XVECLEN (x, i); j++)
11182 check_conversions (insn, XVECEXP (x, i, j));
11188 /* Utility routine for the following function. Verify that all the registers
11189 mentioned in *LOC are valid when *LOC was part of a value set when
11190 label_tick == TICK. Return 0 if some are not.
11192 If REPLACE is nonzero, replace the invalid reference with
11193 (clobber (const_int 0)) and return 1. This replacement is useful because
11194 we often can get useful information about the form of a value (e.g., if
11195 it was produced by a shift that always produces -1 or 0) even though
11196 we don't know exactly what registers it was produced from. */
11199 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11202 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11203 int len = GET_RTX_LENGTH (GET_CODE (x));
11208 unsigned int regno = REGNO (x);
11209 unsigned int endregno
11210 = regno + (regno < FIRST_PSEUDO_REGISTER
11211 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11214 for (j = regno; j < endregno; j++)
11215 if (reg_stat[j].last_set_invalid
11216 /* If this is a pseudo-register that was only set once and not
11217 live at the beginning of the function, it is always valid. */
11218 || (! (regno >= FIRST_PSEUDO_REGISTER
11219 && REG_N_SETS (regno) == 1
11220 && (! REGNO_REG_SET_P
11221 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11223 && reg_stat[j].last_set_label > tick))
11226 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11232 /* If this is a memory reference, make sure that there were
11233 no stores after it that might have clobbered the value. We don't
11234 have alias info, so we assume any store invalidates it. */
11235 else if (MEM_P (x) && !MEM_READONLY_P (x)
11236 && INSN_CUID (insn) <= mem_last_set)
11239 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11243 for (i = 0; i < len; i++)
11247 /* Check for identical subexpressions. If x contains
11248 identical subexpression we only have to traverse one of
11250 if (i == 1 && ARITHMETIC_P (x))
11252 /* Note that at this point x0 has already been checked
11253 and found valid. */
11254 rtx x0 = XEXP (x, 0);
11255 rtx x1 = XEXP (x, 1);
11257 /* If x0 and x1 are identical then x is also valid. */
11261 /* If x1 is identical to a subexpression of x0 then
11262 while checking x0, x1 has already been checked. Thus
11263 it is valid and so as x. */
11264 if (ARITHMETIC_P (x0)
11265 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11268 /* If x0 is identical to a subexpression of x1 then x is
11269 valid iff the rest of x1 is valid. */
11270 if (ARITHMETIC_P (x1)
11271 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11273 get_last_value_validate (&XEXP (x1,
11274 x0 == XEXP (x1, 0) ? 1 : 0),
11275 insn, tick, replace);
11278 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11282 /* Don't bother with these. They shouldn't occur anyway. */
11283 else if (fmt[i] == 'E')
11287 /* If we haven't found a reason for it to be invalid, it is valid. */
11291 /* Get the last value assigned to X, if known. Some registers
11292 in the value may be replaced with (clobber (const_int 0)) if their value
11293 is known longer known reliably. */
11296 get_last_value (rtx x)
11298 unsigned int regno;
11301 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11302 then convert it to the desired mode. If this is a paradoxical SUBREG,
11303 we cannot predict what values the "extra" bits might have. */
11304 if (GET_CODE (x) == SUBREG
11305 && subreg_lowpart_p (x)
11306 && (GET_MODE_SIZE (GET_MODE (x))
11307 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11308 && (value = get_last_value (SUBREG_REG (x))) != 0)
11309 return gen_lowpart (GET_MODE (x), value);
11315 value = reg_stat[regno].last_set_value;
11317 /* If we don't have a value, or if it isn't for this basic block and
11318 it's either a hard register, set more than once, or it's a live
11319 at the beginning of the function, return 0.
11321 Because if it's not live at the beginning of the function then the reg
11322 is always set before being used (is never used without being set).
11323 And, if it's set only once, and it's always set before use, then all
11324 uses must have the same last value, even if it's not from this basic
11328 || (reg_stat[regno].last_set_label != label_tick
11329 && (regno < FIRST_PSEUDO_REGISTER
11330 || REG_N_SETS (regno) != 1
11331 || (REGNO_REG_SET_P
11332 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11336 /* If the value was set in a later insn than the ones we are processing,
11337 we can't use it even if the register was only set once. */
11338 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11341 /* If the value has all its registers valid, return it. */
11342 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11343 reg_stat[regno].last_set_label, 0))
11346 /* Otherwise, make a copy and replace any invalid register with
11347 (clobber (const_int 0)). If that fails for some reason, return 0. */
11349 value = copy_rtx (value);
11350 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11351 reg_stat[regno].last_set_label, 1))
11357 /* Return nonzero if expression X refers to a REG or to memory
11358 that is set in an instruction more recent than FROM_CUID. */
11361 use_crosses_set_p (rtx x, int from_cuid)
11365 enum rtx_code code = GET_CODE (x);
11369 unsigned int regno = REGNO (x);
11370 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11371 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11373 #ifdef PUSH_ROUNDING
11374 /* Don't allow uses of the stack pointer to be moved,
11375 because we don't know whether the move crosses a push insn. */
11376 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11379 for (; regno < endreg; regno++)
11380 if (reg_stat[regno].last_set
11381 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11386 if (code == MEM && mem_last_set > from_cuid)
11389 fmt = GET_RTX_FORMAT (code);
11391 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11396 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11397 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11400 else if (fmt[i] == 'e'
11401 && use_crosses_set_p (XEXP (x, i), from_cuid))
11407 /* Define three variables used for communication between the following
11410 static unsigned int reg_dead_regno, reg_dead_endregno;
11411 static int reg_dead_flag;
11413 /* Function called via note_stores from reg_dead_at_p.
11415 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11416 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11419 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11421 unsigned int regno, endregno;
11426 regno = REGNO (dest);
11427 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11428 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11430 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11431 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11434 /* Return nonzero if REG is known to be dead at INSN.
11436 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11437 referencing REG, it is dead. If we hit a SET referencing REG, it is
11438 live. Otherwise, see if it is live or dead at the start of the basic
11439 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11440 must be assumed to be always live. */
11443 reg_dead_at_p (rtx reg, rtx insn)
11448 /* Set variables for reg_dead_at_p_1. */
11449 reg_dead_regno = REGNO (reg);
11450 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11451 ? hard_regno_nregs[reg_dead_regno]
11457 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11458 we allow the machine description to decide whether use-and-clobber
11459 patterns are OK. */
11460 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11462 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11463 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11467 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11468 beginning of function. */
11469 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11470 insn = prev_nonnote_insn (insn))
11472 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11474 return reg_dead_flag == 1 ? 1 : 0;
11476 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11480 /* Get the basic block that we were in. */
11482 block = ENTRY_BLOCK_PTR->next_bb;
11485 FOR_EACH_BB (block)
11486 if (insn == BB_HEAD (block))
11489 if (block == EXIT_BLOCK_PTR)
11493 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11494 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11500 /* Note hard registers in X that are used. This code is similar to
11501 that in flow.c, but much simpler since we don't care about pseudos. */
11504 mark_used_regs_combine (rtx x)
11506 RTX_CODE code = GET_CODE (x);
11507 unsigned int regno;
11520 case ADDR_DIFF_VEC:
11523 /* CC0 must die in the insn after it is set, so we don't need to take
11524 special note of it here. */
11530 /* If we are clobbering a MEM, mark any hard registers inside the
11531 address as used. */
11532 if (MEM_P (XEXP (x, 0)))
11533 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11538 /* A hard reg in a wide mode may really be multiple registers.
11539 If so, mark all of them just like the first. */
11540 if (regno < FIRST_PSEUDO_REGISTER)
11542 unsigned int endregno, r;
11544 /* None of this applies to the stack, frame or arg pointers. */
11545 if (regno == STACK_POINTER_REGNUM
11546 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11547 || regno == HARD_FRAME_POINTER_REGNUM
11549 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11550 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11552 || regno == FRAME_POINTER_REGNUM)
11555 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11556 for (r = regno; r < endregno; r++)
11557 SET_HARD_REG_BIT (newpat_used_regs, r);
11563 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11565 rtx testreg = SET_DEST (x);
11567 while (GET_CODE (testreg) == SUBREG
11568 || GET_CODE (testreg) == ZERO_EXTRACT
11569 || GET_CODE (testreg) == STRICT_LOW_PART)
11570 testreg = XEXP (testreg, 0);
11572 if (MEM_P (testreg))
11573 mark_used_regs_combine (XEXP (testreg, 0));
11575 mark_used_regs_combine (SET_SRC (x));
11583 /* Recursively scan the operands of this expression. */
11586 const char *fmt = GET_RTX_FORMAT (code);
11588 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11591 mark_used_regs_combine (XEXP (x, i));
11592 else if (fmt[i] == 'E')
11596 for (j = 0; j < XVECLEN (x, i); j++)
11597 mark_used_regs_combine (XVECEXP (x, i, j));
11603 /* Remove register number REGNO from the dead registers list of INSN.
11605 Return the note used to record the death, if there was one. */
11608 remove_death (unsigned int regno, rtx insn)
11610 rtx note = find_regno_note (insn, REG_DEAD, regno);
11614 REG_N_DEATHS (regno)--;
11615 remove_note (insn, note);
11621 /* For each register (hardware or pseudo) used within expression X, if its
11622 death is in an instruction with cuid between FROM_CUID (inclusive) and
11623 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11624 list headed by PNOTES.
11626 That said, don't move registers killed by maybe_kill_insn.
11628 This is done when X is being merged by combination into TO_INSN. These
11629 notes will then be distributed as needed. */
11632 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11637 enum rtx_code code = GET_CODE (x);
11641 unsigned int regno = REGNO (x);
11642 rtx where_dead = reg_stat[regno].last_death;
11643 rtx before_dead, after_dead;
11645 /* Don't move the register if it gets killed in between from and to. */
11646 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11647 && ! reg_referenced_p (x, maybe_kill_insn))
11650 /* WHERE_DEAD could be a USE insn made by combine, so first we
11651 make sure that we have insns with valid INSN_CUID values. */
11652 before_dead = where_dead;
11653 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11654 before_dead = PREV_INSN (before_dead);
11656 after_dead = where_dead;
11657 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11658 after_dead = NEXT_INSN (after_dead);
11660 if (before_dead && after_dead
11661 && INSN_CUID (before_dead) >= from_cuid
11662 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11663 || (where_dead != after_dead
11664 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11666 rtx note = remove_death (regno, where_dead);
11668 /* It is possible for the call above to return 0. This can occur
11669 when last_death points to I2 or I1 that we combined with.
11670 In that case make a new note.
11672 We must also check for the case where X is a hard register
11673 and NOTE is a death note for a range of hard registers
11674 including X. In that case, we must put REG_DEAD notes for
11675 the remaining registers in place of NOTE. */
11677 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11678 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11679 > GET_MODE_SIZE (GET_MODE (x))))
11681 unsigned int deadregno = REGNO (XEXP (note, 0));
11682 unsigned int deadend
11683 = (deadregno + hard_regno_nregs[deadregno]
11684 [GET_MODE (XEXP (note, 0))]);
11685 unsigned int ourend
11686 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11689 for (i = deadregno; i < deadend; i++)
11690 if (i < regno || i >= ourend)
11691 REG_NOTES (where_dead)
11692 = gen_rtx_EXPR_LIST (REG_DEAD,
11694 REG_NOTES (where_dead));
11697 /* If we didn't find any note, or if we found a REG_DEAD note that
11698 covers only part of the given reg, and we have a multi-reg hard
11699 register, then to be safe we must check for REG_DEAD notes
11700 for each register other than the first. They could have
11701 their own REG_DEAD notes lying around. */
11702 else if ((note == 0
11704 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11705 < GET_MODE_SIZE (GET_MODE (x)))))
11706 && regno < FIRST_PSEUDO_REGISTER
11707 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11709 unsigned int ourend
11710 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11711 unsigned int i, offset;
11715 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11719 for (i = regno + offset; i < ourend; i++)
11720 move_deaths (regno_reg_rtx[i],
11721 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11724 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11726 XEXP (note, 1) = *pnotes;
11730 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11732 REG_N_DEATHS (regno)++;
11738 else if (GET_CODE (x) == SET)
11740 rtx dest = SET_DEST (x);
11742 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11744 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11745 that accesses one word of a multi-word item, some
11746 piece of everything register in the expression is used by
11747 this insn, so remove any old death. */
11748 /* ??? So why do we test for equality of the sizes? */
11750 if (GET_CODE (dest) == ZERO_EXTRACT
11751 || GET_CODE (dest) == STRICT_LOW_PART
11752 || (GET_CODE (dest) == SUBREG
11753 && (((GET_MODE_SIZE (GET_MODE (dest))
11754 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11755 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11756 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11758 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11762 /* If this is some other SUBREG, we know it replaces the entire
11763 value, so use that as the destination. */
11764 if (GET_CODE (dest) == SUBREG)
11765 dest = SUBREG_REG (dest);
11767 /* If this is a MEM, adjust deaths of anything used in the address.
11768 For a REG (the only other possibility), the entire value is
11769 being replaced so the old value is not used in this insn. */
11772 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11777 else if (GET_CODE (x) == CLOBBER)
11780 len = GET_RTX_LENGTH (code);
11781 fmt = GET_RTX_FORMAT (code);
11783 for (i = 0; i < len; i++)
11788 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11789 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11792 else if (fmt[i] == 'e')
11793 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11797 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11798 pattern of an insn. X must be a REG. */
11801 reg_bitfield_target_p (rtx x, rtx body)
11805 if (GET_CODE (body) == SET)
11807 rtx dest = SET_DEST (body);
11809 unsigned int regno, tregno, endregno, endtregno;
11811 if (GET_CODE (dest) == ZERO_EXTRACT)
11812 target = XEXP (dest, 0);
11813 else if (GET_CODE (dest) == STRICT_LOW_PART)
11814 target = SUBREG_REG (XEXP (dest, 0));
11818 if (GET_CODE (target) == SUBREG)
11819 target = SUBREG_REG (target);
11821 if (!REG_P (target))
11824 tregno = REGNO (target), regno = REGNO (x);
11825 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11826 return target == x;
11828 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11829 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11831 return endregno > tregno && regno < endtregno;
11834 else if (GET_CODE (body) == PARALLEL)
11835 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11836 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11842 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11843 as appropriate. I3 and I2 are the insns resulting from the combination
11844 insns including FROM (I2 may be zero).
11846 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11847 not need REG_DEAD notes because they are being substituted for. This
11848 saves searching in the most common cases.
11850 Each note in the list is either ignored or placed on some insns, depending
11851 on the type of note. */
11854 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11857 rtx note, next_note;
11860 for (note = notes; note; note = next_note)
11862 rtx place = 0, place2 = 0;
11864 next_note = XEXP (note, 1);
11865 switch (REG_NOTE_KIND (note))
11869 /* Doesn't matter much where we put this, as long as it's somewhere.
11870 It is preferable to keep these notes on branches, which is most
11871 likely to be i3. */
11875 case REG_VALUE_PROFILE:
11876 /* Just get rid of this note, as it is unused later anyway. */
11879 case REG_NON_LOCAL_GOTO:
11884 gcc_assert (i2 && JUMP_P (i2));
11889 case REG_EH_REGION:
11890 /* These notes must remain with the call or trapping instruction. */
11893 else if (i2 && CALL_P (i2))
11897 gcc_assert (flag_non_call_exceptions);
11898 if (may_trap_p (i3))
11900 else if (i2 && may_trap_p (i2))
11902 /* ??? Otherwise assume we've combined things such that we
11903 can now prove that the instructions can't trap. Drop the
11904 note in this case. */
11910 /* These notes must remain with the call. It should not be
11911 possible for both I2 and I3 to be a call. */
11916 gcc_assert (i2 && CALL_P (i2));
11922 /* Any clobbers for i3 may still exist, and so we must process
11923 REG_UNUSED notes from that insn.
11925 Any clobbers from i2 or i1 can only exist if they were added by
11926 recog_for_combine. In that case, recog_for_combine created the
11927 necessary REG_UNUSED notes. Trying to keep any original
11928 REG_UNUSED notes from these insns can cause incorrect output
11929 if it is for the same register as the original i3 dest.
11930 In that case, we will notice that the register is set in i3,
11931 and then add a REG_UNUSED note for the destination of i3, which
11932 is wrong. However, it is possible to have REG_UNUSED notes from
11933 i2 or i1 for register which were both used and clobbered, so
11934 we keep notes from i2 or i1 if they will turn into REG_DEAD
11937 /* If this register is set or clobbered in I3, put the note there
11938 unless there is one already. */
11939 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11941 if (from_insn != i3)
11944 if (! (REG_P (XEXP (note, 0))
11945 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11946 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11949 /* Otherwise, if this register is used by I3, then this register
11950 now dies here, so we must put a REG_DEAD note here unless there
11952 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11953 && ! (REG_P (XEXP (note, 0))
11954 ? find_regno_note (i3, REG_DEAD,
11955 REGNO (XEXP (note, 0)))
11956 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11958 PUT_REG_NOTE_KIND (note, REG_DEAD);
11966 /* These notes say something about results of an insn. We can
11967 only support them if they used to be on I3 in which case they
11968 remain on I3. Otherwise they are ignored.
11970 If the note refers to an expression that is not a constant, we
11971 must also ignore the note since we cannot tell whether the
11972 equivalence is still true. It might be possible to do
11973 slightly better than this (we only have a problem if I2DEST
11974 or I1DEST is present in the expression), but it doesn't
11975 seem worth the trouble. */
11977 if (from_insn == i3
11978 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11983 case REG_NO_CONFLICT:
11984 /* These notes say something about how a register is used. They must
11985 be present on any use of the register in I2 or I3. */
11986 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11989 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11999 /* This can show up in several ways -- either directly in the
12000 pattern, or hidden off in the constant pool with (or without?)
12001 a REG_EQUAL note. */
12002 /* ??? Ignore the without-reg_equal-note problem for now. */
12003 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12004 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12005 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12006 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12010 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12011 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12012 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12013 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12021 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12022 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12023 if (place && JUMP_P (place))
12025 rtx label = JUMP_LABEL (place);
12028 JUMP_LABEL (place) = XEXP (note, 0);
12031 gcc_assert (label == XEXP (note, 0));
12032 if (LABEL_P (label))
12033 LABEL_NUSES (label)--;
12037 if (place2 && JUMP_P (place2))
12039 rtx label = JUMP_LABEL (place2);
12042 JUMP_LABEL (place2) = XEXP (note, 0);
12045 gcc_assert (label == XEXP (note, 0));
12046 if (LABEL_P (label))
12047 LABEL_NUSES (label)--;
12054 /* This note says something about the value of a register prior
12055 to the execution of an insn. It is too much trouble to see
12056 if the note is still correct in all situations. It is better
12057 to simply delete it. */
12061 /* If the insn previously containing this note still exists,
12062 put it back where it was. Otherwise move it to the previous
12063 insn. Adjust the corresponding REG_LIBCALL note. */
12064 if (!NOTE_P (from_insn))
12068 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12069 place = prev_real_insn (from_insn);
12071 XEXP (tem, 0) = place;
12072 /* If we're deleting the last remaining instruction of a
12073 libcall sequence, don't add the notes. */
12074 else if (XEXP (note, 0) == from_insn)
12076 /* Don't add the dangling REG_RETVAL note. */
12083 /* This is handled similarly to REG_RETVAL. */
12084 if (!NOTE_P (from_insn))
12088 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12089 place = next_real_insn (from_insn);
12091 XEXP (tem, 0) = place;
12092 /* If we're deleting the last remaining instruction of a
12093 libcall sequence, don't add the notes. */
12094 else if (XEXP (note, 0) == from_insn)
12096 /* Don't add the dangling REG_LIBCALL note. */
12103 /* If we replaced the right hand side of FROM_INSN with a
12104 REG_EQUAL note, the original use of the dying register
12105 will not have been combined into I3 and I2. In such cases,
12106 FROM_INSN is guaranteed to be the first of the combined
12107 instructions, so we simply need to search back before
12108 FROM_INSN for the previous use or set of this register,
12109 then alter the notes there appropriately.
12111 If the register is used as an input in I3, it dies there.
12112 Similarly for I2, if it is nonzero and adjacent to I3.
12114 If the register is not used as an input in either I3 or I2
12115 and it is not one of the registers we were supposed to eliminate,
12116 there are two possibilities. We might have a non-adjacent I2
12117 or we might have somehow eliminated an additional register
12118 from a computation. For example, we might have had A & B where
12119 we discover that B will always be zero. In this case we will
12120 eliminate the reference to A.
12122 In both cases, we must search to see if we can find a previous
12123 use of A and put the death note there. */
12125 if (from_insn && from_insn == replaced_rhs_insn)
12130 && CALL_P (from_insn)
12131 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12133 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12135 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12136 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12138 else if (rtx_equal_p (XEXP (note, 0), elim_i2)
12139 || rtx_equal_p (XEXP (note, 0), elim_i1))
12146 basic_block bb = this_basic_block;
12148 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12150 if (! INSN_P (tem))
12152 if (tem == BB_HEAD (bb))
12157 /* If the register is being set at TEM, see if that is all
12158 TEM is doing. If so, delete TEM. Otherwise, make this
12159 into a REG_UNUSED note instead. Don't delete sets to
12160 global register vars. */
12161 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12162 || !global_regs[REGNO (XEXP (note, 0))])
12163 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12165 rtx set = single_set (tem);
12166 rtx inner_dest = 0;
12168 rtx cc0_setter = NULL_RTX;
12172 for (inner_dest = SET_DEST (set);
12173 (GET_CODE (inner_dest) == STRICT_LOW_PART
12174 || GET_CODE (inner_dest) == SUBREG
12175 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12176 inner_dest = XEXP (inner_dest, 0))
12179 /* Verify that it was the set, and not a clobber that
12180 modified the register.
12182 CC0 targets must be careful to maintain setter/user
12183 pairs. If we cannot delete the setter due to side
12184 effects, mark the user with an UNUSED note instead
12187 if (set != 0 && ! side_effects_p (SET_SRC (set))
12188 && rtx_equal_p (XEXP (note, 0), inner_dest)
12190 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12191 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12192 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12196 /* Move the notes and links of TEM elsewhere.
12197 This might delete other dead insns recursively.
12198 First set the pattern to something that won't use
12200 rtx old_notes = REG_NOTES (tem);
12202 PATTERN (tem) = pc_rtx;
12203 REG_NOTES (tem) = NULL;
12205 distribute_notes (old_notes, tem, tem, NULL_RTX,
12206 NULL_RTX, NULL_RTX);
12207 distribute_links (LOG_LINKS (tem));
12209 SET_INSN_DELETED (tem);
12212 /* Delete the setter too. */
12215 PATTERN (cc0_setter) = pc_rtx;
12216 old_notes = REG_NOTES (cc0_setter);
12217 REG_NOTES (cc0_setter) = NULL;
12219 distribute_notes (old_notes, cc0_setter,
12220 cc0_setter, NULL_RTX,
12221 NULL_RTX, NULL_RTX);
12222 distribute_links (LOG_LINKS (cc0_setter));
12224 SET_INSN_DELETED (cc0_setter);
12230 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12232 /* If there isn't already a REG_UNUSED note, put one
12233 here. Do not place a REG_DEAD note, even if
12234 the register is also used here; that would not
12235 match the algorithm used in lifetime analysis
12236 and can cause the consistency check in the
12237 scheduler to fail. */
12238 if (! find_regno_note (tem, REG_UNUSED,
12239 REGNO (XEXP (note, 0))))
12244 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12246 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12250 /* If we are doing a 3->2 combination, and we have a
12251 register which formerly died in i3 and was not used
12252 by i2, which now no longer dies in i3 and is used in
12253 i2 but does not die in i2, and place is between i2
12254 and i3, then we may need to move a link from place to
12256 if (i2 && INSN_UID (place) <= max_uid_cuid
12257 && INSN_CUID (place) > INSN_CUID (i2)
12259 && INSN_CUID (from_insn) > INSN_CUID (i2)
12260 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12262 rtx links = LOG_LINKS (place);
12263 LOG_LINKS (place) = 0;
12264 distribute_links (links);
12269 if (tem == BB_HEAD (bb))
12273 /* We haven't found an insn for the death note and it
12274 is still a REG_DEAD note, but we have hit the beginning
12275 of the block. If the existing life info says the reg
12276 was dead, there's nothing left to do. Otherwise, we'll
12277 need to do a global life update after combine. */
12278 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12279 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12280 REGNO (XEXP (note, 0))))
12281 SET_BIT (refresh_blocks, this_basic_block->index);
12284 /* If the register is set or already dead at PLACE, we needn't do
12285 anything with this note if it is still a REG_DEAD note.
12286 We check here if it is set at all, not if is it totally replaced,
12287 which is what `dead_or_set_p' checks, so also check for it being
12290 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12292 unsigned int regno = REGNO (XEXP (note, 0));
12294 /* Similarly, if the instruction on which we want to place
12295 the note is a noop, we'll need do a global live update
12296 after we remove them in delete_noop_moves. */
12297 if (noop_move_p (place))
12298 SET_BIT (refresh_blocks, this_basic_block->index);
12300 if (dead_or_set_p (place, XEXP (note, 0))
12301 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12303 /* Unless the register previously died in PLACE, clear
12304 last_death. [I no longer understand why this is
12306 if (reg_stat[regno].last_death != place)
12307 reg_stat[regno].last_death = 0;
12311 reg_stat[regno].last_death = place;
12313 /* If this is a death note for a hard reg that is occupying
12314 multiple registers, ensure that we are still using all
12315 parts of the object. If we find a piece of the object
12316 that is unused, we must arrange for an appropriate REG_DEAD
12317 note to be added for it. However, we can't just emit a USE
12318 and tag the note to it, since the register might actually
12319 be dead; so we recourse, and the recursive call then finds
12320 the previous insn that used this register. */
12322 if (place && regno < FIRST_PSEUDO_REGISTER
12323 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12325 unsigned int endregno
12326 = regno + hard_regno_nregs[regno]
12327 [GET_MODE (XEXP (note, 0))];
12331 for (i = regno; i < endregno; i++)
12332 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12333 && ! find_regno_fusage (place, USE, i))
12334 || dead_or_set_regno_p (place, i))
12339 /* Put only REG_DEAD notes for pieces that are
12340 not already dead or set. */
12342 for (i = regno; i < endregno;
12343 i += hard_regno_nregs[i][reg_raw_mode[i]])
12345 rtx piece = regno_reg_rtx[i];
12346 basic_block bb = this_basic_block;
12348 if (! dead_or_set_p (place, piece)
12349 && ! reg_bitfield_target_p (piece,
12353 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12355 distribute_notes (new_note, place, place,
12356 NULL_RTX, NULL_RTX, NULL_RTX);
12358 else if (! refers_to_regno_p (i, i + 1,
12359 PATTERN (place), 0)
12360 && ! find_regno_fusage (place, USE, i))
12361 for (tem = PREV_INSN (place); ;
12362 tem = PREV_INSN (tem))
12364 if (! INSN_P (tem))
12366 if (tem == BB_HEAD (bb))
12368 SET_BIT (refresh_blocks,
12369 this_basic_block->index);
12374 if (dead_or_set_p (tem, piece)
12375 || reg_bitfield_target_p (piece,
12379 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12394 /* Any other notes should not be present at this point in the
12396 gcc_unreachable ();
12401 XEXP (note, 1) = REG_NOTES (place);
12402 REG_NOTES (place) = note;
12404 else if ((REG_NOTE_KIND (note) == REG_DEAD
12405 || REG_NOTE_KIND (note) == REG_UNUSED)
12406 && REG_P (XEXP (note, 0)))
12407 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12411 if ((REG_NOTE_KIND (note) == REG_DEAD
12412 || REG_NOTE_KIND (note) == REG_UNUSED)
12413 && REG_P (XEXP (note, 0)))
12414 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12416 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12417 REG_NOTE_KIND (note),
12419 REG_NOTES (place2));
12424 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12425 I3, I2, and I1 to new locations. This is also called to add a link
12426 pointing at I3 when I3's destination is changed. */
12429 distribute_links (rtx links)
12431 rtx link, next_link;
12433 for (link = links; link; link = next_link)
12439 next_link = XEXP (link, 1);
12441 /* If the insn that this link points to is a NOTE or isn't a single
12442 set, ignore it. In the latter case, it isn't clear what we
12443 can do other than ignore the link, since we can't tell which
12444 register it was for. Such links wouldn't be used by combine
12447 It is not possible for the destination of the target of the link to
12448 have been changed by combine. The only potential of this is if we
12449 replace I3, I2, and I1 by I3 and I2. But in that case the
12450 destination of I2 also remains unchanged. */
12452 if (NOTE_P (XEXP (link, 0))
12453 || (set = single_set (XEXP (link, 0))) == 0)
12456 reg = SET_DEST (set);
12457 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12458 || GET_CODE (reg) == STRICT_LOW_PART)
12459 reg = XEXP (reg, 0);
12461 /* A LOG_LINK is defined as being placed on the first insn that uses
12462 a register and points to the insn that sets the register. Start
12463 searching at the next insn after the target of the link and stop
12464 when we reach a set of the register or the end of the basic block.
12466 Note that this correctly handles the link that used to point from
12467 I3 to I2. Also note that not much searching is typically done here
12468 since most links don't point very far away. */
12470 for (insn = NEXT_INSN (XEXP (link, 0));
12471 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12472 || BB_HEAD (this_basic_block->next_bb) != insn));
12473 insn = NEXT_INSN (insn))
12474 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12476 if (reg_referenced_p (reg, PATTERN (insn)))
12480 else if (CALL_P (insn)
12481 && find_reg_fusage (insn, USE, reg))
12486 else if (INSN_P (insn) && reg_set_p (reg, insn))
12489 /* If we found a place to put the link, place it there unless there
12490 is already a link to the same insn as LINK at that point. */
12496 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12497 if (XEXP (link2, 0) == XEXP (link, 0))
12502 XEXP (link, 1) = LOG_LINKS (place);
12503 LOG_LINKS (place) = link;
12505 /* Set added_links_insn to the earliest insn we added a
12507 if (added_links_insn == 0
12508 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12509 added_links_insn = place;
12515 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12516 Check whether the expression pointer to by LOC is a register or
12517 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12518 Otherwise return zero. */
12521 unmentioned_reg_p_1 (rtx *loc, void *expr)
12526 && (REG_P (x) || MEM_P (x))
12527 && ! reg_mentioned_p (x, (rtx) expr))
12532 /* Check for any register or memory mentioned in EQUIV that is not
12533 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12534 of EXPR where some registers may have been replaced by constants. */
12537 unmentioned_reg_p (rtx equiv, rtx expr)
12539 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12542 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12545 insn_cuid (rtx insn)
12547 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12548 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12549 insn = NEXT_INSN (insn);
12551 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12553 return INSN_CUID (insn);
12557 dump_combine_stats (FILE *file)
12561 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12562 combine_attempts, combine_merges, combine_extras, combine_successes);
12566 dump_combine_total_stats (FILE *file)
12570 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12571 total_attempts, total_merges, total_extras, total_successes);
12576 gate_handle_combine (void)
12578 return (optimize > 0);
12581 /* Try combining insns through substitution. */
12582 static unsigned int
12583 rest_of_handle_combine (void)
12585 int rebuild_jump_labels_after_combine
12586 = combine_instructions (get_insns (), max_reg_num ());
12588 /* Combining insns may have turned an indirect jump into a
12589 direct jump. Rebuild the JUMP_LABEL fields of jumping
12591 if (rebuild_jump_labels_after_combine)
12593 timevar_push (TV_JUMP);
12594 rebuild_jump_labels (get_insns ());
12595 timevar_pop (TV_JUMP);
12597 delete_dead_jumptables ();
12598 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12603 struct tree_opt_pass pass_combine =
12605 "combine", /* name */
12606 gate_handle_combine, /* gate */
12607 rest_of_handle_combine, /* execute */
12610 0, /* static_pass_number */
12611 TV_COMBINE, /* tv_id */
12612 0, /* properties_required */
12613 0, /* properties_provided */
12614 0, /* properties_destroyed */
12615 0, /* todo_flags_start */
12617 TODO_ggc_collect, /* todo_flags_finish */