1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid;
129 static int max_uid_cuid;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
242 static struct reg_stat *reg_stat;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost;
299 /* Incremented for each label. */
301 static int label_tick;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r; int i;} old_contents;
326 union {rtx *r; int *i;} where;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences;
349 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
351 unsigned HOST_WIDE_INT,
352 unsigned HOST_WIDE_INT *);
353 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx *, rtx);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
361 static int cant_combine_insn_p (rtx);
362 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
363 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
364 static int contains_muldiv (rtx);
365 static rtx try_combine (rtx, rtx, rtx, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx *find_split_point (rtx *, rtx);
369 static rtx subst (rtx, rtx, rtx, int, int);
370 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
371 static rtx simplify_if_then_else (rtx);
372 static rtx simplify_set (rtx);
373 static rtx simplify_logical (rtx);
374 static rtx expand_compound_operation (rtx);
375 static rtx expand_field_assignment (rtx);
376 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
377 rtx, unsigned HOST_WIDE_INT, int, int, int);
378 static rtx extract_left_shift (rtx, int);
379 static rtx make_compound_operation (rtx, enum rtx_code);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
381 unsigned HOST_WIDE_INT *);
382 static rtx force_to_mode (rtx, enum machine_mode,
383 unsigned HOST_WIDE_INT, rtx, int);
384 static rtx if_then_else_cond (rtx, rtx *, rtx *);
385 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
386 static int rtx_equal_for_field_assignment_p (rtx, rtx);
387 static rtx make_field_assignment (rtx);
388 static rtx apply_distributive_law (rtx);
389 static rtx distribute_and_simplify_rtx (rtx, int);
390 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
391 unsigned HOST_WIDE_INT);
392 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
393 HOST_WIDE_INT, enum machine_mode, int *);
394 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
396 static int recog_for_combine (rtx *, rtx, rtx *);
397 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
398 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
399 static void update_table_tick (rtx);
400 static void record_value_for_reg (rtx, rtx, rtx);
401 static void check_promoted_subreg (rtx, rtx);
402 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
403 static void record_dead_and_set_regs (rtx);
404 static int get_last_value_validate (rtx *, rtx, int, int);
405 static rtx get_last_value (rtx);
406 static int use_crosses_set_p (rtx, int);
407 static void reg_dead_at_p_1 (rtx, rtx, void *);
408 static int reg_dead_at_p (rtx, rtx);
409 static void move_deaths (rtx, rtx, int, rtx, rtx *);
410 static int reg_bitfield_target_p (rtx, rtx);
411 static void distribute_notes (rtx, rtx, rtx, rtx);
412 static void distribute_links (rtx);
413 static void mark_used_regs_combine (rtx);
414 static int insn_cuid (rtx);
415 static void record_promoted_value (rtx, rtx);
416 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
417 static enum rtx_code combine_reversed_comparison_code (rtx);
418 static int unmentioned_reg_p_1 (rtx *, void *);
419 static bool unmentioned_reg_p (rtx, rtx);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
428 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
430 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
431 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
433 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (rtx *into, rtx newval)
448 if (oldval == newval)
451 /* We'd like to catch as many invalid transformations here as
452 possible. Unfortunately, there are way too many mode changes
453 that are perfectly valid, so we'd waste too much effort for
454 little gain doing the checks here. Focus on catching invalid
455 transformations involving integer constants. */
456 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
457 && GET_CODE (newval) == CONST_INT)
459 /* Sanity check that we're replacing oldval with a CONST_INT
460 that is a valid sign-extension for the original mode. */
461 gcc_assert (INTVAL (newval)
462 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
464 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
465 CONST_INT is not valid, because after the replacement, the
466 original mode would be gone. Unfortunately, we can't tell
467 when do_SUBST is called to replace the operand thereof, so we
468 perform this test on oldval instead, checking whether an
469 invalid replacement took place before we got here. */
470 gcc_assert (!(GET_CODE (oldval) == SUBREG
471 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
472 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
473 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
477 buf = undobuf.frees, undobuf.frees = buf->next;
479 buf = xmalloc (sizeof (struct undo));
483 buf->old_contents.r = oldval;
486 buf->next = undobuf.undos, undobuf.undos = buf;
489 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
491 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
492 for the value of a HOST_WIDE_INT value (including CONST_INT) is
496 do_SUBST_INT (int *into, int newval)
501 if (oldval == newval)
505 buf = undobuf.frees, undobuf.frees = buf->next;
507 buf = xmalloc (sizeof (struct undo));
511 buf->old_contents.i = oldval;
514 buf->next = undobuf.undos, undobuf.undos = buf;
517 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
519 /* Subroutine of try_combine. Determine whether the combine replacement
520 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
521 that the original instruction sequence I1, I2 and I3. Note that I1
522 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
523 costs of all instructions can be estimated, and the replacements are
524 more expensive than the original sequence. */
527 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
529 int i1_cost, i2_cost, i3_cost;
530 int new_i2_cost, new_i3_cost;
531 int old_cost, new_cost;
533 /* Lookup the original insn_rtx_costs. */
534 i2_cost = INSN_UID (i2) <= last_insn_cost
535 ? uid_insn_cost[INSN_UID (i2)] : 0;
536 i3_cost = INSN_UID (i3) <= last_insn_cost
537 ? uid_insn_cost[INSN_UID (i3)] : 0;
541 i1_cost = INSN_UID (i1) <= last_insn_cost
542 ? uid_insn_cost[INSN_UID (i1)] : 0;
543 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
544 ? i1_cost + i2_cost + i3_cost : 0;
548 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
552 /* Calculate the replacement insn_rtx_costs. */
553 new_i3_cost = insn_rtx_cost (newpat);
556 new_i2_cost = insn_rtx_cost (newi2pat);
557 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
558 ? new_i2_cost + new_i3_cost : 0;
562 new_cost = new_i3_cost;
566 if (undobuf.other_insn)
568 int old_other_cost, new_other_cost;
570 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
571 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
572 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
573 if (old_other_cost > 0 && new_other_cost > 0)
575 old_cost += old_other_cost;
576 new_cost += new_other_cost;
582 /* Disallow this recombination if both new_cost and old_cost are
583 greater than zero, and new_cost is greater than old cost. */
585 && new_cost > old_cost)
592 "rejecting combination of insns %d, %d and %d\n",
593 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
594 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
595 i1_cost, i2_cost, i3_cost, old_cost);
600 "rejecting combination of insns %d and %d\n",
601 INSN_UID (i2), INSN_UID (i3));
602 fprintf (dump_file, "original costs %d + %d = %d\n",
603 i2_cost, i3_cost, old_cost);
608 fprintf (dump_file, "replacement costs %d + %d = %d\n",
609 new_i2_cost, new_i3_cost, new_cost);
612 fprintf (dump_file, "replacement cost %d\n", new_cost);
618 /* Update the uid_insn_cost array with the replacement costs. */
619 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
620 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
622 uid_insn_cost[INSN_UID (i1)] = 0;
627 /* Main entry point for combiner. F is the first insn of the function.
628 NREGS is the first unused pseudo-reg number.
630 Return nonzero if the combiner has turned an indirect jump
631 instruction into a direct jump. */
633 combine_instructions (rtx f, unsigned int nregs)
640 rtx links, nextlinks;
642 int new_direct_jump_p = 0;
644 combine_attempts = 0;
647 combine_successes = 0;
649 combine_max_regno = nregs;
651 rtl_hooks = combine_rtl_hooks;
653 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
655 init_recog_no_volatile ();
657 /* Compute maximum uid value so uid_cuid can be allocated. */
659 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
660 if (INSN_UID (insn) > i)
663 uid_cuid = xmalloc ((i + 1) * sizeof (int));
666 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
668 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
669 problems when, for example, we have j <<= 1 in a loop. */
671 nonzero_sign_valid = 0;
673 /* Compute the mapping from uids to cuids.
674 Cuids are numbers assigned to insns, like uids,
675 except that cuids increase monotonically through the code.
677 Scan all SETs and see if we can deduce anything about what
678 bits are known to be zero for some registers and how many copies
679 of the sign bit are known to exist for those registers.
681 Also set any known values so that we can use it while searching
682 for what bits are known to be set. */
686 setup_incoming_promotions ();
688 refresh_blocks = sbitmap_alloc (last_basic_block);
689 sbitmap_zero (refresh_blocks);
691 /* Allocate array of current insn_rtx_costs. */
692 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
693 last_insn_cost = max_uid_cuid;
695 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
697 uid_cuid[INSN_UID (insn)] = ++i;
703 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
705 record_dead_and_set_regs (insn);
708 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
709 if (REG_NOTE_KIND (links) == REG_INC)
710 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
714 /* Record the current insn_rtx_cost of this instruction. */
715 if (NONJUMP_INSN_P (insn))
716 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
718 fprintf(dump_file, "insn_cost %d: %d\n",
719 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
726 nonzero_sign_valid = 1;
728 /* Now scan all the insns in forward order. */
734 setup_incoming_promotions ();
736 FOR_EACH_BB (this_basic_block)
738 for (insn = BB_HEAD (this_basic_block);
739 insn != NEXT_INSN (BB_END (this_basic_block));
740 insn = next ? next : NEXT_INSN (insn))
747 else if (INSN_P (insn))
749 /* See if we know about function return values before this
750 insn based upon SUBREG flags. */
751 check_promoted_subreg (insn, PATTERN (insn));
753 /* Try this insn with each insn it links back to. */
755 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
756 if ((next = try_combine (insn, XEXP (links, 0),
757 NULL_RTX, &new_direct_jump_p)) != 0)
760 /* Try each sequence of three linked insns ending with this one. */
762 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
764 rtx link = XEXP (links, 0);
766 /* If the linked insn has been replaced by a note, then there
767 is no point in pursuing this chain any further. */
771 for (nextlinks = LOG_LINKS (link);
773 nextlinks = XEXP (nextlinks, 1))
774 if ((next = try_combine (insn, link,
776 &new_direct_jump_p)) != 0)
781 /* Try to combine a jump insn that uses CC0
782 with a preceding insn that sets CC0, and maybe with its
783 logical predecessor as well.
784 This is how we make decrement-and-branch insns.
785 We need this special code because data flow connections
786 via CC0 do not get entered in LOG_LINKS. */
789 && (prev = prev_nonnote_insn (insn)) != 0
790 && NONJUMP_INSN_P (prev)
791 && sets_cc0_p (PATTERN (prev)))
793 if ((next = try_combine (insn, prev,
794 NULL_RTX, &new_direct_jump_p)) != 0)
797 for (nextlinks = LOG_LINKS (prev); nextlinks;
798 nextlinks = XEXP (nextlinks, 1))
799 if ((next = try_combine (insn, prev,
801 &new_direct_jump_p)) != 0)
805 /* Do the same for an insn that explicitly references CC0. */
806 if (NONJUMP_INSN_P (insn)
807 && (prev = prev_nonnote_insn (insn)) != 0
808 && NONJUMP_INSN_P (prev)
809 && sets_cc0_p (PATTERN (prev))
810 && GET_CODE (PATTERN (insn)) == SET
811 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
813 if ((next = try_combine (insn, prev,
814 NULL_RTX, &new_direct_jump_p)) != 0)
817 for (nextlinks = LOG_LINKS (prev); nextlinks;
818 nextlinks = XEXP (nextlinks, 1))
819 if ((next = try_combine (insn, prev,
821 &new_direct_jump_p)) != 0)
825 /* Finally, see if any of the insns that this insn links to
826 explicitly references CC0. If so, try this insn, that insn,
827 and its predecessor if it sets CC0. */
828 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
829 if (NONJUMP_INSN_P (XEXP (links, 0))
830 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
831 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
832 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
833 && NONJUMP_INSN_P (prev)
834 && sets_cc0_p (PATTERN (prev))
835 && (next = try_combine (insn, XEXP (links, 0),
836 prev, &new_direct_jump_p)) != 0)
840 /* Try combining an insn with two different insns whose results it
842 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
843 for (nextlinks = XEXP (links, 1); nextlinks;
844 nextlinks = XEXP (nextlinks, 1))
845 if ((next = try_combine (insn, XEXP (links, 0),
847 &new_direct_jump_p)) != 0)
850 /* Try this insn with each REG_EQUAL note it links back to. */
851 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
854 rtx temp = XEXP (links, 0);
855 if ((set = single_set (temp)) != 0
856 && (note = find_reg_equal_equiv_note (temp)) != 0
857 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
858 /* Avoid using a register that may already been marked
859 dead by an earlier instruction. */
860 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
862 /* Temporarily replace the set's source with the
863 contents of the REG_EQUAL note. The insn will
864 be deleted or recognized by try_combine. */
865 rtx orig = SET_SRC (set);
866 SET_SRC (set) = XEXP (note, 0);
867 next = try_combine (insn, temp, NULL_RTX,
871 SET_SRC (set) = orig;
876 record_dead_and_set_regs (insn);
885 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
886 BASIC_BLOCK (i)->flags |= BB_DIRTY);
887 new_direct_jump_p |= purge_all_dead_edges (0);
888 delete_noop_moves ();
890 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
891 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
892 | PROP_KILL_DEAD_CODE);
895 sbitmap_free (refresh_blocks);
896 free (uid_insn_cost);
901 struct undo *undo, *next;
902 for (undo = undobuf.frees; undo; undo = next)
910 total_attempts += combine_attempts;
911 total_merges += combine_merges;
912 total_extras += combine_extras;
913 total_successes += combine_successes;
915 nonzero_sign_valid = 0;
916 rtl_hooks = general_rtl_hooks;
918 /* Make recognizer allow volatile MEMs again. */
921 return new_direct_jump_p;
924 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
930 for (i = 0; i < combine_max_regno; i++)
931 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
934 /* Set up any promoted values for incoming argument registers. */
937 setup_incoming_promotions (void)
941 enum machine_mode mode;
943 rtx first = get_insns ();
945 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
947 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
948 /* Check whether this register can hold an incoming pointer
949 argument. FUNCTION_ARG_REGNO_P tests outgoing register
950 numbers, so translate if necessary due to register windows. */
951 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
952 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
955 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
958 gen_rtx_CLOBBER (mode, const0_rtx)));
963 /* Called via note_stores. If X is a pseudo that is narrower than
964 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
966 If we are setting only a portion of X and we can't figure out what
967 portion, assume all bits will be used since we don't know what will
970 Similarly, set how many bits of X are known to be copies of the sign bit
971 at all locations in the function. This is the smallest number implied
975 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
976 void *data ATTRIBUTE_UNUSED)
981 && REGNO (x) >= FIRST_PSEUDO_REGISTER
982 /* If this register is undefined at the start of the file, we can't
983 say what its contents were. */
984 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
985 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
987 if (set == 0 || GET_CODE (set) == CLOBBER)
989 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
990 reg_stat[REGNO (x)].sign_bit_copies = 1;
994 /* If this is a complex assignment, see if we can convert it into a
995 simple assignment. */
996 set = expand_field_assignment (set);
998 /* If this is a simple assignment, or we have a paradoxical SUBREG,
999 set what we know about X. */
1001 if (SET_DEST (set) == x
1002 || (GET_CODE (SET_DEST (set)) == SUBREG
1003 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1004 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1005 && SUBREG_REG (SET_DEST (set)) == x))
1007 rtx src = SET_SRC (set);
1009 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1010 /* If X is narrower than a word and SRC is a non-negative
1011 constant that would appear negative in the mode of X,
1012 sign-extend it for use in reg_stat[].nonzero_bits because some
1013 machines (maybe most) will actually do the sign-extension
1014 and this is the conservative approach.
1016 ??? For 2.5, try to tighten up the MD files in this regard
1017 instead of this kludge. */
1019 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1020 && GET_CODE (src) == CONST_INT
1022 && 0 != (INTVAL (src)
1023 & ((HOST_WIDE_INT) 1
1024 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1025 src = GEN_INT (INTVAL (src)
1026 | ((HOST_WIDE_INT) (-1)
1027 << GET_MODE_BITSIZE (GET_MODE (x))));
1030 /* Don't call nonzero_bits if it cannot change anything. */
1031 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1032 reg_stat[REGNO (x)].nonzero_bits
1033 |= nonzero_bits (src, nonzero_bits_mode);
1034 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1035 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1036 || reg_stat[REGNO (x)].sign_bit_copies > num)
1037 reg_stat[REGNO (x)].sign_bit_copies = num;
1041 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1042 reg_stat[REGNO (x)].sign_bit_copies = 1;
1047 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1048 insns that were previously combined into I3 or that will be combined
1049 into the merger of INSN and I3.
1051 Return 0 if the combination is not allowed for any reason.
1053 If the combination is allowed, *PDEST will be set to the single
1054 destination of INSN and *PSRC to the single source, and this function
1058 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1059 rtx *pdest, rtx *psrc)
1062 rtx set = 0, src, dest;
1067 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1068 && next_active_insn (succ) == i3)
1069 : next_active_insn (insn) == i3);
1071 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1072 or a PARALLEL consisting of such a SET and CLOBBERs.
1074 If INSN has CLOBBER parallel parts, ignore them for our processing.
1075 By definition, these happen during the execution of the insn. When it
1076 is merged with another insn, all bets are off. If they are, in fact,
1077 needed and aren't also supplied in I3, they may be added by
1078 recog_for_combine. Otherwise, it won't match.
1080 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1083 Get the source and destination of INSN. If more than one, can't
1086 if (GET_CODE (PATTERN (insn)) == SET)
1087 set = PATTERN (insn);
1088 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1089 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1091 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1093 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1096 switch (GET_CODE (elt))
1098 /* This is important to combine floating point insns
1099 for the SH4 port. */
1101 /* Combining an isolated USE doesn't make sense.
1102 We depend here on combinable_i3pat to reject them. */
1103 /* The code below this loop only verifies that the inputs of
1104 the SET in INSN do not change. We call reg_set_between_p
1105 to verify that the REG in the USE does not change between
1107 If the USE in INSN was for a pseudo register, the matching
1108 insn pattern will likely match any register; combining this
1109 with any other USE would only be safe if we knew that the
1110 used registers have identical values, or if there was
1111 something to tell them apart, e.g. different modes. For
1112 now, we forgo such complicated tests and simply disallow
1113 combining of USES of pseudo registers with any other USE. */
1114 if (REG_P (XEXP (elt, 0))
1115 && GET_CODE (PATTERN (i3)) == PARALLEL)
1117 rtx i3pat = PATTERN (i3);
1118 int i = XVECLEN (i3pat, 0) - 1;
1119 unsigned int regno = REGNO (XEXP (elt, 0));
1123 rtx i3elt = XVECEXP (i3pat, 0, i);
1125 if (GET_CODE (i3elt) == USE
1126 && REG_P (XEXP (i3elt, 0))
1127 && (REGNO (XEXP (i3elt, 0)) == regno
1128 ? reg_set_between_p (XEXP (elt, 0),
1129 PREV_INSN (insn), i3)
1130 : regno >= FIRST_PSEUDO_REGISTER))
1137 /* We can ignore CLOBBERs. */
1142 /* Ignore SETs whose result isn't used but not those that
1143 have side-effects. */
1144 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1145 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1146 || INTVAL (XEXP (note, 0)) <= 0)
1147 && ! side_effects_p (elt))
1150 /* If we have already found a SET, this is a second one and
1151 so we cannot combine with this insn. */
1159 /* Anything else means we can't combine. */
1165 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1166 so don't do anything with it. */
1167 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1176 set = expand_field_assignment (set);
1177 src = SET_SRC (set), dest = SET_DEST (set);
1179 /* Don't eliminate a store in the stack pointer. */
1180 if (dest == stack_pointer_rtx
1181 /* Don't combine with an insn that sets a register to itself if it has
1182 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1183 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1184 /* Can't merge an ASM_OPERANDS. */
1185 || GET_CODE (src) == ASM_OPERANDS
1186 /* Can't merge a function call. */
1187 || GET_CODE (src) == CALL
1188 /* Don't eliminate a function call argument. */
1190 && (find_reg_fusage (i3, USE, dest)
1192 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1193 && global_regs[REGNO (dest)])))
1194 /* Don't substitute into an incremented register. */
1195 || FIND_REG_INC_NOTE (i3, dest)
1196 || (succ && FIND_REG_INC_NOTE (succ, dest))
1197 /* Don't substitute into a non-local goto, this confuses CFG. */
1198 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1200 /* Don't combine the end of a libcall into anything. */
1201 /* ??? This gives worse code, and appears to be unnecessary, since no
1202 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1203 use REG_RETVAL notes for noconflict blocks, but other code here
1204 makes sure that those insns don't disappear. */
1205 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1207 /* Make sure that DEST is not used after SUCC but before I3. */
1208 || (succ && ! all_adjacent
1209 && reg_used_between_p (dest, succ, i3))
1210 /* Make sure that the value that is to be substituted for the register
1211 does not use any registers whose values alter in between. However,
1212 If the insns are adjacent, a use can't cross a set even though we
1213 think it might (this can happen for a sequence of insns each setting
1214 the same destination; last_set of that register might point to
1215 a NOTE). If INSN has a REG_EQUIV note, the register is always
1216 equivalent to the memory so the substitution is valid even if there
1217 are intervening stores. Also, don't move a volatile asm or
1218 UNSPEC_VOLATILE across any other insns. */
1221 || ! find_reg_note (insn, REG_EQUIV, src))
1222 && use_crosses_set_p (src, INSN_CUID (insn)))
1223 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1224 || GET_CODE (src) == UNSPEC_VOLATILE))
1225 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1226 better register allocation by not doing the combine. */
1227 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1228 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1229 /* Don't combine across a CALL_INSN, because that would possibly
1230 change whether the life span of some REGs crosses calls or not,
1231 and it is a pain to update that information.
1232 Exception: if source is a constant, moving it later can't hurt.
1233 Accept that special case, because it helps -fforce-addr a lot. */
1234 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1237 /* DEST must either be a REG or CC0. */
1240 /* If register alignment is being enforced for multi-word items in all
1241 cases except for parameters, it is possible to have a register copy
1242 insn referencing a hard register that is not allowed to contain the
1243 mode being copied and which would not be valid as an operand of most
1244 insns. Eliminate this problem by not combining with such an insn.
1246 Also, on some machines we don't want to extend the life of a hard
1250 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1251 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1252 /* Don't extend the life of a hard register unless it is
1253 user variable (if we have few registers) or it can't
1254 fit into the desired register (meaning something special
1256 Also avoid substituting a return register into I3, because
1257 reload can't handle a conflict with constraints of other
1259 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1260 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1263 else if (GET_CODE (dest) != CC0)
1267 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1268 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1269 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1271 /* Don't substitute for a register intended as a clobberable
1273 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1274 if (rtx_equal_p (reg, dest))
1277 /* If the clobber represents an earlyclobber operand, we must not
1278 substitute an expression containing the clobbered register.
1279 As we do not analyze the constraint strings here, we have to
1280 make the conservative assumption. However, if the register is
1281 a fixed hard reg, the clobber cannot represent any operand;
1282 we leave it up to the machine description to either accept or
1283 reject use-and-clobber patterns. */
1285 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1286 || !fixed_regs[REGNO (reg)])
1287 if (reg_overlap_mentioned_p (reg, src))
1291 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1292 or not), reject, unless nothing volatile comes between it and I3 */
1294 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1296 /* Make sure succ doesn't contain a volatile reference. */
1297 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1300 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1301 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1305 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1306 to be an explicit register variable, and was chosen for a reason. */
1308 if (GET_CODE (src) == ASM_OPERANDS
1309 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1312 /* If there are any volatile insns between INSN and I3, reject, because
1313 they might affect machine state. */
1315 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1316 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1319 /* If INSN or I2 contains an autoincrement or autodecrement,
1320 make sure that register is not used between there and I3,
1321 and not already used in I3 either.
1322 Also insist that I3 not be a jump; if it were one
1323 and the incremented register were spilled, we would lose. */
1326 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1327 if (REG_NOTE_KIND (link) == REG_INC
1329 || reg_used_between_p (XEXP (link, 0), insn, i3)
1330 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1335 /* Don't combine an insn that follows a CC0-setting insn.
1336 An insn that uses CC0 must not be separated from the one that sets it.
1337 We do, however, allow I2 to follow a CC0-setting insn if that insn
1338 is passed as I1; in that case it will be deleted also.
1339 We also allow combining in this case if all the insns are adjacent
1340 because that would leave the two CC0 insns adjacent as well.
1341 It would be more logical to test whether CC0 occurs inside I1 or I2,
1342 but that would be much slower, and this ought to be equivalent. */
1344 p = prev_nonnote_insn (insn);
1345 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1350 /* If we get here, we have passed all the tests and the combination is
1359 /* LOC is the location within I3 that contains its pattern or the component
1360 of a PARALLEL of the pattern. We validate that it is valid for combining.
1362 One problem is if I3 modifies its output, as opposed to replacing it
1363 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1364 so would produce an insn that is not equivalent to the original insns.
1368 (set (reg:DI 101) (reg:DI 100))
1369 (set (subreg:SI (reg:DI 101) 0) <foo>)
1371 This is NOT equivalent to:
1373 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1374 (set (reg:DI 101) (reg:DI 100))])
1376 Not only does this modify 100 (in which case it might still be valid
1377 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1379 We can also run into a problem if I2 sets a register that I1
1380 uses and I1 gets directly substituted into I3 (not via I2). In that
1381 case, we would be getting the wrong value of I2DEST into I3, so we
1382 must reject the combination. This case occurs when I2 and I1 both
1383 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1384 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1385 of a SET must prevent combination from occurring.
1387 Before doing the above check, we first try to expand a field assignment
1388 into a set of logical operations.
1390 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1391 we place a register that is both set and used within I3. If more than one
1392 such register is detected, we fail.
1394 Return 1 if the combination is valid, zero otherwise. */
1397 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1398 int i1_not_in_src, rtx *pi3dest_killed)
1402 if (GET_CODE (x) == SET)
1405 rtx dest = SET_DEST (set);
1406 rtx src = SET_SRC (set);
1407 rtx inner_dest = dest;
1409 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1410 || GET_CODE (inner_dest) == SUBREG
1411 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1412 inner_dest = XEXP (inner_dest, 0);
1414 /* Check for the case where I3 modifies its output, as discussed
1415 above. We don't want to prevent pseudos from being combined
1416 into the address of a MEM, so only prevent the combination if
1417 i1 or i2 set the same MEM. */
1418 if ((inner_dest != dest &&
1419 (!MEM_P (inner_dest)
1420 || rtx_equal_p (i2dest, inner_dest)
1421 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1422 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1423 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1425 /* This is the same test done in can_combine_p except we can't test
1426 all_adjacent; we don't have to, since this instruction will stay
1427 in place, thus we are not considering increasing the lifetime of
1430 Also, if this insn sets a function argument, combining it with
1431 something that might need a spill could clobber a previous
1432 function argument; the all_adjacent test in can_combine_p also
1433 checks this; here, we do a more specific test for this case. */
1435 || (REG_P (inner_dest)
1436 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1437 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1438 GET_MODE (inner_dest))))
1439 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1442 /* If DEST is used in I3, it is being killed in this insn,
1443 so record that for later.
1444 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1445 STACK_POINTER_REGNUM, since these are always considered to be
1446 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1447 if (pi3dest_killed && REG_P (dest)
1448 && reg_referenced_p (dest, PATTERN (i3))
1449 && REGNO (dest) != FRAME_POINTER_REGNUM
1450 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1451 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1453 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1454 && (REGNO (dest) != ARG_POINTER_REGNUM
1455 || ! fixed_regs [REGNO (dest)])
1457 && REGNO (dest) != STACK_POINTER_REGNUM)
1459 if (*pi3dest_killed)
1462 *pi3dest_killed = dest;
1466 else if (GET_CODE (x) == PARALLEL)
1470 for (i = 0; i < XVECLEN (x, 0); i++)
1471 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1472 i1_not_in_src, pi3dest_killed))
1479 /* Return 1 if X is an arithmetic expression that contains a multiplication
1480 and division. We don't count multiplications by powers of two here. */
1483 contains_muldiv (rtx x)
1485 switch (GET_CODE (x))
1487 case MOD: case DIV: case UMOD: case UDIV:
1491 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1492 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1495 return contains_muldiv (XEXP (x, 0))
1496 || contains_muldiv (XEXP (x, 1));
1499 return contains_muldiv (XEXP (x, 0));
1505 /* Determine whether INSN can be used in a combination. Return nonzero if
1506 not. This is used in try_combine to detect early some cases where we
1507 can't perform combinations. */
1510 cant_combine_insn_p (rtx insn)
1515 /* If this isn't really an insn, we can't do anything.
1516 This can occur when flow deletes an insn that it has merged into an
1517 auto-increment address. */
1518 if (! INSN_P (insn))
1521 /* Never combine loads and stores involving hard regs that are likely
1522 to be spilled. The register allocator can usually handle such
1523 reg-reg moves by tying. If we allow the combiner to make
1524 substitutions of likely-spilled regs, we may abort in reload.
1525 As an exception, we allow combinations involving fixed regs; these are
1526 not available to the register allocator so there's no risk involved. */
1528 set = single_set (insn);
1531 src = SET_SRC (set);
1532 dest = SET_DEST (set);
1533 if (GET_CODE (src) == SUBREG)
1534 src = SUBREG_REG (src);
1535 if (GET_CODE (dest) == SUBREG)
1536 dest = SUBREG_REG (dest);
1537 if (REG_P (src) && REG_P (dest)
1538 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1539 && ! fixed_regs[REGNO (src)]
1540 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1541 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1542 && ! fixed_regs[REGNO (dest)]
1543 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1549 /* Adjust INSN after we made a change to its destination.
1551 Changing the destination can invalidate notes that say something about
1552 the results of the insn and a LOG_LINK pointing to the insn. */
1555 adjust_for_new_dest (rtx insn)
1559 /* For notes, be conservative and simply remove them. */
1560 loc = ®_NOTES (insn);
1563 enum reg_note kind = REG_NOTE_KIND (*loc);
1564 if (kind == REG_EQUAL || kind == REG_EQUIV)
1565 *loc = XEXP (*loc, 1);
1567 loc = &XEXP (*loc, 1);
1570 /* The new insn will have a destination that was previously the destination
1571 of an insn just above it. Call distribute_links to make a LOG_LINK from
1572 the next use of that destination. */
1573 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1576 /* Try to combine the insns I1 and I2 into I3.
1577 Here I1 and I2 appear earlier than I3.
1578 I1 can be zero; then we combine just I2 into I3.
1580 If we are combining three insns and the resulting insn is not recognized,
1581 try splitting it into two insns. If that happens, I2 and I3 are retained
1582 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1585 Return 0 if the combination does not work. Then nothing is changed.
1586 If we did the combination, return the insn at which combine should
1589 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1590 new direct jump instruction. */
1593 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1595 /* New patterns for I3 and I2, respectively. */
1596 rtx newpat, newi2pat = 0;
1597 rtvec newpat_vec_with_clobbers = 0;
1598 int substed_i2 = 0, substed_i1 = 0;
1599 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1600 int added_sets_1, added_sets_2;
1601 /* Total number of SETs to put into I3. */
1603 /* Nonzero if I2's body now appears in I3. */
1605 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1606 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1607 /* Contains I3 if the destination of I3 is used in its source, which means
1608 that the old life of I3 is being killed. If that usage is placed into
1609 I2 and not in I3, a REG_DEAD note must be made. */
1610 rtx i3dest_killed = 0;
1611 /* SET_DEST and SET_SRC of I2 and I1. */
1612 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1613 /* PATTERN (I2), or a copy of it in certain cases. */
1615 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1616 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1617 int i1_feeds_i3 = 0;
1618 /* Notes that must be added to REG_NOTES in I3 and I2. */
1619 rtx new_i3_notes, new_i2_notes;
1620 /* Notes that we substituted I3 into I2 instead of the normal case. */
1621 int i3_subst_into_i2 = 0;
1622 /* Notes that I1, I2 or I3 is a MULT operation. */
1631 /* Exit early if one of the insns involved can't be used for
1633 if (cant_combine_insn_p (i3)
1634 || cant_combine_insn_p (i2)
1635 || (i1 && cant_combine_insn_p (i1))
1636 /* We also can't do anything if I3 has a
1637 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1640 /* ??? This gives worse code, and appears to be unnecessary, since no
1641 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1642 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1648 undobuf.other_insn = 0;
1650 /* Reset the hard register usage information. */
1651 CLEAR_HARD_REG_SET (newpat_used_regs);
1653 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1654 code below, set I1 to be the earlier of the two insns. */
1655 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1656 temp = i1, i1 = i2, i2 = temp;
1658 added_links_insn = 0;
1660 /* First check for one important special-case that the code below will
1661 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1662 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1663 we may be able to replace that destination with the destination of I3.
1664 This occurs in the common code where we compute both a quotient and
1665 remainder into a structure, in which case we want to do the computation
1666 directly into the structure to avoid register-register copies.
1668 Note that this case handles both multiple sets in I2 and also
1669 cases where I2 has a number of CLOBBER or PARALLELs.
1671 We make very conservative checks below and only try to handle the
1672 most common cases of this. For example, we only handle the case
1673 where I2 and I3 are adjacent to avoid making difficult register
1676 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1677 && REG_P (SET_SRC (PATTERN (i3)))
1678 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1679 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1680 && GET_CODE (PATTERN (i2)) == PARALLEL
1681 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1682 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1683 below would need to check what is inside (and reg_overlap_mentioned_p
1684 doesn't support those codes anyway). Don't allow those destinations;
1685 the resulting insn isn't likely to be recognized anyway. */
1686 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1687 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1688 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1689 SET_DEST (PATTERN (i3)))
1690 && next_real_insn (i2) == i3)
1692 rtx p2 = PATTERN (i2);
1694 /* Make sure that the destination of I3,
1695 which we are going to substitute into one output of I2,
1696 is not used within another output of I2. We must avoid making this:
1697 (parallel [(set (mem (reg 69)) ...)
1698 (set (reg 69) ...)])
1699 which is not well-defined as to order of actions.
1700 (Besides, reload can't handle output reloads for this.)
1702 The problem can also happen if the dest of I3 is a memory ref,
1703 if another dest in I2 is an indirect memory ref. */
1704 for (i = 0; i < XVECLEN (p2, 0); i++)
1705 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1706 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1707 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1708 SET_DEST (XVECEXP (p2, 0, i))))
1711 if (i == XVECLEN (p2, 0))
1712 for (i = 0; i < XVECLEN (p2, 0); i++)
1713 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1714 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1715 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1720 subst_low_cuid = INSN_CUID (i2);
1722 added_sets_2 = added_sets_1 = 0;
1723 i2dest = SET_SRC (PATTERN (i3));
1725 /* Replace the dest in I2 with our dest and make the resulting
1726 insn the new pattern for I3. Then skip to where we
1727 validate the pattern. Everything was set up above. */
1728 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1729 SET_DEST (PATTERN (i3)));
1732 i3_subst_into_i2 = 1;
1733 goto validate_replacement;
1737 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1738 one of those words to another constant, merge them by making a new
1741 && (temp = single_set (i2)) != 0
1742 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1743 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1744 && REG_P (SET_DEST (temp))
1745 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1746 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1747 && GET_CODE (PATTERN (i3)) == SET
1748 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1749 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1750 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1751 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1752 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1754 HOST_WIDE_INT lo, hi;
1756 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1757 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1760 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1761 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1764 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1766 /* We don't handle the case of the target word being wider
1767 than a host wide int. */
1768 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1770 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1771 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1772 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1774 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1775 hi = INTVAL (SET_SRC (PATTERN (i3)));
1776 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1778 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1779 >> (HOST_BITS_PER_WIDE_INT - 1));
1781 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1782 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1783 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1784 (INTVAL (SET_SRC (PATTERN (i3)))));
1786 hi = lo < 0 ? -1 : 0;
1789 /* We don't handle the case of the higher word not fitting
1790 entirely in either hi or lo. */
1795 subst_low_cuid = INSN_CUID (i2);
1796 added_sets_2 = added_sets_1 = 0;
1797 i2dest = SET_DEST (temp);
1799 SUBST (SET_SRC (temp),
1800 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1802 newpat = PATTERN (i2);
1803 goto validate_replacement;
1807 /* If we have no I1 and I2 looks like:
1808 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1810 make up a dummy I1 that is
1813 (set (reg:CC X) (compare:CC Y (const_int 0)))
1815 (We can ignore any trailing CLOBBERs.)
1817 This undoes a previous combination and allows us to match a branch-and-
1820 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1821 && XVECLEN (PATTERN (i2), 0) >= 2
1822 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1823 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1825 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1826 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1827 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1828 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1829 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1830 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1832 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1833 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1838 /* We make I1 with the same INSN_UID as I2. This gives it
1839 the same INSN_CUID for value tracking. Our fake I1 will
1840 never appear in the insn stream so giving it the same INSN_UID
1841 as I2 will not cause a problem. */
1843 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1844 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1845 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1848 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1849 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1850 SET_DEST (PATTERN (i1)));
1855 /* Verify that I2 and I1 are valid for combining. */
1856 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1857 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1863 /* Record whether I2DEST is used in I2SRC and similarly for the other
1864 cases. Knowing this will help in register status updating below. */
1865 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1866 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1867 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1869 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1871 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1873 /* Ensure that I3's pattern can be the destination of combines. */
1874 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1875 i1 && i2dest_in_i1src && i1_feeds_i3,
1882 /* See if any of the insns is a MULT operation. Unless one is, we will
1883 reject a combination that is, since it must be slower. Be conservative
1885 if (GET_CODE (i2src) == MULT
1886 || (i1 != 0 && GET_CODE (i1src) == MULT)
1887 || (GET_CODE (PATTERN (i3)) == SET
1888 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1891 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1892 We used to do this EXCEPT in one case: I3 has a post-inc in an
1893 output operand. However, that exception can give rise to insns like
1895 which is a famous insn on the PDP-11 where the value of r3 used as the
1896 source was model-dependent. Avoid this sort of thing. */
1899 if (!(GET_CODE (PATTERN (i3)) == SET
1900 && REG_P (SET_SRC (PATTERN (i3)))
1901 && MEM_P (SET_DEST (PATTERN (i3)))
1902 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1903 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1904 /* It's not the exception. */
1907 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1908 if (REG_NOTE_KIND (link) == REG_INC
1909 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1911 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1918 /* See if the SETs in I1 or I2 need to be kept around in the merged
1919 instruction: whenever the value set there is still needed past I3.
1920 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1922 For the SET in I1, we have two cases: If I1 and I2 independently
1923 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1924 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1925 in I1 needs to be kept around unless I1DEST dies or is set in either
1926 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1927 I1DEST. If so, we know I1 feeds into I2. */
1929 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1932 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1933 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1935 /* If the set in I2 needs to be kept around, we must make a copy of
1936 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1937 PATTERN (I2), we are only substituting for the original I1DEST, not into
1938 an already-substituted copy. This also prevents making self-referential
1939 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1942 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1943 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1947 i2pat = copy_rtx (i2pat);
1951 /* Substitute in the latest insn for the regs set by the earlier ones. */
1953 maxreg = max_reg_num ();
1957 /* It is possible that the source of I2 or I1 may be performing an
1958 unneeded operation, such as a ZERO_EXTEND of something that is known
1959 to have the high part zero. Handle that case by letting subst look at
1960 the innermost one of them.
1962 Another way to do this would be to have a function that tries to
1963 simplify a single insn instead of merging two or more insns. We don't
1964 do this because of the potential of infinite loops and because
1965 of the potential extra memory required. However, doing it the way
1966 we are is a bit of a kludge and doesn't catch all cases.
1968 But only do this if -fexpensive-optimizations since it slows things down
1969 and doesn't usually win. */
1971 if (flag_expensive_optimizations)
1973 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1976 subst_low_cuid = INSN_CUID (i1);
1977 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1981 subst_low_cuid = INSN_CUID (i2);
1982 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1987 /* Many machines that don't use CC0 have insns that can both perform an
1988 arithmetic operation and set the condition code. These operations will
1989 be represented as a PARALLEL with the first element of the vector
1990 being a COMPARE of an arithmetic operation with the constant zero.
1991 The second element of the vector will set some pseudo to the result
1992 of the same arithmetic operation. If we simplify the COMPARE, we won't
1993 match such a pattern and so will generate an extra insn. Here we test
1994 for this case, where both the comparison and the operation result are
1995 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1996 I2SRC. Later we will make the PARALLEL that contains I2. */
1998 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1999 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2000 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2001 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2003 #ifdef SELECT_CC_MODE
2005 enum machine_mode compare_mode;
2008 newpat = PATTERN (i3);
2009 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2013 #ifdef SELECT_CC_MODE
2014 /* See if a COMPARE with the operand we substituted in should be done
2015 with the mode that is currently being used. If not, do the same
2016 processing we do in `subst' for a SET; namely, if the destination
2017 is used only once, try to replace it with a register of the proper
2018 mode and also replace the COMPARE. */
2019 if (undobuf.other_insn == 0
2020 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2021 &undobuf.other_insn))
2022 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2024 != GET_MODE (SET_DEST (newpat))))
2026 unsigned int regno = REGNO (SET_DEST (newpat));
2027 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2029 if (regno < FIRST_PSEUDO_REGISTER
2030 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2031 && ! REG_USERVAR_P (SET_DEST (newpat))))
2033 if (regno >= FIRST_PSEUDO_REGISTER)
2034 SUBST (regno_reg_rtx[regno], new_dest);
2036 SUBST (SET_DEST (newpat), new_dest);
2037 SUBST (XEXP (*cc_use, 0), new_dest);
2038 SUBST (SET_SRC (newpat),
2039 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2042 undobuf.other_insn = 0;
2049 n_occurrences = 0; /* `subst' counts here */
2051 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2052 need to make a unique copy of I2SRC each time we substitute it
2053 to avoid self-referential rtl. */
2055 subst_low_cuid = INSN_CUID (i2);
2056 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2057 ! i1_feeds_i3 && i1dest_in_i1src);
2060 /* Record whether i2's body now appears within i3's body. */
2061 i2_is_used = n_occurrences;
2064 /* If we already got a failure, don't try to do more. Otherwise,
2065 try to substitute in I1 if we have it. */
2067 if (i1 && GET_CODE (newpat) != CLOBBER)
2069 /* Before we can do this substitution, we must redo the test done
2070 above (see detailed comments there) that ensures that I1DEST
2071 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2073 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2081 subst_low_cuid = INSN_CUID (i1);
2082 newpat = subst (newpat, i1dest, i1src, 0, 0);
2086 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2087 to count all the ways that I2SRC and I1SRC can be used. */
2088 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2089 && i2_is_used + added_sets_2 > 1)
2090 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2091 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2093 /* Fail if we tried to make a new register (we used to abort, but there's
2094 really no reason to). */
2095 || max_reg_num () != maxreg
2096 /* Fail if we couldn't do something and have a CLOBBER. */
2097 || GET_CODE (newpat) == CLOBBER
2098 /* Fail if this new pattern is a MULT and we didn't have one before
2099 at the outer level. */
2100 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2107 /* If the actions of the earlier insns must be kept
2108 in addition to substituting them into the latest one,
2109 we must make a new PARALLEL for the latest insn
2110 to hold additional the SETs. */
2112 if (added_sets_1 || added_sets_2)
2116 if (GET_CODE (newpat) == PARALLEL)
2118 rtvec old = XVEC (newpat, 0);
2119 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2120 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2121 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2122 sizeof (old->elem[0]) * old->num_elem);
2127 total_sets = 1 + added_sets_1 + added_sets_2;
2128 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2129 XVECEXP (newpat, 0, 0) = old;
2133 XVECEXP (newpat, 0, --total_sets)
2134 = (GET_CODE (PATTERN (i1)) == PARALLEL
2135 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2139 /* If there is no I1, use I2's body as is. We used to also not do
2140 the subst call below if I2 was substituted into I3,
2141 but that could lose a simplification. */
2143 XVECEXP (newpat, 0, --total_sets) = i2pat;
2145 /* See comment where i2pat is assigned. */
2146 XVECEXP (newpat, 0, --total_sets)
2147 = subst (i2pat, i1dest, i1src, 0, 0);
2151 /* We come here when we are replacing a destination in I2 with the
2152 destination of I3. */
2153 validate_replacement:
2155 /* Note which hard regs this insn has as inputs. */
2156 mark_used_regs_combine (newpat);
2158 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2159 consider splitting this pattern, we might need these clobbers. */
2160 if (i1 && GET_CODE (newpat) == PARALLEL
2161 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2163 int len = XVECLEN (newpat, 0);
2165 newpat_vec_with_clobbers = rtvec_alloc (len);
2166 for (i = 0; i < len; i++)
2167 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2170 /* Is the result of combination a valid instruction? */
2171 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2173 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2174 the second SET's destination is a register that is unused and isn't
2175 marked as an instruction that might trap in an EH region. In that case,
2176 we just need the first SET. This can occur when simplifying a divmod
2177 insn. We *must* test for this case here because the code below that
2178 splits two independent SETs doesn't handle this case correctly when it
2179 updates the register status.
2181 It's pointless doing this if we originally had two sets, one from
2182 i3, and one from i2. Combining then splitting the parallel results
2183 in the original i2 again plus an invalid insn (which we delete).
2184 The net effect is only to move instructions around, which makes
2185 debug info less accurate.
2187 Also check the case where the first SET's destination is unused.
2188 That would not cause incorrect code, but does cause an unneeded
2191 if (insn_code_number < 0
2192 && !(added_sets_2 && i1 == 0)
2193 && GET_CODE (newpat) == PARALLEL
2194 && XVECLEN (newpat, 0) == 2
2195 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2196 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2197 && asm_noperands (newpat) < 0)
2199 rtx set0 = XVECEXP (newpat, 0, 0);
2200 rtx set1 = XVECEXP (newpat, 0, 1);
2203 if (((REG_P (SET_DEST (set1))
2204 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2205 || (GET_CODE (SET_DEST (set1)) == SUBREG
2206 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2207 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2208 || INTVAL (XEXP (note, 0)) <= 0)
2209 && ! side_effects_p (SET_SRC (set1)))
2212 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2215 else if (((REG_P (SET_DEST (set0))
2216 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2217 || (GET_CODE (SET_DEST (set0)) == SUBREG
2218 && find_reg_note (i3, REG_UNUSED,
2219 SUBREG_REG (SET_DEST (set0)))))
2220 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2221 || INTVAL (XEXP (note, 0)) <= 0)
2222 && ! side_effects_p (SET_SRC (set0)))
2225 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2227 if (insn_code_number >= 0)
2229 /* If we will be able to accept this, we have made a
2230 change to the destination of I3. This requires us to
2231 do a few adjustments. */
2233 PATTERN (i3) = newpat;
2234 adjust_for_new_dest (i3);
2239 /* If we were combining three insns and the result is a simple SET
2240 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2241 insns. There are two ways to do this. It can be split using a
2242 machine-specific method (like when you have an addition of a large
2243 constant) or by combine in the function find_split_point. */
2245 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2246 && asm_noperands (newpat) < 0)
2248 rtx m_split, *split;
2249 rtx ni2dest = i2dest;
2251 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2252 use I2DEST as a scratch register will help. In the latter case,
2253 convert I2DEST to the mode of the source of NEWPAT if we can. */
2255 m_split = split_insns (newpat, i3);
2257 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2258 inputs of NEWPAT. */
2260 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2261 possible to try that as a scratch reg. This would require adding
2262 more code to make it work though. */
2264 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2266 /* If I2DEST is a hard register or the only use of a pseudo,
2267 we can change its mode. */
2268 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2269 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2271 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2272 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2273 && ! REG_USERVAR_P (i2dest))))
2274 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2277 m_split = split_insns (gen_rtx_PARALLEL
2279 gen_rtvec (2, newpat,
2280 gen_rtx_CLOBBER (VOIDmode,
2283 /* If the split with the mode-changed register didn't work, try
2284 the original register. */
2285 if (! m_split && ni2dest != i2dest)
2288 m_split = split_insns (gen_rtx_PARALLEL
2290 gen_rtvec (2, newpat,
2291 gen_rtx_CLOBBER (VOIDmode,
2297 /* If recog_for_combine has discarded clobbers, try to use them
2298 again for the split. */
2299 if (m_split == 0 && newpat_vec_with_clobbers)
2301 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2302 newpat_vec_with_clobbers), i3);
2304 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2306 m_split = PATTERN (m_split);
2307 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2308 if (insn_code_number >= 0)
2311 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2312 && (next_real_insn (i2) == i3
2313 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2316 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2317 newi2pat = PATTERN (m_split);
2319 i3set = single_set (NEXT_INSN (m_split));
2320 i2set = single_set (m_split);
2322 /* In case we changed the mode of I2DEST, replace it in the
2323 pseudo-register table here. We can't do it above in case this
2324 code doesn't get executed and we do a split the other way. */
2326 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2327 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2329 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2331 /* If I2 or I3 has multiple SETs, we won't know how to track
2332 register status, so don't use these insns. If I2's destination
2333 is used between I2 and I3, we also can't use these insns. */
2335 if (i2_code_number >= 0 && i2set && i3set
2336 && (next_real_insn (i2) == i3
2337 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2338 insn_code_number = recog_for_combine (&newi3pat, i3,
2340 if (insn_code_number >= 0)
2343 /* It is possible that both insns now set the destination of I3.
2344 If so, we must show an extra use of it. */
2346 if (insn_code_number >= 0)
2348 rtx new_i3_dest = SET_DEST (i3set);
2349 rtx new_i2_dest = SET_DEST (i2set);
2351 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2352 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2353 || GET_CODE (new_i3_dest) == SUBREG)
2354 new_i3_dest = XEXP (new_i3_dest, 0);
2356 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2357 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2358 || GET_CODE (new_i2_dest) == SUBREG)
2359 new_i2_dest = XEXP (new_i2_dest, 0);
2361 if (REG_P (new_i3_dest)
2362 && REG_P (new_i2_dest)
2363 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2364 REG_N_SETS (REGNO (new_i2_dest))++;
2368 /* If we can split it and use I2DEST, go ahead and see if that
2369 helps things be recognized. Verify that none of the registers
2370 are set between I2 and I3. */
2371 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2375 /* We need I2DEST in the proper mode. If it is a hard register
2376 or the only use of a pseudo, we can change its mode. */
2377 && (GET_MODE (*split) == GET_MODE (i2dest)
2378 || GET_MODE (*split) == VOIDmode
2379 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2380 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2381 && ! REG_USERVAR_P (i2dest)))
2382 && (next_real_insn (i2) == i3
2383 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2384 /* We can't overwrite I2DEST if its value is still used by
2386 && ! reg_referenced_p (i2dest, newpat))
2388 rtx newdest = i2dest;
2389 enum rtx_code split_code = GET_CODE (*split);
2390 enum machine_mode split_mode = GET_MODE (*split);
2392 /* Get NEWDEST as a register in the proper mode. We have already
2393 validated that we can do this. */
2394 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2396 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2398 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2399 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2402 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2403 an ASHIFT. This can occur if it was inside a PLUS and hence
2404 appeared to be a memory address. This is a kludge. */
2405 if (split_code == MULT
2406 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2407 && INTVAL (XEXP (*split, 1)) > 0
2408 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2410 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2411 XEXP (*split, 0), GEN_INT (i)));
2412 /* Update split_code because we may not have a multiply
2414 split_code = GET_CODE (*split);
2417 #ifdef INSN_SCHEDULING
2418 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2419 be written as a ZERO_EXTEND. */
2420 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2422 #ifdef LOAD_EXTEND_OP
2423 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2424 what it really is. */
2425 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2427 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2428 SUBREG_REG (*split)));
2431 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2432 SUBREG_REG (*split)));
2436 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2437 SUBST (*split, newdest);
2438 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2440 /* recog_for_combine might have added CLOBBERs to newi2pat.
2441 Make sure NEWPAT does not depend on the clobbered regs. */
2442 if (GET_CODE (newi2pat) == PARALLEL)
2443 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2444 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2446 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2447 if (reg_overlap_mentioned_p (reg, newpat))
2454 /* If the split point was a MULT and we didn't have one before,
2455 don't use one now. */
2456 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2457 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2461 /* Check for a case where we loaded from memory in a narrow mode and
2462 then sign extended it, but we need both registers. In that case,
2463 we have a PARALLEL with both loads from the same memory location.
2464 We can split this into a load from memory followed by a register-register
2465 copy. This saves at least one insn, more if register allocation can
2468 We cannot do this if the destination of the first assignment is a
2469 condition code register or cc0. We eliminate this case by making sure
2470 the SET_DEST and SET_SRC have the same mode.
2472 We cannot do this if the destination of the second assignment is
2473 a register that we have already assumed is zero-extended. Similarly
2474 for a SUBREG of such a register. */
2476 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2477 && GET_CODE (newpat) == PARALLEL
2478 && XVECLEN (newpat, 0) == 2
2479 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2480 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2481 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2482 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2483 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2484 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2485 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2486 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2488 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2489 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2490 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2492 && reg_stat[REGNO (temp)].nonzero_bits != 0
2493 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2494 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2495 && (reg_stat[REGNO (temp)].nonzero_bits
2496 != GET_MODE_MASK (word_mode))))
2497 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2498 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2500 && reg_stat[REGNO (temp)].nonzero_bits != 0
2501 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2502 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2503 && (reg_stat[REGNO (temp)].nonzero_bits
2504 != GET_MODE_MASK (word_mode)))))
2505 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2506 SET_SRC (XVECEXP (newpat, 0, 1)))
2507 && ! find_reg_note (i3, REG_UNUSED,
2508 SET_DEST (XVECEXP (newpat, 0, 0))))
2512 newi2pat = XVECEXP (newpat, 0, 0);
2513 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2514 newpat = XVECEXP (newpat, 0, 1);
2515 SUBST (SET_SRC (newpat),
2516 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2517 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2519 if (i2_code_number >= 0)
2520 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2522 if (insn_code_number >= 0)
2526 /* Similarly, check for a case where we have a PARALLEL of two independent
2527 SETs but we started with three insns. In this case, we can do the sets
2528 as two separate insns. This case occurs when some SET allows two
2529 other insns to combine, but the destination of that SET is still live. */
2531 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2532 && GET_CODE (newpat) == PARALLEL
2533 && XVECLEN (newpat, 0) == 2
2534 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2535 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2536 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2537 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2538 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2539 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2540 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2542 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2543 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2544 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2545 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2546 XVECEXP (newpat, 0, 0))
2547 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2548 XVECEXP (newpat, 0, 1))
2549 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2550 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2552 /* Normally, it doesn't matter which of the two is done first,
2553 but it does if one references cc0. In that case, it has to
2556 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2558 newi2pat = XVECEXP (newpat, 0, 0);
2559 newpat = XVECEXP (newpat, 0, 1);
2564 newi2pat = XVECEXP (newpat, 0, 1);
2565 newpat = XVECEXP (newpat, 0, 0);
2568 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2570 if (i2_code_number >= 0)
2571 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2574 /* If it still isn't recognized, fail and change things back the way they
2576 if ((insn_code_number < 0
2577 /* Is the result a reasonable ASM_OPERANDS? */
2578 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2584 /* If we had to change another insn, make sure it is valid also. */
2585 if (undobuf.other_insn)
2587 rtx other_pat = PATTERN (undobuf.other_insn);
2588 rtx new_other_notes;
2591 CLEAR_HARD_REG_SET (newpat_used_regs);
2593 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2596 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2602 PATTERN (undobuf.other_insn) = other_pat;
2604 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2605 are still valid. Then add any non-duplicate notes added by
2606 recog_for_combine. */
2607 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2609 next = XEXP (note, 1);
2611 if (REG_NOTE_KIND (note) == REG_UNUSED
2612 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2614 if (REG_P (XEXP (note, 0)))
2615 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2617 remove_note (undobuf.other_insn, note);
2621 for (note = new_other_notes; note; note = XEXP (note, 1))
2622 if (REG_P (XEXP (note, 0)))
2623 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2625 distribute_notes (new_other_notes, undobuf.other_insn,
2626 undobuf.other_insn, NULL_RTX);
2629 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2630 they are adjacent to each other or not. */
2632 rtx p = prev_nonnote_insn (i3);
2633 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2634 && sets_cc0_p (newi2pat))
2642 /* Only allow this combination if insn_rtx_costs reports that the
2643 replacement instructions are cheaper than the originals. */
2644 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2650 /* We now know that we can do this combination. Merge the insns and
2651 update the status of registers and LOG_LINKS. */
2659 /* I3 now uses what used to be its destination and which is now
2660 I2's destination. This requires us to do a few adjustments. */
2661 PATTERN (i3) = newpat;
2662 adjust_for_new_dest (i3);
2664 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2667 However, some later insn might be using I2's dest and have
2668 a LOG_LINK pointing at I3. We must remove this link.
2669 The simplest way to remove the link is to point it at I1,
2670 which we know will be a NOTE. */
2672 /* newi2pat is usually a SET here; however, recog_for_combine might
2673 have added some clobbers. */
2674 if (GET_CODE (newi2pat) == PARALLEL)
2675 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2677 ni2dest = SET_DEST (newi2pat);
2679 for (insn = NEXT_INSN (i3);
2680 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2681 || insn != BB_HEAD (this_basic_block->next_bb));
2682 insn = NEXT_INSN (insn))
2684 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2686 for (link = LOG_LINKS (insn); link;
2687 link = XEXP (link, 1))
2688 if (XEXP (link, 0) == i3)
2689 XEXP (link, 0) = i1;
2697 rtx i3notes, i2notes, i1notes = 0;
2698 rtx i3links, i2links, i1links = 0;
2702 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2704 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2705 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2707 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2709 /* Ensure that we do not have something that should not be shared but
2710 occurs multiple times in the new insns. Check this by first
2711 resetting all the `used' flags and then copying anything is shared. */
2713 reset_used_flags (i3notes);
2714 reset_used_flags (i2notes);
2715 reset_used_flags (i1notes);
2716 reset_used_flags (newpat);
2717 reset_used_flags (newi2pat);
2718 if (undobuf.other_insn)
2719 reset_used_flags (PATTERN (undobuf.other_insn));
2721 i3notes = copy_rtx_if_shared (i3notes);
2722 i2notes = copy_rtx_if_shared (i2notes);
2723 i1notes = copy_rtx_if_shared (i1notes);
2724 newpat = copy_rtx_if_shared (newpat);
2725 newi2pat = copy_rtx_if_shared (newi2pat);
2726 if (undobuf.other_insn)
2727 reset_used_flags (PATTERN (undobuf.other_insn));
2729 INSN_CODE (i3) = insn_code_number;
2730 PATTERN (i3) = newpat;
2732 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2734 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2736 reset_used_flags (call_usage);
2737 call_usage = copy_rtx (call_usage);
2740 replace_rtx (call_usage, i2dest, i2src);
2743 replace_rtx (call_usage, i1dest, i1src);
2745 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2748 if (undobuf.other_insn)
2749 INSN_CODE (undobuf.other_insn) = other_code_number;
2751 /* We had one special case above where I2 had more than one set and
2752 we replaced a destination of one of those sets with the destination
2753 of I3. In that case, we have to update LOG_LINKS of insns later
2754 in this basic block. Note that this (expensive) case is rare.
2756 Also, in this case, we must pretend that all REG_NOTEs for I2
2757 actually came from I3, so that REG_UNUSED notes from I2 will be
2758 properly handled. */
2760 if (i3_subst_into_i2)
2762 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2763 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2764 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2765 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2766 && ! find_reg_note (i2, REG_UNUSED,
2767 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2768 for (temp = NEXT_INSN (i2);
2769 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2770 || BB_HEAD (this_basic_block) != temp);
2771 temp = NEXT_INSN (temp))
2772 if (temp != i3 && INSN_P (temp))
2773 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2774 if (XEXP (link, 0) == i2)
2775 XEXP (link, 0) = i3;
2780 while (XEXP (link, 1))
2781 link = XEXP (link, 1);
2782 XEXP (link, 1) = i2notes;
2796 INSN_CODE (i2) = i2_code_number;
2797 PATTERN (i2) = newi2pat;
2800 SET_INSN_DELETED (i2);
2806 SET_INSN_DELETED (i1);
2809 /* Get death notes for everything that is now used in either I3 or
2810 I2 and used to die in a previous insn. If we built two new
2811 patterns, move from I1 to I2 then I2 to I3 so that we get the
2812 proper movement on registers that I2 modifies. */
2816 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2817 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2820 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2823 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2825 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2827 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2829 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2831 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2833 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2834 know these are REG_UNUSED and want them to go to the desired insn,
2835 so we always pass it as i3. We have not counted the notes in
2836 reg_n_deaths yet, so we need to do so now. */
2838 if (newi2pat && new_i2_notes)
2840 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2841 if (REG_P (XEXP (temp, 0)))
2842 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2844 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2849 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2850 if (REG_P (XEXP (temp, 0)))
2851 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2853 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2856 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2857 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2858 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2859 in that case, it might delete I2. Similarly for I2 and I1.
2860 Show an additional death due to the REG_DEAD note we make here. If
2861 we discard it in distribute_notes, we will decrement it again. */
2865 if (REG_P (i3dest_killed))
2866 REG_N_DEATHS (REGNO (i3dest_killed))++;
2868 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2869 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2871 NULL_RTX, i2, NULL_RTX);
2873 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2875 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2878 if (i2dest_in_i2src)
2881 REG_N_DEATHS (REGNO (i2dest))++;
2883 if (newi2pat && reg_set_p (i2dest, newi2pat))
2884 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2885 NULL_RTX, i2, NULL_RTX);
2887 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2888 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2891 if (i1dest_in_i1src)
2894 REG_N_DEATHS (REGNO (i1dest))++;
2896 if (newi2pat && reg_set_p (i1dest, newi2pat))
2897 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2898 NULL_RTX, i2, NULL_RTX);
2900 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2901 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2904 distribute_links (i3links);
2905 distribute_links (i2links);
2906 distribute_links (i1links);
2911 rtx i2_insn = 0, i2_val = 0, set;
2913 /* The insn that used to set this register doesn't exist, and
2914 this life of the register may not exist either. See if one of
2915 I3's links points to an insn that sets I2DEST. If it does,
2916 that is now the last known value for I2DEST. If we don't update
2917 this and I2 set the register to a value that depended on its old
2918 contents, we will get confused. If this insn is used, thing
2919 will be set correctly in combine_instructions. */
2921 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2922 if ((set = single_set (XEXP (link, 0))) != 0
2923 && rtx_equal_p (i2dest, SET_DEST (set)))
2924 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2926 record_value_for_reg (i2dest, i2_insn, i2_val);
2928 /* If the reg formerly set in I2 died only once and that was in I3,
2929 zero its use count so it won't make `reload' do any work. */
2931 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2932 && ! i2dest_in_i2src)
2934 regno = REGNO (i2dest);
2935 REG_N_SETS (regno)--;
2939 if (i1 && REG_P (i1dest))
2942 rtx i1_insn = 0, i1_val = 0, set;
2944 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2945 if ((set = single_set (XEXP (link, 0))) != 0
2946 && rtx_equal_p (i1dest, SET_DEST (set)))
2947 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2949 record_value_for_reg (i1dest, i1_insn, i1_val);
2951 regno = REGNO (i1dest);
2952 if (! added_sets_1 && ! i1dest_in_i1src)
2953 REG_N_SETS (regno)--;
2956 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2957 been made to this insn. The order of
2958 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2959 can affect nonzero_bits of newpat */
2961 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2962 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2964 /* Set new_direct_jump_p if a new return or simple jump instruction
2967 If I3 is now an unconditional jump, ensure that it has a
2968 BARRIER following it since it may have initially been a
2969 conditional jump. It may also be the last nonnote insn. */
2971 if (returnjump_p (i3) || any_uncondjump_p (i3))
2973 *new_direct_jump_p = 1;
2974 mark_jump_label (PATTERN (i3), i3, 0);
2976 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2977 || !BARRIER_P (temp))
2978 emit_barrier_after (i3);
2981 if (undobuf.other_insn != NULL_RTX
2982 && (returnjump_p (undobuf.other_insn)
2983 || any_uncondjump_p (undobuf.other_insn)))
2985 *new_direct_jump_p = 1;
2987 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2988 || !BARRIER_P (temp))
2989 emit_barrier_after (undobuf.other_insn);
2992 /* An NOOP jump does not need barrier, but it does need cleaning up
2994 if (GET_CODE (newpat) == SET
2995 && SET_SRC (newpat) == pc_rtx
2996 && SET_DEST (newpat) == pc_rtx)
2997 *new_direct_jump_p = 1;
3000 combine_successes++;
3003 if (added_links_insn
3004 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3005 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3006 return added_links_insn;
3008 return newi2pat ? i2 : i3;
3011 /* Undo all the modifications recorded in undobuf. */
3016 struct undo *undo, *next;
3018 for (undo = undobuf.undos; undo; undo = next)
3022 *undo->where.i = undo->old_contents.i;
3024 *undo->where.r = undo->old_contents.r;
3026 undo->next = undobuf.frees;
3027 undobuf.frees = undo;
3033 /* We've committed to accepting the changes we made. Move all
3034 of the undos to the free list. */
3039 struct undo *undo, *next;
3041 for (undo = undobuf.undos; undo; undo = next)
3044 undo->next = undobuf.frees;
3045 undobuf.frees = undo;
3051 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3052 where we have an arithmetic expression and return that point. LOC will
3055 try_combine will call this function to see if an insn can be split into
3059 find_split_point (rtx *loc, rtx insn)
3062 enum rtx_code code = GET_CODE (x);
3064 unsigned HOST_WIDE_INT len = 0;
3065 HOST_WIDE_INT pos = 0;
3067 rtx inner = NULL_RTX;
3069 /* First special-case some codes. */
3073 #ifdef INSN_SCHEDULING
3074 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3076 if (MEM_P (SUBREG_REG (x)))
3079 return find_split_point (&SUBREG_REG (x), insn);
3083 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3084 using LO_SUM and HIGH. */
3085 if (GET_CODE (XEXP (x, 0)) == CONST
3086 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3089 gen_rtx_LO_SUM (Pmode,
3090 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3092 return &XEXP (XEXP (x, 0), 0);
3096 /* If we have a PLUS whose second operand is a constant and the
3097 address is not valid, perhaps will can split it up using
3098 the machine-specific way to split large constants. We use
3099 the first pseudo-reg (one of the virtual regs) as a placeholder;
3100 it will not remain in the result. */
3101 if (GET_CODE (XEXP (x, 0)) == PLUS
3102 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3103 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3105 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3106 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3109 /* This should have produced two insns, each of which sets our
3110 placeholder. If the source of the second is a valid address,
3111 we can make put both sources together and make a split point
3115 && NEXT_INSN (seq) != NULL_RTX
3116 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3117 && NONJUMP_INSN_P (seq)
3118 && GET_CODE (PATTERN (seq)) == SET
3119 && SET_DEST (PATTERN (seq)) == reg
3120 && ! reg_mentioned_p (reg,
3121 SET_SRC (PATTERN (seq)))
3122 && NONJUMP_INSN_P (NEXT_INSN (seq))
3123 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3124 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3125 && memory_address_p (GET_MODE (x),
3126 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3128 rtx src1 = SET_SRC (PATTERN (seq));
3129 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3131 /* Replace the placeholder in SRC2 with SRC1. If we can
3132 find where in SRC2 it was placed, that can become our
3133 split point and we can replace this address with SRC2.
3134 Just try two obvious places. */
3136 src2 = replace_rtx (src2, reg, src1);
3138 if (XEXP (src2, 0) == src1)
3139 split = &XEXP (src2, 0);
3140 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3141 && XEXP (XEXP (src2, 0), 0) == src1)
3142 split = &XEXP (XEXP (src2, 0), 0);
3146 SUBST (XEXP (x, 0), src2);
3151 /* If that didn't work, perhaps the first operand is complex and
3152 needs to be computed separately, so make a split point there.
3153 This will occur on machines that just support REG + CONST
3154 and have a constant moved through some previous computation. */
3156 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3157 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3158 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3159 return &XEXP (XEXP (x, 0), 0);
3165 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3166 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3167 we need to put the operand into a register. So split at that
3170 if (SET_DEST (x) == cc0_rtx
3171 && GET_CODE (SET_SRC (x)) != COMPARE
3172 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3173 && !OBJECT_P (SET_SRC (x))
3174 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3175 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3176 return &SET_SRC (x);
3179 /* See if we can split SET_SRC as it stands. */
3180 split = find_split_point (&SET_SRC (x), insn);
3181 if (split && split != &SET_SRC (x))
3184 /* See if we can split SET_DEST as it stands. */
3185 split = find_split_point (&SET_DEST (x), insn);
3186 if (split && split != &SET_DEST (x))
3189 /* See if this is a bitfield assignment with everything constant. If
3190 so, this is an IOR of an AND, so split it into that. */
3191 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3192 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3193 <= HOST_BITS_PER_WIDE_INT)
3194 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3195 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3196 && GET_CODE (SET_SRC (x)) == CONST_INT
3197 && ((INTVAL (XEXP (SET_DEST (x), 1))
3198 + INTVAL (XEXP (SET_DEST (x), 2)))
3199 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3200 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3202 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3203 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3204 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3205 rtx dest = XEXP (SET_DEST (x), 0);
3206 enum machine_mode mode = GET_MODE (dest);
3207 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3209 if (BITS_BIG_ENDIAN)
3210 pos = GET_MODE_BITSIZE (mode) - len - pos;
3214 simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3217 rtx negmask = gen_int_mode (~(mask << pos), mode);
3219 simplify_gen_binary (IOR, mode,
3220 simplify_gen_binary (AND, mode,
3222 GEN_INT (src << pos)));
3225 SUBST (SET_DEST (x), dest);
3227 split = find_split_point (&SET_SRC (x), insn);
3228 if (split && split != &SET_SRC (x))
3232 /* Otherwise, see if this is an operation that we can split into two.
3233 If so, try to split that. */
3234 code = GET_CODE (SET_SRC (x));
3239 /* If we are AND'ing with a large constant that is only a single
3240 bit and the result is only being used in a context where we
3241 need to know if it is zero or nonzero, replace it with a bit
3242 extraction. This will avoid the large constant, which might
3243 have taken more than one insn to make. If the constant were
3244 not a valid argument to the AND but took only one insn to make,
3245 this is no worse, but if it took more than one insn, it will
3248 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3249 && REG_P (XEXP (SET_SRC (x), 0))
3250 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3251 && REG_P (SET_DEST (x))
3252 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3253 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3254 && XEXP (*split, 0) == SET_DEST (x)
3255 && XEXP (*split, 1) == const0_rtx)
3257 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3258 XEXP (SET_SRC (x), 0),
3259 pos, NULL_RTX, 1, 1, 0, 0);
3260 if (extraction != 0)
3262 SUBST (SET_SRC (x), extraction);
3263 return find_split_point (loc, insn);
3269 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3270 is known to be on, this can be converted into a NEG of a shift. */
3271 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3272 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3273 && 1 <= (pos = exact_log2
3274 (nonzero_bits (XEXP (SET_SRC (x), 0),
3275 GET_MODE (XEXP (SET_SRC (x), 0))))))
3277 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3281 gen_rtx_LSHIFTRT (mode,
3282 XEXP (SET_SRC (x), 0),
3285 split = find_split_point (&SET_SRC (x), insn);
3286 if (split && split != &SET_SRC (x))
3292 inner = XEXP (SET_SRC (x), 0);
3294 /* We can't optimize if either mode is a partial integer
3295 mode as we don't know how many bits are significant
3297 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3298 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3302 len = GET_MODE_BITSIZE (GET_MODE (inner));
3308 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3309 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3311 inner = XEXP (SET_SRC (x), 0);
3312 len = INTVAL (XEXP (SET_SRC (x), 1));
3313 pos = INTVAL (XEXP (SET_SRC (x), 2));
3315 if (BITS_BIG_ENDIAN)
3316 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3317 unsignedp = (code == ZERO_EXTRACT);
3325 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3327 enum machine_mode mode = GET_MODE (SET_SRC (x));
3329 /* For unsigned, we have a choice of a shift followed by an
3330 AND or two shifts. Use two shifts for field sizes where the
3331 constant might be too large. We assume here that we can
3332 always at least get 8-bit constants in an AND insn, which is
3333 true for every current RISC. */
3335 if (unsignedp && len <= 8)
3340 (mode, gen_lowpart (mode, inner),
3342 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3344 split = find_split_point (&SET_SRC (x), insn);
3345 if (split && split != &SET_SRC (x))
3352 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3353 gen_rtx_ASHIFT (mode,
3354 gen_lowpart (mode, inner),
3355 GEN_INT (GET_MODE_BITSIZE (mode)
3357 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3359 split = find_split_point (&SET_SRC (x), insn);
3360 if (split && split != &SET_SRC (x))
3365 /* See if this is a simple operation with a constant as the second
3366 operand. It might be that this constant is out of range and hence
3367 could be used as a split point. */
3368 if (BINARY_P (SET_SRC (x))
3369 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3370 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3371 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3372 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3373 return &XEXP (SET_SRC (x), 1);
3375 /* Finally, see if this is a simple operation with its first operand
3376 not in a register. The operation might require this operand in a
3377 register, so return it as a split point. We can always do this
3378 because if the first operand were another operation, we would have
3379 already found it as a split point. */
3380 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3381 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3382 return &XEXP (SET_SRC (x), 0);
3388 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3389 it is better to write this as (not (ior A B)) so we can split it.
3390 Similarly for IOR. */
3391 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3394 gen_rtx_NOT (GET_MODE (x),
3395 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3397 XEXP (XEXP (x, 0), 0),
3398 XEXP (XEXP (x, 1), 0))));
3399 return find_split_point (loc, insn);
3402 /* Many RISC machines have a large set of logical insns. If the
3403 second operand is a NOT, put it first so we will try to split the
3404 other operand first. */
3405 if (GET_CODE (XEXP (x, 1)) == NOT)
3407 rtx tem = XEXP (x, 0);
3408 SUBST (XEXP (x, 0), XEXP (x, 1));
3409 SUBST (XEXP (x, 1), tem);
3417 /* Otherwise, select our actions depending on our rtx class. */
3418 switch (GET_RTX_CLASS (code))
3420 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3422 split = find_split_point (&XEXP (x, 2), insn);
3425 /* ... fall through ... */
3427 case RTX_COMM_ARITH:
3429 case RTX_COMM_COMPARE:
3430 split = find_split_point (&XEXP (x, 1), insn);
3433 /* ... fall through ... */
3435 /* Some machines have (and (shift ...) ...) insns. If X is not
3436 an AND, but XEXP (X, 0) is, use it as our split point. */
3437 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3438 return &XEXP (x, 0);
3440 split = find_split_point (&XEXP (x, 0), insn);
3446 /* Otherwise, we don't have a split point. */
3451 /* Throughout X, replace FROM with TO, and return the result.
3452 The result is TO if X is FROM;
3453 otherwise the result is X, but its contents may have been modified.
3454 If they were modified, a record was made in undobuf so that
3455 undo_all will (among other things) return X to its original state.
3457 If the number of changes necessary is too much to record to undo,
3458 the excess changes are not made, so the result is invalid.
3459 The changes already made can still be undone.
3460 undobuf.num_undo is incremented for such changes, so by testing that
3461 the caller can tell whether the result is valid.
3463 `n_occurrences' is incremented each time FROM is replaced.
3465 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3467 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3468 by copying if `n_occurrences' is nonzero. */
3471 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3473 enum rtx_code code = GET_CODE (x);
3474 enum machine_mode op0_mode = VOIDmode;
3479 /* Two expressions are equal if they are identical copies of a shared
3480 RTX or if they are both registers with the same register number
3483 #define COMBINE_RTX_EQUAL_P(X,Y) \
3485 || (REG_P (X) && REG_P (Y) \
3486 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3488 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3491 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3494 /* If X and FROM are the same register but different modes, they will
3495 not have been seen as equal above. However, flow.c will make a
3496 LOG_LINKS entry for that case. If we do nothing, we will try to
3497 rerecognize our original insn and, when it succeeds, we will
3498 delete the feeding insn, which is incorrect.
3500 So force this insn not to match in this (rare) case. */
3501 if (! in_dest && code == REG && REG_P (from)
3502 && REGNO (x) == REGNO (from))
3503 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3505 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3506 of which may contain things that can be combined. */
3507 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3510 /* It is possible to have a subexpression appear twice in the insn.
3511 Suppose that FROM is a register that appears within TO.
3512 Then, after that subexpression has been scanned once by `subst',
3513 the second time it is scanned, TO may be found. If we were
3514 to scan TO here, we would find FROM within it and create a
3515 self-referent rtl structure which is completely wrong. */
3516 if (COMBINE_RTX_EQUAL_P (x, to))
3519 /* Parallel asm_operands need special attention because all of the
3520 inputs are shared across the arms. Furthermore, unsharing the
3521 rtl results in recognition failures. Failure to handle this case
3522 specially can result in circular rtl.
3524 Solve this by doing a normal pass across the first entry of the
3525 parallel, and only processing the SET_DESTs of the subsequent
3528 if (code == PARALLEL
3529 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3530 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3532 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3534 /* If this substitution failed, this whole thing fails. */
3535 if (GET_CODE (new) == CLOBBER
3536 && XEXP (new, 0) == const0_rtx)
3539 SUBST (XVECEXP (x, 0, 0), new);
3541 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3543 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3546 && GET_CODE (dest) != CC0
3547 && GET_CODE (dest) != PC)
3549 new = subst (dest, from, to, 0, unique_copy);
3551 /* If this substitution failed, this whole thing fails. */
3552 if (GET_CODE (new) == CLOBBER
3553 && XEXP (new, 0) == const0_rtx)
3556 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3562 len = GET_RTX_LENGTH (code);
3563 fmt = GET_RTX_FORMAT (code);
3565 /* We don't need to process a SET_DEST that is a register, CC0,
3566 or PC, so set up to skip this common case. All other cases
3567 where we want to suppress replacing something inside a
3568 SET_SRC are handled via the IN_DEST operand. */
3570 && (REG_P (SET_DEST (x))
3571 || GET_CODE (SET_DEST (x)) == CC0
3572 || GET_CODE (SET_DEST (x)) == PC))
3575 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3578 op0_mode = GET_MODE (XEXP (x, 0));
3580 for (i = 0; i < len; i++)
3585 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3587 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3589 new = (unique_copy && n_occurrences
3590 ? copy_rtx (to) : to);
3595 new = subst (XVECEXP (x, i, j), from, to, 0,
3598 /* If this substitution failed, this whole thing
3600 if (GET_CODE (new) == CLOBBER
3601 && XEXP (new, 0) == const0_rtx)
3605 SUBST (XVECEXP (x, i, j), new);
3608 else if (fmt[i] == 'e')
3610 /* If this is a register being set, ignore it. */
3614 && (((code == SUBREG || code == ZERO_EXTRACT)
3616 || code == STRICT_LOW_PART))
3619 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3621 /* In general, don't install a subreg involving two
3622 modes not tieable. It can worsen register
3623 allocation, and can even make invalid reload
3624 insns, since the reg inside may need to be copied
3625 from in the outside mode, and that may be invalid
3626 if it is an fp reg copied in integer mode.
3628 We allow two exceptions to this: It is valid if
3629 it is inside another SUBREG and the mode of that
3630 SUBREG and the mode of the inside of TO is
3631 tieable and it is valid if X is a SET that copies
3634 if (GET_CODE (to) == SUBREG
3635 && ! MODES_TIEABLE_P (GET_MODE (to),
3636 GET_MODE (SUBREG_REG (to)))
3637 && ! (code == SUBREG
3638 && MODES_TIEABLE_P (GET_MODE (x),
3639 GET_MODE (SUBREG_REG (to))))
3641 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3644 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3646 #ifdef CANNOT_CHANGE_MODE_CLASS
3649 && REGNO (to) < FIRST_PSEUDO_REGISTER
3650 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3653 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3656 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3660 /* If we are in a SET_DEST, suppress most cases unless we
3661 have gone inside a MEM, in which case we want to
3662 simplify the address. We assume here that things that
3663 are actually part of the destination have their inner
3664 parts in the first expression. This is true for SUBREG,
3665 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3666 things aside from REG and MEM that should appear in a
3668 new = subst (XEXP (x, i), from, to,
3670 && (code == SUBREG || code == STRICT_LOW_PART
3671 || code == ZERO_EXTRACT))
3673 && i == 0), unique_copy);
3675 /* If we found that we will have to reject this combination,
3676 indicate that by returning the CLOBBER ourselves, rather than
3677 an expression containing it. This will speed things up as
3678 well as prevent accidents where two CLOBBERs are considered
3679 to be equal, thus producing an incorrect simplification. */
3681 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3684 if (GET_CODE (x) == SUBREG
3685 && (GET_CODE (new) == CONST_INT
3686 || GET_CODE (new) == CONST_DOUBLE))
3688 enum machine_mode mode = GET_MODE (x);
3690 x = simplify_subreg (GET_MODE (x), new,
3691 GET_MODE (SUBREG_REG (x)),
3694 x = gen_rtx_CLOBBER (mode, const0_rtx);
3696 else if (GET_CODE (new) == CONST_INT
3697 && GET_CODE (x) == ZERO_EXTEND)
3699 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3700 new, GET_MODE (XEXP (x, 0)));
3704 SUBST (XEXP (x, i), new);
3709 /* Try to simplify X. If the simplification changed the code, it is likely
3710 that further simplification will help, so loop, but limit the number
3711 of repetitions that will be performed. */
3713 for (i = 0; i < 4; i++)
3715 /* If X is sufficiently simple, don't bother trying to do anything
3717 if (code != CONST_INT && code != REG && code != CLOBBER)
3718 x = combine_simplify_rtx (x, op0_mode, in_dest);
3720 if (GET_CODE (x) == code)
3723 code = GET_CODE (x);
3725 /* We no longer know the original mode of operand 0 since we
3726 have changed the form of X) */
3727 op0_mode = VOIDmode;
3733 /* Simplify X, a piece of RTL. We just operate on the expression at the
3734 outer level; call `subst' to simplify recursively. Return the new
3737 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3738 if we are inside a SET_DEST. */
3741 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3743 enum rtx_code code = GET_CODE (x);
3744 enum machine_mode mode = GET_MODE (x);
3749 /* If this is a commutative operation, put a constant last and a complex
3750 expression first. We don't need to do this for comparisons here. */
3751 if (COMMUTATIVE_ARITH_P (x)
3752 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3755 SUBST (XEXP (x, 0), XEXP (x, 1));
3756 SUBST (XEXP (x, 1), temp);
3759 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3760 sign extension of a PLUS with a constant, reverse the order of the sign
3761 extension and the addition. Note that this not the same as the original
3762 code, but overflow is undefined for signed values. Also note that the
3763 PLUS will have been partially moved "inside" the sign-extension, so that
3764 the first operand of X will really look like:
3765 (ashiftrt (plus (ashift A C4) C5) C4).
3767 (plus (ashiftrt (ashift A C4) C2) C4)
3768 and replace the first operand of X with that expression. Later parts
3769 of this function may simplify the expression further.
3771 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3772 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3773 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3775 We do this to simplify address expressions. */
3777 if ((code == PLUS || code == MINUS || code == MULT)
3778 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3779 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3780 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3781 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3782 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3783 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3784 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3785 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3786 XEXP (XEXP (XEXP (x, 0), 0), 1),
3787 XEXP (XEXP (x, 0), 1))) != 0)
3790 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3791 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3792 INTVAL (XEXP (XEXP (x, 0), 1)));
3794 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3795 INTVAL (XEXP (XEXP (x, 0), 1)));
3797 SUBST (XEXP (x, 0), simplify_gen_binary (PLUS, mode, new, temp));
3800 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3801 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3802 things. Check for cases where both arms are testing the same
3805 Don't do anything if all operands are very simple. */
3808 && ((!OBJECT_P (XEXP (x, 0))
3809 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3810 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3811 || (!OBJECT_P (XEXP (x, 1))
3812 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3813 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3815 && (!OBJECT_P (XEXP (x, 0))
3816 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3817 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3819 rtx cond, true_rtx, false_rtx;
3821 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3823 /* If everything is a comparison, what we have is highly unlikely
3824 to be simpler, so don't use it. */
3825 && ! (COMPARISON_P (x)
3826 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3828 rtx cop1 = const0_rtx;
3829 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3831 if (cond_code == NE && COMPARISON_P (cond))
3834 /* Simplify the alternative arms; this may collapse the true and
3835 false arms to store-flag values. Be careful to use copy_rtx
3836 here since true_rtx or false_rtx might share RTL with x as a
3837 result of the if_then_else_cond call above. */
3838 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3839 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3841 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3842 is unlikely to be simpler. */
3843 if (general_operand (true_rtx, VOIDmode)
3844 && general_operand (false_rtx, VOIDmode))
3846 enum rtx_code reversed;
3848 /* Restarting if we generate a store-flag expression will cause
3849 us to loop. Just drop through in this case. */
3851 /* If the result values are STORE_FLAG_VALUE and zero, we can
3852 just make the comparison operation. */
3853 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3854 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3856 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3857 && ((reversed = reversed_comparison_code_parts
3858 (cond_code, cond, cop1, NULL))
3860 x = simplify_gen_relational (reversed, mode, VOIDmode,
3863 /* Likewise, we can make the negate of a comparison operation
3864 if the result values are - STORE_FLAG_VALUE and zero. */
3865 else if (GET_CODE (true_rtx) == CONST_INT
3866 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3867 && false_rtx == const0_rtx)
3868 x = simplify_gen_unary (NEG, mode,
3869 simplify_gen_relational (cond_code,
3873 else if (GET_CODE (false_rtx) == CONST_INT
3874 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3875 && true_rtx == const0_rtx
3876 && ((reversed = reversed_comparison_code_parts
3877 (cond_code, cond, cop1, NULL))
3879 x = simplify_gen_unary (NEG, mode,
3880 simplify_gen_relational (reversed,
3885 return gen_rtx_IF_THEN_ELSE (mode,
3886 simplify_gen_relational (cond_code,
3891 true_rtx, false_rtx);
3893 code = GET_CODE (x);
3894 op0_mode = VOIDmode;
3899 /* Try to fold this expression in case we have constants that weren't
3902 switch (GET_RTX_CLASS (code))
3905 if (op0_mode == VOIDmode)
3906 op0_mode = GET_MODE (XEXP (x, 0));
3907 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3910 case RTX_COMM_COMPARE:
3912 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3913 if (cmp_mode == VOIDmode)
3915 cmp_mode = GET_MODE (XEXP (x, 1));
3916 if (cmp_mode == VOIDmode)
3917 cmp_mode = op0_mode;
3919 temp = simplify_relational_operation (code, mode, cmp_mode,
3920 XEXP (x, 0), XEXP (x, 1));
3923 case RTX_COMM_ARITH:
3925 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3927 case RTX_BITFIELD_OPS:
3929 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3930 XEXP (x, 1), XEXP (x, 2));
3939 code = GET_CODE (temp);
3940 op0_mode = VOIDmode;
3941 mode = GET_MODE (temp);
3944 /* First see if we can apply the inverse distributive law. */
3945 if (code == PLUS || code == MINUS
3946 || code == AND || code == IOR || code == XOR)
3948 x = apply_distributive_law (x);
3949 code = GET_CODE (x);
3950 op0_mode = VOIDmode;
3953 /* If CODE is an associative operation not otherwise handled, see if we
3954 can associate some operands. This can win if they are constants or
3955 if they are logically related (i.e. (a & b) & a). */
3956 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3957 || code == AND || code == IOR || code == XOR
3958 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3959 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3960 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3962 if (GET_CODE (XEXP (x, 0)) == code)
3964 rtx other = XEXP (XEXP (x, 0), 0);
3965 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3966 rtx inner_op1 = XEXP (x, 1);
3969 /* Make sure we pass the constant operand if any as the second
3970 one if this is a commutative operation. */
3971 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3973 rtx tem = inner_op0;
3974 inner_op0 = inner_op1;
3977 inner = simplify_binary_operation (code == MINUS ? PLUS
3978 : code == DIV ? MULT
3980 mode, inner_op0, inner_op1);
3982 /* For commutative operations, try the other pair if that one
3984 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3986 other = XEXP (XEXP (x, 0), 1);
3987 inner = simplify_binary_operation (code, mode,
3988 XEXP (XEXP (x, 0), 0),
3993 return simplify_gen_binary (code, mode, other, inner);
3997 /* A little bit of algebraic simplification here. */
4001 /* Ensure that our address has any ASHIFTs converted to MULT in case
4002 address-recognizing predicates are called later. */
4003 temp = make_compound_operation (XEXP (x, 0), MEM);
4004 SUBST (XEXP (x, 0), temp);
4008 if (op0_mode == VOIDmode)
4009 op0_mode = GET_MODE (SUBREG_REG (x));
4011 /* See if this can be moved to simplify_subreg. */
4012 if (CONSTANT_P (SUBREG_REG (x))
4013 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4014 /* Don't call gen_lowpart if the inner mode
4015 is VOIDmode and we cannot simplify it, as SUBREG without
4016 inner mode is invalid. */
4017 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4018 || gen_lowpart_common (mode, SUBREG_REG (x))))
4019 return gen_lowpart (mode, SUBREG_REG (x));
4021 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4025 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4031 /* Don't change the mode of the MEM if that would change the meaning
4033 if (MEM_P (SUBREG_REG (x))
4034 && (MEM_VOLATILE_P (SUBREG_REG (x))
4035 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4036 return gen_rtx_CLOBBER (mode, const0_rtx);
4038 /* Note that we cannot do any narrowing for non-constants since
4039 we might have been counting on using the fact that some bits were
4040 zero. We now do this in the SET. */
4045 if (GET_CODE (XEXP (x, 0)) == SUBREG
4046 && subreg_lowpart_p (XEXP (x, 0))
4047 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4048 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4049 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4050 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4052 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4054 x = gen_rtx_ROTATE (inner_mode,
4055 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4057 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4058 return gen_lowpart (mode, x);
4061 /* Apply De Morgan's laws to reduce number of patterns for machines
4062 with negating logical insns (and-not, nand, etc.). If result has
4063 only one NOT, put it first, since that is how the patterns are
4066 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4068 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4069 enum machine_mode op_mode;
4071 op_mode = GET_MODE (in1);
4072 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4074 op_mode = GET_MODE (in2);
4075 if (op_mode == VOIDmode)
4077 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4079 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4082 in2 = in1; in1 = tem;
4085 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4091 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4092 if (GET_CODE (XEXP (x, 0)) == XOR
4093 && XEXP (XEXP (x, 0), 1) == const1_rtx
4094 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4095 return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4098 temp = expand_compound_operation (XEXP (x, 0));
4100 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4101 replaced by (lshiftrt X C). This will convert
4102 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4104 if (GET_CODE (temp) == ASHIFTRT
4105 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4106 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4107 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4108 INTVAL (XEXP (temp, 1)));
4110 /* If X has only a single bit that might be nonzero, say, bit I, convert
4111 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4112 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4113 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4114 or a SUBREG of one since we'd be making the expression more
4115 complex if it was just a register. */
4118 && ! (GET_CODE (temp) == SUBREG
4119 && REG_P (SUBREG_REG (temp)))
4120 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4122 rtx temp1 = simplify_shift_const
4123 (NULL_RTX, ASHIFTRT, mode,
4124 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4125 GET_MODE_BITSIZE (mode) - 1 - i),
4126 GET_MODE_BITSIZE (mode) - 1 - i);
4128 /* If all we did was surround TEMP with the two shifts, we
4129 haven't improved anything, so don't use it. Otherwise,
4130 we are better off with TEMP1. */
4131 if (GET_CODE (temp1) != ASHIFTRT
4132 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4133 || XEXP (XEXP (temp1, 0), 0) != temp)
4139 /* We can't handle truncation to a partial integer mode here
4140 because we don't know the real bitsize of the partial
4142 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4145 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4146 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4147 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4149 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4150 GET_MODE_MASK (mode), NULL_RTX, 0));
4152 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4153 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4154 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4155 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4156 return XEXP (XEXP (x, 0), 0);
4158 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4159 (OP:SI foo:SI) if OP is NEG or ABS. */
4160 if ((GET_CODE (XEXP (x, 0)) == ABS
4161 || GET_CODE (XEXP (x, 0)) == NEG)
4162 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4163 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4164 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4165 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4166 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4168 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4170 if (GET_CODE (XEXP (x, 0)) == SUBREG
4171 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4172 && subreg_lowpart_p (XEXP (x, 0)))
4173 return SUBREG_REG (XEXP (x, 0));
4175 /* If we know that the value is already truncated, we can
4176 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4177 is nonzero for the corresponding modes. But don't do this
4178 for an (LSHIFTRT (MULT ...)) since this will cause problems
4179 with the umulXi3_highpart patterns. */
4180 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4181 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4182 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4183 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4184 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4185 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4186 return gen_lowpart (mode, XEXP (x, 0));
4188 /* A truncate of a comparison can be replaced with a subreg if
4189 STORE_FLAG_VALUE permits. This is like the previous test,
4190 but it works even if the comparison is done in a mode larger
4191 than HOST_BITS_PER_WIDE_INT. */
4192 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4193 && COMPARISON_P (XEXP (x, 0))
4194 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4195 return gen_lowpart (mode, XEXP (x, 0));
4197 /* Similarly, a truncate of a register whose value is a
4198 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4200 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4201 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4202 && (temp = get_last_value (XEXP (x, 0)))
4203 && COMPARISON_P (temp))
4204 return gen_lowpart (mode, XEXP (x, 0));
4208 case FLOAT_TRUNCATE:
4209 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4210 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4211 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4212 return XEXP (XEXP (x, 0), 0);
4214 /* (float_truncate:SF (float_truncate:DF foo:XF))
4215 = (float_truncate:SF foo:XF).
4216 This may eliminate double rounding, so it is unsafe.
4218 (float_truncate:SF (float_extend:XF foo:DF))
4219 = (float_truncate:SF foo:DF).
4221 (float_truncate:DF (float_extend:XF foo:SF))
4222 = (float_extend:SF foo:DF). */
4223 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4224 && flag_unsafe_math_optimizations)
4225 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4226 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4228 > GET_MODE_SIZE (mode)
4229 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4231 XEXP (XEXP (x, 0), 0), mode);
4233 /* (float_truncate (float x)) is (float x) */
4234 if (GET_CODE (XEXP (x, 0)) == FLOAT
4235 && (flag_unsafe_math_optimizations
4236 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4237 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4238 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4239 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4240 return simplify_gen_unary (FLOAT, mode,
4241 XEXP (XEXP (x, 0), 0),
4242 GET_MODE (XEXP (XEXP (x, 0), 0)));
4244 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4245 (OP:SF foo:SF) if OP is NEG or ABS. */
4246 if ((GET_CODE (XEXP (x, 0)) == ABS
4247 || GET_CODE (XEXP (x, 0)) == NEG)
4248 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4249 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4250 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4251 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4253 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4254 is (float_truncate:SF x). */
4255 if (GET_CODE (XEXP (x, 0)) == SUBREG
4256 && subreg_lowpart_p (XEXP (x, 0))
4257 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4258 return SUBREG_REG (XEXP (x, 0));
4261 /* (float_extend (float_extend x)) is (float_extend x)
4263 (float_extend (float x)) is (float x) assuming that double
4264 rounding can't happen.
4266 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4267 || (GET_CODE (XEXP (x, 0)) == FLOAT
4268 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4269 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4270 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4271 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4272 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4273 XEXP (XEXP (x, 0), 0),
4274 GET_MODE (XEXP (XEXP (x, 0), 0)));
4279 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4280 using cc0, in which case we want to leave it as a COMPARE
4281 so we can distinguish it from a register-register-copy. */
4282 if (XEXP (x, 1) == const0_rtx)
4285 /* x - 0 is the same as x unless x's mode has signed zeros and
4286 allows rounding towards -infinity. Under those conditions,
4288 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4289 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4290 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4296 /* (const (const X)) can become (const X). Do it this way rather than
4297 returning the inner CONST since CONST can be shared with a
4299 if (GET_CODE (XEXP (x, 0)) == CONST)
4300 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4305 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4306 can add in an offset. find_split_point will split this address up
4307 again if it doesn't match. */
4308 if (GET_CODE (XEXP (x, 0)) == HIGH
4309 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4315 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4317 if (GET_CODE (XEXP (x, 0)) == MULT
4318 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4322 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4323 in2 = XEXP (XEXP (x, 0), 1);
4324 return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4325 simplify_gen_binary (MULT, mode,
4329 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4330 outermost. That's because that's the way indexed addresses are
4331 supposed to appear. This code used to check many more cases, but
4332 they are now checked elsewhere. */
4333 if (GET_CODE (XEXP (x, 0)) == PLUS
4334 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4335 return simplify_gen_binary (PLUS, mode,
4336 simplify_gen_binary (PLUS, mode,
4337 XEXP (XEXP (x, 0), 0),
4339 XEXP (XEXP (x, 0), 1));
4341 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4342 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4343 bit-field and can be replaced by either a sign_extend or a
4344 sign_extract. The `and' may be a zero_extend and the two
4345 <c>, -<c> constants may be reversed. */
4346 if (GET_CODE (XEXP (x, 0)) == XOR
4347 && GET_CODE (XEXP (x, 1)) == CONST_INT
4348 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4349 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4350 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4351 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4352 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4353 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4354 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4355 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4356 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4357 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4358 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4359 == (unsigned int) i + 1))))
4360 return simplify_shift_const
4361 (NULL_RTX, ASHIFTRT, mode,
4362 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4363 XEXP (XEXP (XEXP (x, 0), 0), 0),
4364 GET_MODE_BITSIZE (mode) - (i + 1)),
4365 GET_MODE_BITSIZE (mode) - (i + 1));
4367 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4368 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4369 is 1. This produces better code than the alternative immediately
4371 if (COMPARISON_P (XEXP (x, 0))
4372 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4373 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4374 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4375 XEXP (XEXP (x, 0), 0),
4376 XEXP (XEXP (x, 0), 1))))
4378 simplify_gen_unary (NEG, mode, reversed, mode);
4380 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4381 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4382 the bitsize of the mode - 1. This allows simplification of
4383 "a = (b & 8) == 0;" */
4384 if (XEXP (x, 1) == constm1_rtx
4385 && !REG_P (XEXP (x, 0))
4386 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4387 && REG_P (SUBREG_REG (XEXP (x, 0))))
4388 && nonzero_bits (XEXP (x, 0), mode) == 1)
4389 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4390 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4391 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4392 GET_MODE_BITSIZE (mode) - 1),
4393 GET_MODE_BITSIZE (mode) - 1);
4395 /* If we are adding two things that have no bits in common, convert
4396 the addition into an IOR. This will often be further simplified,
4397 for example in cases like ((a & 1) + (a & 2)), which can
4400 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4401 && (nonzero_bits (XEXP (x, 0), mode)
4402 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4404 /* Try to simplify the expression further. */
4405 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4406 temp = combine_simplify_rtx (tor, mode, in_dest);
4408 /* If we could, great. If not, do not go ahead with the IOR
4409 replacement, since PLUS appears in many special purpose
4410 address arithmetic instructions. */
4411 if (GET_CODE (temp) != CLOBBER && temp != tor)
4417 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4418 by reversing the comparison code if valid. */
4419 if (STORE_FLAG_VALUE == 1
4420 && XEXP (x, 0) == const1_rtx
4421 && COMPARISON_P (XEXP (x, 1))
4422 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4423 XEXP (XEXP (x, 1), 0),
4424 XEXP (XEXP (x, 1), 1))))
4427 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4428 (and <foo> (const_int pow2-1)) */
4429 if (GET_CODE (XEXP (x, 1)) == AND
4430 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4431 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4432 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4433 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4434 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4436 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4438 if (GET_CODE (XEXP (x, 1)) == MULT
4439 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4443 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4444 in2 = XEXP (XEXP (x, 1), 1);
4445 return simplify_gen_binary (PLUS, mode,
4446 simplify_gen_binary (MULT, mode,
4451 /* Canonicalize (minus (neg A) (mult B C)) to
4452 (minus (mult (neg B) C) A). */
4453 if (GET_CODE (XEXP (x, 1)) == MULT
4454 && GET_CODE (XEXP (x, 0)) == NEG)
4458 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4459 in2 = XEXP (XEXP (x, 1), 1);
4460 return simplify_gen_binary (MINUS, mode,
4461 simplify_gen_binary (MULT, mode,
4463 XEXP (XEXP (x, 0), 0));
4466 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4468 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4469 return simplify_gen_binary (MINUS, mode,
4470 simplify_gen_binary (MINUS, mode,
4472 XEXP (XEXP (x, 1), 0)),
4473 XEXP (XEXP (x, 1), 1));
4477 /* If we have (mult (plus A B) C), apply the distributive law and then
4478 the inverse distributive law to see if things simplify. This
4479 occurs mostly in addresses, often when unrolling loops. */
4481 if (GET_CODE (XEXP (x, 0)) == PLUS)
4483 rtx result = distribute_and_simplify_rtx (x, 0);
4488 /* Try simplify a*(b/c) as (a*b)/c. */
4489 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4490 && GET_CODE (XEXP (x, 0)) == DIV)
4492 rtx tem = simplify_binary_operation (MULT, mode,
4493 XEXP (XEXP (x, 0), 0),
4496 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4501 /* If this is a divide by a power of two, treat it as a shift if
4502 its first operand is a shift. */
4503 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4504 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4505 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4506 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4507 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4508 || GET_CODE (XEXP (x, 0)) == ROTATE
4509 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4510 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4514 case GT: case GTU: case GE: case GEU:
4515 case LT: case LTU: case LE: case LEU:
4516 case UNEQ: case LTGT:
4517 case UNGT: case UNGE:
4518 case UNLT: case UNLE:
4519 case UNORDERED: case ORDERED:
4520 /* If the first operand is a condition code, we can't do anything
4522 if (GET_CODE (XEXP (x, 0)) == COMPARE
4523 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4524 && ! CC0_P (XEXP (x, 0))))
4526 rtx op0 = XEXP (x, 0);
4527 rtx op1 = XEXP (x, 1);
4528 enum rtx_code new_code;
4530 if (GET_CODE (op0) == COMPARE)
4531 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4533 /* Simplify our comparison, if possible. */
4534 new_code = simplify_comparison (code, &op0, &op1);
4536 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4537 if only the low-order bit is possibly nonzero in X (such as when
4538 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4539 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4540 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4543 Remove any ZERO_EXTRACT we made when thinking this was a
4544 comparison. It may now be simpler to use, e.g., an AND. If a
4545 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4546 the call to make_compound_operation in the SET case. */
4548 if (STORE_FLAG_VALUE == 1
4549 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4550 && op1 == const0_rtx
4551 && mode == GET_MODE (op0)
4552 && nonzero_bits (op0, mode) == 1)
4553 return gen_lowpart (mode,
4554 expand_compound_operation (op0));
4556 else if (STORE_FLAG_VALUE == 1
4557 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4558 && op1 == const0_rtx
4559 && mode == GET_MODE (op0)
4560 && (num_sign_bit_copies (op0, mode)
4561 == GET_MODE_BITSIZE (mode)))
4563 op0 = expand_compound_operation (op0);
4564 return simplify_gen_unary (NEG, mode,
4565 gen_lowpart (mode, op0),
4569 else if (STORE_FLAG_VALUE == 1
4570 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4571 && op1 == const0_rtx
4572 && mode == GET_MODE (op0)
4573 && nonzero_bits (op0, mode) == 1)
4575 op0 = expand_compound_operation (op0);
4576 return simplify_gen_binary (XOR, mode,
4577 gen_lowpart (mode, op0),
4581 else if (STORE_FLAG_VALUE == 1
4582 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4583 && op1 == const0_rtx
4584 && mode == GET_MODE (op0)
4585 && (num_sign_bit_copies (op0, mode)
4586 == GET_MODE_BITSIZE (mode)))
4588 op0 = expand_compound_operation (op0);
4589 return plus_constant (gen_lowpart (mode, op0), 1);
4592 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4594 if (STORE_FLAG_VALUE == -1
4595 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4596 && op1 == const0_rtx
4597 && (num_sign_bit_copies (op0, mode)
4598 == GET_MODE_BITSIZE (mode)))
4599 return gen_lowpart (mode,
4600 expand_compound_operation (op0));
4602 else if (STORE_FLAG_VALUE == -1
4603 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4604 && op1 == const0_rtx
4605 && mode == GET_MODE (op0)
4606 && nonzero_bits (op0, mode) == 1)
4608 op0 = expand_compound_operation (op0);
4609 return simplify_gen_unary (NEG, mode,
4610 gen_lowpart (mode, op0),
4614 else if (STORE_FLAG_VALUE == -1
4615 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4616 && op1 == const0_rtx
4617 && mode == GET_MODE (op0)
4618 && (num_sign_bit_copies (op0, mode)
4619 == GET_MODE_BITSIZE (mode)))
4621 op0 = expand_compound_operation (op0);
4622 return simplify_gen_unary (NOT, mode,
4623 gen_lowpart (mode, op0),
4627 /* If X is 0/1, (eq X 0) is X-1. */
4628 else if (STORE_FLAG_VALUE == -1
4629 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4630 && op1 == const0_rtx
4631 && mode == GET_MODE (op0)
4632 && nonzero_bits (op0, mode) == 1)
4634 op0 = expand_compound_operation (op0);
4635 return plus_constant (gen_lowpart (mode, op0), -1);
4638 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4639 one bit that might be nonzero, we can convert (ne x 0) to
4640 (ashift x c) where C puts the bit in the sign bit. Remove any
4641 AND with STORE_FLAG_VALUE when we are done, since we are only
4642 going to test the sign bit. */
4643 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4644 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4645 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4646 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4647 && op1 == const0_rtx
4648 && mode == GET_MODE (op0)
4649 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4651 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4652 expand_compound_operation (op0),
4653 GET_MODE_BITSIZE (mode) - 1 - i);
4654 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4660 /* If the code changed, return a whole new comparison. */
4661 if (new_code != code)
4662 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4664 /* Otherwise, keep this operation, but maybe change its operands.
4665 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4666 SUBST (XEXP (x, 0), op0);
4667 SUBST (XEXP (x, 1), op1);
4672 return simplify_if_then_else (x);
4678 /* If we are processing SET_DEST, we are done. */
4682 return expand_compound_operation (x);
4685 return simplify_set (x);
4690 return simplify_logical (x);
4693 /* (abs (neg <foo>)) -> (abs <foo>) */
4694 if (GET_CODE (XEXP (x, 0)) == NEG)
4695 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4697 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4699 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4702 /* If operand is something known to be positive, ignore the ABS. */
4703 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4704 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4705 <= HOST_BITS_PER_WIDE_INT)
4706 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4707 & ((HOST_WIDE_INT) 1
4708 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4712 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4713 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4714 return gen_rtx_NEG (mode, XEXP (x, 0));
4719 /* (ffs (*_extend <X>)) = (ffs <X>) */
4720 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4721 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4722 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4727 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4728 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4729 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4733 /* (float (sign_extend <X>)) = (float <X>). */
4734 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4735 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4743 /* If this is a shift by a constant amount, simplify it. */
4744 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4745 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4746 INTVAL (XEXP (x, 1)));
4748 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4750 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4752 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4759 rtx op0 = XEXP (x, 0);
4760 rtx op1 = XEXP (x, 1);
4763 gcc_assert (GET_CODE (op1) == PARALLEL);
4764 len = XVECLEN (op1, 0);
4766 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4767 && GET_CODE (op0) == VEC_CONCAT)
4769 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4771 /* Try to find the element in the VEC_CONCAT. */
4774 if (GET_MODE (op0) == GET_MODE (x))
4776 if (GET_CODE (op0) == VEC_CONCAT)
4778 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4779 if (op0_size < offset)
4780 op0 = XEXP (op0, 0);
4784 op0 = XEXP (op0, 1);
4802 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4805 simplify_if_then_else (rtx x)
4807 enum machine_mode mode = GET_MODE (x);
4808 rtx cond = XEXP (x, 0);
4809 rtx true_rtx = XEXP (x, 1);
4810 rtx false_rtx = XEXP (x, 2);
4811 enum rtx_code true_code = GET_CODE (cond);
4812 int comparison_p = COMPARISON_P (cond);
4815 enum rtx_code false_code;
4818 /* Simplify storing of the truth value. */
4819 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4820 return simplify_gen_relational (true_code, mode, VOIDmode,
4821 XEXP (cond, 0), XEXP (cond, 1));
4823 /* Also when the truth value has to be reversed. */
4825 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4826 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4830 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4831 in it is being compared against certain values. Get the true and false
4832 comparisons and see if that says anything about the value of each arm. */
4835 && ((false_code = combine_reversed_comparison_code (cond))
4837 && REG_P (XEXP (cond, 0)))
4840 rtx from = XEXP (cond, 0);
4841 rtx true_val = XEXP (cond, 1);
4842 rtx false_val = true_val;
4845 /* If FALSE_CODE is EQ, swap the codes and arms. */
4847 if (false_code == EQ)
4849 swapped = 1, true_code = EQ, false_code = NE;
4850 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4853 /* If we are comparing against zero and the expression being tested has
4854 only a single bit that might be nonzero, that is its value when it is
4855 not equal to zero. Similarly if it is known to be -1 or 0. */
4857 if (true_code == EQ && true_val == const0_rtx
4858 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4859 false_code = EQ, false_val = GEN_INT (nzb);
4860 else if (true_code == EQ && true_val == const0_rtx
4861 && (num_sign_bit_copies (from, GET_MODE (from))
4862 == GET_MODE_BITSIZE (GET_MODE (from))))
4863 false_code = EQ, false_val = constm1_rtx;
4865 /* Now simplify an arm if we know the value of the register in the
4866 branch and it is used in the arm. Be careful due to the potential
4867 of locally-shared RTL. */
4869 if (reg_mentioned_p (from, true_rtx))
4870 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4872 pc_rtx, pc_rtx, 0, 0);
4873 if (reg_mentioned_p (from, false_rtx))
4874 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4876 pc_rtx, pc_rtx, 0, 0);
4878 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4879 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4881 true_rtx = XEXP (x, 1);
4882 false_rtx = XEXP (x, 2);
4883 true_code = GET_CODE (cond);
4886 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4887 reversed, do so to avoid needing two sets of patterns for
4888 subtract-and-branch insns. Similarly if we have a constant in the true
4889 arm, the false arm is the same as the first operand of the comparison, or
4890 the false arm is more complicated than the true arm. */
4893 && combine_reversed_comparison_code (cond) != UNKNOWN
4894 && (true_rtx == pc_rtx
4895 || (CONSTANT_P (true_rtx)
4896 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4897 || true_rtx == const0_rtx
4898 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4899 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4900 && !OBJECT_P (false_rtx))
4901 || reg_mentioned_p (true_rtx, false_rtx)
4902 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4904 true_code = reversed_comparison_code (cond, NULL);
4906 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4909 SUBST (XEXP (x, 1), false_rtx);
4910 SUBST (XEXP (x, 2), true_rtx);
4912 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4915 /* It is possible that the conditional has been simplified out. */
4916 true_code = GET_CODE (cond);
4917 comparison_p = COMPARISON_P (cond);
4920 /* If the two arms are identical, we don't need the comparison. */
4922 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4925 /* Convert a == b ? b : a to "a". */
4926 if (true_code == EQ && ! side_effects_p (cond)
4927 && !HONOR_NANS (mode)
4928 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4929 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4931 else if (true_code == NE && ! side_effects_p (cond)
4932 && !HONOR_NANS (mode)
4933 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4934 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4937 /* Look for cases where we have (abs x) or (neg (abs X)). */
4939 if (GET_MODE_CLASS (mode) == MODE_INT
4940 && GET_CODE (false_rtx) == NEG
4941 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4943 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4944 && ! side_effects_p (true_rtx))
4949 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4953 simplify_gen_unary (NEG, mode,
4954 simplify_gen_unary (ABS, mode, true_rtx, mode),
4960 /* Look for MIN or MAX. */
4962 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4964 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4965 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4966 && ! side_effects_p (cond))
4971 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4974 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4977 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4980 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4985 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4986 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4987 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4988 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4989 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4990 neither 1 or -1, but it isn't worth checking for. */
4992 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4994 && GET_MODE_CLASS (mode) == MODE_INT
4995 && ! side_effects_p (x))
4997 rtx t = make_compound_operation (true_rtx, SET);
4998 rtx f = make_compound_operation (false_rtx, SET);
4999 rtx cond_op0 = XEXP (cond, 0);
5000 rtx cond_op1 = XEXP (cond, 1);
5001 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5002 enum machine_mode m = mode;
5003 rtx z = 0, c1 = NULL_RTX;
5005 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5006 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5007 || GET_CODE (t) == ASHIFT
5008 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5009 && rtx_equal_p (XEXP (t, 0), f))
5010 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5012 /* If an identity-zero op is commutative, check whether there
5013 would be a match if we swapped the operands. */
5014 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5015 || GET_CODE (t) == XOR)
5016 && rtx_equal_p (XEXP (t, 1), f))
5017 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5018 else if (GET_CODE (t) == SIGN_EXTEND
5019 && (GET_CODE (XEXP (t, 0)) == PLUS
5020 || GET_CODE (XEXP (t, 0)) == MINUS
5021 || GET_CODE (XEXP (t, 0)) == IOR
5022 || GET_CODE (XEXP (t, 0)) == XOR
5023 || GET_CODE (XEXP (t, 0)) == ASHIFT
5024 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5025 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5026 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5027 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5028 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5029 && (num_sign_bit_copies (f, GET_MODE (f))
5031 (GET_MODE_BITSIZE (mode)
5032 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5034 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5035 extend_op = SIGN_EXTEND;
5036 m = GET_MODE (XEXP (t, 0));
5038 else if (GET_CODE (t) == SIGN_EXTEND
5039 && (GET_CODE (XEXP (t, 0)) == PLUS
5040 || GET_CODE (XEXP (t, 0)) == IOR
5041 || GET_CODE (XEXP (t, 0)) == XOR)
5042 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5043 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5044 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5045 && (num_sign_bit_copies (f, GET_MODE (f))
5047 (GET_MODE_BITSIZE (mode)
5048 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5050 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5051 extend_op = SIGN_EXTEND;
5052 m = GET_MODE (XEXP (t, 0));
5054 else if (GET_CODE (t) == ZERO_EXTEND
5055 && (GET_CODE (XEXP (t, 0)) == PLUS
5056 || GET_CODE (XEXP (t, 0)) == MINUS
5057 || GET_CODE (XEXP (t, 0)) == IOR
5058 || GET_CODE (XEXP (t, 0)) == XOR
5059 || GET_CODE (XEXP (t, 0)) == ASHIFT
5060 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5061 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5062 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5063 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5064 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5065 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5066 && ((nonzero_bits (f, GET_MODE (f))
5067 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5070 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5071 extend_op = ZERO_EXTEND;
5072 m = GET_MODE (XEXP (t, 0));
5074 else if (GET_CODE (t) == ZERO_EXTEND
5075 && (GET_CODE (XEXP (t, 0)) == PLUS
5076 || GET_CODE (XEXP (t, 0)) == IOR
5077 || GET_CODE (XEXP (t, 0)) == XOR)
5078 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5079 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5080 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5081 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5082 && ((nonzero_bits (f, GET_MODE (f))
5083 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5086 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5087 extend_op = ZERO_EXTEND;
5088 m = GET_MODE (XEXP (t, 0));
5093 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5094 cond_op0, cond_op1),
5095 pc_rtx, pc_rtx, 0, 0);
5096 temp = simplify_gen_binary (MULT, m, temp,
5097 simplify_gen_binary (MULT, m, c1,
5099 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5100 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5102 if (extend_op != UNKNOWN)
5103 temp = simplify_gen_unary (extend_op, mode, temp, m);
5109 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5110 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5111 negation of a single bit, we can convert this operation to a shift. We
5112 can actually do this more generally, but it doesn't seem worth it. */
5114 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5115 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5116 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5117 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5118 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5119 == GET_MODE_BITSIZE (mode))
5120 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5122 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5123 gen_lowpart (mode, XEXP (cond, 0)), i);
5125 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5126 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5127 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5128 && GET_MODE (XEXP (cond, 0)) == mode
5129 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5130 == nonzero_bits (XEXP (cond, 0), mode)
5131 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5132 return XEXP (cond, 0);
5137 /* Simplify X, a SET expression. Return the new expression. */
5140 simplify_set (rtx x)
5142 rtx src = SET_SRC (x);
5143 rtx dest = SET_DEST (x);
5144 enum machine_mode mode
5145 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5149 /* (set (pc) (return)) gets written as (return). */
5150 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5153 /* Now that we know for sure which bits of SRC we are using, see if we can
5154 simplify the expression for the object knowing that we only need the
5157 if (GET_MODE_CLASS (mode) == MODE_INT
5158 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5160 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5161 SUBST (SET_SRC (x), src);
5164 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5165 the comparison result and try to simplify it unless we already have used
5166 undobuf.other_insn. */
5167 if ((GET_MODE_CLASS (mode) == MODE_CC
5168 || GET_CODE (src) == COMPARE
5170 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5171 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5172 && COMPARISON_P (*cc_use)
5173 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5175 enum rtx_code old_code = GET_CODE (*cc_use);
5176 enum rtx_code new_code;
5178 int other_changed = 0;
5179 enum machine_mode compare_mode = GET_MODE (dest);
5181 if (GET_CODE (src) == COMPARE)
5182 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5184 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5186 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5189 new_code = old_code;
5190 else if (!CONSTANT_P (tmp))
5192 new_code = GET_CODE (tmp);
5193 op0 = XEXP (tmp, 0);
5194 op1 = XEXP (tmp, 1);
5198 rtx pat = PATTERN (other_insn);
5199 undobuf.other_insn = other_insn;
5200 SUBST (*cc_use, tmp);
5202 /* Attempt to simplify CC user. */
5203 if (GET_CODE (pat) == SET)
5205 rtx new = simplify_rtx (SET_SRC (pat));
5206 if (new != NULL_RTX)
5207 SUBST (SET_SRC (pat), new);
5210 /* Convert X into a no-op move. */
5211 SUBST (SET_DEST (x), pc_rtx);
5212 SUBST (SET_SRC (x), pc_rtx);
5216 /* Simplify our comparison, if possible. */
5217 new_code = simplify_comparison (new_code, &op0, &op1);
5219 #ifdef SELECT_CC_MODE
5220 /* If this machine has CC modes other than CCmode, check to see if we
5221 need to use a different CC mode here. */
5222 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5223 compare_mode = GET_MODE (op0);
5225 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5228 /* If the mode changed, we have to change SET_DEST, the mode in the
5229 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5230 a hard register, just build new versions with the proper mode. If it
5231 is a pseudo, we lose unless it is only time we set the pseudo, in
5232 which case we can safely change its mode. */
5233 if (compare_mode != GET_MODE (dest))
5235 unsigned int regno = REGNO (dest);
5236 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5238 if (regno < FIRST_PSEUDO_REGISTER
5239 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5241 if (regno >= FIRST_PSEUDO_REGISTER)
5242 SUBST (regno_reg_rtx[regno], new_dest);
5244 SUBST (SET_DEST (x), new_dest);
5245 SUBST (XEXP (*cc_use, 0), new_dest);
5252 #endif /* SELECT_CC_MODE */
5254 /* If the code changed, we have to build a new comparison in
5255 undobuf.other_insn. */
5256 if (new_code != old_code)
5258 int other_changed_previously = other_changed;
5259 unsigned HOST_WIDE_INT mask;
5261 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5265 /* If the only change we made was to change an EQ into an NE or
5266 vice versa, OP0 has only one bit that might be nonzero, and OP1
5267 is zero, check if changing the user of the condition code will
5268 produce a valid insn. If it won't, we can keep the original code
5269 in that insn by surrounding our operation with an XOR. */
5271 if (((old_code == NE && new_code == EQ)
5272 || (old_code == EQ && new_code == NE))
5273 && ! other_changed_previously && op1 == const0_rtx
5274 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5275 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5277 rtx pat = PATTERN (other_insn), note = 0;
5279 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5280 && ! check_asm_operands (pat)))
5282 PUT_CODE (*cc_use, old_code);
5285 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5286 op0, GEN_INT (mask));
5292 undobuf.other_insn = other_insn;
5295 /* If we are now comparing against zero, change our source if
5296 needed. If we do not use cc0, we always have a COMPARE. */
5297 if (op1 == const0_rtx && dest == cc0_rtx)
5299 SUBST (SET_SRC (x), op0);
5305 /* Otherwise, if we didn't previously have a COMPARE in the
5306 correct mode, we need one. */
5307 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5309 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5314 /* Otherwise, update the COMPARE if needed. */
5315 SUBST (XEXP (src, 0), op0);
5316 SUBST (XEXP (src, 1), op1);
5321 /* Get SET_SRC in a form where we have placed back any
5322 compound expressions. Then do the checks below. */
5323 src = make_compound_operation (src, SET);
5324 SUBST (SET_SRC (x), src);
5327 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5328 and X being a REG or (subreg (reg)), we may be able to convert this to
5329 (set (subreg:m2 x) (op)).
5331 We can always do this if M1 is narrower than M2 because that means that
5332 we only care about the low bits of the result.
5334 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5335 perform a narrower operation than requested since the high-order bits will
5336 be undefined. On machine where it is defined, this transformation is safe
5337 as long as M1 and M2 have the same number of words. */
5339 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5340 && !OBJECT_P (SUBREG_REG (src))
5341 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5343 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5344 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5345 #ifndef WORD_REGISTER_OPERATIONS
5346 && (GET_MODE_SIZE (GET_MODE (src))
5347 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5349 #ifdef CANNOT_CHANGE_MODE_CLASS
5350 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5351 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5352 GET_MODE (SUBREG_REG (src)),
5356 || (GET_CODE (dest) == SUBREG
5357 && REG_P (SUBREG_REG (dest)))))
5359 SUBST (SET_DEST (x),
5360 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5362 SUBST (SET_SRC (x), SUBREG_REG (src));
5364 src = SET_SRC (x), dest = SET_DEST (x);
5368 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5371 && GET_CODE (src) == SUBREG
5372 && subreg_lowpart_p (src)
5373 && (GET_MODE_BITSIZE (GET_MODE (src))
5374 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5376 rtx inner = SUBREG_REG (src);
5377 enum machine_mode inner_mode = GET_MODE (inner);
5379 /* Here we make sure that we don't have a sign bit on. */
5380 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5381 && (nonzero_bits (inner, inner_mode)
5382 < ((unsigned HOST_WIDE_INT) 1
5383 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5385 SUBST (SET_SRC (x), inner);
5391 #ifdef LOAD_EXTEND_OP
5392 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5393 would require a paradoxical subreg. Replace the subreg with a
5394 zero_extend to avoid the reload that would otherwise be required. */
5396 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5397 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5398 && SUBREG_BYTE (src) == 0
5399 && (GET_MODE_SIZE (GET_MODE (src))
5400 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5401 && MEM_P (SUBREG_REG (src)))
5404 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5405 GET_MODE (src), SUBREG_REG (src)));
5411 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5412 are comparing an item known to be 0 or -1 against 0, use a logical
5413 operation instead. Check for one of the arms being an IOR of the other
5414 arm with some value. We compute three terms to be IOR'ed together. In
5415 practice, at most two will be nonzero. Then we do the IOR's. */
5417 if (GET_CODE (dest) != PC
5418 && GET_CODE (src) == IF_THEN_ELSE
5419 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5420 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5421 && XEXP (XEXP (src, 0), 1) == const0_rtx
5422 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5423 #ifdef HAVE_conditional_move
5424 && ! can_conditionally_move_p (GET_MODE (src))
5426 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5427 GET_MODE (XEXP (XEXP (src, 0), 0)))
5428 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5429 && ! side_effects_p (src))
5431 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5432 ? XEXP (src, 1) : XEXP (src, 2));
5433 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5434 ? XEXP (src, 2) : XEXP (src, 1));
5435 rtx term1 = const0_rtx, term2, term3;
5437 if (GET_CODE (true_rtx) == IOR
5438 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5439 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5440 else if (GET_CODE (true_rtx) == IOR
5441 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5442 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5443 else if (GET_CODE (false_rtx) == IOR
5444 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5445 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5446 else if (GET_CODE (false_rtx) == IOR
5447 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5448 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5450 term2 = simplify_gen_binary (AND, GET_MODE (src),
5451 XEXP (XEXP (src, 0), 0), true_rtx);
5452 term3 = simplify_gen_binary (AND, GET_MODE (src),
5453 simplify_gen_unary (NOT, GET_MODE (src),
5454 XEXP (XEXP (src, 0), 0),
5459 simplify_gen_binary (IOR, GET_MODE (src),
5460 simplify_gen_binary (IOR, GET_MODE (src),
5467 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5468 whole thing fail. */
5469 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5471 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5474 /* Convert this into a field assignment operation, if possible. */
5475 return make_field_assignment (x);
5478 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5482 simplify_logical (rtx x)
5484 enum machine_mode mode = GET_MODE (x);
5485 rtx op0 = XEXP (x, 0);
5486 rtx op1 = XEXP (x, 1);
5489 switch (GET_CODE (x))
5492 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5493 insn (and may simplify more). */
5494 if (GET_CODE (op0) == XOR
5495 && rtx_equal_p (XEXP (op0, 0), op1)
5496 && ! side_effects_p (op1))
5497 x = simplify_gen_binary (AND, mode,
5498 simplify_gen_unary (NOT, mode,
5499 XEXP (op0, 1), mode),
5502 if (GET_CODE (op0) == XOR
5503 && rtx_equal_p (XEXP (op0, 1), op1)
5504 && ! side_effects_p (op1))
5505 x = simplify_gen_binary (AND, mode,
5506 simplify_gen_unary (NOT, mode,
5507 XEXP (op0, 0), mode),
5510 /* Similarly for (~(A ^ B)) & A. */
5511 if (GET_CODE (op0) == NOT
5512 && GET_CODE (XEXP (op0, 0)) == XOR
5513 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5514 && ! side_effects_p (op1))
5515 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5517 if (GET_CODE (op0) == NOT
5518 && GET_CODE (XEXP (op0, 0)) == XOR
5519 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5520 && ! side_effects_p (op1))
5521 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5523 /* We can call simplify_and_const_int only if we don't lose
5524 any (sign) bits when converting INTVAL (op1) to
5525 "unsigned HOST_WIDE_INT". */
5526 if (GET_CODE (op1) == CONST_INT
5527 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5528 || INTVAL (op1) > 0))
5530 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5532 /* If we have (ior (and (X C1) C2)) and the next restart would be
5533 the last, simplify this by making C1 as small as possible
5534 and then exit. Only do this if C1 actually changes: for now
5535 this only saves memory but, should this transformation be
5536 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5537 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5538 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5539 && GET_CODE (op1) == CONST_INT
5540 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5541 return simplify_gen_binary (IOR, mode,
5543 (AND, mode, XEXP (op0, 0),
5544 GEN_INT (INTVAL (XEXP (op0, 1))
5545 & ~INTVAL (op1))), op1);
5547 if (GET_CODE (x) != AND)
5554 /* Convert (A | B) & A to A. */
5555 if (GET_CODE (op0) == IOR
5556 && (rtx_equal_p (XEXP (op0, 0), op1)
5557 || rtx_equal_p (XEXP (op0, 1), op1))
5558 && ! side_effects_p (XEXP (op0, 0))
5559 && ! side_effects_p (XEXP (op0, 1)))
5562 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5563 apply the distributive law and then the inverse distributive
5564 law to see if things simplify. */
5565 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5567 rtx result = distribute_and_simplify_rtx (x, 0);
5571 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5573 rtx result = distribute_and_simplify_rtx (x, 1);
5580 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5581 if (GET_CODE (op1) == CONST_INT
5582 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5583 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5586 /* Convert (A & B) | A to A. */
5587 if (GET_CODE (op0) == AND
5588 && (rtx_equal_p (XEXP (op0, 0), op1)
5589 || rtx_equal_p (XEXP (op0, 1), op1))
5590 && ! side_effects_p (XEXP (op0, 0))
5591 && ! side_effects_p (XEXP (op0, 1)))
5594 /* If we have (ior (and A B) C), apply the distributive law and then
5595 the inverse distributive law to see if things simplify. */
5597 if (GET_CODE (op0) == AND)
5599 rtx result = distribute_and_simplify_rtx (x, 0);
5604 if (GET_CODE (op1) == AND)
5606 rtx result = distribute_and_simplify_rtx (x, 1);
5611 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5612 mode size to (rotate A CX). */
5614 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5615 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5616 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5617 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5618 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5619 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5620 == GET_MODE_BITSIZE (mode)))
5621 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5622 (GET_CODE (op0) == ASHIFT
5623 ? XEXP (op0, 1) : XEXP (op1, 1)));
5625 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5626 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5627 does not affect any of the bits in OP1, it can really be done
5628 as a PLUS and we can associate. We do this by seeing if OP1
5629 can be safely shifted left C bits. */
5630 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5631 && GET_CODE (XEXP (op0, 0)) == PLUS
5632 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5633 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5634 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5636 int count = INTVAL (XEXP (op0, 1));
5637 HOST_WIDE_INT mask = INTVAL (op1) << count;
5639 if (mask >> count == INTVAL (op1)
5640 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5642 SUBST (XEXP (XEXP (op0, 0), 1),
5643 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5650 /* If we are XORing two things that have no bits in common,
5651 convert them into an IOR. This helps to detect rotation encoded
5652 using those methods and possibly other simplifications. */
5654 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5655 && (nonzero_bits (op0, mode)
5656 & nonzero_bits (op1, mode)) == 0)
5657 return (simplify_gen_binary (IOR, mode, op0, op1));
5659 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5660 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5663 int num_negated = 0;
5665 if (GET_CODE (op0) == NOT)
5666 num_negated++, op0 = XEXP (op0, 0);
5667 if (GET_CODE (op1) == NOT)
5668 num_negated++, op1 = XEXP (op1, 0);
5670 if (num_negated == 2)
5672 SUBST (XEXP (x, 0), op0);
5673 SUBST (XEXP (x, 1), op1);
5675 else if (num_negated == 1)
5677 simplify_gen_unary (NOT, mode,
5678 simplify_gen_binary (XOR, mode, op0, op1),
5682 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5683 correspond to a machine insn or result in further simplifications
5684 if B is a constant. */
5686 if (GET_CODE (op0) == AND
5687 && rtx_equal_p (XEXP (op0, 1), op1)
5688 && ! side_effects_p (op1))
5689 return simplify_gen_binary (AND, mode,
5690 simplify_gen_unary (NOT, mode,
5691 XEXP (op0, 0), mode),
5694 else if (GET_CODE (op0) == AND
5695 && rtx_equal_p (XEXP (op0, 0), op1)
5696 && ! side_effects_p (op1))
5697 return simplify_gen_binary (AND, mode,
5698 simplify_gen_unary (NOT, mode,
5699 XEXP (op0, 1), mode),
5702 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5703 comparison if STORE_FLAG_VALUE is 1. */
5704 if (STORE_FLAG_VALUE == 1
5705 && op1 == const1_rtx
5706 && COMPARISON_P (op0)
5707 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5711 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5712 is (lt foo (const_int 0)), so we can perform the above
5713 simplification if STORE_FLAG_VALUE is 1. */
5715 if (STORE_FLAG_VALUE == 1
5716 && op1 == const1_rtx
5717 && GET_CODE (op0) == LSHIFTRT
5718 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5719 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5720 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5722 /* (xor (comparison foo bar) (const_int sign-bit))
5723 when STORE_FLAG_VALUE is the sign bit. */
5724 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5725 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5726 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5727 && op1 == const_true_rtx
5728 && COMPARISON_P (op0)
5729 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5742 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5743 operations" because they can be replaced with two more basic operations.
5744 ZERO_EXTEND is also considered "compound" because it can be replaced with
5745 an AND operation, which is simpler, though only one operation.
5747 The function expand_compound_operation is called with an rtx expression
5748 and will convert it to the appropriate shifts and AND operations,
5749 simplifying at each stage.
5751 The function make_compound_operation is called to convert an expression
5752 consisting of shifts and ANDs into the equivalent compound expression.
5753 It is the inverse of this function, loosely speaking. */
5756 expand_compound_operation (rtx x)
5758 unsigned HOST_WIDE_INT pos = 0, len;
5760 unsigned int modewidth;
5763 switch (GET_CODE (x))
5768 /* We can't necessarily use a const_int for a multiword mode;
5769 it depends on implicitly extending the value.
5770 Since we don't know the right way to extend it,
5771 we can't tell whether the implicit way is right.
5773 Even for a mode that is no wider than a const_int,
5774 we can't win, because we need to sign extend one of its bits through
5775 the rest of it, and we don't know which bit. */
5776 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5779 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5780 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5781 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5782 reloaded. If not for that, MEM's would very rarely be safe.
5784 Reject MODEs bigger than a word, because we might not be able
5785 to reference a two-register group starting with an arbitrary register
5786 (and currently gen_lowpart might crash for a SUBREG). */
5788 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5791 /* Reject MODEs that aren't scalar integers because turning vector
5792 or complex modes into shifts causes problems. */
5794 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5797 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5798 /* If the inner object has VOIDmode (the only way this can happen
5799 is if it is an ASM_OPERANDS), we can't do anything since we don't
5800 know how much masking to do. */
5809 /* ... fall through ... */
5812 /* If the operand is a CLOBBER, just return it. */
5813 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5816 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5817 || GET_CODE (XEXP (x, 2)) != CONST_INT
5818 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5821 /* Reject MODEs that aren't scalar integers because turning vector
5822 or complex modes into shifts causes problems. */
5824 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5827 len = INTVAL (XEXP (x, 1));
5828 pos = INTVAL (XEXP (x, 2));
5830 /* If this goes outside the object being extracted, replace the object
5831 with a (use (mem ...)) construct that only combine understands
5832 and is used only for this purpose. */
5833 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5834 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5836 if (BITS_BIG_ENDIAN)
5837 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5844 /* Convert sign extension to zero extension, if we know that the high
5845 bit is not set, as this is easier to optimize. It will be converted
5846 back to cheaper alternative in make_extraction. */
5847 if (GET_CODE (x) == SIGN_EXTEND
5848 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5849 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5850 & ~(((unsigned HOST_WIDE_INT)
5851 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5855 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5856 rtx temp2 = expand_compound_operation (temp);
5858 /* Make sure this is a profitable operation. */
5859 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5861 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5867 /* We can optimize some special cases of ZERO_EXTEND. */
5868 if (GET_CODE (x) == ZERO_EXTEND)
5870 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5871 know that the last value didn't have any inappropriate bits
5873 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5874 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5875 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5876 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5877 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5878 return XEXP (XEXP (x, 0), 0);
5880 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5881 if (GET_CODE (XEXP (x, 0)) == SUBREG
5882 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5883 && subreg_lowpart_p (XEXP (x, 0))
5884 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5885 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5886 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5887 return SUBREG_REG (XEXP (x, 0));
5889 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5890 is a comparison and STORE_FLAG_VALUE permits. This is like
5891 the first case, but it works even when GET_MODE (x) is larger
5892 than HOST_WIDE_INT. */
5893 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5894 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5895 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5896 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5897 <= HOST_BITS_PER_WIDE_INT)
5898 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5899 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5900 return XEXP (XEXP (x, 0), 0);
5902 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5903 if (GET_CODE (XEXP (x, 0)) == SUBREG
5904 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5905 && subreg_lowpart_p (XEXP (x, 0))
5906 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5907 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5908 <= HOST_BITS_PER_WIDE_INT)
5909 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5910 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5911 return SUBREG_REG (XEXP (x, 0));
5915 /* If we reach here, we want to return a pair of shifts. The inner
5916 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5917 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5918 logical depending on the value of UNSIGNEDP.
5920 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5921 converted into an AND of a shift.
5923 We must check for the case where the left shift would have a negative
5924 count. This can happen in a case like (x >> 31) & 255 on machines
5925 that can't shift by a constant. On those machines, we would first
5926 combine the shift with the AND to produce a variable-position
5927 extraction. Then the constant of 31 would be substituted in to produce
5928 a such a position. */
5930 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5931 if (modewidth + len >= pos)
5932 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5934 simplify_shift_const (NULL_RTX, ASHIFT,
5937 modewidth - pos - len),
5940 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5941 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5942 simplify_shift_const (NULL_RTX, LSHIFTRT,
5945 ((HOST_WIDE_INT) 1 << len) - 1);
5947 /* Any other cases we can't handle. */
5950 /* If we couldn't do this for some reason, return the original
5952 if (GET_CODE (tem) == CLOBBER)
5958 /* X is a SET which contains an assignment of one object into
5959 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5960 or certain SUBREGS). If possible, convert it into a series of
5963 We half-heartedly support variable positions, but do not at all
5964 support variable lengths. */
5967 expand_field_assignment (rtx x)
5970 rtx pos; /* Always counts from low bit. */
5972 rtx mask, cleared, masked;
5973 enum machine_mode compute_mode;
5975 /* Loop until we find something we can't simplify. */
5978 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5979 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5981 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5982 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5983 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5985 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5986 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5988 inner = XEXP (SET_DEST (x), 0);
5989 len = INTVAL (XEXP (SET_DEST (x), 1));
5990 pos = XEXP (SET_DEST (x), 2);
5992 /* If the position is constant and spans the width of INNER,
5993 surround INNER with a USE to indicate this. */
5994 if (GET_CODE (pos) == CONST_INT
5995 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5996 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5998 if (BITS_BIG_ENDIAN)
6000 if (GET_CODE (pos) == CONST_INT)
6001 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6003 else if (GET_CODE (pos) == MINUS
6004 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6005 && (INTVAL (XEXP (pos, 1))
6006 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6007 /* If position is ADJUST - X, new position is X. */
6008 pos = XEXP (pos, 0);
6010 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6011 GEN_INT (GET_MODE_BITSIZE (
6018 /* A SUBREG between two modes that occupy the same numbers of words
6019 can be done by moving the SUBREG to the source. */
6020 else if (GET_CODE (SET_DEST (x)) == SUBREG
6021 /* We need SUBREGs to compute nonzero_bits properly. */
6022 && nonzero_sign_valid
6023 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6024 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6025 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6026 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6028 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6030 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6037 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6038 inner = SUBREG_REG (inner);
6040 compute_mode = GET_MODE (inner);
6042 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6043 if (! SCALAR_INT_MODE_P (compute_mode))
6045 enum machine_mode imode;
6047 /* Don't do anything for vector or complex integral types. */
6048 if (! FLOAT_MODE_P (compute_mode))
6051 /* Try to find an integral mode to pun with. */
6052 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6053 if (imode == BLKmode)
6056 compute_mode = imode;
6057 inner = gen_lowpart (imode, inner);
6060 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6061 if (len >= HOST_BITS_PER_WIDE_INT)
6064 /* Now compute the equivalent expression. Make a copy of INNER
6065 for the SET_DEST in case it is a MEM into which we will substitute;
6066 we don't want shared RTL in that case. */
6067 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6068 cleared = simplify_gen_binary (AND, compute_mode,
6069 simplify_gen_unary (NOT, compute_mode,
6070 simplify_gen_binary (ASHIFT,
6075 masked = simplify_gen_binary (ASHIFT, compute_mode,
6076 simplify_gen_binary (
6078 gen_lowpart (compute_mode, SET_SRC (x)),
6082 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6083 simplify_gen_binary (IOR, compute_mode,
6090 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6091 it is an RTX that represents a variable starting position; otherwise,
6092 POS is the (constant) starting bit position (counted from the LSB).
6094 INNER may be a USE. This will occur when we started with a bitfield
6095 that went outside the boundary of the object in memory, which is
6096 allowed on most machines. To isolate this case, we produce a USE
6097 whose mode is wide enough and surround the MEM with it. The only
6098 code that understands the USE is this routine. If it is not removed,
6099 it will cause the resulting insn not to match.
6101 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6104 IN_DEST is nonzero if this is a reference in the destination of a
6105 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6106 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6109 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6110 ZERO_EXTRACT should be built even for bits starting at bit 0.
6112 MODE is the desired mode of the result (if IN_DEST == 0).
6114 The result is an RTX for the extraction or NULL_RTX if the target
6118 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6119 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6120 int in_dest, int in_compare)
6122 /* This mode describes the size of the storage area
6123 to fetch the overall value from. Within that, we
6124 ignore the POS lowest bits, etc. */
6125 enum machine_mode is_mode = GET_MODE (inner);
6126 enum machine_mode inner_mode;
6127 enum machine_mode wanted_inner_mode = byte_mode;
6128 enum machine_mode wanted_inner_reg_mode = word_mode;
6129 enum machine_mode pos_mode = word_mode;
6130 enum machine_mode extraction_mode = word_mode;
6131 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6134 rtx orig_pos_rtx = pos_rtx;
6135 HOST_WIDE_INT orig_pos;
6137 /* Get some information about INNER and get the innermost object. */
6138 if (GET_CODE (inner) == USE)
6139 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6140 /* We don't need to adjust the position because we set up the USE
6141 to pretend that it was a full-word object. */
6142 spans_byte = 1, inner = XEXP (inner, 0);
6143 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6145 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6146 consider just the QI as the memory to extract from.
6147 The subreg adds or removes high bits; its mode is
6148 irrelevant to the meaning of this extraction,
6149 since POS and LEN count from the lsb. */
6150 if (MEM_P (SUBREG_REG (inner)))
6151 is_mode = GET_MODE (SUBREG_REG (inner));
6152 inner = SUBREG_REG (inner);
6154 else if (GET_CODE (inner) == ASHIFT
6155 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6156 && pos_rtx == 0 && pos == 0
6157 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6159 /* We're extracting the least significant bits of an rtx
6160 (ashift X (const_int C)), where LEN > C. Extract the
6161 least significant (LEN - C) bits of X, giving an rtx
6162 whose mode is MODE, then shift it left C times. */
6163 new = make_extraction (mode, XEXP (inner, 0),
6164 0, 0, len - INTVAL (XEXP (inner, 1)),
6165 unsignedp, in_dest, in_compare);
6167 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6170 inner_mode = GET_MODE (inner);
6172 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6173 pos = INTVAL (pos_rtx), pos_rtx = 0;
6175 /* See if this can be done without an extraction. We never can if the
6176 width of the field is not the same as that of some integer mode. For
6177 registers, we can only avoid the extraction if the position is at the
6178 low-order bit and this is either not in the destination or we have the
6179 appropriate STRICT_LOW_PART operation available.
6181 For MEM, we can avoid an extract if the field starts on an appropriate
6182 boundary and we can change the mode of the memory reference. However,
6183 we cannot directly access the MEM if we have a USE and the underlying
6184 MEM is not TMODE. This combination means that MEM was being used in a
6185 context where bits outside its mode were being referenced; that is only
6186 valid in bit-field insns. */
6188 if (tmode != BLKmode
6189 && ! (spans_byte && inner_mode != tmode)
6190 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6194 && have_insn_for (STRICT_LOW_PART, tmode))))
6195 || (MEM_P (inner) && pos_rtx == 0
6197 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6198 : BITS_PER_UNIT)) == 0
6199 /* We can't do this if we are widening INNER_MODE (it
6200 may not be aligned, for one thing). */
6201 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6202 && (inner_mode == tmode
6203 || (! mode_dependent_address_p (XEXP (inner, 0))
6204 && ! MEM_VOLATILE_P (inner))))))
6206 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6207 field. If the original and current mode are the same, we need not
6208 adjust the offset. Otherwise, we do if bytes big endian.
6210 If INNER is not a MEM, get a piece consisting of just the field
6211 of interest (in this case POS % BITS_PER_WORD must be 0). */
6215 HOST_WIDE_INT offset;
6217 /* POS counts from lsb, but make OFFSET count in memory order. */
6218 if (BYTES_BIG_ENDIAN)
6219 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6221 offset = pos / BITS_PER_UNIT;
6223 new = adjust_address_nv (inner, tmode, offset);
6225 else if (REG_P (inner))
6227 if (tmode != inner_mode)
6229 /* We can't call gen_lowpart in a DEST since we
6230 always want a SUBREG (see below) and it would sometimes
6231 return a new hard register. */
6234 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6236 if (WORDS_BIG_ENDIAN
6237 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6238 final_word = ((GET_MODE_SIZE (inner_mode)
6239 - GET_MODE_SIZE (tmode))
6240 / UNITS_PER_WORD) - final_word;
6242 final_word *= UNITS_PER_WORD;
6243 if (BYTES_BIG_ENDIAN &&
6244 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6245 final_word += (GET_MODE_SIZE (inner_mode)
6246 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6248 /* Avoid creating invalid subregs, for example when
6249 simplifying (x>>32)&255. */
6250 if (final_word >= GET_MODE_SIZE (inner_mode))
6253 new = gen_rtx_SUBREG (tmode, inner, final_word);
6256 new = gen_lowpart (tmode, inner);
6262 new = force_to_mode (inner, tmode,
6263 len >= HOST_BITS_PER_WIDE_INT
6264 ? ~(unsigned HOST_WIDE_INT) 0
6265 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6268 /* If this extraction is going into the destination of a SET,
6269 make a STRICT_LOW_PART unless we made a MEM. */
6272 return (MEM_P (new) ? new
6273 : (GET_CODE (new) != SUBREG
6274 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6275 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6280 if (GET_CODE (new) == CONST_INT)
6281 return gen_int_mode (INTVAL (new), mode);
6283 /* If we know that no extraneous bits are set, and that the high
6284 bit is not set, convert the extraction to the cheaper of
6285 sign and zero extension, that are equivalent in these cases. */
6286 if (flag_expensive_optimizations
6287 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6288 && ((nonzero_bits (new, tmode)
6289 & ~(((unsigned HOST_WIDE_INT)
6290 GET_MODE_MASK (tmode))
6294 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6295 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6297 /* Prefer ZERO_EXTENSION, since it gives more information to
6299 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6304 /* Otherwise, sign- or zero-extend unless we already are in the
6307 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6311 /* Unless this is a COMPARE or we have a funny memory reference,
6312 don't do anything with zero-extending field extracts starting at
6313 the low-order bit since they are simple AND operations. */
6314 if (pos_rtx == 0 && pos == 0 && ! in_dest
6315 && ! in_compare && ! spans_byte && unsignedp)
6318 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6319 we would be spanning bytes or if the position is not a constant and the
6320 length is not 1. In all other cases, we would only be going outside
6321 our object in cases when an original shift would have been
6323 if (! spans_byte && MEM_P (inner)
6324 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6325 || (pos_rtx != 0 && len != 1)))
6328 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6329 and the mode for the result. */
6330 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6332 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6333 pos_mode = mode_for_extraction (EP_insv, 2);
6334 extraction_mode = mode_for_extraction (EP_insv, 3);
6337 if (! in_dest && unsignedp
6338 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6340 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6341 pos_mode = mode_for_extraction (EP_extzv, 3);
6342 extraction_mode = mode_for_extraction (EP_extzv, 0);
6345 if (! in_dest && ! unsignedp
6346 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6348 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6349 pos_mode = mode_for_extraction (EP_extv, 3);
6350 extraction_mode = mode_for_extraction (EP_extv, 0);
6353 /* Never narrow an object, since that might not be safe. */
6355 if (mode != VOIDmode
6356 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6357 extraction_mode = mode;
6359 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6360 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6361 pos_mode = GET_MODE (pos_rtx);
6363 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6364 if we have to change the mode of memory and cannot, the desired mode is
6367 wanted_inner_mode = wanted_inner_reg_mode;
6368 else if (inner_mode != wanted_inner_mode
6369 && (mode_dependent_address_p (XEXP (inner, 0))
6370 || MEM_VOLATILE_P (inner)))
6371 wanted_inner_mode = extraction_mode;
6375 if (BITS_BIG_ENDIAN)
6377 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6378 BITS_BIG_ENDIAN style. If position is constant, compute new
6379 position. Otherwise, build subtraction.
6380 Note that POS is relative to the mode of the original argument.
6381 If it's a MEM we need to recompute POS relative to that.
6382 However, if we're extracting from (or inserting into) a register,
6383 we want to recompute POS relative to wanted_inner_mode. */
6384 int width = (MEM_P (inner)
6385 ? GET_MODE_BITSIZE (is_mode)
6386 : GET_MODE_BITSIZE (wanted_inner_mode));
6389 pos = width - len - pos;
6392 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6393 /* POS may be less than 0 now, but we check for that below.
6394 Note that it can only be less than 0 if !MEM_P (inner). */
6397 /* If INNER has a wider mode, make it smaller. If this is a constant
6398 extract, try to adjust the byte to point to the byte containing
6400 if (wanted_inner_mode != VOIDmode
6401 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6403 && (inner_mode == wanted_inner_mode
6404 || (! mode_dependent_address_p (XEXP (inner, 0))
6405 && ! MEM_VOLATILE_P (inner))))))
6409 /* The computations below will be correct if the machine is big
6410 endian in both bits and bytes or little endian in bits and bytes.
6411 If it is mixed, we must adjust. */
6413 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6414 adjust OFFSET to compensate. */
6415 if (BYTES_BIG_ENDIAN
6417 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6418 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6420 /* If this is a constant position, we can move to the desired byte. */
6423 offset += pos / BITS_PER_UNIT;
6424 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6427 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6429 && is_mode != wanted_inner_mode)
6430 offset = (GET_MODE_SIZE (is_mode)
6431 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6433 if (offset != 0 || inner_mode != wanted_inner_mode)
6434 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6437 /* If INNER is not memory, we can always get it into the proper mode. If we
6438 are changing its mode, POS must be a constant and smaller than the size
6440 else if (!MEM_P (inner))
6442 if (GET_MODE (inner) != wanted_inner_mode
6444 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6447 inner = force_to_mode (inner, wanted_inner_mode,
6449 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6450 ? ~(unsigned HOST_WIDE_INT) 0
6451 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6456 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6457 have to zero extend. Otherwise, we can just use a SUBREG. */
6459 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6461 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6463 /* If we know that no extraneous bits are set, and that the high
6464 bit is not set, convert extraction to cheaper one - either
6465 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6467 if (flag_expensive_optimizations
6468 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6469 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6470 & ~(((unsigned HOST_WIDE_INT)
6471 GET_MODE_MASK (GET_MODE (pos_rtx)))
6475 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6477 /* Prefer ZERO_EXTENSION, since it gives more information to
6479 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6484 else if (pos_rtx != 0
6485 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6486 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6488 /* Make POS_RTX unless we already have it and it is correct. If we don't
6489 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6491 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6492 pos_rtx = orig_pos_rtx;
6494 else if (pos_rtx == 0)
6495 pos_rtx = GEN_INT (pos);
6497 /* Make the required operation. See if we can use existing rtx. */
6498 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6499 extraction_mode, inner, GEN_INT (len), pos_rtx);
6501 new = gen_lowpart (mode, new);
6506 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6507 with any other operations in X. Return X without that shift if so. */
6510 extract_left_shift (rtx x, int count)
6512 enum rtx_code code = GET_CODE (x);
6513 enum machine_mode mode = GET_MODE (x);
6519 /* This is the shift itself. If it is wide enough, we will return
6520 either the value being shifted if the shift count is equal to
6521 COUNT or a shift for the difference. */
6522 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6523 && INTVAL (XEXP (x, 1)) >= count)
6524 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6525 INTVAL (XEXP (x, 1)) - count);
6529 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6530 return simplify_gen_unary (code, mode, tem, mode);
6534 case PLUS: case IOR: case XOR: case AND:
6535 /* If we can safely shift this constant and we find the inner shift,
6536 make a new operation. */
6537 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6538 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6539 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6540 return simplify_gen_binary (code, mode, tem,
6541 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6552 /* Look at the expression rooted at X. Look for expressions
6553 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6554 Form these expressions.
6556 Return the new rtx, usually just X.
6558 Also, for machines like the VAX that don't have logical shift insns,
6559 try to convert logical to arithmetic shift operations in cases where
6560 they are equivalent. This undoes the canonicalizations to logical
6561 shifts done elsewhere.
6563 We try, as much as possible, to re-use rtl expressions to save memory.
6565 IN_CODE says what kind of expression we are processing. Normally, it is
6566 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6567 being kludges), it is MEM. When processing the arguments of a comparison
6568 or a COMPARE against zero, it is COMPARE. */
6571 make_compound_operation (rtx x, enum rtx_code in_code)
6573 enum rtx_code code = GET_CODE (x);
6574 enum machine_mode mode = GET_MODE (x);
6575 int mode_width = GET_MODE_BITSIZE (mode);
6577 enum rtx_code next_code;
6583 /* Select the code to be used in recursive calls. Once we are inside an
6584 address, we stay there. If we have a comparison, set to COMPARE,
6585 but once inside, go back to our default of SET. */
6587 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6588 : ((code == COMPARE || COMPARISON_P (x))
6589 && XEXP (x, 1) == const0_rtx) ? COMPARE
6590 : in_code == COMPARE ? SET : in_code);
6592 /* Process depending on the code of this operation. If NEW is set
6593 nonzero, it will be returned. */
6598 /* Convert shifts by constants into multiplications if inside
6600 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6601 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6602 && INTVAL (XEXP (x, 1)) >= 0)
6604 new = make_compound_operation (XEXP (x, 0), next_code);
6605 new = gen_rtx_MULT (mode, new,
6606 GEN_INT ((HOST_WIDE_INT) 1
6607 << INTVAL (XEXP (x, 1))));
6612 /* If the second operand is not a constant, we can't do anything
6614 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6617 /* If the constant is a power of two minus one and the first operand
6618 is a logical right shift, make an extraction. */
6619 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6620 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6622 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6623 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6624 0, in_code == COMPARE);
6627 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6628 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6629 && subreg_lowpart_p (XEXP (x, 0))
6630 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6631 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6633 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6635 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6636 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6637 0, in_code == COMPARE);
6639 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6640 else if ((GET_CODE (XEXP (x, 0)) == XOR
6641 || GET_CODE (XEXP (x, 0)) == IOR)
6642 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6643 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6644 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6646 /* Apply the distributive law, and then try to make extractions. */
6647 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6648 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6650 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6652 new = make_compound_operation (new, in_code);
6655 /* If we are have (and (rotate X C) M) and C is larger than the number
6656 of bits in M, this is an extraction. */
6658 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6659 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6660 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6661 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6663 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6664 new = make_extraction (mode, new,
6665 (GET_MODE_BITSIZE (mode)
6666 - INTVAL (XEXP (XEXP (x, 0), 1))),
6667 NULL_RTX, i, 1, 0, in_code == COMPARE);
6670 /* On machines without logical shifts, if the operand of the AND is
6671 a logical shift and our mask turns off all the propagated sign
6672 bits, we can replace the logical shift with an arithmetic shift. */
6673 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6674 && !have_insn_for (LSHIFTRT, mode)
6675 && have_insn_for (ASHIFTRT, mode)
6676 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6677 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6678 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6679 && mode_width <= HOST_BITS_PER_WIDE_INT)
6681 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6683 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6684 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6686 gen_rtx_ASHIFTRT (mode,
6687 make_compound_operation
6688 (XEXP (XEXP (x, 0), 0), next_code),
6689 XEXP (XEXP (x, 0), 1)));
6692 /* If the constant is one less than a power of two, this might be
6693 representable by an extraction even if no shift is present.
6694 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6695 we are in a COMPARE. */
6696 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6697 new = make_extraction (mode,
6698 make_compound_operation (XEXP (x, 0),
6700 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6702 /* If we are in a comparison and this is an AND with a power of two,
6703 convert this into the appropriate bit extract. */
6704 else if (in_code == COMPARE
6705 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6706 new = make_extraction (mode,
6707 make_compound_operation (XEXP (x, 0),
6709 i, NULL_RTX, 1, 1, 0, 1);
6714 /* If the sign bit is known to be zero, replace this with an
6715 arithmetic shift. */
6716 if (have_insn_for (ASHIFTRT, mode)
6717 && ! have_insn_for (LSHIFTRT, mode)
6718 && mode_width <= HOST_BITS_PER_WIDE_INT
6719 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6721 new = gen_rtx_ASHIFTRT (mode,
6722 make_compound_operation (XEXP (x, 0),
6728 /* ... fall through ... */
6734 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6735 this is a SIGN_EXTRACT. */
6736 if (GET_CODE (rhs) == CONST_INT
6737 && GET_CODE (lhs) == ASHIFT
6738 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6739 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6741 new = make_compound_operation (XEXP (lhs, 0), next_code);
6742 new = make_extraction (mode, new,
6743 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6744 NULL_RTX, mode_width - INTVAL (rhs),
6745 code == LSHIFTRT, 0, in_code == COMPARE);
6749 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6750 If so, try to merge the shifts into a SIGN_EXTEND. We could
6751 also do this for some cases of SIGN_EXTRACT, but it doesn't
6752 seem worth the effort; the case checked for occurs on Alpha. */
6755 && ! (GET_CODE (lhs) == SUBREG
6756 && (OBJECT_P (SUBREG_REG (lhs))))
6757 && GET_CODE (rhs) == CONST_INT
6758 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6759 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6760 new = make_extraction (mode, make_compound_operation (new, next_code),
6761 0, NULL_RTX, mode_width - INTVAL (rhs),
6762 code == LSHIFTRT, 0, in_code == COMPARE);
6767 /* Call ourselves recursively on the inner expression. If we are
6768 narrowing the object and it has a different RTL code from
6769 what it originally did, do this SUBREG as a force_to_mode. */
6771 tem = make_compound_operation (SUBREG_REG (x), in_code);
6772 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6773 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6774 && subreg_lowpart_p (x))
6776 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6779 /* If we have something other than a SUBREG, we might have
6780 done an expansion, so rerun ourselves. */
6781 if (GET_CODE (newer) != SUBREG)
6782 newer = make_compound_operation (newer, in_code);
6787 /* If this is a paradoxical subreg, and the new code is a sign or
6788 zero extension, omit the subreg and widen the extension. If it
6789 is a regular subreg, we can still get rid of the subreg by not
6790 widening so much, or in fact removing the extension entirely. */
6791 if ((GET_CODE (tem) == SIGN_EXTEND
6792 || GET_CODE (tem) == ZERO_EXTEND)
6793 && subreg_lowpart_p (x))
6795 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6796 || (GET_MODE_SIZE (mode) >
6797 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6799 if (! SCALAR_INT_MODE_P (mode))
6801 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6804 tem = gen_lowpart (mode, XEXP (tem, 0));
6815 x = gen_lowpart (mode, new);
6816 code = GET_CODE (x);
6819 /* Now recursively process each operand of this operation. */
6820 fmt = GET_RTX_FORMAT (code);
6821 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6824 new = make_compound_operation (XEXP (x, i), next_code);
6825 SUBST (XEXP (x, i), new);
6831 /* Given M see if it is a value that would select a field of bits
6832 within an item, but not the entire word. Return -1 if not.
6833 Otherwise, return the starting position of the field, where 0 is the
6836 *PLEN is set to the length of the field. */
6839 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6841 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6842 int pos = exact_log2 (m & -m);
6846 /* Now shift off the low-order zero bits and see if we have a
6847 power of two minus 1. */
6848 len = exact_log2 ((m >> pos) + 1);
6857 /* See if X can be simplified knowing that we will only refer to it in
6858 MODE and will only refer to those bits that are nonzero in MASK.
6859 If other bits are being computed or if masking operations are done
6860 that select a superset of the bits in MASK, they can sometimes be
6863 Return a possibly simplified expression, but always convert X to
6864 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6866 Also, if REG is nonzero and X is a register equal in value to REG,
6869 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6870 are all off in X. This is used when X will be complemented, by either
6871 NOT, NEG, or XOR. */
6874 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6875 rtx reg, int just_select)
6877 enum rtx_code code = GET_CODE (x);
6878 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6879 enum machine_mode op_mode;
6880 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6883 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6884 code below will do the wrong thing since the mode of such an
6885 expression is VOIDmode.
6887 Also do nothing if X is a CLOBBER; this can happen if X was
6888 the return value from a call to gen_lowpart. */
6889 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6892 /* We want to perform the operation is its present mode unless we know
6893 that the operation is valid in MODE, in which case we do the operation
6895 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6896 && have_insn_for (code, mode))
6897 ? mode : GET_MODE (x));
6899 /* It is not valid to do a right-shift in a narrower mode
6900 than the one it came in with. */
6901 if ((code == LSHIFTRT || code == ASHIFTRT)
6902 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6903 op_mode = GET_MODE (x);
6905 /* Truncate MASK to fit OP_MODE. */
6907 mask &= GET_MODE_MASK (op_mode);
6909 /* When we have an arithmetic operation, or a shift whose count we
6910 do not know, we need to assume that all bits up to the highest-order
6911 bit in MASK will be needed. This is how we form such a mask. */
6912 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6913 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6915 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6918 /* Determine what bits of X are guaranteed to be (non)zero. */
6919 nonzero = nonzero_bits (x, mode);
6921 /* If none of the bits in X are needed, return a zero. */
6922 if (! just_select && (nonzero & mask) == 0)
6925 /* If X is a CONST_INT, return a new one. Do this here since the
6926 test below will fail. */
6927 if (GET_CODE (x) == CONST_INT)
6929 if (SCALAR_INT_MODE_P (mode))
6930 return gen_int_mode (INTVAL (x) & mask, mode);
6933 x = GEN_INT (INTVAL (x) & mask);
6934 return gen_lowpart_common (mode, x);
6938 /* If X is narrower than MODE and we want all the bits in X's mode, just
6939 get X in the proper mode. */
6940 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6941 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6942 return gen_lowpart (mode, x);
6947 /* If X is a (clobber (const_int)), return it since we know we are
6948 generating something that won't match. */
6952 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6953 spanned the boundary of the MEM. If we are now masking so it is
6954 within that boundary, we don't need the USE any more. */
6955 if (! BITS_BIG_ENDIAN
6956 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6957 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6964 x = expand_compound_operation (x);
6965 if (GET_CODE (x) != code)
6966 return force_to_mode (x, mode, mask, reg, next_select);
6970 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6971 || rtx_equal_p (reg, get_last_value (x))))
6976 if (subreg_lowpart_p (x)
6977 /* We can ignore the effect of this SUBREG if it narrows the mode or
6978 if the constant masks to zero all the bits the mode doesn't
6980 && ((GET_MODE_SIZE (GET_MODE (x))
6981 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6983 & GET_MODE_MASK (GET_MODE (x))
6984 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6985 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6989 /* If this is an AND with a constant, convert it into an AND
6990 whose constant is the AND of that constant with MASK. If it
6991 remains an AND of MASK, delete it since it is redundant. */
6993 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6995 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6996 mask & INTVAL (XEXP (x, 1)));
6998 /* If X is still an AND, see if it is an AND with a mask that
6999 is just some low-order bits. If so, and it is MASK, we don't
7002 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7003 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7007 /* If it remains an AND, try making another AND with the bits
7008 in the mode mask that aren't in MASK turned on. If the
7009 constant in the AND is wide enough, this might make a
7010 cheaper constant. */
7012 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7013 && GET_MODE_MASK (GET_MODE (x)) != mask
7014 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7016 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7017 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7018 int width = GET_MODE_BITSIZE (GET_MODE (x));
7021 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7022 number, sign extend it. */
7023 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7024 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7025 cval |= (HOST_WIDE_INT) -1 << width;
7027 y = simplify_gen_binary (AND, GET_MODE (x),
7028 XEXP (x, 0), GEN_INT (cval));
7029 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7039 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7040 low-order bits (as in an alignment operation) and FOO is already
7041 aligned to that boundary, mask C1 to that boundary as well.
7042 This may eliminate that PLUS and, later, the AND. */
7045 unsigned int width = GET_MODE_BITSIZE (mode);
7046 unsigned HOST_WIDE_INT smask = mask;
7048 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7049 number, sign extend it. */
7051 if (width < HOST_BITS_PER_WIDE_INT
7052 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7053 smask |= (HOST_WIDE_INT) -1 << width;
7055 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7056 && exact_log2 (- smask) >= 0
7057 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7058 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7059 return force_to_mode (plus_constant (XEXP (x, 0),
7060 (INTVAL (XEXP (x, 1)) & smask)),
7061 mode, smask, reg, next_select);
7064 /* ... fall through ... */
7067 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7068 most significant bit in MASK since carries from those bits will
7069 affect the bits we are interested in. */
7074 /* If X is (minus C Y) where C's least set bit is larger than any bit
7075 in the mask, then we may replace with (neg Y). */
7076 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7077 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7078 & -INTVAL (XEXP (x, 0))))
7081 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7083 return force_to_mode (x, mode, mask, reg, next_select);
7086 /* Similarly, if C contains every bit in the fuller_mask, then we may
7087 replace with (not Y). */
7088 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7089 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7090 == INTVAL (XEXP (x, 0))))
7092 x = simplify_gen_unary (NOT, GET_MODE (x),
7093 XEXP (x, 1), GET_MODE (x));
7094 return force_to_mode (x, mode, mask, reg, next_select);
7102 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7103 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7104 operation which may be a bitfield extraction. Ensure that the
7105 constant we form is not wider than the mode of X. */
7107 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7108 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7109 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7110 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7111 && GET_CODE (XEXP (x, 1)) == CONST_INT
7112 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7113 + floor_log2 (INTVAL (XEXP (x, 1))))
7114 < GET_MODE_BITSIZE (GET_MODE (x)))
7115 && (INTVAL (XEXP (x, 1))
7116 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7118 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7119 << INTVAL (XEXP (XEXP (x, 0), 1)));
7120 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7121 XEXP (XEXP (x, 0), 0), temp);
7122 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7123 XEXP (XEXP (x, 0), 1));
7124 return force_to_mode (x, mode, mask, reg, next_select);
7128 /* For most binary operations, just propagate into the operation and
7129 change the mode if we have an operation of that mode. */
7131 op0 = gen_lowpart (op_mode,
7132 force_to_mode (XEXP (x, 0), mode, mask,
7134 op1 = gen_lowpart (op_mode,
7135 force_to_mode (XEXP (x, 1), mode, mask,
7138 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7139 x = simplify_gen_binary (code, op_mode, op0, op1);
7143 /* For left shifts, do the same, but just for the first operand.
7144 However, we cannot do anything with shifts where we cannot
7145 guarantee that the counts are smaller than the size of the mode
7146 because such a count will have a different meaning in a
7149 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7150 && INTVAL (XEXP (x, 1)) >= 0
7151 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7152 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7153 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7154 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7157 /* If the shift count is a constant and we can do arithmetic in
7158 the mode of the shift, refine which bits we need. Otherwise, use the
7159 conservative form of the mask. */
7160 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7161 && INTVAL (XEXP (x, 1)) >= 0
7162 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7163 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7164 mask >>= INTVAL (XEXP (x, 1));
7168 op0 = gen_lowpart (op_mode,
7169 force_to_mode (XEXP (x, 0), op_mode,
7170 mask, reg, next_select));
7172 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7173 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7177 /* Here we can only do something if the shift count is a constant,
7178 this shift constant is valid for the host, and we can do arithmetic
7181 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7182 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7183 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7185 rtx inner = XEXP (x, 0);
7186 unsigned HOST_WIDE_INT inner_mask;
7188 /* Select the mask of the bits we need for the shift operand. */
7189 inner_mask = mask << INTVAL (XEXP (x, 1));
7191 /* We can only change the mode of the shift if we can do arithmetic
7192 in the mode of the shift and INNER_MASK is no wider than the
7193 width of X's mode. */
7194 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7195 op_mode = GET_MODE (x);
7197 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7199 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7200 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7203 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7204 shift and AND produces only copies of the sign bit (C2 is one less
7205 than a power of two), we can do this with just a shift. */
7207 if (GET_CODE (x) == LSHIFTRT
7208 && GET_CODE (XEXP (x, 1)) == CONST_INT
7209 /* The shift puts one of the sign bit copies in the least significant
7211 && ((INTVAL (XEXP (x, 1))
7212 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7213 >= GET_MODE_BITSIZE (GET_MODE (x)))
7214 && exact_log2 (mask + 1) >= 0
7215 /* Number of bits left after the shift must be more than the mask
7217 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7218 <= GET_MODE_BITSIZE (GET_MODE (x)))
7219 /* Must be more sign bit copies than the mask needs. */
7220 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7221 >= exact_log2 (mask + 1)))
7222 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7223 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7224 - exact_log2 (mask + 1)));
7229 /* If we are just looking for the sign bit, we don't need this shift at
7230 all, even if it has a variable count. */
7231 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7232 && (mask == ((unsigned HOST_WIDE_INT) 1
7233 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7234 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7236 /* If this is a shift by a constant, get a mask that contains those bits
7237 that are not copies of the sign bit. We then have two cases: If
7238 MASK only includes those bits, this can be a logical shift, which may
7239 allow simplifications. If MASK is a single-bit field not within
7240 those bits, we are requesting a copy of the sign bit and hence can
7241 shift the sign bit to the appropriate location. */
7243 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7244 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7248 /* If the considered data is wider than HOST_WIDE_INT, we can't
7249 represent a mask for all its bits in a single scalar.
7250 But we only care about the lower bits, so calculate these. */
7252 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7254 nonzero = ~(HOST_WIDE_INT) 0;
7256 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7257 is the number of bits a full-width mask would have set.
7258 We need only shift if these are fewer than nonzero can
7259 hold. If not, we must keep all bits set in nonzero. */
7261 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7262 < HOST_BITS_PER_WIDE_INT)
7263 nonzero >>= INTVAL (XEXP (x, 1))
7264 + HOST_BITS_PER_WIDE_INT
7265 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7269 nonzero = GET_MODE_MASK (GET_MODE (x));
7270 nonzero >>= INTVAL (XEXP (x, 1));
7273 if ((mask & ~nonzero) == 0
7274 || (i = exact_log2 (mask)) >= 0)
7276 x = simplify_shift_const
7277 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7278 i < 0 ? INTVAL (XEXP (x, 1))
7279 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7281 if (GET_CODE (x) != ASHIFTRT)
7282 return force_to_mode (x, mode, mask, reg, next_select);
7286 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7287 even if the shift count isn't a constant. */
7289 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7290 XEXP (x, 0), XEXP (x, 1));
7294 /* If this is a zero- or sign-extension operation that just affects bits
7295 we don't care about, remove it. Be sure the call above returned
7296 something that is still a shift. */
7298 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7299 && GET_CODE (XEXP (x, 1)) == CONST_INT
7300 && INTVAL (XEXP (x, 1)) >= 0
7301 && (INTVAL (XEXP (x, 1))
7302 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7303 && GET_CODE (XEXP (x, 0)) == ASHIFT
7304 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7305 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7312 /* If the shift count is constant and we can do computations
7313 in the mode of X, compute where the bits we care about are.
7314 Otherwise, we can't do anything. Don't change the mode of
7315 the shift or propagate MODE into the shift, though. */
7316 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7317 && INTVAL (XEXP (x, 1)) >= 0)
7319 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7320 GET_MODE (x), GEN_INT (mask),
7322 if (temp && GET_CODE (temp) == CONST_INT)
7324 force_to_mode (XEXP (x, 0), GET_MODE (x),
7325 INTVAL (temp), reg, next_select));
7330 /* If we just want the low-order bit, the NEG isn't needed since it
7331 won't change the low-order bit. */
7333 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7335 /* We need any bits less significant than the most significant bit in
7336 MASK since carries from those bits will affect the bits we are
7342 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7343 same as the XOR case above. Ensure that the constant we form is not
7344 wider than the mode of X. */
7346 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7347 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7348 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7349 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7350 < GET_MODE_BITSIZE (GET_MODE (x)))
7351 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7353 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7355 temp = simplify_gen_binary (XOR, GET_MODE (x),
7356 XEXP (XEXP (x, 0), 0), temp);
7357 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7358 temp, XEXP (XEXP (x, 0), 1));
7360 return force_to_mode (x, mode, mask, reg, next_select);
7363 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7364 use the full mask inside the NOT. */
7368 op0 = gen_lowpart (op_mode,
7369 force_to_mode (XEXP (x, 0), mode, mask,
7371 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7372 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7376 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7377 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7378 which is equal to STORE_FLAG_VALUE. */
7379 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7380 && GET_MODE (XEXP (x, 0)) == mode
7381 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7382 && (nonzero_bits (XEXP (x, 0), mode)
7383 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7384 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7389 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7390 written in a narrower mode. We play it safe and do not do so. */
7393 gen_lowpart (GET_MODE (x),
7394 force_to_mode (XEXP (x, 1), mode,
7395 mask, reg, next_select)));
7397 gen_lowpart (GET_MODE (x),
7398 force_to_mode (XEXP (x, 2), mode,
7399 mask, reg, next_select)));
7406 /* Ensure we return a value of the proper mode. */
7407 return gen_lowpart (mode, x);
7410 /* Return nonzero if X is an expression that has one of two values depending on
7411 whether some other value is zero or nonzero. In that case, we return the
7412 value that is being tested, *PTRUE is set to the value if the rtx being
7413 returned has a nonzero value, and *PFALSE is set to the other alternative.
7415 If we return zero, we set *PTRUE and *PFALSE to X. */
7418 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7420 enum machine_mode mode = GET_MODE (x);
7421 enum rtx_code code = GET_CODE (x);
7422 rtx cond0, cond1, true0, true1, false0, false1;
7423 unsigned HOST_WIDE_INT nz;
7425 /* If we are comparing a value against zero, we are done. */
7426 if ((code == NE || code == EQ)
7427 && XEXP (x, 1) == const0_rtx)
7429 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7430 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7434 /* If this is a unary operation whose operand has one of two values, apply
7435 our opcode to compute those values. */
7436 else if (UNARY_P (x)
7437 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7439 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7440 *pfalse = simplify_gen_unary (code, mode, false0,
7441 GET_MODE (XEXP (x, 0)));
7445 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7446 make can't possibly match and would suppress other optimizations. */
7447 else if (code == COMPARE)
7450 /* If this is a binary operation, see if either side has only one of two
7451 values. If either one does or if both do and they are conditional on
7452 the same value, compute the new true and false values. */
7453 else if (BINARY_P (x))
7455 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7456 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7458 if ((cond0 != 0 || cond1 != 0)
7459 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7461 /* If if_then_else_cond returned zero, then true/false are the
7462 same rtl. We must copy one of them to prevent invalid rtl
7465 true0 = copy_rtx (true0);
7466 else if (cond1 == 0)
7467 true1 = copy_rtx (true1);
7469 if (COMPARISON_P (x))
7471 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7473 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7478 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7479 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7482 return cond0 ? cond0 : cond1;
7485 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7486 operands is zero when the other is nonzero, and vice-versa,
7487 and STORE_FLAG_VALUE is 1 or -1. */
7489 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7490 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7492 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7494 rtx op0 = XEXP (XEXP (x, 0), 1);
7495 rtx op1 = XEXP (XEXP (x, 1), 1);
7497 cond0 = XEXP (XEXP (x, 0), 0);
7498 cond1 = XEXP (XEXP (x, 1), 0);
7500 if (COMPARISON_P (cond0)
7501 && COMPARISON_P (cond1)
7502 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7503 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7504 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7505 || ((swap_condition (GET_CODE (cond0))
7506 == combine_reversed_comparison_code (cond1))
7507 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7508 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7509 && ! side_effects_p (x))
7511 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7512 *pfalse = simplify_gen_binary (MULT, mode,
7514 ? simplify_gen_unary (NEG, mode,
7522 /* Similarly for MULT, AND and UMIN, except that for these the result
7524 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7525 && (code == MULT || code == AND || code == UMIN)
7526 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7528 cond0 = XEXP (XEXP (x, 0), 0);
7529 cond1 = XEXP (XEXP (x, 1), 0);
7531 if (COMPARISON_P (cond0)
7532 && COMPARISON_P (cond1)
7533 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7534 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7535 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7536 || ((swap_condition (GET_CODE (cond0))
7537 == combine_reversed_comparison_code (cond1))
7538 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7539 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7540 && ! side_effects_p (x))
7542 *ptrue = *pfalse = const0_rtx;
7548 else if (code == IF_THEN_ELSE)
7550 /* If we have IF_THEN_ELSE already, extract the condition and
7551 canonicalize it if it is NE or EQ. */
7552 cond0 = XEXP (x, 0);
7553 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7554 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7555 return XEXP (cond0, 0);
7556 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7558 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7559 return XEXP (cond0, 0);
7565 /* If X is a SUBREG, we can narrow both the true and false values
7566 if the inner expression, if there is a condition. */
7567 else if (code == SUBREG
7568 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7571 true0 = simplify_gen_subreg (mode, true0,
7572 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7573 false0 = simplify_gen_subreg (mode, false0,
7574 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7575 if (true0 && false0)
7583 /* If X is a constant, this isn't special and will cause confusions
7584 if we treat it as such. Likewise if it is equivalent to a constant. */
7585 else if (CONSTANT_P (x)
7586 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7589 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7590 will be least confusing to the rest of the compiler. */
7591 else if (mode == BImode)
7593 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7597 /* If X is known to be either 0 or -1, those are the true and
7598 false values when testing X. */
7599 else if (x == constm1_rtx || x == const0_rtx
7600 || (mode != VOIDmode
7601 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7603 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7607 /* Likewise for 0 or a single bit. */
7608 else if (SCALAR_INT_MODE_P (mode)
7609 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7610 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7612 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7616 /* Otherwise fail; show no condition with true and false values the same. */
7617 *ptrue = *pfalse = x;
7621 /* Return the value of expression X given the fact that condition COND
7622 is known to be true when applied to REG as its first operand and VAL
7623 as its second. X is known to not be shared and so can be modified in
7626 We only handle the simplest cases, and specifically those cases that
7627 arise with IF_THEN_ELSE expressions. */
7630 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7632 enum rtx_code code = GET_CODE (x);
7637 if (side_effects_p (x))
7640 /* If either operand of the condition is a floating point value,
7641 then we have to avoid collapsing an EQ comparison. */
7643 && rtx_equal_p (x, reg)
7644 && ! FLOAT_MODE_P (GET_MODE (x))
7645 && ! FLOAT_MODE_P (GET_MODE (val)))
7648 if (cond == UNEQ && rtx_equal_p (x, reg))
7651 /* If X is (abs REG) and we know something about REG's relationship
7652 with zero, we may be able to simplify this. */
7654 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7657 case GE: case GT: case EQ:
7660 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7662 GET_MODE (XEXP (x, 0)));
7667 /* The only other cases we handle are MIN, MAX, and comparisons if the
7668 operands are the same as REG and VAL. */
7670 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7672 if (rtx_equal_p (XEXP (x, 0), val))
7673 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7675 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7677 if (COMPARISON_P (x))
7679 if (comparison_dominates_p (cond, code))
7680 return const_true_rtx;
7682 code = combine_reversed_comparison_code (x);
7684 && comparison_dominates_p (cond, code))
7689 else if (code == SMAX || code == SMIN
7690 || code == UMIN || code == UMAX)
7692 int unsignedp = (code == UMIN || code == UMAX);
7694 /* Do not reverse the condition when it is NE or EQ.
7695 This is because we cannot conclude anything about
7696 the value of 'SMAX (x, y)' when x is not equal to y,
7697 but we can when x equals y. */
7698 if ((code == SMAX || code == UMAX)
7699 && ! (cond == EQ || cond == NE))
7700 cond = reverse_condition (cond);
7705 return unsignedp ? x : XEXP (x, 1);
7707 return unsignedp ? x : XEXP (x, 0);
7709 return unsignedp ? XEXP (x, 1) : x;
7711 return unsignedp ? XEXP (x, 0) : x;
7718 else if (code == SUBREG)
7720 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7721 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7723 if (SUBREG_REG (x) != r)
7725 /* We must simplify subreg here, before we lose track of the
7726 original inner_mode. */
7727 new = simplify_subreg (GET_MODE (x), r,
7728 inner_mode, SUBREG_BYTE (x));
7732 SUBST (SUBREG_REG (x), r);
7737 /* We don't have to handle SIGN_EXTEND here, because even in the
7738 case of replacing something with a modeless CONST_INT, a
7739 CONST_INT is already (supposed to be) a valid sign extension for
7740 its narrower mode, which implies it's already properly
7741 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7742 story is different. */
7743 else if (code == ZERO_EXTEND)
7745 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7746 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7748 if (XEXP (x, 0) != r)
7750 /* We must simplify the zero_extend here, before we lose
7751 track of the original inner_mode. */
7752 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7757 SUBST (XEXP (x, 0), r);
7763 fmt = GET_RTX_FORMAT (code);
7764 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7767 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7768 else if (fmt[i] == 'E')
7769 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7770 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7777 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7778 assignment as a field assignment. */
7781 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7783 if (x == y || rtx_equal_p (x, y))
7786 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7789 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7790 Note that all SUBREGs of MEM are paradoxical; otherwise they
7791 would have been rewritten. */
7792 if (MEM_P (x) && GET_CODE (y) == SUBREG
7793 && MEM_P (SUBREG_REG (y))
7794 && rtx_equal_p (SUBREG_REG (y),
7795 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7798 if (MEM_P (y) && GET_CODE (x) == SUBREG
7799 && MEM_P (SUBREG_REG (x))
7800 && rtx_equal_p (SUBREG_REG (x),
7801 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7804 /* We used to see if get_last_value of X and Y were the same but that's
7805 not correct. In one direction, we'll cause the assignment to have
7806 the wrong destination and in the case, we'll import a register into this
7807 insn that might have already have been dead. So fail if none of the
7808 above cases are true. */
7812 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7813 Return that assignment if so.
7815 We only handle the most common cases. */
7818 make_field_assignment (rtx x)
7820 rtx dest = SET_DEST (x);
7821 rtx src = SET_SRC (x);
7826 unsigned HOST_WIDE_INT len;
7828 enum machine_mode mode;
7830 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7831 a clear of a one-bit field. We will have changed it to
7832 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7835 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7836 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7837 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7838 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7840 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7843 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7847 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7848 && subreg_lowpart_p (XEXP (src, 0))
7849 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7850 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7851 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7852 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7853 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7854 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7856 assign = make_extraction (VOIDmode, dest, 0,
7857 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7860 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7864 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7866 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7867 && XEXP (XEXP (src, 0), 0) == const1_rtx
7868 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7870 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7873 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7877 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7878 SRC is an AND with all bits of that field set, then we can discard
7880 if (GET_CODE (dest) == ZERO_EXTRACT
7881 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7882 && GET_CODE (src) == AND
7883 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7885 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7886 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7887 unsigned HOST_WIDE_INT ze_mask;
7889 if (width >= HOST_BITS_PER_WIDE_INT)
7892 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7894 /* Complete overlap. We can remove the source AND. */
7895 if ((and_mask & ze_mask) == ze_mask)
7896 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7898 /* Partial overlap. We can reduce the source AND. */
7899 if ((and_mask & ze_mask) != and_mask)
7901 mode = GET_MODE (src);
7902 src = gen_rtx_AND (mode, XEXP (src, 0),
7903 gen_int_mode (and_mask & ze_mask, mode));
7904 return gen_rtx_SET (VOIDmode, dest, src);
7908 /* The other case we handle is assignments into a constant-position
7909 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7910 a mask that has all one bits except for a group of zero bits and
7911 OTHER is known to have zeros where C1 has ones, this is such an
7912 assignment. Compute the position and length from C1. Shift OTHER
7913 to the appropriate position, force it to the required mode, and
7914 make the extraction. Check for the AND in both operands. */
7916 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7919 rhs = expand_compound_operation (XEXP (src, 0));
7920 lhs = expand_compound_operation (XEXP (src, 1));
7922 if (GET_CODE (rhs) == AND
7923 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7924 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7925 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7926 else if (GET_CODE (lhs) == AND
7927 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7928 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7929 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7933 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7934 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7935 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7936 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7939 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7943 /* The mode to use for the source is the mode of the assignment, or of
7944 what is inside a possible STRICT_LOW_PART. */
7945 mode = (GET_CODE (assign) == STRICT_LOW_PART
7946 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7948 /* Shift OTHER right POS places and make it the source, restricting it
7949 to the proper length and mode. */
7951 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7952 GET_MODE (src), other, pos),
7954 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7955 ? ~(unsigned HOST_WIDE_INT) 0
7956 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7959 /* If SRC is masked by an AND that does not make a difference in
7960 the value being stored, strip it. */
7961 if (GET_CODE (assign) == ZERO_EXTRACT
7962 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7963 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7964 && GET_CODE (src) == AND
7965 && GET_CODE (XEXP (src, 1)) == CONST_INT
7966 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7967 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7968 src = XEXP (src, 0);
7970 return gen_rtx_SET (VOIDmode, assign, src);
7973 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7977 apply_distributive_law (rtx x)
7979 enum rtx_code code = GET_CODE (x);
7980 enum rtx_code inner_code;
7981 rtx lhs, rhs, other;
7984 /* Distributivity is not true for floating point as it can change the
7985 value. So we don't do it unless -funsafe-math-optimizations. */
7986 if (FLOAT_MODE_P (GET_MODE (x))
7987 && ! flag_unsafe_math_optimizations)
7990 /* The outer operation can only be one of the following: */
7991 if (code != IOR && code != AND && code != XOR
7992 && code != PLUS && code != MINUS)
7998 /* If either operand is a primitive we can't do anything, so get out
8000 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8003 lhs = expand_compound_operation (lhs);
8004 rhs = expand_compound_operation (rhs);
8005 inner_code = GET_CODE (lhs);
8006 if (inner_code != GET_CODE (rhs))
8009 /* See if the inner and outer operations distribute. */
8016 /* These all distribute except over PLUS. */
8017 if (code == PLUS || code == MINUS)
8022 if (code != PLUS && code != MINUS)
8027 /* This is also a multiply, so it distributes over everything. */
8031 /* Non-paradoxical SUBREGs distributes over all operations, provided
8032 the inner modes and byte offsets are the same, this is an extraction
8033 of a low-order part, we don't convert an fp operation to int or
8034 vice versa, and we would not be converting a single-word
8035 operation into a multi-word operation. The latter test is not
8036 required, but it prevents generating unneeded multi-word operations.
8037 Some of the previous tests are redundant given the latter test, but
8038 are retained because they are required for correctness.
8040 We produce the result slightly differently in this case. */
8042 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8043 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8044 || ! subreg_lowpart_p (lhs)
8045 || (GET_MODE_CLASS (GET_MODE (lhs))
8046 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8047 || (GET_MODE_SIZE (GET_MODE (lhs))
8048 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8049 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8052 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8053 SUBREG_REG (lhs), SUBREG_REG (rhs));
8054 return gen_lowpart (GET_MODE (x), tem);
8060 /* Set LHS and RHS to the inner operands (A and B in the example
8061 above) and set OTHER to the common operand (C in the example).
8062 There is only one way to do this unless the inner operation is
8064 if (COMMUTATIVE_ARITH_P (lhs)
8065 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8066 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8067 else if (COMMUTATIVE_ARITH_P (lhs)
8068 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8069 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8070 else if (COMMUTATIVE_ARITH_P (lhs)
8071 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8072 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8073 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8074 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8078 /* Form the new inner operation, seeing if it simplifies first. */
8079 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8081 /* There is one exception to the general way of distributing:
8082 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8083 if (code == XOR && inner_code == IOR)
8086 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8089 /* We may be able to continuing distributing the result, so call
8090 ourselves recursively on the inner operation before forming the
8091 outer operation, which we return. */
8092 return simplify_gen_binary (inner_code, GET_MODE (x),
8093 apply_distributive_law (tem), other);
8096 /* See if X is of the form (* (+ A B) C), and if so convert to
8097 (+ (* A C) (* B C)) and try to simplify.
8099 Most of the time, this results in no change. However, if some of
8100 the operands are the same or inverses of each other, simplifications
8103 For example, (and (ior A B) (not B)) can occur as the result of
8104 expanding a bit field assignment. When we apply the distributive
8105 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8106 which then simplifies to (and (A (not B))).
8108 Note that no checks happen on the validity of applying the inverse
8109 distributive law. This is pointless since we can do it in the
8110 few places where this routine is called.
8112 N is the index of the term that is decomposed (the arithmetic operation,
8113 i.e. (+ A B) in the first example above). !N is the index of the term that
8114 is distributed, i.e. of C in the first example above. */
8116 distribute_and_simplify_rtx (rtx x, int n)
8118 enum machine_mode mode;
8119 enum rtx_code outer_code, inner_code;
8120 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8122 decomposed = XEXP (x, n);
8123 if (!ARITHMETIC_P (decomposed))
8126 mode = GET_MODE (x);
8127 outer_code = GET_CODE (x);
8128 distributed = XEXP (x, !n);
8130 inner_code = GET_CODE (decomposed);
8131 inner_op0 = XEXP (decomposed, 0);
8132 inner_op1 = XEXP (decomposed, 1);
8134 /* Special case (and (xor B C) (not A)), which is equivalent to
8135 (xor (ior A B) (ior A C)) */
8136 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8138 distributed = XEXP (distributed, 0);
8144 /* Distribute the second term. */
8145 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8146 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8150 /* Distribute the first term. */
8151 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8152 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8155 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8157 if (GET_CODE (tmp) != outer_code
8158 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8164 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8167 Return an equivalent form, if different from X. Otherwise, return X. If
8168 X is zero, we are to always construct the equivalent form. */
8171 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8172 unsigned HOST_WIDE_INT constop)
8174 unsigned HOST_WIDE_INT nonzero;
8177 /* Simplify VAROP knowing that we will be only looking at some of the
8180 Note by passing in CONSTOP, we guarantee that the bits not set in
8181 CONSTOP are not significant and will never be examined. We must
8182 ensure that is the case by explicitly masking out those bits
8183 before returning. */
8184 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8186 /* If VAROP is a CLOBBER, we will fail so return it. */
8187 if (GET_CODE (varop) == CLOBBER)
8190 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8191 to VAROP and return the new constant. */
8192 if (GET_CODE (varop) == CONST_INT)
8193 return gen_int_mode (INTVAL (varop) & constop, mode);
8195 /* See what bits may be nonzero in VAROP. Unlike the general case of
8196 a call to nonzero_bits, here we don't care about bits outside
8199 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8201 /* Turn off all bits in the constant that are known to already be zero.
8202 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8203 which is tested below. */
8207 /* If we don't have any bits left, return zero. */
8211 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8212 a power of two, we can replace this with an ASHIFT. */
8213 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8214 && (i = exact_log2 (constop)) >= 0)
8215 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8217 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8218 or XOR, then try to apply the distributive law. This may eliminate
8219 operations if either branch can be simplified because of the AND.
8220 It may also make some cases more complex, but those cases probably
8221 won't match a pattern either with or without this. */
8223 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8227 apply_distributive_law
8228 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8229 simplify_and_const_int (NULL_RTX,
8233 simplify_and_const_int (NULL_RTX,
8238 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8239 the AND and see if one of the operands simplifies to zero. If so, we
8240 may eliminate it. */
8242 if (GET_CODE (varop) == PLUS
8243 && exact_log2 (constop + 1) >= 0)
8247 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8248 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8249 if (o0 == const0_rtx)
8251 if (o1 == const0_rtx)
8255 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8256 if we already had one (just check for the simplest cases). */
8257 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8258 && GET_MODE (XEXP (x, 0)) == mode
8259 && SUBREG_REG (XEXP (x, 0)) == varop)
8260 varop = XEXP (x, 0);
8262 varop = gen_lowpart (mode, varop);
8264 /* If we can't make the SUBREG, try to return what we were given. */
8265 if (GET_CODE (varop) == CLOBBER)
8266 return x ? x : varop;
8268 /* If we are only masking insignificant bits, return VAROP. */
8269 if (constop == nonzero)
8273 /* Otherwise, return an AND. */
8274 constop = trunc_int_for_mode (constop, mode);
8275 /* See how much, if any, of X we can use. */
8276 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8277 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8281 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8282 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8283 SUBST (XEXP (x, 1), GEN_INT (constop));
8285 SUBST (XEXP (x, 0), varop);
8292 /* Given a REG, X, compute which bits in X can be nonzero.
8293 We don't care about bits outside of those defined in MODE.
8295 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8296 a shift, AND, or zero_extract, we can do better. */
8299 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8300 rtx known_x ATTRIBUTE_UNUSED,
8301 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8302 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8303 unsigned HOST_WIDE_INT *nonzero)
8307 /* If X is a register whose nonzero bits value is current, use it.
8308 Otherwise, if X is a register whose value we can find, use that
8309 value. Otherwise, use the previously-computed global nonzero bits
8310 for this register. */
8312 if (reg_stat[REGNO (x)].last_set_value != 0
8313 && (reg_stat[REGNO (x)].last_set_mode == mode
8314 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8315 && GET_MODE_CLASS (mode) == MODE_INT))
8316 && (reg_stat[REGNO (x)].last_set_label == label_tick
8317 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8318 && REG_N_SETS (REGNO (x)) == 1
8319 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8321 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8323 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8327 tem = get_last_value (x);
8331 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8332 /* If X is narrower than MODE and TEM is a non-negative
8333 constant that would appear negative in the mode of X,
8334 sign-extend it for use in reg_nonzero_bits because some
8335 machines (maybe most) will actually do the sign-extension
8336 and this is the conservative approach.
8338 ??? For 2.5, try to tighten up the MD files in this regard
8339 instead of this kludge. */
8341 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8342 && GET_CODE (tem) == CONST_INT
8344 && 0 != (INTVAL (tem)
8345 & ((HOST_WIDE_INT) 1
8346 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8347 tem = GEN_INT (INTVAL (tem)
8348 | ((HOST_WIDE_INT) (-1)
8349 << GET_MODE_BITSIZE (GET_MODE (x))));
8353 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8355 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8357 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8358 /* We don't know anything about the upper bits. */
8359 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8366 /* Return the number of bits at the high-order end of X that are known to
8367 be equal to the sign bit. X will be used in mode MODE; if MODE is
8368 VOIDmode, X will be used in its own mode. The returned value will always
8369 be between 1 and the number of bits in MODE. */
8372 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8373 rtx known_x ATTRIBUTE_UNUSED,
8374 enum machine_mode known_mode
8376 unsigned int known_ret ATTRIBUTE_UNUSED,
8377 unsigned int *result)
8381 if (reg_stat[REGNO (x)].last_set_value != 0
8382 && reg_stat[REGNO (x)].last_set_mode == mode
8383 && (reg_stat[REGNO (x)].last_set_label == label_tick
8384 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8385 && REG_N_SETS (REGNO (x)) == 1
8386 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8388 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8390 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8394 tem = get_last_value (x);
8398 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8399 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8400 *result = reg_stat[REGNO (x)].sign_bit_copies;
8405 /* Return the number of "extended" bits there are in X, when interpreted
8406 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8407 unsigned quantities, this is the number of high-order zero bits.
8408 For signed quantities, this is the number of copies of the sign bit
8409 minus 1. In both case, this function returns the number of "spare"
8410 bits. For example, if two quantities for which this function returns
8411 at least 1 are added, the addition is known not to overflow.
8413 This function will always return 0 unless called during combine, which
8414 implies that it must be called from a define_split. */
8417 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8419 if (nonzero_sign_valid == 0)
8423 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8424 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8425 - floor_log2 (nonzero_bits (x, mode)))
8427 : num_sign_bit_copies (x, mode) - 1);
8430 /* This function is called from `simplify_shift_const' to merge two
8431 outer operations. Specifically, we have already found that we need
8432 to perform operation *POP0 with constant *PCONST0 at the outermost
8433 position. We would now like to also perform OP1 with constant CONST1
8434 (with *POP0 being done last).
8436 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8437 the resulting operation. *PCOMP_P is set to 1 if we would need to
8438 complement the innermost operand, otherwise it is unchanged.
8440 MODE is the mode in which the operation will be done. No bits outside
8441 the width of this mode matter. It is assumed that the width of this mode
8442 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8444 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8445 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8446 result is simply *PCONST0.
8448 If the resulting operation cannot be expressed as one operation, we
8449 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8452 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8454 enum rtx_code op0 = *pop0;
8455 HOST_WIDE_INT const0 = *pconst0;
8457 const0 &= GET_MODE_MASK (mode);
8458 const1 &= GET_MODE_MASK (mode);
8460 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8464 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8467 if (op1 == UNKNOWN || op0 == SET)
8470 else if (op0 == UNKNOWN)
8471 op0 = op1, const0 = const1;
8473 else if (op0 == op1)
8497 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8498 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8501 /* If the two constants aren't the same, we can't do anything. The
8502 remaining six cases can all be done. */
8503 else if (const0 != const1)
8511 /* (a & b) | b == b */
8513 else /* op1 == XOR */
8514 /* (a ^ b) | b == a | b */
8520 /* (a & b) ^ b == (~a) & b */
8521 op0 = AND, *pcomp_p = 1;
8522 else /* op1 == IOR */
8523 /* (a | b) ^ b == a & ~b */
8524 op0 = AND, const0 = ~const0;
8529 /* (a | b) & b == b */
8531 else /* op1 == XOR */
8532 /* (a ^ b) & b) == (~a) & b */
8539 /* Check for NO-OP cases. */
8540 const0 &= GET_MODE_MASK (mode);
8542 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8544 else if (const0 == 0 && op0 == AND)
8546 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8550 /* ??? Slightly redundant with the above mask, but not entirely.
8551 Moving this above means we'd have to sign-extend the mode mask
8552 for the final test. */
8553 const0 = trunc_int_for_mode (const0, mode);
8561 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8562 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8563 that we started with.
8565 The shift is normally computed in the widest mode we find in VAROP, as
8566 long as it isn't a different number of words than RESULT_MODE. Exceptions
8567 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8570 simplify_shift_const (rtx x, enum rtx_code code,
8571 enum machine_mode result_mode, rtx varop,
8574 enum rtx_code orig_code = code;
8577 enum machine_mode mode = result_mode;
8578 enum machine_mode shift_mode, tmode;
8579 unsigned int mode_words
8580 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8581 /* We form (outer_op (code varop count) (outer_const)). */
8582 enum rtx_code outer_op = UNKNOWN;
8583 HOST_WIDE_INT outer_const = 0;
8585 int complement_p = 0;
8588 /* Make sure and truncate the "natural" shift on the way in. We don't
8589 want to do this inside the loop as it makes it more difficult to
8591 if (SHIFT_COUNT_TRUNCATED)
8592 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8594 /* If we were given an invalid count, don't do anything except exactly
8595 what was requested. */
8597 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8602 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8607 /* Unless one of the branches of the `if' in this loop does a `continue',
8608 we will `break' the loop after the `if'. */
8612 /* If we have an operand of (clobber (const_int 0)), just return that
8614 if (GET_CODE (varop) == CLOBBER)
8617 /* If we discovered we had to complement VAROP, leave. Making a NOT
8618 here would cause an infinite loop. */
8622 /* Convert ROTATERT to ROTATE. */
8623 if (code == ROTATERT)
8625 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8627 if (VECTOR_MODE_P (result_mode))
8628 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8630 count = bitsize - count;
8633 /* We need to determine what mode we will do the shift in. If the
8634 shift is a right shift or a ROTATE, we must always do it in the mode
8635 it was originally done in. Otherwise, we can do it in MODE, the
8636 widest mode encountered. */
8638 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8639 ? result_mode : mode);
8641 /* Handle cases where the count is greater than the size of the mode
8642 minus 1. For ASHIFT, use the size minus one as the count (this can
8643 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8644 take the count modulo the size. For other shifts, the result is
8647 Since these shifts are being produced by the compiler by combining
8648 multiple operations, each of which are defined, we know what the
8649 result is supposed to be. */
8651 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8653 if (code == ASHIFTRT)
8654 count = GET_MODE_BITSIZE (shift_mode) - 1;
8655 else if (code == ROTATE || code == ROTATERT)
8656 count %= GET_MODE_BITSIZE (shift_mode);
8659 /* We can't simply return zero because there may be an
8667 /* An arithmetic right shift of a quantity known to be -1 or 0
8669 if (code == ASHIFTRT
8670 && (num_sign_bit_copies (varop, shift_mode)
8671 == GET_MODE_BITSIZE (shift_mode)))
8677 /* If we are doing an arithmetic right shift and discarding all but
8678 the sign bit copies, this is equivalent to doing a shift by the
8679 bitsize minus one. Convert it into that shift because it will often
8680 allow other simplifications. */
8682 if (code == ASHIFTRT
8683 && (count + num_sign_bit_copies (varop, shift_mode)
8684 >= GET_MODE_BITSIZE (shift_mode)))
8685 count = GET_MODE_BITSIZE (shift_mode) - 1;
8687 /* We simplify the tests below and elsewhere by converting
8688 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8689 `make_compound_operation' will convert it to an ASHIFTRT for
8690 those machines (such as VAX) that don't have an LSHIFTRT. */
8691 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8693 && ((nonzero_bits (varop, shift_mode)
8694 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8698 if (code == LSHIFTRT
8699 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8700 && !(nonzero_bits (varop, shift_mode) >> count))
8703 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8704 && !((nonzero_bits (varop, shift_mode) << count)
8705 & GET_MODE_MASK (shift_mode)))
8708 switch (GET_CODE (varop))
8714 new = expand_compound_operation (varop);
8723 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8724 minus the width of a smaller mode, we can do this with a
8725 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8726 if ((code == ASHIFTRT || code == LSHIFTRT)
8727 && ! mode_dependent_address_p (XEXP (varop, 0))
8728 && ! MEM_VOLATILE_P (varop)
8729 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8730 MODE_INT, 1)) != BLKmode)
8732 new = adjust_address_nv (varop, tmode,
8733 BYTES_BIG_ENDIAN ? 0
8734 : count / BITS_PER_UNIT);
8736 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8737 : ZERO_EXTEND, mode, new);
8744 /* Similar to the case above, except that we can only do this if
8745 the resulting mode is the same as that of the underlying
8746 MEM and adjust the address depending on the *bits* endianness
8747 because of the way that bit-field extract insns are defined. */
8748 if ((code == ASHIFTRT || code == LSHIFTRT)
8749 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8750 MODE_INT, 1)) != BLKmode
8751 && tmode == GET_MODE (XEXP (varop, 0)))
8753 if (BITS_BIG_ENDIAN)
8754 new = XEXP (varop, 0);
8757 new = copy_rtx (XEXP (varop, 0));
8758 SUBST (XEXP (new, 0),
8759 plus_constant (XEXP (new, 0),
8760 count / BITS_PER_UNIT));
8763 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8764 : ZERO_EXTEND, mode, new);
8771 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8772 the same number of words as what we've seen so far. Then store
8773 the widest mode in MODE. */
8774 if (subreg_lowpart_p (varop)
8775 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8776 > GET_MODE_SIZE (GET_MODE (varop)))
8777 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8778 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8781 varop = SUBREG_REG (varop);
8782 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8783 mode = GET_MODE (varop);
8789 /* Some machines use MULT instead of ASHIFT because MULT
8790 is cheaper. But it is still better on those machines to
8791 merge two shifts into one. */
8792 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8793 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8796 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8798 GEN_INT (exact_log2 (
8799 INTVAL (XEXP (varop, 1)))));
8805 /* Similar, for when divides are cheaper. */
8806 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8807 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8810 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8812 GEN_INT (exact_log2 (
8813 INTVAL (XEXP (varop, 1)))));
8819 /* If we are extracting just the sign bit of an arithmetic
8820 right shift, that shift is not needed. However, the sign
8821 bit of a wider mode may be different from what would be
8822 interpreted as the sign bit in a narrower mode, so, if
8823 the result is narrower, don't discard the shift. */
8824 if (code == LSHIFTRT
8825 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8826 && (GET_MODE_BITSIZE (result_mode)
8827 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8829 varop = XEXP (varop, 0);
8833 /* ... fall through ... */
8838 /* Here we have two nested shifts. The result is usually the
8839 AND of a new shift with a mask. We compute the result below. */
8840 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8841 && INTVAL (XEXP (varop, 1)) >= 0
8842 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8843 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8844 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8846 enum rtx_code first_code = GET_CODE (varop);
8847 unsigned int first_count = INTVAL (XEXP (varop, 1));
8848 unsigned HOST_WIDE_INT mask;
8851 /* We have one common special case. We can't do any merging if
8852 the inner code is an ASHIFTRT of a smaller mode. However, if
8853 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8854 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8855 we can convert it to
8856 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8857 This simplifies certain SIGN_EXTEND operations. */
8858 if (code == ASHIFT && first_code == ASHIFTRT
8859 && count == (unsigned int)
8860 (GET_MODE_BITSIZE (result_mode)
8861 - GET_MODE_BITSIZE (GET_MODE (varop))))
8863 /* C3 has the low-order C1 bits zero. */
8865 mask = (GET_MODE_MASK (mode)
8866 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8868 varop = simplify_and_const_int (NULL_RTX, result_mode,
8869 XEXP (varop, 0), mask);
8870 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8872 count = first_count;
8877 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8878 than C1 high-order bits equal to the sign bit, we can convert
8879 this to either an ASHIFT or an ASHIFTRT depending on the
8882 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8884 if (code == ASHIFTRT && first_code == ASHIFT
8885 && GET_MODE (varop) == shift_mode
8886 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8889 varop = XEXP (varop, 0);
8891 signed_count = count - first_count;
8892 if (signed_count < 0)
8893 count = -signed_count, code = ASHIFT;
8895 count = signed_count;
8900 /* There are some cases we can't do. If CODE is ASHIFTRT,
8901 we can only do this if FIRST_CODE is also ASHIFTRT.
8903 We can't do the case when CODE is ROTATE and FIRST_CODE is
8906 If the mode of this shift is not the mode of the outer shift,
8907 we can't do this if either shift is a right shift or ROTATE.
8909 Finally, we can't do any of these if the mode is too wide
8910 unless the codes are the same.
8912 Handle the case where the shift codes are the same
8915 if (code == first_code)
8917 if (GET_MODE (varop) != result_mode
8918 && (code == ASHIFTRT || code == LSHIFTRT
8922 count += first_count;
8923 varop = XEXP (varop, 0);
8927 if (code == ASHIFTRT
8928 || (code == ROTATE && first_code == ASHIFTRT)
8929 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8930 || (GET_MODE (varop) != result_mode
8931 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8932 || first_code == ROTATE
8933 || code == ROTATE)))
8936 /* To compute the mask to apply after the shift, shift the
8937 nonzero bits of the inner shift the same way the
8938 outer shift will. */
8940 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8943 = simplify_binary_operation (code, result_mode, mask_rtx,
8946 /* Give up if we can't compute an outer operation to use. */
8948 || GET_CODE (mask_rtx) != CONST_INT
8949 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8951 result_mode, &complement_p))
8954 /* If the shifts are in the same direction, we add the
8955 counts. Otherwise, we subtract them. */
8956 signed_count = count;
8957 if ((code == ASHIFTRT || code == LSHIFTRT)
8958 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8959 signed_count += first_count;
8961 signed_count -= first_count;
8963 /* If COUNT is positive, the new shift is usually CODE,
8964 except for the two exceptions below, in which case it is
8965 FIRST_CODE. If the count is negative, FIRST_CODE should
8967 if (signed_count > 0
8968 && ((first_code == ROTATE && code == ASHIFT)
8969 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8970 code = first_code, count = signed_count;
8971 else if (signed_count < 0)
8972 code = first_code, count = -signed_count;
8974 count = signed_count;
8976 varop = XEXP (varop, 0);
8980 /* If we have (A << B << C) for any shift, we can convert this to
8981 (A << C << B). This wins if A is a constant. Only try this if
8982 B is not a constant. */
8984 else if (GET_CODE (varop) == code
8985 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8987 = simplify_binary_operation (code, mode,
8991 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8998 /* Make this fit the case below. */
8999 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9000 GEN_INT (GET_MODE_MASK (mode)));
9006 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9007 with C the size of VAROP - 1 and the shift is logical if
9008 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9009 we have an (le X 0) operation. If we have an arithmetic shift
9010 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9011 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9013 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9014 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9015 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9016 && (code == LSHIFTRT || code == ASHIFTRT)
9017 && count == (unsigned int)
9018 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9019 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9022 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9025 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9026 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9031 /* If we have (shift (logical)), move the logical to the outside
9032 to allow it to possibly combine with another logical and the
9033 shift to combine with another shift. This also canonicalizes to
9034 what a ZERO_EXTRACT looks like. Also, some machines have
9035 (and (shift)) insns. */
9037 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9038 /* We can't do this if we have (ashiftrt (xor)) and the
9039 constant has its sign bit set in shift_mode. */
9040 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9041 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9043 && (new = simplify_binary_operation (code, result_mode,
9045 GEN_INT (count))) != 0
9046 && GET_CODE (new) == CONST_INT
9047 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9048 INTVAL (new), result_mode, &complement_p))
9050 varop = XEXP (varop, 0);
9054 /* If we can't do that, try to simplify the shift in each arm of the
9055 logical expression, make a new logical expression, and apply
9056 the inverse distributive law. This also can't be done
9057 for some (ashiftrt (xor)). */
9058 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9059 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9060 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9063 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9064 XEXP (varop, 0), count);
9065 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9066 XEXP (varop, 1), count);
9068 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9070 varop = apply_distributive_law (varop);
9078 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9079 says that the sign bit can be tested, FOO has mode MODE, C is
9080 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9081 that may be nonzero. */
9082 if (code == LSHIFTRT
9083 && XEXP (varop, 1) == const0_rtx
9084 && GET_MODE (XEXP (varop, 0)) == result_mode
9085 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9086 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9087 && ((STORE_FLAG_VALUE
9088 & ((HOST_WIDE_INT) 1
9089 < (GET_MODE_BITSIZE (result_mode) - 1))))
9090 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9091 && merge_outer_ops (&outer_op, &outer_const, XOR,
9092 (HOST_WIDE_INT) 1, result_mode,
9095 varop = XEXP (varop, 0);
9102 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9103 than the number of bits in the mode is equivalent to A. */
9104 if (code == LSHIFTRT
9105 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9106 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9108 varop = XEXP (varop, 0);
9113 /* NEG commutes with ASHIFT since it is multiplication. Move the
9114 NEG outside to allow shifts to combine. */
9116 && merge_outer_ops (&outer_op, &outer_const, NEG,
9117 (HOST_WIDE_INT) 0, result_mode,
9120 varop = XEXP (varop, 0);
9126 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9127 is one less than the number of bits in the mode is
9128 equivalent to (xor A 1). */
9129 if (code == LSHIFTRT
9130 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9131 && XEXP (varop, 1) == constm1_rtx
9132 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9133 && merge_outer_ops (&outer_op, &outer_const, XOR,
9134 (HOST_WIDE_INT) 1, result_mode,
9138 varop = XEXP (varop, 0);
9142 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9143 that might be nonzero in BAR are those being shifted out and those
9144 bits are known zero in FOO, we can replace the PLUS with FOO.
9145 Similarly in the other operand order. This code occurs when
9146 we are computing the size of a variable-size array. */
9148 if ((code == ASHIFTRT || code == LSHIFTRT)
9149 && count < HOST_BITS_PER_WIDE_INT
9150 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9151 && (nonzero_bits (XEXP (varop, 1), result_mode)
9152 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9154 varop = XEXP (varop, 0);
9157 else if ((code == ASHIFTRT || code == LSHIFTRT)
9158 && count < HOST_BITS_PER_WIDE_INT
9159 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9160 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9162 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9163 & nonzero_bits (XEXP (varop, 1),
9166 varop = XEXP (varop, 1);
9170 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9172 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9173 && (new = simplify_binary_operation (ASHIFT, result_mode,
9175 GEN_INT (count))) != 0
9176 && GET_CODE (new) == CONST_INT
9177 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9178 INTVAL (new), result_mode, &complement_p))
9180 varop = XEXP (varop, 0);
9184 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9185 signbit', and attempt to change the PLUS to an XOR and move it to
9186 the outer operation as is done above in the AND/IOR/XOR case
9187 leg for shift(logical). See details in logical handling above
9188 for reasoning in doing so. */
9189 if (code == LSHIFTRT
9190 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9191 && mode_signbit_p (result_mode, XEXP (varop, 1))
9192 && (new = simplify_binary_operation (code, result_mode,
9194 GEN_INT (count))) != 0
9195 && GET_CODE (new) == CONST_INT
9196 && merge_outer_ops (&outer_op, &outer_const, XOR,
9197 INTVAL (new), result_mode, &complement_p))
9199 varop = XEXP (varop, 0);
9206 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9207 with C the size of VAROP - 1 and the shift is logical if
9208 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9209 we have a (gt X 0) operation. If the shift is arithmetic with
9210 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9211 we have a (neg (gt X 0)) operation. */
9213 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9214 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9215 && count == (unsigned int)
9216 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9217 && (code == LSHIFTRT || code == ASHIFTRT)
9218 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9219 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9221 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9224 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9227 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9228 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9235 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9236 if the truncate does not affect the value. */
9237 if (code == LSHIFTRT
9238 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9239 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9240 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9241 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9242 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9244 rtx varop_inner = XEXP (varop, 0);
9247 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9248 XEXP (varop_inner, 0),
9250 (count + INTVAL (XEXP (varop_inner, 1))));
9251 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9264 /* We need to determine what mode to do the shift in. If the shift is
9265 a right shift or ROTATE, we must always do it in the mode it was
9266 originally done in. Otherwise, we can do it in MODE, the widest mode
9267 encountered. The code we care about is that of the shift that will
9268 actually be done, not the shift that was originally requested. */
9270 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9271 ? result_mode : mode);
9273 /* We have now finished analyzing the shift. The result should be
9274 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9275 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9276 to the result of the shift. OUTER_CONST is the relevant constant,
9277 but we must turn off all bits turned off in the shift.
9279 If we were passed a value for X, see if we can use any pieces of
9280 it. If not, make new rtx. */
9282 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9283 && GET_CODE (XEXP (x, 1)) == CONST_INT
9284 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9285 const_rtx = XEXP (x, 1);
9287 const_rtx = GEN_INT (count);
9289 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9290 && GET_MODE (XEXP (x, 0)) == shift_mode
9291 && SUBREG_REG (XEXP (x, 0)) == varop)
9292 varop = XEXP (x, 0);
9293 else if (GET_MODE (varop) != shift_mode)
9294 varop = gen_lowpart (shift_mode, varop);
9296 /* If we can't make the SUBREG, try to return what we were given. */
9297 if (GET_CODE (varop) == CLOBBER)
9298 return x ? x : varop;
9300 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9304 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9306 /* If we have an outer operation and we just made a shift, it is
9307 possible that we could have simplified the shift were it not
9308 for the outer operation. So try to do the simplification
9311 if (outer_op != UNKNOWN && GET_CODE (x) == code
9312 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9313 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9314 INTVAL (XEXP (x, 1)));
9316 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9317 turn off all the bits that the shift would have turned off. */
9318 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9319 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9320 GET_MODE_MASK (result_mode) >> orig_count);
9322 /* Do the remainder of the processing in RESULT_MODE. */
9323 x = gen_lowpart (result_mode, x);
9325 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9328 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9330 if (outer_op != UNKNOWN)
9332 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9333 outer_const = trunc_int_for_mode (outer_const, result_mode);
9335 if (outer_op == AND)
9336 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9337 else if (outer_op == SET)
9338 /* This means that we have determined that the result is
9339 equivalent to a constant. This should be rare. */
9340 x = GEN_INT (outer_const);
9341 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9342 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9344 x = simplify_gen_binary (outer_op, result_mode, x,
9345 GEN_INT (outer_const));
9351 /* Like recog, but we receive the address of a pointer to a new pattern.
9352 We try to match the rtx that the pointer points to.
9353 If that fails, we may try to modify or replace the pattern,
9354 storing the replacement into the same pointer object.
9356 Modifications include deletion or addition of CLOBBERs.
9358 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9359 the CLOBBERs are placed.
9361 The value is the final insn code from the pattern ultimately matched,
9365 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9368 int insn_code_number;
9369 int num_clobbers_to_add = 0;
9372 rtx old_notes, old_pat;
9374 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9375 we use to indicate that something didn't match. If we find such a
9376 thing, force rejection. */
9377 if (GET_CODE (pat) == PARALLEL)
9378 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9379 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9380 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9383 old_pat = PATTERN (insn);
9384 old_notes = REG_NOTES (insn);
9385 PATTERN (insn) = pat;
9386 REG_NOTES (insn) = 0;
9388 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9390 /* If it isn't, there is the possibility that we previously had an insn
9391 that clobbered some register as a side effect, but the combined
9392 insn doesn't need to do that. So try once more without the clobbers
9393 unless this represents an ASM insn. */
9395 if (insn_code_number < 0 && ! check_asm_operands (pat)
9396 && GET_CODE (pat) == PARALLEL)
9400 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9401 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9404 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9408 SUBST_INT (XVECLEN (pat, 0), pos);
9411 pat = XVECEXP (pat, 0, 0);
9413 PATTERN (insn) = pat;
9414 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9416 PATTERN (insn) = old_pat;
9417 REG_NOTES (insn) = old_notes;
9419 /* Recognize all noop sets, these will be killed by followup pass. */
9420 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9421 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9423 /* If we had any clobbers to add, make a new pattern than contains
9424 them. Then check to make sure that all of them are dead. */
9425 if (num_clobbers_to_add)
9427 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9428 rtvec_alloc (GET_CODE (pat) == PARALLEL
9430 + num_clobbers_to_add)
9431 : num_clobbers_to_add + 1));
9433 if (GET_CODE (pat) == PARALLEL)
9434 for (i = 0; i < XVECLEN (pat, 0); i++)
9435 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9437 XVECEXP (newpat, 0, 0) = pat;
9439 add_clobbers (newpat, insn_code_number);
9441 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9442 i < XVECLEN (newpat, 0); i++)
9444 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9445 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9447 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9448 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9456 return insn_code_number;
9459 /* Like gen_lowpart_general but for use by combine. In combine it
9460 is not possible to create any new pseudoregs. However, it is
9461 safe to create invalid memory addresses, because combine will
9462 try to recognize them and all they will do is make the combine
9465 If for some reason this cannot do its job, an rtx
9466 (clobber (const_int 0)) is returned.
9467 An insn containing that will not be recognized. */
9470 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9472 enum machine_mode imode = GET_MODE (x);
9473 unsigned int osize = GET_MODE_SIZE (omode);
9474 unsigned int isize = GET_MODE_SIZE (imode);
9480 /* Return identity if this is a CONST or symbolic reference. */
9482 && (GET_CODE (x) == CONST
9483 || GET_CODE (x) == SYMBOL_REF
9484 || GET_CODE (x) == LABEL_REF))
9487 /* We can only support MODE being wider than a word if X is a
9488 constant integer or has a mode the same size. */
9489 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9490 && ! ((imode == VOIDmode
9491 && (GET_CODE (x) == CONST_INT
9492 || GET_CODE (x) == CONST_DOUBLE))
9496 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9497 won't know what to do. So we will strip off the SUBREG here and
9498 process normally. */
9499 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9503 /* For use in case we fall down into the address adjustments
9504 further below, we need to adjust the known mode and size of
9505 x; imode and isize, since we just adjusted x. */
9506 imode = GET_MODE (x);
9511 isize = GET_MODE_SIZE (imode);
9514 result = gen_lowpart_common (omode, x);
9516 #ifdef CANNOT_CHANGE_MODE_CLASS
9517 if (result != 0 && GET_CODE (result) == SUBREG)
9518 record_subregs_of_mode (result);
9528 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9530 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9533 /* If we want to refer to something bigger than the original memref,
9534 generate a paradoxical subreg instead. That will force a reload
9535 of the original memref X. */
9537 return gen_rtx_SUBREG (omode, x, 0);
9539 if (WORDS_BIG_ENDIAN)
9540 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9542 /* Adjust the address so that the address-after-the-data is
9544 if (BYTES_BIG_ENDIAN)
9545 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9547 return adjust_address_nv (x, omode, offset);
9550 /* If X is a comparison operator, rewrite it in a new mode. This
9551 probably won't match, but may allow further simplifications. */
9552 else if (COMPARISON_P (x))
9553 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9555 /* If we couldn't simplify X any other way, just enclose it in a
9556 SUBREG. Normally, this SUBREG won't match, but some patterns may
9557 include an explicit SUBREG or we may simplify it further in combine. */
9563 offset = subreg_lowpart_offset (omode, imode);
9564 if (imode == VOIDmode)
9566 imode = int_mode_for_mode (omode);
9567 x = gen_lowpart_common (imode, x);
9571 res = simplify_gen_subreg (omode, x, imode, offset);
9577 return gen_rtx_CLOBBER (imode, const0_rtx);
9580 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9581 comparison code that will be tested.
9583 The result is a possibly different comparison code to use. *POP0 and
9584 *POP1 may be updated.
9586 It is possible that we might detect that a comparison is either always
9587 true or always false. However, we do not perform general constant
9588 folding in combine, so this knowledge isn't useful. Such tautologies
9589 should have been detected earlier. Hence we ignore all such cases. */
9591 static enum rtx_code
9592 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9598 enum machine_mode mode, tmode;
9600 /* Try a few ways of applying the same transformation to both operands. */
9603 #ifndef WORD_REGISTER_OPERATIONS
9604 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9605 so check specially. */
9606 if (code != GTU && code != GEU && code != LTU && code != LEU
9607 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9608 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9609 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9610 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9611 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9612 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9613 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9614 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9615 && XEXP (op0, 1) == XEXP (op1, 1)
9616 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9617 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9618 && (INTVAL (XEXP (op0, 1))
9619 == (GET_MODE_BITSIZE (GET_MODE (op0))
9621 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9623 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9624 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9628 /* If both operands are the same constant shift, see if we can ignore the
9629 shift. We can if the shift is a rotate or if the bits shifted out of
9630 this shift are known to be zero for both inputs and if the type of
9631 comparison is compatible with the shift. */
9632 if (GET_CODE (op0) == GET_CODE (op1)
9633 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9634 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9635 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9636 && (code != GT && code != LT && code != GE && code != LE))
9637 || (GET_CODE (op0) == ASHIFTRT
9638 && (code != GTU && code != LTU
9639 && code != GEU && code != LEU)))
9640 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9641 && INTVAL (XEXP (op0, 1)) >= 0
9642 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9643 && XEXP (op0, 1) == XEXP (op1, 1))
9645 enum machine_mode mode = GET_MODE (op0);
9646 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9647 int shift_count = INTVAL (XEXP (op0, 1));
9649 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9650 mask &= (mask >> shift_count) << shift_count;
9651 else if (GET_CODE (op0) == ASHIFT)
9652 mask = (mask & (mask << shift_count)) >> shift_count;
9654 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9655 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9656 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9661 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9662 SUBREGs are of the same mode, and, in both cases, the AND would
9663 be redundant if the comparison was done in the narrower mode,
9664 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9665 and the operand's possibly nonzero bits are 0xffffff01; in that case
9666 if we only care about QImode, we don't need the AND). This case
9667 occurs if the output mode of an scc insn is not SImode and
9668 STORE_FLAG_VALUE == 1 (e.g., the 386).
9670 Similarly, check for a case where the AND's are ZERO_EXTEND
9671 operations from some narrower mode even though a SUBREG is not
9674 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9675 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9676 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9678 rtx inner_op0 = XEXP (op0, 0);
9679 rtx inner_op1 = XEXP (op1, 0);
9680 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9681 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9684 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9685 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9686 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9687 && (GET_MODE (SUBREG_REG (inner_op0))
9688 == GET_MODE (SUBREG_REG (inner_op1)))
9689 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9690 <= HOST_BITS_PER_WIDE_INT)
9691 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9692 GET_MODE (SUBREG_REG (inner_op0)))))
9693 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9694 GET_MODE (SUBREG_REG (inner_op1))))))
9696 op0 = SUBREG_REG (inner_op0);
9697 op1 = SUBREG_REG (inner_op1);
9699 /* The resulting comparison is always unsigned since we masked
9700 off the original sign bit. */
9701 code = unsigned_condition (code);
9707 for (tmode = GET_CLASS_NARROWEST_MODE
9708 (GET_MODE_CLASS (GET_MODE (op0)));
9709 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9710 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9712 op0 = gen_lowpart (tmode, inner_op0);
9713 op1 = gen_lowpart (tmode, inner_op1);
9714 code = unsigned_condition (code);
9723 /* If both operands are NOT, we can strip off the outer operation
9724 and adjust the comparison code for swapped operands; similarly for
9725 NEG, except that this must be an equality comparison. */
9726 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9727 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9728 && (code == EQ || code == NE)))
9729 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9735 /* If the first operand is a constant, swap the operands and adjust the
9736 comparison code appropriately, but don't do this if the second operand
9737 is already a constant integer. */
9738 if (swap_commutative_operands_p (op0, op1))
9740 tem = op0, op0 = op1, op1 = tem;
9741 code = swap_condition (code);
9744 /* We now enter a loop during which we will try to simplify the comparison.
9745 For the most part, we only are concerned with comparisons with zero,
9746 but some things may really be comparisons with zero but not start
9747 out looking that way. */
9749 while (GET_CODE (op1) == CONST_INT)
9751 enum machine_mode mode = GET_MODE (op0);
9752 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9753 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9754 int equality_comparison_p;
9755 int sign_bit_comparison_p;
9756 int unsigned_comparison_p;
9757 HOST_WIDE_INT const_op;
9759 /* We only want to handle integral modes. This catches VOIDmode,
9760 CCmode, and the floating-point modes. An exception is that we
9761 can handle VOIDmode if OP0 is a COMPARE or a comparison
9764 if (GET_MODE_CLASS (mode) != MODE_INT
9765 && ! (mode == VOIDmode
9766 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9769 /* Get the constant we are comparing against and turn off all bits
9770 not on in our mode. */
9771 const_op = INTVAL (op1);
9772 if (mode != VOIDmode)
9773 const_op = trunc_int_for_mode (const_op, mode);
9774 op1 = GEN_INT (const_op);
9776 /* If we are comparing against a constant power of two and the value
9777 being compared can only have that single bit nonzero (e.g., it was
9778 `and'ed with that bit), we can replace this with a comparison
9781 && (code == EQ || code == NE || code == GE || code == GEU
9782 || code == LT || code == LTU)
9783 && mode_width <= HOST_BITS_PER_WIDE_INT
9784 && exact_log2 (const_op) >= 0
9785 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9787 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9788 op1 = const0_rtx, const_op = 0;
9791 /* Similarly, if we are comparing a value known to be either -1 or
9792 0 with -1, change it to the opposite comparison against zero. */
9795 && (code == EQ || code == NE || code == GT || code == LE
9796 || code == GEU || code == LTU)
9797 && num_sign_bit_copies (op0, mode) == mode_width)
9799 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9800 op1 = const0_rtx, const_op = 0;
9803 /* Do some canonicalizations based on the comparison code. We prefer
9804 comparisons against zero and then prefer equality comparisons.
9805 If we can reduce the size of a constant, we will do that too. */
9810 /* < C is equivalent to <= (C - 1) */
9814 op1 = GEN_INT (const_op);
9816 /* ... fall through to LE case below. */
9822 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9826 op1 = GEN_INT (const_op);
9830 /* If we are doing a <= 0 comparison on a value known to have
9831 a zero sign bit, we can replace this with == 0. */
9832 else if (const_op == 0
9833 && mode_width <= HOST_BITS_PER_WIDE_INT
9834 && (nonzero_bits (op0, mode)
9835 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9840 /* >= C is equivalent to > (C - 1). */
9844 op1 = GEN_INT (const_op);
9846 /* ... fall through to GT below. */
9852 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9856 op1 = GEN_INT (const_op);
9860 /* If we are doing a > 0 comparison on a value known to have
9861 a zero sign bit, we can replace this with != 0. */
9862 else if (const_op == 0
9863 && mode_width <= HOST_BITS_PER_WIDE_INT
9864 && (nonzero_bits (op0, mode)
9865 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9870 /* < C is equivalent to <= (C - 1). */
9874 op1 = GEN_INT (const_op);
9876 /* ... fall through ... */
9879 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9880 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9881 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9883 const_op = 0, op1 = const0_rtx;
9891 /* unsigned <= 0 is equivalent to == 0 */
9895 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9896 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9897 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9899 const_op = 0, op1 = const0_rtx;
9905 /* >= C is equivalent to > (C - 1). */
9909 op1 = GEN_INT (const_op);
9911 /* ... fall through ... */
9914 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9915 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9916 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9918 const_op = 0, op1 = const0_rtx;
9926 /* unsigned > 0 is equivalent to != 0 */
9930 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9931 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9932 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9934 const_op = 0, op1 = const0_rtx;
9943 /* Compute some predicates to simplify code below. */
9945 equality_comparison_p = (code == EQ || code == NE);
9946 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9947 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9950 /* If this is a sign bit comparison and we can do arithmetic in
9951 MODE, say that we will only be needing the sign bit of OP0. */
9952 if (sign_bit_comparison_p
9953 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9954 op0 = force_to_mode (op0, mode,
9956 << (GET_MODE_BITSIZE (mode) - 1)),
9959 /* Now try cases based on the opcode of OP0. If none of the cases
9960 does a "continue", we exit this loop immediately after the
9963 switch (GET_CODE (op0))
9966 /* If we are extracting a single bit from a variable position in
9967 a constant that has only a single bit set and are comparing it
9968 with zero, we can convert this into an equality comparison
9969 between the position and the location of the single bit. */
9970 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9971 have already reduced the shift count modulo the word size. */
9972 if (!SHIFT_COUNT_TRUNCATED
9973 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9974 && XEXP (op0, 1) == const1_rtx
9975 && equality_comparison_p && const_op == 0
9976 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9978 if (BITS_BIG_ENDIAN)
9980 enum machine_mode new_mode
9981 = mode_for_extraction (EP_extzv, 1);
9982 if (new_mode == MAX_MACHINE_MODE)
9983 i = BITS_PER_WORD - 1 - i;
9987 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9991 op0 = XEXP (op0, 2);
9995 /* Result is nonzero iff shift count is equal to I. */
9996 code = reverse_condition (code);
10000 /* ... fall through ... */
10003 tem = expand_compound_operation (op0);
10012 /* If testing for equality, we can take the NOT of the constant. */
10013 if (equality_comparison_p
10014 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10016 op0 = XEXP (op0, 0);
10021 /* If just looking at the sign bit, reverse the sense of the
10023 if (sign_bit_comparison_p)
10025 op0 = XEXP (op0, 0);
10026 code = (code == GE ? LT : GE);
10032 /* If testing for equality, we can take the NEG of the constant. */
10033 if (equality_comparison_p
10034 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10036 op0 = XEXP (op0, 0);
10041 /* The remaining cases only apply to comparisons with zero. */
10045 /* When X is ABS or is known positive,
10046 (neg X) is < 0 if and only if X != 0. */
10048 if (sign_bit_comparison_p
10049 && (GET_CODE (XEXP (op0, 0)) == ABS
10050 || (mode_width <= HOST_BITS_PER_WIDE_INT
10051 && (nonzero_bits (XEXP (op0, 0), mode)
10052 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10054 op0 = XEXP (op0, 0);
10055 code = (code == LT ? NE : EQ);
10059 /* If we have NEG of something whose two high-order bits are the
10060 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10061 if (num_sign_bit_copies (op0, mode) >= 2)
10063 op0 = XEXP (op0, 0);
10064 code = swap_condition (code);
10070 /* If we are testing equality and our count is a constant, we
10071 can perform the inverse operation on our RHS. */
10072 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10073 && (tem = simplify_binary_operation (ROTATERT, mode,
10074 op1, XEXP (op0, 1))) != 0)
10076 op0 = XEXP (op0, 0);
10081 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10082 a particular bit. Convert it to an AND of a constant of that
10083 bit. This will be converted into a ZERO_EXTRACT. */
10084 if (const_op == 0 && sign_bit_comparison_p
10085 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10086 && mode_width <= HOST_BITS_PER_WIDE_INT)
10088 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10091 - INTVAL (XEXP (op0, 1)))));
10092 code = (code == LT ? NE : EQ);
10096 /* Fall through. */
10099 /* ABS is ignorable inside an equality comparison with zero. */
10100 if (const_op == 0 && equality_comparison_p)
10102 op0 = XEXP (op0, 0);
10108 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10109 (compare FOO CONST) if CONST fits in FOO's mode and we
10110 are either testing inequality or have an unsigned
10111 comparison with ZERO_EXTEND or a signed comparison with
10112 SIGN_EXTEND. But don't do it if we don't have a compare
10113 insn of the given mode, since we'd have to revert it
10114 later on, and then we wouldn't know whether to sign- or
10116 mode = GET_MODE (XEXP (op0, 0));
10117 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10118 && ! unsigned_comparison_p
10119 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10120 && ((unsigned HOST_WIDE_INT) const_op
10121 < (((unsigned HOST_WIDE_INT) 1
10122 << (GET_MODE_BITSIZE (mode) - 1))))
10123 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10125 op0 = XEXP (op0, 0);
10131 /* Check for the case where we are comparing A - C1 with C2, that is
10133 (subreg:MODE (plus (A) (-C1))) op (C2)
10135 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10136 comparison in the wider mode. One of the following two conditions
10137 must be true in order for this to be valid:
10139 1. The mode extension results in the same bit pattern being added
10140 on both sides and the comparison is equality or unsigned. As
10141 C2 has been truncated to fit in MODE, the pattern can only be
10144 2. The mode extension results in the sign bit being copied on
10147 The difficulty here is that we have predicates for A but not for
10148 (A - C1) so we need to check that C1 is within proper bounds so
10149 as to perturbate A as little as possible. */
10151 if (mode_width <= HOST_BITS_PER_WIDE_INT
10152 && subreg_lowpart_p (op0)
10153 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10154 && GET_CODE (SUBREG_REG (op0)) == PLUS
10155 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10157 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10158 rtx a = XEXP (SUBREG_REG (op0), 0);
10159 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10162 && (unsigned HOST_WIDE_INT) c1
10163 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10164 && (equality_comparison_p || unsigned_comparison_p)
10165 /* (A - C1) zero-extends if it is positive and sign-extends
10166 if it is negative, C2 both zero- and sign-extends. */
10167 && ((0 == (nonzero_bits (a, inner_mode)
10168 & ~GET_MODE_MASK (mode))
10170 /* (A - C1) sign-extends if it is positive and 1-extends
10171 if it is negative, C2 both sign- and 1-extends. */
10172 || (num_sign_bit_copies (a, inner_mode)
10173 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10176 || ((unsigned HOST_WIDE_INT) c1
10177 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10178 /* (A - C1) always sign-extends, like C2. */
10179 && num_sign_bit_copies (a, inner_mode)
10180 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10181 - mode_width - 1)))
10183 op0 = SUBREG_REG (op0);
10188 /* If the inner mode is narrower and we are extracting the low part,
10189 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10190 if (subreg_lowpart_p (op0)
10191 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10192 /* Fall through */ ;
10196 /* ... fall through ... */
10199 mode = GET_MODE (XEXP (op0, 0));
10200 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10201 && (unsigned_comparison_p || equality_comparison_p)
10202 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10203 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10204 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10206 op0 = XEXP (op0, 0);
10212 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10213 this for equality comparisons due to pathological cases involving
10215 if (equality_comparison_p
10216 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10217 op1, XEXP (op0, 1))))
10219 op0 = XEXP (op0, 0);
10224 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10225 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10226 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10228 op0 = XEXP (XEXP (op0, 0), 0);
10229 code = (code == LT ? EQ : NE);
10235 /* We used to optimize signed comparisons against zero, but that
10236 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10237 arrive here as equality comparisons, or (GEU, LTU) are
10238 optimized away. No need to special-case them. */
10240 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10241 (eq B (minus A C)), whichever simplifies. We can only do
10242 this for equality comparisons due to pathological cases involving
10244 if (equality_comparison_p
10245 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10246 XEXP (op0, 1), op1)))
10248 op0 = XEXP (op0, 0);
10253 if (equality_comparison_p
10254 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10255 XEXP (op0, 0), op1)))
10257 op0 = XEXP (op0, 1);
10262 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10263 of bits in X minus 1, is one iff X > 0. */
10264 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10265 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10266 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10268 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10270 op0 = XEXP (op0, 1);
10271 code = (code == GE ? LE : GT);
10277 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10278 if C is zero or B is a constant. */
10279 if (equality_comparison_p
10280 && 0 != (tem = simplify_binary_operation (XOR, mode,
10281 XEXP (op0, 1), op1)))
10283 op0 = XEXP (op0, 0);
10290 case UNEQ: case LTGT:
10291 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10292 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10293 case UNORDERED: case ORDERED:
10294 /* We can't do anything if OP0 is a condition code value, rather
10295 than an actual data value. */
10297 || CC0_P (XEXP (op0, 0))
10298 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10301 /* Get the two operands being compared. */
10302 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10303 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10305 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10307 /* Check for the cases where we simply want the result of the
10308 earlier test or the opposite of that result. */
10309 if (code == NE || code == EQ
10310 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10311 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10312 && (STORE_FLAG_VALUE
10313 & (((HOST_WIDE_INT) 1
10314 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10315 && (code == LT || code == GE)))
10317 enum rtx_code new_code;
10318 if (code == LT || code == NE)
10319 new_code = GET_CODE (op0);
10321 new_code = combine_reversed_comparison_code (op0);
10323 if (new_code != UNKNOWN)
10334 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10336 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10337 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10338 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10340 op0 = XEXP (op0, 1);
10341 code = (code == GE ? GT : LE);
10347 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10348 will be converted to a ZERO_EXTRACT later. */
10349 if (const_op == 0 && equality_comparison_p
10350 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10351 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10353 op0 = simplify_and_const_int
10354 (op0, mode, gen_rtx_LSHIFTRT (mode,
10356 XEXP (XEXP (op0, 0), 1)),
10357 (HOST_WIDE_INT) 1);
10361 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10362 zero and X is a comparison and C1 and C2 describe only bits set
10363 in STORE_FLAG_VALUE, we can compare with X. */
10364 if (const_op == 0 && equality_comparison_p
10365 && mode_width <= HOST_BITS_PER_WIDE_INT
10366 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10367 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10368 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10369 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10370 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10372 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10373 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10374 if ((~STORE_FLAG_VALUE & mask) == 0
10375 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10376 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10377 && COMPARISON_P (tem))))
10379 op0 = XEXP (XEXP (op0, 0), 0);
10384 /* If we are doing an equality comparison of an AND of a bit equal
10385 to the sign bit, replace this with a LT or GE comparison of
10386 the underlying value. */
10387 if (equality_comparison_p
10389 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10390 && mode_width <= HOST_BITS_PER_WIDE_INT
10391 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10392 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10394 op0 = XEXP (op0, 0);
10395 code = (code == EQ ? GE : LT);
10399 /* If this AND operation is really a ZERO_EXTEND from a narrower
10400 mode, the constant fits within that mode, and this is either an
10401 equality or unsigned comparison, try to do this comparison in
10402 the narrower mode. */
10403 if ((equality_comparison_p || unsigned_comparison_p)
10404 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10405 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10406 & GET_MODE_MASK (mode))
10408 && const_op >> i == 0
10409 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10411 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10415 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10416 fits in both M1 and M2 and the SUBREG is either paradoxical
10417 or represents the low part, permute the SUBREG and the AND
10419 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10421 unsigned HOST_WIDE_INT c1;
10422 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10423 /* Require an integral mode, to avoid creating something like
10425 if (SCALAR_INT_MODE_P (tmode)
10426 /* It is unsafe to commute the AND into the SUBREG if the
10427 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10428 not defined. As originally written the upper bits
10429 have a defined value due to the AND operation.
10430 However, if we commute the AND inside the SUBREG then
10431 they no longer have defined values and the meaning of
10432 the code has been changed. */
10434 #ifdef WORD_REGISTER_OPERATIONS
10435 || (mode_width > GET_MODE_BITSIZE (tmode)
10436 && mode_width <= BITS_PER_WORD)
10438 || (mode_width <= GET_MODE_BITSIZE (tmode)
10439 && subreg_lowpart_p (XEXP (op0, 0))))
10440 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10441 && mode_width <= HOST_BITS_PER_WIDE_INT
10442 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10443 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10444 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10446 && c1 != GET_MODE_MASK (tmode))
10448 op0 = simplify_gen_binary (AND, tmode,
10449 SUBREG_REG (XEXP (op0, 0)),
10450 gen_int_mode (c1, tmode));
10451 op0 = gen_lowpart (mode, op0);
10456 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10457 if (const_op == 0 && equality_comparison_p
10458 && XEXP (op0, 1) == const1_rtx
10459 && GET_CODE (XEXP (op0, 0)) == NOT)
10461 op0 = simplify_and_const_int
10462 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10463 code = (code == NE ? EQ : NE);
10467 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10468 (eq (and (lshiftrt X) 1) 0).
10469 Also handle the case where (not X) is expressed using xor. */
10470 if (const_op == 0 && equality_comparison_p
10471 && XEXP (op0, 1) == const1_rtx
10472 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10474 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10475 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10477 if (GET_CODE (shift_op) == NOT
10478 || (GET_CODE (shift_op) == XOR
10479 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10480 && GET_CODE (shift_count) == CONST_INT
10481 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10482 && (INTVAL (XEXP (shift_op, 1))
10483 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10485 op0 = simplify_and_const_int
10487 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10488 (HOST_WIDE_INT) 1);
10489 code = (code == NE ? EQ : NE);
10496 /* If we have (compare (ashift FOO N) (const_int C)) and
10497 the high order N bits of FOO (N+1 if an inequality comparison)
10498 are known to be zero, we can do this by comparing FOO with C
10499 shifted right N bits so long as the low-order N bits of C are
10501 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10502 && INTVAL (XEXP (op0, 1)) >= 0
10503 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10504 < HOST_BITS_PER_WIDE_INT)
10506 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10507 && mode_width <= HOST_BITS_PER_WIDE_INT
10508 && (nonzero_bits (XEXP (op0, 0), mode)
10509 & ~(mask >> (INTVAL (XEXP (op0, 1))
10510 + ! equality_comparison_p))) == 0)
10512 /* We must perform a logical shift, not an arithmetic one,
10513 as we want the top N bits of C to be zero. */
10514 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10516 temp >>= INTVAL (XEXP (op0, 1));
10517 op1 = gen_int_mode (temp, mode);
10518 op0 = XEXP (op0, 0);
10522 /* If we are doing a sign bit comparison, it means we are testing
10523 a particular bit. Convert it to the appropriate AND. */
10524 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10525 && mode_width <= HOST_BITS_PER_WIDE_INT)
10527 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10530 - INTVAL (XEXP (op0, 1)))));
10531 code = (code == LT ? NE : EQ);
10535 /* If this an equality comparison with zero and we are shifting
10536 the low bit to the sign bit, we can convert this to an AND of the
10538 if (const_op == 0 && equality_comparison_p
10539 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10540 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10543 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10544 (HOST_WIDE_INT) 1);
10550 /* If this is an equality comparison with zero, we can do this
10551 as a logical shift, which might be much simpler. */
10552 if (equality_comparison_p && const_op == 0
10553 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10555 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10557 INTVAL (XEXP (op0, 1)));
10561 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10562 do the comparison in a narrower mode. */
10563 if (! unsigned_comparison_p
10564 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10565 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10566 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10567 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10568 MODE_INT, 1)) != BLKmode
10569 && (((unsigned HOST_WIDE_INT) const_op
10570 + (GET_MODE_MASK (tmode) >> 1) + 1)
10571 <= GET_MODE_MASK (tmode)))
10573 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10577 /* Likewise if OP0 is a PLUS of a sign extension with a
10578 constant, which is usually represented with the PLUS
10579 between the shifts. */
10580 if (! unsigned_comparison_p
10581 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10582 && GET_CODE (XEXP (op0, 0)) == PLUS
10583 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10584 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10585 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10586 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10587 MODE_INT, 1)) != BLKmode
10588 && (((unsigned HOST_WIDE_INT) const_op
10589 + (GET_MODE_MASK (tmode) >> 1) + 1)
10590 <= GET_MODE_MASK (tmode)))
10592 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10593 rtx add_const = XEXP (XEXP (op0, 0), 1);
10594 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10595 add_const, XEXP (op0, 1));
10597 op0 = simplify_gen_binary (PLUS, tmode,
10598 gen_lowpart (tmode, inner),
10603 /* ... fall through ... */
10605 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10606 the low order N bits of FOO are known to be zero, we can do this
10607 by comparing FOO with C shifted left N bits so long as no
10608 overflow occurs. */
10609 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10610 && INTVAL (XEXP (op0, 1)) >= 0
10611 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10612 && mode_width <= HOST_BITS_PER_WIDE_INT
10613 && (nonzero_bits (XEXP (op0, 0), mode)
10614 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10615 && (((unsigned HOST_WIDE_INT) const_op
10616 + (GET_CODE (op0) != LSHIFTRT
10617 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10620 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10622 /* If the shift was logical, then we must make the condition
10624 if (GET_CODE (op0) == LSHIFTRT)
10625 code = unsigned_condition (code);
10627 const_op <<= INTVAL (XEXP (op0, 1));
10628 op1 = GEN_INT (const_op);
10629 op0 = XEXP (op0, 0);
10633 /* If we are using this shift to extract just the sign bit, we
10634 can replace this with an LT or GE comparison. */
10636 && (equality_comparison_p || sign_bit_comparison_p)
10637 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10638 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10641 op0 = XEXP (op0, 0);
10642 code = (code == NE || code == GT ? LT : GE);
10654 /* Now make any compound operations involved in this comparison. Then,
10655 check for an outmost SUBREG on OP0 that is not doing anything or is
10656 paradoxical. The latter transformation must only be performed when
10657 it is known that the "extra" bits will be the same in op0 and op1 or
10658 that they don't matter. There are three cases to consider:
10660 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10661 care bits and we can assume they have any convenient value. So
10662 making the transformation is safe.
10664 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10665 In this case the upper bits of op0 are undefined. We should not make
10666 the simplification in that case as we do not know the contents of
10669 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10670 UNKNOWN. In that case we know those bits are zeros or ones. We must
10671 also be sure that they are the same as the upper bits of op1.
10673 We can never remove a SUBREG for a non-equality comparison because
10674 the sign bit is in a different place in the underlying object. */
10676 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10677 op1 = make_compound_operation (op1, SET);
10679 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10680 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10681 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10682 && (code == NE || code == EQ))
10684 if (GET_MODE_SIZE (GET_MODE (op0))
10685 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10687 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10689 if (REG_P (SUBREG_REG (op0)))
10691 op0 = SUBREG_REG (op0);
10692 op1 = gen_lowpart (GET_MODE (op0), op1);
10695 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10696 <= HOST_BITS_PER_WIDE_INT)
10697 && (nonzero_bits (SUBREG_REG (op0),
10698 GET_MODE (SUBREG_REG (op0)))
10699 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10701 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10703 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10704 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10705 op0 = SUBREG_REG (op0), op1 = tem;
10709 /* We now do the opposite procedure: Some machines don't have compare
10710 insns in all modes. If OP0's mode is an integer mode smaller than a
10711 word and we can't do a compare in that mode, see if there is a larger
10712 mode for which we can do the compare. There are a number of cases in
10713 which we can use the wider mode. */
10715 mode = GET_MODE (op0);
10716 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10717 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10718 && ! have_insn_for (COMPARE, mode))
10719 for (tmode = GET_MODE_WIDER_MODE (mode);
10721 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10722 tmode = GET_MODE_WIDER_MODE (tmode))
10723 if (have_insn_for (COMPARE, tmode))
10727 /* If the only nonzero bits in OP0 and OP1 are those in the
10728 narrower mode and this is an equality or unsigned comparison,
10729 we can use the wider mode. Similarly for sign-extended
10730 values, in which case it is true for all comparisons. */
10731 zero_extended = ((code == EQ || code == NE
10732 || code == GEU || code == GTU
10733 || code == LEU || code == LTU)
10734 && (nonzero_bits (op0, tmode)
10735 & ~GET_MODE_MASK (mode)) == 0
10736 && ((GET_CODE (op1) == CONST_INT
10737 || (nonzero_bits (op1, tmode)
10738 & ~GET_MODE_MASK (mode)) == 0)));
10741 || ((num_sign_bit_copies (op0, tmode)
10742 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10743 - GET_MODE_BITSIZE (mode)))
10744 && (num_sign_bit_copies (op1, tmode)
10745 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10746 - GET_MODE_BITSIZE (mode)))))
10748 /* If OP0 is an AND and we don't have an AND in MODE either,
10749 make a new AND in the proper mode. */
10750 if (GET_CODE (op0) == AND
10751 && !have_insn_for (AND, mode))
10752 op0 = simplify_gen_binary (AND, tmode,
10753 gen_lowpart (tmode,
10755 gen_lowpart (tmode,
10758 op0 = gen_lowpart (tmode, op0);
10759 if (zero_extended && GET_CODE (op1) == CONST_INT)
10760 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10761 op1 = gen_lowpart (tmode, op1);
10765 /* If this is a test for negative, we can make an explicit
10766 test of the sign bit. */
10768 if (op1 == const0_rtx && (code == LT || code == GE)
10769 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10771 op0 = simplify_gen_binary (AND, tmode,
10772 gen_lowpart (tmode, op0),
10773 GEN_INT ((HOST_WIDE_INT) 1
10774 << (GET_MODE_BITSIZE (mode)
10776 code = (code == LT) ? NE : EQ;
10781 #ifdef CANONICALIZE_COMPARISON
10782 /* If this machine only supports a subset of valid comparisons, see if we
10783 can convert an unsupported one into a supported one. */
10784 CANONICALIZE_COMPARISON (code, op0, op1);
10793 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10794 searching backward. */
10795 static enum rtx_code
10796 combine_reversed_comparison_code (rtx exp)
10798 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10801 if (code1 != UNKNOWN
10802 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10804 /* Otherwise try and find where the condition codes were last set and
10806 x = get_last_value (XEXP (exp, 0));
10807 if (!x || GET_CODE (x) != COMPARE)
10809 return reversed_comparison_code_parts (GET_CODE (exp),
10810 XEXP (x, 0), XEXP (x, 1), NULL);
10813 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10814 Return NULL_RTX in case we fail to do the reversal. */
10816 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10818 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10819 if (reversed_code == UNKNOWN)
10822 return simplify_gen_relational (reversed_code, mode, VOIDmode, op0, op1);
10825 /* Utility function for record_value_for_reg. Count number of
10830 enum rtx_code code = GET_CODE (x);
10834 if (GET_RTX_CLASS (code) == '2'
10835 || GET_RTX_CLASS (code) == 'c')
10837 rtx x0 = XEXP (x, 0);
10838 rtx x1 = XEXP (x, 1);
10841 return 1 + 2 * count_rtxs (x0);
10843 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10844 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10845 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10846 return 2 + 2 * count_rtxs (x0)
10847 + count_rtxs (x == XEXP (x1, 0)
10848 ? XEXP (x1, 1) : XEXP (x1, 0));
10850 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10851 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10852 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10853 return 2 + 2 * count_rtxs (x1)
10854 + count_rtxs (x == XEXP (x0, 0)
10855 ? XEXP (x0, 1) : XEXP (x0, 0));
10858 fmt = GET_RTX_FORMAT (code);
10859 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10861 ret += count_rtxs (XEXP (x, i));
10866 /* Utility function for following routine. Called when X is part of a value
10867 being stored into last_set_value. Sets last_set_table_tick
10868 for each register mentioned. Similar to mention_regs in cse.c */
10871 update_table_tick (rtx x)
10873 enum rtx_code code = GET_CODE (x);
10874 const char *fmt = GET_RTX_FORMAT (code);
10879 unsigned int regno = REGNO (x);
10880 unsigned int endregno
10881 = regno + (regno < FIRST_PSEUDO_REGISTER
10882 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10885 for (r = regno; r < endregno; r++)
10886 reg_stat[r].last_set_table_tick = label_tick;
10891 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10892 /* Note that we can't have an "E" in values stored; see
10893 get_last_value_validate. */
10896 /* Check for identical subexpressions. If x contains
10897 identical subexpression we only have to traverse one of
10899 if (i == 0 && ARITHMETIC_P (x))
10901 /* Note that at this point x1 has already been
10903 rtx x0 = XEXP (x, 0);
10904 rtx x1 = XEXP (x, 1);
10906 /* If x0 and x1 are identical then there is no need to
10911 /* If x0 is identical to a subexpression of x1 then while
10912 processing x1, x0 has already been processed. Thus we
10913 are done with x. */
10914 if (ARITHMETIC_P (x1)
10915 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10918 /* If x1 is identical to a subexpression of x0 then we
10919 still have to process the rest of x0. */
10920 if (ARITHMETIC_P (x0)
10921 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10923 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10928 update_table_tick (XEXP (x, i));
10932 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10933 are saying that the register is clobbered and we no longer know its
10934 value. If INSN is zero, don't update reg_stat[].last_set; this is
10935 only permitted with VALUE also zero and is used to invalidate the
10939 record_value_for_reg (rtx reg, rtx insn, rtx value)
10941 unsigned int regno = REGNO (reg);
10942 unsigned int endregno
10943 = regno + (regno < FIRST_PSEUDO_REGISTER
10944 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10947 /* If VALUE contains REG and we have a previous value for REG, substitute
10948 the previous value. */
10949 if (value && insn && reg_overlap_mentioned_p (reg, value))
10953 /* Set things up so get_last_value is allowed to see anything set up to
10955 subst_low_cuid = INSN_CUID (insn);
10956 tem = get_last_value (reg);
10958 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10959 it isn't going to be useful and will take a lot of time to process,
10960 so just use the CLOBBER. */
10964 if (ARITHMETIC_P (tem)
10965 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10966 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10967 tem = XEXP (tem, 0);
10968 else if (count_occurrences (value, reg, 1) >= 2)
10970 /* If there are two or more occurrences of REG in VALUE,
10971 prevent the value from growing too much. */
10972 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10973 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10976 value = replace_rtx (copy_rtx (value), reg, tem);
10980 /* For each register modified, show we don't know its value, that
10981 we don't know about its bitwise content, that its value has been
10982 updated, and that we don't know the location of the death of the
10984 for (i = regno; i < endregno; i++)
10987 reg_stat[i].last_set = insn;
10989 reg_stat[i].last_set_value = 0;
10990 reg_stat[i].last_set_mode = 0;
10991 reg_stat[i].last_set_nonzero_bits = 0;
10992 reg_stat[i].last_set_sign_bit_copies = 0;
10993 reg_stat[i].last_death = 0;
10996 /* Mark registers that are being referenced in this value. */
10998 update_table_tick (value);
11000 /* Now update the status of each register being set.
11001 If someone is using this register in this block, set this register
11002 to invalid since we will get confused between the two lives in this
11003 basic block. This makes using this register always invalid. In cse, we
11004 scan the table to invalidate all entries using this register, but this
11005 is too much work for us. */
11007 for (i = regno; i < endregno; i++)
11009 reg_stat[i].last_set_label = label_tick;
11010 if (value && reg_stat[i].last_set_table_tick == label_tick)
11011 reg_stat[i].last_set_invalid = 1;
11013 reg_stat[i].last_set_invalid = 0;
11016 /* The value being assigned might refer to X (like in "x++;"). In that
11017 case, we must replace it with (clobber (const_int 0)) to prevent
11019 if (value && ! get_last_value_validate (&value, insn,
11020 reg_stat[regno].last_set_label, 0))
11022 value = copy_rtx (value);
11023 if (! get_last_value_validate (&value, insn,
11024 reg_stat[regno].last_set_label, 1))
11028 /* For the main register being modified, update the value, the mode, the
11029 nonzero bits, and the number of sign bit copies. */
11031 reg_stat[regno].last_set_value = value;
11035 enum machine_mode mode = GET_MODE (reg);
11036 subst_low_cuid = INSN_CUID (insn);
11037 reg_stat[regno].last_set_mode = mode;
11038 if (GET_MODE_CLASS (mode) == MODE_INT
11039 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11040 mode = nonzero_bits_mode;
11041 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
11042 reg_stat[regno].last_set_sign_bit_copies
11043 = num_sign_bit_copies (value, GET_MODE (reg));
11047 /* Called via note_stores from record_dead_and_set_regs to handle one
11048 SET or CLOBBER in an insn. DATA is the instruction in which the
11049 set is occurring. */
11052 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11054 rtx record_dead_insn = (rtx) data;
11056 if (GET_CODE (dest) == SUBREG)
11057 dest = SUBREG_REG (dest);
11061 /* If we are setting the whole register, we know its value. Otherwise
11062 show that we don't know the value. We can handle SUBREG in
11064 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11065 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11066 else if (GET_CODE (setter) == SET
11067 && GET_CODE (SET_DEST (setter)) == SUBREG
11068 && SUBREG_REG (SET_DEST (setter)) == dest
11069 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11070 && subreg_lowpart_p (SET_DEST (setter)))
11071 record_value_for_reg (dest, record_dead_insn,
11072 gen_lowpart (GET_MODE (dest),
11073 SET_SRC (setter)));
11075 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11077 else if (MEM_P (dest)
11078 /* Ignore pushes, they clobber nothing. */
11079 && ! push_operand (dest, GET_MODE (dest)))
11080 mem_last_set = INSN_CUID (record_dead_insn);
11083 /* Update the records of when each REG was most recently set or killed
11084 for the things done by INSN. This is the last thing done in processing
11085 INSN in the combiner loop.
11087 We update reg_stat[], in particular fields last_set, last_set_value,
11088 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11089 last_death, and also the similar information mem_last_set (which insn
11090 most recently modified memory) and last_call_cuid (which insn was the
11091 most recent subroutine call). */
11094 record_dead_and_set_regs (rtx insn)
11099 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11101 if (REG_NOTE_KIND (link) == REG_DEAD
11102 && REG_P (XEXP (link, 0)))
11104 unsigned int regno = REGNO (XEXP (link, 0));
11105 unsigned int endregno
11106 = regno + (regno < FIRST_PSEUDO_REGISTER
11107 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11110 for (i = regno; i < endregno; i++)
11111 reg_stat[i].last_death = insn;
11113 else if (REG_NOTE_KIND (link) == REG_INC)
11114 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11119 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11120 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11122 reg_stat[i].last_set_value = 0;
11123 reg_stat[i].last_set_mode = 0;
11124 reg_stat[i].last_set_nonzero_bits = 0;
11125 reg_stat[i].last_set_sign_bit_copies = 0;
11126 reg_stat[i].last_death = 0;
11129 last_call_cuid = mem_last_set = INSN_CUID (insn);
11131 /* Don't bother recording what this insn does. It might set the
11132 return value register, but we can't combine into a call
11133 pattern anyway, so there's no point trying (and it may cause
11134 a crash, if e.g. we wind up asking for last_set_value of a
11135 SUBREG of the return value register). */
11139 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11142 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11143 register present in the SUBREG, so for each such SUBREG go back and
11144 adjust nonzero and sign bit information of the registers that are
11145 known to have some zero/sign bits set.
11147 This is needed because when combine blows the SUBREGs away, the
11148 information on zero/sign bits is lost and further combines can be
11149 missed because of that. */
11152 record_promoted_value (rtx insn, rtx subreg)
11155 unsigned int regno = REGNO (SUBREG_REG (subreg));
11156 enum machine_mode mode = GET_MODE (subreg);
11158 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11161 for (links = LOG_LINKS (insn); links;)
11163 insn = XEXP (links, 0);
11164 set = single_set (insn);
11166 if (! set || !REG_P (SET_DEST (set))
11167 || REGNO (SET_DEST (set)) != regno
11168 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11170 links = XEXP (links, 1);
11174 if (reg_stat[regno].last_set == insn)
11176 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11177 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11180 if (REG_P (SET_SRC (set)))
11182 regno = REGNO (SET_SRC (set));
11183 links = LOG_LINKS (insn);
11190 /* Scan X for promoted SUBREGs. For each one found,
11191 note what it implies to the registers used in it. */
11194 check_promoted_subreg (rtx insn, rtx x)
11196 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11197 && REG_P (SUBREG_REG (x)))
11198 record_promoted_value (insn, x);
11201 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11204 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11208 check_promoted_subreg (insn, XEXP (x, i));
11212 if (XVEC (x, i) != 0)
11213 for (j = 0; j < XVECLEN (x, i); j++)
11214 check_promoted_subreg (insn, XVECEXP (x, i, j));
11220 /* Utility routine for the following function. Verify that all the registers
11221 mentioned in *LOC are valid when *LOC was part of a value set when
11222 label_tick == TICK. Return 0 if some are not.
11224 If REPLACE is nonzero, replace the invalid reference with
11225 (clobber (const_int 0)) and return 1. This replacement is useful because
11226 we often can get useful information about the form of a value (e.g., if
11227 it was produced by a shift that always produces -1 or 0) even though
11228 we don't know exactly what registers it was produced from. */
11231 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11234 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11235 int len = GET_RTX_LENGTH (GET_CODE (x));
11240 unsigned int regno = REGNO (x);
11241 unsigned int endregno
11242 = regno + (regno < FIRST_PSEUDO_REGISTER
11243 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11246 for (j = regno; j < endregno; j++)
11247 if (reg_stat[j].last_set_invalid
11248 /* If this is a pseudo-register that was only set once and not
11249 live at the beginning of the function, it is always valid. */
11250 || (! (regno >= FIRST_PSEUDO_REGISTER
11251 && REG_N_SETS (regno) == 1
11252 && (! REGNO_REG_SET_P
11253 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11254 && reg_stat[j].last_set_label > tick))
11257 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11263 /* If this is a memory reference, make sure that there were
11264 no stores after it that might have clobbered the value. We don't
11265 have alias info, so we assume any store invalidates it. */
11266 else if (MEM_P (x) && !MEM_READONLY_P (x)
11267 && INSN_CUID (insn) <= mem_last_set)
11270 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11274 for (i = 0; i < len; i++)
11278 /* Check for identical subexpressions. If x contains
11279 identical subexpression we only have to traverse one of
11281 if (i == 1 && ARITHMETIC_P (x))
11283 /* Note that at this point x0 has already been checked
11284 and found valid. */
11285 rtx x0 = XEXP (x, 0);
11286 rtx x1 = XEXP (x, 1);
11288 /* If x0 and x1 are identical then x is also valid. */
11292 /* If x1 is identical to a subexpression of x0 then
11293 while checking x0, x1 has already been checked. Thus
11294 it is valid and so as x. */
11295 if (ARITHMETIC_P (x0)
11296 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11299 /* If x0 is identical to a subexpression of x1 then x is
11300 valid iff the rest of x1 is valid. */
11301 if (ARITHMETIC_P (x1)
11302 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11304 get_last_value_validate (&XEXP (x1,
11305 x0 == XEXP (x1, 0) ? 1 : 0),
11306 insn, tick, replace);
11309 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11313 /* Don't bother with these. They shouldn't occur anyway. */
11314 else if (fmt[i] == 'E')
11318 /* If we haven't found a reason for it to be invalid, it is valid. */
11322 /* Get the last value assigned to X, if known. Some registers
11323 in the value may be replaced with (clobber (const_int 0)) if their value
11324 is known longer known reliably. */
11327 get_last_value (rtx x)
11329 unsigned int regno;
11332 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11333 then convert it to the desired mode. If this is a paradoxical SUBREG,
11334 we cannot predict what values the "extra" bits might have. */
11335 if (GET_CODE (x) == SUBREG
11336 && subreg_lowpart_p (x)
11337 && (GET_MODE_SIZE (GET_MODE (x))
11338 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11339 && (value = get_last_value (SUBREG_REG (x))) != 0)
11340 return gen_lowpart (GET_MODE (x), value);
11346 value = reg_stat[regno].last_set_value;
11348 /* If we don't have a value, or if it isn't for this basic block and
11349 it's either a hard register, set more than once, or it's a live
11350 at the beginning of the function, return 0.
11352 Because if it's not live at the beginning of the function then the reg
11353 is always set before being used (is never used without being set).
11354 And, if it's set only once, and it's always set before use, then all
11355 uses must have the same last value, even if it's not from this basic
11359 || (reg_stat[regno].last_set_label != label_tick
11360 && (regno < FIRST_PSEUDO_REGISTER
11361 || REG_N_SETS (regno) != 1
11362 || (REGNO_REG_SET_P
11363 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11366 /* If the value was set in a later insn than the ones we are processing,
11367 we can't use it even if the register was only set once. */
11368 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11371 /* If the value has all its registers valid, return it. */
11372 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11373 reg_stat[regno].last_set_label, 0))
11376 /* Otherwise, make a copy and replace any invalid register with
11377 (clobber (const_int 0)). If that fails for some reason, return 0. */
11379 value = copy_rtx (value);
11380 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11381 reg_stat[regno].last_set_label, 1))
11387 /* Return nonzero if expression X refers to a REG or to memory
11388 that is set in an instruction more recent than FROM_CUID. */
11391 use_crosses_set_p (rtx x, int from_cuid)
11395 enum rtx_code code = GET_CODE (x);
11399 unsigned int regno = REGNO (x);
11400 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11401 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11403 #ifdef PUSH_ROUNDING
11404 /* Don't allow uses of the stack pointer to be moved,
11405 because we don't know whether the move crosses a push insn. */
11406 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11409 for (; regno < endreg; regno++)
11410 if (reg_stat[regno].last_set
11411 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11416 if (code == MEM && mem_last_set > from_cuid)
11419 fmt = GET_RTX_FORMAT (code);
11421 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11426 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11427 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11430 else if (fmt[i] == 'e'
11431 && use_crosses_set_p (XEXP (x, i), from_cuid))
11437 /* Define three variables used for communication between the following
11440 static unsigned int reg_dead_regno, reg_dead_endregno;
11441 static int reg_dead_flag;
11443 /* Function called via note_stores from reg_dead_at_p.
11445 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11446 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11449 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11451 unsigned int regno, endregno;
11456 regno = REGNO (dest);
11457 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11458 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11460 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11461 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11464 /* Return nonzero if REG is known to be dead at INSN.
11466 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11467 referencing REG, it is dead. If we hit a SET referencing REG, it is
11468 live. Otherwise, see if it is live or dead at the start of the basic
11469 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11470 must be assumed to be always live. */
11473 reg_dead_at_p (rtx reg, rtx insn)
11478 /* Set variables for reg_dead_at_p_1. */
11479 reg_dead_regno = REGNO (reg);
11480 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11481 ? hard_regno_nregs[reg_dead_regno]
11487 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11488 we allow the machine description to decide whether use-and-clobber
11489 patterns are OK. */
11490 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11492 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11493 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11497 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11498 beginning of function. */
11499 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11500 insn = prev_nonnote_insn (insn))
11502 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11504 return reg_dead_flag == 1 ? 1 : 0;
11506 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11510 /* Get the basic block that we were in. */
11512 block = ENTRY_BLOCK_PTR->next_bb;
11515 FOR_EACH_BB (block)
11516 if (insn == BB_HEAD (block))
11519 if (block == EXIT_BLOCK_PTR)
11523 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11524 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11530 /* Note hard registers in X that are used. This code is similar to
11531 that in flow.c, but much simpler since we don't care about pseudos. */
11534 mark_used_regs_combine (rtx x)
11536 RTX_CODE code = GET_CODE (x);
11537 unsigned int regno;
11550 case ADDR_DIFF_VEC:
11553 /* CC0 must die in the insn after it is set, so we don't need to take
11554 special note of it here. */
11560 /* If we are clobbering a MEM, mark any hard registers inside the
11561 address as used. */
11562 if (MEM_P (XEXP (x, 0)))
11563 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11568 /* A hard reg in a wide mode may really be multiple registers.
11569 If so, mark all of them just like the first. */
11570 if (regno < FIRST_PSEUDO_REGISTER)
11572 unsigned int endregno, r;
11574 /* None of this applies to the stack, frame or arg pointers. */
11575 if (regno == STACK_POINTER_REGNUM
11576 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11577 || regno == HARD_FRAME_POINTER_REGNUM
11579 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11580 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11582 || regno == FRAME_POINTER_REGNUM)
11585 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11586 for (r = regno; r < endregno; r++)
11587 SET_HARD_REG_BIT (newpat_used_regs, r);
11593 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11595 rtx testreg = SET_DEST (x);
11597 while (GET_CODE (testreg) == SUBREG
11598 || GET_CODE (testreg) == ZERO_EXTRACT
11599 || GET_CODE (testreg) == STRICT_LOW_PART)
11600 testreg = XEXP (testreg, 0);
11602 if (MEM_P (testreg))
11603 mark_used_regs_combine (XEXP (testreg, 0));
11605 mark_used_regs_combine (SET_SRC (x));
11613 /* Recursively scan the operands of this expression. */
11616 const char *fmt = GET_RTX_FORMAT (code);
11618 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11621 mark_used_regs_combine (XEXP (x, i));
11622 else if (fmt[i] == 'E')
11626 for (j = 0; j < XVECLEN (x, i); j++)
11627 mark_used_regs_combine (XVECEXP (x, i, j));
11633 /* Remove register number REGNO from the dead registers list of INSN.
11635 Return the note used to record the death, if there was one. */
11638 remove_death (unsigned int regno, rtx insn)
11640 rtx note = find_regno_note (insn, REG_DEAD, regno);
11644 REG_N_DEATHS (regno)--;
11645 remove_note (insn, note);
11651 /* For each register (hardware or pseudo) used within expression X, if its
11652 death is in an instruction with cuid between FROM_CUID (inclusive) and
11653 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11654 list headed by PNOTES.
11656 That said, don't move registers killed by maybe_kill_insn.
11658 This is done when X is being merged by combination into TO_INSN. These
11659 notes will then be distributed as needed. */
11662 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11667 enum rtx_code code = GET_CODE (x);
11671 unsigned int regno = REGNO (x);
11672 rtx where_dead = reg_stat[regno].last_death;
11673 rtx before_dead, after_dead;
11675 /* Don't move the register if it gets killed in between from and to. */
11676 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11677 && ! reg_referenced_p (x, maybe_kill_insn))
11680 /* WHERE_DEAD could be a USE insn made by combine, so first we
11681 make sure that we have insns with valid INSN_CUID values. */
11682 before_dead = where_dead;
11683 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11684 before_dead = PREV_INSN (before_dead);
11686 after_dead = where_dead;
11687 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11688 after_dead = NEXT_INSN (after_dead);
11690 if (before_dead && after_dead
11691 && INSN_CUID (before_dead) >= from_cuid
11692 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11693 || (where_dead != after_dead
11694 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11696 rtx note = remove_death (regno, where_dead);
11698 /* It is possible for the call above to return 0. This can occur
11699 when last_death points to I2 or I1 that we combined with.
11700 In that case make a new note.
11702 We must also check for the case where X is a hard register
11703 and NOTE is a death note for a range of hard registers
11704 including X. In that case, we must put REG_DEAD notes for
11705 the remaining registers in place of NOTE. */
11707 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11708 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11709 > GET_MODE_SIZE (GET_MODE (x))))
11711 unsigned int deadregno = REGNO (XEXP (note, 0));
11712 unsigned int deadend
11713 = (deadregno + hard_regno_nregs[deadregno]
11714 [GET_MODE (XEXP (note, 0))]);
11715 unsigned int ourend
11716 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11719 for (i = deadregno; i < deadend; i++)
11720 if (i < regno || i >= ourend)
11721 REG_NOTES (where_dead)
11722 = gen_rtx_EXPR_LIST (REG_DEAD,
11724 REG_NOTES (where_dead));
11727 /* If we didn't find any note, or if we found a REG_DEAD note that
11728 covers only part of the given reg, and we have a multi-reg hard
11729 register, then to be safe we must check for REG_DEAD notes
11730 for each register other than the first. They could have
11731 their own REG_DEAD notes lying around. */
11732 else if ((note == 0
11734 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11735 < GET_MODE_SIZE (GET_MODE (x)))))
11736 && regno < FIRST_PSEUDO_REGISTER
11737 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11739 unsigned int ourend
11740 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11741 unsigned int i, offset;
11745 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11749 for (i = regno + offset; i < ourend; i++)
11750 move_deaths (regno_reg_rtx[i],
11751 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11754 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11756 XEXP (note, 1) = *pnotes;
11760 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11762 REG_N_DEATHS (regno)++;
11768 else if (GET_CODE (x) == SET)
11770 rtx dest = SET_DEST (x);
11772 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11774 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11775 that accesses one word of a multi-word item, some
11776 piece of everything register in the expression is used by
11777 this insn, so remove any old death. */
11778 /* ??? So why do we test for equality of the sizes? */
11780 if (GET_CODE (dest) == ZERO_EXTRACT
11781 || GET_CODE (dest) == STRICT_LOW_PART
11782 || (GET_CODE (dest) == SUBREG
11783 && (((GET_MODE_SIZE (GET_MODE (dest))
11784 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11785 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11786 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11788 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11792 /* If this is some other SUBREG, we know it replaces the entire
11793 value, so use that as the destination. */
11794 if (GET_CODE (dest) == SUBREG)
11795 dest = SUBREG_REG (dest);
11797 /* If this is a MEM, adjust deaths of anything used in the address.
11798 For a REG (the only other possibility), the entire value is
11799 being replaced so the old value is not used in this insn. */
11802 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11807 else if (GET_CODE (x) == CLOBBER)
11810 len = GET_RTX_LENGTH (code);
11811 fmt = GET_RTX_FORMAT (code);
11813 for (i = 0; i < len; i++)
11818 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11819 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11822 else if (fmt[i] == 'e')
11823 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11827 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11828 pattern of an insn. X must be a REG. */
11831 reg_bitfield_target_p (rtx x, rtx body)
11835 if (GET_CODE (body) == SET)
11837 rtx dest = SET_DEST (body);
11839 unsigned int regno, tregno, endregno, endtregno;
11841 if (GET_CODE (dest) == ZERO_EXTRACT)
11842 target = XEXP (dest, 0);
11843 else if (GET_CODE (dest) == STRICT_LOW_PART)
11844 target = SUBREG_REG (XEXP (dest, 0));
11848 if (GET_CODE (target) == SUBREG)
11849 target = SUBREG_REG (target);
11851 if (!REG_P (target))
11854 tregno = REGNO (target), regno = REGNO (x);
11855 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11856 return target == x;
11858 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11859 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11861 return endregno > tregno && regno < endtregno;
11864 else if (GET_CODE (body) == PARALLEL)
11865 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11866 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11872 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11873 as appropriate. I3 and I2 are the insns resulting from the combination
11874 insns including FROM (I2 may be zero).
11876 Each note in the list is either ignored or placed on some insns, depending
11877 on the type of note. */
11880 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11882 rtx note, next_note;
11885 for (note = notes; note; note = next_note)
11887 rtx place = 0, place2 = 0;
11889 /* If this NOTE references a pseudo register, ensure it references
11890 the latest copy of that register. */
11891 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11892 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11893 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11895 next_note = XEXP (note, 1);
11896 switch (REG_NOTE_KIND (note))
11900 /* Doesn't matter much where we put this, as long as it's somewhere.
11901 It is preferable to keep these notes on branches, which is most
11902 likely to be i3. */
11906 case REG_VALUE_PROFILE:
11907 /* Just get rid of this note, as it is unused later anyway. */
11910 case REG_NON_LOCAL_GOTO:
11915 gcc_assert (i2 && JUMP_P (i2));
11920 case REG_EH_REGION:
11921 /* These notes must remain with the call or trapping instruction. */
11924 else if (i2 && CALL_P (i2))
11928 gcc_assert (flag_non_call_exceptions);
11929 if (may_trap_p (i3))
11931 else if (i2 && may_trap_p (i2))
11933 /* ??? Otherwise assume we've combined things such that we
11934 can now prove that the instructions can't trap. Drop the
11935 note in this case. */
11941 /* These notes must remain with the call. It should not be
11942 possible for both I2 and I3 to be a call. */
11947 gcc_assert (i2 && CALL_P (i2));
11953 /* Any clobbers for i3 may still exist, and so we must process
11954 REG_UNUSED notes from that insn.
11956 Any clobbers from i2 or i1 can only exist if they were added by
11957 recog_for_combine. In that case, recog_for_combine created the
11958 necessary REG_UNUSED notes. Trying to keep any original
11959 REG_UNUSED notes from these insns can cause incorrect output
11960 if it is for the same register as the original i3 dest.
11961 In that case, we will notice that the register is set in i3,
11962 and then add a REG_UNUSED note for the destination of i3, which
11963 is wrong. However, it is possible to have REG_UNUSED notes from
11964 i2 or i1 for register which were both used and clobbered, so
11965 we keep notes from i2 or i1 if they will turn into REG_DEAD
11968 /* If this register is set or clobbered in I3, put the note there
11969 unless there is one already. */
11970 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11972 if (from_insn != i3)
11975 if (! (REG_P (XEXP (note, 0))
11976 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11977 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11980 /* Otherwise, if this register is used by I3, then this register
11981 now dies here, so we must put a REG_DEAD note here unless there
11983 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11984 && ! (REG_P (XEXP (note, 0))
11985 ? find_regno_note (i3, REG_DEAD,
11986 REGNO (XEXP (note, 0)))
11987 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11989 PUT_REG_NOTE_KIND (note, REG_DEAD);
11997 /* These notes say something about results of an insn. We can
11998 only support them if they used to be on I3 in which case they
11999 remain on I3. Otherwise they are ignored.
12001 If the note refers to an expression that is not a constant, we
12002 must also ignore the note since we cannot tell whether the
12003 equivalence is still true. It might be possible to do
12004 slightly better than this (we only have a problem if I2DEST
12005 or I1DEST is present in the expression), but it doesn't
12006 seem worth the trouble. */
12008 if (from_insn == i3
12009 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12014 case REG_NO_CONFLICT:
12015 /* These notes say something about how a register is used. They must
12016 be present on any use of the register in I2 or I3. */
12017 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12020 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12030 /* This can show up in several ways -- either directly in the
12031 pattern, or hidden off in the constant pool with (or without?)
12032 a REG_EQUAL note. */
12033 /* ??? Ignore the without-reg_equal-note problem for now. */
12034 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12035 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12036 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12037 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12041 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12042 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12043 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12044 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12052 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12053 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12054 if (place && JUMP_P (place))
12056 rtx label = JUMP_LABEL (place);
12059 JUMP_LABEL (place) = XEXP (note, 0);
12062 gcc_assert (label == XEXP (note, 0));
12063 if (LABEL_P (label))
12064 LABEL_NUSES (label)--;
12068 if (place2 && JUMP_P (place2))
12070 rtx label = JUMP_LABEL (place2);
12073 JUMP_LABEL (place2) = XEXP (note, 0);
12076 gcc_assert (label == XEXP (note, 0));
12077 if (LABEL_P (label))
12078 LABEL_NUSES (label)--;
12085 /* This note says something about the value of a register prior
12086 to the execution of an insn. It is too much trouble to see
12087 if the note is still correct in all situations. It is better
12088 to simply delete it. */
12092 /* If the insn previously containing this note still exists,
12093 put it back where it was. Otherwise move it to the previous
12094 insn. Adjust the corresponding REG_LIBCALL note. */
12095 if (!NOTE_P (from_insn))
12099 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12100 place = prev_real_insn (from_insn);
12102 XEXP (tem, 0) = place;
12103 /* If we're deleting the last remaining instruction of a
12104 libcall sequence, don't add the notes. */
12105 else if (XEXP (note, 0) == from_insn)
12107 /* Don't add the dangling REG_RETVAL note. */
12114 /* This is handled similarly to REG_RETVAL. */
12115 if (!NOTE_P (from_insn))
12119 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12120 place = next_real_insn (from_insn);
12122 XEXP (tem, 0) = place;
12123 /* If we're deleting the last remaining instruction of a
12124 libcall sequence, don't add the notes. */
12125 else if (XEXP (note, 0) == from_insn)
12127 /* Don't add the dangling REG_LIBCALL note. */
12134 /* If the register is used as an input in I3, it dies there.
12135 Similarly for I2, if it is nonzero and adjacent to I3.
12137 If the register is not used as an input in either I3 or I2
12138 and it is not one of the registers we were supposed to eliminate,
12139 there are two possibilities. We might have a non-adjacent I2
12140 or we might have somehow eliminated an additional register
12141 from a computation. For example, we might have had A & B where
12142 we discover that B will always be zero. In this case we will
12143 eliminate the reference to A.
12145 In both cases, we must search to see if we can find a previous
12146 use of A and put the death note there. */
12149 && CALL_P (from_insn)
12150 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12152 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12154 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12155 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12160 basic_block bb = this_basic_block;
12162 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12164 if (! INSN_P (tem))
12166 if (tem == BB_HEAD (bb))
12171 /* If the register is being set at TEM, see if that is all
12172 TEM is doing. If so, delete TEM. Otherwise, make this
12173 into a REG_UNUSED note instead. Don't delete sets to
12174 global register vars. */
12175 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12176 || !global_regs[REGNO (XEXP (note, 0))])
12177 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12179 rtx set = single_set (tem);
12180 rtx inner_dest = 0;
12182 rtx cc0_setter = NULL_RTX;
12186 for (inner_dest = SET_DEST (set);
12187 (GET_CODE (inner_dest) == STRICT_LOW_PART
12188 || GET_CODE (inner_dest) == SUBREG
12189 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12190 inner_dest = XEXP (inner_dest, 0))
12193 /* Verify that it was the set, and not a clobber that
12194 modified the register.
12196 CC0 targets must be careful to maintain setter/user
12197 pairs. If we cannot delete the setter due to side
12198 effects, mark the user with an UNUSED note instead
12201 if (set != 0 && ! side_effects_p (SET_SRC (set))
12202 && rtx_equal_p (XEXP (note, 0), inner_dest)
12204 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12205 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12206 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12210 /* Move the notes and links of TEM elsewhere.
12211 This might delete other dead insns recursively.
12212 First set the pattern to something that won't use
12214 rtx old_notes = REG_NOTES (tem);
12216 PATTERN (tem) = pc_rtx;
12217 REG_NOTES (tem) = NULL;
12219 distribute_notes (old_notes, tem, tem, NULL_RTX);
12220 distribute_links (LOG_LINKS (tem));
12222 SET_INSN_DELETED (tem);
12225 /* Delete the setter too. */
12228 PATTERN (cc0_setter) = pc_rtx;
12229 old_notes = REG_NOTES (cc0_setter);
12230 REG_NOTES (cc0_setter) = NULL;
12232 distribute_notes (old_notes, cc0_setter,
12233 cc0_setter, NULL_RTX);
12234 distribute_links (LOG_LINKS (cc0_setter));
12236 SET_INSN_DELETED (cc0_setter);
12242 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12244 /* If there isn't already a REG_UNUSED note, put one
12245 here. Do not place a REG_DEAD note, even if
12246 the register is also used here; that would not
12247 match the algorithm used in lifetime analysis
12248 and can cause the consistency check in the
12249 scheduler to fail. */
12250 if (! find_regno_note (tem, REG_UNUSED,
12251 REGNO (XEXP (note, 0))))
12256 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12258 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12262 /* If we are doing a 3->2 combination, and we have a
12263 register which formerly died in i3 and was not used
12264 by i2, which now no longer dies in i3 and is used in
12265 i2 but does not die in i2, and place is between i2
12266 and i3, then we may need to move a link from place to
12268 if (i2 && INSN_UID (place) <= max_uid_cuid
12269 && INSN_CUID (place) > INSN_CUID (i2)
12271 && INSN_CUID (from_insn) > INSN_CUID (i2)
12272 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12274 rtx links = LOG_LINKS (place);
12275 LOG_LINKS (place) = 0;
12276 distribute_links (links);
12281 if (tem == BB_HEAD (bb))
12285 /* We haven't found an insn for the death note and it
12286 is still a REG_DEAD note, but we have hit the beginning
12287 of the block. If the existing life info says the reg
12288 was dead, there's nothing left to do. Otherwise, we'll
12289 need to do a global life update after combine. */
12290 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12291 && REGNO_REG_SET_P (bb->global_live_at_start,
12292 REGNO (XEXP (note, 0))))
12293 SET_BIT (refresh_blocks, this_basic_block->index);
12296 /* If the register is set or already dead at PLACE, we needn't do
12297 anything with this note if it is still a REG_DEAD note.
12298 We check here if it is set at all, not if is it totally replaced,
12299 which is what `dead_or_set_p' checks, so also check for it being
12302 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12304 unsigned int regno = REGNO (XEXP (note, 0));
12306 /* Similarly, if the instruction on which we want to place
12307 the note is a noop, we'll need do a global live update
12308 after we remove them in delete_noop_moves. */
12309 if (noop_move_p (place))
12310 SET_BIT (refresh_blocks, this_basic_block->index);
12312 if (dead_or_set_p (place, XEXP (note, 0))
12313 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12315 /* Unless the register previously died in PLACE, clear
12316 last_death. [I no longer understand why this is
12318 if (reg_stat[regno].last_death != place)
12319 reg_stat[regno].last_death = 0;
12323 reg_stat[regno].last_death = place;
12325 /* If this is a death note for a hard reg that is occupying
12326 multiple registers, ensure that we are still using all
12327 parts of the object. If we find a piece of the object
12328 that is unused, we must arrange for an appropriate REG_DEAD
12329 note to be added for it. However, we can't just emit a USE
12330 and tag the note to it, since the register might actually
12331 be dead; so we recourse, and the recursive call then finds
12332 the previous insn that used this register. */
12334 if (place && regno < FIRST_PSEUDO_REGISTER
12335 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12337 unsigned int endregno
12338 = regno + hard_regno_nregs[regno]
12339 [GET_MODE (XEXP (note, 0))];
12343 for (i = regno; i < endregno; i++)
12344 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12345 && ! find_regno_fusage (place, USE, i))
12346 || dead_or_set_regno_p (place, i))
12351 /* Put only REG_DEAD notes for pieces that are
12352 not already dead or set. */
12354 for (i = regno; i < endregno;
12355 i += hard_regno_nregs[i][reg_raw_mode[i]])
12357 rtx piece = regno_reg_rtx[i];
12358 basic_block bb = this_basic_block;
12360 if (! dead_or_set_p (place, piece)
12361 && ! reg_bitfield_target_p (piece,
12365 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12367 distribute_notes (new_note, place, place,
12370 else if (! refers_to_regno_p (i, i + 1,
12371 PATTERN (place), 0)
12372 && ! find_regno_fusage (place, USE, i))
12373 for (tem = PREV_INSN (place); ;
12374 tem = PREV_INSN (tem))
12376 if (! INSN_P (tem))
12378 if (tem == BB_HEAD (bb))
12380 SET_BIT (refresh_blocks,
12381 this_basic_block->index);
12386 if (dead_or_set_p (tem, piece)
12387 || reg_bitfield_target_p (piece,
12391 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12406 /* Any other notes should not be present at this point in the
12408 gcc_unreachable ();
12413 XEXP (note, 1) = REG_NOTES (place);
12414 REG_NOTES (place) = note;
12416 else if ((REG_NOTE_KIND (note) == REG_DEAD
12417 || REG_NOTE_KIND (note) == REG_UNUSED)
12418 && REG_P (XEXP (note, 0)))
12419 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12423 if ((REG_NOTE_KIND (note) == REG_DEAD
12424 || REG_NOTE_KIND (note) == REG_UNUSED)
12425 && REG_P (XEXP (note, 0)))
12426 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12428 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12429 REG_NOTE_KIND (note),
12431 REG_NOTES (place2));
12436 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12437 I3, I2, and I1 to new locations. This is also called to add a link
12438 pointing at I3 when I3's destination is changed. */
12441 distribute_links (rtx links)
12443 rtx link, next_link;
12445 for (link = links; link; link = next_link)
12451 next_link = XEXP (link, 1);
12453 /* If the insn that this link points to is a NOTE or isn't a single
12454 set, ignore it. In the latter case, it isn't clear what we
12455 can do other than ignore the link, since we can't tell which
12456 register it was for. Such links wouldn't be used by combine
12459 It is not possible for the destination of the target of the link to
12460 have been changed by combine. The only potential of this is if we
12461 replace I3, I2, and I1 by I3 and I2. But in that case the
12462 destination of I2 also remains unchanged. */
12464 if (NOTE_P (XEXP (link, 0))
12465 || (set = single_set (XEXP (link, 0))) == 0)
12468 reg = SET_DEST (set);
12469 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12470 || GET_CODE (reg) == STRICT_LOW_PART)
12471 reg = XEXP (reg, 0);
12473 /* A LOG_LINK is defined as being placed on the first insn that uses
12474 a register and points to the insn that sets the register. Start
12475 searching at the next insn after the target of the link and stop
12476 when we reach a set of the register or the end of the basic block.
12478 Note that this correctly handles the link that used to point from
12479 I3 to I2. Also note that not much searching is typically done here
12480 since most links don't point very far away. */
12482 for (insn = NEXT_INSN (XEXP (link, 0));
12483 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12484 || BB_HEAD (this_basic_block->next_bb) != insn));
12485 insn = NEXT_INSN (insn))
12486 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12488 if (reg_referenced_p (reg, PATTERN (insn)))
12492 else if (CALL_P (insn)
12493 && find_reg_fusage (insn, USE, reg))
12498 else if (INSN_P (insn) && reg_set_p (reg, insn))
12501 /* If we found a place to put the link, place it there unless there
12502 is already a link to the same insn as LINK at that point. */
12508 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12509 if (XEXP (link2, 0) == XEXP (link, 0))
12514 XEXP (link, 1) = LOG_LINKS (place);
12515 LOG_LINKS (place) = link;
12517 /* Set added_links_insn to the earliest insn we added a
12519 if (added_links_insn == 0
12520 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12521 added_links_insn = place;
12527 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12528 Check whether the expression pointer to by LOC is a register or
12529 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12530 Otherwise return zero. */
12533 unmentioned_reg_p_1 (rtx *loc, void *expr)
12538 && (REG_P (x) || MEM_P (x))
12539 && ! reg_mentioned_p (x, (rtx) expr))
12544 /* Check for any register or memory mentioned in EQUIV that is not
12545 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12546 of EXPR where some registers may have been replaced by constants. */
12549 unmentioned_reg_p (rtx equiv, rtx expr)
12551 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12554 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12557 insn_cuid (rtx insn)
12559 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12560 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12561 insn = NEXT_INSN (insn);
12563 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12565 return INSN_CUID (insn);
12569 dump_combine_stats (FILE *file)
12573 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12574 combine_attempts, combine_merges, combine_extras, combine_successes);
12578 dump_combine_total_stats (FILE *file)
12582 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12583 total_attempts, total_merges, total_extras, total_successes);
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